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drivers/net: Remove alloc_etherdev error messages
[deliverable/linux.git] / drivers / net / ethernet / dec / tulip / dmfe.c
CommitLineData
1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
dde7c8ef
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
1da177e4
LT		 66#define DRV_NAME "dmfe"
67#define DRV_VERSION "1.36.4"
68#define DRV_RELDATE "2002-01-17"
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/ptrace.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
1da177e4
LT		 77#include <linux/interrupt.h>
78#include <linux/pci.h>
cb199d42 79#include <linux/dma-mapping.h>
1da177e4
LT		 80#include <linux/init.h>
81#include <linux/netdevice.h>
82#include <linux/etherdevice.h>
83#include <linux/ethtool.h>
84#include <linux/skbuff.h>
85#include <linux/delay.h>
86#include <linux/spinlock.h>
87#include <linux/crc32.h>
88#include <linux/bitops.h>
89
90#include <asm/processor.h>
91#include <asm/io.h>
92#include <asm/dma.h>
93#include <asm/uaccess.h>
94#include <asm/irq.h>
95
4d907069
BH		 96#ifdef CONFIG_TULIP_DM910X
97#include <linux/of.h>
98#endif
99
1da177e4
LT		 100
101/* Board/System/Debug information/definition ---------------- */
102#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107#define DM9102_IO_SIZE 0x80
108#define DM9102A_IO_SIZE 0x100
109#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115#define TX_BUF_ALLOC 0x600
116#define RX_ALLOC_SIZE 0x620
117#define DM910X_RESET 1
118#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119#define CR6_DEFAULT 0x00080000 /* HD */
120#define CR7_DEFAULT 0x180c1
121#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123#define MAX_PACKET_SIZE 1514
124#define DMFE_MAX_MULTICAST 14
125#define RX_COPY_SIZE 100
126#define MAX_CHECK_PACKET 0x8000
127#define DM9801_NOISE_FLOOR 8
128#define DM9802_NOISE_FLOOR 5
129
f1069046
ML		 130#define DMFE_WOL_LINKCHANGE 0x20000000
131#define DMFE_WOL_SAMPLEPACKET 0x10000000
132#define DMFE_WOL_MAGICPACKET 0x08000000
133
134
1da177e4
LT		 135#define DMFE_10MHF 0
136#define DMFE_100MHF 1
137#define DMFE_10MFD 4
138#define DMFE_100MFD 5
139#define DMFE_AUTO 8
140#define DMFE_1M_HPNA 0x10
141
142#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
dde7c8ef
JP		 153#define DMFE_DBUG(dbug_now, msg, value) \
154 do { \
155 if (dmfe_debug || (dbug_now)) \
156 pr_err("%s %lx\n", \
157 (msg), (long) (value)); \
f67ba792 158 } while (0)
1da177e4 159
dde7c8ef
JP		 160#define SHOW_MEDIA_TYPE(mode) \
161 pr_info("Change Speed to %sMhz %s duplex\n" , \
162 (mode & 1) ? "100":"10", \
163 (mode & 4) ? "full":"half");
1da177e4
LT		 164
165
166/* CR9 definition: SROM/MII */
167#define CR9_SROM_READ 0x4800
168#define CR9_SRCS 0x1
169#define CR9_SRCLK 0x2
170#define CR9_CRDOUT 0x8
171#define SROM_DATA_0 0x0
172#define SROM_DATA_1 0x4
173#define PHY_DATA_1 0x20000
174#define PHY_DATA_0 0x00000
175#define MDCLKH 0x10000
176
177#define PHY_POWER_DOWN 0x800
178
179#define SROM_V41_CODE 0x14
180
f67ba792
ML		 181#define SROM_CLK_WRITE(data, ioaddr) \
182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
185 udelay(5); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
187 udelay(5);
188
189#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 190 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 191 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 192
44c10138
AK		 193#define CHK_IO_SIZE(pci_dev) \
194 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
195 (pci_dev)->revision))
1da177e4
LT		 196
197/* Sten Check */
198#define DEVICE net_device
199
200/* Structure/enum declaration ------------------------------- */
201struct tx_desc {
a31e40f6 202 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 203 char *tx_buf_ptr; /* Data for us */
204 struct tx_desc *next_tx_desc;
205} __attribute__(( aligned(32) ));
206
207struct rx_desc {
a31e40f6 208 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 209 struct sk_buff *rx_skb_ptr; /* Data for us */
210 struct rx_desc *next_rx_desc;
211} __attribute__(( aligned(32) ));
212
213struct dmfe_board_info {
214 u32 chip_id; /* Chip vendor/Device ID */
44c10138 215 u8 chip_revision; /* Chip revision */
ead9bffb 216 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 217 struct pci_dev *pdev; /* PCI device */
218 spinlock_t lock;
219
220 long ioaddr; /* I/O base address */
221 u32 cr0_data;
222 u32 cr5_data;
223 u32 cr6_data;
224 u32 cr7_data;
225 u32 cr15_data;
226
227 /* pointer for memory physical address */
228 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
229 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
230 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
231 dma_addr_t first_tx_desc_dma;
232 dma_addr_t first_rx_desc_dma;
233
234 /* descriptor pointer */
235 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
236 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
237 unsigned char *desc_pool_ptr; /* descriptor pool memory */
238 struct tx_desc *first_tx_desc;
239 struct tx_desc *tx_insert_ptr;
240 struct tx_desc *tx_remove_ptr;
241 struct rx_desc *first_rx_desc;
242 struct rx_desc *rx_insert_ptr;
243 struct rx_desc *rx_ready_ptr; /* packet come pointer */
244 unsigned long tx_packet_cnt; /* transmitted packet count */
245 unsigned long tx_queue_cnt; /* wait to send packet count */
246 unsigned long rx_avail_cnt; /* available rx descriptor count */
247 unsigned long interval_rx_cnt; /* rx packet count a callback time */
248
249 u16 HPNA_command; /* For HPNA register 16 */
250 u16 HPNA_timer; /* For HPNA remote device check */
251 u16 dbug_cnt;
252 u16 NIC_capability; /* NIC media capability */
253 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
254
255 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
256 u8 chip_type; /* Keep DM9102A chip type */
257 u8 media_mode; /* user specify media mode */
258 u8 op_mode; /* real work media mode */
259 u8 phy_addr;
1da177e4
LT		 260 u8 wait_reset; /* Hardware failed, need to reset */
261 u8 dm910x_chk_mode; /* Operating mode check */
262 u8 first_in_callback; /* Flag to record state */
f1069046 263 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 264 struct timer_list timer;
265
1da177e4
LT		 266 /* Driver defined statistic counter */
267 unsigned long tx_fifo_underrun;
268 unsigned long tx_loss_carrier;
269 unsigned long tx_no_carrier;
270 unsigned long tx_late_collision;
271 unsigned long tx_excessive_collision;
272 unsigned long tx_jabber_timeout;
273 unsigned long reset_count;
274 unsigned long reset_cr8;
275 unsigned long reset_fatal;
276 unsigned long reset_TXtimeout;
277
278 /* NIC SROM data */
279 unsigned char srom[128];
280};
281
282enum dmfe_offsets {
283 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
284 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
285 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
286 DCR15 = 0x78
287};
288
289enum dmfe_CR6_bits {
290 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
291 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
292 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
293};
294
295/* Global variable declaration ----------------------------- */
296static int __devinitdata printed_version;
03f54b3d 297static const char version[] __devinitconst =
1c3319fb 298 "Davicom DM9xxx net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
1da177e4
LT		 299
300static int dmfe_debug;
301static unsigned char dmfe_media_mode = DMFE_AUTO;
302static u32 dmfe_cr6_user_set;
303
304/* For module input parameter */
305static int debug;
306static u32 cr6set;
307static unsigned char mode = 8;
308static u8 chkmode = 1;
309static u8 HPNA_mode; /* Default: Low Power/High Speed */
310static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
311static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
312static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
313static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
314 4: TX pause packet */
315
316
317/* function declaration ------------------------------------- */
318static int dmfe_open(struct DEVICE *);
ad096463 319static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
1da177e4 320static int dmfe_stop(struct DEVICE *);
1da177e4 321static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 322static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 323static u16 read_srom_word(long ,int);
7d12e780 324static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 325#ifdef CONFIG_NET_POLL_CONTROLLER
326static void poll_dmfe (struct net_device *dev);
327#endif
328static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
329static void allocate_rx_buffer(struct dmfe_board_info *);
330static void update_cr6(u32, unsigned long);
4302b67e
JP		 331static void send_filter_frame(struct DEVICE *);
332static void dm9132_id_table(struct DEVICE *);
1da177e4
LT		 333static u16 phy_read(unsigned long, u8, u8, u32);
334static void phy_write(unsigned long, u8, u8, u16, u32);
335static void phy_write_1bit(unsigned long, u32);
336static u16 phy_read_1bit(unsigned long);
337static u8 dmfe_sense_speed(struct dmfe_board_info *);
338static void dmfe_process_mode(struct dmfe_board_info *);
339static void dmfe_timer(unsigned long);
340static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
341static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
342static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
343static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
344static void dmfe_dynamic_reset(struct DEVICE *);
345static void dmfe_free_rxbuffer(struct dmfe_board_info *);
346static void dmfe_init_dm910x(struct DEVICE *);
347static void dmfe_parse_srom(struct dmfe_board_info *);
348static void dmfe_program_DM9801(struct dmfe_board_info *, int);
349static void dmfe_program_DM9802(struct dmfe_board_info *);
350static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
351static void dmfe_set_phyxcer(struct dmfe_board_info *);
352
f67ba792 353/* DM910X network board routine ---------------------------- */
1da177e4 354
2765df58
SH		 355static const struct net_device_ops netdev_ops = {
356 .ndo_open = dmfe_open,
357 .ndo_stop = dmfe_stop,
358 .ndo_start_xmit = dmfe_start_xmit,
afc4b13d 359 .ndo_set_rx_mode = dmfe_set_filter_mode,
2765df58
SH		 360 .ndo_change_mtu = eth_change_mtu,
361 .ndo_set_mac_address = eth_mac_addr,
362 .ndo_validate_addr = eth_validate_addr,
363#ifdef CONFIG_NET_POLL_CONTROLLER
364 .ndo_poll_controller = poll_dmfe,
365#endif
366};
367
1da177e4
LT		 368/*
369 * Search DM910X board ,allocate space and register it
370 */
371
372static int __devinit dmfe_init_one (struct pci_dev *pdev,
373 const struct pci_device_id *ent)
374{
375 struct dmfe_board_info *db; /* board information structure */
376 struct net_device *dev;
44c10138 377 u32 pci_pmr;
1da177e4
LT		 378 int i, err;
379
380 DMFE_DBUG(0, "dmfe_init_one()", 0);
381
382 if (!printed_version++)
1c3319fb 383 pr_info("%s\n", version);
1da177e4 384
4d907069
BH		 385 /*
386 * SPARC on-board DM910x chips should be handled by the main
387 * tulip driver, except for early DM9100s.
388 */
389#ifdef CONFIG_TULIP_DM910X
390 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
391 ent->driver_data == PCI_DM9102_ID) {
392 struct device_node *dp = pci_device_to_OF_node(pdev);
393
394 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
dde7c8ef 395 pr_info("skipping on-board DM910x (use tulip)\n");
4d907069
BH		 396 return -ENODEV;
397 }
398 }
399#endif
400
1da177e4
LT		 401 /* Init network device */
402 dev = alloc_etherdev(sizeof(*db));
403 if (dev == NULL)
404 return -ENOMEM;
1da177e4
LT		 405 SET_NETDEV_DEV(dev, &pdev->dev);
406
284901a9 407 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
163ef0b5 408 pr_warn("32-bit PCI DMA not available\n");
1da177e4
LT		 409 err = -ENODEV;
410 goto err_out_free;
411 }
412
413 /* Enable Master/IO access, Disable memory access */
414 err = pci_enable_device(pdev);
415 if (err)
416 goto err_out_free;
417
418 if (!pci_resource_start(pdev, 0)) {
dde7c8ef 419 pr_err("I/O base is zero\n");
1da177e4
LT		 420 err = -ENODEV;
421 goto err_out_disable;
422 }
423
44c10138 424 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
dde7c8ef 425 pr_err("Allocated I/O size too small\n");
1da177e4
LT		 426 err = -ENODEV;
427 goto err_out_disable;
428 }
429
430#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
431
432 /* Set Latency Timer 80h */
433 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
434 Need a PCI quirk.. */
435
436 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
437#endif
438
439 if (pci_request_regions(pdev, DRV_NAME)) {
dde7c8ef 440 pr_err("Failed to request PCI regions\n");
1da177e4
LT		 441 err = -ENODEV;
442 goto err_out_disable;
443 }
444
445 /* Init system & device */
446 db = netdev_priv(dev);
447
448 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 449 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
450 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
74d5e8ac
FT		 451 if (!db->desc_pool_ptr)
452 goto err_out_res;
f67ba792
ML		 453
454 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
455 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
74d5e8ac
FT		 456 if (!db->buf_pool_ptr)
457 goto err_out_free_desc;
1da177e4
LT		 458
459 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
460 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
461 db->buf_pool_start = db->buf_pool_ptr;
462 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
463
464 db->chip_id = ent->driver_data;
465 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 466 db->chip_revision = pdev->revision;
f1069046 467 db->wol_mode = 0;
1da177e4
LT		 468
469 db->pdev = pdev;
470
471 dev->base_addr = db->ioaddr;
472 dev->irq = pdev->irq;
473 pci_set_drvdata(pdev, dev);
2765df58 474 dev->netdev_ops = &netdev_ops;
1da177e4 475 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 476 netif_carrier_off(dev);
1da177e4
LT		 477 spin_lock_init(&db->lock);
478
479 pci_read_config_dword(pdev, 0x50, &pci_pmr);
480 pci_pmr &= 0x70000;
44c10138 481 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 482 db->chip_type = 1; /* DM9102A E3 */
483 else
484 db->chip_type = 0;
485
486 /* read 64 word srom data */
487 for (i = 0; i < 64; i++)
a31e40f6 488 ((__le16 *) db->srom)[i] =
f67ba792 489 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 490
491 /* Set Node address */
492 for (i = 0; i < 6; i++)
493 dev->dev_addr[i] = db->srom[20 + i];
494
495 err = register_netdev (dev);
496 if (err)
74d5e8ac 497 goto err_out_free_buf;
1da177e4 498
dde7c8ef
JP		 499 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
500 ent->driver_data >> 16,
501 pci_name(pdev), dev->dev_addr, dev->irq);
1da177e4
LT		 502
503 pci_set_master(pdev);
504
505 return 0;
506
74d5e8ac
FT		 507err_out_free_buf:
508 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
509 db->buf_pool_ptr, db->buf_pool_dma_ptr);
510err_out_free_desc:
511 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
512 db->desc_pool_ptr, db->desc_pool_dma_ptr);
1da177e4
LT		 513err_out_res:
514 pci_release_regions(pdev);
515err_out_disable:
516 pci_disable_device(pdev);
517err_out_free:
518 pci_set_drvdata(pdev, NULL);
519 free_netdev(dev);
520
521 return err;
522}
523
524
525static void __devexit dmfe_remove_one (struct pci_dev *pdev)
526{
527 struct net_device *dev = pci_get_drvdata(pdev);
528 struct dmfe_board_info *db = netdev_priv(dev);
529
530 DMFE_DBUG(0, "dmfe_remove_one()", 0);
531
532 if (dev) {
4dc68f3d
ML		 533
534 unregister_netdev(dev);
535
1da177e4
LT		 536 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
537 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
538 db->desc_pool_dma_ptr);
539 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
540 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 541 pci_release_regions(pdev);
542 free_netdev(dev); /* free board information */
4dc68f3d 543
1da177e4
LT		 544 pci_set_drvdata(pdev, NULL);
545 }
546
547 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
548}
549
550
551/*
552 * Open the interface.
553 * The interface is opened whenever "ifconfig" actives it.
554 */
555
556static int dmfe_open(struct DEVICE *dev)
557{
558 int ret;
559 struct dmfe_board_info *db = netdev_priv(dev);
560
561 DMFE_DBUG(0, "dmfe_open", 0);
562
a0607fd3 563 ret = request_irq(dev->irq, dmfe_interrupt,
f67ba792 564 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 565 if (ret)
566 return ret;
567
568 /* system variable init */
569 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
570 db->tx_packet_cnt = 0;
571 db->tx_queue_cnt = 0;
572 db->rx_avail_cnt = 0;
1da177e4
LT		 573 db->wait_reset = 0;
574
575 db->first_in_callback = 0;
576 db->NIC_capability = 0xf; /* All capability*/
577 db->PHY_reg4 = 0x1e0;
578
579 /* CR6 operation mode decision */
580 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 581 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 582 db->cr6_data |= DMFE_TXTH_256;
583 db->cr0_data = CR0_DEFAULT;
584 db->dm910x_chk_mode=4; /* Enter the normal mode */
585 } else {
586 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
587 db->cr0_data = 0;
588 db->dm910x_chk_mode = 1; /* Enter the check mode */
589 }
590
421f91d2 591 /* Initialize DM910X board */
1da177e4
LT		 592 dmfe_init_dm910x(dev);
593
594 /* Active System Interface */
595 netif_wake_queue(dev);
596
597 /* set and active a timer process */
598 init_timer(&db->timer);
599 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
600 db->timer.data = (unsigned long)dev;
c061b18d 601 db->timer.function = dmfe_timer;
1da177e4
LT		 602 add_timer(&db->timer);
603
604 return 0;
605}
606
607
421f91d2 608/* Initialize DM910X board
1da177e4 609 * Reset DM910X board
421f91d2 610 * Initialize TX/Rx descriptor chain structure
1da177e4
LT		 611 * Send the set-up frame
612 * Enable Tx/Rx machine
613 */
614
615static void dmfe_init_dm910x(struct DEVICE *dev)
616{
617 struct dmfe_board_info *db = netdev_priv(dev);
618 unsigned long ioaddr = db->ioaddr;
619
620 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
621
622 /* Reset DM910x MAC controller */
623 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
624 udelay(100);
625 outl(db->cr0_data, ioaddr + DCR0);
626 udelay(5);
627
628 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
629 db->phy_addr = 1;
630
631 /* Parser SROM and media mode */
632 dmfe_parse_srom(db);
633 db->media_mode = dmfe_media_mode;
634
635 /* RESET Phyxcer Chip by GPR port bit 7 */
636 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
637 if (db->chip_id == PCI_DM9009_ID) {
638 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
639 mdelay(300); /* Delay 300 ms */
640 }
641 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
642
643 /* Process Phyxcer Media Mode */
644 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
645 dmfe_set_phyxcer(db);
646
647 /* Media Mode Process */
648 if ( !(db->media_mode & DMFE_AUTO) )
649 db->op_mode = db->media_mode; /* Force Mode */
650
421f91d2 651 /* Initialize Transmit/Receive decriptor and CR3/4 */
1da177e4
LT		 652 dmfe_descriptor_init(db, ioaddr);
653
654 /* Init CR6 to program DM910x operation */
655 update_cr6(db->cr6_data, ioaddr);
656
657 /* Send setup frame */
658 if (db->chip_id == PCI_DM9132_ID)
4302b67e 659 dm9132_id_table(dev); /* DM9132 */
1da177e4 660 else
4302b67e 661 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 662
663 /* Init CR7, interrupt active bit */
664 db->cr7_data = CR7_DEFAULT;
665 outl(db->cr7_data, ioaddr + DCR7);
666
667 /* Init CR15, Tx jabber and Rx watchdog timer */
668 outl(db->cr15_data, ioaddr + DCR15);
669
670 /* Enable DM910X Tx/Rx function */
671 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
672 update_cr6(db->cr6_data, ioaddr);
673}
674
675
676/*
677 * Hardware start transmission.
678 * Send a packet to media from the upper layer.
679 */
680
ad096463
SH		 681static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
682 struct DEVICE *dev)
1da177e4
LT		 683{
684 struct dmfe_board_info *db = netdev_priv(dev);
685 struct tx_desc *txptr;
686 unsigned long flags;
687
688 DMFE_DBUG(0, "dmfe_start_xmit", 0);
689
1da177e4
LT		 690 /* Too large packet check */
691 if (skb->len > MAX_PACKET_SIZE) {
dde7c8ef 692 pr_err("big packet = %d\n", (u16)skb->len);
1da177e4 693 dev_kfree_skb(skb);
ec634fe3 694 return NETDEV_TX_OK;
1da177e4
LT		 695 }
696
e7dfc8db
AL		 697 /* Resource flag check */
698 netif_stop_queue(dev);
699
1da177e4
LT		 700 spin_lock_irqsave(&db->lock, flags);
701
702 /* No Tx resource check, it never happen nromally */
703 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
704 spin_unlock_irqrestore(&db->lock, flags);
dde7c8ef 705 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
5b548140 706 return NETDEV_TX_BUSY;
1da177e4
LT		 707 }
708
709 /* Disable NIC interrupt */
710 outl(0, dev->base_addr + DCR7);
711
712 /* transmit this packet */
713 txptr = db->tx_insert_ptr;
d626f62b 714 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 715 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
716
717 /* Point to next transmit free descriptor */
718 db->tx_insert_ptr = txptr->next_tx_desc;
719
720 /* Transmit Packet Process */
721 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
722 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
723 db->tx_packet_cnt++; /* Ready to send */
724 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
725 dev->trans_start = jiffies; /* saved time stamp */
726 } else {
727 db->tx_queue_cnt++; /* queue TX packet */
728 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
729 }
730
731 /* Tx resource check */
732 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
733 netif_wake_queue(dev);
734
735 /* Restore CR7 to enable interrupt */
736 spin_unlock_irqrestore(&db->lock, flags);
737 outl(db->cr7_data, dev->base_addr + DCR7);
738
739 /* free this SKB */
740 dev_kfree_skb(skb);
741
ec634fe3 742 return NETDEV_TX_OK;
1da177e4
LT		 743}
744
745
746/*
747 * Stop the interface.
748 * The interface is stopped when it is brought.
749 */
750
751static int dmfe_stop(struct DEVICE *dev)
752{
753 struct dmfe_board_info *db = netdev_priv(dev);
754 unsigned long ioaddr = dev->base_addr;
755
756 DMFE_DBUG(0, "dmfe_stop", 0);
757
758 /* disable system */
759 netif_stop_queue(dev);
760
761 /* deleted timer */
762 del_timer_sync(&db->timer);
763
764 /* Reset & stop DM910X board */
765 outl(DM910X_RESET, ioaddr + DCR0);
766 udelay(5);
767 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
768
769 /* free interrupt */
770 free_irq(dev->irq, dev);
771
772 /* free allocated rx buffer */
773 dmfe_free_rxbuffer(db);
774
775#if 0
776 /* show statistic counter */
dde7c8ef
JP		 777 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
778 db->tx_fifo_underrun, db->tx_excessive_collision,
779 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
780 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
781 db->reset_fatal, db->reset_TXtimeout);
1da177e4
LT		 782#endif
783
784 return 0;
785}
786
787
788/*
789 * DM9102 insterrupt handler
790 * receive the packet to upper layer, free the transmitted packet
791 */
792
7d12e780 793static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 794{
795 struct DEVICE *dev = dev_id;
796 struct dmfe_board_info *db = netdev_priv(dev);
797 unsigned long ioaddr = dev->base_addr;
798 unsigned long flags;
799
800 DMFE_DBUG(0, "dmfe_interrupt()", 0);
801
1da177e4
LT		 802 spin_lock_irqsave(&db->lock, flags);
803
804 /* Got DM910X status */
805 db->cr5_data = inl(ioaddr + DCR5);
806 outl(db->cr5_data, ioaddr + DCR5);
807 if ( !(db->cr5_data & 0xc1) ) {
808 spin_unlock_irqrestore(&db->lock, flags);
809 return IRQ_HANDLED;
810 }
811
812 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
813 outl(0, ioaddr + DCR7);
814
815 /* Check system status */
816 if (db->cr5_data & 0x2000) {
817 /* system bus error happen */
818 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
819 db->reset_fatal++;
820 db->wait_reset = 1; /* Need to RESET */
821 spin_unlock_irqrestore(&db->lock, flags);
822 return IRQ_HANDLED;
823 }
824
825 /* Received the coming packet */
826 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
827 dmfe_rx_packet(dev, db);
828
829 /* reallocate rx descriptor buffer */
830 if (db->rx_avail_cnt<RX_DESC_CNT)
831 allocate_rx_buffer(db);
832
833 /* Free the transmitted descriptor */
834 if ( db->cr5_data & 0x01)
835 dmfe_free_tx_pkt(dev, db);
836
837 /* Mode Check */
838 if (db->dm910x_chk_mode & 0x2) {
839 db->dm910x_chk_mode = 0x4;
840 db->cr6_data |= 0x100;
841 update_cr6(db->cr6_data, db->ioaddr);
842 }
843
844 /* Restore CR7 to enable interrupt mask */
845 outl(db->cr7_data, ioaddr + DCR7);
846
847 spin_unlock_irqrestore(&db->lock, flags);
848 return IRQ_HANDLED;
849}
850
851
852#ifdef CONFIG_NET_POLL_CONTROLLER
853/*
854 * Polling 'interrupt' - used by things like netconsole to send skbs
855 * without having to re-enable interrupts. It's not called while
856 * the interrupt routine is executing.
857 */
858
859static void poll_dmfe (struct net_device *dev)
860{
861 /* disable_irq here is not very nice, but with the lockless
862 interrupt handler we have no other choice. */
863 disable_irq(dev->irq);
7d12e780 864 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 865 enable_irq(dev->irq);
866}
867#endif
868
869/*
870 * Free TX resource after TX complete
871 */
872
873static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
874{
875 struct tx_desc *txptr;
876 unsigned long ioaddr = dev->base_addr;
877 u32 tdes0;
878
879 txptr = db->tx_remove_ptr;
880 while(db->tx_packet_cnt) {
881 tdes0 = le32_to_cpu(txptr->tdes0);
1da177e4
LT		 882 if (tdes0 & 0x80000000)
883 break;
884
885 /* A packet sent completed */
886 db->tx_packet_cnt--;
2765df58 887 dev->stats.tx_packets++;
1da177e4
LT		 888
889 /* Transmit statistic counter */
890 if ( tdes0 != 0x7fffffff ) {
2765df58
SH		 891 dev->stats.collisions += (tdes0 >> 3) & 0xf;
892 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
1da177e4 893 if (tdes0 & TDES0_ERR_MASK) {
2765df58 894 dev->stats.tx_errors++;
1da177e4
LT		 895
896 if (tdes0 & 0x0002) { /* UnderRun */
897 db->tx_fifo_underrun++;
898 if ( !(db->cr6_data & CR6_SFT) ) {
899 db->cr6_data = db->cr6_data | CR6_SFT;
900 update_cr6(db->cr6_data, db->ioaddr);
901 }
902 }
903 if (tdes0 & 0x0100)
904 db->tx_excessive_collision++;
905 if (tdes0 & 0x0200)
906 db->tx_late_collision++;
907 if (tdes0 & 0x0400)
908 db->tx_no_carrier++;
909 if (tdes0 & 0x0800)
910 db->tx_loss_carrier++;
911 if (tdes0 & 0x4000)
912 db->tx_jabber_timeout++;
913 }
914 }
915
916 txptr = txptr->next_tx_desc;
917 }/* End of while */
918
919 /* Update TX remove pointer to next */
920 db->tx_remove_ptr = txptr;
921
922 /* Send the Tx packet in queue */
923 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
924 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
925 db->tx_packet_cnt++; /* Ready to send */
926 db->tx_queue_cnt--;
927 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
928 dev->trans_start = jiffies; /* saved time stamp */
929 }
930
931 /* Resource available check */
932 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
933 netif_wake_queue(dev); /* Active upper layer, send again */
934}
935
936
937/*
938 * Calculate the CRC valude of the Rx packet
939 * flag = 1 : return the reverse CRC (for the received packet CRC)
940 * 0 : return the normal CRC (for Hash Table index)
941 */
942
943static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
944{
945 u32 crc = crc32(~0, Data, Len);
946 if (flag) crc = ~crc;
947 return crc;
948}
949
950
951/*
952 * Receive the come packet and pass to upper layer
953 */
954
955static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
956{
957 struct rx_desc *rxptr;
4dc68f3d 958 struct sk_buff *skb, *newskb;
1da177e4
LT		 959 int rxlen;
960 u32 rdes0;
961
962 rxptr = db->rx_ready_ptr;
963
964 while(db->rx_avail_cnt) {
965 rdes0 = le32_to_cpu(rxptr->rdes0);
966 if (rdes0 & 0x80000000) /* packet owner check */
967 break;
968
969 db->rx_avail_cnt--;
970 db->interval_rx_cnt++;
971
f67ba792
ML		 972 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
973 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
974
1da177e4
LT		 975 if ( (rdes0 & 0x300) != 0x300) {
976 /* A packet without First/Last flag */
977 /* reuse this SKB */
978 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
979 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
980 } else {
981 /* A packet with First/Last flag */
982 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
983
984 /* error summary bit check */
985 if (rdes0 & 0x8000) {
986 /* This is a error packet */
2765df58 987 dev->stats.rx_errors++;
1da177e4 988 if (rdes0 & 1)
2765df58 989 dev->stats.rx_fifo_errors++;
1da177e4 990 if (rdes0 & 2)
2765df58 991 dev->stats.rx_crc_errors++;
1da177e4 992 if (rdes0 & 0x80)
2765df58 993 dev->stats.rx_length_errors++;
1da177e4
LT		 994 }
995
996 if ( !(rdes0 & 0x8000) ||
997 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
998 skb = rxptr->rx_skb_ptr;
999
1000 /* Received Packet CRC check need or not */
1001 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 1002 (cal_CRC(skb->data, rxlen, 1) !=
1003 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 1004 /* Found a error received packet */
1005 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1006 db->dm910x_chk_mode = 3;
1007 } else {
1008 /* Good packet, send to upper layer */
1009 /* Shorst packet used new SKB */
4dc68f3d
ML		 1010 if ((rxlen < RX_COPY_SIZE) &&
1011 ((newskb = dev_alloc_skb(rxlen + 2))
1012 != NULL)) {
1013
1014 skb = newskb;
1da177e4 1015 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 1016 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 1017 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1018 skb_put(skb, rxlen),
1019 rxlen);
1da177e4 1020 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 1021 } else
1da177e4 1022 skb_put(skb, rxlen);
4c13eb66 1023
1da177e4
LT		 1024 skb->protocol = eth_type_trans(skb, dev);
1025 netif_rx(skb);
2765df58
SH		 1026 dev->stats.rx_packets++;
1027 dev->stats.rx_bytes += rxlen;
1da177e4
LT		 1028 }
1029 } else {
1030 /* Reuse SKB buffer when the packet is error */
1031 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1032 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1033 }
1034 }
1035
1036 rxptr = rxptr->next_rx_desc;
1037 }
1038
1039 db->rx_ready_ptr = rxptr;
1040}
1041
1da177e4
LT		 1042/*
1043 * Set DM910X multicast address
1044 */
1045
1046static void dmfe_set_filter_mode(struct DEVICE * dev)
1047{
1048 struct dmfe_board_info *db = netdev_priv(dev);
1049 unsigned long flags;
4cd24eaf 1050 int mc_count = netdev_mc_count(dev);
1da177e4
LT		 1051
1052 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1053 spin_lock_irqsave(&db->lock, flags);
1054
1055 if (dev->flags & IFF_PROMISC) {
1056 DMFE_DBUG(0, "Enable PROM Mode", 0);
1057 db->cr6_data |= CR6_PM | CR6_PBF;
1058 update_cr6(db->cr6_data, db->ioaddr);
1059 spin_unlock_irqrestore(&db->lock, flags);
1060 return;
1061 }
1062
4cd24eaf
JP		 1063 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1064 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1da177e4
LT		 1065 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1066 db->cr6_data |= CR6_PAM;
1067 spin_unlock_irqrestore(&db->lock, flags);
1068 return;
1069 }
1070
4cd24eaf 1071 DMFE_DBUG(0, "Set multicast address", mc_count);
1da177e4 1072 if (db->chip_id == PCI_DM9132_ID)
4302b67e 1073 dm9132_id_table(dev); /* DM9132 */
1da177e4 1074 else
4302b67e 1075 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 1076 spin_unlock_irqrestore(&db->lock, flags);
1077}
1078
f1069046
ML		 1079/*
1080 * Ethtool interace
1081 */
1082
1083static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1084 struct ethtool_drvinfo *info)
1085{
1086 struct dmfe_board_info *np = netdev_priv(dev);
1087
68aad78c
RJ		 1088 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1089 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1da177e4 1090 if (np->pdev)
68aad78c
RJ		 1091 strlcpy(info->bus_info, pci_name(np->pdev),
1092 sizeof(info->bus_info));
1da177e4
LT		 1093 else
1094 sprintf(info->bus_info, "EISA 0x%lx %d",
1095 dev->base_addr, dev->irq);
1096}
1097
f1069046
ML		 1098static int dmfe_ethtool_set_wol(struct net_device *dev,
1099 struct ethtool_wolinfo *wolinfo)
1100{
1101 struct dmfe_board_info *db = netdev_priv(dev);
1102
1103 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1104 WAKE_ARP | WAKE_MAGICSECURE))
1105 return -EOPNOTSUPP;
1106
1107 db->wol_mode = wolinfo->wolopts;
1108 return 0;
1109}
1110
1111static void dmfe_ethtool_get_wol(struct net_device *dev,
1112 struct ethtool_wolinfo *wolinfo)
1113{
1114 struct dmfe_board_info *db = netdev_priv(dev);
1115
1116 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1117 wolinfo->wolopts = db->wol_mode;
f1069046
ML		 1118}
1119
1120
7282d491 1121static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1122 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1123 .get_link = ethtool_op_get_link,
f1069046
ML		 1124 .set_wol = dmfe_ethtool_set_wol,
1125 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1126};
1127
1128/*
1129 * A periodic timer routine
1130 * Dynamic media sense, allocate Rx buffer...
1131 */
1132
1133static void dmfe_timer(unsigned long data)
1134{
1135 u32 tmp_cr8;
1136 unsigned char tmp_cr12;
1137 struct DEVICE *dev = (struct DEVICE *) data;
1138 struct dmfe_board_info *db = netdev_priv(dev);
1139 unsigned long flags;
1140
cfa51b9d
ML		 1141 int link_ok, link_ok_phy;
1142
1da177e4
LT		 1143 DMFE_DBUG(0, "dmfe_timer()", 0);
1144 spin_lock_irqsave(&db->lock, flags);
1145
1146 /* Media mode process when Link OK before enter this route */
1147 if (db->first_in_callback == 0) {
1148 db->first_in_callback = 1;
1149 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1150 db->cr6_data &= ~0x40000;
1151 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1152 phy_write(db->ioaddr,
1153 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1154 db->cr6_data |= 0x40000;
1155 update_cr6(db->cr6_data, db->ioaddr);
1156 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1157 add_timer(&db->timer);
1158 spin_unlock_irqrestore(&db->lock, flags);
1159 return;
1160 }
1161 }
1162
1163
1164 /* Operating Mode Check */
1165 if ( (db->dm910x_chk_mode & 0x1) &&
2765df58 1166 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1da177e4
LT		 1167 db->dm910x_chk_mode = 0x4;
1168
1169 /* Dynamic reset DM910X : system error or transmit time-out */
1170 tmp_cr8 = inl(db->ioaddr + DCR8);
1171 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1172 db->reset_cr8++;
1173 db->wait_reset = 1;
1174 }
1175 db->interval_rx_cnt = 0;
1176
1177 /* TX polling kick monitor */
1178 if ( db->tx_packet_cnt &&
1ae5dc34 1179 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1da177e4
LT		 1180 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1181
1182 /* TX Timeout */
1ae5dc34 1183 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
1da177e4
LT		 1184 db->reset_TXtimeout++;
1185 db->wait_reset = 1;
dde7c8ef 1186 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1da177e4
LT		 1187 }
1188 }
1189
1190 if (db->wait_reset) {
1191 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1192 db->reset_count++;
1193 dmfe_dynamic_reset(dev);
1194 db->first_in_callback = 0;
1195 db->timer.expires = DMFE_TIMER_WUT;
1196 add_timer(&db->timer);
1197 spin_unlock_irqrestore(&db->lock, flags);
1198 return;
1199 }
1200
1201 /* Link status check, Dynamic media type change */
1202 if (db->chip_id == PCI_DM9132_ID)
1203 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1204 else
1205 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1206
1207 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1208 (db->chip_revision == 0x30)) ||
1da177e4 1209 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1210 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1211 /* DM9102A Chip */
1212 if (tmp_cr12 & 2)
cfa51b9d 1213 link_ok = 0;
1da177e4 1214 else
cfa51b9d 1215 link_ok = 1;
1da177e4 1216 }
cfa51b9d
ML		 1217 else
1218 /*0x43 is used instead of 0x3 because bit 6 should represent
1219 link status of external PHY */
1220 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1221
1222
1223 /* If chip reports that link is failed it could be because external
25985edc 1224 PHY link status pin is not connected correctly to chip
cfa51b9d
ML		 1225 To be sure ask PHY too.
1226 */
1227
1228 /* need a dummy read because of PHY's register latch*/
1229 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1230 link_ok_phy = (phy_read (db->ioaddr,
1231 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1232
cfa51b9d
ML		 1233 if (link_ok_phy != link_ok) {
1234 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1235 link_ok = link_ok | link_ok_phy;
1236 }
1237
1238 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1239 /* Link Failed */
1240 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1241 netif_carrier_off(dev);
1da177e4
LT		 1242
1243 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1244 /* AUTO or force 1M Homerun/Longrun don't need */
1245 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1246 phy_write(db->ioaddr, db->phy_addr,
1247 0, 0x1000, db->chip_id);
1da177e4
LT		 1248
1249 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1250 if (db->media_mode & DMFE_AUTO) {
1251 /* 10/100M link failed, used 1M Home-Net */
1252 db->cr6_data|=0x00040000; /* bit18=1, MII */
1253 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1254 update_cr6(db->cr6_data, db->ioaddr);
1255 }
cfa51b9d
ML		 1256 } else if (!netif_carrier_ok(dev)) {
1257
1258 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1259
1260 /* Auto Sense Speed */
1261 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1262 netif_carrier_on(dev);
1263 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1264 }
1265
cfa51b9d
ML		 1266 dmfe_process_mode(db);
1267 }
1268
1da177e4
LT		 1269 /* HPNA remote command check */
1270 if (db->HPNA_command & 0xf00) {
1271 db->HPNA_timer--;
1272 if (!db->HPNA_timer)
1273 dmfe_HPNA_remote_cmd_chk(db);
1274 }
1275
1276 /* Timer active again */
1277 db->timer.expires = DMFE_TIMER_WUT;
1278 add_timer(&db->timer);
1279 spin_unlock_irqrestore(&db->lock, flags);
1280}
1281
1282
1283/*
1284 * Dynamic reset the DM910X board
1285 * Stop DM910X board
1286 * Free Tx/Rx allocated memory
1287 * Reset DM910X board
421f91d2 1288 * Re-initialize DM910X board
1da177e4
LT		 1289 */
1290
1291static void dmfe_dynamic_reset(struct DEVICE *dev)
1292{
1293 struct dmfe_board_info *db = netdev_priv(dev);
1294
1295 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1296
1297 /* Sopt MAC controller */
1298 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1299 update_cr6(db->cr6_data, dev->base_addr);
1300 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1301 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1302
1303 /* Disable upper layer interface */
1304 netif_stop_queue(dev);
1305
1306 /* Free Rx Allocate buffer */
1307 dmfe_free_rxbuffer(db);
1308
1309 /* system variable init */
1310 db->tx_packet_cnt = 0;
1311 db->tx_queue_cnt = 0;
1312 db->rx_avail_cnt = 0;
cfa51b9d 1313 netif_carrier_off(dev);
1da177e4
LT		 1314 db->wait_reset = 0;
1315
421f91d2 1316 /* Re-initialize DM910X board */
1da177e4
LT		 1317 dmfe_init_dm910x(dev);
1318
1319 /* Restart upper layer interface */
1320 netif_wake_queue(dev);
1321}
1322
1323
1324/*
1325 * free all allocated rx buffer
1326 */
1327
1328static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1329{
1330 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1331
1332 /* free allocated rx buffer */
1333 while (db->rx_avail_cnt) {
1334 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1335 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1336 db->rx_avail_cnt--;
1337 }
1338}
1339
1340
1341/*
1342 * Reuse the SK buffer
1343 */
1344
1345static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1346{
1347 struct rx_desc *rxptr = db->rx_insert_ptr;
1348
1349 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1350 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1351 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1352 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1353 wmb();
1354 rxptr->rdes0 = cpu_to_le32(0x80000000);
1355 db->rx_avail_cnt++;
1356 db->rx_insert_ptr = rxptr->next_rx_desc;
1357 } else
1358 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1359}
1360
1361
1362/*
1363 * Initialize transmit/Receive descriptor
1364 * Using Chain structure, and allocate Tx/Rx buffer
1365 */
1366
1367static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1368{
1369 struct tx_desc *tmp_tx;
1370 struct rx_desc *tmp_rx;
1371 unsigned char *tmp_buf;
1372 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1373 dma_addr_t tmp_buf_dma;
1374 int i;
1375
1376 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1377
1378 /* tx descriptor start pointer */
1379 db->tx_insert_ptr = db->first_tx_desc;
1380 db->tx_remove_ptr = db->first_tx_desc;
1381 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1382
1383 /* rx descriptor start pointer */
f67ba792
ML		 1384 db->first_rx_desc = (void *)db->first_tx_desc +
1385 sizeof(struct tx_desc) * TX_DESC_CNT;
1386
1387 db->first_rx_desc_dma = db->first_tx_desc_dma +
1388 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1389 db->rx_insert_ptr = db->first_rx_desc;
1390 db->rx_ready_ptr = db->first_rx_desc;
1391 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1392
1393 /* Init Transmit chain */
1394 tmp_buf = db->buf_pool_start;
1395 tmp_buf_dma = db->buf_pool_dma_start;
1396 tmp_tx_dma = db->first_tx_desc_dma;
1397 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1398 tmp_tx->tx_buf_ptr = tmp_buf;
1399 tmp_tx->tdes0 = cpu_to_le32(0);
1400 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1401 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1402 tmp_tx_dma += sizeof(struct tx_desc);
1403 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1404 tmp_tx->next_tx_desc = tmp_tx + 1;
1405 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1406 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1407 }
1408 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1409 tmp_tx->next_tx_desc = db->first_tx_desc;
1410
1411 /* Init Receive descriptor chain */
1412 tmp_rx_dma=db->first_rx_desc_dma;
1413 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1414 tmp_rx->rdes0 = cpu_to_le32(0);
1415 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1416 tmp_rx_dma += sizeof(struct rx_desc);
1417 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1418 tmp_rx->next_rx_desc = tmp_rx + 1;
1419 }
1420 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1421 tmp_rx->next_rx_desc = db->first_rx_desc;
1422
1423 /* pre-allocate Rx buffer */
1424 allocate_rx_buffer(db);
1425}
1426
1427
1428/*
1429 * Update CR6 value
1430 * Firstly stop DM910X , then written value and start
1431 */
1432
1433static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1434{
1435 u32 cr6_tmp;
1436
1437 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1438 outl(cr6_tmp, ioaddr + DCR6);
1439 udelay(5);
1440 outl(cr6_data, ioaddr + DCR6);
1441 udelay(5);
1442}
1443
1444
1445/*
1446 * Send a setup frame for DM9132
421f91d2 1447 * This setup frame initialize DM910X address filter mode
1da177e4
LT		 1448*/
1449
4302b67e 1450static void dm9132_id_table(struct DEVICE *dev)
1da177e4 1451{
22bedad3 1452 struct netdev_hw_addr *ha;
1da177e4
LT		 1453 u16 * addrptr;
1454 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1455 u32 hash_val;
1456 u16 i, hash_table[4];
1457
1458 DMFE_DBUG(0, "dm9132_id_table()", 0);
1459
1460 /* Node address */
1461 addrptr = (u16 *) dev->dev_addr;
1462 outw(addrptr[0], ioaddr);
1463 ioaddr += 4;
1464 outw(addrptr[1], ioaddr);
1465 ioaddr += 4;
1466 outw(addrptr[2], ioaddr);
1467 ioaddr += 4;
1468
1469 /* Clear Hash Table */
4302b67e 1470 memset(hash_table, 0, sizeof(hash_table));
1da177e4
LT		 1471
1472 /* broadcast address */
1473 hash_table[3] = 0x8000;
1474
1475 /* the multicast address in Hash Table : 64 bits */
22bedad3
JP		 1476 netdev_for_each_mc_addr(ha, dev) {
1477 hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f;
1da177e4
LT		 1478 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1479 }
1480
1481 /* Write the hash table to MAC MD table */
1482 for (i = 0; i < 4; i++, ioaddr += 4)
1483 outw(hash_table[i], ioaddr);
1484}
1485
1486
1487/*
1488 * Send a setup frame for DM9102/DM9102A
421f91d2 1489 * This setup frame initialize DM910X address filter mode
1da177e4
LT		 1490 */
1491
4302b67e 1492static void send_filter_frame(struct DEVICE *dev)
1da177e4
LT		 1493{
1494 struct dmfe_board_info *db = netdev_priv(dev);
22bedad3 1495 struct netdev_hw_addr *ha;
1da177e4
LT		 1496 struct tx_desc *txptr;
1497 u16 * addrptr;
1498 u32 * suptr;
1499 int i;
1500
1501 DMFE_DBUG(0, "send_filter_frame()", 0);
1502
1503 txptr = db->tx_insert_ptr;
1504 suptr = (u32 *) txptr->tx_buf_ptr;
1505
1506 /* Node address */
1507 addrptr = (u16 *) dev->dev_addr;
1508 *suptr++ = addrptr[0];
1509 *suptr++ = addrptr[1];
1510 *suptr++ = addrptr[2];
1511
1512 /* broadcast address */
1513 *suptr++ = 0xffff;
1514 *suptr++ = 0xffff;
1515 *suptr++ = 0xffff;
1516
1517 /* fit the multicast address */
22bedad3
JP		 1518 netdev_for_each_mc_addr(ha, dev) {
1519 addrptr = (u16 *) ha->addr;
1da177e4
LT		 1520 *suptr++ = addrptr[0];
1521 *suptr++ = addrptr[1];
1522 *suptr++ = addrptr[2];
1523 }
1524
4302b67e 1525 for (i = netdev_mc_count(dev); i < 14; i++) {
1da177e4
LT		 1526 *suptr++ = 0xffff;
1527 *suptr++ = 0xffff;
1528 *suptr++ = 0xffff;
1529 }
1530
1531 /* prepare the setup frame */
1532 db->tx_insert_ptr = txptr->next_tx_desc;
1533 txptr->tdes1 = cpu_to_le32(0x890000c0);
1534
1535 /* Resource Check and Send the setup packet */
1536 if (!db->tx_packet_cnt) {
1537 /* Resource Empty */
1538 db->tx_packet_cnt++;
1539 txptr->tdes0 = cpu_to_le32(0x80000000);
1540 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1541 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1542 update_cr6(db->cr6_data, dev->base_addr);
1543 dev->trans_start = jiffies;
1544 } else
1545 db->tx_queue_cnt++; /* Put in TX queue */
1546}
1547
1548
1549/*
1550 * Allocate rx buffer,
1551 * As possible as allocate maxiumn Rx buffer
1552 */
1553
1554static void allocate_rx_buffer(struct dmfe_board_info *db)
1555{
1556 struct rx_desc *rxptr;
1557 struct sk_buff *skb;
1558
1559 rxptr = db->rx_insert_ptr;
1560
1561 while(db->rx_avail_cnt < RX_DESC_CNT) {
1562 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1563 break;
1564 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1565 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1566 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1567 wmb();
1568 rxptr->rdes0 = cpu_to_le32(0x80000000);
1569 rxptr = rxptr->next_rx_desc;
1570 db->rx_avail_cnt++;
1571 }
1572
1573 db->rx_insert_ptr = rxptr;
1574}
1575
1576
1577/*
1578 * Read one word data from the serial ROM
1579 */
1580
1581static u16 read_srom_word(long ioaddr, int offset)
1582{
1583 int i;
1584 u16 srom_data = 0;
1585 long cr9_ioaddr = ioaddr + DCR9;
1586
1587 outl(CR9_SROM_READ, cr9_ioaddr);
1588 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1589
1590 /* Send the Read Command 110b */
1591 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1592 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1593 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1594
1595 /* Send the offset */
1596 for (i = 5; i >= 0; i--) {
1597 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1598 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1599 }
1600
1601 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1602
1603 for (i = 16; i > 0; i--) {
1604 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1605 udelay(5);
f67ba792
ML		 1606 srom_data = (srom_data << 1) |
1607 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1608 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1609 udelay(5);
1610 }
1611
1612 outl(CR9_SROM_READ, cr9_ioaddr);
1613 return srom_data;
1614}
1615
1616
1617/*
1618 * Auto sense the media mode
1619 */
1620
1621static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1622{
1623 u8 ErrFlag = 0;
1624 u16 phy_mode;
1625
1626 /* CR6 bit18=0, select 10/100M */
1627 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1628
1629 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1630 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1631
1632 if ( (phy_mode & 0x24) == 0x24 ) {
1633 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1634 phy_mode = phy_read(db->ioaddr,
1635 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1636 else /* DM9102/DM9102A */
f67ba792
ML		 1637 phy_mode = phy_read(db->ioaddr,
1638 db->phy_addr, 17, db->chip_id) & 0xf000;
1da177e4
LT		 1639 switch (phy_mode) {
1640 case 0x1000: db->op_mode = DMFE_10MHF; break;
1641 case 0x2000: db->op_mode = DMFE_10MFD; break;
1642 case 0x4000: db->op_mode = DMFE_100MHF; break;
1643 case 0x8000: db->op_mode = DMFE_100MFD; break;
1644 default: db->op_mode = DMFE_10MHF;
1645 ErrFlag = 1;
1646 break;
1647 }
1648 } else {
1649 db->op_mode = DMFE_10MHF;
1650 DMFE_DBUG(0, "Link Failed :", phy_mode);
1651 ErrFlag = 1;
1652 }
1653
1654 return ErrFlag;
1655}
1656
1657
1658/*
1659 * Set 10/100 phyxcer capability
1660 * AUTO mode : phyxcer register4 is NIC capability
1661 * Force mode: phyxcer register4 is the force media
1662 */
1663
1664static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1665{
1666 u16 phy_reg;
1667
1668 /* Select 10/100M phyxcer */
1669 db->cr6_data &= ~0x40000;
1670 update_cr6(db->cr6_data, db->ioaddr);
1671
1672 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1673 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1674 phy_reg = phy_read(db->ioaddr,
1675 db->phy_addr, 18, db->chip_id) & ~0x1000;
1676
1677 phy_write(db->ioaddr,
1678 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1679 }
1680
1681 /* Phyxcer capability setting */
1682 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1683
1684 if (db->media_mode & DMFE_AUTO) {
1685 /* AUTO Mode */
1686 phy_reg |= db->PHY_reg4;
1687 } else {
1688 /* Force Mode */
1689 switch(db->media_mode) {
1690 case DMFE_10MHF: phy_reg |= 0x20; break;
1691 case DMFE_10MFD: phy_reg |= 0x40; break;
1692 case DMFE_100MHF: phy_reg |= 0x80; break;
1693 case DMFE_100MFD: phy_reg |= 0x100; break;
1694 }
1695 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1696 }
1697
1698 /* Write new capability to Phyxcer Reg4 */
1699 if ( !(phy_reg & 0x01e0)) {
1700 phy_reg|=db->PHY_reg4;
1701 db->media_mode|=DMFE_AUTO;
1702 }
1703 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1704
1705 /* Restart Auto-Negotiation */
1706 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1707 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1708 if ( !db->chip_type )
1709 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1710}
1711
1712
1713/*
1714 * Process op-mode
1715 * AUTO mode : PHY controller in Auto-negotiation Mode
1716 * Force mode: PHY controller in force mode with HUB
1717 * N-way force capability with SWITCH
1718 */
1719
1720static void dmfe_process_mode(struct dmfe_board_info *db)
1721{
1722 u16 phy_reg;
1723
1724 /* Full Duplex Mode Check */
1725 if (db->op_mode & 0x4)
1726 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1727 else
1728 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1729
1730 /* Transciver Selection */
1731 if (db->op_mode & 0x10) /* 1M HomePNA */
1732 db->cr6_data |= 0x40000;/* External MII select */
1733 else
1734 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1735
1736 update_cr6(db->cr6_data, db->ioaddr);
1737
1738 /* 10/100M phyxcer force mode need */
1739 if ( !(db->media_mode & 0x18)) {
1740 /* Forece Mode */
1741 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1742 if ( !(phy_reg & 0x1) ) {
1743 /* parter without N-Way capability */
1744 phy_reg = 0x0;
1745 switch(db->op_mode) {
1746 case DMFE_10MHF: phy_reg = 0x0; break;
1747 case DMFE_10MFD: phy_reg = 0x100; break;
1748 case DMFE_100MHF: phy_reg = 0x2000; break;
1749 case DMFE_100MFD: phy_reg = 0x2100; break;
1750 }
f67ba792
ML		 1751 phy_write(db->ioaddr,
1752 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1753 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1754 mdelay(20);
f67ba792
ML		 1755 phy_write(db->ioaddr,
1756 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1757 }
1758 }
1759}
1760
1761
1762/*
1763 * Write a word to Phy register
1764 */
1765
f67ba792
ML		 1766static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1767 u16 phy_data, u32 chip_id)
1da177e4
LT		 1768{
1769 u16 i;
1770 unsigned long ioaddr;
1771
1772 if (chip_id == PCI_DM9132_ID) {
1773 ioaddr = iobase + 0x80 + offset * 4;
1774 outw(phy_data, ioaddr);
1775 } else {
1776 /* DM9102/DM9102A Chip */
1777 ioaddr = iobase + DCR9;
1778
1779 /* Send 33 synchronization clock to Phy controller */
1780 for (i = 0; i < 35; i++)
1781 phy_write_1bit(ioaddr, PHY_DATA_1);
1782
1783 /* Send start command(01) to Phy */
1784 phy_write_1bit(ioaddr, PHY_DATA_0);
1785 phy_write_1bit(ioaddr, PHY_DATA_1);
1786
1787 /* Send write command(01) to Phy */
1788 phy_write_1bit(ioaddr, PHY_DATA_0);
1789 phy_write_1bit(ioaddr, PHY_DATA_1);
1790
1791 /* Send Phy address */
1792 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1793 phy_write_1bit(ioaddr,
1794 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1795
1796 /* Send register address */
1797 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1798 phy_write_1bit(ioaddr,
1799 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1800
1801 /* written trasnition */
1802 phy_write_1bit(ioaddr, PHY_DATA_1);
1803 phy_write_1bit(ioaddr, PHY_DATA_0);
1804
1805 /* Write a word data to PHY controller */
1806 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1807 phy_write_1bit(ioaddr,
1808 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1809 }
1810}
1811
1812
1813/*
1814 * Read a word data from phy register
1815 */
1816
1817static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1818{
1819 int i;
1820 u16 phy_data;
1821 unsigned long ioaddr;
1822
1823 if (chip_id == PCI_DM9132_ID) {
1824 /* DM9132 Chip */
1825 ioaddr = iobase + 0x80 + offset * 4;
1826 phy_data = inw(ioaddr);
1827 } else {
1828 /* DM9102/DM9102A Chip */
1829 ioaddr = iobase + DCR9;
1830
1831 /* Send 33 synchronization clock to Phy controller */
1832 for (i = 0; i < 35; i++)
1833 phy_write_1bit(ioaddr, PHY_DATA_1);
1834
1835 /* Send start command(01) to Phy */
1836 phy_write_1bit(ioaddr, PHY_DATA_0);
1837 phy_write_1bit(ioaddr, PHY_DATA_1);
1838
1839 /* Send read command(10) to Phy */
1840 phy_write_1bit(ioaddr, PHY_DATA_1);
1841 phy_write_1bit(ioaddr, PHY_DATA_0);
1842
1843 /* Send Phy address */
1844 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1845 phy_write_1bit(ioaddr,
1846 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1847
1848 /* Send register address */
1849 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1850 phy_write_1bit(ioaddr,
1851 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1852
1853 /* Skip transition state */
1854 phy_read_1bit(ioaddr);
1855
1856 /* read 16bit data */
1857 for (phy_data = 0, i = 0; i < 16; i++) {
1858 phy_data <<= 1;
1859 phy_data |= phy_read_1bit(ioaddr);
1860 }
1861 }
1862
1863 return phy_data;
1864}
1865
1866
1867/*
1868 * Write one bit data to Phy Controller
1869 */
1870
1871static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1872{
1873 outl(phy_data, ioaddr); /* MII Clock Low */
1874 udelay(1);
1875 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1876 udelay(1);
1877 outl(phy_data, ioaddr); /* MII Clock Low */
1878 udelay(1);
1879}
1880
1881
1882/*
1883 * Read one bit phy data from PHY controller
1884 */
1885
1886static u16 phy_read_1bit(unsigned long ioaddr)
1887{
1888 u16 phy_data;
1889
1890 outl(0x50000, ioaddr);
1891 udelay(1);
1892 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1893 outl(0x40000, ioaddr);
1894 udelay(1);
1895
1896 return phy_data;
1897}
1898
1899
1900/*
1901 * Parser SROM and media mode
1902 */
1903
1904static void dmfe_parse_srom(struct dmfe_board_info * db)
1905{
1906 char * srom = db->srom;
1907 int dmfe_mode, tmp_reg;
1908
1909 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1910
1911 /* Init CR15 */
1912 db->cr15_data = CR15_DEFAULT;
1913
1914 /* Check SROM Version */
1915 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1916 /* SROM V4.01 */
1917 /* Get NIC support media mode */
4c93566e 1918 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1919 db->PHY_reg4 = 0;
1920 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1921 switch( db->NIC_capability & tmp_reg ) {
1922 case 0x1: db->PHY_reg4 |= 0x0020; break;
1923 case 0x2: db->PHY_reg4 |= 0x0040; break;
1924 case 0x4: db->PHY_reg4 |= 0x0080; break;
1925 case 0x8: db->PHY_reg4 |= 0x0100; break;
1926 }
1927 }
1928
1929 /* Media Mode Force or not check */
4c93566e
DM		 1930 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1931 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1932 switch(dmfe_mode) {
1933 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1934 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1935 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1936 case 0x100:
1937 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1938 }
1939
1940 /* Special Function setting */
1941 /* VLAN function */
1942 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1943 db->cr15_data |= 0x40;
1944
1945 /* Flow Control */
1946 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1947 db->cr15_data |= 0x400;
1948
1949 /* TX pause packet */
1950 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1951 db->cr15_data |= 0x9800;
1952 }
1953
1954 /* Parse HPNA parameter */
1955 db->HPNA_command = 1;
1956
1957 /* Accept remote command or not */
1958 if (HPNA_rx_cmd == 0)
1959 db->HPNA_command |= 0x8000;
1960
1961 /* Issue remote command & operation mode */
1962 if (HPNA_tx_cmd == 1)
1963 switch(HPNA_mode) { /* Issue Remote Command */
1964 case 0: db->HPNA_command |= 0x0904; break;
1965 case 1: db->HPNA_command |= 0x0a00; break;
1966 case 2: db->HPNA_command |= 0x0506; break;
1967 case 3: db->HPNA_command |= 0x0602; break;
1968 }
1969 else
1970 switch(HPNA_mode) { /* Don't Issue */
1971 case 0: db->HPNA_command |= 0x0004; break;
1972 case 1: db->HPNA_command |= 0x0000; break;
1973 case 2: db->HPNA_command |= 0x0006; break;
1974 case 3: db->HPNA_command |= 0x0002; break;
1975 }
1976
1977 /* Check DM9801 or DM9802 present or not */
1978 db->HPNA_present = 0;
1979 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1980 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1981 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1982 /* DM9801 or DM9802 present */
1983 db->HPNA_timer = 8;
1984 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1985 /* DM9801 HomeRun */
1986 db->HPNA_present = 1;
1987 dmfe_program_DM9801(db, tmp_reg);
1988 } else {
1989 /* DM9802 LongRun */
1990 db->HPNA_present = 2;
1991 dmfe_program_DM9802(db);
1992 }
1993 }
1994
1995}
1996
1997
1998/*
1999 * Init HomeRun DM9801
2000 */
2001
2002static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2003{
2004 uint reg17, reg25;
2005
2006 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2007 switch(HPNA_rev) {
2008 case 0xb900: /* DM9801 E3 */
2009 db->HPNA_command |= 0x1000;
2010 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2011 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2012 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2013 break;
2014 case 0xb901: /* DM9801 E4 */
2015 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2016 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2017 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2018 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2019 break;
2020 case 0xb902: /* DM9801 E5 */
2021 case 0xb903: /* DM9801 E6 */
2022 default:
2023 db->HPNA_command |= 0x1000;
2024 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2025 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2026 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2027 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2028 break;
2029 }
2030 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2031 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2032 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2033}
2034
2035
2036/*
2037 * Init HomeRun DM9802
2038 */
2039
2040static void dmfe_program_DM9802(struct dmfe_board_info * db)
2041{
2042 uint phy_reg;
2043
2044 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2045 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2046 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2047 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2048 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2049}
2050
2051
2052/*
2053 * Check remote HPNA power and speed status. If not correct,
2054 * issue command again.
2055*/
2056
2057static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2058{
2059 uint phy_reg;
2060
2061 /* Got remote device status */
2062 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2063 switch(phy_reg) {
2064 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2065 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2066 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2067 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2068 }
2069
2070 /* Check remote device status match our setting ot not */
2071 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2072 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2073 db->chip_id);
1da177e4
LT		 2074 db->HPNA_timer=8;
2075 } else
2076 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2077}
2078
2079
2080
a3aa1884 2081static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
1da177e4
LT		 2082 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2083 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2084 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2085 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2086 { 0, }
2087};
2088MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2089
2090
bc8a8387
ML		 2091#ifdef CONFIG_PM
2092static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2093{
2094 struct net_device *dev = pci_get_drvdata(pci_dev);
2095 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2096 u32 tmp;
bc8a8387
ML		 2097
2098 /* Disable upper layer interface */
2099 netif_device_detach(dev);
2100
2101 /* Disable Tx/Rx */
2102 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2103 update_cr6(db->cr6_data, dev->base_addr);
2104
2105 /* Disable Interrupt */
2106 outl(0, dev->base_addr + DCR7);
2107 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2108
2109 /* Fre RX buffers */
2110 dmfe_free_rxbuffer(db);
2111
f1069046
ML		 2112 /* Enable WOL */
2113 pci_read_config_dword(pci_dev, 0x40, &tmp);
2114 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2115
2116 if (db->wol_mode & WAKE_PHY)
2117 tmp |= DMFE_WOL_LINKCHANGE;
2118 if (db->wol_mode & WAKE_MAGIC)
2119 tmp |= DMFE_WOL_MAGICPACKET;
2120
2121 pci_write_config_dword(pci_dev, 0x40, tmp);
2122
2123 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2124 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2125
bc8a8387 2126 /* Power down device*/
bc8a8387 2127 pci_save_state(pci_dev);
a31e23e1 2128 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2129
2130 return 0;
2131}
2132
2133static int dmfe_resume(struct pci_dev *pci_dev)
2134{
2135 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2136 u32 tmp;
bc8a8387 2137
bc8a8387 2138 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2139 pci_restore_state(pci_dev);
bc8a8387 2140
421f91d2 2141 /* Re-initialize DM910X board */
bc8a8387
ML		 2142 dmfe_init_dm910x(dev);
2143
f1069046
ML		 2144 /* Disable WOL */
2145 pci_read_config_dword(pci_dev, 0x40, &tmp);
2146
2147 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2148 pci_write_config_dword(pci_dev, 0x40, tmp);
2149
2150 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2151 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2152
bc8a8387
ML		 2153 /* Restart upper layer interface */
2154 netif_device_attach(dev);
2155
2156 return 0;
2157}
2158#else
2159#define dmfe_suspend NULL
2160#define dmfe_resume NULL
2161#endif
2162
1da177e4
LT		 2163static struct pci_driver dmfe_driver = {
2164 .name = "dmfe",
2165 .id_table = dmfe_pci_tbl,
2166 .probe = dmfe_init_one,
2167 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2168 .suspend = dmfe_suspend,
2169 .resume = dmfe_resume
1da177e4
LT		 2170};
2171
2172MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2173MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2174MODULE_LICENSE("GPL");
2175MODULE_VERSION(DRV_VERSION);
2176
2177module_param(debug, int, 0);
2178module_param(mode, byte, 0);
2179module_param(cr6set, int, 0);
2180module_param(chkmode, byte, 0);
2181module_param(HPNA_mode, byte, 0);
2182module_param(HPNA_rx_cmd, byte, 0);
2183module_param(HPNA_tx_cmd, byte, 0);
2184module_param(HPNA_NoiseFloor, byte, 0);
2185module_param(SF_mode, byte, 0);
2186MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2187MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2188 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2189
2190MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2191 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2192
2193/* Description:
2194 * when user used insmod to add module, system invoked init_module()
421f91d2 2195 * to initialize and register.
1da177e4
LT		 2196 */
2197
2198static int __init dmfe_init_module(void)
2199{
2200 int rc;
2201
1c3319fb 2202 pr_info("%s\n", version);
1da177e4
LT		 2203 printed_version = 1;
2204
2205 DMFE_DBUG(0, "init_module() ", debug);
2206
2207 if (debug)
2208 dmfe_debug = debug; /* set debug flag */
2209 if (cr6set)
2210 dmfe_cr6_user_set = cr6set;
2211
2212 switch(mode) {
2213 case DMFE_10MHF:
2214 case DMFE_100MHF:
2215 case DMFE_10MFD:
2216 case DMFE_100MFD:
2217 case DMFE_1M_HPNA:
2218 dmfe_media_mode = mode;
2219 break;
2220 default:dmfe_media_mode = DMFE_AUTO;
2221 break;
2222 }
2223
2224 if (HPNA_mode > 4)
2225 HPNA_mode = 0; /* Default: LP/HS */
2226 if (HPNA_rx_cmd > 1)
2227 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2228 if (HPNA_tx_cmd > 1)
2229 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2230 if (HPNA_NoiseFloor > 15)
2231 HPNA_NoiseFloor = 0;
2232
29917620 2233 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2234 if (rc < 0)
2235 return rc;
2236
2237 return 0;
2238}
2239
2240
2241/*
2242 * Description:
2243 * when user used rmmod to delete module, system invoked clean_module()
2244 * to un-register all registered services.
2245 */
2246
2247static void __exit dmfe_cleanup_module(void)
2248{
2249 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2250 pci_unregister_driver(&dmfe_driver);
2251}
2252
2253module_init(dmfe_init_module);
2254module_exit(dmfe_cleanup_module);
Linux kernel - Deliverables
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