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be2net: Fix unnecessary delay in PCI EEH
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_main.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
70c71606 18#include <linux/prefetch.h>
9d9779e7 19#include <linux/module.h>
6b7c5b94 20#include "be.h"
8788fdc2 21#include "be_cmds.h"
65f71b8b 22#include <asm/div64.h>
d6b6d987 23#include <linux/aer.h>
6b7c5b94
SP		 24
25MODULE_VERSION(DRV_VER);
26MODULE_DEVICE_TABLE(pci, be_dev_ids);
27MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
28MODULE_AUTHOR("ServerEngines Corporation");
29MODULE_LICENSE("GPL");
30
ba343c77 31static unsigned int num_vfs;
ba343c77 32module_param(num_vfs, uint, S_IRUGO);
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
11ac75ed
SP		 35static ushort rx_frag_size = 2048;
36module_param(rx_frag_size, ushort, S_IRUGO);
37MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
38
6b7c5b94 39static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 40 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 41 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 42 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
43 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
fe6d2a38 44 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
12f4d0a8 45 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID4)},
ecedb6ae 46 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID5)},
6b7c5b94
SP		 47 { 0 }
48};
49MODULE_DEVICE_TABLE(pci, be_dev_ids);
7c185276 50/* UE Status Low CSR */
42c8b11e 51static const char * const ue_status_low_desc[] = {
7c185276
AK		 52 "CEV",
53 "CTX",
54 "DBUF",
55 "ERX",
56 "Host",
57 "MPU",
58 "NDMA",
59 "PTC ",
60 "RDMA ",
61 "RXF ",
62 "RXIPS ",
63 "RXULP0 ",
64 "RXULP1 ",
65 "RXULP2 ",
66 "TIM ",
67 "TPOST ",
68 "TPRE ",
69 "TXIPS ",
70 "TXULP0 ",
71 "TXULP1 ",
72 "UC ",
73 "WDMA ",
74 "TXULP2 ",
75 "HOST1 ",
76 "P0_OB_LINK ",
77 "P1_OB_LINK ",
78 "HOST_GPIO ",
79 "MBOX ",
80 "AXGMAC0",
81 "AXGMAC1",
82 "JTAG",
83 "MPU_INTPEND"
84};
85/* UE Status High CSR */
42c8b11e 86static const char * const ue_status_hi_desc[] = {
7c185276
AK		 87 "LPCMEMHOST",
88 "MGMT_MAC",
89 "PCS0ONLINE",
90 "MPU_IRAM",
91 "PCS1ONLINE",
92 "PCTL0",
93 "PCTL1",
94 "PMEM",
95 "RR",
96 "TXPB",
97 "RXPP",
98 "XAUI",
99 "TXP",
100 "ARM",
101 "IPC",
102 "HOST2",
103 "HOST3",
104 "HOST4",
105 "HOST5",
106 "HOST6",
107 "HOST7",
108 "HOST8",
109 "HOST9",
42c8b11e 110 "NETC",
7c185276
AK		 111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown",
116 "Unknown",
117 "Unknown",
118 "Unknown"
119};
6b7c5b94 120
752961a1
SP		 121/* Is BE in a multi-channel mode */
122static inline bool be_is_mc(struct be_adapter *adapter) {
123 return (adapter->function_mode & FLEX10_MODE ||
124 adapter->function_mode & VNIC_MODE ||
125 adapter->function_mode & UMC_ENABLED);
126}
127
6b7c5b94
SP		 128static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
129{
130 struct be_dma_mem *mem = &q->dma_mem;
1cfafab9 131 if (mem->va) {
2b7bcebf
IV		 132 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
133 mem->dma);
1cfafab9
SP		 134 mem->va = NULL;
135 }
6b7c5b94
SP		 136}
137
138static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
139 u16 len, u16 entry_size)
140{
141 struct be_dma_mem *mem = &q->dma_mem;
142
143 memset(q, 0, sizeof(*q));
144 q->len = len;
145 q->entry_size = entry_size;
146 mem->size = len * entry_size;
2b7bcebf
IV		 147 mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma,
148 GFP_KERNEL);
6b7c5b94 149 if (!mem->va)
10ef9ab4 150 return -ENOMEM;
6b7c5b94
SP		 151 memset(mem->va, 0, mem->size);
152 return 0;
153}
154
8788fdc2 155static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 156{
db3ea781 157 u32 reg, enabled;
5f0b849e 158
f67ef7ba 159 if (adapter->eeh_error)
cf588477
SP		 160 return;
161
db3ea781
SP		 162 pci_read_config_dword(adapter->pdev, PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET,
163 &reg);
164 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
165
5f0b849e 166 if (!enabled && enable)
6b7c5b94 167 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 168 else if (enabled && !enable)
6b7c5b94 169 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 170 else
6b7c5b94 171 return;
5f0b849e 172
db3ea781
SP		 173 pci_write_config_dword(adapter->pdev,
174 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, reg);
6b7c5b94
SP		 175}
176
8788fdc2 177static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 178{
179 u32 val = 0;
180 val |= qid & DB_RQ_RING_ID_MASK;
181 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 182
183 wmb();
8788fdc2 184 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 185}
186
8788fdc2 187static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 188{
189 u32 val = 0;
190 val |= qid & DB_TXULP_RING_ID_MASK;
191 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 192
193 wmb();
8788fdc2 194 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 195}
196
8788fdc2 197static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 198 bool arm, bool clear_int, u16 num_popped)
199{
200 u32 val = 0;
201 val |= qid & DB_EQ_RING_ID_MASK;
fe6d2a38
SP		 202 val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
203 DB_EQ_RING_ID_EXT_MASK_SHIFT);
cf588477 204
f67ef7ba 205 if (adapter->eeh_error)
cf588477
SP		 206 return;
207
6b7c5b94
SP		 208 if (arm)
209 val |= 1 << DB_EQ_REARM_SHIFT;
210 if (clear_int)
211 val |= 1 << DB_EQ_CLR_SHIFT;
212 val |= 1 << DB_EQ_EVNT_SHIFT;
213 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 214 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 215}
216
8788fdc2 217void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 218{
219 u32 val = 0;
220 val |= qid & DB_CQ_RING_ID_MASK;
fe6d2a38
SP		 221 val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
222 DB_CQ_RING_ID_EXT_MASK_SHIFT);
cf588477 223
f67ef7ba 224 if (adapter->eeh_error)
cf588477
SP		 225 return;
226
6b7c5b94
SP		 227 if (arm)
228 val |= 1 << DB_CQ_REARM_SHIFT;
229 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 230 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 231}
232
6b7c5b94
SP		 233static int be_mac_addr_set(struct net_device *netdev, void *p)
234{
235 struct be_adapter *adapter = netdev_priv(netdev);
236 struct sockaddr *addr = p;
237 int status = 0;
e3a7ae2c 238 u8 current_mac[ETH_ALEN];
fbc13f01 239 u32 pmac_id = adapter->pmac_id[0];
704e4c88 240 bool active_mac = true;
6b7c5b94 241
ca9e4988
AK		 242 if (!is_valid_ether_addr(addr->sa_data))
243 return -EADDRNOTAVAIL;
244
704e4c88
PR		 245 /* For BE VF, MAC address is already activated by PF.
246 * Hence only operation left is updating netdev->devaddr.
247 * Update it if user is passing the same MAC which was used
248 * during configuring VF MAC from PF(Hypervisor).
249 */
250 if (!lancer_chip(adapter) && !be_physfn(adapter)) {
251 status = be_cmd_mac_addr_query(adapter, current_mac,
252 false, adapter->if_handle, 0);
253 if (!status && !memcmp(current_mac, addr->sa_data, ETH_ALEN))
254 goto done;
255 else
256 goto err;
257 }
258
259 if (!memcmp(addr->sa_data, netdev->dev_addr, ETH_ALEN))
260 goto done;
261
262 /* For Lancer check if any MAC is active.
263 * If active, get its mac id.
264 */
265 if (lancer_chip(adapter) && !be_physfn(adapter))
266 be_cmd_get_mac_from_list(adapter, current_mac, &active_mac,
267 &pmac_id, 0);
268
269 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
270 adapter->if_handle,
271 &adapter->pmac_id[0], 0);
272
a65027e4 273 if (status)
e3a7ae2c 274 goto err;
6b7c5b94 275
704e4c88
PR		 276 if (active_mac)
277 be_cmd_pmac_del(adapter, adapter->if_handle,
278 pmac_id, 0);
279done:
e3a7ae2c
SK		 280 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
281 return 0;
282err:
283 dev_err(&adapter->pdev->dev, "MAC %pM set Failed\n", addr->sa_data);
6b7c5b94
SP		 284 return status;
285}
286
89a88ab8
AK		 287static void populate_be2_stats(struct be_adapter *adapter)
288{
ac124ff9
SP		 289 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
290 struct be_pmem_stats *pmem_sts = &hw_stats->pmem;
291 struct be_rxf_stats_v0 *rxf_stats = &hw_stats->rxf;
89a88ab8 292 struct be_port_rxf_stats_v0 *port_stats =
ac124ff9
SP		 293 &rxf_stats->port[adapter->port_num];
294 struct be_drv_stats *drvs = &adapter->drv_stats;
89a88ab8 295
ac124ff9 296 be_dws_le_to_cpu(hw_stats, sizeof(*hw_stats));
89a88ab8
AK		 297 drvs->rx_pause_frames = port_stats->rx_pause_frames;
298 drvs->rx_crc_errors = port_stats->rx_crc_errors;
299 drvs->rx_control_frames = port_stats->rx_control_frames;
300 drvs->rx_in_range_errors = port_stats->rx_in_range_errors;
301 drvs->rx_frame_too_long = port_stats->rx_frame_too_long;
302 drvs->rx_dropped_runt = port_stats->rx_dropped_runt;
303 drvs->rx_ip_checksum_errs = port_stats->rx_ip_checksum_errs;
304 drvs->rx_tcp_checksum_errs = port_stats->rx_tcp_checksum_errs;
305 drvs->rx_udp_checksum_errs = port_stats->rx_udp_checksum_errs;
306 drvs->rxpp_fifo_overflow_drop = port_stats->rx_fifo_overflow;
307 drvs->rx_dropped_tcp_length = port_stats->rx_dropped_tcp_length;
308 drvs->rx_dropped_too_small = port_stats->rx_dropped_too_small;
309 drvs->rx_dropped_too_short = port_stats->rx_dropped_too_short;
310 drvs->rx_out_range_errors = port_stats->rx_out_range_errors;
ac124ff9 311 drvs->rx_input_fifo_overflow_drop = port_stats->rx_input_fifo_overflow;
89a88ab8
AK		 312 drvs->rx_dropped_header_too_small =
313 port_stats->rx_dropped_header_too_small;
d45b9d39
SP		 314 drvs->rx_address_mismatch_drops =
315 port_stats->rx_address_mismatch_drops +
316 port_stats->rx_vlan_mismatch_drops;
89a88ab8
AK		 317 drvs->rx_alignment_symbol_errors =
318 port_stats->rx_alignment_symbol_errors;
319
320 drvs->tx_pauseframes = port_stats->tx_pauseframes;
321 drvs->tx_controlframes = port_stats->tx_controlframes;
322
323 if (adapter->port_num)
ac124ff9 324 drvs->jabber_events = rxf_stats->port1_jabber_events;
89a88ab8 325 else
ac124ff9 326 drvs->jabber_events = rxf_stats->port0_jabber_events;
89a88ab8 327 drvs->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf;
89a88ab8 328 drvs->rx_drops_no_erx_descr = rxf_stats->rx_drops_no_erx_descr;
89a88ab8
AK		 329 drvs->forwarded_packets = rxf_stats->forwarded_packets;
330 drvs->rx_drops_mtu = rxf_stats->rx_drops_mtu;
ac124ff9
SP		 331 drvs->rx_drops_no_tpre_descr = rxf_stats->rx_drops_no_tpre_descr;
332 drvs->rx_drops_too_many_frags = rxf_stats->rx_drops_too_many_frags;
89a88ab8
AK		 333 adapter->drv_stats.eth_red_drops = pmem_sts->eth_red_drops;
334}
335
336static void populate_be3_stats(struct be_adapter *adapter)
337{
ac124ff9
SP		 338 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
339 struct be_pmem_stats *pmem_sts = &hw_stats->pmem;
340 struct be_rxf_stats_v1 *rxf_stats = &hw_stats->rxf;
89a88ab8 341 struct be_port_rxf_stats_v1 *port_stats =
ac124ff9
SP		 342 &rxf_stats->port[adapter->port_num];
343 struct be_drv_stats *drvs = &adapter->drv_stats;
89a88ab8 344
ac124ff9 345 be_dws_le_to_cpu(hw_stats, sizeof(*hw_stats));
02fe7027
AK		 346 drvs->pmem_fifo_overflow_drop = port_stats->pmem_fifo_overflow_drop;
347 drvs->rx_priority_pause_frames = port_stats->rx_priority_pause_frames;
89a88ab8
AK		 348 drvs->rx_pause_frames = port_stats->rx_pause_frames;
349 drvs->rx_crc_errors = port_stats->rx_crc_errors;
350 drvs->rx_control_frames = port_stats->rx_control_frames;
351 drvs->rx_in_range_errors = port_stats->rx_in_range_errors;
352 drvs->rx_frame_too_long = port_stats->rx_frame_too_long;
353 drvs->rx_dropped_runt = port_stats->rx_dropped_runt;
354 drvs->rx_ip_checksum_errs = port_stats->rx_ip_checksum_errs;
355 drvs->rx_tcp_checksum_errs = port_stats->rx_tcp_checksum_errs;
356 drvs->rx_udp_checksum_errs = port_stats->rx_udp_checksum_errs;
357 drvs->rx_dropped_tcp_length = port_stats->rx_dropped_tcp_length;
358 drvs->rx_dropped_too_small = port_stats->rx_dropped_too_small;
359 drvs->rx_dropped_too_short = port_stats->rx_dropped_too_short;
360 drvs->rx_out_range_errors = port_stats->rx_out_range_errors;
361 drvs->rx_dropped_header_too_small =
362 port_stats->rx_dropped_header_too_small;
363 drvs->rx_input_fifo_overflow_drop =
364 port_stats->rx_input_fifo_overflow_drop;
d45b9d39 365 drvs->rx_address_mismatch_drops = port_stats->rx_address_mismatch_drops;
89a88ab8
AK		 366 drvs->rx_alignment_symbol_errors =
367 port_stats->rx_alignment_symbol_errors;
ac124ff9 368 drvs->rxpp_fifo_overflow_drop = port_stats->rxpp_fifo_overflow_drop;
89a88ab8
AK		 369 drvs->tx_pauseframes = port_stats->tx_pauseframes;
370 drvs->tx_controlframes = port_stats->tx_controlframes;
371 drvs->jabber_events = port_stats->jabber_events;
372 drvs->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf;
89a88ab8 373 drvs->rx_drops_no_erx_descr = rxf_stats->rx_drops_no_erx_descr;
89a88ab8
AK		 374 drvs->forwarded_packets = rxf_stats->forwarded_packets;
375 drvs->rx_drops_mtu = rxf_stats->rx_drops_mtu;
ac124ff9
SP		 376 drvs->rx_drops_no_tpre_descr = rxf_stats->rx_drops_no_tpre_descr;
377 drvs->rx_drops_too_many_frags = rxf_stats->rx_drops_too_many_frags;
89a88ab8
AK		 378 adapter->drv_stats.eth_red_drops = pmem_sts->eth_red_drops;
379}
380
005d5696
SX		 381static void populate_lancer_stats(struct be_adapter *adapter)
382{
89a88ab8 383
005d5696 384 struct be_drv_stats *drvs = &adapter->drv_stats;
ac124ff9
SP		 385 struct lancer_pport_stats *pport_stats =
386 pport_stats_from_cmd(adapter);
387
388 be_dws_le_to_cpu(pport_stats, sizeof(*pport_stats));
389 drvs->rx_pause_frames = pport_stats->rx_pause_frames_lo;
390 drvs->rx_crc_errors = pport_stats->rx_crc_errors_lo;
391 drvs->rx_control_frames = pport_stats->rx_control_frames_lo;
005d5696 392 drvs->rx_in_range_errors = pport_stats->rx_in_range_errors;
ac124ff9 393 drvs->rx_frame_too_long = pport_stats->rx_frames_too_long_lo;
005d5696
SX		 394 drvs->rx_dropped_runt = pport_stats->rx_dropped_runt;
395 drvs->rx_ip_checksum_errs = pport_stats->rx_ip_checksum_errors;
396 drvs->rx_tcp_checksum_errs = pport_stats->rx_tcp_checksum_errors;
397 drvs->rx_udp_checksum_errs = pport_stats->rx_udp_checksum_errors;
398 drvs->rx_dropped_tcp_length =
399 pport_stats->rx_dropped_invalid_tcp_length;
400 drvs->rx_dropped_too_small = pport_stats->rx_dropped_too_small;
401 drvs->rx_dropped_too_short = pport_stats->rx_dropped_too_short;
402 drvs->rx_out_range_errors = pport_stats->rx_out_of_range_errors;
403 drvs->rx_dropped_header_too_small =
404 pport_stats->rx_dropped_header_too_small;
405 drvs->rx_input_fifo_overflow_drop = pport_stats->rx_fifo_overflow;
d45b9d39
SP		 406 drvs->rx_address_mismatch_drops =
407 pport_stats->rx_address_mismatch_drops +
408 pport_stats->rx_vlan_mismatch_drops;
ac124ff9 409 drvs->rx_alignment_symbol_errors = pport_stats->rx_symbol_errors_lo;
005d5696 410 drvs->rxpp_fifo_overflow_drop = pport_stats->rx_fifo_overflow;
ac124ff9
SP		 411 drvs->tx_pauseframes = pport_stats->tx_pause_frames_lo;
412 drvs->tx_controlframes = pport_stats->tx_control_frames_lo;
005d5696 413 drvs->jabber_events = pport_stats->rx_jabbers;
ac124ff9
SP		 414 drvs->forwarded_packets = pport_stats->num_forwards_lo;
415 drvs->rx_drops_mtu = pport_stats->rx_drops_mtu_lo;
005d5696 416 drvs->rx_drops_too_many_frags =
ac124ff9 417 pport_stats->rx_drops_too_many_frags_lo;
005d5696 418}
89a88ab8 419
09c1c68f
SP		 420static void accumulate_16bit_val(u32 *acc, u16 val)
421{
422#define lo(x) (x & 0xFFFF)
423#define hi(x) (x & 0xFFFF0000)
424 bool wrapped = val < lo(*acc);
425 u32 newacc = hi(*acc) + val;
426
427 if (wrapped)
428 newacc += 65536;
429 ACCESS_ONCE(*acc) = newacc;
430}
431
89a88ab8
AK		 432void be_parse_stats(struct be_adapter *adapter)
433{
ac124ff9
SP		 434 struct be_erx_stats_v1 *erx = be_erx_stats_from_cmd(adapter);
435 struct be_rx_obj *rxo;
436 int i;
437
005d5696
SX		 438 if (adapter->generation == BE_GEN3) {
439 if (lancer_chip(adapter))
440 populate_lancer_stats(adapter);
441 else
442 populate_be3_stats(adapter);
443 } else {
89a88ab8 444 populate_be2_stats(adapter);
005d5696 445 }
ac124ff9 446
d51ebd33
PR		 447 if (lancer_chip(adapter))
448 goto done;
449
ac124ff9 450 /* as erx_v1 is longer than v0, ok to use v1 defn for v0 access */
09c1c68f
SP		 451 for_all_rx_queues(adapter, rxo, i) {
452 /* below erx HW counter can actually wrap around after
453 * 65535. Driver accumulates a 32-bit value
454 */
455 accumulate_16bit_val(&rx_stats(rxo)->rx_drops_no_frags,
456 (u16)erx->rx_drops_no_fragments[rxo->q.id]);
457 }
d51ebd33
PR		 458done:
459 return;
89a88ab8
AK		 460}
461
ab1594e9
SP		 462static struct rtnl_link_stats64 *be_get_stats64(struct net_device *netdev,
463 struct rtnl_link_stats64 *stats)
6b7c5b94 464{
ab1594e9 465 struct be_adapter *adapter = netdev_priv(netdev);
89a88ab8 466 struct be_drv_stats *drvs = &adapter->drv_stats;
3abcdeda 467 struct be_rx_obj *rxo;
3c8def97 468 struct be_tx_obj *txo;
ab1594e9
SP		 469 u64 pkts, bytes;
470 unsigned int start;
3abcdeda 471 int i;
6b7c5b94 472
3abcdeda 473 for_all_rx_queues(adapter, rxo, i) {
ab1594e9
SP		 474 const struct be_rx_stats *rx_stats = rx_stats(rxo);
475 do {
476 start = u64_stats_fetch_begin_bh(&rx_stats->sync);
477 pkts = rx_stats(rxo)->rx_pkts;
478 bytes = rx_stats(rxo)->rx_bytes;
479 } while (u64_stats_fetch_retry_bh(&rx_stats->sync, start));
480 stats->rx_packets += pkts;
481 stats->rx_bytes += bytes;
482 stats->multicast += rx_stats(rxo)->rx_mcast_pkts;
483 stats->rx_dropped += rx_stats(rxo)->rx_drops_no_skbs +
484 rx_stats(rxo)->rx_drops_no_frags;
3abcdeda
SP		 485 }
486
3c8def97 487 for_all_tx_queues(adapter, txo, i) {
ab1594e9
SP		 488 const struct be_tx_stats *tx_stats = tx_stats(txo);
489 do {
490 start = u64_stats_fetch_begin_bh(&tx_stats->sync);
491 pkts = tx_stats(txo)->tx_pkts;
492 bytes = tx_stats(txo)->tx_bytes;
493 } while (u64_stats_fetch_retry_bh(&tx_stats->sync, start));
494 stats->tx_packets += pkts;
495 stats->tx_bytes += bytes;
3c8def97 496 }
6b7c5b94
SP		 497
498 /* bad pkts received */
ab1594e9 499 stats->rx_errors = drvs->rx_crc_errors +
89a88ab8
AK		 500 drvs->rx_alignment_symbol_errors +
501 drvs->rx_in_range_errors +
502 drvs->rx_out_range_errors +
503 drvs->rx_frame_too_long +
504 drvs->rx_dropped_too_small +
505 drvs->rx_dropped_too_short +
506 drvs->rx_dropped_header_too_small +
507 drvs->rx_dropped_tcp_length +
ab1594e9 508 drvs->rx_dropped_runt;
68110868 509
6b7c5b94 510 /* detailed rx errors */
ab1594e9 511 stats->rx_length_errors = drvs->rx_in_range_errors +
89a88ab8
AK		 512 drvs->rx_out_range_errors +
513 drvs->rx_frame_too_long;
68110868 514
ab1594e9 515 stats->rx_crc_errors = drvs->rx_crc_errors;
6b7c5b94
SP		 516
517 /* frame alignment errors */
ab1594e9 518 stats->rx_frame_errors = drvs->rx_alignment_symbol_errors;
68110868 519
6b7c5b94
SP		 520 /* receiver fifo overrun */
521 /* drops_no_pbuf is no per i/f, it's per BE card */
ab1594e9 522 stats->rx_fifo_errors = drvs->rxpp_fifo_overflow_drop +
89a88ab8
AK		 523 drvs->rx_input_fifo_overflow_drop +
524 drvs->rx_drops_no_pbuf;
ab1594e9 525 return stats;
6b7c5b94
SP		 526}
527
b236916a 528void be_link_status_update(struct be_adapter *adapter, u8 link_status)
6b7c5b94 529{
6b7c5b94
SP		 530 struct net_device *netdev = adapter->netdev;
531
b236916a 532 if (!(adapter->flags & BE_FLAGS_LINK_STATUS_INIT)) {
ea172a01 533 netif_carrier_off(netdev);
b236916a 534 adapter->flags |= BE_FLAGS_LINK_STATUS_INIT;
6b7c5b94 535 }
b236916a
AK		 536
537 if ((link_status & LINK_STATUS_MASK) == LINK_UP)
538 netif_carrier_on(netdev);
539 else
540 netif_carrier_off(netdev);
6b7c5b94
SP		 541}
542
3c8def97 543static void be_tx_stats_update(struct be_tx_obj *txo,
91992e44 544 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 545{
3c8def97
SP		 546 struct be_tx_stats *stats = tx_stats(txo);
547
ab1594e9 548 u64_stats_update_begin(&stats->sync);
ac124ff9
SP		 549 stats->tx_reqs++;
550 stats->tx_wrbs += wrb_cnt;
551 stats->tx_bytes += copied;
552 stats->tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94 553 if (stopped)
ac124ff9 554 stats->tx_stops++;
ab1594e9 555 u64_stats_update_end(&stats->sync);
6b7c5b94
SP		 556}
557
558/* Determine number of WRB entries needed to xmit data in an skb */
fe6d2a38
SP		 559static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
560 bool *dummy)
6b7c5b94 561{
ebc8d2ab
DM		 562 int cnt = (skb->len > skb->data_len);
563
564 cnt += skb_shinfo(skb)->nr_frags;
565
6b7c5b94
SP		 566 /* to account for hdr wrb */
567 cnt++;
fe6d2a38
SP		 568 if (lancer_chip(adapter) || !(cnt & 1)) {
569 *dummy = false;
570 } else {
6b7c5b94
SP		 571 /* add a dummy to make it an even num */
572 cnt++;
573 *dummy = true;
fe6d2a38 574 }
6b7c5b94
SP		 575 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
576 return cnt;
577}
578
579static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
580{
581 wrb->frag_pa_hi = upper_32_bits(addr);
582 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
583 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
89b1f496 584 wrb->rsvd0 = 0;
6b7c5b94
SP		 585}
586
1ded132d
AK		 587static inline u16 be_get_tx_vlan_tag(struct be_adapter *adapter,
588 struct sk_buff *skb)
589{
590 u8 vlan_prio;
591 u16 vlan_tag;
592
593 vlan_tag = vlan_tx_tag_get(skb);
594 vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
595 /* If vlan priority provided by OS is NOT in available bmap */
596 if (!(adapter->vlan_prio_bmap & (1 << vlan_prio)))
597 vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) |
598 adapter->recommended_prio;
599
600 return vlan_tag;
601}
602
93040ae5
SK		 603static int be_vlan_tag_chk(struct be_adapter *adapter, struct sk_buff *skb)
604{
605 return vlan_tx_tag_present(skb) || adapter->pvid;
606}
607
cc4ce020
SK		 608static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
609 struct sk_buff *skb, u32 wrb_cnt, u32 len)
6b7c5b94 610{
1ded132d 611 u16 vlan_tag;
cc4ce020 612
6b7c5b94
SP		 613 memset(hdr, 0, sizeof(*hdr));
614
615 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
616
49e4b847 617 if (skb_is_gso(skb)) {
6b7c5b94
SP		 618 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
619 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
620 hdr, skb_shinfo(skb)->gso_size);
fe6d2a38 621 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
49e4b847 622 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
fe6d2a38
SP		 623 if (lancer_chip(adapter) && adapter->sli_family ==
624 LANCER_A0_SLI_FAMILY) {
625 AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
626 if (is_tcp_pkt(skb))
627 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
628 tcpcs, hdr, 1);
629 else if (is_udp_pkt(skb))
630 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
631 udpcs, hdr, 1);
632 }
6b7c5b94
SP		 633 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
634 if (is_tcp_pkt(skb))
635 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
636 else if (is_udp_pkt(skb))
637 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
638 }
639
4c5102f9 640 if (vlan_tx_tag_present(skb)) {
6b7c5b94 641 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
1ded132d 642 vlan_tag = be_get_tx_vlan_tag(adapter, skb);
cc4ce020 643 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
6b7c5b94
SP		 644 }
645
646 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
647 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
648 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
649 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
650}
651
2b7bcebf 652static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
7101e111
SP		 653 bool unmap_single)
654{
655 dma_addr_t dma;
656
657 be_dws_le_to_cpu(wrb, sizeof(*wrb));
658
659 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 660 if (wrb->frag_len) {
7101e111 661 if (unmap_single)
2b7bcebf
IV		 662 dma_unmap_single(dev, dma, wrb->frag_len,
663 DMA_TO_DEVICE);
7101e111 664 else
2b7bcebf 665 dma_unmap_page(dev, dma, wrb->frag_len, DMA_TO_DEVICE);
7101e111
SP		 666 }
667}
6b7c5b94 668
3c8def97 669static int make_tx_wrbs(struct be_adapter *adapter, struct be_queue_info *txq,
6b7c5b94
SP		 670 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
671{
7101e111
SP		 672 dma_addr_t busaddr;
673 int i, copied = 0;
2b7bcebf 674 struct device *dev = &adapter->pdev->dev;
6b7c5b94 675 struct sk_buff *first_skb = skb;
6b7c5b94
SP		 676 struct be_eth_wrb *wrb;
677 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 678 bool map_single = false;
679 u16 map_head;
6b7c5b94 680
6b7c5b94
SP		 681 hdr = queue_head_node(txq);
682 queue_head_inc(txq);
7101e111 683 map_head = txq->head;
6b7c5b94 684
ebc8d2ab 685 if (skb->len > skb->data_len) {
e743d313 686 int len = skb_headlen(skb);
2b7bcebf
IV		 687 busaddr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
688 if (dma_mapping_error(dev, busaddr))
7101e111
SP		 689 goto dma_err;
690 map_single = true;
ebc8d2ab
DM		 691 wrb = queue_head_node(txq);
692 wrb_fill(wrb, busaddr, len);
693 be_dws_cpu_to_le(wrb, sizeof(*wrb));
694 queue_head_inc(txq);
695 copied += len;
696 }
6b7c5b94 697
ebc8d2ab 698 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 699 const struct skb_frag_struct *frag =
ebc8d2ab 700 &skb_shinfo(skb)->frags[i];
b061b39e 701 busaddr = skb_frag_dma_map(dev, frag, 0,
9e903e08 702 skb_frag_size(frag), DMA_TO_DEVICE);
2b7bcebf 703 if (dma_mapping_error(dev, busaddr))
7101e111 704 goto dma_err;
ebc8d2ab 705 wrb = queue_head_node(txq);
9e903e08 706 wrb_fill(wrb, busaddr, skb_frag_size(frag));
ebc8d2ab
DM		 707 be_dws_cpu_to_le(wrb, sizeof(*wrb));
708 queue_head_inc(txq);
9e903e08 709 copied += skb_frag_size(frag);
6b7c5b94
SP		 710 }
711
712 if (dummy_wrb) {
713 wrb = queue_head_node(txq);
714 wrb_fill(wrb, 0, 0);
715 be_dws_cpu_to_le(wrb, sizeof(*wrb));
716 queue_head_inc(txq);
717 }
718
cc4ce020 719 wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied);
6b7c5b94
SP		 720 be_dws_cpu_to_le(hdr, sizeof(*hdr));
721
722 return copied;
7101e111
SP		 723dma_err:
724 txq->head = map_head;
725 while (copied) {
726 wrb = queue_head_node(txq);
2b7bcebf 727 unmap_tx_frag(dev, wrb, map_single);
7101e111
SP		 728 map_single = false;
729 copied -= wrb->frag_len;
730 queue_head_inc(txq);
731 }
732 return 0;
6b7c5b94
SP		 733}
734
93040ae5
SK		 735static struct sk_buff *be_insert_vlan_in_pkt(struct be_adapter *adapter,
736 struct sk_buff *skb)
737{
738 u16 vlan_tag = 0;
739
740 skb = skb_share_check(skb, GFP_ATOMIC);
741 if (unlikely(!skb))
742 return skb;
743
744 if (vlan_tx_tag_present(skb)) {
745 vlan_tag = be_get_tx_vlan_tag(adapter, skb);
746 __vlan_put_tag(skb, vlan_tag);
747 skb->vlan_tci = 0;
748 }
749
750 return skb;
751}
752
61357325 753static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 754 struct net_device *netdev)
6b7c5b94
SP		 755{
756 struct be_adapter *adapter = netdev_priv(netdev);
3c8def97
SP		 757 struct be_tx_obj *txo = &adapter->tx_obj[skb_get_queue_mapping(skb)];
758 struct be_queue_info *txq = &txo->q;
93040ae5 759 struct iphdr *ip = NULL;
6b7c5b94 760 u32 wrb_cnt = 0, copied = 0;
93040ae5 761 u32 start = txq->head, eth_hdr_len;
6b7c5b94
SP		 762 bool dummy_wrb, stopped = false;
763
93040ae5
SK		 764 eth_hdr_len = ntohs(skb->protocol) == ETH_P_8021Q ?
765 VLAN_ETH_HLEN : ETH_HLEN;
766
767 /* HW has a bug which considers padding bytes as legal
768 * and modifies the IPv4 hdr's 'tot_len' field
1ded132d 769 */
93040ae5
SK		 770 if (skb->len <= 60 && be_vlan_tag_chk(adapter, skb) &&
771 is_ipv4_pkt(skb)) {
772 ip = (struct iphdr *)ip_hdr(skb);
773 pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len));
774 }
1ded132d 775
93040ae5
SK		 776 /* HW has a bug wherein it will calculate CSUM for VLAN
777 * pkts even though it is disabled.
778 * Manually insert VLAN in pkt.
779 */
780 if (skb->ip_summed != CHECKSUM_PARTIAL &&
781 be_vlan_tag_chk(adapter, skb)) {
782 skb = be_insert_vlan_in_pkt(adapter, skb);
1ded132d
AK		 783 if (unlikely(!skb))
784 goto tx_drop;
1ded132d
AK		 785 }
786
fe6d2a38 787 wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
6b7c5b94 788
3c8def97 789 copied = make_tx_wrbs(adapter, txq, skb, wrb_cnt, dummy_wrb);
c190e3c8 790 if (copied) {
cd8f76c0
ED		 791 int gso_segs = skb_shinfo(skb)->gso_segs;
792
c190e3c8 793 /* record the sent skb in the sent_skb table */
3c8def97
SP		 794 BUG_ON(txo->sent_skb_list[start]);
795 txo->sent_skb_list[start] = skb;
c190e3c8
AK		 796
797 /* Ensure txq has space for the next skb; Else stop the queue
798 * *BEFORE* ringing the tx doorbell, so that we serialze the
799 * tx compls of the current transmit which'll wake up the queue
800 */
7101e111 801 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 802 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
803 txq->len) {
3c8def97 804 netif_stop_subqueue(netdev, skb_get_queue_mapping(skb));
c190e3c8
AK		 805 stopped = true;
806 }
6b7c5b94 807
c190e3c8 808 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 809
cd8f76c0 810 be_tx_stats_update(txo, wrb_cnt, copied, gso_segs, stopped);
c190e3c8
AK		 811 } else {
812 txq->head = start;
813 dev_kfree_skb_any(skb);
6b7c5b94 814 }
1ded132d 815tx_drop:
6b7c5b94
SP		 816 return NETDEV_TX_OK;
817}
818
819static int be_change_mtu(struct net_device *netdev, int new_mtu)
820{
821 struct be_adapter *adapter = netdev_priv(netdev);
822 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 823 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
824 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 825 dev_info(&adapter->pdev->dev,
826 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 827 BE_MIN_MTU,
828 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 829 return -EINVAL;
830 }
831 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
832 netdev->mtu, new_mtu);
833 netdev->mtu = new_mtu;
834 return 0;
835}
836
837/*
82903e4b
AK		 838 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
839 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 840 */
10329df8 841static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 842{
10329df8
SP		 843 u16 vids[BE_NUM_VLANS_SUPPORTED];
844 u16 num = 0, i;
82903e4b 845 int status = 0;
1da87b7f 846
c0e64ef4
SP		 847 /* No need to further configure vids if in promiscuous mode */
848 if (adapter->promiscuous)
849 return 0;
850
0fc16ebf
PR		 851 if (adapter->vlans_added > adapter->max_vlans)
852 goto set_vlan_promisc;
853
854 /* Construct VLAN Table to give to HW */
855 for (i = 0; i < VLAN_N_VID; i++)
856 if (adapter->vlan_tag[i])
10329df8 857 vids[num++] = cpu_to_le16(i);
0fc16ebf
PR		 858
859 status = be_cmd_vlan_config(adapter, adapter->if_handle,
10329df8 860 vids, num, 1, 0);
0fc16ebf
PR		 861
862 /* Set to VLAN promisc mode as setting VLAN filter failed */
863 if (status) {
864 dev_info(&adapter->pdev->dev, "Exhausted VLAN HW filters.\n");
865 dev_info(&adapter->pdev->dev, "Disabling HW VLAN filtering.\n");
866 goto set_vlan_promisc;
6b7c5b94 867 }
1da87b7f 868
b31c50a7 869 return status;
0fc16ebf
PR		 870
871set_vlan_promisc:
872 status = be_cmd_vlan_config(adapter, adapter->if_handle,
873 NULL, 0, 1, 1);
874 return status;
6b7c5b94
SP		 875}
876
8e586137 877static int be_vlan_add_vid(struct net_device *netdev, u16 vid)
6b7c5b94
SP		 878{
879 struct be_adapter *adapter = netdev_priv(netdev);
80817cbf 880 int status = 0;
6b7c5b94 881
a85e9986 882 if (!lancer_chip(adapter) && !be_physfn(adapter)) {
80817cbf
AK		 883 status = -EINVAL;
884 goto ret;
885 }
ba343c77 886
a85e9986
PR		 887 /* Packets with VID 0 are always received by Lancer by default */
888 if (lancer_chip(adapter) && vid == 0)
889 goto ret;
890
6b7c5b94 891 adapter->vlan_tag[vid] = 1;
82903e4b 892 if (adapter->vlans_added <= (adapter->max_vlans + 1))
10329df8 893 status = be_vid_config(adapter);
8e586137 894
80817cbf
AK		 895 if (!status)
896 adapter->vlans_added++;
897 else
898 adapter->vlan_tag[vid] = 0;
899ret:
900 return status;
6b7c5b94
SP		 901}
902
8e586137 903static int be_vlan_rem_vid(struct net_device *netdev, u16 vid)
6b7c5b94
SP		 904{
905 struct be_adapter *adapter = netdev_priv(netdev);
80817cbf 906 int status = 0;
6b7c5b94 907
a85e9986 908 if (!lancer_chip(adapter) && !be_physfn(adapter)) {
80817cbf
AK		 909 status = -EINVAL;
910 goto ret;
911 }
ba343c77 912
a85e9986
PR		 913 /* Packets with VID 0 are always received by Lancer by default */
914 if (lancer_chip(adapter) && vid == 0)
915 goto ret;
916
6b7c5b94 917 adapter->vlan_tag[vid] = 0;
82903e4b 918 if (adapter->vlans_added <= adapter->max_vlans)
10329df8 919 status = be_vid_config(adapter);
8e586137 920
80817cbf
AK		 921 if (!status)
922 adapter->vlans_added--;
923 else
924 adapter->vlan_tag[vid] = 1;
925ret:
926 return status;
6b7c5b94
SP		 927}
928
a54769f5 929static void be_set_rx_mode(struct net_device *netdev)
6b7c5b94
SP		 930{
931 struct be_adapter *adapter = netdev_priv(netdev);
0fc16ebf 932 int status;
6b7c5b94 933
24307eef 934 if (netdev->flags & IFF_PROMISC) {
5b8821b7 935 be_cmd_rx_filter(adapter, IFF_PROMISC, ON);
24307eef
SP		 936 adapter->promiscuous = true;
937 goto done;
6b7c5b94
SP		 938 }
939
25985edc 940 /* BE was previously in promiscuous mode; disable it */
24307eef
SP		 941 if (adapter->promiscuous) {
942 adapter->promiscuous = false;
5b8821b7 943 be_cmd_rx_filter(adapter, IFF_PROMISC, OFF);
c0e64ef4
SP		 944
945 if (adapter->vlans_added)
10329df8 946 be_vid_config(adapter);
6b7c5b94
SP		 947 }
948
e7b909a6 949 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf 950 if (netdev->flags & IFF_ALLMULTI ||
abb93951 951 netdev_mc_count(netdev) > adapter->max_mcast_mac) {
5b8821b7 952 be_cmd_rx_filter(adapter, IFF_ALLMULTI, ON);
24307eef 953 goto done;
6b7c5b94 954 }
6b7c5b94 955
fbc13f01
AK		 956 if (netdev_uc_count(netdev) != adapter->uc_macs) {
957 struct netdev_hw_addr *ha;
958 int i = 1; /* First slot is claimed by the Primary MAC */
959
960 for (; adapter->uc_macs > 0; adapter->uc_macs--, i++) {
961 be_cmd_pmac_del(adapter, adapter->if_handle,
962 adapter->pmac_id[i], 0);
963 }
964
965 if (netdev_uc_count(netdev) > adapter->max_pmac_cnt) {
966 be_cmd_rx_filter(adapter, IFF_PROMISC, ON);
967 adapter->promiscuous = true;
968 goto done;
969 }
970
971 netdev_for_each_uc_addr(ha, adapter->netdev) {
972 adapter->uc_macs++; /* First slot is for Primary MAC */
973 be_cmd_pmac_add(adapter, (u8 *)ha->addr,
974 adapter->if_handle,
975 &adapter->pmac_id[adapter->uc_macs], 0);
976 }
977 }
978
0fc16ebf
PR		 979 status = be_cmd_rx_filter(adapter, IFF_MULTICAST, ON);
980
981 /* Set to MCAST promisc mode if setting MULTICAST address fails */
982 if (status) {
983 dev_info(&adapter->pdev->dev, "Exhausted multicast HW filters.\n");
984 dev_info(&adapter->pdev->dev, "Disabling HW multicast filtering.\n");
985 be_cmd_rx_filter(adapter, IFF_ALLMULTI, ON);
986 }
24307eef
SP		 987done:
988 return;
6b7c5b94
SP		 989}
990
ba343c77
SB		 991static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
992{
993 struct be_adapter *adapter = netdev_priv(netdev);
11ac75ed 994 struct be_vf_cfg *vf_cfg = &adapter->vf_cfg[vf];
ba343c77 995 int status;
704e4c88
PR		 996 bool active_mac = false;
997 u32 pmac_id;
998 u8 old_mac[ETH_ALEN];
ba343c77 999
11ac75ed 1000 if (!sriov_enabled(adapter))
ba343c77
SB		 1001 return -EPERM;
1002
11ac75ed 1003 if (!is_valid_ether_addr(mac) || vf >= adapter->num_vfs)
ba343c77
SB		 1004 return -EINVAL;
1005
590c391d 1006 if (lancer_chip(adapter)) {
704e4c88
PR		 1007 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
1008 &pmac_id, vf + 1);
1009 if (!status && active_mac)
1010 be_cmd_pmac_del(adapter, vf_cfg->if_handle,
1011 pmac_id, vf + 1);
1012
590c391d
PR		 1013 status = be_cmd_set_mac_list(adapter, mac, 1, vf + 1);
1014 } else {
11ac75ed
SP		 1015 status = be_cmd_pmac_del(adapter, vf_cfg->if_handle,
1016 vf_cfg->pmac_id, vf + 1);
ba343c77 1017
11ac75ed
SP		 1018 status = be_cmd_pmac_add(adapter, mac, vf_cfg->if_handle,
1019 &vf_cfg->pmac_id, vf + 1);
590c391d
PR		 1020 }
1021
64600ea5 1022 if (status)
ba343c77
SB		 1023 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
1024 mac, vf);
64600ea5 1025 else
11ac75ed 1026 memcpy(vf_cfg->mac_addr, mac, ETH_ALEN);
64600ea5 1027
ba343c77
SB		 1028 return status;
1029}
1030
64600ea5
AK		 1031static int be_get_vf_config(struct net_device *netdev, int vf,
1032 struct ifla_vf_info *vi)
1033{
1034 struct be_adapter *adapter = netdev_priv(netdev);
11ac75ed 1035 struct be_vf_cfg *vf_cfg = &adapter->vf_cfg[vf];
64600ea5 1036
11ac75ed 1037 if (!sriov_enabled(adapter))
64600ea5
AK		 1038 return -EPERM;
1039
11ac75ed 1040 if (vf >= adapter->num_vfs)
64600ea5
AK		 1041 return -EINVAL;
1042
1043 vi->vf = vf;
11ac75ed
SP		 1044 vi->tx_rate = vf_cfg->tx_rate;
1045 vi->vlan = vf_cfg->vlan_tag;
64600ea5 1046 vi->qos = 0;
11ac75ed 1047 memcpy(&vi->mac, vf_cfg->mac_addr, ETH_ALEN);
64600ea5
AK		 1048
1049 return 0;
1050}
1051
1da87b7f
AK		 1052static int be_set_vf_vlan(struct net_device *netdev,
1053 int vf, u16 vlan, u8 qos)
1054{
1055 struct be_adapter *adapter = netdev_priv(netdev);
1056 int status = 0;
1057
11ac75ed 1058 if (!sriov_enabled(adapter))
1da87b7f
AK		 1059 return -EPERM;
1060
11ac75ed 1061 if (vf >= adapter->num_vfs || vlan > 4095)
1da87b7f
AK		 1062 return -EINVAL;
1063
1064 if (vlan) {
f1f3ee1b
AK		 1065 if (adapter->vf_cfg[vf].vlan_tag != vlan) {
1066 /* If this is new value, program it. Else skip. */
1067 adapter->vf_cfg[vf].vlan_tag = vlan;
1068
1069 status = be_cmd_set_hsw_config(adapter, vlan,
1070 vf + 1, adapter->vf_cfg[vf].if_handle);
1071 }
1da87b7f 1072 } else {
f1f3ee1b 1073 /* Reset Transparent Vlan Tagging. */
11ac75ed 1074 adapter->vf_cfg[vf].vlan_tag = 0;
f1f3ee1b
AK		 1075 vlan = adapter->vf_cfg[vf].def_vid;
1076 status = be_cmd_set_hsw_config(adapter, vlan, vf + 1,
1077 adapter->vf_cfg[vf].if_handle);
1da87b7f
AK		 1078 }
1079
1da87b7f
AK		 1080
1081 if (status)
1082 dev_info(&adapter->pdev->dev,
1083 "VLAN %d config on VF %d failed\n", vlan, vf);
1084 return status;
1085}
1086
e1d18735
AK		 1087static int be_set_vf_tx_rate(struct net_device *netdev,
1088 int vf, int rate)
1089{
1090 struct be_adapter *adapter = netdev_priv(netdev);
1091 int status = 0;
1092
11ac75ed 1093 if (!sriov_enabled(adapter))
e1d18735
AK		 1094 return -EPERM;
1095
94f434c2 1096 if (vf >= adapter->num_vfs)
e1d18735
AK		 1097 return -EINVAL;
1098
94f434c2
AK		 1099 if (rate < 100 || rate > 10000) {
1100 dev_err(&adapter->pdev->dev,
1101 "tx rate must be between 100 and 10000 Mbps\n");
1102 return -EINVAL;
1103 }
e1d18735 1104
d5c18473
PR		 1105 if (lancer_chip(adapter))
1106 status = be_cmd_set_profile_config(adapter, rate / 10, vf + 1);
1107 else
1108 status = be_cmd_set_qos(adapter, rate / 10, vf + 1);
e1d18735
AK		 1109
1110 if (status)
94f434c2 1111 dev_err(&adapter->pdev->dev,
e1d18735 1112 "tx rate %d on VF %d failed\n", rate, vf);
94f434c2
AK		 1113 else
1114 adapter->vf_cfg[vf].tx_rate = rate;
e1d18735
AK		 1115 return status;
1116}
1117
39f1d94d
SP		 1118static int be_find_vfs(struct be_adapter *adapter, int vf_state)
1119{
1120 struct pci_dev *dev, *pdev = adapter->pdev;
2f6a0260 1121 int vfs = 0, assigned_vfs = 0, pos;
39f1d94d
SP		 1122 u16 offset, stride;
1123
1124 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
d79c0a20
SP		 1125 if (!pos)
1126 return 0;
39f1d94d
SP		 1127 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_OFFSET, &offset);
1128 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_STRIDE, &stride);
1129
1130 dev = pci_get_device(pdev->vendor, PCI_ANY_ID, NULL);
1131 while (dev) {
2f6a0260 1132 if (dev->is_virtfn && pci_physfn(dev) == pdev) {
39f1d94d
SP		 1133 vfs++;
1134 if (dev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
1135 assigned_vfs++;
1136 }
1137 dev = pci_get_device(pdev->vendor, PCI_ANY_ID, dev);
1138 }
1139 return (vf_state == ASSIGNED) ? assigned_vfs : vfs;
1140}
1141
10ef9ab4 1142static void be_eqd_update(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 1143{
10ef9ab4 1144 struct be_rx_stats *stats = rx_stats(&adapter->rx_obj[eqo->idx]);
4097f663 1145 ulong now = jiffies;
ac124ff9 1146 ulong delta = now - stats->rx_jiffies;
ab1594e9
SP		 1147 u64 pkts;
1148 unsigned int start, eqd;
ac124ff9 1149
10ef9ab4
SP		 1150 if (!eqo->enable_aic) {
1151 eqd = eqo->eqd;
1152 goto modify_eqd;
1153 }
1154
1155 if (eqo->idx >= adapter->num_rx_qs)
ac124ff9 1156 return;
6b7c5b94 1157
10ef9ab4
SP		 1158 stats = rx_stats(&adapter->rx_obj[eqo->idx]);
1159
4097f663 1160 /* Wrapped around */
3abcdeda
SP		 1161 if (time_before(now, stats->rx_jiffies)) {
1162 stats->rx_jiffies = now;
4097f663
SP		 1163 return;
1164 }
6b7c5b94 1165
ac124ff9
SP		 1166 /* Update once a second */
1167 if (delta < HZ)
6b7c5b94
SP		 1168 return;
1169
ab1594e9
SP		 1170 do {
1171 start = u64_stats_fetch_begin_bh(&stats->sync);
1172 pkts = stats->rx_pkts;
1173 } while (u64_stats_fetch_retry_bh(&stats->sync, start));
1174
68c3e5a7 1175 stats->rx_pps = (unsigned long)(pkts - stats->rx_pkts_prev) / (delta / HZ);
ab1594e9 1176 stats->rx_pkts_prev = pkts;
3abcdeda 1177 stats->rx_jiffies = now;
10ef9ab4
SP		 1178 eqd = (stats->rx_pps / 110000) << 3;
1179 eqd = min(eqd, eqo->max_eqd);
1180 eqd = max(eqd, eqo->min_eqd);
ac124ff9
SP		 1181 if (eqd < 10)
1182 eqd = 0;
10ef9ab4
SP		 1183
1184modify_eqd:
1185 if (eqd != eqo->cur_eqd) {
1186 be_cmd_modify_eqd(adapter, eqo->q.id, eqd);
1187 eqo->cur_eqd = eqd;
ac124ff9 1188 }
6b7c5b94
SP		 1189}
1190
3abcdeda 1191static void be_rx_stats_update(struct be_rx_obj *rxo,
2e588f84 1192 struct be_rx_compl_info *rxcp)
4097f663 1193{
ac124ff9 1194 struct be_rx_stats *stats = rx_stats(rxo);
1ef78abe 1195
ab1594e9 1196 u64_stats_update_begin(&stats->sync);
3abcdeda 1197 stats->rx_compl++;
2e588f84 1198 stats->rx_bytes += rxcp->pkt_size;
3abcdeda 1199 stats->rx_pkts++;
2e588f84 1200 if (rxcp->pkt_type == BE_MULTICAST_PACKET)
3abcdeda 1201 stats->rx_mcast_pkts++;
2e588f84 1202 if (rxcp->err)
ac124ff9 1203 stats->rx_compl_err++;
ab1594e9 1204 u64_stats_update_end(&stats->sync);
4097f663
SP		 1205}
1206
2e588f84 1207static inline bool csum_passed(struct be_rx_compl_info *rxcp)
728a9972 1208{
19fad86f
PR		 1209 /* L4 checksum is not reliable for non TCP/UDP packets.
1210 * Also ignore ipcksm for ipv6 pkts */
2e588f84
SP		 1211 return (rxcp->tcpf || rxcp->udpf) && rxcp->l4_csum &&
1212 (rxcp->ip_csum || rxcp->ipv6);
728a9972
AK		 1213}
1214
10ef9ab4
SP		 1215static struct be_rx_page_info *get_rx_page_info(struct be_rx_obj *rxo,
1216 u16 frag_idx)
6b7c5b94 1217{
10ef9ab4 1218 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1219 struct be_rx_page_info *rx_page_info;
3abcdeda 1220 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 1221
3abcdeda 1222 rx_page_info = &rxo->page_info_tbl[frag_idx];
6b7c5b94
SP		 1223 BUG_ON(!rx_page_info->page);
1224
205859a2 1225 if (rx_page_info->last_page_user) {
2b7bcebf
IV		 1226 dma_unmap_page(&adapter->pdev->dev,
1227 dma_unmap_addr(rx_page_info, bus),
1228 adapter->big_page_size, DMA_FROM_DEVICE);
205859a2
AK		 1229 rx_page_info->last_page_user = false;
1230 }
6b7c5b94
SP		 1231
1232 atomic_dec(&rxq->used);
1233 return rx_page_info;
1234}
1235
1236/* Throwaway the data in the Rx completion */
10ef9ab4
SP		 1237static void be_rx_compl_discard(struct be_rx_obj *rxo,
1238 struct be_rx_compl_info *rxcp)
6b7c5b94 1239{
3abcdeda 1240 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 1241 struct be_rx_page_info *page_info;
2e588f84 1242 u16 i, num_rcvd = rxcp->num_rcvd;
6b7c5b94 1243
e80d9da6 1244 for (i = 0; i < num_rcvd; i++) {
10ef9ab4 1245 page_info = get_rx_page_info(rxo, rxcp->rxq_idx);
e80d9da6
PR		 1246 put_page(page_info->page);
1247 memset(page_info, 0, sizeof(*page_info));
2e588f84 1248 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 1249 }
1250}
1251
1252/*
1253 * skb_fill_rx_data forms a complete skb for an ether frame
1254 * indicated by rxcp.
1255 */
10ef9ab4
SP		 1256static void skb_fill_rx_data(struct be_rx_obj *rxo, struct sk_buff *skb,
1257 struct be_rx_compl_info *rxcp)
6b7c5b94 1258{
3abcdeda 1259 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 1260 struct be_rx_page_info *page_info;
2e588f84
SP		 1261 u16 i, j;
1262 u16 hdr_len, curr_frag_len, remaining;
6b7c5b94 1263 u8 *start;
6b7c5b94 1264
10ef9ab4 1265 page_info = get_rx_page_info(rxo, rxcp->rxq_idx);
6b7c5b94
SP		 1266 start = page_address(page_info->page) + page_info->page_offset;
1267 prefetch(start);
1268
1269 /* Copy data in the first descriptor of this completion */
2e588f84 1270 curr_frag_len = min(rxcp->pkt_size, rx_frag_size);
6b7c5b94 1271
6b7c5b94
SP		 1272 skb->len = curr_frag_len;
1273 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
ac1ae5f3 1274 memcpy(skb->data, start, curr_frag_len);
6b7c5b94
SP		 1275 /* Complete packet has now been moved to data */
1276 put_page(page_info->page);
1277 skb->data_len = 0;
1278 skb->tail += curr_frag_len;
1279 } else {
ac1ae5f3
ED		 1280 hdr_len = ETH_HLEN;
1281 memcpy(skb->data, start, hdr_len);
6b7c5b94 1282 skb_shinfo(skb)->nr_frags = 1;
b061b39e 1283 skb_frag_set_page(skb, 0, page_info->page);
6b7c5b94
SP		 1284 skb_shinfo(skb)->frags[0].page_offset =
1285 page_info->page_offset + hdr_len;
9e903e08 1286 skb_frag_size_set(&skb_shinfo(skb)->frags[0], curr_frag_len - hdr_len);
6b7c5b94 1287 skb->data_len = curr_frag_len - hdr_len;
bdb28a97 1288 skb->truesize += rx_frag_size;
6b7c5b94
SP		 1289 skb->tail += hdr_len;
1290 }
205859a2 1291 page_info->page = NULL;
6b7c5b94 1292
2e588f84
SP		 1293 if (rxcp->pkt_size <= rx_frag_size) {
1294 BUG_ON(rxcp->num_rcvd != 1);
1295 return;
6b7c5b94
SP		 1296 }
1297
1298 /* More frags present for this completion */
2e588f84
SP		 1299 index_inc(&rxcp->rxq_idx, rxq->len);
1300 remaining = rxcp->pkt_size - curr_frag_len;
1301 for (i = 1, j = 0; i < rxcp->num_rcvd; i++) {
10ef9ab4 1302 page_info = get_rx_page_info(rxo, rxcp->rxq_idx);
2e588f84 1303 curr_frag_len = min(remaining, rx_frag_size);
6b7c5b94 1304
bd46cb6c
AK		 1305 /* Coalesce all frags from the same physical page in one slot */
1306 if (page_info->page_offset == 0) {
1307 /* Fresh page */
1308 j++;
b061b39e 1309 skb_frag_set_page(skb, j, page_info->page);
bd46cb6c
AK		 1310 skb_shinfo(skb)->frags[j].page_offset =
1311 page_info->page_offset;
9e903e08 1312 skb_frag_size_set(&skb_shinfo(skb)->frags[j], 0);
bd46cb6c
AK		 1313 skb_shinfo(skb)->nr_frags++;
1314 } else {
1315 put_page(page_info->page);
1316 }
1317
9e903e08 1318 skb_frag_size_add(&skb_shinfo(skb)->frags[j], curr_frag_len);
6b7c5b94
SP		 1319 skb->len += curr_frag_len;
1320 skb->data_len += curr_frag_len;
bdb28a97 1321 skb->truesize += rx_frag_size;
2e588f84
SP		 1322 remaining -= curr_frag_len;
1323 index_inc(&rxcp->rxq_idx, rxq->len);
205859a2 1324 page_info->page = NULL;
6b7c5b94 1325 }
bd46cb6c 1326 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94
SP		 1327}
1328
5be93b9a 1329/* Process the RX completion indicated by rxcp when GRO is disabled */
10ef9ab4
SP		 1330static void be_rx_compl_process(struct be_rx_obj *rxo,
1331 struct be_rx_compl_info *rxcp)
6b7c5b94 1332{
10ef9ab4 1333 struct be_adapter *adapter = rxo->adapter;
6332c8d3 1334 struct net_device *netdev = adapter->netdev;
6b7c5b94 1335 struct sk_buff *skb;
89420424 1336
bb349bb4 1337 skb = netdev_alloc_skb_ip_align(netdev, BE_RX_SKB_ALLOC_SIZE);
a058a632 1338 if (unlikely(!skb)) {
ac124ff9 1339 rx_stats(rxo)->rx_drops_no_skbs++;
10ef9ab4 1340 be_rx_compl_discard(rxo, rxcp);
6b7c5b94
SP		 1341 return;
1342 }
1343
10ef9ab4 1344 skb_fill_rx_data(rxo, skb, rxcp);
6b7c5b94 1345
6332c8d3 1346 if (likely((netdev->features & NETIF_F_RXCSUM) && csum_passed(rxcp)))
728a9972 1347 skb->ip_summed = CHECKSUM_UNNECESSARY;
c6ce2f4b
SK		 1348 else
1349 skb_checksum_none_assert(skb);
6b7c5b94 1350
6332c8d3 1351 skb->protocol = eth_type_trans(skb, netdev);
aaa6daec 1352 skb_record_rx_queue(skb, rxo - &adapter->rx_obj[0]);
10ef9ab4 1353 if (netdev->features & NETIF_F_RXHASH)
4b972914
AK		 1354 skb->rxhash = rxcp->rss_hash;
1355
6b7c5b94 1356
343e43c0 1357 if (rxcp->vlanf)
4c5102f9
AK		 1358 __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag);
1359
1360 netif_receive_skb(skb);
6b7c5b94
SP		 1361}
1362
5be93b9a 1363/* Process the RX completion indicated by rxcp when GRO is enabled */
10ef9ab4
SP		 1364void be_rx_compl_process_gro(struct be_rx_obj *rxo, struct napi_struct *napi,
1365 struct be_rx_compl_info *rxcp)
6b7c5b94 1366{
10ef9ab4 1367 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1368 struct be_rx_page_info *page_info;
5be93b9a 1369 struct sk_buff *skb = NULL;
3abcdeda 1370 struct be_queue_info *rxq = &rxo->q;
2e588f84
SP		 1371 u16 remaining, curr_frag_len;
1372 u16 i, j;
3968fa1e 1373
10ef9ab4 1374 skb = napi_get_frags(napi);
5be93b9a 1375 if (!skb) {
10ef9ab4 1376 be_rx_compl_discard(rxo, rxcp);
5be93b9a
AK		 1377 return;
1378 }
1379
2e588f84
SP		 1380 remaining = rxcp->pkt_size;
1381 for (i = 0, j = -1; i < rxcp->num_rcvd; i++) {
10ef9ab4 1382 page_info = get_rx_page_info(rxo, rxcp->rxq_idx);
6b7c5b94
SP		 1383
1384 curr_frag_len = min(remaining, rx_frag_size);
1385
bd46cb6c
AK		 1386 /* Coalesce all frags from the same physical page in one slot */
1387 if (i == 0 || page_info->page_offset == 0) {
1388 /* First frag or Fresh page */
1389 j++;
b061b39e 1390 skb_frag_set_page(skb, j, page_info->page);
5be93b9a
AK		 1391 skb_shinfo(skb)->frags[j].page_offset =
1392 page_info->page_offset;
9e903e08 1393 skb_frag_size_set(&skb_shinfo(skb)->frags[j], 0);
bd46cb6c
AK		 1394 } else {
1395 put_page(page_info->page);
1396 }
9e903e08 1397 skb_frag_size_add(&skb_shinfo(skb)->frags[j], curr_frag_len);
bdb28a97 1398 skb->truesize += rx_frag_size;
bd46cb6c 1399 remaining -= curr_frag_len;
2e588f84 1400 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 1401 memset(page_info, 0, sizeof(*page_info));
1402 }
bd46cb6c 1403 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1404
5be93b9a 1405 skb_shinfo(skb)->nr_frags = j + 1;
2e588f84
SP		 1406 skb->len = rxcp->pkt_size;
1407 skb->data_len = rxcp->pkt_size;
5be93b9a 1408 skb->ip_summed = CHECKSUM_UNNECESSARY;
aaa6daec 1409 skb_record_rx_queue(skb, rxo - &adapter->rx_obj[0]);
4b972914
AK		 1410 if (adapter->netdev->features & NETIF_F_RXHASH)
1411 skb->rxhash = rxcp->rss_hash;
5be93b9a 1412
343e43c0 1413 if (rxcp->vlanf)
4c5102f9
AK		 1414 __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag);
1415
10ef9ab4 1416 napi_gro_frags(napi);
2e588f84
SP		 1417}
1418
10ef9ab4
SP		 1419static void be_parse_rx_compl_v1(struct be_eth_rx_compl *compl,
1420 struct be_rx_compl_info *rxcp)
2e588f84
SP		 1421{
1422 rxcp->pkt_size =
1423 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, pktsize, compl);
1424 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtp, compl);
1425 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, err, compl);
1426 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, tcpf, compl);
9ecb42fd 1427 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, udpf, compl);
2e588f84
SP		 1428 rxcp->ip_csum =
1429 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ipcksm, compl);
1430 rxcp->l4_csum =
1431 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, l4_cksm, compl);
1432 rxcp->ipv6 =
1433 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ip_version, compl);
1434 rxcp->rxq_idx =
1435 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, fragndx, compl);
1436 rxcp->num_rcvd =
1437 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, numfrags, compl);
1438 rxcp->pkt_type =
1439 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, cast_enc, compl);
4b972914 1440 rxcp->rss_hash =
c297977e 1441 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, rsshash, compl);
15d72184
SP		 1442 if (rxcp->vlanf) {
1443 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtm,
3c709f8f
DM		 1444 compl);
1445 rxcp->vlan_tag = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vlan_tag,
1446 compl);
15d72184 1447 }
12004ae9 1448 rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, port, compl);
2e588f84
SP		 1449}
1450
10ef9ab4
SP		 1451static void be_parse_rx_compl_v0(struct be_eth_rx_compl *compl,
1452 struct be_rx_compl_info *rxcp)
2e588f84
SP		 1453{
1454 rxcp->pkt_size =
1455 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, pktsize, compl);
1456 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtp, compl);
1457 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, err, compl);
1458 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, tcpf, compl);
9ecb42fd 1459 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, udpf, compl);
2e588f84
SP		 1460 rxcp->ip_csum =
1461 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ipcksm, compl);
1462 rxcp->l4_csum =
1463 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, l4_cksm, compl);
1464 rxcp->ipv6 =
1465 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ip_version, compl);
1466 rxcp->rxq_idx =
1467 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, fragndx, compl);
1468 rxcp->num_rcvd =
1469 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, numfrags, compl);
1470 rxcp->pkt_type =
1471 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, cast_enc, compl);
4b972914 1472 rxcp->rss_hash =
c297977e 1473 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, rsshash, compl);
15d72184
SP		 1474 if (rxcp->vlanf) {
1475 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtm,
3c709f8f
DM		 1476 compl);
1477 rxcp->vlan_tag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vlan_tag,
1478 compl);
15d72184 1479 }
12004ae9 1480 rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, port, compl);
2e588f84
SP		 1481}
1482
1483static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
1484{
1485 struct be_eth_rx_compl *compl = queue_tail_node(&rxo->cq);
1486 struct be_rx_compl_info *rxcp = &rxo->rxcp;
1487 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1488
2e588f84
SP		 1489 /* For checking the valid bit it is Ok to use either definition as the
1490 * valid bit is at the same position in both v0 and v1 Rx compl */
1491 if (compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] == 0)
1492 return NULL;
6b7c5b94 1493
2e588f84
SP		 1494 rmb();
1495 be_dws_le_to_cpu(compl, sizeof(*compl));
6b7c5b94 1496
2e588f84 1497 if (adapter->be3_native)
10ef9ab4 1498 be_parse_rx_compl_v1(compl, rxcp);
2e588f84 1499 else
10ef9ab4 1500 be_parse_rx_compl_v0(compl, rxcp);
6b7c5b94 1501
15d72184
SP		 1502 if (rxcp->vlanf) {
1503 /* vlanf could be wrongly set in some cards.
1504 * ignore if vtm is not set */
752961a1 1505 if ((adapter->function_mode & FLEX10_MODE) && !rxcp->vtm)
15d72184 1506 rxcp->vlanf = 0;
6b7c5b94 1507
15d72184 1508 if (!lancer_chip(adapter))
3c709f8f 1509 rxcp->vlan_tag = swab16(rxcp->vlan_tag);
6b7c5b94 1510
939cf306 1511 if (adapter->pvid == (rxcp->vlan_tag & VLAN_VID_MASK) &&
3c709f8f 1512 !adapter->vlan_tag[rxcp->vlan_tag])
15d72184
SP		 1513 rxcp->vlanf = 0;
1514 }
2e588f84
SP		 1515
1516 /* As the compl has been parsed, reset it; we wont touch it again */
1517 compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] = 0;
6b7c5b94 1518
3abcdeda 1519 queue_tail_inc(&rxo->cq);
6b7c5b94
SP		 1520 return rxcp;
1521}
1522
1829b086 1523static inline struct page *be_alloc_pages(u32 size, gfp_t gfp)
6b7c5b94 1524{
6b7c5b94 1525 u32 order = get_order(size);
1829b086 1526
6b7c5b94 1527 if (order > 0)
1829b086
ED		 1528 gfp |= __GFP_COMP;
1529 return alloc_pages(gfp, order);
6b7c5b94
SP		 1530}
1531
1532/*
1533 * Allocate a page, split it to fragments of size rx_frag_size and post as
1534 * receive buffers to BE
1535 */
1829b086 1536static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp)
6b7c5b94 1537{
3abcdeda 1538 struct be_adapter *adapter = rxo->adapter;
26d92f92 1539 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
3abcdeda 1540 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 1541 struct page *pagep = NULL;
1542 struct be_eth_rx_d *rxd;
1543 u64 page_dmaaddr = 0, frag_dmaaddr;
1544 u32 posted, page_offset = 0;
1545
3abcdeda 1546 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1547 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1548 if (!pagep) {
1829b086 1549 pagep = be_alloc_pages(adapter->big_page_size, gfp);
6b7c5b94 1550 if (unlikely(!pagep)) {
ac124ff9 1551 rx_stats(rxo)->rx_post_fail++;
6b7c5b94
SP		 1552 break;
1553 }
2b7bcebf
IV		 1554 page_dmaaddr = dma_map_page(&adapter->pdev->dev, pagep,
1555 0, adapter->big_page_size,
1556 DMA_FROM_DEVICE);
6b7c5b94
SP		 1557 page_info->page_offset = 0;
1558 } else {
1559 get_page(pagep);
1560 page_info->page_offset = page_offset + rx_frag_size;
1561 }
1562 page_offset = page_info->page_offset;
1563 page_info->page = pagep;
fac6da5b 1564 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1565 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1566
1567 rxd = queue_head_node(rxq);
1568 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1569 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1570
1571 /* Any space left in the current big page for another frag? */
1572 if ((page_offset + rx_frag_size + rx_frag_size) >
1573 adapter->big_page_size) {
1574 pagep = NULL;
1575 page_info->last_page_user = true;
1576 }
26d92f92
SP		 1577
1578 prev_page_info = page_info;
1579 queue_head_inc(rxq);
10ef9ab4 1580 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1581 }
1582 if (pagep)
26d92f92 1583 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1584
1585 if (posted) {
6b7c5b94 1586 atomic_add(posted, &rxq->used);
8788fdc2 1587 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1588 } else if (atomic_read(&rxq->used) == 0) {
1589 /* Let be_worker replenish when memory is available */
3abcdeda 1590 rxo->rx_post_starved = true;
6b7c5b94 1591 }
6b7c5b94
SP		 1592}
1593
5fb379ee 1594static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1595{
6b7c5b94
SP		 1596 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1597
1598 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1599 return NULL;
1600
f3eb62d2 1601 rmb();
6b7c5b94
SP		 1602 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1603
1604 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1605
1606 queue_tail_inc(tx_cq);
1607 return txcp;
1608}
1609
3c8def97
SP		 1610static u16 be_tx_compl_process(struct be_adapter *adapter,
1611 struct be_tx_obj *txo, u16 last_index)
6b7c5b94 1612{
3c8def97 1613 struct be_queue_info *txq = &txo->q;
a73b796e 1614 struct be_eth_wrb *wrb;
3c8def97 1615 struct sk_buff **sent_skbs = txo->sent_skb_list;
6b7c5b94 1616 struct sk_buff *sent_skb;
ec43b1a6
SP		 1617 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1618 bool unmap_skb_hdr = true;
6b7c5b94 1619
ec43b1a6 1620 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1621 BUG_ON(!sent_skb);
ec43b1a6
SP		 1622 sent_skbs[txq->tail] = NULL;
1623
1624 /* skip header wrb */
a73b796e 1625 queue_tail_inc(txq);
6b7c5b94 1626
ec43b1a6 1627 do {
6b7c5b94 1628 cur_index = txq->tail;
a73b796e 1629 wrb = queue_tail_node(txq);
2b7bcebf
IV		 1630 unmap_tx_frag(&adapter->pdev->dev, wrb,
1631 (unmap_skb_hdr && skb_headlen(sent_skb)));
ec43b1a6
SP		 1632 unmap_skb_hdr = false;
1633
6b7c5b94
SP		 1634 num_wrbs++;
1635 queue_tail_inc(txq);
ec43b1a6 1636 } while (cur_index != last_index);
6b7c5b94 1637
6b7c5b94 1638 kfree_skb(sent_skb);
4d586b82 1639 return num_wrbs;
6b7c5b94
SP		 1640}
1641
10ef9ab4
SP		 1642/* Return the number of events in the event queue */
1643static inline int events_get(struct be_eq_obj *eqo)
859b1e4e 1644{
10ef9ab4
SP		 1645 struct be_eq_entry *eqe;
1646 int num = 0;
859b1e4e 1647
10ef9ab4
SP		 1648 do {
1649 eqe = queue_tail_node(&eqo->q);
1650 if (eqe->evt == 0)
1651 break;
859b1e4e 1652
10ef9ab4
SP		 1653 rmb();
1654 eqe->evt = 0;
1655 num++;
1656 queue_tail_inc(&eqo->q);
1657 } while (true);
1658
1659 return num;
859b1e4e
SP		 1660}
1661
10ef9ab4 1662static int event_handle(struct be_eq_obj *eqo)
859b1e4e 1663{
10ef9ab4
SP		 1664 bool rearm = false;
1665 int num = events_get(eqo);
859b1e4e 1666
10ef9ab4 1667 /* Deal with any spurious interrupts that come without events */
3c8def97
SP		 1668 if (!num)
1669 rearm = true;
1670
af311fe3
PR		 1671 if (num || msix_enabled(eqo->adapter))
1672 be_eq_notify(eqo->adapter, eqo->q.id, rearm, true, num);
1673
859b1e4e 1674 if (num)
10ef9ab4 1675 napi_schedule(&eqo->napi);
859b1e4e
SP		 1676
1677 return num;
1678}
1679
10ef9ab4
SP		 1680/* Leaves the EQ is disarmed state */
1681static void be_eq_clean(struct be_eq_obj *eqo)
859b1e4e 1682{
10ef9ab4 1683 int num = events_get(eqo);
859b1e4e 1684
10ef9ab4 1685 be_eq_notify(eqo->adapter, eqo->q.id, false, true, num);
859b1e4e
SP		 1686}
1687
10ef9ab4 1688static void be_rx_cq_clean(struct be_rx_obj *rxo)
6b7c5b94
SP		 1689{
1690 struct be_rx_page_info *page_info;
3abcdeda
SP		 1691 struct be_queue_info *rxq = &rxo->q;
1692 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1693 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1694 u16 tail;
1695
1696 /* First cleanup pending rx completions */
3abcdeda 1697 while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
10ef9ab4
SP		 1698 be_rx_compl_discard(rxo, rxcp);
1699 be_cq_notify(rxo->adapter, rx_cq->id, false, 1);
6b7c5b94
SP		 1700 }
1701
1702 /* Then free posted rx buffer that were not used */
1703 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1704 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
10ef9ab4 1705 page_info = get_rx_page_info(rxo, tail);
6b7c5b94
SP		 1706 put_page(page_info->page);
1707 memset(page_info, 0, sizeof(*page_info));
1708 }
1709 BUG_ON(atomic_read(&rxq->used));
482c9e79 1710 rxq->tail = rxq->head = 0;
6b7c5b94
SP		 1711}
1712
0ae57bb3 1713static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1714{
0ae57bb3
SP		 1715 struct be_tx_obj *txo;
1716 struct be_queue_info *txq;
a8e9179a 1717 struct be_eth_tx_compl *txcp;
4d586b82 1718 u16 end_idx, cmpl = 0, timeo = 0, num_wrbs = 0;
b03388d6
SP		 1719 struct sk_buff *sent_skb;
1720 bool dummy_wrb;
0ae57bb3 1721 int i, pending_txqs;
a8e9179a
SP		 1722
1723 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1724 do {
0ae57bb3
SP		 1725 pending_txqs = adapter->num_tx_qs;
1726
1727 for_all_tx_queues(adapter, txo, i) {
1728 txq = &txo->q;
1729 while ((txcp = be_tx_compl_get(&txo->cq))) {
1730 end_idx =
1731 AMAP_GET_BITS(struct amap_eth_tx_compl,
1732 wrb_index, txcp);
1733 num_wrbs += be_tx_compl_process(adapter, txo,
1734 end_idx);
1735 cmpl++;
1736 }
1737 if (cmpl) {
1738 be_cq_notify(adapter, txo->cq.id, false, cmpl);
1739 atomic_sub(num_wrbs, &txq->used);
1740 cmpl = 0;
1741 num_wrbs = 0;
1742 }
1743 if (atomic_read(&txq->used) == 0)
1744 pending_txqs--;
a8e9179a
SP		 1745 }
1746
0ae57bb3 1747 if (pending_txqs == 0 || ++timeo > 200)
a8e9179a
SP		 1748 break;
1749
1750 mdelay(1);
1751 } while (true);
1752
0ae57bb3
SP		 1753 for_all_tx_queues(adapter, txo, i) {
1754 txq = &txo->q;
1755 if (atomic_read(&txq->used))
1756 dev_err(&adapter->pdev->dev, "%d pending tx-compls\n",
1757 atomic_read(&txq->used));
1758
1759 /* free posted tx for which compls will never arrive */
1760 while (atomic_read(&txq->used)) {
1761 sent_skb = txo->sent_skb_list[txq->tail];
1762 end_idx = txq->tail;
1763 num_wrbs = wrb_cnt_for_skb(adapter, sent_skb,
1764 &dummy_wrb);
1765 index_adv(&end_idx, num_wrbs - 1, txq->len);
1766 num_wrbs = be_tx_compl_process(adapter, txo, end_idx);
1767 atomic_sub(num_wrbs, &txq->used);
1768 }
b03388d6 1769 }
6b7c5b94
SP		 1770}
1771
10ef9ab4
SP		 1772static void be_evt_queues_destroy(struct be_adapter *adapter)
1773{
1774 struct be_eq_obj *eqo;
1775 int i;
1776
1777 for_all_evt_queues(adapter, eqo, i) {
19d59aa7
PR		 1778 if (eqo->q.created) {
1779 be_eq_clean(eqo);
10ef9ab4 1780 be_cmd_q_destroy(adapter, &eqo->q, QTYPE_EQ);
19d59aa7 1781 }
10ef9ab4
SP		 1782 be_queue_free(adapter, &eqo->q);
1783 }
1784}
1785
1786static int be_evt_queues_create(struct be_adapter *adapter)
1787{
1788 struct be_queue_info *eq;
1789 struct be_eq_obj *eqo;
1790 int i, rc;
1791
1792 adapter->num_evt_qs = num_irqs(adapter);
1793
1794 for_all_evt_queues(adapter, eqo, i) {
1795 eqo->adapter = adapter;
1796 eqo->tx_budget = BE_TX_BUDGET;
1797 eqo->idx = i;
1798 eqo->max_eqd = BE_MAX_EQD;
1799 eqo->enable_aic = true;
1800
1801 eq = &eqo->q;
1802 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1803 sizeof(struct be_eq_entry));
1804 if (rc)
1805 return rc;
1806
1807 rc = be_cmd_eq_create(adapter, eq, eqo->cur_eqd);
1808 if (rc)
1809 return rc;
1810 }
1cfafab9 1811 return 0;
10ef9ab4
SP		 1812}
1813
5fb379ee
SP		 1814static void be_mcc_queues_destroy(struct be_adapter *adapter)
1815{
1816 struct be_queue_info *q;
5fb379ee 1817
8788fdc2 1818 q = &adapter->mcc_obj.q;
5fb379ee 1819 if (q->created)
8788fdc2 1820 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1821 be_queue_free(adapter, q);
1822
8788fdc2 1823 q = &adapter->mcc_obj.cq;
5fb379ee 1824 if (q->created)
8788fdc2 1825 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1826 be_queue_free(adapter, q);
1827}
1828
1829/* Must be called only after TX qs are created as MCC shares TX EQ */
1830static int be_mcc_queues_create(struct be_adapter *adapter)
1831{
1832 struct be_queue_info *q, *cq;
5fb379ee 1833
8788fdc2 1834 cq = &adapter->mcc_obj.cq;
5fb379ee 1835 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1836 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1837 goto err;
1838
10ef9ab4
SP		 1839 /* Use the default EQ for MCC completions */
1840 if (be_cmd_cq_create(adapter, cq, &mcc_eqo(adapter)->q, true, 0))
5fb379ee
SP		 1841 goto mcc_cq_free;
1842
8788fdc2 1843 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1844 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1845 goto mcc_cq_destroy;
1846
8788fdc2 1847 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1848 goto mcc_q_free;
1849
1850 return 0;
1851
1852mcc_q_free:
1853 be_queue_free(adapter, q);
1854mcc_cq_destroy:
8788fdc2 1855 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1856mcc_cq_free:
1857 be_queue_free(adapter, cq);
1858err:
1859 return -1;
1860}
1861
6b7c5b94
SP		 1862static void be_tx_queues_destroy(struct be_adapter *adapter)
1863{
1864 struct be_queue_info *q;
3c8def97
SP		 1865 struct be_tx_obj *txo;
1866 u8 i;
6b7c5b94 1867
3c8def97
SP		 1868 for_all_tx_queues(adapter, txo, i) {
1869 q = &txo->q;
1870 if (q->created)
1871 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
1872 be_queue_free(adapter, q);
6b7c5b94 1873
3c8def97
SP		 1874 q = &txo->cq;
1875 if (q->created)
1876 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1877 be_queue_free(adapter, q);
1878 }
6b7c5b94
SP		 1879}
1880
dafc0fe3
SP		 1881static int be_num_txqs_want(struct be_adapter *adapter)
1882{
abb93951
PR		 1883 if ((!lancer_chip(adapter) && sriov_want(adapter)) ||
1884 be_is_mc(adapter) ||
1885 (!lancer_chip(adapter) && !be_physfn(adapter)) ||
39f1d94d 1886 adapter->generation == BE_GEN2)
dafc0fe3
SP		 1887 return 1;
1888 else
abb93951 1889 return adapter->max_tx_queues;
dafc0fe3
SP		 1890}
1891
10ef9ab4 1892static int be_tx_cqs_create(struct be_adapter *adapter)
6b7c5b94 1893{
10ef9ab4
SP		 1894 struct be_queue_info *cq, *eq;
1895 int status;
3c8def97
SP		 1896 struct be_tx_obj *txo;
1897 u8 i;
6b7c5b94 1898
dafc0fe3 1899 adapter->num_tx_qs = be_num_txqs_want(adapter);
3bb62f4f
PR		 1900 if (adapter->num_tx_qs != MAX_TX_QS) {
1901 rtnl_lock();
dafc0fe3
SP		 1902 netif_set_real_num_tx_queues(adapter->netdev,
1903 adapter->num_tx_qs);
3bb62f4f
PR		 1904 rtnl_unlock();
1905 }
dafc0fe3 1906
10ef9ab4
SP		 1907 for_all_tx_queues(adapter, txo, i) {
1908 cq = &txo->cq;
1909 status = be_queue_alloc(adapter, cq, TX_CQ_LEN,
1910 sizeof(struct be_eth_tx_compl));
1911 if (status)
1912 return status;
3c8def97 1913
10ef9ab4
SP		 1914 /* If num_evt_qs is less than num_tx_qs, then more than
1915 * one txq share an eq
1916 */
1917 eq = &adapter->eq_obj[i % adapter->num_evt_qs].q;
1918 status = be_cmd_cq_create(adapter, cq, eq, false, 3);
1919 if (status)
1920 return status;
1921 }
1922 return 0;
1923}
6b7c5b94 1924
10ef9ab4
SP		 1925static int be_tx_qs_create(struct be_adapter *adapter)
1926{
1927 struct be_tx_obj *txo;
1928 int i, status;
fe6d2a38 1929
3c8def97 1930 for_all_tx_queues(adapter, txo, i) {
10ef9ab4
SP		 1931 status = be_queue_alloc(adapter, &txo->q, TX_Q_LEN,
1932 sizeof(struct be_eth_wrb));
1933 if (status)
1934 return status;
6b7c5b94 1935
10ef9ab4
SP		 1936 status = be_cmd_txq_create(adapter, &txo->q, &txo->cq);
1937 if (status)
1938 return status;
3c8def97 1939 }
6b7c5b94 1940
d379142b
SP		 1941 dev_info(&adapter->pdev->dev, "created %d TX queue(s)\n",
1942 adapter->num_tx_qs);
10ef9ab4 1943 return 0;
6b7c5b94
SP		 1944}
1945
10ef9ab4 1946static void be_rx_cqs_destroy(struct be_adapter *adapter)
6b7c5b94
SP		 1947{
1948 struct be_queue_info *q;
3abcdeda
SP		 1949 struct be_rx_obj *rxo;
1950 int i;
1951
1952 for_all_rx_queues(adapter, rxo, i) {
3abcdeda
SP		 1953 q = &rxo->cq;
1954 if (q->created)
1955 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1956 be_queue_free(adapter, q);
ac6a0c4a
SP		 1957 }
1958}
1959
10ef9ab4 1960static int be_rx_cqs_create(struct be_adapter *adapter)
6b7c5b94 1961{
10ef9ab4 1962 struct be_queue_info *eq, *cq;
3abcdeda
SP		 1963 struct be_rx_obj *rxo;
1964 int rc, i;
6b7c5b94 1965
10ef9ab4
SP		 1966 /* We'll create as many RSS rings as there are irqs.
1967 * But when there's only one irq there's no use creating RSS rings
1968 */
1969 adapter->num_rx_qs = (num_irqs(adapter) > 1) ?
1970 num_irqs(adapter) + 1 : 1;
7f640062
SP		 1971 if (adapter->num_rx_qs != MAX_RX_QS) {
1972 rtnl_lock();
1973 netif_set_real_num_rx_queues(adapter->netdev,
1974 adapter->num_rx_qs);
1975 rtnl_unlock();
1976 }
ac6a0c4a 1977
6b7c5b94 1978 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
3abcdeda
SP		 1979 for_all_rx_queues(adapter, rxo, i) {
1980 rxo->adapter = adapter;
3abcdeda
SP		 1981 cq = &rxo->cq;
1982 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1983 sizeof(struct be_eth_rx_compl));
1984 if (rc)
10ef9ab4 1985 return rc;
3abcdeda 1986
10ef9ab4
SP		 1987 eq = &adapter->eq_obj[i % adapter->num_evt_qs].q;
1988 rc = be_cmd_cq_create(adapter, cq, eq, false, 3);
3abcdeda 1989 if (rc)
10ef9ab4 1990 return rc;
3abcdeda 1991 }
6b7c5b94 1992
d379142b
SP		 1993 dev_info(&adapter->pdev->dev,
1994 "created %d RSS queue(s) and 1 default RX queue\n",
1995 adapter->num_rx_qs - 1);
10ef9ab4 1996 return 0;
b628bde2
SP		 1997}
1998
6b7c5b94
SP		 1999static irqreturn_t be_intx(int irq, void *dev)
2000{
2001 struct be_adapter *adapter = dev;
10ef9ab4 2002 int num_evts;
6b7c5b94 2003
10ef9ab4
SP		 2004 /* With INTx only one EQ is used */
2005 num_evts = event_handle(&adapter->eq_obj[0]);
2006 if (num_evts)
2007 return IRQ_HANDLED;
2008 else
2009 return IRQ_NONE;
6b7c5b94
SP		 2010}
2011
10ef9ab4 2012static irqreturn_t be_msix(int irq, void *dev)
6b7c5b94 2013{
10ef9ab4 2014 struct be_eq_obj *eqo = dev;
6b7c5b94 2015
10ef9ab4 2016 event_handle(eqo);
6b7c5b94
SP		 2017 return IRQ_HANDLED;
2018}
2019
2e588f84 2020static inline bool do_gro(struct be_rx_compl_info *rxcp)
6b7c5b94 2021{
2e588f84 2022 return (rxcp->tcpf && !rxcp->err) ? true : false;
6b7c5b94
SP		 2023}
2024
10ef9ab4
SP		 2025static int be_process_rx(struct be_rx_obj *rxo, struct napi_struct *napi,
2026 int budget)
6b7c5b94 2027{
3abcdeda
SP		 2028 struct be_adapter *adapter = rxo->adapter;
2029 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 2030 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 2031 u32 work_done;
2032
2033 for (work_done = 0; work_done < budget; work_done++) {
3abcdeda 2034 rxcp = be_rx_compl_get(rxo);
6b7c5b94
SP		 2035 if (!rxcp)
2036 break;
2037
12004ae9
SP		 2038 /* Is it a flush compl that has no data */
2039 if (unlikely(rxcp->num_rcvd == 0))
2040 goto loop_continue;
2041
2042 /* Discard compl with partial DMA Lancer B0 */
2043 if (unlikely(!rxcp->pkt_size)) {
10ef9ab4 2044 be_rx_compl_discard(rxo, rxcp);
12004ae9
SP		 2045 goto loop_continue;
2046 }
2047
2048 /* On BE drop pkts that arrive due to imperfect filtering in
2049 * promiscuous mode on some skews
2050 */
2051 if (unlikely(rxcp->port != adapter->port_num &&
2052 !lancer_chip(adapter))) {
10ef9ab4 2053 be_rx_compl_discard(rxo, rxcp);
12004ae9 2054 goto loop_continue;
64642811 2055 }
009dd872 2056
12004ae9 2057 if (do_gro(rxcp))
10ef9ab4 2058 be_rx_compl_process_gro(rxo, napi, rxcp);
12004ae9 2059 else
10ef9ab4 2060 be_rx_compl_process(rxo, rxcp);
12004ae9 2061loop_continue:
2e588f84 2062 be_rx_stats_update(rxo, rxcp);
6b7c5b94
SP		 2063 }
2064
10ef9ab4
SP		 2065 if (work_done) {
2066 be_cq_notify(adapter, rx_cq->id, true, work_done);
9372cacb 2067
10ef9ab4
SP		 2068 if (atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM)
2069 be_post_rx_frags(rxo, GFP_ATOMIC);
6b7c5b94 2070 }
10ef9ab4 2071
6b7c5b94
SP		 2072 return work_done;
2073}
2074
10ef9ab4
SP		 2075static bool be_process_tx(struct be_adapter *adapter, struct be_tx_obj *txo,
2076 int budget, int idx)
6b7c5b94 2077{
6b7c5b94 2078 struct be_eth_tx_compl *txcp;
10ef9ab4 2079 int num_wrbs = 0, work_done;
3c8def97 2080
10ef9ab4
SP		 2081 for (work_done = 0; work_done < budget; work_done++) {
2082 txcp = be_tx_compl_get(&txo->cq);
2083 if (!txcp)
2084 break;
2085 num_wrbs += be_tx_compl_process(adapter, txo,
3c8def97
SP		 2086 AMAP_GET_BITS(struct amap_eth_tx_compl,
2087 wrb_index, txcp));
10ef9ab4 2088 }
6b7c5b94 2089
10ef9ab4
SP		 2090 if (work_done) {
2091 be_cq_notify(adapter, txo->cq.id, true, work_done);
2092 atomic_sub(num_wrbs, &txo->q.used);
3c8def97 2093
10ef9ab4
SP		 2094 /* As Tx wrbs have been freed up, wake up netdev queue
2095 * if it was stopped due to lack of tx wrbs. */
2096 if (__netif_subqueue_stopped(adapter->netdev, idx) &&
2097 atomic_read(&txo->q.used) < txo->q.len / 2) {
2098 netif_wake_subqueue(adapter->netdev, idx);
3c8def97 2099 }
10ef9ab4
SP		 2100
2101 u64_stats_update_begin(&tx_stats(txo)->sync_compl);
2102 tx_stats(txo)->tx_compl += work_done;
2103 u64_stats_update_end(&tx_stats(txo)->sync_compl);
6b7c5b94 2104 }
10ef9ab4
SP		 2105 return (work_done < budget); /* Done */
2106}
6b7c5b94 2107
10ef9ab4
SP		 2108int be_poll(struct napi_struct *napi, int budget)
2109{
2110 struct be_eq_obj *eqo = container_of(napi, struct be_eq_obj, napi);
2111 struct be_adapter *adapter = eqo->adapter;
2112 int max_work = 0, work, i;
2113 bool tx_done;
f31e50a8 2114
10ef9ab4
SP		 2115 /* Process all TXQs serviced by this EQ */
2116 for (i = eqo->idx; i < adapter->num_tx_qs; i += adapter->num_evt_qs) {
2117 tx_done = be_process_tx(adapter, &adapter->tx_obj[i],
2118 eqo->tx_budget, i);
2119 if (!tx_done)
2120 max_work = budget;
f31e50a8
SP		 2121 }
2122
10ef9ab4
SP		 2123 /* This loop will iterate twice for EQ0 in which
2124 * completions of the last RXQ (default one) are also processed
2125 * For other EQs the loop iterates only once
2126 */
2127 for (i = eqo->idx; i < adapter->num_rx_qs; i += adapter->num_evt_qs) {
2128 work = be_process_rx(&adapter->rx_obj[i], napi, budget);
2129 max_work = max(work, max_work);
2130 }
6b7c5b94 2131
10ef9ab4
SP		 2132 if (is_mcc_eqo(eqo))
2133 be_process_mcc(adapter);
93c86700 2134
10ef9ab4
SP		 2135 if (max_work < budget) {
2136 napi_complete(napi);
2137 be_eq_notify(adapter, eqo->q.id, true, false, 0);
2138 } else {
2139 /* As we'll continue in polling mode, count and clear events */
2140 be_eq_notify(adapter, eqo->q.id, false, false, events_get(eqo));
93c86700 2141 }
10ef9ab4 2142 return max_work;
6b7c5b94
SP		 2143}
2144
f67ef7ba 2145void be_detect_error(struct be_adapter *adapter)
7c185276 2146{
e1cfb67a
PR		 2147 u32 ue_lo = 0, ue_hi = 0, ue_lo_mask = 0, ue_hi_mask = 0;
2148 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
7c185276
AK		 2149 u32 i;
2150
f67ef7ba 2151 if (be_crit_error(adapter))
72f02485
SP		 2152 return;
2153
e1cfb67a
PR		 2154 if (lancer_chip(adapter)) {
2155 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
2156 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2157 sliport_err1 = ioread32(adapter->db +
2158 SLIPORT_ERROR1_OFFSET);
2159 sliport_err2 = ioread32(adapter->db +
2160 SLIPORT_ERROR2_OFFSET);
2161 }
2162 } else {
2163 pci_read_config_dword(adapter->pdev,
2164 PCICFG_UE_STATUS_LOW, &ue_lo);
2165 pci_read_config_dword(adapter->pdev,
2166 PCICFG_UE_STATUS_HIGH, &ue_hi);
2167 pci_read_config_dword(adapter->pdev,
2168 PCICFG_UE_STATUS_LOW_MASK, &ue_lo_mask);
2169 pci_read_config_dword(adapter->pdev,
2170 PCICFG_UE_STATUS_HI_MASK, &ue_hi_mask);
2171
f67ef7ba
PR		 2172 ue_lo = (ue_lo & ~ue_lo_mask);
2173 ue_hi = (ue_hi & ~ue_hi_mask);
e1cfb67a 2174 }
7c185276 2175
1451ae6e
AK		 2176 /* On certain platforms BE hardware can indicate spurious UEs.
2177 * Allow the h/w to stop working completely in case of a real UE.
2178 * Hence not setting the hw_error for UE detection.
2179 */
2180 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
f67ef7ba 2181 adapter->hw_error = true;
434b3648 2182 dev_err(&adapter->pdev->dev,
f67ef7ba
PR		 2183 "Error detected in the card\n");
2184 }
2185
2186 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2187 dev_err(&adapter->pdev->dev,
2188 "ERR: sliport status 0x%x\n", sliport_status);
2189 dev_err(&adapter->pdev->dev,
2190 "ERR: sliport error1 0x%x\n", sliport_err1);
2191 dev_err(&adapter->pdev->dev,
2192 "ERR: sliport error2 0x%x\n", sliport_err2);
d053de91
AK		 2193 }
2194
e1cfb67a
PR		 2195 if (ue_lo) {
2196 for (i = 0; ue_lo; ue_lo >>= 1, i++) {
2197 if (ue_lo & 1)
7c185276
AK		 2198 dev_err(&adapter->pdev->dev,
2199 "UE: %s bit set\n", ue_status_low_desc[i]);
2200 }
2201 }
f67ef7ba 2202
e1cfb67a
PR		 2203 if (ue_hi) {
2204 for (i = 0; ue_hi; ue_hi >>= 1, i++) {
2205 if (ue_hi & 1)
7c185276
AK		 2206 dev_err(&adapter->pdev->dev,
2207 "UE: %s bit set\n", ue_status_hi_desc[i]);
2208 }
2209 }
2210
2211}
2212
8d56ff11
SP		 2213static void be_msix_disable(struct be_adapter *adapter)
2214{
ac6a0c4a 2215 if (msix_enabled(adapter)) {
8d56ff11 2216 pci_disable_msix(adapter->pdev);
ac6a0c4a 2217 adapter->num_msix_vec = 0;
3abcdeda
SP		 2218 }
2219}
2220
10ef9ab4
SP		 2221static uint be_num_rss_want(struct be_adapter *adapter)
2222{
30e80b55 2223 u32 num = 0;
abb93951 2224
10ef9ab4 2225 if ((adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
abb93951
PR		 2226 (lancer_chip(adapter) ||
2227 (!sriov_want(adapter) && be_physfn(adapter)))) {
2228 num = adapter->max_rss_queues;
30e80b55
YM		 2229 num = min_t(u32, num, (u32)netif_get_num_default_rss_queues());
2230 }
2231 return num;
10ef9ab4
SP		 2232}
2233
6b7c5b94
SP		 2234static void be_msix_enable(struct be_adapter *adapter)
2235{
10ef9ab4 2236#define BE_MIN_MSIX_VECTORS 1
045508a8 2237 int i, status, num_vec, num_roce_vec = 0;
d379142b 2238 struct device *dev = &adapter->pdev->dev;
6b7c5b94 2239
10ef9ab4
SP		 2240 /* If RSS queues are not used, need a vec for default RX Q */
2241 num_vec = min(be_num_rss_want(adapter), num_online_cpus());
045508a8
PP		 2242 if (be_roce_supported(adapter)) {
2243 num_roce_vec = min_t(u32, MAX_ROCE_MSIX_VECTORS,
2244 (num_online_cpus() + 1));
2245 num_roce_vec = min(num_roce_vec, MAX_ROCE_EQS);
2246 num_vec += num_roce_vec;
2247 num_vec = min(num_vec, MAX_MSIX_VECTORS);
2248 }
10ef9ab4 2249 num_vec = max(num_vec, BE_MIN_MSIX_VECTORS);
3abcdeda 2250
ac6a0c4a 2251 for (i = 0; i < num_vec; i++)
6b7c5b94
SP		 2252 adapter->msix_entries[i].entry = i;
2253
ac6a0c4a 2254 status = pci_enable_msix(adapter->pdev, adapter->msix_entries, num_vec);
3abcdeda
SP		 2255 if (status == 0) {
2256 goto done;
2257 } else if (status >= BE_MIN_MSIX_VECTORS) {
ac6a0c4a 2258 num_vec = status;
3abcdeda 2259 if (pci_enable_msix(adapter->pdev, adapter->msix_entries,
ac6a0c4a 2260 num_vec) == 0)
3abcdeda 2261 goto done;
3abcdeda 2262 }
d379142b
SP		 2263
2264 dev_warn(dev, "MSIx enable failed\n");
3abcdeda
SP		 2265 return;
2266done:
045508a8
PP		 2267 if (be_roce_supported(adapter)) {
2268 if (num_vec > num_roce_vec) {
2269 adapter->num_msix_vec = num_vec - num_roce_vec;
2270 adapter->num_msix_roce_vec =
2271 num_vec - adapter->num_msix_vec;
2272 } else {
2273 adapter->num_msix_vec = num_vec;
2274 adapter->num_msix_roce_vec = 0;
2275 }
2276 } else
2277 adapter->num_msix_vec = num_vec;
d379142b 2278 dev_info(dev, "enabled %d MSI-x vector(s)\n", adapter->num_msix_vec);
ac6a0c4a 2279 return;
6b7c5b94
SP		 2280}
2281
fe6d2a38 2282static inline int be_msix_vec_get(struct be_adapter *adapter,
10ef9ab4 2283 struct be_eq_obj *eqo)
b628bde2 2284{
10ef9ab4 2285 return adapter->msix_entries[eqo->idx].vector;
b628bde2 2286}
6b7c5b94 2287
b628bde2
SP		 2288static int be_msix_register(struct be_adapter *adapter)
2289{
10ef9ab4
SP		 2290 struct net_device *netdev = adapter->netdev;
2291 struct be_eq_obj *eqo;
2292 int status, i, vec;
6b7c5b94 2293
10ef9ab4
SP		 2294 for_all_evt_queues(adapter, eqo, i) {
2295 sprintf(eqo->desc, "%s-q%d", netdev->name, i);
2296 vec = be_msix_vec_get(adapter, eqo);
2297 status = request_irq(vec, be_msix, 0, eqo->desc, eqo);
3abcdeda
SP		 2298 if (status)
2299 goto err_msix;
2300 }
b628bde2 2301
6b7c5b94 2302 return 0;
3abcdeda 2303err_msix:
10ef9ab4
SP		 2304 for (i--, eqo = &adapter->eq_obj[i]; i >= 0; i--, eqo--)
2305 free_irq(be_msix_vec_get(adapter, eqo), eqo);
2306 dev_warn(&adapter->pdev->dev, "MSIX Request IRQ failed - err %d\n",
2307 status);
ac6a0c4a 2308 be_msix_disable(adapter);
6b7c5b94
SP		 2309 return status;
2310}
2311
2312static int be_irq_register(struct be_adapter *adapter)
2313{
2314 struct net_device *netdev = adapter->netdev;
2315 int status;
2316
ac6a0c4a 2317 if (msix_enabled(adapter)) {
6b7c5b94
SP		 2318 status = be_msix_register(adapter);
2319 if (status == 0)
2320 goto done;
ba343c77
SB		 2321 /* INTx is not supported for VF */
2322 if (!be_physfn(adapter))
2323 return status;
6b7c5b94
SP		 2324 }
2325
2326 /* INTx */
2327 netdev->irq = adapter->pdev->irq;
2328 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
2329 adapter);
2330 if (status) {
2331 dev_err(&adapter->pdev->dev,
2332 "INTx request IRQ failed - err %d\n", status);
2333 return status;
2334 }
2335done:
2336 adapter->isr_registered = true;
2337 return 0;
2338}
2339
2340static void be_irq_unregister(struct be_adapter *adapter)
2341{
2342 struct net_device *netdev = adapter->netdev;
10ef9ab4 2343 struct be_eq_obj *eqo;
3abcdeda 2344 int i;
6b7c5b94
SP		 2345
2346 if (!adapter->isr_registered)
2347 return;
2348
2349 /* INTx */
ac6a0c4a 2350 if (!msix_enabled(adapter)) {
6b7c5b94
SP		 2351 free_irq(netdev->irq, adapter);
2352 goto done;
2353 }
2354
2355 /* MSIx */
10ef9ab4
SP		 2356 for_all_evt_queues(adapter, eqo, i)
2357 free_irq(be_msix_vec_get(adapter, eqo), eqo);
3abcdeda 2358
6b7c5b94
SP		 2359done:
2360 adapter->isr_registered = false;
6b7c5b94
SP		 2361}
2362
10ef9ab4 2363static void be_rx_qs_destroy(struct be_adapter *adapter)
482c9e79
SP		 2364{
2365 struct be_queue_info *q;
2366 struct be_rx_obj *rxo;
2367 int i;
2368
2369 for_all_rx_queues(adapter, rxo, i) {
2370 q = &rxo->q;
2371 if (q->created) {
2372 be_cmd_rxq_destroy(adapter, q);
2373 /* After the rxq is invalidated, wait for a grace time
2374 * of 1ms for all dma to end and the flush compl to
2375 * arrive
2376 */
2377 mdelay(1);
10ef9ab4 2378 be_rx_cq_clean(rxo);
482c9e79 2379 }
10ef9ab4 2380 be_queue_free(adapter, q);
482c9e79
SP		 2381 }
2382}
2383
889cd4b2
SP		 2384static int be_close(struct net_device *netdev)
2385{
2386 struct be_adapter *adapter = netdev_priv(netdev);
10ef9ab4
SP		 2387 struct be_eq_obj *eqo;
2388 int i;
889cd4b2 2389
045508a8
PP		 2390 be_roce_dev_close(adapter);
2391
889cd4b2
SP		 2392 be_async_mcc_disable(adapter);
2393
fe6d2a38
SP		 2394 if (!lancer_chip(adapter))
2395 be_intr_set(adapter, false);
889cd4b2 2396
10ef9ab4
SP		 2397 for_all_evt_queues(adapter, eqo, i) {
2398 napi_disable(&eqo->napi);
2399 if (msix_enabled(adapter))
2400 synchronize_irq(be_msix_vec_get(adapter, eqo));
2401 else
2402 synchronize_irq(netdev->irq);
2403 be_eq_clean(eqo);
63fcb27f
PR		 2404 }
2405
889cd4b2
SP		 2406 be_irq_unregister(adapter);
2407
889cd4b2
SP		 2408 /* Wait for all pending tx completions to arrive so that
2409 * all tx skbs are freed.
2410 */
0ae57bb3 2411 be_tx_compl_clean(adapter);
889cd4b2 2412
10ef9ab4 2413 be_rx_qs_destroy(adapter);
482c9e79
SP		 2414 return 0;
2415}
2416
10ef9ab4 2417static int be_rx_qs_create(struct be_adapter *adapter)
482c9e79
SP		 2418{
2419 struct be_rx_obj *rxo;
e9008ee9
PR		 2420 int rc, i, j;
2421 u8 rsstable[128];
482c9e79
SP		 2422
2423 for_all_rx_queues(adapter, rxo, i) {
10ef9ab4
SP		 2424 rc = be_queue_alloc(adapter, &rxo->q, RX_Q_LEN,
2425 sizeof(struct be_eth_rx_d));
2426 if (rc)
2427 return rc;
2428 }
2429
2430 /* The FW would like the default RXQ to be created first */
2431 rxo = default_rxo(adapter);
2432 rc = be_cmd_rxq_create(adapter, &rxo->q, rxo->cq.id, rx_frag_size,
2433 adapter->if_handle, false, &rxo->rss_id);
2434 if (rc)
2435 return rc;
2436
2437 for_all_rss_queues(adapter, rxo, i) {
482c9e79 2438 rc = be_cmd_rxq_create(adapter, &rxo->q, rxo->cq.id,
10ef9ab4
SP		 2439 rx_frag_size, adapter->if_handle,
2440 true, &rxo->rss_id);
482c9e79
SP		 2441 if (rc)
2442 return rc;
2443 }
2444
2445 if (be_multi_rxq(adapter)) {
e9008ee9
PR		 2446 for (j = 0; j < 128; j += adapter->num_rx_qs - 1) {
2447 for_all_rss_queues(adapter, rxo, i) {
2448 if ((j + i) >= 128)
2449 break;
2450 rsstable[j + i] = rxo->rss_id;
2451 }
2452 }
2453 rc = be_cmd_rss_config(adapter, rsstable, 128);
482c9e79
SP		 2454 if (rc)
2455 return rc;
2456 }
2457
2458 /* First time posting */
10ef9ab4 2459 for_all_rx_queues(adapter, rxo, i)
482c9e79 2460 be_post_rx_frags(rxo, GFP_KERNEL);
889cd4b2
SP		 2461 return 0;
2462}
2463
6b7c5b94
SP		 2464static int be_open(struct net_device *netdev)
2465{
2466 struct be_adapter *adapter = netdev_priv(netdev);
10ef9ab4 2467 struct be_eq_obj *eqo;
3abcdeda 2468 struct be_rx_obj *rxo;
10ef9ab4 2469 struct be_tx_obj *txo;
b236916a 2470 u8 link_status;
3abcdeda 2471 int status, i;
5fb379ee 2472
10ef9ab4 2473 status = be_rx_qs_create(adapter);
482c9e79
SP		 2474 if (status)
2475 goto err;
2476
5fb379ee
SP		 2477 be_irq_register(adapter);
2478
fe6d2a38
SP		 2479 if (!lancer_chip(adapter))
2480 be_intr_set(adapter, true);
5fb379ee 2481
10ef9ab4 2482 for_all_rx_queues(adapter, rxo, i)
3abcdeda 2483 be_cq_notify(adapter, rxo->cq.id, true, 0);
5fb379ee 2484
10ef9ab4
SP		 2485 for_all_tx_queues(adapter, txo, i)
2486 be_cq_notify(adapter, txo->cq.id, true, 0);
2487
7a1e9b20
SP		 2488 be_async_mcc_enable(adapter);
2489
10ef9ab4
SP		 2490 for_all_evt_queues(adapter, eqo, i) {
2491 napi_enable(&eqo->napi);
2492 be_eq_notify(adapter, eqo->q.id, true, false, 0);
2493 }
2494
323ff71e 2495 status = be_cmd_link_status_query(adapter, NULL, &link_status, 0);
b236916a
AK		 2496 if (!status)
2497 be_link_status_update(adapter, link_status);
2498
045508a8 2499 be_roce_dev_open(adapter);
889cd4b2
SP		 2500 return 0;
2501err:
2502 be_close(adapter->netdev);
2503 return -EIO;
5fb379ee
SP		 2504}
2505
71d8d1b5
AK		 2506static int be_setup_wol(struct be_adapter *adapter, bool enable)
2507{
2508 struct be_dma_mem cmd;
2509 int status = 0;
2510 u8 mac[ETH_ALEN];
2511
2512 memset(mac, 0, ETH_ALEN);
2513
2514 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
2b7bcebf
IV		 2515 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2516 GFP_KERNEL);
71d8d1b5
AK		 2517 if (cmd.va == NULL)
2518 return -1;
2519 memset(cmd.va, 0, cmd.size);
2520
2521 if (enable) {
2522 status = pci_write_config_dword(adapter->pdev,
2523 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
2524 if (status) {
2525 dev_err(&adapter->pdev->dev,
2381a55c 2526 "Could not enable Wake-on-lan\n");
2b7bcebf
IV		 2527 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
2528 cmd.dma);
71d8d1b5
AK		 2529 return status;
2530 }
2531 status = be_cmd_enable_magic_wol(adapter,
2532 adapter->netdev->dev_addr, &cmd);
2533 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
2534 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
2535 } else {
2536 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
2537 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
2538 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
2539 }
2540
2b7bcebf 2541 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
71d8d1b5
AK		 2542 return status;
2543}
2544
6d87f5c3
AK		 2545/*
2546 * Generate a seed MAC address from the PF MAC Address using jhash.
2547 * MAC Address for VFs are assigned incrementally starting from the seed.
2548 * These addresses are programmed in the ASIC by the PF and the VF driver
2549 * queries for the MAC address during its probe.
2550 */
2551static inline int be_vf_eth_addr_config(struct be_adapter *adapter)
2552{
f9449ab7 2553 u32 vf;
3abcdeda 2554 int status = 0;
6d87f5c3 2555 u8 mac[ETH_ALEN];
11ac75ed 2556 struct be_vf_cfg *vf_cfg;
6d87f5c3
AK		 2557
2558 be_vf_eth_addr_generate(adapter, mac);
2559
11ac75ed 2560 for_all_vfs(adapter, vf_cfg, vf) {
590c391d
PR		 2561 if (lancer_chip(adapter)) {
2562 status = be_cmd_set_mac_list(adapter, mac, 1, vf + 1);
2563 } else {
2564 status = be_cmd_pmac_add(adapter, mac,
11ac75ed
SP		 2565 vf_cfg->if_handle,
2566 &vf_cfg->pmac_id, vf + 1);
590c391d
PR		 2567 }
2568
6d87f5c3
AK		 2569 if (status)
2570 dev_err(&adapter->pdev->dev,
590c391d 2571 "Mac address assignment failed for VF %d\n", vf);
6d87f5c3 2572 else
11ac75ed 2573 memcpy(vf_cfg->mac_addr, mac, ETH_ALEN);
6d87f5c3
AK		 2574
2575 mac[5] += 1;
2576 }
2577 return status;
2578}
2579
f9449ab7 2580static void be_vf_clear(struct be_adapter *adapter)
6d87f5c3 2581{
11ac75ed 2582 struct be_vf_cfg *vf_cfg;
6d87f5c3
AK		 2583 u32 vf;
2584
39f1d94d
SP		 2585 if (be_find_vfs(adapter, ASSIGNED)) {
2586 dev_warn(&adapter->pdev->dev, "VFs are assigned to VMs\n");
2587 goto done;
2588 }
2589
11ac75ed 2590 for_all_vfs(adapter, vf_cfg, vf) {
590c391d
PR		 2591 if (lancer_chip(adapter))
2592 be_cmd_set_mac_list(adapter, NULL, 0, vf + 1);
2593 else
11ac75ed
SP		 2594 be_cmd_pmac_del(adapter, vf_cfg->if_handle,
2595 vf_cfg->pmac_id, vf + 1);
f9449ab7 2596
11ac75ed
SP		 2597 be_cmd_if_destroy(adapter, vf_cfg->if_handle, vf + 1);
2598 }
39f1d94d
SP		 2599 pci_disable_sriov(adapter->pdev);
2600done:
2601 kfree(adapter->vf_cfg);
2602 adapter->num_vfs = 0;
6d87f5c3
AK		 2603}
2604
a54769f5
SP		 2605static int be_clear(struct be_adapter *adapter)
2606{
fbc13f01
AK		 2607 int i = 1;
2608
191eb756
SP		 2609 if (adapter->flags & BE_FLAGS_WORKER_SCHEDULED) {
2610 cancel_delayed_work_sync(&adapter->work);
2611 adapter->flags &= ~BE_FLAGS_WORKER_SCHEDULED;
2612 }
2613
11ac75ed 2614 if (sriov_enabled(adapter))
f9449ab7
SP		 2615 be_vf_clear(adapter);
2616
fbc13f01
AK		 2617 for (; adapter->uc_macs > 0; adapter->uc_macs--, i++)
2618 be_cmd_pmac_del(adapter, adapter->if_handle,
2619 adapter->pmac_id[i], 0);
2620
f9449ab7 2621 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
a54769f5
SP		 2622
2623 be_mcc_queues_destroy(adapter);
10ef9ab4 2624 be_rx_cqs_destroy(adapter);
a54769f5 2625 be_tx_queues_destroy(adapter);
10ef9ab4 2626 be_evt_queues_destroy(adapter);
a54769f5 2627
abb93951
PR		 2628 kfree(adapter->pmac_id);
2629 adapter->pmac_id = NULL;
2630
10ef9ab4 2631 be_msix_disable(adapter);
a54769f5
SP		 2632 return 0;
2633}
2634
abb93951
PR		 2635static void be_get_vf_if_cap_flags(struct be_adapter *adapter,
2636 u32 *cap_flags, u8 domain)
2637{
2638 bool profile_present = false;
2639 int status;
2640
2641 if (lancer_chip(adapter)) {
2642 status = be_cmd_get_profile_config(adapter, cap_flags, domain);
2643 if (!status)
2644 profile_present = true;
2645 }
2646
2647 if (!profile_present)
2648 *cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
2649 BE_IF_FLAGS_MULTICAST;
2650}
2651
39f1d94d 2652static int be_vf_setup_init(struct be_adapter *adapter)
30128031 2653{
11ac75ed 2654 struct be_vf_cfg *vf_cfg;
30128031
SP		 2655 int vf;
2656
39f1d94d
SP		 2657 adapter->vf_cfg = kcalloc(adapter->num_vfs, sizeof(*vf_cfg),
2658 GFP_KERNEL);
2659 if (!adapter->vf_cfg)
2660 return -ENOMEM;
2661
11ac75ed
SP		 2662 for_all_vfs(adapter, vf_cfg, vf) {
2663 vf_cfg->if_handle = -1;
2664 vf_cfg->pmac_id = -1;
30128031 2665 }
39f1d94d 2666 return 0;
30128031
SP		 2667}
2668
f9449ab7
SP		 2669static int be_vf_setup(struct be_adapter *adapter)
2670{
11ac75ed 2671 struct be_vf_cfg *vf_cfg;
39f1d94d 2672 struct device *dev = &adapter->pdev->dev;
f9449ab7 2673 u32 cap_flags, en_flags, vf;
f1f3ee1b 2674 u16 def_vlan, lnk_speed;
39f1d94d
SP		 2675 int status, enabled_vfs;
2676
2677 enabled_vfs = be_find_vfs(adapter, ENABLED);
2678 if (enabled_vfs) {
2679 dev_warn(dev, "%d VFs are already enabled\n", enabled_vfs);
2680 dev_warn(dev, "Ignoring num_vfs=%d setting\n", num_vfs);
2681 return 0;
2682 }
f9449ab7 2683
39f1d94d
SP		 2684 if (num_vfs > adapter->dev_num_vfs) {
2685 dev_warn(dev, "Device supports %d VFs and not %d\n",
2686 adapter->dev_num_vfs, num_vfs);
2687 num_vfs = adapter->dev_num_vfs;
2688 }
2689
2690 status = pci_enable_sriov(adapter->pdev, num_vfs);
2691 if (!status) {
2692 adapter->num_vfs = num_vfs;
2693 } else {
2694 /* Platform doesn't support SRIOV though device supports it */
2695 dev_warn(dev, "SRIOV enable failed\n");
2696 return 0;
2697 }
2698
2699 status = be_vf_setup_init(adapter);
2700 if (status)
2701 goto err;
30128031 2702
11ac75ed 2703 for_all_vfs(adapter, vf_cfg, vf) {
abb93951
PR		 2704 be_get_vf_if_cap_flags(adapter, &cap_flags, vf + 1);
2705
2706 en_flags = cap_flags & (BE_IF_FLAGS_UNTAGGED |
2707 BE_IF_FLAGS_BROADCAST |
2708 BE_IF_FLAGS_MULTICAST);
2709
1578e777
PR		 2710 status = be_cmd_if_create(adapter, cap_flags, en_flags,
2711 &vf_cfg->if_handle, vf + 1);
f9449ab7
SP		 2712 if (status)
2713 goto err;
f9449ab7
SP		 2714 }
2715
39f1d94d
SP		 2716 if (!enabled_vfs) {
2717 status = be_vf_eth_addr_config(adapter);
2718 if (status)
2719 goto err;
2720 }
f9449ab7 2721
11ac75ed 2722 for_all_vfs(adapter, vf_cfg, vf) {
8a046d3b
VV		 2723 lnk_speed = 1000;
2724 status = be_cmd_set_qos(adapter, lnk_speed, vf + 1);
f9449ab7
SP		 2725 if (status)
2726 goto err;
11ac75ed 2727 vf_cfg->tx_rate = lnk_speed * 10;
f1f3ee1b
AK		 2728
2729 status = be_cmd_get_hsw_config(adapter, &def_vlan,
2730 vf + 1, vf_cfg->if_handle);
2731 if (status)
2732 goto err;
2733 vf_cfg->def_vid = def_vlan;
f9449ab7
SP		 2734 }
2735 return 0;
2736err:
2737 return status;
2738}
2739
30128031
SP		 2740static void be_setup_init(struct be_adapter *adapter)
2741{
2742 adapter->vlan_prio_bmap = 0xff;
42f11cf2 2743 adapter->phy.link_speed = -1;
30128031
SP		 2744 adapter->if_handle = -1;
2745 adapter->be3_native = false;
2746 adapter->promiscuous = false;
2747 adapter->eq_next_idx = 0;
f25b119c
PR		 2748
2749 if (be_physfn(adapter))
2750 adapter->cmd_privileges = MAX_PRIVILEGES;
2751 else
2752 adapter->cmd_privileges = MIN_PRIVILEGES;
30128031
SP		 2753}
2754
1578e777
PR		 2755static int be_get_mac_addr(struct be_adapter *adapter, u8 *mac, u32 if_handle,
2756 bool *active_mac, u32 *pmac_id)
590c391d 2757{
1578e777 2758 int status = 0;
e5e1ee89 2759
1578e777
PR		 2760 if (!is_zero_ether_addr(adapter->netdev->perm_addr)) {
2761 memcpy(mac, adapter->netdev->dev_addr, ETH_ALEN);
2762 if (!lancer_chip(adapter) && !be_physfn(adapter))
2763 *active_mac = true;
2764 else
2765 *active_mac = false;
e5e1ee89 2766
1578e777
PR		 2767 return status;
2768 }
e5e1ee89 2769
1578e777
PR		 2770 if (lancer_chip(adapter)) {
2771 status = be_cmd_get_mac_from_list(adapter, mac,
2772 active_mac, pmac_id, 0);
2773 if (*active_mac) {
5ee4979b
SP		 2774 status = be_cmd_mac_addr_query(adapter, mac, false,
2775 if_handle, *pmac_id);
1578e777
PR		 2776 }
2777 } else if (be_physfn(adapter)) {
2778 /* For BE3, for PF get permanent MAC */
5ee4979b 2779 status = be_cmd_mac_addr_query(adapter, mac, true, 0, 0);
1578e777 2780 *active_mac = false;
e5e1ee89 2781 } else {
1578e777 2782 /* For BE3, for VF get soft MAC assigned by PF*/
5ee4979b 2783 status = be_cmd_mac_addr_query(adapter, mac, false,
1578e777
PR		 2784 if_handle, 0);
2785 *active_mac = true;
e5e1ee89 2786 }
590c391d
PR		 2787 return status;
2788}
2789
abb93951
PR		 2790static void be_get_resources(struct be_adapter *adapter)
2791{
2792 int status;
2793 bool profile_present = false;
2794
2795 if (lancer_chip(adapter)) {
2796 status = be_cmd_get_func_config(adapter);
2797
2798 if (!status)
2799 profile_present = true;
2800 }
2801
2802 if (profile_present) {
2803 /* Sanity fixes for Lancer */
2804 adapter->max_pmac_cnt = min_t(u16, adapter->max_pmac_cnt,
2805 BE_UC_PMAC_COUNT);
2806 adapter->max_vlans = min_t(u16, adapter->max_vlans,
2807 BE_NUM_VLANS_SUPPORTED);
2808 adapter->max_mcast_mac = min_t(u16, adapter->max_mcast_mac,
2809 BE_MAX_MC);
2810 adapter->max_tx_queues = min_t(u16, adapter->max_tx_queues,
2811 MAX_TX_QS);
2812 adapter->max_rss_queues = min_t(u16, adapter->max_rss_queues,
2813 BE3_MAX_RSS_QS);
2814 adapter->max_event_queues = min_t(u16,
2815 adapter->max_event_queues,
2816 BE3_MAX_RSS_QS);
2817
2818 if (adapter->max_rss_queues &&
2819 adapter->max_rss_queues == adapter->max_rx_queues)
2820 adapter->max_rss_queues -= 1;
2821
2822 if (adapter->max_event_queues < adapter->max_rss_queues)
2823 adapter->max_rss_queues = adapter->max_event_queues;
2824
2825 } else {
2826 if (be_physfn(adapter))
2827 adapter->max_pmac_cnt = BE_UC_PMAC_COUNT;
2828 else
2829 adapter->max_pmac_cnt = BE_VF_UC_PMAC_COUNT;
2830
2831 if (adapter->function_mode & FLEX10_MODE)
2832 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/8;
2833 else
2834 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2835
2836 adapter->max_mcast_mac = BE_MAX_MC;
2837 adapter->max_tx_queues = MAX_TX_QS;
2838 adapter->max_rss_queues = (adapter->be3_native) ?
2839 BE3_MAX_RSS_QS : BE2_MAX_RSS_QS;
2840 adapter->max_event_queues = BE3_MAX_RSS_QS;
2841
2842 adapter->if_cap_flags = BE_IF_FLAGS_UNTAGGED |
2843 BE_IF_FLAGS_BROADCAST |
2844 BE_IF_FLAGS_MULTICAST |
2845 BE_IF_FLAGS_PASS_L3L4_ERRORS |
2846 BE_IF_FLAGS_MCAST_PROMISCUOUS |
2847 BE_IF_FLAGS_VLAN_PROMISCUOUS |
2848 BE_IF_FLAGS_PROMISCUOUS;
2849
2850 if (adapter->function_caps & BE_FUNCTION_CAPS_RSS)
2851 adapter->if_cap_flags |= BE_IF_FLAGS_RSS;
2852 }
2853}
2854
39f1d94d
SP		 2855/* Routine to query per function resource limits */
2856static int be_get_config(struct be_adapter *adapter)
2857{
abb93951 2858 int pos, status;
39f1d94d
SP		 2859 u16 dev_num_vfs;
2860
abb93951
PR		 2861 status = be_cmd_query_fw_cfg(adapter, &adapter->port_num,
2862 &adapter->function_mode,
2863 &adapter->function_caps);
2864 if (status)
2865 goto err;
2866
2867 be_get_resources(adapter);
2868
2869 /* primary mac needs 1 pmac entry */
2870 adapter->pmac_id = kcalloc(adapter->max_pmac_cnt + 1,
2871 sizeof(u32), GFP_KERNEL);
2872 if (!adapter->pmac_id) {
2873 status = -ENOMEM;
2874 goto err;
2875 }
2876
39f1d94d
SP		 2877 pos = pci_find_ext_capability(adapter->pdev, PCI_EXT_CAP_ID_SRIOV);
2878 if (pos) {
2879 pci_read_config_word(adapter->pdev, pos + PCI_SRIOV_TOTAL_VF,
2880 &dev_num_vfs);
7c5a5242
VV		 2881 if (!lancer_chip(adapter))
2882 dev_num_vfs = min_t(u16, dev_num_vfs, MAX_VFS);
39f1d94d
SP		 2883 adapter->dev_num_vfs = dev_num_vfs;
2884 }
abb93951
PR		 2885err:
2886 return status;
39f1d94d
SP		 2887}
2888
5fb379ee
SP		 2889static int be_setup(struct be_adapter *adapter)
2890{
39f1d94d 2891 struct device *dev = &adapter->pdev->dev;
abb93951 2892 u32 en_flags;
a54769f5 2893 u32 tx_fc, rx_fc;
10ef9ab4 2894 int status;
ba343c77 2895 u8 mac[ETH_ALEN];
1578e777 2896 bool active_mac;
ba343c77 2897
30128031 2898 be_setup_init(adapter);
6b7c5b94 2899
abb93951
PR		 2900 if (!lancer_chip(adapter))
2901 be_cmd_req_native_mode(adapter);
39f1d94d 2902
abb93951
PR		 2903 status = be_get_config(adapter);
2904 if (status)
2905 goto err;
73d540f2 2906
10ef9ab4
SP		 2907 be_msix_enable(adapter);
2908
2909 status = be_evt_queues_create(adapter);
2910 if (status)
a54769f5 2911 goto err;
6b7c5b94 2912
10ef9ab4
SP		 2913 status = be_tx_cqs_create(adapter);
2914 if (status)
2915 goto err;
2916
2917 status = be_rx_cqs_create(adapter);
2918 if (status)
a54769f5 2919 goto err;
6b7c5b94 2920
f9449ab7 2921 status = be_mcc_queues_create(adapter);
10ef9ab4 2922 if (status)
a54769f5 2923 goto err;
6b7c5b94 2924
f25b119c
PR		 2925 be_cmd_get_fn_privileges(adapter, &adapter->cmd_privileges, 0);
2926 /* In UMC mode FW does not return right privileges.
2927 * Override with correct privilege equivalent to PF.
2928 */
2929 if (be_is_mc(adapter))
2930 adapter->cmd_privileges = MAX_PRIVILEGES;
2931
f9449ab7
SP		 2932 en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
2933 BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_PASS_L3L4_ERRORS;
5d5adb93 2934
abb93951 2935 if (adapter->function_caps & BE_FUNCTION_CAPS_RSS)
f9449ab7 2936 en_flags |= BE_IF_FLAGS_RSS;
1578e777 2937
abb93951 2938 en_flags = en_flags & adapter->if_cap_flags;
0b13fb45 2939
abb93951 2940 status = be_cmd_if_create(adapter, adapter->if_cap_flags, en_flags,
1578e777 2941 &adapter->if_handle, 0);
5fb379ee 2942 if (status != 0)
a54769f5 2943 goto err;
6b7c5b94 2944
1578e777
PR		 2945 memset(mac, 0, ETH_ALEN);
2946 active_mac = false;
2947 status = be_get_mac_addr(adapter, mac, adapter->if_handle,
2948 &active_mac, &adapter->pmac_id[0]);
2949 if (status != 0)
2950 goto err;
2951
2952 if (!active_mac) {
2953 status = be_cmd_pmac_add(adapter, mac, adapter->if_handle,
2954 &adapter->pmac_id[0], 0);
2955 if (status != 0)
2956 goto err;
2957 }
2958
2959 if (is_zero_ether_addr(adapter->netdev->dev_addr)) {
2960 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2961 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
f9449ab7 2962 }
0dffc83e 2963
10ef9ab4
SP		 2964 status = be_tx_qs_create(adapter);
2965 if (status)
2966 goto err;
2967
04b71175 2968 be_cmd_get_fw_ver(adapter, adapter->fw_ver, NULL);
5a56eb10 2969
1d1e9a46 2970 if (adapter->vlans_added)
10329df8 2971 be_vid_config(adapter);
7ab8b0b4 2972
a54769f5 2973 be_set_rx_mode(adapter->netdev);
5fb379ee 2974
ddc3f5cb 2975 be_cmd_get_flow_control(adapter, &tx_fc, &rx_fc);
590c391d 2976
ddc3f5cb
AK		 2977 if (rx_fc != adapter->rx_fc || tx_fc != adapter->tx_fc)
2978 be_cmd_set_flow_control(adapter, adapter->tx_fc,
a54769f5 2979 adapter->rx_fc);
2dc1deb6 2980
39f1d94d
SP		 2981 if (be_physfn(adapter) && num_vfs) {
2982 if (adapter->dev_num_vfs)
2983 be_vf_setup(adapter);
2984 else
2985 dev_warn(dev, "device doesn't support SRIOV\n");
f9449ab7
SP		 2986 }
2987
f25b119c
PR		 2988 status = be_cmd_get_phy_info(adapter);
2989 if (!status && be_pause_supported(adapter))
42f11cf2
AK		 2990 adapter->phy.fc_autoneg = 1;
2991
191eb756
SP		 2992 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
2993 adapter->flags |= BE_FLAGS_WORKER_SCHEDULED;
f9449ab7 2994 return 0;
a54769f5
SP		 2995err:
2996 be_clear(adapter);
2997 return status;
2998}
6b7c5b94 2999
66268739
IV		 3000#ifdef CONFIG_NET_POLL_CONTROLLER
3001static void be_netpoll(struct net_device *netdev)
3002{
3003 struct be_adapter *adapter = netdev_priv(netdev);
10ef9ab4 3004 struct be_eq_obj *eqo;
66268739
IV		 3005 int i;
3006
10ef9ab4
SP		 3007 for_all_evt_queues(adapter, eqo, i)
3008 event_handle(eqo);
3009
3010 return;
66268739
IV		 3011}
3012#endif
3013
84517482 3014#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
c165541e
PR		 3015char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
3016
fa9a6fed 3017static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 3018 const u8 *p, u32 img_start, int image_size,
3019 int hdr_size)
fa9a6fed
SB		 3020{
3021 u32 crc_offset;
3022 u8 flashed_crc[4];
3023 int status;
3f0d4560
AK		 3024
3025 crc_offset = hdr_size + img_start + image_size - 4;
3026
fa9a6fed 3027 p += crc_offset;
3f0d4560
AK		 3028
3029 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 3030 (image_size - 4));
fa9a6fed
SB		 3031 if (status) {
3032 dev_err(&adapter->pdev->dev,
3033 "could not get crc from flash, not flashing redboot\n");
3034 return false;
3035 }
3036
3037 /*update redboot only if crc does not match*/
3038 if (!memcmp(flashed_crc, p, 4))
3039 return false;
3040 else
3041 return true;
fa9a6fed
SB		 3042}
3043
306f1348
SP		 3044static bool phy_flashing_required(struct be_adapter *adapter)
3045{
42f11cf2
AK		 3046 return (adapter->phy.phy_type == TN_8022 &&
3047 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
306f1348
SP		 3048}
3049
c165541e
PR		 3050static bool is_comp_in_ufi(struct be_adapter *adapter,
3051 struct flash_section_info *fsec, int type)
3052{
3053 int i = 0, img_type = 0;
3054 struct flash_section_info_g2 *fsec_g2 = NULL;
3055
3056 if (adapter->generation != BE_GEN3)
3057 fsec_g2 = (struct flash_section_info_g2 *)fsec;
3058
3059 for (i = 0; i < MAX_FLASH_COMP; i++) {
3060 if (fsec_g2)
3061 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
3062 else
3063 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
3064
3065 if (img_type == type)
3066 return true;
3067 }
3068 return false;
3069
3070}
3071
3072struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
3073 int header_size,
3074 const struct firmware *fw)
3075{
3076 struct flash_section_info *fsec = NULL;
3077 const u8 *p = fw->data;
3078
3079 p += header_size;
3080 while (p < (fw->data + fw->size)) {
3081 fsec = (struct flash_section_info *)p;
3082 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
3083 return fsec;
3084 p += 32;
3085 }
3086 return NULL;
3087}
3088
3f0d4560 3089static int be_flash_data(struct be_adapter *adapter,
c165541e
PR		 3090 const struct firmware *fw,
3091 struct be_dma_mem *flash_cmd,
3092 int num_of_images)
3f0d4560 3093
84517482 3094{
3f0d4560 3095 int status = 0, i, filehdr_size = 0;
c165541e 3096 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
3f0d4560 3097 u32 total_bytes = 0, flash_op;
84517482
AK		 3098 int num_bytes;
3099 const u8 *p = fw->data;
3100 struct be_cmd_write_flashrom *req = flash_cmd->va;
215faf9c 3101 const struct flash_comp *pflashcomp;
c165541e
PR		 3102 int num_comp, hdr_size;
3103 struct flash_section_info *fsec = NULL;
3104
3105 struct flash_comp gen3_flash_types[] = {
3106 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, OPTYPE_ISCSI_ACTIVE,
3107 FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_iSCSI},
3108 { FLASH_REDBOOT_START_g3, OPTYPE_REDBOOT,
3109 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3, IMAGE_BOOT_CODE},
3110 { FLASH_iSCSI_BIOS_START_g3, OPTYPE_BIOS,
3111 FLASH_BIOS_IMAGE_MAX_SIZE_g3, IMAGE_OPTION_ROM_ISCSI},
3112 { FLASH_PXE_BIOS_START_g3, OPTYPE_PXE_BIOS,
3113 FLASH_BIOS_IMAGE_MAX_SIZE_g3, IMAGE_OPTION_ROM_PXE},
3114 { FLASH_FCoE_BIOS_START_g3, OPTYPE_FCOE_BIOS,
3115 FLASH_BIOS_IMAGE_MAX_SIZE_g3, IMAGE_OPTION_ROM_FCoE},
3116 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, OPTYPE_ISCSI_BACKUP,
3117 FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_BACKUP_iSCSI},
3118 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, OPTYPE_FCOE_FW_ACTIVE,
3119 FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_FCoE},
3120 { FLASH_FCoE_BACKUP_IMAGE_START_g3, OPTYPE_FCOE_FW_BACKUP,
3121 FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_BACKUP_FCoE},
3122 { FLASH_NCSI_START_g3, OPTYPE_NCSI_FW,
3123 FLASH_NCSI_IMAGE_MAX_SIZE_g3, IMAGE_NCSI},
3124 { FLASH_PHY_FW_START_g3, OPTYPE_PHY_FW,
3125 FLASH_PHY_FW_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_PHY}
3f0d4560 3126 };
c165541e
PR		 3127
3128 struct flash_comp gen2_flash_types[] = {
3129 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, OPTYPE_ISCSI_ACTIVE,
3130 FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_iSCSI},
3131 { FLASH_REDBOOT_START_g2, OPTYPE_REDBOOT,
3132 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2, IMAGE_BOOT_CODE},
3133 { FLASH_iSCSI_BIOS_START_g2, OPTYPE_BIOS,
3134 FLASH_BIOS_IMAGE_MAX_SIZE_g2, IMAGE_OPTION_ROM_ISCSI},
3135 { FLASH_PXE_BIOS_START_g2, OPTYPE_PXE_BIOS,
3136 FLASH_BIOS_IMAGE_MAX_SIZE_g2, IMAGE_OPTION_ROM_PXE},
3137 { FLASH_FCoE_BIOS_START_g2, OPTYPE_FCOE_BIOS,
3138 FLASH_BIOS_IMAGE_MAX_SIZE_g2, IMAGE_OPTION_ROM_FCoE},
3139 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, OPTYPE_ISCSI_BACKUP,
3140 FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_BACKUP_iSCSI},
3141 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, OPTYPE_FCOE_FW_ACTIVE,
3142 FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_FCoE},
3143 { FLASH_FCoE_BACKUP_IMAGE_START_g2, OPTYPE_FCOE_FW_BACKUP,
3144 FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_BACKUP_FCoE}
3f0d4560
AK		 3145 };
3146
3147 if (adapter->generation == BE_GEN3) {
3148 pflashcomp = gen3_flash_types;
3149 filehdr_size = sizeof(struct flash_file_hdr_g3);
215faf9c 3150 num_comp = ARRAY_SIZE(gen3_flash_types);
3f0d4560
AK		 3151 } else {
3152 pflashcomp = gen2_flash_types;
3153 filehdr_size = sizeof(struct flash_file_hdr_g2);
215faf9c 3154 num_comp = ARRAY_SIZE(gen2_flash_types);
84517482 3155 }
c165541e
PR		 3156 /* Get flash section info*/
3157 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
3158 if (!fsec) {
3159 dev_err(&adapter->pdev->dev,
3160 "Invalid Cookie. UFI corrupted ?\n");
3161 return -1;
3162 }
9fe96934 3163 for (i = 0; i < num_comp; i++) {
c165541e 3164 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
9fe96934 3165 continue;
c165541e
PR		 3166
3167 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
3168 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
3169 continue;
3170
3171 if (pflashcomp[i].optype == OPTYPE_PHY_FW) {
306f1348
SP		 3172 if (!phy_flashing_required(adapter))
3173 continue;
3174 }
c165541e
PR		 3175
3176 hdr_size = filehdr_size +
3177 (num_of_images * sizeof(struct image_hdr));
3178
3179 if ((pflashcomp[i].optype == OPTYPE_REDBOOT) &&
3180 (!be_flash_redboot(adapter, fw->data, pflashcomp[i].offset,
3181 pflashcomp[i].size, hdr_size)))
3f0d4560 3182 continue;
c165541e
PR		 3183
3184 /* Flash the component */
3f0d4560 3185 p = fw->data;
c165541e 3186 p += filehdr_size + pflashcomp[i].offset + img_hdrs_size;
306f1348
SP		 3187 if (p + pflashcomp[i].size > fw->data + fw->size)
3188 return -1;
3189 total_bytes = pflashcomp[i].size;
3f0d4560
AK		 3190 while (total_bytes) {
3191 if (total_bytes > 32*1024)
3192 num_bytes = 32*1024;
3193 else
3194 num_bytes = total_bytes;
3195 total_bytes -= num_bytes;
306f1348 3196 if (!total_bytes) {
c165541e 3197 if (pflashcomp[i].optype == OPTYPE_PHY_FW)
306f1348
SP		 3198 flash_op = FLASHROM_OPER_PHY_FLASH;
3199 else
3200 flash_op = FLASHROM_OPER_FLASH;
3201 } else {
c165541e 3202 if (pflashcomp[i].optype == OPTYPE_PHY_FW)
306f1348
SP		 3203 flash_op = FLASHROM_OPER_PHY_SAVE;
3204 else
3205 flash_op = FLASHROM_OPER_SAVE;
3206 }
3f0d4560
AK		 3207 memcpy(req->params.data_buf, p, num_bytes);
3208 p += num_bytes;
3209 status = be_cmd_write_flashrom(adapter, flash_cmd,
3210 pflashcomp[i].optype, flash_op, num_bytes);
3211 if (status) {
306f1348
SP		 3212 if ((status == ILLEGAL_IOCTL_REQ) &&
3213 (pflashcomp[i].optype ==
c165541e 3214 OPTYPE_PHY_FW))
306f1348 3215 break;
3f0d4560
AK		 3216 dev_err(&adapter->pdev->dev,
3217 "cmd to write to flash rom failed.\n");
3218 return -1;
3219 }
84517482 3220 }
84517482 3221 }
84517482
AK		 3222 return 0;
3223}
3224
3f0d4560
AK		 3225static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
3226{
3227 if (fhdr == NULL)
3228 return 0;
3229 if (fhdr->build[0] == '3')
3230 return BE_GEN3;
3231 else if (fhdr->build[0] == '2')
3232 return BE_GEN2;
3233 else
3234 return 0;
3235}
3236
f67ef7ba
PR		 3237static int lancer_wait_idle(struct be_adapter *adapter)
3238{
3239#define SLIPORT_IDLE_TIMEOUT 30
3240 u32 reg_val;
3241 int status = 0, i;
3242
3243 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3244 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3245 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3246 break;
3247
3248 ssleep(1);
3249 }
3250
3251 if (i == SLIPORT_IDLE_TIMEOUT)
3252 status = -1;
3253
3254 return status;
3255}
3256
3257static int lancer_fw_reset(struct be_adapter *adapter)
3258{
3259 int status = 0;
3260
3261 status = lancer_wait_idle(adapter);
3262 if (status)
3263 return status;
3264
3265 iowrite32(PHYSDEV_CONTROL_FW_RESET_MASK, adapter->db +
3266 PHYSDEV_CONTROL_OFFSET);
3267
3268 return status;
3269}
3270
485bf569
SN		 3271static int lancer_fw_download(struct be_adapter *adapter,
3272 const struct firmware *fw)
84517482 3273{
485bf569
SN		 3274#define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024)
3275#define LANCER_FW_DOWNLOAD_LOCATION "/prg"
84517482 3276 struct be_dma_mem flash_cmd;
485bf569
SN		 3277 const u8 *data_ptr = NULL;
3278 u8 *dest_image_ptr = NULL;
3279 size_t image_size = 0;
3280 u32 chunk_size = 0;
3281 u32 data_written = 0;
3282 u32 offset = 0;
3283 int status = 0;
3284 u8 add_status = 0;
f67ef7ba 3285 u8 change_status;
84517482 3286
485bf569 3287 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
d9efd2af 3288 dev_err(&adapter->pdev->dev,
485bf569
SN		 3289 "FW Image not properly aligned. "
3290 "Length must be 4 byte aligned.\n");
3291 status = -EINVAL;
3292 goto lancer_fw_exit;
d9efd2af
SB		 3293 }
3294
485bf569
SN		 3295 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3296 + LANCER_FW_DOWNLOAD_CHUNK;
3297 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
3298 &flash_cmd.dma, GFP_KERNEL);
3299 if (!flash_cmd.va) {
3300 status = -ENOMEM;
3301 dev_err(&adapter->pdev->dev,
3302 "Memory allocation failure while flashing\n");
3303 goto lancer_fw_exit;
3304 }
84517482 3305
485bf569
SN		 3306 dest_image_ptr = flash_cmd.va +
3307 sizeof(struct lancer_cmd_req_write_object);
3308 image_size = fw->size;
3309 data_ptr = fw->data;
3310
3311 while (image_size) {
3312 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3313
3314 /* Copy the image chunk content. */
3315 memcpy(dest_image_ptr, data_ptr, chunk_size);
3316
3317 status = lancer_cmd_write_object(adapter, &flash_cmd,
f67ef7ba
PR		 3318 chunk_size, offset,
3319 LANCER_FW_DOWNLOAD_LOCATION,
3320 &data_written, &change_status,
3321 &add_status);
485bf569
SN		 3322 if (status)
3323 break;
3324
3325 offset += data_written;
3326 data_ptr += data_written;
3327 image_size -= data_written;
3328 }
3329
3330 if (!status) {
3331 /* Commit the FW written */
3332 status = lancer_cmd_write_object(adapter, &flash_cmd,
f67ef7ba
PR		 3333 0, offset,
3334 LANCER_FW_DOWNLOAD_LOCATION,
3335 &data_written, &change_status,
3336 &add_status);
485bf569
SN		 3337 }
3338
3339 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
3340 flash_cmd.dma);
3341 if (status) {
3342 dev_err(&adapter->pdev->dev,
3343 "Firmware load error. "
3344 "Status code: 0x%x Additional Status: 0x%x\n",
3345 status, add_status);
3346 goto lancer_fw_exit;
3347 }
3348
f67ef7ba
PR		 3349 if (change_status == LANCER_FW_RESET_NEEDED) {
3350 status = lancer_fw_reset(adapter);
3351 if (status) {
3352 dev_err(&adapter->pdev->dev,
3353 "Adapter busy for FW reset.\n"
3354 "New FW will not be active.\n");
3355 goto lancer_fw_exit;
3356 }
3357 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3358 dev_err(&adapter->pdev->dev,
3359 "System reboot required for new FW"
3360 " to be active\n");
3361 }
3362
485bf569
SN		 3363 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
3364lancer_fw_exit:
3365 return status;
3366}
3367
3368static int be_fw_download(struct be_adapter *adapter, const struct firmware* fw)
3369{
3370 struct flash_file_hdr_g2 *fhdr;
3371 struct flash_file_hdr_g3 *fhdr3;
3372 struct image_hdr *img_hdr_ptr = NULL;
3373 struct be_dma_mem flash_cmd;
3374 const u8 *p;
3375 int status = 0, i = 0, num_imgs = 0;
84517482
AK		 3376
3377 p = fw->data;
3f0d4560 3378 fhdr = (struct flash_file_hdr_g2 *) p;
84517482 3379
84517482 3380 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2b7bcebf
IV		 3381 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
3382 &flash_cmd.dma, GFP_KERNEL);
84517482
AK		 3383 if (!flash_cmd.va) {
3384 status = -ENOMEM;
3385 dev_err(&adapter->pdev->dev,
3386 "Memory allocation failure while flashing\n");
485bf569 3387 goto be_fw_exit;
84517482
AK		 3388 }
3389
3f0d4560
AK		 3390 if ((adapter->generation == BE_GEN3) &&
3391 (get_ufigen_type(fhdr) == BE_GEN3)) {
3392 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 3393 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3394 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 3395 img_hdr_ptr = (struct image_hdr *) (fw->data +
3396 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 3397 i * sizeof(struct image_hdr)));
3398 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
3399 status = be_flash_data(adapter, fw, &flash_cmd,
3400 num_imgs);
3f0d4560
AK		 3401 }
3402 } else if ((adapter->generation == BE_GEN2) &&
3403 (get_ufigen_type(fhdr) == BE_GEN2)) {
3404 status = be_flash_data(adapter, fw, &flash_cmd, 0);
3405 } else {
3406 dev_err(&adapter->pdev->dev,
3407 "UFI and Interface are not compatible for flashing\n");
3408 status = -1;
84517482
AK		 3409 }
3410
2b7bcebf
IV		 3411 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
3412 flash_cmd.dma);
84517482
AK		 3413 if (status) {
3414 dev_err(&adapter->pdev->dev, "Firmware load error\n");
485bf569 3415 goto be_fw_exit;
84517482
AK		 3416 }
3417
af901ca1 3418 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482 3419
485bf569
SN		 3420be_fw_exit:
3421 return status;
3422}
3423
3424int be_load_fw(struct be_adapter *adapter, u8 *fw_file)
3425{
3426 const struct firmware *fw;
3427 int status;
3428
3429 if (!netif_running(adapter->netdev)) {
3430 dev_err(&adapter->pdev->dev,
3431 "Firmware load not allowed (interface is down)\n");
3432 return -1;
3433 }
3434
3435 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
3436 if (status)
3437 goto fw_exit;
3438
3439 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
3440
3441 if (lancer_chip(adapter))
3442 status = lancer_fw_download(adapter, fw);
3443 else
3444 status = be_fw_download(adapter, fw);
3445
84517482
AK		 3446fw_exit:
3447 release_firmware(fw);
3448 return status;
3449}
3450
e5686ad8 3451static const struct net_device_ops be_netdev_ops = {
6b7c5b94
SP		 3452 .ndo_open = be_open,
3453 .ndo_stop = be_close,
3454 .ndo_start_xmit = be_xmit,
a54769f5 3455 .ndo_set_rx_mode = be_set_rx_mode,
6b7c5b94
SP		 3456 .ndo_set_mac_address = be_mac_addr_set,
3457 .ndo_change_mtu = be_change_mtu,
ab1594e9 3458 .ndo_get_stats64 = be_get_stats64,
6b7c5b94 3459 .ndo_validate_addr = eth_validate_addr,
6b7c5b94
SP		 3460 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
3461 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 3462 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 3463 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 3464 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
66268739
IV		 3465 .ndo_get_vf_config = be_get_vf_config,
3466#ifdef CONFIG_NET_POLL_CONTROLLER
3467 .ndo_poll_controller = be_netpoll,
3468#endif
6b7c5b94
SP		 3469};
3470
3471static void be_netdev_init(struct net_device *netdev)
3472{
3473 struct be_adapter *adapter = netdev_priv(netdev);
10ef9ab4 3474 struct be_eq_obj *eqo;
3abcdeda 3475 int i;
6b7c5b94 3476
6332c8d3 3477 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
8b8ddc68
MM		 3478 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
3479 NETIF_F_HW_VLAN_TX;
3480 if (be_multi_rxq(adapter))
3481 netdev->hw_features |= NETIF_F_RXHASH;
6332c8d3
MM		 3482
3483 netdev->features |= netdev->hw_features |
8b8ddc68 3484 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
4b972914 3485
eb8a50d9 3486 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
79032644 3487 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
51c59870 3488
fbc13f01
AK		 3489 netdev->priv_flags |= IFF_UNICAST_FLT;
3490
6b7c5b94
SP		 3491 netdev->flags |= IFF_MULTICAST;
3492
b7e5887e 3493 netif_set_gso_max_size(netdev, 65535 - ETH_HLEN);
c190e3c8 3494
10ef9ab4 3495 netdev->netdev_ops = &be_netdev_ops;
6b7c5b94
SP		 3496
3497 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
3498
10ef9ab4
SP		 3499 for_all_evt_queues(adapter, eqo, i)
3500 netif_napi_add(netdev, &eqo->napi, be_poll, BE_NAPI_WEIGHT);
6b7c5b94
SP		 3501}
3502
3503static void be_unmap_pci_bars(struct be_adapter *adapter)
3504{
8788fdc2
SP		 3505 if (adapter->csr)
3506 iounmap(adapter->csr);
3507 if (adapter->db)
3508 iounmap(adapter->db);
045508a8
PP		 3509 if (adapter->roce_db.base)
3510 pci_iounmap(adapter->pdev, adapter->roce_db.base);
3511}
3512
3513static int lancer_roce_map_pci_bars(struct be_adapter *adapter)
3514{
3515 struct pci_dev *pdev = adapter->pdev;
3516 u8 __iomem *addr;
3517
3518 addr = pci_iomap(pdev, 2, 0);
3519 if (addr == NULL)
3520 return -ENOMEM;
3521
3522 adapter->roce_db.base = addr;
3523 adapter->roce_db.io_addr = pci_resource_start(pdev, 2);
3524 adapter->roce_db.size = 8192;
3525 adapter->roce_db.total_size = pci_resource_len(pdev, 2);
3526 return 0;
6b7c5b94
SP		 3527}
3528
3529static int be_map_pci_bars(struct be_adapter *adapter)
3530{
3531 u8 __iomem *addr;
db3ea781 3532 int db_reg;
6b7c5b94 3533
fe6d2a38 3534 if (lancer_chip(adapter)) {
045508a8
PP		 3535 if (be_type_2_3(adapter)) {
3536 addr = ioremap_nocache(
3537 pci_resource_start(adapter->pdev, 0),
3538 pci_resource_len(adapter->pdev, 0));
3539 if (addr == NULL)
3540 return -ENOMEM;
3541 adapter->db = addr;
3542 }
3543 if (adapter->if_type == SLI_INTF_TYPE_3) {
3544 if (lancer_roce_map_pci_bars(adapter))
3545 goto pci_map_err;
3546 }
fe6d2a38
SP		 3547 return 0;
3548 }
3549
ba343c77
SB		 3550 if (be_physfn(adapter)) {
3551 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
3552 pci_resource_len(adapter->pdev, 2));
3553 if (addr == NULL)
3554 return -ENOMEM;
3555 adapter->csr = addr;
3556 }
6b7c5b94 3557
ba343c77 3558 if (adapter->generation == BE_GEN2) {
ba343c77
SB		 3559 db_reg = 4;
3560 } else {
ba343c77
SB		 3561 if (be_physfn(adapter))
3562 db_reg = 4;
3563 else
3564 db_reg = 0;
3565 }
3566 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
3567 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 3568 if (addr == NULL)
3569 goto pci_map_err;
ba343c77 3570 adapter->db = addr;
045508a8
PP		 3571 if (adapter->sli_family == SKYHAWK_SLI_FAMILY) {
3572 adapter->roce_db.size = 4096;
3573 adapter->roce_db.io_addr =
3574 pci_resource_start(adapter->pdev, db_reg);
3575 adapter->roce_db.total_size =
3576 pci_resource_len(adapter->pdev, db_reg);
3577 }
6b7c5b94
SP		 3578 return 0;
3579pci_map_err:
3580 be_unmap_pci_bars(adapter);
3581 return -ENOMEM;
3582}
3583
6b7c5b94
SP		 3584static void be_ctrl_cleanup(struct be_adapter *adapter)
3585{
8788fdc2 3586 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 3587
3588 be_unmap_pci_bars(adapter);
3589
3590 if (mem->va)
2b7bcebf
IV		 3591 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
3592 mem->dma);
e7b909a6 3593
5b8821b7 3594 mem = &adapter->rx_filter;
e7b909a6 3595 if (mem->va)
2b7bcebf
IV		 3596 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
3597 mem->dma);
6b7c5b94
SP		 3598}
3599
6b7c5b94
SP		 3600static int be_ctrl_init(struct be_adapter *adapter)
3601{
8788fdc2
SP		 3602 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
3603 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
5b8821b7 3604 struct be_dma_mem *rx_filter = &adapter->rx_filter;
6b7c5b94 3605 int status;
6b7c5b94
SP		 3606
3607 status = be_map_pci_bars(adapter);
3608 if (status)
e7b909a6 3609 goto done;
6b7c5b94
SP		 3610
3611 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2b7bcebf
IV		 3612 mbox_mem_alloc->va = dma_alloc_coherent(&adapter->pdev->dev,
3613 mbox_mem_alloc->size,
3614 &mbox_mem_alloc->dma,
3615 GFP_KERNEL);
6b7c5b94 3616 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 3617 status = -ENOMEM;
3618 goto unmap_pci_bars;
6b7c5b94
SP		 3619 }
3620 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
3621 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
3622 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
3623 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6 3624
5b8821b7
SP		 3625 rx_filter->size = sizeof(struct be_cmd_req_rx_filter);
3626 rx_filter->va = dma_alloc_coherent(&adapter->pdev->dev, rx_filter->size,
3627 &rx_filter->dma, GFP_KERNEL);
3628 if (rx_filter->va == NULL) {
e7b909a6
SP		 3629 status = -ENOMEM;
3630 goto free_mbox;
3631 }
5b8821b7 3632 memset(rx_filter->va, 0, rx_filter->size);
2984961c 3633 mutex_init(&adapter->mbox_lock);
8788fdc2
SP		 3634 spin_lock_init(&adapter->mcc_lock);
3635 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 3636
dd131e76 3637 init_completion(&adapter->flash_compl);
cf588477 3638 pci_save_state(adapter->pdev);
6b7c5b94 3639 return 0;
e7b909a6
SP		 3640
3641free_mbox:
2b7bcebf
IV		 3642 dma_free_coherent(&adapter->pdev->dev, mbox_mem_alloc->size,
3643 mbox_mem_alloc->va, mbox_mem_alloc->dma);
e7b909a6
SP		 3644
3645unmap_pci_bars:
3646 be_unmap_pci_bars(adapter);
3647
3648done:
3649 return status;
6b7c5b94
SP		 3650}
3651
3652static void be_stats_cleanup(struct be_adapter *adapter)
3653{
3abcdeda 3654 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 3655
3656 if (cmd->va)
2b7bcebf
IV		 3657 dma_free_coherent(&adapter->pdev->dev, cmd->size,
3658 cmd->va, cmd->dma);
6b7c5b94
SP		 3659}
3660
3661static int be_stats_init(struct be_adapter *adapter)
3662{
3abcdeda 3663 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94 3664
005d5696 3665 if (adapter->generation == BE_GEN2) {
89a88ab8 3666 cmd->size = sizeof(struct be_cmd_req_get_stats_v0);
005d5696
SX		 3667 } else {
3668 if (lancer_chip(adapter))
3669 cmd->size = sizeof(struct lancer_cmd_req_pport_stats);
3670 else
3671 cmd->size = sizeof(struct be_cmd_req_get_stats_v1);
3672 }
2b7bcebf
IV		 3673 cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma,
3674 GFP_KERNEL);
6b7c5b94
SP		 3675 if (cmd->va == NULL)
3676 return -1;
d291b9af 3677 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 3678 return 0;
3679}
3680
3681static void __devexit be_remove(struct pci_dev *pdev)
3682{
3683 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 3684
6b7c5b94
SP		 3685 if (!adapter)
3686 return;
3687
045508a8
PP		 3688 be_roce_dev_remove(adapter);
3689
f67ef7ba
PR		 3690 cancel_delayed_work_sync(&adapter->func_recovery_work);
3691
6b7c5b94
SP		 3692 unregister_netdev(adapter->netdev);
3693
5fb379ee
SP		 3694 be_clear(adapter);
3695
bf99e50d
PR		 3696 /* tell fw we're done with firing cmds */
3697 be_cmd_fw_clean(adapter);
3698
6b7c5b94
SP		 3699 be_stats_cleanup(adapter);
3700
3701 be_ctrl_cleanup(adapter);
3702
d6b6d987
SP		 3703 pci_disable_pcie_error_reporting(pdev);
3704
6b7c5b94
SP		 3705 pci_set_drvdata(pdev, NULL);
3706 pci_release_regions(pdev);
3707 pci_disable_device(pdev);
3708
3709 free_netdev(adapter->netdev);
3710}
3711
4762f6ce
AK		 3712bool be_is_wol_supported(struct be_adapter *adapter)
3713{
3714 return ((adapter->wol_cap & BE_WOL_CAP) &&
3715 !be_is_wol_excluded(adapter)) ? true : false;
3716}
3717
941a77d5
SK		 3718u32 be_get_fw_log_level(struct be_adapter *adapter)
3719{
3720 struct be_dma_mem extfat_cmd;
3721 struct be_fat_conf_params *cfgs;
3722 int status;
3723 u32 level = 0;
3724 int j;
3725
f25b119c
PR		 3726 if (lancer_chip(adapter))
3727 return 0;
3728
941a77d5
SK		 3729 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3730 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3731 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3732 &extfat_cmd.dma);
3733
3734 if (!extfat_cmd.va) {
3735 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3736 __func__);
3737 goto err;
3738 }
3739
3740 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3741 if (!status) {
3742 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3743 sizeof(struct be_cmd_resp_hdr));
ac46a462 3744 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
941a77d5
SK		 3745 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3746 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3747 }
3748 }
3749 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3750 extfat_cmd.dma);
3751err:
3752 return level;
3753}
abb93951 3754
39f1d94d 3755static int be_get_initial_config(struct be_adapter *adapter)
6b7c5b94 3756{
6b7c5b94 3757 int status;
941a77d5 3758 u32 level;
6b7c5b94 3759
9e1453c5
AK		 3760 status = be_cmd_get_cntl_attributes(adapter);
3761 if (status)
3762 return status;
3763
4762f6ce
AK		 3764 status = be_cmd_get_acpi_wol_cap(adapter);
3765 if (status) {
3766 /* in case of a failure to get wol capabillities
3767 * check the exclusion list to determine WOL capability */
3768 if (!be_is_wol_excluded(adapter))
3769 adapter->wol_cap |= BE_WOL_CAP;
3770 }
3771
3772 if (be_is_wol_supported(adapter))
3773 adapter->wol = true;
3774
7aeb2156
PR		 3775 /* Must be a power of 2 or else MODULO will BUG_ON */
3776 adapter->be_get_temp_freq = 64;
3777
941a77d5
SK		 3778 level = be_get_fw_log_level(adapter);
3779 adapter->msg_enable = level <= FW_LOG_LEVEL_DEFAULT ? NETIF_MSG_HW : 0;
3780
2243e2e9 3781 return 0;
6b7c5b94
SP		 3782}
3783
39f1d94d 3784static int be_dev_type_check(struct be_adapter *adapter)
fe6d2a38
SP		 3785{
3786 struct pci_dev *pdev = adapter->pdev;
3787 u32 sli_intf = 0, if_type;
3788
3789 switch (pdev->device) {
3790 case BE_DEVICE_ID1:
3791 case OC_DEVICE_ID1:
3792 adapter->generation = BE_GEN2;
3793 break;
3794 case BE_DEVICE_ID2:
3795 case OC_DEVICE_ID2:
3796 adapter->generation = BE_GEN3;
3797 break;
3798 case OC_DEVICE_ID3:
12f4d0a8 3799 case OC_DEVICE_ID4:
fe6d2a38 3800 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
045508a8
PP		 3801 adapter->if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
3802 SLI_INTF_IF_TYPE_SHIFT;
fe6d2a38
SP		 3803 if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
3804 SLI_INTF_IF_TYPE_SHIFT;
fe6d2a38 3805 if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
045508a8
PP		 3806 !be_type_2_3(adapter)) {
3807 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
3808 return -EINVAL;
3809 }
3810 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
3811 SLI_INTF_FAMILY_SHIFT);
3812 adapter->generation = BE_GEN3;
3813 break;
3814 case OC_DEVICE_ID5:
3815 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
3816 if ((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) {
fe6d2a38
SP		 3817 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
3818 return -EINVAL;
3819 }
fe6d2a38
SP		 3820 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
3821 SLI_INTF_FAMILY_SHIFT);
3822 adapter->generation = BE_GEN3;
3823 break;
3824 default:
3825 adapter->generation = 0;
3826 }
39f1d94d
SP		 3827
3828 pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, &sli_intf);
3829 adapter->virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0;
fe6d2a38
SP		 3830 return 0;
3831}
3832
f67ef7ba 3833static int lancer_recover_func(struct be_adapter *adapter)
d8110f62
PR		 3834{
3835 int status;
d8110f62 3836
f67ef7ba
PR		 3837 status = lancer_test_and_set_rdy_state(adapter);
3838 if (status)
3839 goto err;
d8110f62 3840
f67ef7ba
PR		 3841 if (netif_running(adapter->netdev))
3842 be_close(adapter->netdev);
d8110f62 3843
f67ef7ba
PR		 3844 be_clear(adapter);
3845
3846 adapter->hw_error = false;
3847 adapter->fw_timeout = false;
3848
3849 status = be_setup(adapter);
3850 if (status)
3851 goto err;
d8110f62 3852
f67ef7ba
PR		 3853 if (netif_running(adapter->netdev)) {
3854 status = be_open(adapter->netdev);
d8110f62
PR		 3855 if (status)
3856 goto err;
f67ef7ba 3857 }
d8110f62 3858
f67ef7ba
PR		 3859 dev_err(&adapter->pdev->dev,
3860 "Adapter SLIPORT recovery succeeded\n");
3861 return 0;
3862err:
67297ad8
PR		 3863 if (adapter->eeh_error)
3864 dev_err(&adapter->pdev->dev,
3865 "Adapter SLIPORT recovery failed\n");
d8110f62 3866
f67ef7ba
PR		 3867 return status;
3868}
3869
3870static void be_func_recovery_task(struct work_struct *work)
3871{
3872 struct be_adapter *adapter =
3873 container_of(work, struct be_adapter, func_recovery_work.work);
3874 int status;
d8110f62 3875
f67ef7ba 3876 be_detect_error(adapter);
d8110f62 3877
f67ef7ba 3878 if (adapter->hw_error && lancer_chip(adapter)) {
d8110f62 3879
f67ef7ba
PR		 3880 if (adapter->eeh_error)
3881 goto out;
d8110f62 3882
f67ef7ba
PR		 3883 rtnl_lock();
3884 netif_device_detach(adapter->netdev);
3885 rtnl_unlock();
d8110f62 3886
f67ef7ba 3887 status = lancer_recover_func(adapter);
d8110f62 3888
f67ef7ba
PR		 3889 if (!status)
3890 netif_device_attach(adapter->netdev);
d8110f62 3891 }
f67ef7ba
PR		 3892
3893out:
3894 schedule_delayed_work(&adapter->func_recovery_work,
3895 msecs_to_jiffies(1000));
d8110f62
PR		 3896}
3897
3898static void be_worker(struct work_struct *work)
3899{
3900 struct be_adapter *adapter =
3901 container_of(work, struct be_adapter, work.work);
3902 struct be_rx_obj *rxo;
10ef9ab4 3903 struct be_eq_obj *eqo;
d8110f62
PR		 3904 int i;
3905
d8110f62
PR		 3906 /* when interrupts are not yet enabled, just reap any pending
3907 * mcc completions */
3908 if (!netif_running(adapter->netdev)) {
072a9c48 3909 local_bh_disable();
10ef9ab4 3910 be_process_mcc(adapter);
072a9c48 3911 local_bh_enable();
d8110f62
PR		 3912 goto reschedule;
3913 }
3914
3915 if (!adapter->stats_cmd_sent) {
3916 if (lancer_chip(adapter))
3917 lancer_cmd_get_pport_stats(adapter,
3918 &adapter->stats_cmd);
3919 else
3920 be_cmd_get_stats(adapter, &adapter->stats_cmd);
3921 }
3922
7aeb2156
PR		 3923 if (MODULO(adapter->work_counter, adapter->be_get_temp_freq) == 0)
3924 be_cmd_get_die_temperature(adapter);
3925
d8110f62 3926 for_all_rx_queues(adapter, rxo, i) {
d8110f62
PR		 3927 if (rxo->rx_post_starved) {
3928 rxo->rx_post_starved = false;
3929 be_post_rx_frags(rxo, GFP_KERNEL);
3930 }
3931 }
3932
10ef9ab4
SP		 3933 for_all_evt_queues(adapter, eqo, i)
3934 be_eqd_update(adapter, eqo);
3935
d8110f62
PR		 3936reschedule:
3937 adapter->work_counter++;
3938 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
3939}
3940
39f1d94d
SP		 3941static bool be_reset_required(struct be_adapter *adapter)
3942{
d79c0a20 3943 return be_find_vfs(adapter, ENABLED) > 0 ? false : true;
39f1d94d
SP		 3944}
3945
d379142b
SP		 3946static char *mc_name(struct be_adapter *adapter)
3947{
3948 if (adapter->function_mode & FLEX10_MODE)
3949 return "FLEX10";
3950 else if (adapter->function_mode & VNIC_MODE)
3951 return "vNIC";
3952 else if (adapter->function_mode & UMC_ENABLED)
3953 return "UMC";
3954 else
3955 return "";
3956}
3957
3958static inline char *func_name(struct be_adapter *adapter)
3959{
3960 return be_physfn(adapter) ? "PF" : "VF";
3961}
3962
6b7c5b94
SP		 3963static int __devinit be_probe(struct pci_dev *pdev,
3964 const struct pci_device_id *pdev_id)
3965{
3966 int status = 0;
3967 struct be_adapter *adapter;
3968 struct net_device *netdev;
b4e32a71 3969 char port_name;
6b7c5b94
SP		 3970
3971 status = pci_enable_device(pdev);
3972 if (status)
3973 goto do_none;
3974
3975 status = pci_request_regions(pdev, DRV_NAME);
3976 if (status)
3977 goto disable_dev;
3978 pci_set_master(pdev);
3979
7f640062 3980 netdev = alloc_etherdev_mqs(sizeof(*adapter), MAX_TX_QS, MAX_RX_QS);
6b7c5b94
SP		 3981 if (netdev == NULL) {
3982 status = -ENOMEM;
3983 goto rel_reg;
3984 }
3985 adapter = netdev_priv(netdev);
3986 adapter->pdev = pdev;
3987 pci_set_drvdata(pdev, adapter);
fe6d2a38 3988
39f1d94d 3989 status = be_dev_type_check(adapter);
63657b9c 3990 if (status)
fe6d2a38
SP		 3991 goto free_netdev;
3992
6b7c5b94 3993 adapter->netdev = netdev;
2243e2e9 3994 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94 3995
2b7bcebf 3996 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6b7c5b94
SP		 3997 if (!status) {
3998 netdev->features |= NETIF_F_HIGHDMA;
3999 } else {
2b7bcebf 4000 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6b7c5b94
SP		 4001 if (status) {
4002 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
4003 goto free_netdev;
4004 }
4005 }
4006
d6b6d987
SP		 4007 status = pci_enable_pcie_error_reporting(pdev);
4008 if (status)
4009 dev_err(&pdev->dev, "Could not use PCIe error reporting\n");
4010
6b7c5b94
SP		 4011 status = be_ctrl_init(adapter);
4012 if (status)
39f1d94d 4013 goto free_netdev;
6b7c5b94 4014
2243e2e9 4015 /* sync up with fw's ready state */
ba343c77 4016 if (be_physfn(adapter)) {
bf99e50d 4017 status = be_fw_wait_ready(adapter);
ba343c77
SB		 4018 if (status)
4019 goto ctrl_clean;
ba343c77 4020 }
6b7c5b94 4021
2243e2e9
SP		 4022 /* tell fw we're ready to fire cmds */
4023 status = be_cmd_fw_init(adapter);
6b7c5b94 4024 if (status)
2243e2e9
SP		 4025 goto ctrl_clean;
4026
39f1d94d
SP		 4027 if (be_reset_required(adapter)) {
4028 status = be_cmd_reset_function(adapter);
4029 if (status)
4030 goto ctrl_clean;
4031 }
556ae191 4032
10ef9ab4
SP		 4033 /* The INTR bit may be set in the card when probed by a kdump kernel
4034 * after a crash.
4035 */
4036 if (!lancer_chip(adapter))
4037 be_intr_set(adapter, false);
4038
2243e2e9
SP		 4039 status = be_stats_init(adapter);
4040 if (status)
4041 goto ctrl_clean;
4042
39f1d94d 4043 status = be_get_initial_config(adapter);
6b7c5b94
SP		 4044 if (status)
4045 goto stats_clean;
6b7c5b94
SP		 4046
4047 INIT_DELAYED_WORK(&adapter->work, be_worker);
f67ef7ba 4048 INIT_DELAYED_WORK(&adapter->func_recovery_work, be_func_recovery_task);
a54769f5 4049 adapter->rx_fc = adapter->tx_fc = true;
6b7c5b94 4050
5fb379ee
SP		 4051 status = be_setup(adapter);
4052 if (status)
55f5c3c5 4053 goto stats_clean;
2243e2e9 4054
3abcdeda 4055 be_netdev_init(netdev);
6b7c5b94
SP		 4056 status = register_netdev(netdev);
4057 if (status != 0)
5fb379ee 4058 goto unsetup;
6b7c5b94 4059
045508a8
PP		 4060 be_roce_dev_add(adapter);
4061
f67ef7ba
PR		 4062 schedule_delayed_work(&adapter->func_recovery_work,
4063 msecs_to_jiffies(1000));
b4e32a71
PR		 4064
4065 be_cmd_query_port_name(adapter, &port_name);
4066
d379142b
SP		 4067 dev_info(&pdev->dev, "%s: %s %s port %c\n", nic_name(pdev),
4068 func_name(adapter), mc_name(adapter), port_name);
34b1ef04 4069
6b7c5b94
SP		 4070 return 0;
4071
5fb379ee
SP		 4072unsetup:
4073 be_clear(adapter);
6b7c5b94
SP		 4074stats_clean:
4075 be_stats_cleanup(adapter);
4076ctrl_clean:
4077 be_ctrl_cleanup(adapter);
f9449ab7 4078free_netdev:
fe6d2a38 4079 free_netdev(netdev);
8d56ff11 4080 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 4081rel_reg:
4082 pci_release_regions(pdev);
4083disable_dev:
4084 pci_disable_device(pdev);
4085do_none:
c4ca2374 4086 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 4087 return status;
4088}
4089
4090static int be_suspend(struct pci_dev *pdev, pm_message_t state)
4091{
4092 struct be_adapter *adapter = pci_get_drvdata(pdev);
4093 struct net_device *netdev = adapter->netdev;
4094
71d8d1b5
AK		 4095 if (adapter->wol)
4096 be_setup_wol(adapter, true);
4097
f67ef7ba
PR		 4098 cancel_delayed_work_sync(&adapter->func_recovery_work);
4099
6b7c5b94
SP		 4100 netif_device_detach(netdev);
4101 if (netif_running(netdev)) {
4102 rtnl_lock();
4103 be_close(netdev);
4104 rtnl_unlock();
4105 }
9b0365f1 4106 be_clear(adapter);
6b7c5b94
SP		 4107
4108 pci_save_state(pdev);
4109 pci_disable_device(pdev);
4110 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4111 return 0;
4112}
4113
4114static int be_resume(struct pci_dev *pdev)
4115{
4116 int status = 0;
4117 struct be_adapter *adapter = pci_get_drvdata(pdev);
4118 struct net_device *netdev = adapter->netdev;
4119
4120 netif_device_detach(netdev);
4121
4122 status = pci_enable_device(pdev);
4123 if (status)
4124 return status;
4125
4126 pci_set_power_state(pdev, 0);
4127 pci_restore_state(pdev);
4128
2243e2e9
SP		 4129 /* tell fw we're ready to fire cmds */
4130 status = be_cmd_fw_init(adapter);
4131 if (status)
4132 return status;
4133
9b0365f1 4134 be_setup(adapter);
6b7c5b94
SP		 4135 if (netif_running(netdev)) {
4136 rtnl_lock();
4137 be_open(netdev);
4138 rtnl_unlock();
4139 }
f67ef7ba
PR		 4140
4141 schedule_delayed_work(&adapter->func_recovery_work,
4142 msecs_to_jiffies(1000));
6b7c5b94 4143 netif_device_attach(netdev);
71d8d1b5
AK		 4144
4145 if (adapter->wol)
4146 be_setup_wol(adapter, false);
a4ca055f 4147
6b7c5b94
SP		 4148 return 0;
4149}
4150
82456b03
SP		 4151/*
4152 * An FLR will stop BE from DMAing any data.
4153 */
4154static void be_shutdown(struct pci_dev *pdev)
4155{
4156 struct be_adapter *adapter = pci_get_drvdata(pdev);
82456b03 4157
2d5d4154
AK		 4158 if (!adapter)
4159 return;
82456b03 4160
0f4a6828 4161 cancel_delayed_work_sync(&adapter->work);
f67ef7ba 4162 cancel_delayed_work_sync(&adapter->func_recovery_work);
a4ca055f 4163
2d5d4154 4164 netif_device_detach(adapter->netdev);
82456b03 4165
82456b03
SP		 4166 if (adapter->wol)
4167 be_setup_wol(adapter, true);
4168
57841869
AK		 4169 be_cmd_reset_function(adapter);
4170
82456b03 4171 pci_disable_device(pdev);
82456b03
SP		 4172}
4173
cf588477
SP		 4174static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
4175 pci_channel_state_t state)
4176{
4177 struct be_adapter *adapter = pci_get_drvdata(pdev);
4178 struct net_device *netdev = adapter->netdev;
4179
4180 dev_err(&adapter->pdev->dev, "EEH error detected\n");
4181
f67ef7ba
PR		 4182 adapter->eeh_error = true;
4183
4184 cancel_delayed_work_sync(&adapter->func_recovery_work);
cf588477 4185
f67ef7ba 4186 rtnl_lock();
cf588477 4187 netif_device_detach(netdev);
f67ef7ba 4188 rtnl_unlock();
cf588477
SP		 4189
4190 if (netif_running(netdev)) {
4191 rtnl_lock();
4192 be_close(netdev);
4193 rtnl_unlock();
4194 }
4195 be_clear(adapter);
4196
4197 if (state == pci_channel_io_perm_failure)
4198 return PCI_ERS_RESULT_DISCONNECT;
4199
4200 pci_disable_device(pdev);
4201
eeb7fc7b
SK		 4202 /* The error could cause the FW to trigger a flash debug dump.
4203 * Resetting the card while flash dump is in progress
c8a54163
PR		 4204 * can cause it not to recover; wait for it to finish.
4205 * Wait only for first function as it is needed only once per
4206 * adapter.
eeb7fc7b 4207 */
c8a54163
PR		 4208 if (pdev->devfn == 0)
4209 ssleep(30);
4210
cf588477
SP		 4211 return PCI_ERS_RESULT_NEED_RESET;
4212}
4213
4214static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
4215{
4216 struct be_adapter *adapter = pci_get_drvdata(pdev);
4217 int status;
4218
4219 dev_info(&adapter->pdev->dev, "EEH reset\n");
f67ef7ba 4220 be_clear_all_error(adapter);
cf588477
SP		 4221
4222 status = pci_enable_device(pdev);
4223 if (status)
4224 return PCI_ERS_RESULT_DISCONNECT;
4225
4226 pci_set_master(pdev);
4227 pci_set_power_state(pdev, 0);
4228 pci_restore_state(pdev);
4229
4230 /* Check if card is ok and fw is ready */
bf99e50d 4231 status = be_fw_wait_ready(adapter);
cf588477
SP		 4232 if (status)
4233 return PCI_ERS_RESULT_DISCONNECT;
4234
d6b6d987 4235 pci_cleanup_aer_uncorrect_error_status(pdev);
cf588477
SP		 4236 return PCI_ERS_RESULT_RECOVERED;
4237}
4238
4239static void be_eeh_resume(struct pci_dev *pdev)
4240{
4241 int status = 0;
4242 struct be_adapter *adapter = pci_get_drvdata(pdev);
4243 struct net_device *netdev = adapter->netdev;
4244
4245 dev_info(&adapter->pdev->dev, "EEH resume\n");
4246
4247 pci_save_state(pdev);
4248
4249 /* tell fw we're ready to fire cmds */
4250 status = be_cmd_fw_init(adapter);
4251 if (status)
4252 goto err;
4253
bf99e50d
PR		 4254 status = be_cmd_reset_function(adapter);
4255 if (status)
4256 goto err;
4257
cf588477
SP		 4258 status = be_setup(adapter);
4259 if (status)
4260 goto err;
4261
4262 if (netif_running(netdev)) {
4263 status = be_open(netdev);
4264 if (status)
4265 goto err;
4266 }
f67ef7ba
PR		 4267
4268 schedule_delayed_work(&adapter->func_recovery_work,
4269 msecs_to_jiffies(1000));
cf588477
SP		 4270 netif_device_attach(netdev);
4271 return;
4272err:
4273 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 4274}
4275
3646f0e5 4276static const struct pci_error_handlers be_eeh_handlers = {
cf588477
SP		 4277 .error_detected = be_eeh_err_detected,
4278 .slot_reset = be_eeh_reset,
4279 .resume = be_eeh_resume,
4280};
4281
6b7c5b94
SP		 4282static struct pci_driver be_driver = {
4283 .name = DRV_NAME,
4284 .id_table = be_dev_ids,
4285 .probe = be_probe,
4286 .remove = be_remove,
4287 .suspend = be_suspend,
cf588477 4288 .resume = be_resume,
82456b03 4289 .shutdown = be_shutdown,
cf588477 4290 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 4291};
4292
4293static int __init be_init_module(void)
4294{
8e95a202
JP		 4295 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
4296 rx_frag_size != 2048) {
6b7c5b94
SP		 4297 printk(KERN_WARNING DRV_NAME
4298 " : Module param rx_frag_size must be 2048/4096/8192."
4299 " Using 2048\n");
4300 rx_frag_size = 2048;
4301 }
6b7c5b94
SP		 4302
4303 return pci_register_driver(&be_driver);
4304}
4305module_init(be_init_module);
4306
4307static void __exit be_exit_module(void)
4308{
4309 pci_unregister_driver(&be_driver);
4310}
4311module_exit(be_exit_module);
Linux kernel - Deliverables
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