Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
1da177e4 LT |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
4c09eed9 JB |
37 | #include <linux/in.h> |
38 | #include <linux/ip.h> | |
39 | #include <net/ip.h> | |
40 | #include <linux/tcp.h> | |
41 | #include <linux/udp.h> | |
42 | #include <linux/icmp.h> | |
1da177e4 LT |
43 | #include <linux/spinlock.h> |
44 | #include <linux/workqueue.h> | |
45 | #include <linux/bitops.h> | |
6f501b17 SH |
46 | #include <linux/io.h> |
47 | #include <linux/irq.h> | |
196719ec | 48 | #include <linux/clk.h> |
ead73183 | 49 | #include <linux/platform_device.h> |
e6b043d5 | 50 | #include <linux/phy.h> |
5eb32bd0 | 51 | #include <linux/fec.h> |
ca2cc333 SG |
52 | #include <linux/of.h> |
53 | #include <linux/of_device.h> | |
54 | #include <linux/of_gpio.h> | |
55 | #include <linux/of_net.h> | |
5fa9c0fe | 56 | #include <linux/regulator/consumer.h> |
1da177e4 | 57 | |
080853af | 58 | #include <asm/cacheflush.h> |
196719ec | 59 | |
1da177e4 | 60 | #include "fec.h" |
1da177e4 | 61 | |
085e79ed | 62 | #if defined(CONFIG_ARM) |
196719ec SH |
63 | #define FEC_ALIGNMENT 0xf |
64 | #else | |
65 | #define FEC_ALIGNMENT 0x3 | |
66 | #endif | |
67 | ||
b5680e0b | 68 | #define DRIVER_NAME "fec" |
dc975382 | 69 | #define FEC_NAPI_WEIGHT 64 |
b5680e0b | 70 | |
baa70a5c FL |
71 | /* Pause frame feild and FIFO threshold */ |
72 | #define FEC_ENET_FCE (1 << 5) | |
73 | #define FEC_ENET_RSEM_V 0x84 | |
74 | #define FEC_ENET_RSFL_V 16 | |
75 | #define FEC_ENET_RAEM_V 0x8 | |
76 | #define FEC_ENET_RAFL_V 0x8 | |
77 | #define FEC_ENET_OPD_V 0xFFF0 | |
78 | ||
b5680e0b SG |
79 | /* Controller is ENET-MAC */ |
80 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
81 | /* Controller needs driver to swap frame */ | |
82 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
83 | /* Controller uses gasket */ |
84 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
85 | /* Controller has GBIT support */ |
86 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
87 | /* Controller has extend desc buffer */ |
88 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
48496255 SG |
89 | /* Controller has hardware checksum support */ |
90 | #define FEC_QUIRK_HAS_CSUM (1 << 5) | |
b5680e0b SG |
91 | |
92 | static struct platform_device_id fec_devtype[] = { | |
93 | { | |
0ca1e290 | 94 | /* keep it for coldfire */ |
b5680e0b SG |
95 | .name = DRIVER_NAME, |
96 | .driver_data = 0, | |
0ca1e290 SG |
97 | }, { |
98 | .name = "imx25-fec", | |
99 | .driver_data = FEC_QUIRK_USE_GASKET, | |
100 | }, { | |
101 | .name = "imx27-fec", | |
102 | .driver_data = 0, | |
b5680e0b SG |
103 | }, { |
104 | .name = "imx28-fec", | |
105 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
106 | }, { |
107 | .name = "imx6q-fec", | |
ff43da86 | 108 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
48496255 | 109 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM, |
ca7c4a45 | 110 | }, { |
36803542 | 111 | .name = "mvf600-fec", |
ca7c4a45 | 112 | .driver_data = FEC_QUIRK_ENET_MAC, |
0ca1e290 SG |
113 | }, { |
114 | /* sentinel */ | |
115 | } | |
b5680e0b | 116 | }; |
0ca1e290 | 117 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 118 | |
ca2cc333 | 119 | enum imx_fec_type { |
a7dd3219 | 120 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
121 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
122 | IMX28_FEC, | |
230dec61 | 123 | IMX6Q_FEC, |
36803542 | 124 | MVF600_FEC, |
ca2cc333 SG |
125 | }; |
126 | ||
127 | static const struct of_device_id fec_dt_ids[] = { | |
128 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
129 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
130 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 131 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 132 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ca2cc333 SG |
133 | { /* sentinel */ } |
134 | }; | |
135 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
136 | ||
49da97dc SG |
137 | static unsigned char macaddr[ETH_ALEN]; |
138 | module_param_array(macaddr, byte, NULL, 0); | |
139 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 140 | |
49da97dc | 141 | #if defined(CONFIG_M5272) |
1da177e4 LT |
142 | /* |
143 | * Some hardware gets it MAC address out of local flash memory. | |
144 | * if this is non-zero then assume it is the address to get MAC from. | |
145 | */ | |
146 | #if defined(CONFIG_NETtel) | |
147 | #define FEC_FLASHMAC 0xf0006006 | |
148 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
149 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
150 | #elif defined(CONFIG_CANCam) |
151 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
152 | #elif defined (CONFIG_M5272C3) |
153 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
154 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 155 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
156 | #else |
157 | #define FEC_FLASHMAC 0 | |
158 | #endif | |
43be6366 | 159 | #endif /* CONFIG_M5272 */ |
ead73183 | 160 | |
ff43da86 | 161 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 162 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
163 | #endif |
164 | ||
22f6b860 | 165 | /* Interrupt events/masks. */ |
1da177e4 LT |
166 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
167 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
168 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
169 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
170 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
171 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
172 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
173 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
174 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
175 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
176 | ||
4bee1f9a | 177 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 178 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 179 | |
1da177e4 LT |
180 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
181 | */ | |
182 | #define PKT_MAXBUF_SIZE 1518 | |
183 | #define PKT_MINBUF_SIZE 64 | |
184 | #define PKT_MAXBLR_SIZE 1520 | |
185 | ||
4c09eed9 JB |
186 | /* FEC receive acceleration */ |
187 | #define FEC_RACC_IPDIS (1 << 1) | |
188 | #define FEC_RACC_PRODIS (1 << 2) | |
189 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | |
190 | ||
1da177e4 | 191 | /* |
6b265293 | 192 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
193 | * size bits. Other FEC hardware does not, so we need to take that into |
194 | * account when setting it. | |
195 | */ | |
562d2f8c | 196 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 197 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
198 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
199 | #else | |
200 | #define OPT_FRAME_SIZE 0 | |
201 | #endif | |
202 | ||
e6b043d5 BW |
203 | /* FEC MII MMFR bits definition */ |
204 | #define FEC_MMFR_ST (1 << 30) | |
205 | #define FEC_MMFR_OP_READ (2 << 28) | |
206 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
207 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
208 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
209 | #define FEC_MMFR_TA (2 << 16) | |
210 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 211 | |
c3b084c2 | 212 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 213 | |
22f6b860 SH |
214 | /* Transmitter timeout */ |
215 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 216 | |
baa70a5c FL |
217 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
218 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
219 | ||
e163cc97 LW |
220 | static int mii_cnt; |
221 | ||
ff43da86 FL |
222 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
223 | { | |
224 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
225 | if (is_ex) | |
226 | return (struct bufdesc *)(ex + 1); | |
227 | else | |
228 | return bdp + 1; | |
229 | } | |
230 | ||
231 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
232 | { | |
233 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
234 | if (is_ex) | |
235 | return (struct bufdesc *)(ex - 1); | |
236 | else | |
237 | return bdp - 1; | |
238 | } | |
239 | ||
b5680e0b SG |
240 | static void *swap_buffer(void *bufaddr, int len) |
241 | { | |
242 | int i; | |
243 | unsigned int *buf = bufaddr; | |
244 | ||
ffed61e6 | 245 | for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) |
b5680e0b SG |
246 | *buf = cpu_to_be32(*buf); |
247 | ||
248 | return bufaddr; | |
249 | } | |
250 | ||
4c09eed9 JB |
251 | static int |
252 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
253 | { | |
254 | /* Only run for packets requiring a checksum. */ | |
255 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
256 | return 0; | |
257 | ||
258 | if (unlikely(skb_cow_head(skb, 0))) | |
259 | return -1; | |
260 | ||
261 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
c7621cb3 | 266 | static netdev_tx_t |
c556167f | 267 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 268 | { |
c556167f | 269 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
270 | const struct platform_device_id *id_entry = |
271 | platform_get_device_id(fep->pdev); | |
2e28532f | 272 | struct bufdesc *bdp; |
9555b31e | 273 | void *bufaddr; |
0e702ab3 | 274 | unsigned short status; |
de5fb0a0 | 275 | unsigned int index; |
1da177e4 | 276 | |
1da177e4 | 277 | if (!fep->link) { |
4c09eed9 | 278 | /* Link is down or auto-negotiation is in progress. */ |
5b548140 | 279 | return NETDEV_TX_BUSY; |
1da177e4 LT |
280 | } |
281 | ||
282 | /* Fill in a Tx ring entry */ | |
283 | bdp = fep->cur_tx; | |
284 | ||
0e702ab3 | 285 | status = bdp->cbd_sc; |
22f6b860 | 286 | |
0e702ab3 | 287 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 288 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 289 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 290 | */ |
31b7720c | 291 | netdev_err(ndev, "tx queue full!\n"); |
5b548140 | 292 | return NETDEV_TX_BUSY; |
1da177e4 | 293 | } |
1da177e4 | 294 | |
4c09eed9 JB |
295 | /* Protocol checksum off-load for TCP and UDP. */ |
296 | if (fec_enet_clear_csum(skb, ndev)) { | |
297 | kfree_skb(skb); | |
298 | return NETDEV_TX_OK; | |
299 | } | |
300 | ||
22f6b860 | 301 | /* Clear all of the status flags */ |
0e702ab3 | 302 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 303 | |
22f6b860 | 304 | /* Set buffer length and buffer pointer */ |
9555b31e | 305 | bufaddr = skb->data; |
1da177e4 LT |
306 | bdp->cbd_datlen = skb->len; |
307 | ||
308 | /* | |
22f6b860 SH |
309 | * On some FEC implementations data must be aligned on |
310 | * 4-byte boundaries. Use bounce buffers to copy data | |
311 | * and get it aligned. Ugh. | |
1da177e4 | 312 | */ |
de5fb0a0 FL |
313 | if (fep->bufdesc_ex) |
314 | index = (struct bufdesc_ex *)bdp - | |
315 | (struct bufdesc_ex *)fep->tx_bd_base; | |
316 | else | |
317 | index = bdp - fep->tx_bd_base; | |
318 | ||
9555b31e | 319 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 320 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 321 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
322 | } |
323 | ||
b5680e0b SG |
324 | /* |
325 | * Some design made an incorrect assumption on endian mode of | |
326 | * the system that it's running on. As the result, driver has to | |
327 | * swap every frame going to and coming from the controller. | |
328 | */ | |
329 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
330 | swap_buffer(bufaddr, skb->len); | |
331 | ||
22f6b860 | 332 | /* Save skb pointer */ |
de5fb0a0 | 333 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 334 | |
1da177e4 LT |
335 | /* Push the data cache so the CPM does not get stale memory |
336 | * data. | |
337 | */ | |
d1ab1f54 | 338 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 339 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 340 | |
0e702ab3 GU |
341 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
342 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 343 | */ |
0e702ab3 | 344 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 345 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 346 | bdp->cbd_sc = status; |
1da177e4 | 347 | |
ff43da86 FL |
348 | if (fep->bufdesc_ex) { |
349 | ||
350 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
351 | ebdp->cbd_bdu = 0; | |
352 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 353 | fep->hwts_tx_en)) { |
ff43da86 | 354 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 355 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 356 | } else { |
ff43da86 | 357 | ebdp->cbd_esc = BD_ENET_TX_INT; |
4c09eed9 JB |
358 | |
359 | /* Enable protocol checksum flags | |
360 | * We do not bother with the IP Checksum bits as they | |
361 | * are done by the kernel | |
362 | */ | |
363 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
364 | ebdp->cbd_esc |= BD_ENET_TX_PINS; | |
ff43da86 | 365 | } |
6605b730 | 366 | } |
22f6b860 SH |
367 | /* If this was the last BD in the ring, start at the beginning again. */ |
368 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 369 | bdp = fep->tx_bd_base; |
22f6b860 | 370 | else |
ff43da86 | 371 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 372 | |
de5fb0a0 FL |
373 | fep->cur_tx = bdp; |
374 | ||
375 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 376 | netif_stop_queue(ndev); |
1da177e4 | 377 | |
de5fb0a0 FL |
378 | /* Trigger transmission start */ |
379 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 380 | |
18a03b97 RC |
381 | skb_tx_timestamp(skb); |
382 | ||
6ed10654 | 383 | return NETDEV_TX_OK; |
1da177e4 LT |
384 | } |
385 | ||
14109a59 FL |
386 | /* Init RX & TX buffer descriptors |
387 | */ | |
388 | static void fec_enet_bd_init(struct net_device *dev) | |
389 | { | |
390 | struct fec_enet_private *fep = netdev_priv(dev); | |
391 | struct bufdesc *bdp; | |
392 | unsigned int i; | |
393 | ||
394 | /* Initialize the receive buffer descriptors. */ | |
395 | bdp = fep->rx_bd_base; | |
396 | for (i = 0; i < RX_RING_SIZE; i++) { | |
397 | ||
398 | /* Initialize the BD for every fragment in the page. */ | |
399 | if (bdp->cbd_bufaddr) | |
400 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
401 | else | |
402 | bdp->cbd_sc = 0; | |
403 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
404 | } | |
405 | ||
406 | /* Set the last buffer to wrap */ | |
407 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
408 | bdp->cbd_sc |= BD_SC_WRAP; | |
409 | ||
410 | fep->cur_rx = fep->rx_bd_base; | |
411 | ||
412 | /* ...and the same for transmit */ | |
413 | bdp = fep->tx_bd_base; | |
414 | fep->cur_tx = bdp; | |
415 | for (i = 0; i < TX_RING_SIZE; i++) { | |
416 | ||
417 | /* Initialize the BD for every fragment in the page. */ | |
418 | bdp->cbd_sc = 0; | |
419 | if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { | |
420 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
421 | fep->tx_skbuff[i] = NULL; | |
422 | } | |
423 | bdp->cbd_bufaddr = 0; | |
424 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
425 | } | |
426 | ||
427 | /* Set the last buffer to wrap */ | |
428 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
429 | bdp->cbd_sc |= BD_SC_WRAP; | |
430 | fep->dirty_tx = bdp; | |
431 | } | |
432 | ||
45993653 UKK |
433 | /* This function is called to start or restart the FEC during a link |
434 | * change. This only happens when switching between half and full | |
435 | * duplex. | |
436 | */ | |
1da177e4 | 437 | static void |
45993653 | 438 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 439 | { |
c556167f | 440 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
441 | const struct platform_device_id *id_entry = |
442 | platform_get_device_id(fep->pdev); | |
443 | int i; | |
4c09eed9 | 444 | u32 val; |
cd1f402c UKK |
445 | u32 temp_mac[2]; |
446 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 447 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 448 | |
54309fa6 FL |
449 | if (netif_running(ndev)) { |
450 | netif_device_detach(ndev); | |
451 | napi_disable(&fep->napi); | |
452 | netif_stop_queue(ndev); | |
31691344 | 453 | netif_tx_lock_bh(ndev); |
54309fa6 FL |
454 | } |
455 | ||
45993653 UKK |
456 | /* Whack a reset. We should wait for this. */ |
457 | writel(1, fep->hwp + FEC_ECNTRL); | |
458 | udelay(10); | |
1da177e4 | 459 | |
45993653 UKK |
460 | /* |
461 | * enet-mac reset will reset mac address registers too, | |
462 | * so need to reconfigure it. | |
463 | */ | |
464 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
465 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
466 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
467 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
468 | } | |
1da177e4 | 469 | |
45993653 UKK |
470 | /* Clear any outstanding interrupt. */ |
471 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 472 | |
45993653 UKK |
473 | /* Reset all multicast. */ |
474 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
475 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
476 | #ifndef CONFIG_M5272 | |
477 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
478 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
479 | #endif | |
1da177e4 | 480 | |
45993653 UKK |
481 | /* Set maximum receive buffer size. */ |
482 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 483 | |
14109a59 FL |
484 | fec_enet_bd_init(ndev); |
485 | ||
45993653 UKK |
486 | /* Set receive and transmit descriptor base. */ |
487 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
488 | if (fep->bufdesc_ex) |
489 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
490 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
491 | else | |
492 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
493 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 494 | |
45993653 | 495 | |
45993653 UKK |
496 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
497 | if (fep->tx_skbuff[i]) { | |
498 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
499 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 500 | } |
45993653 | 501 | } |
97b72e43 | 502 | |
45993653 UKK |
503 | /* Enable MII mode */ |
504 | if (duplex) { | |
cd1f402c | 505 | /* FD enable */ |
45993653 UKK |
506 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
507 | } else { | |
cd1f402c UKK |
508 | /* No Rcv on Xmit */ |
509 | rcntl |= 0x02; | |
45993653 UKK |
510 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
511 | } | |
cd1f402c | 512 | |
45993653 UKK |
513 | fep->full_duplex = duplex; |
514 | ||
515 | /* Set MII speed */ | |
516 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
517 | ||
4c09eed9 JB |
518 | /* set RX checksum */ |
519 | val = readl(fep->hwp + FEC_RACC); | |
520 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | |
521 | val |= FEC_RACC_OPTIONS; | |
522 | else | |
523 | val &= ~FEC_RACC_OPTIONS; | |
524 | writel(val, fep->hwp + FEC_RACC); | |
525 | ||
45993653 UKK |
526 | /* |
527 | * The phy interface and speed need to get configured | |
528 | * differently on enet-mac. | |
529 | */ | |
530 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
531 | /* Enable flow control and length check */ |
532 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 533 | |
230dec61 SG |
534 | /* RGMII, RMII or MII */ |
535 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
536 | rcntl |= (1 << 6); | |
537 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 538 | rcntl |= (1 << 8); |
45993653 | 539 | else |
cd1f402c | 540 | rcntl &= ~(1 << 8); |
45993653 | 541 | |
230dec61 SG |
542 | /* 1G, 100M or 10M */ |
543 | if (fep->phy_dev) { | |
544 | if (fep->phy_dev->speed == SPEED_1000) | |
545 | ecntl |= (1 << 5); | |
546 | else if (fep->phy_dev->speed == SPEED_100) | |
547 | rcntl &= ~(1 << 9); | |
548 | else | |
549 | rcntl |= (1 << 9); | |
550 | } | |
45993653 UKK |
551 | } else { |
552 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 553 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 554 | u32 cfgr; |
45993653 UKK |
555 | /* disable the gasket and wait */ |
556 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
557 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
558 | udelay(1); | |
559 | ||
560 | /* | |
561 | * configure the gasket: | |
562 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 563 | * MII, 25 MHz, no loopback, no echo |
45993653 | 564 | */ |
8d82f219 EB |
565 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
566 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
567 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
568 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
569 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
570 | |
571 | /* re-enable the gasket */ | |
572 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 573 | } |
45993653 UKK |
574 | #endif |
575 | } | |
baa70a5c FL |
576 | |
577 | /* enable pause frame*/ | |
578 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
579 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
580 | fep->phy_dev && fep->phy_dev->pause)) { | |
581 | rcntl |= FEC_ENET_FCE; | |
582 | ||
4c09eed9 | 583 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
584 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
585 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
586 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
587 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
588 | ||
589 | /* OPD */ | |
590 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
591 | } else { | |
592 | rcntl &= ~FEC_ENET_FCE; | |
593 | } | |
594 | ||
cd1f402c | 595 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 596 | |
230dec61 SG |
597 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
598 | /* enable ENET endian swap */ | |
599 | ecntl |= (1 << 8); | |
600 | /* enable ENET store and forward mode */ | |
601 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
602 | } | |
603 | ||
ff43da86 FL |
604 | if (fep->bufdesc_ex) |
605 | ecntl |= (1 << 4); | |
6605b730 | 606 | |
45993653 | 607 | /* And last, enable the transmit and receive processing */ |
230dec61 | 608 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
609 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
610 | ||
ff43da86 FL |
611 | if (fep->bufdesc_ex) |
612 | fec_ptp_start_cyclecounter(ndev); | |
613 | ||
45993653 UKK |
614 | /* Enable interrupts we wish to service */ |
615 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
54309fa6 FL |
616 | |
617 | if (netif_running(ndev)) { | |
31691344 | 618 | netif_tx_unlock_bh(ndev); |
54309fa6 | 619 | netif_wake_queue(ndev); |
1ed0d56c FE |
620 | napi_enable(&fep->napi); |
621 | netif_device_attach(ndev); | |
54309fa6 | 622 | } |
45993653 UKK |
623 | } |
624 | ||
625 | static void | |
626 | fec_stop(struct net_device *ndev) | |
627 | { | |
628 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
629 | const struct platform_device_id *id_entry = |
630 | platform_get_device_id(fep->pdev); | |
42431dc2 | 631 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
632 | |
633 | /* We cannot expect a graceful transmit stop without link !!! */ | |
634 | if (fep->link) { | |
635 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
636 | udelay(10); | |
637 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 638 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
639 | } |
640 | ||
641 | /* Whack a reset. We should wait for this. */ | |
642 | writel(1, fep->hwp + FEC_ECNTRL); | |
643 | udelay(10); | |
644 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
645 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
646 | |
647 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 648 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 649 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
650 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
651 | } | |
1da177e4 LT |
652 | } |
653 | ||
654 | ||
45993653 UKK |
655 | static void |
656 | fec_timeout(struct net_device *ndev) | |
657 | { | |
658 | struct fec_enet_private *fep = netdev_priv(ndev); | |
659 | ||
660 | ndev->stats.tx_errors++; | |
661 | ||
54309fa6 FL |
662 | fep->delay_work.timeout = true; |
663 | schedule_delayed_work(&(fep->delay_work.delay_work), 0); | |
664 | } | |
665 | ||
666 | static void fec_enet_work(struct work_struct *work) | |
667 | { | |
668 | struct fec_enet_private *fep = | |
669 | container_of(work, | |
670 | struct fec_enet_private, | |
671 | delay_work.delay_work.work); | |
672 | ||
673 | if (fep->delay_work.timeout) { | |
674 | fep->delay_work.timeout = false; | |
675 | fec_restart(fep->netdev, fep->full_duplex); | |
676 | netif_wake_queue(fep->netdev); | |
677 | } | |
45993653 UKK |
678 | } |
679 | ||
1da177e4 | 680 | static void |
c556167f | 681 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
682 | { |
683 | struct fec_enet_private *fep; | |
2e28532f | 684 | struct bufdesc *bdp; |
0e702ab3 | 685 | unsigned short status; |
1da177e4 | 686 | struct sk_buff *skb; |
de5fb0a0 | 687 | int index = 0; |
1da177e4 | 688 | |
c556167f | 689 | fep = netdev_priv(ndev); |
1da177e4 LT |
690 | bdp = fep->dirty_tx; |
691 | ||
de5fb0a0 FL |
692 | /* get next bdp of dirty_tx */ |
693 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
694 | bdp = fep->tx_bd_base; | |
695 | else | |
696 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
697 | ||
0e702ab3 | 698 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
699 | |
700 | /* current queue is empty */ | |
701 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
702 | break; |
703 | ||
de5fb0a0 FL |
704 | if (fep->bufdesc_ex) |
705 | index = (struct bufdesc_ex *)bdp - | |
706 | (struct bufdesc_ex *)fep->tx_bd_base; | |
707 | else | |
708 | index = bdp - fep->tx_bd_base; | |
709 | ||
d1ab1f54 UKK |
710 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
711 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 712 | bdp->cbd_bufaddr = 0; |
1da177e4 | 713 | |
de5fb0a0 FL |
714 | skb = fep->tx_skbuff[index]; |
715 | ||
1da177e4 | 716 | /* Check for errors. */ |
0e702ab3 | 717 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
718 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
719 | BD_ENET_TX_CSL)) { | |
c556167f | 720 | ndev->stats.tx_errors++; |
0e702ab3 | 721 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 722 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 723 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 724 | ndev->stats.tx_window_errors++; |
0e702ab3 | 725 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 726 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 727 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 728 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 729 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 730 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 731 | } else { |
c556167f | 732 | ndev->stats.tx_packets++; |
1da177e4 LT |
733 | } |
734 | ||
ff43da86 FL |
735 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
736 | fep->bufdesc_ex) { | |
6605b730 FL |
737 | struct skb_shared_hwtstamps shhwtstamps; |
738 | unsigned long flags; | |
ff43da86 | 739 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
740 | |
741 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
742 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
743 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 744 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
745 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
746 | skb_tstamp_tx(skb, &shhwtstamps); | |
747 | } | |
ff43da86 | 748 | |
0e702ab3 | 749 | if (status & BD_ENET_TX_READY) |
31b7720c | 750 | netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); |
22f6b860 | 751 | |
1da177e4 LT |
752 | /* Deferred means some collisions occurred during transmit, |
753 | * but we eventually sent the packet OK. | |
754 | */ | |
0e702ab3 | 755 | if (status & BD_ENET_TX_DEF) |
c556167f | 756 | ndev->stats.collisions++; |
6aa20a22 | 757 | |
22f6b860 | 758 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 759 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
760 | fep->tx_skbuff[index] = NULL; |
761 | ||
762 | fep->dirty_tx = bdp; | |
6aa20a22 | 763 | |
22f6b860 | 764 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 765 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
766 | bdp = fep->tx_bd_base; |
767 | else | |
ff43da86 | 768 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 769 | |
22f6b860 | 770 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 771 | */ |
de5fb0a0 | 772 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
773 | if (netif_queue_stopped(ndev)) |
774 | netif_wake_queue(ndev); | |
1da177e4 LT |
775 | } |
776 | } | |
de5fb0a0 | 777 | return; |
1da177e4 LT |
778 | } |
779 | ||
780 | ||
781 | /* During a receive, the cur_rx points to the current incoming buffer. | |
782 | * When we update through the ring, if the next incoming buffer has | |
783 | * not been given to the system, we just set the empty indicator, | |
784 | * effectively tossing the packet. | |
785 | */ | |
dc975382 FL |
786 | static int |
787 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 788 | { |
c556167f | 789 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
790 | const struct platform_device_id *id_entry = |
791 | platform_get_device_id(fep->pdev); | |
2e28532f | 792 | struct bufdesc *bdp; |
0e702ab3 | 793 | unsigned short status; |
1da177e4 LT |
794 | struct sk_buff *skb; |
795 | ushort pkt_len; | |
796 | __u8 *data; | |
dc975382 | 797 | int pkt_received = 0; |
6aa20a22 | 798 | |
0e702ab3 GU |
799 | #ifdef CONFIG_M532x |
800 | flush_cache_all(); | |
6aa20a22 | 801 | #endif |
1da177e4 | 802 | |
1da177e4 LT |
803 | /* First, grab all of the stats for the incoming packet. |
804 | * These get messed up if we get called due to a busy condition. | |
805 | */ | |
806 | bdp = fep->cur_rx; | |
807 | ||
22f6b860 | 808 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 809 | |
dc975382 FL |
810 | if (pkt_received >= budget) |
811 | break; | |
812 | pkt_received++; | |
813 | ||
22f6b860 SH |
814 | /* Since we have allocated space to hold a complete frame, |
815 | * the last indicator should be set. | |
816 | */ | |
817 | if ((status & BD_ENET_RX_LAST) == 0) | |
31b7720c | 818 | netdev_err(ndev, "rcv is not +last\n"); |
1da177e4 | 819 | |
22f6b860 SH |
820 | if (!fep->opened) |
821 | goto rx_processing_done; | |
1da177e4 | 822 | |
22f6b860 SH |
823 | /* Check for errors. */ |
824 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 825 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 826 | ndev->stats.rx_errors++; |
22f6b860 SH |
827 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
828 | /* Frame too long or too short. */ | |
c556167f | 829 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
830 | } |
831 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 832 | ndev->stats.rx_frame_errors++; |
22f6b860 | 833 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 834 | ndev->stats.rx_crc_errors++; |
22f6b860 | 835 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 836 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 837 | } |
1da177e4 | 838 | |
22f6b860 SH |
839 | /* Report late collisions as a frame error. |
840 | * On this error, the BD is closed, but we don't know what we | |
841 | * have in the buffer. So, just drop this frame on the floor. | |
842 | */ | |
843 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
844 | ndev->stats.rx_errors++; |
845 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
846 | goto rx_processing_done; |
847 | } | |
1da177e4 | 848 | |
22f6b860 | 849 | /* Process the incoming frame. */ |
c556167f | 850 | ndev->stats.rx_packets++; |
22f6b860 | 851 | pkt_len = bdp->cbd_datlen; |
c556167f | 852 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 853 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 854 | |
d1ab1f54 UKK |
855 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
856 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 857 | |
b5680e0b SG |
858 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
859 | swap_buffer(data, pkt_len); | |
860 | ||
22f6b860 SH |
861 | /* This does 16 byte alignment, exactly what we need. |
862 | * The packet length includes FCS, but we don't want to | |
863 | * include that when passing upstream as it messes up | |
864 | * bridging applications. | |
865 | */ | |
b72061a3 | 866 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 867 | |
8549889c | 868 | if (unlikely(!skb)) { |
c556167f | 869 | ndev->stats.rx_dropped++; |
22f6b860 | 870 | } else { |
8549889c | 871 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
872 | skb_put(skb, pkt_len - 4); /* Make room */ |
873 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 874 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 875 | |
6605b730 | 876 | /* Get receive timestamp from the skb */ |
ff43da86 | 877 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
878 | struct skb_shared_hwtstamps *shhwtstamps = |
879 | skb_hwtstamps(skb); | |
880 | unsigned long flags; | |
ff43da86 FL |
881 | struct bufdesc_ex *ebdp = |
882 | (struct bufdesc_ex *)bdp; | |
6605b730 FL |
883 | |
884 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
885 | ||
886 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
887 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 888 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
889 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
890 | } | |
ff43da86 | 891 | |
4c09eed9 JB |
892 | if (fep->bufdesc_ex && |
893 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { | |
894 | struct bufdesc_ex *ebdp = | |
895 | (struct bufdesc_ex *)bdp; | |
896 | if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { | |
897 | /* don't check it */ | |
898 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
899 | } else { | |
900 | skb_checksum_none_assert(skb); | |
901 | } | |
902 | } | |
903 | ||
18a03b97 | 904 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 905 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 906 | } |
f0b3fbea | 907 | |
d1ab1f54 UKK |
908 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
909 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
910 | rx_processing_done: |
911 | /* Clear the status flags for this buffer */ | |
912 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 913 | |
22f6b860 SH |
914 | /* Mark the buffer empty */ |
915 | status |= BD_ENET_RX_EMPTY; | |
916 | bdp->cbd_sc = status; | |
6aa20a22 | 917 | |
ff43da86 FL |
918 | if (fep->bufdesc_ex) { |
919 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
920 | ||
921 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
922 | ebdp->cbd_prot = 0; | |
923 | ebdp->cbd_bdu = 0; | |
924 | } | |
6605b730 | 925 | |
22f6b860 SH |
926 | /* Update BD pointer to next entry */ |
927 | if (status & BD_ENET_RX_WRAP) | |
928 | bdp = fep->rx_bd_base; | |
929 | else | |
ff43da86 | 930 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
931 | /* Doing this here will keep the FEC running while we process |
932 | * incoming frames. On a heavily loaded network, we should be | |
933 | * able to keep up at the expense of system resources. | |
934 | */ | |
935 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
936 | } | |
2e28532f | 937 | fep->cur_rx = bdp; |
1da177e4 | 938 | |
dc975382 | 939 | return pkt_received; |
1da177e4 LT |
940 | } |
941 | ||
45993653 UKK |
942 | static irqreturn_t |
943 | fec_enet_interrupt(int irq, void *dev_id) | |
944 | { | |
945 | struct net_device *ndev = dev_id; | |
946 | struct fec_enet_private *fep = netdev_priv(ndev); | |
947 | uint int_events; | |
948 | irqreturn_t ret = IRQ_NONE; | |
949 | ||
950 | do { | |
951 | int_events = readl(fep->hwp + FEC_IEVENT); | |
952 | writel(int_events, fep->hwp + FEC_IEVENT); | |
953 | ||
de5fb0a0 | 954 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 955 | ret = IRQ_HANDLED; |
dc975382 FL |
956 | |
957 | /* Disable the RX interrupt */ | |
958 | if (napi_schedule_prep(&fep->napi)) { | |
959 | writel(FEC_RX_DISABLED_IMASK, | |
960 | fep->hwp + FEC_IMASK); | |
961 | __napi_schedule(&fep->napi); | |
962 | } | |
45993653 UKK |
963 | } |
964 | ||
45993653 UKK |
965 | if (int_events & FEC_ENET_MII) { |
966 | ret = IRQ_HANDLED; | |
967 | complete(&fep->mdio_done); | |
968 | } | |
969 | } while (int_events); | |
970 | ||
971 | return ret; | |
972 | } | |
973 | ||
dc975382 FL |
974 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
975 | { | |
976 | struct net_device *ndev = napi->dev; | |
977 | int pkts = fec_enet_rx(ndev, budget); | |
978 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 979 | |
de5fb0a0 FL |
980 | fec_enet_tx(ndev); |
981 | ||
dc975382 FL |
982 | if (pkts < budget) { |
983 | napi_complete(napi); | |
984 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
985 | } | |
986 | return pkts; | |
987 | } | |
45993653 | 988 | |
e6b043d5 | 989 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 990 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 991 | { |
c556167f | 992 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 993 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 994 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 995 | |
49da97dc SG |
996 | /* |
997 | * try to get mac address in following order: | |
998 | * | |
999 | * 1) module parameter via kernel command line in form | |
1000 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1001 | */ | |
1002 | iap = macaddr; | |
1003 | ||
ca2cc333 SG |
1004 | /* |
1005 | * 2) from device tree data | |
1006 | */ | |
1007 | if (!is_valid_ether_addr(iap)) { | |
1008 | struct device_node *np = fep->pdev->dev.of_node; | |
1009 | if (np) { | |
1010 | const char *mac = of_get_mac_address(np); | |
1011 | if (mac) | |
1012 | iap = (unsigned char *) mac; | |
1013 | } | |
1014 | } | |
ca2cc333 | 1015 | |
49da97dc | 1016 | /* |
ca2cc333 | 1017 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1018 | */ |
1019 | if (!is_valid_ether_addr(iap)) { | |
1020 | #ifdef CONFIG_M5272 | |
1021 | if (FEC_FLASHMAC) | |
1022 | iap = (unsigned char *)FEC_FLASHMAC; | |
1023 | #else | |
1024 | if (pdata) | |
589efdc7 | 1025 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1026 | #endif |
1027 | } | |
1028 | ||
1029 | /* | |
ca2cc333 | 1030 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1031 | */ |
1032 | if (!is_valid_ether_addr(iap)) { | |
1033 | *((unsigned long *) &tmpaddr[0]) = | |
1034 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
1035 | *((unsigned short *) &tmpaddr[4]) = | |
1036 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1037 | iap = &tmpaddr[0]; |
1da177e4 LT |
1038 | } |
1039 | ||
c556167f | 1040 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1041 | |
49da97dc SG |
1042 | /* Adjust MAC if using macaddr */ |
1043 | if (iap == macaddr) | |
43af940c | 1044 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1045 | } |
1046 | ||
e6b043d5 | 1047 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1048 | |
e6b043d5 BW |
1049 | /* |
1050 | * Phy section | |
1051 | */ | |
c556167f | 1052 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1053 | { |
c556167f | 1054 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1055 | struct phy_device *phy_dev = fep->phy_dev; |
e6b043d5 | 1056 | int status_change = 0; |
1da177e4 | 1057 | |
e6b043d5 BW |
1058 | /* Prevent a state halted on mii error */ |
1059 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1060 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1061 | return; |
e6b043d5 | 1062 | } |
1da177e4 | 1063 | |
e6b043d5 | 1064 | if (phy_dev->link) { |
d97e7497 | 1065 | if (!fep->link) { |
6ea0722f | 1066 | fep->link = phy_dev->link; |
e6b043d5 BW |
1067 | status_change = 1; |
1068 | } | |
1da177e4 | 1069 | |
d97e7497 LS |
1070 | if (fep->full_duplex != phy_dev->duplex) |
1071 | status_change = 1; | |
1072 | ||
1073 | if (phy_dev->speed != fep->speed) { | |
1074 | fep->speed = phy_dev->speed; | |
1075 | status_change = 1; | |
1076 | } | |
1077 | ||
1078 | /* if any of the above changed restart the FEC */ | |
1079 | if (status_change) | |
c556167f | 1080 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
1081 | } else { |
1082 | if (fep->link) { | |
c556167f | 1083 | fec_stop(ndev); |
8d7ed0f0 | 1084 | fep->link = phy_dev->link; |
d97e7497 LS |
1085 | status_change = 1; |
1086 | } | |
1da177e4 | 1087 | } |
6aa20a22 | 1088 | |
e6b043d5 BW |
1089 | if (status_change) |
1090 | phy_print_status(phy_dev); | |
1091 | } | |
1da177e4 | 1092 | |
e6b043d5 | 1093 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1094 | { |
e6b043d5 | 1095 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1096 | unsigned long time_left; |
1da177e4 | 1097 | |
e6b043d5 | 1098 | fep->mii_timeout = 0; |
97b72e43 | 1099 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
1100 | |
1101 | /* start a read op */ | |
1102 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1103 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1104 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1105 | ||
1106 | /* wait for end of transfer */ | |
97b72e43 BS |
1107 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1108 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1109 | if (time_left == 0) { | |
1110 | fep->mii_timeout = 1; | |
31b7720c | 1111 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
97b72e43 | 1112 | return -ETIMEDOUT; |
1da177e4 | 1113 | } |
1da177e4 | 1114 | |
e6b043d5 BW |
1115 | /* return value */ |
1116 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 1117 | } |
6aa20a22 | 1118 | |
e6b043d5 BW |
1119 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1120 | u16 value) | |
1da177e4 | 1121 | { |
e6b043d5 | 1122 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1123 | unsigned long time_left; |
1da177e4 | 1124 | |
e6b043d5 | 1125 | fep->mii_timeout = 0; |
97b72e43 | 1126 | init_completion(&fep->mdio_done); |
1da177e4 | 1127 | |
862f0982 SG |
1128 | /* start a write op */ |
1129 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1130 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1131 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1132 | fep->hwp + FEC_MII_DATA); | |
1133 | ||
1134 | /* wait for end of transfer */ | |
97b72e43 BS |
1135 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1136 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1137 | if (time_left == 0) { | |
1138 | fep->mii_timeout = 1; | |
31b7720c | 1139 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
97b72e43 | 1140 | return -ETIMEDOUT; |
e6b043d5 | 1141 | } |
1da177e4 | 1142 | |
e6b043d5 BW |
1143 | return 0; |
1144 | } | |
1da177e4 | 1145 | |
e6b043d5 | 1146 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1147 | { |
e6b043d5 | 1148 | return 0; |
1da177e4 LT |
1149 | } |
1150 | ||
c556167f | 1151 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1152 | { |
c556167f | 1153 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1154 | const struct platform_device_id *id_entry = |
1155 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1156 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1157 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1158 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1159 | int phy_id; | |
43af940c | 1160 | int dev_id = fep->dev_id; |
562d2f8c | 1161 | |
418bd0d4 BW |
1162 | fep->phy_dev = NULL; |
1163 | ||
6fcc040f GU |
1164 | /* check for attached phy */ |
1165 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1166 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1167 | continue; | |
1168 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1169 | continue; | |
1170 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1171 | continue; | |
b5680e0b SG |
1172 | if (dev_id--) |
1173 | continue; | |
6fcc040f GU |
1174 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1175 | break; | |
e6b043d5 | 1176 | } |
1da177e4 | 1177 | |
6fcc040f | 1178 | if (phy_id >= PHY_MAX_ADDR) { |
31b7720c | 1179 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); |
ea51ade9 | 1180 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1181 | phy_id = 0; |
1182 | } | |
1183 | ||
a7ed07d5 | 1184 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1185 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1186 | fep->phy_interface); |
6fcc040f | 1187 | if (IS_ERR(phy_dev)) { |
31b7720c | 1188 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1189 | return PTR_ERR(phy_dev); |
e6b043d5 | 1190 | } |
1da177e4 | 1191 | |
e6b043d5 | 1192 | /* mask with MAC supported features */ |
baa70a5c | 1193 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1194 | phy_dev->supported &= PHY_GBIT_FEATURES; |
baa70a5c FL |
1195 | phy_dev->supported |= SUPPORTED_Pause; |
1196 | } | |
230dec61 SG |
1197 | else |
1198 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1199 | ||
e6b043d5 | 1200 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1201 | |
e6b043d5 BW |
1202 | fep->phy_dev = phy_dev; |
1203 | fep->link = 0; | |
1204 | fep->full_duplex = 0; | |
1da177e4 | 1205 | |
31b7720c JP |
1206 | netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1207 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
1208 | fep->phy_dev->irq); | |
418bd0d4 | 1209 | |
e6b043d5 | 1210 | return 0; |
1da177e4 LT |
1211 | } |
1212 | ||
e6b043d5 | 1213 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1214 | { |
b5680e0b | 1215 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1216 | struct net_device *ndev = platform_get_drvdata(pdev); |
1217 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1218 | const struct platform_device_id *id_entry = |
1219 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1220 | int err = -ENXIO, i; |
6b265293 | 1221 | |
b5680e0b SG |
1222 | /* |
1223 | * The dual fec interfaces are not equivalent with enet-mac. | |
1224 | * Here are the differences: | |
1225 | * | |
1226 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1227 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1228 | * - external phys can only be configured by fec0 | |
1229 | * | |
1230 | * That is to say fec1 can not work independently. It only works | |
1231 | * when fec0 is working. The reason behind this design is that the | |
1232 | * second interface is added primarily for Switch mode. | |
1233 | * | |
1234 | * Because of the last point above, both phys are attached on fec0 | |
1235 | * mdio interface in board design, and need to be configured by | |
1236 | * fec0 mii_bus. | |
1237 | */ | |
43af940c | 1238 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1239 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1240 | if (mii_cnt && fec0_mii_bus) { |
1241 | fep->mii_bus = fec0_mii_bus; | |
1242 | mii_cnt++; | |
1243 | return 0; | |
1244 | } | |
1245 | return -ENOENT; | |
b5680e0b SG |
1246 | } |
1247 | ||
e6b043d5 | 1248 | fep->mii_timeout = 0; |
1da177e4 | 1249 | |
e6b043d5 BW |
1250 | /* |
1251 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1252 | * |
1253 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1254 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1255 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1256 | * document. | |
e6b043d5 | 1257 | */ |
f4d40de3 | 1258 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1259 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1260 | fep->phy_speed--; | |
1261 | fep->phy_speed <<= 1; | |
e6b043d5 | 1262 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1263 | |
e6b043d5 BW |
1264 | fep->mii_bus = mdiobus_alloc(); |
1265 | if (fep->mii_bus == NULL) { | |
1266 | err = -ENOMEM; | |
1267 | goto err_out; | |
1da177e4 LT |
1268 | } |
1269 | ||
e6b043d5 BW |
1270 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1271 | fep->mii_bus->read = fec_enet_mdio_read; | |
1272 | fep->mii_bus->write = fec_enet_mdio_write; | |
1273 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1274 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1275 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1276 | fep->mii_bus->priv = fep; |
1277 | fep->mii_bus->parent = &pdev->dev; | |
1278 | ||
1279 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1280 | if (!fep->mii_bus->irq) { | |
1281 | err = -ENOMEM; | |
1282 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1283 | } |
1284 | ||
e6b043d5 BW |
1285 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1286 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1287 | |
e6b043d5 BW |
1288 | if (mdiobus_register(fep->mii_bus)) |
1289 | goto err_out_free_mdio_irq; | |
1da177e4 | 1290 | |
e163cc97 LW |
1291 | mii_cnt++; |
1292 | ||
b5680e0b SG |
1293 | /* save fec0 mii_bus */ |
1294 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1295 | fec0_mii_bus = fep->mii_bus; | |
1296 | ||
e6b043d5 | 1297 | return 0; |
1da177e4 | 1298 | |
e6b043d5 BW |
1299 | err_out_free_mdio_irq: |
1300 | kfree(fep->mii_bus->irq); | |
1301 | err_out_free_mdiobus: | |
1302 | mdiobus_free(fep->mii_bus); | |
1303 | err_out: | |
1304 | return err; | |
1da177e4 LT |
1305 | } |
1306 | ||
e6b043d5 | 1307 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1308 | { |
e163cc97 LW |
1309 | if (--mii_cnt == 0) { |
1310 | mdiobus_unregister(fep->mii_bus); | |
1311 | kfree(fep->mii_bus->irq); | |
1312 | mdiobus_free(fep->mii_bus); | |
1313 | } | |
1da177e4 LT |
1314 | } |
1315 | ||
c556167f | 1316 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1317 | struct ethtool_cmd *cmd) |
1da177e4 | 1318 | { |
c556167f | 1319 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1320 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1321 | |
e6b043d5 BW |
1322 | if (!phydev) |
1323 | return -ENODEV; | |
1da177e4 | 1324 | |
e6b043d5 | 1325 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1326 | } |
1327 | ||
c556167f | 1328 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1329 | struct ethtool_cmd *cmd) |
1da177e4 | 1330 | { |
c556167f | 1331 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1332 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1333 | |
e6b043d5 BW |
1334 | if (!phydev) |
1335 | return -ENODEV; | |
1da177e4 | 1336 | |
e6b043d5 | 1337 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1338 | } |
1339 | ||
c556167f | 1340 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1341 | struct ethtool_drvinfo *info) |
1da177e4 | 1342 | { |
c556167f | 1343 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1344 | |
7826d43f JP |
1345 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1346 | sizeof(info->driver)); | |
1347 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1348 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1349 | } |
1350 | ||
5ebae489 FL |
1351 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1352 | struct ethtool_ts_info *info) | |
1353 | { | |
1354 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1355 | ||
1356 | if (fep->bufdesc_ex) { | |
1357 | ||
1358 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1359 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1360 | SOF_TIMESTAMPING_SOFTWARE | | |
1361 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1362 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1363 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1364 | if (fep->ptp_clock) | |
1365 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1366 | else | |
1367 | info->phc_index = -1; | |
1368 | ||
1369 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1370 | (1 << HWTSTAMP_TX_ON); | |
1371 | ||
1372 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1373 | (1 << HWTSTAMP_FILTER_ALL); | |
1374 | return 0; | |
1375 | } else { | |
1376 | return ethtool_op_get_ts_info(ndev, info); | |
1377 | } | |
1378 | } | |
1379 | ||
baa70a5c FL |
1380 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1381 | struct ethtool_pauseparam *pause) | |
1382 | { | |
1383 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1384 | ||
1385 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1386 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1387 | pause->rx_pause = pause->tx_pause; | |
1388 | } | |
1389 | ||
1390 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1391 | struct ethtool_pauseparam *pause) | |
1392 | { | |
1393 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1394 | ||
1395 | if (pause->tx_pause != pause->rx_pause) { | |
1396 | netdev_info(ndev, | |
1397 | "hardware only support enable/disable both tx and rx"); | |
1398 | return -EINVAL; | |
1399 | } | |
1400 | ||
1401 | fep->pause_flag = 0; | |
1402 | ||
1403 | /* tx pause must be same as rx pause */ | |
1404 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1405 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1406 | ||
1407 | if (pause->rx_pause || pause->autoneg) { | |
1408 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1409 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1410 | } else { | |
1411 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1412 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1413 | } | |
1414 | ||
1415 | if (pause->autoneg) { | |
1416 | if (netif_running(ndev)) | |
1417 | fec_stop(ndev); | |
1418 | phy_start_aneg(fep->phy_dev); | |
1419 | } | |
1420 | if (netif_running(ndev)) | |
1421 | fec_restart(ndev, 0); | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
9b07be4b | 1426 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
baa70a5c FL |
1427 | .get_pauseparam = fec_enet_get_pauseparam, |
1428 | .set_pauseparam = fec_enet_set_pauseparam, | |
e6b043d5 BW |
1429 | .get_settings = fec_enet_get_settings, |
1430 | .set_settings = fec_enet_set_settings, | |
1431 | .get_drvinfo = fec_enet_get_drvinfo, | |
1432 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1433 | .get_ts_info = fec_enet_get_ts_info, |
e6b043d5 | 1434 | }; |
1da177e4 | 1435 | |
c556167f | 1436 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1437 | { |
c556167f | 1438 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1439 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1440 | |
c556167f | 1441 | if (!netif_running(ndev)) |
e6b043d5 | 1442 | return -EINVAL; |
1da177e4 | 1443 | |
e6b043d5 BW |
1444 | if (!phydev) |
1445 | return -ENODEV; | |
1446 | ||
ff43da86 | 1447 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1448 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1449 | |
28b04113 | 1450 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1451 | } |
1452 | ||
c556167f | 1453 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1454 | { |
c556167f | 1455 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1456 | unsigned int i; |
f0b3fbea SH |
1457 | struct sk_buff *skb; |
1458 | struct bufdesc *bdp; | |
1459 | ||
1460 | bdp = fep->rx_bd_base; | |
1461 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1462 | skb = fep->rx_skbuff[i]; | |
1463 | ||
1464 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1465 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1466 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1467 | if (skb) | |
1468 | dev_kfree_skb(skb); | |
ff43da86 | 1469 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1470 | } |
1471 | ||
1472 | bdp = fep->tx_bd_base; | |
1473 | for (i = 0; i < TX_RING_SIZE; i++) | |
1474 | kfree(fep->tx_bounce[i]); | |
1475 | } | |
1476 | ||
c556167f | 1477 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1478 | { |
c556167f | 1479 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1480 | unsigned int i; |
f0b3fbea SH |
1481 | struct sk_buff *skb; |
1482 | struct bufdesc *bdp; | |
1483 | ||
1484 | bdp = fep->rx_bd_base; | |
1485 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1486 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1487 | if (!skb) { |
c556167f | 1488 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1489 | return -ENOMEM; |
1490 | } | |
1491 | fep->rx_skbuff[i] = skb; | |
1492 | ||
d1ab1f54 | 1493 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1494 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1495 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1496 | |
1497 | if (fep->bufdesc_ex) { | |
1498 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1499 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1500 | } | |
1501 | ||
1502 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1503 | } |
1504 | ||
1505 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1506 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1507 | bdp->cbd_sc |= BD_SC_WRAP; |
1508 | ||
1509 | bdp = fep->tx_bd_base; | |
1510 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1511 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1512 | ||
1513 | bdp->cbd_sc = 0; | |
1514 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1515 | |
ff43da86 FL |
1516 | if (fep->bufdesc_ex) { |
1517 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
96d2222b | 1518 | ebdp->cbd_esc = BD_ENET_TX_INT; |
ff43da86 FL |
1519 | } |
1520 | ||
1521 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1522 | } |
1523 | ||
1524 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1525 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1526 | bdp->cbd_sc |= BD_SC_WRAP; |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1da177e4 | 1531 | static int |
c556167f | 1532 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1533 | { |
c556167f | 1534 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1535 | int ret; |
1da177e4 | 1536 | |
dc975382 FL |
1537 | napi_enable(&fep->napi); |
1538 | ||
1da177e4 LT |
1539 | /* I should reset the ring buffers here, but I don't yet know |
1540 | * a simple way to do that. | |
1541 | */ | |
1da177e4 | 1542 | |
c556167f | 1543 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1544 | if (ret) |
1545 | return ret; | |
1546 | ||
418bd0d4 | 1547 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1548 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1549 | if (ret) { |
c556167f | 1550 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1551 | return ret; |
1552 | } | |
e6b043d5 | 1553 | phy_start(fep->phy_dev); |
c556167f | 1554 | netif_start_queue(ndev); |
1da177e4 | 1555 | fep->opened = 1; |
22f6b860 | 1556 | return 0; |
1da177e4 LT |
1557 | } |
1558 | ||
1559 | static int | |
c556167f | 1560 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1561 | { |
c556167f | 1562 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1563 | |
22f6b860 | 1564 | /* Don't know what to do yet. */ |
3f104c38 | 1565 | napi_disable(&fep->napi); |
1da177e4 | 1566 | fep->opened = 0; |
c556167f UKK |
1567 | netif_stop_queue(ndev); |
1568 | fec_stop(ndev); | |
1da177e4 | 1569 | |
e497ba82 UKK |
1570 | if (fep->phy_dev) { |
1571 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1572 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1573 | } |
418bd0d4 | 1574 | |
db8880bc | 1575 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1576 | |
1da177e4 LT |
1577 | return 0; |
1578 | } | |
1579 | ||
1da177e4 LT |
1580 | /* Set or clear the multicast filter for this adaptor. |
1581 | * Skeleton taken from sunlance driver. | |
1582 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1583 | * MAC address filtering. Some of the drivers check to make sure it is | |
1584 | * a group multicast address, and discard those that are not. I guess I | |
1585 | * will do the same for now, but just remove the test if you want | |
1586 | * individual filtering as well (do the upper net layers want or support | |
1587 | * this kind of feature?). | |
1588 | */ | |
1589 | ||
1590 | #define HASH_BITS 6 /* #bits in hash */ | |
1591 | #define CRC32_POLY 0xEDB88320 | |
1592 | ||
c556167f | 1593 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1594 | { |
c556167f | 1595 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1596 | struct netdev_hw_addr *ha; |
48e2f183 | 1597 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1598 | unsigned char hash; |
1599 | ||
c556167f | 1600 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1601 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1602 | tmp |= 0x8; | |
1603 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1604 | return; |
1605 | } | |
1da177e4 | 1606 | |
4e831836 SH |
1607 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1608 | tmp &= ~0x8; | |
1609 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1610 | ||
c556167f | 1611 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1612 | /* Catch all multicast addresses, so set the |
1613 | * filter to all 1's | |
1614 | */ | |
1615 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1616 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1617 | ||
1618 | return; | |
1619 | } | |
1620 | ||
1621 | /* Clear filter and add the addresses in hash register | |
1622 | */ | |
1623 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1624 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1625 | ||
c556167f | 1626 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1627 | /* calculate crc32 value of mac address */ |
1628 | crc = 0xffffffff; | |
1629 | ||
c556167f | 1630 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1631 | data = ha->addr[i]; |
4e831836 SH |
1632 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1633 | crc = (crc >> 1) ^ | |
1634 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1635 | } |
1636 | } | |
4e831836 SH |
1637 | |
1638 | /* only upper 6 bits (HASH_BITS) are used | |
1639 | * which point to specific bit in he hash registers | |
1640 | */ | |
1641 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1642 | ||
1643 | if (hash > 31) { | |
1644 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1645 | tmp |= 1 << (hash - 32); | |
1646 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1647 | } else { | |
1648 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1649 | tmp |= 1 << hash; | |
1650 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1651 | } | |
1da177e4 LT |
1652 | } |
1653 | } | |
1654 | ||
22f6b860 | 1655 | /* Set a MAC change in hardware. */ |
009fda83 | 1656 | static int |
c556167f | 1657 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1658 | { |
c556167f | 1659 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1660 | struct sockaddr *addr = p; |
1661 | ||
1662 | if (!is_valid_ether_addr(addr->sa_data)) | |
1663 | return -EADDRNOTAVAIL; | |
1664 | ||
c556167f | 1665 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1666 | |
c556167f UKK |
1667 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1668 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1669 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1670 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1671 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1672 | return 0; |
1da177e4 LT |
1673 | } |
1674 | ||
7f5c6add | 1675 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1676 | /** |
1677 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1678 | * @dev: The FEC network adapter |
1679 | * | |
1680 | * Polled functionality used by netconsole and others in non interrupt mode | |
1681 | * | |
1682 | */ | |
47a5247f | 1683 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
1684 | { |
1685 | int i; | |
1686 | struct fec_enet_private *fep = netdev_priv(dev); | |
1687 | ||
1688 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1689 | if (fep->irq[i] > 0) { | |
1690 | disable_irq(fep->irq[i]); | |
1691 | fec_enet_interrupt(fep->irq[i], dev); | |
1692 | enable_irq(fep->irq[i]); | |
1693 | } | |
1694 | } | |
1695 | } | |
1696 | #endif | |
1697 | ||
4c09eed9 JB |
1698 | static int fec_set_features(struct net_device *netdev, |
1699 | netdev_features_t features) | |
1700 | { | |
1701 | struct fec_enet_private *fep = netdev_priv(netdev); | |
1702 | netdev_features_t changed = features ^ netdev->features; | |
1703 | ||
1704 | netdev->features = features; | |
1705 | ||
1706 | /* Receive checksum has been changed */ | |
1707 | if (changed & NETIF_F_RXCSUM) { | |
1708 | if (features & NETIF_F_RXCSUM) | |
1709 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1710 | else | |
1711 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
1712 | ||
1713 | if (netif_running(netdev)) { | |
1714 | fec_stop(netdev); | |
1715 | fec_restart(netdev, fep->phy_dev->duplex); | |
1716 | netif_wake_queue(netdev); | |
1717 | } else { | |
1718 | fec_restart(netdev, fep->phy_dev->duplex); | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
009fda83 SH |
1725 | static const struct net_device_ops fec_netdev_ops = { |
1726 | .ndo_open = fec_enet_open, | |
1727 | .ndo_stop = fec_enet_close, | |
1728 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1729 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1730 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1731 | .ndo_validate_addr = eth_validate_addr, |
1732 | .ndo_tx_timeout = fec_timeout, | |
1733 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1734 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1735 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1736 | .ndo_poll_controller = fec_poll_controller, | |
1737 | #endif | |
4c09eed9 | 1738 | .ndo_set_features = fec_set_features, |
009fda83 SH |
1739 | }; |
1740 | ||
1da177e4 LT |
1741 | /* |
1742 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1743 | * |
1da177e4 | 1744 | */ |
c556167f | 1745 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1746 | { |
c556167f | 1747 | struct fec_enet_private *fep = netdev_priv(ndev); |
48496255 SG |
1748 | const struct platform_device_id *id_entry = |
1749 | platform_get_device_id(fep->pdev); | |
f0b3fbea | 1750 | struct bufdesc *cbd_base; |
1da177e4 | 1751 | |
8d4dd5cf SH |
1752 | /* Allocate memory for buffer descriptors. */ |
1753 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
d0320f75 JP |
1754 | GFP_KERNEL); |
1755 | if (!cbd_base) | |
562d2f8c | 1756 | return -ENOMEM; |
562d2f8c | 1757 | |
14109a59 | 1758 | memset(cbd_base, 0, PAGE_SIZE); |
3b2b74ca | 1759 | |
c556167f | 1760 | fep->netdev = ndev; |
1da177e4 | 1761 | |
49da97dc | 1762 | /* Get the Ethernet address */ |
c556167f | 1763 | fec_get_mac(ndev); |
1da177e4 | 1764 | |
8d4dd5cf | 1765 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1766 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1767 | if (fep->bufdesc_ex) |
1768 | fep->tx_bd_base = (struct bufdesc *) | |
1769 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1770 | else | |
1771 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1772 | |
22f6b860 | 1773 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1774 | ndev->watchdog_timeo = TX_TIMEOUT; |
1775 | ndev->netdev_ops = &fec_netdev_ops; | |
1776 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1777 | |
dc975382 FL |
1778 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
1779 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | |
1780 | ||
48496255 SG |
1781 | if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { |
1782 | /* enable hw accelerator */ | |
1783 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1784 | | NETIF_F_RXCSUM); | |
1785 | ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1786 | | NETIF_F_RXCSUM); | |
1787 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1788 | } | |
4c09eed9 | 1789 | |
c556167f | 1790 | fec_restart(ndev, 0); |
1da177e4 | 1791 | |
1da177e4 LT |
1792 | return 0; |
1793 | } | |
1794 | ||
ca2cc333 | 1795 | #ifdef CONFIG_OF |
33897cc8 | 1796 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1797 | { |
1798 | int err, phy_reset; | |
a3caad0a | 1799 | int msec = 1; |
ca2cc333 SG |
1800 | struct device_node *np = pdev->dev.of_node; |
1801 | ||
1802 | if (!np) | |
a9b2c8ef | 1803 | return; |
ca2cc333 | 1804 | |
a3caad0a SG |
1805 | of_property_read_u32(np, "phy-reset-duration", &msec); |
1806 | /* A sane reset duration should not be longer than 1s */ | |
1807 | if (msec > 1000) | |
1808 | msec = 1; | |
1809 | ||
ca2cc333 | 1810 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
1811 | if (!gpio_is_valid(phy_reset)) |
1812 | return; | |
1813 | ||
119fc007 SG |
1814 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
1815 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 1816 | if (err) { |
07dcf8e9 | 1817 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 1818 | return; |
ca2cc333 | 1819 | } |
a3caad0a | 1820 | msleep(msec); |
ca2cc333 | 1821 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
1822 | } |
1823 | #else /* CONFIG_OF */ | |
0c7768a0 | 1824 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1825 | { |
1826 | /* | |
1827 | * In case of platform probe, the reset has been done | |
1828 | * by machine code. | |
1829 | */ | |
ca2cc333 SG |
1830 | } |
1831 | #endif /* CONFIG_OF */ | |
1832 | ||
33897cc8 | 1833 | static int |
ead73183 SH |
1834 | fec_probe(struct platform_device *pdev) |
1835 | { | |
1836 | struct fec_enet_private *fep; | |
5eb32bd0 | 1837 | struct fec_platform_data *pdata; |
ead73183 SH |
1838 | struct net_device *ndev; |
1839 | int i, irq, ret = 0; | |
1840 | struct resource *r; | |
ca2cc333 | 1841 | const struct of_device_id *of_id; |
43af940c | 1842 | static int dev_id; |
ca2cc333 SG |
1843 | |
1844 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1845 | if (of_id) | |
1846 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1847 | |
1848 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1849 | if (!r) | |
1850 | return -ENXIO; | |
1851 | ||
ead73183 SH |
1852 | /* Init network device */ |
1853 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
83e519b6 FE |
1854 | if (!ndev) |
1855 | return -ENOMEM; | |
ead73183 SH |
1856 | |
1857 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1858 | ||
1859 | /* setup board info structure */ | |
1860 | fep = netdev_priv(ndev); | |
ead73183 | 1861 | |
baa70a5c FL |
1862 | /* default enable pause frame auto negotiation */ |
1863 | if (pdev->id_entry && | |
1864 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
1865 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
1866 | ||
83e519b6 | 1867 | fep->hwp = devm_request_and_ioremap(&pdev->dev, r); |
e6b043d5 | 1868 | fep->pdev = pdev; |
43af940c | 1869 | fep->dev_id = dev_id++; |
ead73183 | 1870 | |
ff43da86 FL |
1871 | fep->bufdesc_ex = 0; |
1872 | ||
24e531b4 | 1873 | if (!fep->hwp) { |
ead73183 SH |
1874 | ret = -ENOMEM; |
1875 | goto failed_ioremap; | |
1876 | } | |
1877 | ||
1878 | platform_set_drvdata(pdev, ndev); | |
1879 | ||
6c5f7808 | 1880 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 SG |
1881 | if (ret < 0) { |
1882 | pdata = pdev->dev.platform_data; | |
1883 | if (pdata) | |
1884 | fep->phy_interface = pdata->phy; | |
1885 | else | |
1886 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1887 | } else { | |
1888 | fep->phy_interface = ret; | |
1889 | } | |
1890 | ||
f4d40de3 SH |
1891 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1892 | if (IS_ERR(fep->clk_ipg)) { | |
1893 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
1894 | goto failed_clk; |
1895 | } | |
f4d40de3 SH |
1896 | |
1897 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1898 | if (IS_ERR(fep->clk_ahb)) { | |
1899 | ret = PTR_ERR(fep->clk_ahb); | |
1900 | goto failed_clk; | |
1901 | } | |
1902 | ||
daa7d392 WS |
1903 | /* enet_out is optional, depends on board */ |
1904 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
1905 | if (IS_ERR(fep->clk_enet_out)) | |
1906 | fep->clk_enet_out = NULL; | |
1907 | ||
6605b730 | 1908 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
1909 | fep->bufdesc_ex = |
1910 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 | 1911 | if (IS_ERR(fep->clk_ptp)) { |
c29dc2d7 | 1912 | fep->clk_ptp = NULL; |
ff43da86 | 1913 | fep->bufdesc_ex = 0; |
6605b730 | 1914 | } |
6605b730 | 1915 | |
f4d40de3 SH |
1916 | clk_prepare_enable(fep->clk_ahb); |
1917 | clk_prepare_enable(fep->clk_ipg); | |
daa7d392 | 1918 | clk_prepare_enable(fep->clk_enet_out); |
c29dc2d7 | 1919 | clk_prepare_enable(fep->clk_ptp); |
ff43da86 | 1920 | |
f4e9f3d2 FE |
1921 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
1922 | if (!IS_ERR(fep->reg_phy)) { | |
1923 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
1924 | if (ret) { |
1925 | dev_err(&pdev->dev, | |
1926 | "Failed to enable phy regulator: %d\n", ret); | |
1927 | goto failed_regulator; | |
1928 | } | |
1929 | } | |
1930 | ||
2ca9b2aa SG |
1931 | fec_reset_phy(pdev); |
1932 | ||
e2f8d555 FE |
1933 | if (fep->bufdesc_ex) |
1934 | fec_ptp_init(ndev, pdev); | |
1935 | ||
1936 | ret = fec_enet_init(ndev); | |
1937 | if (ret) | |
1938 | goto failed_init; | |
1939 | ||
1940 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1941 | irq = platform_get_irq(pdev, i); | |
1942 | if (irq < 0) { | |
1943 | if (i) | |
1944 | break; | |
1945 | ret = irq; | |
1946 | goto failed_irq; | |
1947 | } | |
1948 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1949 | if (ret) { | |
1950 | while (--i >= 0) { | |
1951 | irq = platform_get_irq(pdev, i); | |
1952 | free_irq(irq, ndev); | |
1953 | } | |
1954 | goto failed_irq; | |
1955 | } | |
1956 | } | |
1957 | ||
e6b043d5 BW |
1958 | ret = fec_enet_mii_init(pdev); |
1959 | if (ret) | |
1960 | goto failed_mii_init; | |
1961 | ||
03c698c9 OS |
1962 | /* Carrier starts down, phylib will bring it up */ |
1963 | netif_carrier_off(ndev); | |
1964 | ||
ead73183 SH |
1965 | ret = register_netdev(ndev); |
1966 | if (ret) | |
1967 | goto failed_register; | |
1968 | ||
eb1d0640 FE |
1969 | if (fep->bufdesc_ex && fep->ptp_clock) |
1970 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
1971 | ||
54309fa6 | 1972 | INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); |
ead73183 SH |
1973 | return 0; |
1974 | ||
1975 | failed_register: | |
e6b043d5 BW |
1976 | fec_enet_mii_remove(fep); |
1977 | failed_mii_init: | |
7a2bbd8d | 1978 | failed_irq: |
e2f8d555 FE |
1979 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1980 | irq = platform_get_irq(pdev, i); | |
1981 | if (irq > 0) | |
1982 | free_irq(irq, ndev); | |
1983 | } | |
7a2bbd8d | 1984 | failed_init: |
5fa9c0fe | 1985 | failed_regulator: |
f4d40de3 SH |
1986 | clk_disable_unprepare(fep->clk_ahb); |
1987 | clk_disable_unprepare(fep->clk_ipg); | |
daa7d392 | 1988 | clk_disable_unprepare(fep->clk_enet_out); |
c29dc2d7 | 1989 | clk_disable_unprepare(fep->clk_ptp); |
ead73183 | 1990 | failed_clk: |
ead73183 SH |
1991 | failed_ioremap: |
1992 | free_netdev(ndev); | |
1993 | ||
1994 | return ret; | |
1995 | } | |
1996 | ||
33897cc8 | 1997 | static int |
ead73183 SH |
1998 | fec_drv_remove(struct platform_device *pdev) |
1999 | { | |
2000 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2001 | struct fec_enet_private *fep = netdev_priv(ndev); | |
e163cc97 | 2002 | int i; |
ead73183 | 2003 | |
54309fa6 | 2004 | cancel_delayed_work_sync(&(fep->delay_work.delay_work)); |
e163cc97 | 2005 | unregister_netdev(ndev); |
e6b043d5 | 2006 | fec_enet_mii_remove(fep); |
6605b730 FL |
2007 | del_timer_sync(&fep->time_keep); |
2008 | clk_disable_unprepare(fep->clk_ptp); | |
2009 | if (fep->ptp_clock) | |
2010 | ptp_clock_unregister(fep->ptp_clock); | |
daa7d392 | 2011 | clk_disable_unprepare(fep->clk_enet_out); |
f4d40de3 SH |
2012 | clk_disable_unprepare(fep->clk_ahb); |
2013 | clk_disable_unprepare(fep->clk_ipg); | |
7f7d6c28 FE |
2014 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
2015 | int irq = platform_get_irq(pdev, i); | |
2016 | if (irq > 0) | |
2017 | free_irq(irq, ndev); | |
2018 | } | |
ead73183 | 2019 | free_netdev(ndev); |
28e2188e | 2020 | |
b3cde36c UKK |
2021 | platform_set_drvdata(pdev, NULL); |
2022 | ||
ead73183 SH |
2023 | return 0; |
2024 | } | |
2025 | ||
bf7bfd7f | 2026 | #ifdef CONFIG_PM_SLEEP |
ead73183 | 2027 | static int |
87cad5c3 | 2028 | fec_suspend(struct device *dev) |
ead73183 | 2029 | { |
87cad5c3 | 2030 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2031 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 2032 | |
04e5216d UKK |
2033 | if (netif_running(ndev)) { |
2034 | fec_stop(ndev); | |
2035 | netif_device_detach(ndev); | |
ead73183 | 2036 | } |
daa7d392 | 2037 | clk_disable_unprepare(fep->clk_enet_out); |
f4d40de3 SH |
2038 | clk_disable_unprepare(fep->clk_ahb); |
2039 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 2040 | |
ead73183 SH |
2041 | return 0; |
2042 | } | |
2043 | ||
2044 | static int | |
87cad5c3 | 2045 | fec_resume(struct device *dev) |
ead73183 | 2046 | { |
87cad5c3 | 2047 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2048 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 2049 | |
daa7d392 | 2050 | clk_prepare_enable(fep->clk_enet_out); |
f4d40de3 SH |
2051 | clk_prepare_enable(fep->clk_ahb); |
2052 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
2053 | if (netif_running(ndev)) { |
2054 | fec_restart(ndev, fep->full_duplex); | |
2055 | netif_device_attach(ndev); | |
ead73183 | 2056 | } |
04e5216d | 2057 | |
ead73183 SH |
2058 | return 0; |
2059 | } | |
bf7bfd7f | 2060 | #endif /* CONFIG_PM_SLEEP */ |
ead73183 | 2061 | |
bf7bfd7f | 2062 | static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); |
59d4289b | 2063 | |
ead73183 SH |
2064 | static struct platform_driver fec_driver = { |
2065 | .driver = { | |
b5680e0b | 2066 | .name = DRIVER_NAME, |
87cad5c3 | 2067 | .owner = THIS_MODULE, |
87cad5c3 | 2068 | .pm = &fec_pm_ops, |
ca2cc333 | 2069 | .of_match_table = fec_dt_ids, |
ead73183 | 2070 | }, |
b5680e0b | 2071 | .id_table = fec_devtype, |
87cad5c3 | 2072 | .probe = fec_probe, |
33897cc8 | 2073 | .remove = fec_drv_remove, |
ead73183 SH |
2074 | }; |
2075 | ||
aaca2377 | 2076 | module_platform_driver(fec_driver); |
1da177e4 LT |
2077 | |
2078 | MODULE_LICENSE("GPL"); |