projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net_sched: remove exceptional & on function name
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
1da177e4
LT		 32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
4c09eed9
JB		 36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
79f33912 39#include <net/tso.h>
4c09eed9
JB		 40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/icmp.h>
1da177e4
LT		 43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
6f501b17
SH		 46#include <linux/io.h>
47#include <linux/irq.h>
196719ec 48#include <linux/clk.h>
ead73183 49#include <linux/platform_device.h>
e6b043d5 50#include <linux/phy.h>
5eb32bd0 51#include <linux/fec.h>
ca2cc333
SG		 52#include <linux/of.h>
53#include <linux/of_device.h>
54#include <linux/of_gpio.h>
55#include <linux/of_net.h>
5fa9c0fe 56#include <linux/regulator/consumer.h>
cdffcf1b 57#include <linux/if_vlan.h>
a68ab98e 58#include <linux/pinctrl/consumer.h>
1da177e4 59
080853af 60#include <asm/cacheflush.h>
196719ec 61
1da177e4 62#include "fec.h"
1da177e4 63
772e42b0
CM		 64static void set_multicast_list(struct net_device *ndev);
65
085e79ed 66#if defined(CONFIG_ARM)
196719ec
SH		 67#define FEC_ALIGNMENT 0xf
68#else
69#define FEC_ALIGNMENT 0x3
70#endif
71
b5680e0b
SG		 72#define DRIVER_NAME "fec"
73
baa70a5c
FL		 74/* Pause frame feild and FIFO threshold */
75#define FEC_ENET_FCE (1 << 5)
76#define FEC_ENET_RSEM_V 0x84
77#define FEC_ENET_RSFL_V 16
78#define FEC_ENET_RAEM_V 0x8
79#define FEC_ENET_RAFL_V 0x8
80#define FEC_ENET_OPD_V 0xFFF0
81
b5680e0b
SG		 82/* Controller is ENET-MAC */
83#define FEC_QUIRK_ENET_MAC (1 << 0)
84/* Controller needs driver to swap frame */
85#define FEC_QUIRK_SWAP_FRAME (1 << 1)
0ca1e290
SG		 86/* Controller uses gasket */
87#define FEC_QUIRK_USE_GASKET (1 << 2)
230dec61
SG		 88/* Controller has GBIT support */
89#define FEC_QUIRK_HAS_GBIT (1 << 3)
ff43da86
FL		 90/* Controller has extend desc buffer */
91#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
48496255
SG		 92/* Controller has hardware checksum support */
93#define FEC_QUIRK_HAS_CSUM (1 << 5)
cdffcf1b
JB		 94/* Controller has hardware vlan support */
95#define FEC_QUIRK_HAS_VLAN (1 << 6)
03191656
FL		 96/* ENET IP errata ERR006358
97 *
98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
99 * detected as not set during a prior frame transmission, then the
100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
03191656
FL		 102 * frames not being transmitted until there is a 0-to-1 transition on
103 * ENET_TDAR[TDAR].
104 */
105#define FEC_QUIRK_ERR006358 (1 << 7)
b5680e0b
SG		 106
107static struct platform_device_id fec_devtype[] = {
108 {
0ca1e290 109 /* keep it for coldfire */
b5680e0b
SG		 110 .name = DRIVER_NAME,
111 .driver_data = 0,
0ca1e290
SG		 112 }, {
113 .name = "imx25-fec",
114 .driver_data = FEC_QUIRK_USE_GASKET,
115 }, {
116 .name = "imx27-fec",
117 .driver_data = 0,
b5680e0b
SG		 118 }, {
119 .name = "imx28-fec",
120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
230dec61
SG		 121 }, {
122 .name = "imx6q-fec",
ff43da86 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
03191656 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
ca7c4a45 126 }, {
36803542 127 .name = "mvf600-fec",
ca7c4a45 128 .driver_data = FEC_QUIRK_ENET_MAC,
0ca1e290
SG		 129 }, {
130 /* sentinel */
131 }
b5680e0b 132};
0ca1e290 133MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 134
ca2cc333 135enum imx_fec_type {
a7dd3219 136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 137 IMX27_FEC, /* runs on i.mx27/35/51 */
138 IMX28_FEC,
230dec61 139 IMX6Q_FEC,
36803542 140 MVF600_FEC,
ca2cc333
SG		 141};
142
143static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ca2cc333
SG		 149 { /* sentinel */ }
150};
151MODULE_DEVICE_TABLE(of, fec_dt_ids);
152
49da97dc
SG		 153static unsigned char macaddr[ETH_ALEN];
154module_param_array(macaddr, byte, NULL, 0);
155MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 156
49da97dc 157#if defined(CONFIG_M5272)
1da177e4
LT		 158/*
159 * Some hardware gets it MAC address out of local flash memory.
160 * if this is non-zero then assume it is the address to get MAC from.
161 */
162#if defined(CONFIG_NETtel)
163#define FEC_FLASHMAC 0xf0006006
164#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
165#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 166#elif defined(CONFIG_CANCam)
167#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 168#elif defined (CONFIG_M5272C3)
169#define FEC_FLASHMAC (0xffe04000 + 4)
170#elif defined(CONFIG_MOD5272)
a7dd3219 171#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 172#else
173#define FEC_FLASHMAC 0
174#endif
43be6366 175#endif /* CONFIG_M5272 */
ead73183 176
22f6b860 177/* Interrupt events/masks. */
1da177e4
LT		 178#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
179#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
180#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
181#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
182#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
183#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
184#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
185#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
186#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
187#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
188
4bee1f9a 189#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
dc975382 190#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
4bee1f9a 191
cdffcf1b 192/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 193 */
cdffcf1b 194#define PKT_MAXBUF_SIZE 1522
1da177e4 195#define PKT_MINBUF_SIZE 64
cdffcf1b 196#define PKT_MAXBLR_SIZE 1536
1da177e4 197
4c09eed9
JB		 198/* FEC receive acceleration */
199#define FEC_RACC_IPDIS (1 << 1)
200#define FEC_RACC_PRODIS (1 << 2)
201#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
202
1da177e4 203/*
6b265293 204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 205 * size bits. Other FEC hardware does not, so we need to take that into
206 * account when setting it.
207 */
562d2f8c 208#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 210#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
211#else
212#define OPT_FRAME_SIZE 0
213#endif
214
e6b043d5
BW		 215/* FEC MII MMFR bits definition */
216#define FEC_MMFR_ST (1 << 30)
217#define FEC_MMFR_OP_READ (2 << 28)
218#define FEC_MMFR_OP_WRITE (1 << 28)
219#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
220#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
221#define FEC_MMFR_TA (2 << 16)
222#define FEC_MMFR_DATA(v) (v & 0xffff)
1da177e4 223
c3b084c2 224#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 225
22f6b860
SH		 226/* Transmitter timeout */
227#define TX_TIMEOUT (2 * HZ)
1da177e4 228
baa70a5c
FL		 229#define FEC_PAUSE_FLAG_AUTONEG 0x1
230#define FEC_PAUSE_FLAG_ENABLE 0x2
231
79f33912
NA		 232#define TSO_HEADER_SIZE 128
233/* Max number of allowed TCP segments for software TSO */
234#define FEC_MAX_TSO_SEGS 100
235#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
236
237#define IS_TSO_HEADER(txq, addr) \
238 ((addr >= txq->tso_hdrs_dma) && \
239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
240
e163cc97
LW		 241static int mii_cnt;
242
36e24e2e
DFB		 243static inline
244struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
ff43da86 245{
36e24e2e
DFB		 246 struct bufdesc *new_bd = bdp + 1;
247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
248 struct bufdesc_ex *ex_base;
249 struct bufdesc *base;
250 int ring_size;
251
252 if (bdp >= fep->tx_bd_base) {
253 base = fep->tx_bd_base;
254 ring_size = fep->tx_ring_size;
255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
256 } else {
257 base = fep->rx_bd_base;
258 ring_size = fep->rx_ring_size;
259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
260 }
261
262 if (fep->bufdesc_ex)
263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
264 ex_base : ex_new_bd);
ff43da86 265 else
36e24e2e
DFB		 266 return (new_bd >= (base + ring_size)) ?
267 base : new_bd;
ff43da86
FL		 268}
269
36e24e2e
DFB		 270static inline
271struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
ff43da86 272{
36e24e2e
DFB		 273 struct bufdesc *new_bd = bdp - 1;
274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
275 struct bufdesc_ex *ex_base;
276 struct bufdesc *base;
277 int ring_size;
278
279 if (bdp >= fep->tx_bd_base) {
280 base = fep->tx_bd_base;
281 ring_size = fep->tx_ring_size;
282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
283 } else {
284 base = fep->rx_bd_base;
285 ring_size = fep->rx_ring_size;
286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
287 }
288
289 if (fep->bufdesc_ex)
290 return (struct bufdesc *)((ex_new_bd < ex_base) ?
291 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 292 else
36e24e2e 293 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 294}
295
61a4427b
NA		 296static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
297 struct fec_enet_private *fep)
298{
299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
300}
301
6e909283
NA		 302static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep)
303{
304 int entries;
305
306 entries = ((const char *)fep->dirty_tx -
307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1;
308
309 return entries > 0 ? entries : entries + fep->tx_ring_size;
310}
311
b5680e0b
SG		 312static void *swap_buffer(void *bufaddr, int len)
313{
314 int i;
315 unsigned int *buf = bufaddr;
316
ffed61e6 317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
b5680e0b
SG		 318 *buf = cpu_to_be32(*buf);
319
320 return bufaddr;
321}
322
344756f6
RK		 323static void fec_dump(struct net_device *ndev)
324{
325 struct fec_enet_private *fep = netdev_priv(ndev);
326 struct bufdesc *bdp = fep->tx_bd_base;
327 unsigned int index = 0;
328
329 netdev_info(ndev, "TX ring dump\n");
330 pr_info("Nr SC addr len SKB\n");
331
332 do {
333 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
334 index,
335 bdp == fep->cur_tx ? 'S' : ' ',
336 bdp == fep->dirty_tx ? 'H' : ' ',
337 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
338 fep->tx_skbuff[index]);
339 bdp = fec_enet_get_nextdesc(bdp, fep);
340 index++;
341 } while (bdp != fep->tx_bd_base);
342}
343
62a02c98
FD		 344static inline bool is_ipv4_pkt(struct sk_buff *skb)
345{
346 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
347}
348
4c09eed9
JB		 349static int
350fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
351{
352 /* Only run for packets requiring a checksum. */
353 if (skb->ip_summed != CHECKSUM_PARTIAL)
354 return 0;
355
356 if (unlikely(skb_cow_head(skb, 0)))
357 return -1;
358
62a02c98
FD		 359 if (is_ipv4_pkt(skb))
360 ip_hdr(skb)->check = 0;
4c09eed9
JB		 361 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
362
363 return 0;
364}
365
6e909283
NA		 366static int
367fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev)
1da177e4 368{
c556167f 369 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 370 const struct platform_device_id *id_entry =
371 platform_get_device_id(fep->pdev);
6e909283
NA		 372 struct bufdesc *bdp = fep->cur_tx;
373 struct bufdesc_ex *ebdp;
374 int nr_frags = skb_shinfo(skb)->nr_frags;
375 int frag, frag_len;
376 unsigned short status;
377 unsigned int estatus = 0;
378 skb_frag_t *this_frag;
de5fb0a0 379 unsigned int index;
6e909283 380 void *bufaddr;
d6bf3143 381 dma_addr_t addr;
6e909283 382 int i;
1da177e4 383
6e909283
NA		 384 for (frag = 0; frag < nr_frags; frag++) {
385 this_frag = &skb_shinfo(skb)->frags[frag];
386 bdp = fec_enet_get_nextdesc(bdp, fep);
387 ebdp = (struct bufdesc_ex *)bdp;
388
389 status = bdp->cbd_sc;
390 status &= ~BD_ENET_TX_STATS;
391 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
392 frag_len = skb_shinfo(skb)->frags[frag].size;
393
394 /* Handle the last BD specially */
395 if (frag == nr_frags - 1) {
396 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
397 if (fep->bufdesc_ex) {
398 estatus |= BD_ENET_TX_INT;
399 if (unlikely(skb_shinfo(skb)->tx_flags &
400 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
401 estatus |= BD_ENET_TX_TS;
402 }
403 }
404
405 if (fep->bufdesc_ex) {
406 if (skb->ip_summed == CHECKSUM_PARTIAL)
407 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
408 ebdp->cbd_bdu = 0;
409 ebdp->cbd_esc = estatus;
410 }
411
412 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
413
414 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
415 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
416 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
417 memcpy(fep->tx_bounce[index], bufaddr, frag_len);
418 bufaddr = fep->tx_bounce[index];
419
420 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
421 swap_buffer(bufaddr, frag_len);
422 }
423
d6bf3143
RK		 424 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
425 DMA_TO_DEVICE);
426 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 427 dev_kfree_skb_any(skb);
428 if (net_ratelimit())
429 netdev_err(ndev, "Tx DMA memory map failed\n");
430 goto dma_mapping_error;
431 }
432
d6bf3143 433 bdp->cbd_bufaddr = addr;
6e909283
NA		 434 bdp->cbd_datlen = frag_len;
435 bdp->cbd_sc = status;
436 }
437
438 fep->cur_tx = bdp;
439
440 return 0;
441
442dma_mapping_error:
1da177e4 443 bdp = fep->cur_tx;
6e909283
NA		 444 for (i = 0; i < frag; i++) {
445 bdp = fec_enet_get_nextdesc(bdp, fep);
446 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
447 bdp->cbd_datlen, DMA_TO_DEVICE);
448 }
449 return NETDEV_TX_OK;
450}
1da177e4 451
6e909283
NA		 452static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
453{
454 struct fec_enet_private *fep = netdev_priv(ndev);
455 const struct platform_device_id *id_entry =
456 platform_get_device_id(fep->pdev);
457 int nr_frags = skb_shinfo(skb)->nr_frags;
458 struct bufdesc *bdp, *last_bdp;
459 void *bufaddr;
d6bf3143 460 dma_addr_t addr;
6e909283
NA		 461 unsigned short status;
462 unsigned short buflen;
463 unsigned int estatus = 0;
464 unsigned int index;
79f33912 465 int entries_free;
6e909283 466 int ret;
22f6b860 467
79f33912
NA		 468 entries_free = fec_enet_get_free_txdesc_num(fep);
469 if (entries_free < MAX_SKB_FRAGS + 1) {
470 dev_kfree_skb_any(skb);
471 if (net_ratelimit())
472 netdev_err(ndev, "NOT enough BD for SG!\n");
473 return NETDEV_TX_OK;
474 }
475
4c09eed9
JB		 476 /* Protocol checksum off-load for TCP and UDP. */
477 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 478 dev_kfree_skb_any(skb);
4c09eed9
JB		 479 return NETDEV_TX_OK;
480 }
481
6e909283
NA		 482 /* Fill in a Tx ring entry */
483 bdp = fep->cur_tx;
484 status = bdp->cbd_sc;
0e702ab3 485 status &= ~BD_ENET_TX_STATS;
1da177e4 486
22f6b860 487 /* Set buffer length and buffer pointer */
9555b31e 488 bufaddr = skb->data;
6e909283 489 buflen = skb_headlen(skb);
1da177e4 490
61a4427b 491 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
6e909283
NA		 492 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
493 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
494 memcpy(fep->tx_bounce[index], skb->data, buflen);
9555b31e 495 bufaddr = fep->tx_bounce[index];
1da177e4 496
6e909283
NA		 497 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
498 swap_buffer(bufaddr, buflen);
499 }
6aa20a22 500
d6bf3143
RK		 501 /* Push the data cache so the CPM does not get stale memory data. */
502 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
503 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 504 dev_kfree_skb_any(skb);
505 if (net_ratelimit())
506 netdev_err(ndev, "Tx DMA memory map failed\n");
507 return NETDEV_TX_OK;
508 }
1da177e4 509
6e909283
NA		 510 if (nr_frags) {
511 ret = fec_enet_txq_submit_frag_skb(skb, ndev);
512 if (ret)
513 return ret;
514 } else {
515 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
516 if (fep->bufdesc_ex) {
517 estatus = BD_ENET_TX_INT;
518 if (unlikely(skb_shinfo(skb)->tx_flags &
519 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
520 estatus |= BD_ENET_TX_TS;
521 }
522 }
523
ff43da86
FL		 524 if (fep->bufdesc_ex) {
525
526 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 527
ff43da86 528 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 529 fep->hwts_tx_en))
6605b730 530 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 531
6e909283
NA		 532 if (skb->ip_summed == CHECKSUM_PARTIAL)
533 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
534
535 ebdp->cbd_bdu = 0;
536 ebdp->cbd_esc = estatus;
6605b730 537 }
03191656 538
6e909283
NA		 539 last_bdp = fep->cur_tx;
540 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep);
541 /* Save skb pointer */
542 fep->tx_skbuff[index] = skb;
543
544 bdp->cbd_datlen = buflen;
d6bf3143 545 bdp->cbd_bufaddr = addr;
6e909283 546
fb8ef788
DFB		 547 /* Send it on its way. Tell FEC it's ready, interrupt when done,
548 * it's the last BD of the frame, and to put the CRC on the end.
549 */
6e909283 550 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
fb8ef788
DFB		 551 bdp->cbd_sc = status;
552
22f6b860 553 /* If this was the last BD in the ring, start at the beginning again. */
6e909283 554 bdp = fec_enet_get_nextdesc(last_bdp, fep);
1da177e4 555
7a2a8451
ED		 556 skb_tx_timestamp(skb);
557
de5fb0a0
FL		 558 fep->cur_tx = bdp;
559
de5fb0a0
FL		 560 /* Trigger transmission start */
561 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1da177e4 562
6e909283 563 return 0;
1da177e4
LT		 564}
565
79f33912
NA		 566static int
567fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev,
568 struct bufdesc *bdp, int index, char *data,
569 int size, bool last_tcp, bool is_last)
61a4427b
NA		 570{
571 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912
NA		 572 const struct platform_device_id *id_entry =
573 platform_get_device_id(fep->pdev);
574 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
575 unsigned short status;
576 unsigned int estatus = 0;
d6bf3143 577 dma_addr_t addr;
61a4427b
NA		 578
579 status = bdp->cbd_sc;
79f33912 580 status &= ~BD_ENET_TX_STATS;
61a4427b 581
79f33912 582 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912
NA		 583
584 if (((unsigned long) data) & FEC_ALIGNMENT ||
585 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
586 memcpy(fep->tx_bounce[index], data, size);
587 data = fep->tx_bounce[index];
588
589 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
590 swap_buffer(data, size);
591 }
592
d6bf3143
RK		 593 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
594 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 595 dev_kfree_skb_any(skb);
6e909283 596 if (net_ratelimit())
79f33912 597 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 598 return NETDEV_TX_BUSY;
599 }
600
d6bf3143
RK		 601 bdp->cbd_datlen = size;
602 bdp->cbd_bufaddr = addr;
603
79f33912
NA		 604 if (fep->bufdesc_ex) {
605 if (skb->ip_summed == CHECKSUM_PARTIAL)
606 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
607 ebdp->cbd_bdu = 0;
608 ebdp->cbd_esc = estatus;
609 }
610
611 /* Handle the last BD specially */
612 if (last_tcp)
613 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
614 if (is_last) {
615 status |= BD_ENET_TX_INTR;
616 if (fep->bufdesc_ex)
617 ebdp->cbd_esc |= BD_ENET_TX_INT;
618 }
619
620 bdp->cbd_sc = status;
621
622 return 0;
623}
624
625static int
626fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev,
627 struct bufdesc *bdp, int index)
628{
629 struct fec_enet_private *fep = netdev_priv(ndev);
630 const struct platform_device_id *id_entry =
631 platform_get_device_id(fep->pdev);
632 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
633 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
634 void *bufaddr;
635 unsigned long dmabuf;
636 unsigned short status;
637 unsigned int estatus = 0;
638
639 status = bdp->cbd_sc;
640 status &= ~BD_ENET_TX_STATS;
641 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
642
643 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
644 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE;
645 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
646 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
647 memcpy(fep->tx_bounce[index], skb->data, hdr_len);
648 bufaddr = fep->tx_bounce[index];
649
650 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
651 swap_buffer(bufaddr, hdr_len);
652
653 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
654 hdr_len, DMA_TO_DEVICE);
655 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
656 dev_kfree_skb_any(skb);
657 if (net_ratelimit())
658 netdev_err(ndev, "Tx DMA memory map failed\n");
659 return NETDEV_TX_BUSY;
660 }
661 }
662
663 bdp->cbd_bufaddr = dmabuf;
664 bdp->cbd_datlen = hdr_len;
665
666 if (fep->bufdesc_ex) {
667 if (skb->ip_summed == CHECKSUM_PARTIAL)
668 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
669 ebdp->cbd_bdu = 0;
670 ebdp->cbd_esc = estatus;
671 }
672
673 bdp->cbd_sc = status;
674
675 return 0;
676}
677
678static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev)
679{
680 struct fec_enet_private *fep = netdev_priv(ndev);
681 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
682 int total_len, data_left;
683 struct bufdesc *bdp = fep->cur_tx;
684 struct tso_t tso;
685 unsigned int index = 0;
686 int ret;
687
688 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) {
689 dev_kfree_skb_any(skb);
690 if (net_ratelimit())
691 netdev_err(ndev, "NOT enough BD for TSO!\n");
692 return NETDEV_TX_OK;
693 }
694
695 /* Protocol checksum off-load for TCP and UDP. */
696 if (fec_enet_clear_csum(skb, ndev)) {
697 dev_kfree_skb_any(skb);
698 return NETDEV_TX_OK;
699 }
700
701 /* Initialize the TSO handler, and prepare the first payload */
702 tso_start(skb, &tso);
703
704 total_len = skb->len - hdr_len;
705 while (total_len > 0) {
706 char *hdr;
707
708 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
709 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
710 total_len -= data_left;
711
712 /* prepare packet headers: MAC + IP + TCP */
713 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
714 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
715 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index);
716 if (ret)
717 goto err_release;
718
719 while (data_left > 0) {
720 int size;
721
722 size = min_t(int, tso.size, data_left);
723 bdp = fec_enet_get_nextdesc(bdp, fep);
724 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
725 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data,
726 size, size == data_left,
727 total_len == 0);
728 if (ret)
729 goto err_release;
730
731 data_left -= size;
732 tso_build_data(skb, &tso, size);
733 }
734
735 bdp = fec_enet_get_nextdesc(bdp, fep);
736 }
737
738 /* Save skb pointer */
739 fep->tx_skbuff[index] = skb;
740
79f33912
NA		 741 skb_tx_timestamp(skb);
742 fep->cur_tx = bdp;
743
744 /* Trigger transmission start */
745 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
746
747 return 0;
748
749err_release:
750 /* TODO: Release all used data descriptors for TSO */
751 return ret;
752}
753
754static netdev_tx_t
755fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
756{
757 struct fec_enet_private *fep = netdev_priv(ndev);
758 int entries_free;
759 int ret;
760
761 if (skb_is_gso(skb))
762 ret = fec_enet_txq_submit_tso(skb, ndev);
763 else
764 ret = fec_enet_txq_submit_skb(skb, ndev);
6e909283
NA		 765 if (ret)
766 return ret;
61a4427b 767
6e909283 768 entries_free = fec_enet_get_free_txdesc_num(fep);
79f33912 769 if (entries_free <= fep->tx_stop_threshold)
61a4427b
NA		 770 netif_stop_queue(ndev);
771
772 return NETDEV_TX_OK;
773}
774
14109a59
FL		 775/* Init RX & TX buffer descriptors
776 */
777static void fec_enet_bd_init(struct net_device *dev)
778{
779 struct fec_enet_private *fep = netdev_priv(dev);
780 struct bufdesc *bdp;
781 unsigned int i;
782
783 /* Initialize the receive buffer descriptors. */
784 bdp = fep->rx_bd_base;
36e24e2e 785 for (i = 0; i < fep->rx_ring_size; i++) {
14109a59
FL		 786
787 /* Initialize the BD for every fragment in the page. */
788 if (bdp->cbd_bufaddr)
789 bdp->cbd_sc = BD_ENET_RX_EMPTY;
790 else
791 bdp->cbd_sc = 0;
36e24e2e 792 bdp = fec_enet_get_nextdesc(bdp, fep);
14109a59
FL		 793 }
794
795 /* Set the last buffer to wrap */
36e24e2e 796 bdp = fec_enet_get_prevdesc(bdp, fep);
14109a59
FL		 797 bdp->cbd_sc |= BD_SC_WRAP;
798
799 fep->cur_rx = fep->rx_bd_base;
800
801 /* ...and the same for transmit */
802 bdp = fep->tx_bd_base;
803 fep->cur_tx = bdp;
36e24e2e 804 for (i = 0; i < fep->tx_ring_size; i++) {
14109a59
FL		 805
806 /* Initialize the BD for every fragment in the page. */
807 bdp->cbd_sc = 0;
d6bf3143 808 if (fep->tx_skbuff[i]) {
14109a59
FL		 809 dev_kfree_skb_any(fep->tx_skbuff[i]);
810 fep->tx_skbuff[i] = NULL;
811 }
812 bdp->cbd_bufaddr = 0;
36e24e2e 813 bdp = fec_enet_get_nextdesc(bdp, fep);
14109a59
FL		 814 }
815
816 /* Set the last buffer to wrap */
36e24e2e 817 bdp = fec_enet_get_prevdesc(bdp, fep);
14109a59
FL		 818 bdp->cbd_sc |= BD_SC_WRAP;
819 fep->dirty_tx = bdp;
820}
821
dbc64a8e
RK		 822/*
823 * This function is called to start or restart the FEC during a link
824 * change, transmit timeout, or to reconfigure the FEC. The network
825 * packet processing for this device must be stopped before this call.
45993653 826 */
1da177e4 827static void
ef83337d 828fec_restart(struct net_device *ndev)
1da177e4 829{
c556167f 830 struct fec_enet_private *fep = netdev_priv(ndev);
45993653
UKK		 831 const struct platform_device_id *id_entry =
832 platform_get_device_id(fep->pdev);
833 int i;
4c09eed9 834 u32 val;
cd1f402c
UKK		 835 u32 temp_mac[2];
836 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 837 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 838
45993653
UKK		 839 /* Whack a reset. We should wait for this. */
840 writel(1, fep->hwp + FEC_ECNTRL);
841 udelay(10);
1da177e4 842
45993653
UKK		 843 /*
844 * enet-mac reset will reset mac address registers too,
845 * so need to reconfigure it.
846 */
847 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
848 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
849 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
850 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
851 }
1da177e4 852
45993653
UKK		 853 /* Clear any outstanding interrupt. */
854 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1da177e4 855
45993653
UKK		 856 /* Set maximum receive buffer size. */
857 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1da177e4 858
14109a59
FL		 859 fec_enet_bd_init(ndev);
860
45993653
UKK		 861 /* Set receive and transmit descriptor base. */
862 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
ff43da86
FL		 863 if (fep->bufdesc_ex)
864 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
36e24e2e 865 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
ff43da86
FL		 866 else
867 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
36e24e2e 868 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
45993653 869
45993653 870
45993653
UKK		 871 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
872 if (fep->tx_skbuff[i]) {
873 dev_kfree_skb_any(fep->tx_skbuff[i]);
874 fep->tx_skbuff[i] = NULL;
1da177e4 875 }
45993653 876 }
97b72e43 877
45993653 878 /* Enable MII mode */
ef83337d 879 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 880 /* FD enable */
45993653
UKK		 881 writel(0x04, fep->hwp + FEC_X_CNTRL);
882 } else {
cd1f402c
UKK		 883 /* No Rcv on Xmit */
884 rcntl |= 0x02;
45993653
UKK		 885 writel(0x0, fep->hwp + FEC_X_CNTRL);
886 }
cd1f402c 887
45993653
UKK		 888 /* Set MII speed */
889 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
890
d1391930 891#if !defined(CONFIG_M5272)
4c09eed9
JB		 892 /* set RX checksum */
893 val = readl(fep->hwp + FEC_RACC);
894 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
895 val |= FEC_RACC_OPTIONS;
896 else
897 val &= ~FEC_RACC_OPTIONS;
898 writel(val, fep->hwp + FEC_RACC);
d1391930 899#endif
4c09eed9 900
45993653
UKK		 901 /*
902 * The phy interface and speed need to get configured
903 * differently on enet-mac.
904 */
905 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 906 /* Enable flow control and length check */
907 rcntl |= 0x40000000 | 0x00000020;
45993653 908
230dec61
SG		 909 /* RGMII, RMII or MII */
910 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
911 rcntl |= (1 << 6);
912 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 913 rcntl |= (1 << 8);
45993653 914 else
cd1f402c 915 rcntl &= ~(1 << 8);
45993653 916
230dec61
SG		 917 /* 1G, 100M or 10M */
918 if (fep->phy_dev) {
919 if (fep->phy_dev->speed == SPEED_1000)
920 ecntl |= (1 << 5);
921 else if (fep->phy_dev->speed == SPEED_100)
922 rcntl &= ~(1 << 9);
923 else
924 rcntl |= (1 << 9);
925 }
45993653
UKK		 926 } else {
927#ifdef FEC_MIIGSK_ENR
0ca1e290 928 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
8d82f219 929 u32 cfgr;
45993653
UKK		 930 /* disable the gasket and wait */
931 writel(0, fep->hwp + FEC_MIIGSK_ENR);
932 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
933 udelay(1);
934
935 /*
936 * configure the gasket:
937 * RMII, 50 MHz, no loopback, no echo
0ca1e290 938 * MII, 25 MHz, no loopback, no echo
45993653 939 */
8d82f219
EB		 940 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
941 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
942 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
943 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
944 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 945
946 /* re-enable the gasket */
947 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 948 }
45993653
UKK		 949#endif
950 }
baa70a5c 951
d1391930 952#if !defined(CONFIG_M5272)
baa70a5c
FL		 953 /* enable pause frame*/
954 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
955 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
956 fep->phy_dev && fep->phy_dev->pause)) {
957 rcntl |= FEC_ENET_FCE;
958
4c09eed9 959 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 960 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
961 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
962 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
963 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
964
965 /* OPD */
966 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
967 } else {
968 rcntl &= ~FEC_ENET_FCE;
969 }
d1391930 970#endif /* !defined(CONFIG_M5272) */
baa70a5c 971
cd1f402c 972 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 973
84fe6182
SW		 974 /* Setup multicast filter. */
975 set_multicast_list(ndev);
976#ifndef CONFIG_M5272
977 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
978 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
979#endif
980
230dec61
SG		 981 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
982 /* enable ENET endian swap */
983 ecntl |= (1 << 8);
984 /* enable ENET store and forward mode */
985 writel(1 << 8, fep->hwp + FEC_X_WMRK);
986 }
987
ff43da86
FL		 988 if (fep->bufdesc_ex)
989 ecntl |= (1 << 4);
6605b730 990
38ae92dc 991#ifndef CONFIG_M5272
b9eef55c
JB		 992 /* Enable the MIB statistic event counters */
993 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 994#endif
995
45993653 996 /* And last, enable the transmit and receive processing */
230dec61 997 writel(ecntl, fep->hwp + FEC_ECNTRL);
45993653
UKK		 998 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
999
ff43da86
FL		 1000 if (fep->bufdesc_ex)
1001 fec_ptp_start_cyclecounter(ndev);
1002
45993653
UKK		 1003 /* Enable interrupts we wish to service */
1004 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1005}
1006
1007static void
1008fec_stop(struct net_device *ndev)
1009{
1010 struct fec_enet_private *fep = netdev_priv(ndev);
230dec61
SG		 1011 const struct platform_device_id *id_entry =
1012 platform_get_device_id(fep->pdev);
42431dc2 1013 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
45993653
UKK		 1014
1015 /* We cannot expect a graceful transmit stop without link !!! */
1016 if (fep->link) {
1017 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1018 udelay(10);
1019 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1020 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1021 }
1022
1023 /* Whack a reset. We should wait for this. */
1024 writel(1, fep->hwp + FEC_ECNTRL);
1025 udelay(10);
1026 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1027 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
230dec61
SG		 1028
1029 /* We have to keep ENET enabled to have MII interrupt stay working */
42431dc2 1030 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
230dec61 1031 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1032 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1033 }
1da177e4
LT		 1034}
1035
1036
45993653
UKK		 1037static void
1038fec_timeout(struct net_device *ndev)
1039{
1040 struct fec_enet_private *fep = netdev_priv(ndev);
1041
344756f6
RK		 1042 fec_dump(ndev);
1043
45993653
UKK		 1044 ndev->stats.tx_errors++;
1045
36cdc743 1046 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1047}
1048
36cdc743 1049static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1050{
1051 struct fec_enet_private *fep =
36cdc743 1052 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1053 struct net_device *ndev = fep->netdev;
54309fa6 1054
36cdc743
RK		 1055 rtnl_lock();
1056 if (netif_device_present(ndev) || netif_running(ndev)) {
1057 napi_disable(&fep->napi);
1058 netif_tx_lock_bh(ndev);
1059 fec_restart(ndev);
1060 netif_wake_queue(ndev);
1061 netif_tx_unlock_bh(ndev);
1062 napi_enable(&fep->napi);
54309fa6 1063 }
36cdc743 1064 rtnl_unlock();
45993653
UKK		 1065}
1066
bfd4ecdd
RK		 1067static void
1068fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1069 struct skb_shared_hwtstamps *hwtstamps)
1070{
1071 unsigned long flags;
1072 u64 ns;
1073
1074 spin_lock_irqsave(&fep->tmreg_lock, flags);
1075 ns = timecounter_cyc2time(&fep->tc, ts);
1076 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1077
1078 memset(hwtstamps, 0, sizeof(*hwtstamps));
1079 hwtstamps->hwtstamp = ns_to_ktime(ns);
1080}
1081
1da177e4 1082static void
c556167f 1083fec_enet_tx(struct net_device *ndev)
1da177e4
LT		 1084{
1085 struct fec_enet_private *fep;
2e28532f 1086 struct bufdesc *bdp;
0e702ab3 1087 unsigned short status;
1da177e4 1088 struct sk_buff *skb;
de5fb0a0 1089 int index = 0;
79f33912 1090 int entries_free;
1da177e4 1091
c556167f 1092 fep = netdev_priv(ndev);
1da177e4
LT		 1093 bdp = fep->dirty_tx;
1094
de5fb0a0 1095 /* get next bdp of dirty_tx */
36e24e2e 1096 bdp = fec_enet_get_nextdesc(bdp, fep);
de5fb0a0 1097
0e702ab3 1098 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
de5fb0a0
FL		 1099
1100 /* current queue is empty */
1101 if (bdp == fep->cur_tx)
f0b3fbea
SH		 1102 break;
1103
61a4427b 1104 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
de5fb0a0 1105
de5fb0a0 1106 skb = fep->tx_skbuff[index];
d6bf3143 1107 fep->tx_skbuff[index] = NULL;
79f33912
NA		 1108 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr))
1109 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1110 bdp->cbd_datlen, DMA_TO_DEVICE);
2488a54e 1111 bdp->cbd_bufaddr = 0;
6e909283
NA		 1112 if (!skb) {
1113 bdp = fec_enet_get_nextdesc(bdp, fep);
1114 continue;
1115 }
de5fb0a0 1116
1da177e4 1117 /* Check for errors. */
0e702ab3 1118 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1119 BD_ENET_TX_RL | BD_ENET_TX_UN |
1120 BD_ENET_TX_CSL)) {
c556167f 1121 ndev->stats.tx_errors++;
0e702ab3 1122 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1123 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1124 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1125 ndev->stats.tx_window_errors++;
0e702ab3 1126 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1127 ndev->stats.tx_aborted_errors++;
0e702ab3 1128 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1129 ndev->stats.tx_fifo_errors++;
0e702ab3 1130 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1131 ndev->stats.tx_carrier_errors++;
1da177e4 1132 } else {
c556167f 1133 ndev->stats.tx_packets++;
6e909283 1134 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1135 }
1136
ff43da86
FL		 1137 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1138 fep->bufdesc_ex) {
6605b730 1139 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1140 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1141
bfd4ecdd 1142 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
6605b730
FL		 1143 skb_tstamp_tx(skb, &shhwtstamps);
1144 }
ff43da86 1145
1da177e4
LT		 1146 /* Deferred means some collisions occurred during transmit,
1147 * but we eventually sent the packet OK.
1148 */
0e702ab3 1149 if (status & BD_ENET_TX_DEF)
c556167f 1150 ndev->stats.collisions++;
6aa20a22 1151
22f6b860 1152 /* Free the sk buffer associated with this last transmit */
1da177e4 1153 dev_kfree_skb_any(skb);
de5fb0a0
FL		 1154
1155 fep->dirty_tx = bdp;
6aa20a22 1156
22f6b860 1157 /* Update pointer to next buffer descriptor to be transmitted */
36e24e2e 1158 bdp = fec_enet_get_nextdesc(bdp, fep);
6aa20a22 1159
22f6b860 1160 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1161 */
79f33912
NA		 1162 if (netif_queue_stopped(ndev)) {
1163 entries_free = fec_enet_get_free_txdesc_num(fep);
1164 if (entries_free >= fep->tx_wake_threshold)
1165 netif_wake_queue(ndev);
1166 }
1da177e4 1167 }
ccea2968
RK		 1168
1169 /* ERR006538: Keep the transmitter going */
1170 if (bdp != fep->cur_tx && readl(fep->hwp + FEC_X_DES_ACTIVE) == 0)
1171 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1da177e4
LT		 1172}
1173
1da177e4
LT		 1174/* During a receive, the cur_rx points to the current incoming buffer.
1175 * When we update through the ring, if the next incoming buffer has
1176 * not been given to the system, we just set the empty indicator,
1177 * effectively tossing the packet.
1178 */
dc975382
FL		 1179static int
1180fec_enet_rx(struct net_device *ndev, int budget)
1da177e4 1181{
c556167f 1182 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 1183 const struct platform_device_id *id_entry =
1184 platform_get_device_id(fep->pdev);
2e28532f 1185 struct bufdesc *bdp;
0e702ab3 1186 unsigned short status;
1da177e4
LT		 1187 struct sk_buff *skb;
1188 ushort pkt_len;
1189 __u8 *data;
dc975382 1190 int pkt_received = 0;
cdffcf1b
JB		 1191 struct bufdesc_ex *ebdp = NULL;
1192 bool vlan_packet_rcvd = false;
1193 u16 vlan_tag;
d842a31f 1194 int index = 0;
6aa20a22 1195
0e702ab3
GU		 1196#ifdef CONFIG_M532x
1197 flush_cache_all();
6aa20a22 1198#endif
1da177e4 1199
1da177e4
LT		 1200 /* First, grab all of the stats for the incoming packet.
1201 * These get messed up if we get called due to a busy condition.
1202 */
1203 bdp = fep->cur_rx;
1204
22f6b860 1205 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4 1206
dc975382
FL		 1207 if (pkt_received >= budget)
1208 break;
1209 pkt_received++;
1210
22f6b860
SH		 1211 /* Since we have allocated space to hold a complete frame,
1212 * the last indicator should be set.
1213 */
1214 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1215 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1216
db3421c1
RK		 1217 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1218
22f6b860
SH		 1219 /* Check for errors. */
1220 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1221 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1222 ndev->stats.rx_errors++;
22f6b860
SH		 1223 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1224 /* Frame too long or too short. */
c556167f 1225 ndev->stats.rx_length_errors++;
22f6b860
SH		 1226 }
1227 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1228 ndev->stats.rx_frame_errors++;
22f6b860 1229 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1230 ndev->stats.rx_crc_errors++;
22f6b860 1231 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1232 ndev->stats.rx_fifo_errors++;
1da177e4 1233 }
1da177e4 1234
22f6b860
SH		 1235 /* Report late collisions as a frame error.
1236 * On this error, the BD is closed, but we don't know what we
1237 * have in the buffer. So, just drop this frame on the floor.
1238 */
1239 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1240 ndev->stats.rx_errors++;
1241 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1242 goto rx_processing_done;
1243 }
1da177e4 1244
22f6b860 1245 /* Process the incoming frame. */
c556167f 1246 ndev->stats.rx_packets++;
22f6b860 1247 pkt_len = bdp->cbd_datlen;
c556167f 1248 ndev->stats.rx_bytes += pkt_len;
1da177e4 1249
61a4427b 1250 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
d842a31f
DFB		 1251 data = fep->rx_skbuff[index]->data;
1252 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1253 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
ccdc4f19 1254
b5680e0b
SG		 1255 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1256 swap_buffer(data, pkt_len);
1257
cdffcf1b
JB		 1258 /* Extract the enhanced buffer descriptor */
1259 ebdp = NULL;
1260 if (fep->bufdesc_ex)
1261 ebdp = (struct bufdesc_ex *)bdp;
1262
1263 /* If this is a VLAN packet remove the VLAN Tag */
1264 vlan_packet_rcvd = false;
1265 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1266 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1267 /* Push and remove the vlan tag */
1268 struct vlan_hdr *vlan_header =
1269 (struct vlan_hdr *) (data + ETH_HLEN);
1270 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1271 pkt_len -= VLAN_HLEN;
1272
1273 vlan_packet_rcvd = true;
1274 }
1275
22f6b860
SH		 1276 /* This does 16 byte alignment, exactly what we need.
1277 * The packet length includes FCS, but we don't want to
1278 * include that when passing upstream as it messes up
1279 * bridging applications.
1280 */
b72061a3 1281 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1da177e4 1282
8549889c 1283 if (unlikely(!skb)) {
c556167f 1284 ndev->stats.rx_dropped++;
22f6b860 1285 } else {
cdffcf1b 1286 int payload_offset = (2 * ETH_ALEN);
8549889c 1287 skb_reserve(skb, NET_IP_ALIGN);
22f6b860 1288 skb_put(skb, pkt_len - 4); /* Make room */
cdffcf1b
JB		 1289
1290 /* Extract the frame data without the VLAN header. */
1291 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1292 if (vlan_packet_rcvd)
1293 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1294 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1295 data + payload_offset,
1296 pkt_len - 4 - (2 * ETH_ALEN));
1297
c556167f 1298 skb->protocol = eth_type_trans(skb, ndev);
ff43da86 1299
6605b730 1300 /* Get receive timestamp from the skb */
bfd4ecdd
RK		 1301 if (fep->hwts_rx_en && fep->bufdesc_ex)
1302 fec_enet_hwtstamp(fep, ebdp->ts,
1303 skb_hwtstamps(skb));
ff43da86 1304
4c09eed9 1305 if (fep->bufdesc_ex &&
cdffcf1b 1306 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
4c09eed9
JB		 1307 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1308 /* don't check it */
1309 skb->ip_summed = CHECKSUM_UNNECESSARY;
1310 } else {
1311 skb_checksum_none_assert(skb);
1312 }
1313 }
1314
cdffcf1b
JB		 1315 /* Handle received VLAN packets */
1316 if (vlan_packet_rcvd)
1317 __vlan_hwaccel_put_tag(skb,
1318 htons(ETH_P_8021Q),
1319 vlan_tag);
1320
0affdf34 1321 napi_gro_receive(&fep->napi, skb);
22f6b860 1322 }
f0b3fbea 1323
d842a31f
DFB		 1324 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1325 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
22f6b860
SH		 1326rx_processing_done:
1327 /* Clear the status flags for this buffer */
1328 status &= ~BD_ENET_RX_STATS;
1da177e4 1329
22f6b860
SH		 1330 /* Mark the buffer empty */
1331 status |= BD_ENET_RX_EMPTY;
1332 bdp->cbd_sc = status;
6aa20a22 1333
ff43da86
FL		 1334 if (fep->bufdesc_ex) {
1335 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1336
1337 ebdp->cbd_esc = BD_ENET_RX_INT;
1338 ebdp->cbd_prot = 0;
1339 ebdp->cbd_bdu = 0;
1340 }
6605b730 1341
22f6b860 1342 /* Update BD pointer to next entry */
36e24e2e
DFB		 1343 bdp = fec_enet_get_nextdesc(bdp, fep);
1344
22f6b860
SH		 1345 /* Doing this here will keep the FEC running while we process
1346 * incoming frames. On a heavily loaded network, we should be
1347 * able to keep up at the expense of system resources.
1348 */
1349 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1350 }
2e28532f 1351 fep->cur_rx = bdp;
1da177e4 1352
dc975382 1353 return pkt_received;
1da177e4
LT		 1354}
1355
45993653
UKK		 1356static irqreturn_t
1357fec_enet_interrupt(int irq, void *dev_id)
1358{
1359 struct net_device *ndev = dev_id;
1360 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c 1361 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
45993653
UKK		 1362 uint int_events;
1363 irqreturn_t ret = IRQ_NONE;
1364
7a16807c
RK		 1365 int_events = readl(fep->hwp + FEC_IEVENT);
1366 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
45993653 1367
7a16807c
RK		 1368 if (int_events & napi_mask) {
1369 ret = IRQ_HANDLED;
dc975382 1370
7a16807c
RK		 1371 /* Disable the NAPI interrupts */
1372 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1373 napi_schedule(&fep->napi);
1374 }
45993653 1375
7a16807c
RK		 1376 if (int_events & FEC_ENET_MII) {
1377 ret = IRQ_HANDLED;
1378 complete(&fep->mdio_done);
1379 }
45993653
UKK		 1380
1381 return ret;
1382}
1383
dc975382
FL		 1384static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1385{
1386 struct net_device *ndev = napi->dev;
dc975382 1387 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1388 int pkts;
1389
1390 /*
1391 * Clear any pending transmit or receive interrupts before
1392 * processing the rings to avoid racing with the hardware.
1393 */
1394 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1395
1396 pkts = fec_enet_rx(ndev, budget);
45993653 1397
de5fb0a0
FL		 1398 fec_enet_tx(ndev);
1399
dc975382
FL		 1400 if (pkts < budget) {
1401 napi_complete(napi);
1402 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1403 }
1404 return pkts;
1405}
45993653 1406
e6b043d5 1407/* ------------------------------------------------------------------------- */
0c7768a0 1408static void fec_get_mac(struct net_device *ndev)
1da177e4 1409{
c556167f 1410 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1411 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1412 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1413
49da97dc
SG		 1414 /*
1415 * try to get mac address in following order:
1416 *
1417 * 1) module parameter via kernel command line in form
1418 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1419 */
1420 iap = macaddr;
1421
ca2cc333
SG		 1422 /*
1423 * 2) from device tree data
1424 */
1425 if (!is_valid_ether_addr(iap)) {
1426 struct device_node *np = fep->pdev->dev.of_node;
1427 if (np) {
1428 const char *mac = of_get_mac_address(np);
1429 if (mac)
1430 iap = (unsigned char *) mac;
1431 }
1432 }
ca2cc333 1433
49da97dc 1434 /*
ca2cc333 1435 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1436 */
1437 if (!is_valid_ether_addr(iap)) {
1438#ifdef CONFIG_M5272
1439 if (FEC_FLASHMAC)
1440 iap = (unsigned char *)FEC_FLASHMAC;
1441#else
1442 if (pdata)
589efdc7 1443 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1444#endif
1445 }
1446
1447 /*
ca2cc333 1448 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1449 */
1450 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1451 *((__be32 *) &tmpaddr[0]) =
1452 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1453 *((__be16 *) &tmpaddr[4]) =
1454 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1455 iap = &tmpaddr[0];
1da177e4
LT		 1456 }
1457
ff5b2fab
LS		 1458 /*
1459 * 5) random mac address
1460 */
1461 if (!is_valid_ether_addr(iap)) {
1462 /* Report it and use a random ethernet address instead */
1463 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1464 eth_hw_addr_random(ndev);
1465 netdev_info(ndev, "Using random MAC address: %pM\n",
1466 ndev->dev_addr);
1467 return;
1468 }
1469
c556167f 1470 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1471
49da97dc
SG		 1472 /* Adjust MAC if using macaddr */
1473 if (iap == macaddr)
43af940c 1474 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1475}
1476
e6b043d5 1477/* ------------------------------------------------------------------------- */
1da177e4 1478
e6b043d5
BW		 1479/*
1480 * Phy section
1481 */
c556167f 1482static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1483{
c556167f 1484 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1485 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1486 int status_change = 0;
1da177e4 1487
e6b043d5
BW		 1488 /* Prevent a state halted on mii error */
1489 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1490 phy_dev->state = PHY_RESUMING;
54309fa6 1491 return;
e6b043d5 1492 }
1da177e4 1493
8ce5624f
RK		 1494 /*
1495 * If the netdev is down, or is going down, we're not interested
1496 * in link state events, so just mark our idea of the link as down
1497 * and ignore the event.
1498 */
1499 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1500 fep->link = 0;
1501 } else if (phy_dev->link) {
d97e7497 1502 if (!fep->link) {
6ea0722f 1503 fep->link = phy_dev->link;
e6b043d5
BW		 1504 status_change = 1;
1505 }
1da177e4 1506
ef83337d
RK		 1507 if (fep->full_duplex != phy_dev->duplex) {
1508 fep->full_duplex = phy_dev->duplex;
d97e7497 1509 status_change = 1;
ef83337d 1510 }
d97e7497
LS		 1511
1512 if (phy_dev->speed != fep->speed) {
1513 fep->speed = phy_dev->speed;
1514 status_change = 1;
1515 }
1516
1517 /* if any of the above changed restart the FEC */
dbc64a8e 1518 if (status_change) {
dbc64a8e 1519 napi_disable(&fep->napi);
dbc64a8e 1520 netif_tx_lock_bh(ndev);
ef83337d 1521 fec_restart(ndev);
dbc64a8e 1522 netif_wake_queue(ndev);
6af42d42 1523 netif_tx_unlock_bh(ndev);
dbc64a8e 1524 napi_enable(&fep->napi);
dbc64a8e 1525 }
d97e7497
LS		 1526 } else {
1527 if (fep->link) {
f208ce10
RK		 1528 napi_disable(&fep->napi);
1529 netif_tx_lock_bh(ndev);
c556167f 1530 fec_stop(ndev);
f208ce10
RK		 1531 netif_tx_unlock_bh(ndev);
1532 napi_enable(&fep->napi);
8d7ed0f0 1533 fep->link = phy_dev->link;
d97e7497
LS		 1534 status_change = 1;
1535 }
1da177e4 1536 }
6aa20a22 1537
e6b043d5
BW		 1538 if (status_change)
1539 phy_print_status(phy_dev);
1540}
1da177e4 1541
e6b043d5 1542static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1543{
e6b043d5 1544 struct fec_enet_private *fep = bus->priv;
97b72e43 1545 unsigned long time_left;
1da177e4 1546
e6b043d5 1547 fep->mii_timeout = 0;
97b72e43 1548 init_completion(&fep->mdio_done);
e6b043d5
BW		 1549
1550 /* start a read op */
1551 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1552 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1553 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1554
1555 /* wait for end of transfer */
97b72e43
BS		 1556 time_left = wait_for_completion_timeout(&fep->mdio_done,
1557 usecs_to_jiffies(FEC_MII_TIMEOUT));
1558 if (time_left == 0) {
1559 fep->mii_timeout = 1;
31b7720c 1560 netdev_err(fep->netdev, "MDIO read timeout\n");
97b72e43 1561 return -ETIMEDOUT;
1da177e4 1562 }
1da177e4 1563
e6b043d5
BW		 1564 /* return value */
1565 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
7dd6a2aa 1566}
6aa20a22 1567
e6b043d5
BW		 1568static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1569 u16 value)
1da177e4 1570{
e6b043d5 1571 struct fec_enet_private *fep = bus->priv;
97b72e43 1572 unsigned long time_left;
1da177e4 1573
e6b043d5 1574 fep->mii_timeout = 0;
97b72e43 1575 init_completion(&fep->mdio_done);
1da177e4 1576
862f0982
SG		 1577 /* start a write op */
1578 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1579 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1580 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1581 fep->hwp + FEC_MII_DATA);
1582
1583 /* wait for end of transfer */
97b72e43
BS		 1584 time_left = wait_for_completion_timeout(&fep->mdio_done,
1585 usecs_to_jiffies(FEC_MII_TIMEOUT));
1586 if (time_left == 0) {
1587 fep->mii_timeout = 1;
31b7720c 1588 netdev_err(fep->netdev, "MDIO write timeout\n");
97b72e43 1589 return -ETIMEDOUT;
e6b043d5 1590 }
1da177e4 1591
e6b043d5
BW		 1592 return 0;
1593}
1da177e4 1594
e8fcfcd5
NA		 1595static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1596{
1597 struct fec_enet_private *fep = netdev_priv(ndev);
1598 int ret;
1599
1600 if (enable) {
1601 ret = clk_prepare_enable(fep->clk_ahb);
1602 if (ret)
1603 return ret;
1604 ret = clk_prepare_enable(fep->clk_ipg);
1605 if (ret)
1606 goto failed_clk_ipg;
1607 if (fep->clk_enet_out) {
1608 ret = clk_prepare_enable(fep->clk_enet_out);
1609 if (ret)
1610 goto failed_clk_enet_out;
1611 }
1612 if (fep->clk_ptp) {
1613 ret = clk_prepare_enable(fep->clk_ptp);
1614 if (ret)
1615 goto failed_clk_ptp;
1616 }
1617 } else {
1618 clk_disable_unprepare(fep->clk_ahb);
1619 clk_disable_unprepare(fep->clk_ipg);
1620 if (fep->clk_enet_out)
1621 clk_disable_unprepare(fep->clk_enet_out);
1622 if (fep->clk_ptp)
1623 clk_disable_unprepare(fep->clk_ptp);
1624 }
1625
1626 return 0;
1627failed_clk_ptp:
1628 if (fep->clk_enet_out)
1629 clk_disable_unprepare(fep->clk_enet_out);
1630failed_clk_enet_out:
1631 clk_disable_unprepare(fep->clk_ipg);
1632failed_clk_ipg:
1633 clk_disable_unprepare(fep->clk_ahb);
1634
1635 return ret;
1636}
1637
c556167f 1638static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1639{
c556167f 1640 struct fec_enet_private *fep = netdev_priv(ndev);
230dec61
SG		 1641 const struct platform_device_id *id_entry =
1642 platform_get_device_id(fep->pdev);
e6b043d5 1643 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1644 char mdio_bus_id[MII_BUS_ID_SIZE];
1645 char phy_name[MII_BUS_ID_SIZE + 3];
1646 int phy_id;
43af940c 1647 int dev_id = fep->dev_id;
562d2f8c 1648
418bd0d4
BW		 1649 fep->phy_dev = NULL;
1650
6fcc040f
GU		 1651 /* check for attached phy */
1652 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1653 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1654 continue;
1655 if (fep->mii_bus->phy_map[phy_id] == NULL)
1656 continue;
1657 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1658 continue;
b5680e0b
SG		 1659 if (dev_id--)
1660 continue;
6fcc040f
GU		 1661 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1662 break;
e6b043d5 1663 }
1da177e4 1664
6fcc040f 1665 if (phy_id >= PHY_MAX_ADDR) {
31b7720c 1666 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
ea51ade9 1667 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
6fcc040f
GU		 1668 phy_id = 0;
1669 }
1670
a7ed07d5 1671 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
f9a8f83b 1672 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
230dec61 1673 fep->phy_interface);
6fcc040f 1674 if (IS_ERR(phy_dev)) {
31b7720c 1675 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1676 return PTR_ERR(phy_dev);
e6b043d5 1677 }
1da177e4 1678
e6b043d5 1679 /* mask with MAC supported features */
baa70a5c 1680 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
230dec61 1681 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1682 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1683#if !defined(CONFIG_M5272)
baa70a5c 1684 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1685#endif
baa70a5c 1686 }
230dec61
SG		 1687 else
1688 phy_dev->supported &= PHY_BASIC_FEATURES;
1689
e6b043d5 1690 phy_dev->advertising = phy_dev->supported;
1da177e4 1691
e6b043d5
BW		 1692 fep->phy_dev = phy_dev;
1693 fep->link = 0;
1694 fep->full_duplex = 0;
1da177e4 1695
31b7720c
JP		 1696 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1697 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1698 fep->phy_dev->irq);
418bd0d4 1699
e6b043d5 1700 return 0;
1da177e4
LT		 1701}
1702
e6b043d5 1703static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1704{
b5680e0b 1705 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1706 struct net_device *ndev = platform_get_drvdata(pdev);
1707 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 1708 const struct platform_device_id *id_entry =
1709 platform_get_device_id(fep->pdev);
e6b043d5 1710 int err = -ENXIO, i;
6b265293 1711
b5680e0b
SG		 1712 /*
1713 * The dual fec interfaces are not equivalent with enet-mac.
1714 * Here are the differences:
1715 *
1716 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1717 * - fec0 acts as the 1588 time master while fec1 is slave
1718 * - external phys can only be configured by fec0
1719 *
1720 * That is to say fec1 can not work independently. It only works
1721 * when fec0 is working. The reason behind this design is that the
1722 * second interface is added primarily for Switch mode.
1723 *
1724 * Because of the last point above, both phys are attached on fec0
1725 * mdio interface in board design, and need to be configured by
1726 * fec0 mii_bus.
1727 */
43af940c 1728 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
b5680e0b 1729 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1730 if (mii_cnt && fec0_mii_bus) {
1731 fep->mii_bus = fec0_mii_bus;
1732 mii_cnt++;
1733 return 0;
1734 }
1735 return -ENOENT;
b5680e0b
SG		 1736 }
1737
e6b043d5 1738 fep->mii_timeout = 0;
1da177e4 1739
e6b043d5
BW		 1740 /*
1741 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1742 *
1743 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1744 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1745 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1746 * document.
e6b043d5 1747 */
98a6eeb8 1748 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
230dec61
SG		 1749 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1750 fep->phy_speed--;
1751 fep->phy_speed <<= 1;
e6b043d5 1752 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 1753
e6b043d5
BW		 1754 fep->mii_bus = mdiobus_alloc();
1755 if (fep->mii_bus == NULL) {
1756 err = -ENOMEM;
1757 goto err_out;
1da177e4
LT		 1758 }
1759
e6b043d5
BW		 1760 fep->mii_bus->name = "fec_enet_mii_bus";
1761 fep->mii_bus->read = fec_enet_mdio_read;
1762 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 1763 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1764 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 1765 fep->mii_bus->priv = fep;
1766 fep->mii_bus->parent = &pdev->dev;
1767
1768 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1769 if (!fep->mii_bus->irq) {
1770 err = -ENOMEM;
1771 goto err_out_free_mdiobus;
1da177e4
LT		 1772 }
1773
e6b043d5
BW		 1774 for (i = 0; i < PHY_MAX_ADDR; i++)
1775 fep->mii_bus->irq[i] = PHY_POLL;
1da177e4 1776
e6b043d5
BW		 1777 if (mdiobus_register(fep->mii_bus))
1778 goto err_out_free_mdio_irq;
1da177e4 1779
e163cc97
LW		 1780 mii_cnt++;
1781
b5680e0b
SG		 1782 /* save fec0 mii_bus */
1783 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1784 fec0_mii_bus = fep->mii_bus;
1785
e6b043d5 1786 return 0;
1da177e4 1787
e6b043d5
BW		 1788err_out_free_mdio_irq:
1789 kfree(fep->mii_bus->irq);
1790err_out_free_mdiobus:
1791 mdiobus_free(fep->mii_bus);
1792err_out:
1793 return err;
1da177e4
LT		 1794}
1795
e6b043d5 1796static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 1797{
e163cc97
LW		 1798 if (--mii_cnt == 0) {
1799 mdiobus_unregister(fep->mii_bus);
1800 kfree(fep->mii_bus->irq);
1801 mdiobus_free(fep->mii_bus);
1802 }
1da177e4
LT		 1803}
1804
c556167f 1805static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 1806 struct ethtool_cmd *cmd)
1da177e4 1807{
c556167f 1808 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1809 struct phy_device *phydev = fep->phy_dev;
1da177e4 1810
e6b043d5
BW		 1811 if (!phydev)
1812 return -ENODEV;
1da177e4 1813
e6b043d5 1814 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 1815}
1816
c556167f 1817static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 1818 struct ethtool_cmd *cmd)
1da177e4 1819{
c556167f 1820 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1821 struct phy_device *phydev = fep->phy_dev;
1da177e4 1822
e6b043d5
BW		 1823 if (!phydev)
1824 return -ENODEV;
1da177e4 1825
e6b043d5 1826 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 1827}
1828
c556167f 1829static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 1830 struct ethtool_drvinfo *info)
1da177e4 1831{
c556167f 1832 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 1833
7826d43f
JP		 1834 strlcpy(info->driver, fep->pdev->dev.driver->name,
1835 sizeof(info->driver));
1836 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1837 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 1838}
1839
5ebae489
FL		 1840static int fec_enet_get_ts_info(struct net_device *ndev,
1841 struct ethtool_ts_info *info)
1842{
1843 struct fec_enet_private *fep = netdev_priv(ndev);
1844
1845 if (fep->bufdesc_ex) {
1846
1847 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1848 SOF_TIMESTAMPING_RX_SOFTWARE |
1849 SOF_TIMESTAMPING_SOFTWARE |
1850 SOF_TIMESTAMPING_TX_HARDWARE |
1851 SOF_TIMESTAMPING_RX_HARDWARE |
1852 SOF_TIMESTAMPING_RAW_HARDWARE;
1853 if (fep->ptp_clock)
1854 info->phc_index = ptp_clock_index(fep->ptp_clock);
1855 else
1856 info->phc_index = -1;
1857
1858 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1859 (1 << HWTSTAMP_TX_ON);
1860
1861 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1862 (1 << HWTSTAMP_FILTER_ALL);
1863 return 0;
1864 } else {
1865 return ethtool_op_get_ts_info(ndev, info);
1866 }
1867}
1868
d1391930
GR		 1869#if !defined(CONFIG_M5272)
1870
baa70a5c
FL		 1871static void fec_enet_get_pauseparam(struct net_device *ndev,
1872 struct ethtool_pauseparam *pause)
1873{
1874 struct fec_enet_private *fep = netdev_priv(ndev);
1875
1876 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1877 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1878 pause->rx_pause = pause->tx_pause;
1879}
1880
1881static int fec_enet_set_pauseparam(struct net_device *ndev,
1882 struct ethtool_pauseparam *pause)
1883{
1884 struct fec_enet_private *fep = netdev_priv(ndev);
1885
0b146ca8
RK		 1886 if (!fep->phy_dev)
1887 return -ENODEV;
1888
baa70a5c
FL		 1889 if (pause->tx_pause != pause->rx_pause) {
1890 netdev_info(ndev,
1891 "hardware only support enable/disable both tx and rx");
1892 return -EINVAL;
1893 }
1894
1895 fep->pause_flag = 0;
1896
1897 /* tx pause must be same as rx pause */
1898 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1899 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1900
1901 if (pause->rx_pause || pause->autoneg) {
1902 fep->phy_dev->supported |= ADVERTISED_Pause;
1903 fep->phy_dev->advertising |= ADVERTISED_Pause;
1904 } else {
1905 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1906 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1907 }
1908
1909 if (pause->autoneg) {
1910 if (netif_running(ndev))
1911 fec_stop(ndev);
1912 phy_start_aneg(fep->phy_dev);
1913 }
dbc64a8e 1914 if (netif_running(ndev)) {
dbc64a8e 1915 napi_disable(&fep->napi);
dbc64a8e 1916 netif_tx_lock_bh(ndev);
ef83337d 1917 fec_restart(ndev);
dbc64a8e 1918 netif_wake_queue(ndev);
6af42d42 1919 netif_tx_unlock_bh(ndev);
dbc64a8e 1920 napi_enable(&fep->napi);
dbc64a8e 1921 }
baa70a5c
FL		 1922
1923 return 0;
1924}
1925
38ae92dc
CH		 1926static const struct fec_stat {
1927 char name[ETH_GSTRING_LEN];
1928 u16 offset;
1929} fec_stats[] = {
1930 /* RMON TX */
1931 { "tx_dropped", RMON_T_DROP },
1932 { "tx_packets", RMON_T_PACKETS },
1933 { "tx_broadcast", RMON_T_BC_PKT },
1934 { "tx_multicast", RMON_T_MC_PKT },
1935 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1936 { "tx_undersize", RMON_T_UNDERSIZE },
1937 { "tx_oversize", RMON_T_OVERSIZE },
1938 { "tx_fragment", RMON_T_FRAG },
1939 { "tx_jabber", RMON_T_JAB },
1940 { "tx_collision", RMON_T_COL },
1941 { "tx_64byte", RMON_T_P64 },
1942 { "tx_65to127byte", RMON_T_P65TO127 },
1943 { "tx_128to255byte", RMON_T_P128TO255 },
1944 { "tx_256to511byte", RMON_T_P256TO511 },
1945 { "tx_512to1023byte", RMON_T_P512TO1023 },
1946 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1947 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1948 { "tx_octets", RMON_T_OCTETS },
1949
1950 /* IEEE TX */
1951 { "IEEE_tx_drop", IEEE_T_DROP },
1952 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1953 { "IEEE_tx_1col", IEEE_T_1COL },
1954 { "IEEE_tx_mcol", IEEE_T_MCOL },
1955 { "IEEE_tx_def", IEEE_T_DEF },
1956 { "IEEE_tx_lcol", IEEE_T_LCOL },
1957 { "IEEE_tx_excol", IEEE_T_EXCOL },
1958 { "IEEE_tx_macerr", IEEE_T_MACERR },
1959 { "IEEE_tx_cserr", IEEE_T_CSERR },
1960 { "IEEE_tx_sqe", IEEE_T_SQE },
1961 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1962 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1963
1964 /* RMON RX */
1965 { "rx_packets", RMON_R_PACKETS },
1966 { "rx_broadcast", RMON_R_BC_PKT },
1967 { "rx_multicast", RMON_R_MC_PKT },
1968 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1969 { "rx_undersize", RMON_R_UNDERSIZE },
1970 { "rx_oversize", RMON_R_OVERSIZE },
1971 { "rx_fragment", RMON_R_FRAG },
1972 { "rx_jabber", RMON_R_JAB },
1973 { "rx_64byte", RMON_R_P64 },
1974 { "rx_65to127byte", RMON_R_P65TO127 },
1975 { "rx_128to255byte", RMON_R_P128TO255 },
1976 { "rx_256to511byte", RMON_R_P256TO511 },
1977 { "rx_512to1023byte", RMON_R_P512TO1023 },
1978 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1979 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1980 { "rx_octets", RMON_R_OCTETS },
1981
1982 /* IEEE RX */
1983 { "IEEE_rx_drop", IEEE_R_DROP },
1984 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1985 { "IEEE_rx_crc", IEEE_R_CRC },
1986 { "IEEE_rx_align", IEEE_R_ALIGN },
1987 { "IEEE_rx_macerr", IEEE_R_MACERR },
1988 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1989 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1990};
1991
1992static void fec_enet_get_ethtool_stats(struct net_device *dev,
1993 struct ethtool_stats *stats, u64 *data)
1994{
1995 struct fec_enet_private *fep = netdev_priv(dev);
1996 int i;
1997
1998 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1999 data[i] = readl(fep->hwp + fec_stats[i].offset);
2000}
2001
2002static void fec_enet_get_strings(struct net_device *netdev,
2003 u32 stringset, u8 *data)
2004{
2005 int i;
2006 switch (stringset) {
2007 case ETH_SS_STATS:
2008 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2009 memcpy(data + i * ETH_GSTRING_LEN,
2010 fec_stats[i].name, ETH_GSTRING_LEN);
2011 break;
2012 }
2013}
2014
2015static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2016{
2017 switch (sset) {
2018 case ETH_SS_STATS:
2019 return ARRAY_SIZE(fec_stats);
2020 default:
2021 return -EOPNOTSUPP;
2022 }
2023}
d1391930 2024#endif /* !defined(CONFIG_M5272) */
38ae92dc 2025
32bc9b46
CH		 2026static int fec_enet_nway_reset(struct net_device *dev)
2027{
2028 struct fec_enet_private *fep = netdev_priv(dev);
2029 struct phy_device *phydev = fep->phy_dev;
2030
2031 if (!phydev)
2032 return -ENODEV;
2033
2034 return genphy_restart_aneg(phydev);
2035}
2036
9b07be4b 2037static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5
BW		 2038 .get_settings = fec_enet_get_settings,
2039 .set_settings = fec_enet_set_settings,
2040 .get_drvinfo = fec_enet_get_drvinfo,
32bc9b46 2041 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2042 .get_link = ethtool_op_get_link,
38ae92dc 2043#ifndef CONFIG_M5272
c1d7c48f
RK		 2044 .get_pauseparam = fec_enet_get_pauseparam,
2045 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2046 .get_strings = fec_enet_get_strings,
c1d7c48f 2047 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2048 .get_sset_count = fec_enet_get_sset_count,
2049#endif
c1d7c48f 2050 .get_ts_info = fec_enet_get_ts_info,
e6b043d5 2051};
1da177e4 2052
c556167f 2053static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2054{
c556167f 2055 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2056 struct phy_device *phydev = fep->phy_dev;
1da177e4 2057
c556167f 2058 if (!netif_running(ndev))
e6b043d5 2059 return -EINVAL;
1da177e4 2060
e6b043d5
BW		 2061 if (!phydev)
2062 return -ENODEV;
2063
1d5244d0
BH		 2064 if (fep->bufdesc_ex) {
2065 if (cmd == SIOCSHWTSTAMP)
2066 return fec_ptp_set(ndev, rq);
2067 if (cmd == SIOCGHWTSTAMP)
2068 return fec_ptp_get(ndev, rq);
2069 }
ff43da86 2070
28b04113 2071 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2072}
2073
c556167f 2074static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2075{
c556167f 2076 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2077 unsigned int i;
f0b3fbea
SH		 2078 struct sk_buff *skb;
2079 struct bufdesc *bdp;
2080
2081 bdp = fep->rx_bd_base;
36e24e2e 2082 for (i = 0; i < fep->rx_ring_size; i++) {
f0b3fbea 2083 skb = fep->rx_skbuff[i];
730ee360
RK		 2084 fep->rx_skbuff[i] = NULL;
2085 if (skb) {
d1ab1f54 2086 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
f0b3fbea 2087 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
f0b3fbea 2088 dev_kfree_skb(skb);
730ee360 2089 }
36e24e2e 2090 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2091 }
2092
2093 bdp = fep->tx_bd_base;
8b7c9efa 2094 for (i = 0; i < fep->tx_ring_size; i++) {
f0b3fbea 2095 kfree(fep->tx_bounce[i]);
8b7c9efa
RK		 2096 fep->tx_bounce[i] = NULL;
2097 skb = fep->tx_skbuff[i];
2098 fep->tx_skbuff[i] = NULL;
2099 dev_kfree_skb(skb);
2100 }
f0b3fbea
SH		 2101}
2102
c556167f 2103static int fec_enet_alloc_buffers(struct net_device *ndev)
f0b3fbea 2104{
c556167f 2105 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2106 unsigned int i;
f0b3fbea
SH		 2107 struct sk_buff *skb;
2108 struct bufdesc *bdp;
2109
2110 bdp = fep->rx_bd_base;
36e24e2e 2111 for (i = 0; i < fep->rx_ring_size; i++) {
730ee360
RK		 2112 dma_addr_t addr;
2113
b72061a3 2114 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2115 if (!skb)
2116 goto err_alloc;
f0b3fbea 2117
730ee360 2118 addr = dma_map_single(&fep->pdev->dev, skb->data,
f0b3fbea 2119 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
730ee360
RK		 2120 if (dma_mapping_error(&fep->pdev->dev, addr)) {
2121 dev_kfree_skb(skb);
d842a31f
DFB		 2122 if (net_ratelimit())
2123 netdev_err(ndev, "Rx DMA memory map failed\n");
ffdce2cc 2124 goto err_alloc;
d842a31f 2125 }
730ee360
RK		 2126
2127 fep->rx_skbuff[i] = skb;
2128 bdp->cbd_bufaddr = addr;
f0b3fbea 2129 bdp->cbd_sc = BD_ENET_RX_EMPTY;
ff43da86
FL		 2130
2131 if (fep->bufdesc_ex) {
2132 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2133 ebdp->cbd_esc = BD_ENET_RX_INT;
2134 }
2135
36e24e2e 2136 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2137 }
2138
2139 /* Set the last buffer to wrap. */
36e24e2e 2140 bdp = fec_enet_get_prevdesc(bdp, fep);
f0b3fbea
SH		 2141 bdp->cbd_sc |= BD_SC_WRAP;
2142
2143 bdp = fep->tx_bd_base;
36e24e2e 2144 for (i = 0; i < fep->tx_ring_size; i++) {
f0b3fbea 2145 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
ffdce2cc
RK		 2146 if (!fep->tx_bounce[i])
2147 goto err_alloc;
f0b3fbea
SH		 2148
2149 bdp->cbd_sc = 0;
2150 bdp->cbd_bufaddr = 0;
6605b730 2151
ff43da86
FL		 2152 if (fep->bufdesc_ex) {
2153 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
96d2222b 2154 ebdp->cbd_esc = BD_ENET_TX_INT;
ff43da86
FL		 2155 }
2156
36e24e2e 2157 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2158 }
2159
2160 /* Set the last buffer to wrap. */
36e24e2e 2161 bdp = fec_enet_get_prevdesc(bdp, fep);
f0b3fbea
SH		 2162 bdp->cbd_sc |= BD_SC_WRAP;
2163
2164 return 0;
ffdce2cc
RK		 2165
2166 err_alloc:
2167 fec_enet_free_buffers(ndev);
2168 return -ENOMEM;
f0b3fbea
SH		 2169}
2170
1da177e4 2171static int
c556167f 2172fec_enet_open(struct net_device *ndev)
1da177e4 2173{
c556167f 2174 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2175 int ret;
1da177e4 2176
5bbde4d2 2177 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2178 ret = fec_enet_clk_enable(ndev, true);
2179 if (ret)
2180 return ret;
2181
1da177e4
LT		 2182 /* I should reset the ring buffers here, but I don't yet know
2183 * a simple way to do that.
2184 */
1da177e4 2185
c556167f 2186 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea
SH		 2187 if (ret)
2188 return ret;
2189
418bd0d4 2190 /* Probe and connect to PHY when open the interface */
c556167f 2191 ret = fec_enet_mii_probe(ndev);
418bd0d4 2192 if (ret) {
c556167f 2193 fec_enet_free_buffers(ndev);
418bd0d4
BW		 2194 return ret;
2195 }
ce5eaf02 2196
ef83337d 2197 fec_restart(ndev);
ce5eaf02 2198 napi_enable(&fep->napi);
e6b043d5 2199 phy_start(fep->phy_dev);
c556167f 2200 netif_start_queue(ndev);
22f6b860 2201 return 0;
1da177e4
LT		 2202}
2203
2204static int
c556167f 2205fec_enet_close(struct net_device *ndev)
1da177e4 2206{
c556167f 2207 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2208
d76cfae9
RK		 2209 phy_stop(fep->phy_dev);
2210
31a6de34
RK		 2211 if (netif_device_present(ndev)) {
2212 napi_disable(&fep->napi);
2213 netif_tx_disable(ndev);
8bbbd3c1 2214 fec_stop(ndev);
31a6de34 2215 }
1da177e4 2216
635cf17c 2217 phy_disconnect(fep->phy_dev);
0b146ca8 2218 fep->phy_dev = NULL;
418bd0d4 2219
e8fcfcd5 2220 fec_enet_clk_enable(ndev, false);
5bbde4d2 2221 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
db8880bc 2222 fec_enet_free_buffers(ndev);
f0b3fbea 2223
1da177e4
LT		 2224 return 0;
2225}
2226
1da177e4
LT		 2227/* Set or clear the multicast filter for this adaptor.
2228 * Skeleton taken from sunlance driver.
2229 * The CPM Ethernet implementation allows Multicast as well as individual
2230 * MAC address filtering. Some of the drivers check to make sure it is
2231 * a group multicast address, and discard those that are not. I guess I
2232 * will do the same for now, but just remove the test if you want
2233 * individual filtering as well (do the upper net layers want or support
2234 * this kind of feature?).
2235 */
2236
2237#define HASH_BITS 6 /* #bits in hash */
2238#define CRC32_POLY 0xEDB88320
2239
c556167f 2240static void set_multicast_list(struct net_device *ndev)
1da177e4 2241{
c556167f 2242 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2243 struct netdev_hw_addr *ha;
48e2f183 2244 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2245 unsigned char hash;
2246
c556167f 2247 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2248 tmp = readl(fep->hwp + FEC_R_CNTRL);
2249 tmp |= 0x8;
2250 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2251 return;
2252 }
1da177e4 2253
4e831836
SH		 2254 tmp = readl(fep->hwp + FEC_R_CNTRL);
2255 tmp &= ~0x8;
2256 writel(tmp, fep->hwp + FEC_R_CNTRL);
2257
c556167f 2258 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2259 /* Catch all multicast addresses, so set the
2260 * filter to all 1's
2261 */
2262 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2263 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2264
2265 return;
2266 }
2267
2268 /* Clear filter and add the addresses in hash register
2269 */
2270 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2271 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2272
c556167f 2273 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2274 /* calculate crc32 value of mac address */
2275 crc = 0xffffffff;
2276
c556167f 2277 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2278 data = ha->addr[i];
4e831836
SH		 2279 for (bit = 0; bit < 8; bit++, data >>= 1) {
2280 crc = (crc >> 1) ^
2281 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2282 }
2283 }
4e831836
SH		 2284
2285 /* only upper 6 bits (HASH_BITS) are used
2286 * which point to specific bit in he hash registers
2287 */
2288 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2289
2290 if (hash > 31) {
2291 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2292 tmp |= 1 << (hash - 32);
2293 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2294 } else {
2295 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2296 tmp |= 1 << hash;
2297 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2298 }
1da177e4
LT		 2299 }
2300}
2301
22f6b860 2302/* Set a MAC change in hardware. */
009fda83 2303static int
c556167f 2304fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2305{
c556167f 2306 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2307 struct sockaddr *addr = p;
2308
44934fac
LS		 2309 if (addr) {
2310 if (!is_valid_ether_addr(addr->sa_data))
2311 return -EADDRNOTAVAIL;
2312 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2313 }
1da177e4 2314
c556167f
UKK		 2315 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2316 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2317 fep->hwp + FEC_ADDR_LOW);
c556167f 2318 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2319 fep->hwp + FEC_ADDR_HIGH);
009fda83 2320 return 0;
1da177e4
LT		 2321}
2322
7f5c6add 2323#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2324/**
2325 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2326 * @dev: The FEC network adapter
2327 *
2328 * Polled functionality used by netconsole and others in non interrupt mode
2329 *
2330 */
47a5247f 2331static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 2332{
2333 int i;
2334 struct fec_enet_private *fep = netdev_priv(dev);
2335
2336 for (i = 0; i < FEC_IRQ_NUM; i++) {
2337 if (fep->irq[i] > 0) {
2338 disable_irq(fep->irq[i]);
2339 fec_enet_interrupt(fep->irq[i], dev);
2340 enable_irq(fep->irq[i]);
2341 }
2342 }
2343}
2344#endif
2345
8506fa1d
RK		 2346#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2347
4c09eed9
JB		 2348static int fec_set_features(struct net_device *netdev,
2349 netdev_features_t features)
2350{
2351 struct fec_enet_private *fep = netdev_priv(netdev);
2352 netdev_features_t changed = features ^ netdev->features;
2353
8506fa1d
RK		 2354 /* Quiesce the device if necessary */
2355 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2356 napi_disable(&fep->napi);
2357 netif_tx_lock_bh(netdev);
2358 fec_stop(netdev);
2359 }
2360
4c09eed9
JB		 2361 netdev->features = features;
2362
2363 /* Receive checksum has been changed */
2364 if (changed & NETIF_F_RXCSUM) {
2365 if (features & NETIF_F_RXCSUM)
2366 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2367 else
2368 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 2369 }
4c09eed9 2370
8506fa1d
RK		 2371 /* Resume the device after updates */
2372 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
ef83337d 2373 fec_restart(netdev);
8506fa1d
RK		 2374 netif_wake_queue(netdev);
2375 netif_tx_unlock_bh(netdev);
2376 napi_enable(&fep->napi);
4c09eed9
JB		 2377 }
2378
2379 return 0;
2380}
2381
009fda83
SH		 2382static const struct net_device_ops fec_netdev_ops = {
2383 .ndo_open = fec_enet_open,
2384 .ndo_stop = fec_enet_close,
2385 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 2386 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 2387 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 2388 .ndo_validate_addr = eth_validate_addr,
2389 .ndo_tx_timeout = fec_timeout,
2390 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 2391 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 2392#ifdef CONFIG_NET_POLL_CONTROLLER
2393 .ndo_poll_controller = fec_poll_controller,
2394#endif
4c09eed9 2395 .ndo_set_features = fec_set_features,
009fda83
SH		 2396};
2397
1da177e4
LT		 2398 /*
2399 * XXX: We need to clean up on failure exits here.
ead73183 2400 *
1da177e4 2401 */
c556167f 2402static int fec_enet_init(struct net_device *ndev)
1da177e4 2403{
c556167f 2404 struct fec_enet_private *fep = netdev_priv(ndev);
48496255
SG		 2405 const struct platform_device_id *id_entry =
2406 platform_get_device_id(fep->pdev);
f0b3fbea 2407 struct bufdesc *cbd_base;
55d0218a
NA		 2408 int bd_size;
2409
2410 /* init the tx & rx ring size */
2411 fep->tx_ring_size = TX_RING_SIZE;
2412 fep->rx_ring_size = RX_RING_SIZE;
2413
79f33912
NA		 2414 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2415 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2;
2416
55d0218a
NA		 2417 if (fep->bufdesc_ex)
2418 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2419 else
2420 fep->bufdesc_size = sizeof(struct bufdesc);
2421 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2422 fep->bufdesc_size;
1da177e4 2423
8d4dd5cf 2424 /* Allocate memory for buffer descriptors. */
55d0218a 2425 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
d0320f75
JP		 2426 GFP_KERNEL);
2427 if (!cbd_base)
562d2f8c 2428 return -ENOMEM;
562d2f8c 2429
79f33912
NA		 2430 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE,
2431 &fep->tso_hdrs_dma, GFP_KERNEL);
2432 if (!fep->tso_hdrs) {
2433 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma);
2434 return -ENOMEM;
2435 }
2436
14109a59 2437 memset(cbd_base, 0, PAGE_SIZE);
3b2b74ca 2438
c556167f 2439 fep->netdev = ndev;
1da177e4 2440
49da97dc 2441 /* Get the Ethernet address */
c556167f 2442 fec_get_mac(ndev);
44934fac
LS		 2443 /* make sure MAC we just acquired is programmed into the hw */
2444 fec_set_mac_address(ndev, NULL);
1da177e4 2445
8d4dd5cf 2446 /* Set receive and transmit descriptor base. */
1da177e4 2447 fep->rx_bd_base = cbd_base;
55d0218a 2448 if (fep->bufdesc_ex)
ff43da86 2449 fep->tx_bd_base = (struct bufdesc *)
36e24e2e 2450 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
55d0218a 2451 else
36e24e2e 2452 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
1da177e4 2453
22f6b860 2454 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 2455 ndev->watchdog_timeo = TX_TIMEOUT;
2456 ndev->netdev_ops = &fec_netdev_ops;
2457 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 2458
dc975382 2459 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 2460 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 2461
09d1e541 2462 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 2463 /* enable hw VLAN support */
2464 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 2465
48496255 2466 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 2467 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
2468
48496255
SG		 2469 /* enable hw accelerator */
2470 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 2471 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 2472 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2473 }
4c09eed9 2474
09d1e541
NA		 2475 ndev->hw_features = ndev->features;
2476
ef83337d 2477 fec_restart(ndev);
1da177e4 2478
1da177e4
LT		 2479 return 0;
2480}
2481
ca2cc333 2482#ifdef CONFIG_OF
33897cc8 2483static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 2484{
2485 int err, phy_reset;
a3caad0a 2486 int msec = 1;
ca2cc333
SG		 2487 struct device_node *np = pdev->dev.of_node;
2488
2489 if (!np)
a9b2c8ef 2490 return;
ca2cc333 2491
a3caad0a
SG		 2492 of_property_read_u32(np, "phy-reset-duration", &msec);
2493 /* A sane reset duration should not be longer than 1s */
2494 if (msec > 1000)
2495 msec = 1;
2496
ca2cc333 2497 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 2498 if (!gpio_is_valid(phy_reset))
2499 return;
2500
119fc007
SG		 2501 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2502 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 2503 if (err) {
07dcf8e9 2504 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 2505 return;
ca2cc333 2506 }
a3caad0a 2507 msleep(msec);
ca2cc333 2508 gpio_set_value(phy_reset, 1);
ca2cc333
SG		 2509}
2510#else /* CONFIG_OF */
0c7768a0 2511static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 2512{
2513 /*
2514 * In case of platform probe, the reset has been done
2515 * by machine code.
2516 */
ca2cc333
SG		 2517}
2518#endif /* CONFIG_OF */
2519
33897cc8 2520static int
ead73183
SH		 2521fec_probe(struct platform_device *pdev)
2522{
2523 struct fec_enet_private *fep;
5eb32bd0 2524 struct fec_platform_data *pdata;
ead73183
SH		 2525 struct net_device *ndev;
2526 int i, irq, ret = 0;
2527 struct resource *r;
ca2cc333 2528 const struct of_device_id *of_id;
43af940c 2529 static int dev_id;
ca2cc333
SG		 2530
2531 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2532 if (of_id)
2533 pdev->id_entry = of_id->data;
ead73183 2534
ead73183
SH		 2535 /* Init network device */
2536 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
83e519b6
FE		 2537 if (!ndev)
2538 return -ENOMEM;
ead73183
SH		 2539
2540 SET_NETDEV_DEV(ndev, &pdev->dev);
2541
2542 /* setup board info structure */
2543 fep = netdev_priv(ndev);
ead73183 2544
d1391930 2545#if !defined(CONFIG_M5272)
baa70a5c
FL		 2546 /* default enable pause frame auto negotiation */
2547 if (pdev->id_entry &&
2548 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2549 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 2550#endif
baa70a5c 2551
5bbde4d2
NA		 2552 /* Select default pin state */
2553 pinctrl_pm_select_default_state(&pdev->dev);
2554
399db75b 2555 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 2556 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2557 if (IS_ERR(fep->hwp)) {
2558 ret = PTR_ERR(fep->hwp);
2559 goto failed_ioremap;
2560 }
2561
e6b043d5 2562 fep->pdev = pdev;
43af940c 2563 fep->dev_id = dev_id++;
ead73183 2564
ff43da86
FL		 2565 fep->bufdesc_ex = 0;
2566
ead73183
SH		 2567 platform_set_drvdata(pdev, ndev);
2568
6c5f7808 2569 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 2570 if (ret < 0) {
94660ba0 2571 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 2572 if (pdata)
2573 fep->phy_interface = pdata->phy;
2574 else
2575 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2576 } else {
2577 fep->phy_interface = ret;
2578 }
2579
f4d40de3
SH		 2580 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2581 if (IS_ERR(fep->clk_ipg)) {
2582 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 2583 goto failed_clk;
2584 }
f4d40de3
SH		 2585
2586 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2587 if (IS_ERR(fep->clk_ahb)) {
2588 ret = PTR_ERR(fep->clk_ahb);
2589 goto failed_clk;
2590 }
2591
daa7d392
WS		 2592 /* enet_out is optional, depends on board */
2593 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2594 if (IS_ERR(fep->clk_enet_out))
2595 fep->clk_enet_out = NULL;
2596
6605b730 2597 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
e2f8d555
FE		 2598 fep->bufdesc_ex =
2599 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730 2600 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 2601 fep->clk_ptp = NULL;
ff43da86 2602 fep->bufdesc_ex = 0;
6605b730 2603 }
6605b730 2604
e8fcfcd5 2605 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 2606 if (ret)
2607 goto failed_clk;
2608
f4e9f3d2
FE		 2609 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2610 if (!IS_ERR(fep->reg_phy)) {
2611 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 2612 if (ret) {
2613 dev_err(&pdev->dev,
2614 "Failed to enable phy regulator: %d\n", ret);
2615 goto failed_regulator;
2616 }
f6a4d607
FE		 2617 } else {
2618 fep->reg_phy = NULL;
5fa9c0fe
SG		 2619 }
2620
2ca9b2aa
SG		 2621 fec_reset_phy(pdev);
2622
e2f8d555 2623 if (fep->bufdesc_ex)
ca162a82 2624 fec_ptp_init(pdev);
e2f8d555
FE		 2625
2626 ret = fec_enet_init(ndev);
2627 if (ret)
2628 goto failed_init;
2629
2630 for (i = 0; i < FEC_IRQ_NUM; i++) {
2631 irq = platform_get_irq(pdev, i);
2632 if (irq < 0) {
2633 if (i)
2634 break;
2635 ret = irq;
2636 goto failed_irq;
2637 }
0d9b2ab1 2638 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 2639 0, pdev->name, ndev);
0d9b2ab1 2640 if (ret)
e2f8d555 2641 goto failed_irq;
e2f8d555
FE		 2642 }
2643
e6b043d5
BW		 2644 ret = fec_enet_mii_init(pdev);
2645 if (ret)
2646 goto failed_mii_init;
2647
03c698c9
OS		 2648 /* Carrier starts down, phylib will bring it up */
2649 netif_carrier_off(ndev);
e8fcfcd5 2650 fec_enet_clk_enable(ndev, false);
5bbde4d2 2651 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 2652
ead73183
SH		 2653 ret = register_netdev(ndev);
2654 if (ret)
2655 goto failed_register;
2656
eb1d0640
FE		 2657 if (fep->bufdesc_ex && fep->ptp_clock)
2658 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2659
36cdc743 2660 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
ead73183
SH		 2661 return 0;
2662
2663failed_register:
e6b043d5
BW		 2664 fec_enet_mii_remove(fep);
2665failed_mii_init:
7a2bbd8d 2666failed_irq:
7a2bbd8d 2667failed_init:
f6a4d607
FE		 2668 if (fep->reg_phy)
2669 regulator_disable(fep->reg_phy);
5fa9c0fe 2670failed_regulator:
e8fcfcd5 2671 fec_enet_clk_enable(ndev, false);
ead73183 2672failed_clk:
ead73183
SH		 2673failed_ioremap:
2674 free_netdev(ndev);
2675
2676 return ret;
2677}
2678
33897cc8 2679static int
ead73183
SH		 2680fec_drv_remove(struct platform_device *pdev)
2681{
2682 struct net_device *ndev = platform_get_drvdata(pdev);
2683 struct fec_enet_private *fep = netdev_priv(ndev);
2684
36cdc743 2685 cancel_work_sync(&fep->tx_timeout_work);
e163cc97 2686 unregister_netdev(ndev);
e6b043d5 2687 fec_enet_mii_remove(fep);
6605b730 2688 del_timer_sync(&fep->time_keep);
f6a4d607
FE		 2689 if (fep->reg_phy)
2690 regulator_disable(fep->reg_phy);
6605b730
FL		 2691 if (fep->ptp_clock)
2692 ptp_clock_unregister(fep->ptp_clock);
e8fcfcd5 2693 fec_enet_clk_enable(ndev, false);
ead73183 2694 free_netdev(ndev);
28e2188e 2695
ead73183
SH		 2696 return 0;
2697}
2698
bf7bfd7f 2699#ifdef CONFIG_PM_SLEEP
ead73183 2700static int
87cad5c3 2701fec_suspend(struct device *dev)
ead73183 2702{
87cad5c3 2703 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 2704 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 2705
da1774e5 2706 rtnl_lock();
04e5216d 2707 if (netif_running(ndev)) {
d76cfae9 2708 phy_stop(fep->phy_dev);
31a6de34
RK		 2709 napi_disable(&fep->napi);
2710 netif_tx_lock_bh(ndev);
04e5216d 2711 netif_device_detach(ndev);
31a6de34
RK		 2712 netif_tx_unlock_bh(ndev);
2713 fec_stop(ndev);
ead73183 2714 }
da1774e5
RK		 2715 rtnl_unlock();
2716
e8fcfcd5 2717 fec_enet_clk_enable(ndev, false);
5bbde4d2 2718 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
04e5216d 2719
238f7bc7
FE		 2720 if (fep->reg_phy)
2721 regulator_disable(fep->reg_phy);
2722
ead73183
SH		 2723 return 0;
2724}
2725
2726static int
87cad5c3 2727fec_resume(struct device *dev)
ead73183 2728{
87cad5c3 2729 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 2730 struct fec_enet_private *fep = netdev_priv(ndev);
238f7bc7
FE		 2731 int ret;
2732
2733 if (fep->reg_phy) {
2734 ret = regulator_enable(fep->reg_phy);
2735 if (ret)
2736 return ret;
2737 }
ead73183 2738
5bbde4d2 2739 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5 2740 ret = fec_enet_clk_enable(ndev, true);
13a097bd 2741 if (ret)
e8fcfcd5 2742 goto failed_clk;
13a097bd 2743
da1774e5 2744 rtnl_lock();
04e5216d 2745 if (netif_running(ndev)) {
ef83337d 2746 fec_restart(ndev);
31a6de34 2747 netif_tx_lock_bh(ndev);
6af42d42 2748 netif_device_attach(ndev);
dbc64a8e 2749 netif_tx_unlock_bh(ndev);
6af42d42 2750 napi_enable(&fep->napi);
d76cfae9 2751 phy_start(fep->phy_dev);
ead73183 2752 }
da1774e5 2753 rtnl_unlock();
04e5216d 2754
ead73183 2755 return 0;
13a097bd 2756
e8fcfcd5 2757failed_clk:
13a097bd
FE		 2758 if (fep->reg_phy)
2759 regulator_disable(fep->reg_phy);
2760 return ret;
ead73183 2761}
bf7bfd7f 2762#endif /* CONFIG_PM_SLEEP */
ead73183 2763
bf7bfd7f 2764static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
59d4289b 2765
ead73183
SH		 2766static struct platform_driver fec_driver = {
2767 .driver = {
b5680e0b 2768 .name = DRIVER_NAME,
87cad5c3 2769 .owner = THIS_MODULE,
87cad5c3 2770 .pm = &fec_pm_ops,
ca2cc333 2771 .of_match_table = fec_dt_ids,
ead73183 2772 },
b5680e0b 2773 .id_table = fec_devtype,
87cad5c3 2774 .probe = fec_probe,
33897cc8 2775 .remove = fec_drv_remove,
ead73183
SH		 2776};
2777
aaca2377 2778module_platform_driver(fec_driver);
1da177e4 2779
f8c0aca9 2780MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 2781MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 1.291955 seconds and 5 git commands to generate.