Merge tag 'mac80211-next-for-davem-2016-06-09' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_mpc52xx.c
CommitLineData
5d031e9e
DP
1/*
2 * Driver for the MPC5200 Fast Ethernet Controller
3 *
4 * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> and
5 * now maintained by Sylvain Munaut <tnt@246tNt.com>
6 *
7 * Copyright (C) 2007 Domen Puncer, Telargo, Inc.
8 * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
9 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 *
15 */
16
31b7720c
JP
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
b7f080cf 19#include <linux/dma-mapping.h>
5d031e9e
DP
20#include <linux/module.h>
21
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/spinlock.h>
5a0e3ad6 25#include <linux/slab.h>
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DP
26#include <linux/errno.h>
27#include <linux/init.h>
a6b7a407 28#include <linux/interrupt.h>
5d031e9e
DP
29#include <linux/crc32.h>
30#include <linux/hardirq.h>
31#include <linux/delay.h>
32#include <linux/of_device.h>
ca816d98 33#include <linux/of_mdio.h>
db98f081 34#include <linux/of_net.h>
5d031e9e
DP
35#include <linux/of_platform.h>
36
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/ethtool.h>
40#include <linux/skbuff.h>
41
42#include <asm/io.h>
43#include <asm/delay.h>
44#include <asm/mpc52xx.h>
45
9a322993
PDM
46#include <linux/fsl/bestcomm/bestcomm.h>
47#include <linux/fsl/bestcomm/fec.h>
5d031e9e
DP
48
49#include "fec_mpc52xx.h"
50
51#define DRIVER_NAME "mpc52xx-fec"
52
80791be1
GL
53/* Private driver data structure */
54struct mpc52xx_fec_priv {
ca816d98 55 struct net_device *ndev;
80791be1
GL
56 int duplex;
57 int speed;
58 int r_irq;
59 int t_irq;
60 struct mpc52xx_fec __iomem *fec;
61 struct bcom_task *rx_dmatsk;
62 struct bcom_task *tx_dmatsk;
63 spinlock_t lock;
64 int msg_enable;
65
66 /* MDIO link details */
ca816d98
GL
67 unsigned int mdio_speed;
68 struct device_node *phy_node;
80791be1 69 enum phy_state link;
ca816d98 70 int seven_wire_mode;
80791be1
GL
71};
72
73
5d031e9e
DP
74static irqreturn_t mpc52xx_fec_interrupt(int, void *);
75static irqreturn_t mpc52xx_fec_rx_interrupt(int, void *);
76static irqreturn_t mpc52xx_fec_tx_interrupt(int, void *);
77static void mpc52xx_fec_stop(struct net_device *dev);
78static void mpc52xx_fec_start(struct net_device *dev);
79static void mpc52xx_fec_reset(struct net_device *dev);
80
5d031e9e 81#define MPC52xx_MESSAGES_DEFAULT ( NETIF_MSG_DRV | NETIF_MSG_PROBE | \
8b983510 82 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
5d031e9e
DP
83static int debug = -1; /* the above default */
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "debugging messages level");
86
87static void mpc52xx_fec_tx_timeout(struct net_device *dev)
88{
1e4e0767
AL
89 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
90 unsigned long flags;
91
5d031e9e
DP
92 dev_warn(&dev->dev, "transmit timed out\n");
93
1e4e0767 94 spin_lock_irqsave(&priv->lock, flags);
5d031e9e 95 mpc52xx_fec_reset(dev);
5d031e9e 96 dev->stats.tx_errors++;
1e4e0767 97 spin_unlock_irqrestore(&priv->lock, flags);
5d031e9e
DP
98
99 netif_wake_queue(dev);
100}
101
102static void mpc52xx_fec_set_paddr(struct net_device *dev, u8 *mac)
103{
104 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
105 struct mpc52xx_fec __iomem *fec = priv->fec;
106
107 out_be32(&fec->paddr1, *(u32 *)(&mac[0]));
108 out_be32(&fec->paddr2, (*(u16 *)(&mac[4]) << 16) | FEC_PADDR2_TYPE);
109}
110
5d031e9e
DP
111static int mpc52xx_fec_set_mac_address(struct net_device *dev, void *addr)
112{
113 struct sockaddr *sock = addr;
114
115 memcpy(dev->dev_addr, sock->sa_data, dev->addr_len);
116
117 mpc52xx_fec_set_paddr(dev, sock->sa_data);
118 return 0;
119}
120
121static void mpc52xx_fec_free_rx_buffers(struct net_device *dev, struct bcom_task *s)
122{
123 while (!bcom_queue_empty(s)) {
124 struct bcom_fec_bd *bd;
125 struct sk_buff *skb;
126
127 skb = bcom_retrieve_buffer(s, NULL, (struct bcom_bd **)&bd);
461cadbc
GL
128 dma_unmap_single(dev->dev.parent, bd->skb_pa, skb->len,
129 DMA_FROM_DEVICE);
5d031e9e
DP
130 kfree_skb(skb);
131 }
132}
133
1e4e0767
AL
134static void
135mpc52xx_fec_rx_submit(struct net_device *dev, struct sk_buff *rskb)
136{
137 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
138 struct bcom_fec_bd *bd;
139
140 bd = (struct bcom_fec_bd *) bcom_prepare_next_buffer(priv->rx_dmatsk);
141 bd->status = FEC_RX_BUFFER_SIZE;
142 bd->skb_pa = dma_map_single(dev->dev.parent, rskb->data,
143 FEC_RX_BUFFER_SIZE, DMA_FROM_DEVICE);
144 bcom_submit_next_buffer(priv->rx_dmatsk, rskb);
145}
146
5d031e9e
DP
147static int mpc52xx_fec_alloc_rx_buffers(struct net_device *dev, struct bcom_task *rxtsk)
148{
1e4e0767 149 struct sk_buff *skb;
5d031e9e 150
1e4e0767 151 while (!bcom_queue_full(rxtsk)) {
21a4e469 152 skb = netdev_alloc_skb(dev, FEC_RX_BUFFER_SIZE);
1e4e0767 153 if (!skb)
5d031e9e
DP
154 return -EAGAIN;
155
156 /* zero out the initial receive buffers to aid debugging */
157 memset(skb->data, 0, FEC_RX_BUFFER_SIZE);
1e4e0767 158 mpc52xx_fec_rx_submit(dev, skb);
5d031e9e 159 }
5d031e9e
DP
160 return 0;
161}
162
163/* based on generic_adjust_link from fs_enet-main.c */
164static void mpc52xx_fec_adjust_link(struct net_device *dev)
165{
166 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
a54d20f8 167 struct phy_device *phydev = dev->phydev;
5d031e9e
DP
168 int new_state = 0;
169
170 if (phydev->link != PHY_DOWN) {
171 if (phydev->duplex != priv->duplex) {
172 struct mpc52xx_fec __iomem *fec = priv->fec;
173 u32 rcntrl;
174 u32 tcntrl;
175
176 new_state = 1;
177 priv->duplex = phydev->duplex;
178
179 rcntrl = in_be32(&fec->r_cntrl);
180 tcntrl = in_be32(&fec->x_cntrl);
181
182 rcntrl &= ~FEC_RCNTRL_DRT;
183 tcntrl &= ~FEC_TCNTRL_FDEN;
184 if (phydev->duplex == DUPLEX_FULL)
185 tcntrl |= FEC_TCNTRL_FDEN; /* FD enable */
186 else
187 rcntrl |= FEC_RCNTRL_DRT; /* disable Rx on Tx (HD) */
188
189 out_be32(&fec->r_cntrl, rcntrl);
190 out_be32(&fec->x_cntrl, tcntrl);
191 }
192
193 if (phydev->speed != priv->speed) {
194 new_state = 1;
195 priv->speed = phydev->speed;
196 }
197
198 if (priv->link == PHY_DOWN) {
199 new_state = 1;
200 priv->link = phydev->link;
5d031e9e
DP
201 }
202
203 } else if (priv->link) {
204 new_state = 1;
205 priv->link = PHY_DOWN;
206 priv->speed = 0;
207 priv->duplex = -1;
5d031e9e
DP
208 }
209
210 if (new_state && netif_msg_link(priv))
211 phy_print_status(phydev);
212}
213
5d031e9e
DP
214static int mpc52xx_fec_open(struct net_device *dev)
215{
216 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
a54d20f8 217 struct phy_device *phydev = NULL;
5d031e9e
DP
218 int err = -EBUSY;
219
ca816d98 220 if (priv->phy_node) {
a54d20f8
PR
221 phydev = of_phy_connect(priv->ndev, priv->phy_node,
222 mpc52xx_fec_adjust_link, 0, 0);
223 if (!phydev) {
ca816d98
GL
224 dev_err(&dev->dev, "of_phy_connect failed\n");
225 return -ENODEV;
226 }
a54d20f8 227 phy_start(phydev);
ca816d98
GL
228 }
229
a0607fd3 230 if (request_irq(dev->irq, mpc52xx_fec_interrupt, IRQF_SHARED,
5d031e9e
DP
231 DRIVER_NAME "_ctrl", dev)) {
232 dev_err(&dev->dev, "ctrl interrupt request failed\n");
ca816d98 233 goto free_phy;
5d031e9e 234 }
a0607fd3 235 if (request_irq(priv->r_irq, mpc52xx_fec_rx_interrupt, 0,
5d031e9e
DP
236 DRIVER_NAME "_rx", dev)) {
237 dev_err(&dev->dev, "rx interrupt request failed\n");
238 goto free_ctrl_irq;
239 }
a0607fd3 240 if (request_irq(priv->t_irq, mpc52xx_fec_tx_interrupt, 0,
5d031e9e
DP
241 DRIVER_NAME "_tx", dev)) {
242 dev_err(&dev->dev, "tx interrupt request failed\n");
243 goto free_2irqs;
244 }
245
246 bcom_fec_rx_reset(priv->rx_dmatsk);
247 bcom_fec_tx_reset(priv->tx_dmatsk);
248
249 err = mpc52xx_fec_alloc_rx_buffers(dev, priv->rx_dmatsk);
250 if (err) {
251 dev_err(&dev->dev, "mpc52xx_fec_alloc_rx_buffers failed\n");
252 goto free_irqs;
253 }
254
5d031e9e
DP
255 bcom_enable(priv->rx_dmatsk);
256 bcom_enable(priv->tx_dmatsk);
257
258 mpc52xx_fec_start(dev);
259
260 netif_start_queue(dev);
261
262 return 0;
263
5d031e9e
DP
264 free_irqs:
265 free_irq(priv->t_irq, dev);
266 free_2irqs:
267 free_irq(priv->r_irq, dev);
268 free_ctrl_irq:
269 free_irq(dev->irq, dev);
ca816d98 270 free_phy:
a54d20f8
PR
271 if (phydev) {
272 phy_stop(phydev);
273 phy_disconnect(phydev);
ca816d98 274 }
5d031e9e
DP
275
276 return err;
277}
278
279static int mpc52xx_fec_close(struct net_device *dev)
280{
281 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
a54d20f8 282 struct phy_device *phydev = dev->phydev;
5d031e9e
DP
283
284 netif_stop_queue(dev);
285
286 mpc52xx_fec_stop(dev);
287
288 mpc52xx_fec_free_rx_buffers(dev, priv->rx_dmatsk);
289
290 free_irq(dev->irq, dev);
291 free_irq(priv->r_irq, dev);
292 free_irq(priv->t_irq, dev);
293
a54d20f8 294 if (phydev) {
ca816d98 295 /* power down phy */
a54d20f8
PR
296 phy_stop(phydev);
297 phy_disconnect(phydev);
ca816d98 298 }
5d031e9e
DP
299
300 return 0;
301}
302
303/* This will only be invoked if your driver is _not_ in XOFF state.
304 * What this means is that you need not check it, and that this
305 * invariant will hold if you make sure that the netif_*_queue()
306 * calls are done at the proper times.
307 */
d360009c 308static int mpc52xx_fec_start_xmit(struct sk_buff *skb, struct net_device *dev)
5d031e9e
DP
309{
310 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
311 struct bcom_fec_bd *bd;
4871953c 312 unsigned long flags;
5d031e9e
DP
313
314 if (bcom_queue_full(priv->tx_dmatsk)) {
315 if (net_ratelimit())
316 dev_err(&dev->dev, "transmit queue overrun\n");
d360009c 317 return NETDEV_TX_BUSY;
5d031e9e
DP
318 }
319
4871953c 320 spin_lock_irqsave(&priv->lock, flags);
5d031e9e
DP
321
322 bd = (struct bcom_fec_bd *)
323 bcom_prepare_next_buffer(priv->tx_dmatsk);
324
325 bd->status = skb->len | BCOM_FEC_TX_BD_TFD | BCOM_FEC_TX_BD_TC;
461cadbc
GL
326 bd->skb_pa = dma_map_single(dev->dev.parent, skb->data, skb->len,
327 DMA_TO_DEVICE);
5d031e9e 328
d6cf0732 329 skb_tx_timestamp(skb);
5d031e9e 330 bcom_submit_next_buffer(priv->tx_dmatsk, skb);
1e4e0767 331 spin_unlock_irqrestore(&priv->lock, flags);
5d031e9e
DP
332
333 if (bcom_queue_full(priv->tx_dmatsk)) {
334 netif_stop_queue(dev);
335 }
336
d360009c 337 return NETDEV_TX_OK;
5d031e9e
DP
338}
339
bd28bdb1
JS
340#ifdef CONFIG_NET_POLL_CONTROLLER
341static void mpc52xx_fec_poll_controller(struct net_device *dev)
342{
343 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
344
345 disable_irq(priv->t_irq);
346 mpc52xx_fec_tx_interrupt(priv->t_irq, dev);
347 enable_irq(priv->t_irq);
348 disable_irq(priv->r_irq);
349 mpc52xx_fec_rx_interrupt(priv->r_irq, dev);
350 enable_irq(priv->r_irq);
351}
352#endif
353
354
5d031e9e
DP
355/* This handles BestComm transmit task interrupts
356 */
357static irqreturn_t mpc52xx_fec_tx_interrupt(int irq, void *dev_id)
358{
359 struct net_device *dev = dev_id;
360 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
361
9d1e5e40 362 spin_lock(&priv->lock);
5d031e9e
DP
363 while (bcom_buffer_done(priv->tx_dmatsk)) {
364 struct sk_buff *skb;
365 struct bcom_fec_bd *bd;
366 skb = bcom_retrieve_buffer(priv->tx_dmatsk, NULL,
367 (struct bcom_bd **)&bd);
461cadbc
GL
368 dma_unmap_single(dev->dev.parent, bd->skb_pa, skb->len,
369 DMA_TO_DEVICE);
5d031e9e
DP
370
371 dev_kfree_skb_irq(skb);
372 }
9d1e5e40 373 spin_unlock(&priv->lock);
5d031e9e
DP
374
375 netif_wake_queue(dev);
376
5d031e9e
DP
377 return IRQ_HANDLED;
378}
379
380static irqreturn_t mpc52xx_fec_rx_interrupt(int irq, void *dev_id)
381{
382 struct net_device *dev = dev_id;
383 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
1e4e0767
AL
384 struct sk_buff *rskb; /* received sk_buff */
385 struct sk_buff *skb; /* new sk_buff to enqueue in its place */
386 struct bcom_fec_bd *bd;
387 u32 status, physaddr;
388 int length;
1e4e0767 389
9d1e5e40 390 spin_lock(&priv->lock);
5d031e9e
DP
391
392 while (bcom_buffer_done(priv->rx_dmatsk)) {
5d031e9e
DP
393
394 rskb = bcom_retrieve_buffer(priv->rx_dmatsk, &status,
1e4e0767
AL
395 (struct bcom_bd **)&bd);
396 physaddr = bd->skb_pa;
5d031e9e
DP
397
398 /* Test for errors in received frame */
399 if (status & BCOM_FEC_RX_BD_ERRORS) {
400 /* Drop packet and reuse the buffer */
1e4e0767 401 mpc52xx_fec_rx_submit(dev, rskb);
5d031e9e 402 dev->stats.rx_dropped++;
5d031e9e
DP
403 continue;
404 }
405
406 /* skbs are allocated on open, so now we allocate a new one,
407 * and remove the old (with the packet) */
21a4e469 408 skb = netdev_alloc_skb(dev, FEC_RX_BUFFER_SIZE);
1e4e0767 409 if (!skb) {
5d031e9e 410 /* Can't get a new one : reuse the same & drop pkt */
1e4e0767
AL
411 dev_notice(&dev->dev, "Low memory - dropped packet.\n");
412 mpc52xx_fec_rx_submit(dev, rskb);
5d031e9e 413 dev->stats.rx_dropped++;
1e4e0767 414 continue;
5d031e9e
DP
415 }
416
1e4e0767
AL
417 /* Enqueue the new sk_buff back on the hardware */
418 mpc52xx_fec_rx_submit(dev, skb);
5d031e9e 419
1e4e0767
AL
420 /* Process the received skb - Drop the spin lock while
421 * calling into the network stack */
9d1e5e40 422 spin_unlock(&priv->lock);
5d031e9e 423
1e4e0767
AL
424 dma_unmap_single(dev->dev.parent, physaddr, rskb->len,
425 DMA_FROM_DEVICE);
426 length = status & BCOM_FEC_RX_BD_LEN_MASK;
427 skb_put(rskb, length - 4); /* length without CRC32 */
1e4e0767 428 rskb->protocol = eth_type_trans(rskb, dev);
9ca3cc6f 429 if (!skb_defer_rx_timestamp(rskb))
d6cf0732 430 netif_rx(rskb);
1e4e0767 431
9d1e5e40 432 spin_lock(&priv->lock);
5d031e9e
DP
433 }
434
9d1e5e40 435 spin_unlock(&priv->lock);
1e4e0767 436
5d031e9e
DP
437 return IRQ_HANDLED;
438}
439
440static irqreturn_t mpc52xx_fec_interrupt(int irq, void *dev_id)
441{
442 struct net_device *dev = dev_id;
443 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
444 struct mpc52xx_fec __iomem *fec = priv->fec;
445 u32 ievent;
446
447 ievent = in_be32(&fec->ievent);
448
449 ievent &= ~FEC_IEVENT_MII; /* mii is handled separately */
450 if (!ievent)
451 return IRQ_NONE;
452
453 out_be32(&fec->ievent, ievent); /* clear pending events */
454
8f3ba2dc
SH
455 /* on fifo error, soft-reset fec */
456 if (ievent & (FEC_IEVENT_RFIFO_ERROR | FEC_IEVENT_XFIFO_ERROR)) {
457
458 if (net_ratelimit() && (ievent & FEC_IEVENT_RFIFO_ERROR))
459 dev_warn(&dev->dev, "FEC_IEVENT_RFIFO_ERROR\n");
460 if (net_ratelimit() && (ievent & FEC_IEVENT_XFIFO_ERROR))
461 dev_warn(&dev->dev, "FEC_IEVENT_XFIFO_ERROR\n");
462
9d1e5e40 463 spin_lock(&priv->lock);
8f3ba2dc 464 mpc52xx_fec_reset(dev);
9d1e5e40 465 spin_unlock(&priv->lock);
8f3ba2dc 466
5d031e9e
DP
467 return IRQ_HANDLED;
468 }
469
8f3ba2dc
SH
470 if (ievent & ~FEC_IEVENT_TFINT)
471 dev_dbg(&dev->dev, "ievent: %08x\n", ievent);
5d031e9e 472
5d031e9e
DP
473 return IRQ_HANDLED;
474}
475
476/*
477 * Get the current statistics.
478 * This may be called with the card open or closed.
479 */
480static struct net_device_stats *mpc52xx_fec_get_stats(struct net_device *dev)
481{
482 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
483 struct net_device_stats *stats = &dev->stats;
484 struct mpc52xx_fec __iomem *fec = priv->fec;
485
486 stats->rx_bytes = in_be32(&fec->rmon_r_octets);
487 stats->rx_packets = in_be32(&fec->rmon_r_packets);
488 stats->rx_errors = in_be32(&fec->rmon_r_crc_align) +
489 in_be32(&fec->rmon_r_undersize) +
490 in_be32(&fec->rmon_r_oversize) +
491 in_be32(&fec->rmon_r_frag) +
492 in_be32(&fec->rmon_r_jab);
493
494 stats->tx_bytes = in_be32(&fec->rmon_t_octets);
495 stats->tx_packets = in_be32(&fec->rmon_t_packets);
496 stats->tx_errors = in_be32(&fec->rmon_t_crc_align) +
497 in_be32(&fec->rmon_t_undersize) +
498 in_be32(&fec->rmon_t_oversize) +
499 in_be32(&fec->rmon_t_frag) +
500 in_be32(&fec->rmon_t_jab);
501
502 stats->multicast = in_be32(&fec->rmon_r_mc_pkt);
503 stats->collisions = in_be32(&fec->rmon_t_col);
504
505 /* detailed rx_errors: */
506 stats->rx_length_errors = in_be32(&fec->rmon_r_undersize)
507 + in_be32(&fec->rmon_r_oversize)
508 + in_be32(&fec->rmon_r_frag)
509 + in_be32(&fec->rmon_r_jab);
510 stats->rx_over_errors = in_be32(&fec->r_macerr);
511 stats->rx_crc_errors = in_be32(&fec->ieee_r_crc);
512 stats->rx_frame_errors = in_be32(&fec->ieee_r_align);
513 stats->rx_fifo_errors = in_be32(&fec->rmon_r_drop);
514 stats->rx_missed_errors = in_be32(&fec->rmon_r_drop);
515
516 /* detailed tx_errors: */
517 stats->tx_aborted_errors = 0;
518 stats->tx_carrier_errors = in_be32(&fec->ieee_t_cserr);
519 stats->tx_fifo_errors = in_be32(&fec->rmon_t_drop);
520 stats->tx_heartbeat_errors = in_be32(&fec->ieee_t_sqe);
521 stats->tx_window_errors = in_be32(&fec->ieee_t_lcol);
522
523 return stats;
524}
525
526/*
527 * Read MIB counters in order to reset them,
528 * then zero all the stats fields in memory
529 */
530static void mpc52xx_fec_reset_stats(struct net_device *dev)
531{
532 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
533 struct mpc52xx_fec __iomem *fec = priv->fec;
534
535 out_be32(&fec->mib_control, FEC_MIB_DISABLE);
cc154ac6
AV
536 memset_io(&fec->rmon_t_drop, 0,
537 offsetof(struct mpc52xx_fec, reserved10) -
538 offsetof(struct mpc52xx_fec, rmon_t_drop));
5d031e9e
DP
539 out_be32(&fec->mib_control, 0);
540
541 memset(&dev->stats, 0, sizeof(dev->stats));
542}
543
544/*
545 * Set or clear the multicast filter for this adaptor.
546 */
547static void mpc52xx_fec_set_multicast_list(struct net_device *dev)
548{
549 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
550 struct mpc52xx_fec __iomem *fec = priv->fec;
551 u32 rx_control;
552
553 rx_control = in_be32(&fec->r_cntrl);
554
555 if (dev->flags & IFF_PROMISC) {
556 rx_control |= FEC_RCNTRL_PROM;
557 out_be32(&fec->r_cntrl, rx_control);
558 } else {
559 rx_control &= ~FEC_RCNTRL_PROM;
560 out_be32(&fec->r_cntrl, rx_control);
561
562 if (dev->flags & IFF_ALLMULTI) {
563 out_be32(&fec->gaddr1, 0xffffffff);
564 out_be32(&fec->gaddr2, 0xffffffff);
565 } else {
566 u32 crc;
22bedad3 567 struct netdev_hw_addr *ha;
5d031e9e
DP
568 u32 gaddr1 = 0x00000000;
569 u32 gaddr2 = 0x00000000;
570
22bedad3
JP
571 netdev_for_each_mc_addr(ha, dev) {
572 crc = ether_crc_le(6, ha->addr) >> 26;
5d031e9e
DP
573 if (crc >= 32)
574 gaddr1 |= 1 << (crc-32);
575 else
576 gaddr2 |= 1 << crc;
5d031e9e
DP
577 }
578 out_be32(&fec->gaddr1, gaddr1);
579 out_be32(&fec->gaddr2, gaddr2);
580 }
581 }
582}
583
584/**
585 * mpc52xx_fec_hw_init
586 * @dev: network device
587 *
588 * Setup various hardware setting, only needed once on start
589 */
590static void mpc52xx_fec_hw_init(struct net_device *dev)
591{
592 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
593 struct mpc52xx_fec __iomem *fec = priv->fec;
594 int i;
595
596 /* Whack a reset. We should wait for this. */
597 out_be32(&fec->ecntrl, FEC_ECNTRL_RESET);
598 for (i = 0; i < FEC_RESET_DELAY; ++i) {
599 if ((in_be32(&fec->ecntrl) & FEC_ECNTRL_RESET) == 0)
600 break;
601 udelay(1);
602 }
603 if (i == FEC_RESET_DELAY)
604 dev_err(&dev->dev, "FEC Reset timeout!\n");
605
606 /* set pause to 0x20 frames */
607 out_be32(&fec->op_pause, FEC_OP_PAUSE_OPCODE | 0x20);
608
609 /* high service request will be deasserted when there's < 7 bytes in fifo
610 * low service request will be deasserted when there's < 4*7 bytes in fifo
611 */
612 out_be32(&fec->rfifo_cntrl, FEC_FIFO_CNTRL_FRAME | FEC_FIFO_CNTRL_LTG_7);
613 out_be32(&fec->tfifo_cntrl, FEC_FIFO_CNTRL_FRAME | FEC_FIFO_CNTRL_LTG_7);
614
615 /* alarm when <= x bytes in FIFO */
616 out_be32(&fec->rfifo_alarm, 0x0000030c);
617 out_be32(&fec->tfifo_alarm, 0x00000100);
618
619 /* begin transmittion when 256 bytes are in FIFO (or EOF or FIFO full) */
620 out_be32(&fec->x_wmrk, FEC_FIFO_WMRK_256B);
621
622 /* enable crc generation */
623 out_be32(&fec->xmit_fsm, FEC_XMIT_FSM_APPEND_CRC | FEC_XMIT_FSM_ENABLE_CRC);
624 out_be32(&fec->iaddr1, 0x00000000); /* No individual filter */
625 out_be32(&fec->iaddr2, 0x00000000); /* No individual filter */
626
627 /* set phy speed.
628 * this can't be done in phy driver, since it needs to be called
629 * before fec stuff (even on resume) */
ca816d98 630 out_be32(&fec->mii_speed, priv->mdio_speed);
5d031e9e
DP
631}
632
633/**
634 * mpc52xx_fec_start
635 * @dev: network device
636 *
637 * This function is called to start or restart the FEC during a link
638 * change. This happens on fifo errors or when switching between half
639 * and full duplex.
640 */
641static void mpc52xx_fec_start(struct net_device *dev)
642{
643 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
644 struct mpc52xx_fec __iomem *fec = priv->fec;
645 u32 rcntrl;
646 u32 tcntrl;
647 u32 tmp;
648
649 /* clear sticky error bits */
650 tmp = FEC_FIFO_STATUS_ERR | FEC_FIFO_STATUS_UF | FEC_FIFO_STATUS_OF;
651 out_be32(&fec->rfifo_status, in_be32(&fec->rfifo_status) & tmp);
652 out_be32(&fec->tfifo_status, in_be32(&fec->tfifo_status) & tmp);
653
654 /* FIFOs will reset on mpc52xx_fec_enable */
655 out_be32(&fec->reset_cntrl, FEC_RESET_CNTRL_ENABLE_IS_RESET);
656
657 /* Set station address. */
658 mpc52xx_fec_set_paddr(dev, dev->dev_addr);
659
660 mpc52xx_fec_set_multicast_list(dev);
661
662 /* set max frame len, enable flow control, select mii mode */
663 rcntrl = FEC_RX_BUFFER_SIZE << 16; /* max frame length */
664 rcntrl |= FEC_RCNTRL_FCE;
665
ca816d98 666 if (!priv->seven_wire_mode)
5d031e9e
DP
667 rcntrl |= FEC_RCNTRL_MII_MODE;
668
669 if (priv->duplex == DUPLEX_FULL)
670 tcntrl = FEC_TCNTRL_FDEN; /* FD enable */
671 else {
672 rcntrl |= FEC_RCNTRL_DRT; /* disable Rx on Tx (HD) */
673 tcntrl = 0;
674 }
675 out_be32(&fec->r_cntrl, rcntrl);
676 out_be32(&fec->x_cntrl, tcntrl);
677
678 /* Clear any outstanding interrupt. */
679 out_be32(&fec->ievent, 0xffffffff);
680
681 /* Enable interrupts we wish to service. */
682 out_be32(&fec->imask, FEC_IMASK_ENABLE);
683
684 /* And last, enable the transmit and receive processing. */
685 out_be32(&fec->ecntrl, FEC_ECNTRL_ETHER_EN);
686 out_be32(&fec->r_des_active, 0x01000000);
687}
688
689/**
690 * mpc52xx_fec_stop
691 * @dev: network device
692 *
693 * stop all activity on fec and empty dma buffers
694 */
695static void mpc52xx_fec_stop(struct net_device *dev)
696{
697 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
698 struct mpc52xx_fec __iomem *fec = priv->fec;
699 unsigned long timeout;
700
701 /* disable all interrupts */
702 out_be32(&fec->imask, 0);
703
704 /* Disable the rx task. */
705 bcom_disable(priv->rx_dmatsk);
706
707 /* Wait for tx queue to drain, but only if we're in process context */
708 if (!in_interrupt()) {
709 timeout = jiffies + msecs_to_jiffies(2000);
710 while (time_before(jiffies, timeout) &&
711 !bcom_queue_empty(priv->tx_dmatsk))
712 msleep(100);
713
714 if (time_after_eq(jiffies, timeout))
715 dev_err(&dev->dev, "queues didn't drain\n");
716#if 1
717 if (time_after_eq(jiffies, timeout)) {
718 dev_err(&dev->dev, " tx: index: %i, outdex: %i\n",
719 priv->tx_dmatsk->index,
720 priv->tx_dmatsk->outdex);
721 dev_err(&dev->dev, " rx: index: %i, outdex: %i\n",
722 priv->rx_dmatsk->index,
723 priv->rx_dmatsk->outdex);
724 }
725#endif
726 }
727
728 bcom_disable(priv->tx_dmatsk);
729
730 /* Stop FEC */
731 out_be32(&fec->ecntrl, in_be32(&fec->ecntrl) & ~FEC_ECNTRL_ETHER_EN);
5d031e9e
DP
732}
733
734/* reset fec and bestcomm tasks */
735static void mpc52xx_fec_reset(struct net_device *dev)
736{
737 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
738 struct mpc52xx_fec __iomem *fec = priv->fec;
739
740 mpc52xx_fec_stop(dev);
741
742 out_be32(&fec->rfifo_status, in_be32(&fec->rfifo_status));
743 out_be32(&fec->reset_cntrl, FEC_RESET_CNTRL_RESET_FIFO);
744
745 mpc52xx_fec_free_rx_buffers(dev, priv->rx_dmatsk);
746
747 mpc52xx_fec_hw_init(dev);
748
5d031e9e
DP
749 bcom_fec_rx_reset(priv->rx_dmatsk);
750 bcom_fec_tx_reset(priv->tx_dmatsk);
751
752 mpc52xx_fec_alloc_rx_buffers(dev, priv->rx_dmatsk);
753
754 bcom_enable(priv->rx_dmatsk);
755 bcom_enable(priv->tx_dmatsk);
756
757 mpc52xx_fec_start(dev);
1e4e0767
AL
758
759 netif_wake_queue(dev);
5d031e9e
DP
760}
761
762
763/* ethtool interface */
5d031e9e 764
5d031e9e
DP
765static u32 mpc52xx_fec_get_msglevel(struct net_device *dev)
766{
767 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
768 return priv->msg_enable;
769}
770
771static void mpc52xx_fec_set_msglevel(struct net_device *dev, u32 level)
772{
773 struct mpc52xx_fec_priv *priv = netdev_priv(dev);
774 priv->msg_enable = level;
775}
776
777static const struct ethtool_ops mpc52xx_fec_ethtool_ops = {
5d031e9e
DP
778 .get_link = ethtool_op_get_link,
779 .get_msglevel = mpc52xx_fec_get_msglevel,
780 .set_msglevel = mpc52xx_fec_set_msglevel,
0a4f2823 781 .get_ts_info = ethtool_op_get_ts_info,
b1725423
PR
782 .get_link_ksettings = phy_ethtool_get_link_ksettings,
783 .set_link_ksettings = phy_ethtool_set_link_ksettings,
5d031e9e
DP
784};
785
786
787static int mpc52xx_fec_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
788{
a54d20f8 789 struct phy_device *phydev = dev->phydev;
5d031e9e 790
a54d20f8 791 if (!phydev)
9404c82b
GL
792 return -ENOTSUPP;
793
a54d20f8 794 return phy_mii_ioctl(phydev, rq, cmd);
5d031e9e
DP
795}
796
d360009c
HS
797static const struct net_device_ops mpc52xx_fec_netdev_ops = {
798 .ndo_open = mpc52xx_fec_open,
799 .ndo_stop = mpc52xx_fec_close,
800 .ndo_start_xmit = mpc52xx_fec_start_xmit,
afc4b13d 801 .ndo_set_rx_mode = mpc52xx_fec_set_multicast_list,
d360009c
HS
802 .ndo_set_mac_address = mpc52xx_fec_set_mac_address,
803 .ndo_validate_addr = eth_validate_addr,
804 .ndo_do_ioctl = mpc52xx_fec_ioctl,
805 .ndo_change_mtu = eth_change_mtu,
806 .ndo_tx_timeout = mpc52xx_fec_tx_timeout,
807 .ndo_get_stats = mpc52xx_fec_get_stats,
808#ifdef CONFIG_NET_POLL_CONTROLLER
809 .ndo_poll_controller = mpc52xx_fec_poll_controller,
810#endif
811};
812
5d031e9e
DP
813/* ======================================================================== */
814/* OF Driver */
815/* ======================================================================== */
816
33897cc8 817static int mpc52xx_fec_probe(struct platform_device *op)
5d031e9e
DP
818{
819 int rv;
820 struct net_device *ndev;
821 struct mpc52xx_fec_priv *priv = NULL;
822 struct resource mem;
80791be1
GL
823 const u32 *prop;
824 int prop_size;
db98f081
SR
825 struct device_node *np = op->dev.of_node;
826 const char *mac_addr;
5d031e9e
DP
827
828 phys_addr_t rx_fifo;
829 phys_addr_t tx_fifo;
830
831 /* Get the ether ndev & it's private zone */
832 ndev = alloc_etherdev(sizeof(struct mpc52xx_fec_priv));
833 if (!ndev)
834 return -ENOMEM;
835
836 priv = netdev_priv(ndev);
ca816d98 837 priv->ndev = ndev;
5d031e9e
DP
838
839 /* Reserve FEC control zone */
db98f081 840 rv = of_address_to_resource(np, 0, &mem);
5d031e9e 841 if (rv) {
31b7720c 842 pr_err("Error while parsing device node resource\n");
fabc51a6 843 goto err_netdev;
5d031e9e 844 }
28f65c11 845 if (resource_size(&mem) < sizeof(struct mpc52xx_fec)) {
31b7720c 846 pr_err("invalid resource size (%lx < %x), check mpc52xx_devices.c\n",
28f65c11
JP
847 (unsigned long)resource_size(&mem),
848 sizeof(struct mpc52xx_fec));
fabc51a6
KV
849 rv = -EINVAL;
850 goto err_netdev;
5d031e9e
DP
851 }
852
fabc51a6
KV
853 if (!request_mem_region(mem.start, sizeof(struct mpc52xx_fec),
854 DRIVER_NAME)) {
855 rv = -EBUSY;
856 goto err_netdev;
857 }
5d031e9e
DP
858
859 /* Init ether ndev with what we have */
d360009c 860 ndev->netdev_ops = &mpc52xx_fec_netdev_ops;
5d031e9e 861 ndev->ethtool_ops = &mpc52xx_fec_ethtool_ops;
5d031e9e
DP
862 ndev->watchdog_timeo = FEC_WATCHDOG_TIMEOUT;
863 ndev->base_addr = mem.start;
ca816d98 864 SET_NETDEV_DEV(ndev, &op->dev);
5d031e9e
DP
865
866 spin_lock_init(&priv->lock);
867
868 /* ioremap the zones */
869 priv->fec = ioremap(mem.start, sizeof(struct mpc52xx_fec));
870
871 if (!priv->fec) {
872 rv = -ENOMEM;
fabc51a6 873 goto err_mem_region;
5d031e9e
DP
874 }
875
876 /* Bestcomm init */
877 rx_fifo = ndev->base_addr + offsetof(struct mpc52xx_fec, rfifo_data);
878 tx_fifo = ndev->base_addr + offsetof(struct mpc52xx_fec, tfifo_data);
879
880 priv->rx_dmatsk = bcom_fec_rx_init(FEC_RX_NUM_BD, rx_fifo, FEC_RX_BUFFER_SIZE);
881 priv->tx_dmatsk = bcom_fec_tx_init(FEC_TX_NUM_BD, tx_fifo);
882
883 if (!priv->rx_dmatsk || !priv->tx_dmatsk) {
31b7720c 884 pr_err("Can not init SDMA tasks\n");
5d031e9e 885 rv = -ENOMEM;
fabc51a6 886 goto err_rx_tx_dmatsk;
5d031e9e
DP
887 }
888
889 /* Get the IRQ we need one by one */
890 /* Control */
db98f081 891 ndev->irq = irq_of_parse_and_map(np, 0);
5d031e9e
DP
892
893 /* RX */
894 priv->r_irq = bcom_get_task_irq(priv->rx_dmatsk);
895
896 /* TX */
897 priv->t_irq = bcom_get_task_irq(priv->tx_dmatsk);
898
db98f081
SR
899 /*
900 * MAC address init:
901 *
902 * First try to read MAC address from DT
903 */
904 mac_addr = of_get_mac_address(np);
905 if (mac_addr) {
906 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
907 } else {
908 struct mpc52xx_fec __iomem *fec = priv->fec;
909
910 /*
911 * If the MAC addresse is not provided via DT then read
912 * it back from the controller regs
913 */
914 *(u32 *)(&ndev->dev_addr[0]) = in_be32(&fec->paddr1);
915 *(u16 *)(&ndev->dev_addr[4]) = in_be32(&fec->paddr2) >> 16;
916 }
917
918 /*
919 * Check if the MAC address is valid, if not get a random one
920 */
921 if (!is_valid_ether_addr(ndev->dev_addr)) {
922 eth_hw_addr_random(ndev);
923 dev_warn(&ndev->dev, "using random MAC address %pM\n",
924 ndev->dev_addr);
925 }
5d031e9e
DP
926
927 priv->msg_enable = netif_msg_init(debug, MPC52xx_MESSAGES_DEFAULT);
5d031e9e 928
80791be1
GL
929 /*
930 * Link mode configuration
931 */
5d031e9e 932
80791be1 933 /* Start with safe defaults for link connection */
80791be1
GL
934 priv->speed = 100;
935 priv->duplex = DUPLEX_HALF;
db98f081 936 priv->mdio_speed = ((mpc5xxx_get_bus_frequency(np) >> 20) / 5) << 1;
80791be1
GL
937
938 /* The current speed preconfigures the speed of the MII link */
db98f081 939 prop = of_get_property(np, "current-speed", &prop_size);
80791be1
GL
940 if (prop && (prop_size >= sizeof(u32) * 2)) {
941 priv->speed = prop[0];
942 priv->duplex = prop[1] ? DUPLEX_FULL : DUPLEX_HALF;
943 }
5d031e9e 944
ca816d98 945 /* If there is a phy handle, then get the PHY node */
db98f081 946 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
ca816d98
GL
947
948 /* the 7-wire property means don't use MII mode */
db98f081 949 if (of_find_property(np, "fsl,7-wire-mode", NULL)) {
ca816d98
GL
950 priv->seven_wire_mode = 1;
951 dev_info(&ndev->dev, "using 7-wire PHY mode\n");
5d031e9e
DP
952 }
953
954 /* Hardware init */
955 mpc52xx_fec_hw_init(ndev);
5d031e9e
DP
956 mpc52xx_fec_reset_stats(ndev);
957
5d031e9e
DP
958 rv = register_netdev(ndev);
959 if (rv < 0)
fabc51a6 960 goto err_node;
5d031e9e
DP
961
962 /* We're done ! */
8513fbd8 963 platform_set_drvdata(op, ndev);
31b7720c
JP
964 netdev_info(ndev, "%s MAC %pM\n",
965 op->dev.of_node->full_name, ndev->dev_addr);
5d031e9e
DP
966
967 return 0;
968
fabc51a6
KV
969err_node:
970 of_node_put(priv->phy_node);
5d031e9e 971 irq_dispose_mapping(ndev->irq);
fabc51a6 972err_rx_tx_dmatsk:
5d031e9e
DP
973 if (priv->rx_dmatsk)
974 bcom_fec_rx_release(priv->rx_dmatsk);
975 if (priv->tx_dmatsk)
976 bcom_fec_tx_release(priv->tx_dmatsk);
fabc51a6
KV
977 iounmap(priv->fec);
978err_mem_region:
5d031e9e 979 release_mem_region(mem.start, sizeof(struct mpc52xx_fec));
fabc51a6 980err_netdev:
5d031e9e
DP
981 free_netdev(ndev);
982
983 return rv;
984}
985
986static int
2dc11581 987mpc52xx_fec_remove(struct platform_device *op)
5d031e9e
DP
988{
989 struct net_device *ndev;
990 struct mpc52xx_fec_priv *priv;
991
8513fbd8 992 ndev = platform_get_drvdata(op);
5d031e9e
DP
993 priv = netdev_priv(ndev);
994
995 unregister_netdev(ndev);
996
f8e8be1c 997 of_node_put(priv->phy_node);
ca816d98
GL
998 priv->phy_node = NULL;
999
5d031e9e
DP
1000 irq_dispose_mapping(ndev->irq);
1001
1002 bcom_fec_rx_release(priv->rx_dmatsk);
1003 bcom_fec_tx_release(priv->tx_dmatsk);
1004
1005 iounmap(priv->fec);
1006
1007 release_mem_region(ndev->base_addr, sizeof(struct mpc52xx_fec));
1008
1009 free_netdev(ndev);
1010
5d031e9e
DP
1011 return 0;
1012}
1013
1014#ifdef CONFIG_PM
2dc11581 1015static int mpc52xx_fec_of_suspend(struct platform_device *op, pm_message_t state)
5d031e9e 1016{
8513fbd8 1017 struct net_device *dev = platform_get_drvdata(op);
5d031e9e
DP
1018
1019 if (netif_running(dev))
1020 mpc52xx_fec_close(dev);
1021
1022 return 0;
1023}
1024
2dc11581 1025static int mpc52xx_fec_of_resume(struct platform_device *op)
5d031e9e 1026{
8513fbd8 1027 struct net_device *dev = platform_get_drvdata(op);
5d031e9e
DP
1028
1029 mpc52xx_fec_hw_init(dev);
1030 mpc52xx_fec_reset_stats(dev);
1031
1032 if (netif_running(dev))
1033 mpc52xx_fec_open(dev);
1034
1035 return 0;
1036}
1037#endif
1038
94e5a2a8 1039static const struct of_device_id mpc52xx_fec_match[] = {
3b5ebf8e
GL
1040 { .compatible = "fsl,mpc5200b-fec", },
1041 { .compatible = "fsl,mpc5200-fec", },
1042 { .compatible = "mpc5200-fec", },
5d031e9e
DP
1043 { }
1044};
1045
1046MODULE_DEVICE_TABLE(of, mpc52xx_fec_match);
1047
74888760 1048static struct platform_driver mpc52xx_fec_driver = {
4018294b
GL
1049 .driver = {
1050 .name = DRIVER_NAME,
4018294b
GL
1051 .of_match_table = mpc52xx_fec_match,
1052 },
5d031e9e
DP
1053 .probe = mpc52xx_fec_probe,
1054 .remove = mpc52xx_fec_remove,
1055#ifdef CONFIG_PM
1056 .suspend = mpc52xx_fec_of_suspend,
1057 .resume = mpc52xx_fec_of_resume,
1058#endif
1059};
1060
1061
1062/* ======================================================================== */
1063/* Module */
1064/* ======================================================================== */
1065
8c7d3972
TR
1066static struct platform_driver * const drivers[] = {
1067#ifdef CONFIG_FEC_MPC52xx_MDIO
1068 &mpc52xx_fec_mdio_driver,
1069#endif
1070 &mpc52xx_fec_driver,
1071};
1072
5d031e9e
DP
1073static int __init
1074mpc52xx_fec_init(void)
1075{
8c7d3972 1076 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
5d031e9e
DP
1077}
1078
1079static void __exit
1080mpc52xx_fec_exit(void)
1081{
8c7d3972 1082 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
5d031e9e
DP
1083}
1084
1085
1086module_init(mpc52xx_fec_init);
1087module_exit(mpc52xx_fec_exit);
1088
1089MODULE_LICENSE("GPL");
1090MODULE_AUTHOR("Dale Farnsworth");
1091MODULE_DESCRIPTION("Ethernet driver for the Freescale MPC52xx FEC");
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