[deliverable/linux.git] / drivers / net / ethernet / freescale / fsl_pq_mdio.c

/*
 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
 * Provides Bus interface for MIIM regs
 *
 * Author: Andy Fleming <afleming@freescale.com>
 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
 *
 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
 *
 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/ucc.h>

#include "gianfar.h"

#define MIIMIND_BUSY		0x00000001
#define MIIMIND_NOTVALID	0x00000004
#define MIIMCFG_INIT_VALUE	0x00000007
#define MIIMCFG_RESET		0x80000000

#define MII_READ_COMMAND	0x00000001

struct fsl_pq_mdio {
	u8 res1[16];
	u32 ieventm;	/* MDIO Interrupt event register (for etsec2)*/
	u32 imaskm;	/* MDIO Interrupt mask register (for etsec2)*/
	u8 res2[4];
	u32 emapm;	/* MDIO Event mapping register (for etsec2)*/
	u8 res3[1280];
	u32 miimcfg;	/* MII management configuration reg */
	u32 miimcom;	/* MII management command reg */
	u32 miimadd;	/* MII management address reg */
	u32 miimcon;	/* MII management control reg */
	u32 miimstat;	/* MII management status reg */
	u32 miimind;	/* MII management indication reg */
	u8 res4[28];
	u32 utbipar;	/* TBI phy address reg (only on UCC) */
	u8 res5[2728];
} __packed;

/* Number of microseconds to wait for an MII register to respond */
#define MII_TIMEOUT	1000

struct fsl_pq_mdio_priv {
	void __iomem *map;
	struct fsl_pq_mdio __iomem *regs;
};

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus attached to the local interface, which may be different from the
 * generic mdio bus (tied to a single interface), waiting until the write is
 * done before returning. This is helpful in programming interfaces like
 * the TBI which control interfaces like onchip SERDES and are always tied to
 * the local mdio pins, which may not be the same as system mdio bus, used for
 * controlling the external PHYs, for example.
 */
static int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
		int regnum, u16 value)
{
	u32 status;

	/* Set the PHY address and the register address we want to write */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Write out the value we want */
	out_be32(&regs->miimcon, value);

	/* Wait for the transaction to finish */
	status = spin_event_timeout(!(in_be32(&regs->miimind) &	MIIMIND_BUSY),
				    MII_TIMEOUT, 0);

	return status ? 0 : -ETIMEDOUT;
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.  All PHY operation
 * done on the bus attached to the local interface,
 * which may be different from the generic mdio bus
 * This is helpful in programming interfaces like
 * the TBI which, in turn, control interfaces like onchip SERDES
 * and are always tied to the local mdio pins, which may not be the
 * same as system mdio bus, used for controlling the external PHYs, for eg.
 */
static int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
		int mii_id, int regnum)
{
	u16 value;
	u32 status;

	/* Set the PHY address and the register address we want to read */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Clear miimcom, and then initiate a read */
	out_be32(&regs->miimcom, 0);
	out_be32(&regs->miimcom, MII_READ_COMMAND);

	/* Wait for the transaction to finish, normally less than 100us */
	status = spin_event_timeout(!(in_be32(&regs->miimind) &
				    (MIIMIND_NOTVALID | MIIMIND_BUSY)),
				    MII_TIMEOUT, 0);
	if (!status)
		return -ETIMEDOUT;

	/* Grab the value of the register from miimstat */
	value = in_be32(&regs->miimstat);

	return value;
}

static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
{
	struct fsl_pq_mdio_priv *priv = bus->priv;

	return priv->regs;
}

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus, waiting until the write is done before returning.
 */
static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
		u16 value)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Write to the local MII regs */
	return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.
 */
static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Read the local MII regs */
	return fsl_pq_local_mdio_read(regs, mii_id, regnum);
}

/* Reset the MIIM registers, and wait for the bus to free */
static int fsl_pq_mdio_reset(struct mii_bus *bus)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
	u32 status;

	mutex_lock(&bus->mdio_lock);

	/* Reset the management interface */
	out_be32(&regs->miimcfg, MIIMCFG_RESET);

	/* Setup the MII Mgmt clock speed */
	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);

	/* Wait until the bus is free */
	status = spin_event_timeout(!(in_be32(&regs->miimind) &	MIIMIND_BUSY),
				    MII_TIMEOUT, 0);

	mutex_unlock(&bus->mdio_lock);

	if (!status) {
		printk(KERN_ERR "%s: The MII Bus is stuck!\n",
				bus->name);
		return -EBUSY;
	}

	return 0;
}

static void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
{
	const u32 *addr;
	u64 taddr = OF_BAD_ADDR;

	addr = of_get_address(np, 0, NULL, NULL);
	if (addr)
		taddr = of_translate_address(np, addr);

	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
		(unsigned long long)taddr);
}


static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
{
#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
	struct gfar __iomem *enet_regs;

	/*
	 * This is mildly evil, but so is our hardware for doing this.
	 * Also, we have to cast back to struct gfar because of
	 * definition weirdness done in gianfar.h.
	 */
	if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
		of_device_is_compatible(np, "fsl,gianfar-tbi") ||
		of_device_is_compatible(np, "gianfar")) {
		enet_regs = (struct gfar __iomem *)regs;
		return &enet_regs->tbipa;
	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi")) {
		return of_iomap(np, 1);
	}
#endif
	return NULL;
}


static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
{
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
	struct device_node *np = NULL;
	int err = 0;

	for_each_compatible_node(np, NULL, "ucc_geth") {
		struct resource tempres;

		err = of_address_to_resource(np, 0, &tempres);
		if (err)
			continue;

		/* if our mdio regs fall within this UCC regs range */
		if ((start >= tempres.start) && (end <= tempres.end)) {
			/* Find the id of the UCC */
			const u32 *id;

			id = of_get_property(np, "cell-index", NULL);
			if (!id) {
				id = of_get_property(np, "device-id", NULL);
				if (!id)
					continue;
			}

			*ucc_id = *id;

			return 0;
		}
	}

	if (err)
		return err;
	else
		return -EINVAL;
#else
	return -ENODEV;
#endif
}

static int fsl_pq_mdio_probe(struct platform_device *ofdev)
{
	struct device_node *np = ofdev->dev.of_node;
	struct device_node *tbi;
	struct fsl_pq_mdio_priv *priv;
	struct fsl_pq_mdio __iomem *regs = NULL;
	void __iomem *map;
	u32 __iomem *tbipa;
	struct mii_bus *new_bus;
	int tbiaddr = -1;
	const u32 *addrp;
	u64 addr = 0, size = 0;
	int err;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	new_bus = mdiobus_alloc();
	if (!new_bus) {
		err = -ENOMEM;
		goto err_free_priv;
	}

	new_bus->name = "Freescale PowerQUICC MII Bus",
	new_bus->read = &fsl_pq_mdio_read,
	new_bus->write = &fsl_pq_mdio_write,
	new_bus->reset = &fsl_pq_mdio_reset,
	new_bus->priv = priv;
	fsl_pq_mdio_bus_name(new_bus->id, np);

	addrp = of_get_address(np, 0, &size, NULL);
	if (!addrp) {
		err = -EINVAL;
		goto err_free_bus;
	}

	/* Set the PHY base address */
	addr = of_translate_address(np, addrp);
	if (addr == OF_BAD_ADDR) {
		err = -EINVAL;
		goto err_free_bus;
	}

	map = ioremap(addr, size);
	if (!map) {
		err = -ENOMEM;
		goto err_free_bus;
	}
	priv->map = map;

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy"))
		map -= offsetof(struct fsl_pq_mdio, miimcfg);
	regs = map;
	priv->regs = regs;

	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);

	if (NULL == new_bus->irq) {
		err = -ENOMEM;
		goto err_unmap_regs;
	}

	new_bus->parent = &ofdev->dev;
	dev_set_drvdata(&ofdev->dev, new_bus);

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi") ||
			of_device_is_compatible(np, "gianfar")) {
		tbipa = get_gfar_tbipa(regs, np);
		if (!tbipa) {
			err = -EINVAL;
			goto err_free_irqs;
		}
	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy")) {
		u32 id;
		static u32 mii_mng_master;

		tbipa = &regs->utbipar;

		if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
			goto err_free_irqs;

		if (!mii_mng_master) {
			mii_mng_master = id;
			ucc_set_qe_mux_mii_mng(id - 1);
		}
	} else {
		err = -ENODEV;
		goto err_free_irqs;
	}

	for_each_child_of_node(np, tbi) {
		if (!strncmp(tbi->type, "tbi-phy", 8))
			break;
	}

	if (tbi) {
		const u32 *prop = of_get_property(tbi, "reg", NULL);

		if (prop)
			tbiaddr = *prop;

		if (tbiaddr == -1) {
			err = -EBUSY;
			goto err_free_irqs;
		} else {
			out_be32(tbipa, tbiaddr);
		}
	}

	err = of_mdiobus_register(new_bus, np);
	if (err) {
		printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
				new_bus->name);
		goto err_free_irqs;
	}

	return 0;

err_free_irqs:
	kfree(new_bus->irq);
err_unmap_regs:
	iounmap(priv->map);
err_free_bus:
	kfree(new_bus);
err_free_priv:
	kfree(priv);
	return err;
}


static int fsl_pq_mdio_remove(struct platform_device *ofdev)
{
	struct device *device = &ofdev->dev;
	struct mii_bus *bus = dev_get_drvdata(device);
	struct fsl_pq_mdio_priv *priv = bus->priv;

	mdiobus_unregister(bus);

	dev_set_drvdata(device, NULL);

	iounmap(priv->map);
	bus->priv = NULL;
	mdiobus_free(bus);
	kfree(priv);

	return 0;
}

static struct of_device_id fsl_pq_mdio_match[] = {
	{
		.type = "mdio",
		.compatible = "ucc_geth_phy",
	},
	{
		.type = "mdio",
		.compatible = "gianfar",
	},
	{
		.compatible = "fsl,ucc-mdio",
	},
	{
		.compatible = "fsl,gianfar-tbi",
	},
	{
		.compatible = "fsl,gianfar-mdio",
	},
	{
		.compatible = "fsl,etsec2-tbi",
	},
	{
		.compatible = "fsl,etsec2-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);

static struct platform_driver fsl_pq_mdio_driver = {
	.driver = {
		.name = "fsl-pq_mdio",
		.owner = THIS_MODULE,
		.of_match_table = fsl_pq_mdio_match,
	},
	.probe = fsl_pq_mdio_probe,
	.remove = fsl_pq_mdio_remove,
};

module_platform_driver(fsl_pq_mdio_driver);

MODULE_LICENSE("GPL");
Commit	Line	Data
1577ecef AF	1	/*
	2	* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
	3	* Provides Bus interface for MIIM regs
	4	*
	5	* Author: Andy Fleming <afleming@freescale.com>
1d2397d7	6	* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1577ecef	7	*
1d2397d7	8	* Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
1577ecef AF	9	*
	10	* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/string.h>
	21	#include <linux/errno.h>
	22	#include <linux/unistd.h>
	23	#include <linux/slab.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/init.h>
	26	#include <linux/delay.h>
	27	#include <linux/netdevice.h>
	28	#include <linux/etherdevice.h>
	29	#include <linux/skbuff.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/mm.h>
	32	#include <linux/module.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/crc32.h>
	35	#include <linux/mii.h>
	36	#include <linux/phy.h>
	37	#include <linux/of.h>
22ae782f	38	#include <linux/of_address.h>
324931ba	39	#include <linux/of_mdio.h>
1577ecef AF	40	#include <linux/of_platform.h>
	41
	42	#include <asm/io.h>
	43	#include <asm/irq.h>
	44	#include <asm/uaccess.h>
	45	#include <asm/ucc.h>
	46
	47	#include "gianfar.h"
19bcd6c6 TT	48
	49	#define MIIMIND_BUSY 0x00000001
	50	#define MIIMIND_NOTVALID 0x00000004
	51	#define MIIMCFG_INIT_VALUE 0x00000007
	52	#define MIIMCFG_RESET 0x80000000
	53
	54	#define MII_READ_COMMAND 0x00000001
	55
	56	struct fsl_pq_mdio {
	57	u8 res1[16];
	58	u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
	59	u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
	60	u8 res2[4];
	61	u32 emapm; /* MDIO Event mapping register (for etsec2)*/
	62	u8 res3[1280];
	63	u32 miimcfg; /* MII management configuration reg */
	64	u32 miimcom; /* MII management command reg */
	65	u32 miimadd; /* MII management address reg */
	66	u32 miimcon; /* MII management control reg */
	67	u32 miimstat; /* MII management status reg */
	68	u32 miimind; /* MII management indication reg */
	69	u8 res4[28];
	70	u32 utbipar; /* TBI phy address reg (only on UCC) */
	71	u8 res5[2728];
	72	} __packed;
1577ecef	73
59399c59 TT	74	/* Number of microseconds to wait for an MII register to respond */
	75	#define MII_TIMEOUT 1000
	76
b3319b10 AV	77	struct fsl_pq_mdio_priv {
	78	void __iomem *map;
	79	struct fsl_pq_mdio __iomem *regs;
	80	};
	81
1577ecef AF	82	/*
	83	* Write value to the PHY at mii_id at register regnum,
	84	* on the bus attached to the local interface, which may be different from the
	85	* generic mdio bus (tied to a single interface), waiting until the write is
	86	* done before returning. This is helpful in programming interfaces like
	87	* the TBI which control interfaces like onchip SERDES and are always tied to
	88	* the local mdio pins, which may not be the same as system mdio bus, used for
	89	* controlling the external PHYs, for example.
	90	*/
19bcd6c6	91	static int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
1577ecef AF	92	int regnum, u16 value)
1577ecef AF	93	{
59399c59 TT	94	u32 status;
59399c59 TT	95
1577ecef AF	96	/* Set the PHY address and the register address we want to write */
	97	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	98
	99	/* Write out the value we want */
	100	out_be32(&regs->miimcon, value);
	101
	102	/* Wait for the transaction to finish */
59399c59 TT	103	status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
59399c59 TT	104	MII_TIMEOUT, 0);
1577ecef	105
59399c59	106	return status ? 0 : -ETIMEDOUT;
1577ecef AF	107	}
	108
	109	/*
	110	* Read the bus for PHY at addr mii_id, register regnum, and
	111	* return the value. Clears miimcom first. All PHY operation
	112	* done on the bus attached to the local interface,
	113	* which may be different from the generic mdio bus
	114	* This is helpful in programming interfaces like
	115	* the TBI which, in turn, control interfaces like onchip SERDES
	116	* and are always tied to the local mdio pins, which may not be the
	117	* same as system mdio bus, used for controlling the external PHYs, for eg.
	118	*/
19bcd6c6	119	static int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
1577ecef AF	120	int mii_id, int regnum)
	121	{
	122	u16 value;
59399c59	123	u32 status;
1577ecef AF	124
	125	/* Set the PHY address and the register address we want to read */
	126	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	127
	128	/* Clear miimcom, and then initiate a read */
	129	out_be32(&regs->miimcom, 0);
	130	out_be32(&regs->miimcom, MII_READ_COMMAND);
	131
59399c59 TT	132	/* Wait for the transaction to finish, normally less than 100us */
	133	status = spin_event_timeout(!(in_be32(&regs->miimind) &
	134	(MIIMIND_NOTVALID \| MIIMIND_BUSY)),
	135	MII_TIMEOUT, 0);
	136	if (!status)
	137	return -ETIMEDOUT;
1577ecef AF	138
	139	/* Grab the value of the register from miimstat */
	140	value = in_be32(&regs->miimstat);
	141
	142	return value;
	143	}
	144
6748f60b AV	145	static struct fsl_pq_mdio __iomem fsl_pq_mdio_get_regs(struct mii_bus bus)
6748f60b AV	146	{
b3319b10 AV	147	struct fsl_pq_mdio_priv *priv = bus->priv;
	148
	149	return priv->regs;
6748f60b AV	150	}
6748f60b AV	151
1577ecef AF	152	/*
	153	* Write value to the PHY at mii_id at register regnum,
	154	* on the bus, waiting until the write is done before returning.
	155	*/
19bcd6c6 TT	156	static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
19bcd6c6 TT	157	u16 value)
1577ecef	158	{
6748f60b	159	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	160
1577ecef AF	161	/* Write to the local MII regs */
807540ba	162	return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
1577ecef AF	163	}
	164
	165	/*
	166	* Read the bus for PHY at addr mii_id, register regnum, and
	167	* return the value. Clears miimcom first.
	168	*/
19bcd6c6	169	static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1577ecef	170	{
6748f60b	171	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	172
1577ecef AF	173	/* Read the local MII regs */
807540ba	174	return fsl_pq_local_mdio_read(regs, mii_id, regnum);
1577ecef AF	175	}
	176
	177	/* Reset the MIIM registers, and wait for the bus to free */
	178	static int fsl_pq_mdio_reset(struct mii_bus *bus)
	179	{
6748f60b	180	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
59399c59	181	u32 status;
1577ecef AF	182
	183	mutex_lock(&bus->mdio_lock);
	184
	185	/* Reset the management interface */
	186	out_be32(&regs->miimcfg, MIIMCFG_RESET);
	187
	188	/* Setup the MII Mgmt clock speed */
	189	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
	190
	191	/* Wait until the bus is free */
59399c59 TT	192	status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
59399c59 TT	193	MII_TIMEOUT, 0);
1577ecef AF	194
	195	mutex_unlock(&bus->mdio_lock);
	196
59399c59	197	if (!status) {
1577ecef AF	198	printk(KERN_ERR "%s: The MII Bus is stuck!\n",
	199	bus->name);
	200	return -EBUSY;
	201	}
	202
	203	return 0;
	204	}
	205
19bcd6c6	206	static void fsl_pq_mdio_bus_name(char name, struct device_node np)
1577ecef	207	{
18f27383 AV	208	const u32 *addr;
18f27383 AV	209	u64 taddr = OF_BAD_ADDR;
1577ecef	210
18f27383 AV	211	addr = of_get_address(np, 0, NULL, NULL);
	212	if (addr)
	213	taddr = of_translate_address(np, addr);
1577ecef	214
18f27383 AV	215	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
18f27383 AV	216	(unsigned long long)taddr);
1577ecef AF	217	}
1577ecef AF	218
1577ecef	219
1d2397d7	220	static u32 __iomem get_gfar_tbipa(struct fsl_pq_mdio __iomem regs, struct device_node *np)
1577ecef	221	{
952c5ca1	222	#if defined(CONFIG_GIANFAR) \|\| defined(CONFIG_GIANFAR_MODULE)
1577ecef AF	223	struct gfar __iomem *enet_regs;
	224
	225	/*
	226	* This is mildly evil, but so is our hardware for doing this.
	227	* Also, we have to cast back to struct gfar because of
	228	* definition weirdness done in gianfar.h.
	229	*/
1d2397d7 SG	230	if(of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	231	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	232	of_device_is_compatible(np, "gianfar")) {
	233	enet_regs = (struct gfar __iomem *)regs;
	234	return &enet_regs->tbipa;
	235	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
	236	of_device_is_compatible(np, "fsl,etsec2-tbi")) {
3b1fd3e5	237	return of_iomap(np, 1);
952c5ca1	238	}
1577ecef	239	#endif
952c5ca1 AF	240	return NULL;
952c5ca1 AF	241	}
1577ecef AF	242
1577ecef AF	243
1577ecef AF	244	static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
1577ecef AF	245	{
952c5ca1	246	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_UCC_GETH_MODULE)
1577ecef AF	247	struct device_node *np = NULL;
	248	int err = 0;
	249
	250	for_each_compatible_node(np, NULL, "ucc_geth") {
	251	struct resource tempres;
	252
	253	err = of_address_to_resource(np, 0, &tempres);
	254	if (err)
	255	continue;
	256
	257	/* if our mdio regs fall within this UCC regs range */
	258	if ((start >= tempres.start) && (end <= tempres.end)) {
	259	/* Find the id of the UCC */
	260	const u32 *id;
	261
	262	id = of_get_property(np, "cell-index", NULL);
	263	if (!id) {
	264	id = of_get_property(np, "device-id", NULL);
	265	if (!id)
	266	continue;
	267	}
	268
	269	ucc_id = id;
	270
	271	return 0;
	272	}
	273	}
	274
	275	if (err)
	276	return err;
	277	else
	278	return -EINVAL;
952c5ca1 AF	279	#else
952c5ca1 AF	280	return -ENODEV;
1577ecef	281	#endif
952c5ca1	282	}
1577ecef	283
74888760	284	static int fsl_pq_mdio_probe(struct platform_device *ofdev)
1577ecef	285	{
61c7a080	286	struct device_node *np = ofdev->dev.of_node;
1577ecef	287	struct device_node *tbi;
b3319b10	288	struct fsl_pq_mdio_priv *priv;
1d2397d7	289	struct fsl_pq_mdio __iomem *regs = NULL;
2951d64e	290	void __iomem *map;
1577ecef AF	291	u32 __iomem *tbipa;
	292	struct mii_bus *new_bus;
	293	int tbiaddr = -1;
3b1fd3e5	294	const u32 *addrp;
2951d64e	295	u64 addr = 0, size = 0;
08d18f3b	296	int err;
1577ecef	297
b3319b10 AV	298	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	299	if (!priv)
	300	return -ENOMEM;
	301
1577ecef	302	new_bus = mdiobus_alloc();
08d18f3b AV	303	if (!new_bus) {
08d18f3b AV	304	err = -ENOMEM;
b3319b10	305	goto err_free_priv;
08d18f3b	306	}
1577ecef AF	307
	308	new_bus->name = "Freescale PowerQUICC MII Bus",
	309	new_bus->read = &fsl_pq_mdio_read,
	310	new_bus->write = &fsl_pq_mdio_write,
	311	new_bus->reset = &fsl_pq_mdio_reset,
b3319b10	312	new_bus->priv = priv;
1577ecef AF	313	fsl_pq_mdio_bus_name(new_bus->id, np);
1577ecef AF	314
3b1fd3e5 AV	315	addrp = of_get_address(np, 0, &size, NULL);
	316	if (!addrp) {
	317	err = -EINVAL;
	318	goto err_free_bus;
	319	}
	320
1577ecef	321	/* Set the PHY base address */
3b1fd3e5 AV	322	addr = of_translate_address(np, addrp);
	323	if (addr == OF_BAD_ADDR) {
	324	err = -EINVAL;
	325	goto err_free_bus;
	326	}
	327
2951d64e AV	328	map = ioremap(addr, size);
2951d64e AV	329	if (!map) {
1577ecef AF	330	err = -ENOMEM;
	331	goto err_free_bus;
	332	}
b3319b10	333	priv->map = map;
1577ecef	334
2951d64e AV	335	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	336	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	337	of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	338	of_device_is_compatible(np, "ucc_geth_phy"))
	339	map -= offsetof(struct fsl_pq_mdio, miimcfg);
	340	regs = map;
b3319b10	341	priv->regs = regs;
1577ecef	342
324931ba	343	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1577ecef AF	344
	345	if (NULL == new_bus->irq) {
	346	err = -ENOMEM;
	347	goto err_unmap_regs;
	348	}
	349
	350	new_bus->parent = &ofdev->dev;
	351	dev_set_drvdata(&ofdev->dev, new_bus);
	352
	353	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
30196845	354	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
1d2397d7 SG	355	of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
1d2397d7 SG	356	of_device_is_compatible(np, "fsl,etsec2-tbi") \|\|
1577ecef	357	of_device_is_compatible(np, "gianfar")) {
1d2397d7 SG	358	tbipa = get_gfar_tbipa(regs, np);
	359	if (!tbipa) {
	360	err = -EINVAL;
	361	goto err_free_irqs;
	362	}
1577ecef AF	363	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
1577ecef AF	364	of_device_is_compatible(np, "ucc_geth_phy")) {
1577ecef	365	u32 id;
fbcc0e2c	366	static u32 mii_mng_master;
1577ecef AF	367
	368	tbipa = &regs->utbipar;
	369
	370	if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
	371	goto err_free_irqs;
	372
fbcc0e2c HW	373	if (!mii_mng_master) {
	374	mii_mng_master = id;
	375	ucc_set_qe_mux_mii_mng(id - 1);
	376	}
1577ecef AF	377	} else {
	378	err = -ENODEV;
	379	goto err_free_irqs;
	380	}
	381
	382	for_each_child_of_node(np, tbi) {
	383	if (!strncmp(tbi->type, "tbi-phy", 8))
	384	break;
	385	}
	386
	387	if (tbi) {
	388	const u32 *prop = of_get_property(tbi, "reg", NULL);
	389
	390	if (prop)
	391	tbiaddr = *prop;
1577ecef	392
464b57da KE	393	if (tbiaddr == -1) {
	394	err = -EBUSY;
	395	goto err_free_irqs;
	396	} else {
	397	out_be32(tbipa, tbiaddr);
	398	}
1577ecef AF	399	}
1577ecef AF	400
324931ba	401	err = of_mdiobus_register(new_bus, np);
1577ecef AF	402	if (err) {
	403	printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
	404	new_bus->name);
	405	goto err_free_irqs;
	406	}
	407
	408	return 0;
	409
	410	err_free_irqs:
	411	kfree(new_bus->irq);
	412	err_unmap_regs:
b3319b10	413	iounmap(priv->map);
1577ecef AF	414	err_free_bus:
1577ecef AF	415	kfree(new_bus);
b3319b10 AV	416	err_free_priv:
b3319b10 AV	417	kfree(priv);
1577ecef AF	418	return err;
	419	}
	420
	421
2dc11581	422	static int fsl_pq_mdio_remove(struct platform_device *ofdev)
1577ecef AF	423	{
	424	struct device *device = &ofdev->dev;
	425	struct mii_bus *bus = dev_get_drvdata(device);
b3319b10	426	struct fsl_pq_mdio_priv *priv = bus->priv;
1577ecef AF	427
	428	mdiobus_unregister(bus);
	429
	430	dev_set_drvdata(device, NULL);
	431
b3319b10	432	iounmap(priv->map);
1577ecef AF	433	bus->priv = NULL;
1577ecef AF	434	mdiobus_free(bus);
b3319b10	435	kfree(priv);
1577ecef AF	436
	437	return 0;
	438	}
	439
	440	static struct of_device_id fsl_pq_mdio_match[] = {
	441	{
	442	.type = "mdio",
	443	.compatible = "ucc_geth_phy",
	444	},
	445	{
	446	.type = "mdio",
	447	.compatible = "gianfar",
	448	},
	449	{
	450	.compatible = "fsl,ucc-mdio",
	451	},
	452	{
	453	.compatible = "fsl,gianfar-tbi",
	454	},
	455	{
	456	.compatible = "fsl,gianfar-mdio",
	457	},
1d2397d7 SG	458	{
	459	.compatible = "fsl,etsec2-tbi",
	460	},
	461	{
	462	.compatible = "fsl,etsec2-mdio",
	463	},
1577ecef AF	464	{},
1577ecef AF	465	};
e72701ac	466	MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
1577ecef	467
74888760	468	static struct platform_driver fsl_pq_mdio_driver = {
4018294b GL	469	.driver = {
	470	.name = "fsl-pq_mdio",
	471	.owner = THIS_MODULE,
	472	.of_match_table = fsl_pq_mdio_match,
	473	},
1577ecef AF	474	.probe = fsl_pq_mdio_probe,
1577ecef AF	475	.remove = fsl_pq_mdio_remove,
1577ecef AF	476	};
1577ecef AF	477
db62f684	478	module_platform_driver(fsl_pq_mdio_driver);
1577ecef	479
26062897	480	MODULE_LICENSE("GPL");