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fe2ddfb5 BA |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
f5e261e6 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
fe2ddfb5 BA |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include "e1000.h" | |
30 | ||
31 | enum e1000_mng_mode { | |
32 | e1000_mng_mode_none = 0, | |
33 | e1000_mng_mode_asf, | |
34 | e1000_mng_mode_pt, | |
35 | e1000_mng_mode_ipmi, | |
36 | e1000_mng_mode_host_if_only | |
37 | }; | |
38 | ||
39 | #define E1000_FACTPS_MNGCG 0x20000000 | |
40 | ||
41 | /* Intel(R) Active Management Technology signature */ | |
42 | #define E1000_IAMT_SIGNATURE 0x544D4149 | |
43 | ||
44 | /** | |
45 | * e1000_calculate_checksum - Calculate checksum for buffer | |
46 | * @buffer: pointer to EEPROM | |
47 | * @length: size of EEPROM to calculate a checksum for | |
48 | * | |
49 | * Calculates the checksum for some buffer on a specified length. The | |
50 | * checksum calculated is returned. | |
51 | **/ | |
52 | static u8 e1000_calculate_checksum(u8 *buffer, u32 length) | |
53 | { | |
54 | u32 i; | |
55 | u8 sum = 0; | |
56 | ||
57 | if (!buffer) | |
58 | return 0; | |
59 | ||
60 | for (i = 0; i < length; i++) | |
61 | sum += buffer[i]; | |
62 | ||
63 | return (u8)(0 - sum); | |
64 | } | |
65 | ||
66 | /** | |
67 | * e1000_mng_enable_host_if - Checks host interface is enabled | |
68 | * @hw: pointer to the HW structure | |
69 | * | |
70 | * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND | |
71 | * | |
72 | * This function checks whether the HOST IF is enabled for command operation | |
73 | * and also checks whether the previous command is completed. It busy waits | |
74 | * in case of previous command is not completed. | |
75 | **/ | |
76 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) | |
77 | { | |
78 | u32 hicr; | |
79 | u8 i; | |
80 | ||
668018d7 | 81 | if (!hw->mac.arc_subsystem_valid) { |
fe2ddfb5 BA |
82 | e_dbg("ARC subsystem not valid.\n"); |
83 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
84 | } | |
85 | ||
86 | /* Check that the host interface is enabled. */ | |
87 | hicr = er32(HICR); | |
04499ec4 | 88 | if (!(hicr & E1000_HICR_EN)) { |
fe2ddfb5 BA |
89 | e_dbg("E1000_HOST_EN bit disabled.\n"); |
90 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
91 | } | |
92 | /* check the previous command is completed */ | |
93 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | |
94 | hicr = er32(HICR); | |
95 | if (!(hicr & E1000_HICR_C)) | |
96 | break; | |
97 | mdelay(1); | |
98 | } | |
99 | ||
100 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { | |
101 | e_dbg("Previous command timeout failed .\n"); | |
102 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
103 | } | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
108 | /** | |
48768329 | 109 | * e1000e_check_mng_mode_generic - Generic check management mode |
fe2ddfb5 BA |
110 | * @hw: pointer to the HW structure |
111 | * | |
112 | * Reads the firmware semaphore register and returns true (>0) if | |
113 | * manageability is enabled, else false (0). | |
114 | **/ | |
115 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw) | |
116 | { | |
117 | u32 fwsm = er32(FWSM); | |
118 | ||
119 | return (fwsm & E1000_FWSM_MODE_MASK) == | |
120 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); | |
121 | } | |
122 | ||
123 | /** | |
124 | * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx | |
125 | * @hw: pointer to the HW structure | |
126 | * | |
127 | * Enables packet filtering on transmit packets if manageability is enabled | |
128 | * and host interface is enabled. | |
129 | **/ | |
130 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |
131 | { | |
132 | struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; | |
133 | u32 *buffer = (u32 *)&hw->mng_cookie; | |
134 | u32 offset; | |
135 | s32 ret_val, hdr_csum, csum; | |
136 | u8 i, len; | |
137 | ||
138 | hw->mac.tx_pkt_filtering = true; | |
139 | ||
140 | /* No manageability, no filtering */ | |
48768329 | 141 | if (!hw->mac.ops.check_mng_mode(hw)) { |
fe2ddfb5 | 142 | hw->mac.tx_pkt_filtering = false; |
5015e53a | 143 | return hw->mac.tx_pkt_filtering; |
fe2ddfb5 BA |
144 | } |
145 | ||
146 | /* | |
147 | * If we can't read from the host interface for whatever | |
148 | * reason, disable filtering. | |
149 | */ | |
150 | ret_val = e1000_mng_enable_host_if(hw); | |
151 | if (ret_val) { | |
152 | hw->mac.tx_pkt_filtering = false; | |
5015e53a | 153 | return hw->mac.tx_pkt_filtering; |
fe2ddfb5 BA |
154 | } |
155 | ||
156 | /* Read in the header. Length and offset are in dwords. */ | |
157 | len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; | |
158 | offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; | |
159 | for (i = 0; i < len; i++) | |
160 | *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, | |
161 | offset + i); | |
162 | hdr_csum = hdr->checksum; | |
163 | hdr->checksum = 0; | |
164 | csum = e1000_calculate_checksum((u8 *)hdr, | |
165 | E1000_MNG_DHCP_COOKIE_LENGTH); | |
166 | /* | |
167 | * If either the checksums or signature don't match, then | |
168 | * the cookie area isn't considered valid, in which case we | |
169 | * take the safe route of assuming Tx filtering is enabled. | |
170 | */ | |
171 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { | |
172 | hw->mac.tx_pkt_filtering = true; | |
5015e53a | 173 | return hw->mac.tx_pkt_filtering; |
fe2ddfb5 BA |
174 | } |
175 | ||
176 | /* Cookie area is valid, make the final check for filtering. */ | |
5015e53a | 177 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) |
fe2ddfb5 | 178 | hw->mac.tx_pkt_filtering = false; |
fe2ddfb5 | 179 | |
fe2ddfb5 BA |
180 | return hw->mac.tx_pkt_filtering; |
181 | } | |
182 | ||
183 | /** | |
184 | * e1000_mng_write_cmd_header - Writes manageability command header | |
185 | * @hw: pointer to the HW structure | |
186 | * @hdr: pointer to the host interface command header | |
187 | * | |
188 | * Writes the command header after does the checksum calculation. | |
189 | **/ | |
190 | static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, | |
191 | struct e1000_host_mng_command_header *hdr) | |
192 | { | |
193 | u16 i, length = sizeof(struct e1000_host_mng_command_header); | |
194 | ||
195 | /* Write the whole command header structure with new checksum. */ | |
196 | ||
197 | hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); | |
198 | ||
199 | length >>= 2; | |
200 | /* Write the relevant command block into the ram area. */ | |
201 | for (i = 0; i < length; i++) { | |
202 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i)); | |
203 | e1e_flush(); | |
204 | } | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | /** | |
210 | * e1000_mng_host_if_write - Write to the manageability host interface | |
211 | * @hw: pointer to the HW structure | |
212 | * @buffer: pointer to the host interface buffer | |
213 | * @length: size of the buffer | |
214 | * @offset: location in the buffer to write to | |
215 | * @sum: sum of the data (not checksum) | |
216 | * | |
217 | * This function writes the buffer content at the offset given on the host if. | |
218 | * It also does alignment considerations to do the writes in most efficient | |
219 | * way. Also fills up the sum of the buffer in *buffer parameter. | |
220 | **/ | |
221 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, | |
222 | u16 length, u16 offset, u8 *sum) | |
223 | { | |
224 | u8 *tmp; | |
225 | u8 *bufptr = buffer; | |
226 | u32 data = 0; | |
227 | u16 remaining, i, j, prev_bytes; | |
228 | ||
229 | /* sum = only sum of the data and it is not checksum */ | |
230 | ||
231 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) | |
232 | return -E1000_ERR_PARAM; | |
233 | ||
234 | tmp = (u8 *)&data; | |
235 | prev_bytes = offset & 0x3; | |
236 | offset >>= 2; | |
237 | ||
238 | if (prev_bytes) { | |
239 | data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset); | |
240 | for (j = prev_bytes; j < sizeof(u32); j++) { | |
241 | *(tmp + j) = *bufptr++; | |
242 | *sum += *(tmp + j); | |
243 | } | |
244 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data); | |
245 | length -= j - prev_bytes; | |
246 | offset++; | |
247 | } | |
248 | ||
249 | remaining = length & 0x3; | |
250 | length -= remaining; | |
251 | ||
252 | /* Calculate length in DWORDs */ | |
253 | length >>= 2; | |
254 | ||
255 | /* | |
256 | * The device driver writes the relevant command block into the | |
257 | * ram area. | |
258 | */ | |
259 | for (i = 0; i < length; i++) { | |
260 | for (j = 0; j < sizeof(u32); j++) { | |
261 | *(tmp + j) = *bufptr++; | |
262 | *sum += *(tmp + j); | |
263 | } | |
264 | ||
265 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); | |
266 | } | |
267 | if (remaining) { | |
268 | for (j = 0; j < sizeof(u32); j++) { | |
269 | if (j < remaining) | |
270 | *(tmp + j) = *bufptr++; | |
271 | else | |
272 | *(tmp + j) = 0; | |
273 | ||
274 | *sum += *(tmp + j); | |
275 | } | |
276 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); | |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | /** | |
283 | * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface | |
284 | * @hw: pointer to the HW structure | |
285 | * @buffer: pointer to the host interface | |
286 | * @length: size of the buffer | |
287 | * | |
288 | * Writes the DHCP information to the host interface. | |
289 | **/ | |
290 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) | |
291 | { | |
292 | struct e1000_host_mng_command_header hdr; | |
293 | s32 ret_val; | |
294 | u32 hicr; | |
295 | ||
296 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | |
297 | hdr.command_length = length; | |
298 | hdr.reserved1 = 0; | |
299 | hdr.reserved2 = 0; | |
300 | hdr.checksum = 0; | |
301 | ||
302 | /* Enable the host interface */ | |
303 | ret_val = e1000_mng_enable_host_if(hw); | |
304 | if (ret_val) | |
305 | return ret_val; | |
306 | ||
307 | /* Populate the host interface with the contents of "buffer". */ | |
308 | ret_val = e1000_mng_host_if_write(hw, buffer, length, | |
309 | sizeof(hdr), &(hdr.checksum)); | |
310 | if (ret_val) | |
311 | return ret_val; | |
312 | ||
313 | /* Write the manageability command header */ | |
314 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | |
315 | if (ret_val) | |
316 | return ret_val; | |
317 | ||
318 | /* Tell the ARC a new command is pending. */ | |
319 | hicr = er32(HICR); | |
320 | ew32(HICR, hicr | E1000_HICR_C); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /** | |
326 | * e1000e_enable_mng_pass_thru - Check if management passthrough is needed | |
327 | * @hw: pointer to the HW structure | |
328 | * | |
329 | * Verifies the hardware needs to leave interface enabled so that frames can | |
330 | * be directed to and from the management interface. | |
331 | **/ | |
332 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) | |
333 | { | |
334 | u32 manc; | |
335 | u32 fwsm, factps; | |
fe2ddfb5 BA |
336 | |
337 | manc = er32(MANC); | |
338 | ||
339 | if (!(manc & E1000_MANC_RCV_TCO_EN)) | |
5015e53a | 340 | return false; |
fe2ddfb5 BA |
341 | |
342 | if (hw->mac.has_fwsm) { | |
343 | fwsm = er32(FWSM); | |
344 | factps = er32(FACTPS); | |
345 | ||
346 | if (!(factps & E1000_FACTPS_MNGCG) && | |
347 | ((fwsm & E1000_FWSM_MODE_MASK) == | |
5015e53a BA |
348 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) |
349 | return true; | |
fe2ddfb5 BA |
350 | } else if ((hw->mac.type == e1000_82574) || |
351 | (hw->mac.type == e1000_82583)) { | |
352 | u16 data; | |
353 | ||
354 | factps = er32(FACTPS); | |
355 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
356 | ||
357 | if (!(factps & E1000_FACTPS_MNGCG) && | |
358 | ((data & E1000_NVM_INIT_CTRL2_MNGM) == | |
5015e53a BA |
359 | (e1000_mng_mode_pt << 13))) |
360 | return true; | |
fe2ddfb5 BA |
361 | } else if ((manc & E1000_MANC_SMBUS_EN) && |
362 | !(manc & E1000_MANC_ASF_EN)) { | |
5015e53a | 363 | return true; |
fe2ddfb5 BA |
364 | } |
365 | ||
5015e53a | 366 | return false; |
fe2ddfb5 | 367 | } |