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net: vlan: prepare for 802.1ad support
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
bc7f75fa
AK		 45#include <linux/ethtool.h>
46#include <linux/if_vlan.h>
47#include <linux/cpu.h>
48#include <linux/smp.h>
e8db0be1 49#include <linux/pm_qos.h>
23606cf5 50#include <linux/pm_runtime.h>
111b9dc5 51#include <linux/aer.h>
70c71606 52#include <linux/prefetch.h>
bc7f75fa
AK		 53
54#include "e1000.h"
55
b3ccf267 56#define DRV_EXTRAVERSION "-k"
c14c643b 57
8defe713 58#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 59char e1000e_driver_name[] = "e1000e";
60const char e1000e_driver_version[] = DRV_VERSION;
61
b3f4d599 62#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
63static int debug = -1;
64module_param(debug, int, 0);
65MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
66
78cd29d5
BA		 67static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
68
bc7f75fa
AK		 69static const struct e1000_info *e1000_info_tbl[] = {
70 [board_82571] = &e1000_82571_info,
71 [board_82572] = &e1000_82572_info,
72 [board_82573] = &e1000_82573_info,
4662e82b 73 [board_82574] = &e1000_82574_info,
8c81c9c3 74 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 75 [board_80003es2lan] = &e1000_es2_info,
76 [board_ich8lan] = &e1000_ich8_info,
77 [board_ich9lan] = &e1000_ich9_info,
f4187b56 78 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 79 [board_pchlan] = &e1000_pch_info,
d3738bb8 80 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 81 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
84f4ee90 89static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 90 /* General Registers */
91 {E1000_CTRL, "CTRL"},
92 {E1000_STATUS, "STATUS"},
93 {E1000_CTRL_EXT, "CTRL_EXT"},
94
95 /* Interrupt Registers */
96 {E1000_ICR, "ICR"},
97
af667a29 98 /* Rx Registers */
84f4ee90 99 {E1000_RCTL, "RCTL"},
1e36052e
BA		 100 {E1000_RDLEN(0), "RDLEN"},
101 {E1000_RDH(0), "RDH"},
102 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 103 {E1000_RDTR, "RDTR"},
104 {E1000_RXDCTL(0), "RXDCTL"},
105 {E1000_ERT, "ERT"},
1e36052e
BA		 106 {E1000_RDBAL(0), "RDBAL"},
107 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 108 {E1000_RDFH, "RDFH"},
109 {E1000_RDFT, "RDFT"},
110 {E1000_RDFHS, "RDFHS"},
111 {E1000_RDFTS, "RDFTS"},
112 {E1000_RDFPC, "RDFPC"},
113
af667a29 114 /* Tx Registers */
84f4ee90 115 {E1000_TCTL, "TCTL"},
1e36052e
BA		 116 {E1000_TDBAL(0), "TDBAL"},
117 {E1000_TDBAH(0), "TDBAH"},
118 {E1000_TDLEN(0), "TDLEN"},
119 {E1000_TDH(0), "TDH"},
120 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 121 {E1000_TIDV, "TIDV"},
122 {E1000_TXDCTL(0), "TXDCTL"},
123 {E1000_TADV, "TADV"},
124 {E1000_TARC(0), "TARC"},
125 {E1000_TDFH, "TDFH"},
126 {E1000_TDFT, "TDFT"},
127 {E1000_TDFHS, "TDFHS"},
128 {E1000_TDFTS, "TDFTS"},
129 {E1000_TDFPC, "TDFPC"},
130
131 /* List Terminator */
f36bb6ca 132 {0, NULL}
84f4ee90
TI		 133};
134
e921eb1a 135/**
84f4ee90 136 * e1000_regdump - register printout routine
e921eb1a
BA		 137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
84f4ee90
TI		 140static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
141{
142 int n = 0;
143 char rname[16];
144 u32 regs[8];
145
146 switch (reginfo->ofs) {
147 case E1000_RXDCTL(0):
148 for (n = 0; n < 2; n++)
149 regs[n] = __er32(hw, E1000_RXDCTL(n));
150 break;
151 case E1000_TXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_TXDCTL(n));
154 break;
155 case E1000_TARC(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TARC(n));
158 break;
159 default:
ef456f85
JK		 160 pr_info("%-15s %08x\n",
161 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 162 return;
163 }
164
165 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 166 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 167}
168
f0c5dadf
ET		 169static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
170 struct e1000_buffer *bi)
171{
172 int i;
173 struct e1000_ps_page *ps_page;
174
175 for (i = 0; i < adapter->rx_ps_pages; i++) {
176 ps_page = &bi->ps_pages[i];
177
178 if (ps_page->page) {
179 pr_info("packet dump for ps_page %d:\n", i);
180 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
181 16, 1, page_address(ps_page->page),
182 PAGE_SIZE, true);
183 }
184 }
185}
186
e921eb1a 187/**
af667a29 188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 189 * @adapter: board private structure
190 **/
84f4ee90
TI		 191static void e1000e_dump(struct e1000_adapter *adapter)
192{
193 struct net_device *netdev = adapter->netdev;
194 struct e1000_hw *hw = &adapter->hw;
195 struct e1000_reg_info *reginfo;
196 struct e1000_ring *tx_ring = adapter->tx_ring;
197 struct e1000_tx_desc *tx_desc;
af667a29 198 struct my_u0 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
af667a29 201 } *u0;
84f4ee90
TI		 202 struct e1000_buffer *buffer_info;
203 struct e1000_ring *rx_ring = adapter->rx_ring;
204 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 205 union e1000_rx_desc_extended *rx_desc;
af667a29 206 struct my_u1 {
e885d762
BA		 207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
af667a29 211 } *u1;
84f4ee90
TI		 212 u32 staterr;
213 int i = 0;
214
215 if (!netif_msg_hw(adapter))
216 return;
217
218 /* Print netdevice Info */
219 if (netdev) {
220 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 221 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 222 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
223 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 224 }
225
226 /* Print Registers */
227 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 228 pr_info(" Register Name Value\n");
84f4ee90
TI		 229 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
230 reginfo->name; reginfo++) {
231 e1000_regdump(hw, reginfo);
232 }
233
af667a29 234 /* Print Tx Ring Summary */
84f4ee90 235 if (!netdev || !netif_running(netdev))
fe1e980f 236 return;
84f4ee90 237
af667a29 238 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 239 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 240 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 241 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
242 0, tx_ring->next_to_use, tx_ring->next_to_clean,
243 (unsigned long long)buffer_info->dma,
244 buffer_info->length,
245 buffer_info->next_to_watch,
246 (unsigned long long)buffer_info->time_stamp);
84f4ee90 247
af667a29 248 /* Print Tx Ring */
84f4ee90
TI		 249 if (!netif_msg_tx_done(adapter))
250 goto rx_ring_summary;
251
af667a29 252 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 253
254 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
255 *
256 * Legacy Transmit Descriptor
257 * +--------------------------------------------------------------+
258 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
259 * +--------------------------------------------------------------+
260 * 8 | Special | CSS | Status | CMD | CSO | Length |
261 * +--------------------------------------------------------------+
262 * 63 48 47 36 35 32 31 24 23 16 15 0
263 *
264 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
265 * 63 48 47 40 39 32 31 16 15 8 7 0
266 * +----------------------------------------------------------------+
267 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
268 * +----------------------------------------------------------------+
269 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
270 * +----------------------------------------------------------------+
271 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
272 *
273 * Extended Data Descriptor (DTYP=0x1)
274 * +----------------------------------------------------------------+
275 * 0 | Buffer Address [63:0] |
276 * +----------------------------------------------------------------+
277 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
278 * +----------------------------------------------------------------+
279 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
280 */
ef456f85
JK		 281 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
282 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
283 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 284 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 285 const char *next_desc;
84f4ee90
TI		 286 tx_desc = E1000_TX_DESC(*tx_ring, i);
287 buffer_info = &tx_ring->buffer_info[i];
288 u0 = (struct my_u0 *)tx_desc;
84f4ee90 289 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 290 next_desc = " NTC/U";
84f4ee90 291 else if (i == tx_ring->next_to_use)
ef456f85 292 next_desc = " NTU";
84f4ee90 293 else if (i == tx_ring->next_to_clean)
ef456f85 294 next_desc = " NTC";
84f4ee90 295 else
ef456f85
JK		 296 next_desc = "";
297 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
298 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
299 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
300 i,
301 (unsigned long long)le64_to_cpu(u0->a),
302 (unsigned long long)le64_to_cpu(u0->b),
303 (unsigned long long)buffer_info->dma,
304 buffer_info->length, buffer_info->next_to_watch,
305 (unsigned long long)buffer_info->time_stamp,
306 buffer_info->skb, next_desc);
84f4ee90 307
f0c5dadf 308 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 309 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 310 16, 1, buffer_info->skb->data,
311 buffer_info->skb->len, true);
84f4ee90
TI		 312 }
313
af667a29 314 /* Print Rx Ring Summary */
84f4ee90 315rx_ring_summary:
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 317 pr_info("Queue [NTU] [NTC]\n");
318 pr_info(" %5d %5X %5X\n",
319 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 320
af667a29 321 /* Print Rx Ring */
84f4ee90 322 if (!netif_msg_rx_status(adapter))
fe1e980f 323 return;
84f4ee90 324
af667a29 325 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 326 switch (adapter->rx_ps_pages) {
327 case 1:
328 case 2:
329 case 3:
330 /* [Extended] Packet Split Receive Descriptor Format
331 *
332 * +-----------------------------------------------------+
333 * 0 | Buffer Address 0 [63:0] |
334 * +-----------------------------------------------------+
335 * 8 | Buffer Address 1 [63:0] |
336 * +-----------------------------------------------------+
337 * 16 | Buffer Address 2 [63:0] |
338 * +-----------------------------------------------------+
339 * 24 | Buffer Address 3 [63:0] |
340 * +-----------------------------------------------------+
341 */
ef456f85 342 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 343 /* [Extended] Receive Descriptor (Write-Back) Format
344 *
345 * 63 48 47 32 31 13 12 8 7 4 3 0
346 * +------------------------------------------------------+
347 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
348 * | Checksum | Ident | | Queue | | Type |
349 * +------------------------------------------------------+
350 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
351 * +------------------------------------------------------+
352 * 63 48 47 32 31 20 19 0
353 */
ef456f85 354 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 355 for (i = 0; i < rx_ring->count; i++) {
ef456f85 356 const char *next_desc;
84f4ee90
TI		 357 buffer_info = &rx_ring->buffer_info[i];
358 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
359 u1 = (struct my_u1 *)rx_desc_ps;
360 staterr =
af667a29 361 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 362
363 if (i == rx_ring->next_to_use)
364 next_desc = " NTU";
365 else if (i == rx_ring->next_to_clean)
366 next_desc = " NTC";
367 else
368 next_desc = "";
369
84f4ee90
TI		 370 if (staterr & E1000_RXD_STAT_DD) {
371 /* Descriptor Done */
ef456f85
JK		 372 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
373 "RWB", i,
374 (unsigned long long)le64_to_cpu(u1->a),
375 (unsigned long long)le64_to_cpu(u1->b),
376 (unsigned long long)le64_to_cpu(u1->c),
377 (unsigned long long)le64_to_cpu(u1->d),
378 buffer_info->skb, next_desc);
84f4ee90 379 } else {
ef456f85
JK		 380 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
381 "R ", i,
382 (unsigned long long)le64_to_cpu(u1->a),
383 (unsigned long long)le64_to_cpu(u1->b),
384 (unsigned long long)le64_to_cpu(u1->c),
385 (unsigned long long)le64_to_cpu(u1->d),
386 (unsigned long long)buffer_info->dma,
387 buffer_info->skb, next_desc);
84f4ee90
TI		 388
389 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 390 e1000e_dump_ps_pages(adapter,
391 buffer_info);
84f4ee90 392 }
84f4ee90
TI		 393 }
394 break;
395 default:
396 case 0:
5f450212 397 /* Extended Receive Descriptor (Read) Format
84f4ee90 398 *
5f450212
BA		 399 * +-----------------------------------------------------+
400 * 0 | Buffer Address [63:0] |
401 * +-----------------------------------------------------+
402 * 8 | Reserved |
403 * +-----------------------------------------------------+
84f4ee90 404 */
ef456f85 405 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 406 /* Extended Receive Descriptor (Write-Back) Format
407 *
408 * 63 48 47 32 31 24 23 4 3 0
409 * +------------------------------------------------------+
410 * | RSS Hash | | | |
411 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
412 * | Packet | IP | | | Type |
413 * | Checksum | Ident | | | |
414 * +------------------------------------------------------+
415 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
416 * +------------------------------------------------------+
417 * 63 48 47 32 31 20 19 0
418 */
ef456f85 419 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 420
421 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 422 const char *next_desc;
423
84f4ee90 424 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 425 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
426 u1 = (struct my_u1 *)rx_desc;
427 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 428
429 if (i == rx_ring->next_to_use)
430 next_desc = " NTU";
431 else if (i == rx_ring->next_to_clean)
432 next_desc = " NTC";
433 else
434 next_desc = "";
435
5f450212
BA		 436 if (staterr & E1000_RXD_STAT_DD) {
437 /* Descriptor Done */
ef456f85
JK		 438 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
439 "RWB", i,
440 (unsigned long long)le64_to_cpu(u1->a),
441 (unsigned long long)le64_to_cpu(u1->b),
442 buffer_info->skb, next_desc);
5f450212 443 } else {
ef456f85
JK		 444 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
445 "R ", i,
446 (unsigned long long)le64_to_cpu(u1->a),
447 (unsigned long long)le64_to_cpu(u1->b),
448 (unsigned long long)buffer_info->dma,
449 buffer_info->skb, next_desc);
5f450212 450
f0c5dadf
ET		 451 if (netif_msg_pktdata(adapter) &&
452 buffer_info->skb)
5f450212
BA		 453 print_hex_dump(KERN_INFO, "",
454 DUMP_PREFIX_ADDRESS, 16,
455 1,
f0c5dadf 456 buffer_info->skb->data,
5f450212
BA		 457 adapter->rx_buffer_len,
458 true);
459 }
84f4ee90
TI		 460 }
461 }
84f4ee90
TI		 462}
463
bc7f75fa
AK		 464/**
465 * e1000_desc_unused - calculate if we have unused descriptors
466 **/
467static int e1000_desc_unused(struct e1000_ring *ring)
468{
469 if (ring->next_to_clean > ring->next_to_use)
470 return ring->next_to_clean - ring->next_to_use - 1;
471
472 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
473}
474
b67e1913
BA		 475/**
476 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
477 * @adapter: board private structure
478 * @hwtstamps: time stamp structure to update
479 * @systim: unsigned 64bit system time value.
480 *
481 * Convert the system time value stored in the RX/TXSTMP registers into a
482 * hwtstamp which can be used by the upper level time stamping functions.
483 *
484 * The 'systim_lock' spinlock is used to protect the consistency of the
485 * system time value. This is needed because reading the 64 bit time
486 * value involves reading two 32 bit registers. The first read latches the
487 * value.
488 **/
489static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
490 struct skb_shared_hwtstamps *hwtstamps,
491 u64 systim)
492{
493 u64 ns;
494 unsigned long flags;
495
496 spin_lock_irqsave(&adapter->systim_lock, flags);
497 ns = timecounter_cyc2time(&adapter->tc, systim);
498 spin_unlock_irqrestore(&adapter->systim_lock, flags);
499
500 memset(hwtstamps, 0, sizeof(*hwtstamps));
501 hwtstamps->hwtstamp = ns_to_ktime(ns);
502}
503
504/**
505 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
506 * @adapter: board private structure
507 * @status: descriptor extended error and status field
508 * @skb: particular skb to include time stamp
509 *
510 * If the time stamp is valid, convert it into the timecounter ns value
511 * and store that result into the shhwtstamps structure which is passed
512 * up the network stack.
513 **/
514static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
515 struct sk_buff *skb)
516{
517 struct e1000_hw *hw = &adapter->hw;
518 u64 rxstmp;
519
520 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
521 !(status & E1000_RXDEXT_STATERR_TST) ||
522 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
523 return;
524
525 /* The Rx time stamp registers contain the time stamp. No other
526 * received packet will be time stamped until the Rx time stamp
527 * registers are read. Because only one packet can be time stamped
528 * at a time, the register values must belong to this packet and
529 * therefore none of the other additional attributes need to be
530 * compared.
531 */
532 rxstmp = (u64)er32(RXSTMPL);
533 rxstmp |= (u64)er32(RXSTMPH) << 32;
534 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
535
536 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
537}
538
bc7f75fa 539/**
ad68076e 540 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 541 * @adapter: board private structure
b67e1913 542 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 543 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
544 * @skb: pointer to sk_buff to be indicated to stack
545 **/
546static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 547 struct net_device *netdev, struct sk_buff *skb,
b67e1913 548 u32 staterr, __le16 vlan)
bc7f75fa 549{
86d70e53 550 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 551
552 e1000e_rx_hwtstamp(adapter, staterr, skb);
553
bc7f75fa
AK		 554 skb->protocol = eth_type_trans(skb, netdev);
555
b67e1913 556 if (staterr & E1000_RXD_STAT_VP)
86d70e53
JK		 557 __vlan_hwaccel_put_tag(skb, tag);
558
559 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 560}
561
562/**
af667a29 563 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 564 * @adapter: board private structure
565 * @status_err: receive descriptor status and error fields
566 * @csum: receive descriptor csum field
567 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 568 **/
569static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 570 struct sk_buff *skb)
bc7f75fa
AK		 571{
572 u16 status = (u16)status_err;
573 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 574
575 skb_checksum_none_assert(skb);
bc7f75fa 576
afd12939
BA		 577 /* Rx checksum disabled */
578 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
579 return;
580
bc7f75fa
AK		 581 /* Ignore Checksum bit is set */
582 if (status & E1000_RXD_STAT_IXSM)
583 return;
afd12939 584
2e1706f2
BA		 585 /* TCP/UDP checksum error bit or IP checksum error bit is set */
586 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 587 /* let the stack verify checksum errors */
588 adapter->hw_csum_err++;
589 return;
590 }
591
592 /* TCP/UDP Checksum has not been calculated */
593 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
594 return;
595
596 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 597 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 598 adapter->hw_csum_good++;
599}
600
55aa6985 601static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 602{
55aa6985 603 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 604 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 605 s32 ret_val = __ew32_prepare(hw);
606
607 writel(i, rx_ring->tail);
c6e7f51e 608
bdc125f7 609 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 610 u32 rctl = er32(RCTL);
611 ew32(RCTL, rctl & ~E1000_RCTL_EN);
612 e_err("ME firmware caused invalid RDT - resetting\n");
613 schedule_work(&adapter->reset_task);
614 }
615}
616
55aa6985 617static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 618{
55aa6985 619 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 620 struct e1000_hw *hw = &adapter->hw;
bdc125f7 621 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 622
bdc125f7
BA		 623 writel(i, tx_ring->tail);
624
625 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 626 u32 tctl = er32(TCTL);
627 ew32(TCTL, tctl & ~E1000_TCTL_EN);
628 e_err("ME firmware caused invalid TDT - resetting\n");
629 schedule_work(&adapter->reset_task);
630 }
631}
632
bc7f75fa 633/**
5f450212 634 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 635 * @rx_ring: Rx descriptor ring
bc7f75fa 636 **/
55aa6985 637static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 638 int cleaned_count, gfp_t gfp)
bc7f75fa 639{
55aa6985 640 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 641 struct net_device *netdev = adapter->netdev;
642 struct pci_dev *pdev = adapter->pdev;
5f450212 643 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 644 struct e1000_buffer *buffer_info;
645 struct sk_buff *skb;
646 unsigned int i;
89d71a66 647 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 648
649 i = rx_ring->next_to_use;
650 buffer_info = &rx_ring->buffer_info[i];
651
652 while (cleaned_count--) {
653 skb = buffer_info->skb;
654 if (skb) {
655 skb_trim(skb, 0);
656 goto map_skb;
657 }
658
c2fed996 659 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 660 if (!skb) {
661 /* Better luck next round */
662 adapter->alloc_rx_buff_failed++;
663 break;
664 }
665
bc7f75fa
AK		 666 buffer_info->skb = skb;
667map_skb:
0be3f55f 668 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 669 adapter->rx_buffer_len,
0be3f55f
NN		 670 DMA_FROM_DEVICE);
671 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 672 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 673 adapter->rx_dma_failed++;
674 break;
675 }
676
5f450212
BA		 677 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
678 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 679
50849d79 680 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 681 /* Force memory writes to complete before letting h/w
50849d79
TH		 682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
c6e7f51e 687 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 688 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 689 else
c5083cf6 690 writel(i, rx_ring->tail);
50849d79 691 }
bc7f75fa
AK		 692 i++;
693 if (i == rx_ring->count)
694 i = 0;
695 buffer_info = &rx_ring->buffer_info[i];
696 }
697
50849d79 698 rx_ring->next_to_use = i;
bc7f75fa
AK		 699}
700
701/**
702 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 703 * @rx_ring: Rx descriptor ring
bc7f75fa 704 **/
55aa6985 705static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 706 int cleaned_count, gfp_t gfp)
bc7f75fa 707{
55aa6985 708 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 709 struct net_device *netdev = adapter->netdev;
710 struct pci_dev *pdev = adapter->pdev;
711 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 712 struct e1000_buffer *buffer_info;
713 struct e1000_ps_page *ps_page;
714 struct sk_buff *skb;
715 unsigned int i, j;
716
717 i = rx_ring->next_to_use;
718 buffer_info = &rx_ring->buffer_info[i];
719
720 while (cleaned_count--) {
721 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
722
723 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 724 ps_page = &buffer_info->ps_pages[j];
725 if (j >= adapter->rx_ps_pages) {
726 /* all unused desc entries get hw null ptr */
af667a29
BA		 727 rx_desc->read.buffer_addr[j + 1] =
728 ~cpu_to_le64(0);
47f44e40
AK		 729 continue;
730 }
731 if (!ps_page->page) {
c2fed996 732 ps_page->page = alloc_page(gfp);
bc7f75fa 733 if (!ps_page->page) {
47f44e40
AK		 734 adapter->alloc_rx_buff_failed++;
735 goto no_buffers;
736 }
0be3f55f
NN		 737 ps_page->dma = dma_map_page(&pdev->dev,
738 ps_page->page,
739 0, PAGE_SIZE,
740 DMA_FROM_DEVICE);
741 if (dma_mapping_error(&pdev->dev,
742 ps_page->dma)) {
47f44e40 743 dev_err(&adapter->pdev->dev,
af667a29 744 "Rx DMA page map failed\n");
47f44e40
AK		 745 adapter->rx_dma_failed++;
746 goto no_buffers;
bc7f75fa 747 }
bc7f75fa 748 }
e921eb1a 749 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 750 * didn't change because each write-back
751 * erases this info.
752 */
af667a29
BA		 753 rx_desc->read.buffer_addr[j + 1] =
754 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 755 }
756
e5fe2541 757 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 758 gfp);
bc7f75fa
AK		 759
760 if (!skb) {
761 adapter->alloc_rx_buff_failed++;
762 break;
763 }
764
bc7f75fa 765 buffer_info->skb = skb;
0be3f55f 766 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 767 adapter->rx_ps_bsize0,
0be3f55f
NN		 768 DMA_FROM_DEVICE);
769 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 770 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 771 adapter->rx_dma_failed++;
772 /* cleanup skb */
773 dev_kfree_skb_any(skb);
774 buffer_info->skb = NULL;
775 break;
776 }
777
778 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
779
50849d79 780 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 781 /* Force memory writes to complete before letting h/w
50849d79
TH		 782 * know there are new descriptors to fetch. (Only
783 * applicable for weak-ordered memory model archs,
784 * such as IA-64).
785 */
786 wmb();
c6e7f51e 787 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 788 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 789 else
c5083cf6 790 writel(i << 1, rx_ring->tail);
50849d79
TH		 791 }
792
bc7f75fa
AK		 793 i++;
794 if (i == rx_ring->count)
795 i = 0;
796 buffer_info = &rx_ring->buffer_info[i];
797 }
798
799no_buffers:
50849d79 800 rx_ring->next_to_use = i;
bc7f75fa
AK		 801}
802
97ac8cae
BA		 803/**
804 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 805 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 806 * @cleaned_count: number of buffers to allocate this pass
807 **/
808
55aa6985 809static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 810 int cleaned_count, gfp_t gfp)
97ac8cae 811{
55aa6985 812 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 813 struct net_device *netdev = adapter->netdev;
814 struct pci_dev *pdev = adapter->pdev;
5f450212 815 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 816 struct e1000_buffer *buffer_info;
817 struct sk_buff *skb;
818 unsigned int i;
2a2293b9 819 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 820
821 i = rx_ring->next_to_use;
822 buffer_info = &rx_ring->buffer_info[i];
823
824 while (cleaned_count--) {
825 skb = buffer_info->skb;
826 if (skb) {
827 skb_trim(skb, 0);
828 goto check_page;
829 }
830
c2fed996 831 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 832 if (unlikely(!skb)) {
833 /* Better luck next round */
834 adapter->alloc_rx_buff_failed++;
835 break;
836 }
837
97ac8cae
BA		 838 buffer_info->skb = skb;
839check_page:
840 /* allocate a new page if necessary */
841 if (!buffer_info->page) {
c2fed996 842 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 843 if (unlikely(!buffer_info->page)) {
844 adapter->alloc_rx_buff_failed++;
845 break;
846 }
847 }
848
37287fae 849 if (!buffer_info->dma) {
0be3f55f 850 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 851 buffer_info->page, 0,
852 PAGE_SIZE,
0be3f55f 853 DMA_FROM_DEVICE);
37287fae
CP		 854 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
855 adapter->alloc_rx_buff_failed++;
856 break;
857 }
858 }
97ac8cae 859
5f450212
BA		 860 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
861 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 862
863 if (unlikely(++i == rx_ring->count))
864 i = 0;
865 buffer_info = &rx_ring->buffer_info[i];
866 }
867
868 if (likely(rx_ring->next_to_use != i)) {
869 rx_ring->next_to_use = i;
870 if (unlikely(i-- == 0))
871 i = (rx_ring->count - 1);
872
873 /* Force memory writes to complete before letting h/w
874 * know there are new descriptors to fetch. (Only
875 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 876 * such as IA-64).
877 */
97ac8cae 878 wmb();
c6e7f51e 879 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 880 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 881 else
c5083cf6 882 writel(i, rx_ring->tail);
97ac8cae
BA		 883 }
884}
885
70495a50
BA		 886static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
887 struct sk_buff *skb)
888{
889 if (netdev->features & NETIF_F_RXHASH)
890 skb->rxhash = le32_to_cpu(rss);
891}
892
bc7f75fa 893/**
55aa6985
BA		 894 * e1000_clean_rx_irq - Send received data up the network stack
895 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 896 *
897 * the return value indicates whether actual cleaning was done, there
898 * is no guarantee that everything was cleaned
899 **/
55aa6985
BA		 900static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
901 int work_to_do)
bc7f75fa 902{
55aa6985 903 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 904 struct net_device *netdev = adapter->netdev;
905 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 906 struct e1000_hw *hw = &adapter->hw;
5f450212 907 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 908 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 909 u32 length, staterr;
bc7f75fa
AK		 910 unsigned int i;
911 int cleaned_count = 0;
3db1cd5c 912 bool cleaned = false;
bc7f75fa
AK		 913 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
914
915 i = rx_ring->next_to_clean;
5f450212
BA		 916 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
917 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 918 buffer_info = &rx_ring->buffer_info[i];
919
5f450212 920 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 921 struct sk_buff *skb;
bc7f75fa
AK		 922
923 if (*work_done >= work_to_do)
924 break;
925 (*work_done)++;
2d0bb1c1 926 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 927
bc7f75fa
AK		 928 skb = buffer_info->skb;
929 buffer_info->skb = NULL;
930
931 prefetch(skb->data - NET_IP_ALIGN);
932
933 i++;
934 if (i == rx_ring->count)
935 i = 0;
5f450212 936 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 937 prefetch(next_rxd);
938
939 next_buffer = &rx_ring->buffer_info[i];
940
3db1cd5c 941 cleaned = true;
bc7f75fa 942 cleaned_count++;
e5fe2541
BA		 943 dma_unmap_single(&pdev->dev, buffer_info->dma,
944 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 945 buffer_info->dma = 0;
946
5f450212 947 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 948
e921eb1a 949 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 950 * packet, if that's the case we need to toss it. In fact, we
951 * need to toss every packet with the EOP bit clear and the
952 * next frame that _does_ have the EOP bit set, as it is by
953 * definition only a frame fragment
954 */
5f450212 955 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 956 adapter->flags2 |= FLAG2_IS_DISCARDING;
957
958 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 959 /* All receives must fit into a single buffer */
3bb99fe2 960 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 961 /* recycle */
962 buffer_info->skb = skb;
5f450212 963 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 964 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 965 goto next_desc;
966 }
967
cf955e6c
BG		 968 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
969 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 970 /* recycle */
971 buffer_info->skb = skb;
972 goto next_desc;
973 }
974
eb7c3adb 975 /* adjust length to remove Ethernet CRC */
0184039a
BG		 976 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
977 /* If configured to store CRC, don't subtract FCS,
978 * but keep the FCS bytes out of the total_rx_bytes
979 * counter
980 */
981 if (netdev->features & NETIF_F_RXFCS)
982 total_rx_bytes -= 4;
983 else
984 length -= 4;
985 }
eb7c3adb 986
bc7f75fa
AK		 987 total_rx_bytes += length;
988 total_rx_packets++;
989
e921eb1a 990 /* code added for copybreak, this should improve
bc7f75fa 991 * performance for small packets with large amounts
ad68076e
BA		 992 * of reassembly being done in the stack
993 */
bc7f75fa
AK		 994 if (length < copybreak) {
995 struct sk_buff *new_skb =
89d71a66 996 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 997 if (new_skb) {
808ff676
BA		 998 skb_copy_to_linear_data_offset(new_skb,
999 -NET_IP_ALIGN,
1000 (skb->data -
1001 NET_IP_ALIGN),
1002 (length +
1003 NET_IP_ALIGN));
bc7f75fa
AK		 1004 /* save the skb in buffer_info as good */
1005 buffer_info->skb = skb;
1006 skb = new_skb;
1007 }
1008 /* else just continue with the old one */
1009 }
1010 /* end copybreak code */
1011 skb_put(skb, length);
1012
1013 /* Receive Checksum Offload */
2e1706f2 1014 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1015
70495a50
BA		 1016 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1017
5f450212
BA		 1018 e1000_receive_skb(adapter, netdev, skb, staterr,
1019 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1020
1021next_desc:
5f450212 1022 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1023
1024 /* return some buffers to hardware, one at a time is too slow */
1025 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1026 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1027 GFP_ATOMIC);
bc7f75fa
AK		 1028 cleaned_count = 0;
1029 }
1030
1031 /* use prefetched values */
1032 rx_desc = next_rxd;
1033 buffer_info = next_buffer;
5f450212
BA		 1034
1035 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1036 }
1037 rx_ring->next_to_clean = i;
1038
1039 cleaned_count = e1000_desc_unused(rx_ring);
1040 if (cleaned_count)
55aa6985 1041 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1042
bc7f75fa 1043 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1044 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1045 return cleaned;
1046}
1047
55aa6985
BA		 1048static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1049 struct e1000_buffer *buffer_info)
bc7f75fa 1050{
55aa6985
BA		 1051 struct e1000_adapter *adapter = tx_ring->adapter;
1052
03b1320d
AD		 1053 if (buffer_info->dma) {
1054 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1055 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1056 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1057 else
0be3f55f
NN		 1058 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1059 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1060 buffer_info->dma = 0;
1061 }
bc7f75fa
AK		 1062 if (buffer_info->skb) {
1063 dev_kfree_skb_any(buffer_info->skb);
1064 buffer_info->skb = NULL;
1065 }
1b7719c4 1066 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1067}
1068
41cec6f1 1069static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1070{
41cec6f1 1071 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1072 struct e1000_adapter,
1073 print_hang_task);
09357b00 1074 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1075 struct e1000_ring *tx_ring = adapter->tx_ring;
1076 unsigned int i = tx_ring->next_to_clean;
1077 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1078 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1079 struct e1000_hw *hw = &adapter->hw;
1080 u16 phy_status, phy_1000t_status, phy_ext_status;
1081 u16 pci_status;
1082
615b32af
JB		 1083 if (test_bit(__E1000_DOWN, &adapter->state))
1084 return;
1085
e5fe2541 1086 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1087 /* May be block on write-back, flush and detect again
09357b00
JK		 1088 * flush pending descriptor writebacks to memory
1089 */
1090 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1091 /* execute the writes immediately */
1092 e1e_flush();
e921eb1a 1093 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1094 * the write is successful
1095 */
1096 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1097 /* execute the writes immediately */
1098 e1e_flush();
09357b00
JK		 1099 adapter->tx_hang_recheck = true;
1100 return;
1101 }
1102 /* Real hang detected */
1103 adapter->tx_hang_recheck = false;
1104 netif_stop_queue(netdev);
1105
c2ade1a4
BA		 1106 e1e_rphy(hw, MII_BMSR, &phy_status);
1107 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1108 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1109
41cec6f1
BA		 1110 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1111
1112 /* detected Hardware unit hang */
1113 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1114 " TDH <%x>\n"
1115 " TDT <%x>\n"
1116 " next_to_use <%x>\n"
1117 " next_to_clean <%x>\n"
1118 "buffer_info[next_to_clean]:\n"
1119 " time_stamp <%lx>\n"
1120 " next_to_watch <%x>\n"
1121 " jiffies <%lx>\n"
41cec6f1
BA		 1122 " next_to_watch.status <%x>\n"
1123 "MAC Status <%x>\n"
1124 "PHY Status <%x>\n"
1125 "PHY 1000BASE-T Status <%x>\n"
1126 "PHY Extended Status <%x>\n"
1127 "PCI Status <%x>\n",
e5fe2541
BA		 1128 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1129 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1130 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1131 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee
BA		 1132
1133 /* Suggest workaround for known h/w issue */
1134 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1135 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1136}
1137
b67e1913
BA		 1138/**
1139 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1140 * @work: pointer to work struct
1141 *
1142 * This work function polls the TSYNCTXCTL valid bit to determine when a
1143 * timestamp has been taken for the current stored skb. The timestamp must
1144 * be for this skb because only one such packet is allowed in the queue.
1145 */
1146static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1147{
1148 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1149 tx_hwtstamp_work);
1150 struct e1000_hw *hw = &adapter->hw;
1151
1152 if (!adapter->tx_hwtstamp_skb)
1153 return;
1154
1155 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1156 struct skb_shared_hwtstamps shhwtstamps;
1157 u64 txstmp;
1158
1159 txstmp = er32(TXSTMPL);
1160 txstmp |= (u64)er32(TXSTMPH) << 32;
1161
1162 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1163
1164 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1165 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1166 adapter->tx_hwtstamp_skb = NULL;
1167 } else {
1168 /* reschedule to check later */
1169 schedule_work(&adapter->tx_hwtstamp_work);
1170 }
1171}
1172
bc7f75fa
AK		 1173/**
1174 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1175 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1176 *
1177 * the return value indicates whether actual cleaning was done, there
1178 * is no guarantee that everything was cleaned
1179 **/
55aa6985 1180static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1181{
55aa6985 1182 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1183 struct net_device *netdev = adapter->netdev;
1184 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1185 struct e1000_tx_desc *tx_desc, *eop_desc;
1186 struct e1000_buffer *buffer_info;
1187 unsigned int i, eop;
1188 unsigned int count = 0;
bc7f75fa 1189 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1190 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1191
1192 i = tx_ring->next_to_clean;
1193 eop = tx_ring->buffer_info[i].next_to_watch;
1194 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1195
12d04a3c
AD		 1196 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1197 (count < tx_ring->count)) {
a86043c2 1198 bool cleaned = false;
2d0bb1c1 1199 rmb(); /* read buffer_info after eop_desc */
a86043c2 1200 for (; !cleaned; count++) {
bc7f75fa
AK		 1201 tx_desc = E1000_TX_DESC(*tx_ring, i);
1202 buffer_info = &tx_ring->buffer_info[i];
1203 cleaned = (i == eop);
1204
1205 if (cleaned) {
9ed318d5
TH		 1206 total_tx_packets += buffer_info->segs;
1207 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1208 if (buffer_info->skb) {
1209 bytes_compl += buffer_info->skb->len;
1210 pkts_compl++;
1211 }
bc7f75fa
AK		 1212 }
1213
55aa6985 1214 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1215 tx_desc->upper.data = 0;
1216
1217 i++;
1218 if (i == tx_ring->count)
1219 i = 0;
1220 }
1221
dac87619
TL		 1222 if (i == tx_ring->next_to_use)
1223 break;
bc7f75fa
AK		 1224 eop = tx_ring->buffer_info[i].next_to_watch;
1225 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1226 }
1227
1228 tx_ring->next_to_clean = i;
1229
3f0cfa3b
TH		 1230 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1231
bc7f75fa 1232#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1233 if (count && netif_carrier_ok(netdev) &&
1234 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1235 /* Make sure that anybody stopping the queue after this
1236 * sees the new next_to_clean.
1237 */
1238 smp_mb();
1239
1240 if (netif_queue_stopped(netdev) &&
1241 !(test_bit(__E1000_DOWN, &adapter->state))) {
1242 netif_wake_queue(netdev);
1243 ++adapter->restart_queue;
1244 }
1245 }
1246
1247 if (adapter->detect_tx_hung) {
e921eb1a 1248 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1249 * check with the clearing of time_stamp and movement of i
1250 */
3db1cd5c 1251 adapter->detect_tx_hung = false;
12d04a3c
AD		 1252 if (tx_ring->buffer_info[i].time_stamp &&
1253 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1254 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1255 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1256 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1257 else
1258 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1259 }
1260 adapter->total_tx_bytes += total_tx_bytes;
1261 adapter->total_tx_packets += total_tx_packets;
807540ba 1262 return count < tx_ring->count;
bc7f75fa
AK		 1263}
1264
bc7f75fa
AK		 1265/**
1266 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1267 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1268 *
1269 * the return value indicates whether actual cleaning was done, there
1270 * is no guarantee that everything was cleaned
1271 **/
55aa6985
BA		 1272static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1273 int work_to_do)
bc7f75fa 1274{
55aa6985 1275 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1276 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1277 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1278 struct net_device *netdev = adapter->netdev;
1279 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1280 struct e1000_buffer *buffer_info, *next_buffer;
1281 struct e1000_ps_page *ps_page;
1282 struct sk_buff *skb;
1283 unsigned int i, j;
1284 u32 length, staterr;
1285 int cleaned_count = 0;
3db1cd5c 1286 bool cleaned = false;
bc7f75fa
AK		 1287 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1288
1289 i = rx_ring->next_to_clean;
1290 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1291 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1292 buffer_info = &rx_ring->buffer_info[i];
1293
1294 while (staterr & E1000_RXD_STAT_DD) {
1295 if (*work_done >= work_to_do)
1296 break;
1297 (*work_done)++;
1298 skb = buffer_info->skb;
2d0bb1c1 1299 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1300
1301 /* in the packet split case this is header only */
1302 prefetch(skb->data - NET_IP_ALIGN);
1303
1304 i++;
1305 if (i == rx_ring->count)
1306 i = 0;
1307 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1308 prefetch(next_rxd);
1309
1310 next_buffer = &rx_ring->buffer_info[i];
1311
3db1cd5c 1312 cleaned = true;
bc7f75fa 1313 cleaned_count++;
0be3f55f 1314 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1315 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1316 buffer_info->dma = 0;
1317
af667a29 1318 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1319 if (!(staterr & E1000_RXD_STAT_EOP))
1320 adapter->flags2 |= FLAG2_IS_DISCARDING;
1321
1322 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1323 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1324 dev_kfree_skb_irq(skb);
b94b5028
JB		 1325 if (staterr & E1000_RXD_STAT_EOP)
1326 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1327 goto next_desc;
1328 }
1329
cf955e6c
BG		 1330 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1331 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1332 dev_kfree_skb_irq(skb);
1333 goto next_desc;
1334 }
1335
1336 length = le16_to_cpu(rx_desc->wb.middle.length0);
1337
1338 if (!length) {
ef456f85 1339 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1340 dev_kfree_skb_irq(skb);
1341 goto next_desc;
1342 }
1343
1344 /* Good Receive */
1345 skb_put(skb, length);
1346
1347 {
e921eb1a 1348 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1349 * it more efficient than reusing j
1350 */
1351 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1352
e921eb1a 1353 /* page alloc/put takes too long and effects small
0e15df49
BA		 1354 * packet throughput, so unsplit small packets and
1355 * save the alloc/put only valid in softirq (napi)
1356 * context to call kmap_*
ad68076e 1357 */
0e15df49
BA		 1358 if (l1 && (l1 <= copybreak) &&
1359 ((length + l1) <= adapter->rx_ps_bsize0)) {
1360 u8 *vaddr;
1361
1362 ps_page = &buffer_info->ps_pages[0];
1363
e921eb1a 1364 /* there is no documentation about how to call
0e15df49
BA		 1365 * kmap_atomic, so we can't hold the mapping
1366 * very long
1367 */
1368 dma_sync_single_for_cpu(&pdev->dev,
1369 ps_page->dma,
1370 PAGE_SIZE,
1371 DMA_FROM_DEVICE);
9f393834 1372 vaddr = kmap_atomic(ps_page->page);
0e15df49 1373 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1374 kunmap_atomic(vaddr);
0e15df49
BA		 1375 dma_sync_single_for_device(&pdev->dev,
1376 ps_page->dma,
1377 PAGE_SIZE,
1378 DMA_FROM_DEVICE);
1379
1380 /* remove the CRC */
0184039a
BG		 1381 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1382 if (!(netdev->features & NETIF_F_RXFCS))
1383 l1 -= 4;
1384 }
0e15df49
BA		 1385
1386 skb_put(skb, l1);
1387 goto copydone;
1388 } /* if */
bc7f75fa
AK		 1389 }
1390
1391 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1392 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1393 if (!length)
1394 break;
1395
47f44e40 1396 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1397 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1398 DMA_FROM_DEVICE);
bc7f75fa
AK		 1399 ps_page->dma = 0;
1400 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1401 ps_page->page = NULL;
1402 skb->len += length;
1403 skb->data_len += length;
98a045d7 1404 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1405 }
1406
eb7c3adb
JK		 1407 /* strip the ethernet crc, problem is we're using pages now so
1408 * this whole operation can get a little cpu intensive
1409 */
0184039a
BG		 1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1411 if (!(netdev->features & NETIF_F_RXFCS))
1412 pskb_trim(skb, skb->len - 4);
1413 }
eb7c3adb 1414
bc7f75fa
AK		 1415copydone:
1416 total_rx_bytes += skb->len;
1417 total_rx_packets++;
1418
2e1706f2 1419 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1420
70495a50
BA		 1421 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1422
bc7f75fa 1423 if (rx_desc->wb.upper.header_status &
17e813ec 1424 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1425 adapter->rx_hdr_split++;
1426
b67e1913
BA		 1427 e1000_receive_skb(adapter, netdev, skb, staterr,
1428 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1429
1430next_desc:
1431 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1432 buffer_info->skb = NULL;
1433
1434 /* return some buffers to hardware, one at a time is too slow */
1435 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1436 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1437 GFP_ATOMIC);
bc7f75fa
AK		 1438 cleaned_count = 0;
1439 }
1440
1441 /* use prefetched values */
1442 rx_desc = next_rxd;
1443 buffer_info = next_buffer;
1444
1445 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1446 }
1447 rx_ring->next_to_clean = i;
1448
1449 cleaned_count = e1000_desc_unused(rx_ring);
1450 if (cleaned_count)
55aa6985 1451 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1452
bc7f75fa 1453 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1454 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1455 return cleaned;
1456}
1457
97ac8cae
BA		 1458/**
1459 * e1000_consume_page - helper function
1460 **/
1461static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1462 u16 length)
97ac8cae
BA		 1463{
1464 bi->page = NULL;
1465 skb->len += length;
1466 skb->data_len += length;
98a045d7 1467 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1468}
1469
1470/**
1471 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1472 * @adapter: board private structure
1473 *
1474 * the return value indicates whether actual cleaning was done, there
1475 * is no guarantee that everything was cleaned
1476 **/
55aa6985
BA		 1477static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1478 int work_to_do)
97ac8cae 1479{
55aa6985 1480 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1481 struct net_device *netdev = adapter->netdev;
1482 struct pci_dev *pdev = adapter->pdev;
5f450212 1483 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1484 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1485 u32 length, staterr;
97ac8cae
BA		 1486 unsigned int i;
1487 int cleaned_count = 0;
1488 bool cleaned = false;
362e20ca 1489 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1490 struct skb_shared_info *shinfo;
97ac8cae
BA		 1491
1492 i = rx_ring->next_to_clean;
5f450212
BA		 1493 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1494 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1495 buffer_info = &rx_ring->buffer_info[i];
1496
5f450212 1497 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1498 struct sk_buff *skb;
97ac8cae
BA		 1499
1500 if (*work_done >= work_to_do)
1501 break;
1502 (*work_done)++;
2d0bb1c1 1503 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1504
97ac8cae
BA		 1505 skb = buffer_info->skb;
1506 buffer_info->skb = NULL;
1507
1508 ++i;
1509 if (i == rx_ring->count)
1510 i = 0;
5f450212 1511 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1512 prefetch(next_rxd);
1513
1514 next_buffer = &rx_ring->buffer_info[i];
1515
1516 cleaned = true;
1517 cleaned_count++;
0be3f55f
NN		 1518 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1519 DMA_FROM_DEVICE);
97ac8cae
BA		 1520 buffer_info->dma = 0;
1521
5f450212 1522 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1523
1524 /* errors is only valid for DD + EOP descriptors */
5f450212 1525 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1526 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1527 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1528 /* recycle both page and skb */
1529 buffer_info->skb = skb;
1530 /* an error means any chain goes out the window too */
1531 if (rx_ring->rx_skb_top)
1532 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1533 rx_ring->rx_skb_top = NULL;
1534 goto next_desc;
97ac8cae 1535 }
f0f1a172 1536#define rxtop (rx_ring->rx_skb_top)
5f450212 1537 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1538 /* this descriptor is only the beginning (or middle) */
1539 if (!rxtop) {
1540 /* this is the beginning of a chain */
1541 rxtop = skb;
1542 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1543 0, length);
97ac8cae
BA		 1544 } else {
1545 /* this is the middle of a chain */
17e813ec
BA		 1546 shinfo = skb_shinfo(rxtop);
1547 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1548 buffer_info->page, 0,
1549 length);
97ac8cae
BA		 1550 /* re-use the skb, only consumed the page */
1551 buffer_info->skb = skb;
1552 }
1553 e1000_consume_page(buffer_info, rxtop, length);
1554 goto next_desc;
1555 } else {
1556 if (rxtop) {
1557 /* end of the chain */
17e813ec
BA		 1558 shinfo = skb_shinfo(rxtop);
1559 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1560 buffer_info->page, 0,
1561 length);
97ac8cae 1562 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1563 * page
1564 */
97ac8cae
BA		 1565 buffer_info->skb = skb;
1566 skb = rxtop;
1567 rxtop = NULL;
1568 e1000_consume_page(buffer_info, skb, length);
1569 } else {
1570 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1571 * copybreak to save the put_page/alloc_page
1572 */
97ac8cae
BA		 1573 if (length <= copybreak &&
1574 skb_tailroom(skb) >= length) {
1575 u8 *vaddr;
4679026d 1576 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1577 memcpy(skb_tail_pointer(skb), vaddr,
1578 length);
4679026d 1579 kunmap_atomic(vaddr);
97ac8cae 1580 /* re-use the page, so don't erase
e921eb1a
BA		 1581 * buffer_info->page
1582 */
97ac8cae
BA		 1583 skb_put(skb, length);
1584 } else {
1585 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1586 buffer_info->page, 0,
1587 length);
97ac8cae 1588 e1000_consume_page(buffer_info, skb,
f0ff4398 1589 length);
97ac8cae
BA		 1590 }
1591 }
1592 }
1593
2e1706f2
BA		 1594 /* Receive Checksum Offload */
1595 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1596
70495a50
BA		 1597 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1598
97ac8cae
BA		 1599 /* probably a little skewed due to removing CRC */
1600 total_rx_bytes += skb->len;
1601 total_rx_packets++;
1602
1603 /* eth type trans needs skb->data to point to something */
1604 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1605 e_err("pskb_may_pull failed.\n");
ef5ab89c 1606 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1607 goto next_desc;
1608 }
1609
5f450212
BA		 1610 e1000_receive_skb(adapter, netdev, skb, staterr,
1611 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1612
1613next_desc:
5f450212 1614 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1615
1616 /* return some buffers to hardware, one at a time is too slow */
1617 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1618 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1619 GFP_ATOMIC);
97ac8cae
BA		 1620 cleaned_count = 0;
1621 }
1622
1623 /* use prefetched values */
1624 rx_desc = next_rxd;
1625 buffer_info = next_buffer;
5f450212
BA		 1626
1627 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1628 }
1629 rx_ring->next_to_clean = i;
1630
1631 cleaned_count = e1000_desc_unused(rx_ring);
1632 if (cleaned_count)
55aa6985 1633 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1634
1635 adapter->total_rx_bytes += total_rx_bytes;
1636 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1637 return cleaned;
1638}
1639
bc7f75fa
AK		 1640/**
1641 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1642 * @rx_ring: Rx descriptor ring
bc7f75fa 1643 **/
55aa6985 1644static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1645{
55aa6985 1646 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1647 struct e1000_buffer *buffer_info;
1648 struct e1000_ps_page *ps_page;
1649 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1650 unsigned int i, j;
1651
1652 /* Free all the Rx ring sk_buffs */
1653 for (i = 0; i < rx_ring->count; i++) {
1654 buffer_info = &rx_ring->buffer_info[i];
1655 if (buffer_info->dma) {
1656 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1657 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1658 adapter->rx_buffer_len,
0be3f55f 1659 DMA_FROM_DEVICE);
97ac8cae 1660 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1661 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1662 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1663 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1664 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1665 adapter->rx_ps_bsize0,
0be3f55f 1666 DMA_FROM_DEVICE);
bc7f75fa
AK		 1667 buffer_info->dma = 0;
1668 }
1669
97ac8cae
BA		 1670 if (buffer_info->page) {
1671 put_page(buffer_info->page);
1672 buffer_info->page = NULL;
1673 }
1674
bc7f75fa
AK		 1675 if (buffer_info->skb) {
1676 dev_kfree_skb(buffer_info->skb);
1677 buffer_info->skb = NULL;
1678 }
1679
1680 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1681 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1682 if (!ps_page->page)
1683 break;
0be3f55f
NN		 1684 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1685 DMA_FROM_DEVICE);
bc7f75fa
AK		 1686 ps_page->dma = 0;
1687 put_page(ps_page->page);
1688 ps_page->page = NULL;
1689 }
1690 }
1691
1692 /* there also may be some cached data from a chained receive */
1693 if (rx_ring->rx_skb_top) {
1694 dev_kfree_skb(rx_ring->rx_skb_top);
1695 rx_ring->rx_skb_top = NULL;
1696 }
1697
bc7f75fa
AK		 1698 /* Zero out the descriptor ring */
1699 memset(rx_ring->desc, 0, rx_ring->size);
1700
1701 rx_ring->next_to_clean = 0;
1702 rx_ring->next_to_use = 0;
b94b5028 1703 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1704
c5083cf6 1705 writel(0, rx_ring->head);
bdc125f7
BA		 1706 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1707 e1000e_update_rdt_wa(rx_ring, 0);
1708 else
1709 writel(0, rx_ring->tail);
bc7f75fa
AK		 1710}
1711
a8f88ff5
JB		 1712static void e1000e_downshift_workaround(struct work_struct *work)
1713{
1714 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1715 struct e1000_adapter,
1716 downshift_task);
a8f88ff5 1717
615b32af
JB		 1718 if (test_bit(__E1000_DOWN, &adapter->state))
1719 return;
1720
a8f88ff5
JB		 1721 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1722}
1723
bc7f75fa
AK		 1724/**
1725 * e1000_intr_msi - Interrupt Handler
1726 * @irq: interrupt number
1727 * @data: pointer to a network interface device structure
1728 **/
8bb62869 1729static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1730{
1731 struct net_device *netdev = data;
1732 struct e1000_adapter *adapter = netdev_priv(netdev);
1733 struct e1000_hw *hw = &adapter->hw;
1734 u32 icr = er32(ICR);
1735
e921eb1a 1736 /* read ICR disables interrupts using IAM */
573cca8c 1737 if (icr & E1000_ICR_LSC) {
f92518dd 1738 hw->mac.get_link_status = true;
e921eb1a 1739 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1740 * disconnect (LSC) before accessing any PHY registers
1741 */
bc7f75fa
AK		 1742 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1743 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1744 schedule_work(&adapter->downshift_task);
bc7f75fa 1745
e921eb1a 1746 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1747 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1748 * adapter in watchdog
1749 */
bc7f75fa
AK		 1750 if (netif_carrier_ok(netdev) &&
1751 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1752 /* disable receives */
1753 u32 rctl = er32(RCTL);
1754 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1755 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1756 }
1757 /* guard against interrupt when we're going down */
1758 if (!test_bit(__E1000_DOWN, &adapter->state))
1759 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1760 }
1761
94fb848b
BA		 1762 /* Reset on uncorrectable ECC error */
1763 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1764 u32 pbeccsts = er32(PBECCSTS);
1765
1766 adapter->corr_errors +=
1767 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1768 adapter->uncorr_errors +=
1769 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1770 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1771
1772 /* Do the reset outside of interrupt context */
1773 schedule_work(&adapter->reset_task);
1774
1775 /* return immediately since reset is imminent */
1776 return IRQ_HANDLED;
1777 }
1778
288379f0 1779 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1780 adapter->total_tx_bytes = 0;
1781 adapter->total_tx_packets = 0;
1782 adapter->total_rx_bytes = 0;
1783 adapter->total_rx_packets = 0;
288379f0 1784 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1785 }
1786
1787 return IRQ_HANDLED;
1788}
1789
1790/**
1791 * e1000_intr - Interrupt Handler
1792 * @irq: interrupt number
1793 * @data: pointer to a network interface device structure
1794 **/
8bb62869 1795static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1796{
1797 struct net_device *netdev = data;
1798 struct e1000_adapter *adapter = netdev_priv(netdev);
1799 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1800 u32 rctl, icr = er32(ICR);
4662e82b 1801
a68ea775 1802 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1803 return IRQ_NONE; /* Not our interrupt */
1804
e921eb1a 1805 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1806 * not set, then the adapter didn't send an interrupt
1807 */
bc7f75fa
AK		 1808 if (!(icr & E1000_ICR_INT_ASSERTED))
1809 return IRQ_NONE;
1810
e921eb1a 1811 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1812 * interrupts are masked. No need for the
1813 * IMC write
1814 */
bc7f75fa 1815
573cca8c 1816 if (icr & E1000_ICR_LSC) {
f92518dd 1817 hw->mac.get_link_status = true;
e921eb1a 1818 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1819 * disconnect (LSC) before accessing any PHY registers
1820 */
bc7f75fa
AK		 1821 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1822 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1823 schedule_work(&adapter->downshift_task);
bc7f75fa 1824
e921eb1a 1825 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1826 * For packet buffer work-around on link down event;
1827 * disable receives here in the ISR and
1828 * reset adapter in watchdog
1829 */
1830 if (netif_carrier_ok(netdev) &&
1831 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1832 /* disable receives */
1833 rctl = er32(RCTL);
1834 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1835 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1836 }
1837 /* guard against interrupt when we're going down */
1838 if (!test_bit(__E1000_DOWN, &adapter->state))
1839 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1840 }
1841
94fb848b
BA		 1842 /* Reset on uncorrectable ECC error */
1843 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1844 u32 pbeccsts = er32(PBECCSTS);
1845
1846 adapter->corr_errors +=
1847 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1848 adapter->uncorr_errors +=
1849 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1850 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1851
1852 /* Do the reset outside of interrupt context */
1853 schedule_work(&adapter->reset_task);
1854
1855 /* return immediately since reset is imminent */
1856 return IRQ_HANDLED;
1857 }
1858
288379f0 1859 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1860 adapter->total_tx_bytes = 0;
1861 adapter->total_tx_packets = 0;
1862 adapter->total_rx_bytes = 0;
1863 adapter->total_rx_packets = 0;
288379f0 1864 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1865 }
1866
1867 return IRQ_HANDLED;
1868}
1869
8bb62869 1870static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1871{
1872 struct net_device *netdev = data;
1873 struct e1000_adapter *adapter = netdev_priv(netdev);
1874 struct e1000_hw *hw = &adapter->hw;
1875 u32 icr = er32(ICR);
1876
1877 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1878 if (!test_bit(__E1000_DOWN, &adapter->state))
1879 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1880 return IRQ_NONE;
1881 }
1882
1883 if (icr & adapter->eiac_mask)
1884 ew32(ICS, (icr & adapter->eiac_mask));
1885
1886 if (icr & E1000_ICR_OTHER) {
1887 if (!(icr & E1000_ICR_LSC))
1888 goto no_link_interrupt;
f92518dd 1889 hw->mac.get_link_status = true;
4662e82b
BA		 1890 /* guard against interrupt when we're going down */
1891 if (!test_bit(__E1000_DOWN, &adapter->state))
1892 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1893 }
1894
1895no_link_interrupt:
a3c69fef
JB		 1896 if (!test_bit(__E1000_DOWN, &adapter->state))
1897 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1898
1899 return IRQ_HANDLED;
1900}
1901
8bb62869 1902static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1903{
1904 struct net_device *netdev = data;
1905 struct e1000_adapter *adapter = netdev_priv(netdev);
1906 struct e1000_hw *hw = &adapter->hw;
1907 struct e1000_ring *tx_ring = adapter->tx_ring;
1908
4662e82b
BA		 1909 adapter->total_tx_bytes = 0;
1910 adapter->total_tx_packets = 0;
1911
55aa6985 1912 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1913 /* Ring was not completely cleaned, so fire another interrupt */
1914 ew32(ICS, tx_ring->ims_val);
1915
1916 return IRQ_HANDLED;
1917}
1918
8bb62869 1919static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1920{
1921 struct net_device *netdev = data;
1922 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1923 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1924
1925 /* Write the ITR value calculated at the end of the
1926 * previous interrupt.
1927 */
55aa6985
BA		 1928 if (rx_ring->set_itr) {
1929 writel(1000000000 / (rx_ring->itr_val * 256),
1930 rx_ring->itr_register);
1931 rx_ring->set_itr = 0;
4662e82b
BA		 1932 }
1933
288379f0 1934 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1935 adapter->total_rx_bytes = 0;
1936 adapter->total_rx_packets = 0;
288379f0 1937 __napi_schedule(&adapter->napi);
4662e82b
BA		 1938 }
1939 return IRQ_HANDLED;
1940}
1941
1942/**
1943 * e1000_configure_msix - Configure MSI-X hardware
1944 *
1945 * e1000_configure_msix sets up the hardware to properly
1946 * generate MSI-X interrupts.
1947 **/
1948static void e1000_configure_msix(struct e1000_adapter *adapter)
1949{
1950 struct e1000_hw *hw = &adapter->hw;
1951 struct e1000_ring *rx_ring = adapter->rx_ring;
1952 struct e1000_ring *tx_ring = adapter->tx_ring;
1953 int vector = 0;
1954 u32 ctrl_ext, ivar = 0;
1955
1956 adapter->eiac_mask = 0;
1957
1958 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1959 if (hw->mac.type == e1000_82574) {
1960 u32 rfctl = er32(RFCTL);
1961 rfctl |= E1000_RFCTL_ACK_DIS;
1962 ew32(RFCTL, rfctl);
1963 }
1964
4662e82b
BA		 1965 /* Configure Rx vector */
1966 rx_ring->ims_val = E1000_IMS_RXQ0;
1967 adapter->eiac_mask |= rx_ring->ims_val;
1968 if (rx_ring->itr_val)
1969 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1970 rx_ring->itr_register);
4662e82b 1971 else
c5083cf6 1972 writel(1, rx_ring->itr_register);
4662e82b
BA		 1973 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1974
1975 /* Configure Tx vector */
1976 tx_ring->ims_val = E1000_IMS_TXQ0;
1977 vector++;
1978 if (tx_ring->itr_val)
1979 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1980 tx_ring->itr_register);
4662e82b 1981 else
c5083cf6 1982 writel(1, tx_ring->itr_register);
4662e82b
BA		 1983 adapter->eiac_mask |= tx_ring->ims_val;
1984 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1985
1986 /* set vector for Other Causes, e.g. link changes */
1987 vector++;
1988 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1989 if (rx_ring->itr_val)
1990 writel(1000000000 / (rx_ring->itr_val * 256),
1991 hw->hw_addr + E1000_EITR_82574(vector));
1992 else
1993 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1994
1995 /* Cause Tx interrupts on every write back */
1996 ivar |= (1 << 31);
1997
1998 ew32(IVAR, ivar);
1999
2000 /* enable MSI-X PBA support */
2001 ctrl_ext = er32(CTRL_EXT);
2002 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2003
2004 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2005 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2006 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2007 ew32(CTRL_EXT, ctrl_ext);
2008 e1e_flush();
2009}
2010
2011void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2012{
2013 if (adapter->msix_entries) {
2014 pci_disable_msix(adapter->pdev);
2015 kfree(adapter->msix_entries);
2016 adapter->msix_entries = NULL;
2017 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2018 pci_disable_msi(adapter->pdev);
2019 adapter->flags &= ~FLAG_MSI_ENABLED;
2020 }
4662e82b
BA		 2021}
2022
2023/**
2024 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2025 *
2026 * Attempt to configure interrupts using the best available
2027 * capabilities of the hardware and kernel.
2028 **/
2029void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2030{
2031 int err;
8e86acd7 2032 int i;
4662e82b
BA		 2033
2034 switch (adapter->int_mode) {
2035 case E1000E_INT_MODE_MSIX:
2036 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2037 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2038 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2039 sizeof(struct
2040 msix_entry),
2041 GFP_KERNEL);
4662e82b 2042 if (adapter->msix_entries) {
8e86acd7 2043 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2044 adapter->msix_entries[i].entry = i;
2045
2046 err = pci_enable_msix(adapter->pdev,
2047 adapter->msix_entries,
8e86acd7 2048 adapter->num_vectors);
b1cdfead 2049 if (err == 0)
4662e82b
BA		 2050 return;
2051 }
2052 /* MSI-X failed, so fall through and try MSI */
ef456f85 2053 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2054 e1000e_reset_interrupt_capability(adapter);
2055 }
2056 adapter->int_mode = E1000E_INT_MODE_MSI;
2057 /* Fall through */
2058 case E1000E_INT_MODE_MSI:
2059 if (!pci_enable_msi(adapter->pdev)) {
2060 adapter->flags |= FLAG_MSI_ENABLED;
2061 } else {
2062 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2063 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2064 }
2065 /* Fall through */
2066 case E1000E_INT_MODE_LEGACY:
2067 /* Don't do anything; this is the system default */
2068 break;
2069 }
8e86acd7
JK		 2070
2071 /* store the number of vectors being used */
2072 adapter->num_vectors = 1;
4662e82b
BA		 2073}
2074
2075/**
2076 * e1000_request_msix - Initialize MSI-X interrupts
2077 *
2078 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2079 * kernel.
2080 **/
2081static int e1000_request_msix(struct e1000_adapter *adapter)
2082{
2083 struct net_device *netdev = adapter->netdev;
2084 int err = 0, vector = 0;
2085
2086 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2087 snprintf(adapter->rx_ring->name,
2088 sizeof(adapter->rx_ring->name) - 1,
2089 "%s-rx-0", netdev->name);
4662e82b
BA		 2090 else
2091 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2092 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2093 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2094 netdev);
2095 if (err)
5015e53a 2096 return err;
c5083cf6
BA		 2097 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2098 E1000_EITR_82574(vector);
4662e82b
BA		 2099 adapter->rx_ring->itr_val = adapter->itr;
2100 vector++;
2101
2102 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2103 snprintf(adapter->tx_ring->name,
2104 sizeof(adapter->tx_ring->name) - 1,
2105 "%s-tx-0", netdev->name);
4662e82b
BA		 2106 else
2107 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2108 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2109 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2110 netdev);
2111 if (err)
5015e53a 2112 return err;
c5083cf6
BA		 2113 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2114 E1000_EITR_82574(vector);
4662e82b
BA		 2115 adapter->tx_ring->itr_val = adapter->itr;
2116 vector++;
2117
2118 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2119 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2120 if (err)
5015e53a 2121 return err;
4662e82b
BA		 2122
2123 e1000_configure_msix(adapter);
5015e53a 2124
4662e82b 2125 return 0;
4662e82b
BA		 2126}
2127
f8d59f78
BA		 2128/**
2129 * e1000_request_irq - initialize interrupts
2130 *
2131 * Attempts to configure interrupts using the best available
2132 * capabilities of the hardware and kernel.
2133 **/
bc7f75fa
AK		 2134static int e1000_request_irq(struct e1000_adapter *adapter)
2135{
2136 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2137 int err;
2138
4662e82b
BA		 2139 if (adapter->msix_entries) {
2140 err = e1000_request_msix(adapter);
2141 if (!err)
2142 return err;
2143 /* fall back to MSI */
2144 e1000e_reset_interrupt_capability(adapter);
2145 adapter->int_mode = E1000E_INT_MODE_MSI;
2146 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2147 }
4662e82b 2148 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2149 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2150 netdev->name, netdev);
2151 if (!err)
2152 return err;
bc7f75fa 2153
4662e82b
BA		 2154 /* fall back to legacy interrupt */
2155 e1000e_reset_interrupt_capability(adapter);
2156 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2157 }
2158
a0607fd3 2159 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2160 netdev->name, netdev);
2161 if (err)
2162 e_err("Unable to allocate interrupt, Error: %d\n", err);
2163
bc7f75fa
AK		 2164 return err;
2165}
2166
2167static void e1000_free_irq(struct e1000_adapter *adapter)
2168{
2169 struct net_device *netdev = adapter->netdev;
2170
4662e82b
BA		 2171 if (adapter->msix_entries) {
2172 int vector = 0;
2173
2174 free_irq(adapter->msix_entries[vector].vector, netdev);
2175 vector++;
2176
2177 free_irq(adapter->msix_entries[vector].vector, netdev);
2178 vector++;
2179
2180 /* Other Causes interrupt vector */
2181 free_irq(adapter->msix_entries[vector].vector, netdev);
2182 return;
bc7f75fa 2183 }
4662e82b
BA		 2184
2185 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2186}
2187
2188/**
2189 * e1000_irq_disable - Mask off interrupt generation on the NIC
2190 **/
2191static void e1000_irq_disable(struct e1000_adapter *adapter)
2192{
2193 struct e1000_hw *hw = &adapter->hw;
2194
bc7f75fa 2195 ew32(IMC, ~0);
4662e82b
BA		 2196 if (adapter->msix_entries)
2197 ew32(EIAC_82574, 0);
bc7f75fa 2198 e1e_flush();
8e86acd7
JK		 2199
2200 if (adapter->msix_entries) {
2201 int i;
2202 for (i = 0; i < adapter->num_vectors; i++)
2203 synchronize_irq(adapter->msix_entries[i].vector);
2204 } else {
2205 synchronize_irq(adapter->pdev->irq);
2206 }
bc7f75fa
AK		 2207}
2208
2209/**
2210 * e1000_irq_enable - Enable default interrupt generation settings
2211 **/
2212static void e1000_irq_enable(struct e1000_adapter *adapter)
2213{
2214 struct e1000_hw *hw = &adapter->hw;
2215
4662e82b
BA		 2216 if (adapter->msix_entries) {
2217 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2218 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2219 } else if (hw->mac.type == e1000_pch_lpt) {
2220 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2221 } else {
2222 ew32(IMS, IMS_ENABLE_MASK);
2223 }
74ef9c39 2224 e1e_flush();
bc7f75fa
AK		 2225}
2226
2227/**
31dbe5b4 2228 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2229 * @adapter: address of board private structure
2230 *
31dbe5b4 2231 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2232 * For ASF and Pass Through versions of f/w this means that
2233 * the driver is loaded. For AMT version (only with 82573)
2234 * of the f/w this means that the network i/f is open.
2235 **/
31dbe5b4 2236void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2237{
2238 struct e1000_hw *hw = &adapter->hw;
2239 u32 ctrl_ext;
2240 u32 swsm;
2241
2242 /* Let firmware know the driver has taken over */
2243 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2244 swsm = er32(SWSM);
2245 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2246 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2247 ctrl_ext = er32(CTRL_EXT);
ad68076e 2248 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2249 }
2250}
2251
2252/**
31dbe5b4 2253 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2254 * @adapter: address of board private structure
2255 *
31dbe5b4 2256 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2257 * For ASF and Pass Through versions of f/w this means that the
2258 * driver is no longer loaded. For AMT version (only with 82573) i
2259 * of the f/w this means that the network i/f is closed.
2260 *
2261 **/
31dbe5b4 2262void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2263{
2264 struct e1000_hw *hw = &adapter->hw;
2265 u32 ctrl_ext;
2266 u32 swsm;
2267
2268 /* Let firmware taken over control of h/w */
2269 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2270 swsm = er32(SWSM);
2271 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2272 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2273 ctrl_ext = er32(CTRL_EXT);
ad68076e 2274 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2275 }
2276}
2277
bc7f75fa 2278/**
49ce9c2c 2279 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2280 **/
2281static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2282 struct e1000_ring *ring)
2283{
2284 struct pci_dev *pdev = adapter->pdev;
2285
2286 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2287 GFP_KERNEL);
2288 if (!ring->desc)
2289 return -ENOMEM;
2290
2291 return 0;
2292}
2293
2294/**
2295 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2296 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2297 *
2298 * Return 0 on success, negative on failure
2299 **/
55aa6985 2300int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2301{
55aa6985 2302 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2303 int err = -ENOMEM, size;
2304
2305 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2306 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2307 if (!tx_ring->buffer_info)
2308 goto err;
bc7f75fa
AK		 2309
2310 /* round up to nearest 4K */
2311 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2312 tx_ring->size = ALIGN(tx_ring->size, 4096);
2313
2314 err = e1000_alloc_ring_dma(adapter, tx_ring);
2315 if (err)
2316 goto err;
2317
2318 tx_ring->next_to_use = 0;
2319 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2320
2321 return 0;
2322err:
2323 vfree(tx_ring->buffer_info);
44defeb3 2324 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2325 return err;
2326}
2327
2328/**
2329 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2330 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2331 *
2332 * Returns 0 on success, negative on failure
2333 **/
55aa6985 2334int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2335{
55aa6985 2336 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2337 struct e1000_buffer *buffer_info;
2338 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2339
2340 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2341 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2342 if (!rx_ring->buffer_info)
2343 goto err;
bc7f75fa 2344
47f44e40
AK		 2345 for (i = 0; i < rx_ring->count; i++) {
2346 buffer_info = &rx_ring->buffer_info[i];
2347 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2348 sizeof(struct e1000_ps_page),
2349 GFP_KERNEL);
2350 if (!buffer_info->ps_pages)
2351 goto err_pages;
2352 }
bc7f75fa
AK		 2353
2354 desc_len = sizeof(union e1000_rx_desc_packet_split);
2355
2356 /* Round up to nearest 4K */
2357 rx_ring->size = rx_ring->count * desc_len;
2358 rx_ring->size = ALIGN(rx_ring->size, 4096);
2359
2360 err = e1000_alloc_ring_dma(adapter, rx_ring);
2361 if (err)
47f44e40 2362 goto err_pages;
bc7f75fa
AK		 2363
2364 rx_ring->next_to_clean = 0;
2365 rx_ring->next_to_use = 0;
2366 rx_ring->rx_skb_top = NULL;
2367
2368 return 0;
47f44e40
AK		 2369
2370err_pages:
2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 kfree(buffer_info->ps_pages);
2374 }
bc7f75fa
AK		 2375err:
2376 vfree(rx_ring->buffer_info);
e9262447 2377 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2378 return err;
2379}
2380
2381/**
2382 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2383 * @tx_ring: Tx descriptor ring
bc7f75fa 2384 **/
55aa6985 2385static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2386{
55aa6985 2387 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2388 struct e1000_buffer *buffer_info;
2389 unsigned long size;
2390 unsigned int i;
2391
2392 for (i = 0; i < tx_ring->count; i++) {
2393 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2394 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2395 }
2396
3f0cfa3b 2397 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2398 size = sizeof(struct e1000_buffer) * tx_ring->count;
2399 memset(tx_ring->buffer_info, 0, size);
2400
2401 memset(tx_ring->desc, 0, tx_ring->size);
2402
2403 tx_ring->next_to_use = 0;
2404 tx_ring->next_to_clean = 0;
2405
c5083cf6 2406 writel(0, tx_ring->head);
bdc125f7
BA		 2407 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2408 e1000e_update_tdt_wa(tx_ring, 0);
2409 else
2410 writel(0, tx_ring->tail);
bc7f75fa
AK		 2411}
2412
2413/**
2414 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2415 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2416 *
2417 * Free all transmit software resources
2418 **/
55aa6985 2419void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2420{
55aa6985 2421 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2422 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2423
55aa6985 2424 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2425
2426 vfree(tx_ring->buffer_info);
2427 tx_ring->buffer_info = NULL;
2428
2429 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2430 tx_ring->dma);
2431 tx_ring->desc = NULL;
2432}
2433
2434/**
2435 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2436 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2437 *
2438 * Free all receive software resources
2439 **/
55aa6985 2440void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2441{
55aa6985 2442 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2443 struct pci_dev *pdev = adapter->pdev;
47f44e40 2444 int i;
bc7f75fa 2445
55aa6985 2446 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2447
b1cdfead 2448 for (i = 0; i < rx_ring->count; i++)
47f44e40 2449 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2450
bc7f75fa
AK		 2451 vfree(rx_ring->buffer_info);
2452 rx_ring->buffer_info = NULL;
2453
bc7f75fa
AK		 2454 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2455 rx_ring->dma);
2456 rx_ring->desc = NULL;
2457}
2458
2459/**
2460 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2461 * @adapter: pointer to adapter
2462 * @itr_setting: current adapter->itr
2463 * @packets: the number of packets during this measurement interval
2464 * @bytes: the number of bytes during this measurement interval
2465 *
bc7f75fa
AK		 2466 * Stores a new ITR value based on packets and byte
2467 * counts during the last interrupt. The advantage of per interrupt
2468 * computation is faster updates and more accurate ITR for the current
2469 * traffic pattern. Constants in this function were computed
2470 * based on theoretical maximum wire speed and thresholds were set based
2471 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2472 * while increasing bulk throughput. This functionality is controlled
2473 * by the InterruptThrottleRate module parameter.
bc7f75fa 2474 **/
8bb62869 2475static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2476{
2477 unsigned int retval = itr_setting;
2478
2479 if (packets == 0)
5015e53a 2480 return itr_setting;
bc7f75fa
AK		 2481
2482 switch (itr_setting) {
2483 case lowest_latency:
2484 /* handle TSO and jumbo frames */
362e20ca 2485 if (bytes / packets > 8000)
bc7f75fa 2486 retval = bulk_latency;
b1cdfead 2487 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2488 retval = low_latency;
bc7f75fa
AK		 2489 break;
2490 case low_latency: /* 50 usec aka 20000 ints/s */
2491 if (bytes > 10000) {
2492 /* this if handles the TSO accounting */
362e20ca 2493 if (bytes / packets > 8000)
bc7f75fa 2494 retval = bulk_latency;
362e20ca 2495 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2496 retval = bulk_latency;
b1cdfead 2497 else if ((packets > 35))
bc7f75fa 2498 retval = lowest_latency;
362e20ca 2499 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2500 retval = bulk_latency;
2501 } else if (packets <= 2 && bytes < 512) {
2502 retval = lowest_latency;
2503 }
2504 break;
2505 case bulk_latency: /* 250 usec aka 4000 ints/s */
2506 if (bytes > 25000) {
b1cdfead 2507 if (packets > 35)
bc7f75fa 2508 retval = low_latency;
bc7f75fa
AK		 2509 } else if (bytes < 6000) {
2510 retval = low_latency;
2511 }
2512 break;
2513 }
2514
bc7f75fa
AK		 2515 return retval;
2516}
2517
2518static void e1000_set_itr(struct e1000_adapter *adapter)
2519{
bc7f75fa
AK		 2520 u16 current_itr;
2521 u32 new_itr = adapter->itr;
2522
2523 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2524 if (adapter->link_speed != SPEED_1000) {
2525 current_itr = 0;
2526 new_itr = 4000;
2527 goto set_itr_now;
2528 }
2529
828bac87
BA		 2530 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2531 new_itr = 0;
2532 goto set_itr_now;
2533 }
2534
8bb62869
BA		 2535 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2536 adapter->total_tx_packets,
2537 adapter->total_tx_bytes);
bc7f75fa
AK		 2538 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2539 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2540 adapter->tx_itr = low_latency;
2541
8bb62869
BA		 2542 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2543 adapter->total_rx_packets,
2544 adapter->total_rx_bytes);
bc7f75fa
AK		 2545 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2546 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2547 adapter->rx_itr = low_latency;
2548
2549 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2550
bc7f75fa 2551 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2552 switch (current_itr) {
bc7f75fa
AK		 2553 case lowest_latency:
2554 new_itr = 70000;
2555 break;
2556 case low_latency:
2557 new_itr = 20000; /* aka hwitr = ~200 */
2558 break;
2559 case bulk_latency:
2560 new_itr = 4000;
2561 break;
2562 default:
2563 break;
2564 }
2565
2566set_itr_now:
2567 if (new_itr != adapter->itr) {
e921eb1a 2568 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2569 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2570 * increasing
2571 */
bc7f75fa 2572 new_itr = new_itr > adapter->itr ?
f0ff4398 2573 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2574 adapter->itr = new_itr;
4662e82b
BA		 2575 adapter->rx_ring->itr_val = new_itr;
2576 if (adapter->msix_entries)
2577 adapter->rx_ring->set_itr = 1;
2578 else
e3d14b08 2579 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2580 }
2581}
2582
22a4cca2
MV		 2583/**
2584 * e1000e_write_itr - write the ITR value to the appropriate registers
2585 * @adapter: address of board private structure
2586 * @itr: new ITR value to program
2587 *
2588 * e1000e_write_itr determines if the adapter is in MSI-X mode
2589 * and, if so, writes the EITR registers with the ITR value.
2590 * Otherwise, it writes the ITR value into the ITR register.
2591 **/
2592void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2593{
2594 struct e1000_hw *hw = &adapter->hw;
2595 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2596
2597 if (adapter->msix_entries) {
2598 int vector;
2599
2600 for (vector = 0; vector < adapter->num_vectors; vector++)
2601 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2602 } else {
2603 ew32(ITR, new_itr);
2604 }
2605}
2606
4662e82b
BA		 2607/**
2608 * e1000_alloc_queues - Allocate memory for all rings
2609 * @adapter: board private structure to initialize
2610 **/
9f9a12f8 2611static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2612{
55aa6985
BA		 2613 int size = sizeof(struct e1000_ring);
2614
2615 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2616 if (!adapter->tx_ring)
2617 goto err;
55aa6985
BA		 2618 adapter->tx_ring->count = adapter->tx_ring_count;
2619 adapter->tx_ring->adapter = adapter;
4662e82b 2620
55aa6985 2621 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2622 if (!adapter->rx_ring)
2623 goto err;
55aa6985
BA		 2624 adapter->rx_ring->count = adapter->rx_ring_count;
2625 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2626
2627 return 0;
2628err:
2629 e_err("Unable to allocate memory for queues\n");
2630 kfree(adapter->rx_ring);
2631 kfree(adapter->tx_ring);
2632 return -ENOMEM;
2633}
2634
bc7f75fa 2635/**
c58c8a78 2636 * e1000e_poll - NAPI Rx polling callback
ad68076e 2637 * @napi: struct associated with this polling callback
c58c8a78 2638 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2639 **/
c58c8a78 2640static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2641{
c58c8a78
BA		 2642 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2643 napi);
4662e82b 2644 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2645 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2646 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2647
4cf1653a 2648 adapter = netdev_priv(poll_dev);
bc7f75fa 2649
c58c8a78
BA		 2650 if (!adapter->msix_entries ||
2651 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2652 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2653
c58c8a78 2654 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2655
12d04a3c 2656 if (!tx_cleaned)
c58c8a78 2657 work_done = weight;
bc7f75fa 2658
c58c8a78
BA		 2659 /* If weight not fully consumed, exit the polling mode */
2660 if (work_done < weight) {
bc7f75fa
AK		 2661 if (adapter->itr_setting & 3)
2662 e1000_set_itr(adapter);
288379f0 2663 napi_complete(napi);
a3c69fef
JB		 2664 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2665 if (adapter->msix_entries)
2666 ew32(IMS, adapter->rx_ring->ims_val);
2667 else
2668 e1000_irq_enable(adapter);
2669 }
bc7f75fa
AK		 2670 }
2671
2672 return work_done;
2673}
2674
80d5c368
PM		 2675static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2676 __be16 proto, u16 vid)
bc7f75fa
AK		 2677{
2678 struct e1000_adapter *adapter = netdev_priv(netdev);
2679 struct e1000_hw *hw = &adapter->hw;
2680 u32 vfta, index;
2681
2682 /* don't update vlan cookie if already programmed */
2683 if ((adapter->hw.mng_cookie.status &
2684 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2685 (vid == adapter->mng_vlan_id))
8e586137 2686 return 0;
caaddaf8 2687
bc7f75fa 2688 /* add VID to filter table */
caaddaf8
BA		 2689 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2690 index = (vid >> 5) & 0x7F;
2691 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2692 vfta |= (1 << (vid & 0x1F));
2693 hw->mac.ops.write_vfta(hw, index, vfta);
2694 }
86d70e53
JK		 2695
2696 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2697
2698 return 0;
bc7f75fa
AK		 2699}
2700
80d5c368
PM		 2701static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2702 __be16 proto, u16 vid)
bc7f75fa
AK		 2703{
2704 struct e1000_adapter *adapter = netdev_priv(netdev);
2705 struct e1000_hw *hw = &adapter->hw;
2706 u32 vfta, index;
2707
bc7f75fa
AK		 2708 if ((adapter->hw.mng_cookie.status &
2709 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2710 (vid == adapter->mng_vlan_id)) {
2711 /* release control to f/w */
31dbe5b4 2712 e1000e_release_hw_control(adapter);
8e586137 2713 return 0;
bc7f75fa
AK		 2714 }
2715
2716 /* remove VID from filter table */
caaddaf8
BA		 2717 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2718 index = (vid >> 5) & 0x7F;
2719 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2720 vfta &= ~(1 << (vid & 0x1F));
2721 hw->mac.ops.write_vfta(hw, index, vfta);
2722 }
86d70e53
JK		 2723
2724 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2725
2726 return 0;
bc7f75fa
AK		 2727}
2728
86d70e53
JK		 2729/**
2730 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2731 * @adapter: board private structure to initialize
2732 **/
2733static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2734{
2735 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2736 struct e1000_hw *hw = &adapter->hw;
2737 u32 rctl;
bc7f75fa 2738
86d70e53
JK		 2739 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2740 /* disable VLAN receive filtering */
2741 rctl = er32(RCTL);
2742 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2743 ew32(RCTL, rctl);
2744
2745 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2746 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2747 adapter->mng_vlan_id);
86d70e53 2748 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2749 }
bc7f75fa
AK		 2750 }
2751}
2752
86d70e53
JK		 2753/**
2754 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2755 * @adapter: board private structure to initialize
2756 **/
2757static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2758{
2759 struct e1000_hw *hw = &adapter->hw;
2760 u32 rctl;
2761
2762 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2763 /* enable VLAN receive filtering */
2764 rctl = er32(RCTL);
2765 rctl |= E1000_RCTL_VFE;
2766 rctl &= ~E1000_RCTL_CFIEN;
2767 ew32(RCTL, rctl);
2768 }
2769}
bc7f75fa 2770
86d70e53
JK		 2771/**
2772 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2773 * @adapter: board private structure to initialize
2774 **/
2775static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2776{
bc7f75fa 2777 struct e1000_hw *hw = &adapter->hw;
86d70e53 2778 u32 ctrl;
bc7f75fa 2779
86d70e53
JK		 2780 /* disable VLAN tag insert/strip */
2781 ctrl = er32(CTRL);
2782 ctrl &= ~E1000_CTRL_VME;
2783 ew32(CTRL, ctrl);
2784}
bc7f75fa 2785
86d70e53
JK		 2786/**
2787 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2788 * @adapter: board private structure to initialize
2789 **/
2790static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2791{
2792 struct e1000_hw *hw = &adapter->hw;
2793 u32 ctrl;
bc7f75fa 2794
86d70e53
JK		 2795 /* enable VLAN tag insert/strip */
2796 ctrl = er32(CTRL);
2797 ctrl |= E1000_CTRL_VME;
2798 ew32(CTRL, ctrl);
2799}
bc7f75fa 2800
86d70e53
JK		 2801static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2802{
2803 struct net_device *netdev = adapter->netdev;
2804 u16 vid = adapter->hw.mng_cookie.vlan_id;
2805 u16 old_vid = adapter->mng_vlan_id;
2806
e5fe2541 2807 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2808 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2809 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2810 }
2811
86d70e53 2812 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2813 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2814}
2815
2816static void e1000_restore_vlan(struct e1000_adapter *adapter)
2817{
2818 u16 vid;
2819
80d5c368 2820 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2821
86d70e53 2822 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2823 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2824}
2825
cd791618 2826static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2827{
2828 struct e1000_hw *hw = &adapter->hw;
cd791618 2829 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2830
2831 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2832 return;
2833
2834 manc = er32(MANC);
2835
e921eb1a 2836 /* enable receiving management packets to the host. this will probably
bc7f75fa 2837 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2838 * the packets will be handled on SMBUS
2839 */
bc7f75fa
AK		 2840 manc |= E1000_MANC_EN_MNG2HOST;
2841 manc2h = er32(MANC2H);
cd791618
BA		 2842
2843 switch (hw->mac.type) {
2844 default:
2845 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2846 break;
2847 case e1000_82574:
2848 case e1000_82583:
e921eb1a 2849 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2850 * if so, enable it.
2851 */
2852 for (i = 0, j = 0; i < 8; i++) {
2853 mdef = er32(MDEF(i));
2854
2855 /* Ignore filters with anything other than IPMI ports */
3b21b508 2856 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2857 continue;
2858
2859 /* Enable this decision filter in MANC2H */
2860 if (mdef)
2861 manc2h |= (1 << i);
2862
2863 j |= mdef;
2864 }
2865
2866 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2867 break;
2868
2869 /* Create new decision filter in an empty filter */
2870 for (i = 0, j = 0; i < 8; i++)
2871 if (er32(MDEF(i)) == 0) {
2872 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2873 E1000_MDEF_PORT_664));
2874 manc2h |= (1 << 1);
2875 j++;
2876 break;
2877 }
2878
2879 if (!j)
2880 e_warn("Unable to create IPMI pass-through filter\n");
2881 break;
2882 }
2883
bc7f75fa
AK		 2884 ew32(MANC2H, manc2h);
2885 ew32(MANC, manc);
2886}
2887
2888/**
af667a29 2889 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2890 * @adapter: board private structure
2891 *
2892 * Configure the Tx unit of the MAC after a reset.
2893 **/
2894static void e1000_configure_tx(struct e1000_adapter *adapter)
2895{
2896 struct e1000_hw *hw = &adapter->hw;
2897 struct e1000_ring *tx_ring = adapter->tx_ring;
2898 u64 tdba;
c550b121 2899 u32 tdlen, tarc;
bc7f75fa
AK		 2900
2901 /* Setup the HW Tx Head and Tail descriptor pointers */
2902 tdba = tx_ring->dma;
2903 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2904 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2905 ew32(TDBAH(0), (tdba >> 32));
2906 ew32(TDLEN(0), tdlen);
2907 ew32(TDH(0), 0);
2908 ew32(TDT(0), 0);
2909 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2910 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2911
bc7f75fa
AK		 2912 /* Set the Tx Interrupt Delay register */
2913 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2914 /* Tx irq moderation */
bc7f75fa
AK		 2915 ew32(TADV, adapter->tx_abs_int_delay);
2916
3a3b7586
JB		 2917 if (adapter->flags2 & FLAG2_DMA_BURST) {
2918 u32 txdctl = er32(TXDCTL(0));
2919 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2920 E1000_TXDCTL_WTHRESH);
e921eb1a 2921 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2922 * hardware to use the bus more efficiently in bursts, depends
2923 * on the tx_int_delay to be enabled,
8edc0e62 2924 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2925 * hthresh = 1 ==> prefetch when one or more available
2926 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2927 * BEWARE: this seems to work but should be considered first if
af667a29 2928 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2929 */
2930 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2931 ew32(TXDCTL(0), txdctl);
3a3b7586 2932 }
56032be7
BA		 2933 /* erratum work around: set txdctl the same for both queues */
2934 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2935
bc7f75fa 2936 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2937 tarc = er32(TARC(0));
e921eb1a 2938 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2939 * gigabit link later
2940 */
bc7f75fa
AK		 2941#define SPEED_MODE_BIT (1 << 21)
2942 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2943 ew32(TARC(0), tarc);
bc7f75fa
AK		 2944 }
2945
2946 /* errata: program both queues to unweighted RR */
2947 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2948 tarc = er32(TARC(0));
bc7f75fa 2949 tarc |= 1;
e9ec2c0f
JK		 2950 ew32(TARC(0), tarc);
2951 tarc = er32(TARC(1));
bc7f75fa 2952 tarc |= 1;
e9ec2c0f 2953 ew32(TARC(1), tarc);
bc7f75fa
AK		 2954 }
2955
bc7f75fa
AK		 2956 /* Setup Transmit Descriptor Settings for eop descriptor */
2957 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2958
2959 /* only set IDE if we are delaying interrupts using the timers */
2960 if (adapter->tx_int_delay)
2961 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2962
2963 /* enable Report Status bit */
2964 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2965
57cde763 2966 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2967}
2968
2969/**
2970 * e1000_setup_rctl - configure the receive control registers
2971 * @adapter: Board private structure
2972 **/
2973#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2974 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2975static void e1000_setup_rctl(struct e1000_adapter *adapter)
2976{
2977 struct e1000_hw *hw = &adapter->hw;
2978 u32 rctl, rfctl;
bc7f75fa
AK		 2979 u32 pages = 0;
2980
2fbe4526
BA		 2981 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2982 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2983 s32 ret_val;
2984
2985 if (adapter->netdev->mtu > ETH_DATA_LEN)
2986 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2987 else
2988 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2989
2990 if (ret_val)
2991 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2992 }
2993
bc7f75fa
AK		 2994 /* Program MC offset vector base */
2995 rctl = er32(RCTL);
2996 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2997 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 2998 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2999 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3000
3001 /* Do not Store bad packets */
3002 rctl &= ~E1000_RCTL_SBP;
3003
3004 /* Enable Long Packet receive */
3005 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3006 rctl &= ~E1000_RCTL_LPE;
3007 else
3008 rctl |= E1000_RCTL_LPE;
3009
eb7c3adb
JK		 3010 /* Some systems expect that the CRC is included in SMBUS traffic. The
3011 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3012 * host memory when this is enabled
3013 */
3014 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3015 rctl |= E1000_RCTL_SECRC;
5918bd88 3016
a4f58f54
BA		 3017 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3018 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3019 u16 phy_data;
3020
3021 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3022 phy_data &= 0xfff8;
3023 phy_data |= (1 << 2);
3024 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3025
3026 e1e_rphy(hw, 22, &phy_data);
3027 phy_data &= 0x0fff;
3028 phy_data |= (1 << 14);
3029 e1e_wphy(hw, 0x10, 0x2823);
3030 e1e_wphy(hw, 0x11, 0x0003);
3031 e1e_wphy(hw, 22, phy_data);
3032 }
3033
bc7f75fa
AK		 3034 /* Setup buffer sizes */
3035 rctl &= ~E1000_RCTL_SZ_4096;
3036 rctl |= E1000_RCTL_BSEX;
3037 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3038 case 2048:
3039 default:
3040 rctl |= E1000_RCTL_SZ_2048;
3041 rctl &= ~E1000_RCTL_BSEX;
3042 break;
3043 case 4096:
3044 rctl |= E1000_RCTL_SZ_4096;
3045 break;
3046 case 8192:
3047 rctl |= E1000_RCTL_SZ_8192;
3048 break;
3049 case 16384:
3050 rctl |= E1000_RCTL_SZ_16384;
3051 break;
3052 }
3053
5f450212
BA		 3054 /* Enable Extended Status in all Receive Descriptors */
3055 rfctl = er32(RFCTL);
3056 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3057 ew32(RFCTL, rfctl);
5f450212 3058
e921eb1a 3059 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3060 * header is placed in skb->data and the packet data is
3061 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3062 * In the case of a non-split, skb->data is linearly filled,
3063 * followed by the page buffers. Therefore, skb->data is
3064 * sized to hold the largest protocol header.
3065 *
3066 * allocations using alloc_page take too long for regular MTU
3067 * so only enable packet split for jumbo frames
3068 *
3069 * Using pages when the page size is greater than 16k wastes
3070 * a lot of memory, since we allocate 3 pages at all times
3071 * per packet.
3072 */
bc7f75fa 3073 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3074 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3075 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3076 else
3077 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3078
3079 if (adapter->rx_ps_pages) {
90da0669
BA		 3080 u32 psrctl = 0;
3081
140a7480
AK		 3082 /* Enable Packet split descriptors */
3083 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3084
e5fe2541 3085 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3086
3087 switch (adapter->rx_ps_pages) {
3088 case 3:
e5fe2541
BA		 3089 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3090 /* fall-through */
bc7f75fa 3091 case 2:
e5fe2541
BA		 3092 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3093 /* fall-through */
bc7f75fa 3094 case 1:
e5fe2541 3095 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3096 break;
3097 }
3098
3099 ew32(PSRCTL, psrctl);
3100 }
3101
cf955e6c
BG		 3102 /* This is useful for sniffing bad packets. */
3103 if (adapter->netdev->features & NETIF_F_RXALL) {
3104 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3105 * in e1000e_set_rx_mode
3106 */
cf955e6c
BG		 3107 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3108 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3109 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3110
3111 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3112 E1000_RCTL_DPF | /* Allow filtered pause */
3113 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3114 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3115 * and that breaks VLANs.
3116 */
3117 }
3118
bc7f75fa 3119 ew32(RCTL, rctl);
318a94d6 3120 /* just started the receive unit, no need to restart */
12d43f7d 3121 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3122}
3123
3124/**
3125 * e1000_configure_rx - Configure Receive Unit after Reset
3126 * @adapter: board private structure
3127 *
3128 * Configure the Rx unit of the MAC after a reset.
3129 **/
3130static void e1000_configure_rx(struct e1000_adapter *adapter)
3131{
3132 struct e1000_hw *hw = &adapter->hw;
3133 struct e1000_ring *rx_ring = adapter->rx_ring;
3134 u64 rdba;
3135 u32 rdlen, rctl, rxcsum, ctrl_ext;
3136
3137 if (adapter->rx_ps_pages) {
3138 /* this is a 32 byte descriptor */
3139 rdlen = rx_ring->count *
af667a29 3140 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3141 adapter->clean_rx = e1000_clean_rx_irq_ps;
3142 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3143 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3144 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3145 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3146 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3147 } else {
5f450212 3148 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3149 adapter->clean_rx = e1000_clean_rx_irq;
3150 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3151 }
3152
3153 /* disable receives while setting up the descriptors */
3154 rctl = er32(RCTL);
7f99ae63
BA		 3155 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3156 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3157 e1e_flush();
1bba4386 3158 usleep_range(10000, 20000);
bc7f75fa 3159
3a3b7586 3160 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3161 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3162 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3163 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3164 * granularity = 01
3165 * wthresh = 04,
3166 * hthresh = 04,
3167 * pthresh = 0x20
3168 */
3169 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3170 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3171
e921eb1a 3172 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3173 * the value was not set by the user via module options
3174 */
3175 if (adapter->rx_int_delay == DEFAULT_RDTR)
3176 adapter->rx_int_delay = BURST_RDTR;
3177 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3178 adapter->rx_abs_int_delay = BURST_RADV;
3179 }
3180
bc7f75fa
AK		 3181 /* set the Receive Delay Timer Register */
3182 ew32(RDTR, adapter->rx_int_delay);
3183
3184 /* irq moderation */
3185 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3186 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3187 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3188
3189 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3190 /* Auto-Mask interrupts upon ICR access */
3191 ctrl_ext |= E1000_CTRL_EXT_IAME;
3192 ew32(IAM, 0xffffffff);
3193 ew32(CTRL_EXT, ctrl_ext);
3194 e1e_flush();
3195
e921eb1a 3196 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3197 * the Base and Length of the Rx Descriptor Ring
3198 */
bc7f75fa 3199 rdba = rx_ring->dma;
1e36052e
BA		 3200 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3201 ew32(RDBAH(0), (rdba >> 32));
3202 ew32(RDLEN(0), rdlen);
3203 ew32(RDH(0), 0);
3204 ew32(RDT(0), 0);
3205 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3206 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3207
3208 /* Enable Receive Checksum Offload for TCP and UDP */
3209 rxcsum = er32(RXCSUM);
2e1706f2 3210 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3211 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3212 else
bc7f75fa 3213 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3214 ew32(RXCSUM, rxcsum);
3215
3e35d991
BA		 3216 /* With jumbo frames, excessive C-state transition latencies result
3217 * in dropped transactions.
3218 */
3219 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3220 u32 lat =
3221 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3222 adapter->max_frame_size) * 8 / 1000;
3223
3224 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3225 u32 rxdctl = er32(RXDCTL(0));
3226 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3227 }
3e35d991
BA		 3228
3229 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3230 } else {
3231 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3232 PM_QOS_DEFAULT_VALUE);
97ac8cae 3233 }
bc7f75fa
AK		 3234
3235 /* Enable Receives */
3236 ew32(RCTL, rctl);
3237}
3238
3239/**
ef9b965a
JB		 3240 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3241 * @netdev: network interface device structure
bc7f75fa 3242 *
ef9b965a
JB		 3243 * Writes multicast address list to the MTA hash table.
3244 * Returns: -ENOMEM on failure
3245 * 0 on no addresses written
3246 * X on writing X addresses to MTA
3247 */
3248static int e1000e_write_mc_addr_list(struct net_device *netdev)
3249{
3250 struct e1000_adapter *adapter = netdev_priv(netdev);
3251 struct e1000_hw *hw = &adapter->hw;
3252 struct netdev_hw_addr *ha;
3253 u8 *mta_list;
3254 int i;
3255
3256 if (netdev_mc_empty(netdev)) {
3257 /* nothing to program, so clear mc list */
3258 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3259 return 0;
3260 }
3261
3262 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3263 if (!mta_list)
3264 return -ENOMEM;
3265
3266 /* update_mc_addr_list expects a packed array of only addresses. */
3267 i = 0;
3268 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3269 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3270
3271 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3272 kfree(mta_list);
3273
3274 return netdev_mc_count(netdev);
3275}
3276
3277/**
3278 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3279 * @netdev: network interface device structure
bc7f75fa 3280 *
ef9b965a
JB		 3281 * Writes unicast address list to the RAR table.
3282 * Returns: -ENOMEM on failure/insufficient address space
3283 * 0 on no addresses written
3284 * X on writing X addresses to the RAR table
bc7f75fa 3285 **/
ef9b965a 3286static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3287{
ef9b965a
JB		 3288 struct e1000_adapter *adapter = netdev_priv(netdev);
3289 struct e1000_hw *hw = &adapter->hw;
3290 unsigned int rar_entries = hw->mac.rar_entry_count;
3291 int count = 0;
3292
3293 /* save a rar entry for our hardware address */
3294 rar_entries--;
3295
3296 /* save a rar entry for the LAA workaround */
3297 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3298 rar_entries--;
3299
3300 /* return ENOMEM indicating insufficient memory for addresses */
3301 if (netdev_uc_count(netdev) > rar_entries)
3302 return -ENOMEM;
3303
3304 if (!netdev_uc_empty(netdev) && rar_entries) {
3305 struct netdev_hw_addr *ha;
3306
e921eb1a 3307 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3308 * combining
3309 */
3310 netdev_for_each_uc_addr(ha, netdev) {
3311 if (!rar_entries)
3312 break;
69e1e019 3313 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3314 count++;
3315 }
3316 }
3317
3318 /* zero out the remaining RAR entries not used above */
3319 for (; rar_entries > 0; rar_entries--) {
3320 ew32(RAH(rar_entries), 0);
3321 ew32(RAL(rar_entries), 0);
3322 }
3323 e1e_flush();
3324
3325 return count;
bc7f75fa
AK		 3326}
3327
3328/**
ef9b965a 3329 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3330 * @netdev: network interface device structure
3331 *
ef9b965a
JB		 3332 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3333 * address list or the network interface flags are updated. This routine is
3334 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3335 * promiscuous mode, and all-multi behavior.
3336 **/
ef9b965a 3337static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3338{
3339 struct e1000_adapter *adapter = netdev_priv(netdev);
3340 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3341 u32 rctl;
bc7f75fa
AK		 3342
3343 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3344 rctl = er32(RCTL);
3345
ef9b965a
JB		 3346 /* clear the affected bits */
3347 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3348
bc7f75fa
AK		 3349 if (netdev->flags & IFF_PROMISC) {
3350 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3351 /* Do not hardware filter VLANs in promisc mode */
3352 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3353 } else {
ef9b965a 3354 int count;
3d3a1676 3355
746b9f02
PM		 3356 if (netdev->flags & IFF_ALLMULTI) {
3357 rctl |= E1000_RCTL_MPE;
746b9f02 3358 } else {
e921eb1a 3359 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3360 * then we should just turn on promiscuous mode so
3361 * that we can at least receive multicast traffic
3362 */
3363 count = e1000e_write_mc_addr_list(netdev);
3364 if (count < 0)
3365 rctl |= E1000_RCTL_MPE;
746b9f02 3366 }
86d70e53 3367 e1000e_vlan_filter_enable(adapter);
e921eb1a 3368 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3369 * sufficient space to store all the addresses then enable
3370 * unicast promiscuous mode
bc7f75fa 3371 */
ef9b965a
JB		 3372 count = e1000e_write_uc_addr_list(netdev);
3373 if (count < 0)
3374 rctl |= E1000_RCTL_UPE;
bc7f75fa 3375 }
86d70e53 3376
ef9b965a
JB		 3377 ew32(RCTL, rctl);
3378
f646968f 3379 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3380 e1000e_vlan_strip_enable(adapter);
3381 else
3382 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3383}
3384
70495a50
BA		 3385static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3386{
3387 struct e1000_hw *hw = &adapter->hw;
3388 u32 mrqc, rxcsum;
3389 int i;
3390 static const u32 rsskey[10] = {
3391 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3392 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3393 };
3394
3395 /* Fill out hash function seed */
3396 for (i = 0; i < 10; i++)
3397 ew32(RSSRK(i), rsskey[i]);
3398
3399 /* Direct all traffic to queue 0 */
3400 for (i = 0; i < 32; i++)
3401 ew32(RETA(i), 0);
3402
e921eb1a 3403 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3404 * descriptor on writeback.
3405 */
3406 rxcsum = er32(RXCSUM);
3407 rxcsum |= E1000_RXCSUM_PCSD;
3408
3409 ew32(RXCSUM, rxcsum);
3410
3411 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3412 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3413 E1000_MRQC_RSS_FIELD_IPV6 |
3414 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3415 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3416
3417 ew32(MRQC, mrqc);
3418}
3419
b67e1913
BA		 3420/**
3421 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3422 * @adapter: board private structure
3423 * @timinca: pointer to returned time increment attributes
3424 *
3425 * Get attributes for incrementing the System Time Register SYSTIML/H at
3426 * the default base frequency, and set the cyclecounter shift value.
3427 **/
d89777bf 3428s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3429{
3430 struct e1000_hw *hw = &adapter->hw;
3431 u32 incvalue, incperiod, shift;
3432
3433 /* Make sure clock is enabled on I217 before checking the frequency */
3434 if ((hw->mac.type == e1000_pch_lpt) &&
3435 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3436 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3437 u32 fextnvm7 = er32(FEXTNVM7);
3438
3439 if (!(fextnvm7 & (1 << 0))) {
3440 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3441 e1e_flush();
3442 }
3443 }
3444
3445 switch (hw->mac.type) {
3446 case e1000_pch2lan:
3447 case e1000_pch_lpt:
3448 /* On I217, the clock frequency is 25MHz or 96MHz as
3449 * indicated by the System Clock Frequency Indication
3450 */
3451 if ((hw->mac.type != e1000_pch_lpt) ||
3452 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3453 /* Stable 96MHz frequency */
3454 incperiod = INCPERIOD_96MHz;
3455 incvalue = INCVALUE_96MHz;
3456 shift = INCVALUE_SHIFT_96MHz;
3457 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3458 break;
3459 }
3460 /* fall-through */
3461 case e1000_82574:
3462 case e1000_82583:
3463 /* Stable 25MHz frequency */
3464 incperiod = INCPERIOD_25MHz;
3465 incvalue = INCVALUE_25MHz;
3466 shift = INCVALUE_SHIFT_25MHz;
3467 adapter->cc.shift = shift;
3468 break;
3469 default:
3470 return -EINVAL;
3471 }
3472
3473 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3474 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3475
3476 return 0;
3477}
3478
3479/**
3480 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3481 * @adapter: board private structure
3482 *
3483 * Outgoing time stamping can be enabled and disabled. Play nice and
3484 * disable it when requested, although it shouldn't cause any overhead
3485 * when no packet needs it. At most one packet in the queue may be
3486 * marked for time stamping, otherwise it would be impossible to tell
3487 * for sure to which packet the hardware time stamp belongs.
3488 *
3489 * Incoming time stamping has to be configured via the hardware filters.
3490 * Not all combinations are supported, in particular event type has to be
3491 * specified. Matching the kind of event packet is not supported, with the
3492 * exception of "all V2 events regardless of level 2 or 4".
3493 **/
3494static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3495{
3496 struct e1000_hw *hw = &adapter->hw;
3497 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3498 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3499 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3500 u32 rxmtrl = 0;
3501 u16 rxudp = 0;
3502 bool is_l4 = false;
3503 bool is_l2 = false;
b67e1913
BA		 3504 u32 regval;
3505 s32 ret_val;
3506
3507 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3508 return -EINVAL;
3509
3510 /* flags reserved for future extensions - must be zero */
3511 if (config->flags)
3512 return -EINVAL;
3513
3514 switch (config->tx_type) {
3515 case HWTSTAMP_TX_OFF:
3516 tsync_tx_ctl = 0;
3517 break;
3518 case HWTSTAMP_TX_ON:
3519 break;
3520 default:
3521 return -ERANGE;
3522 }
3523
3524 switch (config->rx_filter) {
3525 case HWTSTAMP_FILTER_NONE:
3526 tsync_rx_ctl = 0;
3527 break;
d89777bf
BA		 3528 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3529 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3530 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3531 is_l4 = true;
3532 break;
3533 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3534 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3535 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3536 is_l4 = true;
3537 break;
3538 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3539 /* Also time stamps V2 L2 Path Delay Request/Response */
3540 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3541 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3542 is_l2 = true;
3543 break;
3544 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3545 /* Also time stamps V2 L2 Path Delay Request/Response. */
3546 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3547 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3548 is_l2 = true;
3549 break;
3550 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3551 /* Hardware cannot filter just V2 L4 Sync messages;
3552 * fall-through to V2 (both L2 and L4) Sync.
3553 */
3554 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3555 /* Also time stamps V2 Path Delay Request/Response. */
3556 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3557 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3558 is_l2 = true;
3559 is_l4 = true;
3560 break;
3561 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3562 /* Hardware cannot filter just V2 L4 Delay Request messages;
3563 * fall-through to V2 (both L2 and L4) Delay Request.
3564 */
3565 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3566 /* Also time stamps V2 Path Delay Request/Response. */
3567 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3568 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3569 is_l2 = true;
3570 is_l4 = true;
3571 break;
3572 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3573 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3574 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3575 * fall-through to all V2 (both L2 and L4) Events.
3576 */
3577 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3578 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3579 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3580 is_l2 = true;
3581 is_l4 = true;
3582 break;
3583 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3584 /* For V1, the hardware can only filter Sync messages or
3585 * Delay Request messages but not both so fall-through to
3586 * time stamp all packets.
3587 */
b67e1913 3588 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3589 is_l2 = true;
3590 is_l4 = true;
b67e1913
BA		 3591 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3592 config->rx_filter = HWTSTAMP_FILTER_ALL;
3593 break;
3594 default:
3595 return -ERANGE;
3596 }
3597
3598 /* enable/disable Tx h/w time stamping */
3599 regval = er32(TSYNCTXCTL);
3600 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3601 regval |= tsync_tx_ctl;
3602 ew32(TSYNCTXCTL, regval);
3603 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3604 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3605 e_err("Timesync Tx Control register not set as expected\n");
3606 return -EAGAIN;
3607 }
3608
3609 /* enable/disable Rx h/w time stamping */
3610 regval = er32(TSYNCRXCTL);
3611 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3612 regval |= tsync_rx_ctl;
3613 ew32(TSYNCRXCTL, regval);
3614 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3615 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3616 (regval & (E1000_TSYNCRXCTL_ENABLED |
3617 E1000_TSYNCRXCTL_TYPE_MASK))) {
3618 e_err("Timesync Rx Control register not set as expected\n");
3619 return -EAGAIN;
3620 }
3621
d89777bf
BA		 3622 /* L2: define ethertype filter for time stamped packets */
3623 if (is_l2)
3624 rxmtrl |= ETH_P_1588;
3625
3626 /* define which PTP packets get time stamped */
3627 ew32(RXMTRL, rxmtrl);
3628
3629 /* Filter by destination port */
3630 if (is_l4) {
3631 rxudp = PTP_EV_PORT;
3632 cpu_to_be16s(&rxudp);
3633 }
3634 ew32(RXUDP, rxudp);
3635
3636 e1e_flush();
3637
b67e1913 3638 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3639 er32(RXSTMPH);
3640 er32(TXSTMPH);
b67e1913
BA		 3641
3642 /* Get and set the System Time Register SYSTIM base frequency */
3643 ret_val = e1000e_get_base_timinca(adapter, &regval);
3644 if (ret_val)
3645 return ret_val;
3646 ew32(TIMINCA, regval);
3647
3648 /* reset the ns time counter */
3649 timecounter_init(&adapter->tc, &adapter->cc,
3650 ktime_to_ns(ktime_get_real()));
3651
3652 return 0;
3653}
3654
bc7f75fa 3655/**
ad68076e 3656 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3657 * @adapter: private board structure
3658 **/
3659static void e1000_configure(struct e1000_adapter *adapter)
3660{
55aa6985
BA		 3661 struct e1000_ring *rx_ring = adapter->rx_ring;
3662
ef9b965a 3663 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3664
3665 e1000_restore_vlan(adapter);
cd791618 3666 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3667
3668 e1000_configure_tx(adapter);
70495a50
BA		 3669
3670 if (adapter->netdev->features & NETIF_F_RXHASH)
3671 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3672 e1000_setup_rctl(adapter);
3673 e1000_configure_rx(adapter);
55aa6985 3674 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3675}
3676
3677/**
3678 * e1000e_power_up_phy - restore link in case the phy was powered down
3679 * @adapter: address of board private structure
3680 *
3681 * The phy may be powered down to save power and turn off link when the
3682 * driver is unloaded and wake on lan is not enabled (among others)
3683 * *** this routine MUST be followed by a call to e1000e_reset ***
3684 **/
3685void e1000e_power_up_phy(struct e1000_adapter *adapter)
3686{
17f208de
BA		 3687 if (adapter->hw.phy.ops.power_up)
3688 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3689
3690 adapter->hw.mac.ops.setup_link(&adapter->hw);
3691}
3692
3693/**
3694 * e1000_power_down_phy - Power down the PHY
3695 *
17f208de
BA		 3696 * Power down the PHY so no link is implied when interface is down.
3697 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3698 */
3699static void e1000_power_down_phy(struct e1000_adapter *adapter)
3700{
bc7f75fa 3701 /* WoL is enabled */
23b66e2b 3702 if (adapter->wol)
bc7f75fa
AK		 3703 return;
3704
17f208de
BA		 3705 if (adapter->hw.phy.ops.power_down)
3706 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3707}
3708
3709/**
3710 * e1000e_reset - bring the hardware into a known good state
3711 *
3712 * This function boots the hardware and enables some settings that
3713 * require a configuration cycle of the hardware - those cannot be
3714 * set/changed during runtime. After reset the device needs to be
ad68076e 3715 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3716 */
3717void e1000e_reset(struct e1000_adapter *adapter)
3718{
3719 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3720 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3721 struct e1000_hw *hw = &adapter->hw;
3722 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3723 u32 pba = adapter->pba;
bc7f75fa
AK		 3724 u16 hwm;
3725
ad68076e 3726 /* reset Packet Buffer Allocation to default */
318a94d6 3727 ew32(PBA, pba);
df762464 3728
318a94d6 3729 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3730 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3731 * large enough to accommodate two full transmit packets,
3732 * rounded up to the next 1KB and expressed in KB. Likewise,
3733 * the Rx FIFO should be large enough to accommodate at least
3734 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3735 * expressed in KB.
3736 */
df762464 3737 pba = er32(PBA);
bc7f75fa 3738 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3739 tx_space = pba >> 16;
bc7f75fa 3740 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3741 pba &= 0xffff;
e921eb1a 3742 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3743 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3744 */
3745 min_tx_space = (adapter->max_frame_size +
e5fe2541 3746 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3747 min_tx_space = ALIGN(min_tx_space, 1024);
3748 min_tx_space >>= 10;
3749 /* software strips receive CRC, so leave room for it */
318a94d6 3750 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3751 min_rx_space = ALIGN(min_rx_space, 1024);
3752 min_rx_space >>= 10;
3753
e921eb1a 3754 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3755 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3756 * allocation, take space away from current Rx allocation
3757 */
df762464
AK		 3758 if ((tx_space < min_tx_space) &&
3759 ((min_tx_space - tx_space) < pba)) {
3760 pba -= min_tx_space - tx_space;
bc7f75fa 3761
e921eb1a 3762 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3763 * adjustment
ad68076e 3764 */
79d4e908 3765 if (pba < min_rx_space)
df762464 3766 pba = min_rx_space;
bc7f75fa 3767 }
df762464
AK		 3768
3769 ew32(PBA, pba);
bc7f75fa
AK		 3770 }
3771
e921eb1a 3772 /* flow control settings
ad68076e 3773 *
38eb394e 3774 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3775 * (or the size used for early receive) above it in the Rx FIFO.
3776 * Set it to the lower of:
3777 * - 90% of the Rx FIFO size, and
38eb394e 3778 * - the full Rx FIFO size minus one full frame
ad68076e 3779 */
d3738bb8
BA		 3780 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3781 fc->pause_time = 0xFFFF;
3782 else
3783 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3784 fc->send_xon = true;
d3738bb8
BA		 3785 fc->current_mode = fc->requested_mode;
3786
3787 switch (hw->mac.type) {
79d4e908
BA		 3788 case e1000_ich9lan:
3789 case e1000_ich10lan:
3790 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3791 pba = 14;
3792 ew32(PBA, pba);
3793 fc->high_water = 0x2800;
3794 fc->low_water = fc->high_water - 8;
3795 break;
3796 }
3797 /* fall-through */
d3738bb8 3798 default:
79d4e908
BA		 3799 hwm = min(((pba << 10) * 9 / 10),
3800 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3801
3802 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3803 fc->low_water = fc->high_water - 8;
3804 break;
3805 case e1000_pchlan:
e921eb1a 3806 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3807 * loads. If hangs persist, try disabling Tx flow control.
3808 */
3809 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3810 fc->high_water = 0x3500;
3811 fc->low_water = 0x1500;
3812 } else {
3813 fc->high_water = 0x5000;
3814 fc->low_water = 0x3000;
3815 }
a305595b 3816 fc->refresh_time = 0x1000;
d3738bb8
BA		 3817 break;
3818 case e1000_pch2lan:
2fbe4526 3819 case e1000_pch_lpt:
d3738bb8 3820 fc->refresh_time = 0x0400;
347b5201
BA		 3821
3822 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3823 fc->high_water = 0x05C20;
3824 fc->low_water = 0x05048;
3825 fc->pause_time = 0x0650;
3826 break;
828bac87 3827 }
347b5201
BA		 3828
3829 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3830 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3831 break;
38eb394e 3832 }
bc7f75fa 3833
e921eb1a 3834 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3835 * maximum size per Tx descriptor limited only to the transmit
3836 * allocation of the packet buffer minus 96 bytes with an upper
3837 * limit of 24KB due to receive synchronization limitations.
3838 */
3839 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3840 24 << 10);
3841
e921eb1a 3842 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3843 * fit in receive buffer.
828bac87
BA		 3844 */
3845 if (adapter->itr_setting & 0x3) {
79d4e908 3846 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3847 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3848 dev_info(&adapter->pdev->dev,
17e813ec 3849 "Interrupt Throttle Rate off\n");
828bac87 3850 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3851 e1000e_write_itr(adapter, 0);
828bac87
BA		 3852 }
3853 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3854 dev_info(&adapter->pdev->dev,
17e813ec 3855 "Interrupt Throttle Rate on\n");
828bac87
BA		 3856 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3857 adapter->itr = 20000;
22a4cca2 3858 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3859 }
3860 }
3861
bc7f75fa
AK		 3862 /* Allow time for pending master requests to run */
3863 mac->ops.reset_hw(hw);
97ac8cae 3864
e921eb1a 3865 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3866 * that the network interface is in control
3867 */
c43bc57e 3868 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3869 e1000e_get_hw_control(adapter);
97ac8cae 3870
bc7f75fa
AK		 3871 ew32(WUC, 0);
3872
3873 if (mac->ops.init_hw(hw))
44defeb3 3874 e_err("Hardware Error\n");
bc7f75fa
AK		 3875
3876 e1000_update_mng_vlan(adapter);
3877
3878 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3879 ew32(VET, ETH_P_8021Q);
3880
3881 e1000e_reset_adaptive(hw);
31dbe5b4 3882
b67e1913
BA		 3883 /* initialize systim and reset the ns time counter */
3884 e1000e_config_hwtstamp(adapter);
3885
d495bcb8
BA		 3886 /* Set EEE advertisement as appropriate */
3887 if (adapter->flags2 & FLAG2_HAS_EEE) {
3888 s32 ret_val;
3889 u16 adv_addr;
3890
3891 switch (hw->phy.type) {
3892 case e1000_phy_82579:
3893 adv_addr = I82579_EEE_ADVERTISEMENT;
3894 break;
3895 case e1000_phy_i217:
3896 adv_addr = I217_EEE_ADVERTISEMENT;
3897 break;
3898 default:
3899 dev_err(&adapter->pdev->dev,
3900 "Invalid PHY type setting EEE advertisement\n");
3901 return;
3902 }
3903
3904 ret_val = hw->phy.ops.acquire(hw);
3905 if (ret_val) {
3906 dev_err(&adapter->pdev->dev,
3907 "EEE advertisement - unable to acquire PHY\n");
3908 return;
3909 }
3910
3911 e1000_write_emi_reg_locked(hw, adv_addr,
3912 hw->dev_spec.ich8lan.eee_disable ?
3913 0 : adapter->eee_advert);
3914
3915 hw->phy.ops.release(hw);
3916 }
3917
31dbe5b4
BA		 3918 if (!netif_running(adapter->netdev) &&
3919 !test_bit(__E1000_TESTING, &adapter->state)) {
3920 e1000_power_down_phy(adapter);
3921 return;
3922 }
3923
bc7f75fa
AK		 3924 e1000_get_phy_info(hw);
3925
918d7197
BA		 3926 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3927 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3928 u16 phy_data = 0;
e921eb1a 3929 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3930 * the return value of this function because there is nothing
ad68076e
BA		 3931 * different we would do if it failed
3932 */
bc7f75fa
AK		 3933 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3934 phy_data &= ~IGP02E1000_PM_SPD;
3935 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3936 }
bc7f75fa
AK		 3937}
3938
3939int e1000e_up(struct e1000_adapter *adapter)
3940{
3941 struct e1000_hw *hw = &adapter->hw;
3942
3943 /* hardware has been reset, we need to reload some things */
3944 e1000_configure(adapter);
3945
3946 clear_bit(__E1000_DOWN, &adapter->state);
3947
4662e82b
BA		 3948 if (adapter->msix_entries)
3949 e1000_configure_msix(adapter);
bc7f75fa
AK		 3950 e1000_irq_enable(adapter);
3951
400484fa 3952 netif_start_queue(adapter->netdev);
4cb9be7a 3953
bc7f75fa 3954 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3955 if (adapter->msix_entries)
3956 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3957 else
3958 ew32(ICS, E1000_ICS_LSC);
3959
bc7f75fa
AK		 3960 return 0;
3961}
3962
713b3c9e
JB		 3963static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3964{
3965 struct e1000_hw *hw = &adapter->hw;
3966
3967 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3968 return;
3969
3970 /* flush pending descriptor writebacks to memory */
3971 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3972 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3973
3974 /* execute the writes immediately */
3975 e1e_flush();
bf03085f 3976
e921eb1a 3977 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3978 * write is successful
3979 */
3980 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3981 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3982
3983 /* execute the writes immediately */
3984 e1e_flush();
3985}
3986
67fd4fcb
JK		 3987static void e1000e_update_stats(struct e1000_adapter *adapter);
3988
bc7f75fa
AK		 3989void e1000e_down(struct e1000_adapter *adapter)
3990{
3991 struct net_device *netdev = adapter->netdev;
3992 struct e1000_hw *hw = &adapter->hw;
3993 u32 tctl, rctl;
3994
e921eb1a 3995 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3996 * reschedule our watchdog timer
3997 */
bc7f75fa
AK		 3998 set_bit(__E1000_DOWN, &adapter->state);
3999
4000 /* disable receives in the hardware */
4001 rctl = er32(RCTL);
7f99ae63
BA		 4002 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4003 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4004 /* flush and sleep below */
4005
4cb9be7a 4006 netif_stop_queue(netdev);
bc7f75fa
AK		 4007
4008 /* disable transmits in the hardware */
4009 tctl = er32(TCTL);
4010 tctl &= ~E1000_TCTL_EN;
4011 ew32(TCTL, tctl);
7f99ae63 4012
bc7f75fa
AK		 4013 /* flush both disables and wait for them to finish */
4014 e1e_flush();
1bba4386 4015 usleep_range(10000, 20000);
bc7f75fa 4016
bc7f75fa
AK		 4017 e1000_irq_disable(adapter);
4018
4019 del_timer_sync(&adapter->watchdog_timer);
4020 del_timer_sync(&adapter->phy_info_timer);
4021
bc7f75fa 4022 netif_carrier_off(netdev);
67fd4fcb
JK		 4023
4024 spin_lock(&adapter->stats64_lock);
4025 e1000e_update_stats(adapter);
4026 spin_unlock(&adapter->stats64_lock);
4027
400484fa 4028 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4029 e1000_clean_tx_ring(adapter->tx_ring);
4030 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4031
bc7f75fa
AK		 4032 adapter->link_speed = 0;
4033 adapter->link_duplex = 0;
4034
52cc3086
JK		 4035 if (!pci_channel_offline(adapter->pdev))
4036 e1000e_reset(adapter);
713b3c9e 4037
e921eb1a 4038 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 4039 * pci_disable_device here.
4040 */
4041}
4042
4043void e1000e_reinit_locked(struct e1000_adapter *adapter)
4044{
4045 might_sleep();
4046 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4047 usleep_range(1000, 2000);
bc7f75fa
AK		 4048 e1000e_down(adapter);
4049 e1000e_up(adapter);
4050 clear_bit(__E1000_RESETTING, &adapter->state);
4051}
4052
b67e1913
BA		 4053/**
4054 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4055 * @cc: cyclecounter structure
4056 **/
4057static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4058{
4059 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4060 cc);
4061 struct e1000_hw *hw = &adapter->hw;
4062 cycle_t systim;
4063
4064 /* latch SYSTIMH on read of SYSTIML */
4065 systim = (cycle_t)er32(SYSTIML);
4066 systim |= (cycle_t)er32(SYSTIMH) << 32;
4067
4068 return systim;
4069}
4070
bc7f75fa
AK		 4071/**
4072 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4073 * @adapter: board private structure to initialize
4074 *
4075 * e1000_sw_init initializes the Adapter private data structure.
4076 * Fields are initialized based on PCI device information and
4077 * OS network device settings (MTU size).
4078 **/
9f9a12f8 4079static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4080{
bc7f75fa
AK		 4081 struct net_device *netdev = adapter->netdev;
4082
4083 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4084 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4085 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4086 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4087 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4088 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4089
67fd4fcb
JK		 4090 spin_lock_init(&adapter->stats64_lock);
4091
4662e82b 4092 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4093
4662e82b
BA		 4094 if (e1000_alloc_queues(adapter))
4095 return -ENOMEM;
bc7f75fa 4096
b67e1913
BA		 4097 /* Setup hardware time stamping cyclecounter */
4098 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4099 adapter->cc.read = e1000e_cyclecounter_read;
4100 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4101 adapter->cc.mult = 1;
4102 /* cc.shift set in e1000e_get_base_tininca() */
4103
4104 spin_lock_init(&adapter->systim_lock);
4105 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4106 }
4107
bc7f75fa 4108 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4109 e1000_irq_disable(adapter);
4110
bc7f75fa
AK		 4111 set_bit(__E1000_DOWN, &adapter->state);
4112 return 0;
bc7f75fa
AK		 4113}
4114
f8d59f78
BA		 4115/**
4116 * e1000_intr_msi_test - Interrupt Handler
4117 * @irq: interrupt number
4118 * @data: pointer to a network interface device structure
4119 **/
8bb62869 4120static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4121{
4122 struct net_device *netdev = data;
4123 struct e1000_adapter *adapter = netdev_priv(netdev);
4124 struct e1000_hw *hw = &adapter->hw;
4125 u32 icr = er32(ICR);
4126
3bb99fe2 4127 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4128 if (icr & E1000_ICR_RXSEQ) {
4129 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4130 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4131 * interrupt is handled.
4132 */
f8d59f78
BA		 4133 wmb();
4134 }
4135
4136 return IRQ_HANDLED;
4137}
4138
4139/**
4140 * e1000_test_msi_interrupt - Returns 0 for successful test
4141 * @adapter: board private struct
4142 *
4143 * code flow taken from tg3.c
4144 **/
4145static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4146{
4147 struct net_device *netdev = adapter->netdev;
4148 struct e1000_hw *hw = &adapter->hw;
4149 int err;
4150
4151 /* poll_enable hasn't been called yet, so don't need disable */
4152 /* clear any pending events */
4153 er32(ICR);
4154
4155 /* free the real vector and request a test handler */
4156 e1000_free_irq(adapter);
4662e82b 4157 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4158
4159 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4160 * MSI irq handler will unset this flag
4161 */
f8d59f78
BA		 4162 adapter->flags |= FLAG_MSI_TEST_FAILED;
4163
4164 err = pci_enable_msi(adapter->pdev);
4165 if (err)
4166 goto msi_test_failed;
4167
a0607fd3 4168 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4169 netdev->name, netdev);
4170 if (err) {
4171 pci_disable_msi(adapter->pdev);
4172 goto msi_test_failed;
4173 }
4174
e921eb1a 4175 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4176 * interrupt.
4177 */
f8d59f78
BA		 4178 wmb();
4179
4180 e1000_irq_enable(adapter);
4181
4182 /* fire an unusual interrupt on the test handler */
4183 ew32(ICS, E1000_ICS_RXSEQ);
4184 e1e_flush();
569a3aff 4185 msleep(100);
f8d59f78
BA		 4186
4187 e1000_irq_disable(adapter);
4188
bc76329d 4189 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4190
4191 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4192 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4193 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4194 } else {
068e8a30 4195 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4196 }
f8d59f78
BA		 4197
4198 free_irq(adapter->pdev->irq, netdev);
4199 pci_disable_msi(adapter->pdev);
4200
f8d59f78 4201msi_test_failed:
4662e82b 4202 e1000e_set_interrupt_capability(adapter);
068e8a30 4203 return e1000_request_irq(adapter);
f8d59f78
BA		 4204}
4205
4206/**
4207 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4208 * @adapter: board private struct
4209 *
4210 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4211 **/
4212static int e1000_test_msi(struct e1000_adapter *adapter)
4213{
4214 int err;
4215 u16 pci_cmd;
4216
4217 if (!(adapter->flags & FLAG_MSI_ENABLED))
4218 return 0;
4219
4220 /* disable SERR in case the MSI write causes a master abort */
4221 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4222 if (pci_cmd & PCI_COMMAND_SERR)
4223 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4224 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4225
4226 err = e1000_test_msi_interrupt(adapter);
4227
36f2407f
DN		 4228 /* re-enable SERR */
4229 if (pci_cmd & PCI_COMMAND_SERR) {
4230 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4231 pci_cmd |= PCI_COMMAND_SERR;
4232 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4233 }
f8d59f78 4234
f8d59f78
BA		 4235 return err;
4236}
4237
bc7f75fa
AK		 4238/**
4239 * e1000_open - Called when a network interface is made active
4240 * @netdev: network interface device structure
4241 *
4242 * Returns 0 on success, negative value on failure
4243 *
4244 * The open entry point is called when a network interface is made
4245 * active by the system (IFF_UP). At this point all resources needed
4246 * for transmit and receive operations are allocated, the interrupt
4247 * handler is registered with the OS, the watchdog timer is started,
4248 * and the stack is notified that the interface is ready.
4249 **/
4250static int e1000_open(struct net_device *netdev)
4251{
4252 struct e1000_adapter *adapter = netdev_priv(netdev);
4253 struct e1000_hw *hw = &adapter->hw;
23606cf5 4254 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4255 int err;
4256
4257 /* disallow open during test */
4258 if (test_bit(__E1000_TESTING, &adapter->state))
4259 return -EBUSY;
4260
23606cf5
RW		 4261 pm_runtime_get_sync(&pdev->dev);
4262
9c563d20
JB		 4263 netif_carrier_off(netdev);
4264
bc7f75fa 4265 /* allocate transmit descriptors */
55aa6985 4266 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4267 if (err)
4268 goto err_setup_tx;
4269
4270 /* allocate receive descriptors */
55aa6985 4271 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4272 if (err)
4273 goto err_setup_rx;
4274
e921eb1a 4275 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4276 * interface is now open and reset the part to a known state.
4277 */
4278 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4279 e1000e_get_hw_control(adapter);
11b08be8
BA		 4280 e1000e_reset(adapter);
4281 }
4282
bc7f75fa
AK		 4283 e1000e_power_up_phy(adapter);
4284
4285 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4286 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4287 e1000_update_mng_vlan(adapter);
4288
79d4e908 4289 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4290 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4291 PM_QOS_DEFAULT_VALUE);
c128ec29 4292
e921eb1a 4293 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4294 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4295 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4296 * clean_rx handler before we do so.
4297 */
bc7f75fa
AK		 4298 e1000_configure(adapter);
4299
4300 err = e1000_request_irq(adapter);
4301 if (err)
4302 goto err_req_irq;
4303
e921eb1a 4304 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4305 * ignore e1000e MSI messages, which means we need to test our MSI
4306 * interrupt now
4307 */
4662e82b 4308 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4309 err = e1000_test_msi(adapter);
4310 if (err) {
4311 e_err("Interrupt allocation failed\n");
4312 goto err_req_irq;
4313 }
4314 }
4315
bc7f75fa
AK		 4316 /* From here on the code is the same as e1000e_up() */
4317 clear_bit(__E1000_DOWN, &adapter->state);
4318
4319 napi_enable(&adapter->napi);
4320
4321 e1000_irq_enable(adapter);
4322
09357b00 4323 adapter->tx_hang_recheck = false;
4cb9be7a 4324 netif_start_queue(netdev);
d55b53ff 4325
23606cf5 4326 adapter->idle_check = true;
66148bab 4327 hw->mac.get_link_status = true;
23606cf5
RW		 4328 pm_runtime_put(&pdev->dev);
4329
bc7f75fa 4330 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4331 if (adapter->msix_entries)
4332 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4333 else
4334 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4335
4336 return 0;
4337
4338err_req_irq:
31dbe5b4 4339 e1000e_release_hw_control(adapter);
bc7f75fa 4340 e1000_power_down_phy(adapter);
55aa6985 4341 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4342err_setup_rx:
55aa6985 4343 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4344err_setup_tx:
4345 e1000e_reset(adapter);
23606cf5 4346 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4347
4348 return err;
4349}
4350
4351/**
4352 * e1000_close - Disables a network interface
4353 * @netdev: network interface device structure
4354 *
4355 * Returns 0, this is not allowed to fail
4356 *
4357 * The close entry point is called when an interface is de-activated
4358 * by the OS. The hardware is still under the drivers control, but
4359 * needs to be disabled. A global MAC reset is issued to stop the
4360 * hardware, and all transmit and receive resources are freed.
4361 **/
4362static int e1000_close(struct net_device *netdev)
4363{
4364 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4365 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4366 int count = E1000_CHECK_RESET_COUNT;
4367
4368 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4369 usleep_range(10000, 20000);
bc7f75fa
AK		 4370
4371 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4372
4373 pm_runtime_get_sync(&pdev->dev);
4374
5f4a780d
BA		 4375 napi_disable(&adapter->napi);
4376
23606cf5
RW		 4377 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4378 e1000e_down(adapter);
4379 e1000_free_irq(adapter);
4380 }
bc7f75fa 4381 e1000_power_down_phy(adapter);
bc7f75fa 4382
55aa6985
BA		 4383 e1000e_free_tx_resources(adapter->tx_ring);
4384 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4385
e921eb1a 4386 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4387 * the same ID is registered on the host OS (let 8021q kill it)
4388 */
e5fe2541 4389 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4390 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4391 adapter->mng_vlan_id);
bc7f75fa 4392
e921eb1a 4393 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4394 * interface is now closed
4395 */
31dbe5b4
BA		 4396 if ((adapter->flags & FLAG_HAS_AMT) &&
4397 !test_bit(__E1000_TESTING, &adapter->state))
4398 e1000e_release_hw_control(adapter);
bc7f75fa 4399
3e35d991 4400 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4401
23606cf5
RW		 4402 pm_runtime_put_sync(&pdev->dev);
4403
bc7f75fa
AK		 4404 return 0;
4405}
fc830b78 4406
bc7f75fa
AK		 4407/**
4408 * e1000_set_mac - Change the Ethernet Address of the NIC
4409 * @netdev: network interface device structure
4410 * @p: pointer to an address structure
4411 *
4412 * Returns 0 on success, negative on failure
4413 **/
4414static int e1000_set_mac(struct net_device *netdev, void *p)
4415{
4416 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4417 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4418 struct sockaddr *addr = p;
4419
4420 if (!is_valid_ether_addr(addr->sa_data))
4421 return -EADDRNOTAVAIL;
4422
4423 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4424 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4425
69e1e019 4426 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4427
4428 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4429 /* activate the work around */
4430 e1000e_set_laa_state_82571(&adapter->hw, 1);
4431
e921eb1a 4432 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4433 * between the time RAR[0] gets clobbered and the time it
4434 * gets fixed (in e1000_watchdog), the actual LAA is in one
4435 * of the RARs and no incoming packets directed to this port
4436 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4437 * RAR[14]
4438 */
69e1e019
BA		 4439 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4440 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4441 }
4442
4443 return 0;
4444}
4445
a8f88ff5
JB		 4446/**
4447 * e1000e_update_phy_task - work thread to update phy
4448 * @work: pointer to our work struct
4449 *
4450 * this worker thread exists because we must acquire a
4451 * semaphore to read the phy, which we could msleep while
4452 * waiting for it, and we can't msleep in a timer.
4453 **/
4454static void e1000e_update_phy_task(struct work_struct *work)
4455{
4456 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4457 struct e1000_adapter,
4458 update_phy_task);
615b32af
JB		 4459
4460 if (test_bit(__E1000_DOWN, &adapter->state))
4461 return;
4462
a8f88ff5
JB		 4463 e1000_get_phy_info(&adapter->hw);
4464}
4465
e921eb1a
BA		 4466/**
4467 * e1000_update_phy_info - timre call-back to update PHY info
4468 * @data: pointer to adapter cast into an unsigned long
4469 *
ad68076e
BA		 4470 * Need to wait a few seconds after link up to get diagnostic information from
4471 * the phy
e921eb1a 4472 **/
bc7f75fa
AK		 4473static void e1000_update_phy_info(unsigned long data)
4474{
53aa82da 4475 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4476
4477 if (test_bit(__E1000_DOWN, &adapter->state))
4478 return;
4479
a8f88ff5 4480 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4481}
4482
8c7bbb92
BA		 4483/**
4484 * e1000e_update_phy_stats - Update the PHY statistics counters
4485 * @adapter: board private structure
2b6b168d
BA		 4486 *
4487 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4488 **/
4489static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4490{
4491 struct e1000_hw *hw = &adapter->hw;
4492 s32 ret_val;
4493 u16 phy_data;
4494
4495 ret_val = hw->phy.ops.acquire(hw);
4496 if (ret_val)
4497 return;
4498
e921eb1a 4499 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4500 * If not, set to the page with the PHY status registers.
4501 */
2b6b168d 4502 hw->phy.addr = 1;
8c7bbb92
BA		 4503 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4504 &phy_data);
4505 if (ret_val)
4506 goto release;
2b6b168d
BA		 4507 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4508 ret_val = hw->phy.ops.set_page(hw,
4509 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4510 if (ret_val)
4511 goto release;
4512 }
4513
8c7bbb92 4514 /* Single Collision Count */
2b6b168d
BA		 4515 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4516 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4517 if (!ret_val)
4518 adapter->stats.scc += phy_data;
4519
4520 /* Excessive Collision Count */
2b6b168d
BA		 4521 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4522 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4523 if (!ret_val)
4524 adapter->stats.ecol += phy_data;
4525
4526 /* Multiple Collision Count */
2b6b168d
BA		 4527 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4528 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4529 if (!ret_val)
4530 adapter->stats.mcc += phy_data;
4531
4532 /* Late Collision Count */
2b6b168d
BA		 4533 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4534 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4535 if (!ret_val)
4536 adapter->stats.latecol += phy_data;
4537
4538 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4539 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4540 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4541 if (!ret_val)
4542 hw->mac.collision_delta = phy_data;
4543
4544 /* Defer Count */
2b6b168d
BA		 4545 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4546 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4547 if (!ret_val)
4548 adapter->stats.dc += phy_data;
4549
4550 /* Transmit with no CRS */
2b6b168d
BA		 4551 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4552 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4553 if (!ret_val)
4554 adapter->stats.tncrs += phy_data;
4555
4556release:
4557 hw->phy.ops.release(hw);
4558}
4559
bc7f75fa
AK		 4560/**
4561 * e1000e_update_stats - Update the board statistics counters
4562 * @adapter: board private structure
4563 **/
67fd4fcb 4564static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4565{
7274c20f 4566 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4567 struct e1000_hw *hw = &adapter->hw;
4568 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4569
e921eb1a 4570 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4571 * connection is down.
4572 */
4573 if (adapter->link_speed == 0)
4574 return;
4575 if (pci_channel_offline(pdev))
4576 return;
4577
bc7f75fa
AK		 4578 adapter->stats.crcerrs += er32(CRCERRS);
4579 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4580 adapter->stats.gorc += er32(GORCL);
4581 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4582 adapter->stats.bprc += er32(BPRC);
4583 adapter->stats.mprc += er32(MPRC);
4584 adapter->stats.roc += er32(ROC);
4585
bc7f75fa 4586 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4587
4588 /* Half-duplex statistics */
4589 if (adapter->link_duplex == HALF_DUPLEX) {
4590 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4591 e1000e_update_phy_stats(adapter);
4592 } else {
4593 adapter->stats.scc += er32(SCC);
4594 adapter->stats.ecol += er32(ECOL);
4595 adapter->stats.mcc += er32(MCC);
4596 adapter->stats.latecol += er32(LATECOL);
4597 adapter->stats.dc += er32(DC);
4598
4599 hw->mac.collision_delta = er32(COLC);
4600
4601 if ((hw->mac.type != e1000_82574) &&
4602 (hw->mac.type != e1000_82583))
4603 adapter->stats.tncrs += er32(TNCRS);
4604 }
4605 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4606 }
8c7bbb92 4607
bc7f75fa
AK		 4608 adapter->stats.xonrxc += er32(XONRXC);
4609 adapter->stats.xontxc += er32(XONTXC);
4610 adapter->stats.xoffrxc += er32(XOFFRXC);
4611 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4612 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4613 adapter->stats.gotc += er32(GOTCL);
4614 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4615 adapter->stats.rnbc += er32(RNBC);
4616 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4617
4618 adapter->stats.mptc += er32(MPTC);
4619 adapter->stats.bptc += er32(BPTC);
4620
4621 /* used for adaptive IFS */
4622
4623 hw->mac.tx_packet_delta = er32(TPT);
4624 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4625
4626 adapter->stats.algnerrc += er32(ALGNERRC);
4627 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4628 adapter->stats.cexterr += er32(CEXTERR);
4629 adapter->stats.tsctc += er32(TSCTC);
4630 adapter->stats.tsctfc += er32(TSCTFC);
4631
bc7f75fa 4632 /* Fill out the OS statistics structure */
7274c20f
AK		 4633 netdev->stats.multicast = adapter->stats.mprc;
4634 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4635
4636 /* Rx Errors */
4637
e921eb1a 4638 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4639 * our own version based on RUC and ROC
4640 */
7274c20f 4641 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4642 adapter->stats.crcerrs + adapter->stats.algnerrc +
4643 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4644 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4645 adapter->stats.roc;
7274c20f
AK		 4646 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4647 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4648 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4649
4650 /* Tx Errors */
f0ff4398 4651 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4652 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4653 netdev->stats.tx_window_errors = adapter->stats.latecol;
4654 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4655
4656 /* Tx Dropped needs to be maintained elsewhere */
4657
bc7f75fa
AK		 4658 /* Management Stats */
4659 adapter->stats.mgptc += er32(MGTPTC);
4660 adapter->stats.mgprc += er32(MGTPRC);
4661 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4662
4663 /* Correctable ECC Errors */
4664 if (hw->mac.type == e1000_pch_lpt) {
4665 u32 pbeccsts = er32(PBECCSTS);
4666 adapter->corr_errors +=
4667 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4668 adapter->uncorr_errors +=
4669 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4670 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4671 }
bc7f75fa
AK		 4672}
4673
7c25769f
BA		 4674/**
4675 * e1000_phy_read_status - Update the PHY register status snapshot
4676 * @adapter: board private structure
4677 **/
4678static void e1000_phy_read_status(struct e1000_adapter *adapter)
4679{
4680 struct e1000_hw *hw = &adapter->hw;
4681 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4682
4683 if ((er32(STATUS) & E1000_STATUS_LU) &&
4684 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4685 int ret_val;
4686
e60b22c5 4687 pm_runtime_get_sync(&adapter->pdev->dev);
c2ade1a4
BA		 4688 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4689 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4690 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4691 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4692 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4693 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4694 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4695 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4696 if (ret_val)
44defeb3 4697 e_warn("Error reading PHY register\n");
e60b22c5 4698 pm_runtime_put_sync(&adapter->pdev->dev);
7c25769f 4699 } else {
e921eb1a 4700 /* Do not read PHY registers if link is not up
7c25769f
BA		 4701 * Set values to typical power-on defaults
4702 */
4703 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4704 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4705 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4706 BMSR_ERCAP);
4707 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4708 ADVERTISE_ALL | ADVERTISE_CSMA);
4709 phy->lpa = 0;
4710 phy->expansion = EXPANSION_ENABLENPAGE;
4711 phy->ctrl1000 = ADVERTISE_1000FULL;
4712 phy->stat1000 = 0;
4713 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4714 }
7c25769f
BA		 4715}
4716
bc7f75fa
AK		 4717static void e1000_print_link_info(struct e1000_adapter *adapter)
4718{
bc7f75fa
AK		 4719 struct e1000_hw *hw = &adapter->hw;
4720 u32 ctrl = er32(CTRL);
4721
8f12fe86 4722 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4723 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4724 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4725 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4726 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4727 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4728 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4729}
4730
0c6bdb30 4731static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4732{
4733 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4734 bool link_active = false;
318a94d6
JK		 4735 s32 ret_val = 0;
4736
e921eb1a 4737 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4738 * Rx sequence error interrupt. get_link_status will stay
4739 * false until the check_for_link establishes link
4740 * for copper adapters ONLY
4741 */
4742 switch (hw->phy.media_type) {
4743 case e1000_media_type_copper:
4744 if (hw->mac.get_link_status) {
4745 ret_val = hw->mac.ops.check_for_link(hw);
4746 link_active = !hw->mac.get_link_status;
4747 } else {
3db1cd5c 4748 link_active = true;
318a94d6
JK		 4749 }
4750 break;
4751 case e1000_media_type_fiber:
4752 ret_val = hw->mac.ops.check_for_link(hw);
4753 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4754 break;
4755 case e1000_media_type_internal_serdes:
4756 ret_val = hw->mac.ops.check_for_link(hw);
4757 link_active = adapter->hw.mac.serdes_has_link;
4758 break;
4759 default:
4760 case e1000_media_type_unknown:
4761 break;
4762 }
4763
4764 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4765 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4766 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4767 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4768 }
4769
4770 return link_active;
4771}
4772
4773static void e1000e_enable_receives(struct e1000_adapter *adapter)
4774{
4775 /* make sure the receive unit is started */
4776 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4777 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4778 struct e1000_hw *hw = &adapter->hw;
4779 u32 rctl = er32(RCTL);
4780 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4781 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4782 }
4783}
4784
ff10e13c
CW		 4785static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4786{
4787 struct e1000_hw *hw = &adapter->hw;
4788
e921eb1a 4789 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4790 * for hung state and reset, if two calls return true
4791 */
4792 if (e1000_check_phy_82574(hw))
4793 adapter->phy_hang_count++;
4794 else
4795 adapter->phy_hang_count = 0;
4796
4797 if (adapter->phy_hang_count > 1) {
4798 adapter->phy_hang_count = 0;
4799 schedule_work(&adapter->reset_task);
4800 }
4801}
4802
bc7f75fa
AK		 4803/**
4804 * e1000_watchdog - Timer Call-back
4805 * @data: pointer to adapter cast into an unsigned long
4806 **/
4807static void e1000_watchdog(unsigned long data)
4808{
53aa82da 4809 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4810
4811 /* Do the rest outside of interrupt context */
4812 schedule_work(&adapter->watchdog_task);
4813
4814 /* TODO: make this use queue_delayed_work() */
4815}
4816
4817static void e1000_watchdog_task(struct work_struct *work)
4818{
4819 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4820 struct e1000_adapter,
4821 watchdog_task);
bc7f75fa
AK		 4822 struct net_device *netdev = adapter->netdev;
4823 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4824 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4825 struct e1000_ring *tx_ring = adapter->tx_ring;
4826 struct e1000_hw *hw = &adapter->hw;
4827 u32 link, tctl;
bc7f75fa 4828
615b32af
JB		 4829 if (test_bit(__E1000_DOWN, &adapter->state))
4830 return;
4831
b405e8df 4832 link = e1000e_has_link(adapter);
318a94d6 4833 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4834 /* Cancel scheduled suspend requests. */
4835 pm_runtime_resume(netdev->dev.parent);
4836
318a94d6 4837 e1000e_enable_receives(adapter);
bc7f75fa 4838 goto link_up;
bc7f75fa
AK		 4839 }
4840
4841 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4842 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4843 e1000_update_mng_vlan(adapter);
4844
bc7f75fa
AK		 4845 if (link) {
4846 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4847 bool txb2b = true;
23606cf5
RW		 4848
4849 /* Cancel scheduled suspend requests. */
4850 pm_runtime_resume(netdev->dev.parent);
4851
318a94d6 4852 /* update snapshot of PHY registers on LSC */
7c25769f 4853 e1000_phy_read_status(adapter);
bc7f75fa 4854 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4855 &adapter->link_speed,
4856 &adapter->link_duplex);
bc7f75fa 4857 e1000_print_link_info(adapter);
e792cd91
KS		 4858
4859 /* check if SmartSpeed worked */
4860 e1000e_check_downshift(hw);
4861 if (phy->speed_downgraded)
4862 netdev_warn(netdev,
4863 "Link Speed was downgraded by SmartSpeed\n");
4864
e921eb1a 4865 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4866 * if link has autonegotiated at 10/100 half
4867 */
4868 if ((hw->phy.type == e1000_phy_igp_3 ||
4869 hw->phy.type == e1000_phy_bm) &&
4870 (hw->mac.autoneg == true) &&
4871 (adapter->link_speed == SPEED_10 ||
4872 adapter->link_speed == SPEED_100) &&
4873 (adapter->link_duplex == HALF_DUPLEX)) {
4874 u16 autoneg_exp;
4875
c2ade1a4 4876 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4877
c2ade1a4 4878 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4879 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4880 }
4881
f49c57e1 4882 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4883 adapter->tx_timeout_factor = 1;
4884 switch (adapter->link_speed) {
4885 case SPEED_10:
3db1cd5c 4886 txb2b = false;
10f1b492 4887 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4888 break;
4889 case SPEED_100:
3db1cd5c 4890 txb2b = false;
4c86e0b9 4891 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4892 break;
4893 }
4894
e921eb1a 4895 /* workaround: re-program speed mode bit after
ad68076e
BA		 4896 * link-up event
4897 */
bc7f75fa
AK		 4898 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4899 !txb2b) {
4900 u32 tarc0;
e9ec2c0f 4901 tarc0 = er32(TARC(0));
bc7f75fa 4902 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4903 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4904 }
4905
e921eb1a 4906 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4907 * some hardware issues
4908 */
bc7f75fa
AK		 4909 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4910 switch (adapter->link_speed) {
4911 case SPEED_10:
4912 case SPEED_100:
44defeb3 4913 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4914 netdev->features &= ~NETIF_F_TSO;
4915 netdev->features &= ~NETIF_F_TSO6;
4916 break;
4917 case SPEED_1000:
4918 netdev->features |= NETIF_F_TSO;
4919 netdev->features |= NETIF_F_TSO6;
4920 break;
4921 default:
4922 /* oops */
4923 break;
4924 }
4925 }
4926
e921eb1a 4927 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4928 * after setting TARC(0)
4929 */
bc7f75fa
AK		 4930 tctl = er32(TCTL);
4931 tctl |= E1000_TCTL_EN;
4932 ew32(TCTL, tctl);
4933
e921eb1a 4934 /* Perform any post-link-up configuration before
75eb0fad
BA		 4935 * reporting link up.
4936 */
4937 if (phy->ops.cfg_on_link_up)
4938 phy->ops.cfg_on_link_up(hw);
4939
bc7f75fa 4940 netif_carrier_on(netdev);
bc7f75fa
AK		 4941
4942 if (!test_bit(__E1000_DOWN, &adapter->state))
4943 mod_timer(&adapter->phy_info_timer,
4944 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4945 }
4946 } else {
4947 if (netif_carrier_ok(netdev)) {
4948 adapter->link_speed = 0;
4949 adapter->link_duplex = 0;
8f12fe86 4950 /* Link status message must follow this format */
7dbc1672 4951 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4952 netif_carrier_off(netdev);
bc7f75fa
AK		 4953 if (!test_bit(__E1000_DOWN, &adapter->state))
4954 mod_timer(&adapter->phy_info_timer,
4955 round_jiffies(jiffies + 2 * HZ));
4956
12d43f7d
BA		 4957 /* The link is lost so the controller stops DMA.
4958 * If there is queued Tx work that cannot be done
4959 * or if on an 8000ES2LAN which requires a Rx packet
4960 * buffer work-around on link down event, reset the
4961 * controller to flush the Tx/Rx packet buffers.
4962 * (Do the reset outside of interrupt context).
4963 */
4964 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4965 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4966 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4967 else
4968 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4969 LINK_TIMEOUT);
bc7f75fa
AK		 4970 }
4971 }
4972
4973link_up:
67fd4fcb 4974 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4975 e1000e_update_stats(adapter);
4976
4977 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4978 adapter->tpt_old = adapter->stats.tpt;
4979 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4980 adapter->colc_old = adapter->stats.colc;
4981
7c25769f
BA		 4982 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4983 adapter->gorc_old = adapter->stats.gorc;
4984 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4985 adapter->gotc_old = adapter->stats.gotc;
2084b114 4986 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4987
12d43f7d 4988 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4989 schedule_work(&adapter->reset_task);
4990 /* return immediately since reset is imminent */
4991 return;
bc7f75fa
AK		 4992 }
4993
12d43f7d
BA		 4994 e1000e_update_adaptive(&adapter->hw);
4995
eab2abf5
JB		 4996 /* Simple mode for Interrupt Throttle Rate (ITR) */
4997 if (adapter->itr_setting == 4) {
e921eb1a 4998 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4999 * Total asymmetrical Tx or Rx gets ITR=8000;
5000 * everyone else is between 2000-8000.
5001 */
5002 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5003 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5004 adapter->gotc - adapter->gorc :
5005 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5006 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5007
22a4cca2 5008 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5009 }
5010
ad68076e 5011 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5012 if (adapter->msix_entries)
5013 ew32(ICS, adapter->rx_ring->ims_val);
5014 else
5015 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5016
713b3c9e
JB		 5017 /* flush pending descriptors to memory before detecting Tx hang */
5018 e1000e_flush_descriptors(adapter);
5019
bc7f75fa 5020 /* Force detection of hung controller every watchdog period */
3db1cd5c 5021 adapter->detect_tx_hung = true;
bc7f75fa 5022
e921eb1a 5023 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5024 * reset from the other port. Set the appropriate LAA in RAR[0]
5025 */
bc7f75fa 5026 if (e1000e_get_laa_state_82571(hw))
69e1e019 5027 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5028
ff10e13c
CW		 5029 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5030 e1000e_check_82574_phy_workaround(adapter);
5031
b67e1913
BA		 5032 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5033 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5034 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5035 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5036 er32(RXSTMPH);
5037 adapter->rx_hwtstamp_cleared++;
5038 } else {
5039 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5040 }
5041 }
5042
bc7f75fa
AK		 5043 /* Reset the timer */
5044 if (!test_bit(__E1000_DOWN, &adapter->state))
5045 mod_timer(&adapter->watchdog_timer,
5046 round_jiffies(jiffies + 2 * HZ));
5047}
5048
5049#define E1000_TX_FLAGS_CSUM 0x00000001
5050#define E1000_TX_FLAGS_VLAN 0x00000002
5051#define E1000_TX_FLAGS_TSO 0x00000004
5052#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5053#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5054#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5055#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5056#define E1000_TX_FLAGS_VLAN_SHIFT 16
5057
55aa6985 5058static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5059{
bc7f75fa
AK		 5060 struct e1000_context_desc *context_desc;
5061 struct e1000_buffer *buffer_info;
5062 unsigned int i;
5063 u32 cmd_length = 0;
70443ae9 5064 u16 ipcse = 0, mss;
bc7f75fa 5065 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5066
3d5e33c9
BA		 5067 if (!skb_is_gso(skb))
5068 return 0;
bc7f75fa 5069
3d5e33c9 5070 if (skb_header_cloned(skb)) {
90da0669
BA		 5071 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5072
3d5e33c9
BA		 5073 if (err)
5074 return err;
bc7f75fa
AK		 5075 }
5076
3d5e33c9
BA		 5077 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5078 mss = skb_shinfo(skb)->gso_size;
5079 if (skb->protocol == htons(ETH_P_IP)) {
5080 struct iphdr *iph = ip_hdr(skb);
5081 iph->tot_len = 0;
5082 iph->check = 0;
5083 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5084 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5085 cmd_length = E1000_TXD_CMD_IP;
5086 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5087 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5088 ipv6_hdr(skb)->payload_len = 0;
5089 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5090 &ipv6_hdr(skb)->daddr,
5091 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5092 ipcse = 0;
5093 }
5094 ipcss = skb_network_offset(skb);
5095 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5096 tucss = skb_transport_offset(skb);
5097 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5098
5099 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5100 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5101
5102 i = tx_ring->next_to_use;
5103 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5104 buffer_info = &tx_ring->buffer_info[i];
5105
5106 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5107 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5108 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5109 context_desc->upper_setup.tcp_fields.tucss = tucss;
5110 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5111 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 5112 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5113 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5114 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5115
5116 buffer_info->time_stamp = jiffies;
5117 buffer_info->next_to_watch = i;
5118
5119 i++;
5120 if (i == tx_ring->count)
5121 i = 0;
5122 tx_ring->next_to_use = i;
5123
5124 return 1;
bc7f75fa
AK		 5125}
5126
55aa6985 5127static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5128{
55aa6985 5129 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5130 struct e1000_context_desc *context_desc;
5131 struct e1000_buffer *buffer_info;
5132 unsigned int i;
5133 u8 css;
af807c82 5134 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5135 __be16 protocol;
bc7f75fa 5136
af807c82
DG		 5137 if (skb->ip_summed != CHECKSUM_PARTIAL)
5138 return 0;
bc7f75fa 5139
5f66f208
AJ		 5140 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5141 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5142 else
5143 protocol = skb->protocol;
5144
3f518390 5145 switch (protocol) {
09640e63 5146 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5147 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5148 cmd_len |= E1000_TXD_CMD_TCP;
5149 break;
09640e63 5150 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5151 /* XXX not handling all IPV6 headers */
5152 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5153 cmd_len |= E1000_TXD_CMD_TCP;
5154 break;
5155 default:
5156 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5157 e_warn("checksum_partial proto=%x!\n",
5158 be16_to_cpu(protocol));
af807c82 5159 break;
bc7f75fa
AK		 5160 }
5161
0d0b1672 5162 css = skb_checksum_start_offset(skb);
af807c82
DG		 5163
5164 i = tx_ring->next_to_use;
5165 buffer_info = &tx_ring->buffer_info[i];
5166 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5167
5168 context_desc->lower_setup.ip_config = 0;
5169 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5170 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5171 context_desc->upper_setup.tcp_fields.tucse = 0;
5172 context_desc->tcp_seg_setup.data = 0;
5173 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5174
5175 buffer_info->time_stamp = jiffies;
5176 buffer_info->next_to_watch = i;
5177
5178 i++;
5179 if (i == tx_ring->count)
5180 i = 0;
5181 tx_ring->next_to_use = i;
5182
5183 return 1;
bc7f75fa
AK		 5184}
5185
55aa6985
BA		 5186static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5187 unsigned int first, unsigned int max_per_txd,
d821a4c4 5188 unsigned int nr_frags)
bc7f75fa 5189{
55aa6985 5190 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5191 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5192 struct e1000_buffer *buffer_info;
8ddc951c 5193 unsigned int len = skb_headlen(skb);
03b1320d 5194 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5195 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5196
5197 i = tx_ring->next_to_use;
5198
5199 while (len) {
1b7719c4 5200 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5201 size = min(len, max_per_txd);
5202
bc7f75fa 5203 buffer_info->length = size;
bc7f75fa 5204 buffer_info->time_stamp = jiffies;
bc7f75fa 5205 buffer_info->next_to_watch = i;
0be3f55f
NN		 5206 buffer_info->dma = dma_map_single(&pdev->dev,
5207 skb->data + offset,
af667a29 5208 size, DMA_TO_DEVICE);
03b1320d 5209 buffer_info->mapped_as_page = false;
0be3f55f 5210 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5211 goto dma_error;
bc7f75fa
AK		 5212
5213 len -= size;
5214 offset += size;
03b1320d 5215 count++;
1b7719c4
AD		 5216
5217 if (len) {
5218 i++;
5219 if (i == tx_ring->count)
5220 i = 0;
5221 }
bc7f75fa
AK		 5222 }
5223
5224 for (f = 0; f < nr_frags; f++) {
9e903e08 5225 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5226
5227 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5228 len = skb_frag_size(frag);
877749bf 5229 offset = 0;
bc7f75fa
AK		 5230
5231 while (len) {
1b7719c4
AD		 5232 i++;
5233 if (i == tx_ring->count)
5234 i = 0;
5235
bc7f75fa
AK		 5236 buffer_info = &tx_ring->buffer_info[i];
5237 size = min(len, max_per_txd);
bc7f75fa
AK		 5238
5239 buffer_info->length = size;
5240 buffer_info->time_stamp = jiffies;
bc7f75fa 5241 buffer_info->next_to_watch = i;
877749bf 5242 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5243 offset, size,
5244 DMA_TO_DEVICE);
03b1320d 5245 buffer_info->mapped_as_page = true;
0be3f55f 5246 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5247 goto dma_error;
bc7f75fa
AK		 5248
5249 len -= size;
5250 offset += size;
5251 count++;
bc7f75fa
AK		 5252 }
5253 }
5254
af667a29 5255 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5256 /* multiply data chunks by size of headers */
5257 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5258
bc7f75fa 5259 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5260 tx_ring->buffer_info[i].segs = segs;
5261 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5262 tx_ring->buffer_info[first].next_to_watch = i;
5263
5264 return count;
03b1320d
AD		 5265
5266dma_error:
af667a29 5267 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5268 buffer_info->dma = 0;
c1fa347f 5269 if (count)
03b1320d 5270 count--;
c1fa347f
RK		 5271
5272 while (count--) {
af667a29 5273 if (i == 0)
03b1320d 5274 i += tx_ring->count;
c1fa347f 5275 i--;
03b1320d 5276 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5277 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5278 }
5279
5280 return 0;
bc7f75fa
AK		 5281}
5282
55aa6985 5283static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5284{
55aa6985 5285 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5286 struct e1000_tx_desc *tx_desc = NULL;
5287 struct e1000_buffer *buffer_info;
5288 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5289 unsigned int i;
5290
5291 if (tx_flags & E1000_TX_FLAGS_TSO) {
5292 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5293 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5294 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5295
5296 if (tx_flags & E1000_TX_FLAGS_IPV4)
5297 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5298 }
5299
5300 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5301 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5302 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5303 }
5304
5305 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5306 txd_lower |= E1000_TXD_CMD_VLE;
5307 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5308 }
5309
943146de
BG		 5310 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5311 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5312
b67e1913
BA		 5313 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5314 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5315 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5316 }
5317
bc7f75fa
AK		 5318 i = tx_ring->next_to_use;
5319
36b973df 5320 do {
bc7f75fa
AK		 5321 buffer_info = &tx_ring->buffer_info[i];
5322 tx_desc = E1000_TX_DESC(*tx_ring, i);
5323 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5324 tx_desc->lower.data = cpu_to_le32(txd_lower |
5325 buffer_info->length);
bc7f75fa
AK		 5326 tx_desc->upper.data = cpu_to_le32(txd_upper);
5327
5328 i++;
5329 if (i == tx_ring->count)
5330 i = 0;
36b973df 5331 } while (--count > 0);
bc7f75fa
AK		 5332
5333 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5334
943146de
BG		 5335 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5336 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5337 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5338
e921eb1a 5339 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5340 * know there are new descriptors to fetch. (Only
5341 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5342 * such as IA-64).
5343 */
bc7f75fa
AK		 5344 wmb();
5345
5346 tx_ring->next_to_use = i;
c6e7f51e
BA		 5347
5348 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5349 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5350 else
c5083cf6 5351 writel(i, tx_ring->tail);
c6e7f51e 5352
e921eb1a 5353 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5354 * at a time, it synchronizes IO on IA64/Altix systems
5355 */
bc7f75fa
AK		 5356 mmiowb();
5357}
5358
5359#define MINIMUM_DHCP_PACKET_SIZE 282
5360static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5361 struct sk_buff *skb)
5362{
5363 struct e1000_hw *hw = &adapter->hw;
5364 u16 length, offset;
5365
d60923c4
BA		 5366 if (vlan_tx_tag_present(skb) &&
5367 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5368 (adapter->hw.mng_cookie.status &
5369 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5370 return 0;
bc7f75fa
AK		 5371
5372 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5373 return 0;
5374
53aa82da 5375 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5376 return 0;
5377
5378 {
362e20ca 5379 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5380 struct udphdr *udp;
5381
5382 if (ip->protocol != IPPROTO_UDP)
5383 return 0;
5384
5385 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5386 if (ntohs(udp->dest) != 67)
5387 return 0;
5388
5389 offset = (u8 *)udp + 8 - skb->data;
5390 length = skb->len - offset;
5391 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5392 }
5393
5394 return 0;
5395}
5396
55aa6985 5397static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5398{
55aa6985 5399 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5400
55aa6985 5401 netif_stop_queue(adapter->netdev);
e921eb1a 5402 /* Herbert's original patch had:
bc7f75fa 5403 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5404 * but since that doesn't exist yet, just open code it.
5405 */
bc7f75fa
AK		 5406 smp_mb();
5407
e921eb1a 5408 /* We need to check again in a case another CPU has just
ad68076e
BA		 5409 * made room available.
5410 */
55aa6985 5411 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5412 return -EBUSY;
5413
5414 /* A reprieve! */
55aa6985 5415 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5416 ++adapter->restart_queue;
5417 return 0;
5418}
5419
55aa6985 5420static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5421{
d821a4c4
BA		 5422 BUG_ON(size > tx_ring->count);
5423
55aa6985 5424 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5425 return 0;
55aa6985 5426 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5427}
5428
3b29a56d
SH		 5429static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5430 struct net_device *netdev)
bc7f75fa
AK		 5431{
5432 struct e1000_adapter *adapter = netdev_priv(netdev);
5433 struct e1000_ring *tx_ring = adapter->tx_ring;
5434 unsigned int first;
bc7f75fa 5435 unsigned int tx_flags = 0;
e743d313 5436 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5437 unsigned int nr_frags;
5438 unsigned int mss;
bc7f75fa
AK		 5439 int count = 0;
5440 int tso;
5441 unsigned int f;
bc7f75fa
AK		 5442
5443 if (test_bit(__E1000_DOWN, &adapter->state)) {
5444 dev_kfree_skb_any(skb);
5445 return NETDEV_TX_OK;
5446 }
5447
5448 if (skb->len <= 0) {
5449 dev_kfree_skb_any(skb);
5450 return NETDEV_TX_OK;
5451 }
5452
e921eb1a 5453 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5454 * pad skb in order to meet this minimum size requirement
5455 */
5456 if (unlikely(skb->len < 17)) {
5457 if (skb_pad(skb, 17 - skb->len))
5458 return NETDEV_TX_OK;
5459 skb->len = 17;
5460 skb_set_tail_pointer(skb, 17);
5461 }
5462
bc7f75fa 5463 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5464 if (mss) {
5465 u8 hdr_len;
bc7f75fa 5466
e921eb1a 5467 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5468 * points to just header, pull a few bytes of payload from
5469 * frags into skb->data
5470 */
bc7f75fa 5471 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5472 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5473 * avoiding it could save a lot of cycles
5474 */
4e6c709c 5475 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5476 unsigned int pull_size;
5477
a2a5b323 5478 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5479 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5480 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5481 dev_kfree_skb_any(skb);
5482 return NETDEV_TX_OK;
5483 }
e743d313 5484 len = skb_headlen(skb);
bc7f75fa
AK		 5485 }
5486 }
5487
5488 /* reserve a descriptor for the offload context */
5489 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5490 count++;
5491 count++;
5492
d821a4c4 5493 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5494
5495 nr_frags = skb_shinfo(skb)->nr_frags;
5496 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5497 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5498 adapter->tx_fifo_limit);
bc7f75fa
AK		 5499
5500 if (adapter->hw.mac.tx_pkt_filtering)
5501 e1000_transfer_dhcp_info(adapter, skb);
5502
e921eb1a 5503 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5504 * head, otherwise try next time
5505 */
55aa6985 5506 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5507 return NETDEV_TX_BUSY;
bc7f75fa 5508
eab6d18d 5509 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5510 tx_flags |= E1000_TX_FLAGS_VLAN;
5511 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5512 }
5513
5514 first = tx_ring->next_to_use;
5515
55aa6985 5516 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5517 if (tso < 0) {
5518 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5519 return NETDEV_TX_OK;
5520 }
5521
5522 if (tso)
5523 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5524 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5525 tx_flags |= E1000_TX_FLAGS_CSUM;
5526
e921eb1a 5527 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5528 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5529 * no longer assume, we must.
5530 */
bc7f75fa
AK		 5531 if (skb->protocol == htons(ETH_P_IP))
5532 tx_flags |= E1000_TX_FLAGS_IPV4;
5533
943146de
BG		 5534 if (unlikely(skb->no_fcs))
5535 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5536
25985edc 5537 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5538 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5539 nr_frags);
1b7719c4 5540 if (count) {
b67e1913
BA		 5541 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5542 !adapter->tx_hwtstamp_skb)) {
5543 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5544 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5545 adapter->tx_hwtstamp_skb = skb_get(skb);
5546 schedule_work(&adapter->tx_hwtstamp_work);
5547 } else {
5548 skb_tx_timestamp(skb);
5549 }
80be3129 5550
3f0cfa3b 5551 netdev_sent_queue(netdev, skb->len);
55aa6985 5552 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5553 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5554 e1000_maybe_stop_tx(tx_ring,
5555 (MAX_SKB_FRAGS *
5556 DIV_ROUND_UP(PAGE_SIZE,
5557 adapter->tx_fifo_limit) + 2));
1b7719c4 5558 } else {
bc7f75fa 5559 dev_kfree_skb_any(skb);
1b7719c4
AD		 5560 tx_ring->buffer_info[first].time_stamp = 0;
5561 tx_ring->next_to_use = first;
bc7f75fa
AK		 5562 }
5563
bc7f75fa
AK		 5564 return NETDEV_TX_OK;
5565}
5566
5567/**
5568 * e1000_tx_timeout - Respond to a Tx Hang
5569 * @netdev: network interface device structure
5570 **/
5571static void e1000_tx_timeout(struct net_device *netdev)
5572{
5573 struct e1000_adapter *adapter = netdev_priv(netdev);
5574
5575 /* Do the reset outside of interrupt context */
5576 adapter->tx_timeout_count++;
5577 schedule_work(&adapter->reset_task);
5578}
5579
5580static void e1000_reset_task(struct work_struct *work)
5581{
5582 struct e1000_adapter *adapter;
5583 adapter = container_of(work, struct e1000_adapter, reset_task);
5584
615b32af
JB		 5585 /* don't run the task if already down */
5586 if (test_bit(__E1000_DOWN, &adapter->state))
5587 return;
5588
12d43f7d 5589 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5590 e1000e_dump(adapter);
12d43f7d 5591 e_err("Reset adapter unexpectedly\n");
affa9dfb 5592 }
bc7f75fa
AK		 5593 e1000e_reinit_locked(adapter);
5594}
5595
5596/**
67fd4fcb 5597 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5598 * @netdev: network interface device structure
67fd4fcb 5599 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5600 *
5601 * Returns the address of the device statistics structure.
bc7f75fa 5602 **/
67fd4fcb 5603struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5604 struct rtnl_link_stats64 *stats)
bc7f75fa 5605{
67fd4fcb
JK		 5606 struct e1000_adapter *adapter = netdev_priv(netdev);
5607
5608 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5609 spin_lock(&adapter->stats64_lock);
5610 e1000e_update_stats(adapter);
5611 /* Fill out the OS statistics structure */
5612 stats->rx_bytes = adapter->stats.gorc;
5613 stats->rx_packets = adapter->stats.gprc;
5614 stats->tx_bytes = adapter->stats.gotc;
5615 stats->tx_packets = adapter->stats.gptc;
5616 stats->multicast = adapter->stats.mprc;
5617 stats->collisions = adapter->stats.colc;
5618
5619 /* Rx Errors */
5620
e921eb1a 5621 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5622 * our own version based on RUC and ROC
5623 */
5624 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5625 adapter->stats.crcerrs + adapter->stats.algnerrc +
5626 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5627 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5628 stats->rx_crc_errors = adapter->stats.crcerrs;
5629 stats->rx_frame_errors = adapter->stats.algnerrc;
5630 stats->rx_missed_errors = adapter->stats.mpc;
5631
5632 /* Tx Errors */
f0ff4398 5633 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5634 stats->tx_aborted_errors = adapter->stats.ecol;
5635 stats->tx_window_errors = adapter->stats.latecol;
5636 stats->tx_carrier_errors = adapter->stats.tncrs;
5637
5638 /* Tx Dropped needs to be maintained elsewhere */
5639
5640 spin_unlock(&adapter->stats64_lock);
5641 return stats;
bc7f75fa
AK		 5642}
5643
5644/**
5645 * e1000_change_mtu - Change the Maximum Transfer Unit
5646 * @netdev: network interface device structure
5647 * @new_mtu: new value for maximum frame size
5648 *
5649 * Returns 0 on success, negative on failure
5650 **/
5651static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5652{
5653 struct e1000_adapter *adapter = netdev_priv(netdev);
5654 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5655
2adc55c9 5656 /* Jumbo frame support */
2e1706f2
BA		 5657 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5658 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5659 e_err("Jumbo Frames not supported.\n");
5660 return -EINVAL;
bc7f75fa
AK		 5661 }
5662
2adc55c9
BA		 5663 /* Supported frame sizes */
5664 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5665 (max_frame > adapter->max_hw_frame_size)) {
5666 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5667 return -EINVAL;
5668 }
5669
2fbe4526
BA		 5670 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5671 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5672 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5673 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5674 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5675 return -EINVAL;
5676 }
5677
bc7f75fa 5678 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5679 usleep_range(1000, 2000);
610c9928 5680 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5681 adapter->max_frame_size = max_frame;
610c9928
BA		 5682 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5683 netdev->mtu = new_mtu;
bc7f75fa
AK		 5684 if (netif_running(netdev))
5685 e1000e_down(adapter);
5686
e921eb1a 5687 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5688 * means we reserve 2 more, this pushes us to allocate from the next
5689 * larger slab size.
ad68076e 5690 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5691 * However with the new *_jumbo_rx* routines, jumbo receives will use
5692 * fragmented skbs
ad68076e 5693 */
bc7f75fa 5694
9926146b 5695 if (max_frame <= 2048)
bc7f75fa
AK		 5696 adapter->rx_buffer_len = 2048;
5697 else
5698 adapter->rx_buffer_len = 4096;
5699
5700 /* adjust allocation if LPE protects us, and we aren't using SBP */
5701 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5702 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5703 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5704 + ETH_FCS_LEN;
bc7f75fa 5705
bc7f75fa
AK		 5706 if (netif_running(netdev))
5707 e1000e_up(adapter);
5708 else
5709 e1000e_reset(adapter);
5710
5711 clear_bit(__E1000_RESETTING, &adapter->state);
5712
5713 return 0;
5714}
5715
5716static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5717 int cmd)
5718{
5719 struct e1000_adapter *adapter = netdev_priv(netdev);
5720 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5721
318a94d6 5722 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5723 return -EOPNOTSUPP;
5724
5725 switch (cmd) {
5726 case SIOCGMIIPHY:
5727 data->phy_id = adapter->hw.phy.addr;
5728 break;
5729 case SIOCGMIIREG:
b16a002e
BA		 5730 e1000_phy_read_status(adapter);
5731
7c25769f
BA		 5732 switch (data->reg_num & 0x1F) {
5733 case MII_BMCR:
5734 data->val_out = adapter->phy_regs.bmcr;
5735 break;
5736 case MII_BMSR:
5737 data->val_out = adapter->phy_regs.bmsr;
5738 break;
5739 case MII_PHYSID1:
5740 data->val_out = (adapter->hw.phy.id >> 16);
5741 break;
5742 case MII_PHYSID2:
5743 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5744 break;
5745 case MII_ADVERTISE:
5746 data->val_out = adapter->phy_regs.advertise;
5747 break;
5748 case MII_LPA:
5749 data->val_out = adapter->phy_regs.lpa;
5750 break;
5751 case MII_EXPANSION:
5752 data->val_out = adapter->phy_regs.expansion;
5753 break;
5754 case MII_CTRL1000:
5755 data->val_out = adapter->phy_regs.ctrl1000;
5756 break;
5757 case MII_STAT1000:
5758 data->val_out = adapter->phy_regs.stat1000;
5759 break;
5760 case MII_ESTATUS:
5761 data->val_out = adapter->phy_regs.estatus;
5762 break;
5763 default:
bc7f75fa
AK		 5764 return -EIO;
5765 }
bc7f75fa
AK		 5766 break;
5767 case SIOCSMIIREG:
5768 default:
5769 return -EOPNOTSUPP;
5770 }
5771 return 0;
5772}
5773
b67e1913
BA		 5774/**
5775 * e1000e_hwtstamp_ioctl - control hardware time stamping
5776 * @netdev: network interface device structure
5777 * @ifreq: interface request
5778 *
5779 * Outgoing time stamping can be enabled and disabled. Play nice and
5780 * disable it when requested, although it shouldn't cause any overhead
5781 * when no packet needs it. At most one packet in the queue may be
5782 * marked for time stamping, otherwise it would be impossible to tell
5783 * for sure to which packet the hardware time stamp belongs.
5784 *
5785 * Incoming time stamping has to be configured via the hardware filters.
5786 * Not all combinations are supported, in particular event type has to be
5787 * specified. Matching the kind of event packet is not supported, with the
5788 * exception of "all V2 events regardless of level 2 or 4".
5789 **/
5790static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5791{
5792 struct e1000_adapter *adapter = netdev_priv(netdev);
5793 struct hwtstamp_config config;
5794 int ret_val;
5795
5796 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5797 return -EFAULT;
5798
5799 adapter->hwtstamp_config = config;
5800
5801 ret_val = e1000e_config_hwtstamp(adapter);
5802 if (ret_val)
5803 return ret_val;
5804
5805 config = adapter->hwtstamp_config;
5806
d89777bf
BA		 5807 switch (config.rx_filter) {
5808 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5809 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5810 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5811 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5812 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5813 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5814 /* With V2 type filters which specify a Sync or Delay Request,
5815 * Path Delay Request/Response messages are also time stamped
5816 * by hardware so notify the caller the requested packets plus
5817 * some others are time stamped.
5818 */
5819 config.rx_filter = HWTSTAMP_FILTER_SOME;
5820 break;
5821 default:
5822 break;
5823 }
5824
b67e1913
BA		 5825 return copy_to_user(ifr->ifr_data, &config,
5826 sizeof(config)) ? -EFAULT : 0;
5827}
5828
bc7f75fa
AK		 5829static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5830{
5831 switch (cmd) {
5832 case SIOCGMIIPHY:
5833 case SIOCGMIIREG:
5834 case SIOCSMIIREG:
5835 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913
BA		 5836 case SIOCSHWTSTAMP:
5837 return e1000e_hwtstamp_ioctl(netdev, ifr);
bc7f75fa
AK		 5838 default:
5839 return -EOPNOTSUPP;
5840 }
5841}
5842
a4f58f54
BA		 5843static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5844{
5845 struct e1000_hw *hw = &adapter->hw;
5846 u32 i, mac_reg;
2b6b168d 5847 u16 phy_reg, wuc_enable;
70806a7f 5848 int retval;
a4f58f54
BA		 5849
5850 /* copy MAC RARs to PHY RARs */
d3738bb8 5851 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5852
2b6b168d
BA		 5853 retval = hw->phy.ops.acquire(hw);
5854 if (retval) {
5855 e_err("Could not acquire PHY\n");
5856 return retval;
5857 }
5858
5859 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5860 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5861 if (retval)
75ce1532 5862 goto release;
2b6b168d
BA		 5863
5864 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5865 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5866 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5867 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5868 (u16)(mac_reg & 0xFFFF));
5869 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5870 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5871 }
5872
5873 /* configure PHY Rx Control register */
2b6b168d 5874 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5875 mac_reg = er32(RCTL);
5876 if (mac_reg & E1000_RCTL_UPE)
5877 phy_reg |= BM_RCTL_UPE;
5878 if (mac_reg & E1000_RCTL_MPE)
5879 phy_reg |= BM_RCTL_MPE;
5880 phy_reg &= ~(BM_RCTL_MO_MASK);
5881 if (mac_reg & E1000_RCTL_MO_3)
5882 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5883 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5884 if (mac_reg & E1000_RCTL_BAM)
5885 phy_reg |= BM_RCTL_BAM;
5886 if (mac_reg & E1000_RCTL_PMCF)
5887 phy_reg |= BM_RCTL_PMCF;
5888 mac_reg = er32(CTRL);
5889 if (mac_reg & E1000_CTRL_RFCE)
5890 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5891 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5892
5893 /* enable PHY wakeup in MAC register */
5894 ew32(WUFC, wufc);
5895 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5896
5897 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5898 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5899 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5900
5901 /* activate PHY wakeup */
2b6b168d
BA		 5902 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5903 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5904 if (retval)
5905 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5906release:
94d8186a 5907 hw->phy.ops.release(hw);
a4f58f54
BA		 5908
5909 return retval;
5910}
5911
66148bab 5912static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
bc7f75fa
AK		 5913{
5914 struct net_device *netdev = pci_get_drvdata(pdev);
5915 struct e1000_adapter *adapter = netdev_priv(netdev);
5916 struct e1000_hw *hw = &adapter->hw;
5917 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5918 /* Runtime suspend should only enable wakeup for link changes */
5919 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5920 int retval = 0;
5921
5922 netif_device_detach(netdev);
5923
5924 if (netif_running(netdev)) {
bb9e44d0
BA		 5925 int count = E1000_CHECK_RESET_COUNT;
5926
5927 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5928 usleep_range(10000, 20000);
5929
bc7f75fa
AK		 5930 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5931 e1000e_down(adapter);
5932 e1000_free_irq(adapter);
5933 }
4662e82b 5934 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 5935
bc7f75fa
AK		 5936 status = er32(STATUS);
5937 if (status & E1000_STATUS_LU)
5938 wufc &= ~E1000_WUFC_LNKC;
5939
5940 if (wufc) {
5941 e1000_setup_rctl(adapter);
ef9b965a 5942 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5943
5944 /* turn on all-multi mode if wake on multicast is enabled */
5945 if (wufc & E1000_WUFC_MC) {
5946 rctl = er32(RCTL);
5947 rctl |= E1000_RCTL_MPE;
5948 ew32(RCTL, rctl);
5949 }
5950
5951 ctrl = er32(CTRL);
a4f58f54
BA		 5952 ctrl |= E1000_CTRL_ADVD3WUC;
5953 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5954 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5955 ew32(CTRL, ctrl);
5956
318a94d6
JK		 5957 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5958 adapter->hw.phy.media_type ==
5959 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5960 /* keep the laser running in D3 */
5961 ctrl_ext = er32(CTRL_EXT);
93a23f48 5962 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5963 ew32(CTRL_EXT, ctrl_ext);
5964 }
5965
97ac8cae 5966 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5967 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5968
bc7f75fa
AK		 5969 /* Allow time for pending master requests to run */
5970 e1000e_disable_pcie_master(&adapter->hw);
5971
82776a4b 5972 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5973 /* enable wakeup by the PHY */
5974 retval = e1000_init_phy_wakeup(adapter, wufc);
5975 if (retval)
5976 return retval;
5977 } else {
5978 /* enable wakeup by the MAC */
5979 ew32(WUFC, wufc);
5980 ew32(WUC, E1000_WUC_PME_EN);
5981 }
bc7f75fa
AK		 5982 } else {
5983 ew32(WUC, 0);
5984 ew32(WUFC, 0);
bc7f75fa
AK		 5985 }
5986
bc7f75fa
AK		 5987 if (adapter->hw.phy.type == e1000_phy_igp_3)
5988 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5989
e921eb1a 5990 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5991 * would have already happened in close and is redundant.
5992 */
31dbe5b4 5993 e1000e_release_hw_control(adapter);
bc7f75fa 5994
e921eb1a 5995 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 5996 * correctable error when the MAC transitions from D0 to D3. To
5997 * prevent this we need to mask off the correctable errors on the
5998 * downstream port of the pci-e switch.
5999 */
6000 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6001 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6002 u16 devctl;
6003
f8c0fcac
JL		 6004 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6005 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6006 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6007
66148bab
KK		 6008 pci_save_state(pdev);
6009 pci_prepare_to_sleep(pdev);
005cbdfc 6010
f8c0fcac 6011 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6012 }
66148bab
KK		 6013
6014 return 0;
bc7f75fa
AK		 6015}
6016
6f461f6c
BA		 6017#ifdef CONFIG_PCIEASPM
6018static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6019{
9f728f53 6020 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 6021}
6022#else
6023static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 6024{
ffe0b2ff
BH		 6025 u16 aspm_ctl = 0;
6026
6027 if (state & PCIE_LINK_STATE_L0S)
6028 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
6029 if (state & PCIE_LINK_STATE_L1)
6030 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
6031
e921eb1a 6032 /* Both device and parent should have the same ASPM setting.
6f461f6c 6033 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6034 */
ffe0b2ff 6035 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
0c75ba22 6036
f8c0fcac
JL		 6037 if (pdev->bus->self)
6038 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
ffe0b2ff 6039 aspm_ctl);
6f461f6c
BA		 6040}
6041#endif
78cd29d5 6042static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 6043{
6044 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6045 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
6046 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
6047
6048 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 6049}
6050
aa338601 6051#ifdef CONFIG_PM
23606cf5 6052static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 6053{
23606cf5 6054 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 6055}
6056
23606cf5 6057static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6058{
6059 struct net_device *netdev = pci_get_drvdata(pdev);
6060 struct e1000_adapter *adapter = netdev_priv(netdev);
6061 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6062 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6063 u32 err;
6064
78cd29d5
BA		 6065 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6066 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6067 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6068 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6069 if (aspm_disable_flag)
6070 e1000e_disable_aspm(pdev, aspm_disable_flag);
6071
66148bab 6072 pci_set_master(pdev);
6e4f6f6b 6073
4662e82b 6074 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 6075 if (netif_running(netdev)) {
6076 err = e1000_request_irq(adapter);
6077 if (err)
6078 return err;
6079 }
6080
2fbe4526 6081 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6082 e1000_resume_workarounds_pchlan(&adapter->hw);
6083
bc7f75fa 6084 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6085
6086 /* report the system wakeup cause from S3/S4 */
6087 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6088 u16 phy_data;
6089
6090 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6091 if (phy_data) {
6092 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6093 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6094 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6095 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6096 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6097 phy_data & E1000_WUS_LNKC ?
6098 "Link Status Change" : "other");
a4f58f54
BA		 6099 }
6100 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6101 } else {
6102 u32 wus = er32(WUS);
6103 if (wus) {
6104 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6105 wus & E1000_WUS_EX ? "Unicast Packet" :
6106 wus & E1000_WUS_MC ? "Multicast Packet" :
6107 wus & E1000_WUS_BC ? "Broadcast Packet" :
6108 wus & E1000_WUS_MAG ? "Magic Packet" :
6109 wus & E1000_WUS_LNKC ? "Link Status Change" :
6110 "other");
a4f58f54
BA		 6111 }
6112 ew32(WUS, ~0);
6113 }
6114
bc7f75fa 6115 e1000e_reset(adapter);
bc7f75fa 6116
cd791618 6117 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6118
6119 if (netif_running(netdev))
6120 e1000e_up(adapter);
6121
6122 netif_device_attach(netdev);
6123
e921eb1a 6124 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6125 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6126 * under the control of the driver.
6127 */
c43bc57e 6128 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6129 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6130
6131 return 0;
6132}
23606cf5 6133
a0340162
RW		 6134#ifdef CONFIG_PM_SLEEP
6135static int e1000_suspend(struct device *dev)
6136{
6137 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6138
66148bab 6139 return __e1000_shutdown(pdev, false);
a0340162
RW		 6140}
6141
23606cf5
RW		 6142static int e1000_resume(struct device *dev)
6143{
6144 struct pci_dev *pdev = to_pci_dev(dev);
6145 struct net_device *netdev = pci_get_drvdata(pdev);
6146 struct e1000_adapter *adapter = netdev_priv(netdev);
6147
6148 if (e1000e_pm_ready(adapter))
6149 adapter->idle_check = true;
6150
6151 return __e1000_resume(pdev);
6152}
a0340162
RW		 6153#endif /* CONFIG_PM_SLEEP */
6154
6155#ifdef CONFIG_PM_RUNTIME
6156static int e1000_runtime_suspend(struct device *dev)
6157{
6158 struct pci_dev *pdev = to_pci_dev(dev);
6159 struct net_device *netdev = pci_get_drvdata(pdev);
6160 struct e1000_adapter *adapter = netdev_priv(netdev);
6161
66148bab
KK		 6162 if (!e1000e_pm_ready(adapter))
6163 return 0;
a0340162 6164
66148bab 6165 return __e1000_shutdown(pdev, true);
a0340162
RW		 6166}
6167
6168static int e1000_idle(struct device *dev)
6169{
6170 struct pci_dev *pdev = to_pci_dev(dev);
6171 struct net_device *netdev = pci_get_drvdata(pdev);
6172 struct e1000_adapter *adapter = netdev_priv(netdev);
6173
6174 if (!e1000e_pm_ready(adapter))
6175 return 0;
6176
6177 if (adapter->idle_check) {
6178 adapter->idle_check = false;
6179 if (!e1000e_has_link(adapter))
6180 pm_schedule_suspend(dev, MSEC_PER_SEC);
6181 }
6182
6183 return -EBUSY;
6184}
23606cf5
RW		 6185
6186static int e1000_runtime_resume(struct device *dev)
6187{
6188 struct pci_dev *pdev = to_pci_dev(dev);
6189 struct net_device *netdev = pci_get_drvdata(pdev);
6190 struct e1000_adapter *adapter = netdev_priv(netdev);
6191
6192 if (!e1000e_pm_ready(adapter))
6193 return 0;
6194
6195 adapter->idle_check = !dev->power.runtime_auto;
6196 return __e1000_resume(pdev);
6197}
a0340162 6198#endif /* CONFIG_PM_RUNTIME */
aa338601 6199#endif /* CONFIG_PM */
bc7f75fa
AK		 6200
6201static void e1000_shutdown(struct pci_dev *pdev)
6202{
66148bab 6203 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6204}
6205
6206#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6207
8bb62869 6208static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6209{
6210 struct net_device *netdev = data;
6211 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6212
6213 if (adapter->msix_entries) {
90da0669
BA		 6214 int vector, msix_irq;
6215
147b2c8c
DD		 6216 vector = 0;
6217 msix_irq = adapter->msix_entries[vector].vector;
6218 disable_irq(msix_irq);
6219 e1000_intr_msix_rx(msix_irq, netdev);
6220 enable_irq(msix_irq);
6221
6222 vector++;
6223 msix_irq = adapter->msix_entries[vector].vector;
6224 disable_irq(msix_irq);
6225 e1000_intr_msix_tx(msix_irq, netdev);
6226 enable_irq(msix_irq);
6227
6228 vector++;
6229 msix_irq = adapter->msix_entries[vector].vector;
6230 disable_irq(msix_irq);
6231 e1000_msix_other(msix_irq, netdev);
6232 enable_irq(msix_irq);
6233 }
6234
6235 return IRQ_HANDLED;
6236}
6237
e921eb1a
BA		 6238/**
6239 * e1000_netpoll
6240 * @netdev: network interface device structure
6241 *
bc7f75fa
AK		 6242 * Polling 'interrupt' - used by things like netconsole to send skbs
6243 * without having to re-enable interrupts. It's not called while
6244 * the interrupt routine is executing.
6245 */
6246static void e1000_netpoll(struct net_device *netdev)
6247{
6248 struct e1000_adapter *adapter = netdev_priv(netdev);
6249
147b2c8c
DD		 6250 switch (adapter->int_mode) {
6251 case E1000E_INT_MODE_MSIX:
6252 e1000_intr_msix(adapter->pdev->irq, netdev);
6253 break;
6254 case E1000E_INT_MODE_MSI:
6255 disable_irq(adapter->pdev->irq);
6256 e1000_intr_msi(adapter->pdev->irq, netdev);
6257 enable_irq(adapter->pdev->irq);
6258 break;
6259 default: /* E1000E_INT_MODE_LEGACY */
6260 disable_irq(adapter->pdev->irq);
6261 e1000_intr(adapter->pdev->irq, netdev);
6262 enable_irq(adapter->pdev->irq);
6263 break;
6264 }
bc7f75fa
AK		 6265}
6266#endif
6267
6268/**
6269 * e1000_io_error_detected - called when PCI error is detected
6270 * @pdev: Pointer to PCI device
6271 * @state: The current pci connection state
6272 *
6273 * This function is called after a PCI bus error affecting
6274 * this device has been detected.
6275 */
6276static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6277 pci_channel_state_t state)
6278{
6279 struct net_device *netdev = pci_get_drvdata(pdev);
6280 struct e1000_adapter *adapter = netdev_priv(netdev);
6281
6282 netif_device_detach(netdev);
6283
c93b5a76
MM		 6284 if (state == pci_channel_io_perm_failure)
6285 return PCI_ERS_RESULT_DISCONNECT;
6286
bc7f75fa
AK		 6287 if (netif_running(netdev))
6288 e1000e_down(adapter);
6289 pci_disable_device(pdev);
6290
6291 /* Request a slot slot reset. */
6292 return PCI_ERS_RESULT_NEED_RESET;
6293}
6294
6295/**
6296 * e1000_io_slot_reset - called after the pci bus has been reset.
6297 * @pdev: Pointer to PCI device
6298 *
6299 * Restart the card from scratch, as if from a cold-boot. Implementation
6300 * resembles the first-half of the e1000_resume routine.
6301 */
6302static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6303{
6304 struct net_device *netdev = pci_get_drvdata(pdev);
6305 struct e1000_adapter *adapter = netdev_priv(netdev);
6306 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6307 u16 aspm_disable_flag = 0;
6e4f6f6b 6308 int err;
111b9dc5 6309 pci_ers_result_t result;
bc7f75fa 6310
78cd29d5
BA		 6311 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6312 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6313 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6314 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6315 if (aspm_disable_flag)
6316 e1000e_disable_aspm(pdev, aspm_disable_flag);
6317
f0f422e5 6318 err = pci_enable_device_mem(pdev);
6e4f6f6b 6319 if (err) {
bc7f75fa
AK		 6320 dev_err(&pdev->dev,
6321 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6322 result = PCI_ERS_RESULT_DISCONNECT;
6323 } else {
23606cf5 6324 pdev->state_saved = true;
111b9dc5 6325 pci_restore_state(pdev);
66148bab 6326 pci_set_master(pdev);
bc7f75fa 6327
111b9dc5
JB		 6328 pci_enable_wake(pdev, PCI_D3hot, 0);
6329 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6330
111b9dc5
JB		 6331 e1000e_reset(adapter);
6332 ew32(WUS, ~0);
6333 result = PCI_ERS_RESULT_RECOVERED;
6334 }
bc7f75fa 6335
111b9dc5
JB		 6336 pci_cleanup_aer_uncorrect_error_status(pdev);
6337
6338 return result;
bc7f75fa
AK		 6339}
6340
6341/**
6342 * e1000_io_resume - called when traffic can start flowing again.
6343 * @pdev: Pointer to PCI device
6344 *
6345 * This callback is called when the error recovery driver tells us that
6346 * its OK to resume normal operation. Implementation resembles the
6347 * second-half of the e1000_resume routine.
6348 */
6349static void e1000_io_resume(struct pci_dev *pdev)
6350{
6351 struct net_device *netdev = pci_get_drvdata(pdev);
6352 struct e1000_adapter *adapter = netdev_priv(netdev);
6353
cd791618 6354 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6355
6356 if (netif_running(netdev)) {
6357 if (e1000e_up(adapter)) {
6358 dev_err(&pdev->dev,
6359 "can't bring device back up after reset\n");
6360 return;
6361 }
6362 }
6363
6364 netif_device_attach(netdev);
6365
e921eb1a 6366 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6367 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6368 * under the control of the driver.
6369 */
c43bc57e 6370 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6371 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6372}
6373
6374static void e1000_print_device_info(struct e1000_adapter *adapter)
6375{
6376 struct e1000_hw *hw = &adapter->hw;
6377 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6378 u32 ret_val;
6379 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6380
6381 /* print bus type/speed/width info */
a5cc7642 6382 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6383 /* bus width */
6384 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6385 "Width x1"),
44defeb3 6386 /* MAC address */
7c510e4b 6387 netdev->dev_addr);
44defeb3
JK		 6388 e_info("Intel(R) PRO/%s Network Connection\n",
6389 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6390 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6391 E1000_PBANUM_LENGTH);
6392 if (ret_val)
f2315bf1 6393 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6394 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6395 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6396}
6397
10aa4c04
AK		 6398static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6399{
6400 struct e1000_hw *hw = &adapter->hw;
6401 int ret_val;
6402 u16 buf = 0;
6403
6404 if (hw->mac.type != e1000_82573)
6405 return;
6406
6407 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6408 le16_to_cpus(&buf);
6409 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6410 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6411 dev_warn(&adapter->pdev->dev,
6412 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6413 }
10aa4c04
AK		 6414}
6415
c8f44aff 6416static int e1000_set_features(struct net_device *netdev,
70495a50 6417 netdev_features_t features)
dc221294
BA		 6418{
6419 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6420 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6421
6422 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6423 adapter->flags |= FLAG_TSO_FORCE;
6424
f646968f 6425 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6426 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6427 NETIF_F_RXALL)))
dc221294
BA		 6428 return 0;
6429
0184039a
BG		 6430 if (changed & NETIF_F_RXFCS) {
6431 if (features & NETIF_F_RXFCS) {
6432 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6433 } else {
6434 /* We need to take it back to defaults, which might mean
6435 * stripping is still disabled at the adapter level.
6436 */
6437 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6438 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6439 else
6440 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6441 }
6442 }
6443
70495a50
BA		 6444 netdev->features = features;
6445
dc221294
BA		 6446 if (netif_running(netdev))
6447 e1000e_reinit_locked(adapter);
6448 else
6449 e1000e_reset(adapter);
6450
6451 return 0;
6452}
6453
651c2466
SH		 6454static const struct net_device_ops e1000e_netdev_ops = {
6455 .ndo_open = e1000_open,
6456 .ndo_stop = e1000_close,
00829823 6457 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6458 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6459 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6460 .ndo_set_mac_address = e1000_set_mac,
6461 .ndo_change_mtu = e1000_change_mtu,
6462 .ndo_do_ioctl = e1000_ioctl,
6463 .ndo_tx_timeout = e1000_tx_timeout,
6464 .ndo_validate_addr = eth_validate_addr,
6465
651c2466
SH		 6466 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6467 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6468#ifdef CONFIG_NET_POLL_CONTROLLER
6469 .ndo_poll_controller = e1000_netpoll,
6470#endif
dc221294 6471 .ndo_set_features = e1000_set_features,
651c2466
SH		 6472};
6473
bc7f75fa
AK		 6474/**
6475 * e1000_probe - Device Initialization Routine
6476 * @pdev: PCI device information struct
6477 * @ent: entry in e1000_pci_tbl
6478 *
6479 * Returns 0 on success, negative on failure
6480 *
6481 * e1000_probe initializes an adapter identified by a pci_dev structure.
6482 * The OS initialization, configuring of the adapter private structure,
6483 * and a hardware reset occur.
6484 **/
1dd06ae8 6485static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6486{
6487 struct net_device *netdev;
6488 struct e1000_adapter *adapter;
6489 struct e1000_hw *hw;
6490 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6491 resource_size_t mmio_start, mmio_len;
6492 resource_size_t flash_start, flash_len;
bc7f75fa 6493 static int cards_found;
78cd29d5 6494 u16 aspm_disable_flag = 0;
17e813ec 6495 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6496 u16 eeprom_data = 0;
6497 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6498
78cd29d5
BA		 6499 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6500 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6501 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6502 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6503 if (aspm_disable_flag)
6504 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6505
f0f422e5 6506 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6507 if (err)
6508 return err;
6509
6510 pci_using_dac = 0;
0be3f55f 6511 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6512 if (!err) {
0be3f55f 6513 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6514 if (!err)
6515 pci_using_dac = 1;
6516 } else {
0be3f55f 6517 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6518 if (err) {
0be3f55f
NN		 6519 err = dma_set_coherent_mask(&pdev->dev,
6520 DMA_BIT_MASK(32));
bc7f75fa 6521 if (err) {
f0ff4398
BA		 6522 dev_err(&pdev->dev,
6523 "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6524 goto err_dma;
6525 }
6526 }
6527 }
6528
17e813ec
BA		 6529 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6530 err = pci_request_selected_regions_exclusive(pdev, bars,
6531 e1000e_driver_name);
bc7f75fa
AK		 6532 if (err)
6533 goto err_pci_reg;
6534
68eac460 6535 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6536 pci_enable_pcie_error_reporting(pdev);
68eac460 6537
bc7f75fa 6538 pci_set_master(pdev);
438b365a
BA		 6539 /* PCI config space info */
6540 err = pci_save_state(pdev);
6541 if (err)
6542 goto err_alloc_etherdev;
bc7f75fa
AK		 6543
6544 err = -ENOMEM;
6545 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6546 if (!netdev)
6547 goto err_alloc_etherdev;
6548
bc7f75fa
AK		 6549 SET_NETDEV_DEV(netdev, &pdev->dev);
6550
f85e4dfa
TH		 6551 netdev->irq = pdev->irq;
6552
bc7f75fa
AK		 6553 pci_set_drvdata(pdev, netdev);
6554 adapter = netdev_priv(netdev);
6555 hw = &adapter->hw;
6556 adapter->netdev = netdev;
6557 adapter->pdev = pdev;
6558 adapter->ei = ei;
6559 adapter->pba = ei->pba;
6560 adapter->flags = ei->flags;
eb7c3adb 6561 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6562 adapter->hw.adapter = adapter;
6563 adapter->hw.mac.type = ei->mac;
2adc55c9 6564 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6565 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6566
6567 mmio_start = pci_resource_start(pdev, 0);
6568 mmio_len = pci_resource_len(pdev, 0);
6569
6570 err = -EIO;
6571 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6572 if (!adapter->hw.hw_addr)
6573 goto err_ioremap;
6574
6575 if ((adapter->flags & FLAG_HAS_FLASH) &&
6576 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6577 flash_start = pci_resource_start(pdev, 1);
6578 flash_len = pci_resource_len(pdev, 1);
6579 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6580 if (!adapter->hw.flash_address)
6581 goto err_flashmap;
6582 }
6583
d495bcb8
BA		 6584 /* Set default EEE advertisement */
6585 if (adapter->flags2 & FLAG2_HAS_EEE)
6586 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6587
bc7f75fa 6588 /* construct the net_device struct */
651c2466 6589 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6590 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6591 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6592 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6593 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6594
6595 netdev->mem_start = mmio_start;
6596 netdev->mem_end = mmio_start + mmio_len;
6597
6598 adapter->bd_number = cards_found++;
6599
4662e82b
BA		 6600 e1000e_check_options(adapter);
6601
bc7f75fa
AK		 6602 /* setup adapter struct */
6603 err = e1000_sw_init(adapter);
6604 if (err)
6605 goto err_sw_init;
6606
bc7f75fa
AK		 6607 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6608 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6609 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6610
69e3fd8c 6611 err = ei->get_variants(adapter);
bc7f75fa
AK		 6612 if (err)
6613 goto err_hw_init;
6614
4a770358
BA		 6615 if ((adapter->flags & FLAG_IS_ICH) &&
6616 (adapter->flags & FLAG_READ_ONLY_NVM))
6617 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6618
bc7f75fa
AK		 6619 hw->mac.ops.get_bus_info(&adapter->hw);
6620
318a94d6 6621 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6622
6623 /* Copper options */
318a94d6 6624 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6625 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6626 adapter->hw.phy.disable_polarity_correction = 0;
6627 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6628 }
6629
470a5420 6630 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6631 dev_info(&pdev->dev,
6632 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6633
dc221294
BA		 6634 /* Set initial default active device features */
6635 netdev->features = (NETIF_F_SG |
f646968f
PM		 6636 NETIF_F_HW_VLAN_CTAG_RX |
6637 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6638 NETIF_F_TSO |
6639 NETIF_F_TSO6 |
70495a50 6640 NETIF_F_RXHASH |
dc221294
BA		 6641 NETIF_F_RXCSUM |
6642 NETIF_F_HW_CSUM);
6643
6644 /* Set user-changeable features (subset of all device features) */
6645 netdev->hw_features = netdev->features;
0184039a 6646 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6647 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6648 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6649
6650 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6651 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6652
dc221294
BA		 6653 netdev->vlan_features |= (NETIF_F_SG |
6654 NETIF_F_TSO |
6655 NETIF_F_TSO6 |
6656 NETIF_F_HW_CSUM);
a5136e23 6657
ef9b965a
JB		 6658 netdev->priv_flags |= IFF_UNICAST_FLT;
6659
7b872a55 6660 if (pci_using_dac) {
bc7f75fa 6661 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6662 netdev->vlan_features |= NETIF_F_HIGHDMA;
6663 }
bc7f75fa 6664
bc7f75fa
AK		 6665 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6666 adapter->flags |= FLAG_MNG_PT_ENABLED;
6667
e921eb1a 6668 /* before reading the NVM, reset the controller to
ad68076e
BA		 6669 * put the device in a known good starting state
6670 */
bc7f75fa
AK		 6671 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6672
e921eb1a 6673 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6674 * attempt. Let's give it a few tries
6675 */
6676 for (i = 0;; i++) {
6677 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6678 break;
6679 if (i == 2) {
185095fb 6680 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6681 err = -EIO;
6682 goto err_eeprom;
6683 }
6684 }
6685
10aa4c04
AK		 6686 e1000_eeprom_checks(adapter);
6687
608f8a0d 6688 /* copy the MAC address */
bc7f75fa 6689 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6690 dev_err(&pdev->dev,
6691 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6692
6693 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6694
aaeb6cdf 6695 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6696 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6697 netdev->dev_addr);
bc7f75fa
AK		 6698 err = -EIO;
6699 goto err_eeprom;
6700 }
6701
6702 init_timer(&adapter->watchdog_timer);
c061b18d 6703 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6704 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6705
6706 init_timer(&adapter->phy_info_timer);
c061b18d 6707 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6708 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6709
6710 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6711 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6712 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6713 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6714 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6715
bc7f75fa
AK		 6716 /* Initialize link parameters. User can change them with ethtool */
6717 adapter->hw.mac.autoneg = 1;
3db1cd5c 6718 adapter->fc_autoneg = true;
5c48ef3e
BA		 6719 adapter->hw.fc.requested_mode = e1000_fc_default;
6720 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6721 adapter->hw.phy.autoneg_advertised = 0x2f;
6722
6723 /* ring size defaults */
d821a4c4
BA		 6724 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6725 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6726
e921eb1a 6727 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6728 * the EEPROM, enable the ACPI Magic Packet filter
6729 */
6730 if (adapter->flags & FLAG_APME_IN_WUC) {
6731 /* APME bit in EEPROM is mapped to WUC.APME */
6732 eeprom_data = er32(WUC);
6733 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6734 if ((hw->mac.type > e1000_ich10lan) &&
6735 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6736 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6737 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6738 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6739 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6740 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6741 1, &eeprom_data);
bc7f75fa 6742 else
3d3a1676
BA		 6743 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6744 1, &eeprom_data);
bc7f75fa
AK		 6745 }
6746
6747 /* fetch WoL from EEPROM */
6748 if (eeprom_data & eeprom_apme_mask)
6749 adapter->eeprom_wol |= E1000_WUFC_MAG;
6750
e921eb1a 6751 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6752 * where the eeprom may be wrong or the board simply won't support
6753 * wake on lan on a particular port
6754 */
6755 if (!(adapter->flags & FLAG_HAS_WOL))
6756 adapter->eeprom_wol = 0;
6757
6758 /* initialize the wol settings based on the eeprom settings */
6759 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6760
6761 /* make sure adapter isn't asleep if manageability is enabled */
6762 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6763 (hw->mac.ops.check_mng_mode(hw)))
6764 device_wakeup_enable(&pdev->dev);
bc7f75fa 6765
84527590
BA		 6766 /* save off EEPROM version number */
6767 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6768
bc7f75fa
AK		 6769 /* reset the hardware with the new settings */
6770 e1000e_reset(adapter);
6771
e921eb1a 6772 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6773 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6774 * under the control of the driver.
6775 */
c43bc57e 6776 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6777 e1000e_get_hw_control(adapter);
bc7f75fa 6778
f2315bf1 6779 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6780 err = register_netdev(netdev);
6781 if (err)
6782 goto err_register;
6783
9c563d20
JB		 6784 /* carrier off reporting is important to ethtool even BEFORE open */
6785 netif_carrier_off(netdev);
6786
d89777bf
BA		 6787 /* init PTP hardware clock */
6788 e1000e_ptp_init(adapter);
6789
bc7f75fa
AK		 6790 e1000_print_device_info(adapter);
6791
f3ec4f87
AS		 6792 if (pci_dev_run_wake(pdev))
6793 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6794
bc7f75fa
AK		 6795 return 0;
6796
6797err_register:
c43bc57e 6798 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6799 e1000e_release_hw_control(adapter);
bc7f75fa 6800err_eeprom:
470a5420 6801 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6802 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6803err_hw_init:
bc7f75fa
AK		 6804 kfree(adapter->tx_ring);
6805 kfree(adapter->rx_ring);
6806err_sw_init:
c43bc57e
JB		 6807 if (adapter->hw.flash_address)
6808 iounmap(adapter->hw.flash_address);
e82f54ba 6809 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6810err_flashmap:
bc7f75fa
AK		 6811 iounmap(adapter->hw.hw_addr);
6812err_ioremap:
6813 free_netdev(netdev);
6814err_alloc_etherdev:
f0f422e5 6815 pci_release_selected_regions(pdev,
f0ff4398 6816 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6817err_pci_reg:
6818err_dma:
6819 pci_disable_device(pdev);
6820 return err;
6821}
6822
6823/**
6824 * e1000_remove - Device Removal Routine
6825 * @pdev: PCI device information struct
6826 *
6827 * e1000_remove is called by the PCI subsystem to alert the driver
6828 * that it should release a PCI device. The could be caused by a
6829 * Hot-Plug event, or because the driver is going to be removed from
6830 * memory.
6831 **/
9f9a12f8 6832static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6833{
6834 struct net_device *netdev = pci_get_drvdata(pdev);
6835 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6836 bool down = test_bit(__E1000_DOWN, &adapter->state);
6837
d89777bf
BA		 6838 e1000e_ptp_remove(adapter);
6839
e921eb1a 6840 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6841 * from being rescheduled.
ad68076e 6842 */
23606cf5
RW		 6843 if (!down)
6844 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6845 del_timer_sync(&adapter->watchdog_timer);
6846 del_timer_sync(&adapter->phy_info_timer);
6847
41cec6f1
BA		 6848 cancel_work_sync(&adapter->reset_task);
6849 cancel_work_sync(&adapter->watchdog_task);
6850 cancel_work_sync(&adapter->downshift_task);
6851 cancel_work_sync(&adapter->update_phy_task);
6852 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6853
b67e1913
BA		 6854 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6855 cancel_work_sync(&adapter->tx_hwtstamp_work);
6856 if (adapter->tx_hwtstamp_skb) {
6857 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6858 adapter->tx_hwtstamp_skb = NULL;
6859 }
6860 }
6861
17f208de
BA		 6862 if (!(netdev->flags & IFF_UP))
6863 e1000_power_down_phy(adapter);
6864
23606cf5
RW		 6865 /* Don't lie to e1000_close() down the road. */
6866 if (!down)
6867 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6868 unregister_netdev(netdev);
6869
f3ec4f87
AS		 6870 if (pci_dev_run_wake(pdev))
6871 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6872
e921eb1a 6873 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6874 * would have already happened in close and is redundant.
6875 */
31dbe5b4 6876 e1000e_release_hw_control(adapter);
bc7f75fa 6877
4662e82b 6878 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6879 kfree(adapter->tx_ring);
6880 kfree(adapter->rx_ring);
6881
6882 iounmap(adapter->hw.hw_addr);
6883 if (adapter->hw.flash_address)
6884 iounmap(adapter->hw.flash_address);
f0f422e5 6885 pci_release_selected_regions(pdev,
f0ff4398 6886 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6887
6888 free_netdev(netdev);
6889
111b9dc5 6890 /* AER disable */
19d5afd4 6891 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6892
bc7f75fa
AK		 6893 pci_disable_device(pdev);
6894}
6895
6896/* PCI Error Recovery (ERS) */
3646f0e5 6897static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6898 .error_detected = e1000_io_error_detected,
6899 .slot_reset = e1000_io_slot_reset,
6900 .resume = e1000_io_resume,
6901};
6902
a3aa1884 6903static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 6907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
6908 board_82571 },
bc7f75fa
AK		 6909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6914
bc7f75fa
AK		 6915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6919
bc7f75fa
AK		 6920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6923
4662e82b 6924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6927
bc7f75fa
AK		 6928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6929 board_80003es2lan },
6930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6931 board_80003es2lan },
6932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6933 board_80003es2lan },
6934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6935 board_80003es2lan },
ad68076e 6936
bc7f75fa
AK		 6937 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6939 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6940 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6941 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6943 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6944 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6945
bc7f75fa
AK		 6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6947 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6948 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6949 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6950 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6951 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6952 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6954 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6955
6956 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6957 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6959
f4187b56
BA		 6960 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6961 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6962 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6963
a4f58f54
BA		 6964 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6966 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6968
d3738bb8
BA		 6969 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6971
2fbe4526
BA		 6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6973 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6975 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6976
f36bb6ca 6977 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6978};
6979MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6980
aa338601 6981#ifdef CONFIG_PM
23606cf5 6982static const struct dev_pm_ops e1000_pm_ops = {
a0340162 6983 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
17e813ec
BA		 6984 SET_RUNTIME_PM_OPS(e1000_runtime_suspend, e1000_runtime_resume,
6985 e1000_idle)
23606cf5 6986};
e50208a0 6987#endif
23606cf5 6988
bc7f75fa
AK		 6989/* PCI Device API Driver */
6990static struct pci_driver e1000_driver = {
6991 .name = e1000e_driver_name,
6992 .id_table = e1000_pci_tbl,
6993 .probe = e1000_probe,
9f9a12f8 6994 .remove = e1000_remove,
aa338601 6995#ifdef CONFIG_PM
f36bb6ca
BA		 6996 .driver = {
6997 .pm = &e1000_pm_ops,
6998 },
bc7f75fa
AK		 6999#endif
7000 .shutdown = e1000_shutdown,
7001 .err_handler = &e1000_err_handler
7002};
7003
7004/**
7005 * e1000_init_module - Driver Registration Routine
7006 *
7007 * e1000_init_module is the first routine called when the driver is
7008 * loaded. All it does is register with the PCI subsystem.
7009 **/
7010static int __init e1000_init_module(void)
7011{
7012 int ret;
8544b9f7
BA		 7013 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7014 e1000e_driver_version);
bf67044b 7015 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
bc7f75fa 7016 ret = pci_register_driver(&e1000_driver);
53ec5498 7017
bc7f75fa
AK		 7018 return ret;
7019}
7020module_init(e1000_init_module);
7021
7022/**
7023 * e1000_exit_module - Driver Exit Cleanup Routine
7024 *
7025 * e1000_exit_module is called just before the driver is removed
7026 * from memory.
7027 **/
7028static void __exit e1000_exit_module(void)
7029{
7030 pci_unregister_driver(&e1000_driver);
7031}
7032module_exit(e1000_exit_module);
7033
7034
7035MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7036MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7037MODULE_LICENSE("GPL");
7038MODULE_VERSION(DRV_VERSION);
7039
06c24b91 7040/* netdev.c */
Linux kernel - Deliverables
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