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e1000e: add ethtool .get_eee/.set_eee
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
076d8070 59#define DRV_VERSION "2.1.4" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 82 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 83};
84
84f4ee90
TI		 85struct e1000_reg_info {
86 u32 ofs;
87 char *name;
88};
89
af667a29
BA		 90#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
91#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
92#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
93#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
94#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
95
96#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
97#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
98#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
99#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
100#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 101
102static const struct e1000_reg_info e1000_reg_info_tbl[] = {
103
104 /* General Registers */
105 {E1000_CTRL, "CTRL"},
106 {E1000_STATUS, "STATUS"},
107 {E1000_CTRL_EXT, "CTRL_EXT"},
108
109 /* Interrupt Registers */
110 {E1000_ICR, "ICR"},
111
af667a29 112 /* Rx Registers */
84f4ee90 113 {E1000_RCTL, "RCTL"},
1e36052e
BA		 114 {E1000_RDLEN(0), "RDLEN"},
115 {E1000_RDH(0), "RDH"},
116 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 117 {E1000_RDTR, "RDTR"},
118 {E1000_RXDCTL(0), "RXDCTL"},
119 {E1000_ERT, "ERT"},
1e36052e
BA		 120 {E1000_RDBAL(0), "RDBAL"},
121 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 122 {E1000_RDFH, "RDFH"},
123 {E1000_RDFT, "RDFT"},
124 {E1000_RDFHS, "RDFHS"},
125 {E1000_RDFTS, "RDFTS"},
126 {E1000_RDFPC, "RDFPC"},
127
af667a29 128 /* Tx Registers */
84f4ee90 129 {E1000_TCTL, "TCTL"},
1e36052e
BA		 130 {E1000_TDBAL(0), "TDBAL"},
131 {E1000_TDBAH(0), "TDBAH"},
132 {E1000_TDLEN(0), "TDLEN"},
133 {E1000_TDH(0), "TDH"},
134 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 135 {E1000_TIDV, "TIDV"},
136 {E1000_TXDCTL(0), "TXDCTL"},
137 {E1000_TADV, "TADV"},
138 {E1000_TARC(0), "TARC"},
139 {E1000_TDFH, "TDFH"},
140 {E1000_TDFT, "TDFT"},
141 {E1000_TDFHS, "TDFHS"},
142 {E1000_TDFTS, "TDFTS"},
143 {E1000_TDFPC, "TDFPC"},
144
145 /* List Terminator */
f36bb6ca 146 {0, NULL}
84f4ee90
TI		 147};
148
e921eb1a 149/**
84f4ee90 150 * e1000_regdump - register printout routine
e921eb1a
BA		 151 * @hw: pointer to the HW structure
152 * @reginfo: pointer to the register info table
153 **/
84f4ee90
TI		 154static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
155{
156 int n = 0;
157 char rname[16];
158 u32 regs[8];
159
160 switch (reginfo->ofs) {
161 case E1000_RXDCTL(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_RXDCTL(n));
164 break;
165 case E1000_TXDCTL(0):
166 for (n = 0; n < 2; n++)
167 regs[n] = __er32(hw, E1000_TXDCTL(n));
168 break;
169 case E1000_TARC(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_TARC(n));
172 break;
173 default:
ef456f85
JK		 174 pr_info("%-15s %08x\n",
175 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 176 return;
177 }
178
179 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 180 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 181}
182
f0c5dadf
ET		 183static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
184 struct e1000_buffer *bi)
185{
186 int i;
187 struct e1000_ps_page *ps_page;
188
189 for (i = 0; i < adapter->rx_ps_pages; i++) {
190 ps_page = &bi->ps_pages[i];
191
192 if (ps_page->page) {
193 pr_info("packet dump for ps_page %d:\n", i);
194 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
195 16, 1, page_address(ps_page->page),
196 PAGE_SIZE, true);
197 }
198 }
199}
200
e921eb1a 201/**
af667a29 202 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 203 * @adapter: board private structure
204 **/
84f4ee90
TI		 205static void e1000e_dump(struct e1000_adapter *adapter)
206{
207 struct net_device *netdev = adapter->netdev;
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_reg_info *reginfo;
210 struct e1000_ring *tx_ring = adapter->tx_ring;
211 struct e1000_tx_desc *tx_desc;
af667a29 212 struct my_u0 {
e885d762
BA		 213 __le64 a;
214 __le64 b;
af667a29 215 } *u0;
84f4ee90
TI		 216 struct e1000_buffer *buffer_info;
217 struct e1000_ring *rx_ring = adapter->rx_ring;
218 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 219 union e1000_rx_desc_extended *rx_desc;
af667a29 220 struct my_u1 {
e885d762
BA		 221 __le64 a;
222 __le64 b;
223 __le64 c;
224 __le64 d;
af667a29 225 } *u1;
84f4ee90
TI		 226 u32 staterr;
227 int i = 0;
228
229 if (!netif_msg_hw(adapter))
230 return;
231
232 /* Print netdevice Info */
233 if (netdev) {
234 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 235 pr_info("Device Name state trans_start last_rx\n");
236 pr_info("%-15s %016lX %016lX %016lX\n",
237 netdev->name, netdev->state, netdev->trans_start,
238 netdev->last_rx);
84f4ee90
TI		 239 }
240
241 /* Print Registers */
242 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 243 pr_info(" Register Name Value\n");
84f4ee90
TI		 244 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
245 reginfo->name; reginfo++) {
246 e1000_regdump(hw, reginfo);
247 }
248
af667a29 249 /* Print Tx Ring Summary */
84f4ee90 250 if (!netdev || !netif_running(netdev))
fe1e980f 251 return;
84f4ee90 252
af667a29 253 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 254 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 255 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 256 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
257 0, tx_ring->next_to_use, tx_ring->next_to_clean,
258 (unsigned long long)buffer_info->dma,
259 buffer_info->length,
260 buffer_info->next_to_watch,
261 (unsigned long long)buffer_info->time_stamp);
84f4ee90 262
af667a29 263 /* Print Tx Ring */
84f4ee90
TI		 264 if (!netif_msg_tx_done(adapter))
265 goto rx_ring_summary;
266
af667a29 267 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 268
269 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
270 *
271 * Legacy Transmit Descriptor
272 * +--------------------------------------------------------------+
273 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
274 * +--------------------------------------------------------------+
275 * 8 | Special | CSS | Status | CMD | CSO | Length |
276 * +--------------------------------------------------------------+
277 * 63 48 47 36 35 32 31 24 23 16 15 0
278 *
279 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
280 * 63 48 47 40 39 32 31 16 15 8 7 0
281 * +----------------------------------------------------------------+
282 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
283 * +----------------------------------------------------------------+
284 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
285 * +----------------------------------------------------------------+
286 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
287 *
288 * Extended Data Descriptor (DTYP=0x1)
289 * +----------------------------------------------------------------+
290 * 0 | Buffer Address [63:0] |
291 * +----------------------------------------------------------------+
292 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
293 * +----------------------------------------------------------------+
294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
295 */
ef456f85
JK		 296 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
297 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
298 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 299 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 300 const char *next_desc;
84f4ee90
TI		 301 tx_desc = E1000_TX_DESC(*tx_ring, i);
302 buffer_info = &tx_ring->buffer_info[i];
303 u0 = (struct my_u0 *)tx_desc;
84f4ee90 304 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 305 next_desc = " NTC/U";
84f4ee90 306 else if (i == tx_ring->next_to_use)
ef456f85 307 next_desc = " NTU";
84f4ee90 308 else if (i == tx_ring->next_to_clean)
ef456f85 309 next_desc = " NTC";
84f4ee90 310 else
ef456f85
JK		 311 next_desc = "";
312 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
313 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
314 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
315 i,
316 (unsigned long long)le64_to_cpu(u0->a),
317 (unsigned long long)le64_to_cpu(u0->b),
318 (unsigned long long)buffer_info->dma,
319 buffer_info->length, buffer_info->next_to_watch,
320 (unsigned long long)buffer_info->time_stamp,
321 buffer_info->skb, next_desc);
84f4ee90 322
f0c5dadf 323 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 324 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 325 16, 1, buffer_info->skb->data,
326 buffer_info->skb->len, true);
84f4ee90
TI		 327 }
328
af667a29 329 /* Print Rx Ring Summary */
84f4ee90 330rx_ring_summary:
af667a29 331 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 332 pr_info("Queue [NTU] [NTC]\n");
333 pr_info(" %5d %5X %5X\n",
334 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 335
af667a29 336 /* Print Rx Ring */
84f4ee90 337 if (!netif_msg_rx_status(adapter))
fe1e980f 338 return;
84f4ee90 339
af667a29 340 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 341 switch (adapter->rx_ps_pages) {
342 case 1:
343 case 2:
344 case 3:
345 /* [Extended] Packet Split Receive Descriptor Format
346 *
347 * +-----------------------------------------------------+
348 * 0 | Buffer Address 0 [63:0] |
349 * +-----------------------------------------------------+
350 * 8 | Buffer Address 1 [63:0] |
351 * +-----------------------------------------------------+
352 * 16 | Buffer Address 2 [63:0] |
353 * +-----------------------------------------------------+
354 * 24 | Buffer Address 3 [63:0] |
355 * +-----------------------------------------------------+
356 */
ef456f85 357 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 358 /* [Extended] Receive Descriptor (Write-Back) Format
359 *
360 * 63 48 47 32 31 13 12 8 7 4 3 0
361 * +------------------------------------------------------+
362 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
363 * | Checksum | Ident | | Queue | | Type |
364 * +------------------------------------------------------+
365 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
366 * +------------------------------------------------------+
367 * 63 48 47 32 31 20 19 0
368 */
ef456f85 369 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 370 for (i = 0; i < rx_ring->count; i++) {
ef456f85 371 const char *next_desc;
84f4ee90
TI		 372 buffer_info = &rx_ring->buffer_info[i];
373 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
374 u1 = (struct my_u1 *)rx_desc_ps;
375 staterr =
af667a29 376 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 377
378 if (i == rx_ring->next_to_use)
379 next_desc = " NTU";
380 else if (i == rx_ring->next_to_clean)
381 next_desc = " NTC";
382 else
383 next_desc = "";
384
84f4ee90
TI		 385 if (staterr & E1000_RXD_STAT_DD) {
386 /* Descriptor Done */
ef456f85
JK		 387 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
388 "RWB", i,
389 (unsigned long long)le64_to_cpu(u1->a),
390 (unsigned long long)le64_to_cpu(u1->b),
391 (unsigned long long)le64_to_cpu(u1->c),
392 (unsigned long long)le64_to_cpu(u1->d),
393 buffer_info->skb, next_desc);
84f4ee90 394 } else {
ef456f85
JK		 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
396 "R ", i,
397 (unsigned long long)le64_to_cpu(u1->a),
398 (unsigned long long)le64_to_cpu(u1->b),
399 (unsigned long long)le64_to_cpu(u1->c),
400 (unsigned long long)le64_to_cpu(u1->d),
401 (unsigned long long)buffer_info->dma,
402 buffer_info->skb, next_desc);
84f4ee90
TI		 403
404 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 405 e1000e_dump_ps_pages(adapter,
406 buffer_info);
84f4ee90 407 }
84f4ee90
TI		 408 }
409 break;
410 default:
411 case 0:
5f450212 412 /* Extended Receive Descriptor (Read) Format
84f4ee90 413 *
5f450212
BA		 414 * +-----------------------------------------------------+
415 * 0 | Buffer Address [63:0] |
416 * +-----------------------------------------------------+
417 * 8 | Reserved |
418 * +-----------------------------------------------------+
84f4ee90 419 */
ef456f85 420 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 421 /* Extended Receive Descriptor (Write-Back) Format
422 *
423 * 63 48 47 32 31 24 23 4 3 0
424 * +------------------------------------------------------+
425 * | RSS Hash | | | |
426 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
427 * | Packet | IP | | | Type |
428 * | Checksum | Ident | | | |
429 * +------------------------------------------------------+
430 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
431 * +------------------------------------------------------+
432 * 63 48 47 32 31 20 19 0
433 */
ef456f85 434 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 435
436 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 437 const char *next_desc;
438
84f4ee90 439 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 440 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
441 u1 = (struct my_u1 *)rx_desc;
442 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 443
444 if (i == rx_ring->next_to_use)
445 next_desc = " NTU";
446 else if (i == rx_ring->next_to_clean)
447 next_desc = " NTC";
448 else
449 next_desc = "";
450
5f450212
BA		 451 if (staterr & E1000_RXD_STAT_DD) {
452 /* Descriptor Done */
ef456f85
JK		 453 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
454 "RWB", i,
455 (unsigned long long)le64_to_cpu(u1->a),
456 (unsigned long long)le64_to_cpu(u1->b),
457 buffer_info->skb, next_desc);
5f450212 458 } else {
ef456f85
JK		 459 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
460 "R ", i,
461 (unsigned long long)le64_to_cpu(u1->a),
462 (unsigned long long)le64_to_cpu(u1->b),
463 (unsigned long long)buffer_info->dma,
464 buffer_info->skb, next_desc);
5f450212 465
f0c5dadf
ET		 466 if (netif_msg_pktdata(adapter) &&
467 buffer_info->skb)
5f450212
BA		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16,
470 1,
f0c5dadf 471 buffer_info->skb->data,
5f450212
BA		 472 adapter->rx_buffer_len,
473 true);
474 }
84f4ee90
TI		 475 }
476 }
84f4ee90
TI		 477}
478
bc7f75fa
AK		 479/**
480 * e1000_desc_unused - calculate if we have unused descriptors
481 **/
482static int e1000_desc_unused(struct e1000_ring *ring)
483{
484 if (ring->next_to_clean > ring->next_to_use)
485 return ring->next_to_clean - ring->next_to_use - 1;
486
487 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
488}
489
490/**
ad68076e 491 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 492 * @adapter: board private structure
493 * @status: descriptor status field as written by hardware
494 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
495 * @skb: pointer to sk_buff to be indicated to stack
496 **/
497static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 498 struct net_device *netdev, struct sk_buff *skb,
a39fe742 499 u8 status, __le16 vlan)
bc7f75fa 500{
86d70e53 501 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 502 skb->protocol = eth_type_trans(skb, netdev);
503
86d70e53
JK		 504 if (status & E1000_RXD_STAT_VP)
505 __vlan_hwaccel_put_tag(skb, tag);
506
507 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 508}
509
510/**
af667a29 511 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 512 * @adapter: board private structure
513 * @status_err: receive descriptor status and error fields
514 * @csum: receive descriptor csum field
515 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 516 **/
517static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 518 struct sk_buff *skb)
bc7f75fa
AK		 519{
520 u16 status = (u16)status_err;
521 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 522
523 skb_checksum_none_assert(skb);
bc7f75fa 524
afd12939
BA		 525 /* Rx checksum disabled */
526 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
527 return;
528
bc7f75fa
AK		 529 /* Ignore Checksum bit is set */
530 if (status & E1000_RXD_STAT_IXSM)
531 return;
afd12939 532
2e1706f2
BA		 533 /* TCP/UDP checksum error bit or IP checksum error bit is set */
534 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 535 /* let the stack verify checksum errors */
536 adapter->hw_csum_err++;
537 return;
538 }
539
540 /* TCP/UDP Checksum has not been calculated */
541 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
542 return;
543
544 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 545 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 546 adapter->hw_csum_good++;
547}
548
55aa6985 549static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 550{
55aa6985 551 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 552 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 553 s32 ret_val = __ew32_prepare(hw);
554
555 writel(i, rx_ring->tail);
c6e7f51e 556
bdc125f7 557 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 558 u32 rctl = er32(RCTL);
559 ew32(RCTL, rctl & ~E1000_RCTL_EN);
560 e_err("ME firmware caused invalid RDT - resetting\n");
561 schedule_work(&adapter->reset_task);
562 }
563}
564
55aa6985 565static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 566{
55aa6985 567 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 568 struct e1000_hw *hw = &adapter->hw;
bdc125f7 569 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 570
bdc125f7
BA		 571 writel(i, tx_ring->tail);
572
573 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 574 u32 tctl = er32(TCTL);
575 ew32(TCTL, tctl & ~E1000_TCTL_EN);
576 e_err("ME firmware caused invalid TDT - resetting\n");
577 schedule_work(&adapter->reset_task);
578 }
579}
580
bc7f75fa 581/**
5f450212 582 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 583 * @rx_ring: Rx descriptor ring
bc7f75fa 584 **/
55aa6985 585static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 586 int cleaned_count, gfp_t gfp)
bc7f75fa 587{
55aa6985 588 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 589 struct net_device *netdev = adapter->netdev;
590 struct pci_dev *pdev = adapter->pdev;
5f450212 591 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 592 struct e1000_buffer *buffer_info;
593 struct sk_buff *skb;
594 unsigned int i;
89d71a66 595 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 596
597 i = rx_ring->next_to_use;
598 buffer_info = &rx_ring->buffer_info[i];
599
600 while (cleaned_count--) {
601 skb = buffer_info->skb;
602 if (skb) {
603 skb_trim(skb, 0);
604 goto map_skb;
605 }
606
c2fed996 607 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 608 if (!skb) {
609 /* Better luck next round */
610 adapter->alloc_rx_buff_failed++;
611 break;
612 }
613
bc7f75fa
AK		 614 buffer_info->skb = skb;
615map_skb:
0be3f55f 616 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 617 adapter->rx_buffer_len,
0be3f55f
NN		 618 DMA_FROM_DEVICE);
619 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 620 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 621 adapter->rx_dma_failed++;
622 break;
623 }
624
5f450212
BA		 625 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
626 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 627
50849d79 628 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 629 /* Force memory writes to complete before letting h/w
50849d79
TH		 630 * know there are new descriptors to fetch. (Only
631 * applicable for weak-ordered memory model archs,
632 * such as IA-64).
633 */
634 wmb();
c6e7f51e 635 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 636 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 637 else
c5083cf6 638 writel(i, rx_ring->tail);
50849d79 639 }
bc7f75fa
AK		 640 i++;
641 if (i == rx_ring->count)
642 i = 0;
643 buffer_info = &rx_ring->buffer_info[i];
644 }
645
50849d79 646 rx_ring->next_to_use = i;
bc7f75fa
AK		 647}
648
649/**
650 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 651 * @rx_ring: Rx descriptor ring
bc7f75fa 652 **/
55aa6985 653static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 654 int cleaned_count, gfp_t gfp)
bc7f75fa 655{
55aa6985 656 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 657 struct net_device *netdev = adapter->netdev;
658 struct pci_dev *pdev = adapter->pdev;
659 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 660 struct e1000_buffer *buffer_info;
661 struct e1000_ps_page *ps_page;
662 struct sk_buff *skb;
663 unsigned int i, j;
664
665 i = rx_ring->next_to_use;
666 buffer_info = &rx_ring->buffer_info[i];
667
668 while (cleaned_count--) {
669 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
670
671 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 672 ps_page = &buffer_info->ps_pages[j];
673 if (j >= adapter->rx_ps_pages) {
674 /* all unused desc entries get hw null ptr */
af667a29
BA		 675 rx_desc->read.buffer_addr[j + 1] =
676 ~cpu_to_le64(0);
47f44e40
AK		 677 continue;
678 }
679 if (!ps_page->page) {
c2fed996 680 ps_page->page = alloc_page(gfp);
bc7f75fa 681 if (!ps_page->page) {
47f44e40
AK		 682 adapter->alloc_rx_buff_failed++;
683 goto no_buffers;
684 }
0be3f55f
NN		 685 ps_page->dma = dma_map_page(&pdev->dev,
686 ps_page->page,
687 0, PAGE_SIZE,
688 DMA_FROM_DEVICE);
689 if (dma_mapping_error(&pdev->dev,
690 ps_page->dma)) {
47f44e40 691 dev_err(&adapter->pdev->dev,
af667a29 692 "Rx DMA page map failed\n");
47f44e40
AK		 693 adapter->rx_dma_failed++;
694 goto no_buffers;
bc7f75fa 695 }
bc7f75fa 696 }
e921eb1a 697 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 698 * didn't change because each write-back
699 * erases this info.
700 */
af667a29
BA		 701 rx_desc->read.buffer_addr[j + 1] =
702 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 703 }
704
c2fed996
JK		 705 skb = __netdev_alloc_skb_ip_align(netdev,
706 adapter->rx_ps_bsize0,
707 gfp);
bc7f75fa
AK		 708
709 if (!skb) {
710 adapter->alloc_rx_buff_failed++;
711 break;
712 }
713
bc7f75fa 714 buffer_info->skb = skb;
0be3f55f 715 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 716 adapter->rx_ps_bsize0,
0be3f55f
NN		 717 DMA_FROM_DEVICE);
718 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 719 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 720 adapter->rx_dma_failed++;
721 /* cleanup skb */
722 dev_kfree_skb_any(skb);
723 buffer_info->skb = NULL;
724 break;
725 }
726
727 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
728
50849d79 729 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 730 /* Force memory writes to complete before letting h/w
50849d79
TH		 731 * know there are new descriptors to fetch. (Only
732 * applicable for weak-ordered memory model archs,
733 * such as IA-64).
734 */
735 wmb();
c6e7f51e 736 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 737 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 738 else
c5083cf6 739 writel(i << 1, rx_ring->tail);
50849d79
TH		 740 }
741
bc7f75fa
AK		 742 i++;
743 if (i == rx_ring->count)
744 i = 0;
745 buffer_info = &rx_ring->buffer_info[i];
746 }
747
748no_buffers:
50849d79 749 rx_ring->next_to_use = i;
bc7f75fa
AK		 750}
751
97ac8cae
BA		 752/**
753 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 754 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 755 * @cleaned_count: number of buffers to allocate this pass
756 **/
757
55aa6985 758static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 759 int cleaned_count, gfp_t gfp)
97ac8cae 760{
55aa6985 761 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 762 struct net_device *netdev = adapter->netdev;
763 struct pci_dev *pdev = adapter->pdev;
5f450212 764 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 765 struct e1000_buffer *buffer_info;
766 struct sk_buff *skb;
767 unsigned int i;
2a2293b9 768 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 769
770 i = rx_ring->next_to_use;
771 buffer_info = &rx_ring->buffer_info[i];
772
773 while (cleaned_count--) {
774 skb = buffer_info->skb;
775 if (skb) {
776 skb_trim(skb, 0);
777 goto check_page;
778 }
779
c2fed996 780 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 781 if (unlikely(!skb)) {
782 /* Better luck next round */
783 adapter->alloc_rx_buff_failed++;
784 break;
785 }
786
97ac8cae
BA		 787 buffer_info->skb = skb;
788check_page:
789 /* allocate a new page if necessary */
790 if (!buffer_info->page) {
c2fed996 791 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 792 if (unlikely(!buffer_info->page)) {
793 adapter->alloc_rx_buff_failed++;
794 break;
795 }
796 }
797
798 if (!buffer_info->dma)
0be3f55f 799 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 800 buffer_info->page, 0,
801 PAGE_SIZE,
0be3f55f 802 DMA_FROM_DEVICE);
97ac8cae 803
5f450212
BA		 804 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
805 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 806
807 if (unlikely(++i == rx_ring->count))
808 i = 0;
809 buffer_info = &rx_ring->buffer_info[i];
810 }
811
812 if (likely(rx_ring->next_to_use != i)) {
813 rx_ring->next_to_use = i;
814 if (unlikely(i-- == 0))
815 i = (rx_ring->count - 1);
816
817 /* Force memory writes to complete before letting h/w
818 * know there are new descriptors to fetch. (Only
819 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 820 * such as IA-64).
821 */
97ac8cae 822 wmb();
c6e7f51e 823 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 824 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 825 else
c5083cf6 826 writel(i, rx_ring->tail);
97ac8cae
BA		 827 }
828}
829
70495a50
BA		 830static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
831 struct sk_buff *skb)
832{
833 if (netdev->features & NETIF_F_RXHASH)
834 skb->rxhash = le32_to_cpu(rss);
835}
836
bc7f75fa 837/**
55aa6985
BA		 838 * e1000_clean_rx_irq - Send received data up the network stack
839 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 840 *
841 * the return value indicates whether actual cleaning was done, there
842 * is no guarantee that everything was cleaned
843 **/
55aa6985
BA		 844static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
845 int work_to_do)
bc7f75fa 846{
55aa6985 847 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 848 struct net_device *netdev = adapter->netdev;
849 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 850 struct e1000_hw *hw = &adapter->hw;
5f450212 851 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 852 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 853 u32 length, staterr;
bc7f75fa
AK		 854 unsigned int i;
855 int cleaned_count = 0;
3db1cd5c 856 bool cleaned = false;
bc7f75fa
AK		 857 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
858
859 i = rx_ring->next_to_clean;
5f450212
BA		 860 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
861 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 862 buffer_info = &rx_ring->buffer_info[i];
863
5f450212 864 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 865 struct sk_buff *skb;
bc7f75fa
AK		 866
867 if (*work_done >= work_to_do)
868 break;
869 (*work_done)++;
2d0bb1c1 870 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 871
bc7f75fa
AK		 872 skb = buffer_info->skb;
873 buffer_info->skb = NULL;
874
875 prefetch(skb->data - NET_IP_ALIGN);
876
877 i++;
878 if (i == rx_ring->count)
879 i = 0;
5f450212 880 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 881 prefetch(next_rxd);
882
883 next_buffer = &rx_ring->buffer_info[i];
884
3db1cd5c 885 cleaned = true;
bc7f75fa 886 cleaned_count++;
0be3f55f 887 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 888 buffer_info->dma,
889 adapter->rx_buffer_len,
0be3f55f 890 DMA_FROM_DEVICE);
bc7f75fa
AK		 891 buffer_info->dma = 0;
892
5f450212 893 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 894
e921eb1a 895 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 896 * packet, if that's the case we need to toss it. In fact, we
897 * need to toss every packet with the EOP bit clear and the
898 * next frame that _does_ have the EOP bit set, as it is by
899 * definition only a frame fragment
900 */
5f450212 901 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 902 adapter->flags2 |= FLAG2_IS_DISCARDING;
903
904 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 905 /* All receives must fit into a single buffer */
3bb99fe2 906 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 907 /* recycle */
908 buffer_info->skb = skb;
5f450212 909 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 910 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 911 goto next_desc;
912 }
913
cf955e6c
BG		 914 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
915 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 916 /* recycle */
917 buffer_info->skb = skb;
918 goto next_desc;
919 }
920
eb7c3adb 921 /* adjust length to remove Ethernet CRC */
0184039a
BG		 922 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
923 /* If configured to store CRC, don't subtract FCS,
924 * but keep the FCS bytes out of the total_rx_bytes
925 * counter
926 */
927 if (netdev->features & NETIF_F_RXFCS)
928 total_rx_bytes -= 4;
929 else
930 length -= 4;
931 }
eb7c3adb 932
bc7f75fa
AK		 933 total_rx_bytes += length;
934 total_rx_packets++;
935
e921eb1a 936 /* code added for copybreak, this should improve
bc7f75fa 937 * performance for small packets with large amounts
ad68076e
BA		 938 * of reassembly being done in the stack
939 */
bc7f75fa
AK		 940 if (length < copybreak) {
941 struct sk_buff *new_skb =
89d71a66 942 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 943 if (new_skb) {
808ff676
BA		 944 skb_copy_to_linear_data_offset(new_skb,
945 -NET_IP_ALIGN,
946 (skb->data -
947 NET_IP_ALIGN),
948 (length +
949 NET_IP_ALIGN));
bc7f75fa
AK		 950 /* save the skb in buffer_info as good */
951 buffer_info->skb = skb;
952 skb = new_skb;
953 }
954 /* else just continue with the old one */
955 }
956 /* end copybreak code */
957 skb_put(skb, length);
958
959 /* Receive Checksum Offload */
2e1706f2 960 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 961
70495a50
BA		 962 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
963
5f450212
BA		 964 e1000_receive_skb(adapter, netdev, skb, staterr,
965 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 966
967next_desc:
5f450212 968 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 969
970 /* return some buffers to hardware, one at a time is too slow */
971 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 972 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 973 GFP_ATOMIC);
bc7f75fa
AK		 974 cleaned_count = 0;
975 }
976
977 /* use prefetched values */
978 rx_desc = next_rxd;
979 buffer_info = next_buffer;
5f450212
BA		 980
981 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 982 }
983 rx_ring->next_to_clean = i;
984
985 cleaned_count = e1000_desc_unused(rx_ring);
986 if (cleaned_count)
55aa6985 987 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 988
bc7f75fa 989 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 990 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 991 return cleaned;
992}
993
55aa6985
BA		 994static void e1000_put_txbuf(struct e1000_ring *tx_ring,
995 struct e1000_buffer *buffer_info)
bc7f75fa 996{
55aa6985
BA		 997 struct e1000_adapter *adapter = tx_ring->adapter;
998
03b1320d
AD		 999 if (buffer_info->dma) {
1000 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1001 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1002 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1003 else
0be3f55f
NN		 1004 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1005 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1006 buffer_info->dma = 0;
1007 }
bc7f75fa
AK		 1008 if (buffer_info->skb) {
1009 dev_kfree_skb_any(buffer_info->skb);
1010 buffer_info->skb = NULL;
1011 }
1b7719c4 1012 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1013}
1014
41cec6f1 1015static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1016{
41cec6f1
BA		 1017 struct e1000_adapter *adapter = container_of(work,
1018 struct e1000_adapter,
1019 print_hang_task);
09357b00 1020 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1021 struct e1000_ring *tx_ring = adapter->tx_ring;
1022 unsigned int i = tx_ring->next_to_clean;
1023 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1024 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1025 struct e1000_hw *hw = &adapter->hw;
1026 u16 phy_status, phy_1000t_status, phy_ext_status;
1027 u16 pci_status;
1028
615b32af
JB		 1029 if (test_bit(__E1000_DOWN, &adapter->state))
1030 return;
1031
09357b00
JK		 1032 if (!adapter->tx_hang_recheck &&
1033 (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1034 /* May be block on write-back, flush and detect again
09357b00
JK		 1035 * flush pending descriptor writebacks to memory
1036 */
1037 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1038 /* execute the writes immediately */
1039 e1e_flush();
e921eb1a 1040 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1041 * the write is successful
1042 */
1043 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1044 /* execute the writes immediately */
1045 e1e_flush();
09357b00
JK		 1046 adapter->tx_hang_recheck = true;
1047 return;
1048 }
1049 /* Real hang detected */
1050 adapter->tx_hang_recheck = false;
1051 netif_stop_queue(netdev);
1052
41cec6f1
BA		 1053 e1e_rphy(hw, PHY_STATUS, &phy_status);
1054 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1055 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1056
41cec6f1
BA		 1057 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1058
1059 /* detected Hardware unit hang */
1060 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1061 " TDH <%x>\n"
1062 " TDT <%x>\n"
1063 " next_to_use <%x>\n"
1064 " next_to_clean <%x>\n"
1065 "buffer_info[next_to_clean]:\n"
1066 " time_stamp <%lx>\n"
1067 " next_to_watch <%x>\n"
1068 " jiffies <%lx>\n"
41cec6f1
BA		 1069 " next_to_watch.status <%x>\n"
1070 "MAC Status <%x>\n"
1071 "PHY Status <%x>\n"
1072 "PHY 1000BASE-T Status <%x>\n"
1073 "PHY Extended Status <%x>\n"
1074 "PCI Status <%x>\n",
c5083cf6
BA		 1075 readl(tx_ring->head),
1076 readl(tx_ring->tail),
44defeb3
JK		 1077 tx_ring->next_to_use,
1078 tx_ring->next_to_clean,
1079 tx_ring->buffer_info[eop].time_stamp,
1080 eop,
1081 jiffies,
41cec6f1
BA		 1082 eop_desc->upper.fields.status,
1083 er32(STATUS),
1084 phy_status,
1085 phy_1000t_status,
1086 phy_ext_status,
1087 pci_status);
7c0427ee
BA		 1088
1089 /* Suggest workaround for known h/w issue */
1090 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1091 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1092}
1093
1094/**
1095 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1096 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1097 *
1098 * the return value indicates whether actual cleaning was done, there
1099 * is no guarantee that everything was cleaned
1100 **/
55aa6985 1101static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1102{
55aa6985 1103 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1104 struct net_device *netdev = adapter->netdev;
1105 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1106 struct e1000_tx_desc *tx_desc, *eop_desc;
1107 struct e1000_buffer *buffer_info;
1108 unsigned int i, eop;
1109 unsigned int count = 0;
bc7f75fa 1110 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1111 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1112
1113 i = tx_ring->next_to_clean;
1114 eop = tx_ring->buffer_info[i].next_to_watch;
1115 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1116
12d04a3c
AD		 1117 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1118 (count < tx_ring->count)) {
a86043c2 1119 bool cleaned = false;
2d0bb1c1 1120 rmb(); /* read buffer_info after eop_desc */
a86043c2 1121 for (; !cleaned; count++) {
bc7f75fa
AK		 1122 tx_desc = E1000_TX_DESC(*tx_ring, i);
1123 buffer_info = &tx_ring->buffer_info[i];
1124 cleaned = (i == eop);
1125
1126 if (cleaned) {
9ed318d5
TH		 1127 total_tx_packets += buffer_info->segs;
1128 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1129 if (buffer_info->skb) {
1130 bytes_compl += buffer_info->skb->len;
1131 pkts_compl++;
1132 }
bc7f75fa
AK		 1133 }
1134
55aa6985 1135 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1136 tx_desc->upper.data = 0;
1137
1138 i++;
1139 if (i == tx_ring->count)
1140 i = 0;
1141 }
1142
dac87619
TL		 1143 if (i == tx_ring->next_to_use)
1144 break;
bc7f75fa
AK		 1145 eop = tx_ring->buffer_info[i].next_to_watch;
1146 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1147 }
1148
1149 tx_ring->next_to_clean = i;
1150
3f0cfa3b
TH		 1151 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1152
bc7f75fa 1153#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1154 if (count && netif_carrier_ok(netdev) &&
1155 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1156 /* Make sure that anybody stopping the queue after this
1157 * sees the new next_to_clean.
1158 */
1159 smp_mb();
1160
1161 if (netif_queue_stopped(netdev) &&
1162 !(test_bit(__E1000_DOWN, &adapter->state))) {
1163 netif_wake_queue(netdev);
1164 ++adapter->restart_queue;
1165 }
1166 }
1167
1168 if (adapter->detect_tx_hung) {
e921eb1a 1169 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1170 * check with the clearing of time_stamp and movement of i
1171 */
3db1cd5c 1172 adapter->detect_tx_hung = false;
12d04a3c
AD		 1173 if (tx_ring->buffer_info[i].time_stamp &&
1174 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1175 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1176 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1177 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1178 else
1179 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1180 }
1181 adapter->total_tx_bytes += total_tx_bytes;
1182 adapter->total_tx_packets += total_tx_packets;
807540ba 1183 return count < tx_ring->count;
bc7f75fa
AK		 1184}
1185
bc7f75fa
AK		 1186/**
1187 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1188 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1189 *
1190 * the return value indicates whether actual cleaning was done, there
1191 * is no guarantee that everything was cleaned
1192 **/
55aa6985
BA		 1193static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1194 int work_to_do)
bc7f75fa 1195{
55aa6985 1196 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1197 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1198 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1199 struct net_device *netdev = adapter->netdev;
1200 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1201 struct e1000_buffer *buffer_info, *next_buffer;
1202 struct e1000_ps_page *ps_page;
1203 struct sk_buff *skb;
1204 unsigned int i, j;
1205 u32 length, staterr;
1206 int cleaned_count = 0;
3db1cd5c 1207 bool cleaned = false;
bc7f75fa
AK		 1208 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1209
1210 i = rx_ring->next_to_clean;
1211 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1212 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1213 buffer_info = &rx_ring->buffer_info[i];
1214
1215 while (staterr & E1000_RXD_STAT_DD) {
1216 if (*work_done >= work_to_do)
1217 break;
1218 (*work_done)++;
1219 skb = buffer_info->skb;
2d0bb1c1 1220 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1221
1222 /* in the packet split case this is header only */
1223 prefetch(skb->data - NET_IP_ALIGN);
1224
1225 i++;
1226 if (i == rx_ring->count)
1227 i = 0;
1228 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1229 prefetch(next_rxd);
1230
1231 next_buffer = &rx_ring->buffer_info[i];
1232
3db1cd5c 1233 cleaned = true;
bc7f75fa 1234 cleaned_count++;
0be3f55f 1235 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1236 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1237 buffer_info->dma = 0;
1238
af667a29 1239 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1240 if (!(staterr & E1000_RXD_STAT_EOP))
1241 adapter->flags2 |= FLAG2_IS_DISCARDING;
1242
1243 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1244 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1245 dev_kfree_skb_irq(skb);
b94b5028
JB		 1246 if (staterr & E1000_RXD_STAT_EOP)
1247 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1248 goto next_desc;
1249 }
1250
cf955e6c
BG		 1251 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1252 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1253 dev_kfree_skb_irq(skb);
1254 goto next_desc;
1255 }
1256
1257 length = le16_to_cpu(rx_desc->wb.middle.length0);
1258
1259 if (!length) {
ef456f85 1260 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1261 dev_kfree_skb_irq(skb);
1262 goto next_desc;
1263 }
1264
1265 /* Good Receive */
1266 skb_put(skb, length);
1267
1268 {
e921eb1a 1269 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1270 * it more efficient than reusing j
1271 */
1272 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1273
e921eb1a 1274 /* page alloc/put takes too long and effects small
0e15df49
BA		 1275 * packet throughput, so unsplit small packets and
1276 * save the alloc/put only valid in softirq (napi)
1277 * context to call kmap_*
ad68076e 1278 */
0e15df49
BA		 1279 if (l1 && (l1 <= copybreak) &&
1280 ((length + l1) <= adapter->rx_ps_bsize0)) {
1281 u8 *vaddr;
1282
1283 ps_page = &buffer_info->ps_pages[0];
1284
e921eb1a 1285 /* there is no documentation about how to call
0e15df49
BA		 1286 * kmap_atomic, so we can't hold the mapping
1287 * very long
1288 */
1289 dma_sync_single_for_cpu(&pdev->dev,
1290 ps_page->dma,
1291 PAGE_SIZE,
1292 DMA_FROM_DEVICE);
9f393834 1293 vaddr = kmap_atomic(ps_page->page);
0e15df49 1294 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1295 kunmap_atomic(vaddr);
0e15df49
BA		 1296 dma_sync_single_for_device(&pdev->dev,
1297 ps_page->dma,
1298 PAGE_SIZE,
1299 DMA_FROM_DEVICE);
1300
1301 /* remove the CRC */
0184039a
BG		 1302 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1303 if (!(netdev->features & NETIF_F_RXFCS))
1304 l1 -= 4;
1305 }
0e15df49
BA		 1306
1307 skb_put(skb, l1);
1308 goto copydone;
1309 } /* if */
bc7f75fa
AK		 1310 }
1311
1312 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1313 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1314 if (!length)
1315 break;
1316
47f44e40 1317 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1318 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1319 DMA_FROM_DEVICE);
bc7f75fa
AK		 1320 ps_page->dma = 0;
1321 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1322 ps_page->page = NULL;
1323 skb->len += length;
1324 skb->data_len += length;
98a045d7 1325 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1326 }
1327
eb7c3adb
JK		 1328 /* strip the ethernet crc, problem is we're using pages now so
1329 * this whole operation can get a little cpu intensive
1330 */
0184039a
BG		 1331 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1332 if (!(netdev->features & NETIF_F_RXFCS))
1333 pskb_trim(skb, skb->len - 4);
1334 }
eb7c3adb 1335
bc7f75fa
AK		 1336copydone:
1337 total_rx_bytes += skb->len;
1338 total_rx_packets++;
1339
2e1706f2 1340 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1341
70495a50
BA		 1342 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1343
bc7f75fa
AK		 1344 if (rx_desc->wb.upper.header_status &
1345 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1346 adapter->rx_hdr_split++;
1347
1348 e1000_receive_skb(adapter, netdev, skb,
1349 staterr, rx_desc->wb.middle.vlan);
1350
1351next_desc:
1352 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1353 buffer_info->skb = NULL;
1354
1355 /* return some buffers to hardware, one at a time is too slow */
1356 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1357 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1358 GFP_ATOMIC);
bc7f75fa
AK		 1359 cleaned_count = 0;
1360 }
1361
1362 /* use prefetched values */
1363 rx_desc = next_rxd;
1364 buffer_info = next_buffer;
1365
1366 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1367 }
1368 rx_ring->next_to_clean = i;
1369
1370 cleaned_count = e1000_desc_unused(rx_ring);
1371 if (cleaned_count)
55aa6985 1372 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1373
bc7f75fa 1374 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1375 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1376 return cleaned;
1377}
1378
97ac8cae
BA		 1379/**
1380 * e1000_consume_page - helper function
1381 **/
1382static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1383 u16 length)
1384{
1385 bi->page = NULL;
1386 skb->len += length;
1387 skb->data_len += length;
98a045d7 1388 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1389}
1390
1391/**
1392 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1393 * @adapter: board private structure
1394 *
1395 * the return value indicates whether actual cleaning was done, there
1396 * is no guarantee that everything was cleaned
1397 **/
55aa6985
BA		 1398static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1399 int work_to_do)
97ac8cae 1400{
55aa6985 1401 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1402 struct net_device *netdev = adapter->netdev;
1403 struct pci_dev *pdev = adapter->pdev;
5f450212 1404 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1405 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1406 u32 length, staterr;
97ac8cae
BA		 1407 unsigned int i;
1408 int cleaned_count = 0;
1409 bool cleaned = false;
1410 unsigned int total_rx_bytes=0, total_rx_packets=0;
1411
1412 i = rx_ring->next_to_clean;
5f450212
BA		 1413 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1414 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1415 buffer_info = &rx_ring->buffer_info[i];
1416
5f450212 1417 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1418 struct sk_buff *skb;
97ac8cae
BA		 1419
1420 if (*work_done >= work_to_do)
1421 break;
1422 (*work_done)++;
2d0bb1c1 1423 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1424
97ac8cae
BA		 1425 skb = buffer_info->skb;
1426 buffer_info->skb = NULL;
1427
1428 ++i;
1429 if (i == rx_ring->count)
1430 i = 0;
5f450212 1431 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1432 prefetch(next_rxd);
1433
1434 next_buffer = &rx_ring->buffer_info[i];
1435
1436 cleaned = true;
1437 cleaned_count++;
0be3f55f
NN		 1438 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1439 DMA_FROM_DEVICE);
97ac8cae
BA		 1440 buffer_info->dma = 0;
1441
5f450212 1442 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1443
1444 /* errors is only valid for DD + EOP descriptors */
5f450212 1445 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1446 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1447 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1448 /* recycle both page and skb */
1449 buffer_info->skb = skb;
1450 /* an error means any chain goes out the window too */
1451 if (rx_ring->rx_skb_top)
1452 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1453 rx_ring->rx_skb_top = NULL;
1454 goto next_desc;
97ac8cae
BA		 1455 }
1456
f0f1a172 1457#define rxtop (rx_ring->rx_skb_top)
5f450212 1458 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1459 /* this descriptor is only the beginning (or middle) */
1460 if (!rxtop) {
1461 /* this is the beginning of a chain */
1462 rxtop = skb;
1463 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1464 0, length);
1465 } else {
1466 /* this is the middle of a chain */
1467 skb_fill_page_desc(rxtop,
1468 skb_shinfo(rxtop)->nr_frags,
1469 buffer_info->page, 0, length);
1470 /* re-use the skb, only consumed the page */
1471 buffer_info->skb = skb;
1472 }
1473 e1000_consume_page(buffer_info, rxtop, length);
1474 goto next_desc;
1475 } else {
1476 if (rxtop) {
1477 /* end of the chain */
1478 skb_fill_page_desc(rxtop,
1479 skb_shinfo(rxtop)->nr_frags,
1480 buffer_info->page, 0, length);
1481 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1482 * page
1483 */
97ac8cae
BA		 1484 buffer_info->skb = skb;
1485 skb = rxtop;
1486 rxtop = NULL;
1487 e1000_consume_page(buffer_info, skb, length);
1488 } else {
1489 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1490 * copybreak to save the put_page/alloc_page
1491 */
97ac8cae
BA		 1492 if (length <= copybreak &&
1493 skb_tailroom(skb) >= length) {
1494 u8 *vaddr;
4679026d 1495 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1496 memcpy(skb_tail_pointer(skb), vaddr,
1497 length);
4679026d 1498 kunmap_atomic(vaddr);
97ac8cae 1499 /* re-use the page, so don't erase
e921eb1a
BA		 1500 * buffer_info->page
1501 */
97ac8cae
BA		 1502 skb_put(skb, length);
1503 } else {
1504 skb_fill_page_desc(skb, 0,
1505 buffer_info->page, 0,
1506 length);
1507 e1000_consume_page(buffer_info, skb,
1508 length);
1509 }
1510 }
1511 }
1512
2e1706f2
BA		 1513 /* Receive Checksum Offload */
1514 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1515
70495a50
BA		 1516 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1517
97ac8cae
BA		 1518 /* probably a little skewed due to removing CRC */
1519 total_rx_bytes += skb->len;
1520 total_rx_packets++;
1521
1522 /* eth type trans needs skb->data to point to something */
1523 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1524 e_err("pskb_may_pull failed.\n");
ef5ab89c 1525 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1526 goto next_desc;
1527 }
1528
5f450212
BA		 1529 e1000_receive_skb(adapter, netdev, skb, staterr,
1530 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1531
1532next_desc:
5f450212 1533 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1534
1535 /* return some buffers to hardware, one at a time is too slow */
1536 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1537 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1538 GFP_ATOMIC);
97ac8cae
BA		 1539 cleaned_count = 0;
1540 }
1541
1542 /* use prefetched values */
1543 rx_desc = next_rxd;
1544 buffer_info = next_buffer;
5f450212
BA		 1545
1546 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1547 }
1548 rx_ring->next_to_clean = i;
1549
1550 cleaned_count = e1000_desc_unused(rx_ring);
1551 if (cleaned_count)
55aa6985 1552 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1553
1554 adapter->total_rx_bytes += total_rx_bytes;
1555 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1556 return cleaned;
1557}
1558
bc7f75fa
AK		 1559/**
1560 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1561 * @rx_ring: Rx descriptor ring
bc7f75fa 1562 **/
55aa6985 1563static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1564{
55aa6985 1565 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1566 struct e1000_buffer *buffer_info;
1567 struct e1000_ps_page *ps_page;
1568 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1569 unsigned int i, j;
1570
1571 /* Free all the Rx ring sk_buffs */
1572 for (i = 0; i < rx_ring->count; i++) {
1573 buffer_info = &rx_ring->buffer_info[i];
1574 if (buffer_info->dma) {
1575 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1576 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1577 adapter->rx_buffer_len,
0be3f55f 1578 DMA_FROM_DEVICE);
97ac8cae 1579 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1580 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1581 PAGE_SIZE,
0be3f55f 1582 DMA_FROM_DEVICE);
bc7f75fa 1583 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1584 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1585 adapter->rx_ps_bsize0,
0be3f55f 1586 DMA_FROM_DEVICE);
bc7f75fa
AK		 1587 buffer_info->dma = 0;
1588 }
1589
97ac8cae
BA		 1590 if (buffer_info->page) {
1591 put_page(buffer_info->page);
1592 buffer_info->page = NULL;
1593 }
1594
bc7f75fa
AK		 1595 if (buffer_info->skb) {
1596 dev_kfree_skb(buffer_info->skb);
1597 buffer_info->skb = NULL;
1598 }
1599
1600 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1601 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1602 if (!ps_page->page)
1603 break;
0be3f55f
NN		 1604 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1605 DMA_FROM_DEVICE);
bc7f75fa
AK		 1606 ps_page->dma = 0;
1607 put_page(ps_page->page);
1608 ps_page->page = NULL;
1609 }
1610 }
1611
1612 /* there also may be some cached data from a chained receive */
1613 if (rx_ring->rx_skb_top) {
1614 dev_kfree_skb(rx_ring->rx_skb_top);
1615 rx_ring->rx_skb_top = NULL;
1616 }
1617
bc7f75fa
AK		 1618 /* Zero out the descriptor ring */
1619 memset(rx_ring->desc, 0, rx_ring->size);
1620
1621 rx_ring->next_to_clean = 0;
1622 rx_ring->next_to_use = 0;
b94b5028 1623 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1624
c5083cf6 1625 writel(0, rx_ring->head);
bdc125f7
BA		 1626 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1627 e1000e_update_rdt_wa(rx_ring, 0);
1628 else
1629 writel(0, rx_ring->tail);
bc7f75fa
AK		 1630}
1631
a8f88ff5
JB		 1632static void e1000e_downshift_workaround(struct work_struct *work)
1633{
1634 struct e1000_adapter *adapter = container_of(work,
1635 struct e1000_adapter, downshift_task);
1636
615b32af
JB		 1637 if (test_bit(__E1000_DOWN, &adapter->state))
1638 return;
1639
a8f88ff5
JB		 1640 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1641}
1642
bc7f75fa
AK		 1643/**
1644 * e1000_intr_msi - Interrupt Handler
1645 * @irq: interrupt number
1646 * @data: pointer to a network interface device structure
1647 **/
1648static irqreturn_t e1000_intr_msi(int irq, void *data)
1649{
1650 struct net_device *netdev = data;
1651 struct e1000_adapter *adapter = netdev_priv(netdev);
1652 struct e1000_hw *hw = &adapter->hw;
1653 u32 icr = er32(ICR);
1654
e921eb1a 1655 /* read ICR disables interrupts using IAM */
573cca8c 1656 if (icr & E1000_ICR_LSC) {
f92518dd 1657 hw->mac.get_link_status = true;
e921eb1a 1658 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1659 * disconnect (LSC) before accessing any PHY registers
1660 */
bc7f75fa
AK		 1661 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1662 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1663 schedule_work(&adapter->downshift_task);
bc7f75fa 1664
e921eb1a 1665 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1666 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1667 * adapter in watchdog
1668 */
bc7f75fa
AK		 1669 if (netif_carrier_ok(netdev) &&
1670 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1671 /* disable receives */
1672 u32 rctl = er32(RCTL);
1673 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1674 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1675 }
1676 /* guard against interrupt when we're going down */
1677 if (!test_bit(__E1000_DOWN, &adapter->state))
1678 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1679 }
1680
288379f0 1681 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1682 adapter->total_tx_bytes = 0;
1683 adapter->total_tx_packets = 0;
1684 adapter->total_rx_bytes = 0;
1685 adapter->total_rx_packets = 0;
288379f0 1686 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1687 }
1688
1689 return IRQ_HANDLED;
1690}
1691
1692/**
1693 * e1000_intr - Interrupt Handler
1694 * @irq: interrupt number
1695 * @data: pointer to a network interface device structure
1696 **/
1697static irqreturn_t e1000_intr(int irq, void *data)
1698{
1699 struct net_device *netdev = data;
1700 struct e1000_adapter *adapter = netdev_priv(netdev);
1701 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1702 u32 rctl, icr = er32(ICR);
4662e82b 1703
a68ea775 1704 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1705 return IRQ_NONE; /* Not our interrupt */
1706
e921eb1a 1707 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1708 * not set, then the adapter didn't send an interrupt
1709 */
bc7f75fa
AK		 1710 if (!(icr & E1000_ICR_INT_ASSERTED))
1711 return IRQ_NONE;
1712
e921eb1a 1713 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1714 * interrupts are masked. No need for the
1715 * IMC write
1716 */
bc7f75fa 1717
573cca8c 1718 if (icr & E1000_ICR_LSC) {
f92518dd 1719 hw->mac.get_link_status = true;
e921eb1a 1720 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1721 * disconnect (LSC) before accessing any PHY registers
1722 */
bc7f75fa
AK		 1723 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1724 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1725 schedule_work(&adapter->downshift_task);
bc7f75fa 1726
e921eb1a 1727 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1728 * For packet buffer work-around on link down event;
1729 * disable receives here in the ISR and
1730 * reset adapter in watchdog
1731 */
1732 if (netif_carrier_ok(netdev) &&
1733 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1734 /* disable receives */
1735 rctl = er32(RCTL);
1736 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1737 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1738 }
1739 /* guard against interrupt when we're going down */
1740 if (!test_bit(__E1000_DOWN, &adapter->state))
1741 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1742 }
1743
288379f0 1744 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1745 adapter->total_tx_bytes = 0;
1746 adapter->total_tx_packets = 0;
1747 adapter->total_rx_bytes = 0;
1748 adapter->total_rx_packets = 0;
288379f0 1749 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1750 }
1751
1752 return IRQ_HANDLED;
1753}
1754
4662e82b
BA		 1755static irqreturn_t e1000_msix_other(int irq, void *data)
1756{
1757 struct net_device *netdev = data;
1758 struct e1000_adapter *adapter = netdev_priv(netdev);
1759 struct e1000_hw *hw = &adapter->hw;
1760 u32 icr = er32(ICR);
1761
1762 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1763 if (!test_bit(__E1000_DOWN, &adapter->state))
1764 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1765 return IRQ_NONE;
1766 }
1767
1768 if (icr & adapter->eiac_mask)
1769 ew32(ICS, (icr & adapter->eiac_mask));
1770
1771 if (icr & E1000_ICR_OTHER) {
1772 if (!(icr & E1000_ICR_LSC))
1773 goto no_link_interrupt;
f92518dd 1774 hw->mac.get_link_status = true;
4662e82b
BA		 1775 /* guard against interrupt when we're going down */
1776 if (!test_bit(__E1000_DOWN, &adapter->state))
1777 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1778 }
1779
1780no_link_interrupt:
a3c69fef
JB		 1781 if (!test_bit(__E1000_DOWN, &adapter->state))
1782 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1783
1784 return IRQ_HANDLED;
1785}
1786
1787
1788static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1789{
1790 struct net_device *netdev = data;
1791 struct e1000_adapter *adapter = netdev_priv(netdev);
1792 struct e1000_hw *hw = &adapter->hw;
1793 struct e1000_ring *tx_ring = adapter->tx_ring;
1794
1795
1796 adapter->total_tx_bytes = 0;
1797 adapter->total_tx_packets = 0;
1798
55aa6985 1799 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1800 /* Ring was not completely cleaned, so fire another interrupt */
1801 ew32(ICS, tx_ring->ims_val);
1802
1803 return IRQ_HANDLED;
1804}
1805
1806static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1807{
1808 struct net_device *netdev = data;
1809 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1810 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1811
1812 /* Write the ITR value calculated at the end of the
1813 * previous interrupt.
1814 */
55aa6985
BA		 1815 if (rx_ring->set_itr) {
1816 writel(1000000000 / (rx_ring->itr_val * 256),
1817 rx_ring->itr_register);
1818 rx_ring->set_itr = 0;
4662e82b
BA		 1819 }
1820
288379f0 1821 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1822 adapter->total_rx_bytes = 0;
1823 adapter->total_rx_packets = 0;
288379f0 1824 __napi_schedule(&adapter->napi);
4662e82b
BA		 1825 }
1826 return IRQ_HANDLED;
1827}
1828
1829/**
1830 * e1000_configure_msix - Configure MSI-X hardware
1831 *
1832 * e1000_configure_msix sets up the hardware to properly
1833 * generate MSI-X interrupts.
1834 **/
1835static void e1000_configure_msix(struct e1000_adapter *adapter)
1836{
1837 struct e1000_hw *hw = &adapter->hw;
1838 struct e1000_ring *rx_ring = adapter->rx_ring;
1839 struct e1000_ring *tx_ring = adapter->tx_ring;
1840 int vector = 0;
1841 u32 ctrl_ext, ivar = 0;
1842
1843 adapter->eiac_mask = 0;
1844
1845 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1846 if (hw->mac.type == e1000_82574) {
1847 u32 rfctl = er32(RFCTL);
1848 rfctl |= E1000_RFCTL_ACK_DIS;
1849 ew32(RFCTL, rfctl);
1850 }
1851
1852#define E1000_IVAR_INT_ALLOC_VALID 0x8
1853 /* Configure Rx vector */
1854 rx_ring->ims_val = E1000_IMS_RXQ0;
1855 adapter->eiac_mask |= rx_ring->ims_val;
1856 if (rx_ring->itr_val)
1857 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1858 rx_ring->itr_register);
4662e82b 1859 else
c5083cf6 1860 writel(1, rx_ring->itr_register);
4662e82b
BA		 1861 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1862
1863 /* Configure Tx vector */
1864 tx_ring->ims_val = E1000_IMS_TXQ0;
1865 vector++;
1866 if (tx_ring->itr_val)
1867 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1868 tx_ring->itr_register);
4662e82b 1869 else
c5083cf6 1870 writel(1, tx_ring->itr_register);
4662e82b
BA		 1871 adapter->eiac_mask |= tx_ring->ims_val;
1872 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1873
1874 /* set vector for Other Causes, e.g. link changes */
1875 vector++;
1876 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1877 if (rx_ring->itr_val)
1878 writel(1000000000 / (rx_ring->itr_val * 256),
1879 hw->hw_addr + E1000_EITR_82574(vector));
1880 else
1881 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1882
1883 /* Cause Tx interrupts on every write back */
1884 ivar |= (1 << 31);
1885
1886 ew32(IVAR, ivar);
1887
1888 /* enable MSI-X PBA support */
1889 ctrl_ext = er32(CTRL_EXT);
1890 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1891
1892 /* Auto-Mask Other interrupts upon ICR read */
1893#define E1000_EIAC_MASK_82574 0x01F00000
1894 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1895 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1896 ew32(CTRL_EXT, ctrl_ext);
1897 e1e_flush();
1898}
1899
1900void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1901{
1902 if (adapter->msix_entries) {
1903 pci_disable_msix(adapter->pdev);
1904 kfree(adapter->msix_entries);
1905 adapter->msix_entries = NULL;
1906 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1907 pci_disable_msi(adapter->pdev);
1908 adapter->flags &= ~FLAG_MSI_ENABLED;
1909 }
4662e82b
BA		 1910}
1911
1912/**
1913 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1914 *
1915 * Attempt to configure interrupts using the best available
1916 * capabilities of the hardware and kernel.
1917 **/
1918void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1919{
1920 int err;
8e86acd7 1921 int i;
4662e82b
BA		 1922
1923 switch (adapter->int_mode) {
1924 case E1000E_INT_MODE_MSIX:
1925 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1926 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1927 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1928 sizeof(struct msix_entry),
1929 GFP_KERNEL);
1930 if (adapter->msix_entries) {
8e86acd7 1931 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1932 adapter->msix_entries[i].entry = i;
1933
1934 err = pci_enable_msix(adapter->pdev,
1935 adapter->msix_entries,
8e86acd7 1936 adapter->num_vectors);
b1cdfead 1937 if (err == 0)
4662e82b
BA		 1938 return;
1939 }
1940 /* MSI-X failed, so fall through and try MSI */
ef456f85 1941 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1942 e1000e_reset_interrupt_capability(adapter);
1943 }
1944 adapter->int_mode = E1000E_INT_MODE_MSI;
1945 /* Fall through */
1946 case E1000E_INT_MODE_MSI:
1947 if (!pci_enable_msi(adapter->pdev)) {
1948 adapter->flags |= FLAG_MSI_ENABLED;
1949 } else {
1950 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1951 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1952 }
1953 /* Fall through */
1954 case E1000E_INT_MODE_LEGACY:
1955 /* Don't do anything; this is the system default */
1956 break;
1957 }
8e86acd7
JK		 1958
1959 /* store the number of vectors being used */
1960 adapter->num_vectors = 1;
4662e82b
BA		 1961}
1962
1963/**
1964 * e1000_request_msix - Initialize MSI-X interrupts
1965 *
1966 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1967 * kernel.
1968 **/
1969static int e1000_request_msix(struct e1000_adapter *adapter)
1970{
1971 struct net_device *netdev = adapter->netdev;
1972 int err = 0, vector = 0;
1973
1974 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1975 snprintf(adapter->rx_ring->name,
1976 sizeof(adapter->rx_ring->name) - 1,
1977 "%s-rx-0", netdev->name);
4662e82b
BA		 1978 else
1979 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1980 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1981 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1982 netdev);
1983 if (err)
5015e53a 1984 return err;
c5083cf6
BA		 1985 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
1986 E1000_EITR_82574(vector);
4662e82b
BA		 1987 adapter->rx_ring->itr_val = adapter->itr;
1988 vector++;
1989
1990 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1991 snprintf(adapter->tx_ring->name,
1992 sizeof(adapter->tx_ring->name) - 1,
1993 "%s-tx-0", netdev->name);
4662e82b
BA		 1994 else
1995 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1996 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1997 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1998 netdev);
1999 if (err)
5015e53a 2000 return err;
c5083cf6
BA		 2001 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2002 E1000_EITR_82574(vector);
4662e82b
BA		 2003 adapter->tx_ring->itr_val = adapter->itr;
2004 vector++;
2005
2006 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2007 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2008 if (err)
5015e53a 2009 return err;
4662e82b
BA		 2010
2011 e1000_configure_msix(adapter);
5015e53a 2012
4662e82b 2013 return 0;
4662e82b
BA		 2014}
2015
f8d59f78
BA		 2016/**
2017 * e1000_request_irq - initialize interrupts
2018 *
2019 * Attempts to configure interrupts using the best available
2020 * capabilities of the hardware and kernel.
2021 **/
bc7f75fa
AK		 2022static int e1000_request_irq(struct e1000_adapter *adapter)
2023{
2024 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2025 int err;
2026
4662e82b
BA		 2027 if (adapter->msix_entries) {
2028 err = e1000_request_msix(adapter);
2029 if (!err)
2030 return err;
2031 /* fall back to MSI */
2032 e1000e_reset_interrupt_capability(adapter);
2033 adapter->int_mode = E1000E_INT_MODE_MSI;
2034 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2035 }
4662e82b 2036 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2037 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2038 netdev->name, netdev);
2039 if (!err)
2040 return err;
bc7f75fa 2041
4662e82b
BA		 2042 /* fall back to legacy interrupt */
2043 e1000e_reset_interrupt_capability(adapter);
2044 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2045 }
2046
a0607fd3 2047 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2048 netdev->name, netdev);
2049 if (err)
2050 e_err("Unable to allocate interrupt, Error: %d\n", err);
2051
bc7f75fa
AK		 2052 return err;
2053}
2054
2055static void e1000_free_irq(struct e1000_adapter *adapter)
2056{
2057 struct net_device *netdev = adapter->netdev;
2058
4662e82b
BA		 2059 if (adapter->msix_entries) {
2060 int vector = 0;
2061
2062 free_irq(adapter->msix_entries[vector].vector, netdev);
2063 vector++;
2064
2065 free_irq(adapter->msix_entries[vector].vector, netdev);
2066 vector++;
2067
2068 /* Other Causes interrupt vector */
2069 free_irq(adapter->msix_entries[vector].vector, netdev);
2070 return;
bc7f75fa 2071 }
4662e82b
BA		 2072
2073 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2074}
2075
2076/**
2077 * e1000_irq_disable - Mask off interrupt generation on the NIC
2078 **/
2079static void e1000_irq_disable(struct e1000_adapter *adapter)
2080{
2081 struct e1000_hw *hw = &adapter->hw;
2082
bc7f75fa 2083 ew32(IMC, ~0);
4662e82b
BA		 2084 if (adapter->msix_entries)
2085 ew32(EIAC_82574, 0);
bc7f75fa 2086 e1e_flush();
8e86acd7
JK		 2087
2088 if (adapter->msix_entries) {
2089 int i;
2090 for (i = 0; i < adapter->num_vectors; i++)
2091 synchronize_irq(adapter->msix_entries[i].vector);
2092 } else {
2093 synchronize_irq(adapter->pdev->irq);
2094 }
bc7f75fa
AK		 2095}
2096
2097/**
2098 * e1000_irq_enable - Enable default interrupt generation settings
2099 **/
2100static void e1000_irq_enable(struct e1000_adapter *adapter)
2101{
2102 struct e1000_hw *hw = &adapter->hw;
2103
4662e82b
BA		 2104 if (adapter->msix_entries) {
2105 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2106 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2107 } else {
2108 ew32(IMS, IMS_ENABLE_MASK);
2109 }
74ef9c39 2110 e1e_flush();
bc7f75fa
AK		 2111}
2112
2113/**
31dbe5b4 2114 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2115 * @adapter: address of board private structure
2116 *
31dbe5b4 2117 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2118 * For ASF and Pass Through versions of f/w this means that
2119 * the driver is loaded. For AMT version (only with 82573)
2120 * of the f/w this means that the network i/f is open.
2121 **/
31dbe5b4 2122void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2123{
2124 struct e1000_hw *hw = &adapter->hw;
2125 u32 ctrl_ext;
2126 u32 swsm;
2127
2128 /* Let firmware know the driver has taken over */
2129 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2130 swsm = er32(SWSM);
2131 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2132 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2133 ctrl_ext = er32(CTRL_EXT);
ad68076e 2134 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2135 }
2136}
2137
2138/**
31dbe5b4 2139 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2140 * @adapter: address of board private structure
2141 *
31dbe5b4 2142 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2143 * For ASF and Pass Through versions of f/w this means that the
2144 * driver is no longer loaded. For AMT version (only with 82573) i
2145 * of the f/w this means that the network i/f is closed.
2146 *
2147 **/
31dbe5b4 2148void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2149{
2150 struct e1000_hw *hw = &adapter->hw;
2151 u32 ctrl_ext;
2152 u32 swsm;
2153
2154 /* Let firmware taken over control of h/w */
2155 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2156 swsm = er32(SWSM);
2157 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2158 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2159 ctrl_ext = er32(CTRL_EXT);
ad68076e 2160 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2161 }
2162}
2163
bc7f75fa 2164/**
49ce9c2c 2165 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2166 **/
2167static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2168 struct e1000_ring *ring)
2169{
2170 struct pci_dev *pdev = adapter->pdev;
2171
2172 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2173 GFP_KERNEL);
2174 if (!ring->desc)
2175 return -ENOMEM;
2176
2177 return 0;
2178}
2179
2180/**
2181 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2182 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2183 *
2184 * Return 0 on success, negative on failure
2185 **/
55aa6985 2186int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2187{
55aa6985 2188 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2189 int err = -ENOMEM, size;
2190
2191 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2192 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2193 if (!tx_ring->buffer_info)
2194 goto err;
bc7f75fa
AK		 2195
2196 /* round up to nearest 4K */
2197 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2198 tx_ring->size = ALIGN(tx_ring->size, 4096);
2199
2200 err = e1000_alloc_ring_dma(adapter, tx_ring);
2201 if (err)
2202 goto err;
2203
2204 tx_ring->next_to_use = 0;
2205 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2206
2207 return 0;
2208err:
2209 vfree(tx_ring->buffer_info);
44defeb3 2210 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2211 return err;
2212}
2213
2214/**
2215 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2216 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2217 *
2218 * Returns 0 on success, negative on failure
2219 **/
55aa6985 2220int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2221{
55aa6985 2222 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2223 struct e1000_buffer *buffer_info;
2224 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2225
2226 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2227 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2228 if (!rx_ring->buffer_info)
2229 goto err;
bc7f75fa 2230
47f44e40
AK		 2231 for (i = 0; i < rx_ring->count; i++) {
2232 buffer_info = &rx_ring->buffer_info[i];
2233 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2234 sizeof(struct e1000_ps_page),
2235 GFP_KERNEL);
2236 if (!buffer_info->ps_pages)
2237 goto err_pages;
2238 }
bc7f75fa
AK		 2239
2240 desc_len = sizeof(union e1000_rx_desc_packet_split);
2241
2242 /* Round up to nearest 4K */
2243 rx_ring->size = rx_ring->count * desc_len;
2244 rx_ring->size = ALIGN(rx_ring->size, 4096);
2245
2246 err = e1000_alloc_ring_dma(adapter, rx_ring);
2247 if (err)
47f44e40 2248 goto err_pages;
bc7f75fa
AK		 2249
2250 rx_ring->next_to_clean = 0;
2251 rx_ring->next_to_use = 0;
2252 rx_ring->rx_skb_top = NULL;
2253
2254 return 0;
47f44e40
AK		 2255
2256err_pages:
2257 for (i = 0; i < rx_ring->count; i++) {
2258 buffer_info = &rx_ring->buffer_info[i];
2259 kfree(buffer_info->ps_pages);
2260 }
bc7f75fa
AK		 2261err:
2262 vfree(rx_ring->buffer_info);
e9262447 2263 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2264 return err;
2265}
2266
2267/**
2268 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2269 * @tx_ring: Tx descriptor ring
bc7f75fa 2270 **/
55aa6985 2271static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2272{
55aa6985 2273 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2274 struct e1000_buffer *buffer_info;
2275 unsigned long size;
2276 unsigned int i;
2277
2278 for (i = 0; i < tx_ring->count; i++) {
2279 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2280 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2281 }
2282
3f0cfa3b 2283 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2284 size = sizeof(struct e1000_buffer) * tx_ring->count;
2285 memset(tx_ring->buffer_info, 0, size);
2286
2287 memset(tx_ring->desc, 0, tx_ring->size);
2288
2289 tx_ring->next_to_use = 0;
2290 tx_ring->next_to_clean = 0;
2291
c5083cf6 2292 writel(0, tx_ring->head);
bdc125f7
BA		 2293 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2294 e1000e_update_tdt_wa(tx_ring, 0);
2295 else
2296 writel(0, tx_ring->tail);
bc7f75fa
AK		 2297}
2298
2299/**
2300 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2301 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2302 *
2303 * Free all transmit software resources
2304 **/
55aa6985 2305void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2306{
55aa6985 2307 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2308 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2309
55aa6985 2310 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2311
2312 vfree(tx_ring->buffer_info);
2313 tx_ring->buffer_info = NULL;
2314
2315 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2316 tx_ring->dma);
2317 tx_ring->desc = NULL;
2318}
2319
2320/**
2321 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2322 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2323 *
2324 * Free all receive software resources
2325 **/
55aa6985 2326void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2327{
55aa6985 2328 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2329 struct pci_dev *pdev = adapter->pdev;
47f44e40 2330 int i;
bc7f75fa 2331
55aa6985 2332 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2333
b1cdfead 2334 for (i = 0; i < rx_ring->count; i++)
47f44e40 2335 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2336
bc7f75fa
AK		 2337 vfree(rx_ring->buffer_info);
2338 rx_ring->buffer_info = NULL;
2339
bc7f75fa
AK		 2340 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2341 rx_ring->dma);
2342 rx_ring->desc = NULL;
2343}
2344
2345/**
2346 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2347 * @adapter: pointer to adapter
2348 * @itr_setting: current adapter->itr
2349 * @packets: the number of packets during this measurement interval
2350 * @bytes: the number of bytes during this measurement interval
2351 *
bc7f75fa
AK		 2352 * Stores a new ITR value based on packets and byte
2353 * counts during the last interrupt. The advantage of per interrupt
2354 * computation is faster updates and more accurate ITR for the current
2355 * traffic pattern. Constants in this function were computed
2356 * based on theoretical maximum wire speed and thresholds were set based
2357 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2358 * while increasing bulk throughput. This functionality is controlled
2359 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2360 **/
2361static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2362 u16 itr_setting, int packets,
2363 int bytes)
2364{
2365 unsigned int retval = itr_setting;
2366
2367 if (packets == 0)
5015e53a 2368 return itr_setting;
bc7f75fa
AK		 2369
2370 switch (itr_setting) {
2371 case lowest_latency:
2372 /* handle TSO and jumbo frames */
2373 if (bytes/packets > 8000)
2374 retval = bulk_latency;
b1cdfead 2375 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2376 retval = low_latency;
bc7f75fa
AK		 2377 break;
2378 case low_latency: /* 50 usec aka 20000 ints/s */
2379 if (bytes > 10000) {
2380 /* this if handles the TSO accounting */
b1cdfead 2381 if (bytes/packets > 8000)
bc7f75fa 2382 retval = bulk_latency;
b1cdfead 2383 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2384 retval = bulk_latency;
b1cdfead 2385 else if ((packets > 35))
bc7f75fa 2386 retval = lowest_latency;
bc7f75fa
AK		 2387 } else if (bytes/packets > 2000) {
2388 retval = bulk_latency;
2389 } else if (packets <= 2 && bytes < 512) {
2390 retval = lowest_latency;
2391 }
2392 break;
2393 case bulk_latency: /* 250 usec aka 4000 ints/s */
2394 if (bytes > 25000) {
b1cdfead 2395 if (packets > 35)
bc7f75fa 2396 retval = low_latency;
bc7f75fa
AK		 2397 } else if (bytes < 6000) {
2398 retval = low_latency;
2399 }
2400 break;
2401 }
2402
bc7f75fa
AK		 2403 return retval;
2404}
2405
2406static void e1000_set_itr(struct e1000_adapter *adapter)
2407{
bc7f75fa
AK		 2408 u16 current_itr;
2409 u32 new_itr = adapter->itr;
2410
2411 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2412 if (adapter->link_speed != SPEED_1000) {
2413 current_itr = 0;
2414 new_itr = 4000;
2415 goto set_itr_now;
2416 }
2417
828bac87
BA		 2418 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2419 new_itr = 0;
2420 goto set_itr_now;
2421 }
2422
bc7f75fa
AK		 2423 adapter->tx_itr = e1000_update_itr(adapter,
2424 adapter->tx_itr,
2425 adapter->total_tx_packets,
2426 adapter->total_tx_bytes);
2427 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2428 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2429 adapter->tx_itr = low_latency;
2430
2431 adapter->rx_itr = e1000_update_itr(adapter,
2432 adapter->rx_itr,
2433 adapter->total_rx_packets,
2434 adapter->total_rx_bytes);
2435 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2436 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2437 adapter->rx_itr = low_latency;
2438
2439 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2440
2441 switch (current_itr) {
2442 /* counts and packets in update_itr are dependent on these numbers */
2443 case lowest_latency:
2444 new_itr = 70000;
2445 break;
2446 case low_latency:
2447 new_itr = 20000; /* aka hwitr = ~200 */
2448 break;
2449 case bulk_latency:
2450 new_itr = 4000;
2451 break;
2452 default:
2453 break;
2454 }
2455
2456set_itr_now:
2457 if (new_itr != adapter->itr) {
e921eb1a 2458 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2459 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2460 * increasing
2461 */
bc7f75fa
AK		 2462 new_itr = new_itr > adapter->itr ?
2463 min(adapter->itr + (new_itr >> 2), new_itr) :
2464 new_itr;
2465 adapter->itr = new_itr;
4662e82b
BA		 2466 adapter->rx_ring->itr_val = new_itr;
2467 if (adapter->msix_entries)
2468 adapter->rx_ring->set_itr = 1;
2469 else
e3d14b08 2470 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2471 }
2472}
2473
22a4cca2
MV		 2474/**
2475 * e1000e_write_itr - write the ITR value to the appropriate registers
2476 * @adapter: address of board private structure
2477 * @itr: new ITR value to program
2478 *
2479 * e1000e_write_itr determines if the adapter is in MSI-X mode
2480 * and, if so, writes the EITR registers with the ITR value.
2481 * Otherwise, it writes the ITR value into the ITR register.
2482 **/
2483void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2484{
2485 struct e1000_hw *hw = &adapter->hw;
2486 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2487
2488 if (adapter->msix_entries) {
2489 int vector;
2490
2491 for (vector = 0; vector < adapter->num_vectors; vector++)
2492 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2493 } else {
2494 ew32(ITR, new_itr);
2495 }
2496}
2497
4662e82b
BA		 2498/**
2499 * e1000_alloc_queues - Allocate memory for all rings
2500 * @adapter: board private structure to initialize
2501 **/
9f9a12f8 2502static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2503{
55aa6985
BA		 2504 int size = sizeof(struct e1000_ring);
2505
2506 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2507 if (!adapter->tx_ring)
2508 goto err;
55aa6985
BA		 2509 adapter->tx_ring->count = adapter->tx_ring_count;
2510 adapter->tx_ring->adapter = adapter;
4662e82b 2511
55aa6985 2512 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2513 if (!adapter->rx_ring)
2514 goto err;
55aa6985
BA		 2515 adapter->rx_ring->count = adapter->rx_ring_count;
2516 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2517
2518 return 0;
2519err:
2520 e_err("Unable to allocate memory for queues\n");
2521 kfree(adapter->rx_ring);
2522 kfree(adapter->tx_ring);
2523 return -ENOMEM;
2524}
2525
bc7f75fa 2526/**
c58c8a78 2527 * e1000e_poll - NAPI Rx polling callback
ad68076e 2528 * @napi: struct associated with this polling callback
c58c8a78 2529 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2530 **/
c58c8a78 2531static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2532{
c58c8a78
BA		 2533 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2534 napi);
4662e82b 2535 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2536 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2537 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2538
4cf1653a 2539 adapter = netdev_priv(poll_dev);
bc7f75fa 2540
c58c8a78
BA		 2541 if (!adapter->msix_entries ||
2542 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2543 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2544
c58c8a78 2545 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2546
12d04a3c 2547 if (!tx_cleaned)
c58c8a78 2548 work_done = weight;
bc7f75fa 2549
c58c8a78
BA		 2550 /* If weight not fully consumed, exit the polling mode */
2551 if (work_done < weight) {
bc7f75fa
AK		 2552 if (adapter->itr_setting & 3)
2553 e1000_set_itr(adapter);
288379f0 2554 napi_complete(napi);
a3c69fef
JB		 2555 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2556 if (adapter->msix_entries)
2557 ew32(IMS, adapter->rx_ring->ims_val);
2558 else
2559 e1000_irq_enable(adapter);
2560 }
bc7f75fa
AK		 2561 }
2562
2563 return work_done;
2564}
2565
8e586137 2566static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2567{
2568 struct e1000_adapter *adapter = netdev_priv(netdev);
2569 struct e1000_hw *hw = &adapter->hw;
2570 u32 vfta, index;
2571
2572 /* don't update vlan cookie if already programmed */
2573 if ((adapter->hw.mng_cookie.status &
2574 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2575 (vid == adapter->mng_vlan_id))
8e586137 2576 return 0;
caaddaf8 2577
bc7f75fa 2578 /* add VID to filter table */
caaddaf8
BA		 2579 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2580 index = (vid >> 5) & 0x7F;
2581 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2582 vfta |= (1 << (vid & 0x1F));
2583 hw->mac.ops.write_vfta(hw, index, vfta);
2584 }
86d70e53
JK		 2585
2586 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2587
2588 return 0;
bc7f75fa
AK		 2589}
2590
8e586137 2591static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2592{
2593 struct e1000_adapter *adapter = netdev_priv(netdev);
2594 struct e1000_hw *hw = &adapter->hw;
2595 u32 vfta, index;
2596
bc7f75fa
AK		 2597 if ((adapter->hw.mng_cookie.status &
2598 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2599 (vid == adapter->mng_vlan_id)) {
2600 /* release control to f/w */
31dbe5b4 2601 e1000e_release_hw_control(adapter);
8e586137 2602 return 0;
bc7f75fa
AK		 2603 }
2604
2605 /* remove VID from filter table */
caaddaf8
BA		 2606 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2607 index = (vid >> 5) & 0x7F;
2608 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2609 vfta &= ~(1 << (vid & 0x1F));
2610 hw->mac.ops.write_vfta(hw, index, vfta);
2611 }
86d70e53
JK		 2612
2613 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2614
2615 return 0;
bc7f75fa
AK		 2616}
2617
86d70e53
JK		 2618/**
2619 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2620 * @adapter: board private structure to initialize
2621 **/
2622static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2623{
2624 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2625 struct e1000_hw *hw = &adapter->hw;
2626 u32 rctl;
bc7f75fa 2627
86d70e53
JK		 2628 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2629 /* disable VLAN receive filtering */
2630 rctl = er32(RCTL);
2631 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2632 ew32(RCTL, rctl);
2633
2634 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2635 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2636 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2637 }
bc7f75fa
AK		 2638 }
2639}
2640
86d70e53
JK		 2641/**
2642 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2643 * @adapter: board private structure to initialize
2644 **/
2645static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2646{
2647 struct e1000_hw *hw = &adapter->hw;
2648 u32 rctl;
2649
2650 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2651 /* enable VLAN receive filtering */
2652 rctl = er32(RCTL);
2653 rctl |= E1000_RCTL_VFE;
2654 rctl &= ~E1000_RCTL_CFIEN;
2655 ew32(RCTL, rctl);
2656 }
2657}
bc7f75fa 2658
86d70e53
JK		 2659/**
2660 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2661 * @adapter: board private structure to initialize
2662 **/
2663static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2664{
bc7f75fa 2665 struct e1000_hw *hw = &adapter->hw;
86d70e53 2666 u32 ctrl;
bc7f75fa 2667
86d70e53
JK		 2668 /* disable VLAN tag insert/strip */
2669 ctrl = er32(CTRL);
2670 ctrl &= ~E1000_CTRL_VME;
2671 ew32(CTRL, ctrl);
2672}
bc7f75fa 2673
86d70e53
JK		 2674/**
2675 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2676 * @adapter: board private structure to initialize
2677 **/
2678static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2679{
2680 struct e1000_hw *hw = &adapter->hw;
2681 u32 ctrl;
bc7f75fa 2682
86d70e53
JK		 2683 /* enable VLAN tag insert/strip */
2684 ctrl = er32(CTRL);
2685 ctrl |= E1000_CTRL_VME;
2686 ew32(CTRL, ctrl);
2687}
bc7f75fa 2688
86d70e53
JK		 2689static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2690{
2691 struct net_device *netdev = adapter->netdev;
2692 u16 vid = adapter->hw.mng_cookie.vlan_id;
2693 u16 old_vid = adapter->mng_vlan_id;
2694
2695 if (adapter->hw.mng_cookie.status &
2696 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2697 e1000_vlan_rx_add_vid(netdev, vid);
2698 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2699 }
2700
86d70e53
JK		 2701 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2702 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2703}
2704
2705static void e1000_restore_vlan(struct e1000_adapter *adapter)
2706{
2707 u16 vid;
2708
86d70e53 2709 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2710
86d70e53 2711 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2712 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2713}
2714
cd791618 2715static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2716{
2717 struct e1000_hw *hw = &adapter->hw;
cd791618 2718 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2719
2720 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2721 return;
2722
2723 manc = er32(MANC);
2724
e921eb1a 2725 /* enable receiving management packets to the host. this will probably
bc7f75fa 2726 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2727 * the packets will be handled on SMBUS
2728 */
bc7f75fa
AK		 2729 manc |= E1000_MANC_EN_MNG2HOST;
2730 manc2h = er32(MANC2H);
cd791618
BA		 2731
2732 switch (hw->mac.type) {
2733 default:
2734 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2735 break;
2736 case e1000_82574:
2737 case e1000_82583:
e921eb1a 2738 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2739 * if so, enable it.
2740 */
2741 for (i = 0, j = 0; i < 8; i++) {
2742 mdef = er32(MDEF(i));
2743
2744 /* Ignore filters with anything other than IPMI ports */
3b21b508 2745 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2746 continue;
2747
2748 /* Enable this decision filter in MANC2H */
2749 if (mdef)
2750 manc2h |= (1 << i);
2751
2752 j |= mdef;
2753 }
2754
2755 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2756 break;
2757
2758 /* Create new decision filter in an empty filter */
2759 for (i = 0, j = 0; i < 8; i++)
2760 if (er32(MDEF(i)) == 0) {
2761 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2762 E1000_MDEF_PORT_664));
2763 manc2h |= (1 << 1);
2764 j++;
2765 break;
2766 }
2767
2768 if (!j)
2769 e_warn("Unable to create IPMI pass-through filter\n");
2770 break;
2771 }
2772
bc7f75fa
AK		 2773 ew32(MANC2H, manc2h);
2774 ew32(MANC, manc);
2775}
2776
2777/**
af667a29 2778 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2779 * @adapter: board private structure
2780 *
2781 * Configure the Tx unit of the MAC after a reset.
2782 **/
2783static void e1000_configure_tx(struct e1000_adapter *adapter)
2784{
2785 struct e1000_hw *hw = &adapter->hw;
2786 struct e1000_ring *tx_ring = adapter->tx_ring;
2787 u64 tdba;
c550b121 2788 u32 tdlen, tarc;
bc7f75fa
AK		 2789
2790 /* Setup the HW Tx Head and Tail descriptor pointers */
2791 tdba = tx_ring->dma;
2792 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2793 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2794 ew32(TDBAH(0), (tdba >> 32));
2795 ew32(TDLEN(0), tdlen);
2796 ew32(TDH(0), 0);
2797 ew32(TDT(0), 0);
2798 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2799 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2800
bc7f75fa
AK		 2801 /* Set the Tx Interrupt Delay register */
2802 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2803 /* Tx irq moderation */
bc7f75fa
AK		 2804 ew32(TADV, adapter->tx_abs_int_delay);
2805
3a3b7586
JB		 2806 if (adapter->flags2 & FLAG2_DMA_BURST) {
2807 u32 txdctl = er32(TXDCTL(0));
2808 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2809 E1000_TXDCTL_WTHRESH);
e921eb1a 2810 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2811 * hardware to use the bus more efficiently in bursts, depends
2812 * on the tx_int_delay to be enabled,
8edc0e62 2813 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2814 * hthresh = 1 ==> prefetch when one or more available
2815 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2816 * BEWARE: this seems to work but should be considered first if
af667a29 2817 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2818 */
2819 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2820 ew32(TXDCTL(0), txdctl);
3a3b7586 2821 }
56032be7
BA		 2822 /* erratum work around: set txdctl the same for both queues */
2823 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2824
bc7f75fa 2825 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2826 tarc = er32(TARC(0));
e921eb1a 2827 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2828 * gigabit link later
2829 */
bc7f75fa
AK		 2830#define SPEED_MODE_BIT (1 << 21)
2831 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2832 ew32(TARC(0), tarc);
bc7f75fa
AK		 2833 }
2834
2835 /* errata: program both queues to unweighted RR */
2836 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2837 tarc = er32(TARC(0));
bc7f75fa 2838 tarc |= 1;
e9ec2c0f
JK		 2839 ew32(TARC(0), tarc);
2840 tarc = er32(TARC(1));
bc7f75fa 2841 tarc |= 1;
e9ec2c0f 2842 ew32(TARC(1), tarc);
bc7f75fa
AK		 2843 }
2844
bc7f75fa
AK		 2845 /* Setup Transmit Descriptor Settings for eop descriptor */
2846 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2847
2848 /* only set IDE if we are delaying interrupts using the timers */
2849 if (adapter->tx_int_delay)
2850 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2851
2852 /* enable Report Status bit */
2853 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2854
57cde763 2855 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2856}
2857
2858/**
2859 * e1000_setup_rctl - configure the receive control registers
2860 * @adapter: Board private structure
2861 **/
2862#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2863 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2864static void e1000_setup_rctl(struct e1000_adapter *adapter)
2865{
2866 struct e1000_hw *hw = &adapter->hw;
2867 u32 rctl, rfctl;
bc7f75fa
AK		 2868 u32 pages = 0;
2869
2fbe4526
BA		 2870 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2871 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2872 s32 ret_val;
2873
2874 if (adapter->netdev->mtu > ETH_DATA_LEN)
2875 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2876 else
2877 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2878
2879 if (ret_val)
2880 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2881 }
2882
bc7f75fa
AK		 2883 /* Program MC offset vector base */
2884 rctl = er32(RCTL);
2885 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2886 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2887 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2888 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2889
2890 /* Do not Store bad packets */
2891 rctl &= ~E1000_RCTL_SBP;
2892
2893 /* Enable Long Packet receive */
2894 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2895 rctl &= ~E1000_RCTL_LPE;
2896 else
2897 rctl |= E1000_RCTL_LPE;
2898
eb7c3adb
JK		 2899 /* Some systems expect that the CRC is included in SMBUS traffic. The
2900 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2901 * host memory when this is enabled
2902 */
2903 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2904 rctl |= E1000_RCTL_SECRC;
5918bd88 2905
a4f58f54
BA		 2906 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2907 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2908 u16 phy_data;
2909
2910 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2911 phy_data &= 0xfff8;
2912 phy_data |= (1 << 2);
2913 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2914
2915 e1e_rphy(hw, 22, &phy_data);
2916 phy_data &= 0x0fff;
2917 phy_data |= (1 << 14);
2918 e1e_wphy(hw, 0x10, 0x2823);
2919 e1e_wphy(hw, 0x11, 0x0003);
2920 e1e_wphy(hw, 22, phy_data);
2921 }
2922
bc7f75fa
AK		 2923 /* Setup buffer sizes */
2924 rctl &= ~E1000_RCTL_SZ_4096;
2925 rctl |= E1000_RCTL_BSEX;
2926 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2927 case 2048:
2928 default:
2929 rctl |= E1000_RCTL_SZ_2048;
2930 rctl &= ~E1000_RCTL_BSEX;
2931 break;
2932 case 4096:
2933 rctl |= E1000_RCTL_SZ_4096;
2934 break;
2935 case 8192:
2936 rctl |= E1000_RCTL_SZ_8192;
2937 break;
2938 case 16384:
2939 rctl |= E1000_RCTL_SZ_16384;
2940 break;
2941 }
2942
5f450212
BA		 2943 /* Enable Extended Status in all Receive Descriptors */
2944 rfctl = er32(RFCTL);
2945 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 2946 ew32(RFCTL, rfctl);
5f450212 2947
e921eb1a 2948 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 2949 * header is placed in skb->data and the packet data is
2950 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2951 * In the case of a non-split, skb->data is linearly filled,
2952 * followed by the page buffers. Therefore, skb->data is
2953 * sized to hold the largest protocol header.
2954 *
2955 * allocations using alloc_page take too long for regular MTU
2956 * so only enable packet split for jumbo frames
2957 *
2958 * Using pages when the page size is greater than 16k wastes
2959 * a lot of memory, since we allocate 3 pages at all times
2960 * per packet.
2961 */
bc7f75fa 2962 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2963 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2964 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2965 else
2966 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2967
2968 if (adapter->rx_ps_pages) {
90da0669
BA		 2969 u32 psrctl = 0;
2970
140a7480
AK		 2971 /* Enable Packet split descriptors */
2972 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2973
2974 psrctl |= adapter->rx_ps_bsize0 >>
2975 E1000_PSRCTL_BSIZE0_SHIFT;
2976
2977 switch (adapter->rx_ps_pages) {
2978 case 3:
2979 psrctl |= PAGE_SIZE <<
2980 E1000_PSRCTL_BSIZE3_SHIFT;
2981 case 2:
2982 psrctl |= PAGE_SIZE <<
2983 E1000_PSRCTL_BSIZE2_SHIFT;
2984 case 1:
2985 psrctl |= PAGE_SIZE >>
2986 E1000_PSRCTL_BSIZE1_SHIFT;
2987 break;
2988 }
2989
2990 ew32(PSRCTL, psrctl);
2991 }
2992
cf955e6c
BG		 2993 /* This is useful for sniffing bad packets. */
2994 if (adapter->netdev->features & NETIF_F_RXALL) {
2995 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 2996 * in e1000e_set_rx_mode
2997 */
cf955e6c
BG		 2998 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2999 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3000 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3001
3002 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3003 E1000_RCTL_DPF | /* Allow filtered pause */
3004 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3005 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3006 * and that breaks VLANs.
3007 */
3008 }
3009
bc7f75fa 3010 ew32(RCTL, rctl);
318a94d6 3011 /* just started the receive unit, no need to restart */
12d43f7d 3012 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3013}
3014
3015/**
3016 * e1000_configure_rx - Configure Receive Unit after Reset
3017 * @adapter: board private structure
3018 *
3019 * Configure the Rx unit of the MAC after a reset.
3020 **/
3021static void e1000_configure_rx(struct e1000_adapter *adapter)
3022{
3023 struct e1000_hw *hw = &adapter->hw;
3024 struct e1000_ring *rx_ring = adapter->rx_ring;
3025 u64 rdba;
3026 u32 rdlen, rctl, rxcsum, ctrl_ext;
3027
3028 if (adapter->rx_ps_pages) {
3029 /* this is a 32 byte descriptor */
3030 rdlen = rx_ring->count *
af667a29 3031 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3032 adapter->clean_rx = e1000_clean_rx_irq_ps;
3033 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3034 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3035 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3036 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3037 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3038 } else {
5f450212 3039 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3040 adapter->clean_rx = e1000_clean_rx_irq;
3041 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3042 }
3043
3044 /* disable receives while setting up the descriptors */
3045 rctl = er32(RCTL);
7f99ae63
BA		 3046 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3047 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3048 e1e_flush();
1bba4386 3049 usleep_range(10000, 20000);
bc7f75fa 3050
3a3b7586 3051 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3052 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3053 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3054 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3055 * granularity = 01
3056 * wthresh = 04,
3057 * hthresh = 04,
3058 * pthresh = 0x20
3059 */
3060 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3061 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3062
e921eb1a 3063 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3064 * the value was not set by the user via module options
3065 */
3066 if (adapter->rx_int_delay == DEFAULT_RDTR)
3067 adapter->rx_int_delay = BURST_RDTR;
3068 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3069 adapter->rx_abs_int_delay = BURST_RADV;
3070 }
3071
bc7f75fa
AK		 3072 /* set the Receive Delay Timer Register */
3073 ew32(RDTR, adapter->rx_int_delay);
3074
3075 /* irq moderation */
3076 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3077 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3078 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3079
3080 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3081 /* Auto-Mask interrupts upon ICR access */
3082 ctrl_ext |= E1000_CTRL_EXT_IAME;
3083 ew32(IAM, 0xffffffff);
3084 ew32(CTRL_EXT, ctrl_ext);
3085 e1e_flush();
3086
e921eb1a 3087 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3088 * the Base and Length of the Rx Descriptor Ring
3089 */
bc7f75fa 3090 rdba = rx_ring->dma;
1e36052e
BA		 3091 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3092 ew32(RDBAH(0), (rdba >> 32));
3093 ew32(RDLEN(0), rdlen);
3094 ew32(RDH(0), 0);
3095 ew32(RDT(0), 0);
3096 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3097 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3098
3099 /* Enable Receive Checksum Offload for TCP and UDP */
3100 rxcsum = er32(RXCSUM);
2e1706f2 3101 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3102 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3103 else
bc7f75fa 3104 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3105 ew32(RXCSUM, rxcsum);
3106
79d4e908 3107 if (adapter->hw.mac.type == e1000_pch2lan) {
e921eb1a 3108 /* With jumbo frames, excessive C-state transition
79d4e908
BA		 3109 * latencies result in dropped transactions.
3110 */
53ec5498
BA		 3111 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3112 u32 rxdctl = er32(RXDCTL(0));
3113 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3114 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3115 } else {
af667a29
BA		 3116 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3117 PM_QOS_DEFAULT_VALUE);
53ec5498 3118 }
97ac8cae 3119 }
bc7f75fa
AK		 3120
3121 /* Enable Receives */
3122 ew32(RCTL, rctl);
3123}
3124
3125/**
ef9b965a
JB		 3126 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3127 * @netdev: network interface device structure
bc7f75fa 3128 *
ef9b965a
JB		 3129 * Writes multicast address list to the MTA hash table.
3130 * Returns: -ENOMEM on failure
3131 * 0 on no addresses written
3132 * X on writing X addresses to MTA
3133 */
3134static int e1000e_write_mc_addr_list(struct net_device *netdev)
3135{
3136 struct e1000_adapter *adapter = netdev_priv(netdev);
3137 struct e1000_hw *hw = &adapter->hw;
3138 struct netdev_hw_addr *ha;
3139 u8 *mta_list;
3140 int i;
3141
3142 if (netdev_mc_empty(netdev)) {
3143 /* nothing to program, so clear mc list */
3144 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3145 return 0;
3146 }
3147
3148 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3149 if (!mta_list)
3150 return -ENOMEM;
3151
3152 /* update_mc_addr_list expects a packed array of only addresses. */
3153 i = 0;
3154 netdev_for_each_mc_addr(ha, netdev)
3155 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3156
3157 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3158 kfree(mta_list);
3159
3160 return netdev_mc_count(netdev);
3161}
3162
3163/**
3164 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3165 * @netdev: network interface device structure
bc7f75fa 3166 *
ef9b965a
JB		 3167 * Writes unicast address list to the RAR table.
3168 * Returns: -ENOMEM on failure/insufficient address space
3169 * 0 on no addresses written
3170 * X on writing X addresses to the RAR table
bc7f75fa 3171 **/
ef9b965a 3172static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3173{
ef9b965a
JB		 3174 struct e1000_adapter *adapter = netdev_priv(netdev);
3175 struct e1000_hw *hw = &adapter->hw;
3176 unsigned int rar_entries = hw->mac.rar_entry_count;
3177 int count = 0;
3178
3179 /* save a rar entry for our hardware address */
3180 rar_entries--;
3181
3182 /* save a rar entry for the LAA workaround */
3183 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3184 rar_entries--;
3185
3186 /* return ENOMEM indicating insufficient memory for addresses */
3187 if (netdev_uc_count(netdev) > rar_entries)
3188 return -ENOMEM;
3189
3190 if (!netdev_uc_empty(netdev) && rar_entries) {
3191 struct netdev_hw_addr *ha;
3192
e921eb1a 3193 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3194 * combining
3195 */
3196 netdev_for_each_uc_addr(ha, netdev) {
3197 if (!rar_entries)
3198 break;
69e1e019 3199 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3200 count++;
3201 }
3202 }
3203
3204 /* zero out the remaining RAR entries not used above */
3205 for (; rar_entries > 0; rar_entries--) {
3206 ew32(RAH(rar_entries), 0);
3207 ew32(RAL(rar_entries), 0);
3208 }
3209 e1e_flush();
3210
3211 return count;
bc7f75fa
AK		 3212}
3213
3214/**
ef9b965a 3215 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3216 * @netdev: network interface device structure
3217 *
ef9b965a
JB		 3218 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3219 * address list or the network interface flags are updated. This routine is
3220 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3221 * promiscuous mode, and all-multi behavior.
3222 **/
ef9b965a 3223static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3224{
3225 struct e1000_adapter *adapter = netdev_priv(netdev);
3226 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3227 u32 rctl;
bc7f75fa
AK		 3228
3229 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3230 rctl = er32(RCTL);
3231
ef9b965a
JB		 3232 /* clear the affected bits */
3233 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3234
bc7f75fa
AK		 3235 if (netdev->flags & IFF_PROMISC) {
3236 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3237 /* Do not hardware filter VLANs in promisc mode */
3238 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3239 } else {
ef9b965a 3240 int count;
3d3a1676 3241
746b9f02
PM		 3242 if (netdev->flags & IFF_ALLMULTI) {
3243 rctl |= E1000_RCTL_MPE;
746b9f02 3244 } else {
e921eb1a 3245 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3246 * then we should just turn on promiscuous mode so
3247 * that we can at least receive multicast traffic
3248 */
3249 count = e1000e_write_mc_addr_list(netdev);
3250 if (count < 0)
3251 rctl |= E1000_RCTL_MPE;
746b9f02 3252 }
86d70e53 3253 e1000e_vlan_filter_enable(adapter);
e921eb1a 3254 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3255 * sufficient space to store all the addresses then enable
3256 * unicast promiscuous mode
bc7f75fa 3257 */
ef9b965a
JB		 3258 count = e1000e_write_uc_addr_list(netdev);
3259 if (count < 0)
3260 rctl |= E1000_RCTL_UPE;
bc7f75fa 3261 }
86d70e53 3262
ef9b965a
JB		 3263 ew32(RCTL, rctl);
3264
86d70e53
JK		 3265 if (netdev->features & NETIF_F_HW_VLAN_RX)
3266 e1000e_vlan_strip_enable(adapter);
3267 else
3268 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3269}
3270
70495a50
BA		 3271static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3272{
3273 struct e1000_hw *hw = &adapter->hw;
3274 u32 mrqc, rxcsum;
3275 int i;
3276 static const u32 rsskey[10] = {
3277 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3278 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3279 };
3280
3281 /* Fill out hash function seed */
3282 for (i = 0; i < 10; i++)
3283 ew32(RSSRK(i), rsskey[i]);
3284
3285 /* Direct all traffic to queue 0 */
3286 for (i = 0; i < 32; i++)
3287 ew32(RETA(i), 0);
3288
e921eb1a 3289 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3290 * descriptor on writeback.
3291 */
3292 rxcsum = er32(RXCSUM);
3293 rxcsum |= E1000_RXCSUM_PCSD;
3294
3295 ew32(RXCSUM, rxcsum);
3296
3297 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3298 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3299 E1000_MRQC_RSS_FIELD_IPV6 |
3300 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3301 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3302
3303 ew32(MRQC, mrqc);
3304}
3305
bc7f75fa 3306/**
ad68076e 3307 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3308 * @adapter: private board structure
3309 **/
3310static void e1000_configure(struct e1000_adapter *adapter)
3311{
55aa6985
BA		 3312 struct e1000_ring *rx_ring = adapter->rx_ring;
3313
ef9b965a 3314 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3315
3316 e1000_restore_vlan(adapter);
cd791618 3317 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3318
3319 e1000_configure_tx(adapter);
70495a50
BA		 3320
3321 if (adapter->netdev->features & NETIF_F_RXHASH)
3322 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3323 e1000_setup_rctl(adapter);
3324 e1000_configure_rx(adapter);
55aa6985 3325 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3326}
3327
3328/**
3329 * e1000e_power_up_phy - restore link in case the phy was powered down
3330 * @adapter: address of board private structure
3331 *
3332 * The phy may be powered down to save power and turn off link when the
3333 * driver is unloaded and wake on lan is not enabled (among others)
3334 * *** this routine MUST be followed by a call to e1000e_reset ***
3335 **/
3336void e1000e_power_up_phy(struct e1000_adapter *adapter)
3337{
17f208de
BA		 3338 if (adapter->hw.phy.ops.power_up)
3339 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3340
3341 adapter->hw.mac.ops.setup_link(&adapter->hw);
3342}
3343
3344/**
3345 * e1000_power_down_phy - Power down the PHY
3346 *
17f208de
BA		 3347 * Power down the PHY so no link is implied when interface is down.
3348 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3349 */
3350static void e1000_power_down_phy(struct e1000_adapter *adapter)
3351{
bc7f75fa 3352 /* WoL is enabled */
23b66e2b 3353 if (adapter->wol)
bc7f75fa
AK		 3354 return;
3355
17f208de
BA		 3356 if (adapter->hw.phy.ops.power_down)
3357 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3358}
3359
3360/**
3361 * e1000e_reset - bring the hardware into a known good state
3362 *
3363 * This function boots the hardware and enables some settings that
3364 * require a configuration cycle of the hardware - those cannot be
3365 * set/changed during runtime. After reset the device needs to be
ad68076e 3366 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3367 */
3368void e1000e_reset(struct e1000_adapter *adapter)
3369{
3370 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3371 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3372 struct e1000_hw *hw = &adapter->hw;
3373 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3374 u32 pba = adapter->pba;
bc7f75fa
AK		 3375 u16 hwm;
3376
ad68076e 3377 /* reset Packet Buffer Allocation to default */
318a94d6 3378 ew32(PBA, pba);
df762464 3379
318a94d6 3380 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3381 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3382 * large enough to accommodate two full transmit packets,
3383 * rounded up to the next 1KB and expressed in KB. Likewise,
3384 * the Rx FIFO should be large enough to accommodate at least
3385 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3386 * expressed in KB.
3387 */
df762464 3388 pba = er32(PBA);
bc7f75fa 3389 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3390 tx_space = pba >> 16;
bc7f75fa 3391 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3392 pba &= 0xffff;
e921eb1a 3393 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3394 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3395 */
3396 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3397 sizeof(struct e1000_tx_desc) -
3398 ETH_FCS_LEN) * 2;
3399 min_tx_space = ALIGN(min_tx_space, 1024);
3400 min_tx_space >>= 10;
3401 /* software strips receive CRC, so leave room for it */
318a94d6 3402 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3403 min_rx_space = ALIGN(min_rx_space, 1024);
3404 min_rx_space >>= 10;
3405
e921eb1a 3406 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3407 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3408 * allocation, take space away from current Rx allocation
3409 */
df762464
AK		 3410 if ((tx_space < min_tx_space) &&
3411 ((min_tx_space - tx_space) < pba)) {
3412 pba -= min_tx_space - tx_space;
bc7f75fa 3413
e921eb1a 3414 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3415 * adjustment
ad68076e 3416 */
79d4e908 3417 if (pba < min_rx_space)
df762464 3418 pba = min_rx_space;
bc7f75fa 3419 }
df762464
AK		 3420
3421 ew32(PBA, pba);
bc7f75fa
AK		 3422 }
3423
e921eb1a 3424 /* flow control settings
ad68076e 3425 *
38eb394e 3426 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3427 * (or the size used for early receive) above it in the Rx FIFO.
3428 * Set it to the lower of:
3429 * - 90% of the Rx FIFO size, and
38eb394e 3430 * - the full Rx FIFO size minus one full frame
ad68076e 3431 */
d3738bb8
BA		 3432 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3433 fc->pause_time = 0xFFFF;
3434 else
3435 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3436 fc->send_xon = true;
d3738bb8
BA		 3437 fc->current_mode = fc->requested_mode;
3438
3439 switch (hw->mac.type) {
79d4e908
BA		 3440 case e1000_ich9lan:
3441 case e1000_ich10lan:
3442 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3443 pba = 14;
3444 ew32(PBA, pba);
3445 fc->high_water = 0x2800;
3446 fc->low_water = fc->high_water - 8;
3447 break;
3448 }
3449 /* fall-through */
d3738bb8 3450 default:
79d4e908
BA		 3451 hwm = min(((pba << 10) * 9 / 10),
3452 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3453
3454 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3455 fc->low_water = fc->high_water - 8;
3456 break;
3457 case e1000_pchlan:
e921eb1a 3458 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3459 * loads. If hangs persist, try disabling Tx flow control.
3460 */
3461 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3462 fc->high_water = 0x3500;
3463 fc->low_water = 0x1500;
3464 } else {
3465 fc->high_water = 0x5000;
3466 fc->low_water = 0x3000;
3467 }
a305595b 3468 fc->refresh_time = 0x1000;
d3738bb8
BA		 3469 break;
3470 case e1000_pch2lan:
2fbe4526 3471 case e1000_pch_lpt:
d3738bb8
BA		 3472 fc->high_water = 0x05C20;
3473 fc->low_water = 0x05048;
3474 fc->pause_time = 0x0650;
3475 fc->refresh_time = 0x0400;
828bac87
BA		 3476 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3477 pba = 14;
3478 ew32(PBA, pba);
3479 }
d3738bb8 3480 break;
38eb394e 3481 }
bc7f75fa 3482
e921eb1a 3483 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3484 * maximum size per Tx descriptor limited only to the transmit
3485 * allocation of the packet buffer minus 96 bytes with an upper
3486 * limit of 24KB due to receive synchronization limitations.
3487 */
3488 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3489 24 << 10);
3490
e921eb1a 3491 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3492 * fit in receive buffer.
828bac87
BA		 3493 */
3494 if (adapter->itr_setting & 0x3) {
79d4e908 3495 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3496 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3497 dev_info(&adapter->pdev->dev,
3498 "Interrupt Throttle Rate turned off\n");
3499 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3500 e1000e_write_itr(adapter, 0);
828bac87
BA		 3501 }
3502 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3503 dev_info(&adapter->pdev->dev,
3504 "Interrupt Throttle Rate turned on\n");
3505 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3506 adapter->itr = 20000;
22a4cca2 3507 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3508 }
3509 }
3510
bc7f75fa
AK		 3511 /* Allow time for pending master requests to run */
3512 mac->ops.reset_hw(hw);
97ac8cae 3513
e921eb1a 3514 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3515 * that the network interface is in control
3516 */
c43bc57e 3517 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3518 e1000e_get_hw_control(adapter);
97ac8cae 3519
bc7f75fa
AK		 3520 ew32(WUC, 0);
3521
3522 if (mac->ops.init_hw(hw))
44defeb3 3523 e_err("Hardware Error\n");
bc7f75fa
AK		 3524
3525 e1000_update_mng_vlan(adapter);
3526
3527 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3528 ew32(VET, ETH_P_8021Q);
3529
3530 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3531
3532 if (!netif_running(adapter->netdev) &&
3533 !test_bit(__E1000_TESTING, &adapter->state)) {
3534 e1000_power_down_phy(adapter);
3535 return;
3536 }
3537
bc7f75fa
AK		 3538 e1000_get_phy_info(hw);
3539
918d7197
BA		 3540 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3541 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3542 u16 phy_data = 0;
e921eb1a 3543 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3544 * the return value of this function because there is nothing
ad68076e
BA		 3545 * different we would do if it failed
3546 */
bc7f75fa
AK		 3547 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3548 phy_data &= ~IGP02E1000_PM_SPD;
3549 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3550 }
bc7f75fa
AK		 3551}
3552
3553int e1000e_up(struct e1000_adapter *adapter)
3554{
3555 struct e1000_hw *hw = &adapter->hw;
3556
3557 /* hardware has been reset, we need to reload some things */
3558 e1000_configure(adapter);
3559
3560 clear_bit(__E1000_DOWN, &adapter->state);
3561
4662e82b
BA		 3562 if (adapter->msix_entries)
3563 e1000_configure_msix(adapter);
bc7f75fa
AK		 3564 e1000_irq_enable(adapter);
3565
400484fa 3566 netif_start_queue(adapter->netdev);
4cb9be7a 3567
bc7f75fa 3568 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3569 if (adapter->msix_entries)
3570 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3571 else
3572 ew32(ICS, E1000_ICS_LSC);
3573
bc7f75fa
AK		 3574 return 0;
3575}
3576
713b3c9e
JB		 3577static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3578{
3579 struct e1000_hw *hw = &adapter->hw;
3580
3581 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3582 return;
3583
3584 /* flush pending descriptor writebacks to memory */
3585 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3586 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3587
3588 /* execute the writes immediately */
3589 e1e_flush();
bf03085f 3590
e921eb1a 3591 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3592 * write is successful
3593 */
3594 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3595 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3596
3597 /* execute the writes immediately */
3598 e1e_flush();
3599}
3600
67fd4fcb
JK		 3601static void e1000e_update_stats(struct e1000_adapter *adapter);
3602
bc7f75fa
AK		 3603void e1000e_down(struct e1000_adapter *adapter)
3604{
3605 struct net_device *netdev = adapter->netdev;
3606 struct e1000_hw *hw = &adapter->hw;
3607 u32 tctl, rctl;
3608
e921eb1a 3609 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3610 * reschedule our watchdog timer
3611 */
bc7f75fa
AK		 3612 set_bit(__E1000_DOWN, &adapter->state);
3613
3614 /* disable receives in the hardware */
3615 rctl = er32(RCTL);
7f99ae63
BA		 3616 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3618 /* flush and sleep below */
3619
4cb9be7a 3620 netif_stop_queue(netdev);
bc7f75fa
AK		 3621
3622 /* disable transmits in the hardware */
3623 tctl = er32(TCTL);
3624 tctl &= ~E1000_TCTL_EN;
3625 ew32(TCTL, tctl);
7f99ae63 3626
bc7f75fa
AK		 3627 /* flush both disables and wait for them to finish */
3628 e1e_flush();
1bba4386 3629 usleep_range(10000, 20000);
bc7f75fa 3630
bc7f75fa
AK		 3631 e1000_irq_disable(adapter);
3632
3633 del_timer_sync(&adapter->watchdog_timer);
3634 del_timer_sync(&adapter->phy_info_timer);
3635
bc7f75fa 3636 netif_carrier_off(netdev);
67fd4fcb
JK		 3637
3638 spin_lock(&adapter->stats64_lock);
3639 e1000e_update_stats(adapter);
3640 spin_unlock(&adapter->stats64_lock);
3641
400484fa 3642 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3643 e1000_clean_tx_ring(adapter->tx_ring);
3644 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3645
bc7f75fa
AK		 3646 adapter->link_speed = 0;
3647 adapter->link_duplex = 0;
3648
52cc3086
JK		 3649 if (!pci_channel_offline(adapter->pdev))
3650 e1000e_reset(adapter);
713b3c9e 3651
e921eb1a 3652 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 3653 * pci_disable_device here.
3654 */
3655}
3656
3657void e1000e_reinit_locked(struct e1000_adapter *adapter)
3658{
3659 might_sleep();
3660 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3661 usleep_range(1000, 2000);
bc7f75fa
AK		 3662 e1000e_down(adapter);
3663 e1000e_up(adapter);
3664 clear_bit(__E1000_RESETTING, &adapter->state);
3665}
3666
3667/**
3668 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3669 * @adapter: board private structure to initialize
3670 *
3671 * e1000_sw_init initializes the Adapter private data structure.
3672 * Fields are initialized based on PCI device information and
3673 * OS network device settings (MTU size).
3674 **/
9f9a12f8 3675static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 3676{
bc7f75fa
AK		 3677 struct net_device *netdev = adapter->netdev;
3678
3679 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3680 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3681 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3682 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3683 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3684 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3685
67fd4fcb
JK		 3686 spin_lock_init(&adapter->stats64_lock);
3687
4662e82b 3688 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3689
4662e82b
BA		 3690 if (e1000_alloc_queues(adapter))
3691 return -ENOMEM;
bc7f75fa 3692
bc7f75fa 3693 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3694 e1000_irq_disable(adapter);
3695
bc7f75fa
AK		 3696 set_bit(__E1000_DOWN, &adapter->state);
3697 return 0;
bc7f75fa
AK		 3698}
3699
f8d59f78
BA		 3700/**
3701 * e1000_intr_msi_test - Interrupt Handler
3702 * @irq: interrupt number
3703 * @data: pointer to a network interface device structure
3704 **/
3705static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3706{
3707 struct net_device *netdev = data;
3708 struct e1000_adapter *adapter = netdev_priv(netdev);
3709 struct e1000_hw *hw = &adapter->hw;
3710 u32 icr = er32(ICR);
3711
3bb99fe2 3712 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3713 if (icr & E1000_ICR_RXSEQ) {
3714 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 3715 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 3716 * interrupt is handled.
3717 */
f8d59f78
BA		 3718 wmb();
3719 }
3720
3721 return IRQ_HANDLED;
3722}
3723
3724/**
3725 * e1000_test_msi_interrupt - Returns 0 for successful test
3726 * @adapter: board private struct
3727 *
3728 * code flow taken from tg3.c
3729 **/
3730static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3731{
3732 struct net_device *netdev = adapter->netdev;
3733 struct e1000_hw *hw = &adapter->hw;
3734 int err;
3735
3736 /* poll_enable hasn't been called yet, so don't need disable */
3737 /* clear any pending events */
3738 er32(ICR);
3739
3740 /* free the real vector and request a test handler */
3741 e1000_free_irq(adapter);
4662e82b 3742 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3743
3744 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 3745 * MSI irq handler will unset this flag
3746 */
f8d59f78
BA		 3747 adapter->flags |= FLAG_MSI_TEST_FAILED;
3748
3749 err = pci_enable_msi(adapter->pdev);
3750 if (err)
3751 goto msi_test_failed;
3752
a0607fd3 3753 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3754 netdev->name, netdev);
3755 if (err) {
3756 pci_disable_msi(adapter->pdev);
3757 goto msi_test_failed;
3758 }
3759
e921eb1a 3760 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 3761 * interrupt.
3762 */
f8d59f78
BA		 3763 wmb();
3764
3765 e1000_irq_enable(adapter);
3766
3767 /* fire an unusual interrupt on the test handler */
3768 ew32(ICS, E1000_ICS_RXSEQ);
3769 e1e_flush();
569a3aff 3770 msleep(100);
f8d59f78
BA		 3771
3772 e1000_irq_disable(adapter);
3773
bc76329d 3774 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 3775
3776 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3777 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3778 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3779 } else {
068e8a30 3780 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3781 }
f8d59f78
BA		 3782
3783 free_irq(adapter->pdev->irq, netdev);
3784 pci_disable_msi(adapter->pdev);
3785
f8d59f78 3786msi_test_failed:
4662e82b 3787 e1000e_set_interrupt_capability(adapter);
068e8a30 3788 return e1000_request_irq(adapter);
f8d59f78
BA		 3789}
3790
3791/**
3792 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3793 * @adapter: board private struct
3794 *
3795 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3796 **/
3797static int e1000_test_msi(struct e1000_adapter *adapter)
3798{
3799 int err;
3800 u16 pci_cmd;
3801
3802 if (!(adapter->flags & FLAG_MSI_ENABLED))
3803 return 0;
3804
3805 /* disable SERR in case the MSI write causes a master abort */
3806 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3807 if (pci_cmd & PCI_COMMAND_SERR)
3808 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3809 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3810
3811 err = e1000_test_msi_interrupt(adapter);
3812
36f2407f
DN		 3813 /* re-enable SERR */
3814 if (pci_cmd & PCI_COMMAND_SERR) {
3815 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3816 pci_cmd |= PCI_COMMAND_SERR;
3817 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3818 }
f8d59f78 3819
f8d59f78
BA		 3820 return err;
3821}
3822
bc7f75fa
AK		 3823/**
3824 * e1000_open - Called when a network interface is made active
3825 * @netdev: network interface device structure
3826 *
3827 * Returns 0 on success, negative value on failure
3828 *
3829 * The open entry point is called when a network interface is made
3830 * active by the system (IFF_UP). At this point all resources needed
3831 * for transmit and receive operations are allocated, the interrupt
3832 * handler is registered with the OS, the watchdog timer is started,
3833 * and the stack is notified that the interface is ready.
3834 **/
3835static int e1000_open(struct net_device *netdev)
3836{
3837 struct e1000_adapter *adapter = netdev_priv(netdev);
3838 struct e1000_hw *hw = &adapter->hw;
23606cf5 3839 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3840 int err;
3841
3842 /* disallow open during test */
3843 if (test_bit(__E1000_TESTING, &adapter->state))
3844 return -EBUSY;
3845
23606cf5
RW		 3846 pm_runtime_get_sync(&pdev->dev);
3847
9c563d20
JB		 3848 netif_carrier_off(netdev);
3849
bc7f75fa 3850 /* allocate transmit descriptors */
55aa6985 3851 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3852 if (err)
3853 goto err_setup_tx;
3854
3855 /* allocate receive descriptors */
55aa6985 3856 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3857 if (err)
3858 goto err_setup_rx;
3859
e921eb1a 3860 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 3861 * interface is now open and reset the part to a known state.
3862 */
3863 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3864 e1000e_get_hw_control(adapter);
11b08be8
BA		 3865 e1000e_reset(adapter);
3866 }
3867
bc7f75fa
AK		 3868 e1000e_power_up_phy(adapter);
3869
3870 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3871 if ((adapter->hw.mng_cookie.status &
3872 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3873 e1000_update_mng_vlan(adapter);
3874
79d4e908
BA		 3875 /* DMA latency requirement to workaround jumbo issue */
3876 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3877 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3878 PM_QOS_CPU_DMA_LATENCY,
3879 PM_QOS_DEFAULT_VALUE);
c128ec29 3880
e921eb1a 3881 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3882 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3883 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3884 * clean_rx handler before we do so.
3885 */
bc7f75fa
AK		 3886 e1000_configure(adapter);
3887
3888 err = e1000_request_irq(adapter);
3889 if (err)
3890 goto err_req_irq;
3891
e921eb1a 3892 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 3893 * ignore e1000e MSI messages, which means we need to test our MSI
3894 * interrupt now
3895 */
4662e82b 3896 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3897 err = e1000_test_msi(adapter);
3898 if (err) {
3899 e_err("Interrupt allocation failed\n");
3900 goto err_req_irq;
3901 }
3902 }
3903
bc7f75fa
AK		 3904 /* From here on the code is the same as e1000e_up() */
3905 clear_bit(__E1000_DOWN, &adapter->state);
3906
3907 napi_enable(&adapter->napi);
3908
3909 e1000_irq_enable(adapter);
3910
09357b00 3911 adapter->tx_hang_recheck = false;
4cb9be7a 3912 netif_start_queue(netdev);
d55b53ff 3913
23606cf5
RW		 3914 adapter->idle_check = true;
3915 pm_runtime_put(&pdev->dev);
3916
bc7f75fa 3917 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3918 if (adapter->msix_entries)
3919 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3920 else
3921 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3922
3923 return 0;
3924
3925err_req_irq:
31dbe5b4 3926 e1000e_release_hw_control(adapter);
bc7f75fa 3927 e1000_power_down_phy(adapter);
55aa6985 3928 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3929err_setup_rx:
55aa6985 3930 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3931err_setup_tx:
3932 e1000e_reset(adapter);
23606cf5 3933 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3934
3935 return err;
3936}
3937
3938/**
3939 * e1000_close - Disables a network interface
3940 * @netdev: network interface device structure
3941 *
3942 * Returns 0, this is not allowed to fail
3943 *
3944 * The close entry point is called when an interface is de-activated
3945 * by the OS. The hardware is still under the drivers control, but
3946 * needs to be disabled. A global MAC reset is issued to stop the
3947 * hardware, and all transmit and receive resources are freed.
3948 **/
3949static int e1000_close(struct net_device *netdev)
3950{
3951 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3952 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 3953 int count = E1000_CHECK_RESET_COUNT;
3954
3955 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
3956 usleep_range(10000, 20000);
bc7f75fa
AK		 3957
3958 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3959
3960 pm_runtime_get_sync(&pdev->dev);
3961
5f4a780d
BA		 3962 napi_disable(&adapter->napi);
3963
23606cf5
RW		 3964 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3965 e1000e_down(adapter);
3966 e1000_free_irq(adapter);
3967 }
bc7f75fa 3968 e1000_power_down_phy(adapter);
bc7f75fa 3969
55aa6985
BA		 3970 e1000e_free_tx_resources(adapter->tx_ring);
3971 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3972
e921eb1a 3973 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 3974 * the same ID is registered on the host OS (let 8021q kill it)
3975 */
86d70e53
JK		 3976 if (adapter->hw.mng_cookie.status &
3977 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3978 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3979
e921eb1a 3980 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 3981 * interface is now closed
3982 */
31dbe5b4
BA		 3983 if ((adapter->flags & FLAG_HAS_AMT) &&
3984 !test_bit(__E1000_TESTING, &adapter->state))
3985 e1000e_release_hw_control(adapter);
bc7f75fa 3986
79d4e908 3987 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 3988 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3989
23606cf5
RW		 3990 pm_runtime_put_sync(&pdev->dev);
3991
bc7f75fa
AK		 3992 return 0;
3993}
3994/**
3995 * e1000_set_mac - Change the Ethernet Address of the NIC
3996 * @netdev: network interface device structure
3997 * @p: pointer to an address structure
3998 *
3999 * Returns 0 on success, negative on failure
4000 **/
4001static int e1000_set_mac(struct net_device *netdev, void *p)
4002{
4003 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4004 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4005 struct sockaddr *addr = p;
4006
4007 if (!is_valid_ether_addr(addr->sa_data))
4008 return -EADDRNOTAVAIL;
4009
4010 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4011 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4012
69e1e019 4013 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4014
4015 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4016 /* activate the work around */
4017 e1000e_set_laa_state_82571(&adapter->hw, 1);
4018
e921eb1a 4019 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4020 * between the time RAR[0] gets clobbered and the time it
4021 * gets fixed (in e1000_watchdog), the actual LAA is in one
4022 * of the RARs and no incoming packets directed to this port
4023 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4024 * RAR[14]
4025 */
69e1e019
BA		 4026 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4027 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4028 }
4029
4030 return 0;
4031}
4032
a8f88ff5
JB		 4033/**
4034 * e1000e_update_phy_task - work thread to update phy
4035 * @work: pointer to our work struct
4036 *
4037 * this worker thread exists because we must acquire a
4038 * semaphore to read the phy, which we could msleep while
4039 * waiting for it, and we can't msleep in a timer.
4040 **/
4041static void e1000e_update_phy_task(struct work_struct *work)
4042{
4043 struct e1000_adapter *adapter = container_of(work,
4044 struct e1000_adapter, update_phy_task);
615b32af
JB		 4045
4046 if (test_bit(__E1000_DOWN, &adapter->state))
4047 return;
4048
a8f88ff5
JB		 4049 e1000_get_phy_info(&adapter->hw);
4050}
4051
e921eb1a
BA		 4052/**
4053 * e1000_update_phy_info - timre call-back to update PHY info
4054 * @data: pointer to adapter cast into an unsigned long
4055 *
ad68076e
BA		 4056 * Need to wait a few seconds after link up to get diagnostic information from
4057 * the phy
e921eb1a 4058 **/
bc7f75fa
AK		 4059static void e1000_update_phy_info(unsigned long data)
4060{
4061 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4062
4063 if (test_bit(__E1000_DOWN, &adapter->state))
4064 return;
4065
a8f88ff5 4066 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4067}
4068
8c7bbb92
BA		 4069/**
4070 * e1000e_update_phy_stats - Update the PHY statistics counters
4071 * @adapter: board private structure
2b6b168d
BA		 4072 *
4073 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4074 **/
4075static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4076{
4077 struct e1000_hw *hw = &adapter->hw;
4078 s32 ret_val;
4079 u16 phy_data;
4080
4081 ret_val = hw->phy.ops.acquire(hw);
4082 if (ret_val)
4083 return;
4084
e921eb1a 4085 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4086 * If not, set to the page with the PHY status registers.
4087 */
2b6b168d 4088 hw->phy.addr = 1;
8c7bbb92
BA		 4089 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4090 &phy_data);
4091 if (ret_val)
4092 goto release;
2b6b168d
BA		 4093 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4094 ret_val = hw->phy.ops.set_page(hw,
4095 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4096 if (ret_val)
4097 goto release;
4098 }
4099
8c7bbb92 4100 /* Single Collision Count */
2b6b168d
BA		 4101 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4102 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4103 if (!ret_val)
4104 adapter->stats.scc += phy_data;
4105
4106 /* Excessive Collision Count */
2b6b168d
BA		 4107 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4108 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4109 if (!ret_val)
4110 adapter->stats.ecol += phy_data;
4111
4112 /* Multiple Collision Count */
2b6b168d
BA		 4113 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4114 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4115 if (!ret_val)
4116 adapter->stats.mcc += phy_data;
4117
4118 /* Late Collision Count */
2b6b168d
BA		 4119 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4120 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4121 if (!ret_val)
4122 adapter->stats.latecol += phy_data;
4123
4124 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4125 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4126 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4127 if (!ret_val)
4128 hw->mac.collision_delta = phy_data;
4129
4130 /* Defer Count */
2b6b168d
BA		 4131 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4132 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4133 if (!ret_val)
4134 adapter->stats.dc += phy_data;
4135
4136 /* Transmit with no CRS */
2b6b168d
BA		 4137 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4138 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4139 if (!ret_val)
4140 adapter->stats.tncrs += phy_data;
4141
4142release:
4143 hw->phy.ops.release(hw);
4144}
4145
bc7f75fa
AK		 4146/**
4147 * e1000e_update_stats - Update the board statistics counters
4148 * @adapter: board private structure
4149 **/
67fd4fcb 4150static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4151{
7274c20f 4152 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4153 struct e1000_hw *hw = &adapter->hw;
4154 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4155
e921eb1a 4156 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4157 * connection is down.
4158 */
4159 if (adapter->link_speed == 0)
4160 return;
4161 if (pci_channel_offline(pdev))
4162 return;
4163
bc7f75fa
AK		 4164 adapter->stats.crcerrs += er32(CRCERRS);
4165 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4166 adapter->stats.gorc += er32(GORCL);
4167 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4168 adapter->stats.bprc += er32(BPRC);
4169 adapter->stats.mprc += er32(MPRC);
4170 adapter->stats.roc += er32(ROC);
4171
bc7f75fa 4172 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4173
4174 /* Half-duplex statistics */
4175 if (adapter->link_duplex == HALF_DUPLEX) {
4176 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4177 e1000e_update_phy_stats(adapter);
4178 } else {
4179 adapter->stats.scc += er32(SCC);
4180 adapter->stats.ecol += er32(ECOL);
4181 adapter->stats.mcc += er32(MCC);
4182 adapter->stats.latecol += er32(LATECOL);
4183 adapter->stats.dc += er32(DC);
4184
4185 hw->mac.collision_delta = er32(COLC);
4186
4187 if ((hw->mac.type != e1000_82574) &&
4188 (hw->mac.type != e1000_82583))
4189 adapter->stats.tncrs += er32(TNCRS);
4190 }
4191 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4192 }
8c7bbb92 4193
bc7f75fa
AK		 4194 adapter->stats.xonrxc += er32(XONRXC);
4195 adapter->stats.xontxc += er32(XONTXC);
4196 adapter->stats.xoffrxc += er32(XOFFRXC);
4197 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4198 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4199 adapter->stats.gotc += er32(GOTCL);
4200 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4201 adapter->stats.rnbc += er32(RNBC);
4202 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4203
4204 adapter->stats.mptc += er32(MPTC);
4205 adapter->stats.bptc += er32(BPTC);
4206
4207 /* used for adaptive IFS */
4208
4209 hw->mac.tx_packet_delta = er32(TPT);
4210 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4211
4212 adapter->stats.algnerrc += er32(ALGNERRC);
4213 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4214 adapter->stats.cexterr += er32(CEXTERR);
4215 adapter->stats.tsctc += er32(TSCTC);
4216 adapter->stats.tsctfc += er32(TSCTFC);
4217
bc7f75fa 4218 /* Fill out the OS statistics structure */
7274c20f
AK		 4219 netdev->stats.multicast = adapter->stats.mprc;
4220 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4221
4222 /* Rx Errors */
4223
e921eb1a 4224 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4225 * our own version based on RUC and ROC
4226 */
7274c20f 4227 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4228 adapter->stats.crcerrs + adapter->stats.algnerrc +
4229 adapter->stats.ruc + adapter->stats.roc +
4230 adapter->stats.cexterr;
7274c20f 4231 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4232 adapter->stats.roc;
7274c20f
AK		 4233 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4234 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4235 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4236
4237 /* Tx Errors */
7274c20f 4238 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4239 adapter->stats.latecol;
7274c20f
AK		 4240 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4241 netdev->stats.tx_window_errors = adapter->stats.latecol;
4242 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4243
4244 /* Tx Dropped needs to be maintained elsewhere */
4245
bc7f75fa
AK		 4246 /* Management Stats */
4247 adapter->stats.mgptc += er32(MGTPTC);
4248 adapter->stats.mgprc += er32(MGTPRC);
4249 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4250}
4251
7c25769f
BA		 4252/**
4253 * e1000_phy_read_status - Update the PHY register status snapshot
4254 * @adapter: board private structure
4255 **/
4256static void e1000_phy_read_status(struct e1000_adapter *adapter)
4257{
4258 struct e1000_hw *hw = &adapter->hw;
4259 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4260
4261 if ((er32(STATUS) & E1000_STATUS_LU) &&
4262 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4263 int ret_val;
4264
7c25769f
BA		 4265 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4266 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4267 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4268 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4269 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4270 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4271 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4272 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4273 if (ret_val)
44defeb3 4274 e_warn("Error reading PHY register\n");
7c25769f 4275 } else {
e921eb1a 4276 /* Do not read PHY registers if link is not up
7c25769f
BA		 4277 * Set values to typical power-on defaults
4278 */
4279 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4280 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4281 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4282 BMSR_ERCAP);
4283 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4284 ADVERTISE_ALL | ADVERTISE_CSMA);
4285 phy->lpa = 0;
4286 phy->expansion = EXPANSION_ENABLENPAGE;
4287 phy->ctrl1000 = ADVERTISE_1000FULL;
4288 phy->stat1000 = 0;
4289 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4290 }
7c25769f
BA		 4291}
4292
bc7f75fa
AK		 4293static void e1000_print_link_info(struct e1000_adapter *adapter)
4294{
bc7f75fa
AK		 4295 struct e1000_hw *hw = &adapter->hw;
4296 u32 ctrl = er32(CTRL);
4297
8f12fe86 4298 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4299 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4300 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4301 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4302 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4303 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4304 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4305}
4306
0c6bdb30 4307static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4308{
4309 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4310 bool link_active = false;
318a94d6
JK		 4311 s32 ret_val = 0;
4312
e921eb1a 4313 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4314 * Rx sequence error interrupt. get_link_status will stay
4315 * false until the check_for_link establishes link
4316 * for copper adapters ONLY
4317 */
4318 switch (hw->phy.media_type) {
4319 case e1000_media_type_copper:
4320 if (hw->mac.get_link_status) {
4321 ret_val = hw->mac.ops.check_for_link(hw);
4322 link_active = !hw->mac.get_link_status;
4323 } else {
3db1cd5c 4324 link_active = true;
318a94d6
JK		 4325 }
4326 break;
4327 case e1000_media_type_fiber:
4328 ret_val = hw->mac.ops.check_for_link(hw);
4329 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4330 break;
4331 case e1000_media_type_internal_serdes:
4332 ret_val = hw->mac.ops.check_for_link(hw);
4333 link_active = adapter->hw.mac.serdes_has_link;
4334 break;
4335 default:
4336 case e1000_media_type_unknown:
4337 break;
4338 }
4339
4340 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4341 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4342 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4343 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4344 }
4345
4346 return link_active;
4347}
4348
4349static void e1000e_enable_receives(struct e1000_adapter *adapter)
4350{
4351 /* make sure the receive unit is started */
4352 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4353 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4354 struct e1000_hw *hw = &adapter->hw;
4355 u32 rctl = er32(RCTL);
4356 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4357 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4358 }
4359}
4360
ff10e13c
CW		 4361static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4362{
4363 struct e1000_hw *hw = &adapter->hw;
4364
e921eb1a 4365 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4366 * for hung state and reset, if two calls return true
4367 */
4368 if (e1000_check_phy_82574(hw))
4369 adapter->phy_hang_count++;
4370 else
4371 adapter->phy_hang_count = 0;
4372
4373 if (adapter->phy_hang_count > 1) {
4374 adapter->phy_hang_count = 0;
4375 schedule_work(&adapter->reset_task);
4376 }
4377}
4378
bc7f75fa
AK		 4379/**
4380 * e1000_watchdog - Timer Call-back
4381 * @data: pointer to adapter cast into an unsigned long
4382 **/
4383static void e1000_watchdog(unsigned long data)
4384{
4385 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4386
4387 /* Do the rest outside of interrupt context */
4388 schedule_work(&adapter->watchdog_task);
4389
4390 /* TODO: make this use queue_delayed_work() */
4391}
4392
4393static void e1000_watchdog_task(struct work_struct *work)
4394{
4395 struct e1000_adapter *adapter = container_of(work,
4396 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4397 struct net_device *netdev = adapter->netdev;
4398 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4399 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4400 struct e1000_ring *tx_ring = adapter->tx_ring;
4401 struct e1000_hw *hw = &adapter->hw;
4402 u32 link, tctl;
bc7f75fa 4403
615b32af
JB		 4404 if (test_bit(__E1000_DOWN, &adapter->state))
4405 return;
4406
b405e8df 4407 link = e1000e_has_link(adapter);
318a94d6 4408 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4409 /* Cancel scheduled suspend requests. */
4410 pm_runtime_resume(netdev->dev.parent);
4411
318a94d6 4412 e1000e_enable_receives(adapter);
bc7f75fa 4413 goto link_up;
bc7f75fa
AK		 4414 }
4415
4416 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4417 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4418 e1000_update_mng_vlan(adapter);
4419
bc7f75fa
AK		 4420 if (link) {
4421 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4422 bool txb2b = true;
23606cf5
RW		 4423
4424 /* Cancel scheduled suspend requests. */
4425 pm_runtime_resume(netdev->dev.parent);
4426
318a94d6 4427 /* update snapshot of PHY registers on LSC */
7c25769f 4428 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4429 mac->ops.get_link_up_info(&adapter->hw,
4430 &adapter->link_speed,
4431 &adapter->link_duplex);
4432 e1000_print_link_info(adapter);
e921eb1a 4433 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4434 * if link has autonegotiated at 10/100 half
4435 */
4436 if ((hw->phy.type == e1000_phy_igp_3 ||
4437 hw->phy.type == e1000_phy_bm) &&
4438 (hw->mac.autoneg == true) &&
4439 (adapter->link_speed == SPEED_10 ||
4440 adapter->link_speed == SPEED_100) &&
4441 (adapter->link_duplex == HALF_DUPLEX)) {
4442 u16 autoneg_exp;
4443
4444 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4445
4446 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4447 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4448 }
4449
f49c57e1 4450 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4451 adapter->tx_timeout_factor = 1;
4452 switch (adapter->link_speed) {
4453 case SPEED_10:
3db1cd5c 4454 txb2b = false;
10f1b492 4455 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4456 break;
4457 case SPEED_100:
3db1cd5c 4458 txb2b = false;
4c86e0b9 4459 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4460 break;
4461 }
4462
e921eb1a 4463 /* workaround: re-program speed mode bit after
ad68076e
BA		 4464 * link-up event
4465 */
bc7f75fa
AK		 4466 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4467 !txb2b) {
4468 u32 tarc0;
e9ec2c0f 4469 tarc0 = er32(TARC(0));
bc7f75fa 4470 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4471 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4472 }
4473
e921eb1a 4474 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4475 * some hardware issues
4476 */
bc7f75fa
AK		 4477 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4478 switch (adapter->link_speed) {
4479 case SPEED_10:
4480 case SPEED_100:
44defeb3 4481 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4482 netdev->features &= ~NETIF_F_TSO;
4483 netdev->features &= ~NETIF_F_TSO6;
4484 break;
4485 case SPEED_1000:
4486 netdev->features |= NETIF_F_TSO;
4487 netdev->features |= NETIF_F_TSO6;
4488 break;
4489 default:
4490 /* oops */
4491 break;
4492 }
4493 }
4494
e921eb1a 4495 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4496 * after setting TARC(0)
4497 */
bc7f75fa
AK		 4498 tctl = er32(TCTL);
4499 tctl |= E1000_TCTL_EN;
4500 ew32(TCTL, tctl);
4501
e921eb1a 4502 /* Perform any post-link-up configuration before
75eb0fad
BA		 4503 * reporting link up.
4504 */
4505 if (phy->ops.cfg_on_link_up)
4506 phy->ops.cfg_on_link_up(hw);
4507
bc7f75fa 4508 netif_carrier_on(netdev);
bc7f75fa
AK		 4509
4510 if (!test_bit(__E1000_DOWN, &adapter->state))
4511 mod_timer(&adapter->phy_info_timer,
4512 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4513 }
4514 } else {
4515 if (netif_carrier_ok(netdev)) {
4516 adapter->link_speed = 0;
4517 adapter->link_duplex = 0;
8f12fe86 4518 /* Link status message must follow this format */
7dbc1672 4519 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4520 netif_carrier_off(netdev);
bc7f75fa
AK		 4521 if (!test_bit(__E1000_DOWN, &adapter->state))
4522 mod_timer(&adapter->phy_info_timer,
4523 round_jiffies(jiffies + 2 * HZ));
4524
12d43f7d
BA		 4525 /* The link is lost so the controller stops DMA.
4526 * If there is queued Tx work that cannot be done
4527 * or if on an 8000ES2LAN which requires a Rx packet
4528 * buffer work-around on link down event, reset the
4529 * controller to flush the Tx/Rx packet buffers.
4530 * (Do the reset outside of interrupt context).
4531 */
4532 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4533 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4534 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4535 else
4536 pm_schedule_suspend(netdev->dev.parent,
4537 LINK_TIMEOUT);
bc7f75fa
AK		 4538 }
4539 }
4540
4541link_up:
67fd4fcb 4542 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4543 e1000e_update_stats(adapter);
4544
4545 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4546 adapter->tpt_old = adapter->stats.tpt;
4547 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4548 adapter->colc_old = adapter->stats.colc;
4549
7c25769f
BA		 4550 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4551 adapter->gorc_old = adapter->stats.gorc;
4552 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4553 adapter->gotc_old = adapter->stats.gotc;
2084b114 4554 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4555
12d43f7d 4556 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4557 schedule_work(&adapter->reset_task);
4558 /* return immediately since reset is imminent */
4559 return;
bc7f75fa
AK		 4560 }
4561
12d43f7d
BA		 4562 e1000e_update_adaptive(&adapter->hw);
4563
eab2abf5
JB		 4564 /* Simple mode for Interrupt Throttle Rate (ITR) */
4565 if (adapter->itr_setting == 4) {
e921eb1a 4566 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4567 * Total asymmetrical Tx or Rx gets ITR=8000;
4568 * everyone else is between 2000-8000.
4569 */
4570 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4571 u32 dif = (adapter->gotc > adapter->gorc ?
4572 adapter->gotc - adapter->gorc :
4573 adapter->gorc - adapter->gotc) / 10000;
4574 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4575
22a4cca2 4576 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4577 }
4578
ad68076e 4579 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4580 if (adapter->msix_entries)
4581 ew32(ICS, adapter->rx_ring->ims_val);
4582 else
4583 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4584
713b3c9e
JB		 4585 /* flush pending descriptors to memory before detecting Tx hang */
4586 e1000e_flush_descriptors(adapter);
4587
bc7f75fa 4588 /* Force detection of hung controller every watchdog period */
3db1cd5c 4589 adapter->detect_tx_hung = true;
bc7f75fa 4590
e921eb1a 4591 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 4592 * reset from the other port. Set the appropriate LAA in RAR[0]
4593 */
bc7f75fa 4594 if (e1000e_get_laa_state_82571(hw))
69e1e019 4595 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 4596
ff10e13c
CW		 4597 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4598 e1000e_check_82574_phy_workaround(adapter);
4599
bc7f75fa
AK		 4600 /* Reset the timer */
4601 if (!test_bit(__E1000_DOWN, &adapter->state))
4602 mod_timer(&adapter->watchdog_timer,
4603 round_jiffies(jiffies + 2 * HZ));
4604}
4605
4606#define E1000_TX_FLAGS_CSUM 0x00000001
4607#define E1000_TX_FLAGS_VLAN 0x00000002
4608#define E1000_TX_FLAGS_TSO 0x00000004
4609#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4610#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4611#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4612#define E1000_TX_FLAGS_VLAN_SHIFT 16
4613
55aa6985 4614static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4615{
bc7f75fa
AK		 4616 struct e1000_context_desc *context_desc;
4617 struct e1000_buffer *buffer_info;
4618 unsigned int i;
4619 u32 cmd_length = 0;
70443ae9 4620 u16 ipcse = 0, mss;
bc7f75fa 4621 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4622
3d5e33c9
BA		 4623 if (!skb_is_gso(skb))
4624 return 0;
bc7f75fa 4625
3d5e33c9 4626 if (skb_header_cloned(skb)) {
90da0669
BA		 4627 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4628
3d5e33c9
BA		 4629 if (err)
4630 return err;
bc7f75fa
AK		 4631 }
4632
3d5e33c9
BA		 4633 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4634 mss = skb_shinfo(skb)->gso_size;
4635 if (skb->protocol == htons(ETH_P_IP)) {
4636 struct iphdr *iph = ip_hdr(skb);
4637 iph->tot_len = 0;
4638 iph->check = 0;
4639 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4640 0, IPPROTO_TCP, 0);
4641 cmd_length = E1000_TXD_CMD_IP;
4642 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4643 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4644 ipv6_hdr(skb)->payload_len = 0;
4645 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4646 &ipv6_hdr(skb)->daddr,
4647 0, IPPROTO_TCP, 0);
4648 ipcse = 0;
4649 }
4650 ipcss = skb_network_offset(skb);
4651 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4652 tucss = skb_transport_offset(skb);
4653 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 4654
4655 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4656 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4657
4658 i = tx_ring->next_to_use;
4659 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4660 buffer_info = &tx_ring->buffer_info[i];
4661
4662 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4663 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4664 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4665 context_desc->upper_setup.tcp_fields.tucss = tucss;
4666 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 4667 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 4668 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4669 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4670 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4671
4672 buffer_info->time_stamp = jiffies;
4673 buffer_info->next_to_watch = i;
4674
4675 i++;
4676 if (i == tx_ring->count)
4677 i = 0;
4678 tx_ring->next_to_use = i;
4679
4680 return 1;
bc7f75fa
AK		 4681}
4682
55aa6985 4683static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4684{
55aa6985 4685 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4686 struct e1000_context_desc *context_desc;
4687 struct e1000_buffer *buffer_info;
4688 unsigned int i;
4689 u8 css;
af807c82 4690 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4691 __be16 protocol;
bc7f75fa 4692
af807c82
DG		 4693 if (skb->ip_summed != CHECKSUM_PARTIAL)
4694 return 0;
bc7f75fa 4695
5f66f208
AJ		 4696 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4697 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4698 else
4699 protocol = skb->protocol;
4700
3f518390 4701 switch (protocol) {
09640e63 4702 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4703 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4704 cmd_len |= E1000_TXD_CMD_TCP;
4705 break;
09640e63 4706 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4707 /* XXX not handling all IPV6 headers */
4708 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4709 cmd_len |= E1000_TXD_CMD_TCP;
4710 break;
4711 default:
4712 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4713 e_warn("checksum_partial proto=%x!\n",
4714 be16_to_cpu(protocol));
af807c82 4715 break;
bc7f75fa
AK		 4716 }
4717
0d0b1672 4718 css = skb_checksum_start_offset(skb);
af807c82
DG		 4719
4720 i = tx_ring->next_to_use;
4721 buffer_info = &tx_ring->buffer_info[i];
4722 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4723
4724 context_desc->lower_setup.ip_config = 0;
4725 context_desc->upper_setup.tcp_fields.tucss = css;
4726 context_desc->upper_setup.tcp_fields.tucso =
4727 css + skb->csum_offset;
4728 context_desc->upper_setup.tcp_fields.tucse = 0;
4729 context_desc->tcp_seg_setup.data = 0;
4730 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4731
4732 buffer_info->time_stamp = jiffies;
4733 buffer_info->next_to_watch = i;
4734
4735 i++;
4736 if (i == tx_ring->count)
4737 i = 0;
4738 tx_ring->next_to_use = i;
4739
4740 return 1;
bc7f75fa
AK		 4741}
4742
55aa6985
BA		 4743static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4744 unsigned int first, unsigned int max_per_txd,
d821a4c4 4745 unsigned int nr_frags)
bc7f75fa 4746{
55aa6985 4747 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4748 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4749 struct e1000_buffer *buffer_info;
8ddc951c 4750 unsigned int len = skb_headlen(skb);
03b1320d 4751 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4752 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4753
4754 i = tx_ring->next_to_use;
4755
4756 while (len) {
1b7719c4 4757 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4758 size = min(len, max_per_txd);
4759
bc7f75fa 4760 buffer_info->length = size;
bc7f75fa 4761 buffer_info->time_stamp = jiffies;
bc7f75fa 4762 buffer_info->next_to_watch = i;
0be3f55f
NN		 4763 buffer_info->dma = dma_map_single(&pdev->dev,
4764 skb->data + offset,
af667a29 4765 size, DMA_TO_DEVICE);
03b1320d 4766 buffer_info->mapped_as_page = false;
0be3f55f 4767 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4768 goto dma_error;
bc7f75fa
AK		 4769
4770 len -= size;
4771 offset += size;
03b1320d 4772 count++;
1b7719c4
AD		 4773
4774 if (len) {
4775 i++;
4776 if (i == tx_ring->count)
4777 i = 0;
4778 }
bc7f75fa
AK		 4779 }
4780
4781 for (f = 0; f < nr_frags; f++) {
9e903e08 4782 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4783
4784 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4785 len = skb_frag_size(frag);
877749bf 4786 offset = 0;
bc7f75fa
AK		 4787
4788 while (len) {
1b7719c4
AD		 4789 i++;
4790 if (i == tx_ring->count)
4791 i = 0;
4792
bc7f75fa
AK		 4793 buffer_info = &tx_ring->buffer_info[i];
4794 size = min(len, max_per_txd);
bc7f75fa
AK		 4795
4796 buffer_info->length = size;
4797 buffer_info->time_stamp = jiffies;
bc7f75fa 4798 buffer_info->next_to_watch = i;
877749bf
IC		 4799 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4800 offset, size, DMA_TO_DEVICE);
03b1320d 4801 buffer_info->mapped_as_page = true;
0be3f55f 4802 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4803 goto dma_error;
bc7f75fa
AK		 4804
4805 len -= size;
4806 offset += size;
4807 count++;
bc7f75fa
AK		 4808 }
4809 }
4810
af667a29 4811 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4812 /* multiply data chunks by size of headers */
4813 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4814
bc7f75fa 4815 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4816 tx_ring->buffer_info[i].segs = segs;
4817 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4818 tx_ring->buffer_info[first].next_to_watch = i;
4819
4820 return count;
03b1320d
AD		 4821
4822dma_error:
af667a29 4823 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4824 buffer_info->dma = 0;
c1fa347f 4825 if (count)
03b1320d 4826 count--;
c1fa347f
RK		 4827
4828 while (count--) {
af667a29 4829 if (i == 0)
03b1320d 4830 i += tx_ring->count;
c1fa347f 4831 i--;
03b1320d 4832 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4833 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4834 }
4835
4836 return 0;
bc7f75fa
AK		 4837}
4838
55aa6985 4839static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4840{
55aa6985 4841 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4842 struct e1000_tx_desc *tx_desc = NULL;
4843 struct e1000_buffer *buffer_info;
4844 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4845 unsigned int i;
4846
4847 if (tx_flags & E1000_TX_FLAGS_TSO) {
4848 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4849 E1000_TXD_CMD_TSE;
4850 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4851
4852 if (tx_flags & E1000_TX_FLAGS_IPV4)
4853 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4854 }
4855
4856 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4857 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4858 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4859 }
4860
4861 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4862 txd_lower |= E1000_TXD_CMD_VLE;
4863 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4864 }
4865
943146de
BG		 4866 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4867 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4868
bc7f75fa
AK		 4869 i = tx_ring->next_to_use;
4870
36b973df 4871 do {
bc7f75fa
AK		 4872 buffer_info = &tx_ring->buffer_info[i];
4873 tx_desc = E1000_TX_DESC(*tx_ring, i);
4874 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4875 tx_desc->lower.data =
4876 cpu_to_le32(txd_lower | buffer_info->length);
4877 tx_desc->upper.data = cpu_to_le32(txd_upper);
4878
4879 i++;
4880 if (i == tx_ring->count)
4881 i = 0;
36b973df 4882 } while (--count > 0);
bc7f75fa
AK		 4883
4884 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4885
943146de
BG		 4886 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4887 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4888 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4889
e921eb1a 4890 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 4891 * know there are new descriptors to fetch. (Only
4892 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4893 * such as IA-64).
4894 */
bc7f75fa
AK		 4895 wmb();
4896
4897 tx_ring->next_to_use = i;
c6e7f51e
BA		 4898
4899 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4900 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4901 else
c5083cf6 4902 writel(i, tx_ring->tail);
c6e7f51e 4903
e921eb1a 4904 /* we need this if more than one processor can write to our tail
ad68076e
BA		 4905 * at a time, it synchronizes IO on IA64/Altix systems
4906 */
bc7f75fa
AK		 4907 mmiowb();
4908}
4909
4910#define MINIMUM_DHCP_PACKET_SIZE 282
4911static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4912 struct sk_buff *skb)
4913{
4914 struct e1000_hw *hw = &adapter->hw;
4915 u16 length, offset;
4916
d60923c4
BA		 4917 if (vlan_tx_tag_present(skb) &&
4918 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4919 (adapter->hw.mng_cookie.status &
4920 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4921 return 0;
bc7f75fa
AK		 4922
4923 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4924 return 0;
4925
4926 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4927 return 0;
4928
4929 {
4930 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4931 struct udphdr *udp;
4932
4933 if (ip->protocol != IPPROTO_UDP)
4934 return 0;
4935
4936 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4937 if (ntohs(udp->dest) != 67)
4938 return 0;
4939
4940 offset = (u8 *)udp + 8 - skb->data;
4941 length = skb->len - offset;
4942 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4943 }
4944
4945 return 0;
4946}
4947
55aa6985 4948static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4949{
55aa6985 4950 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4951
55aa6985 4952 netif_stop_queue(adapter->netdev);
e921eb1a 4953 /* Herbert's original patch had:
bc7f75fa 4954 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4955 * but since that doesn't exist yet, just open code it.
4956 */
bc7f75fa
AK		 4957 smp_mb();
4958
e921eb1a 4959 /* We need to check again in a case another CPU has just
ad68076e
BA		 4960 * made room available.
4961 */
55aa6985 4962 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 4963 return -EBUSY;
4964
4965 /* A reprieve! */
55aa6985 4966 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 4967 ++adapter->restart_queue;
4968 return 0;
4969}
4970
55aa6985 4971static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4972{
d821a4c4
BA		 4973 BUG_ON(size > tx_ring->count);
4974
55aa6985 4975 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 4976 return 0;
55aa6985 4977 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 4978}
4979
3b29a56d
SH		 4980static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
4981 struct net_device *netdev)
bc7f75fa
AK		 4982{
4983 struct e1000_adapter *adapter = netdev_priv(netdev);
4984 struct e1000_ring *tx_ring = adapter->tx_ring;
4985 unsigned int first;
bc7f75fa 4986 unsigned int tx_flags = 0;
e743d313 4987 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 4988 unsigned int nr_frags;
4989 unsigned int mss;
bc7f75fa
AK		 4990 int count = 0;
4991 int tso;
4992 unsigned int f;
bc7f75fa
AK		 4993
4994 if (test_bit(__E1000_DOWN, &adapter->state)) {
4995 dev_kfree_skb_any(skb);
4996 return NETDEV_TX_OK;
4997 }
4998
4999 if (skb->len <= 0) {
5000 dev_kfree_skb_any(skb);
5001 return NETDEV_TX_OK;
5002 }
5003
e921eb1a 5004 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5005 * pad skb in order to meet this minimum size requirement
5006 */
5007 if (unlikely(skb->len < 17)) {
5008 if (skb_pad(skb, 17 - skb->len))
5009 return NETDEV_TX_OK;
5010 skb->len = 17;
5011 skb_set_tail_pointer(skb, 17);
5012 }
5013
bc7f75fa 5014 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5015 if (mss) {
5016 u8 hdr_len;
bc7f75fa 5017
e921eb1a 5018 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5019 * points to just header, pull a few bytes of payload from
5020 * frags into skb->data
5021 */
bc7f75fa 5022 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5023 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5024 * avoiding it could save a lot of cycles
5025 */
4e6c709c 5026 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5027 unsigned int pull_size;
5028
a2a5b323 5029 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5030 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5031 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5032 dev_kfree_skb_any(skb);
5033 return NETDEV_TX_OK;
5034 }
e743d313 5035 len = skb_headlen(skb);
bc7f75fa
AK		 5036 }
5037 }
5038
5039 /* reserve a descriptor for the offload context */
5040 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5041 count++;
5042 count++;
5043
d821a4c4 5044 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5045
5046 nr_frags = skb_shinfo(skb)->nr_frags;
5047 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5048 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5049 adapter->tx_fifo_limit);
bc7f75fa
AK		 5050
5051 if (adapter->hw.mac.tx_pkt_filtering)
5052 e1000_transfer_dhcp_info(adapter, skb);
5053
e921eb1a 5054 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5055 * head, otherwise try next time
5056 */
55aa6985 5057 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5058 return NETDEV_TX_BUSY;
bc7f75fa 5059
eab6d18d 5060 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5061 tx_flags |= E1000_TX_FLAGS_VLAN;
5062 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5063 }
5064
5065 first = tx_ring->next_to_use;
5066
55aa6985 5067 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5068 if (tso < 0) {
5069 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5070 return NETDEV_TX_OK;
5071 }
5072
5073 if (tso)
5074 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5075 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5076 tx_flags |= E1000_TX_FLAGS_CSUM;
5077
e921eb1a 5078 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5079 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5080 * no longer assume, we must.
5081 */
bc7f75fa
AK		 5082 if (skb->protocol == htons(ETH_P_IP))
5083 tx_flags |= E1000_TX_FLAGS_IPV4;
5084
943146de
BG		 5085 if (unlikely(skb->no_fcs))
5086 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5087
25985edc 5088 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5089 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5090 nr_frags);
1b7719c4 5091 if (count) {
80be3129
WB		 5092 skb_tx_timestamp(skb);
5093
3f0cfa3b 5094 netdev_sent_queue(netdev, skb->len);
55aa6985 5095 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5096 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5097 e1000_maybe_stop_tx(tx_ring,
5098 (MAX_SKB_FRAGS *
5099 DIV_ROUND_UP(PAGE_SIZE,
5100 adapter->tx_fifo_limit) + 2));
1b7719c4 5101 } else {
bc7f75fa 5102 dev_kfree_skb_any(skb);
1b7719c4
AD		 5103 tx_ring->buffer_info[first].time_stamp = 0;
5104 tx_ring->next_to_use = first;
bc7f75fa
AK		 5105 }
5106
bc7f75fa
AK		 5107 return NETDEV_TX_OK;
5108}
5109
5110/**
5111 * e1000_tx_timeout - Respond to a Tx Hang
5112 * @netdev: network interface device structure
5113 **/
5114static void e1000_tx_timeout(struct net_device *netdev)
5115{
5116 struct e1000_adapter *adapter = netdev_priv(netdev);
5117
5118 /* Do the reset outside of interrupt context */
5119 adapter->tx_timeout_count++;
5120 schedule_work(&adapter->reset_task);
5121}
5122
5123static void e1000_reset_task(struct work_struct *work)
5124{
5125 struct e1000_adapter *adapter;
5126 adapter = container_of(work, struct e1000_adapter, reset_task);
5127
615b32af
JB		 5128 /* don't run the task if already down */
5129 if (test_bit(__E1000_DOWN, &adapter->state))
5130 return;
5131
12d43f7d 5132 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5133 e1000e_dump(adapter);
12d43f7d 5134 e_err("Reset adapter unexpectedly\n");
affa9dfb 5135 }
bc7f75fa
AK		 5136 e1000e_reinit_locked(adapter);
5137}
5138
5139/**
67fd4fcb 5140 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5141 * @netdev: network interface device structure
67fd4fcb 5142 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5143 *
5144 * Returns the address of the device statistics structure.
bc7f75fa 5145 **/
67fd4fcb
JK		 5146struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5147 struct rtnl_link_stats64 *stats)
bc7f75fa 5148{
67fd4fcb
JK		 5149 struct e1000_adapter *adapter = netdev_priv(netdev);
5150
5151 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5152 spin_lock(&adapter->stats64_lock);
5153 e1000e_update_stats(adapter);
5154 /* Fill out the OS statistics structure */
5155 stats->rx_bytes = adapter->stats.gorc;
5156 stats->rx_packets = adapter->stats.gprc;
5157 stats->tx_bytes = adapter->stats.gotc;
5158 stats->tx_packets = adapter->stats.gptc;
5159 stats->multicast = adapter->stats.mprc;
5160 stats->collisions = adapter->stats.colc;
5161
5162 /* Rx Errors */
5163
e921eb1a 5164 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5165 * our own version based on RUC and ROC
5166 */
5167 stats->rx_errors = adapter->stats.rxerrc +
5168 adapter->stats.crcerrs + adapter->stats.algnerrc +
5169 adapter->stats.ruc + adapter->stats.roc +
5170 adapter->stats.cexterr;
5171 stats->rx_length_errors = adapter->stats.ruc +
5172 adapter->stats.roc;
5173 stats->rx_crc_errors = adapter->stats.crcerrs;
5174 stats->rx_frame_errors = adapter->stats.algnerrc;
5175 stats->rx_missed_errors = adapter->stats.mpc;
5176
5177 /* Tx Errors */
5178 stats->tx_errors = adapter->stats.ecol +
5179 adapter->stats.latecol;
5180 stats->tx_aborted_errors = adapter->stats.ecol;
5181 stats->tx_window_errors = adapter->stats.latecol;
5182 stats->tx_carrier_errors = adapter->stats.tncrs;
5183
5184 /* Tx Dropped needs to be maintained elsewhere */
5185
5186 spin_unlock(&adapter->stats64_lock);
5187 return stats;
bc7f75fa
AK		 5188}
5189
5190/**
5191 * e1000_change_mtu - Change the Maximum Transfer Unit
5192 * @netdev: network interface device structure
5193 * @new_mtu: new value for maximum frame size
5194 *
5195 * Returns 0 on success, negative on failure
5196 **/
5197static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5198{
5199 struct e1000_adapter *adapter = netdev_priv(netdev);
5200 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5201
2adc55c9 5202 /* Jumbo frame support */
2e1706f2
BA		 5203 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5204 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5205 e_err("Jumbo Frames not supported.\n");
5206 return -EINVAL;
bc7f75fa
AK		 5207 }
5208
2adc55c9
BA		 5209 /* Supported frame sizes */
5210 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5211 (max_frame > adapter->max_hw_frame_size)) {
5212 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5213 return -EINVAL;
5214 }
5215
2fbe4526
BA		 5216 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5217 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5218 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5219 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5220 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5221 return -EINVAL;
5222 }
5223
bc7f75fa 5224 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5225 usleep_range(1000, 2000);
610c9928 5226 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5227 adapter->max_frame_size = max_frame;
610c9928
BA		 5228 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5229 netdev->mtu = new_mtu;
bc7f75fa
AK		 5230 if (netif_running(netdev))
5231 e1000e_down(adapter);
5232
e921eb1a 5233 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5234 * means we reserve 2 more, this pushes us to allocate from the next
5235 * larger slab size.
ad68076e 5236 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5237 * However with the new *_jumbo_rx* routines, jumbo receives will use
5238 * fragmented skbs
ad68076e 5239 */
bc7f75fa 5240
9926146b 5241 if (max_frame <= 2048)
bc7f75fa
AK		 5242 adapter->rx_buffer_len = 2048;
5243 else
5244 adapter->rx_buffer_len = 4096;
5245
5246 /* adjust allocation if LPE protects us, and we aren't using SBP */
5247 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5248 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5249 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5250 + ETH_FCS_LEN;
bc7f75fa 5251
bc7f75fa
AK		 5252 if (netif_running(netdev))
5253 e1000e_up(adapter);
5254 else
5255 e1000e_reset(adapter);
5256
5257 clear_bit(__E1000_RESETTING, &adapter->state);
5258
5259 return 0;
5260}
5261
5262static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5263 int cmd)
5264{
5265 struct e1000_adapter *adapter = netdev_priv(netdev);
5266 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5267
318a94d6 5268 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5269 return -EOPNOTSUPP;
5270
5271 switch (cmd) {
5272 case SIOCGMIIPHY:
5273 data->phy_id = adapter->hw.phy.addr;
5274 break;
5275 case SIOCGMIIREG:
b16a002e
BA		 5276 e1000_phy_read_status(adapter);
5277
7c25769f
BA		 5278 switch (data->reg_num & 0x1F) {
5279 case MII_BMCR:
5280 data->val_out = adapter->phy_regs.bmcr;
5281 break;
5282 case MII_BMSR:
5283 data->val_out = adapter->phy_regs.bmsr;
5284 break;
5285 case MII_PHYSID1:
5286 data->val_out = (adapter->hw.phy.id >> 16);
5287 break;
5288 case MII_PHYSID2:
5289 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5290 break;
5291 case MII_ADVERTISE:
5292 data->val_out = adapter->phy_regs.advertise;
5293 break;
5294 case MII_LPA:
5295 data->val_out = adapter->phy_regs.lpa;
5296 break;
5297 case MII_EXPANSION:
5298 data->val_out = adapter->phy_regs.expansion;
5299 break;
5300 case MII_CTRL1000:
5301 data->val_out = adapter->phy_regs.ctrl1000;
5302 break;
5303 case MII_STAT1000:
5304 data->val_out = adapter->phy_regs.stat1000;
5305 break;
5306 case MII_ESTATUS:
5307 data->val_out = adapter->phy_regs.estatus;
5308 break;
5309 default:
bc7f75fa
AK		 5310 return -EIO;
5311 }
bc7f75fa
AK		 5312 break;
5313 case SIOCSMIIREG:
5314 default:
5315 return -EOPNOTSUPP;
5316 }
5317 return 0;
5318}
5319
5320static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5321{
5322 switch (cmd) {
5323 case SIOCGMIIPHY:
5324 case SIOCGMIIREG:
5325 case SIOCSMIIREG:
5326 return e1000_mii_ioctl(netdev, ifr, cmd);
5327 default:
5328 return -EOPNOTSUPP;
5329 }
5330}
5331
a4f58f54
BA		 5332static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5333{
5334 struct e1000_hw *hw = &adapter->hw;
5335 u32 i, mac_reg;
2b6b168d 5336 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5337 int retval = 0;
5338
5339 /* copy MAC RARs to PHY RARs */
d3738bb8 5340 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5341
2b6b168d
BA		 5342 retval = hw->phy.ops.acquire(hw);
5343 if (retval) {
5344 e_err("Could not acquire PHY\n");
5345 return retval;
5346 }
5347
5348 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5349 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5350 if (retval)
75ce1532 5351 goto release;
2b6b168d
BA		 5352
5353 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5354 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5355 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5356 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5357 (u16)(mac_reg & 0xFFFF));
5358 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5359 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5360 }
5361
5362 /* configure PHY Rx Control register */
2b6b168d 5363 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5364 mac_reg = er32(RCTL);
5365 if (mac_reg & E1000_RCTL_UPE)
5366 phy_reg |= BM_RCTL_UPE;
5367 if (mac_reg & E1000_RCTL_MPE)
5368 phy_reg |= BM_RCTL_MPE;
5369 phy_reg &= ~(BM_RCTL_MO_MASK);
5370 if (mac_reg & E1000_RCTL_MO_3)
5371 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5372 << BM_RCTL_MO_SHIFT);
5373 if (mac_reg & E1000_RCTL_BAM)
5374 phy_reg |= BM_RCTL_BAM;
5375 if (mac_reg & E1000_RCTL_PMCF)
5376 phy_reg |= BM_RCTL_PMCF;
5377 mac_reg = er32(CTRL);
5378 if (mac_reg & E1000_CTRL_RFCE)
5379 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5380 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5381
5382 /* enable PHY wakeup in MAC register */
5383 ew32(WUFC, wufc);
5384 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5385
5386 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5387 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5388 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5389
5390 /* activate PHY wakeup */
2b6b168d
BA		 5391 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5392 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5393 if (retval)
5394 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5395release:
94d8186a 5396 hw->phy.ops.release(hw);
a4f58f54
BA		 5397
5398 return retval;
5399}
5400
23606cf5
RW		 5401static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5402 bool runtime)
bc7f75fa
AK		 5403{
5404 struct net_device *netdev = pci_get_drvdata(pdev);
5405 struct e1000_adapter *adapter = netdev_priv(netdev);
5406 struct e1000_hw *hw = &adapter->hw;
5407 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5408 /* Runtime suspend should only enable wakeup for link changes */
5409 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5410 int retval = 0;
5411
5412 netif_device_detach(netdev);
5413
5414 if (netif_running(netdev)) {
bb9e44d0
BA		 5415 int count = E1000_CHECK_RESET_COUNT;
5416
5417 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5418 usleep_range(10000, 20000);
5419
bc7f75fa
AK		 5420 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5421 e1000e_down(adapter);
5422 e1000_free_irq(adapter);
5423 }
4662e82b 5424 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5425
5426 retval = pci_save_state(pdev);
5427 if (retval)
5428 return retval;
5429
5430 status = er32(STATUS);
5431 if (status & E1000_STATUS_LU)
5432 wufc &= ~E1000_WUFC_LNKC;
5433
5434 if (wufc) {
5435 e1000_setup_rctl(adapter);
ef9b965a 5436 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5437
5438 /* turn on all-multi mode if wake on multicast is enabled */
5439 if (wufc & E1000_WUFC_MC) {
5440 rctl = er32(RCTL);
5441 rctl |= E1000_RCTL_MPE;
5442 ew32(RCTL, rctl);
5443 }
5444
5445 ctrl = er32(CTRL);
5446 /* advertise wake from D3Cold */
5447 #define E1000_CTRL_ADVD3WUC 0x00100000
5448 /* phy power management enable */
5449 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5450 ctrl |= E1000_CTRL_ADVD3WUC;
5451 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5452 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5453 ew32(CTRL, ctrl);
5454
318a94d6
JK		 5455 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5456 adapter->hw.phy.media_type ==
5457 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5458 /* keep the laser running in D3 */
5459 ctrl_ext = er32(CTRL_EXT);
93a23f48 5460 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5461 ew32(CTRL_EXT, ctrl_ext);
5462 }
5463
97ac8cae 5464 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5465 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5466
bc7f75fa
AK		 5467 /* Allow time for pending master requests to run */
5468 e1000e_disable_pcie_master(&adapter->hw);
5469
82776a4b 5470 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5471 /* enable wakeup by the PHY */
5472 retval = e1000_init_phy_wakeup(adapter, wufc);
5473 if (retval)
5474 return retval;
5475 } else {
5476 /* enable wakeup by the MAC */
5477 ew32(WUFC, wufc);
5478 ew32(WUC, E1000_WUC_PME_EN);
5479 }
bc7f75fa
AK		 5480 } else {
5481 ew32(WUC, 0);
5482 ew32(WUFC, 0);
bc7f75fa
AK		 5483 }
5484
4f9de721
RW		 5485 *enable_wake = !!wufc;
5486
bc7f75fa 5487 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5488 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5489 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5490 *enable_wake = true;
bc7f75fa
AK		 5491
5492 if (adapter->hw.phy.type == e1000_phy_igp_3)
5493 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5494
e921eb1a 5495 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5496 * would have already happened in close and is redundant.
5497 */
31dbe5b4 5498 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5499
5500 pci_disable_device(pdev);
5501
4f9de721
RW		 5502 return 0;
5503}
5504
5505static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5506{
5507 if (sleep && wake) {
5508 pci_prepare_to_sleep(pdev);
5509 return;
5510 }
5511
5512 pci_wake_from_d3(pdev, wake);
5513 pci_set_power_state(pdev, PCI_D3hot);
5514}
5515
5516static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5517 bool wake)
5518{
5519 struct net_device *netdev = pci_get_drvdata(pdev);
5520 struct e1000_adapter *adapter = netdev_priv(netdev);
5521
e921eb1a 5522 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 5523 * correctable error when the MAC transitions from D0 to D3. To
5524 * prevent this we need to mask off the correctable errors on the
5525 * downstream port of the pci-e switch.
5526 */
5527 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5528 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 5529 u16 devctl;
5530
f8c0fcac
JL		 5531 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
5532 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
5533 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 5534
4f9de721 5535 e1000_power_off(pdev, sleep, wake);
005cbdfc 5536
f8c0fcac 5537 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 5538 } else {
4f9de721 5539 e1000_power_off(pdev, sleep, wake);
005cbdfc 5540 }
bc7f75fa
AK		 5541}
5542
6f461f6c
BA		 5543#ifdef CONFIG_PCIEASPM
5544static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5545{
9f728f53 5546 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5547}
5548#else
5549static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 5550{
e921eb1a 5551 /* Both device and parent should have the same ASPM setting.
6f461f6c 5552 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5553 */
f8c0fcac 5554 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
0c75ba22 5555
f8c0fcac
JL		 5556 if (pdev->bus->self)
5557 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
5558 state);
6f461f6c
BA		 5559}
5560#endif
78cd29d5 5561static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5562{
5563 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5564 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5565 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5566
5567 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5568}
5569
aa338601 5570#ifdef CONFIG_PM
23606cf5 5571static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5572{
23606cf5 5573 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5574}
5575
23606cf5 5576static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5577{
5578 struct net_device *netdev = pci_get_drvdata(pdev);
5579 struct e1000_adapter *adapter = netdev_priv(netdev);
5580 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5581 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5582 u32 err;
5583
78cd29d5
BA		 5584 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5585 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5586 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5587 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5588 if (aspm_disable_flag)
5589 e1000e_disable_aspm(pdev, aspm_disable_flag);
5590
bc7f75fa
AK		 5591 pci_set_power_state(pdev, PCI_D0);
5592 pci_restore_state(pdev);
28b8f04a 5593 pci_save_state(pdev);
6e4f6f6b 5594
4662e82b 5595 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5596 if (netif_running(netdev)) {
5597 err = e1000_request_irq(adapter);
5598 if (err)
5599 return err;
5600 }
5601
2fbe4526 5602 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 5603 e1000_resume_workarounds_pchlan(&adapter->hw);
5604
bc7f75fa 5605 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5606
5607 /* report the system wakeup cause from S3/S4 */
5608 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5609 u16 phy_data;
5610
5611 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5612 if (phy_data) {
5613 e_info("PHY Wakeup cause - %s\n",
5614 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5615 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5616 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5617 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5618 phy_data & E1000_WUS_LNKC ?
5619 "Link Status Change" : "other");
a4f58f54
BA		 5620 }
5621 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5622 } else {
5623 u32 wus = er32(WUS);
5624 if (wus) {
5625 e_info("MAC Wakeup cause - %s\n",
5626 wus & E1000_WUS_EX ? "Unicast Packet" :
5627 wus & E1000_WUS_MC ? "Multicast Packet" :
5628 wus & E1000_WUS_BC ? "Broadcast Packet" :
5629 wus & E1000_WUS_MAG ? "Magic Packet" :
5630 wus & E1000_WUS_LNKC ? "Link Status Change" :
5631 "other");
5632 }
5633 ew32(WUS, ~0);
5634 }
5635
bc7f75fa 5636 e1000e_reset(adapter);
bc7f75fa 5637
cd791618 5638 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5639
5640 if (netif_running(netdev))
5641 e1000e_up(adapter);
5642
5643 netif_device_attach(netdev);
5644
e921eb1a 5645 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5646 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5647 * under the control of the driver.
5648 */
c43bc57e 5649 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5650 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5651
5652 return 0;
5653}
23606cf5 5654
a0340162
RW		 5655#ifdef CONFIG_PM_SLEEP
5656static int e1000_suspend(struct device *dev)
5657{
5658 struct pci_dev *pdev = to_pci_dev(dev);
5659 int retval;
5660 bool wake;
5661
5662 retval = __e1000_shutdown(pdev, &wake, false);
5663 if (!retval)
5664 e1000_complete_shutdown(pdev, true, wake);
5665
5666 return retval;
5667}
5668
23606cf5
RW		 5669static int e1000_resume(struct device *dev)
5670{
5671 struct pci_dev *pdev = to_pci_dev(dev);
5672 struct net_device *netdev = pci_get_drvdata(pdev);
5673 struct e1000_adapter *adapter = netdev_priv(netdev);
5674
5675 if (e1000e_pm_ready(adapter))
5676 adapter->idle_check = true;
5677
5678 return __e1000_resume(pdev);
5679}
a0340162
RW		 5680#endif /* CONFIG_PM_SLEEP */
5681
5682#ifdef CONFIG_PM_RUNTIME
5683static int e1000_runtime_suspend(struct device *dev)
5684{
5685 struct pci_dev *pdev = to_pci_dev(dev);
5686 struct net_device *netdev = pci_get_drvdata(pdev);
5687 struct e1000_adapter *adapter = netdev_priv(netdev);
5688
5689 if (e1000e_pm_ready(adapter)) {
5690 bool wake;
5691
5692 __e1000_shutdown(pdev, &wake, true);
5693 }
5694
5695 return 0;
5696}
5697
5698static int e1000_idle(struct device *dev)
5699{
5700 struct pci_dev *pdev = to_pci_dev(dev);
5701 struct net_device *netdev = pci_get_drvdata(pdev);
5702 struct e1000_adapter *adapter = netdev_priv(netdev);
5703
5704 if (!e1000e_pm_ready(adapter))
5705 return 0;
5706
5707 if (adapter->idle_check) {
5708 adapter->idle_check = false;
5709 if (!e1000e_has_link(adapter))
5710 pm_schedule_suspend(dev, MSEC_PER_SEC);
5711 }
5712
5713 return -EBUSY;
5714}
23606cf5
RW		 5715
5716static int e1000_runtime_resume(struct device *dev)
5717{
5718 struct pci_dev *pdev = to_pci_dev(dev);
5719 struct net_device *netdev = pci_get_drvdata(pdev);
5720 struct e1000_adapter *adapter = netdev_priv(netdev);
5721
5722 if (!e1000e_pm_ready(adapter))
5723 return 0;
5724
5725 adapter->idle_check = !dev->power.runtime_auto;
5726 return __e1000_resume(pdev);
5727}
a0340162 5728#endif /* CONFIG_PM_RUNTIME */
aa338601 5729#endif /* CONFIG_PM */
bc7f75fa
AK		 5730
5731static void e1000_shutdown(struct pci_dev *pdev)
5732{
4f9de721
RW		 5733 bool wake = false;
5734
23606cf5 5735 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5736
5737 if (system_state == SYSTEM_POWER_OFF)
5738 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5739}
5740
5741#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5742
5743static irqreturn_t e1000_intr_msix(int irq, void *data)
5744{
5745 struct net_device *netdev = data;
5746 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5747
5748 if (adapter->msix_entries) {
90da0669
BA		 5749 int vector, msix_irq;
5750
147b2c8c
DD		 5751 vector = 0;
5752 msix_irq = adapter->msix_entries[vector].vector;
5753 disable_irq(msix_irq);
5754 e1000_intr_msix_rx(msix_irq, netdev);
5755 enable_irq(msix_irq);
5756
5757 vector++;
5758 msix_irq = adapter->msix_entries[vector].vector;
5759 disable_irq(msix_irq);
5760 e1000_intr_msix_tx(msix_irq, netdev);
5761 enable_irq(msix_irq);
5762
5763 vector++;
5764 msix_irq = adapter->msix_entries[vector].vector;
5765 disable_irq(msix_irq);
5766 e1000_msix_other(msix_irq, netdev);
5767 enable_irq(msix_irq);
5768 }
5769
5770 return IRQ_HANDLED;
5771}
5772
e921eb1a
BA		 5773/**
5774 * e1000_netpoll
5775 * @netdev: network interface device structure
5776 *
bc7f75fa
AK		 5777 * Polling 'interrupt' - used by things like netconsole to send skbs
5778 * without having to re-enable interrupts. It's not called while
5779 * the interrupt routine is executing.
5780 */
5781static void e1000_netpoll(struct net_device *netdev)
5782{
5783 struct e1000_adapter *adapter = netdev_priv(netdev);
5784
147b2c8c
DD		 5785 switch (adapter->int_mode) {
5786 case E1000E_INT_MODE_MSIX:
5787 e1000_intr_msix(adapter->pdev->irq, netdev);
5788 break;
5789 case E1000E_INT_MODE_MSI:
5790 disable_irq(adapter->pdev->irq);
5791 e1000_intr_msi(adapter->pdev->irq, netdev);
5792 enable_irq(adapter->pdev->irq);
5793 break;
5794 default: /* E1000E_INT_MODE_LEGACY */
5795 disable_irq(adapter->pdev->irq);
5796 e1000_intr(adapter->pdev->irq, netdev);
5797 enable_irq(adapter->pdev->irq);
5798 break;
5799 }
bc7f75fa
AK		 5800}
5801#endif
5802
5803/**
5804 * e1000_io_error_detected - called when PCI error is detected
5805 * @pdev: Pointer to PCI device
5806 * @state: The current pci connection state
5807 *
5808 * This function is called after a PCI bus error affecting
5809 * this device has been detected.
5810 */
5811static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5812 pci_channel_state_t state)
5813{
5814 struct net_device *netdev = pci_get_drvdata(pdev);
5815 struct e1000_adapter *adapter = netdev_priv(netdev);
5816
5817 netif_device_detach(netdev);
5818
c93b5a76
MM		 5819 if (state == pci_channel_io_perm_failure)
5820 return PCI_ERS_RESULT_DISCONNECT;
5821
bc7f75fa
AK		 5822 if (netif_running(netdev))
5823 e1000e_down(adapter);
5824 pci_disable_device(pdev);
5825
5826 /* Request a slot slot reset. */
5827 return PCI_ERS_RESULT_NEED_RESET;
5828}
5829
5830/**
5831 * e1000_io_slot_reset - called after the pci bus has been reset.
5832 * @pdev: Pointer to PCI device
5833 *
5834 * Restart the card from scratch, as if from a cold-boot. Implementation
5835 * resembles the first-half of the e1000_resume routine.
5836 */
5837static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5838{
5839 struct net_device *netdev = pci_get_drvdata(pdev);
5840 struct e1000_adapter *adapter = netdev_priv(netdev);
5841 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5842 u16 aspm_disable_flag = 0;
6e4f6f6b 5843 int err;
111b9dc5 5844 pci_ers_result_t result;
bc7f75fa 5845
78cd29d5
BA		 5846 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5847 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5848 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5849 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5850 if (aspm_disable_flag)
5851 e1000e_disable_aspm(pdev, aspm_disable_flag);
5852
f0f422e5 5853 err = pci_enable_device_mem(pdev);
6e4f6f6b 5854 if (err) {
bc7f75fa
AK		 5855 dev_err(&pdev->dev,
5856 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5857 result = PCI_ERS_RESULT_DISCONNECT;
5858 } else {
5859 pci_set_master(pdev);
23606cf5 5860 pdev->state_saved = true;
111b9dc5 5861 pci_restore_state(pdev);
bc7f75fa 5862
111b9dc5
JB		 5863 pci_enable_wake(pdev, PCI_D3hot, 0);
5864 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5865
111b9dc5
JB		 5866 e1000e_reset(adapter);
5867 ew32(WUS, ~0);
5868 result = PCI_ERS_RESULT_RECOVERED;
5869 }
bc7f75fa 5870
111b9dc5
JB		 5871 pci_cleanup_aer_uncorrect_error_status(pdev);
5872
5873 return result;
bc7f75fa
AK		 5874}
5875
5876/**
5877 * e1000_io_resume - called when traffic can start flowing again.
5878 * @pdev: Pointer to PCI device
5879 *
5880 * This callback is called when the error recovery driver tells us that
5881 * its OK to resume normal operation. Implementation resembles the
5882 * second-half of the e1000_resume routine.
5883 */
5884static void e1000_io_resume(struct pci_dev *pdev)
5885{
5886 struct net_device *netdev = pci_get_drvdata(pdev);
5887 struct e1000_adapter *adapter = netdev_priv(netdev);
5888
cd791618 5889 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5890
5891 if (netif_running(netdev)) {
5892 if (e1000e_up(adapter)) {
5893 dev_err(&pdev->dev,
5894 "can't bring device back up after reset\n");
5895 return;
5896 }
5897 }
5898
5899 netif_device_attach(netdev);
5900
e921eb1a 5901 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5902 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5903 * under the control of the driver.
5904 */
c43bc57e 5905 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5906 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5907
5908}
5909
5910static void e1000_print_device_info(struct e1000_adapter *adapter)
5911{
5912 struct e1000_hw *hw = &adapter->hw;
5913 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5914 u32 ret_val;
5915 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5916
5917 /* print bus type/speed/width info */
a5cc7642 5918 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5919 /* bus width */
5920 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5921 "Width x1"),
5922 /* MAC address */
7c510e4b 5923 netdev->dev_addr);
44defeb3
JK		 5924 e_info("Intel(R) PRO/%s Network Connection\n",
5925 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5926 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5927 E1000_PBANUM_LENGTH);
5928 if (ret_val)
f2315bf1 5929 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 5930 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5931 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5932}
5933
10aa4c04
AK		 5934static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5935{
5936 struct e1000_hw *hw = &adapter->hw;
5937 int ret_val;
5938 u16 buf = 0;
5939
5940 if (hw->mac.type != e1000_82573)
5941 return;
5942
5943 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 5944 le16_to_cpus(&buf);
5945 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 5946 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5947 dev_warn(&adapter->pdev->dev,
5948 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5949 }
10aa4c04
AK		 5950}
5951
c8f44aff 5952static int e1000_set_features(struct net_device *netdev,
70495a50 5953 netdev_features_t features)
dc221294
BA		 5954{
5955 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 5956 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 5957
5958 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
5959 adapter->flags |= FLAG_TSO_FORCE;
5960
5961 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 5962 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
5963 NETIF_F_RXALL)))
dc221294
BA		 5964 return 0;
5965
0184039a
BG		 5966 if (changed & NETIF_F_RXFCS) {
5967 if (features & NETIF_F_RXFCS) {
5968 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
5969 } else {
5970 /* We need to take it back to defaults, which might mean
5971 * stripping is still disabled at the adapter level.
5972 */
5973 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
5974 adapter->flags2 |= FLAG2_CRC_STRIPPING;
5975 else
5976 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
5977 }
5978 }
5979
70495a50
BA		 5980 netdev->features = features;
5981
dc221294
BA		 5982 if (netif_running(netdev))
5983 e1000e_reinit_locked(adapter);
5984 else
5985 e1000e_reset(adapter);
5986
5987 return 0;
5988}
5989
651c2466
SH		 5990static const struct net_device_ops e1000e_netdev_ops = {
5991 .ndo_open = e1000_open,
5992 .ndo_stop = e1000_close,
00829823 5993 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 5994 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 5995 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 5996 .ndo_set_mac_address = e1000_set_mac,
5997 .ndo_change_mtu = e1000_change_mtu,
5998 .ndo_do_ioctl = e1000_ioctl,
5999 .ndo_tx_timeout = e1000_tx_timeout,
6000 .ndo_validate_addr = eth_validate_addr,
6001
651c2466
SH		 6002 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6003 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6004#ifdef CONFIG_NET_POLL_CONTROLLER
6005 .ndo_poll_controller = e1000_netpoll,
6006#endif
dc221294 6007 .ndo_set_features = e1000_set_features,
651c2466
SH		 6008};
6009
bc7f75fa
AK		 6010/**
6011 * e1000_probe - Device Initialization Routine
6012 * @pdev: PCI device information struct
6013 * @ent: entry in e1000_pci_tbl
6014 *
6015 * Returns 0 on success, negative on failure
6016 *
6017 * e1000_probe initializes an adapter identified by a pci_dev structure.
6018 * The OS initialization, configuring of the adapter private structure,
6019 * and a hardware reset occur.
6020 **/
1dd06ae8 6021static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6022{
6023 struct net_device *netdev;
6024 struct e1000_adapter *adapter;
6025 struct e1000_hw *hw;
6026 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6027 resource_size_t mmio_start, mmio_len;
6028 resource_size_t flash_start, flash_len;
bc7f75fa 6029 static int cards_found;
78cd29d5 6030 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6031 int i, err, pci_using_dac;
6032 u16 eeprom_data = 0;
6033 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6034
78cd29d5
BA		 6035 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6036 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6037 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6038 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6039 if (aspm_disable_flag)
6040 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6041
f0f422e5 6042 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6043 if (err)
6044 return err;
6045
6046 pci_using_dac = 0;
0be3f55f 6047 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6048 if (!err) {
0be3f55f 6049 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6050 if (!err)
6051 pci_using_dac = 1;
6052 } else {
0be3f55f 6053 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6054 if (err) {
0be3f55f
NN		 6055 err = dma_set_coherent_mask(&pdev->dev,
6056 DMA_BIT_MASK(32));
bc7f75fa 6057 if (err) {
ef456f85 6058 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6059 goto err_dma;
6060 }
6061 }
6062 }
6063
e8de1481 6064 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6065 pci_select_bars(pdev, IORESOURCE_MEM),
6066 e1000e_driver_name);
bc7f75fa
AK		 6067 if (err)
6068 goto err_pci_reg;
6069
68eac460 6070 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6071 pci_enable_pcie_error_reporting(pdev);
68eac460 6072
bc7f75fa 6073 pci_set_master(pdev);
438b365a
BA		 6074 /* PCI config space info */
6075 err = pci_save_state(pdev);
6076 if (err)
6077 goto err_alloc_etherdev;
bc7f75fa
AK		 6078
6079 err = -ENOMEM;
6080 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6081 if (!netdev)
6082 goto err_alloc_etherdev;
6083
bc7f75fa
AK		 6084 SET_NETDEV_DEV(netdev, &pdev->dev);
6085
f85e4dfa
TH		 6086 netdev->irq = pdev->irq;
6087
bc7f75fa
AK		 6088 pci_set_drvdata(pdev, netdev);
6089 adapter = netdev_priv(netdev);
6090 hw = &adapter->hw;
6091 adapter->netdev = netdev;
6092 adapter->pdev = pdev;
6093 adapter->ei = ei;
6094 adapter->pba = ei->pba;
6095 adapter->flags = ei->flags;
eb7c3adb 6096 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6097 adapter->hw.adapter = adapter;
6098 adapter->hw.mac.type = ei->mac;
2adc55c9 6099 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6100 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6101
6102 mmio_start = pci_resource_start(pdev, 0);
6103 mmio_len = pci_resource_len(pdev, 0);
6104
6105 err = -EIO;
6106 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6107 if (!adapter->hw.hw_addr)
6108 goto err_ioremap;
6109
6110 if ((adapter->flags & FLAG_HAS_FLASH) &&
6111 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6112 flash_start = pci_resource_start(pdev, 1);
6113 flash_len = pci_resource_len(pdev, 1);
6114 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6115 if (!adapter->hw.flash_address)
6116 goto err_flashmap;
6117 }
6118
6119 /* construct the net_device struct */
651c2466 6120 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6121 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6122 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6123 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6124 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6125
6126 netdev->mem_start = mmio_start;
6127 netdev->mem_end = mmio_start + mmio_len;
6128
6129 adapter->bd_number = cards_found++;
6130
4662e82b
BA		 6131 e1000e_check_options(adapter);
6132
bc7f75fa
AK		 6133 /* setup adapter struct */
6134 err = e1000_sw_init(adapter);
6135 if (err)
6136 goto err_sw_init;
6137
bc7f75fa
AK		 6138 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6139 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6140 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6141
69e3fd8c 6142 err = ei->get_variants(adapter);
bc7f75fa
AK		 6143 if (err)
6144 goto err_hw_init;
6145
4a770358
BA		 6146 if ((adapter->flags & FLAG_IS_ICH) &&
6147 (adapter->flags & FLAG_READ_ONLY_NVM))
6148 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6149
bc7f75fa
AK		 6150 hw->mac.ops.get_bus_info(&adapter->hw);
6151
318a94d6 6152 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6153
6154 /* Copper options */
318a94d6 6155 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6156 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6157 adapter->hw.phy.disable_polarity_correction = 0;
6158 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6159 }
6160
470a5420 6161 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6162 dev_info(&pdev->dev,
6163 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6164
dc221294
BA		 6165 /* Set initial default active device features */
6166 netdev->features = (NETIF_F_SG |
6167 NETIF_F_HW_VLAN_RX |
6168 NETIF_F_HW_VLAN_TX |
6169 NETIF_F_TSO |
6170 NETIF_F_TSO6 |
70495a50 6171 NETIF_F_RXHASH |
dc221294
BA		 6172 NETIF_F_RXCSUM |
6173 NETIF_F_HW_CSUM);
6174
6175 /* Set user-changeable features (subset of all device features) */
6176 netdev->hw_features = netdev->features;
0184039a 6177 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6178 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6179 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6180
6181 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6182 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6183
dc221294
BA		 6184 netdev->vlan_features |= (NETIF_F_SG |
6185 NETIF_F_TSO |
6186 NETIF_F_TSO6 |
6187 NETIF_F_HW_CSUM);
a5136e23 6188
ef9b965a
JB		 6189 netdev->priv_flags |= IFF_UNICAST_FLT;
6190
7b872a55 6191 if (pci_using_dac) {
bc7f75fa 6192 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6193 netdev->vlan_features |= NETIF_F_HIGHDMA;
6194 }
bc7f75fa 6195
bc7f75fa
AK		 6196 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6197 adapter->flags |= FLAG_MNG_PT_ENABLED;
6198
e921eb1a 6199 /* before reading the NVM, reset the controller to
ad68076e
BA		 6200 * put the device in a known good starting state
6201 */
bc7f75fa
AK		 6202 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6203
e921eb1a 6204 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6205 * attempt. Let's give it a few tries
6206 */
6207 for (i = 0;; i++) {
6208 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6209 break;
6210 if (i == 2) {
185095fb 6211 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6212 err = -EIO;
6213 goto err_eeprom;
6214 }
6215 }
6216
10aa4c04
AK		 6217 e1000_eeprom_checks(adapter);
6218
608f8a0d 6219 /* copy the MAC address */
bc7f75fa 6220 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6221 dev_err(&pdev->dev,
6222 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6223
6224 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6225
aaeb6cdf 6226 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6227 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6228 netdev->dev_addr);
bc7f75fa
AK		 6229 err = -EIO;
6230 goto err_eeprom;
6231 }
6232
6233 init_timer(&adapter->watchdog_timer);
c061b18d 6234 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6235 adapter->watchdog_timer.data = (unsigned long) adapter;
6236
6237 init_timer(&adapter->phy_info_timer);
c061b18d 6238 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6239 adapter->phy_info_timer.data = (unsigned long) adapter;
6240
6241 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6242 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6243 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6244 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6245 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6246
bc7f75fa
AK		 6247 /* Initialize link parameters. User can change them with ethtool */
6248 adapter->hw.mac.autoneg = 1;
3db1cd5c 6249 adapter->fc_autoneg = true;
5c48ef3e
BA		 6250 adapter->hw.fc.requested_mode = e1000_fc_default;
6251 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6252 adapter->hw.phy.autoneg_advertised = 0x2f;
6253
6254 /* ring size defaults */
d821a4c4
BA		 6255 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6256 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6257
e921eb1a 6258 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6259 * the EEPROM, enable the ACPI Magic Packet filter
6260 */
6261 if (adapter->flags & FLAG_APME_IN_WUC) {
6262 /* APME bit in EEPROM is mapped to WUC.APME */
6263 eeprom_data = er32(WUC);
6264 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6265 if ((hw->mac.type > e1000_ich10lan) &&
6266 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6267 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6268 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6269 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6270 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6271 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6272 1, &eeprom_data);
bc7f75fa 6273 else
3d3a1676
BA		 6274 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6275 1, &eeprom_data);
bc7f75fa
AK		 6276 }
6277
6278 /* fetch WoL from EEPROM */
6279 if (eeprom_data & eeprom_apme_mask)
6280 adapter->eeprom_wol |= E1000_WUFC_MAG;
6281
e921eb1a 6282 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6283 * where the eeprom may be wrong or the board simply won't support
6284 * wake on lan on a particular port
6285 */
6286 if (!(adapter->flags & FLAG_HAS_WOL))
6287 adapter->eeprom_wol = 0;
6288
6289 /* initialize the wol settings based on the eeprom settings */
6290 adapter->wol = adapter->eeprom_wol;
6ff68026 6291 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6292
84527590
BA		 6293 /* save off EEPROM version number */
6294 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6295
bc7f75fa
AK		 6296 /* reset the hardware with the new settings */
6297 e1000e_reset(adapter);
6298
e921eb1a 6299 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6300 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6301 * under the control of the driver.
6302 */
c43bc57e 6303 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6304 e1000e_get_hw_control(adapter);
bc7f75fa 6305
f2315bf1 6306 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6307 err = register_netdev(netdev);
6308 if (err)
6309 goto err_register;
6310
9c563d20
JB		 6311 /* carrier off reporting is important to ethtool even BEFORE open */
6312 netif_carrier_off(netdev);
6313
bc7f75fa
AK		 6314 e1000_print_device_info(adapter);
6315
f3ec4f87
AS		 6316 if (pci_dev_run_wake(pdev))
6317 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6318
bc7f75fa
AK		 6319 return 0;
6320
6321err_register:
c43bc57e 6322 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6323 e1000e_release_hw_control(adapter);
bc7f75fa 6324err_eeprom:
470a5420 6325 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6326 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6327err_hw_init:
bc7f75fa
AK		 6328 kfree(adapter->tx_ring);
6329 kfree(adapter->rx_ring);
6330err_sw_init:
c43bc57e
JB		 6331 if (adapter->hw.flash_address)
6332 iounmap(adapter->hw.flash_address);
e82f54ba 6333 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6334err_flashmap:
bc7f75fa
AK		 6335 iounmap(adapter->hw.hw_addr);
6336err_ioremap:
6337 free_netdev(netdev);
6338err_alloc_etherdev:
f0f422e5
BA		 6339 pci_release_selected_regions(pdev,
6340 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6341err_pci_reg:
6342err_dma:
6343 pci_disable_device(pdev);
6344 return err;
6345}
6346
6347/**
6348 * e1000_remove - Device Removal Routine
6349 * @pdev: PCI device information struct
6350 *
6351 * e1000_remove is called by the PCI subsystem to alert the driver
6352 * that it should release a PCI device. The could be caused by a
6353 * Hot-Plug event, or because the driver is going to be removed from
6354 * memory.
6355 **/
9f9a12f8 6356static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6357{
6358 struct net_device *netdev = pci_get_drvdata(pdev);
6359 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6360 bool down = test_bit(__E1000_DOWN, &adapter->state);
6361
e921eb1a 6362 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6363 * from being rescheduled.
ad68076e 6364 */
23606cf5
RW		 6365 if (!down)
6366 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6367 del_timer_sync(&adapter->watchdog_timer);
6368 del_timer_sync(&adapter->phy_info_timer);
6369
41cec6f1
BA		 6370 cancel_work_sync(&adapter->reset_task);
6371 cancel_work_sync(&adapter->watchdog_task);
6372 cancel_work_sync(&adapter->downshift_task);
6373 cancel_work_sync(&adapter->update_phy_task);
6374 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6375
17f208de
BA		 6376 if (!(netdev->flags & IFF_UP))
6377 e1000_power_down_phy(adapter);
6378
23606cf5
RW		 6379 /* Don't lie to e1000_close() down the road. */
6380 if (!down)
6381 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6382 unregister_netdev(netdev);
6383
f3ec4f87
AS		 6384 if (pci_dev_run_wake(pdev))
6385 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6386
e921eb1a 6387 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6388 * would have already happened in close and is redundant.
6389 */
31dbe5b4 6390 e1000e_release_hw_control(adapter);
bc7f75fa 6391
4662e82b 6392 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6393 kfree(adapter->tx_ring);
6394 kfree(adapter->rx_ring);
6395
6396 iounmap(adapter->hw.hw_addr);
6397 if (adapter->hw.flash_address)
6398 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6399 pci_release_selected_regions(pdev,
6400 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6401
6402 free_netdev(netdev);
6403
111b9dc5 6404 /* AER disable */
19d5afd4 6405 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6406
bc7f75fa
AK		 6407 pci_disable_device(pdev);
6408}
6409
6410/* PCI Error Recovery (ERS) */
3646f0e5 6411static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6412 .error_detected = e1000_io_error_detected,
6413 .slot_reset = e1000_io_slot_reset,
6414 .resume = e1000_io_resume,
6415};
6416
a3aa1884 6417static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6418 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6419 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6420 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6421 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6422 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6424 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6427
bc7f75fa
AK		 6428 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6431 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6432
bc7f75fa
AK		 6433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6435 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6436
4662e82b 6437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6439 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6440
bc7f75fa
AK		 6441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6442 board_80003es2lan },
6443 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6444 board_80003es2lan },
6445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6446 board_80003es2lan },
6447 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6448 board_80003es2lan },
ad68076e 6449
bc7f75fa
AK		 6450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6458
bc7f75fa
AK		 6459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6468
6469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6472
f4187b56
BA		 6473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6476
a4f58f54
BA		 6477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6481
d3738bb8
BA		 6482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6484
2fbe4526
BA		 6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6489
f36bb6ca 6490 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6491};
6492MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6493
aa338601 6494#ifdef CONFIG_PM
23606cf5 6495static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6496 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6497 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6498 e1000_runtime_resume, e1000_idle)
23606cf5 6499};
e50208a0 6500#endif
23606cf5 6501
bc7f75fa
AK		 6502/* PCI Device API Driver */
6503static struct pci_driver e1000_driver = {
6504 .name = e1000e_driver_name,
6505 .id_table = e1000_pci_tbl,
6506 .probe = e1000_probe,
9f9a12f8 6507 .remove = e1000_remove,
aa338601 6508#ifdef CONFIG_PM
f36bb6ca
BA		 6509 .driver = {
6510 .pm = &e1000_pm_ops,
6511 },
bc7f75fa
AK		 6512#endif
6513 .shutdown = e1000_shutdown,
6514 .err_handler = &e1000_err_handler
6515};
6516
6517/**
6518 * e1000_init_module - Driver Registration Routine
6519 *
6520 * e1000_init_module is the first routine called when the driver is
6521 * loaded. All it does is register with the PCI subsystem.
6522 **/
6523static int __init e1000_init_module(void)
6524{
6525 int ret;
8544b9f7
BA		 6526 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6527 e1000e_driver_version);
f5e261e6 6528 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6529 ret = pci_register_driver(&e1000_driver);
53ec5498 6530
bc7f75fa
AK		 6531 return ret;
6532}
6533module_init(e1000_init_module);
6534
6535/**
6536 * e1000_exit_module - Driver Exit Cleanup Routine
6537 *
6538 * e1000_exit_module is called just before the driver is removed
6539 * from memory.
6540 **/
6541static void __exit e1000_exit_module(void)
6542{
6543 pci_unregister_driver(&e1000_driver);
6544}
6545module_exit(e1000_exit_module);
6546
6547
6548MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6549MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6550MODULE_LICENSE("GPL");
6551MODULE_VERSION(DRV_VERSION);
6552
06c24b91 6553/* netdev.c */
Linux kernel - Deliverables
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