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e1000e: Refactor PM flows
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1
DE		 1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
8defe713 51#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 73};
74
84f4ee90
TI		 75struct e1000_reg_info {
76 u32 ofs;
77 char *name;
78};
79
84f4ee90 80static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 81 /* General Registers */
82 {E1000_CTRL, "CTRL"},
83 {E1000_STATUS, "STATUS"},
84 {E1000_CTRL_EXT, "CTRL_EXT"},
85
86 /* Interrupt Registers */
87 {E1000_ICR, "ICR"},
88
af667a29 89 /* Rx Registers */
84f4ee90 90 {E1000_RCTL, "RCTL"},
1e36052e
BA		 91 {E1000_RDLEN(0), "RDLEN"},
92 {E1000_RDH(0), "RDH"},
93 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 94 {E1000_RDTR, "RDTR"},
95 {E1000_RXDCTL(0), "RXDCTL"},
96 {E1000_ERT, "ERT"},
1e36052e
BA		 97 {E1000_RDBAL(0), "RDBAL"},
98 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 99 {E1000_RDFH, "RDFH"},
100 {E1000_RDFT, "RDFT"},
101 {E1000_RDFHS, "RDFHS"},
102 {E1000_RDFTS, "RDFTS"},
103 {E1000_RDFPC, "RDFPC"},
104
af667a29 105 /* Tx Registers */
84f4ee90 106 {E1000_TCTL, "TCTL"},
1e36052e
BA		 107 {E1000_TDBAL(0), "TDBAL"},
108 {E1000_TDBAH(0), "TDBAH"},
109 {E1000_TDLEN(0), "TDLEN"},
110 {E1000_TDH(0), "TDH"},
111 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 112 {E1000_TIDV, "TIDV"},
113 {E1000_TXDCTL(0), "TXDCTL"},
114 {E1000_TADV, "TADV"},
115 {E1000_TARC(0), "TARC"},
116 {E1000_TDFH, "TDFH"},
117 {E1000_TDFT, "TDFT"},
118 {E1000_TDFHS, "TDFHS"},
119 {E1000_TDFTS, "TDFTS"},
120 {E1000_TDFPC, "TDFPC"},
121
122 /* List Terminator */
f36bb6ca 123 {0, NULL}
84f4ee90
TI		 124};
125
e921eb1a 126/**
84f4ee90 127 * e1000_regdump - register printout routine
e921eb1a
BA		 128 * @hw: pointer to the HW structure
129 * @reginfo: pointer to the register info table
130 **/
84f4ee90
TI		 131static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
132{
133 int n = 0;
134 char rname[16];
135 u32 regs[8];
136
137 switch (reginfo->ofs) {
138 case E1000_RXDCTL(0):
139 for (n = 0; n < 2; n++)
140 regs[n] = __er32(hw, E1000_RXDCTL(n));
141 break;
142 case E1000_TXDCTL(0):
143 for (n = 0; n < 2; n++)
144 regs[n] = __er32(hw, E1000_TXDCTL(n));
145 break;
146 case E1000_TARC(0):
147 for (n = 0; n < 2; n++)
148 regs[n] = __er32(hw, E1000_TARC(n));
149 break;
150 default:
ef456f85
JK		 151 pr_info("%-15s %08x\n",
152 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 153 return;
154 }
155
156 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 157 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 158}
159
f0c5dadf
ET		 160static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
161 struct e1000_buffer *bi)
162{
163 int i;
164 struct e1000_ps_page *ps_page;
165
166 for (i = 0; i < adapter->rx_ps_pages; i++) {
167 ps_page = &bi->ps_pages[i];
168
169 if (ps_page->page) {
170 pr_info("packet dump for ps_page %d:\n", i);
171 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
172 16, 1, page_address(ps_page->page),
173 PAGE_SIZE, true);
174 }
175 }
176}
177
e921eb1a 178/**
af667a29 179 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 180 * @adapter: board private structure
181 **/
84f4ee90
TI		 182static void e1000e_dump(struct e1000_adapter *adapter)
183{
184 struct net_device *netdev = adapter->netdev;
185 struct e1000_hw *hw = &adapter->hw;
186 struct e1000_reg_info *reginfo;
187 struct e1000_ring *tx_ring = adapter->tx_ring;
188 struct e1000_tx_desc *tx_desc;
af667a29 189 struct my_u0 {
e885d762
BA		 190 __le64 a;
191 __le64 b;
af667a29 192 } *u0;
84f4ee90
TI		 193 struct e1000_buffer *buffer_info;
194 struct e1000_ring *rx_ring = adapter->rx_ring;
195 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 196 union e1000_rx_desc_extended *rx_desc;
af667a29 197 struct my_u1 {
e885d762
BA		 198 __le64 a;
199 __le64 b;
200 __le64 c;
201 __le64 d;
af667a29 202 } *u1;
84f4ee90
TI		 203 u32 staterr;
204 int i = 0;
205
206 if (!netif_msg_hw(adapter))
207 return;
208
209 /* Print netdevice Info */
210 if (netdev) {
211 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 212 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 213 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
214 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 215 }
216
217 /* Print Registers */
218 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 219 pr_info(" Register Name Value\n");
84f4ee90
TI		 220 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
221 reginfo->name; reginfo++) {
222 e1000_regdump(hw, reginfo);
223 }
224
af667a29 225 /* Print Tx Ring Summary */
84f4ee90 226 if (!netdev || !netif_running(netdev))
fe1e980f 227 return;
84f4ee90 228
af667a29 229 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 230 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 231 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 232 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
233 0, tx_ring->next_to_use, tx_ring->next_to_clean,
234 (unsigned long long)buffer_info->dma,
235 buffer_info->length,
236 buffer_info->next_to_watch,
237 (unsigned long long)buffer_info->time_stamp);
84f4ee90 238
af667a29 239 /* Print Tx Ring */
84f4ee90
TI		 240 if (!netif_msg_tx_done(adapter))
241 goto rx_ring_summary;
242
af667a29 243 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 244
245 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
246 *
247 * Legacy Transmit Descriptor
248 * +--------------------------------------------------------------+
249 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
250 * +--------------------------------------------------------------+
251 * 8 | Special | CSS | Status | CMD | CSO | Length |
252 * +--------------------------------------------------------------+
253 * 63 48 47 36 35 32 31 24 23 16 15 0
254 *
255 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
256 * 63 48 47 40 39 32 31 16 15 8 7 0
257 * +----------------------------------------------------------------+
258 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
259 * +----------------------------------------------------------------+
260 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
261 * +----------------------------------------------------------------+
262 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
263 *
264 * Extended Data Descriptor (DTYP=0x1)
265 * +----------------------------------------------------------------+
266 * 0 | Buffer Address [63:0] |
267 * +----------------------------------------------------------------+
268 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
269 * +----------------------------------------------------------------+
270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
271 */
ef456f85
JK		 272 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
273 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
274 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 275 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 276 const char *next_desc;
84f4ee90
TI		 277 tx_desc = E1000_TX_DESC(*tx_ring, i);
278 buffer_info = &tx_ring->buffer_info[i];
279 u0 = (struct my_u0 *)tx_desc;
84f4ee90 280 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 281 next_desc = " NTC/U";
84f4ee90 282 else if (i == tx_ring->next_to_use)
ef456f85 283 next_desc = " NTU";
84f4ee90 284 else if (i == tx_ring->next_to_clean)
ef456f85 285 next_desc = " NTC";
84f4ee90 286 else
ef456f85
JK		 287 next_desc = "";
288 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
289 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
290 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
291 i,
292 (unsigned long long)le64_to_cpu(u0->a),
293 (unsigned long long)le64_to_cpu(u0->b),
294 (unsigned long long)buffer_info->dma,
295 buffer_info->length, buffer_info->next_to_watch,
296 (unsigned long long)buffer_info->time_stamp,
297 buffer_info->skb, next_desc);
84f4ee90 298
f0c5dadf 299 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 300 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 301 16, 1, buffer_info->skb->data,
302 buffer_info->skb->len, true);
84f4ee90
TI		 303 }
304
af667a29 305 /* Print Rx Ring Summary */
84f4ee90 306rx_ring_summary:
af667a29 307 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 308 pr_info("Queue [NTU] [NTC]\n");
309 pr_info(" %5d %5X %5X\n",
310 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 311
af667a29 312 /* Print Rx Ring */
84f4ee90 313 if (!netif_msg_rx_status(adapter))
fe1e980f 314 return;
84f4ee90 315
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 317 switch (adapter->rx_ps_pages) {
318 case 1:
319 case 2:
320 case 3:
321 /* [Extended] Packet Split Receive Descriptor Format
322 *
323 * +-----------------------------------------------------+
324 * 0 | Buffer Address 0 [63:0] |
325 * +-----------------------------------------------------+
326 * 8 | Buffer Address 1 [63:0] |
327 * +-----------------------------------------------------+
328 * 16 | Buffer Address 2 [63:0] |
329 * +-----------------------------------------------------+
330 * 24 | Buffer Address 3 [63:0] |
331 * +-----------------------------------------------------+
332 */
ef456f85 333 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 334 /* [Extended] Receive Descriptor (Write-Back) Format
335 *
336 * 63 48 47 32 31 13 12 8 7 4 3 0
337 * +------------------------------------------------------+
338 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
339 * | Checksum | Ident | | Queue | | Type |
340 * +------------------------------------------------------+
341 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
342 * +------------------------------------------------------+
343 * 63 48 47 32 31 20 19 0
344 */
ef456f85 345 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 346 for (i = 0; i < rx_ring->count; i++) {
ef456f85 347 const char *next_desc;
84f4ee90
TI		 348 buffer_info = &rx_ring->buffer_info[i];
349 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
350 u1 = (struct my_u1 *)rx_desc_ps;
351 staterr =
af667a29 352 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 353
354 if (i == rx_ring->next_to_use)
355 next_desc = " NTU";
356 else if (i == rx_ring->next_to_clean)
357 next_desc = " NTC";
358 else
359 next_desc = "";
360
84f4ee90
TI		 361 if (staterr & E1000_RXD_STAT_DD) {
362 /* Descriptor Done */
ef456f85
JK		 363 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
364 "RWB", i,
365 (unsigned long long)le64_to_cpu(u1->a),
366 (unsigned long long)le64_to_cpu(u1->b),
367 (unsigned long long)le64_to_cpu(u1->c),
368 (unsigned long long)le64_to_cpu(u1->d),
369 buffer_info->skb, next_desc);
84f4ee90 370 } else {
ef456f85
JK		 371 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
372 "R ", i,
373 (unsigned long long)le64_to_cpu(u1->a),
374 (unsigned long long)le64_to_cpu(u1->b),
375 (unsigned long long)le64_to_cpu(u1->c),
376 (unsigned long long)le64_to_cpu(u1->d),
377 (unsigned long long)buffer_info->dma,
378 buffer_info->skb, next_desc);
84f4ee90
TI		 379
380 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 381 e1000e_dump_ps_pages(adapter,
382 buffer_info);
84f4ee90 383 }
84f4ee90
TI		 384 }
385 break;
386 default:
387 case 0:
5f450212 388 /* Extended Receive Descriptor (Read) Format
84f4ee90 389 *
5f450212
BA		 390 * +-----------------------------------------------------+
391 * 0 | Buffer Address [63:0] |
392 * +-----------------------------------------------------+
393 * 8 | Reserved |
394 * +-----------------------------------------------------+
84f4ee90 395 */
ef456f85 396 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 397 /* Extended Receive Descriptor (Write-Back) Format
398 *
399 * 63 48 47 32 31 24 23 4 3 0
400 * +------------------------------------------------------+
401 * | RSS Hash | | | |
402 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
403 * | Packet | IP | | | Type |
404 * | Checksum | Ident | | | |
405 * +------------------------------------------------------+
406 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
407 * +------------------------------------------------------+
408 * 63 48 47 32 31 20 19 0
409 */
ef456f85 410 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 411
412 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 413 const char *next_desc;
414
84f4ee90 415 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 416 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
417 u1 = (struct my_u1 *)rx_desc;
418 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 419
420 if (i == rx_ring->next_to_use)
421 next_desc = " NTU";
422 else if (i == rx_ring->next_to_clean)
423 next_desc = " NTC";
424 else
425 next_desc = "";
426
5f450212
BA		 427 if (staterr & E1000_RXD_STAT_DD) {
428 /* Descriptor Done */
ef456f85
JK		 429 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
430 "RWB", i,
431 (unsigned long long)le64_to_cpu(u1->a),
432 (unsigned long long)le64_to_cpu(u1->b),
433 buffer_info->skb, next_desc);
5f450212 434 } else {
ef456f85
JK		 435 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
436 "R ", i,
437 (unsigned long long)le64_to_cpu(u1->a),
438 (unsigned long long)le64_to_cpu(u1->b),
439 (unsigned long long)buffer_info->dma,
440 buffer_info->skb, next_desc);
5f450212 441
f0c5dadf
ET		 442 if (netif_msg_pktdata(adapter) &&
443 buffer_info->skb)
5f450212
BA		 444 print_hex_dump(KERN_INFO, "",
445 DUMP_PREFIX_ADDRESS, 16,
446 1,
f0c5dadf 447 buffer_info->skb->data,
5f450212
BA		 448 adapter->rx_buffer_len,
449 true);
450 }
84f4ee90
TI		 451 }
452 }
84f4ee90
TI		 453}
454
bc7f75fa
AK		 455/**
456 * e1000_desc_unused - calculate if we have unused descriptors
457 **/
458static int e1000_desc_unused(struct e1000_ring *ring)
459{
460 if (ring->next_to_clean > ring->next_to_use)
461 return ring->next_to_clean - ring->next_to_use - 1;
462
463 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
464}
465
b67e1913
BA		 466/**
467 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
468 * @adapter: board private structure
469 * @hwtstamps: time stamp structure to update
470 * @systim: unsigned 64bit system time value.
471 *
472 * Convert the system time value stored in the RX/TXSTMP registers into a
473 * hwtstamp which can be used by the upper level time stamping functions.
474 *
475 * The 'systim_lock' spinlock is used to protect the consistency of the
476 * system time value. This is needed because reading the 64 bit time
477 * value involves reading two 32 bit registers. The first read latches the
478 * value.
479 **/
480static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
481 struct skb_shared_hwtstamps *hwtstamps,
482 u64 systim)
483{
484 u64 ns;
485 unsigned long flags;
486
487 spin_lock_irqsave(&adapter->systim_lock, flags);
488 ns = timecounter_cyc2time(&adapter->tc, systim);
489 spin_unlock_irqrestore(&adapter->systim_lock, flags);
490
491 memset(hwtstamps, 0, sizeof(*hwtstamps));
492 hwtstamps->hwtstamp = ns_to_ktime(ns);
493}
494
495/**
496 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
497 * @adapter: board private structure
498 * @status: descriptor extended error and status field
499 * @skb: particular skb to include time stamp
500 *
501 * If the time stamp is valid, convert it into the timecounter ns value
502 * and store that result into the shhwtstamps structure which is passed
503 * up the network stack.
504 **/
505static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
506 struct sk_buff *skb)
507{
508 struct e1000_hw *hw = &adapter->hw;
509 u64 rxstmp;
510
511 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
512 !(status & E1000_RXDEXT_STATERR_TST) ||
513 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
514 return;
515
516 /* The Rx time stamp registers contain the time stamp. No other
517 * received packet will be time stamped until the Rx time stamp
518 * registers are read. Because only one packet can be time stamped
519 * at a time, the register values must belong to this packet and
520 * therefore none of the other additional attributes need to be
521 * compared.
522 */
523 rxstmp = (u64)er32(RXSTMPL);
524 rxstmp |= (u64)er32(RXSTMPH) << 32;
525 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
526
527 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
528}
529
bc7f75fa 530/**
ad68076e 531 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 532 * @adapter: board private structure
b67e1913 533 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 534 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
535 * @skb: pointer to sk_buff to be indicated to stack
536 **/
537static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 538 struct net_device *netdev, struct sk_buff *skb,
b67e1913 539 u32 staterr, __le16 vlan)
bc7f75fa 540{
86d70e53 541 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 542
543 e1000e_rx_hwtstamp(adapter, staterr, skb);
544
bc7f75fa
AK		 545 skb->protocol = eth_type_trans(skb, netdev);
546
b67e1913 547 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 548 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 549
550 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 551}
552
553/**
af667a29 554 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 555 * @adapter: board private structure
556 * @status_err: receive descriptor status and error fields
557 * @csum: receive descriptor csum field
558 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 559 **/
560static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 561 struct sk_buff *skb)
bc7f75fa
AK		 562{
563 u16 status = (u16)status_err;
564 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 565
566 skb_checksum_none_assert(skb);
bc7f75fa 567
afd12939
BA		 568 /* Rx checksum disabled */
569 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
570 return;
571
bc7f75fa
AK		 572 /* Ignore Checksum bit is set */
573 if (status & E1000_RXD_STAT_IXSM)
574 return;
afd12939 575
2e1706f2
BA		 576 /* TCP/UDP checksum error bit or IP checksum error bit is set */
577 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 578 /* let the stack verify checksum errors */
579 adapter->hw_csum_err++;
580 return;
581 }
582
583 /* TCP/UDP Checksum has not been calculated */
584 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
585 return;
586
587 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 588 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 589 adapter->hw_csum_good++;
590}
591
55aa6985 592static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 593{
55aa6985 594 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 595 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 596 s32 ret_val = __ew32_prepare(hw);
597
598 writel(i, rx_ring->tail);
c6e7f51e 599
bdc125f7 600 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 601 u32 rctl = er32(RCTL);
602 ew32(RCTL, rctl & ~E1000_RCTL_EN);
603 e_err("ME firmware caused invalid RDT - resetting\n");
604 schedule_work(&adapter->reset_task);
605 }
606}
607
55aa6985 608static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 609{
55aa6985 610 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 611 struct e1000_hw *hw = &adapter->hw;
bdc125f7 612 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 613
bdc125f7
BA		 614 writel(i, tx_ring->tail);
615
616 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 617 u32 tctl = er32(TCTL);
618 ew32(TCTL, tctl & ~E1000_TCTL_EN);
619 e_err("ME firmware caused invalid TDT - resetting\n");
620 schedule_work(&adapter->reset_task);
621 }
622}
623
bc7f75fa 624/**
5f450212 625 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 626 * @rx_ring: Rx descriptor ring
bc7f75fa 627 **/
55aa6985 628static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 629 int cleaned_count, gfp_t gfp)
bc7f75fa 630{
55aa6985 631 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 632 struct net_device *netdev = adapter->netdev;
633 struct pci_dev *pdev = adapter->pdev;
5f450212 634 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 635 struct e1000_buffer *buffer_info;
636 struct sk_buff *skb;
637 unsigned int i;
89d71a66 638 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 639
640 i = rx_ring->next_to_use;
641 buffer_info = &rx_ring->buffer_info[i];
642
643 while (cleaned_count--) {
644 skb = buffer_info->skb;
645 if (skb) {
646 skb_trim(skb, 0);
647 goto map_skb;
648 }
649
c2fed996 650 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 651 if (!skb) {
652 /* Better luck next round */
653 adapter->alloc_rx_buff_failed++;
654 break;
655 }
656
bc7f75fa
AK		 657 buffer_info->skb = skb;
658map_skb:
0be3f55f 659 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 660 adapter->rx_buffer_len,
0be3f55f
NN		 661 DMA_FROM_DEVICE);
662 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 663 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 664 adapter->rx_dma_failed++;
665 break;
666 }
667
5f450212
BA		 668 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
669 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 670
50849d79 671 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 672 /* Force memory writes to complete before letting h/w
50849d79
TH		 673 * know there are new descriptors to fetch. (Only
674 * applicable for weak-ordered memory model archs,
675 * such as IA-64).
676 */
677 wmb();
c6e7f51e 678 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 679 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 680 else
c5083cf6 681 writel(i, rx_ring->tail);
50849d79 682 }
bc7f75fa
AK		 683 i++;
684 if (i == rx_ring->count)
685 i = 0;
686 buffer_info = &rx_ring->buffer_info[i];
687 }
688
50849d79 689 rx_ring->next_to_use = i;
bc7f75fa
AK		 690}
691
692/**
693 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 694 * @rx_ring: Rx descriptor ring
bc7f75fa 695 **/
55aa6985 696static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 697 int cleaned_count, gfp_t gfp)
bc7f75fa 698{
55aa6985 699 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 700 struct net_device *netdev = adapter->netdev;
701 struct pci_dev *pdev = adapter->pdev;
702 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 703 struct e1000_buffer *buffer_info;
704 struct e1000_ps_page *ps_page;
705 struct sk_buff *skb;
706 unsigned int i, j;
707
708 i = rx_ring->next_to_use;
709 buffer_info = &rx_ring->buffer_info[i];
710
711 while (cleaned_count--) {
712 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
713
714 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 715 ps_page = &buffer_info->ps_pages[j];
716 if (j >= adapter->rx_ps_pages) {
717 /* all unused desc entries get hw null ptr */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 ~cpu_to_le64(0);
47f44e40
AK		 720 continue;
721 }
722 if (!ps_page->page) {
c2fed996 723 ps_page->page = alloc_page(gfp);
bc7f75fa 724 if (!ps_page->page) {
47f44e40
AK		 725 adapter->alloc_rx_buff_failed++;
726 goto no_buffers;
727 }
0be3f55f
NN		 728 ps_page->dma = dma_map_page(&pdev->dev,
729 ps_page->page,
730 0, PAGE_SIZE,
731 DMA_FROM_DEVICE);
732 if (dma_mapping_error(&pdev->dev,
733 ps_page->dma)) {
47f44e40 734 dev_err(&adapter->pdev->dev,
af667a29 735 "Rx DMA page map failed\n");
47f44e40
AK		 736 adapter->rx_dma_failed++;
737 goto no_buffers;
bc7f75fa 738 }
bc7f75fa 739 }
e921eb1a 740 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 741 * didn't change because each write-back
742 * erases this info.
743 */
af667a29
BA		 744 rx_desc->read.buffer_addr[j + 1] =
745 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 746 }
747
e5fe2541 748 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 749 gfp);
bc7f75fa
AK		 750
751 if (!skb) {
752 adapter->alloc_rx_buff_failed++;
753 break;
754 }
755
bc7f75fa 756 buffer_info->skb = skb;
0be3f55f 757 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 758 adapter->rx_ps_bsize0,
0be3f55f
NN		 759 DMA_FROM_DEVICE);
760 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 761 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 762 adapter->rx_dma_failed++;
763 /* cleanup skb */
764 dev_kfree_skb_any(skb);
765 buffer_info->skb = NULL;
766 break;
767 }
768
769 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
770
50849d79 771 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 772 /* Force memory writes to complete before letting h/w
50849d79
TH		 773 * know there are new descriptors to fetch. (Only
774 * applicable for weak-ordered memory model archs,
775 * such as IA-64).
776 */
777 wmb();
c6e7f51e 778 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 779 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 780 else
c5083cf6 781 writel(i << 1, rx_ring->tail);
50849d79
TH		 782 }
783
bc7f75fa
AK		 784 i++;
785 if (i == rx_ring->count)
786 i = 0;
787 buffer_info = &rx_ring->buffer_info[i];
788 }
789
790no_buffers:
50849d79 791 rx_ring->next_to_use = i;
bc7f75fa
AK		 792}
793
97ac8cae
BA		 794/**
795 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 796 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 797 * @cleaned_count: number of buffers to allocate this pass
798 **/
799
55aa6985 800static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 801 int cleaned_count, gfp_t gfp)
97ac8cae 802{
55aa6985 803 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 804 struct net_device *netdev = adapter->netdev;
805 struct pci_dev *pdev = adapter->pdev;
5f450212 806 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 807 struct e1000_buffer *buffer_info;
808 struct sk_buff *skb;
809 unsigned int i;
2a2293b9 810 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 811
812 i = rx_ring->next_to_use;
813 buffer_info = &rx_ring->buffer_info[i];
814
815 while (cleaned_count--) {
816 skb = buffer_info->skb;
817 if (skb) {
818 skb_trim(skb, 0);
819 goto check_page;
820 }
821
c2fed996 822 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 823 if (unlikely(!skb)) {
824 /* Better luck next round */
825 adapter->alloc_rx_buff_failed++;
826 break;
827 }
828
97ac8cae
BA		 829 buffer_info->skb = skb;
830check_page:
831 /* allocate a new page if necessary */
832 if (!buffer_info->page) {
c2fed996 833 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 834 if (unlikely(!buffer_info->page)) {
835 adapter->alloc_rx_buff_failed++;
836 break;
837 }
838 }
839
37287fae 840 if (!buffer_info->dma) {
0be3f55f 841 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 842 buffer_info->page, 0,
843 PAGE_SIZE,
0be3f55f 844 DMA_FROM_DEVICE);
37287fae
CP		 845 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849 }
97ac8cae 850
5f450212
BA		 851 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
852 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 853
854 if (unlikely(++i == rx_ring->count))
855 i = 0;
856 buffer_info = &rx_ring->buffer_info[i];
857 }
858
859 if (likely(rx_ring->next_to_use != i)) {
860 rx_ring->next_to_use = i;
861 if (unlikely(i-- == 0))
862 i = (rx_ring->count - 1);
863
864 /* Force memory writes to complete before letting h/w
865 * know there are new descriptors to fetch. (Only
866 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 867 * such as IA-64).
868 */
97ac8cae 869 wmb();
c6e7f51e 870 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 871 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 872 else
c5083cf6 873 writel(i, rx_ring->tail);
97ac8cae
BA		 874 }
875}
876
70495a50
BA		 877static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
878 struct sk_buff *skb)
879{
880 if (netdev->features & NETIF_F_RXHASH)
881 skb->rxhash = le32_to_cpu(rss);
882}
883
bc7f75fa 884/**
55aa6985
BA		 885 * e1000_clean_rx_irq - Send received data up the network stack
886 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 887 *
888 * the return value indicates whether actual cleaning was done, there
889 * is no guarantee that everything was cleaned
890 **/
55aa6985
BA		 891static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
892 int work_to_do)
bc7f75fa 893{
55aa6985 894 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 895 struct net_device *netdev = adapter->netdev;
896 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 897 struct e1000_hw *hw = &adapter->hw;
5f450212 898 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 899 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 900 u32 length, staterr;
bc7f75fa
AK		 901 unsigned int i;
902 int cleaned_count = 0;
3db1cd5c 903 bool cleaned = false;
bc7f75fa
AK		 904 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
905
906 i = rx_ring->next_to_clean;
5f450212
BA		 907 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
908 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 909 buffer_info = &rx_ring->buffer_info[i];
910
5f450212 911 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 912 struct sk_buff *skb;
bc7f75fa
AK		 913
914 if (*work_done >= work_to_do)
915 break;
916 (*work_done)++;
2d0bb1c1 917 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 918
bc7f75fa
AK		 919 skb = buffer_info->skb;
920 buffer_info->skb = NULL;
921
922 prefetch(skb->data - NET_IP_ALIGN);
923
924 i++;
925 if (i == rx_ring->count)
926 i = 0;
5f450212 927 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 928 prefetch(next_rxd);
929
930 next_buffer = &rx_ring->buffer_info[i];
931
3db1cd5c 932 cleaned = true;
bc7f75fa 933 cleaned_count++;
e5fe2541
BA		 934 dma_unmap_single(&pdev->dev, buffer_info->dma,
935 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 936 buffer_info->dma = 0;
937
5f450212 938 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 939
e921eb1a 940 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 941 * packet, if that's the case we need to toss it. In fact, we
942 * need to toss every packet with the EOP bit clear and the
943 * next frame that _does_ have the EOP bit set, as it is by
944 * definition only a frame fragment
945 */
5f450212 946 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 947 adapter->flags2 |= FLAG2_IS_DISCARDING;
948
949 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 950 /* All receives must fit into a single buffer */
3bb99fe2 951 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 952 /* recycle */
953 buffer_info->skb = skb;
5f450212 954 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 955 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 956 goto next_desc;
957 }
958
cf955e6c
BG		 959 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
960 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 961 /* recycle */
962 buffer_info->skb = skb;
963 goto next_desc;
964 }
965
eb7c3adb 966 /* adjust length to remove Ethernet CRC */
0184039a
BG		 967 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
968 /* If configured to store CRC, don't subtract FCS,
969 * but keep the FCS bytes out of the total_rx_bytes
970 * counter
971 */
972 if (netdev->features & NETIF_F_RXFCS)
973 total_rx_bytes -= 4;
974 else
975 length -= 4;
976 }
eb7c3adb 977
bc7f75fa
AK		 978 total_rx_bytes += length;
979 total_rx_packets++;
980
e921eb1a 981 /* code added for copybreak, this should improve
bc7f75fa 982 * performance for small packets with large amounts
ad68076e
BA		 983 * of reassembly being done in the stack
984 */
bc7f75fa
AK		 985 if (length < copybreak) {
986 struct sk_buff *new_skb =
89d71a66 987 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 988 if (new_skb) {
808ff676
BA		 989 skb_copy_to_linear_data_offset(new_skb,
990 -NET_IP_ALIGN,
991 (skb->data -
992 NET_IP_ALIGN),
993 (length +
994 NET_IP_ALIGN));
bc7f75fa
AK		 995 /* save the skb in buffer_info as good */
996 buffer_info->skb = skb;
997 skb = new_skb;
998 }
999 /* else just continue with the old one */
1000 }
1001 /* end copybreak code */
1002 skb_put(skb, length);
1003
1004 /* Receive Checksum Offload */
2e1706f2 1005 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1006
70495a50
BA		 1007 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1008
5f450212
BA		 1009 e1000_receive_skb(adapter, netdev, skb, staterr,
1010 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1011
1012next_desc:
5f450212 1013 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1014
1015 /* return some buffers to hardware, one at a time is too slow */
1016 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1017 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1018 GFP_ATOMIC);
bc7f75fa
AK		 1019 cleaned_count = 0;
1020 }
1021
1022 /* use prefetched values */
1023 rx_desc = next_rxd;
1024 buffer_info = next_buffer;
5f450212
BA		 1025
1026 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1027 }
1028 rx_ring->next_to_clean = i;
1029
1030 cleaned_count = e1000_desc_unused(rx_ring);
1031 if (cleaned_count)
55aa6985 1032 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1033
bc7f75fa 1034 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1035 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1036 return cleaned;
1037}
1038
55aa6985
BA		 1039static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1040 struct e1000_buffer *buffer_info)
bc7f75fa 1041{
55aa6985
BA		 1042 struct e1000_adapter *adapter = tx_ring->adapter;
1043
03b1320d
AD		 1044 if (buffer_info->dma) {
1045 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1046 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1047 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1048 else
0be3f55f
NN		 1049 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1050 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1051 buffer_info->dma = 0;
1052 }
bc7f75fa
AK		 1053 if (buffer_info->skb) {
1054 dev_kfree_skb_any(buffer_info->skb);
1055 buffer_info->skb = NULL;
1056 }
1b7719c4 1057 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1058}
1059
41cec6f1 1060static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1061{
41cec6f1 1062 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1063 struct e1000_adapter,
1064 print_hang_task);
09357b00 1065 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1066 struct e1000_ring *tx_ring = adapter->tx_ring;
1067 unsigned int i = tx_ring->next_to_clean;
1068 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1069 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1070 struct e1000_hw *hw = &adapter->hw;
1071 u16 phy_status, phy_1000t_status, phy_ext_status;
1072 u16 pci_status;
1073
615b32af
JB		 1074 if (test_bit(__E1000_DOWN, &adapter->state))
1075 return;
1076
e5fe2541 1077 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1078 /* May be block on write-back, flush and detect again
09357b00
JK		 1079 * flush pending descriptor writebacks to memory
1080 */
1081 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1082 /* execute the writes immediately */
1083 e1e_flush();
e921eb1a 1084 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1085 * the write is successful
1086 */
1087 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1088 /* execute the writes immediately */
1089 e1e_flush();
09357b00
JK		 1090 adapter->tx_hang_recheck = true;
1091 return;
1092 }
1093 /* Real hang detected */
1094 adapter->tx_hang_recheck = false;
1095 netif_stop_queue(netdev);
1096
c2ade1a4
BA		 1097 e1e_rphy(hw, MII_BMSR, &phy_status);
1098 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1099 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1100
41cec6f1
BA		 1101 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1102
1103 /* detected Hardware unit hang */
1104 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1105 " TDH <%x>\n"
1106 " TDT <%x>\n"
1107 " next_to_use <%x>\n"
1108 " next_to_clean <%x>\n"
1109 "buffer_info[next_to_clean]:\n"
1110 " time_stamp <%lx>\n"
1111 " next_to_watch <%x>\n"
1112 " jiffies <%lx>\n"
41cec6f1
BA		 1113 " next_to_watch.status <%x>\n"
1114 "MAC Status <%x>\n"
1115 "PHY Status <%x>\n"
1116 "PHY 1000BASE-T Status <%x>\n"
1117 "PHY Extended Status <%x>\n"
1118 "PCI Status <%x>\n",
e5fe2541
BA		 1119 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1120 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1121 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1122 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee
BA		 1123
1124 /* Suggest workaround for known h/w issue */
1125 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1126 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1127}
1128
b67e1913
BA		 1129/**
1130 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1131 * @work: pointer to work struct
1132 *
1133 * This work function polls the TSYNCTXCTL valid bit to determine when a
1134 * timestamp has been taken for the current stored skb. The timestamp must
1135 * be for this skb because only one such packet is allowed in the queue.
1136 */
1137static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1138{
1139 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1140 tx_hwtstamp_work);
1141 struct e1000_hw *hw = &adapter->hw;
1142
1143 if (!adapter->tx_hwtstamp_skb)
1144 return;
1145
1146 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1147 struct skb_shared_hwtstamps shhwtstamps;
1148 u64 txstmp;
1149
1150 txstmp = er32(TXSTMPL);
1151 txstmp |= (u64)er32(TXSTMPH) << 32;
1152
1153 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1154
1155 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1156 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1157 adapter->tx_hwtstamp_skb = NULL;
1158 } else {
1159 /* reschedule to check later */
1160 schedule_work(&adapter->tx_hwtstamp_work);
1161 }
1162}
1163
bc7f75fa
AK		 1164/**
1165 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1166 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1167 *
1168 * the return value indicates whether actual cleaning was done, there
1169 * is no guarantee that everything was cleaned
1170 **/
55aa6985 1171static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1172{
55aa6985 1173 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1174 struct net_device *netdev = adapter->netdev;
1175 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1176 struct e1000_tx_desc *tx_desc, *eop_desc;
1177 struct e1000_buffer *buffer_info;
1178 unsigned int i, eop;
1179 unsigned int count = 0;
bc7f75fa 1180 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1181 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1182
1183 i = tx_ring->next_to_clean;
1184 eop = tx_ring->buffer_info[i].next_to_watch;
1185 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1186
12d04a3c
AD		 1187 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1188 (count < tx_ring->count)) {
a86043c2 1189 bool cleaned = false;
e80bd1d1 1190 rmb(); /* read buffer_info after eop_desc */
a86043c2 1191 for (; !cleaned; count++) {
bc7f75fa
AK		 1192 tx_desc = E1000_TX_DESC(*tx_ring, i);
1193 buffer_info = &tx_ring->buffer_info[i];
1194 cleaned = (i == eop);
1195
1196 if (cleaned) {
9ed318d5
TH		 1197 total_tx_packets += buffer_info->segs;
1198 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1199 if (buffer_info->skb) {
1200 bytes_compl += buffer_info->skb->len;
1201 pkts_compl++;
1202 }
bc7f75fa
AK		 1203 }
1204
55aa6985 1205 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1206 tx_desc->upper.data = 0;
1207
1208 i++;
1209 if (i == tx_ring->count)
1210 i = 0;
1211 }
1212
dac87619
TL		 1213 if (i == tx_ring->next_to_use)
1214 break;
bc7f75fa
AK		 1215 eop = tx_ring->buffer_info[i].next_to_watch;
1216 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1217 }
1218
1219 tx_ring->next_to_clean = i;
1220
3f0cfa3b
TH		 1221 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1222
bc7f75fa 1223#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1224 if (count && netif_carrier_ok(netdev) &&
1225 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1226 /* Make sure that anybody stopping the queue after this
1227 * sees the new next_to_clean.
1228 */
1229 smp_mb();
1230
1231 if (netif_queue_stopped(netdev) &&
1232 !(test_bit(__E1000_DOWN, &adapter->state))) {
1233 netif_wake_queue(netdev);
1234 ++adapter->restart_queue;
1235 }
1236 }
1237
1238 if (adapter->detect_tx_hung) {
e921eb1a 1239 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1240 * check with the clearing of time_stamp and movement of i
1241 */
3db1cd5c 1242 adapter->detect_tx_hung = false;
12d04a3c
AD		 1243 if (tx_ring->buffer_info[i].time_stamp &&
1244 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1245 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1246 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1247 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1248 else
1249 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1250 }
1251 adapter->total_tx_bytes += total_tx_bytes;
1252 adapter->total_tx_packets += total_tx_packets;
807540ba 1253 return count < tx_ring->count;
bc7f75fa
AK		 1254}
1255
bc7f75fa
AK		 1256/**
1257 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1258 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1259 *
1260 * the return value indicates whether actual cleaning was done, there
1261 * is no guarantee that everything was cleaned
1262 **/
55aa6985
BA		 1263static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1264 int work_to_do)
bc7f75fa 1265{
55aa6985 1266 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1267 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1268 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1269 struct net_device *netdev = adapter->netdev;
1270 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1271 struct e1000_buffer *buffer_info, *next_buffer;
1272 struct e1000_ps_page *ps_page;
1273 struct sk_buff *skb;
1274 unsigned int i, j;
1275 u32 length, staterr;
1276 int cleaned_count = 0;
3db1cd5c 1277 bool cleaned = false;
bc7f75fa
AK		 1278 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1279
1280 i = rx_ring->next_to_clean;
1281 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1282 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1283 buffer_info = &rx_ring->buffer_info[i];
1284
1285 while (staterr & E1000_RXD_STAT_DD) {
1286 if (*work_done >= work_to_do)
1287 break;
1288 (*work_done)++;
1289 skb = buffer_info->skb;
2d0bb1c1 1290 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1291
1292 /* in the packet split case this is header only */
1293 prefetch(skb->data - NET_IP_ALIGN);
1294
1295 i++;
1296 if (i == rx_ring->count)
1297 i = 0;
1298 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1299 prefetch(next_rxd);
1300
1301 next_buffer = &rx_ring->buffer_info[i];
1302
3db1cd5c 1303 cleaned = true;
bc7f75fa 1304 cleaned_count++;
0be3f55f 1305 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1306 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1307 buffer_info->dma = 0;
1308
af667a29 1309 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1310 if (!(staterr & E1000_RXD_STAT_EOP))
1311 adapter->flags2 |= FLAG2_IS_DISCARDING;
1312
1313 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1314 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1315 dev_kfree_skb_irq(skb);
b94b5028
JB		 1316 if (staterr & E1000_RXD_STAT_EOP)
1317 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1318 goto next_desc;
1319 }
1320
cf955e6c
BG		 1321 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1322 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1323 dev_kfree_skb_irq(skb);
1324 goto next_desc;
1325 }
1326
1327 length = le16_to_cpu(rx_desc->wb.middle.length0);
1328
1329 if (!length) {
ef456f85 1330 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1331 dev_kfree_skb_irq(skb);
1332 goto next_desc;
1333 }
1334
1335 /* Good Receive */
1336 skb_put(skb, length);
1337
1338 {
e921eb1a 1339 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1340 * it more efficient than reusing j
1341 */
1342 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1343
e921eb1a 1344 /* page alloc/put takes too long and effects small
0e15df49
BA		 1345 * packet throughput, so unsplit small packets and
1346 * save the alloc/put only valid in softirq (napi)
1347 * context to call kmap_*
ad68076e 1348 */
0e15df49
BA		 1349 if (l1 && (l1 <= copybreak) &&
1350 ((length + l1) <= adapter->rx_ps_bsize0)) {
1351 u8 *vaddr;
1352
1353 ps_page = &buffer_info->ps_pages[0];
1354
e921eb1a 1355 /* there is no documentation about how to call
0e15df49
BA		 1356 * kmap_atomic, so we can't hold the mapping
1357 * very long
1358 */
1359 dma_sync_single_for_cpu(&pdev->dev,
1360 ps_page->dma,
1361 PAGE_SIZE,
1362 DMA_FROM_DEVICE);
9f393834 1363 vaddr = kmap_atomic(ps_page->page);
0e15df49 1364 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1365 kunmap_atomic(vaddr);
0e15df49
BA		 1366 dma_sync_single_for_device(&pdev->dev,
1367 ps_page->dma,
1368 PAGE_SIZE,
1369 DMA_FROM_DEVICE);
1370
1371 /* remove the CRC */
0184039a
BG		 1372 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1373 if (!(netdev->features & NETIF_F_RXFCS))
1374 l1 -= 4;
1375 }
0e15df49
BA		 1376
1377 skb_put(skb, l1);
1378 goto copydone;
e80bd1d1 1379 } /* if */
bc7f75fa
AK		 1380 }
1381
1382 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1383 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1384 if (!length)
1385 break;
1386
47f44e40 1387 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1388 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1389 DMA_FROM_DEVICE);
bc7f75fa
AK		 1390 ps_page->dma = 0;
1391 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1392 ps_page->page = NULL;
1393 skb->len += length;
1394 skb->data_len += length;
98a045d7 1395 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1396 }
1397
eb7c3adb
JK		 1398 /* strip the ethernet crc, problem is we're using pages now so
1399 * this whole operation can get a little cpu intensive
1400 */
0184039a
BG		 1401 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1402 if (!(netdev->features & NETIF_F_RXFCS))
1403 pskb_trim(skb, skb->len - 4);
1404 }
eb7c3adb 1405
bc7f75fa
AK		 1406copydone:
1407 total_rx_bytes += skb->len;
1408 total_rx_packets++;
1409
2e1706f2 1410 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1411
70495a50
BA		 1412 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1413
bc7f75fa 1414 if (rx_desc->wb.upper.header_status &
17e813ec 1415 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1416 adapter->rx_hdr_split++;
1417
b67e1913
BA		 1418 e1000_receive_skb(adapter, netdev, skb, staterr,
1419 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1420
1421next_desc:
1422 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1423 buffer_info->skb = NULL;
1424
1425 /* return some buffers to hardware, one at a time is too slow */
1426 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1427 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1428 GFP_ATOMIC);
bc7f75fa
AK		 1429 cleaned_count = 0;
1430 }
1431
1432 /* use prefetched values */
1433 rx_desc = next_rxd;
1434 buffer_info = next_buffer;
1435
1436 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1437 }
1438 rx_ring->next_to_clean = i;
1439
1440 cleaned_count = e1000_desc_unused(rx_ring);
1441 if (cleaned_count)
55aa6985 1442 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1443
bc7f75fa 1444 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1445 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1446 return cleaned;
1447}
1448
97ac8cae
BA		 1449/**
1450 * e1000_consume_page - helper function
1451 **/
1452static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1453 u16 length)
97ac8cae
BA		 1454{
1455 bi->page = NULL;
1456 skb->len += length;
1457 skb->data_len += length;
98a045d7 1458 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1459}
1460
1461/**
1462 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1463 * @adapter: board private structure
1464 *
1465 * the return value indicates whether actual cleaning was done, there
1466 * is no guarantee that everything was cleaned
1467 **/
55aa6985
BA		 1468static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1469 int work_to_do)
97ac8cae 1470{
55aa6985 1471 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1472 struct net_device *netdev = adapter->netdev;
1473 struct pci_dev *pdev = adapter->pdev;
5f450212 1474 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1475 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1476 u32 length, staterr;
97ac8cae
BA		 1477 unsigned int i;
1478 int cleaned_count = 0;
1479 bool cleaned = false;
362e20ca 1480 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1481 struct skb_shared_info *shinfo;
97ac8cae
BA		 1482
1483 i = rx_ring->next_to_clean;
5f450212
BA		 1484 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1485 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1486 buffer_info = &rx_ring->buffer_info[i];
1487
5f450212 1488 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1489 struct sk_buff *skb;
97ac8cae
BA		 1490
1491 if (*work_done >= work_to_do)
1492 break;
1493 (*work_done)++;
2d0bb1c1 1494 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1495
97ac8cae
BA		 1496 skb = buffer_info->skb;
1497 buffer_info->skb = NULL;
1498
1499 ++i;
1500 if (i == rx_ring->count)
1501 i = 0;
5f450212 1502 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1503 prefetch(next_rxd);
1504
1505 next_buffer = &rx_ring->buffer_info[i];
1506
1507 cleaned = true;
1508 cleaned_count++;
0be3f55f
NN		 1509 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1510 DMA_FROM_DEVICE);
97ac8cae
BA		 1511 buffer_info->dma = 0;
1512
5f450212 1513 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1514
1515 /* errors is only valid for DD + EOP descriptors */
5f450212 1516 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1517 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1518 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1519 /* recycle both page and skb */
1520 buffer_info->skb = skb;
1521 /* an error means any chain goes out the window too */
1522 if (rx_ring->rx_skb_top)
1523 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1524 rx_ring->rx_skb_top = NULL;
1525 goto next_desc;
97ac8cae 1526 }
f0f1a172 1527#define rxtop (rx_ring->rx_skb_top)
5f450212 1528 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1529 /* this descriptor is only the beginning (or middle) */
1530 if (!rxtop) {
1531 /* this is the beginning of a chain */
1532 rxtop = skb;
1533 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1534 0, length);
97ac8cae
BA		 1535 } else {
1536 /* this is the middle of a chain */
17e813ec
BA		 1537 shinfo = skb_shinfo(rxtop);
1538 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1539 buffer_info->page, 0,
1540 length);
97ac8cae
BA		 1541 /* re-use the skb, only consumed the page */
1542 buffer_info->skb = skb;
1543 }
1544 e1000_consume_page(buffer_info, rxtop, length);
1545 goto next_desc;
1546 } else {
1547 if (rxtop) {
1548 /* end of the chain */
17e813ec
BA		 1549 shinfo = skb_shinfo(rxtop);
1550 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1551 buffer_info->page, 0,
1552 length);
97ac8cae 1553 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1554 * page
1555 */
97ac8cae
BA		 1556 buffer_info->skb = skb;
1557 skb = rxtop;
1558 rxtop = NULL;
1559 e1000_consume_page(buffer_info, skb, length);
1560 } else {
1561 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1562 * copybreak to save the put_page/alloc_page
1563 */
97ac8cae
BA		 1564 if (length <= copybreak &&
1565 skb_tailroom(skb) >= length) {
1566 u8 *vaddr;
4679026d 1567 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1568 memcpy(skb_tail_pointer(skb), vaddr,
1569 length);
4679026d 1570 kunmap_atomic(vaddr);
97ac8cae 1571 /* re-use the page, so don't erase
e921eb1a
BA		 1572 * buffer_info->page
1573 */
97ac8cae
BA		 1574 skb_put(skb, length);
1575 } else {
1576 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1577 buffer_info->page, 0,
1578 length);
97ac8cae 1579 e1000_consume_page(buffer_info, skb,
f0ff4398 1580 length);
97ac8cae
BA		 1581 }
1582 }
1583 }
1584
2e1706f2
BA		 1585 /* Receive Checksum Offload */
1586 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1587
70495a50
BA		 1588 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1589
97ac8cae
BA		 1590 /* probably a little skewed due to removing CRC */
1591 total_rx_bytes += skb->len;
1592 total_rx_packets++;
1593
1594 /* eth type trans needs skb->data to point to something */
1595 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1596 e_err("pskb_may_pull failed.\n");
ef5ab89c 1597 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1598 goto next_desc;
1599 }
1600
5f450212
BA		 1601 e1000_receive_skb(adapter, netdev, skb, staterr,
1602 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1603
1604next_desc:
5f450212 1605 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1606
1607 /* return some buffers to hardware, one at a time is too slow */
1608 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1609 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1610 GFP_ATOMIC);
97ac8cae
BA		 1611 cleaned_count = 0;
1612 }
1613
1614 /* use prefetched values */
1615 rx_desc = next_rxd;
1616 buffer_info = next_buffer;
5f450212
BA		 1617
1618 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1619 }
1620 rx_ring->next_to_clean = i;
1621
1622 cleaned_count = e1000_desc_unused(rx_ring);
1623 if (cleaned_count)
55aa6985 1624 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1625
1626 adapter->total_rx_bytes += total_rx_bytes;
1627 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1628 return cleaned;
1629}
1630
bc7f75fa
AK		 1631/**
1632 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1633 * @rx_ring: Rx descriptor ring
bc7f75fa 1634 **/
55aa6985 1635static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1636{
55aa6985 1637 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1638 struct e1000_buffer *buffer_info;
1639 struct e1000_ps_page *ps_page;
1640 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1641 unsigned int i, j;
1642
1643 /* Free all the Rx ring sk_buffs */
1644 for (i = 0; i < rx_ring->count; i++) {
1645 buffer_info = &rx_ring->buffer_info[i];
1646 if (buffer_info->dma) {
1647 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1648 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1649 adapter->rx_buffer_len,
0be3f55f 1650 DMA_FROM_DEVICE);
97ac8cae 1651 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1652 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1653 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1654 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1655 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1656 adapter->rx_ps_bsize0,
0be3f55f 1657 DMA_FROM_DEVICE);
bc7f75fa
AK		 1658 buffer_info->dma = 0;
1659 }
1660
97ac8cae
BA		 1661 if (buffer_info->page) {
1662 put_page(buffer_info->page);
1663 buffer_info->page = NULL;
1664 }
1665
bc7f75fa
AK		 1666 if (buffer_info->skb) {
1667 dev_kfree_skb(buffer_info->skb);
1668 buffer_info->skb = NULL;
1669 }
1670
1671 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1672 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1673 if (!ps_page->page)
1674 break;
0be3f55f
NN		 1675 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1676 DMA_FROM_DEVICE);
bc7f75fa
AK		 1677 ps_page->dma = 0;
1678 put_page(ps_page->page);
1679 ps_page->page = NULL;
1680 }
1681 }
1682
1683 /* there also may be some cached data from a chained receive */
1684 if (rx_ring->rx_skb_top) {
1685 dev_kfree_skb(rx_ring->rx_skb_top);
1686 rx_ring->rx_skb_top = NULL;
1687 }
1688
bc7f75fa
AK		 1689 /* Zero out the descriptor ring */
1690 memset(rx_ring->desc, 0, rx_ring->size);
1691
1692 rx_ring->next_to_clean = 0;
1693 rx_ring->next_to_use = 0;
b94b5028 1694 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1695
c5083cf6 1696 writel(0, rx_ring->head);
b485dbae 1697 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 1698 e1000e_update_rdt_wa(rx_ring, 0);
1699 else
1700 writel(0, rx_ring->tail);
bc7f75fa
AK		 1701}
1702
a8f88ff5
JB		 1703static void e1000e_downshift_workaround(struct work_struct *work)
1704{
1705 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1706 struct e1000_adapter,
1707 downshift_task);
a8f88ff5 1708
615b32af
JB		 1709 if (test_bit(__E1000_DOWN, &adapter->state))
1710 return;
1711
a8f88ff5
JB		 1712 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1713}
1714
bc7f75fa
AK		 1715/**
1716 * e1000_intr_msi - Interrupt Handler
1717 * @irq: interrupt number
1718 * @data: pointer to a network interface device structure
1719 **/
8bb62869 1720static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1721{
1722 struct net_device *netdev = data;
1723 struct e1000_adapter *adapter = netdev_priv(netdev);
1724 struct e1000_hw *hw = &adapter->hw;
1725 u32 icr = er32(ICR);
1726
e921eb1a 1727 /* read ICR disables interrupts using IAM */
573cca8c 1728 if (icr & E1000_ICR_LSC) {
f92518dd 1729 hw->mac.get_link_status = true;
e921eb1a 1730 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1731 * disconnect (LSC) before accessing any PHY registers
1732 */
bc7f75fa
AK		 1733 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1734 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1735 schedule_work(&adapter->downshift_task);
bc7f75fa 1736
e921eb1a 1737 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1738 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1739 * adapter in watchdog
1740 */
bc7f75fa
AK		 1741 if (netif_carrier_ok(netdev) &&
1742 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1743 /* disable receives */
1744 u32 rctl = er32(RCTL);
1745 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1746 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1747 }
1748 /* guard against interrupt when we're going down */
1749 if (!test_bit(__E1000_DOWN, &adapter->state))
1750 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1751 }
1752
94fb848b
BA		 1753 /* Reset on uncorrectable ECC error */
1754 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1755 u32 pbeccsts = er32(PBECCSTS);
1756
1757 adapter->corr_errors +=
1758 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1759 adapter->uncorr_errors +=
1760 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1761 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1762
1763 /* Do the reset outside of interrupt context */
1764 schedule_work(&adapter->reset_task);
1765
1766 /* return immediately since reset is imminent */
1767 return IRQ_HANDLED;
1768 }
1769
288379f0 1770 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1771 adapter->total_tx_bytes = 0;
1772 adapter->total_tx_packets = 0;
1773 adapter->total_rx_bytes = 0;
1774 adapter->total_rx_packets = 0;
288379f0 1775 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1776 }
1777
1778 return IRQ_HANDLED;
1779}
1780
1781/**
1782 * e1000_intr - Interrupt Handler
1783 * @irq: interrupt number
1784 * @data: pointer to a network interface device structure
1785 **/
8bb62869 1786static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1787{
1788 struct net_device *netdev = data;
1789 struct e1000_adapter *adapter = netdev_priv(netdev);
1790 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1791 u32 rctl, icr = er32(ICR);
4662e82b 1792
a68ea775 1793 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1794 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1795
e921eb1a 1796 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1797 * not set, then the adapter didn't send an interrupt
1798 */
bc7f75fa
AK		 1799 if (!(icr & E1000_ICR_INT_ASSERTED))
1800 return IRQ_NONE;
1801
e921eb1a 1802 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1803 * interrupts are masked. No need for the
1804 * IMC write
1805 */
bc7f75fa 1806
573cca8c 1807 if (icr & E1000_ICR_LSC) {
f92518dd 1808 hw->mac.get_link_status = true;
e921eb1a 1809 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1810 * disconnect (LSC) before accessing any PHY registers
1811 */
bc7f75fa
AK		 1812 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1813 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1814 schedule_work(&adapter->downshift_task);
bc7f75fa 1815
e921eb1a 1816 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1817 * For packet buffer work-around on link down event;
1818 * disable receives here in the ISR and
1819 * reset adapter in watchdog
1820 */
1821 if (netif_carrier_ok(netdev) &&
1822 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1823 /* disable receives */
1824 rctl = er32(RCTL);
1825 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1826 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1827 }
1828 /* guard against interrupt when we're going down */
1829 if (!test_bit(__E1000_DOWN, &adapter->state))
1830 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1831 }
1832
94fb848b
BA		 1833 /* Reset on uncorrectable ECC error */
1834 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1835 u32 pbeccsts = er32(PBECCSTS);
1836
1837 adapter->corr_errors +=
1838 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1839 adapter->uncorr_errors +=
1840 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1841 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1842
1843 /* Do the reset outside of interrupt context */
1844 schedule_work(&adapter->reset_task);
1845
1846 /* return immediately since reset is imminent */
1847 return IRQ_HANDLED;
1848 }
1849
288379f0 1850 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1851 adapter->total_tx_bytes = 0;
1852 adapter->total_tx_packets = 0;
1853 adapter->total_rx_bytes = 0;
1854 adapter->total_rx_packets = 0;
288379f0 1855 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1856 }
1857
1858 return IRQ_HANDLED;
1859}
1860
8bb62869 1861static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1862{
1863 struct net_device *netdev = data;
1864 struct e1000_adapter *adapter = netdev_priv(netdev);
1865 struct e1000_hw *hw = &adapter->hw;
1866 u32 icr = er32(ICR);
1867
1868 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1869 if (!test_bit(__E1000_DOWN, &adapter->state))
1870 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1871 return IRQ_NONE;
1872 }
1873
1874 if (icr & adapter->eiac_mask)
1875 ew32(ICS, (icr & adapter->eiac_mask));
1876
1877 if (icr & E1000_ICR_OTHER) {
1878 if (!(icr & E1000_ICR_LSC))
1879 goto no_link_interrupt;
f92518dd 1880 hw->mac.get_link_status = true;
4662e82b
BA		 1881 /* guard against interrupt when we're going down */
1882 if (!test_bit(__E1000_DOWN, &adapter->state))
1883 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1884 }
1885
1886no_link_interrupt:
a3c69fef
JB		 1887 if (!test_bit(__E1000_DOWN, &adapter->state))
1888 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1889
1890 return IRQ_HANDLED;
1891}
1892
8bb62869 1893static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1894{
1895 struct net_device *netdev = data;
1896 struct e1000_adapter *adapter = netdev_priv(netdev);
1897 struct e1000_hw *hw = &adapter->hw;
1898 struct e1000_ring *tx_ring = adapter->tx_ring;
1899
4662e82b
BA		 1900 adapter->total_tx_bytes = 0;
1901 adapter->total_tx_packets = 0;
1902
55aa6985 1903 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1904 /* Ring was not completely cleaned, so fire another interrupt */
1905 ew32(ICS, tx_ring->ims_val);
1906
1907 return IRQ_HANDLED;
1908}
1909
8bb62869 1910static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1911{
1912 struct net_device *netdev = data;
1913 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1914 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1915
1916 /* Write the ITR value calculated at the end of the
1917 * previous interrupt.
1918 */
55aa6985
BA		 1919 if (rx_ring->set_itr) {
1920 writel(1000000000 / (rx_ring->itr_val * 256),
1921 rx_ring->itr_register);
1922 rx_ring->set_itr = 0;
4662e82b
BA		 1923 }
1924
288379f0 1925 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1926 adapter->total_rx_bytes = 0;
1927 adapter->total_rx_packets = 0;
288379f0 1928 __napi_schedule(&adapter->napi);
4662e82b
BA		 1929 }
1930 return IRQ_HANDLED;
1931}
1932
1933/**
1934 * e1000_configure_msix - Configure MSI-X hardware
1935 *
1936 * e1000_configure_msix sets up the hardware to properly
1937 * generate MSI-X interrupts.
1938 **/
1939static void e1000_configure_msix(struct e1000_adapter *adapter)
1940{
1941 struct e1000_hw *hw = &adapter->hw;
1942 struct e1000_ring *rx_ring = adapter->rx_ring;
1943 struct e1000_ring *tx_ring = adapter->tx_ring;
1944 int vector = 0;
1945 u32 ctrl_ext, ivar = 0;
1946
1947 adapter->eiac_mask = 0;
1948
1949 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1950 if (hw->mac.type == e1000_82574) {
1951 u32 rfctl = er32(RFCTL);
1952 rfctl |= E1000_RFCTL_ACK_DIS;
1953 ew32(RFCTL, rfctl);
1954 }
1955
4662e82b
BA		 1956 /* Configure Rx vector */
1957 rx_ring->ims_val = E1000_IMS_RXQ0;
1958 adapter->eiac_mask |= rx_ring->ims_val;
1959 if (rx_ring->itr_val)
1960 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1961 rx_ring->itr_register);
4662e82b 1962 else
c5083cf6 1963 writel(1, rx_ring->itr_register);
4662e82b
BA		 1964 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1965
1966 /* Configure Tx vector */
1967 tx_ring->ims_val = E1000_IMS_TXQ0;
1968 vector++;
1969 if (tx_ring->itr_val)
1970 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1971 tx_ring->itr_register);
4662e82b 1972 else
c5083cf6 1973 writel(1, tx_ring->itr_register);
4662e82b
BA		 1974 adapter->eiac_mask |= tx_ring->ims_val;
1975 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1976
1977 /* set vector for Other Causes, e.g. link changes */
1978 vector++;
1979 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1980 if (rx_ring->itr_val)
1981 writel(1000000000 / (rx_ring->itr_val * 256),
1982 hw->hw_addr + E1000_EITR_82574(vector));
1983 else
1984 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1985
1986 /* Cause Tx interrupts on every write back */
1987 ivar |= (1 << 31);
1988
1989 ew32(IVAR, ivar);
1990
1991 /* enable MSI-X PBA support */
1992 ctrl_ext = er32(CTRL_EXT);
1993 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1994
1995 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 1996 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1997 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1998 ew32(CTRL_EXT, ctrl_ext);
1999 e1e_flush();
2000}
2001
2002void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2003{
2004 if (adapter->msix_entries) {
2005 pci_disable_msix(adapter->pdev);
2006 kfree(adapter->msix_entries);
2007 adapter->msix_entries = NULL;
2008 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2009 pci_disable_msi(adapter->pdev);
2010 adapter->flags &= ~FLAG_MSI_ENABLED;
2011 }
4662e82b
BA		 2012}
2013
2014/**
2015 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2016 *
2017 * Attempt to configure interrupts using the best available
2018 * capabilities of the hardware and kernel.
2019 **/
2020void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2021{
2022 int err;
8e86acd7 2023 int i;
4662e82b
BA		 2024
2025 switch (adapter->int_mode) {
2026 case E1000E_INT_MODE_MSIX:
2027 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2028 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2029 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2030 sizeof(struct
2031 msix_entry),
2032 GFP_KERNEL);
4662e82b 2033 if (adapter->msix_entries) {
0cc7c959
AG		 2034 struct e1000_adapter *a = adapter;
2035
8e86acd7 2036 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2037 adapter->msix_entries[i].entry = i;
2038
0cc7c959
AG		 2039 err = pci_enable_msix_range(a->pdev,
2040 a->msix_entries,
2041 a->num_vectors,
2042 a->num_vectors);
2043 if (err > 0)
4662e82b
BA		 2044 return;
2045 }
2046 /* MSI-X failed, so fall through and try MSI */
ef456f85 2047 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2048 e1000e_reset_interrupt_capability(adapter);
2049 }
2050 adapter->int_mode = E1000E_INT_MODE_MSI;
2051 /* Fall through */
2052 case E1000E_INT_MODE_MSI:
2053 if (!pci_enable_msi(adapter->pdev)) {
2054 adapter->flags |= FLAG_MSI_ENABLED;
2055 } else {
2056 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2057 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2058 }
2059 /* Fall through */
2060 case E1000E_INT_MODE_LEGACY:
2061 /* Don't do anything; this is the system default */
2062 break;
2063 }
8e86acd7
JK		 2064
2065 /* store the number of vectors being used */
2066 adapter->num_vectors = 1;
4662e82b
BA		 2067}
2068
2069/**
2070 * e1000_request_msix - Initialize MSI-X interrupts
2071 *
2072 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2073 * kernel.
2074 **/
2075static int e1000_request_msix(struct e1000_adapter *adapter)
2076{
2077 struct net_device *netdev = adapter->netdev;
2078 int err = 0, vector = 0;
2079
2080 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2081 snprintf(adapter->rx_ring->name,
2082 sizeof(adapter->rx_ring->name) - 1,
2083 "%s-rx-0", netdev->name);
4662e82b
BA		 2084 else
2085 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2086 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2087 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2088 netdev);
2089 if (err)
5015e53a 2090 return err;
c5083cf6
BA		 2091 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2092 E1000_EITR_82574(vector);
4662e82b
BA		 2093 adapter->rx_ring->itr_val = adapter->itr;
2094 vector++;
2095
2096 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2097 snprintf(adapter->tx_ring->name,
2098 sizeof(adapter->tx_ring->name) - 1,
2099 "%s-tx-0", netdev->name);
4662e82b
BA		 2100 else
2101 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2102 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2103 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2104 netdev);
2105 if (err)
5015e53a 2106 return err;
c5083cf6
BA		 2107 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2108 E1000_EITR_82574(vector);
4662e82b
BA		 2109 adapter->tx_ring->itr_val = adapter->itr;
2110 vector++;
2111
2112 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2113 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2114 if (err)
5015e53a 2115 return err;
4662e82b
BA		 2116
2117 e1000_configure_msix(adapter);
5015e53a 2118
4662e82b 2119 return 0;
4662e82b
BA		 2120}
2121
f8d59f78
BA		 2122/**
2123 * e1000_request_irq - initialize interrupts
2124 *
2125 * Attempts to configure interrupts using the best available
2126 * capabilities of the hardware and kernel.
2127 **/
bc7f75fa
AK		 2128static int e1000_request_irq(struct e1000_adapter *adapter)
2129{
2130 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2131 int err;
2132
4662e82b
BA		 2133 if (adapter->msix_entries) {
2134 err = e1000_request_msix(adapter);
2135 if (!err)
2136 return err;
2137 /* fall back to MSI */
2138 e1000e_reset_interrupt_capability(adapter);
2139 adapter->int_mode = E1000E_INT_MODE_MSI;
2140 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2141 }
4662e82b 2142 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2143 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2144 netdev->name, netdev);
2145 if (!err)
2146 return err;
bc7f75fa 2147
4662e82b
BA		 2148 /* fall back to legacy interrupt */
2149 e1000e_reset_interrupt_capability(adapter);
2150 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2151 }
2152
a0607fd3 2153 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2154 netdev->name, netdev);
2155 if (err)
2156 e_err("Unable to allocate interrupt, Error: %d\n", err);
2157
bc7f75fa
AK		 2158 return err;
2159}
2160
2161static void e1000_free_irq(struct e1000_adapter *adapter)
2162{
2163 struct net_device *netdev = adapter->netdev;
2164
4662e82b
BA		 2165 if (adapter->msix_entries) {
2166 int vector = 0;
2167
2168 free_irq(adapter->msix_entries[vector].vector, netdev);
2169 vector++;
2170
2171 free_irq(adapter->msix_entries[vector].vector, netdev);
2172 vector++;
2173
2174 /* Other Causes interrupt vector */
2175 free_irq(adapter->msix_entries[vector].vector, netdev);
2176 return;
bc7f75fa 2177 }
4662e82b
BA		 2178
2179 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2180}
2181
2182/**
2183 * e1000_irq_disable - Mask off interrupt generation on the NIC
2184 **/
2185static void e1000_irq_disable(struct e1000_adapter *adapter)
2186{
2187 struct e1000_hw *hw = &adapter->hw;
2188
bc7f75fa 2189 ew32(IMC, ~0);
4662e82b
BA		 2190 if (adapter->msix_entries)
2191 ew32(EIAC_82574, 0);
bc7f75fa 2192 e1e_flush();
8e86acd7
JK		 2193
2194 if (adapter->msix_entries) {
2195 int i;
2196 for (i = 0; i < adapter->num_vectors; i++)
2197 synchronize_irq(adapter->msix_entries[i].vector);
2198 } else {
2199 synchronize_irq(adapter->pdev->irq);
2200 }
bc7f75fa
AK		 2201}
2202
2203/**
2204 * e1000_irq_enable - Enable default interrupt generation settings
2205 **/
2206static void e1000_irq_enable(struct e1000_adapter *adapter)
2207{
2208 struct e1000_hw *hw = &adapter->hw;
2209
4662e82b
BA		 2210 if (adapter->msix_entries) {
2211 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2212 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2213 } else if (hw->mac.type == e1000_pch_lpt) {
2214 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2215 } else {
2216 ew32(IMS, IMS_ENABLE_MASK);
2217 }
74ef9c39 2218 e1e_flush();
bc7f75fa
AK		 2219}
2220
2221/**
31dbe5b4 2222 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2223 * @adapter: address of board private structure
2224 *
31dbe5b4 2225 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2226 * For ASF and Pass Through versions of f/w this means that
2227 * the driver is loaded. For AMT version (only with 82573)
2228 * of the f/w this means that the network i/f is open.
2229 **/
31dbe5b4 2230void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2231{
2232 struct e1000_hw *hw = &adapter->hw;
2233 u32 ctrl_ext;
2234 u32 swsm;
2235
2236 /* Let firmware know the driver has taken over */
2237 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2238 swsm = er32(SWSM);
2239 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2240 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2241 ctrl_ext = er32(CTRL_EXT);
ad68076e 2242 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2243 }
2244}
2245
2246/**
31dbe5b4 2247 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2248 * @adapter: address of board private structure
2249 *
31dbe5b4 2250 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2251 * For ASF and Pass Through versions of f/w this means that the
2252 * driver is no longer loaded. For AMT version (only with 82573) i
2253 * of the f/w this means that the network i/f is closed.
2254 *
2255 **/
31dbe5b4 2256void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2257{
2258 struct e1000_hw *hw = &adapter->hw;
2259 u32 ctrl_ext;
2260 u32 swsm;
2261
2262 /* Let firmware taken over control of h/w */
2263 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2264 swsm = er32(SWSM);
2265 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2266 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2267 ctrl_ext = er32(CTRL_EXT);
ad68076e 2268 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2269 }
2270}
2271
bc7f75fa 2272/**
49ce9c2c 2273 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2274 **/
2275static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2276 struct e1000_ring *ring)
2277{
2278 struct pci_dev *pdev = adapter->pdev;
2279
2280 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2281 GFP_KERNEL);
2282 if (!ring->desc)
2283 return -ENOMEM;
2284
2285 return 0;
2286}
2287
2288/**
2289 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2290 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2291 *
2292 * Return 0 on success, negative on failure
2293 **/
55aa6985 2294int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2295{
55aa6985 2296 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2297 int err = -ENOMEM, size;
2298
2299 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2300 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2301 if (!tx_ring->buffer_info)
2302 goto err;
bc7f75fa
AK		 2303
2304 /* round up to nearest 4K */
2305 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2306 tx_ring->size = ALIGN(tx_ring->size, 4096);
2307
2308 err = e1000_alloc_ring_dma(adapter, tx_ring);
2309 if (err)
2310 goto err;
2311
2312 tx_ring->next_to_use = 0;
2313 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2314
2315 return 0;
2316err:
2317 vfree(tx_ring->buffer_info);
44defeb3 2318 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2319 return err;
2320}
2321
2322/**
2323 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2324 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2325 *
2326 * Returns 0 on success, negative on failure
2327 **/
55aa6985 2328int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2329{
55aa6985 2330 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2331 struct e1000_buffer *buffer_info;
2332 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2333
2334 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2335 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2336 if (!rx_ring->buffer_info)
2337 goto err;
bc7f75fa 2338
47f44e40
AK		 2339 for (i = 0; i < rx_ring->count; i++) {
2340 buffer_info = &rx_ring->buffer_info[i];
2341 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2342 sizeof(struct e1000_ps_page),
2343 GFP_KERNEL);
2344 if (!buffer_info->ps_pages)
2345 goto err_pages;
2346 }
bc7f75fa
AK		 2347
2348 desc_len = sizeof(union e1000_rx_desc_packet_split);
2349
2350 /* Round up to nearest 4K */
2351 rx_ring->size = rx_ring->count * desc_len;
2352 rx_ring->size = ALIGN(rx_ring->size, 4096);
2353
2354 err = e1000_alloc_ring_dma(adapter, rx_ring);
2355 if (err)
47f44e40 2356 goto err_pages;
bc7f75fa
AK		 2357
2358 rx_ring->next_to_clean = 0;
2359 rx_ring->next_to_use = 0;
2360 rx_ring->rx_skb_top = NULL;
2361
2362 return 0;
47f44e40
AK		 2363
2364err_pages:
2365 for (i = 0; i < rx_ring->count; i++) {
2366 buffer_info = &rx_ring->buffer_info[i];
2367 kfree(buffer_info->ps_pages);
2368 }
bc7f75fa
AK		 2369err:
2370 vfree(rx_ring->buffer_info);
e9262447 2371 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2372 return err;
2373}
2374
2375/**
2376 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2377 * @tx_ring: Tx descriptor ring
bc7f75fa 2378 **/
55aa6985 2379static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2380{
55aa6985 2381 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2382 struct e1000_buffer *buffer_info;
2383 unsigned long size;
2384 unsigned int i;
2385
2386 for (i = 0; i < tx_ring->count; i++) {
2387 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2388 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2389 }
2390
3f0cfa3b 2391 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2392 size = sizeof(struct e1000_buffer) * tx_ring->count;
2393 memset(tx_ring->buffer_info, 0, size);
2394
2395 memset(tx_ring->desc, 0, tx_ring->size);
2396
2397 tx_ring->next_to_use = 0;
2398 tx_ring->next_to_clean = 0;
2399
c5083cf6 2400 writel(0, tx_ring->head);
b485dbae 2401 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 2402 e1000e_update_tdt_wa(tx_ring, 0);
2403 else
2404 writel(0, tx_ring->tail);
bc7f75fa
AK		 2405}
2406
2407/**
2408 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2409 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2410 *
2411 * Free all transmit software resources
2412 **/
55aa6985 2413void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2414{
55aa6985 2415 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2416 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2417
55aa6985 2418 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2419
2420 vfree(tx_ring->buffer_info);
2421 tx_ring->buffer_info = NULL;
2422
2423 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2424 tx_ring->dma);
2425 tx_ring->desc = NULL;
2426}
2427
2428/**
2429 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2430 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2431 *
2432 * Free all receive software resources
2433 **/
55aa6985 2434void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2435{
55aa6985 2436 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2437 struct pci_dev *pdev = adapter->pdev;
47f44e40 2438 int i;
bc7f75fa 2439
55aa6985 2440 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2441
b1cdfead 2442 for (i = 0; i < rx_ring->count; i++)
47f44e40 2443 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2444
bc7f75fa
AK		 2445 vfree(rx_ring->buffer_info);
2446 rx_ring->buffer_info = NULL;
2447
bc7f75fa
AK		 2448 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2449 rx_ring->dma);
2450 rx_ring->desc = NULL;
2451}
2452
2453/**
2454 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2455 * @adapter: pointer to adapter
2456 * @itr_setting: current adapter->itr
2457 * @packets: the number of packets during this measurement interval
2458 * @bytes: the number of bytes during this measurement interval
2459 *
bc7f75fa
AK		 2460 * Stores a new ITR value based on packets and byte
2461 * counts during the last interrupt. The advantage of per interrupt
2462 * computation is faster updates and more accurate ITR for the current
2463 * traffic pattern. Constants in this function were computed
2464 * based on theoretical maximum wire speed and thresholds were set based
2465 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2466 * while increasing bulk throughput. This functionality is controlled
2467 * by the InterruptThrottleRate module parameter.
bc7f75fa 2468 **/
8bb62869 2469static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2470{
2471 unsigned int retval = itr_setting;
2472
2473 if (packets == 0)
5015e53a 2474 return itr_setting;
bc7f75fa
AK		 2475
2476 switch (itr_setting) {
2477 case lowest_latency:
2478 /* handle TSO and jumbo frames */
362e20ca 2479 if (bytes / packets > 8000)
bc7f75fa 2480 retval = bulk_latency;
b1cdfead 2481 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2482 retval = low_latency;
bc7f75fa 2483 break;
e80bd1d1 2484 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2485 if (bytes > 10000) {
2486 /* this if handles the TSO accounting */
362e20ca 2487 if (bytes / packets > 8000)
bc7f75fa 2488 retval = bulk_latency;
362e20ca 2489 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2490 retval = bulk_latency;
b1cdfead 2491 else if ((packets > 35))
bc7f75fa 2492 retval = lowest_latency;
362e20ca 2493 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2494 retval = bulk_latency;
2495 } else if (packets <= 2 && bytes < 512) {
2496 retval = lowest_latency;
2497 }
2498 break;
e80bd1d1 2499 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2500 if (bytes > 25000) {
b1cdfead 2501 if (packets > 35)
bc7f75fa 2502 retval = low_latency;
bc7f75fa
AK		 2503 } else if (bytes < 6000) {
2504 retval = low_latency;
2505 }
2506 break;
2507 }
2508
bc7f75fa
AK		 2509 return retval;
2510}
2511
2512static void e1000_set_itr(struct e1000_adapter *adapter)
2513{
bc7f75fa
AK		 2514 u16 current_itr;
2515 u32 new_itr = adapter->itr;
2516
2517 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2518 if (adapter->link_speed != SPEED_1000) {
2519 current_itr = 0;
2520 new_itr = 4000;
2521 goto set_itr_now;
2522 }
2523
828bac87
BA		 2524 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2525 new_itr = 0;
2526 goto set_itr_now;
2527 }
2528
8bb62869
BA		 2529 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2530 adapter->total_tx_packets,
2531 adapter->total_tx_bytes);
bc7f75fa
AK		 2532 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2533 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2534 adapter->tx_itr = low_latency;
2535
8bb62869
BA		 2536 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2537 adapter->total_rx_packets,
2538 adapter->total_rx_bytes);
bc7f75fa
AK		 2539 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2540 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2541 adapter->rx_itr = low_latency;
2542
2543 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2544
bc7f75fa 2545 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2546 switch (current_itr) {
bc7f75fa
AK		 2547 case lowest_latency:
2548 new_itr = 70000;
2549 break;
2550 case low_latency:
e80bd1d1 2551 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2552 break;
2553 case bulk_latency:
2554 new_itr = 4000;
2555 break;
2556 default:
2557 break;
2558 }
2559
2560set_itr_now:
2561 if (new_itr != adapter->itr) {
e921eb1a 2562 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2563 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2564 * increasing
2565 */
bc7f75fa 2566 new_itr = new_itr > adapter->itr ?
f0ff4398 2567 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2568 adapter->itr = new_itr;
4662e82b
BA		 2569 adapter->rx_ring->itr_val = new_itr;
2570 if (adapter->msix_entries)
2571 adapter->rx_ring->set_itr = 1;
2572 else
e3d14b08 2573 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2574 }
2575}
2576
22a4cca2
MV		 2577/**
2578 * e1000e_write_itr - write the ITR value to the appropriate registers
2579 * @adapter: address of board private structure
2580 * @itr: new ITR value to program
2581 *
2582 * e1000e_write_itr determines if the adapter is in MSI-X mode
2583 * and, if so, writes the EITR registers with the ITR value.
2584 * Otherwise, it writes the ITR value into the ITR register.
2585 **/
2586void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2587{
2588 struct e1000_hw *hw = &adapter->hw;
2589 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2590
2591 if (adapter->msix_entries) {
2592 int vector;
2593
2594 for (vector = 0; vector < adapter->num_vectors; vector++)
2595 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2596 } else {
2597 ew32(ITR, new_itr);
2598 }
2599}
2600
4662e82b
BA		 2601/**
2602 * e1000_alloc_queues - Allocate memory for all rings
2603 * @adapter: board private structure to initialize
2604 **/
9f9a12f8 2605static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2606{
55aa6985
BA		 2607 int size = sizeof(struct e1000_ring);
2608
2609 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2610 if (!adapter->tx_ring)
2611 goto err;
55aa6985
BA		 2612 adapter->tx_ring->count = adapter->tx_ring_count;
2613 adapter->tx_ring->adapter = adapter;
4662e82b 2614
55aa6985 2615 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2616 if (!adapter->rx_ring)
2617 goto err;
55aa6985
BA		 2618 adapter->rx_ring->count = adapter->rx_ring_count;
2619 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2620
2621 return 0;
2622err:
2623 e_err("Unable to allocate memory for queues\n");
2624 kfree(adapter->rx_ring);
2625 kfree(adapter->tx_ring);
2626 return -ENOMEM;
2627}
2628
bc7f75fa 2629/**
c58c8a78 2630 * e1000e_poll - NAPI Rx polling callback
ad68076e 2631 * @napi: struct associated with this polling callback
c58c8a78 2632 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2633 **/
c58c8a78 2634static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2635{
c58c8a78
BA		 2636 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2637 napi);
4662e82b 2638 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2639 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2640 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2641
4cf1653a 2642 adapter = netdev_priv(poll_dev);
bc7f75fa 2643
c58c8a78
BA		 2644 if (!adapter->msix_entries ||
2645 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2646 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2647
c58c8a78 2648 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2649
12d04a3c 2650 if (!tx_cleaned)
c58c8a78 2651 work_done = weight;
bc7f75fa 2652
c58c8a78
BA		 2653 /* If weight not fully consumed, exit the polling mode */
2654 if (work_done < weight) {
bc7f75fa
AK		 2655 if (adapter->itr_setting & 3)
2656 e1000_set_itr(adapter);
288379f0 2657 napi_complete(napi);
a3c69fef
JB		 2658 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2659 if (adapter->msix_entries)
2660 ew32(IMS, adapter->rx_ring->ims_val);
2661 else
2662 e1000_irq_enable(adapter);
2663 }
bc7f75fa
AK		 2664 }
2665
2666 return work_done;
2667}
2668
80d5c368 2669static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2670 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2671{
2672 struct e1000_adapter *adapter = netdev_priv(netdev);
2673 struct e1000_hw *hw = &adapter->hw;
2674 u32 vfta, index;
2675
2676 /* don't update vlan cookie if already programmed */
2677 if ((adapter->hw.mng_cookie.status &
2678 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2679 (vid == adapter->mng_vlan_id))
8e586137 2680 return 0;
caaddaf8 2681
bc7f75fa 2682 /* add VID to filter table */
caaddaf8
BA		 2683 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2684 index = (vid >> 5) & 0x7F;
2685 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2686 vfta |= (1 << (vid & 0x1F));
2687 hw->mac.ops.write_vfta(hw, index, vfta);
2688 }
86d70e53
JK		 2689
2690 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2691
2692 return 0;
bc7f75fa
AK		 2693}
2694
80d5c368 2695static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2696 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2697{
2698 struct e1000_adapter *adapter = netdev_priv(netdev);
2699 struct e1000_hw *hw = &adapter->hw;
2700 u32 vfta, index;
2701
bc7f75fa
AK		 2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id)) {
2705 /* release control to f/w */
31dbe5b4 2706 e1000e_release_hw_control(adapter);
8e586137 2707 return 0;
bc7f75fa
AK		 2708 }
2709
2710 /* remove VID from filter table */
caaddaf8
BA		 2711 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2712 index = (vid >> 5) & 0x7F;
2713 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2714 vfta &= ~(1 << (vid & 0x1F));
2715 hw->mac.ops.write_vfta(hw, index, vfta);
2716 }
86d70e53
JK		 2717
2718 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2719
2720 return 0;
bc7f75fa
AK		 2721}
2722
86d70e53
JK		 2723/**
2724 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2725 * @adapter: board private structure to initialize
2726 **/
2727static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2728{
2729 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2730 struct e1000_hw *hw = &adapter->hw;
2731 u32 rctl;
bc7f75fa 2732
86d70e53
JK		 2733 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2734 /* disable VLAN receive filtering */
2735 rctl = er32(RCTL);
2736 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2737 ew32(RCTL, rctl);
2738
2739 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2740 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2741 adapter->mng_vlan_id);
86d70e53 2742 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2743 }
bc7f75fa
AK		 2744 }
2745}
2746
86d70e53
JK		 2747/**
2748 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2749 * @adapter: board private structure to initialize
2750 **/
2751static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2752{
2753 struct e1000_hw *hw = &adapter->hw;
2754 u32 rctl;
2755
2756 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2757 /* enable VLAN receive filtering */
2758 rctl = er32(RCTL);
2759 rctl |= E1000_RCTL_VFE;
2760 rctl &= ~E1000_RCTL_CFIEN;
2761 ew32(RCTL, rctl);
2762 }
2763}
bc7f75fa 2764
86d70e53
JK		 2765/**
2766 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2767 * @adapter: board private structure to initialize
2768 **/
2769static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2770{
bc7f75fa 2771 struct e1000_hw *hw = &adapter->hw;
86d70e53 2772 u32 ctrl;
bc7f75fa 2773
86d70e53
JK		 2774 /* disable VLAN tag insert/strip */
2775 ctrl = er32(CTRL);
2776 ctrl &= ~E1000_CTRL_VME;
2777 ew32(CTRL, ctrl);
2778}
bc7f75fa 2779
86d70e53
JK		 2780/**
2781 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2782 * @adapter: board private structure to initialize
2783 **/
2784static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2785{
2786 struct e1000_hw *hw = &adapter->hw;
2787 u32 ctrl;
bc7f75fa 2788
86d70e53
JK		 2789 /* enable VLAN tag insert/strip */
2790 ctrl = er32(CTRL);
2791 ctrl |= E1000_CTRL_VME;
2792 ew32(CTRL, ctrl);
2793}
bc7f75fa 2794
86d70e53
JK		 2795static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2796{
2797 struct net_device *netdev = adapter->netdev;
2798 u16 vid = adapter->hw.mng_cookie.vlan_id;
2799 u16 old_vid = adapter->mng_vlan_id;
2800
e5fe2541 2801 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2802 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2803 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2804 }
2805
86d70e53 2806 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2807 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2808}
2809
2810static void e1000_restore_vlan(struct e1000_adapter *adapter)
2811{
2812 u16 vid;
2813
80d5c368 2814 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2815
86d70e53 2816 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2817 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2818}
2819
cd791618 2820static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2821{
2822 struct e1000_hw *hw = &adapter->hw;
cd791618 2823 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2824
2825 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2826 return;
2827
2828 manc = er32(MANC);
2829
e921eb1a 2830 /* enable receiving management packets to the host. this will probably
bc7f75fa 2831 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2832 * the packets will be handled on SMBUS
2833 */
bc7f75fa
AK		 2834 manc |= E1000_MANC_EN_MNG2HOST;
2835 manc2h = er32(MANC2H);
cd791618
BA		 2836
2837 switch (hw->mac.type) {
2838 default:
2839 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2840 break;
2841 case e1000_82574:
2842 case e1000_82583:
e921eb1a 2843 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2844 * if so, enable it.
2845 */
2846 for (i = 0, j = 0; i < 8; i++) {
2847 mdef = er32(MDEF(i));
2848
2849 /* Ignore filters with anything other than IPMI ports */
3b21b508 2850 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2851 continue;
2852
2853 /* Enable this decision filter in MANC2H */
2854 if (mdef)
2855 manc2h |= (1 << i);
2856
2857 j |= mdef;
2858 }
2859
2860 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2861 break;
2862
2863 /* Create new decision filter in an empty filter */
2864 for (i = 0, j = 0; i < 8; i++)
2865 if (er32(MDEF(i)) == 0) {
2866 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2867 E1000_MDEF_PORT_664));
2868 manc2h |= (1 << 1);
2869 j++;
2870 break;
2871 }
2872
2873 if (!j)
2874 e_warn("Unable to create IPMI pass-through filter\n");
2875 break;
2876 }
2877
bc7f75fa
AK		 2878 ew32(MANC2H, manc2h);
2879 ew32(MANC, manc);
2880}
2881
2882/**
af667a29 2883 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2884 * @adapter: board private structure
2885 *
2886 * Configure the Tx unit of the MAC after a reset.
2887 **/
2888static void e1000_configure_tx(struct e1000_adapter *adapter)
2889{
2890 struct e1000_hw *hw = &adapter->hw;
2891 struct e1000_ring *tx_ring = adapter->tx_ring;
2892 u64 tdba;
c550b121 2893 u32 tdlen, tarc;
bc7f75fa
AK		 2894
2895 /* Setup the HW Tx Head and Tail descriptor pointers */
2896 tdba = tx_ring->dma;
2897 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2898 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2899 ew32(TDBAH(0), (tdba >> 32));
2900 ew32(TDLEN(0), tdlen);
2901 ew32(TDH(0), 0);
2902 ew32(TDT(0), 0);
2903 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2904 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2905
bc7f75fa
AK		 2906 /* Set the Tx Interrupt Delay register */
2907 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2908 /* Tx irq moderation */
bc7f75fa
AK		 2909 ew32(TADV, adapter->tx_abs_int_delay);
2910
3a3b7586
JB		 2911 if (adapter->flags2 & FLAG2_DMA_BURST) {
2912 u32 txdctl = er32(TXDCTL(0));
2913 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2914 E1000_TXDCTL_WTHRESH);
e921eb1a 2915 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2916 * hardware to use the bus more efficiently in bursts, depends
2917 * on the tx_int_delay to be enabled,
8edc0e62 2918 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2919 * hthresh = 1 ==> prefetch when one or more available
2920 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2921 * BEWARE: this seems to work but should be considered first if
af667a29 2922 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2923 */
2924 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2925 ew32(TXDCTL(0), txdctl);
3a3b7586 2926 }
56032be7
BA		 2927 /* erratum work around: set txdctl the same for both queues */
2928 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2929
bc7f75fa 2930 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2931 tarc = er32(TARC(0));
e921eb1a 2932 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2933 * gigabit link later
2934 */
bc7f75fa
AK		 2935#define SPEED_MODE_BIT (1 << 21)
2936 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2937 ew32(TARC(0), tarc);
bc7f75fa
AK		 2938 }
2939
2940 /* errata: program both queues to unweighted RR */
2941 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2942 tarc = er32(TARC(0));
bc7f75fa 2943 tarc |= 1;
e9ec2c0f
JK		 2944 ew32(TARC(0), tarc);
2945 tarc = er32(TARC(1));
bc7f75fa 2946 tarc |= 1;
e9ec2c0f 2947 ew32(TARC(1), tarc);
bc7f75fa
AK		 2948 }
2949
bc7f75fa
AK		 2950 /* Setup Transmit Descriptor Settings for eop descriptor */
2951 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2952
2953 /* only set IDE if we are delaying interrupts using the timers */
2954 if (adapter->tx_int_delay)
2955 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2956
2957 /* enable Report Status bit */
2958 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2959
57cde763 2960 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2961}
2962
2963/**
2964 * e1000_setup_rctl - configure the receive control registers
2965 * @adapter: Board private structure
2966 **/
2967#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2968 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2969static void e1000_setup_rctl(struct e1000_adapter *adapter)
2970{
2971 struct e1000_hw *hw = &adapter->hw;
2972 u32 rctl, rfctl;
bc7f75fa
AK		 2973 u32 pages = 0;
2974
2fbe4526 2975 /* Workaround Si errata on PCHx - configure jumbo frame flow */
da1e2046
BA		 2976 if ((hw->mac.type >= e1000_pch2lan) &&
2977 (adapter->netdev->mtu > ETH_DATA_LEN) &&
2978 e1000_lv_jumbo_workaround_ich8lan(hw, true))
2979 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473 2980
bc7f75fa
AK		 2981 /* Program MC offset vector base */
2982 rctl = er32(RCTL);
2983 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2984 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 2985 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2986 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 2987
2988 /* Do not Store bad packets */
2989 rctl &= ~E1000_RCTL_SBP;
2990
2991 /* Enable Long Packet receive */
2992 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2993 rctl &= ~E1000_RCTL_LPE;
2994 else
2995 rctl |= E1000_RCTL_LPE;
2996
eb7c3adb
JK		 2997 /* Some systems expect that the CRC is included in SMBUS traffic. The
2998 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2999 * host memory when this is enabled
3000 */
3001 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3002 rctl |= E1000_RCTL_SECRC;
5918bd88 3003
a4f58f54
BA		 3004 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3005 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3006 u16 phy_data;
3007
3008 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3009 phy_data &= 0xfff8;
3010 phy_data |= (1 << 2);
3011 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3012
3013 e1e_rphy(hw, 22, &phy_data);
3014 phy_data &= 0x0fff;
3015 phy_data |= (1 << 14);
3016 e1e_wphy(hw, 0x10, 0x2823);
3017 e1e_wphy(hw, 0x11, 0x0003);
3018 e1e_wphy(hw, 22, phy_data);
3019 }
3020
bc7f75fa
AK		 3021 /* Setup buffer sizes */
3022 rctl &= ~E1000_RCTL_SZ_4096;
3023 rctl |= E1000_RCTL_BSEX;
3024 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3025 case 2048:
3026 default:
3027 rctl |= E1000_RCTL_SZ_2048;
3028 rctl &= ~E1000_RCTL_BSEX;
3029 break;
3030 case 4096:
3031 rctl |= E1000_RCTL_SZ_4096;
3032 break;
3033 case 8192:
3034 rctl |= E1000_RCTL_SZ_8192;
3035 break;
3036 case 16384:
3037 rctl |= E1000_RCTL_SZ_16384;
3038 break;
3039 }
3040
5f450212
BA		 3041 /* Enable Extended Status in all Receive Descriptors */
3042 rfctl = er32(RFCTL);
3043 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3044 ew32(RFCTL, rfctl);
5f450212 3045
e921eb1a 3046 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3047 * header is placed in skb->data and the packet data is
3048 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3049 * In the case of a non-split, skb->data is linearly filled,
3050 * followed by the page buffers. Therefore, skb->data is
3051 * sized to hold the largest protocol header.
3052 *
3053 * allocations using alloc_page take too long for regular MTU
3054 * so only enable packet split for jumbo frames
3055 *
3056 * Using pages when the page size is greater than 16k wastes
3057 * a lot of memory, since we allocate 3 pages at all times
3058 * per packet.
3059 */
bc7f75fa 3060 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3061 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3062 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3063 else
3064 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3065
3066 if (adapter->rx_ps_pages) {
90da0669
BA		 3067 u32 psrctl = 0;
3068
140a7480
AK		 3069 /* Enable Packet split descriptors */
3070 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3071
e5fe2541 3072 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3073
3074 switch (adapter->rx_ps_pages) {
3075 case 3:
e5fe2541
BA		 3076 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3077 /* fall-through */
bc7f75fa 3078 case 2:
e5fe2541
BA		 3079 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3080 /* fall-through */
bc7f75fa 3081 case 1:
e5fe2541 3082 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3083 break;
3084 }
3085
3086 ew32(PSRCTL, psrctl);
3087 }
3088
cf955e6c
BG		 3089 /* This is useful for sniffing bad packets. */
3090 if (adapter->netdev->features & NETIF_F_RXALL) {
3091 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3092 * in e1000e_set_rx_mode
3093 */
e80bd1d1
BA		 3094 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3095 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3096 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3097
e80bd1d1
BA		 3098 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3099 E1000_RCTL_DPF | /* Allow filtered pause */
3100 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3101 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3102 * and that breaks VLANs.
3103 */
3104 }
3105
bc7f75fa 3106 ew32(RCTL, rctl);
318a94d6 3107 /* just started the receive unit, no need to restart */
12d43f7d 3108 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3109}
3110
3111/**
3112 * e1000_configure_rx - Configure Receive Unit after Reset
3113 * @adapter: board private structure
3114 *
3115 * Configure the Rx unit of the MAC after a reset.
3116 **/
3117static void e1000_configure_rx(struct e1000_adapter *adapter)
3118{
3119 struct e1000_hw *hw = &adapter->hw;
3120 struct e1000_ring *rx_ring = adapter->rx_ring;
3121 u64 rdba;
3122 u32 rdlen, rctl, rxcsum, ctrl_ext;
3123
3124 if (adapter->rx_ps_pages) {
3125 /* this is a 32 byte descriptor */
3126 rdlen = rx_ring->count *
af667a29 3127 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3128 adapter->clean_rx = e1000_clean_rx_irq_ps;
3129 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3130 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3131 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3132 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3133 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3134 } else {
5f450212 3135 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3136 adapter->clean_rx = e1000_clean_rx_irq;
3137 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3138 }
3139
3140 /* disable receives while setting up the descriptors */
3141 rctl = er32(RCTL);
7f99ae63
BA		 3142 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3143 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3144 e1e_flush();
1bba4386 3145 usleep_range(10000, 20000);
bc7f75fa 3146
3a3b7586 3147 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3148 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3149 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3150 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3151 * granularity = 01
3152 * wthresh = 04,
3153 * hthresh = 04,
3154 * pthresh = 0x20
3155 */
3156 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3157 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3158
e921eb1a 3159 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3160 * the value was not set by the user via module options
3161 */
3162 if (adapter->rx_int_delay == DEFAULT_RDTR)
3163 adapter->rx_int_delay = BURST_RDTR;
3164 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3165 adapter->rx_abs_int_delay = BURST_RADV;
3166 }
3167
bc7f75fa
AK		 3168 /* set the Receive Delay Timer Register */
3169 ew32(RDTR, adapter->rx_int_delay);
3170
3171 /* irq moderation */
3172 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3173 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3174 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3175
3176 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3177 /* Auto-Mask interrupts upon ICR access */
3178 ctrl_ext |= E1000_CTRL_EXT_IAME;
3179 ew32(IAM, 0xffffffff);
3180 ew32(CTRL_EXT, ctrl_ext);
3181 e1e_flush();
3182
e921eb1a 3183 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3184 * the Base and Length of the Rx Descriptor Ring
3185 */
bc7f75fa 3186 rdba = rx_ring->dma;
1e36052e
BA		 3187 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3188 ew32(RDBAH(0), (rdba >> 32));
3189 ew32(RDLEN(0), rdlen);
3190 ew32(RDH(0), 0);
3191 ew32(RDT(0), 0);
3192 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3193 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3194
3195 /* Enable Receive Checksum Offload for TCP and UDP */
3196 rxcsum = er32(RXCSUM);
2e1706f2 3197 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3198 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3199 else
bc7f75fa 3200 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3201 ew32(RXCSUM, rxcsum);
3202
3e35d991
BA		 3203 /* With jumbo frames, excessive C-state transition latencies result
3204 * in dropped transactions.
3205 */
3206 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3207 u32 lat =
3208 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3209 adapter->max_frame_size) * 8 / 1000;
3210
3211 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3212 u32 rxdctl = er32(RXDCTL(0));
3213 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3214 }
3e35d991
BA		 3215
3216 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3217 } else {
3218 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3219 PM_QOS_DEFAULT_VALUE);
97ac8cae 3220 }
bc7f75fa
AK		 3221
3222 /* Enable Receives */
3223 ew32(RCTL, rctl);
3224}
3225
3226/**
ef9b965a
JB		 3227 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3228 * @netdev: network interface device structure
bc7f75fa 3229 *
ef9b965a
JB		 3230 * Writes multicast address list to the MTA hash table.
3231 * Returns: -ENOMEM on failure
3232 * 0 on no addresses written
3233 * X on writing X addresses to MTA
3234 */
3235static int e1000e_write_mc_addr_list(struct net_device *netdev)
3236{
3237 struct e1000_adapter *adapter = netdev_priv(netdev);
3238 struct e1000_hw *hw = &adapter->hw;
3239 struct netdev_hw_addr *ha;
3240 u8 *mta_list;
3241 int i;
3242
3243 if (netdev_mc_empty(netdev)) {
3244 /* nothing to program, so clear mc list */
3245 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3246 return 0;
3247 }
3248
3249 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3250 if (!mta_list)
3251 return -ENOMEM;
3252
3253 /* update_mc_addr_list expects a packed array of only addresses. */
3254 i = 0;
3255 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3256 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3257
3258 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3259 kfree(mta_list);
3260
3261 return netdev_mc_count(netdev);
3262}
3263
3264/**
3265 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3266 * @netdev: network interface device structure
bc7f75fa 3267 *
ef9b965a
JB		 3268 * Writes unicast address list to the RAR table.
3269 * Returns: -ENOMEM on failure/insufficient address space
3270 * 0 on no addresses written
3271 * X on writing X addresses to the RAR table
bc7f75fa 3272 **/
ef9b965a 3273static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3274{
ef9b965a
JB		 3275 struct e1000_adapter *adapter = netdev_priv(netdev);
3276 struct e1000_hw *hw = &adapter->hw;
3277 unsigned int rar_entries = hw->mac.rar_entry_count;
3278 int count = 0;
3279
3280 /* save a rar entry for our hardware address */
3281 rar_entries--;
3282
3283 /* save a rar entry for the LAA workaround */
3284 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3285 rar_entries--;
3286
3287 /* return ENOMEM indicating insufficient memory for addresses */
3288 if (netdev_uc_count(netdev) > rar_entries)
3289 return -ENOMEM;
3290
3291 if (!netdev_uc_empty(netdev) && rar_entries) {
3292 struct netdev_hw_addr *ha;
3293
e921eb1a 3294 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3295 * combining
3296 */
3297 netdev_for_each_uc_addr(ha, netdev) {
3298 if (!rar_entries)
3299 break;
69e1e019 3300 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3301 count++;
3302 }
3303 }
3304
3305 /* zero out the remaining RAR entries not used above */
3306 for (; rar_entries > 0; rar_entries--) {
3307 ew32(RAH(rar_entries), 0);
3308 ew32(RAL(rar_entries), 0);
3309 }
3310 e1e_flush();
3311
3312 return count;
bc7f75fa
AK		 3313}
3314
3315/**
ef9b965a 3316 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3317 * @netdev: network interface device structure
3318 *
ef9b965a
JB		 3319 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3320 * address list or the network interface flags are updated. This routine is
3321 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3322 * promiscuous mode, and all-multi behavior.
3323 **/
ef9b965a 3324static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3325{
3326 struct e1000_adapter *adapter = netdev_priv(netdev);
3327 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3328 u32 rctl;
bc7f75fa
AK		 3329
3330 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3331 rctl = er32(RCTL);
3332
ef9b965a
JB		 3333 /* clear the affected bits */
3334 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3335
bc7f75fa
AK		 3336 if (netdev->flags & IFF_PROMISC) {
3337 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3338 /* Do not hardware filter VLANs in promisc mode */
3339 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3340 } else {
ef9b965a 3341 int count;
3d3a1676 3342
746b9f02
PM		 3343 if (netdev->flags & IFF_ALLMULTI) {
3344 rctl |= E1000_RCTL_MPE;
746b9f02 3345 } else {
e921eb1a 3346 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3347 * then we should just turn on promiscuous mode so
3348 * that we can at least receive multicast traffic
3349 */
3350 count = e1000e_write_mc_addr_list(netdev);
3351 if (count < 0)
3352 rctl |= E1000_RCTL_MPE;
746b9f02 3353 }
86d70e53 3354 e1000e_vlan_filter_enable(adapter);
e921eb1a 3355 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3356 * sufficient space to store all the addresses then enable
3357 * unicast promiscuous mode
bc7f75fa 3358 */
ef9b965a
JB		 3359 count = e1000e_write_uc_addr_list(netdev);
3360 if (count < 0)
3361 rctl |= E1000_RCTL_UPE;
bc7f75fa 3362 }
86d70e53 3363
ef9b965a
JB		 3364 ew32(RCTL, rctl);
3365
f646968f 3366 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3367 e1000e_vlan_strip_enable(adapter);
3368 else
3369 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3370}
3371
70495a50
BA		 3372static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3373{
3374 struct e1000_hw *hw = &adapter->hw;
3375 u32 mrqc, rxcsum;
3376 int i;
3377 static const u32 rsskey[10] = {
3378 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3379 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3380 };
3381
3382 /* Fill out hash function seed */
3383 for (i = 0; i < 10; i++)
3384 ew32(RSSRK(i), rsskey[i]);
3385
3386 /* Direct all traffic to queue 0 */
3387 for (i = 0; i < 32; i++)
3388 ew32(RETA(i), 0);
3389
e921eb1a 3390 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3391 * descriptor on writeback.
3392 */
3393 rxcsum = er32(RXCSUM);
3394 rxcsum |= E1000_RXCSUM_PCSD;
3395
3396 ew32(RXCSUM, rxcsum);
3397
3398 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3399 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3400 E1000_MRQC_RSS_FIELD_IPV6 |
3401 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3402 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3403
3404 ew32(MRQC, mrqc);
3405}
3406
b67e1913
BA		 3407/**
3408 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3409 * @adapter: board private structure
3410 * @timinca: pointer to returned time increment attributes
3411 *
3412 * Get attributes for incrementing the System Time Register SYSTIML/H at
3413 * the default base frequency, and set the cyclecounter shift value.
3414 **/
d89777bf 3415s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3416{
3417 struct e1000_hw *hw = &adapter->hw;
3418 u32 incvalue, incperiod, shift;
3419
3420 /* Make sure clock is enabled on I217 before checking the frequency */
3421 if ((hw->mac.type == e1000_pch_lpt) &&
3422 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3423 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3424 u32 fextnvm7 = er32(FEXTNVM7);
3425
3426 if (!(fextnvm7 & (1 << 0))) {
3427 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3428 e1e_flush();
3429 }
3430 }
3431
3432 switch (hw->mac.type) {
3433 case e1000_pch2lan:
3434 case e1000_pch_lpt:
3435 /* On I217, the clock frequency is 25MHz or 96MHz as
3436 * indicated by the System Clock Frequency Indication
3437 */
3438 if ((hw->mac.type != e1000_pch_lpt) ||
3439 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3440 /* Stable 96MHz frequency */
3441 incperiod = INCPERIOD_96MHz;
3442 incvalue = INCVALUE_96MHz;
3443 shift = INCVALUE_SHIFT_96MHz;
3444 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3445 break;
3446 }
3447 /* fall-through */
3448 case e1000_82574:
3449 case e1000_82583:
3450 /* Stable 25MHz frequency */
3451 incperiod = INCPERIOD_25MHz;
3452 incvalue = INCVALUE_25MHz;
3453 shift = INCVALUE_SHIFT_25MHz;
3454 adapter->cc.shift = shift;
3455 break;
3456 default:
3457 return -EINVAL;
3458 }
3459
3460 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3461 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3462
3463 return 0;
3464}
3465
3466/**
3467 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3468 * @adapter: board private structure
3469 *
3470 * Outgoing time stamping can be enabled and disabled. Play nice and
3471 * disable it when requested, although it shouldn't cause any overhead
3472 * when no packet needs it. At most one packet in the queue may be
3473 * marked for time stamping, otherwise it would be impossible to tell
3474 * for sure to which packet the hardware time stamp belongs.
3475 *
3476 * Incoming time stamping has to be configured via the hardware filters.
3477 * Not all combinations are supported, in particular event type has to be
3478 * specified. Matching the kind of event packet is not supported, with the
3479 * exception of "all V2 events regardless of level 2 or 4".
3480 **/
62d7e3a2
BH		 3481static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3482 struct hwtstamp_config *config)
b67e1913
BA		 3483{
3484 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3485 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3486 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3487 u32 rxmtrl = 0;
3488 u16 rxudp = 0;
3489 bool is_l4 = false;
3490 bool is_l2 = false;
b67e1913
BA		 3491 u32 regval;
3492 s32 ret_val;
3493
3494 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3495 return -EINVAL;
3496
3497 /* flags reserved for future extensions - must be zero */
3498 if (config->flags)
3499 return -EINVAL;
3500
3501 switch (config->tx_type) {
3502 case HWTSTAMP_TX_OFF:
3503 tsync_tx_ctl = 0;
3504 break;
3505 case HWTSTAMP_TX_ON:
3506 break;
3507 default:
3508 return -ERANGE;
3509 }
3510
3511 switch (config->rx_filter) {
3512 case HWTSTAMP_FILTER_NONE:
3513 tsync_rx_ctl = 0;
3514 break;
d89777bf
BA		 3515 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3516 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3517 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3518 is_l4 = true;
3519 break;
3520 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3521 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3522 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3523 is_l4 = true;
3524 break;
3525 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3526 /* Also time stamps V2 L2 Path Delay Request/Response */
3527 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3528 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3529 is_l2 = true;
3530 break;
3531 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3532 /* Also time stamps V2 L2 Path Delay Request/Response. */
3533 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3534 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3535 is_l2 = true;
3536 break;
3537 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3538 /* Hardware cannot filter just V2 L4 Sync messages;
3539 * fall-through to V2 (both L2 and L4) Sync.
3540 */
3541 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3542 /* Also time stamps V2 Path Delay Request/Response. */
3543 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3544 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3545 is_l2 = true;
3546 is_l4 = true;
3547 break;
3548 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3549 /* Hardware cannot filter just V2 L4 Delay Request messages;
3550 * fall-through to V2 (both L2 and L4) Delay Request.
3551 */
3552 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3553 /* Also time stamps V2 Path Delay Request/Response. */
3554 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3555 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3556 is_l2 = true;
3557 is_l4 = true;
3558 break;
3559 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3560 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3561 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3562 * fall-through to all V2 (both L2 and L4) Events.
3563 */
3564 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3565 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3566 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3567 is_l2 = true;
3568 is_l4 = true;
3569 break;
3570 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3571 /* For V1, the hardware can only filter Sync messages or
3572 * Delay Request messages but not both so fall-through to
3573 * time stamp all packets.
3574 */
b67e1913 3575 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3576 is_l2 = true;
3577 is_l4 = true;
b67e1913
BA		 3578 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3579 config->rx_filter = HWTSTAMP_FILTER_ALL;
3580 break;
3581 default:
3582 return -ERANGE;
3583 }
3584
62d7e3a2
BH		 3585 adapter->hwtstamp_config = *config;
3586
b67e1913
BA		 3587 /* enable/disable Tx h/w time stamping */
3588 regval = er32(TSYNCTXCTL);
3589 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3590 regval |= tsync_tx_ctl;
3591 ew32(TSYNCTXCTL, regval);
3592 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3593 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3594 e_err("Timesync Tx Control register not set as expected\n");
3595 return -EAGAIN;
3596 }
3597
3598 /* enable/disable Rx h/w time stamping */
3599 regval = er32(TSYNCRXCTL);
3600 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3601 regval |= tsync_rx_ctl;
3602 ew32(TSYNCRXCTL, regval);
3603 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3604 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3605 (regval & (E1000_TSYNCRXCTL_ENABLED |
3606 E1000_TSYNCRXCTL_TYPE_MASK))) {
3607 e_err("Timesync Rx Control register not set as expected\n");
3608 return -EAGAIN;
3609 }
3610
d89777bf
BA		 3611 /* L2: define ethertype filter for time stamped packets */
3612 if (is_l2)
3613 rxmtrl |= ETH_P_1588;
3614
3615 /* define which PTP packets get time stamped */
3616 ew32(RXMTRL, rxmtrl);
3617
3618 /* Filter by destination port */
3619 if (is_l4) {
3620 rxudp = PTP_EV_PORT;
3621 cpu_to_be16s(&rxudp);
3622 }
3623 ew32(RXUDP, rxudp);
3624
3625 e1e_flush();
3626
b67e1913 3627 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3628 er32(RXSTMPH);
3629 er32(TXSTMPH);
b67e1913
BA		 3630
3631 /* Get and set the System Time Register SYSTIM base frequency */
3632 ret_val = e1000e_get_base_timinca(adapter, &regval);
3633 if (ret_val)
3634 return ret_val;
3635 ew32(TIMINCA, regval);
3636
3637 /* reset the ns time counter */
3638 timecounter_init(&adapter->tc, &adapter->cc,
3639 ktime_to_ns(ktime_get_real()));
3640
3641 return 0;
3642}
3643
bc7f75fa 3644/**
ad68076e 3645 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3646 * @adapter: private board structure
3647 **/
3648static void e1000_configure(struct e1000_adapter *adapter)
3649{
55aa6985
BA		 3650 struct e1000_ring *rx_ring = adapter->rx_ring;
3651
ef9b965a 3652 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3653
3654 e1000_restore_vlan(adapter);
cd791618 3655 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3656
3657 e1000_configure_tx(adapter);
70495a50
BA		 3658
3659 if (adapter->netdev->features & NETIF_F_RXHASH)
3660 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3661 e1000_setup_rctl(adapter);
3662 e1000_configure_rx(adapter);
55aa6985 3663 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3664}
3665
3666/**
3667 * e1000e_power_up_phy - restore link in case the phy was powered down
3668 * @adapter: address of board private structure
3669 *
3670 * The phy may be powered down to save power and turn off link when the
3671 * driver is unloaded and wake on lan is not enabled (among others)
3672 * *** this routine MUST be followed by a call to e1000e_reset ***
3673 **/
3674void e1000e_power_up_phy(struct e1000_adapter *adapter)
3675{
17f208de
BA		 3676 if (adapter->hw.phy.ops.power_up)
3677 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3678
3679 adapter->hw.mac.ops.setup_link(&adapter->hw);
3680}
3681
3682/**
3683 * e1000_power_down_phy - Power down the PHY
3684 *
17f208de
BA		 3685 * Power down the PHY so no link is implied when interface is down.
3686 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3687 */
3688static void e1000_power_down_phy(struct e1000_adapter *adapter)
3689{
17f208de
BA		 3690 if (adapter->hw.phy.ops.power_down)
3691 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3692}
3693
3694/**
3695 * e1000e_reset - bring the hardware into a known good state
3696 *
3697 * This function boots the hardware and enables some settings that
3698 * require a configuration cycle of the hardware - those cannot be
3699 * set/changed during runtime. After reset the device needs to be
ad68076e 3700 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3701 */
3702void e1000e_reset(struct e1000_adapter *adapter)
3703{
3704 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3705 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3706 struct e1000_hw *hw = &adapter->hw;
3707 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3708 u32 pba = adapter->pba;
bc7f75fa
AK		 3709 u16 hwm;
3710
ad68076e 3711 /* reset Packet Buffer Allocation to default */
318a94d6 3712 ew32(PBA, pba);
df762464 3713
318a94d6 3714 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3715 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3716 * large enough to accommodate two full transmit packets,
3717 * rounded up to the next 1KB and expressed in KB. Likewise,
3718 * the Rx FIFO should be large enough to accommodate at least
3719 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3720 * expressed in KB.
3721 */
df762464 3722 pba = er32(PBA);
bc7f75fa 3723 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3724 tx_space = pba >> 16;
bc7f75fa 3725 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3726 pba &= 0xffff;
e921eb1a 3727 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3728 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3729 */
3730 min_tx_space = (adapter->max_frame_size +
e5fe2541 3731 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3732 min_tx_space = ALIGN(min_tx_space, 1024);
3733 min_tx_space >>= 10;
3734 /* software strips receive CRC, so leave room for it */
318a94d6 3735 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3736 min_rx_space = ALIGN(min_rx_space, 1024);
3737 min_rx_space >>= 10;
3738
e921eb1a 3739 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3740 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3741 * allocation, take space away from current Rx allocation
3742 */
df762464
AK		 3743 if ((tx_space < min_tx_space) &&
3744 ((min_tx_space - tx_space) < pba)) {
3745 pba -= min_tx_space - tx_space;
bc7f75fa 3746
e921eb1a 3747 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3748 * adjustment
ad68076e 3749 */
79d4e908 3750 if (pba < min_rx_space)
df762464 3751 pba = min_rx_space;
bc7f75fa 3752 }
df762464
AK		 3753
3754 ew32(PBA, pba);
bc7f75fa
AK		 3755 }
3756
e921eb1a 3757 /* flow control settings
ad68076e 3758 *
38eb394e 3759 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3760 * (or the size used for early receive) above it in the Rx FIFO.
3761 * Set it to the lower of:
3762 * - 90% of the Rx FIFO size, and
38eb394e 3763 * - the full Rx FIFO size minus one full frame
ad68076e 3764 */
d3738bb8
BA		 3765 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3766 fc->pause_time = 0xFFFF;
3767 else
3768 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3769 fc->send_xon = true;
d3738bb8
BA		 3770 fc->current_mode = fc->requested_mode;
3771
3772 switch (hw->mac.type) {
79d4e908
BA		 3773 case e1000_ich9lan:
3774 case e1000_ich10lan:
3775 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3776 pba = 14;
3777 ew32(PBA, pba);
3778 fc->high_water = 0x2800;
3779 fc->low_water = fc->high_water - 8;
3780 break;
3781 }
3782 /* fall-through */
d3738bb8 3783 default:
79d4e908
BA		 3784 hwm = min(((pba << 10) * 9 / 10),
3785 ((pba << 10) - adapter->max_frame_size));
d3738bb8 3786
e80bd1d1 3787 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 3788 fc->low_water = fc->high_water - 8;
3789 break;
3790 case e1000_pchlan:
e921eb1a 3791 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3792 * loads. If hangs persist, try disabling Tx flow control.
3793 */
3794 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3795 fc->high_water = 0x3500;
e80bd1d1 3796 fc->low_water = 0x1500;
38eb394e
BA		 3797 } else {
3798 fc->high_water = 0x5000;
e80bd1d1 3799 fc->low_water = 0x3000;
38eb394e 3800 }
a305595b 3801 fc->refresh_time = 0x1000;
d3738bb8
BA		 3802 break;
3803 case e1000_pch2lan:
2fbe4526 3804 case e1000_pch_lpt:
d3738bb8 3805 fc->refresh_time = 0x0400;
347b5201
BA		 3806
3807 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3808 fc->high_water = 0x05C20;
3809 fc->low_water = 0x05048;
3810 fc->pause_time = 0x0650;
3811 break;
828bac87 3812 }
347b5201 3813
ce345e08
BA		 3814 pba = 14;
3815 ew32(PBA, pba);
347b5201
BA		 3816 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3817 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3818 break;
38eb394e 3819 }
bc7f75fa 3820
e921eb1a 3821 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3822 * maximum size per Tx descriptor limited only to the transmit
3823 * allocation of the packet buffer minus 96 bytes with an upper
3824 * limit of 24KB due to receive synchronization limitations.
3825 */
3826 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3827 24 << 10);
3828
e921eb1a 3829 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3830 * fit in receive buffer.
828bac87
BA		 3831 */
3832 if (adapter->itr_setting & 0x3) {
79d4e908 3833 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3834 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3835 dev_info(&adapter->pdev->dev,
17e813ec 3836 "Interrupt Throttle Rate off\n");
828bac87 3837 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3838 e1000e_write_itr(adapter, 0);
828bac87
BA		 3839 }
3840 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3841 dev_info(&adapter->pdev->dev,
17e813ec 3842 "Interrupt Throttle Rate on\n");
828bac87
BA		 3843 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3844 adapter->itr = 20000;
22a4cca2 3845 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3846 }
3847 }
3848
bc7f75fa
AK		 3849 /* Allow time for pending master requests to run */
3850 mac->ops.reset_hw(hw);
97ac8cae 3851
e921eb1a 3852 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3853 * that the network interface is in control
3854 */
c43bc57e 3855 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3856 e1000e_get_hw_control(adapter);
97ac8cae 3857
bc7f75fa
AK		 3858 ew32(WUC, 0);
3859
3860 if (mac->ops.init_hw(hw))
44defeb3 3861 e_err("Hardware Error\n");
bc7f75fa
AK		 3862
3863 e1000_update_mng_vlan(adapter);
3864
3865 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3866 ew32(VET, ETH_P_8021Q);
3867
3868 e1000e_reset_adaptive(hw);
31dbe5b4 3869
b67e1913 3870 /* initialize systim and reset the ns time counter */
62d7e3a2 3871 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
b67e1913 3872
d495bcb8
BA		 3873 /* Set EEE advertisement as appropriate */
3874 if (adapter->flags2 & FLAG2_HAS_EEE) {
3875 s32 ret_val;
3876 u16 adv_addr;
3877
3878 switch (hw->phy.type) {
3879 case e1000_phy_82579:
3880 adv_addr = I82579_EEE_ADVERTISEMENT;
3881 break;
3882 case e1000_phy_i217:
3883 adv_addr = I217_EEE_ADVERTISEMENT;
3884 break;
3885 default:
3886 dev_err(&adapter->pdev->dev,
3887 "Invalid PHY type setting EEE advertisement\n");
3888 return;
3889 }
3890
3891 ret_val = hw->phy.ops.acquire(hw);
3892 if (ret_val) {
3893 dev_err(&adapter->pdev->dev,
3894 "EEE advertisement - unable to acquire PHY\n");
3895 return;
3896 }
3897
3898 e1000_write_emi_reg_locked(hw, adv_addr,
3899 hw->dev_spec.ich8lan.eee_disable ?
3900 0 : adapter->eee_advert);
3901
3902 hw->phy.ops.release(hw);
3903 }
3904
31dbe5b4 3905 if (!netif_running(adapter->netdev) &&
28002099 3906 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 3907 e1000_power_down_phy(adapter);
31dbe5b4 3908
bc7f75fa
AK		 3909 e1000_get_phy_info(hw);
3910
918d7197
BA		 3911 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3912 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3913 u16 phy_data = 0;
e921eb1a 3914 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3915 * the return value of this function because there is nothing
ad68076e
BA		 3916 * different we would do if it failed
3917 */
bc7f75fa
AK		 3918 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3919 phy_data &= ~IGP02E1000_PM_SPD;
3920 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3921 }
bc7f75fa
AK		 3922}
3923
3924int e1000e_up(struct e1000_adapter *adapter)
3925{
3926 struct e1000_hw *hw = &adapter->hw;
3927
3928 /* hardware has been reset, we need to reload some things */
3929 e1000_configure(adapter);
3930
3931 clear_bit(__E1000_DOWN, &adapter->state);
3932
4662e82b
BA		 3933 if (adapter->msix_entries)
3934 e1000_configure_msix(adapter);
bc7f75fa
AK		 3935 e1000_irq_enable(adapter);
3936
400484fa 3937 netif_start_queue(adapter->netdev);
4cb9be7a 3938
bc7f75fa 3939 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3940 if (adapter->msix_entries)
3941 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3942 else
3943 ew32(ICS, E1000_ICS_LSC);
3944
bc7f75fa
AK		 3945 return 0;
3946}
3947
713b3c9e
JB		 3948static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3949{
3950 struct e1000_hw *hw = &adapter->hw;
3951
3952 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3953 return;
3954
3955 /* flush pending descriptor writebacks to memory */
3956 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3957 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3958
3959 /* execute the writes immediately */
3960 e1e_flush();
bf03085f 3961
e921eb1a 3962 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3963 * write is successful
3964 */
3965 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3966 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3967
3968 /* execute the writes immediately */
3969 e1e_flush();
3970}
3971
67fd4fcb
JK		 3972static void e1000e_update_stats(struct e1000_adapter *adapter);
3973
28002099
DE		 3974/**
3975 * e1000e_down - quiesce the device and optionally reset the hardware
3976 * @adapter: board private structure
3977 * @reset: boolean flag to reset the hardware or not
3978 */
3979void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 3980{
3981 struct net_device *netdev = adapter->netdev;
3982 struct e1000_hw *hw = &adapter->hw;
3983 u32 tctl, rctl;
3984
e921eb1a 3985 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3986 * reschedule our watchdog timer
3987 */
bc7f75fa
AK		 3988 set_bit(__E1000_DOWN, &adapter->state);
3989
3990 /* disable receives in the hardware */
3991 rctl = er32(RCTL);
7f99ae63
BA		 3992 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3993 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3994 /* flush and sleep below */
3995
4cb9be7a 3996 netif_stop_queue(netdev);
bc7f75fa
AK		 3997
3998 /* disable transmits in the hardware */
3999 tctl = er32(TCTL);
4000 tctl &= ~E1000_TCTL_EN;
4001 ew32(TCTL, tctl);
7f99ae63 4002
bc7f75fa
AK		 4003 /* flush both disables and wait for them to finish */
4004 e1e_flush();
1bba4386 4005 usleep_range(10000, 20000);
bc7f75fa 4006
bc7f75fa
AK		 4007 e1000_irq_disable(adapter);
4008
a3b87a4c
BA		 4009 napi_synchronize(&adapter->napi);
4010
bc7f75fa
AK		 4011 del_timer_sync(&adapter->watchdog_timer);
4012 del_timer_sync(&adapter->phy_info_timer);
4013
bc7f75fa 4014 netif_carrier_off(netdev);
67fd4fcb
JK		 4015
4016 spin_lock(&adapter->stats64_lock);
4017 e1000e_update_stats(adapter);
4018 spin_unlock(&adapter->stats64_lock);
4019
400484fa 4020 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4021 e1000_clean_tx_ring(adapter->tx_ring);
4022 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4023
bc7f75fa
AK		 4024 adapter->link_speed = 0;
4025 adapter->link_duplex = 0;
4026
da1e2046
BA		 4027 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4028 if ((hw->mac.type >= e1000_pch2lan) &&
4029 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4030 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4031 e_dbg("failed to disable jumbo frame workaround mode\n");
4032
28002099 4033 if (reset && !pci_channel_offline(adapter->pdev))
52cc3086 4034 e1000e_reset(adapter);
bc7f75fa
AK		 4035}
4036
4037void e1000e_reinit_locked(struct e1000_adapter *adapter)
4038{
4039 might_sleep();
4040 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4041 usleep_range(1000, 2000);
28002099 4042 e1000e_down(adapter, true);
bc7f75fa
AK		 4043 e1000e_up(adapter);
4044 clear_bit(__E1000_RESETTING, &adapter->state);
4045}
4046
b67e1913
BA		 4047/**
4048 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4049 * @cc: cyclecounter structure
4050 **/
4051static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4052{
4053 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4054 cc);
4055 struct e1000_hw *hw = &adapter->hw;
4056 cycle_t systim;
4057
4058 /* latch SYSTIMH on read of SYSTIML */
4059 systim = (cycle_t)er32(SYSTIML);
4060 systim |= (cycle_t)er32(SYSTIMH) << 32;
4061
4062 return systim;
4063}
4064
bc7f75fa
AK		 4065/**
4066 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4067 * @adapter: board private structure to initialize
4068 *
4069 * e1000_sw_init initializes the Adapter private data structure.
4070 * Fields are initialized based on PCI device information and
4071 * OS network device settings (MTU size).
4072 **/
9f9a12f8 4073static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4074{
bc7f75fa
AK		 4075 struct net_device *netdev = adapter->netdev;
4076
4077 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4078 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4079 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4080 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4081 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4082 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4083
67fd4fcb
JK		 4084 spin_lock_init(&adapter->stats64_lock);
4085
4662e82b 4086 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4087
4662e82b
BA		 4088 if (e1000_alloc_queues(adapter))
4089 return -ENOMEM;
bc7f75fa 4090
b67e1913
BA		 4091 /* Setup hardware time stamping cyclecounter */
4092 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4093 adapter->cc.read = e1000e_cyclecounter_read;
4094 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4095 adapter->cc.mult = 1;
4096 /* cc.shift set in e1000e_get_base_tininca() */
4097
4098 spin_lock_init(&adapter->systim_lock);
4099 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4100 }
4101
bc7f75fa 4102 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4103 e1000_irq_disable(adapter);
4104
bc7f75fa
AK		 4105 set_bit(__E1000_DOWN, &adapter->state);
4106 return 0;
bc7f75fa
AK		 4107}
4108
f8d59f78
BA		 4109/**
4110 * e1000_intr_msi_test - Interrupt Handler
4111 * @irq: interrupt number
4112 * @data: pointer to a network interface device structure
4113 **/
8bb62869 4114static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4115{
4116 struct net_device *netdev = data;
4117 struct e1000_adapter *adapter = netdev_priv(netdev);
4118 struct e1000_hw *hw = &adapter->hw;
4119 u32 icr = er32(ICR);
4120
3bb99fe2 4121 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4122 if (icr & E1000_ICR_RXSEQ) {
4123 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4124 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4125 * interrupt is handled.
4126 */
f8d59f78
BA		 4127 wmb();
4128 }
4129
4130 return IRQ_HANDLED;
4131}
4132
4133/**
4134 * e1000_test_msi_interrupt - Returns 0 for successful test
4135 * @adapter: board private struct
4136 *
4137 * code flow taken from tg3.c
4138 **/
4139static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4140{
4141 struct net_device *netdev = adapter->netdev;
4142 struct e1000_hw *hw = &adapter->hw;
4143 int err;
4144
4145 /* poll_enable hasn't been called yet, so don't need disable */
4146 /* clear any pending events */
4147 er32(ICR);
4148
4149 /* free the real vector and request a test handler */
4150 e1000_free_irq(adapter);
4662e82b 4151 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4152
4153 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4154 * MSI irq handler will unset this flag
4155 */
f8d59f78
BA		 4156 adapter->flags |= FLAG_MSI_TEST_FAILED;
4157
4158 err = pci_enable_msi(adapter->pdev);
4159 if (err)
4160 goto msi_test_failed;
4161
a0607fd3 4162 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4163 netdev->name, netdev);
4164 if (err) {
4165 pci_disable_msi(adapter->pdev);
4166 goto msi_test_failed;
4167 }
4168
e921eb1a 4169 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4170 * interrupt.
4171 */
f8d59f78
BA		 4172 wmb();
4173
4174 e1000_irq_enable(adapter);
4175
4176 /* fire an unusual interrupt on the test handler */
4177 ew32(ICS, E1000_ICS_RXSEQ);
4178 e1e_flush();
569a3aff 4179 msleep(100);
f8d59f78
BA		 4180
4181 e1000_irq_disable(adapter);
4182
bc76329d 4183 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4184
4185 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4186 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4187 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4188 } else {
068e8a30 4189 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4190 }
f8d59f78
BA		 4191
4192 free_irq(adapter->pdev->irq, netdev);
4193 pci_disable_msi(adapter->pdev);
4194
f8d59f78 4195msi_test_failed:
4662e82b 4196 e1000e_set_interrupt_capability(adapter);
068e8a30 4197 return e1000_request_irq(adapter);
f8d59f78
BA		 4198}
4199
4200/**
4201 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4202 * @adapter: board private struct
4203 *
4204 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4205 **/
4206static int e1000_test_msi(struct e1000_adapter *adapter)
4207{
4208 int err;
4209 u16 pci_cmd;
4210
4211 if (!(adapter->flags & FLAG_MSI_ENABLED))
4212 return 0;
4213
4214 /* disable SERR in case the MSI write causes a master abort */
4215 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4216 if (pci_cmd & PCI_COMMAND_SERR)
4217 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4218 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4219
4220 err = e1000_test_msi_interrupt(adapter);
4221
36f2407f
DN		 4222 /* re-enable SERR */
4223 if (pci_cmd & PCI_COMMAND_SERR) {
4224 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4225 pci_cmd |= PCI_COMMAND_SERR;
4226 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4227 }
f8d59f78 4228
f8d59f78
BA		 4229 return err;
4230}
4231
bc7f75fa
AK		 4232/**
4233 * e1000_open - Called when a network interface is made active
4234 * @netdev: network interface device structure
4235 *
4236 * Returns 0 on success, negative value on failure
4237 *
4238 * The open entry point is called when a network interface is made
4239 * active by the system (IFF_UP). At this point all resources needed
4240 * for transmit and receive operations are allocated, the interrupt
4241 * handler is registered with the OS, the watchdog timer is started,
4242 * and the stack is notified that the interface is ready.
4243 **/
4244static int e1000_open(struct net_device *netdev)
4245{
4246 struct e1000_adapter *adapter = netdev_priv(netdev);
4247 struct e1000_hw *hw = &adapter->hw;
23606cf5 4248 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4249 int err;
4250
4251 /* disallow open during test */
4252 if (test_bit(__E1000_TESTING, &adapter->state))
4253 return -EBUSY;
4254
23606cf5
RW		 4255 pm_runtime_get_sync(&pdev->dev);
4256
9c563d20
JB		 4257 netif_carrier_off(netdev);
4258
bc7f75fa 4259 /* allocate transmit descriptors */
55aa6985 4260 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4261 if (err)
4262 goto err_setup_tx;
4263
4264 /* allocate receive descriptors */
55aa6985 4265 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4266 if (err)
4267 goto err_setup_rx;
4268
e921eb1a 4269 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4270 * interface is now open and reset the part to a known state.
4271 */
4272 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4273 e1000e_get_hw_control(adapter);
11b08be8
BA		 4274 e1000e_reset(adapter);
4275 }
4276
bc7f75fa
AK		 4277 e1000e_power_up_phy(adapter);
4278
4279 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4280 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4281 e1000_update_mng_vlan(adapter);
4282
79d4e908 4283 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4284 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4285 PM_QOS_DEFAULT_VALUE);
c128ec29 4286
e921eb1a 4287 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4288 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4289 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4290 * clean_rx handler before we do so.
4291 */
bc7f75fa
AK		 4292 e1000_configure(adapter);
4293
4294 err = e1000_request_irq(adapter);
4295 if (err)
4296 goto err_req_irq;
4297
e921eb1a 4298 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4299 * ignore e1000e MSI messages, which means we need to test our MSI
4300 * interrupt now
4301 */
4662e82b 4302 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4303 err = e1000_test_msi(adapter);
4304 if (err) {
4305 e_err("Interrupt allocation failed\n");
4306 goto err_req_irq;
4307 }
4308 }
4309
bc7f75fa
AK		 4310 /* From here on the code is the same as e1000e_up() */
4311 clear_bit(__E1000_DOWN, &adapter->state);
4312
4313 napi_enable(&adapter->napi);
4314
4315 e1000_irq_enable(adapter);
4316
09357b00 4317 adapter->tx_hang_recheck = false;
4cb9be7a 4318 netif_start_queue(netdev);
d55b53ff 4319
23606cf5 4320 adapter->idle_check = true;
66148bab 4321 hw->mac.get_link_status = true;
23606cf5
RW		 4322 pm_runtime_put(&pdev->dev);
4323
bc7f75fa 4324 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4325 if (adapter->msix_entries)
4326 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4327 else
4328 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4329
4330 return 0;
4331
4332err_req_irq:
31dbe5b4 4333 e1000e_release_hw_control(adapter);
bc7f75fa 4334 e1000_power_down_phy(adapter);
55aa6985 4335 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4336err_setup_rx:
55aa6985 4337 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4338err_setup_tx:
4339 e1000e_reset(adapter);
23606cf5 4340 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4341
4342 return err;
4343}
4344
4345/**
4346 * e1000_close - Disables a network interface
4347 * @netdev: network interface device structure
4348 *
4349 * Returns 0, this is not allowed to fail
4350 *
4351 * The close entry point is called when an interface is de-activated
4352 * by the OS. The hardware is still under the drivers control, but
4353 * needs to be disabled. A global MAC reset is issued to stop the
4354 * hardware, and all transmit and receive resources are freed.
4355 **/
4356static int e1000_close(struct net_device *netdev)
4357{
4358 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4359 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4360 int count = E1000_CHECK_RESET_COUNT;
4361
4362 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4363 usleep_range(10000, 20000);
bc7f75fa
AK		 4364
4365 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4366
4367 pm_runtime_get_sync(&pdev->dev);
4368
4369 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4370 e1000e_down(adapter, true);
23606cf5
RW		 4371 e1000_free_irq(adapter);
4372 }
a3b87a4c
BA		 4373
4374 napi_disable(&adapter->napi);
4375
55aa6985
BA		 4376 e1000e_free_tx_resources(adapter->tx_ring);
4377 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4378
e921eb1a 4379 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4380 * the same ID is registered on the host OS (let 8021q kill it)
4381 */
e5fe2541 4382 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4383 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4384 adapter->mng_vlan_id);
bc7f75fa 4385
e921eb1a 4386 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4387 * interface is now closed
4388 */
31dbe5b4
BA		 4389 if ((adapter->flags & FLAG_HAS_AMT) &&
4390 !test_bit(__E1000_TESTING, &adapter->state))
4391 e1000e_release_hw_control(adapter);
bc7f75fa 4392
3e35d991 4393 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4394
23606cf5
RW		 4395 pm_runtime_put_sync(&pdev->dev);
4396
bc7f75fa
AK		 4397 return 0;
4398}
fc830b78 4399
bc7f75fa
AK		 4400/**
4401 * e1000_set_mac - Change the Ethernet Address of the NIC
4402 * @netdev: network interface device structure
4403 * @p: pointer to an address structure
4404 *
4405 * Returns 0 on success, negative on failure
4406 **/
4407static int e1000_set_mac(struct net_device *netdev, void *p)
4408{
4409 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4410 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4411 struct sockaddr *addr = p;
4412
4413 if (!is_valid_ether_addr(addr->sa_data))
4414 return -EADDRNOTAVAIL;
4415
4416 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4417 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4418
69e1e019 4419 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4420
4421 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4422 /* activate the work around */
4423 e1000e_set_laa_state_82571(&adapter->hw, 1);
4424
e921eb1a 4425 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4426 * between the time RAR[0] gets clobbered and the time it
4427 * gets fixed (in e1000_watchdog), the actual LAA is in one
4428 * of the RARs and no incoming packets directed to this port
4429 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4430 * RAR[14]
4431 */
69e1e019
BA		 4432 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4433 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4434 }
4435
4436 return 0;
4437}
4438
a8f88ff5
JB		 4439/**
4440 * e1000e_update_phy_task - work thread to update phy
4441 * @work: pointer to our work struct
4442 *
4443 * this worker thread exists because we must acquire a
4444 * semaphore to read the phy, which we could msleep while
4445 * waiting for it, and we can't msleep in a timer.
4446 **/
4447static void e1000e_update_phy_task(struct work_struct *work)
4448{
4449 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4450 struct e1000_adapter,
4451 update_phy_task);
a03206ed 4452 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4453
4454 if (test_bit(__E1000_DOWN, &adapter->state))
4455 return;
4456
a03206ed
DE		 4457 e1000_get_phy_info(hw);
4458
4459 /* Enable EEE on 82579 after link up */
4460 if (hw->phy.type == e1000_phy_82579)
4461 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4462}
4463
e921eb1a
BA		 4464/**
4465 * e1000_update_phy_info - timre call-back to update PHY info
4466 * @data: pointer to adapter cast into an unsigned long
4467 *
ad68076e
BA		 4468 * Need to wait a few seconds after link up to get diagnostic information from
4469 * the phy
e921eb1a 4470 **/
bc7f75fa
AK		 4471static void e1000_update_phy_info(unsigned long data)
4472{
53aa82da 4473 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4474
4475 if (test_bit(__E1000_DOWN, &adapter->state))
4476 return;
4477
a8f88ff5 4478 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4479}
4480
8c7bbb92
BA		 4481/**
4482 * e1000e_update_phy_stats - Update the PHY statistics counters
4483 * @adapter: board private structure
2b6b168d
BA		 4484 *
4485 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4486 **/
4487static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4488{
4489 struct e1000_hw *hw = &adapter->hw;
4490 s32 ret_val;
4491 u16 phy_data;
4492
4493 ret_val = hw->phy.ops.acquire(hw);
4494 if (ret_val)
4495 return;
4496
e921eb1a 4497 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4498 * If not, set to the page with the PHY status registers.
4499 */
2b6b168d 4500 hw->phy.addr = 1;
8c7bbb92
BA		 4501 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4502 &phy_data);
4503 if (ret_val)
4504 goto release;
2b6b168d
BA		 4505 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4506 ret_val = hw->phy.ops.set_page(hw,
4507 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4508 if (ret_val)
4509 goto release;
4510 }
4511
8c7bbb92 4512 /* Single Collision Count */
2b6b168d
BA		 4513 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4514 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4515 if (!ret_val)
4516 adapter->stats.scc += phy_data;
4517
4518 /* Excessive Collision Count */
2b6b168d
BA		 4519 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4520 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4521 if (!ret_val)
4522 adapter->stats.ecol += phy_data;
4523
4524 /* Multiple Collision Count */
2b6b168d
BA		 4525 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4526 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4527 if (!ret_val)
4528 adapter->stats.mcc += phy_data;
4529
4530 /* Late Collision Count */
2b6b168d
BA		 4531 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4532 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4533 if (!ret_val)
4534 adapter->stats.latecol += phy_data;
4535
4536 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4537 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4538 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4539 if (!ret_val)
4540 hw->mac.collision_delta = phy_data;
4541
4542 /* Defer Count */
2b6b168d
BA		 4543 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4544 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4545 if (!ret_val)
4546 adapter->stats.dc += phy_data;
4547
4548 /* Transmit with no CRS */
2b6b168d
BA		 4549 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4550 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4551 if (!ret_val)
4552 adapter->stats.tncrs += phy_data;
4553
4554release:
4555 hw->phy.ops.release(hw);
4556}
4557
bc7f75fa
AK		 4558/**
4559 * e1000e_update_stats - Update the board statistics counters
4560 * @adapter: board private structure
4561 **/
67fd4fcb 4562static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4563{
7274c20f 4564 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4565 struct e1000_hw *hw = &adapter->hw;
4566 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4567
e921eb1a 4568 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4569 * connection is down.
4570 */
4571 if (adapter->link_speed == 0)
4572 return;
4573 if (pci_channel_offline(pdev))
4574 return;
4575
bc7f75fa
AK		 4576 adapter->stats.crcerrs += er32(CRCERRS);
4577 adapter->stats.gprc += er32(GPRC);
7c25769f 4578 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4579 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4580 adapter->stats.bprc += er32(BPRC);
4581 adapter->stats.mprc += er32(MPRC);
4582 adapter->stats.roc += er32(ROC);
4583
bc7f75fa 4584 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4585
4586 /* Half-duplex statistics */
4587 if (adapter->link_duplex == HALF_DUPLEX) {
4588 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4589 e1000e_update_phy_stats(adapter);
4590 } else {
4591 adapter->stats.scc += er32(SCC);
4592 adapter->stats.ecol += er32(ECOL);
4593 adapter->stats.mcc += er32(MCC);
4594 adapter->stats.latecol += er32(LATECOL);
4595 adapter->stats.dc += er32(DC);
4596
4597 hw->mac.collision_delta = er32(COLC);
4598
4599 if ((hw->mac.type != e1000_82574) &&
4600 (hw->mac.type != e1000_82583))
4601 adapter->stats.tncrs += er32(TNCRS);
4602 }
4603 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4604 }
8c7bbb92 4605
bc7f75fa
AK		 4606 adapter->stats.xonrxc += er32(XONRXC);
4607 adapter->stats.xontxc += er32(XONTXC);
4608 adapter->stats.xoffrxc += er32(XOFFRXC);
4609 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4610 adapter->stats.gptc += er32(GPTC);
7c25769f 4611 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4612 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4613 adapter->stats.rnbc += er32(RNBC);
4614 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4615
4616 adapter->stats.mptc += er32(MPTC);
4617 adapter->stats.bptc += er32(BPTC);
4618
4619 /* used for adaptive IFS */
4620
4621 hw->mac.tx_packet_delta = er32(TPT);
4622 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4623
4624 adapter->stats.algnerrc += er32(ALGNERRC);
4625 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4626 adapter->stats.cexterr += er32(CEXTERR);
4627 adapter->stats.tsctc += er32(TSCTC);
4628 adapter->stats.tsctfc += er32(TSCTFC);
4629
bc7f75fa 4630 /* Fill out the OS statistics structure */
7274c20f
AK		 4631 netdev->stats.multicast = adapter->stats.mprc;
4632 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4633
4634 /* Rx Errors */
4635
e921eb1a 4636 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4637 * our own version based on RUC and ROC
4638 */
7274c20f 4639 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4640 adapter->stats.crcerrs + adapter->stats.algnerrc +
4641 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4642 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4643 adapter->stats.roc;
7274c20f
AK		 4644 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4645 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4646 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4647
4648 /* Tx Errors */
f0ff4398 4649 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4650 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4651 netdev->stats.tx_window_errors = adapter->stats.latecol;
4652 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4653
4654 /* Tx Dropped needs to be maintained elsewhere */
4655
bc7f75fa
AK		 4656 /* Management Stats */
4657 adapter->stats.mgptc += er32(MGTPTC);
4658 adapter->stats.mgprc += er32(MGTPRC);
4659 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4660
4661 /* Correctable ECC Errors */
4662 if (hw->mac.type == e1000_pch_lpt) {
4663 u32 pbeccsts = er32(PBECCSTS);
4664 adapter->corr_errors +=
4665 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4666 adapter->uncorr_errors +=
4667 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4668 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4669 }
bc7f75fa
AK		 4670}
4671
7c25769f
BA		 4672/**
4673 * e1000_phy_read_status - Update the PHY register status snapshot
4674 * @adapter: board private structure
4675 **/
4676static void e1000_phy_read_status(struct e1000_adapter *adapter)
4677{
4678 struct e1000_hw *hw = &adapter->hw;
4679 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4680
97390ab8
BA		 4681 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4682 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4683 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4684 int ret_val;
4685
c2ade1a4
BA		 4686 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4687 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4688 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4689 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4690 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4691 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4692 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4693 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4694 if (ret_val)
44defeb3 4695 e_warn("Error reading PHY register\n");
7c25769f 4696 } else {
e921eb1a 4697 /* Do not read PHY registers if link is not up
7c25769f
BA		 4698 * Set values to typical power-on defaults
4699 */
4700 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4701 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4702 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4703 BMSR_ERCAP);
4704 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4705 ADVERTISE_ALL | ADVERTISE_CSMA);
4706 phy->lpa = 0;
4707 phy->expansion = EXPANSION_ENABLENPAGE;
4708 phy->ctrl1000 = ADVERTISE_1000FULL;
4709 phy->stat1000 = 0;
4710 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4711 }
7c25769f
BA		 4712}
4713
bc7f75fa
AK		 4714static void e1000_print_link_info(struct e1000_adapter *adapter)
4715{
bc7f75fa
AK		 4716 struct e1000_hw *hw = &adapter->hw;
4717 u32 ctrl = er32(CTRL);
4718
8f12fe86 4719 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4720 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4721 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4722 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4723 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4724 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4725 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4726}
4727
0c6bdb30 4728static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4729{
4730 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4731 bool link_active = false;
318a94d6
JK		 4732 s32 ret_val = 0;
4733
e921eb1a 4734 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4735 * Rx sequence error interrupt. get_link_status will stay
4736 * false until the check_for_link establishes link
4737 * for copper adapters ONLY
4738 */
4739 switch (hw->phy.media_type) {
4740 case e1000_media_type_copper:
4741 if (hw->mac.get_link_status) {
4742 ret_val = hw->mac.ops.check_for_link(hw);
4743 link_active = !hw->mac.get_link_status;
4744 } else {
3db1cd5c 4745 link_active = true;
318a94d6
JK		 4746 }
4747 break;
4748 case e1000_media_type_fiber:
4749 ret_val = hw->mac.ops.check_for_link(hw);
4750 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4751 break;
4752 case e1000_media_type_internal_serdes:
4753 ret_val = hw->mac.ops.check_for_link(hw);
4754 link_active = adapter->hw.mac.serdes_has_link;
4755 break;
4756 default:
4757 case e1000_media_type_unknown:
4758 break;
4759 }
4760
4761 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4762 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4763 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4764 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4765 }
4766
4767 return link_active;
4768}
4769
4770static void e1000e_enable_receives(struct e1000_adapter *adapter)
4771{
4772 /* make sure the receive unit is started */
4773 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4774 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4775 struct e1000_hw *hw = &adapter->hw;
4776 u32 rctl = er32(RCTL);
4777 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4778 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4779 }
4780}
4781
ff10e13c
CW		 4782static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4783{
4784 struct e1000_hw *hw = &adapter->hw;
4785
e921eb1a 4786 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4787 * for hung state and reset, if two calls return true
4788 */
4789 if (e1000_check_phy_82574(hw))
4790 adapter->phy_hang_count++;
4791 else
4792 adapter->phy_hang_count = 0;
4793
4794 if (adapter->phy_hang_count > 1) {
4795 adapter->phy_hang_count = 0;
4796 schedule_work(&adapter->reset_task);
4797 }
4798}
4799
bc7f75fa
AK		 4800/**
4801 * e1000_watchdog - Timer Call-back
4802 * @data: pointer to adapter cast into an unsigned long
4803 **/
4804static void e1000_watchdog(unsigned long data)
4805{
53aa82da 4806 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4807
4808 /* Do the rest outside of interrupt context */
4809 schedule_work(&adapter->watchdog_task);
4810
4811 /* TODO: make this use queue_delayed_work() */
4812}
4813
4814static void e1000_watchdog_task(struct work_struct *work)
4815{
4816 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4817 struct e1000_adapter,
4818 watchdog_task);
bc7f75fa
AK		 4819 struct net_device *netdev = adapter->netdev;
4820 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4821 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4822 struct e1000_ring *tx_ring = adapter->tx_ring;
4823 struct e1000_hw *hw = &adapter->hw;
4824 u32 link, tctl;
bc7f75fa 4825
615b32af
JB		 4826 if (test_bit(__E1000_DOWN, &adapter->state))
4827 return;
4828
b405e8df 4829 link = e1000e_has_link(adapter);
318a94d6 4830 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4831 /* Cancel scheduled suspend requests. */
4832 pm_runtime_resume(netdev->dev.parent);
4833
318a94d6 4834 e1000e_enable_receives(adapter);
bc7f75fa 4835 goto link_up;
bc7f75fa
AK		 4836 }
4837
4838 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4839 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4840 e1000_update_mng_vlan(adapter);
4841
bc7f75fa
AK		 4842 if (link) {
4843 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4844 bool txb2b = true;
23606cf5
RW		 4845
4846 /* Cancel scheduled suspend requests. */
4847 pm_runtime_resume(netdev->dev.parent);
4848
318a94d6 4849 /* update snapshot of PHY registers on LSC */
7c25769f 4850 e1000_phy_read_status(adapter);
bc7f75fa 4851 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4852 &adapter->link_speed,
4853 &adapter->link_duplex);
bc7f75fa 4854 e1000_print_link_info(adapter);
e792cd91
KS		 4855
4856 /* check if SmartSpeed worked */
4857 e1000e_check_downshift(hw);
4858 if (phy->speed_downgraded)
4859 netdev_warn(netdev,
4860 "Link Speed was downgraded by SmartSpeed\n");
4861
e921eb1a 4862 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4863 * if link has autonegotiated at 10/100 half
4864 */
4865 if ((hw->phy.type == e1000_phy_igp_3 ||
4866 hw->phy.type == e1000_phy_bm) &&
138953bb 4867 hw->mac.autoneg &&
f4187b56
BA		 4868 (adapter->link_speed == SPEED_10 ||
4869 adapter->link_speed == SPEED_100) &&
4870 (adapter->link_duplex == HALF_DUPLEX)) {
4871 u16 autoneg_exp;
4872
c2ade1a4 4873 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4874
c2ade1a4 4875 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4876 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4877 }
4878
f49c57e1 4879 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4880 adapter->tx_timeout_factor = 1;
4881 switch (adapter->link_speed) {
4882 case SPEED_10:
3db1cd5c 4883 txb2b = false;
10f1b492 4884 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4885 break;
4886 case SPEED_100:
3db1cd5c 4887 txb2b = false;
4c86e0b9 4888 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4889 break;
4890 }
4891
e921eb1a 4892 /* workaround: re-program speed mode bit after
ad68076e
BA		 4893 * link-up event
4894 */
bc7f75fa
AK		 4895 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4896 !txb2b) {
4897 u32 tarc0;
e9ec2c0f 4898 tarc0 = er32(TARC(0));
bc7f75fa 4899 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4900 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4901 }
4902
e921eb1a 4903 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4904 * some hardware issues
4905 */
bc7f75fa
AK		 4906 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4907 switch (adapter->link_speed) {
4908 case SPEED_10:
4909 case SPEED_100:
44defeb3 4910 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4911 netdev->features &= ~NETIF_F_TSO;
4912 netdev->features &= ~NETIF_F_TSO6;
4913 break;
4914 case SPEED_1000:
4915 netdev->features |= NETIF_F_TSO;
4916 netdev->features |= NETIF_F_TSO6;
4917 break;
4918 default:
4919 /* oops */
4920 break;
4921 }
4922 }
4923
e921eb1a 4924 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4925 * after setting TARC(0)
4926 */
bc7f75fa
AK		 4927 tctl = er32(TCTL);
4928 tctl |= E1000_TCTL_EN;
4929 ew32(TCTL, tctl);
4930
e921eb1a 4931 /* Perform any post-link-up configuration before
75eb0fad
BA		 4932 * reporting link up.
4933 */
4934 if (phy->ops.cfg_on_link_up)
4935 phy->ops.cfg_on_link_up(hw);
4936
bc7f75fa 4937 netif_carrier_on(netdev);
bc7f75fa
AK		 4938
4939 if (!test_bit(__E1000_DOWN, &adapter->state))
4940 mod_timer(&adapter->phy_info_timer,
4941 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4942 }
4943 } else {
4944 if (netif_carrier_ok(netdev)) {
4945 adapter->link_speed = 0;
4946 adapter->link_duplex = 0;
8f12fe86 4947 /* Link status message must follow this format */
7dbc1672 4948 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4949 netif_carrier_off(netdev);
bc7f75fa
AK		 4950 if (!test_bit(__E1000_DOWN, &adapter->state))
4951 mod_timer(&adapter->phy_info_timer,
4952 round_jiffies(jiffies + 2 * HZ));
4953
12d43f7d
BA		 4954 /* The link is lost so the controller stops DMA.
4955 * If there is queued Tx work that cannot be done
4956 * or if on an 8000ES2LAN which requires a Rx packet
4957 * buffer work-around on link down event, reset the
4958 * controller to flush the Tx/Rx packet buffers.
4959 * (Do the reset outside of interrupt context).
4960 */
4961 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4962 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4963 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4964 else
4965 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4966 LINK_TIMEOUT);
bc7f75fa
AK		 4967 }
4968 }
4969
4970link_up:
67fd4fcb 4971 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4972 e1000e_update_stats(adapter);
4973
4974 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4975 adapter->tpt_old = adapter->stats.tpt;
4976 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4977 adapter->colc_old = adapter->stats.colc;
4978
7c25769f
BA		 4979 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4980 adapter->gorc_old = adapter->stats.gorc;
4981 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4982 adapter->gotc_old = adapter->stats.gotc;
2084b114 4983 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4984
12d43f7d 4985 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4986 schedule_work(&adapter->reset_task);
4987 /* return immediately since reset is imminent */
4988 return;
bc7f75fa
AK		 4989 }
4990
12d43f7d
BA		 4991 e1000e_update_adaptive(&adapter->hw);
4992
eab2abf5
JB		 4993 /* Simple mode for Interrupt Throttle Rate (ITR) */
4994 if (adapter->itr_setting == 4) {
e921eb1a 4995 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4996 * Total asymmetrical Tx or Rx gets ITR=8000;
4997 * everyone else is between 2000-8000.
4998 */
4999 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5000 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5001 adapter->gotc - adapter->gorc :
5002 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5003 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5004
22a4cca2 5005 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5006 }
5007
ad68076e 5008 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5009 if (adapter->msix_entries)
5010 ew32(ICS, adapter->rx_ring->ims_val);
5011 else
5012 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5013
713b3c9e
JB		 5014 /* flush pending descriptors to memory before detecting Tx hang */
5015 e1000e_flush_descriptors(adapter);
5016
bc7f75fa 5017 /* Force detection of hung controller every watchdog period */
3db1cd5c 5018 adapter->detect_tx_hung = true;
bc7f75fa 5019
e921eb1a 5020 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5021 * reset from the other port. Set the appropriate LAA in RAR[0]
5022 */
bc7f75fa 5023 if (e1000e_get_laa_state_82571(hw))
69e1e019 5024 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5025
ff10e13c
CW		 5026 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5027 e1000e_check_82574_phy_workaround(adapter);
5028
b67e1913
BA		 5029 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5030 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5031 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5032 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5033 er32(RXSTMPH);
5034 adapter->rx_hwtstamp_cleared++;
5035 } else {
5036 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5037 }
5038 }
5039
bc7f75fa
AK		 5040 /* Reset the timer */
5041 if (!test_bit(__E1000_DOWN, &adapter->state))
5042 mod_timer(&adapter->watchdog_timer,
5043 round_jiffies(jiffies + 2 * HZ));
5044}
5045
5046#define E1000_TX_FLAGS_CSUM 0x00000001
5047#define E1000_TX_FLAGS_VLAN 0x00000002
5048#define E1000_TX_FLAGS_TSO 0x00000004
5049#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5050#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5051#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5052#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5053#define E1000_TX_FLAGS_VLAN_SHIFT 16
5054
55aa6985 5055static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5056{
bc7f75fa
AK		 5057 struct e1000_context_desc *context_desc;
5058 struct e1000_buffer *buffer_info;
5059 unsigned int i;
5060 u32 cmd_length = 0;
70443ae9 5061 u16 ipcse = 0, mss;
bc7f75fa 5062 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5063
3d5e33c9
BA		 5064 if (!skb_is_gso(skb))
5065 return 0;
bc7f75fa 5066
3d5e33c9 5067 if (skb_header_cloned(skb)) {
90da0669
BA		 5068 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5069
3d5e33c9
BA		 5070 if (err)
5071 return err;
bc7f75fa
AK		 5072 }
5073
3d5e33c9
BA		 5074 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5075 mss = skb_shinfo(skb)->gso_size;
5076 if (skb->protocol == htons(ETH_P_IP)) {
5077 struct iphdr *iph = ip_hdr(skb);
5078 iph->tot_len = 0;
5079 iph->check = 0;
5080 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5081 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5082 cmd_length = E1000_TXD_CMD_IP;
5083 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5084 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5085 ipv6_hdr(skb)->payload_len = 0;
5086 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5087 &ipv6_hdr(skb)->daddr,
5088 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5089 ipcse = 0;
5090 }
5091 ipcss = skb_network_offset(skb);
5092 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5093 tucss = skb_transport_offset(skb);
5094 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5095
5096 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5097 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5098
5099 i = tx_ring->next_to_use;
5100 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5101 buffer_info = &tx_ring->buffer_info[i];
5102
e80bd1d1
BA		 5103 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5104 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5105 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5106 context_desc->upper_setup.tcp_fields.tucss = tucss;
5107 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5108 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5109 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5110 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5111 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5112
5113 buffer_info->time_stamp = jiffies;
5114 buffer_info->next_to_watch = i;
5115
5116 i++;
5117 if (i == tx_ring->count)
5118 i = 0;
5119 tx_ring->next_to_use = i;
5120
5121 return 1;
bc7f75fa
AK		 5122}
5123
55aa6985 5124static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5125{
55aa6985 5126 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5127 struct e1000_context_desc *context_desc;
5128 struct e1000_buffer *buffer_info;
5129 unsigned int i;
5130 u8 css;
af807c82 5131 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5132 __be16 protocol;
bc7f75fa 5133
af807c82
DG		 5134 if (skb->ip_summed != CHECKSUM_PARTIAL)
5135 return 0;
bc7f75fa 5136
5f66f208
AJ		 5137 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5138 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5139 else
5140 protocol = skb->protocol;
5141
3f518390 5142 switch (protocol) {
09640e63 5143 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5144 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5145 cmd_len |= E1000_TXD_CMD_TCP;
5146 break;
09640e63 5147 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5148 /* XXX not handling all IPV6 headers */
5149 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5150 cmd_len |= E1000_TXD_CMD_TCP;
5151 break;
5152 default:
5153 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5154 e_warn("checksum_partial proto=%x!\n",
5155 be16_to_cpu(protocol));
af807c82 5156 break;
bc7f75fa
AK		 5157 }
5158
0d0b1672 5159 css = skb_checksum_start_offset(skb);
af807c82
DG		 5160
5161 i = tx_ring->next_to_use;
5162 buffer_info = &tx_ring->buffer_info[i];
5163 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5164
5165 context_desc->lower_setup.ip_config = 0;
5166 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5167 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5168 context_desc->upper_setup.tcp_fields.tucse = 0;
5169 context_desc->tcp_seg_setup.data = 0;
5170 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5171
5172 buffer_info->time_stamp = jiffies;
5173 buffer_info->next_to_watch = i;
5174
5175 i++;
5176 if (i == tx_ring->count)
5177 i = 0;
5178 tx_ring->next_to_use = i;
5179
5180 return 1;
bc7f75fa
AK		 5181}
5182
55aa6985
BA		 5183static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5184 unsigned int first, unsigned int max_per_txd,
d821a4c4 5185 unsigned int nr_frags)
bc7f75fa 5186{
55aa6985 5187 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5188 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5189 struct e1000_buffer *buffer_info;
8ddc951c 5190 unsigned int len = skb_headlen(skb);
03b1320d 5191 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5192 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5193
5194 i = tx_ring->next_to_use;
5195
5196 while (len) {
1b7719c4 5197 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5198 size = min(len, max_per_txd);
5199
bc7f75fa 5200 buffer_info->length = size;
bc7f75fa 5201 buffer_info->time_stamp = jiffies;
bc7f75fa 5202 buffer_info->next_to_watch = i;
0be3f55f
NN		 5203 buffer_info->dma = dma_map_single(&pdev->dev,
5204 skb->data + offset,
af667a29 5205 size, DMA_TO_DEVICE);
03b1320d 5206 buffer_info->mapped_as_page = false;
0be3f55f 5207 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5208 goto dma_error;
bc7f75fa
AK		 5209
5210 len -= size;
5211 offset += size;
03b1320d 5212 count++;
1b7719c4
AD		 5213
5214 if (len) {
5215 i++;
5216 if (i == tx_ring->count)
5217 i = 0;
5218 }
bc7f75fa
AK		 5219 }
5220
5221 for (f = 0; f < nr_frags; f++) {
9e903e08 5222 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5223
5224 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5225 len = skb_frag_size(frag);
877749bf 5226 offset = 0;
bc7f75fa
AK		 5227
5228 while (len) {
1b7719c4
AD		 5229 i++;
5230 if (i == tx_ring->count)
5231 i = 0;
5232
bc7f75fa
AK		 5233 buffer_info = &tx_ring->buffer_info[i];
5234 size = min(len, max_per_txd);
bc7f75fa
AK		 5235
5236 buffer_info->length = size;
5237 buffer_info->time_stamp = jiffies;
bc7f75fa 5238 buffer_info->next_to_watch = i;
877749bf 5239 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5240 offset, size,
5241 DMA_TO_DEVICE);
03b1320d 5242 buffer_info->mapped_as_page = true;
0be3f55f 5243 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5244 goto dma_error;
bc7f75fa
AK		 5245
5246 len -= size;
5247 offset += size;
5248 count++;
bc7f75fa
AK		 5249 }
5250 }
5251
af667a29 5252 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5253 /* multiply data chunks by size of headers */
5254 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5255
bc7f75fa 5256 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5257 tx_ring->buffer_info[i].segs = segs;
5258 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5259 tx_ring->buffer_info[first].next_to_watch = i;
5260
5261 return count;
03b1320d
AD		 5262
5263dma_error:
af667a29 5264 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5265 buffer_info->dma = 0;
c1fa347f 5266 if (count)
03b1320d 5267 count--;
c1fa347f
RK		 5268
5269 while (count--) {
af667a29 5270 if (i == 0)
03b1320d 5271 i += tx_ring->count;
c1fa347f 5272 i--;
03b1320d 5273 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5274 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5275 }
5276
5277 return 0;
bc7f75fa
AK		 5278}
5279
55aa6985 5280static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5281{
55aa6985 5282 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5283 struct e1000_tx_desc *tx_desc = NULL;
5284 struct e1000_buffer *buffer_info;
5285 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5286 unsigned int i;
5287
5288 if (tx_flags & E1000_TX_FLAGS_TSO) {
5289 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5290 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5291 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5292
5293 if (tx_flags & E1000_TX_FLAGS_IPV4)
5294 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5295 }
5296
5297 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5298 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5299 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5300 }
5301
5302 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5303 txd_lower |= E1000_TXD_CMD_VLE;
5304 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5305 }
5306
943146de
BG		 5307 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5308 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5309
b67e1913
BA		 5310 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5311 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5312 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5313 }
5314
bc7f75fa
AK		 5315 i = tx_ring->next_to_use;
5316
36b973df 5317 do {
bc7f75fa
AK		 5318 buffer_info = &tx_ring->buffer_info[i];
5319 tx_desc = E1000_TX_DESC(*tx_ring, i);
5320 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5321 tx_desc->lower.data = cpu_to_le32(txd_lower |
5322 buffer_info->length);
bc7f75fa
AK		 5323 tx_desc->upper.data = cpu_to_le32(txd_upper);
5324
5325 i++;
5326 if (i == tx_ring->count)
5327 i = 0;
36b973df 5328 } while (--count > 0);
bc7f75fa
AK		 5329
5330 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5331
943146de
BG		 5332 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5333 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5334 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5335
e921eb1a 5336 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5337 * know there are new descriptors to fetch. (Only
5338 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5339 * such as IA-64).
5340 */
bc7f75fa
AK		 5341 wmb();
5342
5343 tx_ring->next_to_use = i;
c6e7f51e
BA		 5344
5345 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5346 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5347 else
c5083cf6 5348 writel(i, tx_ring->tail);
c6e7f51e 5349
e921eb1a 5350 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5351 * at a time, it synchronizes IO on IA64/Altix systems
5352 */
bc7f75fa
AK		 5353 mmiowb();
5354}
5355
5356#define MINIMUM_DHCP_PACKET_SIZE 282
5357static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5358 struct sk_buff *skb)
5359{
e80bd1d1 5360 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5361 u16 length, offset;
5362
d60923c4
BA		 5363 if (vlan_tx_tag_present(skb) &&
5364 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5365 (adapter->hw.mng_cookie.status &
5366 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5367 return 0;
bc7f75fa
AK		 5368
5369 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5370 return 0;
5371
53aa82da 5372 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5373 return 0;
5374
5375 {
362e20ca 5376 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5377 struct udphdr *udp;
5378
5379 if (ip->protocol != IPPROTO_UDP)
5380 return 0;
5381
5382 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5383 if (ntohs(udp->dest) != 67)
5384 return 0;
5385
5386 offset = (u8 *)udp + 8 - skb->data;
5387 length = skb->len - offset;
5388 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5389 }
5390
5391 return 0;
5392}
5393
55aa6985 5394static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5395{
55aa6985 5396 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5397
55aa6985 5398 netif_stop_queue(adapter->netdev);
e921eb1a 5399 /* Herbert's original patch had:
bc7f75fa 5400 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5401 * but since that doesn't exist yet, just open code it.
5402 */
bc7f75fa
AK		 5403 smp_mb();
5404
e921eb1a 5405 /* We need to check again in a case another CPU has just
ad68076e
BA		 5406 * made room available.
5407 */
55aa6985 5408 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5409 return -EBUSY;
5410
5411 /* A reprieve! */
55aa6985 5412 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5413 ++adapter->restart_queue;
5414 return 0;
5415}
5416
55aa6985 5417static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5418{
d821a4c4
BA		 5419 BUG_ON(size > tx_ring->count);
5420
55aa6985 5421 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5422 return 0;
55aa6985 5423 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5424}
5425
3b29a56d
SH		 5426static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5427 struct net_device *netdev)
bc7f75fa
AK		 5428{
5429 struct e1000_adapter *adapter = netdev_priv(netdev);
5430 struct e1000_ring *tx_ring = adapter->tx_ring;
5431 unsigned int first;
bc7f75fa 5432 unsigned int tx_flags = 0;
e743d313 5433 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5434 unsigned int nr_frags;
5435 unsigned int mss;
bc7f75fa
AK		 5436 int count = 0;
5437 int tso;
5438 unsigned int f;
bc7f75fa
AK		 5439
5440 if (test_bit(__E1000_DOWN, &adapter->state)) {
5441 dev_kfree_skb_any(skb);
5442 return NETDEV_TX_OK;
5443 }
5444
5445 if (skb->len <= 0) {
5446 dev_kfree_skb_any(skb);
5447 return NETDEV_TX_OK;
5448 }
5449
e921eb1a 5450 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5451 * pad skb in order to meet this minimum size requirement
5452 */
5453 if (unlikely(skb->len < 17)) {
5454 if (skb_pad(skb, 17 - skb->len))
5455 return NETDEV_TX_OK;
5456 skb->len = 17;
5457 skb_set_tail_pointer(skb, 17);
5458 }
5459
bc7f75fa 5460 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5461 if (mss) {
5462 u8 hdr_len;
bc7f75fa 5463
e921eb1a 5464 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5465 * points to just header, pull a few bytes of payload from
5466 * frags into skb->data
5467 */
bc7f75fa 5468 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5469 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5470 * avoiding it could save a lot of cycles
5471 */
4e6c709c 5472 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5473 unsigned int pull_size;
5474
a2a5b323 5475 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5476 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5477 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5478 dev_kfree_skb_any(skb);
5479 return NETDEV_TX_OK;
5480 }
e743d313 5481 len = skb_headlen(skb);
bc7f75fa
AK		 5482 }
5483 }
5484
5485 /* reserve a descriptor for the offload context */
5486 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5487 count++;
5488 count++;
5489
d821a4c4 5490 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5491
5492 nr_frags = skb_shinfo(skb)->nr_frags;
5493 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5494 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5495 adapter->tx_fifo_limit);
bc7f75fa
AK		 5496
5497 if (adapter->hw.mac.tx_pkt_filtering)
5498 e1000_transfer_dhcp_info(adapter, skb);
5499
e921eb1a 5500 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5501 * head, otherwise try next time
5502 */
55aa6985 5503 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5504 return NETDEV_TX_BUSY;
bc7f75fa 5505
eab6d18d 5506 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5507 tx_flags |= E1000_TX_FLAGS_VLAN;
5508 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5509 }
5510
5511 first = tx_ring->next_to_use;
5512
55aa6985 5513 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5514 if (tso < 0) {
5515 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5516 return NETDEV_TX_OK;
5517 }
5518
5519 if (tso)
5520 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5521 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5522 tx_flags |= E1000_TX_FLAGS_CSUM;
5523
e921eb1a 5524 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5525 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5526 * no longer assume, we must.
5527 */
bc7f75fa
AK		 5528 if (skb->protocol == htons(ETH_P_IP))
5529 tx_flags |= E1000_TX_FLAGS_IPV4;
5530
943146de
BG		 5531 if (unlikely(skb->no_fcs))
5532 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5533
25985edc 5534 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5535 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5536 nr_frags);
1b7719c4 5537 if (count) {
b67e1913
BA		 5538 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5539 !adapter->tx_hwtstamp_skb)) {
5540 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5541 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5542 adapter->tx_hwtstamp_skb = skb_get(skb);
5543 schedule_work(&adapter->tx_hwtstamp_work);
5544 } else {
5545 skb_tx_timestamp(skb);
5546 }
80be3129 5547
3f0cfa3b 5548 netdev_sent_queue(netdev, skb->len);
55aa6985 5549 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5550 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5551 e1000_maybe_stop_tx(tx_ring,
5552 (MAX_SKB_FRAGS *
5553 DIV_ROUND_UP(PAGE_SIZE,
5554 adapter->tx_fifo_limit) + 2));
1b7719c4 5555 } else {
bc7f75fa 5556 dev_kfree_skb_any(skb);
1b7719c4
AD		 5557 tx_ring->buffer_info[first].time_stamp = 0;
5558 tx_ring->next_to_use = first;
bc7f75fa
AK		 5559 }
5560
bc7f75fa
AK		 5561 return NETDEV_TX_OK;
5562}
5563
5564/**
5565 * e1000_tx_timeout - Respond to a Tx Hang
5566 * @netdev: network interface device structure
5567 **/
5568static void e1000_tx_timeout(struct net_device *netdev)
5569{
5570 struct e1000_adapter *adapter = netdev_priv(netdev);
5571
5572 /* Do the reset outside of interrupt context */
5573 adapter->tx_timeout_count++;
5574 schedule_work(&adapter->reset_task);
5575}
5576
5577static void e1000_reset_task(struct work_struct *work)
5578{
5579 struct e1000_adapter *adapter;
5580 adapter = container_of(work, struct e1000_adapter, reset_task);
5581
615b32af
JB		 5582 /* don't run the task if already down */
5583 if (test_bit(__E1000_DOWN, &adapter->state))
5584 return;
5585
12d43f7d 5586 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5587 e1000e_dump(adapter);
12d43f7d 5588 e_err("Reset adapter unexpectedly\n");
affa9dfb 5589 }
bc7f75fa
AK		 5590 e1000e_reinit_locked(adapter);
5591}
5592
5593/**
67fd4fcb 5594 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5595 * @netdev: network interface device structure
67fd4fcb 5596 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5597 *
5598 * Returns the address of the device statistics structure.
bc7f75fa 5599 **/
67fd4fcb 5600struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5601 struct rtnl_link_stats64 *stats)
bc7f75fa 5602{
67fd4fcb
JK		 5603 struct e1000_adapter *adapter = netdev_priv(netdev);
5604
5605 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5606 spin_lock(&adapter->stats64_lock);
5607 e1000e_update_stats(adapter);
5608 /* Fill out the OS statistics structure */
5609 stats->rx_bytes = adapter->stats.gorc;
5610 stats->rx_packets = adapter->stats.gprc;
5611 stats->tx_bytes = adapter->stats.gotc;
5612 stats->tx_packets = adapter->stats.gptc;
5613 stats->multicast = adapter->stats.mprc;
5614 stats->collisions = adapter->stats.colc;
5615
5616 /* Rx Errors */
5617
e921eb1a 5618 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5619 * our own version based on RUC and ROC
5620 */
5621 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5622 adapter->stats.crcerrs + adapter->stats.algnerrc +
5623 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5624 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5625 stats->rx_crc_errors = adapter->stats.crcerrs;
5626 stats->rx_frame_errors = adapter->stats.algnerrc;
5627 stats->rx_missed_errors = adapter->stats.mpc;
5628
5629 /* Tx Errors */
f0ff4398 5630 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5631 stats->tx_aborted_errors = adapter->stats.ecol;
5632 stats->tx_window_errors = adapter->stats.latecol;
5633 stats->tx_carrier_errors = adapter->stats.tncrs;
5634
5635 /* Tx Dropped needs to be maintained elsewhere */
5636
5637 spin_unlock(&adapter->stats64_lock);
5638 return stats;
bc7f75fa
AK		 5639}
5640
5641/**
5642 * e1000_change_mtu - Change the Maximum Transfer Unit
5643 * @netdev: network interface device structure
5644 * @new_mtu: new value for maximum frame size
5645 *
5646 * Returns 0 on success, negative on failure
5647 **/
5648static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5649{
5650 struct e1000_adapter *adapter = netdev_priv(netdev);
5651 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5652
2adc55c9 5653 /* Jumbo frame support */
2e1706f2
BA		 5654 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5655 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5656 e_err("Jumbo Frames not supported.\n");
5657 return -EINVAL;
bc7f75fa
AK		 5658 }
5659
2adc55c9
BA		 5660 /* Supported frame sizes */
5661 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5662 (max_frame > adapter->max_hw_frame_size)) {
5663 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5664 return -EINVAL;
5665 }
5666
2fbe4526
BA		 5667 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5668 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5669 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5670 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5671 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5672 return -EINVAL;
5673 }
5674
bc7f75fa 5675 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5676 usleep_range(1000, 2000);
610c9928 5677 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5678 adapter->max_frame_size = max_frame;
610c9928
BA		 5679 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5680 netdev->mtu = new_mtu;
bc7f75fa 5681 if (netif_running(netdev))
28002099 5682 e1000e_down(adapter, true);
bc7f75fa 5683
e921eb1a 5684 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5685 * means we reserve 2 more, this pushes us to allocate from the next
5686 * larger slab size.
ad68076e 5687 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5688 * However with the new *_jumbo_rx* routines, jumbo receives will use
5689 * fragmented skbs
ad68076e 5690 */
bc7f75fa 5691
9926146b 5692 if (max_frame <= 2048)
bc7f75fa
AK		 5693 adapter->rx_buffer_len = 2048;
5694 else
5695 adapter->rx_buffer_len = 4096;
5696
5697 /* adjust allocation if LPE protects us, and we aren't using SBP */
5698 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5699 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5700 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5701 + ETH_FCS_LEN;
bc7f75fa 5702
bc7f75fa
AK		 5703 if (netif_running(netdev))
5704 e1000e_up(adapter);
5705 else
5706 e1000e_reset(adapter);
5707
5708 clear_bit(__E1000_RESETTING, &adapter->state);
5709
5710 return 0;
5711}
5712
5713static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5714 int cmd)
5715{
5716 struct e1000_adapter *adapter = netdev_priv(netdev);
5717 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5718
318a94d6 5719 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5720 return -EOPNOTSUPP;
5721
5722 switch (cmd) {
5723 case SIOCGMIIPHY:
5724 data->phy_id = adapter->hw.phy.addr;
5725 break;
5726 case SIOCGMIIREG:
b16a002e
BA		 5727 e1000_phy_read_status(adapter);
5728
7c25769f
BA		 5729 switch (data->reg_num & 0x1F) {
5730 case MII_BMCR:
5731 data->val_out = adapter->phy_regs.bmcr;
5732 break;
5733 case MII_BMSR:
5734 data->val_out = adapter->phy_regs.bmsr;
5735 break;
5736 case MII_PHYSID1:
5737 data->val_out = (adapter->hw.phy.id >> 16);
5738 break;
5739 case MII_PHYSID2:
5740 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5741 break;
5742 case MII_ADVERTISE:
5743 data->val_out = adapter->phy_regs.advertise;
5744 break;
5745 case MII_LPA:
5746 data->val_out = adapter->phy_regs.lpa;
5747 break;
5748 case MII_EXPANSION:
5749 data->val_out = adapter->phy_regs.expansion;
5750 break;
5751 case MII_CTRL1000:
5752 data->val_out = adapter->phy_regs.ctrl1000;
5753 break;
5754 case MII_STAT1000:
5755 data->val_out = adapter->phy_regs.stat1000;
5756 break;
5757 case MII_ESTATUS:
5758 data->val_out = adapter->phy_regs.estatus;
5759 break;
5760 default:
bc7f75fa
AK		 5761 return -EIO;
5762 }
bc7f75fa
AK		 5763 break;
5764 case SIOCSMIIREG:
5765 default:
5766 return -EOPNOTSUPP;
5767 }
5768 return 0;
5769}
5770
b67e1913
BA		 5771/**
5772 * e1000e_hwtstamp_ioctl - control hardware time stamping
5773 * @netdev: network interface device structure
5774 * @ifreq: interface request
5775 *
5776 * Outgoing time stamping can be enabled and disabled. Play nice and
5777 * disable it when requested, although it shouldn't cause any overhead
5778 * when no packet needs it. At most one packet in the queue may be
5779 * marked for time stamping, otherwise it would be impossible to tell
5780 * for sure to which packet the hardware time stamp belongs.
5781 *
5782 * Incoming time stamping has to be configured via the hardware filters.
5783 * Not all combinations are supported, in particular event type has to be
5784 * specified. Matching the kind of event packet is not supported, with the
5785 * exception of "all V2 events regardless of level 2 or 4".
5786 **/
4e8cff64 5787static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 5788{
5789 struct e1000_adapter *adapter = netdev_priv(netdev);
5790 struct hwtstamp_config config;
5791 int ret_val;
5792
5793 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5794 return -EFAULT;
5795
62d7e3a2 5796 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 5797 if (ret_val)
5798 return ret_val;
5799
d89777bf
BA		 5800 switch (config.rx_filter) {
5801 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5802 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5803 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5804 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5805 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5806 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5807 /* With V2 type filters which specify a Sync or Delay Request,
5808 * Path Delay Request/Response messages are also time stamped
5809 * by hardware so notify the caller the requested packets plus
5810 * some others are time stamped.
5811 */
5812 config.rx_filter = HWTSTAMP_FILTER_SOME;
5813 break;
5814 default:
5815 break;
5816 }
5817
b67e1913
BA		 5818 return copy_to_user(ifr->ifr_data, &config,
5819 sizeof(config)) ? -EFAULT : 0;
5820}
5821
4e8cff64
BH		 5822static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
5823{
5824 struct e1000_adapter *adapter = netdev_priv(netdev);
5825
5826 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
5827 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
5828}
5829
bc7f75fa
AK		 5830static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5831{
5832 switch (cmd) {
5833 case SIOCGMIIPHY:
5834 case SIOCGMIIREG:
5835 case SIOCSMIIREG:
5836 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 5837 case SIOCSHWTSTAMP:
4e8cff64
BH		 5838 return e1000e_hwtstamp_set(netdev, ifr);
5839 case SIOCGHWTSTAMP:
5840 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 5841 default:
5842 return -EOPNOTSUPP;
5843 }
5844}
5845
a4f58f54
BA		 5846static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5847{
5848 struct e1000_hw *hw = &adapter->hw;
5849 u32 i, mac_reg;
2b6b168d 5850 u16 phy_reg, wuc_enable;
70806a7f 5851 int retval;
a4f58f54
BA		 5852
5853 /* copy MAC RARs to PHY RARs */
d3738bb8 5854 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5855
2b6b168d
BA		 5856 retval = hw->phy.ops.acquire(hw);
5857 if (retval) {
5858 e_err("Could not acquire PHY\n");
5859 return retval;
5860 }
5861
5862 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5863 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5864 if (retval)
75ce1532 5865 goto release;
2b6b168d
BA		 5866
5867 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5868 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5869 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5870 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5871 (u16)(mac_reg & 0xFFFF));
5872 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5873 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5874 }
5875
5876 /* configure PHY Rx Control register */
2b6b168d 5877 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5878 mac_reg = er32(RCTL);
5879 if (mac_reg & E1000_RCTL_UPE)
5880 phy_reg |= BM_RCTL_UPE;
5881 if (mac_reg & E1000_RCTL_MPE)
5882 phy_reg |= BM_RCTL_MPE;
5883 phy_reg &= ~(BM_RCTL_MO_MASK);
5884 if (mac_reg & E1000_RCTL_MO_3)
5885 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5886 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5887 if (mac_reg & E1000_RCTL_BAM)
5888 phy_reg |= BM_RCTL_BAM;
5889 if (mac_reg & E1000_RCTL_PMCF)
5890 phy_reg |= BM_RCTL_PMCF;
5891 mac_reg = er32(CTRL);
5892 if (mac_reg & E1000_CTRL_RFCE)
5893 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5894 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5895
5896 /* enable PHY wakeup in MAC register */
5897 ew32(WUFC, wufc);
5898 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5899
5900 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5901 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5902 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5903
5904 /* activate PHY wakeup */
2b6b168d
BA		 5905 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5906 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5907 if (retval)
5908 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5909release:
94d8186a 5910 hw->phy.ops.release(hw);
a4f58f54
BA		 5911
5912 return retval;
5913}
5914
28002099 5915static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 5916{
28002099 5917 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 5918 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 5919
5920 netif_device_detach(netdev);
5921
5922 if (netif_running(netdev)) {
bb9e44d0
BA		 5923 int count = E1000_CHECK_RESET_COUNT;
5924
5925 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5926 usleep_range(10000, 20000);
5927
bc7f75fa 5928 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 5929
5930 /* Quiesce the device without resetting the hardware */
5931 e1000e_down(adapter, false);
bc7f75fa
AK		 5932 e1000_free_irq(adapter);
5933 }
4662e82b 5934 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 5935
28002099
DE		 5936 /* Allow time for pending master requests to run */
5937 e1000e_disable_pcie_master(&adapter->hw);
5938
5939 return 0;
5940}
5941
5942static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
5943{
5944 struct net_device *netdev = pci_get_drvdata(pdev);
5945 struct e1000_adapter *adapter = netdev_priv(netdev);
5946 struct e1000_hw *hw = &adapter->hw;
5947 u32 ctrl, ctrl_ext, rctl, status;
5948 /* Runtime suspend should only enable wakeup for link changes */
5949 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
5950 int retval = 0;
5951
bc7f75fa
AK		 5952 status = er32(STATUS);
5953 if (status & E1000_STATUS_LU)
5954 wufc &= ~E1000_WUFC_LNKC;
5955
5956 if (wufc) {
5957 e1000_setup_rctl(adapter);
ef9b965a 5958 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5959
5960 /* turn on all-multi mode if wake on multicast is enabled */
5961 if (wufc & E1000_WUFC_MC) {
5962 rctl = er32(RCTL);
5963 rctl |= E1000_RCTL_MPE;
5964 ew32(RCTL, rctl);
5965 }
5966
5967 ctrl = er32(CTRL);
a4f58f54
BA		 5968 ctrl |= E1000_CTRL_ADVD3WUC;
5969 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5970 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5971 ew32(CTRL, ctrl);
5972
318a94d6
JK		 5973 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5974 adapter->hw.phy.media_type ==
5975 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5976 /* keep the laser running in D3 */
5977 ctrl_ext = er32(CTRL_EXT);
93a23f48 5978 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5979 ew32(CTRL_EXT, ctrl_ext);
5980 }
5981
97ac8cae 5982 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5983 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5984
82776a4b 5985 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5986 /* enable wakeup by the PHY */
5987 retval = e1000_init_phy_wakeup(adapter, wufc);
5988 if (retval)
5989 return retval;
5990 } else {
5991 /* enable wakeup by the MAC */
5992 ew32(WUFC, wufc);
5993 ew32(WUC, E1000_WUC_PME_EN);
5994 }
bc7f75fa
AK		 5995 } else {
5996 ew32(WUC, 0);
5997 ew32(WUFC, 0);
28002099
DE		 5998
5999 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6000 }
6001
bc7f75fa
AK		 6002 if (adapter->hw.phy.type == e1000_phy_igp_3)
6003 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6004
e921eb1a 6005 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6006 * would have already happened in close and is redundant.
6007 */
31dbe5b4 6008 e1000e_release_hw_control(adapter);
bc7f75fa 6009
24b41c97
DN		 6010 pci_clear_master(pdev);
6011
e921eb1a 6012 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6013 * correctable error when the MAC transitions from D0 to D3. To
6014 * prevent this we need to mask off the correctable errors on the
6015 * downstream port of the pci-e switch.
e8c254c5
LZ		 6016 *
6017 * We don't have the associated upstream bridge while assigning
6018 * the PCI device into guest. For example, the KVM on power is
6019 * one of the cases.
005cbdfc
AD		 6020 */
6021 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6022 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6023 u16 devctl;
6024
e8c254c5
LZ		 6025 if (!us_dev)
6026 return 0;
6027
f8c0fcac
JL		 6028 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6029 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6030 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6031
66148bab
KK		 6032 pci_save_state(pdev);
6033 pci_prepare_to_sleep(pdev);
005cbdfc 6034
f8c0fcac 6035 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6036 }
66148bab
KK		 6037
6038 return 0;
bc7f75fa
AK		 6039}
6040
13129d9b
CW		 6041/**
6042 * e1000e_disable_aspm - Disable ASPM states
6043 * @pdev: pointer to PCI device struct
6044 * @state: bit-mask of ASPM states to disable
6045 *
6046 * Some devices *must* have certain ASPM states disabled per hardware errata.
6047 **/
6048static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c 6049{
13129d9b
CW		 6050 struct pci_dev *parent = pdev->bus->self;
6051 u16 aspm_dis_mask = 0;
6052 u16 pdev_aspmc, parent_aspmc;
6053
6054 switch (state) {
6055 case PCIE_LINK_STATE_L0S:
6056 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6057 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6058 /* fall-through - can't have L1 without L0s */
6059 case PCIE_LINK_STATE_L1:
6060 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6061 break;
6062 default:
6063 return;
6064 }
6065
6066 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6067 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6068
6069 if (parent) {
6070 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6071 &parent_aspmc);
6072 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6073 }
6074
6075 /* Nothing to do if the ASPM states to be disabled already are */
6076 if (!(pdev_aspmc & aspm_dis_mask) &&
6077 (!parent || !(parent_aspmc & aspm_dis_mask)))
6078 return;
6079
6080 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6081 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6082 "L0s" : "",
6083 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6084 "L1" : "");
6085
6086#ifdef CONFIG_PCIEASPM
9f728f53 6087 pci_disable_link_state_locked(pdev, state);
ffe0b2ff 6088
13129d9b
CW		 6089 /* Double-check ASPM control. If not disabled by the above, the
6090 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6091 * not enabled); override by writing PCI config space directly.
6092 */
6093 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6094 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6095
6096 if (!(aspm_dis_mask & pdev_aspmc))
6097 return;
6098#endif
ffe0b2ff 6099
e921eb1a 6100 /* Both device and parent should have the same ASPM setting.
6f461f6c 6101 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6102 */
13129d9b 6103 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6104
13129d9b
CW		 6105 if (parent)
6106 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6107 aspm_dis_mask);
1eae4eb2
AK		 6108}
6109
aa338601 6110#ifdef CONFIG_PM
23606cf5 6111static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 6112{
23606cf5 6113 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 6114}
6115
23606cf5 6116static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6117{
6118 struct net_device *netdev = pci_get_drvdata(pdev);
6119 struct e1000_adapter *adapter = netdev_priv(netdev);
6120 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6121 u16 aspm_disable_flag = 0;
bc7f75fa 6122
78cd29d5
BA		 6123 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6124 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6125 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6126 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6127 if (aspm_disable_flag)
6128 e1000e_disable_aspm(pdev, aspm_disable_flag);
6129
66148bab 6130 pci_set_master(pdev);
6e4f6f6b 6131
2fbe4526 6132 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6133 e1000_resume_workarounds_pchlan(&adapter->hw);
6134
bc7f75fa 6135 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6136
6137 /* report the system wakeup cause from S3/S4 */
6138 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6139 u16 phy_data;
6140
6141 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6142 if (phy_data) {
6143 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6144 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6145 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6146 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6147 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6148 phy_data & E1000_WUS_LNKC ?
6149 "Link Status Change" : "other");
a4f58f54
BA		 6150 }
6151 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6152 } else {
6153 u32 wus = er32(WUS);
6154 if (wus) {
6155 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6156 wus & E1000_WUS_EX ? "Unicast Packet" :
6157 wus & E1000_WUS_MC ? "Multicast Packet" :
6158 wus & E1000_WUS_BC ? "Broadcast Packet" :
6159 wus & E1000_WUS_MAG ? "Magic Packet" :
6160 wus & E1000_WUS_LNKC ? "Link Status Change" :
6161 "other");
a4f58f54
BA		 6162 }
6163 ew32(WUS, ~0);
6164 }
6165
bc7f75fa 6166 e1000e_reset(adapter);
bc7f75fa 6167
cd791618 6168 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6169
6170 if (netif_running(netdev))
6171 e1000e_up(adapter);
6172
6173 netif_device_attach(netdev);
6174
e921eb1a 6175 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6176 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6177 * under the control of the driver.
6178 */
c43bc57e 6179 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6180 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6181
6182 return 0;
6183}
23606cf5 6184
28002099
DE		 6185static int e1000e_pm_thaw(struct device *dev)
6186{
6187 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6188 struct e1000_adapter *adapter = netdev_priv(netdev);
6189
6190 e1000e_set_interrupt_capability(adapter);
6191 if (netif_running(netdev)) {
6192 u32 err = e1000_request_irq(adapter);
6193
6194 if (err)
6195 return err;
6196
6197 e1000e_up(adapter);
6198 }
6199
6200 netif_device_attach(netdev);
6201
6202 return 0;
6203}
6204
38a529b5 6205#ifdef CONFIG_PM_SLEEP
28002099 6206static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6207{
6208 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6209
28002099
DE		 6210 e1000e_pm_freeze(dev);
6211
66148bab 6212 return __e1000_shutdown(pdev, false);
a0340162
RW		 6213}
6214
28002099 6215static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6216{
6217 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6218 int rc;
23606cf5 6219
28002099
DE		 6220 rc = __e1000_resume(pdev);
6221 if (rc)
6222 return rc;
23606cf5 6223
28002099 6224 return e1000e_pm_thaw(dev);
23606cf5 6225}
38a529b5 6226#endif /* CONFIG_PM_SLEEP */
a0340162
RW		 6227
6228#ifdef CONFIG_PM_RUNTIME
6229static int e1000_runtime_suspend(struct device *dev)
6230{
6231 struct pci_dev *pdev = to_pci_dev(dev);
6232 struct net_device *netdev = pci_get_drvdata(pdev);
6233 struct e1000_adapter *adapter = netdev_priv(netdev);
6234
66148bab
KK		 6235 if (!e1000e_pm_ready(adapter))
6236 return 0;
a0340162 6237
66148bab 6238 return __e1000_shutdown(pdev, true);
a0340162
RW		 6239}
6240
6241static int e1000_idle(struct device *dev)
6242{
6243 struct pci_dev *pdev = to_pci_dev(dev);
6244 struct net_device *netdev = pci_get_drvdata(pdev);
6245 struct e1000_adapter *adapter = netdev_priv(netdev);
6246
6247 if (!e1000e_pm_ready(adapter))
6248 return 0;
6249
6250 if (adapter->idle_check) {
6251 adapter->idle_check = false;
6252 if (!e1000e_has_link(adapter))
6253 pm_schedule_suspend(dev, MSEC_PER_SEC);
6254 }
6255
6256 return -EBUSY;
6257}
23606cf5
RW		 6258
6259static int e1000_runtime_resume(struct device *dev)
6260{
6261 struct pci_dev *pdev = to_pci_dev(dev);
6262 struct net_device *netdev = pci_get_drvdata(pdev);
6263 struct e1000_adapter *adapter = netdev_priv(netdev);
6264
6265 if (!e1000e_pm_ready(adapter))
6266 return 0;
6267
6268 adapter->idle_check = !dev->power.runtime_auto;
6269 return __e1000_resume(pdev);
6270}
a0340162 6271#endif /* CONFIG_PM_RUNTIME */
aa338601 6272#endif /* CONFIG_PM */
bc7f75fa
AK		 6273
6274static void e1000_shutdown(struct pci_dev *pdev)
6275{
28002099
DE		 6276 e1000e_pm_freeze(&pdev->dev);
6277
66148bab 6278 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6279}
6280
6281#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6282
8bb62869 6283static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6284{
6285 struct net_device *netdev = data;
6286 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6287
6288 if (adapter->msix_entries) {
90da0669
BA		 6289 int vector, msix_irq;
6290
147b2c8c
DD		 6291 vector = 0;
6292 msix_irq = adapter->msix_entries[vector].vector;
6293 disable_irq(msix_irq);
6294 e1000_intr_msix_rx(msix_irq, netdev);
6295 enable_irq(msix_irq);
6296
6297 vector++;
6298 msix_irq = adapter->msix_entries[vector].vector;
6299 disable_irq(msix_irq);
6300 e1000_intr_msix_tx(msix_irq, netdev);
6301 enable_irq(msix_irq);
6302
6303 vector++;
6304 msix_irq = adapter->msix_entries[vector].vector;
6305 disable_irq(msix_irq);
6306 e1000_msix_other(msix_irq, netdev);
6307 enable_irq(msix_irq);
6308 }
6309
6310 return IRQ_HANDLED;
6311}
6312
e921eb1a
BA		 6313/**
6314 * e1000_netpoll
6315 * @netdev: network interface device structure
6316 *
bc7f75fa
AK		 6317 * Polling 'interrupt' - used by things like netconsole to send skbs
6318 * without having to re-enable interrupts. It's not called while
6319 * the interrupt routine is executing.
6320 */
6321static void e1000_netpoll(struct net_device *netdev)
6322{
6323 struct e1000_adapter *adapter = netdev_priv(netdev);
6324
147b2c8c
DD		 6325 switch (adapter->int_mode) {
6326 case E1000E_INT_MODE_MSIX:
6327 e1000_intr_msix(adapter->pdev->irq, netdev);
6328 break;
6329 case E1000E_INT_MODE_MSI:
6330 disable_irq(adapter->pdev->irq);
6331 e1000_intr_msi(adapter->pdev->irq, netdev);
6332 enable_irq(adapter->pdev->irq);
6333 break;
e80bd1d1 6334 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6335 disable_irq(adapter->pdev->irq);
6336 e1000_intr(adapter->pdev->irq, netdev);
6337 enable_irq(adapter->pdev->irq);
6338 break;
6339 }
bc7f75fa
AK		 6340}
6341#endif
6342
6343/**
6344 * e1000_io_error_detected - called when PCI error is detected
6345 * @pdev: Pointer to PCI device
6346 * @state: The current pci connection state
6347 *
6348 * This function is called after a PCI bus error affecting
6349 * this device has been detected.
6350 */
6351static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6352 pci_channel_state_t state)
6353{
6354 struct net_device *netdev = pci_get_drvdata(pdev);
6355 struct e1000_adapter *adapter = netdev_priv(netdev);
6356
6357 netif_device_detach(netdev);
6358
c93b5a76
MM		 6359 if (state == pci_channel_io_perm_failure)
6360 return PCI_ERS_RESULT_DISCONNECT;
6361
bc7f75fa 6362 if (netif_running(netdev))
28002099 6363 e1000e_down(adapter, true);
bc7f75fa
AK		 6364 pci_disable_device(pdev);
6365
6366 /* Request a slot slot reset. */
6367 return PCI_ERS_RESULT_NEED_RESET;
6368}
6369
6370/**
6371 * e1000_io_slot_reset - called after the pci bus has been reset.
6372 * @pdev: Pointer to PCI device
6373 *
6374 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6375 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6376 */
6377static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6378{
6379 struct net_device *netdev = pci_get_drvdata(pdev);
6380 struct e1000_adapter *adapter = netdev_priv(netdev);
6381 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6382 u16 aspm_disable_flag = 0;
6e4f6f6b 6383 int err;
111b9dc5 6384 pci_ers_result_t result;
bc7f75fa 6385
78cd29d5
BA		 6386 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6387 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6388 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6389 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6390 if (aspm_disable_flag)
6391 e1000e_disable_aspm(pdev, aspm_disable_flag);
6392
f0f422e5 6393 err = pci_enable_device_mem(pdev);
6e4f6f6b 6394 if (err) {
bc7f75fa
AK		 6395 dev_err(&pdev->dev,
6396 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6397 result = PCI_ERS_RESULT_DISCONNECT;
6398 } else {
23606cf5 6399 pdev->state_saved = true;
111b9dc5 6400 pci_restore_state(pdev);
66148bab 6401 pci_set_master(pdev);
bc7f75fa 6402
111b9dc5
JB		 6403 pci_enable_wake(pdev, PCI_D3hot, 0);
6404 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6405
111b9dc5
JB		 6406 e1000e_reset(adapter);
6407 ew32(WUS, ~0);
6408 result = PCI_ERS_RESULT_RECOVERED;
6409 }
bc7f75fa 6410
111b9dc5
JB		 6411 pci_cleanup_aer_uncorrect_error_status(pdev);
6412
6413 return result;
bc7f75fa
AK		 6414}
6415
6416/**
6417 * e1000_io_resume - called when traffic can start flowing again.
6418 * @pdev: Pointer to PCI device
6419 *
6420 * This callback is called when the error recovery driver tells us that
6421 * its OK to resume normal operation. Implementation resembles the
28002099 6422 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6423 */
6424static void e1000_io_resume(struct pci_dev *pdev)
6425{
6426 struct net_device *netdev = pci_get_drvdata(pdev);
6427 struct e1000_adapter *adapter = netdev_priv(netdev);
6428
cd791618 6429 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6430
6431 if (netif_running(netdev)) {
6432 if (e1000e_up(adapter)) {
6433 dev_err(&pdev->dev,
6434 "can't bring device back up after reset\n");
6435 return;
6436 }
6437 }
6438
6439 netif_device_attach(netdev);
6440
e921eb1a 6441 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6442 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6443 * under the control of the driver.
6444 */
c43bc57e 6445 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6446 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6447}
6448
6449static void e1000_print_device_info(struct e1000_adapter *adapter)
6450{
6451 struct e1000_hw *hw = &adapter->hw;
6452 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6453 u32 ret_val;
6454 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6455
6456 /* print bus type/speed/width info */
a5cc7642 6457 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6458 /* bus width */
6459 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6460 "Width x1"),
44defeb3 6461 /* MAC address */
7c510e4b 6462 netdev->dev_addr);
44defeb3
JK		 6463 e_info("Intel(R) PRO/%s Network Connection\n",
6464 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6465 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6466 E1000_PBANUM_LENGTH);
6467 if (ret_val)
f2315bf1 6468 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6469 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6470 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6471}
6472
10aa4c04
AK		 6473static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6474{
6475 struct e1000_hw *hw = &adapter->hw;
6476 int ret_val;
6477 u16 buf = 0;
6478
6479 if (hw->mac.type != e1000_82573)
6480 return;
6481
6482 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6483 le16_to_cpus(&buf);
6484 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6485 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6486 dev_warn(&adapter->pdev->dev,
6487 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6488 }
10aa4c04
AK		 6489}
6490
c8f44aff 6491static int e1000_set_features(struct net_device *netdev,
70495a50 6492 netdev_features_t features)
dc221294
BA		 6493{
6494 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6495 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6496
6497 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6498 adapter->flags |= FLAG_TSO_FORCE;
6499
f646968f 6500 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6501 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6502 NETIF_F_RXALL)))
dc221294
BA		 6503 return 0;
6504
0184039a
BG		 6505 if (changed & NETIF_F_RXFCS) {
6506 if (features & NETIF_F_RXFCS) {
6507 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6508 } else {
6509 /* We need to take it back to defaults, which might mean
6510 * stripping is still disabled at the adapter level.
6511 */
6512 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6513 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6514 else
6515 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6516 }
6517 }
6518
70495a50
BA		 6519 netdev->features = features;
6520
dc221294
BA		 6521 if (netif_running(netdev))
6522 e1000e_reinit_locked(adapter);
6523 else
6524 e1000e_reset(adapter);
6525
6526 return 0;
6527}
6528
651c2466
SH		 6529static const struct net_device_ops e1000e_netdev_ops = {
6530 .ndo_open = e1000_open,
6531 .ndo_stop = e1000_close,
00829823 6532 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6533 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6534 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6535 .ndo_set_mac_address = e1000_set_mac,
6536 .ndo_change_mtu = e1000_change_mtu,
6537 .ndo_do_ioctl = e1000_ioctl,
6538 .ndo_tx_timeout = e1000_tx_timeout,
6539 .ndo_validate_addr = eth_validate_addr,
6540
651c2466
SH		 6541 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6542 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6543#ifdef CONFIG_NET_POLL_CONTROLLER
6544 .ndo_poll_controller = e1000_netpoll,
6545#endif
dc221294 6546 .ndo_set_features = e1000_set_features,
651c2466
SH		 6547};
6548
bc7f75fa
AK		 6549/**
6550 * e1000_probe - Device Initialization Routine
6551 * @pdev: PCI device information struct
6552 * @ent: entry in e1000_pci_tbl
6553 *
6554 * Returns 0 on success, negative on failure
6555 *
6556 * e1000_probe initializes an adapter identified by a pci_dev structure.
6557 * The OS initialization, configuring of the adapter private structure,
6558 * and a hardware reset occur.
6559 **/
1dd06ae8 6560static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6561{
6562 struct net_device *netdev;
6563 struct e1000_adapter *adapter;
6564 struct e1000_hw *hw;
6565 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6566 resource_size_t mmio_start, mmio_len;
6567 resource_size_t flash_start, flash_len;
bc7f75fa 6568 static int cards_found;
78cd29d5 6569 u16 aspm_disable_flag = 0;
17e813ec 6570 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6571 u16 eeprom_data = 0;
6572 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6573
78cd29d5
BA		 6574 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6575 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6576 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6577 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6578 if (aspm_disable_flag)
6579 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6580
f0f422e5 6581 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6582 if (err)
6583 return err;
6584
6585 pci_using_dac = 0;
718a39eb 6586 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6587 if (!err) {
718a39eb 6588 pci_using_dac = 1;
bc7f75fa 6589 } else {
718a39eb 6590 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6591 if (err) {
718a39eb
RK		 6592 dev_err(&pdev->dev,
6593 "No usable DMA configuration, aborting\n");
6594 goto err_dma;
bc7f75fa
AK		 6595 }
6596 }
6597
17e813ec
BA		 6598 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6599 err = pci_request_selected_regions_exclusive(pdev, bars,
6600 e1000e_driver_name);
bc7f75fa
AK		 6601 if (err)
6602 goto err_pci_reg;
6603
68eac460 6604 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6605 pci_enable_pcie_error_reporting(pdev);
68eac460 6606
bc7f75fa 6607 pci_set_master(pdev);
438b365a
BA		 6608 /* PCI config space info */
6609 err = pci_save_state(pdev);
6610 if (err)
6611 goto err_alloc_etherdev;
bc7f75fa
AK		 6612
6613 err = -ENOMEM;
6614 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6615 if (!netdev)
6616 goto err_alloc_etherdev;
6617
bc7f75fa
AK		 6618 SET_NETDEV_DEV(netdev, &pdev->dev);
6619
f85e4dfa
TH		 6620 netdev->irq = pdev->irq;
6621
bc7f75fa
AK		 6622 pci_set_drvdata(pdev, netdev);
6623 adapter = netdev_priv(netdev);
6624 hw = &adapter->hw;
6625 adapter->netdev = netdev;
6626 adapter->pdev = pdev;
6627 adapter->ei = ei;
6628 adapter->pba = ei->pba;
6629 adapter->flags = ei->flags;
eb7c3adb 6630 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6631 adapter->hw.adapter = adapter;
6632 adapter->hw.mac.type = ei->mac;
2adc55c9 6633 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6634 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6635
6636 mmio_start = pci_resource_start(pdev, 0);
6637 mmio_len = pci_resource_len(pdev, 0);
6638
6639 err = -EIO;
6640 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6641 if (!adapter->hw.hw_addr)
6642 goto err_ioremap;
6643
6644 if ((adapter->flags & FLAG_HAS_FLASH) &&
6645 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6646 flash_start = pci_resource_start(pdev, 1);
6647 flash_len = pci_resource_len(pdev, 1);
6648 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6649 if (!adapter->hw.flash_address)
6650 goto err_flashmap;
6651 }
6652
d495bcb8
BA		 6653 /* Set default EEE advertisement */
6654 if (adapter->flags2 & FLAG2_HAS_EEE)
6655 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6656
bc7f75fa 6657 /* construct the net_device struct */
e80bd1d1 6658 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6659 e1000e_set_ethtool_ops(netdev);
e80bd1d1 6660 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6661 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6662 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6663
6664 netdev->mem_start = mmio_start;
6665 netdev->mem_end = mmio_start + mmio_len;
6666
6667 adapter->bd_number = cards_found++;
6668
4662e82b
BA		 6669 e1000e_check_options(adapter);
6670
bc7f75fa
AK		 6671 /* setup adapter struct */
6672 err = e1000_sw_init(adapter);
6673 if (err)
6674 goto err_sw_init;
6675
bc7f75fa
AK		 6676 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6677 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6678 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6679
69e3fd8c 6680 err = ei->get_variants(adapter);
bc7f75fa
AK		 6681 if (err)
6682 goto err_hw_init;
6683
4a770358
BA		 6684 if ((adapter->flags & FLAG_IS_ICH) &&
6685 (adapter->flags & FLAG_READ_ONLY_NVM))
6686 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6687
bc7f75fa
AK		 6688 hw->mac.ops.get_bus_info(&adapter->hw);
6689
318a94d6 6690 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6691
6692 /* Copper options */
318a94d6 6693 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6694 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6695 adapter->hw.phy.disable_polarity_correction = 0;
6696 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6697 }
6698
470a5420 6699 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6700 dev_info(&pdev->dev,
6701 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6702
dc221294
BA		 6703 /* Set initial default active device features */
6704 netdev->features = (NETIF_F_SG |
f646968f
PM		 6705 NETIF_F_HW_VLAN_CTAG_RX |
6706 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6707 NETIF_F_TSO |
6708 NETIF_F_TSO6 |
70495a50 6709 NETIF_F_RXHASH |
dc221294
BA		 6710 NETIF_F_RXCSUM |
6711 NETIF_F_HW_CSUM);
6712
6713 /* Set user-changeable features (subset of all device features) */
6714 netdev->hw_features = netdev->features;
0184039a 6715 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6716 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6717 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6718
6719 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6720 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6721
dc221294
BA		 6722 netdev->vlan_features |= (NETIF_F_SG |
6723 NETIF_F_TSO |
6724 NETIF_F_TSO6 |
6725 NETIF_F_HW_CSUM);
a5136e23 6726
ef9b965a
JB		 6727 netdev->priv_flags |= IFF_UNICAST_FLT;
6728
7b872a55 6729 if (pci_using_dac) {
bc7f75fa 6730 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6731 netdev->vlan_features |= NETIF_F_HIGHDMA;
6732 }
bc7f75fa 6733
bc7f75fa
AK		 6734 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6735 adapter->flags |= FLAG_MNG_PT_ENABLED;
6736
e921eb1a 6737 /* before reading the NVM, reset the controller to
ad68076e
BA		 6738 * put the device in a known good starting state
6739 */
bc7f75fa
AK		 6740 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6741
e921eb1a 6742 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6743 * attempt. Let's give it a few tries
6744 */
6745 for (i = 0;; i++) {
6746 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6747 break;
6748 if (i == 2) {
185095fb 6749 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6750 err = -EIO;
6751 goto err_eeprom;
6752 }
6753 }
6754
10aa4c04
AK		 6755 e1000_eeprom_checks(adapter);
6756
608f8a0d 6757 /* copy the MAC address */
bc7f75fa 6758 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6759 dev_err(&pdev->dev,
6760 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6761
6762 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6763
aaeb6cdf 6764 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6765 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6766 netdev->dev_addr);
bc7f75fa
AK		 6767 err = -EIO;
6768 goto err_eeprom;
6769 }
6770
6771 init_timer(&adapter->watchdog_timer);
c061b18d 6772 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6773 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6774
6775 init_timer(&adapter->phy_info_timer);
c061b18d 6776 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6777 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6778
6779 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6780 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6781 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6782 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6783 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6784
bc7f75fa
AK		 6785 /* Initialize link parameters. User can change them with ethtool */
6786 adapter->hw.mac.autoneg = 1;
3db1cd5c 6787 adapter->fc_autoneg = true;
5c48ef3e
BA		 6788 adapter->hw.fc.requested_mode = e1000_fc_default;
6789 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6790 adapter->hw.phy.autoneg_advertised = 0x2f;
6791
e921eb1a 6792 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6793 * the EEPROM, enable the ACPI Magic Packet filter
6794 */
6795 if (adapter->flags & FLAG_APME_IN_WUC) {
6796 /* APME bit in EEPROM is mapped to WUC.APME */
6797 eeprom_data = er32(WUC);
6798 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6799 if ((hw->mac.type > e1000_ich10lan) &&
6800 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6801 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6802 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6803 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6804 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6805 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6806 1, &eeprom_data);
bc7f75fa 6807 else
3d3a1676
BA		 6808 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6809 1, &eeprom_data);
bc7f75fa
AK		 6810 }
6811
6812 /* fetch WoL from EEPROM */
6813 if (eeprom_data & eeprom_apme_mask)
6814 adapter->eeprom_wol |= E1000_WUFC_MAG;
6815
e921eb1a 6816 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6817 * where the eeprom may be wrong or the board simply won't support
6818 * wake on lan on a particular port
6819 */
6820 if (!(adapter->flags & FLAG_HAS_WOL))
6821 adapter->eeprom_wol = 0;
6822
6823 /* initialize the wol settings based on the eeprom settings */
6824 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6825
6826 /* make sure adapter isn't asleep if manageability is enabled */
6827 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6828 (hw->mac.ops.check_mng_mode(hw)))
6829 device_wakeup_enable(&pdev->dev);
bc7f75fa 6830
84527590
BA		 6831 /* save off EEPROM version number */
6832 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6833
bc7f75fa
AK		 6834 /* reset the hardware with the new settings */
6835 e1000e_reset(adapter);
6836
e921eb1a 6837 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6838 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6839 * under the control of the driver.
6840 */
c43bc57e 6841 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6842 e1000e_get_hw_control(adapter);
bc7f75fa 6843
f2315bf1 6844 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6845 err = register_netdev(netdev);
6846 if (err)
6847 goto err_register;
6848
9c563d20
JB		 6849 /* carrier off reporting is important to ethtool even BEFORE open */
6850 netif_carrier_off(netdev);
6851
d89777bf
BA		 6852 /* init PTP hardware clock */
6853 e1000e_ptp_init(adapter);
6854
bc7f75fa
AK		 6855 e1000_print_device_info(adapter);
6856
f3ec4f87
AS		 6857 if (pci_dev_run_wake(pdev))
6858 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6859
bc7f75fa
AK		 6860 return 0;
6861
6862err_register:
c43bc57e 6863 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6864 e1000e_release_hw_control(adapter);
bc7f75fa 6865err_eeprom:
470a5420 6866 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6867 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6868err_hw_init:
bc7f75fa
AK		 6869 kfree(adapter->tx_ring);
6870 kfree(adapter->rx_ring);
6871err_sw_init:
c43bc57e
JB		 6872 if (adapter->hw.flash_address)
6873 iounmap(adapter->hw.flash_address);
e82f54ba 6874 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6875err_flashmap:
bc7f75fa
AK		 6876 iounmap(adapter->hw.hw_addr);
6877err_ioremap:
6878 free_netdev(netdev);
6879err_alloc_etherdev:
f0f422e5 6880 pci_release_selected_regions(pdev,
f0ff4398 6881 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6882err_pci_reg:
6883err_dma:
6884 pci_disable_device(pdev);
6885 return err;
6886}
6887
6888/**
6889 * e1000_remove - Device Removal Routine
6890 * @pdev: PCI device information struct
6891 *
6892 * e1000_remove is called by the PCI subsystem to alert the driver
6893 * that it should release a PCI device. The could be caused by a
6894 * Hot-Plug event, or because the driver is going to be removed from
6895 * memory.
6896 **/
9f9a12f8 6897static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6898{
6899 struct net_device *netdev = pci_get_drvdata(pdev);
6900 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6901 bool down = test_bit(__E1000_DOWN, &adapter->state);
6902
d89777bf
BA		 6903 e1000e_ptp_remove(adapter);
6904
e921eb1a 6905 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6906 * from being rescheduled.
ad68076e 6907 */
23606cf5
RW		 6908 if (!down)
6909 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6910 del_timer_sync(&adapter->watchdog_timer);
6911 del_timer_sync(&adapter->phy_info_timer);
6912
41cec6f1
BA		 6913 cancel_work_sync(&adapter->reset_task);
6914 cancel_work_sync(&adapter->watchdog_task);
6915 cancel_work_sync(&adapter->downshift_task);
6916 cancel_work_sync(&adapter->update_phy_task);
6917 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6918
b67e1913
BA		 6919 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6920 cancel_work_sync(&adapter->tx_hwtstamp_work);
6921 if (adapter->tx_hwtstamp_skb) {
6922 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6923 adapter->tx_hwtstamp_skb = NULL;
6924 }
6925 }
6926
23606cf5
RW		 6927 /* Don't lie to e1000_close() down the road. */
6928 if (!down)
6929 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6930 unregister_netdev(netdev);
6931
f3ec4f87
AS		 6932 if (pci_dev_run_wake(pdev))
6933 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6934
e921eb1a 6935 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6936 * would have already happened in close and is redundant.
6937 */
31dbe5b4 6938 e1000e_release_hw_control(adapter);
bc7f75fa 6939
4662e82b 6940 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6941 kfree(adapter->tx_ring);
6942 kfree(adapter->rx_ring);
6943
6944 iounmap(adapter->hw.hw_addr);
6945 if (adapter->hw.flash_address)
6946 iounmap(adapter->hw.flash_address);
f0f422e5 6947 pci_release_selected_regions(pdev,
f0ff4398 6948 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6949
6950 free_netdev(netdev);
6951
111b9dc5 6952 /* AER disable */
19d5afd4 6953 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6954
bc7f75fa
AK		 6955 pci_disable_device(pdev);
6956}
6957
6958/* PCI Error Recovery (ERS) */
3646f0e5 6959static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6960 .error_detected = e1000_io_error_detected,
6961 .slot_reset = e1000_io_slot_reset,
6962 .resume = e1000_io_resume,
6963};
6964
a3aa1884 6965static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6966 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6968 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 6969 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
6970 board_82571 },
bc7f75fa
AK		 6971 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6973 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6975 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6976
bc7f75fa
AK		 6977 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6978 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6979 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6980 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6981
bc7f75fa
AK		 6982 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6983 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6984 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6985
4662e82b 6986 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6987 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6988 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6989
bc7f75fa
AK		 6990 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6991 board_80003es2lan },
6992 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6993 board_80003es2lan },
6994 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6995 board_80003es2lan },
6996 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6997 board_80003es2lan },
ad68076e 6998
bc7f75fa
AK		 6999 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7000 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7001 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7002 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7003 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7004 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7005 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7006 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7007
bc7f75fa
AK		 7008 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7009 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7010 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7011 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7012 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7013 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7014 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7015 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7016 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7017
7018 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7019 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7020 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7021
f4187b56
BA		 7022 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7023 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7024 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7025
a4f58f54
BA		 7026 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7027 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7028 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7029 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7030
d3738bb8
BA		 7031 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7032 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7033
2fbe4526
BA		 7034 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7035 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7036 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7037 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7038 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7039 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7040 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7041 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
2fbe4526 7042
f36bb6ca 7043 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7044};
7045MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7046
23606cf5 7047static const struct dev_pm_ops e1000_pm_ops = {
28002099
DE		 7048 .suspend = e1000e_pm_suspend,
7049 .resume = e1000e_pm_resume,
7050 .freeze = e1000e_pm_freeze,
7051 .thaw = e1000e_pm_thaw,
7052 .poweroff = e1000e_pm_suspend,
7053 .restore = e1000e_pm_resume,
17e813ec
BA		 7054 SET_RUNTIME_PM_OPS(e1000_runtime_suspend, e1000_runtime_resume,
7055 e1000_idle)
23606cf5
RW		 7056};
7057
bc7f75fa
AK		 7058/* PCI Device API Driver */
7059static struct pci_driver e1000_driver = {
7060 .name = e1000e_driver_name,
7061 .id_table = e1000_pci_tbl,
7062 .probe = e1000_probe,
9f9a12f8 7063 .remove = e1000_remove,
f36bb6ca
BA		 7064 .driver = {
7065 .pm = &e1000_pm_ops,
7066 },
bc7f75fa
AK		 7067 .shutdown = e1000_shutdown,
7068 .err_handler = &e1000_err_handler
7069};
7070
7071/**
7072 * e1000_init_module - Driver Registration Routine
7073 *
7074 * e1000_init_module is the first routine called when the driver is
7075 * loaded. All it does is register with the PCI subsystem.
7076 **/
7077static int __init e1000_init_module(void)
7078{
7079 int ret;
8544b9f7
BA		 7080 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7081 e1000e_driver_version);
e78b80b1 7082 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n");
bc7f75fa 7083 ret = pci_register_driver(&e1000_driver);
53ec5498 7084
bc7f75fa
AK		 7085 return ret;
7086}
7087module_init(e1000_init_module);
7088
7089/**
7090 * e1000_exit_module - Driver Exit Cleanup Routine
7091 *
7092 * e1000_exit_module is called just before the driver is removed
7093 * from memory.
7094 **/
7095static void __exit e1000_exit_module(void)
7096{
7097 pci_unregister_driver(&e1000_driver);
7098}
7099module_exit(e1000_exit_module);
7100
bc7f75fa
AK		 7101MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7102MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7103MODULE_LICENSE("GPL");
7104MODULE_VERSION(DRV_VERSION);
7105
06c24b91 7106/* netdev.c */
Linux kernel - Deliverables
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