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ipv6: Use ipv6_addr_any()
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
0d6057e4 4 Copyright(c) 1999 - 2011 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
c5778b43 59#define DRV_VERSION "1.5.1" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
78cd29d5
BA		 63static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
64
bc7f75fa
AK		 65static const struct e1000_info *e1000_info_tbl[] = {
66 [board_82571] = &e1000_82571_info,
67 [board_82572] = &e1000_82572_info,
68 [board_82573] = &e1000_82573_info,
4662e82b 69 [board_82574] = &e1000_82574_info,
8c81c9c3 70 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 71 [board_80003es2lan] = &e1000_es2_info,
72 [board_ich8lan] = &e1000_ich8_info,
73 [board_ich9lan] = &e1000_ich9_info,
f4187b56 74 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 75 [board_pchlan] = &e1000_pch_info,
d3738bb8 76 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 77};
78
84f4ee90
TI		 79struct e1000_reg_info {
80 u32 ofs;
81 char *name;
82};
83
af667a29
BA		 84#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
85#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
86#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
87#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
88#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
89
90#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
91#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
92#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
93#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
94#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 95
96static const struct e1000_reg_info e1000_reg_info_tbl[] = {
97
98 /* General Registers */
99 {E1000_CTRL, "CTRL"},
100 {E1000_STATUS, "STATUS"},
101 {E1000_CTRL_EXT, "CTRL_EXT"},
102
103 /* Interrupt Registers */
104 {E1000_ICR, "ICR"},
105
af667a29 106 /* Rx Registers */
84f4ee90
TI		 107 {E1000_RCTL, "RCTL"},
108 {E1000_RDLEN, "RDLEN"},
109 {E1000_RDH, "RDH"},
110 {E1000_RDT, "RDT"},
111 {E1000_RDTR, "RDTR"},
112 {E1000_RXDCTL(0), "RXDCTL"},
113 {E1000_ERT, "ERT"},
114 {E1000_RDBAL, "RDBAL"},
115 {E1000_RDBAH, "RDBAH"},
116 {E1000_RDFH, "RDFH"},
117 {E1000_RDFT, "RDFT"},
118 {E1000_RDFHS, "RDFHS"},
119 {E1000_RDFTS, "RDFTS"},
120 {E1000_RDFPC, "RDFPC"},
121
af667a29 122 /* Tx Registers */
84f4ee90
TI		 123 {E1000_TCTL, "TCTL"},
124 {E1000_TDBAL, "TDBAL"},
125 {E1000_TDBAH, "TDBAH"},
126 {E1000_TDLEN, "TDLEN"},
127 {E1000_TDH, "TDH"},
128 {E1000_TDT, "TDT"},
129 {E1000_TIDV, "TIDV"},
130 {E1000_TXDCTL(0), "TXDCTL"},
131 {E1000_TADV, "TADV"},
132 {E1000_TARC(0), "TARC"},
133 {E1000_TDFH, "TDFH"},
134 {E1000_TDFT, "TDFT"},
135 {E1000_TDFHS, "TDFHS"},
136 {E1000_TDFTS, "TDFTS"},
137 {E1000_TDFPC, "TDFPC"},
138
139 /* List Terminator */
140 {}
141};
142
143/*
144 * e1000_regdump - register printout routine
145 */
146static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
147{
148 int n = 0;
149 char rname[16];
150 u32 regs[8];
151
152 switch (reginfo->ofs) {
153 case E1000_RXDCTL(0):
154 for (n = 0; n < 2; n++)
155 regs[n] = __er32(hw, E1000_RXDCTL(n));
156 break;
157 case E1000_TXDCTL(0):
158 for (n = 0; n < 2; n++)
159 regs[n] = __er32(hw, E1000_TXDCTL(n));
160 break;
161 case E1000_TARC(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_TARC(n));
164 break;
165 default:
ef456f85
JK		 166 pr_info("%-15s %08x\n",
167 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 168 return;
169 }
170
171 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 172 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 173}
174
84f4ee90 175/*
af667a29 176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 177 */
178static void e1000e_dump(struct e1000_adapter *adapter)
179{
180 struct net_device *netdev = adapter->netdev;
181 struct e1000_hw *hw = &adapter->hw;
182 struct e1000_reg_info *reginfo;
183 struct e1000_ring *tx_ring = adapter->tx_ring;
184 struct e1000_tx_desc *tx_desc;
af667a29
BA		 185 struct my_u0 {
186 u64 a;
187 u64 b;
188 } *u0;
84f4ee90
TI		 189 struct e1000_buffer *buffer_info;
190 struct e1000_ring *rx_ring = adapter->rx_ring;
191 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 192 union e1000_rx_desc_extended *rx_desc;
af667a29
BA		 193 struct my_u1 {
194 u64 a;
195 u64 b;
196 u64 c;
197 u64 d;
198 } *u1;
84f4ee90
TI		 199 u32 staterr;
200 int i = 0;
201
202 if (!netif_msg_hw(adapter))
203 return;
204
205 /* Print netdevice Info */
206 if (netdev) {
207 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 208 pr_info("Device Name state trans_start last_rx\n");
209 pr_info("%-15s %016lX %016lX %016lX\n",
210 netdev->name, netdev->state, netdev->trans_start,
211 netdev->last_rx);
84f4ee90
TI		 212 }
213
214 /* Print Registers */
215 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 216 pr_info(" Register Name Value\n");
84f4ee90
TI		 217 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
218 reginfo->name; reginfo++) {
219 e1000_regdump(hw, reginfo);
220 }
221
af667a29 222 /* Print Tx Ring Summary */
84f4ee90
TI		 223 if (!netdev || !netif_running(netdev))
224 goto exit;
225
af667a29 226 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 227 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 228 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 229 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
230 0, tx_ring->next_to_use, tx_ring->next_to_clean,
231 (unsigned long long)buffer_info->dma,
232 buffer_info->length,
233 buffer_info->next_to_watch,
234 (unsigned long long)buffer_info->time_stamp);
84f4ee90 235
af667a29 236 /* Print Tx Ring */
84f4ee90
TI		 237 if (!netif_msg_tx_done(adapter))
238 goto rx_ring_summary;
239
af667a29 240 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 241
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
ef456f85
JK		 269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 272 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 273 const char *next_desc;
84f4ee90
TI		 274 tx_desc = E1000_TX_DESC(*tx_ring, i);
275 buffer_info = &tx_ring->buffer_info[i];
276 u0 = (struct my_u0 *)tx_desc;
84f4ee90 277 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 278 next_desc = " NTC/U";
84f4ee90 279 else if (i == tx_ring->next_to_use)
ef456f85 280 next_desc = " NTU";
84f4ee90 281 else if (i == tx_ring->next_to_clean)
ef456f85 282 next_desc = " NTC";
84f4ee90 283 else
ef456f85
JK		 284 next_desc = "";
285 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
286 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
287 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
288 i,
289 (unsigned long long)le64_to_cpu(u0->a),
290 (unsigned long long)le64_to_cpu(u0->b),
291 (unsigned long long)buffer_info->dma,
292 buffer_info->length, buffer_info->next_to_watch,
293 (unsigned long long)buffer_info->time_stamp,
294 buffer_info->skb, next_desc);
84f4ee90
TI		 295
296 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
297 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 298 16, 1, phys_to_virt(buffer_info->dma),
299 buffer_info->length, true);
84f4ee90
TI		 300 }
301
af667a29 302 /* Print Rx Ring Summary */
84f4ee90 303rx_ring_summary:
af667a29 304 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 305 pr_info("Queue [NTU] [NTC]\n");
306 pr_info(" %5d %5X %5X\n",
307 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 308
af667a29 309 /* Print Rx Ring */
84f4ee90
TI		 310 if (!netif_msg_rx_status(adapter))
311 goto exit;
312
af667a29 313 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 314 switch (adapter->rx_ps_pages) {
315 case 1:
316 case 2:
317 case 3:
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
ef456f85 330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
ef456f85 342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 343 for (i = 0; i < rx_ring->count; i++) {
ef456f85 344 const char *next_desc;
84f4ee90
TI		 345 buffer_info = &rx_ring->buffer_info[i];
346 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
347 u1 = (struct my_u1 *)rx_desc_ps;
348 staterr =
af667a29 349 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 350
351 if (i == rx_ring->next_to_use)
352 next_desc = " NTU";
353 else if (i == rx_ring->next_to_clean)
354 next_desc = " NTC";
355 else
356 next_desc = "";
357
84f4ee90
TI		 358 if (staterr & E1000_RXD_STAT_DD) {
359 /* Descriptor Done */
ef456f85
JK		 360 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
361 "RWB", i,
362 (unsigned long long)le64_to_cpu(u1->a),
363 (unsigned long long)le64_to_cpu(u1->b),
364 (unsigned long long)le64_to_cpu(u1->c),
365 (unsigned long long)le64_to_cpu(u1->d),
366 buffer_info->skb, next_desc);
84f4ee90 367 } else {
ef456f85
JK		 368 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
369 "R ", i,
370 (unsigned long long)le64_to_cpu(u1->a),
371 (unsigned long long)le64_to_cpu(u1->b),
372 (unsigned long long)le64_to_cpu(u1->c),
373 (unsigned long long)le64_to_cpu(u1->d),
374 (unsigned long long)buffer_info->dma,
375 buffer_info->skb, next_desc);
84f4ee90
TI		 376
377 if (netif_msg_pktdata(adapter))
378 print_hex_dump(KERN_INFO, "",
379 DUMP_PREFIX_ADDRESS, 16, 1,
380 phys_to_virt(buffer_info->dma),
381 adapter->rx_ps_bsize0, true);
382 }
84f4ee90
TI		 383 }
384 break;
385 default:
386 case 0:
5f450212 387 /* Extended Receive Descriptor (Read) Format
84f4ee90 388 *
5f450212
BA		 389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
84f4ee90 394 */
ef456f85 395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
ef456f85 409 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 410
411 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 412 const char *next_desc;
413
84f4ee90 414 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 415 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
416 u1 = (struct my_u1 *)rx_desc;
417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 418
419 if (i == rx_ring->next_to_use)
420 next_desc = " NTU";
421 else if (i == rx_ring->next_to_clean)
422 next_desc = " NTC";
423 else
424 next_desc = "";
425
5f450212
BA		 426 if (staterr & E1000_RXD_STAT_DD) {
427 /* Descriptor Done */
ef456f85
JK		 428 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
429 "RWB", i,
430 (unsigned long long)le64_to_cpu(u1->a),
431 (unsigned long long)le64_to_cpu(u1->b),
432 buffer_info->skb, next_desc);
5f450212 433 } else {
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
435 "R ", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 (unsigned long long)buffer_info->dma,
439 buffer_info->skb, next_desc);
5f450212
BA		 440
441 if (netif_msg_pktdata(adapter))
442 print_hex_dump(KERN_INFO, "",
443 DUMP_PREFIX_ADDRESS, 16,
444 1,
445 phys_to_virt
446 (buffer_info->dma),
447 adapter->rx_buffer_len,
448 true);
449 }
84f4ee90
TI		 450 }
451 }
452
453exit:
454 return;
455}
456
bc7f75fa
AK		 457/**
458 * e1000_desc_unused - calculate if we have unused descriptors
459 **/
460static int e1000_desc_unused(struct e1000_ring *ring)
461{
462 if (ring->next_to_clean > ring->next_to_use)
463 return ring->next_to_clean - ring->next_to_use - 1;
464
465 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
466}
467
468/**
ad68076e 469 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 470 * @adapter: board private structure
471 * @status: descriptor status field as written by hardware
472 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
473 * @skb: pointer to sk_buff to be indicated to stack
474 **/
475static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 476 struct net_device *netdev, struct sk_buff *skb,
a39fe742 477 u8 status, __le16 vlan)
bc7f75fa 478{
86d70e53 479 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 480 skb->protocol = eth_type_trans(skb, netdev);
481
86d70e53
JK		 482 if (status & E1000_RXD_STAT_VP)
483 __vlan_hwaccel_put_tag(skb, tag);
484
485 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 486}
487
488/**
af667a29 489 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 490 * @adapter: board private structure
491 * @status_err: receive descriptor status and error fields
492 * @csum: receive descriptor csum field
493 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 494 **/
495static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 496 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 497{
498 u16 status = (u16)status_err;
499 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 500
501 skb_checksum_none_assert(skb);
bc7f75fa 502
afd12939
BA		 503 /* Rx checksum disabled */
504 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
505 return;
506
bc7f75fa
AK		 507 /* Ignore Checksum bit is set */
508 if (status & E1000_RXD_STAT_IXSM)
509 return;
afd12939 510
bc7f75fa
AK		 511 /* TCP/UDP checksum error bit is set */
512 if (errors & E1000_RXD_ERR_TCPE) {
513 /* let the stack verify checksum errors */
514 adapter->hw_csum_err++;
515 return;
516 }
517
518 /* TCP/UDP Checksum has not been calculated */
519 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
520 return;
521
522 /* It must be a TCP or UDP packet with a valid checksum */
523 if (status & E1000_RXD_STAT_TCPCS) {
524 /* TCP checksum is good */
525 skb->ip_summed = CHECKSUM_UNNECESSARY;
526 } else {
ad68076e
BA		 527 /*
528 * IP fragment with UDP payload
529 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 530 * and then put the value in host order for further stack use.
531 */
afd12939 532 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 533 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 534 skb->ip_summed = CHECKSUM_COMPLETE;
535 }
536 adapter->hw_csum_good++;
537}
538
c6e7f51e
BA		 539/**
540 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
541 * @hw: pointer to the HW structure
542 * @tail: address of tail descriptor register
543 * @i: value to write to tail descriptor register
544 *
545 * When updating the tail register, the ME could be accessing Host CSR
546 * registers at the same time. Normally, this is handled in h/w by an
547 * arbiter but on some parts there is a bug that acknowledges Host accesses
548 * later than it should which could result in the descriptor register to
549 * have an incorrect value. Workaround this by checking the FWSM register
550 * which has bit 24 set while ME is accessing Host CSR registers, wait
551 * if it is set and try again a number of times.
552 **/
c5083cf6 553static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, void __iomem *tail,
c6e7f51e
BA		 554 unsigned int i)
555{
556 unsigned int j = 0;
557
558 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
559 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
560 udelay(50);
561
562 writel(i, tail);
563
564 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
565 return E1000_ERR_SWFW_SYNC;
566
567 return 0;
568}
569
55aa6985 570static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 571{
55aa6985 572 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e
BA		 573 struct e1000_hw *hw = &adapter->hw;
574
55aa6985 575 if (e1000e_update_tail_wa(hw, rx_ring->tail, i)) {
c6e7f51e
BA		 576 u32 rctl = er32(RCTL);
577 ew32(RCTL, rctl & ~E1000_RCTL_EN);
578 e_err("ME firmware caused invalid RDT - resetting\n");
579 schedule_work(&adapter->reset_task);
580 }
581}
582
55aa6985 583static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 584{
55aa6985 585 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 586 struct e1000_hw *hw = &adapter->hw;
587
55aa6985 588 if (e1000e_update_tail_wa(hw, tx_ring->tail, i)) {
c6e7f51e
BA		 589 u32 tctl = er32(TCTL);
590 ew32(TCTL, tctl & ~E1000_TCTL_EN);
591 e_err("ME firmware caused invalid TDT - resetting\n");
592 schedule_work(&adapter->reset_task);
593 }
594}
595
bc7f75fa 596/**
5f450212 597 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 598 * @rx_ring: Rx descriptor ring
bc7f75fa 599 **/
55aa6985 600static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 601 int cleaned_count, gfp_t gfp)
bc7f75fa 602{
55aa6985 603 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 604 struct net_device *netdev = adapter->netdev;
605 struct pci_dev *pdev = adapter->pdev;
5f450212 606 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 607 struct e1000_buffer *buffer_info;
608 struct sk_buff *skb;
609 unsigned int i;
89d71a66 610 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 611
612 i = rx_ring->next_to_use;
613 buffer_info = &rx_ring->buffer_info[i];
614
615 while (cleaned_count--) {
616 skb = buffer_info->skb;
617 if (skb) {
618 skb_trim(skb, 0);
619 goto map_skb;
620 }
621
c2fed996 622 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 623 if (!skb) {
624 /* Better luck next round */
625 adapter->alloc_rx_buff_failed++;
626 break;
627 }
628
bc7f75fa
AK		 629 buffer_info->skb = skb;
630map_skb:
0be3f55f 631 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 632 adapter->rx_buffer_len,
0be3f55f
NN		 633 DMA_FROM_DEVICE);
634 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 635 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 636 adapter->rx_dma_failed++;
637 break;
638 }
639
5f450212
BA		 640 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
641 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 642
50849d79
TH		 643 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
644 /*
645 * Force memory writes to complete before letting h/w
646 * know there are new descriptors to fetch. (Only
647 * applicable for weak-ordered memory model archs,
648 * such as IA-64).
649 */
650 wmb();
c6e7f51e 651 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 652 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 653 else
c5083cf6 654 writel(i, rx_ring->tail);
50849d79 655 }
bc7f75fa
AK		 656 i++;
657 if (i == rx_ring->count)
658 i = 0;
659 buffer_info = &rx_ring->buffer_info[i];
660 }
661
50849d79 662 rx_ring->next_to_use = i;
bc7f75fa
AK		 663}
664
665/**
666 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 667 * @rx_ring: Rx descriptor ring
bc7f75fa 668 **/
55aa6985 669static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 670 int cleaned_count, gfp_t gfp)
bc7f75fa 671{
55aa6985 672 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 673 struct net_device *netdev = adapter->netdev;
674 struct pci_dev *pdev = adapter->pdev;
675 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 676 struct e1000_buffer *buffer_info;
677 struct e1000_ps_page *ps_page;
678 struct sk_buff *skb;
679 unsigned int i, j;
680
681 i = rx_ring->next_to_use;
682 buffer_info = &rx_ring->buffer_info[i];
683
684 while (cleaned_count--) {
685 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
686
687 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 688 ps_page = &buffer_info->ps_pages[j];
689 if (j >= adapter->rx_ps_pages) {
690 /* all unused desc entries get hw null ptr */
af667a29
BA		 691 rx_desc->read.buffer_addr[j + 1] =
692 ~cpu_to_le64(0);
47f44e40
AK		 693 continue;
694 }
695 if (!ps_page->page) {
c2fed996 696 ps_page->page = alloc_page(gfp);
bc7f75fa 697 if (!ps_page->page) {
47f44e40
AK		 698 adapter->alloc_rx_buff_failed++;
699 goto no_buffers;
700 }
0be3f55f
NN		 701 ps_page->dma = dma_map_page(&pdev->dev,
702 ps_page->page,
703 0, PAGE_SIZE,
704 DMA_FROM_DEVICE);
705 if (dma_mapping_error(&pdev->dev,
706 ps_page->dma)) {
47f44e40 707 dev_err(&adapter->pdev->dev,
af667a29 708 "Rx DMA page map failed\n");
47f44e40
AK		 709 adapter->rx_dma_failed++;
710 goto no_buffers;
bc7f75fa 711 }
bc7f75fa 712 }
47f44e40
AK		 713 /*
714 * Refresh the desc even if buffer_addrs
715 * didn't change because each write-back
716 * erases this info.
717 */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 720 }
721
c2fed996
JK		 722 skb = __netdev_alloc_skb_ip_align(netdev,
723 adapter->rx_ps_bsize0,
724 gfp);
bc7f75fa
AK		 725
726 if (!skb) {
727 adapter->alloc_rx_buff_failed++;
728 break;
729 }
730
bc7f75fa 731 buffer_info->skb = skb;
0be3f55f 732 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 733 adapter->rx_ps_bsize0,
0be3f55f
NN		 734 DMA_FROM_DEVICE);
735 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 736 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 737 adapter->rx_dma_failed++;
738 /* cleanup skb */
739 dev_kfree_skb_any(skb);
740 buffer_info->skb = NULL;
741 break;
742 }
743
744 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
745
50849d79
TH		 746 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
747 /*
748 * Force memory writes to complete before letting h/w
749 * know there are new descriptors to fetch. (Only
750 * applicable for weak-ordered memory model archs,
751 * such as IA-64).
752 */
753 wmb();
c6e7f51e 754 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 755 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 756 else
c5083cf6 757 writel(i << 1, rx_ring->tail);
50849d79
TH		 758 }
759
bc7f75fa
AK		 760 i++;
761 if (i == rx_ring->count)
762 i = 0;
763 buffer_info = &rx_ring->buffer_info[i];
764 }
765
766no_buffers:
50849d79 767 rx_ring->next_to_use = i;
bc7f75fa
AK		 768}
769
97ac8cae
BA		 770/**
771 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 772 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 773 * @cleaned_count: number of buffers to allocate this pass
774 **/
775
55aa6985 776static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 777 int cleaned_count, gfp_t gfp)
97ac8cae 778{
55aa6985 779 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 780 struct net_device *netdev = adapter->netdev;
781 struct pci_dev *pdev = adapter->pdev;
5f450212 782 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 783 struct e1000_buffer *buffer_info;
784 struct sk_buff *skb;
785 unsigned int i;
89d71a66 786 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 787
788 i = rx_ring->next_to_use;
789 buffer_info = &rx_ring->buffer_info[i];
790
791 while (cleaned_count--) {
792 skb = buffer_info->skb;
793 if (skb) {
794 skb_trim(skb, 0);
795 goto check_page;
796 }
797
c2fed996 798 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 799 if (unlikely(!skb)) {
800 /* Better luck next round */
801 adapter->alloc_rx_buff_failed++;
802 break;
803 }
804
97ac8cae
BA		 805 buffer_info->skb = skb;
806check_page:
807 /* allocate a new page if necessary */
808 if (!buffer_info->page) {
c2fed996 809 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 810 if (unlikely(!buffer_info->page)) {
811 adapter->alloc_rx_buff_failed++;
812 break;
813 }
814 }
815
816 if (!buffer_info->dma)
0be3f55f 817 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 818 buffer_info->page, 0,
819 PAGE_SIZE,
0be3f55f 820 DMA_FROM_DEVICE);
97ac8cae 821
5f450212
BA		 822 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
823 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 824
825 if (unlikely(++i == rx_ring->count))
826 i = 0;
827 buffer_info = &rx_ring->buffer_info[i];
828 }
829
830 if (likely(rx_ring->next_to_use != i)) {
831 rx_ring->next_to_use = i;
832 if (unlikely(i-- == 0))
833 i = (rx_ring->count - 1);
834
835 /* Force memory writes to complete before letting h/w
836 * know there are new descriptors to fetch. (Only
837 * applicable for weak-ordered memory model archs,
838 * such as IA-64). */
839 wmb();
c6e7f51e 840 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 841 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 842 else
c5083cf6 843 writel(i, rx_ring->tail);
97ac8cae
BA		 844 }
845}
846
70495a50
BA		 847static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
848 struct sk_buff *skb)
849{
850 if (netdev->features & NETIF_F_RXHASH)
851 skb->rxhash = le32_to_cpu(rss);
852}
853
bc7f75fa 854/**
55aa6985
BA		 855 * e1000_clean_rx_irq - Send received data up the network stack
856 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 857 *
858 * the return value indicates whether actual cleaning was done, there
859 * is no guarantee that everything was cleaned
860 **/
55aa6985
BA		 861static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
862 int work_to_do)
bc7f75fa 863{
55aa6985 864 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 865 struct net_device *netdev = adapter->netdev;
866 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 867 struct e1000_hw *hw = &adapter->hw;
5f450212 868 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 869 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 870 u32 length, staterr;
bc7f75fa
AK		 871 unsigned int i;
872 int cleaned_count = 0;
3db1cd5c 873 bool cleaned = false;
bc7f75fa
AK		 874 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
875
876 i = rx_ring->next_to_clean;
5f450212
BA		 877 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
878 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 879 buffer_info = &rx_ring->buffer_info[i];
880
5f450212 881 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 882 struct sk_buff *skb;
bc7f75fa
AK		 883
884 if (*work_done >= work_to_do)
885 break;
886 (*work_done)++;
2d0bb1c1 887 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 888
bc7f75fa
AK		 889 skb = buffer_info->skb;
890 buffer_info->skb = NULL;
891
892 prefetch(skb->data - NET_IP_ALIGN);
893
894 i++;
895 if (i == rx_ring->count)
896 i = 0;
5f450212 897 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 898 prefetch(next_rxd);
899
900 next_buffer = &rx_ring->buffer_info[i];
901
3db1cd5c 902 cleaned = true;
bc7f75fa 903 cleaned_count++;
0be3f55f 904 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 905 buffer_info->dma,
906 adapter->rx_buffer_len,
0be3f55f 907 DMA_FROM_DEVICE);
bc7f75fa
AK		 908 buffer_info->dma = 0;
909
5f450212 910 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 911
b94b5028
JB		 912 /*
913 * !EOP means multiple descriptors were used to store a single
914 * packet, if that's the case we need to toss it. In fact, we
915 * need to toss every packet with the EOP bit clear and the
916 * next frame that _does_ have the EOP bit set, as it is by
917 * definition only a frame fragment
918 */
5f450212 919 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 920 adapter->flags2 |= FLAG2_IS_DISCARDING;
921
922 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 923 /* All receives must fit into a single buffer */
3bb99fe2 924 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 925 /* recycle */
926 buffer_info->skb = skb;
5f450212 927 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 928 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 929 goto next_desc;
930 }
931
5f450212 932 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
bc7f75fa
AK		 933 /* recycle */
934 buffer_info->skb = skb;
935 goto next_desc;
936 }
937
eb7c3adb
JK		 938 /* adjust length to remove Ethernet CRC */
939 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
940 length -= 4;
941
bc7f75fa
AK		 942 total_rx_bytes += length;
943 total_rx_packets++;
944
ad68076e
BA		 945 /*
946 * code added for copybreak, this should improve
bc7f75fa 947 * performance for small packets with large amounts
ad68076e
BA		 948 * of reassembly being done in the stack
949 */
bc7f75fa
AK		 950 if (length < copybreak) {
951 struct sk_buff *new_skb =
89d71a66 952 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 953 if (new_skb) {
808ff676
BA		 954 skb_copy_to_linear_data_offset(new_skb,
955 -NET_IP_ALIGN,
956 (skb->data -
957 NET_IP_ALIGN),
958 (length +
959 NET_IP_ALIGN));
bc7f75fa
AK		 960 /* save the skb in buffer_info as good */
961 buffer_info->skb = skb;
962 skb = new_skb;
963 }
964 /* else just continue with the old one */
965 }
966 /* end copybreak code */
967 skb_put(skb, length);
968
969 /* Receive Checksum Offload */
5f450212 970 e1000_rx_checksum(adapter, staterr,
afd12939 971 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 972
70495a50
BA		 973 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
974
5f450212
BA		 975 e1000_receive_skb(adapter, netdev, skb, staterr,
976 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 977
978next_desc:
5f450212 979 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 980
981 /* return some buffers to hardware, one at a time is too slow */
982 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 983 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 984 GFP_ATOMIC);
bc7f75fa
AK		 985 cleaned_count = 0;
986 }
987
988 /* use prefetched values */
989 rx_desc = next_rxd;
990 buffer_info = next_buffer;
5f450212
BA		 991
992 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 993 }
994 rx_ring->next_to_clean = i;
995
996 cleaned_count = e1000_desc_unused(rx_ring);
997 if (cleaned_count)
55aa6985 998 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 999
bc7f75fa 1000 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1001 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1002 return cleaned;
1003}
1004
55aa6985
BA		 1005static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1006 struct e1000_buffer *buffer_info)
bc7f75fa 1007{
55aa6985
BA		 1008 struct e1000_adapter *adapter = tx_ring->adapter;
1009
03b1320d
AD		 1010 if (buffer_info->dma) {
1011 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1012 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1013 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1014 else
0be3f55f
NN		 1015 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1016 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1017 buffer_info->dma = 0;
1018 }
bc7f75fa
AK		 1019 if (buffer_info->skb) {
1020 dev_kfree_skb_any(buffer_info->skb);
1021 buffer_info->skb = NULL;
1022 }
1b7719c4 1023 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1024}
1025
41cec6f1 1026static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1027{
41cec6f1
BA		 1028 struct e1000_adapter *adapter = container_of(work,
1029 struct e1000_adapter,
1030 print_hang_task);
09357b00 1031 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1032 struct e1000_ring *tx_ring = adapter->tx_ring;
1033 unsigned int i = tx_ring->next_to_clean;
1034 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1035 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1036 struct e1000_hw *hw = &adapter->hw;
1037 u16 phy_status, phy_1000t_status, phy_ext_status;
1038 u16 pci_status;
1039
615b32af
JB		 1040 if (test_bit(__E1000_DOWN, &adapter->state))
1041 return;
1042
09357b00
JK		 1043 if (!adapter->tx_hang_recheck &&
1044 (adapter->flags2 & FLAG2_DMA_BURST)) {
1045 /* May be block on write-back, flush and detect again
1046 * flush pending descriptor writebacks to memory
1047 */
1048 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1049 /* execute the writes immediately */
1050 e1e_flush();
1051 adapter->tx_hang_recheck = true;
1052 return;
1053 }
1054 /* Real hang detected */
1055 adapter->tx_hang_recheck = false;
1056 netif_stop_queue(netdev);
1057
41cec6f1
BA		 1058 e1e_rphy(hw, PHY_STATUS, &phy_status);
1059 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1060 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1061
41cec6f1
BA		 1062 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1063
1064 /* detected Hardware unit hang */
1065 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1066 " TDH <%x>\n"
1067 " TDT <%x>\n"
1068 " next_to_use <%x>\n"
1069 " next_to_clean <%x>\n"
1070 "buffer_info[next_to_clean]:\n"
1071 " time_stamp <%lx>\n"
1072 " next_to_watch <%x>\n"
1073 " jiffies <%lx>\n"
41cec6f1
BA		 1074 " next_to_watch.status <%x>\n"
1075 "MAC Status <%x>\n"
1076 "PHY Status <%x>\n"
1077 "PHY 1000BASE-T Status <%x>\n"
1078 "PHY Extended Status <%x>\n"
1079 "PCI Status <%x>\n",
c5083cf6
BA		 1080 readl(tx_ring->head),
1081 readl(tx_ring->tail),
44defeb3
JK		 1082 tx_ring->next_to_use,
1083 tx_ring->next_to_clean,
1084 tx_ring->buffer_info[eop].time_stamp,
1085 eop,
1086 jiffies,
41cec6f1
BA		 1087 eop_desc->upper.fields.status,
1088 er32(STATUS),
1089 phy_status,
1090 phy_1000t_status,
1091 phy_ext_status,
1092 pci_status);
bc7f75fa
AK		 1093}
1094
1095/**
1096 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1097 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1098 *
1099 * the return value indicates whether actual cleaning was done, there
1100 * is no guarantee that everything was cleaned
1101 **/
55aa6985 1102static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1103{
55aa6985 1104 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1105 struct net_device *netdev = adapter->netdev;
1106 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1107 struct e1000_tx_desc *tx_desc, *eop_desc;
1108 struct e1000_buffer *buffer_info;
1109 unsigned int i, eop;
1110 unsigned int count = 0;
bc7f75fa 1111 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1112 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1113
1114 i = tx_ring->next_to_clean;
1115 eop = tx_ring->buffer_info[i].next_to_watch;
1116 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1117
12d04a3c
AD		 1118 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1119 (count < tx_ring->count)) {
a86043c2 1120 bool cleaned = false;
2d0bb1c1 1121 rmb(); /* read buffer_info after eop_desc */
a86043c2 1122 for (; !cleaned; count++) {
bc7f75fa
AK		 1123 tx_desc = E1000_TX_DESC(*tx_ring, i);
1124 buffer_info = &tx_ring->buffer_info[i];
1125 cleaned = (i == eop);
1126
1127 if (cleaned) {
9ed318d5
TH		 1128 total_tx_packets += buffer_info->segs;
1129 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1130 if (buffer_info->skb) {
1131 bytes_compl += buffer_info->skb->len;
1132 pkts_compl++;
1133 }
bc7f75fa
AK		 1134 }
1135
55aa6985 1136 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1137 tx_desc->upper.data = 0;
1138
1139 i++;
1140 if (i == tx_ring->count)
1141 i = 0;
1142 }
1143
dac87619
TL		 1144 if (i == tx_ring->next_to_use)
1145 break;
bc7f75fa
AK		 1146 eop = tx_ring->buffer_info[i].next_to_watch;
1147 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1148 }
1149
1150 tx_ring->next_to_clean = i;
1151
3f0cfa3b
TH		 1152 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1153
bc7f75fa 1154#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1155 if (count && netif_carrier_ok(netdev) &&
1156 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1157 /* Make sure that anybody stopping the queue after this
1158 * sees the new next_to_clean.
1159 */
1160 smp_mb();
1161
1162 if (netif_queue_stopped(netdev) &&
1163 !(test_bit(__E1000_DOWN, &adapter->state))) {
1164 netif_wake_queue(netdev);
1165 ++adapter->restart_queue;
1166 }
1167 }
1168
1169 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1170 /*
1171 * Detect a transmit hang in hardware, this serializes the
1172 * check with the clearing of time_stamp and movement of i
1173 */
3db1cd5c 1174 adapter->detect_tx_hung = false;
12d04a3c
AD		 1175 if (tx_ring->buffer_info[i].time_stamp &&
1176 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1177 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1178 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1179 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1180 else
1181 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1182 }
1183 adapter->total_tx_bytes += total_tx_bytes;
1184 adapter->total_tx_packets += total_tx_packets;
807540ba 1185 return count < tx_ring->count;
bc7f75fa
AK		 1186}
1187
bc7f75fa
AK		 1188/**
1189 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1190 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1191 *
1192 * the return value indicates whether actual cleaning was done, there
1193 * is no guarantee that everything was cleaned
1194 **/
55aa6985
BA		 1195static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1196 int work_to_do)
bc7f75fa 1197{
55aa6985 1198 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1199 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1200 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1201 struct net_device *netdev = adapter->netdev;
1202 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1203 struct e1000_buffer *buffer_info, *next_buffer;
1204 struct e1000_ps_page *ps_page;
1205 struct sk_buff *skb;
1206 unsigned int i, j;
1207 u32 length, staterr;
1208 int cleaned_count = 0;
3db1cd5c 1209 bool cleaned = false;
bc7f75fa
AK		 1210 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1211
1212 i = rx_ring->next_to_clean;
1213 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1214 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1215 buffer_info = &rx_ring->buffer_info[i];
1216
1217 while (staterr & E1000_RXD_STAT_DD) {
1218 if (*work_done >= work_to_do)
1219 break;
1220 (*work_done)++;
1221 skb = buffer_info->skb;
2d0bb1c1 1222 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1223
1224 /* in the packet split case this is header only */
1225 prefetch(skb->data - NET_IP_ALIGN);
1226
1227 i++;
1228 if (i == rx_ring->count)
1229 i = 0;
1230 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1231 prefetch(next_rxd);
1232
1233 next_buffer = &rx_ring->buffer_info[i];
1234
3db1cd5c 1235 cleaned = true;
bc7f75fa 1236 cleaned_count++;
0be3f55f 1237 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1238 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1239 buffer_info->dma = 0;
1240
af667a29 1241 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1242 if (!(staterr & E1000_RXD_STAT_EOP))
1243 adapter->flags2 |= FLAG2_IS_DISCARDING;
1244
1245 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1246 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1247 dev_kfree_skb_irq(skb);
b94b5028
JB		 1248 if (staterr & E1000_RXD_STAT_EOP)
1249 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1250 goto next_desc;
1251 }
1252
1253 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
1254 dev_kfree_skb_irq(skb);
1255 goto next_desc;
1256 }
1257
1258 length = le16_to_cpu(rx_desc->wb.middle.length0);
1259
1260 if (!length) {
ef456f85 1261 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1262 dev_kfree_skb_irq(skb);
1263 goto next_desc;
1264 }
1265
1266 /* Good Receive */
1267 skb_put(skb, length);
1268
1269 {
ad68076e
BA		 1270 /*
1271 * this looks ugly, but it seems compiler issues make it
1272 * more efficient than reusing j
1273 */
bc7f75fa
AK		 1274 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1275
ad68076e
BA		 1276 /*
1277 * page alloc/put takes too long and effects small packet
1278 * throughput, so unsplit small packets and save the alloc/put
1279 * only valid in softirq (napi) context to call kmap_*
1280 */
bc7f75fa
AK		 1281 if (l1 && (l1 <= copybreak) &&
1282 ((length + l1) <= adapter->rx_ps_bsize0)) {
1283 u8 *vaddr;
1284
47f44e40 1285 ps_page = &buffer_info->ps_pages[0];
bc7f75fa 1286
ad68076e
BA		 1287 /*
1288 * there is no documentation about how to call
bc7f75fa 1289 * kmap_atomic, so we can't hold the mapping
ad68076e
BA		 1290 * very long
1291 */
0be3f55f
NN		 1292 dma_sync_single_for_cpu(&pdev->dev, ps_page->dma,
1293 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa
AK		 1294 vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
1295 memcpy(skb_tail_pointer(skb), vaddr, l1);
1296 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
0be3f55f
NN		 1297 dma_sync_single_for_device(&pdev->dev, ps_page->dma,
1298 PAGE_SIZE, DMA_FROM_DEVICE);
140a7480 1299
eb7c3adb
JK		 1300 /* remove the CRC */
1301 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1302 l1 -= 4;
1303
bc7f75fa
AK		 1304 skb_put(skb, l1);
1305 goto copydone;
1306 } /* if */
1307 }
1308
1309 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1310 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1311 if (!length)
1312 break;
1313
47f44e40 1314 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1315 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1316 DMA_FROM_DEVICE);
bc7f75fa
AK		 1317 ps_page->dma = 0;
1318 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1319 ps_page->page = NULL;
1320 skb->len += length;
1321 skb->data_len += length;
98a045d7 1322 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1323 }
1324
eb7c3adb
JK		 1325 /* strip the ethernet crc, problem is we're using pages now so
1326 * this whole operation can get a little cpu intensive
1327 */
1328 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1329 pskb_trim(skb, skb->len - 4);
1330
bc7f75fa
AK		 1331copydone:
1332 total_rx_bytes += skb->len;
1333 total_rx_packets++;
1334
afd12939
BA		 1335 e1000_rx_checksum(adapter, staterr,
1336 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1337
70495a50
BA		 1338 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1339
bc7f75fa
AK		 1340 if (rx_desc->wb.upper.header_status &
1341 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1342 adapter->rx_hdr_split++;
1343
1344 e1000_receive_skb(adapter, netdev, skb,
1345 staterr, rx_desc->wb.middle.vlan);
1346
1347next_desc:
1348 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1349 buffer_info->skb = NULL;
1350
1351 /* return some buffers to hardware, one at a time is too slow */
1352 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1353 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1354 GFP_ATOMIC);
bc7f75fa
AK		 1355 cleaned_count = 0;
1356 }
1357
1358 /* use prefetched values */
1359 rx_desc = next_rxd;
1360 buffer_info = next_buffer;
1361
1362 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1363 }
1364 rx_ring->next_to_clean = i;
1365
1366 cleaned_count = e1000_desc_unused(rx_ring);
1367 if (cleaned_count)
55aa6985 1368 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1369
bc7f75fa 1370 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1371 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1372 return cleaned;
1373}
1374
97ac8cae
BA		 1375/**
1376 * e1000_consume_page - helper function
1377 **/
1378static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1379 u16 length)
1380{
1381 bi->page = NULL;
1382 skb->len += length;
1383 skb->data_len += length;
98a045d7 1384 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1385}
1386
1387/**
1388 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1389 * @adapter: board private structure
1390 *
1391 * the return value indicates whether actual cleaning was done, there
1392 * is no guarantee that everything was cleaned
1393 **/
55aa6985
BA		 1394static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1395 int work_to_do)
97ac8cae 1396{
55aa6985 1397 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1398 struct net_device *netdev = adapter->netdev;
1399 struct pci_dev *pdev = adapter->pdev;
5f450212 1400 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1401 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1402 u32 length, staterr;
97ac8cae
BA		 1403 unsigned int i;
1404 int cleaned_count = 0;
1405 bool cleaned = false;
1406 unsigned int total_rx_bytes=0, total_rx_packets=0;
1407
1408 i = rx_ring->next_to_clean;
5f450212
BA		 1409 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1410 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1411 buffer_info = &rx_ring->buffer_info[i];
1412
5f450212 1413 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1414 struct sk_buff *skb;
97ac8cae
BA		 1415
1416 if (*work_done >= work_to_do)
1417 break;
1418 (*work_done)++;
2d0bb1c1 1419 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1420
97ac8cae
BA		 1421 skb = buffer_info->skb;
1422 buffer_info->skb = NULL;
1423
1424 ++i;
1425 if (i == rx_ring->count)
1426 i = 0;
5f450212 1427 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1428 prefetch(next_rxd);
1429
1430 next_buffer = &rx_ring->buffer_info[i];
1431
1432 cleaned = true;
1433 cleaned_count++;
0be3f55f
NN		 1434 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1435 DMA_FROM_DEVICE);
97ac8cae
BA		 1436 buffer_info->dma = 0;
1437
5f450212 1438 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1439
1440 /* errors is only valid for DD + EOP descriptors */
5f450212
BA		 1441 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1442 (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK))) {
1443 /* recycle both page and skb */
1444 buffer_info->skb = skb;
1445 /* an error means any chain goes out the window too */
1446 if (rx_ring->rx_skb_top)
1447 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1448 rx_ring->rx_skb_top = NULL;
1449 goto next_desc;
97ac8cae
BA		 1450 }
1451
f0f1a172 1452#define rxtop (rx_ring->rx_skb_top)
5f450212 1453 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1454 /* this descriptor is only the beginning (or middle) */
1455 if (!rxtop) {
1456 /* this is the beginning of a chain */
1457 rxtop = skb;
1458 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1459 0, length);
1460 } else {
1461 /* this is the middle of a chain */
1462 skb_fill_page_desc(rxtop,
1463 skb_shinfo(rxtop)->nr_frags,
1464 buffer_info->page, 0, length);
1465 /* re-use the skb, only consumed the page */
1466 buffer_info->skb = skb;
1467 }
1468 e1000_consume_page(buffer_info, rxtop, length);
1469 goto next_desc;
1470 } else {
1471 if (rxtop) {
1472 /* end of the chain */
1473 skb_fill_page_desc(rxtop,
1474 skb_shinfo(rxtop)->nr_frags,
1475 buffer_info->page, 0, length);
1476 /* re-use the current skb, we only consumed the
1477 * page */
1478 buffer_info->skb = skb;
1479 skb = rxtop;
1480 rxtop = NULL;
1481 e1000_consume_page(buffer_info, skb, length);
1482 } else {
1483 /* no chain, got EOP, this buf is the packet
1484 * copybreak to save the put_page/alloc_page */
1485 if (length <= copybreak &&
1486 skb_tailroom(skb) >= length) {
1487 u8 *vaddr;
1488 vaddr = kmap_atomic(buffer_info->page,
1489 KM_SKB_DATA_SOFTIRQ);
1490 memcpy(skb_tail_pointer(skb), vaddr,
1491 length);
1492 kunmap_atomic(vaddr,
1493 KM_SKB_DATA_SOFTIRQ);
1494 /* re-use the page, so don't erase
1495 * buffer_info->page */
1496 skb_put(skb, length);
1497 } else {
1498 skb_fill_page_desc(skb, 0,
1499 buffer_info->page, 0,
1500 length);
1501 e1000_consume_page(buffer_info, skb,
1502 length);
1503 }
1504 }
1505 }
1506
1507 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1508 e1000_rx_checksum(adapter, staterr,
afd12939 1509 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1510
70495a50
BA		 1511 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1512
97ac8cae
BA		 1513 /* probably a little skewed due to removing CRC */
1514 total_rx_bytes += skb->len;
1515 total_rx_packets++;
1516
1517 /* eth type trans needs skb->data to point to something */
1518 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1519 e_err("pskb_may_pull failed.\n");
ef5ab89c 1520 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1521 goto next_desc;
1522 }
1523
5f450212
BA		 1524 e1000_receive_skb(adapter, netdev, skb, staterr,
1525 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1526
1527next_desc:
5f450212 1528 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1529
1530 /* return some buffers to hardware, one at a time is too slow */
1531 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1532 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1533 GFP_ATOMIC);
97ac8cae
BA		 1534 cleaned_count = 0;
1535 }
1536
1537 /* use prefetched values */
1538 rx_desc = next_rxd;
1539 buffer_info = next_buffer;
5f450212
BA		 1540
1541 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1542 }
1543 rx_ring->next_to_clean = i;
1544
1545 cleaned_count = e1000_desc_unused(rx_ring);
1546 if (cleaned_count)
55aa6985 1547 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1548
1549 adapter->total_rx_bytes += total_rx_bytes;
1550 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1551 return cleaned;
1552}
1553
bc7f75fa
AK		 1554/**
1555 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1556 * @rx_ring: Rx descriptor ring
bc7f75fa 1557 **/
55aa6985 1558static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1559{
55aa6985 1560 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1561 struct e1000_buffer *buffer_info;
1562 struct e1000_ps_page *ps_page;
1563 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1564 unsigned int i, j;
1565
1566 /* Free all the Rx ring sk_buffs */
1567 for (i = 0; i < rx_ring->count; i++) {
1568 buffer_info = &rx_ring->buffer_info[i];
1569 if (buffer_info->dma) {
1570 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1571 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1572 adapter->rx_buffer_len,
0be3f55f 1573 DMA_FROM_DEVICE);
97ac8cae 1574 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1575 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1576 PAGE_SIZE,
0be3f55f 1577 DMA_FROM_DEVICE);
bc7f75fa 1578 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1579 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1580 adapter->rx_ps_bsize0,
0be3f55f 1581 DMA_FROM_DEVICE);
bc7f75fa
AK		 1582 buffer_info->dma = 0;
1583 }
1584
97ac8cae
BA		 1585 if (buffer_info->page) {
1586 put_page(buffer_info->page);
1587 buffer_info->page = NULL;
1588 }
1589
bc7f75fa
AK		 1590 if (buffer_info->skb) {
1591 dev_kfree_skb(buffer_info->skb);
1592 buffer_info->skb = NULL;
1593 }
1594
1595 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1596 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1597 if (!ps_page->page)
1598 break;
0be3f55f
NN		 1599 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1600 DMA_FROM_DEVICE);
bc7f75fa
AK		 1601 ps_page->dma = 0;
1602 put_page(ps_page->page);
1603 ps_page->page = NULL;
1604 }
1605 }
1606
1607 /* there also may be some cached data from a chained receive */
1608 if (rx_ring->rx_skb_top) {
1609 dev_kfree_skb(rx_ring->rx_skb_top);
1610 rx_ring->rx_skb_top = NULL;
1611 }
1612
bc7f75fa
AK		 1613 /* Zero out the descriptor ring */
1614 memset(rx_ring->desc, 0, rx_ring->size);
1615
1616 rx_ring->next_to_clean = 0;
1617 rx_ring->next_to_use = 0;
b94b5028 1618 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1619
c5083cf6
BA		 1620 writel(0, rx_ring->head);
1621 writel(0, rx_ring->tail);
bc7f75fa
AK		 1622}
1623
a8f88ff5
JB		 1624static void e1000e_downshift_workaround(struct work_struct *work)
1625{
1626 struct e1000_adapter *adapter = container_of(work,
1627 struct e1000_adapter, downshift_task);
1628
615b32af
JB		 1629 if (test_bit(__E1000_DOWN, &adapter->state))
1630 return;
1631
a8f88ff5
JB		 1632 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1633}
1634
bc7f75fa
AK		 1635/**
1636 * e1000_intr_msi - Interrupt Handler
1637 * @irq: interrupt number
1638 * @data: pointer to a network interface device structure
1639 **/
1640static irqreturn_t e1000_intr_msi(int irq, void *data)
1641{
1642 struct net_device *netdev = data;
1643 struct e1000_adapter *adapter = netdev_priv(netdev);
1644 struct e1000_hw *hw = &adapter->hw;
1645 u32 icr = er32(ICR);
1646
ad68076e
BA		 1647 /*
1648 * read ICR disables interrupts using IAM
1649 */
bc7f75fa 1650
573cca8c 1651 if (icr & E1000_ICR_LSC) {
bc7f75fa 1652 hw->mac.get_link_status = 1;
ad68076e
BA		 1653 /*
1654 * ICH8 workaround-- Call gig speed drop workaround on cable
1655 * disconnect (LSC) before accessing any PHY registers
1656 */
bc7f75fa
AK		 1657 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1658 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1659 schedule_work(&adapter->downshift_task);
bc7f75fa 1660
ad68076e
BA		 1661 /*
1662 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1663 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1664 * adapter in watchdog
1665 */
bc7f75fa
AK		 1666 if (netif_carrier_ok(netdev) &&
1667 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1668 /* disable receives */
1669 u32 rctl = er32(RCTL);
1670 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1671 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1672 }
1673 /* guard against interrupt when we're going down */
1674 if (!test_bit(__E1000_DOWN, &adapter->state))
1675 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1676 }
1677
288379f0 1678 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1679 adapter->total_tx_bytes = 0;
1680 adapter->total_tx_packets = 0;
1681 adapter->total_rx_bytes = 0;
1682 adapter->total_rx_packets = 0;
288379f0 1683 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1684 }
1685
1686 return IRQ_HANDLED;
1687}
1688
1689/**
1690 * e1000_intr - Interrupt Handler
1691 * @irq: interrupt number
1692 * @data: pointer to a network interface device structure
1693 **/
1694static irqreturn_t e1000_intr(int irq, void *data)
1695{
1696 struct net_device *netdev = data;
1697 struct e1000_adapter *adapter = netdev_priv(netdev);
1698 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1699 u32 rctl, icr = er32(ICR);
4662e82b 1700
a68ea775 1701 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1702 return IRQ_NONE; /* Not our interrupt */
1703
ad68076e
BA		 1704 /*
1705 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1706 * not set, then the adapter didn't send an interrupt
1707 */
bc7f75fa
AK		 1708 if (!(icr & E1000_ICR_INT_ASSERTED))
1709 return IRQ_NONE;
1710
ad68076e
BA		 1711 /*
1712 * Interrupt Auto-Mask...upon reading ICR,
1713 * interrupts are masked. No need for the
1714 * IMC write
1715 */
bc7f75fa 1716
573cca8c 1717 if (icr & E1000_ICR_LSC) {
bc7f75fa 1718 hw->mac.get_link_status = 1;
ad68076e
BA		 1719 /*
1720 * ICH8 workaround-- Call gig speed drop workaround on cable
1721 * disconnect (LSC) before accessing any PHY registers
1722 */
bc7f75fa
AK		 1723 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1724 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1725 schedule_work(&adapter->downshift_task);
bc7f75fa 1726
ad68076e
BA		 1727 /*
1728 * 80003ES2LAN workaround--
bc7f75fa
AK		 1729 * For packet buffer work-around on link down event;
1730 * disable receives here in the ISR and
1731 * reset adapter in watchdog
1732 */
1733 if (netif_carrier_ok(netdev) &&
1734 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1735 /* disable receives */
1736 rctl = er32(RCTL);
1737 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1738 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1739 }
1740 /* guard against interrupt when we're going down */
1741 if (!test_bit(__E1000_DOWN, &adapter->state))
1742 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1743 }
1744
288379f0 1745 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1746 adapter->total_tx_bytes = 0;
1747 adapter->total_tx_packets = 0;
1748 adapter->total_rx_bytes = 0;
1749 adapter->total_rx_packets = 0;
288379f0 1750 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1751 }
1752
1753 return IRQ_HANDLED;
1754}
1755
4662e82b
BA		 1756static irqreturn_t e1000_msix_other(int irq, void *data)
1757{
1758 struct net_device *netdev = data;
1759 struct e1000_adapter *adapter = netdev_priv(netdev);
1760 struct e1000_hw *hw = &adapter->hw;
1761 u32 icr = er32(ICR);
1762
1763 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1764 if (!test_bit(__E1000_DOWN, &adapter->state))
1765 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1766 return IRQ_NONE;
1767 }
1768
1769 if (icr & adapter->eiac_mask)
1770 ew32(ICS, (icr & adapter->eiac_mask));
1771
1772 if (icr & E1000_ICR_OTHER) {
1773 if (!(icr & E1000_ICR_LSC))
1774 goto no_link_interrupt;
1775 hw->mac.get_link_status = 1;
1776 /* guard against interrupt when we're going down */
1777 if (!test_bit(__E1000_DOWN, &adapter->state))
1778 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1779 }
1780
1781no_link_interrupt:
a3c69fef
JB		 1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1784
1785 return IRQ_HANDLED;
1786}
1787
1788
1789static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1790{
1791 struct net_device *netdev = data;
1792 struct e1000_adapter *adapter = netdev_priv(netdev);
1793 struct e1000_hw *hw = &adapter->hw;
1794 struct e1000_ring *tx_ring = adapter->tx_ring;
1795
1796
1797 adapter->total_tx_bytes = 0;
1798 adapter->total_tx_packets = 0;
1799
55aa6985 1800 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1801 /* Ring was not completely cleaned, so fire another interrupt */
1802 ew32(ICS, tx_ring->ims_val);
1803
1804 return IRQ_HANDLED;
1805}
1806
1807static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1808{
1809 struct net_device *netdev = data;
1810 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1811 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1812
1813 /* Write the ITR value calculated at the end of the
1814 * previous interrupt.
1815 */
55aa6985
BA		 1816 if (rx_ring->set_itr) {
1817 writel(1000000000 / (rx_ring->itr_val * 256),
1818 rx_ring->itr_register);
1819 rx_ring->set_itr = 0;
4662e82b
BA		 1820 }
1821
288379f0 1822 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1823 adapter->total_rx_bytes = 0;
1824 adapter->total_rx_packets = 0;
288379f0 1825 __napi_schedule(&adapter->napi);
4662e82b
BA		 1826 }
1827 return IRQ_HANDLED;
1828}
1829
1830/**
1831 * e1000_configure_msix - Configure MSI-X hardware
1832 *
1833 * e1000_configure_msix sets up the hardware to properly
1834 * generate MSI-X interrupts.
1835 **/
1836static void e1000_configure_msix(struct e1000_adapter *adapter)
1837{
1838 struct e1000_hw *hw = &adapter->hw;
1839 struct e1000_ring *rx_ring = adapter->rx_ring;
1840 struct e1000_ring *tx_ring = adapter->tx_ring;
1841 int vector = 0;
1842 u32 ctrl_ext, ivar = 0;
1843
1844 adapter->eiac_mask = 0;
1845
1846 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1847 if (hw->mac.type == e1000_82574) {
1848 u32 rfctl = er32(RFCTL);
1849 rfctl |= E1000_RFCTL_ACK_DIS;
1850 ew32(RFCTL, rfctl);
1851 }
1852
1853#define E1000_IVAR_INT_ALLOC_VALID 0x8
1854 /* Configure Rx vector */
1855 rx_ring->ims_val = E1000_IMS_RXQ0;
1856 adapter->eiac_mask |= rx_ring->ims_val;
1857 if (rx_ring->itr_val)
1858 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1859 rx_ring->itr_register);
4662e82b 1860 else
c5083cf6 1861 writel(1, rx_ring->itr_register);
4662e82b
BA		 1862 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1863
1864 /* Configure Tx vector */
1865 tx_ring->ims_val = E1000_IMS_TXQ0;
1866 vector++;
1867 if (tx_ring->itr_val)
1868 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1869 tx_ring->itr_register);
4662e82b 1870 else
c5083cf6 1871 writel(1, tx_ring->itr_register);
4662e82b
BA		 1872 adapter->eiac_mask |= tx_ring->ims_val;
1873 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1874
1875 /* set vector for Other Causes, e.g. link changes */
1876 vector++;
1877 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1878 if (rx_ring->itr_val)
1879 writel(1000000000 / (rx_ring->itr_val * 256),
1880 hw->hw_addr + E1000_EITR_82574(vector));
1881 else
1882 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1883
1884 /* Cause Tx interrupts on every write back */
1885 ivar |= (1 << 31);
1886
1887 ew32(IVAR, ivar);
1888
1889 /* enable MSI-X PBA support */
1890 ctrl_ext = er32(CTRL_EXT);
1891 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1892
1893 /* Auto-Mask Other interrupts upon ICR read */
1894#define E1000_EIAC_MASK_82574 0x01F00000
1895 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1896 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1897 ew32(CTRL_EXT, ctrl_ext);
1898 e1e_flush();
1899}
1900
1901void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1902{
1903 if (adapter->msix_entries) {
1904 pci_disable_msix(adapter->pdev);
1905 kfree(adapter->msix_entries);
1906 adapter->msix_entries = NULL;
1907 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1908 pci_disable_msi(adapter->pdev);
1909 adapter->flags &= ~FLAG_MSI_ENABLED;
1910 }
4662e82b
BA		 1911}
1912
1913/**
1914 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1915 *
1916 * Attempt to configure interrupts using the best available
1917 * capabilities of the hardware and kernel.
1918 **/
1919void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1920{
1921 int err;
8e86acd7 1922 int i;
4662e82b
BA		 1923
1924 switch (adapter->int_mode) {
1925 case E1000E_INT_MODE_MSIX:
1926 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1927 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1928 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1929 sizeof(struct msix_entry),
1930 GFP_KERNEL);
1931 if (adapter->msix_entries) {
8e86acd7 1932 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1933 adapter->msix_entries[i].entry = i;
1934
1935 err = pci_enable_msix(adapter->pdev,
1936 adapter->msix_entries,
8e86acd7 1937 adapter->num_vectors);
b1cdfead 1938 if (err == 0)
4662e82b
BA		 1939 return;
1940 }
1941 /* MSI-X failed, so fall through and try MSI */
ef456f85 1942 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1943 e1000e_reset_interrupt_capability(adapter);
1944 }
1945 adapter->int_mode = E1000E_INT_MODE_MSI;
1946 /* Fall through */
1947 case E1000E_INT_MODE_MSI:
1948 if (!pci_enable_msi(adapter->pdev)) {
1949 adapter->flags |= FLAG_MSI_ENABLED;
1950 } else {
1951 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1952 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1953 }
1954 /* Fall through */
1955 case E1000E_INT_MODE_LEGACY:
1956 /* Don't do anything; this is the system default */
1957 break;
1958 }
8e86acd7
JK		 1959
1960 /* store the number of vectors being used */
1961 adapter->num_vectors = 1;
4662e82b
BA		 1962}
1963
1964/**
1965 * e1000_request_msix - Initialize MSI-X interrupts
1966 *
1967 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1968 * kernel.
1969 **/
1970static int e1000_request_msix(struct e1000_adapter *adapter)
1971{
1972 struct net_device *netdev = adapter->netdev;
1973 int err = 0, vector = 0;
1974
1975 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1976 snprintf(adapter->rx_ring->name,
1977 sizeof(adapter->rx_ring->name) - 1,
1978 "%s-rx-0", netdev->name);
4662e82b
BA		 1979 else
1980 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1981 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1982 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1983 netdev);
1984 if (err)
1985 goto out;
c5083cf6
BA		 1986 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
1987 E1000_EITR_82574(vector);
4662e82b
BA		 1988 adapter->rx_ring->itr_val = adapter->itr;
1989 vector++;
1990
1991 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1992 snprintf(adapter->tx_ring->name,
1993 sizeof(adapter->tx_ring->name) - 1,
1994 "%s-tx-0", netdev->name);
4662e82b
BA		 1995 else
1996 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1997 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1998 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1999 netdev);
2000 if (err)
2001 goto out;
c5083cf6
BA		 2002 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2003 E1000_EITR_82574(vector);
4662e82b
BA		 2004 adapter->tx_ring->itr_val = adapter->itr;
2005 vector++;
2006
2007 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2008 e1000_msix_other, 0, netdev->name, netdev);
4662e82b
BA		 2009 if (err)
2010 goto out;
2011
2012 e1000_configure_msix(adapter);
2013 return 0;
2014out:
2015 return err;
2016}
2017
f8d59f78
BA		 2018/**
2019 * e1000_request_irq - initialize interrupts
2020 *
2021 * Attempts to configure interrupts using the best available
2022 * capabilities of the hardware and kernel.
2023 **/
bc7f75fa
AK		 2024static int e1000_request_irq(struct e1000_adapter *adapter)
2025{
2026 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2027 int err;
2028
4662e82b
BA		 2029 if (adapter->msix_entries) {
2030 err = e1000_request_msix(adapter);
2031 if (!err)
2032 return err;
2033 /* fall back to MSI */
2034 e1000e_reset_interrupt_capability(adapter);
2035 adapter->int_mode = E1000E_INT_MODE_MSI;
2036 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2037 }
4662e82b 2038 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2039 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2040 netdev->name, netdev);
2041 if (!err)
2042 return err;
bc7f75fa 2043
4662e82b
BA		 2044 /* fall back to legacy interrupt */
2045 e1000e_reset_interrupt_capability(adapter);
2046 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2047 }
2048
a0607fd3 2049 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2050 netdev->name, netdev);
2051 if (err)
2052 e_err("Unable to allocate interrupt, Error: %d\n", err);
2053
bc7f75fa
AK		 2054 return err;
2055}
2056
2057static void e1000_free_irq(struct e1000_adapter *adapter)
2058{
2059 struct net_device *netdev = adapter->netdev;
2060
4662e82b
BA		 2061 if (adapter->msix_entries) {
2062 int vector = 0;
2063
2064 free_irq(adapter->msix_entries[vector].vector, netdev);
2065 vector++;
2066
2067 free_irq(adapter->msix_entries[vector].vector, netdev);
2068 vector++;
2069
2070 /* Other Causes interrupt vector */
2071 free_irq(adapter->msix_entries[vector].vector, netdev);
2072 return;
bc7f75fa 2073 }
4662e82b
BA		 2074
2075 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2076}
2077
2078/**
2079 * e1000_irq_disable - Mask off interrupt generation on the NIC
2080 **/
2081static void e1000_irq_disable(struct e1000_adapter *adapter)
2082{
2083 struct e1000_hw *hw = &adapter->hw;
2084
bc7f75fa 2085 ew32(IMC, ~0);
4662e82b
BA		 2086 if (adapter->msix_entries)
2087 ew32(EIAC_82574, 0);
bc7f75fa 2088 e1e_flush();
8e86acd7
JK		 2089
2090 if (adapter->msix_entries) {
2091 int i;
2092 for (i = 0; i < adapter->num_vectors; i++)
2093 synchronize_irq(adapter->msix_entries[i].vector);
2094 } else {
2095 synchronize_irq(adapter->pdev->irq);
2096 }
bc7f75fa
AK		 2097}
2098
2099/**
2100 * e1000_irq_enable - Enable default interrupt generation settings
2101 **/
2102static void e1000_irq_enable(struct e1000_adapter *adapter)
2103{
2104 struct e1000_hw *hw = &adapter->hw;
2105
4662e82b
BA		 2106 if (adapter->msix_entries) {
2107 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2108 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2109 } else {
2110 ew32(IMS, IMS_ENABLE_MASK);
2111 }
74ef9c39 2112 e1e_flush();
bc7f75fa
AK		 2113}
2114
2115/**
31dbe5b4 2116 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2117 * @adapter: address of board private structure
2118 *
31dbe5b4 2119 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2120 * For ASF and Pass Through versions of f/w this means that
2121 * the driver is loaded. For AMT version (only with 82573)
2122 * of the f/w this means that the network i/f is open.
2123 **/
31dbe5b4 2124void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2125{
2126 struct e1000_hw *hw = &adapter->hw;
2127 u32 ctrl_ext;
2128 u32 swsm;
2129
2130 /* Let firmware know the driver has taken over */
2131 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2132 swsm = er32(SWSM);
2133 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2134 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2135 ctrl_ext = er32(CTRL_EXT);
ad68076e 2136 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2137 }
2138}
2139
2140/**
31dbe5b4 2141 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2142 * @adapter: address of board private structure
2143 *
31dbe5b4 2144 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2145 * For ASF and Pass Through versions of f/w this means that the
2146 * driver is no longer loaded. For AMT version (only with 82573) i
2147 * of the f/w this means that the network i/f is closed.
2148 *
2149 **/
31dbe5b4 2150void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2151{
2152 struct e1000_hw *hw = &adapter->hw;
2153 u32 ctrl_ext;
2154 u32 swsm;
2155
2156 /* Let firmware taken over control of h/w */
2157 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2158 swsm = er32(SWSM);
2159 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2160 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2161 ctrl_ext = er32(CTRL_EXT);
ad68076e 2162 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2163 }
2164}
2165
bc7f75fa
AK		 2166/**
2167 * @e1000_alloc_ring - allocate memory for a ring structure
2168 **/
2169static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2170 struct e1000_ring *ring)
2171{
2172 struct pci_dev *pdev = adapter->pdev;
2173
2174 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2175 GFP_KERNEL);
2176 if (!ring->desc)
2177 return -ENOMEM;
2178
2179 return 0;
2180}
2181
2182/**
2183 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2184 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2185 *
2186 * Return 0 on success, negative on failure
2187 **/
55aa6985 2188int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2189{
55aa6985 2190 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2191 int err = -ENOMEM, size;
2192
2193 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2194 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2195 if (!tx_ring->buffer_info)
2196 goto err;
bc7f75fa
AK		 2197
2198 /* round up to nearest 4K */
2199 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2200 tx_ring->size = ALIGN(tx_ring->size, 4096);
2201
2202 err = e1000_alloc_ring_dma(adapter, tx_ring);
2203 if (err)
2204 goto err;
2205
2206 tx_ring->next_to_use = 0;
2207 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2208
2209 return 0;
2210err:
2211 vfree(tx_ring->buffer_info);
44defeb3 2212 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2213 return err;
2214}
2215
2216/**
2217 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2218 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2219 *
2220 * Returns 0 on success, negative on failure
2221 **/
55aa6985 2222int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2223{
55aa6985 2224 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2225 struct e1000_buffer *buffer_info;
2226 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2227
2228 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2229 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2230 if (!rx_ring->buffer_info)
2231 goto err;
bc7f75fa 2232
47f44e40
AK		 2233 for (i = 0; i < rx_ring->count; i++) {
2234 buffer_info = &rx_ring->buffer_info[i];
2235 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2236 sizeof(struct e1000_ps_page),
2237 GFP_KERNEL);
2238 if (!buffer_info->ps_pages)
2239 goto err_pages;
2240 }
bc7f75fa
AK		 2241
2242 desc_len = sizeof(union e1000_rx_desc_packet_split);
2243
2244 /* Round up to nearest 4K */
2245 rx_ring->size = rx_ring->count * desc_len;
2246 rx_ring->size = ALIGN(rx_ring->size, 4096);
2247
2248 err = e1000_alloc_ring_dma(adapter, rx_ring);
2249 if (err)
47f44e40 2250 goto err_pages;
bc7f75fa
AK		 2251
2252 rx_ring->next_to_clean = 0;
2253 rx_ring->next_to_use = 0;
2254 rx_ring->rx_skb_top = NULL;
2255
2256 return 0;
47f44e40
AK		 2257
2258err_pages:
2259 for (i = 0; i < rx_ring->count; i++) {
2260 buffer_info = &rx_ring->buffer_info[i];
2261 kfree(buffer_info->ps_pages);
2262 }
bc7f75fa
AK		 2263err:
2264 vfree(rx_ring->buffer_info);
e9262447 2265 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2266 return err;
2267}
2268
2269/**
2270 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2271 * @tx_ring: Tx descriptor ring
bc7f75fa 2272 **/
55aa6985 2273static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2274{
55aa6985 2275 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2276 struct e1000_buffer *buffer_info;
2277 unsigned long size;
2278 unsigned int i;
2279
2280 for (i = 0; i < tx_ring->count; i++) {
2281 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2282 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2283 }
2284
3f0cfa3b 2285 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2286 size = sizeof(struct e1000_buffer) * tx_ring->count;
2287 memset(tx_ring->buffer_info, 0, size);
2288
2289 memset(tx_ring->desc, 0, tx_ring->size);
2290
2291 tx_ring->next_to_use = 0;
2292 tx_ring->next_to_clean = 0;
2293
c5083cf6
BA		 2294 writel(0, tx_ring->head);
2295 writel(0, tx_ring->tail);
bc7f75fa
AK		 2296}
2297
2298/**
2299 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2300 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2301 *
2302 * Free all transmit software resources
2303 **/
55aa6985 2304void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2305{
55aa6985 2306 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2307 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2308
55aa6985 2309 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2310
2311 vfree(tx_ring->buffer_info);
2312 tx_ring->buffer_info = NULL;
2313
2314 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2315 tx_ring->dma);
2316 tx_ring->desc = NULL;
2317}
2318
2319/**
2320 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2321 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2322 *
2323 * Free all receive software resources
2324 **/
55aa6985 2325void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2326{
55aa6985 2327 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2328 struct pci_dev *pdev = adapter->pdev;
47f44e40 2329 int i;
bc7f75fa 2330
55aa6985 2331 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2332
b1cdfead 2333 for (i = 0; i < rx_ring->count; i++)
47f44e40 2334 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2335
bc7f75fa
AK		 2336 vfree(rx_ring->buffer_info);
2337 rx_ring->buffer_info = NULL;
2338
bc7f75fa
AK		 2339 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2340 rx_ring->dma);
2341 rx_ring->desc = NULL;
2342}
2343
2344/**
2345 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2346 * @adapter: pointer to adapter
2347 * @itr_setting: current adapter->itr
2348 * @packets: the number of packets during this measurement interval
2349 * @bytes: the number of bytes during this measurement interval
2350 *
bc7f75fa
AK		 2351 * Stores a new ITR value based on packets and byte
2352 * counts during the last interrupt. The advantage of per interrupt
2353 * computation is faster updates and more accurate ITR for the current
2354 * traffic pattern. Constants in this function were computed
2355 * based on theoretical maximum wire speed and thresholds were set based
2356 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2357 * while increasing bulk throughput. This functionality is controlled
2358 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2359 **/
2360static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2361 u16 itr_setting, int packets,
2362 int bytes)
2363{
2364 unsigned int retval = itr_setting;
2365
2366 if (packets == 0)
2367 goto update_itr_done;
2368
2369 switch (itr_setting) {
2370 case lowest_latency:
2371 /* handle TSO and jumbo frames */
2372 if (bytes/packets > 8000)
2373 retval = bulk_latency;
b1cdfead 2374 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2375 retval = low_latency;
bc7f75fa
AK		 2376 break;
2377 case low_latency: /* 50 usec aka 20000 ints/s */
2378 if (bytes > 10000) {
2379 /* this if handles the TSO accounting */
b1cdfead 2380 if (bytes/packets > 8000)
bc7f75fa 2381 retval = bulk_latency;
b1cdfead 2382 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2383 retval = bulk_latency;
b1cdfead 2384 else if ((packets > 35))
bc7f75fa 2385 retval = lowest_latency;
bc7f75fa
AK		 2386 } else if (bytes/packets > 2000) {
2387 retval = bulk_latency;
2388 } else if (packets <= 2 && bytes < 512) {
2389 retval = lowest_latency;
2390 }
2391 break;
2392 case bulk_latency: /* 250 usec aka 4000 ints/s */
2393 if (bytes > 25000) {
b1cdfead 2394 if (packets > 35)
bc7f75fa 2395 retval = low_latency;
bc7f75fa
AK		 2396 } else if (bytes < 6000) {
2397 retval = low_latency;
2398 }
2399 break;
2400 }
2401
2402update_itr_done:
2403 return retval;
2404}
2405
2406static void e1000_set_itr(struct e1000_adapter *adapter)
2407{
2408 struct e1000_hw *hw = &adapter->hw;
2409 u16 current_itr;
2410 u32 new_itr = adapter->itr;
2411
2412 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2413 if (adapter->link_speed != SPEED_1000) {
2414 current_itr = 0;
2415 new_itr = 4000;
2416 goto set_itr_now;
2417 }
2418
828bac87
BA		 2419 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2420 new_itr = 0;
2421 goto set_itr_now;
2422 }
2423
bc7f75fa
AK		 2424 adapter->tx_itr = e1000_update_itr(adapter,
2425 adapter->tx_itr,
2426 adapter->total_tx_packets,
2427 adapter->total_tx_bytes);
2428 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2429 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2430 adapter->tx_itr = low_latency;
2431
2432 adapter->rx_itr = e1000_update_itr(adapter,
2433 adapter->rx_itr,
2434 adapter->total_rx_packets,
2435 adapter->total_rx_bytes);
2436 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2437 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2438 adapter->rx_itr = low_latency;
2439
2440 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2441
2442 switch (current_itr) {
2443 /* counts and packets in update_itr are dependent on these numbers */
2444 case lowest_latency:
2445 new_itr = 70000;
2446 break;
2447 case low_latency:
2448 new_itr = 20000; /* aka hwitr = ~200 */
2449 break;
2450 case bulk_latency:
2451 new_itr = 4000;
2452 break;
2453 default:
2454 break;
2455 }
2456
2457set_itr_now:
2458 if (new_itr != adapter->itr) {
ad68076e
BA		 2459 /*
2460 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2461 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2462 * increasing
2463 */
bc7f75fa
AK		 2464 new_itr = new_itr > adapter->itr ?
2465 min(adapter->itr + (new_itr >> 2), new_itr) :
2466 new_itr;
2467 adapter->itr = new_itr;
4662e82b
BA		 2468 adapter->rx_ring->itr_val = new_itr;
2469 if (adapter->msix_entries)
2470 adapter->rx_ring->set_itr = 1;
2471 else
828bac87
BA		 2472 if (new_itr)
2473 ew32(ITR, 1000000000 / (new_itr * 256));
2474 else
2475 ew32(ITR, 0);
bc7f75fa
AK		 2476 }
2477}
2478
4662e82b
BA		 2479/**
2480 * e1000_alloc_queues - Allocate memory for all rings
2481 * @adapter: board private structure to initialize
2482 **/
2483static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2484{
55aa6985
BA		 2485 int size = sizeof(struct e1000_ring);
2486
2487 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2488 if (!adapter->tx_ring)
2489 goto err;
55aa6985
BA		 2490 adapter->tx_ring->count = adapter->tx_ring_count;
2491 adapter->tx_ring->adapter = adapter;
4662e82b 2492
55aa6985 2493 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2494 if (!adapter->rx_ring)
2495 goto err;
55aa6985
BA		 2496 adapter->rx_ring->count = adapter->rx_ring_count;
2497 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2498
2499 return 0;
2500err:
2501 e_err("Unable to allocate memory for queues\n");
2502 kfree(adapter->rx_ring);
2503 kfree(adapter->tx_ring);
2504 return -ENOMEM;
2505}
2506
bc7f75fa
AK		 2507/**
2508 * e1000_clean - NAPI Rx polling callback
ad68076e 2509 * @napi: struct associated with this polling callback
489815ce 2510 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2511 **/
2512static int e1000_clean(struct napi_struct *napi, int budget)
2513{
2514 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2515 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2516 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2517 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2518
4cf1653a 2519 adapter = netdev_priv(poll_dev);
bc7f75fa 2520
4662e82b
BA		 2521 if (adapter->msix_entries &&
2522 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2523 goto clean_rx;
2524
55aa6985 2525 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
bc7f75fa 2526
4662e82b 2527clean_rx:
55aa6985 2528 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
d2c7ddd6 2529
12d04a3c 2530 if (!tx_cleaned)
d2c7ddd6 2531 work_done = budget;
bc7f75fa 2532
53e52c72
DM		 2533 /* If budget not fully consumed, exit the polling mode */
2534 if (work_done < budget) {
bc7f75fa
AK		 2535 if (adapter->itr_setting & 3)
2536 e1000_set_itr(adapter);
288379f0 2537 napi_complete(napi);
a3c69fef
JB		 2538 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2539 if (adapter->msix_entries)
2540 ew32(IMS, adapter->rx_ring->ims_val);
2541 else
2542 e1000_irq_enable(adapter);
2543 }
bc7f75fa
AK		 2544 }
2545
2546 return work_done;
2547}
2548
8e586137 2549static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2550{
2551 struct e1000_adapter *adapter = netdev_priv(netdev);
2552 struct e1000_hw *hw = &adapter->hw;
2553 u32 vfta, index;
2554
2555 /* don't update vlan cookie if already programmed */
2556 if ((adapter->hw.mng_cookie.status &
2557 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2558 (vid == adapter->mng_vlan_id))
8e586137 2559 return 0;
caaddaf8 2560
bc7f75fa 2561 /* add VID to filter table */
caaddaf8
BA		 2562 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2563 index = (vid >> 5) & 0x7F;
2564 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2565 vfta |= (1 << (vid & 0x1F));
2566 hw->mac.ops.write_vfta(hw, index, vfta);
2567 }
86d70e53
JK		 2568
2569 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2570
2571 return 0;
bc7f75fa
AK		 2572}
2573
8e586137 2574static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2575{
2576 struct e1000_adapter *adapter = netdev_priv(netdev);
2577 struct e1000_hw *hw = &adapter->hw;
2578 u32 vfta, index;
2579
bc7f75fa
AK		 2580 if ((adapter->hw.mng_cookie.status &
2581 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2582 (vid == adapter->mng_vlan_id)) {
2583 /* release control to f/w */
31dbe5b4 2584 e1000e_release_hw_control(adapter);
8e586137 2585 return 0;
bc7f75fa
AK		 2586 }
2587
2588 /* remove VID from filter table */
caaddaf8
BA		 2589 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2590 index = (vid >> 5) & 0x7F;
2591 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2592 vfta &= ~(1 << (vid & 0x1F));
2593 hw->mac.ops.write_vfta(hw, index, vfta);
2594 }
86d70e53
JK		 2595
2596 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2597
2598 return 0;
bc7f75fa
AK		 2599}
2600
86d70e53
JK		 2601/**
2602 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2603 * @adapter: board private structure to initialize
2604 **/
2605static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2606{
2607 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2608 struct e1000_hw *hw = &adapter->hw;
2609 u32 rctl;
bc7f75fa 2610
86d70e53
JK		 2611 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2612 /* disable VLAN receive filtering */
2613 rctl = er32(RCTL);
2614 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2615 ew32(RCTL, rctl);
2616
2617 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2618 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2619 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2620 }
bc7f75fa
AK		 2621 }
2622}
2623
86d70e53
JK		 2624/**
2625 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2626 * @adapter: board private structure to initialize
2627 **/
2628static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2629{
2630 struct e1000_hw *hw = &adapter->hw;
2631 u32 rctl;
2632
2633 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2634 /* enable VLAN receive filtering */
2635 rctl = er32(RCTL);
2636 rctl |= E1000_RCTL_VFE;
2637 rctl &= ~E1000_RCTL_CFIEN;
2638 ew32(RCTL, rctl);
2639 }
2640}
bc7f75fa 2641
86d70e53
JK		 2642/**
2643 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2644 * @adapter: board private structure to initialize
2645 **/
2646static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2647{
bc7f75fa 2648 struct e1000_hw *hw = &adapter->hw;
86d70e53 2649 u32 ctrl;
bc7f75fa 2650
86d70e53
JK		 2651 /* disable VLAN tag insert/strip */
2652 ctrl = er32(CTRL);
2653 ctrl &= ~E1000_CTRL_VME;
2654 ew32(CTRL, ctrl);
2655}
bc7f75fa 2656
86d70e53
JK		 2657/**
2658 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2659 * @adapter: board private structure to initialize
2660 **/
2661static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2662{
2663 struct e1000_hw *hw = &adapter->hw;
2664 u32 ctrl;
bc7f75fa 2665
86d70e53
JK		 2666 /* enable VLAN tag insert/strip */
2667 ctrl = er32(CTRL);
2668 ctrl |= E1000_CTRL_VME;
2669 ew32(CTRL, ctrl);
2670}
bc7f75fa 2671
86d70e53
JK		 2672static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2673{
2674 struct net_device *netdev = adapter->netdev;
2675 u16 vid = adapter->hw.mng_cookie.vlan_id;
2676 u16 old_vid = adapter->mng_vlan_id;
2677
2678 if (adapter->hw.mng_cookie.status &
2679 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2680 e1000_vlan_rx_add_vid(netdev, vid);
2681 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2682 }
2683
86d70e53
JK		 2684 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2685 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2686}
2687
2688static void e1000_restore_vlan(struct e1000_adapter *adapter)
2689{
2690 u16 vid;
2691
86d70e53 2692 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2693
86d70e53 2694 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2695 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2696}
2697
cd791618 2698static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2699{
2700 struct e1000_hw *hw = &adapter->hw;
cd791618 2701 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2702
2703 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2704 return;
2705
2706 manc = er32(MANC);
2707
ad68076e
BA		 2708 /*
2709 * enable receiving management packets to the host. this will probably
bc7f75fa 2710 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2711 * the packets will be handled on SMBUS
2712 */
bc7f75fa
AK		 2713 manc |= E1000_MANC_EN_MNG2HOST;
2714 manc2h = er32(MANC2H);
cd791618
BA		 2715
2716 switch (hw->mac.type) {
2717 default:
2718 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2719 break;
2720 case e1000_82574:
2721 case e1000_82583:
2722 /*
2723 * Check if IPMI pass-through decision filter already exists;
2724 * if so, enable it.
2725 */
2726 for (i = 0, j = 0; i < 8; i++) {
2727 mdef = er32(MDEF(i));
2728
2729 /* Ignore filters with anything other than IPMI ports */
3b21b508 2730 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2731 continue;
2732
2733 /* Enable this decision filter in MANC2H */
2734 if (mdef)
2735 manc2h |= (1 << i);
2736
2737 j |= mdef;
2738 }
2739
2740 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2741 break;
2742
2743 /* Create new decision filter in an empty filter */
2744 for (i = 0, j = 0; i < 8; i++)
2745 if (er32(MDEF(i)) == 0) {
2746 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2747 E1000_MDEF_PORT_664));
2748 manc2h |= (1 << 1);
2749 j++;
2750 break;
2751 }
2752
2753 if (!j)
2754 e_warn("Unable to create IPMI pass-through filter\n");
2755 break;
2756 }
2757
bc7f75fa
AK		 2758 ew32(MANC2H, manc2h);
2759 ew32(MANC, manc);
2760}
2761
2762/**
af667a29 2763 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2764 * @adapter: board private structure
2765 *
2766 * Configure the Tx unit of the MAC after a reset.
2767 **/
2768static void e1000_configure_tx(struct e1000_adapter *adapter)
2769{
2770 struct e1000_hw *hw = &adapter->hw;
2771 struct e1000_ring *tx_ring = adapter->tx_ring;
2772 u64 tdba;
c550b121 2773 u32 tdlen, tarc;
bc7f75fa
AK		 2774
2775 /* Setup the HW Tx Head and Tail descriptor pointers */
2776 tdba = tx_ring->dma;
2777 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2778 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2779 ew32(TDBAH, (tdba >> 32));
2780 ew32(TDLEN, tdlen);
2781 ew32(TDH, 0);
2782 ew32(TDT, 0);
c5083cf6
BA		 2783 tx_ring->head = adapter->hw.hw_addr + E1000_TDH;
2784 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT;
bc7f75fa 2785
bc7f75fa
AK		 2786 /* Set the Tx Interrupt Delay register */
2787 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2788 /* Tx irq moderation */
bc7f75fa
AK		 2789 ew32(TADV, adapter->tx_abs_int_delay);
2790
3a3b7586
JB		 2791 if (adapter->flags2 & FLAG2_DMA_BURST) {
2792 u32 txdctl = er32(TXDCTL(0));
2793 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2794 E1000_TXDCTL_WTHRESH);
2795 /*
2796 * set up some performance related parameters to encourage the
2797 * hardware to use the bus more efficiently in bursts, depends
2798 * on the tx_int_delay to be enabled,
2799 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2800 * hthresh = 1 ==> prefetch when one or more available
2801 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2802 * BEWARE: this seems to work but should be considered first if
af667a29 2803 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2804 */
2805 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2806 ew32(TXDCTL(0), txdctl);
3a3b7586 2807 }
56032be7
BA		 2808 /* erratum work around: set txdctl the same for both queues */
2809 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2810
bc7f75fa 2811 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2812 tarc = er32(TARC(0));
ad68076e
BA		 2813 /*
2814 * set the speed mode bit, we'll clear it if we're not at
2815 * gigabit link later
2816 */
bc7f75fa
AK		 2817#define SPEED_MODE_BIT (1 << 21)
2818 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2819 ew32(TARC(0), tarc);
bc7f75fa
AK		 2820 }
2821
2822 /* errata: program both queues to unweighted RR */
2823 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2824 tarc = er32(TARC(0));
bc7f75fa 2825 tarc |= 1;
e9ec2c0f
JK		 2826 ew32(TARC(0), tarc);
2827 tarc = er32(TARC(1));
bc7f75fa 2828 tarc |= 1;
e9ec2c0f 2829 ew32(TARC(1), tarc);
bc7f75fa
AK		 2830 }
2831
bc7f75fa
AK		 2832 /* Setup Transmit Descriptor Settings for eop descriptor */
2833 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2834
2835 /* only set IDE if we are delaying interrupts using the timers */
2836 if (adapter->tx_int_delay)
2837 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2838
2839 /* enable Report Status bit */
2840 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2841
edfea6e6 2842 e1000e_config_collision_dist(hw);
bc7f75fa
AK		 2843}
2844
2845/**
2846 * e1000_setup_rctl - configure the receive control registers
2847 * @adapter: Board private structure
2848 **/
2849#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2850 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2851static void e1000_setup_rctl(struct e1000_adapter *adapter)
2852{
2853 struct e1000_hw *hw = &adapter->hw;
2854 u32 rctl, rfctl;
bc7f75fa
AK		 2855 u32 pages = 0;
2856
a1ce6473
BA		 2857 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2858 if (hw->mac.type == e1000_pch2lan) {
2859 s32 ret_val;
2860
2861 if (adapter->netdev->mtu > ETH_DATA_LEN)
2862 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2863 else
2864 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2865
2866 if (ret_val)
2867 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2868 }
2869
bc7f75fa
AK		 2870 /* Program MC offset vector base */
2871 rctl = er32(RCTL);
2872 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2873 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2874 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2875 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2876
2877 /* Do not Store bad packets */
2878 rctl &= ~E1000_RCTL_SBP;
2879
2880 /* Enable Long Packet receive */
2881 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2882 rctl &= ~E1000_RCTL_LPE;
2883 else
2884 rctl |= E1000_RCTL_LPE;
2885
eb7c3adb
JK		 2886 /* Some systems expect that the CRC is included in SMBUS traffic. The
2887 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2888 * host memory when this is enabled
2889 */
2890 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2891 rctl |= E1000_RCTL_SECRC;
5918bd88 2892
a4f58f54
BA		 2893 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2894 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2895 u16 phy_data;
2896
2897 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2898 phy_data &= 0xfff8;
2899 phy_data |= (1 << 2);
2900 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2901
2902 e1e_rphy(hw, 22, &phy_data);
2903 phy_data &= 0x0fff;
2904 phy_data |= (1 << 14);
2905 e1e_wphy(hw, 0x10, 0x2823);
2906 e1e_wphy(hw, 0x11, 0x0003);
2907 e1e_wphy(hw, 22, phy_data);
2908 }
2909
bc7f75fa
AK		 2910 /* Setup buffer sizes */
2911 rctl &= ~E1000_RCTL_SZ_4096;
2912 rctl |= E1000_RCTL_BSEX;
2913 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2914 case 2048:
2915 default:
2916 rctl |= E1000_RCTL_SZ_2048;
2917 rctl &= ~E1000_RCTL_BSEX;
2918 break;
2919 case 4096:
2920 rctl |= E1000_RCTL_SZ_4096;
2921 break;
2922 case 8192:
2923 rctl |= E1000_RCTL_SZ_8192;
2924 break;
2925 case 16384:
2926 rctl |= E1000_RCTL_SZ_16384;
2927 break;
2928 }
2929
5f450212
BA		 2930 /* Enable Extended Status in all Receive Descriptors */
2931 rfctl = er32(RFCTL);
2932 rfctl |= E1000_RFCTL_EXTEN;
2933
bc7f75fa
AK		 2934 /*
2935 * 82571 and greater support packet-split where the protocol
2936 * header is placed in skb->data and the packet data is
2937 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2938 * In the case of a non-split, skb->data is linearly filled,
2939 * followed by the page buffers. Therefore, skb->data is
2940 * sized to hold the largest protocol header.
2941 *
2942 * allocations using alloc_page take too long for regular MTU
2943 * so only enable packet split for jumbo frames
2944 *
2945 * Using pages when the page size is greater than 16k wastes
2946 * a lot of memory, since we allocate 3 pages at all times
2947 * per packet.
2948 */
bc7f75fa 2949 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
dbcb9fec 2950 if (!(adapter->flags & FLAG_HAS_ERT) && (pages <= 3) &&
97ac8cae 2951 (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2952 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2953 else
2954 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2955
2956 if (adapter->rx_ps_pages) {
90da0669
BA		 2957 u32 psrctl = 0;
2958
ad68076e
BA		 2959 /*
2960 * disable packet split support for IPv6 extension headers,
2961 * because some malformed IPv6 headers can hang the Rx
2962 */
bc7f75fa
AK		 2963 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2964 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2965
140a7480
AK		 2966 /* Enable Packet split descriptors */
2967 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2968
2969 psrctl |= adapter->rx_ps_bsize0 >>
2970 E1000_PSRCTL_BSIZE0_SHIFT;
2971
2972 switch (adapter->rx_ps_pages) {
2973 case 3:
2974 psrctl |= PAGE_SIZE <<
2975 E1000_PSRCTL_BSIZE3_SHIFT;
2976 case 2:
2977 psrctl |= PAGE_SIZE <<
2978 E1000_PSRCTL_BSIZE2_SHIFT;
2979 case 1:
2980 psrctl |= PAGE_SIZE >>
2981 E1000_PSRCTL_BSIZE1_SHIFT;
2982 break;
2983 }
2984
2985 ew32(PSRCTL, psrctl);
2986 }
2987
5f450212 2988 ew32(RFCTL, rfctl);
bc7f75fa 2989 ew32(RCTL, rctl);
318a94d6
JK		 2990 /* just started the receive unit, no need to restart */
2991 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 2992}
2993
2994/**
2995 * e1000_configure_rx - Configure Receive Unit after Reset
2996 * @adapter: board private structure
2997 *
2998 * Configure the Rx unit of the MAC after a reset.
2999 **/
3000static void e1000_configure_rx(struct e1000_adapter *adapter)
3001{
3002 struct e1000_hw *hw = &adapter->hw;
3003 struct e1000_ring *rx_ring = adapter->rx_ring;
3004 u64 rdba;
3005 u32 rdlen, rctl, rxcsum, ctrl_ext;
3006
3007 if (adapter->rx_ps_pages) {
3008 /* this is a 32 byte descriptor */
3009 rdlen = rx_ring->count *
af667a29 3010 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3011 adapter->clean_rx = e1000_clean_rx_irq_ps;
3012 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3013 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3014 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3015 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3016 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3017 } else {
5f450212 3018 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3019 adapter->clean_rx = e1000_clean_rx_irq;
3020 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3021 }
3022
3023 /* disable receives while setting up the descriptors */
3024 rctl = er32(RCTL);
7f99ae63
BA		 3025 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3026 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3027 e1e_flush();
1bba4386 3028 usleep_range(10000, 20000);
bc7f75fa 3029
3a3b7586
JB		 3030 if (adapter->flags2 & FLAG2_DMA_BURST) {
3031 /*
3032 * set the writeback threshold (only takes effect if the RDTR
3033 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3034 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3035 * granularity = 01
3036 * wthresh = 04,
3037 * hthresh = 04,
3038 * pthresh = 0x20
3039 */
3040 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3041 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3042
3043 /*
3044 * override the delay timers for enabling bursting, only if
3045 * the value was not set by the user via module options
3046 */
3047 if (adapter->rx_int_delay == DEFAULT_RDTR)
3048 adapter->rx_int_delay = BURST_RDTR;
3049 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3050 adapter->rx_abs_int_delay = BURST_RADV;
3051 }
3052
bc7f75fa
AK		 3053 /* set the Receive Delay Timer Register */
3054 ew32(RDTR, adapter->rx_int_delay);
3055
3056 /* irq moderation */
3057 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3058 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3059 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3060
3061 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3062 /* Auto-Mask interrupts upon ICR access */
3063 ctrl_ext |= E1000_CTRL_EXT_IAME;
3064 ew32(IAM, 0xffffffff);
3065 ew32(CTRL_EXT, ctrl_ext);
3066 e1e_flush();
3067
ad68076e
BA		 3068 /*
3069 * Setup the HW Rx Head and Tail Descriptor Pointers and
3070 * the Base and Length of the Rx Descriptor Ring
3071 */
bc7f75fa 3072 rdba = rx_ring->dma;
284901a9 3073 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3074 ew32(RDBAH, (rdba >> 32));
3075 ew32(RDLEN, rdlen);
3076 ew32(RDH, 0);
3077 ew32(RDT, 0);
c5083cf6
BA		 3078 rx_ring->head = adapter->hw.hw_addr + E1000_RDH;
3079 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT;
bc7f75fa
AK		 3080
3081 /* Enable Receive Checksum Offload for TCP and UDP */
3082 rxcsum = er32(RXCSUM);
dc221294 3083 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3084 rxcsum |= E1000_RXCSUM_TUOFL;
3085
ad68076e
BA		 3086 /*
3087 * IPv4 payload checksum for UDP fragments must be
3088 * used in conjunction with packet-split.
3089 */
bc7f75fa
AK		 3090 if (adapter->rx_ps_pages)
3091 rxcsum |= E1000_RXCSUM_IPPCSE;
3092 } else {
3093 rxcsum &= ~E1000_RXCSUM_TUOFL;
3094 /* no need to clear IPPCSE as it defaults to 0 */
3095 }
3096 ew32(RXCSUM, rxcsum);
3097
ad68076e
BA		 3098 /*
3099 * Enable early receives on supported devices, only takes effect when
bc7f75fa 3100 * packet size is equal or larger than the specified value (in 8 byte
ad68076e
BA		 3101 * units), e.g. using jumbo frames when setting to E1000_ERT_2048
3102 */
828bac87
BA		 3103 if ((adapter->flags & FLAG_HAS_ERT) ||
3104 (adapter->hw.mac.type == e1000_pch2lan)) {
53ec5498
BA		 3105 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3106 u32 rxdctl = er32(RXDCTL(0));
3107 ew32(RXDCTL(0), rxdctl | 0x3);
828bac87
BA		 3108 if (adapter->flags & FLAG_HAS_ERT)
3109 ew32(ERT, E1000_ERT_2048 | (1 << 13));
53ec5498
BA		 3110 /*
3111 * With jumbo frames and early-receive enabled,
3112 * excessive C-state transition latencies result in
3113 * dropped transactions.
3114 */
af667a29 3115 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3116 } else {
af667a29
BA		 3117 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3118 PM_QOS_DEFAULT_VALUE);
53ec5498 3119 }
97ac8cae 3120 }
bc7f75fa
AK		 3121
3122 /* Enable Receives */
3123 ew32(RCTL, rctl);
3124}
3125
3126/**
ef9b965a
JB		 3127 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3128 * @netdev: network interface device structure
bc7f75fa 3129 *
ef9b965a
JB		 3130 * Writes multicast address list to the MTA hash table.
3131 * Returns: -ENOMEM on failure
3132 * 0 on no addresses written
3133 * X on writing X addresses to MTA
3134 */
3135static int e1000e_write_mc_addr_list(struct net_device *netdev)
3136{
3137 struct e1000_adapter *adapter = netdev_priv(netdev);
3138 struct e1000_hw *hw = &adapter->hw;
3139 struct netdev_hw_addr *ha;
3140 u8 *mta_list;
3141 int i;
3142
3143 if (netdev_mc_empty(netdev)) {
3144 /* nothing to program, so clear mc list */
3145 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3146 return 0;
3147 }
3148
3149 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3150 if (!mta_list)
3151 return -ENOMEM;
3152
3153 /* update_mc_addr_list expects a packed array of only addresses. */
3154 i = 0;
3155 netdev_for_each_mc_addr(ha, netdev)
3156 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3157
3158 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3159 kfree(mta_list);
3160
3161 return netdev_mc_count(netdev);
3162}
3163
3164/**
3165 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3166 * @netdev: network interface device structure
bc7f75fa 3167 *
ef9b965a
JB		 3168 * Writes unicast address list to the RAR table.
3169 * Returns: -ENOMEM on failure/insufficient address space
3170 * 0 on no addresses written
3171 * X on writing X addresses to the RAR table
bc7f75fa 3172 **/
ef9b965a 3173static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3174{
ef9b965a
JB		 3175 struct e1000_adapter *adapter = netdev_priv(netdev);
3176 struct e1000_hw *hw = &adapter->hw;
3177 unsigned int rar_entries = hw->mac.rar_entry_count;
3178 int count = 0;
3179
3180 /* save a rar entry for our hardware address */
3181 rar_entries--;
3182
3183 /* save a rar entry for the LAA workaround */
3184 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3185 rar_entries--;
3186
3187 /* return ENOMEM indicating insufficient memory for addresses */
3188 if (netdev_uc_count(netdev) > rar_entries)
3189 return -ENOMEM;
3190
3191 if (!netdev_uc_empty(netdev) && rar_entries) {
3192 struct netdev_hw_addr *ha;
3193
3194 /*
3195 * write the addresses in reverse order to avoid write
3196 * combining
3197 */
3198 netdev_for_each_uc_addr(ha, netdev) {
3199 if (!rar_entries)
3200 break;
3201 e1000e_rar_set(hw, ha->addr, rar_entries--);
3202 count++;
3203 }
3204 }
3205
3206 /* zero out the remaining RAR entries not used above */
3207 for (; rar_entries > 0; rar_entries--) {
3208 ew32(RAH(rar_entries), 0);
3209 ew32(RAL(rar_entries), 0);
3210 }
3211 e1e_flush();
3212
3213 return count;
bc7f75fa
AK		 3214}
3215
3216/**
ef9b965a 3217 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3218 * @netdev: network interface device structure
3219 *
ef9b965a
JB		 3220 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3221 * address list or the network interface flags are updated. This routine is
3222 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3223 * promiscuous mode, and all-multi behavior.
3224 **/
ef9b965a 3225static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3226{
3227 struct e1000_adapter *adapter = netdev_priv(netdev);
3228 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3229 u32 rctl;
bc7f75fa
AK		 3230
3231 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3232 rctl = er32(RCTL);
3233
ef9b965a
JB		 3234 /* clear the affected bits */
3235 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3236
bc7f75fa
AK		 3237 if (netdev->flags & IFF_PROMISC) {
3238 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3239 /* Do not hardware filter VLANs in promisc mode */
3240 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3241 } else {
ef9b965a 3242 int count;
746b9f02
PM		 3243 if (netdev->flags & IFF_ALLMULTI) {
3244 rctl |= E1000_RCTL_MPE;
746b9f02 3245 } else {
ef9b965a
JB		 3246 /*
3247 * Write addresses to the MTA, if the attempt fails
3248 * then we should just turn on promiscuous mode so
3249 * that we can at least receive multicast traffic
3250 */
3251 count = e1000e_write_mc_addr_list(netdev);
3252 if (count < 0)
3253 rctl |= E1000_RCTL_MPE;
746b9f02 3254 }
86d70e53 3255 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3256 /*
ef9b965a
JB		 3257 * Write addresses to available RAR registers, if there is not
3258 * sufficient space to store all the addresses then enable
3259 * unicast promiscuous mode
bc7f75fa 3260 */
ef9b965a
JB		 3261 count = e1000e_write_uc_addr_list(netdev);
3262 if (count < 0)
3263 rctl |= E1000_RCTL_UPE;
bc7f75fa 3264 }
86d70e53 3265
ef9b965a
JB		 3266 ew32(RCTL, rctl);
3267
86d70e53
JK		 3268 if (netdev->features & NETIF_F_HW_VLAN_RX)
3269 e1000e_vlan_strip_enable(adapter);
3270 else
3271 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3272}
3273
70495a50
BA		 3274static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3275{
3276 struct e1000_hw *hw = &adapter->hw;
3277 u32 mrqc, rxcsum;
3278 int i;
3279 static const u32 rsskey[10] = {
3280 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3281 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3282 };
3283
3284 /* Fill out hash function seed */
3285 for (i = 0; i < 10; i++)
3286 ew32(RSSRK(i), rsskey[i]);
3287
3288 /* Direct all traffic to queue 0 */
3289 for (i = 0; i < 32; i++)
3290 ew32(RETA(i), 0);
3291
3292 /*
3293 * Disable raw packet checksumming so that RSS hash is placed in
3294 * descriptor on writeback.
3295 */
3296 rxcsum = er32(RXCSUM);
3297 rxcsum |= E1000_RXCSUM_PCSD;
3298
3299 ew32(RXCSUM, rxcsum);
3300
3301 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3302 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3303 E1000_MRQC_RSS_FIELD_IPV6 |
3304 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3305 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3306
3307 ew32(MRQC, mrqc);
3308}
3309
bc7f75fa 3310/**
ad68076e 3311 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3312 * @adapter: private board structure
3313 **/
3314static void e1000_configure(struct e1000_adapter *adapter)
3315{
55aa6985
BA		 3316 struct e1000_ring *rx_ring = adapter->rx_ring;
3317
ef9b965a 3318 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3319
3320 e1000_restore_vlan(adapter);
cd791618 3321 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3322
3323 e1000_configure_tx(adapter);
70495a50
BA		 3324
3325 if (adapter->netdev->features & NETIF_F_RXHASH)
3326 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3327 e1000_setup_rctl(adapter);
3328 e1000_configure_rx(adapter);
55aa6985 3329 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3330}
3331
3332/**
3333 * e1000e_power_up_phy - restore link in case the phy was powered down
3334 * @adapter: address of board private structure
3335 *
3336 * The phy may be powered down to save power and turn off link when the
3337 * driver is unloaded and wake on lan is not enabled (among others)
3338 * *** this routine MUST be followed by a call to e1000e_reset ***
3339 **/
3340void e1000e_power_up_phy(struct e1000_adapter *adapter)
3341{
17f208de
BA		 3342 if (adapter->hw.phy.ops.power_up)
3343 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3344
3345 adapter->hw.mac.ops.setup_link(&adapter->hw);
3346}
3347
3348/**
3349 * e1000_power_down_phy - Power down the PHY
3350 *
17f208de
BA		 3351 * Power down the PHY so no link is implied when interface is down.
3352 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3353 */
3354static void e1000_power_down_phy(struct e1000_adapter *adapter)
3355{
bc7f75fa 3356 /* WoL is enabled */
23b66e2b 3357 if (adapter->wol)
bc7f75fa
AK		 3358 return;
3359
17f208de
BA		 3360 if (adapter->hw.phy.ops.power_down)
3361 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3362}
3363
3364/**
3365 * e1000e_reset - bring the hardware into a known good state
3366 *
3367 * This function boots the hardware and enables some settings that
3368 * require a configuration cycle of the hardware - those cannot be
3369 * set/changed during runtime. After reset the device needs to be
ad68076e 3370 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3371 */
3372void e1000e_reset(struct e1000_adapter *adapter)
3373{
3374 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3375 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3376 struct e1000_hw *hw = &adapter->hw;
3377 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3378 u32 pba = adapter->pba;
bc7f75fa
AK		 3379 u16 hwm;
3380
ad68076e 3381 /* reset Packet Buffer Allocation to default */
318a94d6 3382 ew32(PBA, pba);
df762464 3383
318a94d6 3384 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3385 /*
3386 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3387 * large enough to accommodate two full transmit packets,
3388 * rounded up to the next 1KB and expressed in KB. Likewise,
3389 * the Rx FIFO should be large enough to accommodate at least
3390 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3391 * expressed in KB.
3392 */
df762464 3393 pba = er32(PBA);
bc7f75fa 3394 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3395 tx_space = pba >> 16;
bc7f75fa 3396 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3397 pba &= 0xffff;
ad68076e 3398 /*
af667a29 3399 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3400 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3401 */
3402 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3403 sizeof(struct e1000_tx_desc) -
3404 ETH_FCS_LEN) * 2;
3405 min_tx_space = ALIGN(min_tx_space, 1024);
3406 min_tx_space >>= 10;
3407 /* software strips receive CRC, so leave room for it */
318a94d6 3408 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3409 min_rx_space = ALIGN(min_rx_space, 1024);
3410 min_rx_space >>= 10;
3411
ad68076e
BA		 3412 /*
3413 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3414 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3415 * allocation, take space away from current Rx allocation
3416 */
df762464
AK		 3417 if ((tx_space < min_tx_space) &&
3418 ((min_tx_space - tx_space) < pba)) {
3419 pba -= min_tx_space - tx_space;
bc7f75fa 3420
ad68076e 3421 /*
af667a29 3422 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3423 * adjustment or use Early Receive if available
3424 */
df762464 3425 if ((pba < min_rx_space) &&
bc7f75fa
AK		 3426 (!(adapter->flags & FLAG_HAS_ERT)))
3427 /* ERT enabled in e1000_configure_rx */
df762464 3428 pba = min_rx_space;
bc7f75fa 3429 }
df762464
AK		 3430
3431 ew32(PBA, pba);
bc7f75fa
AK		 3432 }
3433
ad68076e
BA		 3434 /*
3435 * flow control settings
3436 *
38eb394e 3437 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3438 * (or the size used for early receive) above it in the Rx FIFO.
3439 * Set it to the lower of:
3440 * - 90% of the Rx FIFO size, and
3441 * - the full Rx FIFO size minus the early receive size (for parts
3442 * with ERT support assuming ERT set to E1000_ERT_2048), or
38eb394e 3443 * - the full Rx FIFO size minus one full frame
ad68076e 3444 */
d3738bb8
BA		 3445 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3446 fc->pause_time = 0xFFFF;
3447 else
3448 fc->pause_time = E1000_FC_PAUSE_TIME;
3449 fc->send_xon = 1;
3450 fc->current_mode = fc->requested_mode;
3451
3452 switch (hw->mac.type) {
3453 default:
3454 if ((adapter->flags & FLAG_HAS_ERT) &&
3455 (adapter->netdev->mtu > ETH_DATA_LEN))
3456 hwm = min(((pba << 10) * 9 / 10),
3457 ((pba << 10) - (E1000_ERT_2048 << 3)));
3458 else
3459 hwm = min(((pba << 10) * 9 / 10),
3460 ((pba << 10) - adapter->max_frame_size));
3461
3462 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3463 fc->low_water = fc->high_water - 8;
3464 break;
3465 case e1000_pchlan:
38eb394e
BA		 3466 /*
3467 * Workaround PCH LOM adapter hangs with certain network
3468 * loads. If hangs persist, try disabling Tx flow control.
3469 */
3470 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3471 fc->high_water = 0x3500;
3472 fc->low_water = 0x1500;
3473 } else {
3474 fc->high_water = 0x5000;
3475 fc->low_water = 0x3000;
3476 }
a305595b 3477 fc->refresh_time = 0x1000;
d3738bb8
BA		 3478 break;
3479 case e1000_pch2lan:
3480 fc->high_water = 0x05C20;
3481 fc->low_water = 0x05048;
3482 fc->pause_time = 0x0650;
3483 fc->refresh_time = 0x0400;
828bac87
BA		 3484 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3485 pba = 14;
3486 ew32(PBA, pba);
3487 }
d3738bb8 3488 break;
38eb394e 3489 }
bc7f75fa 3490
828bac87
BA		 3491 /*
3492 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3493 * fit in receive buffer and early-receive not supported.
3494 */
3495 if (adapter->itr_setting & 0x3) {
3496 if (((adapter->max_frame_size * 2) > (pba << 10)) &&
3497 !(adapter->flags & FLAG_HAS_ERT)) {
3498 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3499 dev_info(&adapter->pdev->dev,
3500 "Interrupt Throttle Rate turned off\n");
3501 adapter->flags2 |= FLAG2_DISABLE_AIM;
3502 ew32(ITR, 0);
3503 }
3504 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3505 dev_info(&adapter->pdev->dev,
3506 "Interrupt Throttle Rate turned on\n");
3507 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3508 adapter->itr = 20000;
3509 ew32(ITR, 1000000000 / (adapter->itr * 256));
3510 }
3511 }
3512
bc7f75fa
AK		 3513 /* Allow time for pending master requests to run */
3514 mac->ops.reset_hw(hw);
97ac8cae
BA		 3515
3516 /*
3517 * For parts with AMT enabled, let the firmware know
3518 * that the network interface is in control
3519 */
c43bc57e 3520 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3521 e1000e_get_hw_control(adapter);
97ac8cae 3522
bc7f75fa
AK		 3523 ew32(WUC, 0);
3524
3525 if (mac->ops.init_hw(hw))
44defeb3 3526 e_err("Hardware Error\n");
bc7f75fa
AK		 3527
3528 e1000_update_mng_vlan(adapter);
3529
3530 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3531 ew32(VET, ETH_P_8021Q);
3532
3533 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3534
3535 if (!netif_running(adapter->netdev) &&
3536 !test_bit(__E1000_TESTING, &adapter->state)) {
3537 e1000_power_down_phy(adapter);
3538 return;
3539 }
3540
bc7f75fa
AK		 3541 e1000_get_phy_info(hw);
3542
918d7197
BA		 3543 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3544 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3545 u16 phy_data = 0;
ad68076e
BA		 3546 /*
3547 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3548 * the return value of this function because there is nothing
ad68076e
BA		 3549 * different we would do if it failed
3550 */
bc7f75fa
AK		 3551 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3552 phy_data &= ~IGP02E1000_PM_SPD;
3553 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3554 }
bc7f75fa
AK		 3555}
3556
3557int e1000e_up(struct e1000_adapter *adapter)
3558{
3559 struct e1000_hw *hw = &adapter->hw;
3560
3561 /* hardware has been reset, we need to reload some things */
3562 e1000_configure(adapter);
3563
3564 clear_bit(__E1000_DOWN, &adapter->state);
3565
4662e82b
BA		 3566 if (adapter->msix_entries)
3567 e1000_configure_msix(adapter);
bc7f75fa
AK		 3568 e1000_irq_enable(adapter);
3569
400484fa 3570 netif_start_queue(adapter->netdev);
4cb9be7a 3571
bc7f75fa 3572 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3573 if (adapter->msix_entries)
3574 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3575 else
3576 ew32(ICS, E1000_ICS_LSC);
3577
bc7f75fa
AK		 3578 return 0;
3579}
3580
713b3c9e
JB		 3581static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3582{
3583 struct e1000_hw *hw = &adapter->hw;
3584
3585 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3586 return;
3587
3588 /* flush pending descriptor writebacks to memory */
3589 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3590 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3591
3592 /* execute the writes immediately */
3593 e1e_flush();
3594}
3595
67fd4fcb
JK		 3596static void e1000e_update_stats(struct e1000_adapter *adapter);
3597
bc7f75fa
AK		 3598void e1000e_down(struct e1000_adapter *adapter)
3599{
3600 struct net_device *netdev = adapter->netdev;
3601 struct e1000_hw *hw = &adapter->hw;
3602 u32 tctl, rctl;
3603
ad68076e
BA		 3604 /*
3605 * signal that we're down so the interrupt handler does not
3606 * reschedule our watchdog timer
3607 */
bc7f75fa
AK		 3608 set_bit(__E1000_DOWN, &adapter->state);
3609
3610 /* disable receives in the hardware */
3611 rctl = er32(RCTL);
7f99ae63
BA		 3612 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3613 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3614 /* flush and sleep below */
3615
4cb9be7a 3616 netif_stop_queue(netdev);
bc7f75fa
AK		 3617
3618 /* disable transmits in the hardware */
3619 tctl = er32(TCTL);
3620 tctl &= ~E1000_TCTL_EN;
3621 ew32(TCTL, tctl);
7f99ae63 3622
bc7f75fa
AK		 3623 /* flush both disables and wait for them to finish */
3624 e1e_flush();
1bba4386 3625 usleep_range(10000, 20000);
bc7f75fa 3626
bc7f75fa
AK		 3627 e1000_irq_disable(adapter);
3628
3629 del_timer_sync(&adapter->watchdog_timer);
3630 del_timer_sync(&adapter->phy_info_timer);
3631
bc7f75fa 3632 netif_carrier_off(netdev);
67fd4fcb
JK		 3633
3634 spin_lock(&adapter->stats64_lock);
3635 e1000e_update_stats(adapter);
3636 spin_unlock(&adapter->stats64_lock);
3637
400484fa 3638 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3639 e1000_clean_tx_ring(adapter->tx_ring);
3640 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3641
bc7f75fa
AK		 3642 adapter->link_speed = 0;
3643 adapter->link_duplex = 0;
3644
52cc3086
JK		 3645 if (!pci_channel_offline(adapter->pdev))
3646 e1000e_reset(adapter);
713b3c9e 3647
bc7f75fa
AK		 3648 /*
3649 * TODO: for power management, we could drop the link and
3650 * pci_disable_device here.
3651 */
3652}
3653
3654void e1000e_reinit_locked(struct e1000_adapter *adapter)
3655{
3656 might_sleep();
3657 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3658 usleep_range(1000, 2000);
bc7f75fa
AK		 3659 e1000e_down(adapter);
3660 e1000e_up(adapter);
3661 clear_bit(__E1000_RESETTING, &adapter->state);
3662}
3663
3664/**
3665 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3666 * @adapter: board private structure to initialize
3667 *
3668 * e1000_sw_init initializes the Adapter private data structure.
3669 * Fields are initialized based on PCI device information and
3670 * OS network device settings (MTU size).
3671 **/
3672static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3673{
bc7f75fa
AK		 3674 struct net_device *netdev = adapter->netdev;
3675
3676 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3677 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3678 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3679 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3680 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3681 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3682
67fd4fcb
JK		 3683 spin_lock_init(&adapter->stats64_lock);
3684
4662e82b 3685 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3686
4662e82b
BA		 3687 if (e1000_alloc_queues(adapter))
3688 return -ENOMEM;
bc7f75fa 3689
bc7f75fa 3690 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3691 e1000_irq_disable(adapter);
3692
bc7f75fa
AK		 3693 set_bit(__E1000_DOWN, &adapter->state);
3694 return 0;
bc7f75fa
AK		 3695}
3696
f8d59f78
BA		 3697/**
3698 * e1000_intr_msi_test - Interrupt Handler
3699 * @irq: interrupt number
3700 * @data: pointer to a network interface device structure
3701 **/
3702static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3703{
3704 struct net_device *netdev = data;
3705 struct e1000_adapter *adapter = netdev_priv(netdev);
3706 struct e1000_hw *hw = &adapter->hw;
3707 u32 icr = er32(ICR);
3708
3bb99fe2 3709 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3710 if (icr & E1000_ICR_RXSEQ) {
3711 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3712 wmb();
3713 }
3714
3715 return IRQ_HANDLED;
3716}
3717
3718/**
3719 * e1000_test_msi_interrupt - Returns 0 for successful test
3720 * @adapter: board private struct
3721 *
3722 * code flow taken from tg3.c
3723 **/
3724static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3725{
3726 struct net_device *netdev = adapter->netdev;
3727 struct e1000_hw *hw = &adapter->hw;
3728 int err;
3729
3730 /* poll_enable hasn't been called yet, so don't need disable */
3731 /* clear any pending events */
3732 er32(ICR);
3733
3734 /* free the real vector and request a test handler */
3735 e1000_free_irq(adapter);
4662e82b 3736 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3737
3738 /* Assume that the test fails, if it succeeds then the test
3739 * MSI irq handler will unset this flag */
3740 adapter->flags |= FLAG_MSI_TEST_FAILED;
3741
3742 err = pci_enable_msi(adapter->pdev);
3743 if (err)
3744 goto msi_test_failed;
3745
a0607fd3 3746 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3747 netdev->name, netdev);
3748 if (err) {
3749 pci_disable_msi(adapter->pdev);
3750 goto msi_test_failed;
3751 }
3752
3753 wmb();
3754
3755 e1000_irq_enable(adapter);
3756
3757 /* fire an unusual interrupt on the test handler */
3758 ew32(ICS, E1000_ICS_RXSEQ);
3759 e1e_flush();
3760 msleep(50);
3761
3762 e1000_irq_disable(adapter);
3763
3764 rmb();
3765
3766 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3767 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30
JD		 3768 e_info("MSI interrupt test failed, using legacy interrupt.\n");
3769 } else
3770 e_dbg("MSI interrupt test succeeded!\n");
f8d59f78
BA		 3771
3772 free_irq(adapter->pdev->irq, netdev);
3773 pci_disable_msi(adapter->pdev);
3774
f8d59f78 3775msi_test_failed:
4662e82b 3776 e1000e_set_interrupt_capability(adapter);
068e8a30 3777 return e1000_request_irq(adapter);
f8d59f78
BA		 3778}
3779
3780/**
3781 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3782 * @adapter: board private struct
3783 *
3784 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3785 **/
3786static int e1000_test_msi(struct e1000_adapter *adapter)
3787{
3788 int err;
3789 u16 pci_cmd;
3790
3791 if (!(adapter->flags & FLAG_MSI_ENABLED))
3792 return 0;
3793
3794 /* disable SERR in case the MSI write causes a master abort */
3795 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3796 if (pci_cmd & PCI_COMMAND_SERR)
3797 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3798 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3799
3800 err = e1000_test_msi_interrupt(adapter);
3801
36f2407f
DN		 3802 /* re-enable SERR */
3803 if (pci_cmd & PCI_COMMAND_SERR) {
3804 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3805 pci_cmd |= PCI_COMMAND_SERR;
3806 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3807 }
f8d59f78 3808
f8d59f78
BA		 3809 return err;
3810}
3811
bc7f75fa
AK		 3812/**
3813 * e1000_open - Called when a network interface is made active
3814 * @netdev: network interface device structure
3815 *
3816 * Returns 0 on success, negative value on failure
3817 *
3818 * The open entry point is called when a network interface is made
3819 * active by the system (IFF_UP). At this point all resources needed
3820 * for transmit and receive operations are allocated, the interrupt
3821 * handler is registered with the OS, the watchdog timer is started,
3822 * and the stack is notified that the interface is ready.
3823 **/
3824static int e1000_open(struct net_device *netdev)
3825{
3826 struct e1000_adapter *adapter = netdev_priv(netdev);
3827 struct e1000_hw *hw = &adapter->hw;
23606cf5 3828 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3829 int err;
3830
3831 /* disallow open during test */
3832 if (test_bit(__E1000_TESTING, &adapter->state))
3833 return -EBUSY;
3834
23606cf5
RW		 3835 pm_runtime_get_sync(&pdev->dev);
3836
9c563d20
JB		 3837 netif_carrier_off(netdev);
3838
bc7f75fa 3839 /* allocate transmit descriptors */
55aa6985 3840 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3841 if (err)
3842 goto err_setup_tx;
3843
3844 /* allocate receive descriptors */
55aa6985 3845 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3846 if (err)
3847 goto err_setup_rx;
3848
11b08be8
BA		 3849 /*
3850 * If AMT is enabled, let the firmware know that the network
3851 * interface is now open and reset the part to a known state.
3852 */
3853 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3854 e1000e_get_hw_control(adapter);
11b08be8
BA		 3855 e1000e_reset(adapter);
3856 }
3857
bc7f75fa
AK		 3858 e1000e_power_up_phy(adapter);
3859
3860 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3861 if ((adapter->hw.mng_cookie.status &
3862 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3863 e1000_update_mng_vlan(adapter);
3864
c128ec29 3865 /* DMA latency requirement to workaround early-receive/jumbo issue */
828bac87
BA		 3866 if ((adapter->flags & FLAG_HAS_ERT) ||
3867 (adapter->hw.mac.type == e1000_pch2lan))
6ba74014
LT		 3868 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3869 PM_QOS_CPU_DMA_LATENCY,
3870 PM_QOS_DEFAULT_VALUE);
c128ec29 3871
ad68076e
BA		 3872 /*
3873 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3874 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3875 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3876 * clean_rx handler before we do so.
3877 */
bc7f75fa
AK		 3878 e1000_configure(adapter);
3879
3880 err = e1000_request_irq(adapter);
3881 if (err)
3882 goto err_req_irq;
3883
f8d59f78
BA		 3884 /*
3885 * Work around PCIe errata with MSI interrupts causing some chipsets to
3886 * ignore e1000e MSI messages, which means we need to test our MSI
3887 * interrupt now
3888 */
4662e82b 3889 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3890 err = e1000_test_msi(adapter);
3891 if (err) {
3892 e_err("Interrupt allocation failed\n");
3893 goto err_req_irq;
3894 }
3895 }
3896
bc7f75fa
AK		 3897 /* From here on the code is the same as e1000e_up() */
3898 clear_bit(__E1000_DOWN, &adapter->state);
3899
3900 napi_enable(&adapter->napi);
3901
3902 e1000_irq_enable(adapter);
3903
09357b00 3904 adapter->tx_hang_recheck = false;
4cb9be7a 3905 netif_start_queue(netdev);
d55b53ff 3906
23606cf5
RW		 3907 adapter->idle_check = true;
3908 pm_runtime_put(&pdev->dev);
3909
bc7f75fa 3910 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3911 if (adapter->msix_entries)
3912 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3913 else
3914 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3915
3916 return 0;
3917
3918err_req_irq:
31dbe5b4 3919 e1000e_release_hw_control(adapter);
bc7f75fa 3920 e1000_power_down_phy(adapter);
55aa6985 3921 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3922err_setup_rx:
55aa6985 3923 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3924err_setup_tx:
3925 e1000e_reset(adapter);
23606cf5 3926 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3927
3928 return err;
3929}
3930
3931/**
3932 * e1000_close - Disables a network interface
3933 * @netdev: network interface device structure
3934 *
3935 * Returns 0, this is not allowed to fail
3936 *
3937 * The close entry point is called when an interface is de-activated
3938 * by the OS. The hardware is still under the drivers control, but
3939 * needs to be disabled. A global MAC reset is issued to stop the
3940 * hardware, and all transmit and receive resources are freed.
3941 **/
3942static int e1000_close(struct net_device *netdev)
3943{
3944 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3945 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3946
3947 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3948
3949 pm_runtime_get_sync(&pdev->dev);
3950
5f4a780d
BA		 3951 napi_disable(&adapter->napi);
3952
23606cf5
RW		 3953 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3954 e1000e_down(adapter);
3955 e1000_free_irq(adapter);
3956 }
bc7f75fa 3957 e1000_power_down_phy(adapter);
bc7f75fa 3958
55aa6985
BA		 3959 e1000e_free_tx_resources(adapter->tx_ring);
3960 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3961
ad68076e
BA		 3962 /*
3963 * kill manageability vlan ID if supported, but not if a vlan with
3964 * the same ID is registered on the host OS (let 8021q kill it)
3965 */
86d70e53
JK		 3966 if (adapter->hw.mng_cookie.status &
3967 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3968 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3969
ad68076e
BA		 3970 /*
3971 * If AMT is enabled, let the firmware know that the network
3972 * interface is now closed
3973 */
31dbe5b4
BA		 3974 if ((adapter->flags & FLAG_HAS_AMT) &&
3975 !test_bit(__E1000_TESTING, &adapter->state))
3976 e1000e_release_hw_control(adapter);
bc7f75fa 3977
828bac87
BA		 3978 if ((adapter->flags & FLAG_HAS_ERT) ||
3979 (adapter->hw.mac.type == e1000_pch2lan))
6ba74014 3980 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3981
23606cf5
RW		 3982 pm_runtime_put_sync(&pdev->dev);
3983
bc7f75fa
AK		 3984 return 0;
3985}
3986/**
3987 * e1000_set_mac - Change the Ethernet Address of the NIC
3988 * @netdev: network interface device structure
3989 * @p: pointer to an address structure
3990 *
3991 * Returns 0 on success, negative on failure
3992 **/
3993static int e1000_set_mac(struct net_device *netdev, void *p)
3994{
3995 struct e1000_adapter *adapter = netdev_priv(netdev);
3996 struct sockaddr *addr = p;
3997
3998 if (!is_valid_ether_addr(addr->sa_data))
3999 return -EADDRNOTAVAIL;
4000
4001 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4002 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4003
4004 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4005
4006 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4007 /* activate the work around */
4008 e1000e_set_laa_state_82571(&adapter->hw, 1);
4009
ad68076e
BA		 4010 /*
4011 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4012 * between the time RAR[0] gets clobbered and the time it
4013 * gets fixed (in e1000_watchdog), the actual LAA is in one
4014 * of the RARs and no incoming packets directed to this port
4015 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4016 * RAR[14]
4017 */
bc7f75fa
AK		 4018 e1000e_rar_set(&adapter->hw,
4019 adapter->hw.mac.addr,
4020 adapter->hw.mac.rar_entry_count - 1);
4021 }
4022
4023 return 0;
4024}
4025
a8f88ff5
JB		 4026/**
4027 * e1000e_update_phy_task - work thread to update phy
4028 * @work: pointer to our work struct
4029 *
4030 * this worker thread exists because we must acquire a
4031 * semaphore to read the phy, which we could msleep while
4032 * waiting for it, and we can't msleep in a timer.
4033 **/
4034static void e1000e_update_phy_task(struct work_struct *work)
4035{
4036 struct e1000_adapter *adapter = container_of(work,
4037 struct e1000_adapter, update_phy_task);
615b32af
JB		 4038
4039 if (test_bit(__E1000_DOWN, &adapter->state))
4040 return;
4041
a8f88ff5
JB		 4042 e1000_get_phy_info(&adapter->hw);
4043}
4044
ad68076e
BA		 4045/*
4046 * Need to wait a few seconds after link up to get diagnostic information from
4047 * the phy
4048 */
bc7f75fa
AK		 4049static void e1000_update_phy_info(unsigned long data)
4050{
4051 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4052
4053 if (test_bit(__E1000_DOWN, &adapter->state))
4054 return;
4055
a8f88ff5 4056 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4057}
4058
8c7bbb92
BA		 4059/**
4060 * e1000e_update_phy_stats - Update the PHY statistics counters
4061 * @adapter: board private structure
2b6b168d
BA		 4062 *
4063 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4064 **/
4065static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4066{
4067 struct e1000_hw *hw = &adapter->hw;
4068 s32 ret_val;
4069 u16 phy_data;
4070
4071 ret_val = hw->phy.ops.acquire(hw);
4072 if (ret_val)
4073 return;
4074
8c7bbb92
BA		 4075 /*
4076 * A page set is expensive so check if already on desired page.
4077 * If not, set to the page with the PHY status registers.
4078 */
2b6b168d 4079 hw->phy.addr = 1;
8c7bbb92
BA		 4080 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4081 &phy_data);
4082 if (ret_val)
4083 goto release;
2b6b168d
BA		 4084 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4085 ret_val = hw->phy.ops.set_page(hw,
4086 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4087 if (ret_val)
4088 goto release;
4089 }
4090
8c7bbb92 4091 /* Single Collision Count */
2b6b168d
BA		 4092 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4093 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4094 if (!ret_val)
4095 adapter->stats.scc += phy_data;
4096
4097 /* Excessive Collision Count */
2b6b168d
BA		 4098 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4099 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4100 if (!ret_val)
4101 adapter->stats.ecol += phy_data;
4102
4103 /* Multiple Collision Count */
2b6b168d
BA		 4104 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4105 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4106 if (!ret_val)
4107 adapter->stats.mcc += phy_data;
4108
4109 /* Late Collision Count */
2b6b168d
BA		 4110 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4111 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4112 if (!ret_val)
4113 adapter->stats.latecol += phy_data;
4114
4115 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4116 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4117 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4118 if (!ret_val)
4119 hw->mac.collision_delta = phy_data;
4120
4121 /* Defer Count */
2b6b168d
BA		 4122 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4123 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4124 if (!ret_val)
4125 adapter->stats.dc += phy_data;
4126
4127 /* Transmit with no CRS */
2b6b168d
BA		 4128 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4129 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4130 if (!ret_val)
4131 adapter->stats.tncrs += phy_data;
4132
4133release:
4134 hw->phy.ops.release(hw);
4135}
4136
bc7f75fa
AK		 4137/**
4138 * e1000e_update_stats - Update the board statistics counters
4139 * @adapter: board private structure
4140 **/
67fd4fcb 4141static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4142{
7274c20f 4143 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4144 struct e1000_hw *hw = &adapter->hw;
4145 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4146
4147 /*
4148 * Prevent stats update while adapter is being reset, or if the pci
4149 * connection is down.
4150 */
4151 if (adapter->link_speed == 0)
4152 return;
4153 if (pci_channel_offline(pdev))
4154 return;
4155
bc7f75fa
AK		 4156 adapter->stats.crcerrs += er32(CRCERRS);
4157 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4158 adapter->stats.gorc += er32(GORCL);
4159 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4160 adapter->stats.bprc += er32(BPRC);
4161 adapter->stats.mprc += er32(MPRC);
4162 adapter->stats.roc += er32(ROC);
4163
bc7f75fa 4164 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4165
4166 /* Half-duplex statistics */
4167 if (adapter->link_duplex == HALF_DUPLEX) {
4168 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4169 e1000e_update_phy_stats(adapter);
4170 } else {
4171 adapter->stats.scc += er32(SCC);
4172 adapter->stats.ecol += er32(ECOL);
4173 adapter->stats.mcc += er32(MCC);
4174 adapter->stats.latecol += er32(LATECOL);
4175 adapter->stats.dc += er32(DC);
4176
4177 hw->mac.collision_delta = er32(COLC);
4178
4179 if ((hw->mac.type != e1000_82574) &&
4180 (hw->mac.type != e1000_82583))
4181 adapter->stats.tncrs += er32(TNCRS);
4182 }
4183 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4184 }
8c7bbb92 4185
bc7f75fa
AK		 4186 adapter->stats.xonrxc += er32(XONRXC);
4187 adapter->stats.xontxc += er32(XONTXC);
4188 adapter->stats.xoffrxc += er32(XOFFRXC);
4189 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4190 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4191 adapter->stats.gotc += er32(GOTCL);
4192 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4193 adapter->stats.rnbc += er32(RNBC);
4194 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4195
4196 adapter->stats.mptc += er32(MPTC);
4197 adapter->stats.bptc += er32(BPTC);
4198
4199 /* used for adaptive IFS */
4200
4201 hw->mac.tx_packet_delta = er32(TPT);
4202 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4203
4204 adapter->stats.algnerrc += er32(ALGNERRC);
4205 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4206 adapter->stats.cexterr += er32(CEXTERR);
4207 adapter->stats.tsctc += er32(TSCTC);
4208 adapter->stats.tsctfc += er32(TSCTFC);
4209
bc7f75fa 4210 /* Fill out the OS statistics structure */
7274c20f
AK		 4211 netdev->stats.multicast = adapter->stats.mprc;
4212 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4213
4214 /* Rx Errors */
4215
ad68076e
BA		 4216 /*
4217 * RLEC on some newer hardware can be incorrect so build
4218 * our own version based on RUC and ROC
4219 */
7274c20f 4220 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4221 adapter->stats.crcerrs + adapter->stats.algnerrc +
4222 adapter->stats.ruc + adapter->stats.roc +
4223 adapter->stats.cexterr;
7274c20f 4224 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4225 adapter->stats.roc;
7274c20f
AK		 4226 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4227 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4228 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4229
4230 /* Tx Errors */
7274c20f 4231 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4232 adapter->stats.latecol;
7274c20f
AK		 4233 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4234 netdev->stats.tx_window_errors = adapter->stats.latecol;
4235 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4236
4237 /* Tx Dropped needs to be maintained elsewhere */
4238
bc7f75fa
AK		 4239 /* Management Stats */
4240 adapter->stats.mgptc += er32(MGTPTC);
4241 adapter->stats.mgprc += er32(MGTPRC);
4242 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4243}
4244
7c25769f
BA		 4245/**
4246 * e1000_phy_read_status - Update the PHY register status snapshot
4247 * @adapter: board private structure
4248 **/
4249static void e1000_phy_read_status(struct e1000_adapter *adapter)
4250{
4251 struct e1000_hw *hw = &adapter->hw;
4252 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4253
4254 if ((er32(STATUS) & E1000_STATUS_LU) &&
4255 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4256 int ret_val;
4257
7c25769f
BA		 4258 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4259 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4260 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4261 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4262 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4263 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4264 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4265 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4266 if (ret_val)
44defeb3 4267 e_warn("Error reading PHY register\n");
7c25769f
BA		 4268 } else {
4269 /*
4270 * Do not read PHY registers if link is not up
4271 * Set values to typical power-on defaults
4272 */
4273 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4274 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4275 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4276 BMSR_ERCAP);
4277 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4278 ADVERTISE_ALL | ADVERTISE_CSMA);
4279 phy->lpa = 0;
4280 phy->expansion = EXPANSION_ENABLENPAGE;
4281 phy->ctrl1000 = ADVERTISE_1000FULL;
4282 phy->stat1000 = 0;
4283 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4284 }
7c25769f
BA		 4285}
4286
bc7f75fa
AK		 4287static void e1000_print_link_info(struct e1000_adapter *adapter)
4288{
bc7f75fa
AK		 4289 struct e1000_hw *hw = &adapter->hw;
4290 u32 ctrl = er32(CTRL);
4291
8f12fe86 4292 /* Link status message must follow this format for user tools */
ef456f85
JK		 4293 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4294 adapter->netdev->name,
4295 adapter->link_speed,
4296 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4297 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4298 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4299 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4300}
4301
0c6bdb30 4302static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4303{
4304 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4305 bool link_active = false;
318a94d6
JK		 4306 s32 ret_val = 0;
4307
4308 /*
4309 * get_link_status is set on LSC (link status) interrupt or
4310 * Rx sequence error interrupt. get_link_status will stay
4311 * false until the check_for_link establishes link
4312 * for copper adapters ONLY
4313 */
4314 switch (hw->phy.media_type) {
4315 case e1000_media_type_copper:
4316 if (hw->mac.get_link_status) {
4317 ret_val = hw->mac.ops.check_for_link(hw);
4318 link_active = !hw->mac.get_link_status;
4319 } else {
3db1cd5c 4320 link_active = true;
318a94d6
JK		 4321 }
4322 break;
4323 case e1000_media_type_fiber:
4324 ret_val = hw->mac.ops.check_for_link(hw);
4325 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4326 break;
4327 case e1000_media_type_internal_serdes:
4328 ret_val = hw->mac.ops.check_for_link(hw);
4329 link_active = adapter->hw.mac.serdes_has_link;
4330 break;
4331 default:
4332 case e1000_media_type_unknown:
4333 break;
4334 }
4335
4336 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4337 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4338 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4339 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4340 }
4341
4342 return link_active;
4343}
4344
4345static void e1000e_enable_receives(struct e1000_adapter *adapter)
4346{
4347 /* make sure the receive unit is started */
4348 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4349 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4350 struct e1000_hw *hw = &adapter->hw;
4351 u32 rctl = er32(RCTL);
4352 ew32(RCTL, rctl | E1000_RCTL_EN);
4353 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4354 }
4355}
4356
ff10e13c
CW		 4357static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4358{
4359 struct e1000_hw *hw = &adapter->hw;
4360
4361 /*
4362 * With 82574 controllers, PHY needs to be checked periodically
4363 * for hung state and reset, if two calls return true
4364 */
4365 if (e1000_check_phy_82574(hw))
4366 adapter->phy_hang_count++;
4367 else
4368 adapter->phy_hang_count = 0;
4369
4370 if (adapter->phy_hang_count > 1) {
4371 adapter->phy_hang_count = 0;
4372 schedule_work(&adapter->reset_task);
4373 }
4374}
4375
bc7f75fa
AK		 4376/**
4377 * e1000_watchdog - Timer Call-back
4378 * @data: pointer to adapter cast into an unsigned long
4379 **/
4380static void e1000_watchdog(unsigned long data)
4381{
4382 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4383
4384 /* Do the rest outside of interrupt context */
4385 schedule_work(&adapter->watchdog_task);
4386
4387 /* TODO: make this use queue_delayed_work() */
4388}
4389
4390static void e1000_watchdog_task(struct work_struct *work)
4391{
4392 struct e1000_adapter *adapter = container_of(work,
4393 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4394 struct net_device *netdev = adapter->netdev;
4395 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4396 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4397 struct e1000_ring *tx_ring = adapter->tx_ring;
4398 struct e1000_hw *hw = &adapter->hw;
4399 u32 link, tctl;
bc7f75fa 4400
615b32af
JB		 4401 if (test_bit(__E1000_DOWN, &adapter->state))
4402 return;
4403
b405e8df 4404 link = e1000e_has_link(adapter);
318a94d6 4405 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4406 /* Cancel scheduled suspend requests. */
4407 pm_runtime_resume(netdev->dev.parent);
4408
318a94d6 4409 e1000e_enable_receives(adapter);
bc7f75fa 4410 goto link_up;
bc7f75fa
AK		 4411 }
4412
4413 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4414 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4415 e1000_update_mng_vlan(adapter);
4416
bc7f75fa
AK		 4417 if (link) {
4418 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4419 bool txb2b = true;
23606cf5
RW		 4420
4421 /* Cancel scheduled suspend requests. */
4422 pm_runtime_resume(netdev->dev.parent);
4423
318a94d6 4424 /* update snapshot of PHY registers on LSC */
7c25769f 4425 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4426 mac->ops.get_link_up_info(&adapter->hw,
4427 &adapter->link_speed,
4428 &adapter->link_duplex);
4429 e1000_print_link_info(adapter);
f4187b56
BA		 4430 /*
4431 * On supported PHYs, check for duplex mismatch only
4432 * if link has autonegotiated at 10/100 half
4433 */
4434 if ((hw->phy.type == e1000_phy_igp_3 ||
4435 hw->phy.type == e1000_phy_bm) &&
4436 (hw->mac.autoneg == true) &&
4437 (adapter->link_speed == SPEED_10 ||
4438 adapter->link_speed == SPEED_100) &&
4439 (adapter->link_duplex == HALF_DUPLEX)) {
4440 u16 autoneg_exp;
4441
4442 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4443
4444 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4445 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4446 }
4447
f49c57e1 4448 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4449 adapter->tx_timeout_factor = 1;
4450 switch (adapter->link_speed) {
4451 case SPEED_10:
3db1cd5c 4452 txb2b = false;
10f1b492 4453 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4454 break;
4455 case SPEED_100:
3db1cd5c 4456 txb2b = false;
4c86e0b9 4457 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4458 break;
4459 }
4460
ad68076e
BA		 4461 /*
4462 * workaround: re-program speed mode bit after
4463 * link-up event
4464 */
bc7f75fa
AK		 4465 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4466 !txb2b) {
4467 u32 tarc0;
e9ec2c0f 4468 tarc0 = er32(TARC(0));
bc7f75fa 4469 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4470 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4471 }
4472
ad68076e
BA		 4473 /*
4474 * disable TSO for pcie and 10/100 speeds, to avoid
4475 * some hardware issues
4476 */
bc7f75fa
AK		 4477 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4478 switch (adapter->link_speed) {
4479 case SPEED_10:
4480 case SPEED_100:
44defeb3 4481 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4482 netdev->features &= ~NETIF_F_TSO;
4483 netdev->features &= ~NETIF_F_TSO6;
4484 break;
4485 case SPEED_1000:
4486 netdev->features |= NETIF_F_TSO;
4487 netdev->features |= NETIF_F_TSO6;
4488 break;
4489 default:
4490 /* oops */
4491 break;
4492 }
4493 }
4494
ad68076e
BA		 4495 /*
4496 * enable transmits in the hardware, need to do this
4497 * after setting TARC(0)
4498 */
bc7f75fa
AK		 4499 tctl = er32(TCTL);
4500 tctl |= E1000_TCTL_EN;
4501 ew32(TCTL, tctl);
4502
75eb0fad
BA		 4503 /*
4504 * Perform any post-link-up configuration before
4505 * reporting link up.
4506 */
4507 if (phy->ops.cfg_on_link_up)
4508 phy->ops.cfg_on_link_up(hw);
4509
bc7f75fa 4510 netif_carrier_on(netdev);
bc7f75fa
AK		 4511
4512 if (!test_bit(__E1000_DOWN, &adapter->state))
4513 mod_timer(&adapter->phy_info_timer,
4514 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4515 }
4516 } else {
4517 if (netif_carrier_ok(netdev)) {
4518 adapter->link_speed = 0;
4519 adapter->link_duplex = 0;
8f12fe86
BA		 4520 /* Link status message must follow this format */
4521 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4522 adapter->netdev->name);
bc7f75fa 4523 netif_carrier_off(netdev);
bc7f75fa
AK		 4524 if (!test_bit(__E1000_DOWN, &adapter->state))
4525 mod_timer(&adapter->phy_info_timer,
4526 round_jiffies(jiffies + 2 * HZ));
4527
4528 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4529 schedule_work(&adapter->reset_task);
23606cf5
RW		 4530 else
4531 pm_schedule_suspend(netdev->dev.parent,
4532 LINK_TIMEOUT);
bc7f75fa
AK		 4533 }
4534 }
4535
4536link_up:
67fd4fcb 4537 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4538 e1000e_update_stats(adapter);
4539
4540 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4541 adapter->tpt_old = adapter->stats.tpt;
4542 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4543 adapter->colc_old = adapter->stats.colc;
4544
7c25769f
BA		 4545 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4546 adapter->gorc_old = adapter->stats.gorc;
4547 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4548 adapter->gotc_old = adapter->stats.gotc;
2084b114 4549 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4550
4551 e1000e_update_adaptive(&adapter->hw);
4552
90da0669
BA		 4553 if (!netif_carrier_ok(netdev) &&
4554 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4555 /*
4556 * We've lost link, so the controller stops DMA,
4557 * but we've got queued Tx work that's never going
4558 * to get done, so reset controller to flush Tx.
4559 * (Do the reset outside of interrupt context).
4560 */
90da0669
BA		 4561 schedule_work(&adapter->reset_task);
4562 /* return immediately since reset is imminent */
4563 return;
bc7f75fa
AK		 4564 }
4565
eab2abf5
JB		 4566 /* Simple mode for Interrupt Throttle Rate (ITR) */
4567 if (adapter->itr_setting == 4) {
4568 /*
4569 * Symmetric Tx/Rx gets a reduced ITR=2000;
4570 * Total asymmetrical Tx or Rx gets ITR=8000;
4571 * everyone else is between 2000-8000.
4572 */
4573 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4574 u32 dif = (adapter->gotc > adapter->gorc ?
4575 adapter->gotc - adapter->gorc :
4576 adapter->gorc - adapter->gotc) / 10000;
4577 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4578
4579 ew32(ITR, 1000000000 / (itr * 256));
4580 }
4581
ad68076e 4582 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4583 if (adapter->msix_entries)
4584 ew32(ICS, adapter->rx_ring->ims_val);
4585 else
4586 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4587
713b3c9e
JB		 4588 /* flush pending descriptors to memory before detecting Tx hang */
4589 e1000e_flush_descriptors(adapter);
4590
bc7f75fa 4591 /* Force detection of hung controller every watchdog period */
3db1cd5c 4592 adapter->detect_tx_hung = true;
bc7f75fa 4593
ad68076e
BA		 4594 /*
4595 * With 82571 controllers, LAA may be overwritten due to controller
4596 * reset from the other port. Set the appropriate LAA in RAR[0]
4597 */
bc7f75fa
AK		 4598 if (e1000e_get_laa_state_82571(hw))
4599 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4600
ff10e13c
CW		 4601 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4602 e1000e_check_82574_phy_workaround(adapter);
4603
bc7f75fa
AK		 4604 /* Reset the timer */
4605 if (!test_bit(__E1000_DOWN, &adapter->state))
4606 mod_timer(&adapter->watchdog_timer,
4607 round_jiffies(jiffies + 2 * HZ));
4608}
4609
4610#define E1000_TX_FLAGS_CSUM 0x00000001
4611#define E1000_TX_FLAGS_VLAN 0x00000002
4612#define E1000_TX_FLAGS_TSO 0x00000004
4613#define E1000_TX_FLAGS_IPV4 0x00000008
4614#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4615#define E1000_TX_FLAGS_VLAN_SHIFT 16
4616
55aa6985 4617static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4618{
bc7f75fa
AK		 4619 struct e1000_context_desc *context_desc;
4620 struct e1000_buffer *buffer_info;
4621 unsigned int i;
4622 u32 cmd_length = 0;
4623 u16 ipcse = 0, tucse, mss;
4624 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4625
3d5e33c9
BA		 4626 if (!skb_is_gso(skb))
4627 return 0;
bc7f75fa 4628
3d5e33c9 4629 if (skb_header_cloned(skb)) {
90da0669
BA		 4630 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4631
3d5e33c9
BA		 4632 if (err)
4633 return err;
bc7f75fa
AK		 4634 }
4635
3d5e33c9
BA		 4636 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4637 mss = skb_shinfo(skb)->gso_size;
4638 if (skb->protocol == htons(ETH_P_IP)) {
4639 struct iphdr *iph = ip_hdr(skb);
4640 iph->tot_len = 0;
4641 iph->check = 0;
4642 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4643 0, IPPROTO_TCP, 0);
4644 cmd_length = E1000_TXD_CMD_IP;
4645 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4646 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4647 ipv6_hdr(skb)->payload_len = 0;
4648 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4649 &ipv6_hdr(skb)->daddr,
4650 0, IPPROTO_TCP, 0);
4651 ipcse = 0;
4652 }
4653 ipcss = skb_network_offset(skb);
4654 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4655 tucss = skb_transport_offset(skb);
4656 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4657 tucse = 0;
4658
4659 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4660 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4661
4662 i = tx_ring->next_to_use;
4663 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4664 buffer_info = &tx_ring->buffer_info[i];
4665
4666 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4667 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4668 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4669 context_desc->upper_setup.tcp_fields.tucss = tucss;
4670 context_desc->upper_setup.tcp_fields.tucso = tucso;
4671 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4672 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4673 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4674 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4675
4676 buffer_info->time_stamp = jiffies;
4677 buffer_info->next_to_watch = i;
4678
4679 i++;
4680 if (i == tx_ring->count)
4681 i = 0;
4682 tx_ring->next_to_use = i;
4683
4684 return 1;
bc7f75fa
AK		 4685}
4686
55aa6985 4687static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4688{
55aa6985 4689 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4690 struct e1000_context_desc *context_desc;
4691 struct e1000_buffer *buffer_info;
4692 unsigned int i;
4693 u8 css;
af807c82 4694 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4695 __be16 protocol;
bc7f75fa 4696
af807c82
DG		 4697 if (skb->ip_summed != CHECKSUM_PARTIAL)
4698 return 0;
bc7f75fa 4699
5f66f208
AJ		 4700 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4701 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4702 else
4703 protocol = skb->protocol;
4704
3f518390 4705 switch (protocol) {
09640e63 4706 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4707 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4708 cmd_len |= E1000_TXD_CMD_TCP;
4709 break;
09640e63 4710 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4711 /* XXX not handling all IPV6 headers */
4712 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4713 cmd_len |= E1000_TXD_CMD_TCP;
4714 break;
4715 default:
4716 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4717 e_warn("checksum_partial proto=%x!\n",
4718 be16_to_cpu(protocol));
af807c82 4719 break;
bc7f75fa
AK		 4720 }
4721
0d0b1672 4722 css = skb_checksum_start_offset(skb);
af807c82
DG		 4723
4724 i = tx_ring->next_to_use;
4725 buffer_info = &tx_ring->buffer_info[i];
4726 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4727
4728 context_desc->lower_setup.ip_config = 0;
4729 context_desc->upper_setup.tcp_fields.tucss = css;
4730 context_desc->upper_setup.tcp_fields.tucso =
4731 css + skb->csum_offset;
4732 context_desc->upper_setup.tcp_fields.tucse = 0;
4733 context_desc->tcp_seg_setup.data = 0;
4734 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4735
4736 buffer_info->time_stamp = jiffies;
4737 buffer_info->next_to_watch = i;
4738
4739 i++;
4740 if (i == tx_ring->count)
4741 i = 0;
4742 tx_ring->next_to_use = i;
4743
4744 return 1;
bc7f75fa
AK		 4745}
4746
4747#define E1000_MAX_PER_TXD 8192
4748#define E1000_MAX_TXD_PWR 12
4749
55aa6985
BA		 4750static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4751 unsigned int first, unsigned int max_per_txd,
4752 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4753{
55aa6985 4754 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4755 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4756 struct e1000_buffer *buffer_info;
8ddc951c 4757 unsigned int len = skb_headlen(skb);
03b1320d 4758 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4759 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4760
4761 i = tx_ring->next_to_use;
4762
4763 while (len) {
1b7719c4 4764 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4765 size = min(len, max_per_txd);
4766
bc7f75fa 4767 buffer_info->length = size;
bc7f75fa 4768 buffer_info->time_stamp = jiffies;
bc7f75fa 4769 buffer_info->next_to_watch = i;
0be3f55f
NN		 4770 buffer_info->dma = dma_map_single(&pdev->dev,
4771 skb->data + offset,
af667a29 4772 size, DMA_TO_DEVICE);
03b1320d 4773 buffer_info->mapped_as_page = false;
0be3f55f 4774 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4775 goto dma_error;
bc7f75fa
AK		 4776
4777 len -= size;
4778 offset += size;
03b1320d 4779 count++;
1b7719c4
AD		 4780
4781 if (len) {
4782 i++;
4783 if (i == tx_ring->count)
4784 i = 0;
4785 }
bc7f75fa
AK		 4786 }
4787
4788 for (f = 0; f < nr_frags; f++) {
9e903e08 4789 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4790
4791 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4792 len = skb_frag_size(frag);
877749bf 4793 offset = 0;
bc7f75fa
AK		 4794
4795 while (len) {
1b7719c4
AD		 4796 i++;
4797 if (i == tx_ring->count)
4798 i = 0;
4799
bc7f75fa
AK		 4800 buffer_info = &tx_ring->buffer_info[i];
4801 size = min(len, max_per_txd);
bc7f75fa
AK		 4802
4803 buffer_info->length = size;
4804 buffer_info->time_stamp = jiffies;
bc7f75fa 4805 buffer_info->next_to_watch = i;
877749bf
IC		 4806 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4807 offset, size, DMA_TO_DEVICE);
03b1320d 4808 buffer_info->mapped_as_page = true;
0be3f55f 4809 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4810 goto dma_error;
bc7f75fa
AK		 4811
4812 len -= size;
4813 offset += size;
4814 count++;
bc7f75fa
AK		 4815 }
4816 }
4817
af667a29 4818 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4819 /* multiply data chunks by size of headers */
4820 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4821
bc7f75fa 4822 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4823 tx_ring->buffer_info[i].segs = segs;
4824 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4825 tx_ring->buffer_info[first].next_to_watch = i;
4826
4827 return count;
03b1320d
AD		 4828
4829dma_error:
af667a29 4830 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4831 buffer_info->dma = 0;
c1fa347f 4832 if (count)
03b1320d 4833 count--;
c1fa347f
RK		 4834
4835 while (count--) {
af667a29 4836 if (i == 0)
03b1320d 4837 i += tx_ring->count;
c1fa347f 4838 i--;
03b1320d 4839 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4840 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4841 }
4842
4843 return 0;
bc7f75fa
AK		 4844}
4845
55aa6985 4846static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4847{
55aa6985 4848 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4849 struct e1000_tx_desc *tx_desc = NULL;
4850 struct e1000_buffer *buffer_info;
4851 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4852 unsigned int i;
4853
4854 if (tx_flags & E1000_TX_FLAGS_TSO) {
4855 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4856 E1000_TXD_CMD_TSE;
4857 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4858
4859 if (tx_flags & E1000_TX_FLAGS_IPV4)
4860 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4861 }
4862
4863 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4864 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4865 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4866 }
4867
4868 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4869 txd_lower |= E1000_TXD_CMD_VLE;
4870 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4871 }
4872
4873 i = tx_ring->next_to_use;
4874
36b973df 4875 do {
bc7f75fa
AK		 4876 buffer_info = &tx_ring->buffer_info[i];
4877 tx_desc = E1000_TX_DESC(*tx_ring, i);
4878 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4879 tx_desc->lower.data =
4880 cpu_to_le32(txd_lower | buffer_info->length);
4881 tx_desc->upper.data = cpu_to_le32(txd_upper);
4882
4883 i++;
4884 if (i == tx_ring->count)
4885 i = 0;
36b973df 4886 } while (--count > 0);
bc7f75fa
AK		 4887
4888 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4889
ad68076e
BA		 4890 /*
4891 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4892 * know there are new descriptors to fetch. (Only
4893 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4894 * such as IA-64).
4895 */
bc7f75fa
AK		 4896 wmb();
4897
4898 tx_ring->next_to_use = i;
c6e7f51e
BA		 4899
4900 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4901 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4902 else
c5083cf6 4903 writel(i, tx_ring->tail);
c6e7f51e 4904
ad68076e
BA		 4905 /*
4906 * we need this if more than one processor can write to our tail
4907 * at a time, it synchronizes IO on IA64/Altix systems
4908 */
bc7f75fa
AK		 4909 mmiowb();
4910}
4911
4912#define MINIMUM_DHCP_PACKET_SIZE 282
4913static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4914 struct sk_buff *skb)
4915{
4916 struct e1000_hw *hw = &adapter->hw;
4917 u16 length, offset;
4918
4919 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4920 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4921 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4922 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4923 return 0;
4924 }
4925
4926 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4927 return 0;
4928
4929 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4930 return 0;
4931
4932 {
4933 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4934 struct udphdr *udp;
4935
4936 if (ip->protocol != IPPROTO_UDP)
4937 return 0;
4938
4939 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4940 if (ntohs(udp->dest) != 67)
4941 return 0;
4942
4943 offset = (u8 *)udp + 8 - skb->data;
4944 length = skb->len - offset;
4945 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4946 }
4947
4948 return 0;
4949}
4950
55aa6985 4951static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4952{
55aa6985 4953 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4954
55aa6985 4955 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4956 /*
4957 * Herbert's original patch had:
bc7f75fa 4958 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4959 * but since that doesn't exist yet, just open code it.
4960 */
bc7f75fa
AK		 4961 smp_mb();
4962
ad68076e
BA		 4963 /*
4964 * We need to check again in a case another CPU has just
4965 * made room available.
4966 */
55aa6985 4967 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 4968 return -EBUSY;
4969
4970 /* A reprieve! */
55aa6985 4971 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 4972 ++adapter->restart_queue;
4973 return 0;
4974}
4975
55aa6985 4976static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4977{
55aa6985 4978 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 4979 return 0;
55aa6985 4980 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 4981}
4982
4983#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3b29a56d
SH		 4984static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
4985 struct net_device *netdev)
bc7f75fa
AK		 4986{
4987 struct e1000_adapter *adapter = netdev_priv(netdev);
4988 struct e1000_ring *tx_ring = adapter->tx_ring;
4989 unsigned int first;
4990 unsigned int max_per_txd = E1000_MAX_PER_TXD;
4991 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
4992 unsigned int tx_flags = 0;
e743d313 4993 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 4994 unsigned int nr_frags;
4995 unsigned int mss;
bc7f75fa
AK		 4996 int count = 0;
4997 int tso;
4998 unsigned int f;
bc7f75fa
AK		 4999
5000 if (test_bit(__E1000_DOWN, &adapter->state)) {
5001 dev_kfree_skb_any(skb);
5002 return NETDEV_TX_OK;
5003 }
5004
5005 if (skb->len <= 0) {
5006 dev_kfree_skb_any(skb);
5007 return NETDEV_TX_OK;
5008 }
5009
5010 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5011 /*
5012 * The controller does a simple calculation to
bc7f75fa
AK		 5013 * make sure there is enough room in the FIFO before
5014 * initiating the DMA for each buffer. The calc is:
5015 * 4 = ceil(buffer len/mss). To make sure we don't
5016 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5017 * drops.
5018 */
bc7f75fa
AK		 5019 if (mss) {
5020 u8 hdr_len;
5021 max_per_txd = min(mss << 2, max_per_txd);
5022 max_txd_pwr = fls(max_per_txd) - 1;
5023
ad68076e
BA		 5024 /*
5025 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5026 * points to just header, pull a few bytes of payload from
5027 * frags into skb->data
5028 */
bc7f75fa 5029 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5030 /*
5031 * we do this workaround for ES2LAN, but it is un-necessary,
5032 * avoiding it could save a lot of cycles
5033 */
4e6c709c 5034 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5035 unsigned int pull_size;
5036
5037 pull_size = min((unsigned int)4, skb->data_len);
5038 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5039 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5040 dev_kfree_skb_any(skb);
5041 return NETDEV_TX_OK;
5042 }
e743d313 5043 len = skb_headlen(skb);
bc7f75fa
AK		 5044 }
5045 }
5046
5047 /* reserve a descriptor for the offload context */
5048 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5049 count++;
5050 count++;
5051
5052 count += TXD_USE_COUNT(len, max_txd_pwr);
5053
5054 nr_frags = skb_shinfo(skb)->nr_frags;
5055 for (f = 0; f < nr_frags; f++)
9e903e08 5056 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5057 max_txd_pwr);
5058
5059 if (adapter->hw.mac.tx_pkt_filtering)
5060 e1000_transfer_dhcp_info(adapter, skb);
5061
ad68076e
BA		 5062 /*
5063 * need: count + 2 desc gap to keep tail from touching
5064 * head, otherwise try next time
5065 */
55aa6985 5066 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5067 return NETDEV_TX_BUSY;
bc7f75fa 5068
eab6d18d 5069 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5070 tx_flags |= E1000_TX_FLAGS_VLAN;
5071 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5072 }
5073
5074 first = tx_ring->next_to_use;
5075
55aa6985 5076 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5077 if (tso < 0) {
5078 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5079 return NETDEV_TX_OK;
5080 }
5081
5082 if (tso)
5083 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5084 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5085 tx_flags |= E1000_TX_FLAGS_CSUM;
5086
ad68076e
BA		 5087 /*
5088 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5089 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5090 * no longer assume, we must.
5091 */
bc7f75fa
AK		 5092 if (skb->protocol == htons(ETH_P_IP))
5093 tx_flags |= E1000_TX_FLAGS_IPV4;
5094
25985edc 5095 /* if count is 0 then mapping error has occurred */
55aa6985 5096 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5097 if (count) {
3f0cfa3b 5098 netdev_sent_queue(netdev, skb->len);
55aa6985 5099 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5100 /* Make sure there is space in the ring for the next send. */
55aa6985 5101 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5102
5103 } else {
bc7f75fa 5104 dev_kfree_skb_any(skb);
1b7719c4
AD		 5105 tx_ring->buffer_info[first].time_stamp = 0;
5106 tx_ring->next_to_use = first;
bc7f75fa
AK		 5107 }
5108
bc7f75fa
AK		 5109 return NETDEV_TX_OK;
5110}
5111
5112/**
5113 * e1000_tx_timeout - Respond to a Tx Hang
5114 * @netdev: network interface device structure
5115 **/
5116static void e1000_tx_timeout(struct net_device *netdev)
5117{
5118 struct e1000_adapter *adapter = netdev_priv(netdev);
5119
5120 /* Do the reset outside of interrupt context */
5121 adapter->tx_timeout_count++;
5122 schedule_work(&adapter->reset_task);
5123}
5124
5125static void e1000_reset_task(struct work_struct *work)
5126{
5127 struct e1000_adapter *adapter;
5128 adapter = container_of(work, struct e1000_adapter, reset_task);
5129
615b32af
JB		 5130 /* don't run the task if already down */
5131 if (test_bit(__E1000_DOWN, &adapter->state))
5132 return;
5133
affa9dfb
CW		 5134 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5135 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5136 e1000e_dump(adapter);
5137 e_err("Reset adapter\n");
5138 }
bc7f75fa
AK		 5139 e1000e_reinit_locked(adapter);
5140}
5141
5142/**
67fd4fcb 5143 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5144 * @netdev: network interface device structure
67fd4fcb 5145 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5146 *
5147 * Returns the address of the device statistics structure.
bc7f75fa 5148 **/
67fd4fcb
JK		 5149struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5150 struct rtnl_link_stats64 *stats)
bc7f75fa 5151{
67fd4fcb
JK		 5152 struct e1000_adapter *adapter = netdev_priv(netdev);
5153
5154 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5155 spin_lock(&adapter->stats64_lock);
5156 e1000e_update_stats(adapter);
5157 /* Fill out the OS statistics structure */
5158 stats->rx_bytes = adapter->stats.gorc;
5159 stats->rx_packets = adapter->stats.gprc;
5160 stats->tx_bytes = adapter->stats.gotc;
5161 stats->tx_packets = adapter->stats.gptc;
5162 stats->multicast = adapter->stats.mprc;
5163 stats->collisions = adapter->stats.colc;
5164
5165 /* Rx Errors */
5166
5167 /*
5168 * RLEC on some newer hardware can be incorrect so build
5169 * our own version based on RUC and ROC
5170 */
5171 stats->rx_errors = adapter->stats.rxerrc +
5172 adapter->stats.crcerrs + adapter->stats.algnerrc +
5173 adapter->stats.ruc + adapter->stats.roc +
5174 adapter->stats.cexterr;
5175 stats->rx_length_errors = adapter->stats.ruc +
5176 adapter->stats.roc;
5177 stats->rx_crc_errors = adapter->stats.crcerrs;
5178 stats->rx_frame_errors = adapter->stats.algnerrc;
5179 stats->rx_missed_errors = adapter->stats.mpc;
5180
5181 /* Tx Errors */
5182 stats->tx_errors = adapter->stats.ecol +
5183 adapter->stats.latecol;
5184 stats->tx_aborted_errors = adapter->stats.ecol;
5185 stats->tx_window_errors = adapter->stats.latecol;
5186 stats->tx_carrier_errors = adapter->stats.tncrs;
5187
5188 /* Tx Dropped needs to be maintained elsewhere */
5189
5190 spin_unlock(&adapter->stats64_lock);
5191 return stats;
bc7f75fa
AK		 5192}
5193
5194/**
5195 * e1000_change_mtu - Change the Maximum Transfer Unit
5196 * @netdev: network interface device structure
5197 * @new_mtu: new value for maximum frame size
5198 *
5199 * Returns 0 on success, negative on failure
5200 **/
5201static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5202{
5203 struct e1000_adapter *adapter = netdev_priv(netdev);
5204 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5205
2adc55c9 5206 /* Jumbo frame support */
70495a50
BA		 5207 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5208 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5209 e_err("Jumbo Frames not supported.\n");
5210 return -EINVAL;
5211 }
5212
5213 /*
5214 * IP payload checksum (enabled with jumbos/packet-split when
5215 * Rx checksum is enabled) and generation of RSS hash is
5216 * mutually exclusive in the hardware.
5217 */
5218 if ((netdev->features & NETIF_F_RXCSUM) &&
5219 (netdev->features & NETIF_F_RXHASH)) {
5220 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5221 return -EINVAL;
5222 }
bc7f75fa
AK		 5223 }
5224
2adc55c9
BA		 5225 /* Supported frame sizes */
5226 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5227 (max_frame > adapter->max_hw_frame_size)) {
5228 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5229 return -EINVAL;
5230 }
5231
a1ce6473
BA		 5232 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5233 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5234 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5235 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5236 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5237 return -EINVAL;
5238 }
5239
6f461f6c
BA		 5240 /* 82573 Errata 17 */
5241 if (((adapter->hw.mac.type == e1000_82573) ||
5242 (adapter->hw.mac.type == e1000_82574)) &&
5243 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5244 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5245 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5246 }
5247
bc7f75fa 5248 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5249 usleep_range(1000, 2000);
610c9928 5250 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5251 adapter->max_frame_size = max_frame;
610c9928
BA		 5252 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5253 netdev->mtu = new_mtu;
bc7f75fa
AK		 5254 if (netif_running(netdev))
5255 e1000e_down(adapter);
5256
ad68076e
BA		 5257 /*
5258 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5259 * means we reserve 2 more, this pushes us to allocate from the next
5260 * larger slab size.
ad68076e 5261 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5262 * However with the new *_jumbo_rx* routines, jumbo receives will use
5263 * fragmented skbs
ad68076e 5264 */
bc7f75fa 5265
9926146b 5266 if (max_frame <= 2048)
bc7f75fa
AK		 5267 adapter->rx_buffer_len = 2048;
5268 else
5269 adapter->rx_buffer_len = 4096;
5270
5271 /* adjust allocation if LPE protects us, and we aren't using SBP */
5272 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5273 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5274 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5275 + ETH_FCS_LEN;
bc7f75fa 5276
bc7f75fa
AK		 5277 if (netif_running(netdev))
5278 e1000e_up(adapter);
5279 else
5280 e1000e_reset(adapter);
5281
5282 clear_bit(__E1000_RESETTING, &adapter->state);
5283
5284 return 0;
5285}
5286
5287static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5288 int cmd)
5289{
5290 struct e1000_adapter *adapter = netdev_priv(netdev);
5291 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5292
318a94d6 5293 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5294 return -EOPNOTSUPP;
5295
5296 switch (cmd) {
5297 case SIOCGMIIPHY:
5298 data->phy_id = adapter->hw.phy.addr;
5299 break;
5300 case SIOCGMIIREG:
b16a002e
BA		 5301 e1000_phy_read_status(adapter);
5302
7c25769f
BA		 5303 switch (data->reg_num & 0x1F) {
5304 case MII_BMCR:
5305 data->val_out = adapter->phy_regs.bmcr;
5306 break;
5307 case MII_BMSR:
5308 data->val_out = adapter->phy_regs.bmsr;
5309 break;
5310 case MII_PHYSID1:
5311 data->val_out = (adapter->hw.phy.id >> 16);
5312 break;
5313 case MII_PHYSID2:
5314 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5315 break;
5316 case MII_ADVERTISE:
5317 data->val_out = adapter->phy_regs.advertise;
5318 break;
5319 case MII_LPA:
5320 data->val_out = adapter->phy_regs.lpa;
5321 break;
5322 case MII_EXPANSION:
5323 data->val_out = adapter->phy_regs.expansion;
5324 break;
5325 case MII_CTRL1000:
5326 data->val_out = adapter->phy_regs.ctrl1000;
5327 break;
5328 case MII_STAT1000:
5329 data->val_out = adapter->phy_regs.stat1000;
5330 break;
5331 case MII_ESTATUS:
5332 data->val_out = adapter->phy_regs.estatus;
5333 break;
5334 default:
bc7f75fa
AK		 5335 return -EIO;
5336 }
bc7f75fa
AK		 5337 break;
5338 case SIOCSMIIREG:
5339 default:
5340 return -EOPNOTSUPP;
5341 }
5342 return 0;
5343}
5344
5345static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5346{
5347 switch (cmd) {
5348 case SIOCGMIIPHY:
5349 case SIOCGMIIREG:
5350 case SIOCSMIIREG:
5351 return e1000_mii_ioctl(netdev, ifr, cmd);
5352 default:
5353 return -EOPNOTSUPP;
5354 }
5355}
5356
a4f58f54
BA		 5357static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5358{
5359 struct e1000_hw *hw = &adapter->hw;
5360 u32 i, mac_reg;
2b6b168d 5361 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5362 int retval = 0;
5363
5364 /* copy MAC RARs to PHY RARs */
d3738bb8 5365 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5366
2b6b168d
BA		 5367 retval = hw->phy.ops.acquire(hw);
5368 if (retval) {
5369 e_err("Could not acquire PHY\n");
5370 return retval;
5371 }
5372
5373 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5374 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5375 if (retval)
5376 goto out;
5377
5378 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5379 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5380 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5381 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5382 (u16)(mac_reg & 0xFFFF));
5383 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5384 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5385 }
5386
5387 /* configure PHY Rx Control register */
2b6b168d 5388 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5389 mac_reg = er32(RCTL);
5390 if (mac_reg & E1000_RCTL_UPE)
5391 phy_reg |= BM_RCTL_UPE;
5392 if (mac_reg & E1000_RCTL_MPE)
5393 phy_reg |= BM_RCTL_MPE;
5394 phy_reg &= ~(BM_RCTL_MO_MASK);
5395 if (mac_reg & E1000_RCTL_MO_3)
5396 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5397 << BM_RCTL_MO_SHIFT);
5398 if (mac_reg & E1000_RCTL_BAM)
5399 phy_reg |= BM_RCTL_BAM;
5400 if (mac_reg & E1000_RCTL_PMCF)
5401 phy_reg |= BM_RCTL_PMCF;
5402 mac_reg = er32(CTRL);
5403 if (mac_reg & E1000_CTRL_RFCE)
5404 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5405 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5406
5407 /* enable PHY wakeup in MAC register */
5408 ew32(WUFC, wufc);
5409 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5410
5411 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5412 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5413 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5414
5415 /* activate PHY wakeup */
2b6b168d
BA		 5416 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5417 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5418 if (retval)
5419 e_err("Could not set PHY Host Wakeup bit\n");
5420out:
94d8186a 5421 hw->phy.ops.release(hw);
a4f58f54
BA		 5422
5423 return retval;
5424}
5425
23606cf5
RW		 5426static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5427 bool runtime)
bc7f75fa
AK		 5428{
5429 struct net_device *netdev = pci_get_drvdata(pdev);
5430 struct e1000_adapter *adapter = netdev_priv(netdev);
5431 struct e1000_hw *hw = &adapter->hw;
5432 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5433 /* Runtime suspend should only enable wakeup for link changes */
5434 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5435 int retval = 0;
5436
5437 netif_device_detach(netdev);
5438
5439 if (netif_running(netdev)) {
5440 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5441 e1000e_down(adapter);
5442 e1000_free_irq(adapter);
5443 }
4662e82b 5444 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5445
5446 retval = pci_save_state(pdev);
5447 if (retval)
5448 return retval;
5449
5450 status = er32(STATUS);
5451 if (status & E1000_STATUS_LU)
5452 wufc &= ~E1000_WUFC_LNKC;
5453
5454 if (wufc) {
5455 e1000_setup_rctl(adapter);
ef9b965a 5456 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5457
5458 /* turn on all-multi mode if wake on multicast is enabled */
5459 if (wufc & E1000_WUFC_MC) {
5460 rctl = er32(RCTL);
5461 rctl |= E1000_RCTL_MPE;
5462 ew32(RCTL, rctl);
5463 }
5464
5465 ctrl = er32(CTRL);
5466 /* advertise wake from D3Cold */
5467 #define E1000_CTRL_ADVD3WUC 0x00100000
5468 /* phy power management enable */
5469 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5470 ctrl |= E1000_CTRL_ADVD3WUC;
5471 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5472 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5473 ew32(CTRL, ctrl);
5474
318a94d6
JK		 5475 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5476 adapter->hw.phy.media_type ==
5477 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5478 /* keep the laser running in D3 */
5479 ctrl_ext = er32(CTRL_EXT);
93a23f48 5480 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5481 ew32(CTRL_EXT, ctrl_ext);
5482 }
5483
97ac8cae 5484 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5485 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5486
bc7f75fa
AK		 5487 /* Allow time for pending master requests to run */
5488 e1000e_disable_pcie_master(&adapter->hw);
5489
82776a4b 5490 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5491 /* enable wakeup by the PHY */
5492 retval = e1000_init_phy_wakeup(adapter, wufc);
5493 if (retval)
5494 return retval;
5495 } else {
5496 /* enable wakeup by the MAC */
5497 ew32(WUFC, wufc);
5498 ew32(WUC, E1000_WUC_PME_EN);
5499 }
bc7f75fa
AK		 5500 } else {
5501 ew32(WUC, 0);
5502 ew32(WUFC, 0);
bc7f75fa
AK		 5503 }
5504
4f9de721
RW		 5505 *enable_wake = !!wufc;
5506
bc7f75fa 5507 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5508 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5509 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5510 *enable_wake = true;
bc7f75fa
AK		 5511
5512 if (adapter->hw.phy.type == e1000_phy_igp_3)
5513 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5514
ad68076e
BA		 5515 /*
5516 * Release control of h/w to f/w. If f/w is AMT enabled, this
5517 * would have already happened in close and is redundant.
5518 */
31dbe5b4 5519 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5520
5521 pci_disable_device(pdev);
5522
4f9de721
RW		 5523 return 0;
5524}
5525
5526static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5527{
5528 if (sleep && wake) {
5529 pci_prepare_to_sleep(pdev);
5530 return;
5531 }
5532
5533 pci_wake_from_d3(pdev, wake);
5534 pci_set_power_state(pdev, PCI_D3hot);
5535}
5536
5537static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5538 bool wake)
5539{
5540 struct net_device *netdev = pci_get_drvdata(pdev);
5541 struct e1000_adapter *adapter = netdev_priv(netdev);
5542
005cbdfc
AD		 5543 /*
5544 * The pci-e switch on some quad port adapters will report a
5545 * correctable error when the MAC transitions from D0 to D3. To
5546 * prevent this we need to mask off the correctable errors on the
5547 * downstream port of the pci-e switch.
5548 */
5549 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5550 struct pci_dev *us_dev = pdev->bus->self;
353064de 5551 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5552 u16 devctl;
5553
5554 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5555 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5556 (devctl & ~PCI_EXP_DEVCTL_CERE));
5557
4f9de721 5558 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5559
5560 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5561 } else {
4f9de721 5562 e1000_power_off(pdev, sleep, wake);
005cbdfc 5563 }
bc7f75fa
AK		 5564}
5565
6f461f6c
BA		 5566#ifdef CONFIG_PCIEASPM
5567static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5568{
9f728f53 5569 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5570}
5571#else
5572static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5573{
5574 int pos;
6f461f6c 5575 u16 reg16;
1eae4eb2
AK		 5576
5577 /*
6f461f6c
BA		 5578 * Both device and parent should have the same ASPM setting.
5579 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5580 */
6f461f6c
BA		 5581 pos = pci_pcie_cap(pdev);
5582 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5583 reg16 &= ~state;
5584 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5585
0c75ba22
AB		 5586 if (!pdev->bus->self)
5587 return;
5588
6f461f6c
BA		 5589 pos = pci_pcie_cap(pdev->bus->self);
5590 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5591 reg16 &= ~state;
5592 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5593}
5594#endif
78cd29d5 5595static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5596{
5597 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5598 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5599 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5600
5601 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5602}
5603
aa338601 5604#ifdef CONFIG_PM
23606cf5 5605static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5606{
23606cf5 5607 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5608}
5609
23606cf5 5610static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5611{
5612 struct net_device *netdev = pci_get_drvdata(pdev);
5613 struct e1000_adapter *adapter = netdev_priv(netdev);
5614 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5615 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5616 u32 err;
5617
78cd29d5
BA		 5618 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5619 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5620 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5621 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5622 if (aspm_disable_flag)
5623 e1000e_disable_aspm(pdev, aspm_disable_flag);
5624
bc7f75fa
AK		 5625 pci_set_power_state(pdev, PCI_D0);
5626 pci_restore_state(pdev);
28b8f04a 5627 pci_save_state(pdev);
6e4f6f6b 5628
4662e82b 5629 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5630 if (netif_running(netdev)) {
5631 err = e1000_request_irq(adapter);
5632 if (err)
5633 return err;
5634 }
5635
99730e4c
BA		 5636 if (hw->mac.type == e1000_pch2lan)
5637 e1000_resume_workarounds_pchlan(&adapter->hw);
5638
bc7f75fa 5639 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5640
5641 /* report the system wakeup cause from S3/S4 */
5642 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5643 u16 phy_data;
5644
5645 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5646 if (phy_data) {
5647 e_info("PHY Wakeup cause - %s\n",
5648 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5649 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5650 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5651 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5652 phy_data & E1000_WUS_LNKC ?
5653 "Link Status Change" : "other");
a4f58f54
BA		 5654 }
5655 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5656 } else {
5657 u32 wus = er32(WUS);
5658 if (wus) {
5659 e_info("MAC Wakeup cause - %s\n",
5660 wus & E1000_WUS_EX ? "Unicast Packet" :
5661 wus & E1000_WUS_MC ? "Multicast Packet" :
5662 wus & E1000_WUS_BC ? "Broadcast Packet" :
5663 wus & E1000_WUS_MAG ? "Magic Packet" :
5664 wus & E1000_WUS_LNKC ? "Link Status Change" :
5665 "other");
5666 }
5667 ew32(WUS, ~0);
5668 }
5669
bc7f75fa 5670 e1000e_reset(adapter);
bc7f75fa 5671
cd791618 5672 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5673
5674 if (netif_running(netdev))
5675 e1000e_up(adapter);
5676
5677 netif_device_attach(netdev);
5678
ad68076e
BA		 5679 /*
5680 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5681 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5682 * under the control of the driver.
5683 */
c43bc57e 5684 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5685 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5686
5687 return 0;
5688}
23606cf5 5689
a0340162
RW		 5690#ifdef CONFIG_PM_SLEEP
5691static int e1000_suspend(struct device *dev)
5692{
5693 struct pci_dev *pdev = to_pci_dev(dev);
5694 int retval;
5695 bool wake;
5696
5697 retval = __e1000_shutdown(pdev, &wake, false);
5698 if (!retval)
5699 e1000_complete_shutdown(pdev, true, wake);
5700
5701 return retval;
5702}
5703
23606cf5
RW		 5704static int e1000_resume(struct device *dev)
5705{
5706 struct pci_dev *pdev = to_pci_dev(dev);
5707 struct net_device *netdev = pci_get_drvdata(pdev);
5708 struct e1000_adapter *adapter = netdev_priv(netdev);
5709
5710 if (e1000e_pm_ready(adapter))
5711 adapter->idle_check = true;
5712
5713 return __e1000_resume(pdev);
5714}
a0340162
RW		 5715#endif /* CONFIG_PM_SLEEP */
5716
5717#ifdef CONFIG_PM_RUNTIME
5718static int e1000_runtime_suspend(struct device *dev)
5719{
5720 struct pci_dev *pdev = to_pci_dev(dev);
5721 struct net_device *netdev = pci_get_drvdata(pdev);
5722 struct e1000_adapter *adapter = netdev_priv(netdev);
5723
5724 if (e1000e_pm_ready(adapter)) {
5725 bool wake;
5726
5727 __e1000_shutdown(pdev, &wake, true);
5728 }
5729
5730 return 0;
5731}
5732
5733static int e1000_idle(struct device *dev)
5734{
5735 struct pci_dev *pdev = to_pci_dev(dev);
5736 struct net_device *netdev = pci_get_drvdata(pdev);
5737 struct e1000_adapter *adapter = netdev_priv(netdev);
5738
5739 if (!e1000e_pm_ready(adapter))
5740 return 0;
5741
5742 if (adapter->idle_check) {
5743 adapter->idle_check = false;
5744 if (!e1000e_has_link(adapter))
5745 pm_schedule_suspend(dev, MSEC_PER_SEC);
5746 }
5747
5748 return -EBUSY;
5749}
23606cf5
RW		 5750
5751static int e1000_runtime_resume(struct device *dev)
5752{
5753 struct pci_dev *pdev = to_pci_dev(dev);
5754 struct net_device *netdev = pci_get_drvdata(pdev);
5755 struct e1000_adapter *adapter = netdev_priv(netdev);
5756
5757 if (!e1000e_pm_ready(adapter))
5758 return 0;
5759
5760 adapter->idle_check = !dev->power.runtime_auto;
5761 return __e1000_resume(pdev);
5762}
a0340162 5763#endif /* CONFIG_PM_RUNTIME */
aa338601 5764#endif /* CONFIG_PM */
bc7f75fa
AK		 5765
5766static void e1000_shutdown(struct pci_dev *pdev)
5767{
4f9de721
RW		 5768 bool wake = false;
5769
23606cf5 5770 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5771
5772 if (system_state == SYSTEM_POWER_OFF)
5773 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5774}
5775
5776#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5777
5778static irqreturn_t e1000_intr_msix(int irq, void *data)
5779{
5780 struct net_device *netdev = data;
5781 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5782
5783 if (adapter->msix_entries) {
90da0669
BA		 5784 int vector, msix_irq;
5785
147b2c8c
DD		 5786 vector = 0;
5787 msix_irq = adapter->msix_entries[vector].vector;
5788 disable_irq(msix_irq);
5789 e1000_intr_msix_rx(msix_irq, netdev);
5790 enable_irq(msix_irq);
5791
5792 vector++;
5793 msix_irq = adapter->msix_entries[vector].vector;
5794 disable_irq(msix_irq);
5795 e1000_intr_msix_tx(msix_irq, netdev);
5796 enable_irq(msix_irq);
5797
5798 vector++;
5799 msix_irq = adapter->msix_entries[vector].vector;
5800 disable_irq(msix_irq);
5801 e1000_msix_other(msix_irq, netdev);
5802 enable_irq(msix_irq);
5803 }
5804
5805 return IRQ_HANDLED;
5806}
5807
bc7f75fa
AK		 5808/*
5809 * Polling 'interrupt' - used by things like netconsole to send skbs
5810 * without having to re-enable interrupts. It's not called while
5811 * the interrupt routine is executing.
5812 */
5813static void e1000_netpoll(struct net_device *netdev)
5814{
5815 struct e1000_adapter *adapter = netdev_priv(netdev);
5816
147b2c8c
DD		 5817 switch (adapter->int_mode) {
5818 case E1000E_INT_MODE_MSIX:
5819 e1000_intr_msix(adapter->pdev->irq, netdev);
5820 break;
5821 case E1000E_INT_MODE_MSI:
5822 disable_irq(adapter->pdev->irq);
5823 e1000_intr_msi(adapter->pdev->irq, netdev);
5824 enable_irq(adapter->pdev->irq);
5825 break;
5826 default: /* E1000E_INT_MODE_LEGACY */
5827 disable_irq(adapter->pdev->irq);
5828 e1000_intr(adapter->pdev->irq, netdev);
5829 enable_irq(adapter->pdev->irq);
5830 break;
5831 }
bc7f75fa
AK		 5832}
5833#endif
5834
5835/**
5836 * e1000_io_error_detected - called when PCI error is detected
5837 * @pdev: Pointer to PCI device
5838 * @state: The current pci connection state
5839 *
5840 * This function is called after a PCI bus error affecting
5841 * this device has been detected.
5842 */
5843static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5844 pci_channel_state_t state)
5845{
5846 struct net_device *netdev = pci_get_drvdata(pdev);
5847 struct e1000_adapter *adapter = netdev_priv(netdev);
5848
5849 netif_device_detach(netdev);
5850
c93b5a76
MM		 5851 if (state == pci_channel_io_perm_failure)
5852 return PCI_ERS_RESULT_DISCONNECT;
5853
bc7f75fa
AK		 5854 if (netif_running(netdev))
5855 e1000e_down(adapter);
5856 pci_disable_device(pdev);
5857
5858 /* Request a slot slot reset. */
5859 return PCI_ERS_RESULT_NEED_RESET;
5860}
5861
5862/**
5863 * e1000_io_slot_reset - called after the pci bus has been reset.
5864 * @pdev: Pointer to PCI device
5865 *
5866 * Restart the card from scratch, as if from a cold-boot. Implementation
5867 * resembles the first-half of the e1000_resume routine.
5868 */
5869static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5870{
5871 struct net_device *netdev = pci_get_drvdata(pdev);
5872 struct e1000_adapter *adapter = netdev_priv(netdev);
5873 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5874 u16 aspm_disable_flag = 0;
6e4f6f6b 5875 int err;
111b9dc5 5876 pci_ers_result_t result;
bc7f75fa 5877
78cd29d5
BA		 5878 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5879 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5880 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5881 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5882 if (aspm_disable_flag)
5883 e1000e_disable_aspm(pdev, aspm_disable_flag);
5884
f0f422e5 5885 err = pci_enable_device_mem(pdev);
6e4f6f6b 5886 if (err) {
bc7f75fa
AK		 5887 dev_err(&pdev->dev,
5888 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5889 result = PCI_ERS_RESULT_DISCONNECT;
5890 } else {
5891 pci_set_master(pdev);
23606cf5 5892 pdev->state_saved = true;
111b9dc5 5893 pci_restore_state(pdev);
bc7f75fa 5894
111b9dc5
JB		 5895 pci_enable_wake(pdev, PCI_D3hot, 0);
5896 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5897
111b9dc5
JB		 5898 e1000e_reset(adapter);
5899 ew32(WUS, ~0);
5900 result = PCI_ERS_RESULT_RECOVERED;
5901 }
bc7f75fa 5902
111b9dc5
JB		 5903 pci_cleanup_aer_uncorrect_error_status(pdev);
5904
5905 return result;
bc7f75fa
AK		 5906}
5907
5908/**
5909 * e1000_io_resume - called when traffic can start flowing again.
5910 * @pdev: Pointer to PCI device
5911 *
5912 * This callback is called when the error recovery driver tells us that
5913 * its OK to resume normal operation. Implementation resembles the
5914 * second-half of the e1000_resume routine.
5915 */
5916static void e1000_io_resume(struct pci_dev *pdev)
5917{
5918 struct net_device *netdev = pci_get_drvdata(pdev);
5919 struct e1000_adapter *adapter = netdev_priv(netdev);
5920
cd791618 5921 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5922
5923 if (netif_running(netdev)) {
5924 if (e1000e_up(adapter)) {
5925 dev_err(&pdev->dev,
5926 "can't bring device back up after reset\n");
5927 return;
5928 }
5929 }
5930
5931 netif_device_attach(netdev);
5932
ad68076e
BA		 5933 /*
5934 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5935 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5936 * under the control of the driver.
5937 */
c43bc57e 5938 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5939 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5940
5941}
5942
5943static void e1000_print_device_info(struct e1000_adapter *adapter)
5944{
5945 struct e1000_hw *hw = &adapter->hw;
5946 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5947 u32 ret_val;
5948 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5949
5950 /* print bus type/speed/width info */
a5cc7642 5951 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5952 /* bus width */
5953 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5954 "Width x1"),
5955 /* MAC address */
7c510e4b 5956 netdev->dev_addr);
44defeb3
JK		 5957 e_info("Intel(R) PRO/%s Network Connection\n",
5958 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5959 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5960 E1000_PBANUM_LENGTH);
5961 if (ret_val)
e0dc4f12 5962 strncpy((char *)pba_str, "Unknown", sizeof(pba_str) - 1);
073287c0
BA		 5963 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5964 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5965}
5966
10aa4c04
AK		 5967static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5968{
5969 struct e1000_hw *hw = &adapter->hw;
5970 int ret_val;
5971 u16 buf = 0;
5972
5973 if (hw->mac.type != e1000_82573)
5974 return;
5975
5976 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e243455d 5977 if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) {
10aa4c04 5978 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5979 dev_warn(&adapter->pdev->dev,
5980 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5981 }
10aa4c04
AK		 5982}
5983
c8f44aff 5984static int e1000_set_features(struct net_device *netdev,
70495a50 5985 netdev_features_t features)
dc221294
BA		 5986{
5987 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 5988 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 5989
5990 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
5991 adapter->flags |= FLAG_TSO_FORCE;
5992
5993 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
70495a50 5994 NETIF_F_RXCSUM | NETIF_F_RXHASH)))
dc221294
BA		 5995 return 0;
5996
70495a50
BA		 5997 /*
5998 * IP payload checksum (enabled with jumbos/packet-split when Rx
5999 * checksum is enabled) and generation of RSS hash is mutually
6000 * exclusive in the hardware.
6001 */
6002 if (adapter->rx_ps_pages &&
6003 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6004 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6005 return -EINVAL;
6006 }
6007
6008 netdev->features = features;
6009
dc221294
BA		 6010 if (netif_running(netdev))
6011 e1000e_reinit_locked(adapter);
6012 else
6013 e1000e_reset(adapter);
6014
6015 return 0;
6016}
6017
651c2466
SH		 6018static const struct net_device_ops e1000e_netdev_ops = {
6019 .ndo_open = e1000_open,
6020 .ndo_stop = e1000_close,
00829823 6021 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6022 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6023 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6024 .ndo_set_mac_address = e1000_set_mac,
6025 .ndo_change_mtu = e1000_change_mtu,
6026 .ndo_do_ioctl = e1000_ioctl,
6027 .ndo_tx_timeout = e1000_tx_timeout,
6028 .ndo_validate_addr = eth_validate_addr,
6029
651c2466
SH		 6030 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6031 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6032#ifdef CONFIG_NET_POLL_CONTROLLER
6033 .ndo_poll_controller = e1000_netpoll,
6034#endif
dc221294 6035 .ndo_set_features = e1000_set_features,
651c2466
SH		 6036};
6037
bc7f75fa
AK		 6038/**
6039 * e1000_probe - Device Initialization Routine
6040 * @pdev: PCI device information struct
6041 * @ent: entry in e1000_pci_tbl
6042 *
6043 * Returns 0 on success, negative on failure
6044 *
6045 * e1000_probe initializes an adapter identified by a pci_dev structure.
6046 * The OS initialization, configuring of the adapter private structure,
6047 * and a hardware reset occur.
6048 **/
6049static int __devinit e1000_probe(struct pci_dev *pdev,
6050 const struct pci_device_id *ent)
6051{
6052 struct net_device *netdev;
6053 struct e1000_adapter *adapter;
6054 struct e1000_hw *hw;
6055 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6056 resource_size_t mmio_start, mmio_len;
6057 resource_size_t flash_start, flash_len;
bc7f75fa
AK		 6058
6059 static int cards_found;
78cd29d5 6060 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6061 int i, err, pci_using_dac;
6062 u16 eeprom_data = 0;
6063 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6064
78cd29d5
BA		 6065 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6066 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6067 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6068 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6069 if (aspm_disable_flag)
6070 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6071
f0f422e5 6072 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6073 if (err)
6074 return err;
6075
6076 pci_using_dac = 0;
0be3f55f 6077 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6078 if (!err) {
0be3f55f 6079 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6080 if (!err)
6081 pci_using_dac = 1;
6082 } else {
0be3f55f 6083 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6084 if (err) {
0be3f55f
NN		 6085 err = dma_set_coherent_mask(&pdev->dev,
6086 DMA_BIT_MASK(32));
bc7f75fa 6087 if (err) {
ef456f85 6088 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6089 goto err_dma;
6090 }
6091 }
6092 }
6093
e8de1481 6094 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6095 pci_select_bars(pdev, IORESOURCE_MEM),
6096 e1000e_driver_name);
bc7f75fa
AK		 6097 if (err)
6098 goto err_pci_reg;
6099
68eac460 6100 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6101 pci_enable_pcie_error_reporting(pdev);
68eac460 6102
bc7f75fa 6103 pci_set_master(pdev);
438b365a
BA		 6104 /* PCI config space info */
6105 err = pci_save_state(pdev);
6106 if (err)
6107 goto err_alloc_etherdev;
bc7f75fa
AK		 6108
6109 err = -ENOMEM;
6110 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6111 if (!netdev)
6112 goto err_alloc_etherdev;
6113
bc7f75fa
AK		 6114 SET_NETDEV_DEV(netdev, &pdev->dev);
6115
f85e4dfa
TH		 6116 netdev->irq = pdev->irq;
6117
bc7f75fa
AK		 6118 pci_set_drvdata(pdev, netdev);
6119 adapter = netdev_priv(netdev);
6120 hw = &adapter->hw;
6121 adapter->netdev = netdev;
6122 adapter->pdev = pdev;
6123 adapter->ei = ei;
6124 adapter->pba = ei->pba;
6125 adapter->flags = ei->flags;
eb7c3adb 6126 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6127 adapter->hw.adapter = adapter;
6128 adapter->hw.mac.type = ei->mac;
2adc55c9 6129 adapter->max_hw_frame_size = ei->max_hw_frame_size;
bc7f75fa
AK		 6130 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
6131
6132 mmio_start = pci_resource_start(pdev, 0);
6133 mmio_len = pci_resource_len(pdev, 0);
6134
6135 err = -EIO;
6136 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6137 if (!adapter->hw.hw_addr)
6138 goto err_ioremap;
6139
6140 if ((adapter->flags & FLAG_HAS_FLASH) &&
6141 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6142 flash_start = pci_resource_start(pdev, 1);
6143 flash_len = pci_resource_len(pdev, 1);
6144 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6145 if (!adapter->hw.flash_address)
6146 goto err_flashmap;
6147 }
6148
6149 /* construct the net_device struct */
651c2466 6150 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6151 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6152 netdev->watchdog_timeo = 5 * HZ;
6153 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
bc7f75fa
AK		 6154 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6155
6156 netdev->mem_start = mmio_start;
6157 netdev->mem_end = mmio_start + mmio_len;
6158
6159 adapter->bd_number = cards_found++;
6160
4662e82b
BA		 6161 e1000e_check_options(adapter);
6162
bc7f75fa
AK		 6163 /* setup adapter struct */
6164 err = e1000_sw_init(adapter);
6165 if (err)
6166 goto err_sw_init;
6167
bc7f75fa
AK		 6168 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6169 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6170 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6171
69e3fd8c 6172 err = ei->get_variants(adapter);
bc7f75fa
AK		 6173 if (err)
6174 goto err_hw_init;
6175
4a770358
BA		 6176 if ((adapter->flags & FLAG_IS_ICH) &&
6177 (adapter->flags & FLAG_READ_ONLY_NVM))
6178 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6179
bc7f75fa
AK		 6180 hw->mac.ops.get_bus_info(&adapter->hw);
6181
318a94d6 6182 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6183
6184 /* Copper options */
318a94d6 6185 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6186 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6187 adapter->hw.phy.disable_polarity_correction = 0;
6188 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6189 }
6190
6191 if (e1000_check_reset_block(&adapter->hw))
44defeb3 6192 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6193
dc221294
BA		 6194 /* Set initial default active device features */
6195 netdev->features = (NETIF_F_SG |
6196 NETIF_F_HW_VLAN_RX |
6197 NETIF_F_HW_VLAN_TX |
6198 NETIF_F_TSO |
6199 NETIF_F_TSO6 |
70495a50 6200 NETIF_F_RXHASH |
dc221294
BA		 6201 NETIF_F_RXCSUM |
6202 NETIF_F_HW_CSUM);
6203
6204 /* Set user-changeable features (subset of all device features) */
6205 netdev->hw_features = netdev->features;
bc7f75fa
AK		 6206
6207 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6208 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6209
dc221294
BA		 6210 netdev->vlan_features |= (NETIF_F_SG |
6211 NETIF_F_TSO |
6212 NETIF_F_TSO6 |
6213 NETIF_F_HW_CSUM);
a5136e23 6214
ef9b965a
JB		 6215 netdev->priv_flags |= IFF_UNICAST_FLT;
6216
7b872a55 6217 if (pci_using_dac) {
bc7f75fa 6218 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6219 netdev->vlan_features |= NETIF_F_HIGHDMA;
6220 }
bc7f75fa 6221
bc7f75fa
AK		 6222 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6223 adapter->flags |= FLAG_MNG_PT_ENABLED;
6224
ad68076e
BA		 6225 /*
6226 * before reading the NVM, reset the controller to
6227 * put the device in a known good starting state
6228 */
bc7f75fa
AK		 6229 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6230
6231 /*
6232 * systems with ASPM and others may see the checksum fail on the first
6233 * attempt. Let's give it a few tries
6234 */
6235 for (i = 0;; i++) {
6236 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6237 break;
6238 if (i == 2) {
44defeb3 6239 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6240 err = -EIO;
6241 goto err_eeprom;
6242 }
6243 }
6244
10aa4c04
AK		 6245 e1000_eeprom_checks(adapter);
6246
608f8a0d 6247 /* copy the MAC address */
bc7f75fa 6248 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6249 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6250
6251 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6252 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6253
6254 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6255 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6256 err = -EIO;
6257 goto err_eeprom;
6258 }
6259
6260 init_timer(&adapter->watchdog_timer);
c061b18d 6261 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6262 adapter->watchdog_timer.data = (unsigned long) adapter;
6263
6264 init_timer(&adapter->phy_info_timer);
c061b18d 6265 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6266 adapter->phy_info_timer.data = (unsigned long) adapter;
6267
6268 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6269 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6270 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6271 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6272 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6273
bc7f75fa
AK		 6274 /* Initialize link parameters. User can change them with ethtool */
6275 adapter->hw.mac.autoneg = 1;
3db1cd5c 6276 adapter->fc_autoneg = true;
5c48ef3e
BA		 6277 adapter->hw.fc.requested_mode = e1000_fc_default;
6278 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6279 adapter->hw.phy.autoneg_advertised = 0x2f;
6280
6281 /* ring size defaults */
6282 adapter->rx_ring->count = 256;
6283 adapter->tx_ring->count = 256;
6284
6285 /*
6286 * Initial Wake on LAN setting - If APM wake is enabled in
6287 * the EEPROM, enable the ACPI Magic Packet filter
6288 */
6289 if (adapter->flags & FLAG_APME_IN_WUC) {
6290 /* APME bit in EEPROM is mapped to WUC.APME */
6291 eeprom_data = er32(WUC);
6292 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6293 if ((hw->mac.type > e1000_ich10lan) &&
6294 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6295 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6296 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6297 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6298 (adapter->hw.bus.func == 1))
6299 e1000_read_nvm(&adapter->hw,
6300 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
6301 else
6302 e1000_read_nvm(&adapter->hw,
6303 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6304 }
6305
6306 /* fetch WoL from EEPROM */
6307 if (eeprom_data & eeprom_apme_mask)
6308 adapter->eeprom_wol |= E1000_WUFC_MAG;
6309
6310 /*
6311 * now that we have the eeprom settings, apply the special cases
6312 * where the eeprom may be wrong or the board simply won't support
6313 * wake on lan on a particular port
6314 */
6315 if (!(adapter->flags & FLAG_HAS_WOL))
6316 adapter->eeprom_wol = 0;
6317
6318 /* initialize the wol settings based on the eeprom settings */
6319 adapter->wol = adapter->eeprom_wol;
6ff68026 6320 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6321
84527590
BA		 6322 /* save off EEPROM version number */
6323 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6324
bc7f75fa
AK		 6325 /* reset the hardware with the new settings */
6326 e1000e_reset(adapter);
6327
ad68076e
BA		 6328 /*
6329 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6330 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6331 * under the control of the driver.
6332 */
c43bc57e 6333 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6334 e1000e_get_hw_control(adapter);
bc7f75fa 6335
e0dc4f12 6336 strncpy(netdev->name, "eth%d", sizeof(netdev->name) - 1);
bc7f75fa
AK		 6337 err = register_netdev(netdev);
6338 if (err)
6339 goto err_register;
6340
9c563d20
JB		 6341 /* carrier off reporting is important to ethtool even BEFORE open */
6342 netif_carrier_off(netdev);
6343
bc7f75fa
AK		 6344 e1000_print_device_info(adapter);
6345
f3ec4f87
AS		 6346 if (pci_dev_run_wake(pdev))
6347 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6348
bc7f75fa
AK		 6349 return 0;
6350
6351err_register:
c43bc57e 6352 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6353 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 6354err_eeprom:
6355 if (!e1000_check_reset_block(&adapter->hw))
6356 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6357err_hw_init:
bc7f75fa
AK		 6358 kfree(adapter->tx_ring);
6359 kfree(adapter->rx_ring);
6360err_sw_init:
c43bc57e
JB		 6361 if (adapter->hw.flash_address)
6362 iounmap(adapter->hw.flash_address);
e82f54ba 6363 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6364err_flashmap:
bc7f75fa
AK		 6365 iounmap(adapter->hw.hw_addr);
6366err_ioremap:
6367 free_netdev(netdev);
6368err_alloc_etherdev:
f0f422e5
BA		 6369 pci_release_selected_regions(pdev,
6370 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6371err_pci_reg:
6372err_dma:
6373 pci_disable_device(pdev);
6374 return err;
6375}
6376
6377/**
6378 * e1000_remove - Device Removal Routine
6379 * @pdev: PCI device information struct
6380 *
6381 * e1000_remove is called by the PCI subsystem to alert the driver
6382 * that it should release a PCI device. The could be caused by a
6383 * Hot-Plug event, or because the driver is going to be removed from
6384 * memory.
6385 **/
6386static void __devexit e1000_remove(struct pci_dev *pdev)
6387{
6388 struct net_device *netdev = pci_get_drvdata(pdev);
6389 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6390 bool down = test_bit(__E1000_DOWN, &adapter->state);
6391
ad68076e 6392 /*
23f333a2
TH		 6393 * The timers may be rescheduled, so explicitly disable them
6394 * from being rescheduled.
ad68076e 6395 */
23606cf5
RW		 6396 if (!down)
6397 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6398 del_timer_sync(&adapter->watchdog_timer);
6399 del_timer_sync(&adapter->phy_info_timer);
6400
41cec6f1
BA		 6401 cancel_work_sync(&adapter->reset_task);
6402 cancel_work_sync(&adapter->watchdog_task);
6403 cancel_work_sync(&adapter->downshift_task);
6404 cancel_work_sync(&adapter->update_phy_task);
6405 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6406
17f208de
BA		 6407 if (!(netdev->flags & IFF_UP))
6408 e1000_power_down_phy(adapter);
6409
23606cf5
RW		 6410 /* Don't lie to e1000_close() down the road. */
6411 if (!down)
6412 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6413 unregister_netdev(netdev);
6414
f3ec4f87
AS		 6415 if (pci_dev_run_wake(pdev))
6416 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6417
ad68076e
BA		 6418 /*
6419 * Release control of h/w to f/w. If f/w is AMT enabled, this
6420 * would have already happened in close and is redundant.
6421 */
31dbe5b4 6422 e1000e_release_hw_control(adapter);
bc7f75fa 6423
4662e82b 6424 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6425 kfree(adapter->tx_ring);
6426 kfree(adapter->rx_ring);
6427
6428 iounmap(adapter->hw.hw_addr);
6429 if (adapter->hw.flash_address)
6430 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6431 pci_release_selected_regions(pdev,
6432 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6433
6434 free_netdev(netdev);
6435
111b9dc5 6436 /* AER disable */
19d5afd4 6437 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6438
bc7f75fa
AK		 6439 pci_disable_device(pdev);
6440}
6441
6442/* PCI Error Recovery (ERS) */
6443static struct pci_error_handlers e1000_err_handler = {
6444 .error_detected = e1000_io_error_detected,
6445 .slot_reset = e1000_io_slot_reset,
6446 .resume = e1000_io_resume,
6447};
6448
a3aa1884 6449static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6459
bc7f75fa
AK		 6460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6464
bc7f75fa
AK		 6465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6468
4662e82b 6469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6472
bc7f75fa
AK		 6473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6474 board_80003es2lan },
6475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6476 board_80003es2lan },
6477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6478 board_80003es2lan },
6479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6480 board_80003es2lan },
ad68076e 6481
bc7f75fa
AK		 6482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6490
bc7f75fa
AK		 6491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6496 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6500
6501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6504
f4187b56
BA		 6505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6508
a4f58f54
BA		 6509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6513
d3738bb8
BA		 6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6516
bc7f75fa
AK		 6517 { } /* terminate list */
6518};
6519MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6520
aa338601 6521#ifdef CONFIG_PM
23606cf5 6522static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6523 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6524 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6525 e1000_runtime_resume, e1000_idle)
23606cf5 6526};
e50208a0 6527#endif
23606cf5 6528
bc7f75fa
AK		 6529/* PCI Device API Driver */
6530static struct pci_driver e1000_driver = {
6531 .name = e1000e_driver_name,
6532 .id_table = e1000_pci_tbl,
6533 .probe = e1000_probe,
6534 .remove = __devexit_p(e1000_remove),
aa338601 6535#ifdef CONFIG_PM
23606cf5 6536 .driver.pm = &e1000_pm_ops,
bc7f75fa
AK		 6537#endif
6538 .shutdown = e1000_shutdown,
6539 .err_handler = &e1000_err_handler
6540};
6541
6542/**
6543 * e1000_init_module - Driver Registration Routine
6544 *
6545 * e1000_init_module is the first routine called when the driver is
6546 * loaded. All it does is register with the PCI subsystem.
6547 **/
6548static int __init e1000_init_module(void)
6549{
6550 int ret;
8544b9f7
BA		 6551 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6552 e1000e_driver_version);
0d6057e4 6553 pr_info("Copyright(c) 1999 - 2011 Intel Corporation.\n");
bc7f75fa 6554 ret = pci_register_driver(&e1000_driver);
53ec5498 6555
bc7f75fa
AK		 6556 return ret;
6557}
6558module_init(e1000_init_module);
6559
6560/**
6561 * e1000_exit_module - Driver Exit Cleanup Routine
6562 *
6563 * e1000_exit_module is called just before the driver is removed
6564 * from memory.
6565 **/
6566static void __exit e1000_exit_module(void)
6567{
6568 pci_unregister_driver(&e1000_driver);
6569}
6570module_exit(e1000_exit_module);
6571
6572
6573MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6574MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6575MODULE_LICENSE("GPL");
6576MODULE_VERSION(DRV_VERSION);
6577
6578/* e1000_main.c */
Linux kernel - Deliverables
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