projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
bc7f75fa
AK		 45#include <linux/ethtool.h>
46#include <linux/if_vlan.h>
47#include <linux/cpu.h>
48#include <linux/smp.h>
e8db0be1 49#include <linux/pm_qos.h>
23606cf5 50#include <linux/pm_runtime.h>
111b9dc5 51#include <linux/aer.h>
70c71606 52#include <linux/prefetch.h>
bc7f75fa
AK		 53
54#include "e1000.h"
55
b3ccf267 56#define DRV_EXTRAVERSION "-k"
c14c643b 57
8defe713 58#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 59char e1000e_driver_name[] = "e1000e";
60const char e1000e_driver_version[] = DRV_VERSION;
61
b3f4d599 62#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
63static int debug = -1;
64module_param(debug, int, 0);
65MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
66
78cd29d5
BA		 67static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
68
bc7f75fa
AK		 69static const struct e1000_info *e1000_info_tbl[] = {
70 [board_82571] = &e1000_82571_info,
71 [board_82572] = &e1000_82572_info,
72 [board_82573] = &e1000_82573_info,
4662e82b 73 [board_82574] = &e1000_82574_info,
8c81c9c3 74 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 75 [board_80003es2lan] = &e1000_es2_info,
76 [board_ich8lan] = &e1000_ich8_info,
77 [board_ich9lan] = &e1000_ich9_info,
f4187b56 78 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 79 [board_pchlan] = &e1000_pch_info,
d3738bb8 80 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 81 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
84f4ee90 89static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 90 /* General Registers */
91 {E1000_CTRL, "CTRL"},
92 {E1000_STATUS, "STATUS"},
93 {E1000_CTRL_EXT, "CTRL_EXT"},
94
95 /* Interrupt Registers */
96 {E1000_ICR, "ICR"},
97
af667a29 98 /* Rx Registers */
84f4ee90 99 {E1000_RCTL, "RCTL"},
1e36052e
BA		 100 {E1000_RDLEN(0), "RDLEN"},
101 {E1000_RDH(0), "RDH"},
102 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 103 {E1000_RDTR, "RDTR"},
104 {E1000_RXDCTL(0), "RXDCTL"},
105 {E1000_ERT, "ERT"},
1e36052e
BA		 106 {E1000_RDBAL(0), "RDBAL"},
107 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 108 {E1000_RDFH, "RDFH"},
109 {E1000_RDFT, "RDFT"},
110 {E1000_RDFHS, "RDFHS"},
111 {E1000_RDFTS, "RDFTS"},
112 {E1000_RDFPC, "RDFPC"},
113
af667a29 114 /* Tx Registers */
84f4ee90 115 {E1000_TCTL, "TCTL"},
1e36052e
BA		 116 {E1000_TDBAL(0), "TDBAL"},
117 {E1000_TDBAH(0), "TDBAH"},
118 {E1000_TDLEN(0), "TDLEN"},
119 {E1000_TDH(0), "TDH"},
120 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 121 {E1000_TIDV, "TIDV"},
122 {E1000_TXDCTL(0), "TXDCTL"},
123 {E1000_TADV, "TADV"},
124 {E1000_TARC(0), "TARC"},
125 {E1000_TDFH, "TDFH"},
126 {E1000_TDFT, "TDFT"},
127 {E1000_TDFHS, "TDFHS"},
128 {E1000_TDFTS, "TDFTS"},
129 {E1000_TDFPC, "TDFPC"},
130
131 /* List Terminator */
f36bb6ca 132 {0, NULL}
84f4ee90
TI		 133};
134
e921eb1a 135/**
84f4ee90 136 * e1000_regdump - register printout routine
e921eb1a
BA		 137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
84f4ee90
TI		 140static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
141{
142 int n = 0;
143 char rname[16];
144 u32 regs[8];
145
146 switch (reginfo->ofs) {
147 case E1000_RXDCTL(0):
148 for (n = 0; n < 2; n++)
149 regs[n] = __er32(hw, E1000_RXDCTL(n));
150 break;
151 case E1000_TXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_TXDCTL(n));
154 break;
155 case E1000_TARC(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TARC(n));
158 break;
159 default:
ef456f85
JK		 160 pr_info("%-15s %08x\n",
161 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 162 return;
163 }
164
165 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 166 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 167}
168
f0c5dadf
ET		 169static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
170 struct e1000_buffer *bi)
171{
172 int i;
173 struct e1000_ps_page *ps_page;
174
175 for (i = 0; i < adapter->rx_ps_pages; i++) {
176 ps_page = &bi->ps_pages[i];
177
178 if (ps_page->page) {
179 pr_info("packet dump for ps_page %d:\n", i);
180 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
181 16, 1, page_address(ps_page->page),
182 PAGE_SIZE, true);
183 }
184 }
185}
186
e921eb1a 187/**
af667a29 188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 189 * @adapter: board private structure
190 **/
84f4ee90
TI		 191static void e1000e_dump(struct e1000_adapter *adapter)
192{
193 struct net_device *netdev = adapter->netdev;
194 struct e1000_hw *hw = &adapter->hw;
195 struct e1000_reg_info *reginfo;
196 struct e1000_ring *tx_ring = adapter->tx_ring;
197 struct e1000_tx_desc *tx_desc;
af667a29 198 struct my_u0 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
af667a29 201 } *u0;
84f4ee90
TI		 202 struct e1000_buffer *buffer_info;
203 struct e1000_ring *rx_ring = adapter->rx_ring;
204 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 205 union e1000_rx_desc_extended *rx_desc;
af667a29 206 struct my_u1 {
e885d762
BA		 207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
af667a29 211 } *u1;
84f4ee90
TI		 212 u32 staterr;
213 int i = 0;
214
215 if (!netif_msg_hw(adapter))
216 return;
217
218 /* Print netdevice Info */
219 if (netdev) {
220 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 221 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 222 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
223 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 224 }
225
226 /* Print Registers */
227 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 228 pr_info(" Register Name Value\n");
84f4ee90
TI		 229 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
230 reginfo->name; reginfo++) {
231 e1000_regdump(hw, reginfo);
232 }
233
af667a29 234 /* Print Tx Ring Summary */
84f4ee90 235 if (!netdev || !netif_running(netdev))
fe1e980f 236 return;
84f4ee90 237
af667a29 238 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 239 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 240 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 241 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
242 0, tx_ring->next_to_use, tx_ring->next_to_clean,
243 (unsigned long long)buffer_info->dma,
244 buffer_info->length,
245 buffer_info->next_to_watch,
246 (unsigned long long)buffer_info->time_stamp);
84f4ee90 247
af667a29 248 /* Print Tx Ring */
84f4ee90
TI		 249 if (!netif_msg_tx_done(adapter))
250 goto rx_ring_summary;
251
af667a29 252 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 253
254 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
255 *
256 * Legacy Transmit Descriptor
257 * +--------------------------------------------------------------+
258 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
259 * +--------------------------------------------------------------+
260 * 8 | Special | CSS | Status | CMD | CSO | Length |
261 * +--------------------------------------------------------------+
262 * 63 48 47 36 35 32 31 24 23 16 15 0
263 *
264 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
265 * 63 48 47 40 39 32 31 16 15 8 7 0
266 * +----------------------------------------------------------------+
267 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
268 * +----------------------------------------------------------------+
269 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
270 * +----------------------------------------------------------------+
271 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
272 *
273 * Extended Data Descriptor (DTYP=0x1)
274 * +----------------------------------------------------------------+
275 * 0 | Buffer Address [63:0] |
276 * +----------------------------------------------------------------+
277 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
278 * +----------------------------------------------------------------+
279 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
280 */
ef456f85
JK		 281 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
282 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
283 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 284 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 285 const char *next_desc;
84f4ee90
TI		 286 tx_desc = E1000_TX_DESC(*tx_ring, i);
287 buffer_info = &tx_ring->buffer_info[i];
288 u0 = (struct my_u0 *)tx_desc;
84f4ee90 289 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 290 next_desc = " NTC/U";
84f4ee90 291 else if (i == tx_ring->next_to_use)
ef456f85 292 next_desc = " NTU";
84f4ee90 293 else if (i == tx_ring->next_to_clean)
ef456f85 294 next_desc = " NTC";
84f4ee90 295 else
ef456f85
JK		 296 next_desc = "";
297 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
298 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
299 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
300 i,
301 (unsigned long long)le64_to_cpu(u0->a),
302 (unsigned long long)le64_to_cpu(u0->b),
303 (unsigned long long)buffer_info->dma,
304 buffer_info->length, buffer_info->next_to_watch,
305 (unsigned long long)buffer_info->time_stamp,
306 buffer_info->skb, next_desc);
84f4ee90 307
f0c5dadf 308 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 309 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 310 16, 1, buffer_info->skb->data,
311 buffer_info->skb->len, true);
84f4ee90
TI		 312 }
313
af667a29 314 /* Print Rx Ring Summary */
84f4ee90 315rx_ring_summary:
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 317 pr_info("Queue [NTU] [NTC]\n");
318 pr_info(" %5d %5X %5X\n",
319 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 320
af667a29 321 /* Print Rx Ring */
84f4ee90 322 if (!netif_msg_rx_status(adapter))
fe1e980f 323 return;
84f4ee90 324
af667a29 325 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 326 switch (adapter->rx_ps_pages) {
327 case 1:
328 case 2:
329 case 3:
330 /* [Extended] Packet Split Receive Descriptor Format
331 *
332 * +-----------------------------------------------------+
333 * 0 | Buffer Address 0 [63:0] |
334 * +-----------------------------------------------------+
335 * 8 | Buffer Address 1 [63:0] |
336 * +-----------------------------------------------------+
337 * 16 | Buffer Address 2 [63:0] |
338 * +-----------------------------------------------------+
339 * 24 | Buffer Address 3 [63:0] |
340 * +-----------------------------------------------------+
341 */
ef456f85 342 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 343 /* [Extended] Receive Descriptor (Write-Back) Format
344 *
345 * 63 48 47 32 31 13 12 8 7 4 3 0
346 * +------------------------------------------------------+
347 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
348 * | Checksum | Ident | | Queue | | Type |
349 * +------------------------------------------------------+
350 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
351 * +------------------------------------------------------+
352 * 63 48 47 32 31 20 19 0
353 */
ef456f85 354 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 355 for (i = 0; i < rx_ring->count; i++) {
ef456f85 356 const char *next_desc;
84f4ee90
TI		 357 buffer_info = &rx_ring->buffer_info[i];
358 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
359 u1 = (struct my_u1 *)rx_desc_ps;
360 staterr =
af667a29 361 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 362
363 if (i == rx_ring->next_to_use)
364 next_desc = " NTU";
365 else if (i == rx_ring->next_to_clean)
366 next_desc = " NTC";
367 else
368 next_desc = "";
369
84f4ee90
TI		 370 if (staterr & E1000_RXD_STAT_DD) {
371 /* Descriptor Done */
ef456f85
JK		 372 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
373 "RWB", i,
374 (unsigned long long)le64_to_cpu(u1->a),
375 (unsigned long long)le64_to_cpu(u1->b),
376 (unsigned long long)le64_to_cpu(u1->c),
377 (unsigned long long)le64_to_cpu(u1->d),
378 buffer_info->skb, next_desc);
84f4ee90 379 } else {
ef456f85
JK		 380 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
381 "R ", i,
382 (unsigned long long)le64_to_cpu(u1->a),
383 (unsigned long long)le64_to_cpu(u1->b),
384 (unsigned long long)le64_to_cpu(u1->c),
385 (unsigned long long)le64_to_cpu(u1->d),
386 (unsigned long long)buffer_info->dma,
387 buffer_info->skb, next_desc);
84f4ee90
TI		 388
389 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 390 e1000e_dump_ps_pages(adapter,
391 buffer_info);
84f4ee90 392 }
84f4ee90
TI		 393 }
394 break;
395 default:
396 case 0:
5f450212 397 /* Extended Receive Descriptor (Read) Format
84f4ee90 398 *
5f450212
BA		 399 * +-----------------------------------------------------+
400 * 0 | Buffer Address [63:0] |
401 * +-----------------------------------------------------+
402 * 8 | Reserved |
403 * +-----------------------------------------------------+
84f4ee90 404 */
ef456f85 405 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 406 /* Extended Receive Descriptor (Write-Back) Format
407 *
408 * 63 48 47 32 31 24 23 4 3 0
409 * +------------------------------------------------------+
410 * | RSS Hash | | | |
411 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
412 * | Packet | IP | | | Type |
413 * | Checksum | Ident | | | |
414 * +------------------------------------------------------+
415 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
416 * +------------------------------------------------------+
417 * 63 48 47 32 31 20 19 0
418 */
ef456f85 419 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 420
421 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 422 const char *next_desc;
423
84f4ee90 424 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 425 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
426 u1 = (struct my_u1 *)rx_desc;
427 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 428
429 if (i == rx_ring->next_to_use)
430 next_desc = " NTU";
431 else if (i == rx_ring->next_to_clean)
432 next_desc = " NTC";
433 else
434 next_desc = "";
435
5f450212
BA		 436 if (staterr & E1000_RXD_STAT_DD) {
437 /* Descriptor Done */
ef456f85
JK		 438 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
439 "RWB", i,
440 (unsigned long long)le64_to_cpu(u1->a),
441 (unsigned long long)le64_to_cpu(u1->b),
442 buffer_info->skb, next_desc);
5f450212 443 } else {
ef456f85
JK		 444 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
445 "R ", i,
446 (unsigned long long)le64_to_cpu(u1->a),
447 (unsigned long long)le64_to_cpu(u1->b),
448 (unsigned long long)buffer_info->dma,
449 buffer_info->skb, next_desc);
5f450212 450
f0c5dadf
ET		 451 if (netif_msg_pktdata(adapter) &&
452 buffer_info->skb)
5f450212
BA		 453 print_hex_dump(KERN_INFO, "",
454 DUMP_PREFIX_ADDRESS, 16,
455 1,
f0c5dadf 456 buffer_info->skb->data,
5f450212
BA		 457 adapter->rx_buffer_len,
458 true);
459 }
84f4ee90
TI		 460 }
461 }
84f4ee90
TI		 462}
463
bc7f75fa
AK		 464/**
465 * e1000_desc_unused - calculate if we have unused descriptors
466 **/
467static int e1000_desc_unused(struct e1000_ring *ring)
468{
469 if (ring->next_to_clean > ring->next_to_use)
470 return ring->next_to_clean - ring->next_to_use - 1;
471
472 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
473}
474
b67e1913
BA		 475/**
476 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
477 * @adapter: board private structure
478 * @hwtstamps: time stamp structure to update
479 * @systim: unsigned 64bit system time value.
480 *
481 * Convert the system time value stored in the RX/TXSTMP registers into a
482 * hwtstamp which can be used by the upper level time stamping functions.
483 *
484 * The 'systim_lock' spinlock is used to protect the consistency of the
485 * system time value. This is needed because reading the 64 bit time
486 * value involves reading two 32 bit registers. The first read latches the
487 * value.
488 **/
489static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
490 struct skb_shared_hwtstamps *hwtstamps,
491 u64 systim)
492{
493 u64 ns;
494 unsigned long flags;
495
496 spin_lock_irqsave(&adapter->systim_lock, flags);
497 ns = timecounter_cyc2time(&adapter->tc, systim);
498 spin_unlock_irqrestore(&adapter->systim_lock, flags);
499
500 memset(hwtstamps, 0, sizeof(*hwtstamps));
501 hwtstamps->hwtstamp = ns_to_ktime(ns);
502}
503
504/**
505 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
506 * @adapter: board private structure
507 * @status: descriptor extended error and status field
508 * @skb: particular skb to include time stamp
509 *
510 * If the time stamp is valid, convert it into the timecounter ns value
511 * and store that result into the shhwtstamps structure which is passed
512 * up the network stack.
513 **/
514static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
515 struct sk_buff *skb)
516{
517 struct e1000_hw *hw = &adapter->hw;
518 u64 rxstmp;
519
520 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
521 !(status & E1000_RXDEXT_STATERR_TST) ||
522 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
523 return;
524
525 /* The Rx time stamp registers contain the time stamp. No other
526 * received packet will be time stamped until the Rx time stamp
527 * registers are read. Because only one packet can be time stamped
528 * at a time, the register values must belong to this packet and
529 * therefore none of the other additional attributes need to be
530 * compared.
531 */
532 rxstmp = (u64)er32(RXSTMPL);
533 rxstmp |= (u64)er32(RXSTMPH) << 32;
534 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
535
536 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
537}
538
bc7f75fa 539/**
ad68076e 540 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 541 * @adapter: board private structure
b67e1913 542 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 543 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
544 * @skb: pointer to sk_buff to be indicated to stack
545 **/
546static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 547 struct net_device *netdev, struct sk_buff *skb,
b67e1913 548 u32 staterr, __le16 vlan)
bc7f75fa 549{
86d70e53 550 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 551
552 e1000e_rx_hwtstamp(adapter, staterr, skb);
553
bc7f75fa
AK		 554 skb->protocol = eth_type_trans(skb, netdev);
555
b67e1913 556 if (staterr & E1000_RXD_STAT_VP)
86d70e53
JK		 557 __vlan_hwaccel_put_tag(skb, tag);
558
559 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 560}
561
562/**
af667a29 563 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 564 * @adapter: board private structure
565 * @status_err: receive descriptor status and error fields
566 * @csum: receive descriptor csum field
567 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 568 **/
569static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 570 struct sk_buff *skb)
bc7f75fa
AK		 571{
572 u16 status = (u16)status_err;
573 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 574
575 skb_checksum_none_assert(skb);
bc7f75fa 576
afd12939
BA		 577 /* Rx checksum disabled */
578 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
579 return;
580
bc7f75fa
AK		 581 /* Ignore Checksum bit is set */
582 if (status & E1000_RXD_STAT_IXSM)
583 return;
afd12939 584
2e1706f2
BA		 585 /* TCP/UDP checksum error bit or IP checksum error bit is set */
586 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 587 /* let the stack verify checksum errors */
588 adapter->hw_csum_err++;
589 return;
590 }
591
592 /* TCP/UDP Checksum has not been calculated */
593 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
594 return;
595
596 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 597 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 598 adapter->hw_csum_good++;
599}
600
55aa6985 601static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 602{
55aa6985 603 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 604 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 605 s32 ret_val = __ew32_prepare(hw);
606
607 writel(i, rx_ring->tail);
c6e7f51e 608
bdc125f7 609 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 610 u32 rctl = er32(RCTL);
611 ew32(RCTL, rctl & ~E1000_RCTL_EN);
612 e_err("ME firmware caused invalid RDT - resetting\n");
613 schedule_work(&adapter->reset_task);
614 }
615}
616
55aa6985 617static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 618{
55aa6985 619 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 620 struct e1000_hw *hw = &adapter->hw;
bdc125f7 621 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 622
bdc125f7
BA		 623 writel(i, tx_ring->tail);
624
625 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 626 u32 tctl = er32(TCTL);
627 ew32(TCTL, tctl & ~E1000_TCTL_EN);
628 e_err("ME firmware caused invalid TDT - resetting\n");
629 schedule_work(&adapter->reset_task);
630 }
631}
632
bc7f75fa 633/**
5f450212 634 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 635 * @rx_ring: Rx descriptor ring
bc7f75fa 636 **/
55aa6985 637static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 638 int cleaned_count, gfp_t gfp)
bc7f75fa 639{
55aa6985 640 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 641 struct net_device *netdev = adapter->netdev;
642 struct pci_dev *pdev = adapter->pdev;
5f450212 643 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 644 struct e1000_buffer *buffer_info;
645 struct sk_buff *skb;
646 unsigned int i;
89d71a66 647 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 648
649 i = rx_ring->next_to_use;
650 buffer_info = &rx_ring->buffer_info[i];
651
652 while (cleaned_count--) {
653 skb = buffer_info->skb;
654 if (skb) {
655 skb_trim(skb, 0);
656 goto map_skb;
657 }
658
c2fed996 659 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 660 if (!skb) {
661 /* Better luck next round */
662 adapter->alloc_rx_buff_failed++;
663 break;
664 }
665
bc7f75fa
AK		 666 buffer_info->skb = skb;
667map_skb:
0be3f55f 668 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 669 adapter->rx_buffer_len,
0be3f55f
NN		 670 DMA_FROM_DEVICE);
671 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 672 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 673 adapter->rx_dma_failed++;
674 break;
675 }
676
5f450212
BA		 677 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
678 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 679
50849d79 680 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 681 /* Force memory writes to complete before letting h/w
50849d79
TH		 682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
c6e7f51e 687 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 688 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 689 else
c5083cf6 690 writel(i, rx_ring->tail);
50849d79 691 }
bc7f75fa
AK		 692 i++;
693 if (i == rx_ring->count)
694 i = 0;
695 buffer_info = &rx_ring->buffer_info[i];
696 }
697
50849d79 698 rx_ring->next_to_use = i;
bc7f75fa
AK		 699}
700
701/**
702 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 703 * @rx_ring: Rx descriptor ring
bc7f75fa 704 **/
55aa6985 705static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 706 int cleaned_count, gfp_t gfp)
bc7f75fa 707{
55aa6985 708 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 709 struct net_device *netdev = adapter->netdev;
710 struct pci_dev *pdev = adapter->pdev;
711 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 712 struct e1000_buffer *buffer_info;
713 struct e1000_ps_page *ps_page;
714 struct sk_buff *skb;
715 unsigned int i, j;
716
717 i = rx_ring->next_to_use;
718 buffer_info = &rx_ring->buffer_info[i];
719
720 while (cleaned_count--) {
721 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
722
723 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 724 ps_page = &buffer_info->ps_pages[j];
725 if (j >= adapter->rx_ps_pages) {
726 /* all unused desc entries get hw null ptr */
af667a29
BA		 727 rx_desc->read.buffer_addr[j + 1] =
728 ~cpu_to_le64(0);
47f44e40
AK		 729 continue;
730 }
731 if (!ps_page->page) {
c2fed996 732 ps_page->page = alloc_page(gfp);
bc7f75fa 733 if (!ps_page->page) {
47f44e40
AK		 734 adapter->alloc_rx_buff_failed++;
735 goto no_buffers;
736 }
0be3f55f
NN		 737 ps_page->dma = dma_map_page(&pdev->dev,
738 ps_page->page,
739 0, PAGE_SIZE,
740 DMA_FROM_DEVICE);
741 if (dma_mapping_error(&pdev->dev,
742 ps_page->dma)) {
47f44e40 743 dev_err(&adapter->pdev->dev,
af667a29 744 "Rx DMA page map failed\n");
47f44e40
AK		 745 adapter->rx_dma_failed++;
746 goto no_buffers;
bc7f75fa 747 }
bc7f75fa 748 }
e921eb1a 749 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 750 * didn't change because each write-back
751 * erases this info.
752 */
af667a29
BA		 753 rx_desc->read.buffer_addr[j + 1] =
754 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 755 }
756
e5fe2541 757 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 758 gfp);
bc7f75fa
AK		 759
760 if (!skb) {
761 adapter->alloc_rx_buff_failed++;
762 break;
763 }
764
bc7f75fa 765 buffer_info->skb = skb;
0be3f55f 766 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 767 adapter->rx_ps_bsize0,
0be3f55f
NN		 768 DMA_FROM_DEVICE);
769 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 770 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 771 adapter->rx_dma_failed++;
772 /* cleanup skb */
773 dev_kfree_skb_any(skb);
774 buffer_info->skb = NULL;
775 break;
776 }
777
778 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
779
50849d79 780 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 781 /* Force memory writes to complete before letting h/w
50849d79
TH		 782 * know there are new descriptors to fetch. (Only
783 * applicable for weak-ordered memory model archs,
784 * such as IA-64).
785 */
786 wmb();
c6e7f51e 787 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 788 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 789 else
c5083cf6 790 writel(i << 1, rx_ring->tail);
50849d79
TH		 791 }
792
bc7f75fa
AK		 793 i++;
794 if (i == rx_ring->count)
795 i = 0;
796 buffer_info = &rx_ring->buffer_info[i];
797 }
798
799no_buffers:
50849d79 800 rx_ring->next_to_use = i;
bc7f75fa
AK		 801}
802
97ac8cae
BA		 803/**
804 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 805 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 806 * @cleaned_count: number of buffers to allocate this pass
807 **/
808
55aa6985 809static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 810 int cleaned_count, gfp_t gfp)
97ac8cae 811{
55aa6985 812 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 813 struct net_device *netdev = adapter->netdev;
814 struct pci_dev *pdev = adapter->pdev;
5f450212 815 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 816 struct e1000_buffer *buffer_info;
817 struct sk_buff *skb;
818 unsigned int i;
2a2293b9 819 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 820
821 i = rx_ring->next_to_use;
822 buffer_info = &rx_ring->buffer_info[i];
823
824 while (cleaned_count--) {
825 skb = buffer_info->skb;
826 if (skb) {
827 skb_trim(skb, 0);
828 goto check_page;
829 }
830
c2fed996 831 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 832 if (unlikely(!skb)) {
833 /* Better luck next round */
834 adapter->alloc_rx_buff_failed++;
835 break;
836 }
837
97ac8cae
BA		 838 buffer_info->skb = skb;
839check_page:
840 /* allocate a new page if necessary */
841 if (!buffer_info->page) {
c2fed996 842 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 843 if (unlikely(!buffer_info->page)) {
844 adapter->alloc_rx_buff_failed++;
845 break;
846 }
847 }
848
37287fae 849 if (!buffer_info->dma) {
0be3f55f 850 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 851 buffer_info->page, 0,
852 PAGE_SIZE,
0be3f55f 853 DMA_FROM_DEVICE);
37287fae
CP		 854 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
855 adapter->alloc_rx_buff_failed++;
856 break;
857 }
858 }
97ac8cae 859
5f450212
BA		 860 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
861 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 862
863 if (unlikely(++i == rx_ring->count))
864 i = 0;
865 buffer_info = &rx_ring->buffer_info[i];
866 }
867
868 if (likely(rx_ring->next_to_use != i)) {
869 rx_ring->next_to_use = i;
870 if (unlikely(i-- == 0))
871 i = (rx_ring->count - 1);
872
873 /* Force memory writes to complete before letting h/w
874 * know there are new descriptors to fetch. (Only
875 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 876 * such as IA-64).
877 */
97ac8cae 878 wmb();
c6e7f51e 879 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 880 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 881 else
c5083cf6 882 writel(i, rx_ring->tail);
97ac8cae
BA		 883 }
884}
885
70495a50
BA		 886static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
887 struct sk_buff *skb)
888{
889 if (netdev->features & NETIF_F_RXHASH)
890 skb->rxhash = le32_to_cpu(rss);
891}
892
bc7f75fa 893/**
55aa6985
BA		 894 * e1000_clean_rx_irq - Send received data up the network stack
895 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 896 *
897 * the return value indicates whether actual cleaning was done, there
898 * is no guarantee that everything was cleaned
899 **/
55aa6985
BA		 900static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
901 int work_to_do)
bc7f75fa 902{
55aa6985 903 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 904 struct net_device *netdev = adapter->netdev;
905 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 906 struct e1000_hw *hw = &adapter->hw;
5f450212 907 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 908 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 909 u32 length, staterr;
bc7f75fa
AK		 910 unsigned int i;
911 int cleaned_count = 0;
3db1cd5c 912 bool cleaned = false;
bc7f75fa
AK		 913 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
914
915 i = rx_ring->next_to_clean;
5f450212
BA		 916 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
917 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 918 buffer_info = &rx_ring->buffer_info[i];
919
5f450212 920 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 921 struct sk_buff *skb;
bc7f75fa
AK		 922
923 if (*work_done >= work_to_do)
924 break;
925 (*work_done)++;
2d0bb1c1 926 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 927
bc7f75fa
AK		 928 skb = buffer_info->skb;
929 buffer_info->skb = NULL;
930
931 prefetch(skb->data - NET_IP_ALIGN);
932
933 i++;
934 if (i == rx_ring->count)
935 i = 0;
5f450212 936 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 937 prefetch(next_rxd);
938
939 next_buffer = &rx_ring->buffer_info[i];
940
3db1cd5c 941 cleaned = true;
bc7f75fa 942 cleaned_count++;
e5fe2541
BA		 943 dma_unmap_single(&pdev->dev, buffer_info->dma,
944 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 945 buffer_info->dma = 0;
946
5f450212 947 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 948
e921eb1a 949 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 950 * packet, if that's the case we need to toss it. In fact, we
951 * need to toss every packet with the EOP bit clear and the
952 * next frame that _does_ have the EOP bit set, as it is by
953 * definition only a frame fragment
954 */
5f450212 955 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 956 adapter->flags2 |= FLAG2_IS_DISCARDING;
957
958 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 959 /* All receives must fit into a single buffer */
3bb99fe2 960 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 961 /* recycle */
962 buffer_info->skb = skb;
5f450212 963 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 964 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 965 goto next_desc;
966 }
967
cf955e6c
BG		 968 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
969 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 970 /* recycle */
971 buffer_info->skb = skb;
972 goto next_desc;
973 }
974
eb7c3adb 975 /* adjust length to remove Ethernet CRC */
0184039a
BG		 976 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
977 /* If configured to store CRC, don't subtract FCS,
978 * but keep the FCS bytes out of the total_rx_bytes
979 * counter
980 */
981 if (netdev->features & NETIF_F_RXFCS)
982 total_rx_bytes -= 4;
983 else
984 length -= 4;
985 }
eb7c3adb 986
bc7f75fa
AK		 987 total_rx_bytes += length;
988 total_rx_packets++;
989
e921eb1a 990 /* code added for copybreak, this should improve
bc7f75fa 991 * performance for small packets with large amounts
ad68076e
BA		 992 * of reassembly being done in the stack
993 */
bc7f75fa
AK		 994 if (length < copybreak) {
995 struct sk_buff *new_skb =
89d71a66 996 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 997 if (new_skb) {
808ff676
BA		 998 skb_copy_to_linear_data_offset(new_skb,
999 -NET_IP_ALIGN,
1000 (skb->data -
1001 NET_IP_ALIGN),
1002 (length +
1003 NET_IP_ALIGN));
bc7f75fa
AK		 1004 /* save the skb in buffer_info as good */
1005 buffer_info->skb = skb;
1006 skb = new_skb;
1007 }
1008 /* else just continue with the old one */
1009 }
1010 /* end copybreak code */
1011 skb_put(skb, length);
1012
1013 /* Receive Checksum Offload */
2e1706f2 1014 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1015
70495a50
BA		 1016 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1017
5f450212
BA		 1018 e1000_receive_skb(adapter, netdev, skb, staterr,
1019 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1020
1021next_desc:
5f450212 1022 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1023
1024 /* return some buffers to hardware, one at a time is too slow */
1025 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1026 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1027 GFP_ATOMIC);
bc7f75fa
AK		 1028 cleaned_count = 0;
1029 }
1030
1031 /* use prefetched values */
1032 rx_desc = next_rxd;
1033 buffer_info = next_buffer;
5f450212
BA		 1034
1035 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1036 }
1037 rx_ring->next_to_clean = i;
1038
1039 cleaned_count = e1000_desc_unused(rx_ring);
1040 if (cleaned_count)
55aa6985 1041 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1042
bc7f75fa 1043 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1044 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1045 return cleaned;
1046}
1047
55aa6985
BA		 1048static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1049 struct e1000_buffer *buffer_info)
bc7f75fa 1050{
55aa6985
BA		 1051 struct e1000_adapter *adapter = tx_ring->adapter;
1052
03b1320d
AD		 1053 if (buffer_info->dma) {
1054 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1055 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1056 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1057 else
0be3f55f
NN		 1058 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1059 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1060 buffer_info->dma = 0;
1061 }
bc7f75fa
AK		 1062 if (buffer_info->skb) {
1063 dev_kfree_skb_any(buffer_info->skb);
1064 buffer_info->skb = NULL;
1065 }
1b7719c4 1066 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1067}
1068
41cec6f1 1069static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1070{
41cec6f1 1071 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1072 struct e1000_adapter,
1073 print_hang_task);
09357b00 1074 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1075 struct e1000_ring *tx_ring = adapter->tx_ring;
1076 unsigned int i = tx_ring->next_to_clean;
1077 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1078 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1079 struct e1000_hw *hw = &adapter->hw;
1080 u16 phy_status, phy_1000t_status, phy_ext_status;
1081 u16 pci_status;
1082
615b32af
JB		 1083 if (test_bit(__E1000_DOWN, &adapter->state))
1084 return;
1085
e5fe2541 1086 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1087 /* May be block on write-back, flush and detect again
09357b00
JK		 1088 * flush pending descriptor writebacks to memory
1089 */
1090 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1091 /* execute the writes immediately */
1092 e1e_flush();
e921eb1a 1093 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1094 * the write is successful
1095 */
1096 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1097 /* execute the writes immediately */
1098 e1e_flush();
09357b00
JK		 1099 adapter->tx_hang_recheck = true;
1100 return;
1101 }
1102 /* Real hang detected */
1103 adapter->tx_hang_recheck = false;
1104 netif_stop_queue(netdev);
1105
c2ade1a4
BA		 1106 e1e_rphy(hw, MII_BMSR, &phy_status);
1107 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1108 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1109
41cec6f1
BA		 1110 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1111
1112 /* detected Hardware unit hang */
1113 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1114 " TDH <%x>\n"
1115 " TDT <%x>\n"
1116 " next_to_use <%x>\n"
1117 " next_to_clean <%x>\n"
1118 "buffer_info[next_to_clean]:\n"
1119 " time_stamp <%lx>\n"
1120 " next_to_watch <%x>\n"
1121 " jiffies <%lx>\n"
41cec6f1
BA		 1122 " next_to_watch.status <%x>\n"
1123 "MAC Status <%x>\n"
1124 "PHY Status <%x>\n"
1125 "PHY 1000BASE-T Status <%x>\n"
1126 "PHY Extended Status <%x>\n"
1127 "PCI Status <%x>\n",
e5fe2541
BA		 1128 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1129 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1130 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1131 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee
BA		 1132
1133 /* Suggest workaround for known h/w issue */
1134 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1135 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1136}
1137
b67e1913
BA		 1138/**
1139 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1140 * @work: pointer to work struct
1141 *
1142 * This work function polls the TSYNCTXCTL valid bit to determine when a
1143 * timestamp has been taken for the current stored skb. The timestamp must
1144 * be for this skb because only one such packet is allowed in the queue.
1145 */
1146static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1147{
1148 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1149 tx_hwtstamp_work);
1150 struct e1000_hw *hw = &adapter->hw;
1151
1152 if (!adapter->tx_hwtstamp_skb)
1153 return;
1154
1155 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1156 struct skb_shared_hwtstamps shhwtstamps;
1157 u64 txstmp;
1158
1159 txstmp = er32(TXSTMPL);
1160 txstmp |= (u64)er32(TXSTMPH) << 32;
1161
1162 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1163
1164 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1165 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1166 adapter->tx_hwtstamp_skb = NULL;
1167 } else {
1168 /* reschedule to check later */
1169 schedule_work(&adapter->tx_hwtstamp_work);
1170 }
1171}
1172
bc7f75fa
AK		 1173/**
1174 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1175 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1176 *
1177 * the return value indicates whether actual cleaning was done, there
1178 * is no guarantee that everything was cleaned
1179 **/
55aa6985 1180static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1181{
55aa6985 1182 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1183 struct net_device *netdev = adapter->netdev;
1184 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1185 struct e1000_tx_desc *tx_desc, *eop_desc;
1186 struct e1000_buffer *buffer_info;
1187 unsigned int i, eop;
1188 unsigned int count = 0;
bc7f75fa 1189 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1190 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1191
1192 i = tx_ring->next_to_clean;
1193 eop = tx_ring->buffer_info[i].next_to_watch;
1194 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1195
12d04a3c
AD		 1196 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1197 (count < tx_ring->count)) {
a86043c2 1198 bool cleaned = false;
2d0bb1c1 1199 rmb(); /* read buffer_info after eop_desc */
a86043c2 1200 for (; !cleaned; count++) {
bc7f75fa
AK		 1201 tx_desc = E1000_TX_DESC(*tx_ring, i);
1202 buffer_info = &tx_ring->buffer_info[i];
1203 cleaned = (i == eop);
1204
1205 if (cleaned) {
9ed318d5
TH		 1206 total_tx_packets += buffer_info->segs;
1207 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1208 if (buffer_info->skb) {
1209 bytes_compl += buffer_info->skb->len;
1210 pkts_compl++;
1211 }
bc7f75fa
AK		 1212 }
1213
55aa6985 1214 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1215 tx_desc->upper.data = 0;
1216
1217 i++;
1218 if (i == tx_ring->count)
1219 i = 0;
1220 }
1221
dac87619
TL		 1222 if (i == tx_ring->next_to_use)
1223 break;
bc7f75fa
AK		 1224 eop = tx_ring->buffer_info[i].next_to_watch;
1225 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1226 }
1227
1228 tx_ring->next_to_clean = i;
1229
3f0cfa3b
TH		 1230 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1231
bc7f75fa 1232#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1233 if (count && netif_carrier_ok(netdev) &&
1234 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1235 /* Make sure that anybody stopping the queue after this
1236 * sees the new next_to_clean.
1237 */
1238 smp_mb();
1239
1240 if (netif_queue_stopped(netdev) &&
1241 !(test_bit(__E1000_DOWN, &adapter->state))) {
1242 netif_wake_queue(netdev);
1243 ++adapter->restart_queue;
1244 }
1245 }
1246
1247 if (adapter->detect_tx_hung) {
e921eb1a 1248 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1249 * check with the clearing of time_stamp and movement of i
1250 */
3db1cd5c 1251 adapter->detect_tx_hung = false;
12d04a3c
AD		 1252 if (tx_ring->buffer_info[i].time_stamp &&
1253 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1254 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1255 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1256 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1257 else
1258 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1259 }
1260 adapter->total_tx_bytes += total_tx_bytes;
1261 adapter->total_tx_packets += total_tx_packets;
807540ba 1262 return count < tx_ring->count;
bc7f75fa
AK		 1263}
1264
bc7f75fa
AK		 1265/**
1266 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1267 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1268 *
1269 * the return value indicates whether actual cleaning was done, there
1270 * is no guarantee that everything was cleaned
1271 **/
55aa6985
BA		 1272static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1273 int work_to_do)
bc7f75fa 1274{
55aa6985 1275 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1276 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1277 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1278 struct net_device *netdev = adapter->netdev;
1279 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1280 struct e1000_buffer *buffer_info, *next_buffer;
1281 struct e1000_ps_page *ps_page;
1282 struct sk_buff *skb;
1283 unsigned int i, j;
1284 u32 length, staterr;
1285 int cleaned_count = 0;
3db1cd5c 1286 bool cleaned = false;
bc7f75fa
AK		 1287 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1288
1289 i = rx_ring->next_to_clean;
1290 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1291 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1292 buffer_info = &rx_ring->buffer_info[i];
1293
1294 while (staterr & E1000_RXD_STAT_DD) {
1295 if (*work_done >= work_to_do)
1296 break;
1297 (*work_done)++;
1298 skb = buffer_info->skb;
2d0bb1c1 1299 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1300
1301 /* in the packet split case this is header only */
1302 prefetch(skb->data - NET_IP_ALIGN);
1303
1304 i++;
1305 if (i == rx_ring->count)
1306 i = 0;
1307 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1308 prefetch(next_rxd);
1309
1310 next_buffer = &rx_ring->buffer_info[i];
1311
3db1cd5c 1312 cleaned = true;
bc7f75fa 1313 cleaned_count++;
0be3f55f 1314 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1315 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1316 buffer_info->dma = 0;
1317
af667a29 1318 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1319 if (!(staterr & E1000_RXD_STAT_EOP))
1320 adapter->flags2 |= FLAG2_IS_DISCARDING;
1321
1322 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1323 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1324 dev_kfree_skb_irq(skb);
b94b5028
JB		 1325 if (staterr & E1000_RXD_STAT_EOP)
1326 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1327 goto next_desc;
1328 }
1329
cf955e6c
BG		 1330 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1331 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1332 dev_kfree_skb_irq(skb);
1333 goto next_desc;
1334 }
1335
1336 length = le16_to_cpu(rx_desc->wb.middle.length0);
1337
1338 if (!length) {
ef456f85 1339 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1340 dev_kfree_skb_irq(skb);
1341 goto next_desc;
1342 }
1343
1344 /* Good Receive */
1345 skb_put(skb, length);
1346
1347 {
e921eb1a 1348 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1349 * it more efficient than reusing j
1350 */
1351 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1352
e921eb1a 1353 /* page alloc/put takes too long and effects small
0e15df49
BA		 1354 * packet throughput, so unsplit small packets and
1355 * save the alloc/put only valid in softirq (napi)
1356 * context to call kmap_*
ad68076e 1357 */
0e15df49
BA		 1358 if (l1 && (l1 <= copybreak) &&
1359 ((length + l1) <= adapter->rx_ps_bsize0)) {
1360 u8 *vaddr;
1361
1362 ps_page = &buffer_info->ps_pages[0];
1363
e921eb1a 1364 /* there is no documentation about how to call
0e15df49
BA		 1365 * kmap_atomic, so we can't hold the mapping
1366 * very long
1367 */
1368 dma_sync_single_for_cpu(&pdev->dev,
1369 ps_page->dma,
1370 PAGE_SIZE,
1371 DMA_FROM_DEVICE);
9f393834 1372 vaddr = kmap_atomic(ps_page->page);
0e15df49 1373 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1374 kunmap_atomic(vaddr);
0e15df49
BA		 1375 dma_sync_single_for_device(&pdev->dev,
1376 ps_page->dma,
1377 PAGE_SIZE,
1378 DMA_FROM_DEVICE);
1379
1380 /* remove the CRC */
0184039a
BG		 1381 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1382 if (!(netdev->features & NETIF_F_RXFCS))
1383 l1 -= 4;
1384 }
0e15df49
BA		 1385
1386 skb_put(skb, l1);
1387 goto copydone;
1388 } /* if */
bc7f75fa
AK		 1389 }
1390
1391 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1392 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1393 if (!length)
1394 break;
1395
47f44e40 1396 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1397 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1398 DMA_FROM_DEVICE);
bc7f75fa
AK		 1399 ps_page->dma = 0;
1400 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1401 ps_page->page = NULL;
1402 skb->len += length;
1403 skb->data_len += length;
98a045d7 1404 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1405 }
1406
eb7c3adb
JK		 1407 /* strip the ethernet crc, problem is we're using pages now so
1408 * this whole operation can get a little cpu intensive
1409 */
0184039a
BG		 1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1411 if (!(netdev->features & NETIF_F_RXFCS))
1412 pskb_trim(skb, skb->len - 4);
1413 }
eb7c3adb 1414
bc7f75fa
AK		 1415copydone:
1416 total_rx_bytes += skb->len;
1417 total_rx_packets++;
1418
2e1706f2 1419 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1420
70495a50
BA		 1421 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1422
bc7f75fa 1423 if (rx_desc->wb.upper.header_status &
17e813ec 1424 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1425 adapter->rx_hdr_split++;
1426
b67e1913
BA		 1427 e1000_receive_skb(adapter, netdev, skb, staterr,
1428 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1429
1430next_desc:
1431 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1432 buffer_info->skb = NULL;
1433
1434 /* return some buffers to hardware, one at a time is too slow */
1435 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1436 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1437 GFP_ATOMIC);
bc7f75fa
AK		 1438 cleaned_count = 0;
1439 }
1440
1441 /* use prefetched values */
1442 rx_desc = next_rxd;
1443 buffer_info = next_buffer;
1444
1445 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1446 }
1447 rx_ring->next_to_clean = i;
1448
1449 cleaned_count = e1000_desc_unused(rx_ring);
1450 if (cleaned_count)
55aa6985 1451 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1452
bc7f75fa 1453 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1454 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1455 return cleaned;
1456}
1457
97ac8cae
BA		 1458/**
1459 * e1000_consume_page - helper function
1460 **/
1461static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1462 u16 length)
97ac8cae
BA		 1463{
1464 bi->page = NULL;
1465 skb->len += length;
1466 skb->data_len += length;
98a045d7 1467 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1468}
1469
1470/**
1471 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1472 * @adapter: board private structure
1473 *
1474 * the return value indicates whether actual cleaning was done, there
1475 * is no guarantee that everything was cleaned
1476 **/
55aa6985
BA		 1477static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1478 int work_to_do)
97ac8cae 1479{
55aa6985 1480 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1481 struct net_device *netdev = adapter->netdev;
1482 struct pci_dev *pdev = adapter->pdev;
5f450212 1483 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1484 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1485 u32 length, staterr;
97ac8cae
BA		 1486 unsigned int i;
1487 int cleaned_count = 0;
1488 bool cleaned = false;
362e20ca 1489 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1490 struct skb_shared_info *shinfo;
97ac8cae
BA		 1491
1492 i = rx_ring->next_to_clean;
5f450212
BA		 1493 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1494 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1495 buffer_info = &rx_ring->buffer_info[i];
1496
5f450212 1497 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1498 struct sk_buff *skb;
97ac8cae
BA		 1499
1500 if (*work_done >= work_to_do)
1501 break;
1502 (*work_done)++;
2d0bb1c1 1503 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1504
97ac8cae
BA		 1505 skb = buffer_info->skb;
1506 buffer_info->skb = NULL;
1507
1508 ++i;
1509 if (i == rx_ring->count)
1510 i = 0;
5f450212 1511 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1512 prefetch(next_rxd);
1513
1514 next_buffer = &rx_ring->buffer_info[i];
1515
1516 cleaned = true;
1517 cleaned_count++;
0be3f55f
NN		 1518 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1519 DMA_FROM_DEVICE);
97ac8cae
BA		 1520 buffer_info->dma = 0;
1521
5f450212 1522 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1523
1524 /* errors is only valid for DD + EOP descriptors */
5f450212 1525 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1526 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1527 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1528 /* recycle both page and skb */
1529 buffer_info->skb = skb;
1530 /* an error means any chain goes out the window too */
1531 if (rx_ring->rx_skb_top)
1532 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1533 rx_ring->rx_skb_top = NULL;
1534 goto next_desc;
97ac8cae 1535 }
f0f1a172 1536#define rxtop (rx_ring->rx_skb_top)
5f450212 1537 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1538 /* this descriptor is only the beginning (or middle) */
1539 if (!rxtop) {
1540 /* this is the beginning of a chain */
1541 rxtop = skb;
1542 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1543 0, length);
97ac8cae
BA		 1544 } else {
1545 /* this is the middle of a chain */
17e813ec
BA		 1546 shinfo = skb_shinfo(rxtop);
1547 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1548 buffer_info->page, 0,
1549 length);
97ac8cae
BA		 1550 /* re-use the skb, only consumed the page */
1551 buffer_info->skb = skb;
1552 }
1553 e1000_consume_page(buffer_info, rxtop, length);
1554 goto next_desc;
1555 } else {
1556 if (rxtop) {
1557 /* end of the chain */
17e813ec
BA		 1558 shinfo = skb_shinfo(rxtop);
1559 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1560 buffer_info->page, 0,
1561 length);
97ac8cae 1562 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1563 * page
1564 */
97ac8cae
BA		 1565 buffer_info->skb = skb;
1566 skb = rxtop;
1567 rxtop = NULL;
1568 e1000_consume_page(buffer_info, skb, length);
1569 } else {
1570 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1571 * copybreak to save the put_page/alloc_page
1572 */
97ac8cae
BA		 1573 if (length <= copybreak &&
1574 skb_tailroom(skb) >= length) {
1575 u8 *vaddr;
4679026d 1576 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1577 memcpy(skb_tail_pointer(skb), vaddr,
1578 length);
4679026d 1579 kunmap_atomic(vaddr);
97ac8cae 1580 /* re-use the page, so don't erase
e921eb1a
BA		 1581 * buffer_info->page
1582 */
97ac8cae
BA		 1583 skb_put(skb, length);
1584 } else {
1585 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1586 buffer_info->page, 0,
1587 length);
97ac8cae 1588 e1000_consume_page(buffer_info, skb,
f0ff4398 1589 length);
97ac8cae
BA		 1590 }
1591 }
1592 }
1593
2e1706f2
BA		 1594 /* Receive Checksum Offload */
1595 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1596
70495a50
BA		 1597 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1598
97ac8cae
BA		 1599 /* probably a little skewed due to removing CRC */
1600 total_rx_bytes += skb->len;
1601 total_rx_packets++;
1602
1603 /* eth type trans needs skb->data to point to something */
1604 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1605 e_err("pskb_may_pull failed.\n");
ef5ab89c 1606 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1607 goto next_desc;
1608 }
1609
5f450212
BA		 1610 e1000_receive_skb(adapter, netdev, skb, staterr,
1611 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1612
1613next_desc:
5f450212 1614 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1615
1616 /* return some buffers to hardware, one at a time is too slow */
1617 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1618 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1619 GFP_ATOMIC);
97ac8cae
BA		 1620 cleaned_count = 0;
1621 }
1622
1623 /* use prefetched values */
1624 rx_desc = next_rxd;
1625 buffer_info = next_buffer;
5f450212
BA		 1626
1627 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1628 }
1629 rx_ring->next_to_clean = i;
1630
1631 cleaned_count = e1000_desc_unused(rx_ring);
1632 if (cleaned_count)
55aa6985 1633 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1634
1635 adapter->total_rx_bytes += total_rx_bytes;
1636 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1637 return cleaned;
1638}
1639
bc7f75fa
AK		 1640/**
1641 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1642 * @rx_ring: Rx descriptor ring
bc7f75fa 1643 **/
55aa6985 1644static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1645{
55aa6985 1646 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1647 struct e1000_buffer *buffer_info;
1648 struct e1000_ps_page *ps_page;
1649 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1650 unsigned int i, j;
1651
1652 /* Free all the Rx ring sk_buffs */
1653 for (i = 0; i < rx_ring->count; i++) {
1654 buffer_info = &rx_ring->buffer_info[i];
1655 if (buffer_info->dma) {
1656 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1657 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1658 adapter->rx_buffer_len,
0be3f55f 1659 DMA_FROM_DEVICE);
97ac8cae 1660 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1661 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1662 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1663 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1664 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1665 adapter->rx_ps_bsize0,
0be3f55f 1666 DMA_FROM_DEVICE);
bc7f75fa
AK		 1667 buffer_info->dma = 0;
1668 }
1669
97ac8cae
BA		 1670 if (buffer_info->page) {
1671 put_page(buffer_info->page);
1672 buffer_info->page = NULL;
1673 }
1674
bc7f75fa
AK		 1675 if (buffer_info->skb) {
1676 dev_kfree_skb(buffer_info->skb);
1677 buffer_info->skb = NULL;
1678 }
1679
1680 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1681 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1682 if (!ps_page->page)
1683 break;
0be3f55f
NN		 1684 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1685 DMA_FROM_DEVICE);
bc7f75fa
AK		 1686 ps_page->dma = 0;
1687 put_page(ps_page->page);
1688 ps_page->page = NULL;
1689 }
1690 }
1691
1692 /* there also may be some cached data from a chained receive */
1693 if (rx_ring->rx_skb_top) {
1694 dev_kfree_skb(rx_ring->rx_skb_top);
1695 rx_ring->rx_skb_top = NULL;
1696 }
1697
bc7f75fa
AK		 1698 /* Zero out the descriptor ring */
1699 memset(rx_ring->desc, 0, rx_ring->size);
1700
1701 rx_ring->next_to_clean = 0;
1702 rx_ring->next_to_use = 0;
b94b5028 1703 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1704
c5083cf6 1705 writel(0, rx_ring->head);
bdc125f7
BA		 1706 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1707 e1000e_update_rdt_wa(rx_ring, 0);
1708 else
1709 writel(0, rx_ring->tail);
bc7f75fa
AK		 1710}
1711
a8f88ff5
JB		 1712static void e1000e_downshift_workaround(struct work_struct *work)
1713{
1714 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1715 struct e1000_adapter,
1716 downshift_task);
a8f88ff5 1717
615b32af
JB		 1718 if (test_bit(__E1000_DOWN, &adapter->state))
1719 return;
1720
a8f88ff5
JB		 1721 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1722}
1723
bc7f75fa
AK		 1724/**
1725 * e1000_intr_msi - Interrupt Handler
1726 * @irq: interrupt number
1727 * @data: pointer to a network interface device structure
1728 **/
8bb62869 1729static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1730{
1731 struct net_device *netdev = data;
1732 struct e1000_adapter *adapter = netdev_priv(netdev);
1733 struct e1000_hw *hw = &adapter->hw;
1734 u32 icr = er32(ICR);
1735
e921eb1a 1736 /* read ICR disables interrupts using IAM */
573cca8c 1737 if (icr & E1000_ICR_LSC) {
f92518dd 1738 hw->mac.get_link_status = true;
e921eb1a 1739 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1740 * disconnect (LSC) before accessing any PHY registers
1741 */
bc7f75fa
AK		 1742 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1743 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1744 schedule_work(&adapter->downshift_task);
bc7f75fa 1745
e921eb1a 1746 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1747 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1748 * adapter in watchdog
1749 */
bc7f75fa
AK		 1750 if (netif_carrier_ok(netdev) &&
1751 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1752 /* disable receives */
1753 u32 rctl = er32(RCTL);
1754 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1755 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1756 }
1757 /* guard against interrupt when we're going down */
1758 if (!test_bit(__E1000_DOWN, &adapter->state))
1759 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1760 }
1761
94fb848b
BA		 1762 /* Reset on uncorrectable ECC error */
1763 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1764 u32 pbeccsts = er32(PBECCSTS);
1765
1766 adapter->corr_errors +=
1767 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1768 adapter->uncorr_errors +=
1769 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1770 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1771
1772 /* Do the reset outside of interrupt context */
1773 schedule_work(&adapter->reset_task);
1774
1775 /* return immediately since reset is imminent */
1776 return IRQ_HANDLED;
1777 }
1778
288379f0 1779 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1780 adapter->total_tx_bytes = 0;
1781 adapter->total_tx_packets = 0;
1782 adapter->total_rx_bytes = 0;
1783 adapter->total_rx_packets = 0;
288379f0 1784 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1785 }
1786
1787 return IRQ_HANDLED;
1788}
1789
1790/**
1791 * e1000_intr - Interrupt Handler
1792 * @irq: interrupt number
1793 * @data: pointer to a network interface device structure
1794 **/
8bb62869 1795static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1796{
1797 struct net_device *netdev = data;
1798 struct e1000_adapter *adapter = netdev_priv(netdev);
1799 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1800 u32 rctl, icr = er32(ICR);
4662e82b 1801
a68ea775 1802 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1803 return IRQ_NONE; /* Not our interrupt */
1804
e921eb1a 1805 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1806 * not set, then the adapter didn't send an interrupt
1807 */
bc7f75fa
AK		 1808 if (!(icr & E1000_ICR_INT_ASSERTED))
1809 return IRQ_NONE;
1810
e921eb1a 1811 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1812 * interrupts are masked. No need for the
1813 * IMC write
1814 */
bc7f75fa 1815
573cca8c 1816 if (icr & E1000_ICR_LSC) {
f92518dd 1817 hw->mac.get_link_status = true;
e921eb1a 1818 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1819 * disconnect (LSC) before accessing any PHY registers
1820 */
bc7f75fa
AK		 1821 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1822 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1823 schedule_work(&adapter->downshift_task);
bc7f75fa 1824
e921eb1a 1825 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1826 * For packet buffer work-around on link down event;
1827 * disable receives here in the ISR and
1828 * reset adapter in watchdog
1829 */
1830 if (netif_carrier_ok(netdev) &&
1831 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1832 /* disable receives */
1833 rctl = er32(RCTL);
1834 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1835 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1836 }
1837 /* guard against interrupt when we're going down */
1838 if (!test_bit(__E1000_DOWN, &adapter->state))
1839 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1840 }
1841
94fb848b
BA		 1842 /* Reset on uncorrectable ECC error */
1843 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1844 u32 pbeccsts = er32(PBECCSTS);
1845
1846 adapter->corr_errors +=
1847 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1848 adapter->uncorr_errors +=
1849 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1850 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1851
1852 /* Do the reset outside of interrupt context */
1853 schedule_work(&adapter->reset_task);
1854
1855 /* return immediately since reset is imminent */
1856 return IRQ_HANDLED;
1857 }
1858
288379f0 1859 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1860 adapter->total_tx_bytes = 0;
1861 adapter->total_tx_packets = 0;
1862 adapter->total_rx_bytes = 0;
1863 adapter->total_rx_packets = 0;
288379f0 1864 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1865 }
1866
1867 return IRQ_HANDLED;
1868}
1869
8bb62869 1870static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1871{
1872 struct net_device *netdev = data;
1873 struct e1000_adapter *adapter = netdev_priv(netdev);
1874 struct e1000_hw *hw = &adapter->hw;
1875 u32 icr = er32(ICR);
1876
1877 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1878 if (!test_bit(__E1000_DOWN, &adapter->state))
1879 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1880 return IRQ_NONE;
1881 }
1882
1883 if (icr & adapter->eiac_mask)
1884 ew32(ICS, (icr & adapter->eiac_mask));
1885
1886 if (icr & E1000_ICR_OTHER) {
1887 if (!(icr & E1000_ICR_LSC))
1888 goto no_link_interrupt;
f92518dd 1889 hw->mac.get_link_status = true;
4662e82b
BA		 1890 /* guard against interrupt when we're going down */
1891 if (!test_bit(__E1000_DOWN, &adapter->state))
1892 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1893 }
1894
1895no_link_interrupt:
a3c69fef
JB		 1896 if (!test_bit(__E1000_DOWN, &adapter->state))
1897 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1898
1899 return IRQ_HANDLED;
1900}
1901
8bb62869 1902static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1903{
1904 struct net_device *netdev = data;
1905 struct e1000_adapter *adapter = netdev_priv(netdev);
1906 struct e1000_hw *hw = &adapter->hw;
1907 struct e1000_ring *tx_ring = adapter->tx_ring;
1908
4662e82b
BA		 1909 adapter->total_tx_bytes = 0;
1910 adapter->total_tx_packets = 0;
1911
55aa6985 1912 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1913 /* Ring was not completely cleaned, so fire another interrupt */
1914 ew32(ICS, tx_ring->ims_val);
1915
1916 return IRQ_HANDLED;
1917}
1918
8bb62869 1919static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1920{
1921 struct net_device *netdev = data;
1922 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1923 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1924
1925 /* Write the ITR value calculated at the end of the
1926 * previous interrupt.
1927 */
55aa6985
BA		 1928 if (rx_ring->set_itr) {
1929 writel(1000000000 / (rx_ring->itr_val * 256),
1930 rx_ring->itr_register);
1931 rx_ring->set_itr = 0;
4662e82b
BA		 1932 }
1933
288379f0 1934 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1935 adapter->total_rx_bytes = 0;
1936 adapter->total_rx_packets = 0;
288379f0 1937 __napi_schedule(&adapter->napi);
4662e82b
BA		 1938 }
1939 return IRQ_HANDLED;
1940}
1941
1942/**
1943 * e1000_configure_msix - Configure MSI-X hardware
1944 *
1945 * e1000_configure_msix sets up the hardware to properly
1946 * generate MSI-X interrupts.
1947 **/
1948static void e1000_configure_msix(struct e1000_adapter *adapter)
1949{
1950 struct e1000_hw *hw = &adapter->hw;
1951 struct e1000_ring *rx_ring = adapter->rx_ring;
1952 struct e1000_ring *tx_ring = adapter->tx_ring;
1953 int vector = 0;
1954 u32 ctrl_ext, ivar = 0;
1955
1956 adapter->eiac_mask = 0;
1957
1958 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1959 if (hw->mac.type == e1000_82574) {
1960 u32 rfctl = er32(RFCTL);
1961 rfctl |= E1000_RFCTL_ACK_DIS;
1962 ew32(RFCTL, rfctl);
1963 }
1964
4662e82b
BA		 1965 /* Configure Rx vector */
1966 rx_ring->ims_val = E1000_IMS_RXQ0;
1967 adapter->eiac_mask |= rx_ring->ims_val;
1968 if (rx_ring->itr_val)
1969 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1970 rx_ring->itr_register);
4662e82b 1971 else
c5083cf6 1972 writel(1, rx_ring->itr_register);
4662e82b
BA		 1973 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1974
1975 /* Configure Tx vector */
1976 tx_ring->ims_val = E1000_IMS_TXQ0;
1977 vector++;
1978 if (tx_ring->itr_val)
1979 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1980 tx_ring->itr_register);
4662e82b 1981 else
c5083cf6 1982 writel(1, tx_ring->itr_register);
4662e82b
BA		 1983 adapter->eiac_mask |= tx_ring->ims_val;
1984 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1985
1986 /* set vector for Other Causes, e.g. link changes */
1987 vector++;
1988 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1989 if (rx_ring->itr_val)
1990 writel(1000000000 / (rx_ring->itr_val * 256),
1991 hw->hw_addr + E1000_EITR_82574(vector));
1992 else
1993 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1994
1995 /* Cause Tx interrupts on every write back */
1996 ivar |= (1 << 31);
1997
1998 ew32(IVAR, ivar);
1999
2000 /* enable MSI-X PBA support */
2001 ctrl_ext = er32(CTRL_EXT);
2002 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2003
2004 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2005 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2006 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2007 ew32(CTRL_EXT, ctrl_ext);
2008 e1e_flush();
2009}
2010
2011void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2012{
2013 if (adapter->msix_entries) {
2014 pci_disable_msix(adapter->pdev);
2015 kfree(adapter->msix_entries);
2016 adapter->msix_entries = NULL;
2017 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2018 pci_disable_msi(adapter->pdev);
2019 adapter->flags &= ~FLAG_MSI_ENABLED;
2020 }
4662e82b
BA		 2021}
2022
2023/**
2024 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2025 *
2026 * Attempt to configure interrupts using the best available
2027 * capabilities of the hardware and kernel.
2028 **/
2029void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2030{
2031 int err;
8e86acd7 2032 int i;
4662e82b
BA		 2033
2034 switch (adapter->int_mode) {
2035 case E1000E_INT_MODE_MSIX:
2036 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2037 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2038 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2039 sizeof(struct
2040 msix_entry),
2041 GFP_KERNEL);
4662e82b 2042 if (adapter->msix_entries) {
8e86acd7 2043 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2044 adapter->msix_entries[i].entry = i;
2045
2046 err = pci_enable_msix(adapter->pdev,
2047 adapter->msix_entries,
8e86acd7 2048 adapter->num_vectors);
b1cdfead 2049 if (err == 0)
4662e82b
BA		 2050 return;
2051 }
2052 /* MSI-X failed, so fall through and try MSI */
ef456f85 2053 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2054 e1000e_reset_interrupt_capability(adapter);
2055 }
2056 adapter->int_mode = E1000E_INT_MODE_MSI;
2057 /* Fall through */
2058 case E1000E_INT_MODE_MSI:
2059 if (!pci_enable_msi(adapter->pdev)) {
2060 adapter->flags |= FLAG_MSI_ENABLED;
2061 } else {
2062 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2063 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2064 }
2065 /* Fall through */
2066 case E1000E_INT_MODE_LEGACY:
2067 /* Don't do anything; this is the system default */
2068 break;
2069 }
8e86acd7
JK		 2070
2071 /* store the number of vectors being used */
2072 adapter->num_vectors = 1;
4662e82b
BA		 2073}
2074
2075/**
2076 * e1000_request_msix - Initialize MSI-X interrupts
2077 *
2078 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2079 * kernel.
2080 **/
2081static int e1000_request_msix(struct e1000_adapter *adapter)
2082{
2083 struct net_device *netdev = adapter->netdev;
2084 int err = 0, vector = 0;
2085
2086 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2087 snprintf(adapter->rx_ring->name,
2088 sizeof(adapter->rx_ring->name) - 1,
2089 "%s-rx-0", netdev->name);
4662e82b
BA		 2090 else
2091 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2092 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2093 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2094 netdev);
2095 if (err)
5015e53a 2096 return err;
c5083cf6
BA		 2097 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2098 E1000_EITR_82574(vector);
4662e82b
BA		 2099 adapter->rx_ring->itr_val = adapter->itr;
2100 vector++;
2101
2102 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2103 snprintf(adapter->tx_ring->name,
2104 sizeof(adapter->tx_ring->name) - 1,
2105 "%s-tx-0", netdev->name);
4662e82b
BA		 2106 else
2107 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2108 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2109 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2110 netdev);
2111 if (err)
5015e53a 2112 return err;
c5083cf6
BA		 2113 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2114 E1000_EITR_82574(vector);
4662e82b
BA		 2115 adapter->tx_ring->itr_val = adapter->itr;
2116 vector++;
2117
2118 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2119 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2120 if (err)
5015e53a 2121 return err;
4662e82b
BA		 2122
2123 e1000_configure_msix(adapter);
5015e53a 2124
4662e82b 2125 return 0;
4662e82b
BA		 2126}
2127
f8d59f78
BA		 2128/**
2129 * e1000_request_irq - initialize interrupts
2130 *
2131 * Attempts to configure interrupts using the best available
2132 * capabilities of the hardware and kernel.
2133 **/
bc7f75fa
AK		 2134static int e1000_request_irq(struct e1000_adapter *adapter)
2135{
2136 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2137 int err;
2138
4662e82b
BA		 2139 if (adapter->msix_entries) {
2140 err = e1000_request_msix(adapter);
2141 if (!err)
2142 return err;
2143 /* fall back to MSI */
2144 e1000e_reset_interrupt_capability(adapter);
2145 adapter->int_mode = E1000E_INT_MODE_MSI;
2146 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2147 }
4662e82b 2148 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2149 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2150 netdev->name, netdev);
2151 if (!err)
2152 return err;
bc7f75fa 2153
4662e82b
BA		 2154 /* fall back to legacy interrupt */
2155 e1000e_reset_interrupt_capability(adapter);
2156 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2157 }
2158
a0607fd3 2159 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2160 netdev->name, netdev);
2161 if (err)
2162 e_err("Unable to allocate interrupt, Error: %d\n", err);
2163
bc7f75fa
AK		 2164 return err;
2165}
2166
2167static void e1000_free_irq(struct e1000_adapter *adapter)
2168{
2169 struct net_device *netdev = adapter->netdev;
2170
4662e82b
BA		 2171 if (adapter->msix_entries) {
2172 int vector = 0;
2173
2174 free_irq(adapter->msix_entries[vector].vector, netdev);
2175 vector++;
2176
2177 free_irq(adapter->msix_entries[vector].vector, netdev);
2178 vector++;
2179
2180 /* Other Causes interrupt vector */
2181 free_irq(adapter->msix_entries[vector].vector, netdev);
2182 return;
bc7f75fa 2183 }
4662e82b
BA		 2184
2185 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2186}
2187
2188/**
2189 * e1000_irq_disable - Mask off interrupt generation on the NIC
2190 **/
2191static void e1000_irq_disable(struct e1000_adapter *adapter)
2192{
2193 struct e1000_hw *hw = &adapter->hw;
2194
bc7f75fa 2195 ew32(IMC, ~0);
4662e82b
BA		 2196 if (adapter->msix_entries)
2197 ew32(EIAC_82574, 0);
bc7f75fa 2198 e1e_flush();
8e86acd7
JK		 2199
2200 if (adapter->msix_entries) {
2201 int i;
2202 for (i = 0; i < adapter->num_vectors; i++)
2203 synchronize_irq(adapter->msix_entries[i].vector);
2204 } else {
2205 synchronize_irq(adapter->pdev->irq);
2206 }
bc7f75fa
AK		 2207}
2208
2209/**
2210 * e1000_irq_enable - Enable default interrupt generation settings
2211 **/
2212static void e1000_irq_enable(struct e1000_adapter *adapter)
2213{
2214 struct e1000_hw *hw = &adapter->hw;
2215
4662e82b
BA		 2216 if (adapter->msix_entries) {
2217 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2218 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2219 } else if (hw->mac.type == e1000_pch_lpt) {
2220 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2221 } else {
2222 ew32(IMS, IMS_ENABLE_MASK);
2223 }
74ef9c39 2224 e1e_flush();
bc7f75fa
AK		 2225}
2226
2227/**
31dbe5b4 2228 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2229 * @adapter: address of board private structure
2230 *
31dbe5b4 2231 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2232 * For ASF and Pass Through versions of f/w this means that
2233 * the driver is loaded. For AMT version (only with 82573)
2234 * of the f/w this means that the network i/f is open.
2235 **/
31dbe5b4 2236void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2237{
2238 struct e1000_hw *hw = &adapter->hw;
2239 u32 ctrl_ext;
2240 u32 swsm;
2241
2242 /* Let firmware know the driver has taken over */
2243 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2244 swsm = er32(SWSM);
2245 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2246 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2247 ctrl_ext = er32(CTRL_EXT);
ad68076e 2248 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2249 }
2250}
2251
2252/**
31dbe5b4 2253 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2254 * @adapter: address of board private structure
2255 *
31dbe5b4 2256 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2257 * For ASF and Pass Through versions of f/w this means that the
2258 * driver is no longer loaded. For AMT version (only with 82573) i
2259 * of the f/w this means that the network i/f is closed.
2260 *
2261 **/
31dbe5b4 2262void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2263{
2264 struct e1000_hw *hw = &adapter->hw;
2265 u32 ctrl_ext;
2266 u32 swsm;
2267
2268 /* Let firmware taken over control of h/w */
2269 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2270 swsm = er32(SWSM);
2271 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2272 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2273 ctrl_ext = er32(CTRL_EXT);
ad68076e 2274 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2275 }
2276}
2277
bc7f75fa 2278/**
49ce9c2c 2279 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2280 **/
2281static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2282 struct e1000_ring *ring)
2283{
2284 struct pci_dev *pdev = adapter->pdev;
2285
2286 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2287 GFP_KERNEL);
2288 if (!ring->desc)
2289 return -ENOMEM;
2290
2291 return 0;
2292}
2293
2294/**
2295 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2296 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2297 *
2298 * Return 0 on success, negative on failure
2299 **/
55aa6985 2300int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2301{
55aa6985 2302 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2303 int err = -ENOMEM, size;
2304
2305 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2306 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2307 if (!tx_ring->buffer_info)
2308 goto err;
bc7f75fa
AK		 2309
2310 /* round up to nearest 4K */
2311 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2312 tx_ring->size = ALIGN(tx_ring->size, 4096);
2313
2314 err = e1000_alloc_ring_dma(adapter, tx_ring);
2315 if (err)
2316 goto err;
2317
2318 tx_ring->next_to_use = 0;
2319 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2320
2321 return 0;
2322err:
2323 vfree(tx_ring->buffer_info);
44defeb3 2324 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2325 return err;
2326}
2327
2328/**
2329 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2330 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2331 *
2332 * Returns 0 on success, negative on failure
2333 **/
55aa6985 2334int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2335{
55aa6985 2336 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2337 struct e1000_buffer *buffer_info;
2338 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2339
2340 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2341 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2342 if (!rx_ring->buffer_info)
2343 goto err;
bc7f75fa 2344
47f44e40
AK		 2345 for (i = 0; i < rx_ring->count; i++) {
2346 buffer_info = &rx_ring->buffer_info[i];
2347 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2348 sizeof(struct e1000_ps_page),
2349 GFP_KERNEL);
2350 if (!buffer_info->ps_pages)
2351 goto err_pages;
2352 }
bc7f75fa
AK		 2353
2354 desc_len = sizeof(union e1000_rx_desc_packet_split);
2355
2356 /* Round up to nearest 4K */
2357 rx_ring->size = rx_ring->count * desc_len;
2358 rx_ring->size = ALIGN(rx_ring->size, 4096);
2359
2360 err = e1000_alloc_ring_dma(adapter, rx_ring);
2361 if (err)
47f44e40 2362 goto err_pages;
bc7f75fa
AK		 2363
2364 rx_ring->next_to_clean = 0;
2365 rx_ring->next_to_use = 0;
2366 rx_ring->rx_skb_top = NULL;
2367
2368 return 0;
47f44e40
AK		 2369
2370err_pages:
2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 kfree(buffer_info->ps_pages);
2374 }
bc7f75fa
AK		 2375err:
2376 vfree(rx_ring->buffer_info);
e9262447 2377 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2378 return err;
2379}
2380
2381/**
2382 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2383 * @tx_ring: Tx descriptor ring
bc7f75fa 2384 **/
55aa6985 2385static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2386{
55aa6985 2387 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2388 struct e1000_buffer *buffer_info;
2389 unsigned long size;
2390 unsigned int i;
2391
2392 for (i = 0; i < tx_ring->count; i++) {
2393 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2394 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2395 }
2396
3f0cfa3b 2397 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2398 size = sizeof(struct e1000_buffer) * tx_ring->count;
2399 memset(tx_ring->buffer_info, 0, size);
2400
2401 memset(tx_ring->desc, 0, tx_ring->size);
2402
2403 tx_ring->next_to_use = 0;
2404 tx_ring->next_to_clean = 0;
2405
c5083cf6 2406 writel(0, tx_ring->head);
bdc125f7
BA		 2407 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2408 e1000e_update_tdt_wa(tx_ring, 0);
2409 else
2410 writel(0, tx_ring->tail);
bc7f75fa
AK		 2411}
2412
2413/**
2414 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2415 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2416 *
2417 * Free all transmit software resources
2418 **/
55aa6985 2419void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2420{
55aa6985 2421 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2422 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2423
55aa6985 2424 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2425
2426 vfree(tx_ring->buffer_info);
2427 tx_ring->buffer_info = NULL;
2428
2429 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2430 tx_ring->dma);
2431 tx_ring->desc = NULL;
2432}
2433
2434/**
2435 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2436 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2437 *
2438 * Free all receive software resources
2439 **/
55aa6985 2440void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2441{
55aa6985 2442 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2443 struct pci_dev *pdev = adapter->pdev;
47f44e40 2444 int i;
bc7f75fa 2445
55aa6985 2446 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2447
b1cdfead 2448 for (i = 0; i < rx_ring->count; i++)
47f44e40 2449 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2450
bc7f75fa
AK		 2451 vfree(rx_ring->buffer_info);
2452 rx_ring->buffer_info = NULL;
2453
bc7f75fa
AK		 2454 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2455 rx_ring->dma);
2456 rx_ring->desc = NULL;
2457}
2458
2459/**
2460 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2461 * @adapter: pointer to adapter
2462 * @itr_setting: current adapter->itr
2463 * @packets: the number of packets during this measurement interval
2464 * @bytes: the number of bytes during this measurement interval
2465 *
bc7f75fa
AK		 2466 * Stores a new ITR value based on packets and byte
2467 * counts during the last interrupt. The advantage of per interrupt
2468 * computation is faster updates and more accurate ITR for the current
2469 * traffic pattern. Constants in this function were computed
2470 * based on theoretical maximum wire speed and thresholds were set based
2471 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2472 * while increasing bulk throughput. This functionality is controlled
2473 * by the InterruptThrottleRate module parameter.
bc7f75fa 2474 **/
8bb62869 2475static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2476{
2477 unsigned int retval = itr_setting;
2478
2479 if (packets == 0)
5015e53a 2480 return itr_setting;
bc7f75fa
AK		 2481
2482 switch (itr_setting) {
2483 case lowest_latency:
2484 /* handle TSO and jumbo frames */
362e20ca 2485 if (bytes / packets > 8000)
bc7f75fa 2486 retval = bulk_latency;
b1cdfead 2487 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2488 retval = low_latency;
bc7f75fa
AK		 2489 break;
2490 case low_latency: /* 50 usec aka 20000 ints/s */
2491 if (bytes > 10000) {
2492 /* this if handles the TSO accounting */
362e20ca 2493 if (bytes / packets > 8000)
bc7f75fa 2494 retval = bulk_latency;
362e20ca 2495 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2496 retval = bulk_latency;
b1cdfead 2497 else if ((packets > 35))
bc7f75fa 2498 retval = lowest_latency;
362e20ca 2499 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2500 retval = bulk_latency;
2501 } else if (packets <= 2 && bytes < 512) {
2502 retval = lowest_latency;
2503 }
2504 break;
2505 case bulk_latency: /* 250 usec aka 4000 ints/s */
2506 if (bytes > 25000) {
b1cdfead 2507 if (packets > 35)
bc7f75fa 2508 retval = low_latency;
bc7f75fa
AK		 2509 } else if (bytes < 6000) {
2510 retval = low_latency;
2511 }
2512 break;
2513 }
2514
bc7f75fa
AK		 2515 return retval;
2516}
2517
2518static void e1000_set_itr(struct e1000_adapter *adapter)
2519{
bc7f75fa
AK		 2520 u16 current_itr;
2521 u32 new_itr = adapter->itr;
2522
2523 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2524 if (adapter->link_speed != SPEED_1000) {
2525 current_itr = 0;
2526 new_itr = 4000;
2527 goto set_itr_now;
2528 }
2529
828bac87
BA		 2530 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2531 new_itr = 0;
2532 goto set_itr_now;
2533 }
2534
8bb62869
BA		 2535 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2536 adapter->total_tx_packets,
2537 adapter->total_tx_bytes);
bc7f75fa
AK		 2538 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2539 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2540 adapter->tx_itr = low_latency;
2541
8bb62869
BA		 2542 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2543 adapter->total_rx_packets,
2544 adapter->total_rx_bytes);
bc7f75fa
AK		 2545 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2546 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2547 adapter->rx_itr = low_latency;
2548
2549 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2550
bc7f75fa 2551 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2552 switch (current_itr) {
bc7f75fa
AK		 2553 case lowest_latency:
2554 new_itr = 70000;
2555 break;
2556 case low_latency:
2557 new_itr = 20000; /* aka hwitr = ~200 */
2558 break;
2559 case bulk_latency:
2560 new_itr = 4000;
2561 break;
2562 default:
2563 break;
2564 }
2565
2566set_itr_now:
2567 if (new_itr != adapter->itr) {
e921eb1a 2568 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2569 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2570 * increasing
2571 */
bc7f75fa 2572 new_itr = new_itr > adapter->itr ?
f0ff4398 2573 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2574 adapter->itr = new_itr;
4662e82b
BA		 2575 adapter->rx_ring->itr_val = new_itr;
2576 if (adapter->msix_entries)
2577 adapter->rx_ring->set_itr = 1;
2578 else
e3d14b08 2579 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2580 }
2581}
2582
22a4cca2
MV		 2583/**
2584 * e1000e_write_itr - write the ITR value to the appropriate registers
2585 * @adapter: address of board private structure
2586 * @itr: new ITR value to program
2587 *
2588 * e1000e_write_itr determines if the adapter is in MSI-X mode
2589 * and, if so, writes the EITR registers with the ITR value.
2590 * Otherwise, it writes the ITR value into the ITR register.
2591 **/
2592void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2593{
2594 struct e1000_hw *hw = &adapter->hw;
2595 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2596
2597 if (adapter->msix_entries) {
2598 int vector;
2599
2600 for (vector = 0; vector < adapter->num_vectors; vector++)
2601 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2602 } else {
2603 ew32(ITR, new_itr);
2604 }
2605}
2606
4662e82b
BA		 2607/**
2608 * e1000_alloc_queues - Allocate memory for all rings
2609 * @adapter: board private structure to initialize
2610 **/
9f9a12f8 2611static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2612{
55aa6985
BA		 2613 int size = sizeof(struct e1000_ring);
2614
2615 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2616 if (!adapter->tx_ring)
2617 goto err;
55aa6985
BA		 2618 adapter->tx_ring->count = adapter->tx_ring_count;
2619 adapter->tx_ring->adapter = adapter;
4662e82b 2620
55aa6985 2621 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2622 if (!adapter->rx_ring)
2623 goto err;
55aa6985
BA		 2624 adapter->rx_ring->count = adapter->rx_ring_count;
2625 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2626
2627 return 0;
2628err:
2629 e_err("Unable to allocate memory for queues\n");
2630 kfree(adapter->rx_ring);
2631 kfree(adapter->tx_ring);
2632 return -ENOMEM;
2633}
2634
bc7f75fa 2635/**
c58c8a78 2636 * e1000e_poll - NAPI Rx polling callback
ad68076e 2637 * @napi: struct associated with this polling callback
c58c8a78 2638 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2639 **/
c58c8a78 2640static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2641{
c58c8a78
BA		 2642 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2643 napi);
4662e82b 2644 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2645 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2646 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2647
4cf1653a 2648 adapter = netdev_priv(poll_dev);
bc7f75fa 2649
c58c8a78
BA		 2650 if (!adapter->msix_entries ||
2651 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2652 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2653
c58c8a78 2654 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2655
12d04a3c 2656 if (!tx_cleaned)
c58c8a78 2657 work_done = weight;
bc7f75fa 2658
c58c8a78
BA		 2659 /* If weight not fully consumed, exit the polling mode */
2660 if (work_done < weight) {
bc7f75fa
AK		 2661 if (adapter->itr_setting & 3)
2662 e1000_set_itr(adapter);
288379f0 2663 napi_complete(napi);
a3c69fef
JB		 2664 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2665 if (adapter->msix_entries)
2666 ew32(IMS, adapter->rx_ring->ims_val);
2667 else
2668 e1000_irq_enable(adapter);
2669 }
bc7f75fa
AK		 2670 }
2671
2672 return work_done;
2673}
2674
8e586137 2675static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2676{
2677 struct e1000_adapter *adapter = netdev_priv(netdev);
2678 struct e1000_hw *hw = &adapter->hw;
2679 u32 vfta, index;
2680
2681 /* don't update vlan cookie if already programmed */
2682 if ((adapter->hw.mng_cookie.status &
2683 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2684 (vid == adapter->mng_vlan_id))
8e586137 2685 return 0;
caaddaf8 2686
bc7f75fa 2687 /* add VID to filter table */
caaddaf8
BA		 2688 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2689 index = (vid >> 5) & 0x7F;
2690 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2691 vfta |= (1 << (vid & 0x1F));
2692 hw->mac.ops.write_vfta(hw, index, vfta);
2693 }
86d70e53
JK		 2694
2695 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2696
2697 return 0;
bc7f75fa
AK		 2698}
2699
8e586137 2700static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2701{
2702 struct e1000_adapter *adapter = netdev_priv(netdev);
2703 struct e1000_hw *hw = &adapter->hw;
2704 u32 vfta, index;
2705
bc7f75fa
AK		 2706 if ((adapter->hw.mng_cookie.status &
2707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2708 (vid == adapter->mng_vlan_id)) {
2709 /* release control to f/w */
31dbe5b4 2710 e1000e_release_hw_control(adapter);
8e586137 2711 return 0;
bc7f75fa
AK		 2712 }
2713
2714 /* remove VID from filter table */
caaddaf8
BA		 2715 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2716 index = (vid >> 5) & 0x7F;
2717 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2718 vfta &= ~(1 << (vid & 0x1F));
2719 hw->mac.ops.write_vfta(hw, index, vfta);
2720 }
86d70e53
JK		 2721
2722 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2723
2724 return 0;
bc7f75fa
AK		 2725}
2726
86d70e53
JK		 2727/**
2728 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2729 * @adapter: board private structure to initialize
2730 **/
2731static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2732{
2733 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2734 struct e1000_hw *hw = &adapter->hw;
2735 u32 rctl;
bc7f75fa 2736
86d70e53
JK		 2737 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2738 /* disable VLAN receive filtering */
2739 rctl = er32(RCTL);
2740 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2741 ew32(RCTL, rctl);
2742
2743 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2744 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2745 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2746 }
bc7f75fa
AK		 2747 }
2748}
2749
86d70e53
JK		 2750/**
2751 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2752 * @adapter: board private structure to initialize
2753 **/
2754static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2755{
2756 struct e1000_hw *hw = &adapter->hw;
2757 u32 rctl;
2758
2759 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2760 /* enable VLAN receive filtering */
2761 rctl = er32(RCTL);
2762 rctl |= E1000_RCTL_VFE;
2763 rctl &= ~E1000_RCTL_CFIEN;
2764 ew32(RCTL, rctl);
2765 }
2766}
bc7f75fa 2767
86d70e53
JK		 2768/**
2769 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2770 * @adapter: board private structure to initialize
2771 **/
2772static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2773{
bc7f75fa 2774 struct e1000_hw *hw = &adapter->hw;
86d70e53 2775 u32 ctrl;
bc7f75fa 2776
86d70e53
JK		 2777 /* disable VLAN tag insert/strip */
2778 ctrl = er32(CTRL);
2779 ctrl &= ~E1000_CTRL_VME;
2780 ew32(CTRL, ctrl);
2781}
bc7f75fa 2782
86d70e53
JK		 2783/**
2784 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2785 * @adapter: board private structure to initialize
2786 **/
2787static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2788{
2789 struct e1000_hw *hw = &adapter->hw;
2790 u32 ctrl;
bc7f75fa 2791
86d70e53
JK		 2792 /* enable VLAN tag insert/strip */
2793 ctrl = er32(CTRL);
2794 ctrl |= E1000_CTRL_VME;
2795 ew32(CTRL, ctrl);
2796}
bc7f75fa 2797
86d70e53
JK		 2798static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2799{
2800 struct net_device *netdev = adapter->netdev;
2801 u16 vid = adapter->hw.mng_cookie.vlan_id;
2802 u16 old_vid = adapter->mng_vlan_id;
2803
e5fe2541 2804 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
86d70e53
JK		 2805 e1000_vlan_rx_add_vid(netdev, vid);
2806 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2807 }
2808
86d70e53
JK		 2809 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2810 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2811}
2812
2813static void e1000_restore_vlan(struct e1000_adapter *adapter)
2814{
2815 u16 vid;
2816
86d70e53 2817 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2818
86d70e53 2819 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
f0ff4398 2820 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2821}
2822
cd791618 2823static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2824{
2825 struct e1000_hw *hw = &adapter->hw;
cd791618 2826 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2827
2828 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2829 return;
2830
2831 manc = er32(MANC);
2832
e921eb1a 2833 /* enable receiving management packets to the host. this will probably
bc7f75fa 2834 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2835 * the packets will be handled on SMBUS
2836 */
bc7f75fa
AK		 2837 manc |= E1000_MANC_EN_MNG2HOST;
2838 manc2h = er32(MANC2H);
cd791618
BA		 2839
2840 switch (hw->mac.type) {
2841 default:
2842 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2843 break;
2844 case e1000_82574:
2845 case e1000_82583:
e921eb1a 2846 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2847 * if so, enable it.
2848 */
2849 for (i = 0, j = 0; i < 8; i++) {
2850 mdef = er32(MDEF(i));
2851
2852 /* Ignore filters with anything other than IPMI ports */
3b21b508 2853 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2854 continue;
2855
2856 /* Enable this decision filter in MANC2H */
2857 if (mdef)
2858 manc2h |= (1 << i);
2859
2860 j |= mdef;
2861 }
2862
2863 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2864 break;
2865
2866 /* Create new decision filter in an empty filter */
2867 for (i = 0, j = 0; i < 8; i++)
2868 if (er32(MDEF(i)) == 0) {
2869 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2870 E1000_MDEF_PORT_664));
2871 manc2h |= (1 << 1);
2872 j++;
2873 break;
2874 }
2875
2876 if (!j)
2877 e_warn("Unable to create IPMI pass-through filter\n");
2878 break;
2879 }
2880
bc7f75fa
AK		 2881 ew32(MANC2H, manc2h);
2882 ew32(MANC, manc);
2883}
2884
2885/**
af667a29 2886 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2887 * @adapter: board private structure
2888 *
2889 * Configure the Tx unit of the MAC after a reset.
2890 **/
2891static void e1000_configure_tx(struct e1000_adapter *adapter)
2892{
2893 struct e1000_hw *hw = &adapter->hw;
2894 struct e1000_ring *tx_ring = adapter->tx_ring;
2895 u64 tdba;
c550b121 2896 u32 tdlen, tarc;
bc7f75fa
AK		 2897
2898 /* Setup the HW Tx Head and Tail descriptor pointers */
2899 tdba = tx_ring->dma;
2900 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2901 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2902 ew32(TDBAH(0), (tdba >> 32));
2903 ew32(TDLEN(0), tdlen);
2904 ew32(TDH(0), 0);
2905 ew32(TDT(0), 0);
2906 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2907 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2908
bc7f75fa
AK		 2909 /* Set the Tx Interrupt Delay register */
2910 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2911 /* Tx irq moderation */
bc7f75fa
AK		 2912 ew32(TADV, adapter->tx_abs_int_delay);
2913
3a3b7586
JB		 2914 if (adapter->flags2 & FLAG2_DMA_BURST) {
2915 u32 txdctl = er32(TXDCTL(0));
2916 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2917 E1000_TXDCTL_WTHRESH);
e921eb1a 2918 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2919 * hardware to use the bus more efficiently in bursts, depends
2920 * on the tx_int_delay to be enabled,
8edc0e62 2921 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2922 * hthresh = 1 ==> prefetch when one or more available
2923 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2924 * BEWARE: this seems to work but should be considered first if
af667a29 2925 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2926 */
2927 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2928 ew32(TXDCTL(0), txdctl);
3a3b7586 2929 }
56032be7
BA		 2930 /* erratum work around: set txdctl the same for both queues */
2931 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2932
bc7f75fa 2933 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2934 tarc = er32(TARC(0));
e921eb1a 2935 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2936 * gigabit link later
2937 */
bc7f75fa
AK		 2938#define SPEED_MODE_BIT (1 << 21)
2939 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2940 ew32(TARC(0), tarc);
bc7f75fa
AK		 2941 }
2942
2943 /* errata: program both queues to unweighted RR */
2944 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2945 tarc = er32(TARC(0));
bc7f75fa 2946 tarc |= 1;
e9ec2c0f
JK		 2947 ew32(TARC(0), tarc);
2948 tarc = er32(TARC(1));
bc7f75fa 2949 tarc |= 1;
e9ec2c0f 2950 ew32(TARC(1), tarc);
bc7f75fa
AK		 2951 }
2952
bc7f75fa
AK		 2953 /* Setup Transmit Descriptor Settings for eop descriptor */
2954 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2955
2956 /* only set IDE if we are delaying interrupts using the timers */
2957 if (adapter->tx_int_delay)
2958 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2959
2960 /* enable Report Status bit */
2961 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2962
57cde763 2963 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2964}
2965
2966/**
2967 * e1000_setup_rctl - configure the receive control registers
2968 * @adapter: Board private structure
2969 **/
2970#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2971 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2972static void e1000_setup_rctl(struct e1000_adapter *adapter)
2973{
2974 struct e1000_hw *hw = &adapter->hw;
2975 u32 rctl, rfctl;
bc7f75fa
AK		 2976 u32 pages = 0;
2977
2fbe4526
BA		 2978 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2979 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2980 s32 ret_val;
2981
2982 if (adapter->netdev->mtu > ETH_DATA_LEN)
2983 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2984 else
2985 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2986
2987 if (ret_val)
2988 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2989 }
2990
bc7f75fa
AK		 2991 /* Program MC offset vector base */
2992 rctl = er32(RCTL);
2993 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2994 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 2995 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2996 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 2997
2998 /* Do not Store bad packets */
2999 rctl &= ~E1000_RCTL_SBP;
3000
3001 /* Enable Long Packet receive */
3002 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3003 rctl &= ~E1000_RCTL_LPE;
3004 else
3005 rctl |= E1000_RCTL_LPE;
3006
eb7c3adb
JK		 3007 /* Some systems expect that the CRC is included in SMBUS traffic. The
3008 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3009 * host memory when this is enabled
3010 */
3011 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3012 rctl |= E1000_RCTL_SECRC;
5918bd88 3013
a4f58f54
BA		 3014 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3015 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3016 u16 phy_data;
3017
3018 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3019 phy_data &= 0xfff8;
3020 phy_data |= (1 << 2);
3021 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3022
3023 e1e_rphy(hw, 22, &phy_data);
3024 phy_data &= 0x0fff;
3025 phy_data |= (1 << 14);
3026 e1e_wphy(hw, 0x10, 0x2823);
3027 e1e_wphy(hw, 0x11, 0x0003);
3028 e1e_wphy(hw, 22, phy_data);
3029 }
3030
bc7f75fa
AK		 3031 /* Setup buffer sizes */
3032 rctl &= ~E1000_RCTL_SZ_4096;
3033 rctl |= E1000_RCTL_BSEX;
3034 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3035 case 2048:
3036 default:
3037 rctl |= E1000_RCTL_SZ_2048;
3038 rctl &= ~E1000_RCTL_BSEX;
3039 break;
3040 case 4096:
3041 rctl |= E1000_RCTL_SZ_4096;
3042 break;
3043 case 8192:
3044 rctl |= E1000_RCTL_SZ_8192;
3045 break;
3046 case 16384:
3047 rctl |= E1000_RCTL_SZ_16384;
3048 break;
3049 }
3050
5f450212
BA		 3051 /* Enable Extended Status in all Receive Descriptors */
3052 rfctl = er32(RFCTL);
3053 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3054 ew32(RFCTL, rfctl);
5f450212 3055
e921eb1a 3056 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3057 * header is placed in skb->data and the packet data is
3058 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3059 * In the case of a non-split, skb->data is linearly filled,
3060 * followed by the page buffers. Therefore, skb->data is
3061 * sized to hold the largest protocol header.
3062 *
3063 * allocations using alloc_page take too long for regular MTU
3064 * so only enable packet split for jumbo frames
3065 *
3066 * Using pages when the page size is greater than 16k wastes
3067 * a lot of memory, since we allocate 3 pages at all times
3068 * per packet.
3069 */
bc7f75fa 3070 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3071 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3072 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3073 else
3074 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3075
3076 if (adapter->rx_ps_pages) {
90da0669
BA		 3077 u32 psrctl = 0;
3078
140a7480
AK		 3079 /* Enable Packet split descriptors */
3080 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3081
e5fe2541 3082 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3083
3084 switch (adapter->rx_ps_pages) {
3085 case 3:
e5fe2541
BA		 3086 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3087 /* fall-through */
bc7f75fa 3088 case 2:
e5fe2541
BA		 3089 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3090 /* fall-through */
bc7f75fa 3091 case 1:
e5fe2541 3092 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3093 break;
3094 }
3095
3096 ew32(PSRCTL, psrctl);
3097 }
3098
cf955e6c
BG		 3099 /* This is useful for sniffing bad packets. */
3100 if (adapter->netdev->features & NETIF_F_RXALL) {
3101 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3102 * in e1000e_set_rx_mode
3103 */
cf955e6c
BG		 3104 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3105 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3106 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3107
3108 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3109 E1000_RCTL_DPF | /* Allow filtered pause */
3110 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3111 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3112 * and that breaks VLANs.
3113 */
3114 }
3115
bc7f75fa 3116 ew32(RCTL, rctl);
318a94d6 3117 /* just started the receive unit, no need to restart */
12d43f7d 3118 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3119}
3120
3121/**
3122 * e1000_configure_rx - Configure Receive Unit after Reset
3123 * @adapter: board private structure
3124 *
3125 * Configure the Rx unit of the MAC after a reset.
3126 **/
3127static void e1000_configure_rx(struct e1000_adapter *adapter)
3128{
3129 struct e1000_hw *hw = &adapter->hw;
3130 struct e1000_ring *rx_ring = adapter->rx_ring;
3131 u64 rdba;
3132 u32 rdlen, rctl, rxcsum, ctrl_ext;
3133
3134 if (adapter->rx_ps_pages) {
3135 /* this is a 32 byte descriptor */
3136 rdlen = rx_ring->count *
af667a29 3137 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3138 adapter->clean_rx = e1000_clean_rx_irq_ps;
3139 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3140 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3141 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3142 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3143 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3144 } else {
5f450212 3145 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3146 adapter->clean_rx = e1000_clean_rx_irq;
3147 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3148 }
3149
3150 /* disable receives while setting up the descriptors */
3151 rctl = er32(RCTL);
7f99ae63
BA		 3152 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3153 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3154 e1e_flush();
1bba4386 3155 usleep_range(10000, 20000);
bc7f75fa 3156
3a3b7586 3157 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3158 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3159 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3160 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3161 * granularity = 01
3162 * wthresh = 04,
3163 * hthresh = 04,
3164 * pthresh = 0x20
3165 */
3166 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3167 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3168
e921eb1a 3169 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3170 * the value was not set by the user via module options
3171 */
3172 if (adapter->rx_int_delay == DEFAULT_RDTR)
3173 adapter->rx_int_delay = BURST_RDTR;
3174 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3175 adapter->rx_abs_int_delay = BURST_RADV;
3176 }
3177
bc7f75fa
AK		 3178 /* set the Receive Delay Timer Register */
3179 ew32(RDTR, adapter->rx_int_delay);
3180
3181 /* irq moderation */
3182 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3183 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3184 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3185
3186 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3187 /* Auto-Mask interrupts upon ICR access */
3188 ctrl_ext |= E1000_CTRL_EXT_IAME;
3189 ew32(IAM, 0xffffffff);
3190 ew32(CTRL_EXT, ctrl_ext);
3191 e1e_flush();
3192
e921eb1a 3193 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3194 * the Base and Length of the Rx Descriptor Ring
3195 */
bc7f75fa 3196 rdba = rx_ring->dma;
1e36052e
BA		 3197 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3198 ew32(RDBAH(0), (rdba >> 32));
3199 ew32(RDLEN(0), rdlen);
3200 ew32(RDH(0), 0);
3201 ew32(RDT(0), 0);
3202 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3203 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3204
3205 /* Enable Receive Checksum Offload for TCP and UDP */
3206 rxcsum = er32(RXCSUM);
2e1706f2 3207 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3208 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3209 else
bc7f75fa 3210 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3211 ew32(RXCSUM, rxcsum);
3212
3e35d991
BA		 3213 /* With jumbo frames, excessive C-state transition latencies result
3214 * in dropped transactions.
3215 */
3216 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3217 u32 lat =
3218 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3219 adapter->max_frame_size) * 8 / 1000;
3220
3221 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3222 u32 rxdctl = er32(RXDCTL(0));
3223 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3224 }
3e35d991
BA		 3225
3226 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3227 } else {
3228 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3229 PM_QOS_DEFAULT_VALUE);
97ac8cae 3230 }
bc7f75fa
AK		 3231
3232 /* Enable Receives */
3233 ew32(RCTL, rctl);
3234}
3235
3236/**
ef9b965a
JB		 3237 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3238 * @netdev: network interface device structure
bc7f75fa 3239 *
ef9b965a
JB		 3240 * Writes multicast address list to the MTA hash table.
3241 * Returns: -ENOMEM on failure
3242 * 0 on no addresses written
3243 * X on writing X addresses to MTA
3244 */
3245static int e1000e_write_mc_addr_list(struct net_device *netdev)
3246{
3247 struct e1000_adapter *adapter = netdev_priv(netdev);
3248 struct e1000_hw *hw = &adapter->hw;
3249 struct netdev_hw_addr *ha;
3250 u8 *mta_list;
3251 int i;
3252
3253 if (netdev_mc_empty(netdev)) {
3254 /* nothing to program, so clear mc list */
3255 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3256 return 0;
3257 }
3258
3259 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3260 if (!mta_list)
3261 return -ENOMEM;
3262
3263 /* update_mc_addr_list expects a packed array of only addresses. */
3264 i = 0;
3265 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3266 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3267
3268 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3269 kfree(mta_list);
3270
3271 return netdev_mc_count(netdev);
3272}
3273
3274/**
3275 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3276 * @netdev: network interface device structure
bc7f75fa 3277 *
ef9b965a
JB		 3278 * Writes unicast address list to the RAR table.
3279 * Returns: -ENOMEM on failure/insufficient address space
3280 * 0 on no addresses written
3281 * X on writing X addresses to the RAR table
bc7f75fa 3282 **/
ef9b965a 3283static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3284{
ef9b965a
JB		 3285 struct e1000_adapter *adapter = netdev_priv(netdev);
3286 struct e1000_hw *hw = &adapter->hw;
3287 unsigned int rar_entries = hw->mac.rar_entry_count;
3288 int count = 0;
3289
3290 /* save a rar entry for our hardware address */
3291 rar_entries--;
3292
3293 /* save a rar entry for the LAA workaround */
3294 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3295 rar_entries--;
3296
3297 /* return ENOMEM indicating insufficient memory for addresses */
3298 if (netdev_uc_count(netdev) > rar_entries)
3299 return -ENOMEM;
3300
3301 if (!netdev_uc_empty(netdev) && rar_entries) {
3302 struct netdev_hw_addr *ha;
3303
e921eb1a 3304 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3305 * combining
3306 */
3307 netdev_for_each_uc_addr(ha, netdev) {
3308 if (!rar_entries)
3309 break;
69e1e019 3310 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3311 count++;
3312 }
3313 }
3314
3315 /* zero out the remaining RAR entries not used above */
3316 for (; rar_entries > 0; rar_entries--) {
3317 ew32(RAH(rar_entries), 0);
3318 ew32(RAL(rar_entries), 0);
3319 }
3320 e1e_flush();
3321
3322 return count;
bc7f75fa
AK		 3323}
3324
3325/**
ef9b965a 3326 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3327 * @netdev: network interface device structure
3328 *
ef9b965a
JB		 3329 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3330 * address list or the network interface flags are updated. This routine is
3331 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3332 * promiscuous mode, and all-multi behavior.
3333 **/
ef9b965a 3334static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3335{
3336 struct e1000_adapter *adapter = netdev_priv(netdev);
3337 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3338 u32 rctl;
bc7f75fa
AK		 3339
3340 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3341 rctl = er32(RCTL);
3342
ef9b965a
JB		 3343 /* clear the affected bits */
3344 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3345
bc7f75fa
AK		 3346 if (netdev->flags & IFF_PROMISC) {
3347 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3348 /* Do not hardware filter VLANs in promisc mode */
3349 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3350 } else {
ef9b965a 3351 int count;
3d3a1676 3352
746b9f02
PM		 3353 if (netdev->flags & IFF_ALLMULTI) {
3354 rctl |= E1000_RCTL_MPE;
746b9f02 3355 } else {
e921eb1a 3356 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3357 * then we should just turn on promiscuous mode so
3358 * that we can at least receive multicast traffic
3359 */
3360 count = e1000e_write_mc_addr_list(netdev);
3361 if (count < 0)
3362 rctl |= E1000_RCTL_MPE;
746b9f02 3363 }
86d70e53 3364 e1000e_vlan_filter_enable(adapter);
e921eb1a 3365 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3366 * sufficient space to store all the addresses then enable
3367 * unicast promiscuous mode
bc7f75fa 3368 */
ef9b965a
JB		 3369 count = e1000e_write_uc_addr_list(netdev);
3370 if (count < 0)
3371 rctl |= E1000_RCTL_UPE;
bc7f75fa 3372 }
86d70e53 3373
ef9b965a
JB		 3374 ew32(RCTL, rctl);
3375
f646968f 3376 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3377 e1000e_vlan_strip_enable(adapter);
3378 else
3379 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3380}
3381
70495a50
BA		 3382static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3383{
3384 struct e1000_hw *hw = &adapter->hw;
3385 u32 mrqc, rxcsum;
3386 int i;
3387 static const u32 rsskey[10] = {
3388 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3389 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3390 };
3391
3392 /* Fill out hash function seed */
3393 for (i = 0; i < 10; i++)
3394 ew32(RSSRK(i), rsskey[i]);
3395
3396 /* Direct all traffic to queue 0 */
3397 for (i = 0; i < 32; i++)
3398 ew32(RETA(i), 0);
3399
e921eb1a 3400 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3401 * descriptor on writeback.
3402 */
3403 rxcsum = er32(RXCSUM);
3404 rxcsum |= E1000_RXCSUM_PCSD;
3405
3406 ew32(RXCSUM, rxcsum);
3407
3408 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3409 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3410 E1000_MRQC_RSS_FIELD_IPV6 |
3411 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3412 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3413
3414 ew32(MRQC, mrqc);
3415}
3416
b67e1913
BA		 3417/**
3418 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3419 * @adapter: board private structure
3420 * @timinca: pointer to returned time increment attributes
3421 *
3422 * Get attributes for incrementing the System Time Register SYSTIML/H at
3423 * the default base frequency, and set the cyclecounter shift value.
3424 **/
d89777bf 3425s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3426{
3427 struct e1000_hw *hw = &adapter->hw;
3428 u32 incvalue, incperiod, shift;
3429
3430 /* Make sure clock is enabled on I217 before checking the frequency */
3431 if ((hw->mac.type == e1000_pch_lpt) &&
3432 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3433 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3434 u32 fextnvm7 = er32(FEXTNVM7);
3435
3436 if (!(fextnvm7 & (1 << 0))) {
3437 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3438 e1e_flush();
3439 }
3440 }
3441
3442 switch (hw->mac.type) {
3443 case e1000_pch2lan:
3444 case e1000_pch_lpt:
3445 /* On I217, the clock frequency is 25MHz or 96MHz as
3446 * indicated by the System Clock Frequency Indication
3447 */
3448 if ((hw->mac.type != e1000_pch_lpt) ||
3449 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3450 /* Stable 96MHz frequency */
3451 incperiod = INCPERIOD_96MHz;
3452 incvalue = INCVALUE_96MHz;
3453 shift = INCVALUE_SHIFT_96MHz;
3454 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3455 break;
3456 }
3457 /* fall-through */
3458 case e1000_82574:
3459 case e1000_82583:
3460 /* Stable 25MHz frequency */
3461 incperiod = INCPERIOD_25MHz;
3462 incvalue = INCVALUE_25MHz;
3463 shift = INCVALUE_SHIFT_25MHz;
3464 adapter->cc.shift = shift;
3465 break;
3466 default:
3467 return -EINVAL;
3468 }
3469
3470 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3471 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3472
3473 return 0;
3474}
3475
3476/**
3477 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3478 * @adapter: board private structure
3479 *
3480 * Outgoing time stamping can be enabled and disabled. Play nice and
3481 * disable it when requested, although it shouldn't cause any overhead
3482 * when no packet needs it. At most one packet in the queue may be
3483 * marked for time stamping, otherwise it would be impossible to tell
3484 * for sure to which packet the hardware time stamp belongs.
3485 *
3486 * Incoming time stamping has to be configured via the hardware filters.
3487 * Not all combinations are supported, in particular event type has to be
3488 * specified. Matching the kind of event packet is not supported, with the
3489 * exception of "all V2 events regardless of level 2 or 4".
3490 **/
3491static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3492{
3493 struct e1000_hw *hw = &adapter->hw;
3494 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3495 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3496 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3497 u32 rxmtrl = 0;
3498 u16 rxudp = 0;
3499 bool is_l4 = false;
3500 bool is_l2 = false;
b67e1913
BA		 3501 u32 regval;
3502 s32 ret_val;
3503
3504 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3505 return -EINVAL;
3506
3507 /* flags reserved for future extensions - must be zero */
3508 if (config->flags)
3509 return -EINVAL;
3510
3511 switch (config->tx_type) {
3512 case HWTSTAMP_TX_OFF:
3513 tsync_tx_ctl = 0;
3514 break;
3515 case HWTSTAMP_TX_ON:
3516 break;
3517 default:
3518 return -ERANGE;
3519 }
3520
3521 switch (config->rx_filter) {
3522 case HWTSTAMP_FILTER_NONE:
3523 tsync_rx_ctl = 0;
3524 break;
d89777bf
BA		 3525 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3526 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3527 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3528 is_l4 = true;
3529 break;
3530 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3531 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3532 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3533 is_l4 = true;
3534 break;
3535 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3536 /* Also time stamps V2 L2 Path Delay Request/Response */
3537 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3538 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3539 is_l2 = true;
3540 break;
3541 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3542 /* Also time stamps V2 L2 Path Delay Request/Response. */
3543 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3544 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3545 is_l2 = true;
3546 break;
3547 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3548 /* Hardware cannot filter just V2 L4 Sync messages;
3549 * fall-through to V2 (both L2 and L4) Sync.
3550 */
3551 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3552 /* Also time stamps V2 Path Delay Request/Response. */
3553 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3554 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3555 is_l2 = true;
3556 is_l4 = true;
3557 break;
3558 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3559 /* Hardware cannot filter just V2 L4 Delay Request messages;
3560 * fall-through to V2 (both L2 and L4) Delay Request.
3561 */
3562 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3563 /* Also time stamps V2 Path Delay Request/Response. */
3564 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3565 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3566 is_l2 = true;
3567 is_l4 = true;
3568 break;
3569 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3570 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3571 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3572 * fall-through to all V2 (both L2 and L4) Events.
3573 */
3574 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3575 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3576 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3577 is_l2 = true;
3578 is_l4 = true;
3579 break;
3580 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3581 /* For V1, the hardware can only filter Sync messages or
3582 * Delay Request messages but not both so fall-through to
3583 * time stamp all packets.
3584 */
b67e1913 3585 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3586 is_l2 = true;
3587 is_l4 = true;
b67e1913
BA		 3588 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3589 config->rx_filter = HWTSTAMP_FILTER_ALL;
3590 break;
3591 default:
3592 return -ERANGE;
3593 }
3594
3595 /* enable/disable Tx h/w time stamping */
3596 regval = er32(TSYNCTXCTL);
3597 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3598 regval |= tsync_tx_ctl;
3599 ew32(TSYNCTXCTL, regval);
3600 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3601 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3602 e_err("Timesync Tx Control register not set as expected\n");
3603 return -EAGAIN;
3604 }
3605
3606 /* enable/disable Rx h/w time stamping */
3607 regval = er32(TSYNCRXCTL);
3608 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3609 regval |= tsync_rx_ctl;
3610 ew32(TSYNCRXCTL, regval);
3611 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3612 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3613 (regval & (E1000_TSYNCRXCTL_ENABLED |
3614 E1000_TSYNCRXCTL_TYPE_MASK))) {
3615 e_err("Timesync Rx Control register not set as expected\n");
3616 return -EAGAIN;
3617 }
3618
d89777bf
BA		 3619 /* L2: define ethertype filter for time stamped packets */
3620 if (is_l2)
3621 rxmtrl |= ETH_P_1588;
3622
3623 /* define which PTP packets get time stamped */
3624 ew32(RXMTRL, rxmtrl);
3625
3626 /* Filter by destination port */
3627 if (is_l4) {
3628 rxudp = PTP_EV_PORT;
3629 cpu_to_be16s(&rxudp);
3630 }
3631 ew32(RXUDP, rxudp);
3632
3633 e1e_flush();
3634
b67e1913 3635 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3636 er32(RXSTMPH);
3637 er32(TXSTMPH);
b67e1913
BA		 3638
3639 /* Get and set the System Time Register SYSTIM base frequency */
3640 ret_val = e1000e_get_base_timinca(adapter, &regval);
3641 if (ret_val)
3642 return ret_val;
3643 ew32(TIMINCA, regval);
3644
3645 /* reset the ns time counter */
3646 timecounter_init(&adapter->tc, &adapter->cc,
3647 ktime_to_ns(ktime_get_real()));
3648
3649 return 0;
3650}
3651
bc7f75fa 3652/**
ad68076e 3653 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3654 * @adapter: private board structure
3655 **/
3656static void e1000_configure(struct e1000_adapter *adapter)
3657{
55aa6985
BA		 3658 struct e1000_ring *rx_ring = adapter->rx_ring;
3659
ef9b965a 3660 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3661
3662 e1000_restore_vlan(adapter);
cd791618 3663 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3664
3665 e1000_configure_tx(adapter);
70495a50
BA		 3666
3667 if (adapter->netdev->features & NETIF_F_RXHASH)
3668 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3669 e1000_setup_rctl(adapter);
3670 e1000_configure_rx(adapter);
55aa6985 3671 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3672}
3673
3674/**
3675 * e1000e_power_up_phy - restore link in case the phy was powered down
3676 * @adapter: address of board private structure
3677 *
3678 * The phy may be powered down to save power and turn off link when the
3679 * driver is unloaded and wake on lan is not enabled (among others)
3680 * *** this routine MUST be followed by a call to e1000e_reset ***
3681 **/
3682void e1000e_power_up_phy(struct e1000_adapter *adapter)
3683{
17f208de
BA		 3684 if (adapter->hw.phy.ops.power_up)
3685 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3686
3687 adapter->hw.mac.ops.setup_link(&adapter->hw);
3688}
3689
3690/**
3691 * e1000_power_down_phy - Power down the PHY
3692 *
17f208de
BA		 3693 * Power down the PHY so no link is implied when interface is down.
3694 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3695 */
3696static void e1000_power_down_phy(struct e1000_adapter *adapter)
3697{
bc7f75fa 3698 /* WoL is enabled */
23b66e2b 3699 if (adapter->wol)
bc7f75fa
AK		 3700 return;
3701
17f208de
BA		 3702 if (adapter->hw.phy.ops.power_down)
3703 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3704}
3705
3706/**
3707 * e1000e_reset - bring the hardware into a known good state
3708 *
3709 * This function boots the hardware and enables some settings that
3710 * require a configuration cycle of the hardware - those cannot be
3711 * set/changed during runtime. After reset the device needs to be
ad68076e 3712 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3713 */
3714void e1000e_reset(struct e1000_adapter *adapter)
3715{
3716 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3717 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3718 struct e1000_hw *hw = &adapter->hw;
3719 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3720 u32 pba = adapter->pba;
bc7f75fa
AK		 3721 u16 hwm;
3722
ad68076e 3723 /* reset Packet Buffer Allocation to default */
318a94d6 3724 ew32(PBA, pba);
df762464 3725
318a94d6 3726 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3727 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3728 * large enough to accommodate two full transmit packets,
3729 * rounded up to the next 1KB and expressed in KB. Likewise,
3730 * the Rx FIFO should be large enough to accommodate at least
3731 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3732 * expressed in KB.
3733 */
df762464 3734 pba = er32(PBA);
bc7f75fa 3735 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3736 tx_space = pba >> 16;
bc7f75fa 3737 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3738 pba &= 0xffff;
e921eb1a 3739 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3740 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3741 */
3742 min_tx_space = (adapter->max_frame_size +
e5fe2541 3743 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3744 min_tx_space = ALIGN(min_tx_space, 1024);
3745 min_tx_space >>= 10;
3746 /* software strips receive CRC, so leave room for it */
318a94d6 3747 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3748 min_rx_space = ALIGN(min_rx_space, 1024);
3749 min_rx_space >>= 10;
3750
e921eb1a 3751 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3752 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3753 * allocation, take space away from current Rx allocation
3754 */
df762464
AK		 3755 if ((tx_space < min_tx_space) &&
3756 ((min_tx_space - tx_space) < pba)) {
3757 pba -= min_tx_space - tx_space;
bc7f75fa 3758
e921eb1a 3759 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3760 * adjustment
ad68076e 3761 */
79d4e908 3762 if (pba < min_rx_space)
df762464 3763 pba = min_rx_space;
bc7f75fa 3764 }
df762464
AK		 3765
3766 ew32(PBA, pba);
bc7f75fa
AK		 3767 }
3768
e921eb1a 3769 /* flow control settings
ad68076e 3770 *
38eb394e 3771 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3772 * (or the size used for early receive) above it in the Rx FIFO.
3773 * Set it to the lower of:
3774 * - 90% of the Rx FIFO size, and
38eb394e 3775 * - the full Rx FIFO size minus one full frame
ad68076e 3776 */
d3738bb8
BA		 3777 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3778 fc->pause_time = 0xFFFF;
3779 else
3780 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3781 fc->send_xon = true;
d3738bb8
BA		 3782 fc->current_mode = fc->requested_mode;
3783
3784 switch (hw->mac.type) {
79d4e908
BA		 3785 case e1000_ich9lan:
3786 case e1000_ich10lan:
3787 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3788 pba = 14;
3789 ew32(PBA, pba);
3790 fc->high_water = 0x2800;
3791 fc->low_water = fc->high_water - 8;
3792 break;
3793 }
3794 /* fall-through */
d3738bb8 3795 default:
79d4e908
BA		 3796 hwm = min(((pba << 10) * 9 / 10),
3797 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3798
3799 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3800 fc->low_water = fc->high_water - 8;
3801 break;
3802 case e1000_pchlan:
e921eb1a 3803 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3804 * loads. If hangs persist, try disabling Tx flow control.
3805 */
3806 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3807 fc->high_water = 0x3500;
3808 fc->low_water = 0x1500;
3809 } else {
3810 fc->high_water = 0x5000;
3811 fc->low_water = 0x3000;
3812 }
a305595b 3813 fc->refresh_time = 0x1000;
d3738bb8
BA		 3814 break;
3815 case e1000_pch2lan:
2fbe4526 3816 case e1000_pch_lpt:
d3738bb8 3817 fc->refresh_time = 0x0400;
347b5201
BA		 3818
3819 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3820 fc->high_water = 0x05C20;
3821 fc->low_water = 0x05048;
3822 fc->pause_time = 0x0650;
3823 break;
828bac87 3824 }
347b5201
BA		 3825
3826 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3827 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3828 break;
38eb394e 3829 }
bc7f75fa 3830
e921eb1a 3831 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3832 * maximum size per Tx descriptor limited only to the transmit
3833 * allocation of the packet buffer minus 96 bytes with an upper
3834 * limit of 24KB due to receive synchronization limitations.
3835 */
3836 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3837 24 << 10);
3838
e921eb1a 3839 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3840 * fit in receive buffer.
828bac87
BA		 3841 */
3842 if (adapter->itr_setting & 0x3) {
79d4e908 3843 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3844 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3845 dev_info(&adapter->pdev->dev,
17e813ec 3846 "Interrupt Throttle Rate off\n");
828bac87 3847 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3848 e1000e_write_itr(adapter, 0);
828bac87
BA		 3849 }
3850 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3851 dev_info(&adapter->pdev->dev,
17e813ec 3852 "Interrupt Throttle Rate on\n");
828bac87
BA		 3853 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3854 adapter->itr = 20000;
22a4cca2 3855 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3856 }
3857 }
3858
bc7f75fa
AK		 3859 /* Allow time for pending master requests to run */
3860 mac->ops.reset_hw(hw);
97ac8cae 3861
e921eb1a 3862 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3863 * that the network interface is in control
3864 */
c43bc57e 3865 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3866 e1000e_get_hw_control(adapter);
97ac8cae 3867
bc7f75fa
AK		 3868 ew32(WUC, 0);
3869
3870 if (mac->ops.init_hw(hw))
44defeb3 3871 e_err("Hardware Error\n");
bc7f75fa
AK		 3872
3873 e1000_update_mng_vlan(adapter);
3874
3875 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3876 ew32(VET, ETH_P_8021Q);
3877
3878 e1000e_reset_adaptive(hw);
31dbe5b4 3879
b67e1913
BA		 3880 /* initialize systim and reset the ns time counter */
3881 e1000e_config_hwtstamp(adapter);
3882
d495bcb8
BA		 3883 /* Set EEE advertisement as appropriate */
3884 if (adapter->flags2 & FLAG2_HAS_EEE) {
3885 s32 ret_val;
3886 u16 adv_addr;
3887
3888 switch (hw->phy.type) {
3889 case e1000_phy_82579:
3890 adv_addr = I82579_EEE_ADVERTISEMENT;
3891 break;
3892 case e1000_phy_i217:
3893 adv_addr = I217_EEE_ADVERTISEMENT;
3894 break;
3895 default:
3896 dev_err(&adapter->pdev->dev,
3897 "Invalid PHY type setting EEE advertisement\n");
3898 return;
3899 }
3900
3901 ret_val = hw->phy.ops.acquire(hw);
3902 if (ret_val) {
3903 dev_err(&adapter->pdev->dev,
3904 "EEE advertisement - unable to acquire PHY\n");
3905 return;
3906 }
3907
3908 e1000_write_emi_reg_locked(hw, adv_addr,
3909 hw->dev_spec.ich8lan.eee_disable ?
3910 0 : adapter->eee_advert);
3911
3912 hw->phy.ops.release(hw);
3913 }
3914
31dbe5b4
BA		 3915 if (!netif_running(adapter->netdev) &&
3916 !test_bit(__E1000_TESTING, &adapter->state)) {
3917 e1000_power_down_phy(adapter);
3918 return;
3919 }
3920
bc7f75fa
AK		 3921 e1000_get_phy_info(hw);
3922
918d7197
BA		 3923 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3924 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3925 u16 phy_data = 0;
e921eb1a 3926 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3927 * the return value of this function because there is nothing
ad68076e
BA		 3928 * different we would do if it failed
3929 */
bc7f75fa
AK		 3930 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3931 phy_data &= ~IGP02E1000_PM_SPD;
3932 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3933 }
bc7f75fa
AK		 3934}
3935
3936int e1000e_up(struct e1000_adapter *adapter)
3937{
3938 struct e1000_hw *hw = &adapter->hw;
3939
3940 /* hardware has been reset, we need to reload some things */
3941 e1000_configure(adapter);
3942
3943 clear_bit(__E1000_DOWN, &adapter->state);
3944
4662e82b
BA		 3945 if (adapter->msix_entries)
3946 e1000_configure_msix(adapter);
bc7f75fa
AK		 3947 e1000_irq_enable(adapter);
3948
400484fa 3949 netif_start_queue(adapter->netdev);
4cb9be7a 3950
bc7f75fa 3951 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3952 if (adapter->msix_entries)
3953 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3954 else
3955 ew32(ICS, E1000_ICS_LSC);
3956
bc7f75fa
AK		 3957 return 0;
3958}
3959
713b3c9e
JB		 3960static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3961{
3962 struct e1000_hw *hw = &adapter->hw;
3963
3964 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3965 return;
3966
3967 /* flush pending descriptor writebacks to memory */
3968 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3969 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3970
3971 /* execute the writes immediately */
3972 e1e_flush();
bf03085f 3973
e921eb1a 3974 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3975 * write is successful
3976 */
3977 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3978 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3979
3980 /* execute the writes immediately */
3981 e1e_flush();
3982}
3983
67fd4fcb
JK		 3984static void e1000e_update_stats(struct e1000_adapter *adapter);
3985
bc7f75fa
AK		 3986void e1000e_down(struct e1000_adapter *adapter)
3987{
3988 struct net_device *netdev = adapter->netdev;
3989 struct e1000_hw *hw = &adapter->hw;
3990 u32 tctl, rctl;
3991
e921eb1a 3992 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3993 * reschedule our watchdog timer
3994 */
bc7f75fa
AK		 3995 set_bit(__E1000_DOWN, &adapter->state);
3996
3997 /* disable receives in the hardware */
3998 rctl = er32(RCTL);
7f99ae63
BA		 3999 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4000 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4001 /* flush and sleep below */
4002
4cb9be7a 4003 netif_stop_queue(netdev);
bc7f75fa
AK		 4004
4005 /* disable transmits in the hardware */
4006 tctl = er32(TCTL);
4007 tctl &= ~E1000_TCTL_EN;
4008 ew32(TCTL, tctl);
7f99ae63 4009
bc7f75fa
AK		 4010 /* flush both disables and wait for them to finish */
4011 e1e_flush();
1bba4386 4012 usleep_range(10000, 20000);
bc7f75fa 4013
bc7f75fa
AK		 4014 e1000_irq_disable(adapter);
4015
4016 del_timer_sync(&adapter->watchdog_timer);
4017 del_timer_sync(&adapter->phy_info_timer);
4018
bc7f75fa 4019 netif_carrier_off(netdev);
67fd4fcb
JK		 4020
4021 spin_lock(&adapter->stats64_lock);
4022 e1000e_update_stats(adapter);
4023 spin_unlock(&adapter->stats64_lock);
4024
400484fa 4025 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4026 e1000_clean_tx_ring(adapter->tx_ring);
4027 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4028
bc7f75fa
AK		 4029 adapter->link_speed = 0;
4030 adapter->link_duplex = 0;
4031
52cc3086
JK		 4032 if (!pci_channel_offline(adapter->pdev))
4033 e1000e_reset(adapter);
713b3c9e 4034
e921eb1a 4035 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 4036 * pci_disable_device here.
4037 */
4038}
4039
4040void e1000e_reinit_locked(struct e1000_adapter *adapter)
4041{
4042 might_sleep();
4043 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4044 usleep_range(1000, 2000);
bc7f75fa
AK		 4045 e1000e_down(adapter);
4046 e1000e_up(adapter);
4047 clear_bit(__E1000_RESETTING, &adapter->state);
4048}
4049
b67e1913
BA		 4050/**
4051 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4052 * @cc: cyclecounter structure
4053 **/
4054static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4055{
4056 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4057 cc);
4058 struct e1000_hw *hw = &adapter->hw;
4059 cycle_t systim;
4060
4061 /* latch SYSTIMH on read of SYSTIML */
4062 systim = (cycle_t)er32(SYSTIML);
4063 systim |= (cycle_t)er32(SYSTIMH) << 32;
4064
4065 return systim;
4066}
4067
bc7f75fa
AK		 4068/**
4069 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4070 * @adapter: board private structure to initialize
4071 *
4072 * e1000_sw_init initializes the Adapter private data structure.
4073 * Fields are initialized based on PCI device information and
4074 * OS network device settings (MTU size).
4075 **/
9f9a12f8 4076static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4077{
bc7f75fa
AK		 4078 struct net_device *netdev = adapter->netdev;
4079
4080 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4081 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4082 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4083 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4084 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4085 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4086
67fd4fcb
JK		 4087 spin_lock_init(&adapter->stats64_lock);
4088
4662e82b 4089 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4090
4662e82b
BA		 4091 if (e1000_alloc_queues(adapter))
4092 return -ENOMEM;
bc7f75fa 4093
b67e1913
BA		 4094 /* Setup hardware time stamping cyclecounter */
4095 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4096 adapter->cc.read = e1000e_cyclecounter_read;
4097 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4098 adapter->cc.mult = 1;
4099 /* cc.shift set in e1000e_get_base_tininca() */
4100
4101 spin_lock_init(&adapter->systim_lock);
4102 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4103 }
4104
bc7f75fa 4105 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4106 e1000_irq_disable(adapter);
4107
bc7f75fa
AK		 4108 set_bit(__E1000_DOWN, &adapter->state);
4109 return 0;
bc7f75fa
AK		 4110}
4111
f8d59f78
BA		 4112/**
4113 * e1000_intr_msi_test - Interrupt Handler
4114 * @irq: interrupt number
4115 * @data: pointer to a network interface device structure
4116 **/
8bb62869 4117static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4118{
4119 struct net_device *netdev = data;
4120 struct e1000_adapter *adapter = netdev_priv(netdev);
4121 struct e1000_hw *hw = &adapter->hw;
4122 u32 icr = er32(ICR);
4123
3bb99fe2 4124 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4125 if (icr & E1000_ICR_RXSEQ) {
4126 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4127 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4128 * interrupt is handled.
4129 */
f8d59f78
BA		 4130 wmb();
4131 }
4132
4133 return IRQ_HANDLED;
4134}
4135
4136/**
4137 * e1000_test_msi_interrupt - Returns 0 for successful test
4138 * @adapter: board private struct
4139 *
4140 * code flow taken from tg3.c
4141 **/
4142static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4143{
4144 struct net_device *netdev = adapter->netdev;
4145 struct e1000_hw *hw = &adapter->hw;
4146 int err;
4147
4148 /* poll_enable hasn't been called yet, so don't need disable */
4149 /* clear any pending events */
4150 er32(ICR);
4151
4152 /* free the real vector and request a test handler */
4153 e1000_free_irq(adapter);
4662e82b 4154 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4155
4156 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4157 * MSI irq handler will unset this flag
4158 */
f8d59f78
BA		 4159 adapter->flags |= FLAG_MSI_TEST_FAILED;
4160
4161 err = pci_enable_msi(adapter->pdev);
4162 if (err)
4163 goto msi_test_failed;
4164
a0607fd3 4165 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4166 netdev->name, netdev);
4167 if (err) {
4168 pci_disable_msi(adapter->pdev);
4169 goto msi_test_failed;
4170 }
4171
e921eb1a 4172 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4173 * interrupt.
4174 */
f8d59f78
BA		 4175 wmb();
4176
4177 e1000_irq_enable(adapter);
4178
4179 /* fire an unusual interrupt on the test handler */
4180 ew32(ICS, E1000_ICS_RXSEQ);
4181 e1e_flush();
569a3aff 4182 msleep(100);
f8d59f78
BA		 4183
4184 e1000_irq_disable(adapter);
4185
bc76329d 4186 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4187
4188 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4189 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4190 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4191 } else {
068e8a30 4192 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4193 }
f8d59f78
BA		 4194
4195 free_irq(adapter->pdev->irq, netdev);
4196 pci_disable_msi(adapter->pdev);
4197
f8d59f78 4198msi_test_failed:
4662e82b 4199 e1000e_set_interrupt_capability(adapter);
068e8a30 4200 return e1000_request_irq(adapter);
f8d59f78
BA		 4201}
4202
4203/**
4204 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4205 * @adapter: board private struct
4206 *
4207 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4208 **/
4209static int e1000_test_msi(struct e1000_adapter *adapter)
4210{
4211 int err;
4212 u16 pci_cmd;
4213
4214 if (!(adapter->flags & FLAG_MSI_ENABLED))
4215 return 0;
4216
4217 /* disable SERR in case the MSI write causes a master abort */
4218 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4219 if (pci_cmd & PCI_COMMAND_SERR)
4220 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4221 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4222
4223 err = e1000_test_msi_interrupt(adapter);
4224
36f2407f
DN		 4225 /* re-enable SERR */
4226 if (pci_cmd & PCI_COMMAND_SERR) {
4227 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4228 pci_cmd |= PCI_COMMAND_SERR;
4229 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4230 }
f8d59f78 4231
f8d59f78
BA		 4232 return err;
4233}
4234
bc7f75fa
AK		 4235/**
4236 * e1000_open - Called when a network interface is made active
4237 * @netdev: network interface device structure
4238 *
4239 * Returns 0 on success, negative value on failure
4240 *
4241 * The open entry point is called when a network interface is made
4242 * active by the system (IFF_UP). At this point all resources needed
4243 * for transmit and receive operations are allocated, the interrupt
4244 * handler is registered with the OS, the watchdog timer is started,
4245 * and the stack is notified that the interface is ready.
4246 **/
4247static int e1000_open(struct net_device *netdev)
4248{
4249 struct e1000_adapter *adapter = netdev_priv(netdev);
4250 struct e1000_hw *hw = &adapter->hw;
23606cf5 4251 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4252 int err;
4253
4254 /* disallow open during test */
4255 if (test_bit(__E1000_TESTING, &adapter->state))
4256 return -EBUSY;
4257
23606cf5
RW		 4258 pm_runtime_get_sync(&pdev->dev);
4259
9c563d20
JB		 4260 netif_carrier_off(netdev);
4261
bc7f75fa 4262 /* allocate transmit descriptors */
55aa6985 4263 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4264 if (err)
4265 goto err_setup_tx;
4266
4267 /* allocate receive descriptors */
55aa6985 4268 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4269 if (err)
4270 goto err_setup_rx;
4271
e921eb1a 4272 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4273 * interface is now open and reset the part to a known state.
4274 */
4275 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4276 e1000e_get_hw_control(adapter);
11b08be8
BA		 4277 e1000e_reset(adapter);
4278 }
4279
bc7f75fa
AK		 4280 e1000e_power_up_phy(adapter);
4281
4282 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4283 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4284 e1000_update_mng_vlan(adapter);
4285
79d4e908 4286 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4287 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4288 PM_QOS_DEFAULT_VALUE);
c128ec29 4289
e921eb1a 4290 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4291 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4292 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4293 * clean_rx handler before we do so.
4294 */
bc7f75fa
AK		 4295 e1000_configure(adapter);
4296
4297 err = e1000_request_irq(adapter);
4298 if (err)
4299 goto err_req_irq;
4300
e921eb1a 4301 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4302 * ignore e1000e MSI messages, which means we need to test our MSI
4303 * interrupt now
4304 */
4662e82b 4305 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4306 err = e1000_test_msi(adapter);
4307 if (err) {
4308 e_err("Interrupt allocation failed\n");
4309 goto err_req_irq;
4310 }
4311 }
4312
bc7f75fa
AK		 4313 /* From here on the code is the same as e1000e_up() */
4314 clear_bit(__E1000_DOWN, &adapter->state);
4315
4316 napi_enable(&adapter->napi);
4317
4318 e1000_irq_enable(adapter);
4319
09357b00 4320 adapter->tx_hang_recheck = false;
4cb9be7a 4321 netif_start_queue(netdev);
d55b53ff 4322
23606cf5 4323 adapter->idle_check = true;
66148bab 4324 hw->mac.get_link_status = true;
23606cf5
RW		 4325 pm_runtime_put(&pdev->dev);
4326
bc7f75fa 4327 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4328 if (adapter->msix_entries)
4329 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4330 else
4331 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4332
4333 return 0;
4334
4335err_req_irq:
31dbe5b4 4336 e1000e_release_hw_control(adapter);
bc7f75fa 4337 e1000_power_down_phy(adapter);
55aa6985 4338 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4339err_setup_rx:
55aa6985 4340 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4341err_setup_tx:
4342 e1000e_reset(adapter);
23606cf5 4343 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4344
4345 return err;
4346}
4347
4348/**
4349 * e1000_close - Disables a network interface
4350 * @netdev: network interface device structure
4351 *
4352 * Returns 0, this is not allowed to fail
4353 *
4354 * The close entry point is called when an interface is de-activated
4355 * by the OS. The hardware is still under the drivers control, but
4356 * needs to be disabled. A global MAC reset is issued to stop the
4357 * hardware, and all transmit and receive resources are freed.
4358 **/
4359static int e1000_close(struct net_device *netdev)
4360{
4361 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4362 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4363 int count = E1000_CHECK_RESET_COUNT;
4364
4365 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4366 usleep_range(10000, 20000);
bc7f75fa
AK		 4367
4368 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4369
4370 pm_runtime_get_sync(&pdev->dev);
4371
5f4a780d
BA		 4372 napi_disable(&adapter->napi);
4373
23606cf5
RW		 4374 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4375 e1000e_down(adapter);
4376 e1000_free_irq(adapter);
4377 }
bc7f75fa 4378 e1000_power_down_phy(adapter);
bc7f75fa 4379
55aa6985
BA		 4380 e1000e_free_tx_resources(adapter->tx_ring);
4381 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4382
e921eb1a 4383 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4384 * the same ID is registered on the host OS (let 8021q kill it)
4385 */
e5fe2541 4386 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 4387 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4388
e921eb1a 4389 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4390 * interface is now closed
4391 */
31dbe5b4
BA		 4392 if ((adapter->flags & FLAG_HAS_AMT) &&
4393 !test_bit(__E1000_TESTING, &adapter->state))
4394 e1000e_release_hw_control(adapter);
bc7f75fa 4395
3e35d991 4396 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4397
23606cf5
RW		 4398 pm_runtime_put_sync(&pdev->dev);
4399
bc7f75fa
AK		 4400 return 0;
4401}
fc830b78 4402
bc7f75fa
AK		 4403/**
4404 * e1000_set_mac - Change the Ethernet Address of the NIC
4405 * @netdev: network interface device structure
4406 * @p: pointer to an address structure
4407 *
4408 * Returns 0 on success, negative on failure
4409 **/
4410static int e1000_set_mac(struct net_device *netdev, void *p)
4411{
4412 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4413 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4414 struct sockaddr *addr = p;
4415
4416 if (!is_valid_ether_addr(addr->sa_data))
4417 return -EADDRNOTAVAIL;
4418
4419 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4420 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4421
69e1e019 4422 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4423
4424 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4425 /* activate the work around */
4426 e1000e_set_laa_state_82571(&adapter->hw, 1);
4427
e921eb1a 4428 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4429 * between the time RAR[0] gets clobbered and the time it
4430 * gets fixed (in e1000_watchdog), the actual LAA is in one
4431 * of the RARs and no incoming packets directed to this port
4432 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4433 * RAR[14]
4434 */
69e1e019
BA		 4435 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4436 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4437 }
4438
4439 return 0;
4440}
4441
a8f88ff5
JB		 4442/**
4443 * e1000e_update_phy_task - work thread to update phy
4444 * @work: pointer to our work struct
4445 *
4446 * this worker thread exists because we must acquire a
4447 * semaphore to read the phy, which we could msleep while
4448 * waiting for it, and we can't msleep in a timer.
4449 **/
4450static void e1000e_update_phy_task(struct work_struct *work)
4451{
4452 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4453 struct e1000_adapter,
4454 update_phy_task);
615b32af
JB		 4455
4456 if (test_bit(__E1000_DOWN, &adapter->state))
4457 return;
4458
a8f88ff5
JB		 4459 e1000_get_phy_info(&adapter->hw);
4460}
4461
e921eb1a
BA		 4462/**
4463 * e1000_update_phy_info - timre call-back to update PHY info
4464 * @data: pointer to adapter cast into an unsigned long
4465 *
ad68076e
BA		 4466 * Need to wait a few seconds after link up to get diagnostic information from
4467 * the phy
e921eb1a 4468 **/
bc7f75fa
AK		 4469static void e1000_update_phy_info(unsigned long data)
4470{
53aa82da 4471 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4472
4473 if (test_bit(__E1000_DOWN, &adapter->state))
4474 return;
4475
a8f88ff5 4476 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4477}
4478
8c7bbb92
BA		 4479/**
4480 * e1000e_update_phy_stats - Update the PHY statistics counters
4481 * @adapter: board private structure
2b6b168d
BA		 4482 *
4483 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4484 **/
4485static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4486{
4487 struct e1000_hw *hw = &adapter->hw;
4488 s32 ret_val;
4489 u16 phy_data;
4490
4491 ret_val = hw->phy.ops.acquire(hw);
4492 if (ret_val)
4493 return;
4494
e921eb1a 4495 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4496 * If not, set to the page with the PHY status registers.
4497 */
2b6b168d 4498 hw->phy.addr = 1;
8c7bbb92
BA		 4499 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4500 &phy_data);
4501 if (ret_val)
4502 goto release;
2b6b168d
BA		 4503 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4504 ret_val = hw->phy.ops.set_page(hw,
4505 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4506 if (ret_val)
4507 goto release;
4508 }
4509
8c7bbb92 4510 /* Single Collision Count */
2b6b168d
BA		 4511 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4512 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4513 if (!ret_val)
4514 adapter->stats.scc += phy_data;
4515
4516 /* Excessive Collision Count */
2b6b168d
BA		 4517 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4518 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4519 if (!ret_val)
4520 adapter->stats.ecol += phy_data;
4521
4522 /* Multiple Collision Count */
2b6b168d
BA		 4523 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4524 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4525 if (!ret_val)
4526 adapter->stats.mcc += phy_data;
4527
4528 /* Late Collision Count */
2b6b168d
BA		 4529 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4530 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4531 if (!ret_val)
4532 adapter->stats.latecol += phy_data;
4533
4534 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4535 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4536 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4537 if (!ret_val)
4538 hw->mac.collision_delta = phy_data;
4539
4540 /* Defer Count */
2b6b168d
BA		 4541 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4542 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4543 if (!ret_val)
4544 adapter->stats.dc += phy_data;
4545
4546 /* Transmit with no CRS */
2b6b168d
BA		 4547 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4548 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4549 if (!ret_val)
4550 adapter->stats.tncrs += phy_data;
4551
4552release:
4553 hw->phy.ops.release(hw);
4554}
4555
bc7f75fa
AK		 4556/**
4557 * e1000e_update_stats - Update the board statistics counters
4558 * @adapter: board private structure
4559 **/
67fd4fcb 4560static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4561{
7274c20f 4562 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4563 struct e1000_hw *hw = &adapter->hw;
4564 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4565
e921eb1a 4566 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4567 * connection is down.
4568 */
4569 if (adapter->link_speed == 0)
4570 return;
4571 if (pci_channel_offline(pdev))
4572 return;
4573
bc7f75fa
AK		 4574 adapter->stats.crcerrs += er32(CRCERRS);
4575 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4576 adapter->stats.gorc += er32(GORCL);
4577 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4578 adapter->stats.bprc += er32(BPRC);
4579 adapter->stats.mprc += er32(MPRC);
4580 adapter->stats.roc += er32(ROC);
4581
bc7f75fa 4582 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4583
4584 /* Half-duplex statistics */
4585 if (adapter->link_duplex == HALF_DUPLEX) {
4586 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4587 e1000e_update_phy_stats(adapter);
4588 } else {
4589 adapter->stats.scc += er32(SCC);
4590 adapter->stats.ecol += er32(ECOL);
4591 adapter->stats.mcc += er32(MCC);
4592 adapter->stats.latecol += er32(LATECOL);
4593 adapter->stats.dc += er32(DC);
4594
4595 hw->mac.collision_delta = er32(COLC);
4596
4597 if ((hw->mac.type != e1000_82574) &&
4598 (hw->mac.type != e1000_82583))
4599 adapter->stats.tncrs += er32(TNCRS);
4600 }
4601 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4602 }
8c7bbb92 4603
bc7f75fa
AK		 4604 adapter->stats.xonrxc += er32(XONRXC);
4605 adapter->stats.xontxc += er32(XONTXC);
4606 adapter->stats.xoffrxc += er32(XOFFRXC);
4607 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4608 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4609 adapter->stats.gotc += er32(GOTCL);
4610 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4611 adapter->stats.rnbc += er32(RNBC);
4612 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4613
4614 adapter->stats.mptc += er32(MPTC);
4615 adapter->stats.bptc += er32(BPTC);
4616
4617 /* used for adaptive IFS */
4618
4619 hw->mac.tx_packet_delta = er32(TPT);
4620 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4621
4622 adapter->stats.algnerrc += er32(ALGNERRC);
4623 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4624 adapter->stats.cexterr += er32(CEXTERR);
4625 adapter->stats.tsctc += er32(TSCTC);
4626 adapter->stats.tsctfc += er32(TSCTFC);
4627
bc7f75fa 4628 /* Fill out the OS statistics structure */
7274c20f
AK		 4629 netdev->stats.multicast = adapter->stats.mprc;
4630 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4631
4632 /* Rx Errors */
4633
e921eb1a 4634 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4635 * our own version based on RUC and ROC
4636 */
7274c20f 4637 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4638 adapter->stats.crcerrs + adapter->stats.algnerrc +
4639 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4640 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4641 adapter->stats.roc;
7274c20f
AK		 4642 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4643 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4644 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4645
4646 /* Tx Errors */
f0ff4398 4647 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4648 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4649 netdev->stats.tx_window_errors = adapter->stats.latecol;
4650 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4651
4652 /* Tx Dropped needs to be maintained elsewhere */
4653
bc7f75fa
AK		 4654 /* Management Stats */
4655 adapter->stats.mgptc += er32(MGTPTC);
4656 adapter->stats.mgprc += er32(MGTPRC);
4657 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4658
4659 /* Correctable ECC Errors */
4660 if (hw->mac.type == e1000_pch_lpt) {
4661 u32 pbeccsts = er32(PBECCSTS);
4662 adapter->corr_errors +=
4663 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4664 adapter->uncorr_errors +=
4665 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4666 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4667 }
bc7f75fa
AK		 4668}
4669
7c25769f
BA		 4670/**
4671 * e1000_phy_read_status - Update the PHY register status snapshot
4672 * @adapter: board private structure
4673 **/
4674static void e1000_phy_read_status(struct e1000_adapter *adapter)
4675{
4676 struct e1000_hw *hw = &adapter->hw;
4677 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4678
4679 if ((er32(STATUS) & E1000_STATUS_LU) &&
4680 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4681 int ret_val;
4682
e60b22c5 4683 pm_runtime_get_sync(&adapter->pdev->dev);
c2ade1a4
BA		 4684 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4685 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4686 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4687 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4688 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4689 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4690 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4691 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4692 if (ret_val)
44defeb3 4693 e_warn("Error reading PHY register\n");
e60b22c5 4694 pm_runtime_put_sync(&adapter->pdev->dev);
7c25769f 4695 } else {
e921eb1a 4696 /* Do not read PHY registers if link is not up
7c25769f
BA		 4697 * Set values to typical power-on defaults
4698 */
4699 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4700 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4701 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4702 BMSR_ERCAP);
4703 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4704 ADVERTISE_ALL | ADVERTISE_CSMA);
4705 phy->lpa = 0;
4706 phy->expansion = EXPANSION_ENABLENPAGE;
4707 phy->ctrl1000 = ADVERTISE_1000FULL;
4708 phy->stat1000 = 0;
4709 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4710 }
7c25769f
BA		 4711}
4712
bc7f75fa
AK		 4713static void e1000_print_link_info(struct e1000_adapter *adapter)
4714{
bc7f75fa
AK		 4715 struct e1000_hw *hw = &adapter->hw;
4716 u32 ctrl = er32(CTRL);
4717
8f12fe86 4718 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4719 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4720 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4721 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4722 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4723 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4724 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4725}
4726
0c6bdb30 4727static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4728{
4729 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4730 bool link_active = false;
318a94d6
JK		 4731 s32 ret_val = 0;
4732
e921eb1a 4733 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4734 * Rx sequence error interrupt. get_link_status will stay
4735 * false until the check_for_link establishes link
4736 * for copper adapters ONLY
4737 */
4738 switch (hw->phy.media_type) {
4739 case e1000_media_type_copper:
4740 if (hw->mac.get_link_status) {
4741 ret_val = hw->mac.ops.check_for_link(hw);
4742 link_active = !hw->mac.get_link_status;
4743 } else {
3db1cd5c 4744 link_active = true;
318a94d6
JK		 4745 }
4746 break;
4747 case e1000_media_type_fiber:
4748 ret_val = hw->mac.ops.check_for_link(hw);
4749 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4750 break;
4751 case e1000_media_type_internal_serdes:
4752 ret_val = hw->mac.ops.check_for_link(hw);
4753 link_active = adapter->hw.mac.serdes_has_link;
4754 break;
4755 default:
4756 case e1000_media_type_unknown:
4757 break;
4758 }
4759
4760 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4761 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4762 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4763 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4764 }
4765
4766 return link_active;
4767}
4768
4769static void e1000e_enable_receives(struct e1000_adapter *adapter)
4770{
4771 /* make sure the receive unit is started */
4772 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4773 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4774 struct e1000_hw *hw = &adapter->hw;
4775 u32 rctl = er32(RCTL);
4776 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4777 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4778 }
4779}
4780
ff10e13c
CW		 4781static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4782{
4783 struct e1000_hw *hw = &adapter->hw;
4784
e921eb1a 4785 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4786 * for hung state and reset, if two calls return true
4787 */
4788 if (e1000_check_phy_82574(hw))
4789 adapter->phy_hang_count++;
4790 else
4791 adapter->phy_hang_count = 0;
4792
4793 if (adapter->phy_hang_count > 1) {
4794 adapter->phy_hang_count = 0;
4795 schedule_work(&adapter->reset_task);
4796 }
4797}
4798
bc7f75fa
AK		 4799/**
4800 * e1000_watchdog - Timer Call-back
4801 * @data: pointer to adapter cast into an unsigned long
4802 **/
4803static void e1000_watchdog(unsigned long data)
4804{
53aa82da 4805 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4806
4807 /* Do the rest outside of interrupt context */
4808 schedule_work(&adapter->watchdog_task);
4809
4810 /* TODO: make this use queue_delayed_work() */
4811}
4812
4813static void e1000_watchdog_task(struct work_struct *work)
4814{
4815 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4816 struct e1000_adapter,
4817 watchdog_task);
bc7f75fa
AK		 4818 struct net_device *netdev = adapter->netdev;
4819 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4820 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4821 struct e1000_ring *tx_ring = adapter->tx_ring;
4822 struct e1000_hw *hw = &adapter->hw;
4823 u32 link, tctl;
bc7f75fa 4824
615b32af
JB		 4825 if (test_bit(__E1000_DOWN, &adapter->state))
4826 return;
4827
b405e8df 4828 link = e1000e_has_link(adapter);
318a94d6 4829 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4830 /* Cancel scheduled suspend requests. */
4831 pm_runtime_resume(netdev->dev.parent);
4832
318a94d6 4833 e1000e_enable_receives(adapter);
bc7f75fa 4834 goto link_up;
bc7f75fa
AK		 4835 }
4836
4837 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4838 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4839 e1000_update_mng_vlan(adapter);
4840
bc7f75fa
AK		 4841 if (link) {
4842 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4843 bool txb2b = true;
23606cf5
RW		 4844
4845 /* Cancel scheduled suspend requests. */
4846 pm_runtime_resume(netdev->dev.parent);
4847
318a94d6 4848 /* update snapshot of PHY registers on LSC */
7c25769f 4849 e1000_phy_read_status(adapter);
bc7f75fa 4850 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4851 &adapter->link_speed,
4852 &adapter->link_duplex);
bc7f75fa 4853 e1000_print_link_info(adapter);
e792cd91
KS		 4854
4855 /* check if SmartSpeed worked */
4856 e1000e_check_downshift(hw);
4857 if (phy->speed_downgraded)
4858 netdev_warn(netdev,
4859 "Link Speed was downgraded by SmartSpeed\n");
4860
e921eb1a 4861 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4862 * if link has autonegotiated at 10/100 half
4863 */
4864 if ((hw->phy.type == e1000_phy_igp_3 ||
4865 hw->phy.type == e1000_phy_bm) &&
4866 (hw->mac.autoneg == true) &&
4867 (adapter->link_speed == SPEED_10 ||
4868 adapter->link_speed == SPEED_100) &&
4869 (adapter->link_duplex == HALF_DUPLEX)) {
4870 u16 autoneg_exp;
4871
c2ade1a4 4872 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4873
c2ade1a4 4874 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4875 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4876 }
4877
f49c57e1 4878 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4879 adapter->tx_timeout_factor = 1;
4880 switch (adapter->link_speed) {
4881 case SPEED_10:
3db1cd5c 4882 txb2b = false;
10f1b492 4883 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4884 break;
4885 case SPEED_100:
3db1cd5c 4886 txb2b = false;
4c86e0b9 4887 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4888 break;
4889 }
4890
e921eb1a 4891 /* workaround: re-program speed mode bit after
ad68076e
BA		 4892 * link-up event
4893 */
bc7f75fa
AK		 4894 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4895 !txb2b) {
4896 u32 tarc0;
e9ec2c0f 4897 tarc0 = er32(TARC(0));
bc7f75fa 4898 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4899 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4900 }
4901
e921eb1a 4902 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4903 * some hardware issues
4904 */
bc7f75fa
AK		 4905 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4906 switch (adapter->link_speed) {
4907 case SPEED_10:
4908 case SPEED_100:
44defeb3 4909 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4910 netdev->features &= ~NETIF_F_TSO;
4911 netdev->features &= ~NETIF_F_TSO6;
4912 break;
4913 case SPEED_1000:
4914 netdev->features |= NETIF_F_TSO;
4915 netdev->features |= NETIF_F_TSO6;
4916 break;
4917 default:
4918 /* oops */
4919 break;
4920 }
4921 }
4922
e921eb1a 4923 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4924 * after setting TARC(0)
4925 */
bc7f75fa
AK		 4926 tctl = er32(TCTL);
4927 tctl |= E1000_TCTL_EN;
4928 ew32(TCTL, tctl);
4929
e921eb1a 4930 /* Perform any post-link-up configuration before
75eb0fad
BA		 4931 * reporting link up.
4932 */
4933 if (phy->ops.cfg_on_link_up)
4934 phy->ops.cfg_on_link_up(hw);
4935
bc7f75fa 4936 netif_carrier_on(netdev);
bc7f75fa
AK		 4937
4938 if (!test_bit(__E1000_DOWN, &adapter->state))
4939 mod_timer(&adapter->phy_info_timer,
4940 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4941 }
4942 } else {
4943 if (netif_carrier_ok(netdev)) {
4944 adapter->link_speed = 0;
4945 adapter->link_duplex = 0;
8f12fe86 4946 /* Link status message must follow this format */
7dbc1672 4947 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4948 netif_carrier_off(netdev);
bc7f75fa
AK		 4949 if (!test_bit(__E1000_DOWN, &adapter->state))
4950 mod_timer(&adapter->phy_info_timer,
4951 round_jiffies(jiffies + 2 * HZ));
4952
12d43f7d
BA		 4953 /* The link is lost so the controller stops DMA.
4954 * If there is queued Tx work that cannot be done
4955 * or if on an 8000ES2LAN which requires a Rx packet
4956 * buffer work-around on link down event, reset the
4957 * controller to flush the Tx/Rx packet buffers.
4958 * (Do the reset outside of interrupt context).
4959 */
4960 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4961 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4962 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4963 else
4964 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4965 LINK_TIMEOUT);
bc7f75fa
AK		 4966 }
4967 }
4968
4969link_up:
67fd4fcb 4970 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4971 e1000e_update_stats(adapter);
4972
4973 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4974 adapter->tpt_old = adapter->stats.tpt;
4975 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4976 adapter->colc_old = adapter->stats.colc;
4977
7c25769f
BA		 4978 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4979 adapter->gorc_old = adapter->stats.gorc;
4980 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4981 adapter->gotc_old = adapter->stats.gotc;
2084b114 4982 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4983
12d43f7d 4984 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4985 schedule_work(&adapter->reset_task);
4986 /* return immediately since reset is imminent */
4987 return;
bc7f75fa
AK		 4988 }
4989
12d43f7d
BA		 4990 e1000e_update_adaptive(&adapter->hw);
4991
eab2abf5
JB		 4992 /* Simple mode for Interrupt Throttle Rate (ITR) */
4993 if (adapter->itr_setting == 4) {
e921eb1a 4994 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4995 * Total asymmetrical Tx or Rx gets ITR=8000;
4996 * everyone else is between 2000-8000.
4997 */
4998 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4999 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5000 adapter->gotc - adapter->gorc :
5001 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5002 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5003
22a4cca2 5004 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5005 }
5006
ad68076e 5007 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5008 if (adapter->msix_entries)
5009 ew32(ICS, adapter->rx_ring->ims_val);
5010 else
5011 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5012
713b3c9e
JB		 5013 /* flush pending descriptors to memory before detecting Tx hang */
5014 e1000e_flush_descriptors(adapter);
5015
bc7f75fa 5016 /* Force detection of hung controller every watchdog period */
3db1cd5c 5017 adapter->detect_tx_hung = true;
bc7f75fa 5018
e921eb1a 5019 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5020 * reset from the other port. Set the appropriate LAA in RAR[0]
5021 */
bc7f75fa 5022 if (e1000e_get_laa_state_82571(hw))
69e1e019 5023 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5024
ff10e13c
CW		 5025 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5026 e1000e_check_82574_phy_workaround(adapter);
5027
b67e1913
BA		 5028 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5029 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5030 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5031 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5032 er32(RXSTMPH);
5033 adapter->rx_hwtstamp_cleared++;
5034 } else {
5035 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5036 }
5037 }
5038
bc7f75fa
AK		 5039 /* Reset the timer */
5040 if (!test_bit(__E1000_DOWN, &adapter->state))
5041 mod_timer(&adapter->watchdog_timer,
5042 round_jiffies(jiffies + 2 * HZ));
5043}
5044
5045#define E1000_TX_FLAGS_CSUM 0x00000001
5046#define E1000_TX_FLAGS_VLAN 0x00000002
5047#define E1000_TX_FLAGS_TSO 0x00000004
5048#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5049#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5050#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5051#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5052#define E1000_TX_FLAGS_VLAN_SHIFT 16
5053
55aa6985 5054static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5055{
bc7f75fa
AK		 5056 struct e1000_context_desc *context_desc;
5057 struct e1000_buffer *buffer_info;
5058 unsigned int i;
5059 u32 cmd_length = 0;
70443ae9 5060 u16 ipcse = 0, mss;
bc7f75fa 5061 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5062
3d5e33c9
BA		 5063 if (!skb_is_gso(skb))
5064 return 0;
bc7f75fa 5065
3d5e33c9 5066 if (skb_header_cloned(skb)) {
90da0669
BA		 5067 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5068
3d5e33c9
BA		 5069 if (err)
5070 return err;
bc7f75fa
AK		 5071 }
5072
3d5e33c9
BA		 5073 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5074 mss = skb_shinfo(skb)->gso_size;
5075 if (skb->protocol == htons(ETH_P_IP)) {
5076 struct iphdr *iph = ip_hdr(skb);
5077 iph->tot_len = 0;
5078 iph->check = 0;
5079 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5080 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5081 cmd_length = E1000_TXD_CMD_IP;
5082 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5083 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5084 ipv6_hdr(skb)->payload_len = 0;
5085 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5086 &ipv6_hdr(skb)->daddr,
5087 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5088 ipcse = 0;
5089 }
5090 ipcss = skb_network_offset(skb);
5091 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5092 tucss = skb_transport_offset(skb);
5093 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5094
5095 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5096 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5097
5098 i = tx_ring->next_to_use;
5099 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5100 buffer_info = &tx_ring->buffer_info[i];
5101
5102 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5103 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5104 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5105 context_desc->upper_setup.tcp_fields.tucss = tucss;
5106 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5107 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 5108 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5109 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5110 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5111
5112 buffer_info->time_stamp = jiffies;
5113 buffer_info->next_to_watch = i;
5114
5115 i++;
5116 if (i == tx_ring->count)
5117 i = 0;
5118 tx_ring->next_to_use = i;
5119
5120 return 1;
bc7f75fa
AK		 5121}
5122
55aa6985 5123static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5124{
55aa6985 5125 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5126 struct e1000_context_desc *context_desc;
5127 struct e1000_buffer *buffer_info;
5128 unsigned int i;
5129 u8 css;
af807c82 5130 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5131 __be16 protocol;
bc7f75fa 5132
af807c82
DG		 5133 if (skb->ip_summed != CHECKSUM_PARTIAL)
5134 return 0;
bc7f75fa 5135
5f66f208
AJ		 5136 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5137 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5138 else
5139 protocol = skb->protocol;
5140
3f518390 5141 switch (protocol) {
09640e63 5142 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5143 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5144 cmd_len |= E1000_TXD_CMD_TCP;
5145 break;
09640e63 5146 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5147 /* XXX not handling all IPV6 headers */
5148 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5149 cmd_len |= E1000_TXD_CMD_TCP;
5150 break;
5151 default:
5152 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5153 e_warn("checksum_partial proto=%x!\n",
5154 be16_to_cpu(protocol));
af807c82 5155 break;
bc7f75fa
AK		 5156 }
5157
0d0b1672 5158 css = skb_checksum_start_offset(skb);
af807c82
DG		 5159
5160 i = tx_ring->next_to_use;
5161 buffer_info = &tx_ring->buffer_info[i];
5162 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5163
5164 context_desc->lower_setup.ip_config = 0;
5165 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5166 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5167 context_desc->upper_setup.tcp_fields.tucse = 0;
5168 context_desc->tcp_seg_setup.data = 0;
5169 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5170
5171 buffer_info->time_stamp = jiffies;
5172 buffer_info->next_to_watch = i;
5173
5174 i++;
5175 if (i == tx_ring->count)
5176 i = 0;
5177 tx_ring->next_to_use = i;
5178
5179 return 1;
bc7f75fa
AK		 5180}
5181
55aa6985
BA		 5182static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5183 unsigned int first, unsigned int max_per_txd,
d821a4c4 5184 unsigned int nr_frags)
bc7f75fa 5185{
55aa6985 5186 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5187 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5188 struct e1000_buffer *buffer_info;
8ddc951c 5189 unsigned int len = skb_headlen(skb);
03b1320d 5190 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5191 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5192
5193 i = tx_ring->next_to_use;
5194
5195 while (len) {
1b7719c4 5196 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5197 size = min(len, max_per_txd);
5198
bc7f75fa 5199 buffer_info->length = size;
bc7f75fa 5200 buffer_info->time_stamp = jiffies;
bc7f75fa 5201 buffer_info->next_to_watch = i;
0be3f55f
NN		 5202 buffer_info->dma = dma_map_single(&pdev->dev,
5203 skb->data + offset,
af667a29 5204 size, DMA_TO_DEVICE);
03b1320d 5205 buffer_info->mapped_as_page = false;
0be3f55f 5206 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5207 goto dma_error;
bc7f75fa
AK		 5208
5209 len -= size;
5210 offset += size;
03b1320d 5211 count++;
1b7719c4
AD		 5212
5213 if (len) {
5214 i++;
5215 if (i == tx_ring->count)
5216 i = 0;
5217 }
bc7f75fa
AK		 5218 }
5219
5220 for (f = 0; f < nr_frags; f++) {
9e903e08 5221 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5222
5223 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5224 len = skb_frag_size(frag);
877749bf 5225 offset = 0;
bc7f75fa
AK		 5226
5227 while (len) {
1b7719c4
AD		 5228 i++;
5229 if (i == tx_ring->count)
5230 i = 0;
5231
bc7f75fa
AK		 5232 buffer_info = &tx_ring->buffer_info[i];
5233 size = min(len, max_per_txd);
bc7f75fa
AK		 5234
5235 buffer_info->length = size;
5236 buffer_info->time_stamp = jiffies;
bc7f75fa 5237 buffer_info->next_to_watch = i;
877749bf 5238 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5239 offset, size,
5240 DMA_TO_DEVICE);
03b1320d 5241 buffer_info->mapped_as_page = true;
0be3f55f 5242 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5243 goto dma_error;
bc7f75fa
AK		 5244
5245 len -= size;
5246 offset += size;
5247 count++;
bc7f75fa
AK		 5248 }
5249 }
5250
af667a29 5251 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5252 /* multiply data chunks by size of headers */
5253 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5254
bc7f75fa 5255 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5256 tx_ring->buffer_info[i].segs = segs;
5257 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5258 tx_ring->buffer_info[first].next_to_watch = i;
5259
5260 return count;
03b1320d
AD		 5261
5262dma_error:
af667a29 5263 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5264 buffer_info->dma = 0;
c1fa347f 5265 if (count)
03b1320d 5266 count--;
c1fa347f
RK		 5267
5268 while (count--) {
af667a29 5269 if (i == 0)
03b1320d 5270 i += tx_ring->count;
c1fa347f 5271 i--;
03b1320d 5272 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5273 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5274 }
5275
5276 return 0;
bc7f75fa
AK		 5277}
5278
55aa6985 5279static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5280{
55aa6985 5281 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5282 struct e1000_tx_desc *tx_desc = NULL;
5283 struct e1000_buffer *buffer_info;
5284 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5285 unsigned int i;
5286
5287 if (tx_flags & E1000_TX_FLAGS_TSO) {
5288 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5289 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5290 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5291
5292 if (tx_flags & E1000_TX_FLAGS_IPV4)
5293 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5294 }
5295
5296 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5297 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5298 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5299 }
5300
5301 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5302 txd_lower |= E1000_TXD_CMD_VLE;
5303 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5304 }
5305
943146de
BG		 5306 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5307 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5308
b67e1913
BA		 5309 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5310 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5311 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5312 }
5313
bc7f75fa
AK		 5314 i = tx_ring->next_to_use;
5315
36b973df 5316 do {
bc7f75fa
AK		 5317 buffer_info = &tx_ring->buffer_info[i];
5318 tx_desc = E1000_TX_DESC(*tx_ring, i);
5319 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5320 tx_desc->lower.data = cpu_to_le32(txd_lower |
5321 buffer_info->length);
bc7f75fa
AK		 5322 tx_desc->upper.data = cpu_to_le32(txd_upper);
5323
5324 i++;
5325 if (i == tx_ring->count)
5326 i = 0;
36b973df 5327 } while (--count > 0);
bc7f75fa
AK		 5328
5329 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5330
943146de
BG		 5331 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5332 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5333 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5334
e921eb1a 5335 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5336 * know there are new descriptors to fetch. (Only
5337 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5338 * such as IA-64).
5339 */
bc7f75fa
AK		 5340 wmb();
5341
5342 tx_ring->next_to_use = i;
c6e7f51e
BA		 5343
5344 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5345 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5346 else
c5083cf6 5347 writel(i, tx_ring->tail);
c6e7f51e 5348
e921eb1a 5349 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5350 * at a time, it synchronizes IO on IA64/Altix systems
5351 */
bc7f75fa
AK		 5352 mmiowb();
5353}
5354
5355#define MINIMUM_DHCP_PACKET_SIZE 282
5356static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5357 struct sk_buff *skb)
5358{
5359 struct e1000_hw *hw = &adapter->hw;
5360 u16 length, offset;
5361
d60923c4
BA		 5362 if (vlan_tx_tag_present(skb) &&
5363 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5364 (adapter->hw.mng_cookie.status &
5365 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5366 return 0;
bc7f75fa
AK		 5367
5368 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5369 return 0;
5370
53aa82da 5371 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5372 return 0;
5373
5374 {
362e20ca 5375 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5376 struct udphdr *udp;
5377
5378 if (ip->protocol != IPPROTO_UDP)
5379 return 0;
5380
5381 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5382 if (ntohs(udp->dest) != 67)
5383 return 0;
5384
5385 offset = (u8 *)udp + 8 - skb->data;
5386 length = skb->len - offset;
5387 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5388 }
5389
5390 return 0;
5391}
5392
55aa6985 5393static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5394{
55aa6985 5395 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5396
55aa6985 5397 netif_stop_queue(adapter->netdev);
e921eb1a 5398 /* Herbert's original patch had:
bc7f75fa 5399 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5400 * but since that doesn't exist yet, just open code it.
5401 */
bc7f75fa
AK		 5402 smp_mb();
5403
e921eb1a 5404 /* We need to check again in a case another CPU has just
ad68076e
BA		 5405 * made room available.
5406 */
55aa6985 5407 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5408 return -EBUSY;
5409
5410 /* A reprieve! */
55aa6985 5411 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5412 ++adapter->restart_queue;
5413 return 0;
5414}
5415
55aa6985 5416static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5417{
d821a4c4
BA		 5418 BUG_ON(size > tx_ring->count);
5419
55aa6985 5420 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5421 return 0;
55aa6985 5422 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5423}
5424
3b29a56d
SH		 5425static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5426 struct net_device *netdev)
bc7f75fa
AK		 5427{
5428 struct e1000_adapter *adapter = netdev_priv(netdev);
5429 struct e1000_ring *tx_ring = adapter->tx_ring;
5430 unsigned int first;
bc7f75fa 5431 unsigned int tx_flags = 0;
e743d313 5432 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5433 unsigned int nr_frags;
5434 unsigned int mss;
bc7f75fa
AK		 5435 int count = 0;
5436 int tso;
5437 unsigned int f;
bc7f75fa
AK		 5438
5439 if (test_bit(__E1000_DOWN, &adapter->state)) {
5440 dev_kfree_skb_any(skb);
5441 return NETDEV_TX_OK;
5442 }
5443
5444 if (skb->len <= 0) {
5445 dev_kfree_skb_any(skb);
5446 return NETDEV_TX_OK;
5447 }
5448
e921eb1a 5449 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5450 * pad skb in order to meet this minimum size requirement
5451 */
5452 if (unlikely(skb->len < 17)) {
5453 if (skb_pad(skb, 17 - skb->len))
5454 return NETDEV_TX_OK;
5455 skb->len = 17;
5456 skb_set_tail_pointer(skb, 17);
5457 }
5458
bc7f75fa 5459 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5460 if (mss) {
5461 u8 hdr_len;
bc7f75fa 5462
e921eb1a 5463 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5464 * points to just header, pull a few bytes of payload from
5465 * frags into skb->data
5466 */
bc7f75fa 5467 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5468 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5469 * avoiding it could save a lot of cycles
5470 */
4e6c709c 5471 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5472 unsigned int pull_size;
5473
a2a5b323 5474 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5475 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5476 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5477 dev_kfree_skb_any(skb);
5478 return NETDEV_TX_OK;
5479 }
e743d313 5480 len = skb_headlen(skb);
bc7f75fa
AK		 5481 }
5482 }
5483
5484 /* reserve a descriptor for the offload context */
5485 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5486 count++;
5487 count++;
5488
d821a4c4 5489 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5490
5491 nr_frags = skb_shinfo(skb)->nr_frags;
5492 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5493 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5494 adapter->tx_fifo_limit);
bc7f75fa
AK		 5495
5496 if (adapter->hw.mac.tx_pkt_filtering)
5497 e1000_transfer_dhcp_info(adapter, skb);
5498
e921eb1a 5499 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5500 * head, otherwise try next time
5501 */
55aa6985 5502 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5503 return NETDEV_TX_BUSY;
bc7f75fa 5504
eab6d18d 5505 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5506 tx_flags |= E1000_TX_FLAGS_VLAN;
5507 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5508 }
5509
5510 first = tx_ring->next_to_use;
5511
55aa6985 5512 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5513 if (tso < 0) {
5514 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5515 return NETDEV_TX_OK;
5516 }
5517
5518 if (tso)
5519 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5520 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5521 tx_flags |= E1000_TX_FLAGS_CSUM;
5522
e921eb1a 5523 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5524 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5525 * no longer assume, we must.
5526 */
bc7f75fa
AK		 5527 if (skb->protocol == htons(ETH_P_IP))
5528 tx_flags |= E1000_TX_FLAGS_IPV4;
5529
943146de
BG		 5530 if (unlikely(skb->no_fcs))
5531 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5532
25985edc 5533 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5534 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5535 nr_frags);
1b7719c4 5536 if (count) {
b67e1913
BA		 5537 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5538 !adapter->tx_hwtstamp_skb)) {
5539 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5540 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5541 adapter->tx_hwtstamp_skb = skb_get(skb);
5542 schedule_work(&adapter->tx_hwtstamp_work);
5543 } else {
5544 skb_tx_timestamp(skb);
5545 }
80be3129 5546
3f0cfa3b 5547 netdev_sent_queue(netdev, skb->len);
55aa6985 5548 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5549 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5550 e1000_maybe_stop_tx(tx_ring,
5551 (MAX_SKB_FRAGS *
5552 DIV_ROUND_UP(PAGE_SIZE,
5553 adapter->tx_fifo_limit) + 2));
1b7719c4 5554 } else {
bc7f75fa 5555 dev_kfree_skb_any(skb);
1b7719c4
AD		 5556 tx_ring->buffer_info[first].time_stamp = 0;
5557 tx_ring->next_to_use = first;
bc7f75fa
AK		 5558 }
5559
bc7f75fa
AK		 5560 return NETDEV_TX_OK;
5561}
5562
5563/**
5564 * e1000_tx_timeout - Respond to a Tx Hang
5565 * @netdev: network interface device structure
5566 **/
5567static void e1000_tx_timeout(struct net_device *netdev)
5568{
5569 struct e1000_adapter *adapter = netdev_priv(netdev);
5570
5571 /* Do the reset outside of interrupt context */
5572 adapter->tx_timeout_count++;
5573 schedule_work(&adapter->reset_task);
5574}
5575
5576static void e1000_reset_task(struct work_struct *work)
5577{
5578 struct e1000_adapter *adapter;
5579 adapter = container_of(work, struct e1000_adapter, reset_task);
5580
615b32af
JB		 5581 /* don't run the task if already down */
5582 if (test_bit(__E1000_DOWN, &adapter->state))
5583 return;
5584
12d43f7d 5585 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5586 e1000e_dump(adapter);
12d43f7d 5587 e_err("Reset adapter unexpectedly\n");
affa9dfb 5588 }
bc7f75fa
AK		 5589 e1000e_reinit_locked(adapter);
5590}
5591
5592/**
67fd4fcb 5593 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5594 * @netdev: network interface device structure
67fd4fcb 5595 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5596 *
5597 * Returns the address of the device statistics structure.
bc7f75fa 5598 **/
67fd4fcb 5599struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5600 struct rtnl_link_stats64 *stats)
bc7f75fa 5601{
67fd4fcb
JK		 5602 struct e1000_adapter *adapter = netdev_priv(netdev);
5603
5604 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5605 spin_lock(&adapter->stats64_lock);
5606 e1000e_update_stats(adapter);
5607 /* Fill out the OS statistics structure */
5608 stats->rx_bytes = adapter->stats.gorc;
5609 stats->rx_packets = adapter->stats.gprc;
5610 stats->tx_bytes = adapter->stats.gotc;
5611 stats->tx_packets = adapter->stats.gptc;
5612 stats->multicast = adapter->stats.mprc;
5613 stats->collisions = adapter->stats.colc;
5614
5615 /* Rx Errors */
5616
e921eb1a 5617 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5618 * our own version based on RUC and ROC
5619 */
5620 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5621 adapter->stats.crcerrs + adapter->stats.algnerrc +
5622 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5623 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5624 stats->rx_crc_errors = adapter->stats.crcerrs;
5625 stats->rx_frame_errors = adapter->stats.algnerrc;
5626 stats->rx_missed_errors = adapter->stats.mpc;
5627
5628 /* Tx Errors */
f0ff4398 5629 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5630 stats->tx_aborted_errors = adapter->stats.ecol;
5631 stats->tx_window_errors = adapter->stats.latecol;
5632 stats->tx_carrier_errors = adapter->stats.tncrs;
5633
5634 /* Tx Dropped needs to be maintained elsewhere */
5635
5636 spin_unlock(&adapter->stats64_lock);
5637 return stats;
bc7f75fa
AK		 5638}
5639
5640/**
5641 * e1000_change_mtu - Change the Maximum Transfer Unit
5642 * @netdev: network interface device structure
5643 * @new_mtu: new value for maximum frame size
5644 *
5645 * Returns 0 on success, negative on failure
5646 **/
5647static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5648{
5649 struct e1000_adapter *adapter = netdev_priv(netdev);
5650 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5651
2adc55c9 5652 /* Jumbo frame support */
2e1706f2
BA		 5653 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5654 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5655 e_err("Jumbo Frames not supported.\n");
5656 return -EINVAL;
bc7f75fa
AK		 5657 }
5658
2adc55c9
BA		 5659 /* Supported frame sizes */
5660 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5661 (max_frame > adapter->max_hw_frame_size)) {
5662 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5663 return -EINVAL;
5664 }
5665
2fbe4526
BA		 5666 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5667 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5668 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5669 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5670 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5671 return -EINVAL;
5672 }
5673
bc7f75fa 5674 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5675 usleep_range(1000, 2000);
610c9928 5676 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5677 adapter->max_frame_size = max_frame;
610c9928
BA		 5678 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5679 netdev->mtu = new_mtu;
bc7f75fa
AK		 5680 if (netif_running(netdev))
5681 e1000e_down(adapter);
5682
e921eb1a 5683 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5684 * means we reserve 2 more, this pushes us to allocate from the next
5685 * larger slab size.
ad68076e 5686 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5687 * However with the new *_jumbo_rx* routines, jumbo receives will use
5688 * fragmented skbs
ad68076e 5689 */
bc7f75fa 5690
9926146b 5691 if (max_frame <= 2048)
bc7f75fa
AK		 5692 adapter->rx_buffer_len = 2048;
5693 else
5694 adapter->rx_buffer_len = 4096;
5695
5696 /* adjust allocation if LPE protects us, and we aren't using SBP */
5697 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5698 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5699 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5700 + ETH_FCS_LEN;
bc7f75fa 5701
bc7f75fa
AK		 5702 if (netif_running(netdev))
5703 e1000e_up(adapter);
5704 else
5705 e1000e_reset(adapter);
5706
5707 clear_bit(__E1000_RESETTING, &adapter->state);
5708
5709 return 0;
5710}
5711
5712static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5713 int cmd)
5714{
5715 struct e1000_adapter *adapter = netdev_priv(netdev);
5716 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5717
318a94d6 5718 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5719 return -EOPNOTSUPP;
5720
5721 switch (cmd) {
5722 case SIOCGMIIPHY:
5723 data->phy_id = adapter->hw.phy.addr;
5724 break;
5725 case SIOCGMIIREG:
b16a002e
BA		 5726 e1000_phy_read_status(adapter);
5727
7c25769f
BA		 5728 switch (data->reg_num & 0x1F) {
5729 case MII_BMCR:
5730 data->val_out = adapter->phy_regs.bmcr;
5731 break;
5732 case MII_BMSR:
5733 data->val_out = adapter->phy_regs.bmsr;
5734 break;
5735 case MII_PHYSID1:
5736 data->val_out = (adapter->hw.phy.id >> 16);
5737 break;
5738 case MII_PHYSID2:
5739 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5740 break;
5741 case MII_ADVERTISE:
5742 data->val_out = adapter->phy_regs.advertise;
5743 break;
5744 case MII_LPA:
5745 data->val_out = adapter->phy_regs.lpa;
5746 break;
5747 case MII_EXPANSION:
5748 data->val_out = adapter->phy_regs.expansion;
5749 break;
5750 case MII_CTRL1000:
5751 data->val_out = adapter->phy_regs.ctrl1000;
5752 break;
5753 case MII_STAT1000:
5754 data->val_out = adapter->phy_regs.stat1000;
5755 break;
5756 case MII_ESTATUS:
5757 data->val_out = adapter->phy_regs.estatus;
5758 break;
5759 default:
bc7f75fa
AK		 5760 return -EIO;
5761 }
bc7f75fa
AK		 5762 break;
5763 case SIOCSMIIREG:
5764 default:
5765 return -EOPNOTSUPP;
5766 }
5767 return 0;
5768}
5769
b67e1913
BA		 5770/**
5771 * e1000e_hwtstamp_ioctl - control hardware time stamping
5772 * @netdev: network interface device structure
5773 * @ifreq: interface request
5774 *
5775 * Outgoing time stamping can be enabled and disabled. Play nice and
5776 * disable it when requested, although it shouldn't cause any overhead
5777 * when no packet needs it. At most one packet in the queue may be
5778 * marked for time stamping, otherwise it would be impossible to tell
5779 * for sure to which packet the hardware time stamp belongs.
5780 *
5781 * Incoming time stamping has to be configured via the hardware filters.
5782 * Not all combinations are supported, in particular event type has to be
5783 * specified. Matching the kind of event packet is not supported, with the
5784 * exception of "all V2 events regardless of level 2 or 4".
5785 **/
5786static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5787{
5788 struct e1000_adapter *adapter = netdev_priv(netdev);
5789 struct hwtstamp_config config;
5790 int ret_val;
5791
5792 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5793 return -EFAULT;
5794
5795 adapter->hwtstamp_config = config;
5796
5797 ret_val = e1000e_config_hwtstamp(adapter);
5798 if (ret_val)
5799 return ret_val;
5800
5801 config = adapter->hwtstamp_config;
5802
d89777bf
BA		 5803 switch (config.rx_filter) {
5804 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5805 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5806 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5807 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5808 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5809 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5810 /* With V2 type filters which specify a Sync or Delay Request,
5811 * Path Delay Request/Response messages are also time stamped
5812 * by hardware so notify the caller the requested packets plus
5813 * some others are time stamped.
5814 */
5815 config.rx_filter = HWTSTAMP_FILTER_SOME;
5816 break;
5817 default:
5818 break;
5819 }
5820
b67e1913
BA		 5821 return copy_to_user(ifr->ifr_data, &config,
5822 sizeof(config)) ? -EFAULT : 0;
5823}
5824
bc7f75fa
AK		 5825static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5826{
5827 switch (cmd) {
5828 case SIOCGMIIPHY:
5829 case SIOCGMIIREG:
5830 case SIOCSMIIREG:
5831 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913
BA		 5832 case SIOCSHWTSTAMP:
5833 return e1000e_hwtstamp_ioctl(netdev, ifr);
bc7f75fa
AK		 5834 default:
5835 return -EOPNOTSUPP;
5836 }
5837}
5838
a4f58f54
BA		 5839static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5840{
5841 struct e1000_hw *hw = &adapter->hw;
5842 u32 i, mac_reg;
2b6b168d 5843 u16 phy_reg, wuc_enable;
70806a7f 5844 int retval;
a4f58f54
BA		 5845
5846 /* copy MAC RARs to PHY RARs */
d3738bb8 5847 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5848
2b6b168d
BA		 5849 retval = hw->phy.ops.acquire(hw);
5850 if (retval) {
5851 e_err("Could not acquire PHY\n");
5852 return retval;
5853 }
5854
5855 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5856 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5857 if (retval)
75ce1532 5858 goto release;
2b6b168d
BA		 5859
5860 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5861 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5862 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5863 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5864 (u16)(mac_reg & 0xFFFF));
5865 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5866 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5867 }
5868
5869 /* configure PHY Rx Control register */
2b6b168d 5870 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5871 mac_reg = er32(RCTL);
5872 if (mac_reg & E1000_RCTL_UPE)
5873 phy_reg |= BM_RCTL_UPE;
5874 if (mac_reg & E1000_RCTL_MPE)
5875 phy_reg |= BM_RCTL_MPE;
5876 phy_reg &= ~(BM_RCTL_MO_MASK);
5877 if (mac_reg & E1000_RCTL_MO_3)
5878 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5879 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5880 if (mac_reg & E1000_RCTL_BAM)
5881 phy_reg |= BM_RCTL_BAM;
5882 if (mac_reg & E1000_RCTL_PMCF)
5883 phy_reg |= BM_RCTL_PMCF;
5884 mac_reg = er32(CTRL);
5885 if (mac_reg & E1000_CTRL_RFCE)
5886 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5887 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5888
5889 /* enable PHY wakeup in MAC register */
5890 ew32(WUFC, wufc);
5891 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5892
5893 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5894 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5895 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5896
5897 /* activate PHY wakeup */
2b6b168d
BA		 5898 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5899 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5900 if (retval)
5901 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5902release:
94d8186a 5903 hw->phy.ops.release(hw);
a4f58f54
BA		 5904
5905 return retval;
5906}
5907
66148bab 5908static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
bc7f75fa
AK		 5909{
5910 struct net_device *netdev = pci_get_drvdata(pdev);
5911 struct e1000_adapter *adapter = netdev_priv(netdev);
5912 struct e1000_hw *hw = &adapter->hw;
5913 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5914 /* Runtime suspend should only enable wakeup for link changes */
5915 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5916 int retval = 0;
5917
5918 netif_device_detach(netdev);
5919
5920 if (netif_running(netdev)) {
bb9e44d0
BA		 5921 int count = E1000_CHECK_RESET_COUNT;
5922
5923 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5924 usleep_range(10000, 20000);
5925
bc7f75fa
AK		 5926 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5927 e1000e_down(adapter);
5928 e1000_free_irq(adapter);
5929 }
4662e82b 5930 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 5931
bc7f75fa
AK		 5932 status = er32(STATUS);
5933 if (status & E1000_STATUS_LU)
5934 wufc &= ~E1000_WUFC_LNKC;
5935
5936 if (wufc) {
5937 e1000_setup_rctl(adapter);
ef9b965a 5938 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5939
5940 /* turn on all-multi mode if wake on multicast is enabled */
5941 if (wufc & E1000_WUFC_MC) {
5942 rctl = er32(RCTL);
5943 rctl |= E1000_RCTL_MPE;
5944 ew32(RCTL, rctl);
5945 }
5946
5947 ctrl = er32(CTRL);
a4f58f54
BA		 5948 ctrl |= E1000_CTRL_ADVD3WUC;
5949 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5950 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5951 ew32(CTRL, ctrl);
5952
318a94d6
JK		 5953 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5954 adapter->hw.phy.media_type ==
5955 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5956 /* keep the laser running in D3 */
5957 ctrl_ext = er32(CTRL_EXT);
93a23f48 5958 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5959 ew32(CTRL_EXT, ctrl_ext);
5960 }
5961
97ac8cae 5962 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5963 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5964
bc7f75fa
AK		 5965 /* Allow time for pending master requests to run */
5966 e1000e_disable_pcie_master(&adapter->hw);
5967
82776a4b 5968 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5969 /* enable wakeup by the PHY */
5970 retval = e1000_init_phy_wakeup(adapter, wufc);
5971 if (retval)
5972 return retval;
5973 } else {
5974 /* enable wakeup by the MAC */
5975 ew32(WUFC, wufc);
5976 ew32(WUC, E1000_WUC_PME_EN);
5977 }
bc7f75fa
AK		 5978 } else {
5979 ew32(WUC, 0);
5980 ew32(WUFC, 0);
bc7f75fa
AK		 5981 }
5982
bc7f75fa
AK		 5983 if (adapter->hw.phy.type == e1000_phy_igp_3)
5984 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5985
e921eb1a 5986 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5987 * would have already happened in close and is redundant.
5988 */
31dbe5b4 5989 e1000e_release_hw_control(adapter);
bc7f75fa 5990
e921eb1a 5991 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 5992 * correctable error when the MAC transitions from D0 to D3. To
5993 * prevent this we need to mask off the correctable errors on the
5994 * downstream port of the pci-e switch.
5995 */
5996 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5997 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 5998 u16 devctl;
5999
f8c0fcac
JL		 6000 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6001 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6002 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6003
66148bab
KK		 6004 pci_save_state(pdev);
6005 pci_prepare_to_sleep(pdev);
005cbdfc 6006
f8c0fcac 6007 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6008 }
66148bab
KK		 6009
6010 return 0;
bc7f75fa
AK		 6011}
6012
6f461f6c
BA		 6013#ifdef CONFIG_PCIEASPM
6014static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6015{
9f728f53 6016 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 6017}
6018#else
6019static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 6020{
ffe0b2ff
BH		 6021 u16 aspm_ctl = 0;
6022
6023 if (state & PCIE_LINK_STATE_L0S)
6024 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
6025 if (state & PCIE_LINK_STATE_L1)
6026 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
6027
e921eb1a 6028 /* Both device and parent should have the same ASPM setting.
6f461f6c 6029 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6030 */
ffe0b2ff 6031 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
0c75ba22 6032
f8c0fcac
JL		 6033 if (pdev->bus->self)
6034 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
ffe0b2ff 6035 aspm_ctl);
6f461f6c
BA		 6036}
6037#endif
78cd29d5 6038static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 6039{
6040 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6041 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
6042 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
6043
6044 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 6045}
6046
aa338601 6047#ifdef CONFIG_PM
23606cf5 6048static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 6049{
23606cf5 6050 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 6051}
6052
23606cf5 6053static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6054{
6055 struct net_device *netdev = pci_get_drvdata(pdev);
6056 struct e1000_adapter *adapter = netdev_priv(netdev);
6057 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6058 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6059 u32 err;
6060
78cd29d5
BA		 6061 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6062 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6063 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6064 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6065 if (aspm_disable_flag)
6066 e1000e_disable_aspm(pdev, aspm_disable_flag);
6067
66148bab 6068 pci_set_master(pdev);
6e4f6f6b 6069
4662e82b 6070 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 6071 if (netif_running(netdev)) {
6072 err = e1000_request_irq(adapter);
6073 if (err)
6074 return err;
6075 }
6076
2fbe4526 6077 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6078 e1000_resume_workarounds_pchlan(&adapter->hw);
6079
bc7f75fa 6080 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6081
6082 /* report the system wakeup cause from S3/S4 */
6083 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6084 u16 phy_data;
6085
6086 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6087 if (phy_data) {
6088 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6089 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6090 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6091 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6092 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6093 phy_data & E1000_WUS_LNKC ?
6094 "Link Status Change" : "other");
a4f58f54
BA		 6095 }
6096 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6097 } else {
6098 u32 wus = er32(WUS);
6099 if (wus) {
6100 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6101 wus & E1000_WUS_EX ? "Unicast Packet" :
6102 wus & E1000_WUS_MC ? "Multicast Packet" :
6103 wus & E1000_WUS_BC ? "Broadcast Packet" :
6104 wus & E1000_WUS_MAG ? "Magic Packet" :
6105 wus & E1000_WUS_LNKC ? "Link Status Change" :
6106 "other");
a4f58f54
BA		 6107 }
6108 ew32(WUS, ~0);
6109 }
6110
bc7f75fa 6111 e1000e_reset(adapter);
bc7f75fa 6112
cd791618 6113 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6114
6115 if (netif_running(netdev))
6116 e1000e_up(adapter);
6117
6118 netif_device_attach(netdev);
6119
e921eb1a 6120 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6121 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6122 * under the control of the driver.
6123 */
c43bc57e 6124 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6125 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6126
6127 return 0;
6128}
23606cf5 6129
a0340162
RW		 6130#ifdef CONFIG_PM_SLEEP
6131static int e1000_suspend(struct device *dev)
6132{
6133 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6134
66148bab 6135 return __e1000_shutdown(pdev, false);
a0340162
RW		 6136}
6137
23606cf5
RW		 6138static int e1000_resume(struct device *dev)
6139{
6140 struct pci_dev *pdev = to_pci_dev(dev);
6141 struct net_device *netdev = pci_get_drvdata(pdev);
6142 struct e1000_adapter *adapter = netdev_priv(netdev);
6143
6144 if (e1000e_pm_ready(adapter))
6145 adapter->idle_check = true;
6146
6147 return __e1000_resume(pdev);
6148}
a0340162
RW		 6149#endif /* CONFIG_PM_SLEEP */
6150
6151#ifdef CONFIG_PM_RUNTIME
6152static int e1000_runtime_suspend(struct device *dev)
6153{
6154 struct pci_dev *pdev = to_pci_dev(dev);
6155 struct net_device *netdev = pci_get_drvdata(pdev);
6156 struct e1000_adapter *adapter = netdev_priv(netdev);
6157
66148bab
KK		 6158 if (!e1000e_pm_ready(adapter))
6159 return 0;
a0340162 6160
66148bab 6161 return __e1000_shutdown(pdev, true);
a0340162
RW		 6162}
6163
6164static int e1000_idle(struct device *dev)
6165{
6166 struct pci_dev *pdev = to_pci_dev(dev);
6167 struct net_device *netdev = pci_get_drvdata(pdev);
6168 struct e1000_adapter *adapter = netdev_priv(netdev);
6169
6170 if (!e1000e_pm_ready(adapter))
6171 return 0;
6172
6173 if (adapter->idle_check) {
6174 adapter->idle_check = false;
6175 if (!e1000e_has_link(adapter))
6176 pm_schedule_suspend(dev, MSEC_PER_SEC);
6177 }
6178
6179 return -EBUSY;
6180}
23606cf5
RW		 6181
6182static int e1000_runtime_resume(struct device *dev)
6183{
6184 struct pci_dev *pdev = to_pci_dev(dev);
6185 struct net_device *netdev = pci_get_drvdata(pdev);
6186 struct e1000_adapter *adapter = netdev_priv(netdev);
6187
6188 if (!e1000e_pm_ready(adapter))
6189 return 0;
6190
6191 adapter->idle_check = !dev->power.runtime_auto;
6192 return __e1000_resume(pdev);
6193}
a0340162 6194#endif /* CONFIG_PM_RUNTIME */
aa338601 6195#endif /* CONFIG_PM */
bc7f75fa
AK		 6196
6197static void e1000_shutdown(struct pci_dev *pdev)
6198{
66148bab 6199 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6200}
6201
6202#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6203
8bb62869 6204static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6205{
6206 struct net_device *netdev = data;
6207 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6208
6209 if (adapter->msix_entries) {
90da0669
BA		 6210 int vector, msix_irq;
6211
147b2c8c
DD		 6212 vector = 0;
6213 msix_irq = adapter->msix_entries[vector].vector;
6214 disable_irq(msix_irq);
6215 e1000_intr_msix_rx(msix_irq, netdev);
6216 enable_irq(msix_irq);
6217
6218 vector++;
6219 msix_irq = adapter->msix_entries[vector].vector;
6220 disable_irq(msix_irq);
6221 e1000_intr_msix_tx(msix_irq, netdev);
6222 enable_irq(msix_irq);
6223
6224 vector++;
6225 msix_irq = adapter->msix_entries[vector].vector;
6226 disable_irq(msix_irq);
6227 e1000_msix_other(msix_irq, netdev);
6228 enable_irq(msix_irq);
6229 }
6230
6231 return IRQ_HANDLED;
6232}
6233
e921eb1a
BA		 6234/**
6235 * e1000_netpoll
6236 * @netdev: network interface device structure
6237 *
bc7f75fa
AK		 6238 * Polling 'interrupt' - used by things like netconsole to send skbs
6239 * without having to re-enable interrupts. It's not called while
6240 * the interrupt routine is executing.
6241 */
6242static void e1000_netpoll(struct net_device *netdev)
6243{
6244 struct e1000_adapter *adapter = netdev_priv(netdev);
6245
147b2c8c
DD		 6246 switch (adapter->int_mode) {
6247 case E1000E_INT_MODE_MSIX:
6248 e1000_intr_msix(adapter->pdev->irq, netdev);
6249 break;
6250 case E1000E_INT_MODE_MSI:
6251 disable_irq(adapter->pdev->irq);
6252 e1000_intr_msi(adapter->pdev->irq, netdev);
6253 enable_irq(adapter->pdev->irq);
6254 break;
6255 default: /* E1000E_INT_MODE_LEGACY */
6256 disable_irq(adapter->pdev->irq);
6257 e1000_intr(adapter->pdev->irq, netdev);
6258 enable_irq(adapter->pdev->irq);
6259 break;
6260 }
bc7f75fa
AK		 6261}
6262#endif
6263
6264/**
6265 * e1000_io_error_detected - called when PCI error is detected
6266 * @pdev: Pointer to PCI device
6267 * @state: The current pci connection state
6268 *
6269 * This function is called after a PCI bus error affecting
6270 * this device has been detected.
6271 */
6272static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6273 pci_channel_state_t state)
6274{
6275 struct net_device *netdev = pci_get_drvdata(pdev);
6276 struct e1000_adapter *adapter = netdev_priv(netdev);
6277
6278 netif_device_detach(netdev);
6279
c93b5a76
MM		 6280 if (state == pci_channel_io_perm_failure)
6281 return PCI_ERS_RESULT_DISCONNECT;
6282
bc7f75fa
AK		 6283 if (netif_running(netdev))
6284 e1000e_down(adapter);
6285 pci_disable_device(pdev);
6286
6287 /* Request a slot slot reset. */
6288 return PCI_ERS_RESULT_NEED_RESET;
6289}
6290
6291/**
6292 * e1000_io_slot_reset - called after the pci bus has been reset.
6293 * @pdev: Pointer to PCI device
6294 *
6295 * Restart the card from scratch, as if from a cold-boot. Implementation
6296 * resembles the first-half of the e1000_resume routine.
6297 */
6298static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6299{
6300 struct net_device *netdev = pci_get_drvdata(pdev);
6301 struct e1000_adapter *adapter = netdev_priv(netdev);
6302 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6303 u16 aspm_disable_flag = 0;
6e4f6f6b 6304 int err;
111b9dc5 6305 pci_ers_result_t result;
bc7f75fa 6306
78cd29d5
BA		 6307 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6308 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6309 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6310 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6311 if (aspm_disable_flag)
6312 e1000e_disable_aspm(pdev, aspm_disable_flag);
6313
f0f422e5 6314 err = pci_enable_device_mem(pdev);
6e4f6f6b 6315 if (err) {
bc7f75fa
AK		 6316 dev_err(&pdev->dev,
6317 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6318 result = PCI_ERS_RESULT_DISCONNECT;
6319 } else {
23606cf5 6320 pdev->state_saved = true;
111b9dc5 6321 pci_restore_state(pdev);
66148bab 6322 pci_set_master(pdev);
bc7f75fa 6323
111b9dc5
JB		 6324 pci_enable_wake(pdev, PCI_D3hot, 0);
6325 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6326
111b9dc5
JB		 6327 e1000e_reset(adapter);
6328 ew32(WUS, ~0);
6329 result = PCI_ERS_RESULT_RECOVERED;
6330 }
bc7f75fa 6331
111b9dc5
JB		 6332 pci_cleanup_aer_uncorrect_error_status(pdev);
6333
6334 return result;
bc7f75fa
AK		 6335}
6336
6337/**
6338 * e1000_io_resume - called when traffic can start flowing again.
6339 * @pdev: Pointer to PCI device
6340 *
6341 * This callback is called when the error recovery driver tells us that
6342 * its OK to resume normal operation. Implementation resembles the
6343 * second-half of the e1000_resume routine.
6344 */
6345static void e1000_io_resume(struct pci_dev *pdev)
6346{
6347 struct net_device *netdev = pci_get_drvdata(pdev);
6348 struct e1000_adapter *adapter = netdev_priv(netdev);
6349
cd791618 6350 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6351
6352 if (netif_running(netdev)) {
6353 if (e1000e_up(adapter)) {
6354 dev_err(&pdev->dev,
6355 "can't bring device back up after reset\n");
6356 return;
6357 }
6358 }
6359
6360 netif_device_attach(netdev);
6361
e921eb1a 6362 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6363 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6364 * under the control of the driver.
6365 */
c43bc57e 6366 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6367 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6368}
6369
6370static void e1000_print_device_info(struct e1000_adapter *adapter)
6371{
6372 struct e1000_hw *hw = &adapter->hw;
6373 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6374 u32 ret_val;
6375 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6376
6377 /* print bus type/speed/width info */
a5cc7642 6378 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6379 /* bus width */
6380 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6381 "Width x1"),
44defeb3 6382 /* MAC address */
7c510e4b 6383 netdev->dev_addr);
44defeb3
JK		 6384 e_info("Intel(R) PRO/%s Network Connection\n",
6385 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6386 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6387 E1000_PBANUM_LENGTH);
6388 if (ret_val)
f2315bf1 6389 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6390 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6391 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6392}
6393
10aa4c04
AK		 6394static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6395{
6396 struct e1000_hw *hw = &adapter->hw;
6397 int ret_val;
6398 u16 buf = 0;
6399
6400 if (hw->mac.type != e1000_82573)
6401 return;
6402
6403 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6404 le16_to_cpus(&buf);
6405 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6406 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6407 dev_warn(&adapter->pdev->dev,
6408 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6409 }
10aa4c04
AK		 6410}
6411
c8f44aff 6412static int e1000_set_features(struct net_device *netdev,
70495a50 6413 netdev_features_t features)
dc221294
BA		 6414{
6415 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6416 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6417
6418 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6419 adapter->flags |= FLAG_TSO_FORCE;
6420
f646968f 6421 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6422 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6423 NETIF_F_RXALL)))
dc221294
BA		 6424 return 0;
6425
0184039a
BG		 6426 if (changed & NETIF_F_RXFCS) {
6427 if (features & NETIF_F_RXFCS) {
6428 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6429 } else {
6430 /* We need to take it back to defaults, which might mean
6431 * stripping is still disabled at the adapter level.
6432 */
6433 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6434 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6435 else
6436 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6437 }
6438 }
6439
70495a50
BA		 6440 netdev->features = features;
6441
dc221294
BA		 6442 if (netif_running(netdev))
6443 e1000e_reinit_locked(adapter);
6444 else
6445 e1000e_reset(adapter);
6446
6447 return 0;
6448}
6449
651c2466
SH		 6450static const struct net_device_ops e1000e_netdev_ops = {
6451 .ndo_open = e1000_open,
6452 .ndo_stop = e1000_close,
00829823 6453 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6454 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6455 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6456 .ndo_set_mac_address = e1000_set_mac,
6457 .ndo_change_mtu = e1000_change_mtu,
6458 .ndo_do_ioctl = e1000_ioctl,
6459 .ndo_tx_timeout = e1000_tx_timeout,
6460 .ndo_validate_addr = eth_validate_addr,
6461
651c2466
SH		 6462 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6463 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6464#ifdef CONFIG_NET_POLL_CONTROLLER
6465 .ndo_poll_controller = e1000_netpoll,
6466#endif
dc221294 6467 .ndo_set_features = e1000_set_features,
651c2466
SH		 6468};
6469
bc7f75fa
AK		 6470/**
6471 * e1000_probe - Device Initialization Routine
6472 * @pdev: PCI device information struct
6473 * @ent: entry in e1000_pci_tbl
6474 *
6475 * Returns 0 on success, negative on failure
6476 *
6477 * e1000_probe initializes an adapter identified by a pci_dev structure.
6478 * The OS initialization, configuring of the adapter private structure,
6479 * and a hardware reset occur.
6480 **/
1dd06ae8 6481static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6482{
6483 struct net_device *netdev;
6484 struct e1000_adapter *adapter;
6485 struct e1000_hw *hw;
6486 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6487 resource_size_t mmio_start, mmio_len;
6488 resource_size_t flash_start, flash_len;
bc7f75fa 6489 static int cards_found;
78cd29d5 6490 u16 aspm_disable_flag = 0;
17e813ec 6491 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6492 u16 eeprom_data = 0;
6493 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6494
78cd29d5
BA		 6495 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6496 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6497 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6498 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6499 if (aspm_disable_flag)
6500 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6501
f0f422e5 6502 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6503 if (err)
6504 return err;
6505
6506 pci_using_dac = 0;
0be3f55f 6507 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6508 if (!err) {
0be3f55f 6509 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6510 if (!err)
6511 pci_using_dac = 1;
6512 } else {
0be3f55f 6513 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6514 if (err) {
0be3f55f
NN		 6515 err = dma_set_coherent_mask(&pdev->dev,
6516 DMA_BIT_MASK(32));
bc7f75fa 6517 if (err) {
f0ff4398
BA		 6518 dev_err(&pdev->dev,
6519 "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6520 goto err_dma;
6521 }
6522 }
6523 }
6524
17e813ec
BA		 6525 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6526 err = pci_request_selected_regions_exclusive(pdev, bars,
6527 e1000e_driver_name);
bc7f75fa
AK		 6528 if (err)
6529 goto err_pci_reg;
6530
68eac460 6531 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6532 pci_enable_pcie_error_reporting(pdev);
68eac460 6533
bc7f75fa 6534 pci_set_master(pdev);
438b365a
BA		 6535 /* PCI config space info */
6536 err = pci_save_state(pdev);
6537 if (err)
6538 goto err_alloc_etherdev;
bc7f75fa
AK		 6539
6540 err = -ENOMEM;
6541 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6542 if (!netdev)
6543 goto err_alloc_etherdev;
6544
bc7f75fa
AK		 6545 SET_NETDEV_DEV(netdev, &pdev->dev);
6546
f85e4dfa
TH		 6547 netdev->irq = pdev->irq;
6548
bc7f75fa
AK		 6549 pci_set_drvdata(pdev, netdev);
6550 adapter = netdev_priv(netdev);
6551 hw = &adapter->hw;
6552 adapter->netdev = netdev;
6553 adapter->pdev = pdev;
6554 adapter->ei = ei;
6555 adapter->pba = ei->pba;
6556 adapter->flags = ei->flags;
eb7c3adb 6557 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6558 adapter->hw.adapter = adapter;
6559 adapter->hw.mac.type = ei->mac;
2adc55c9 6560 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6561 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6562
6563 mmio_start = pci_resource_start(pdev, 0);
6564 mmio_len = pci_resource_len(pdev, 0);
6565
6566 err = -EIO;
6567 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6568 if (!adapter->hw.hw_addr)
6569 goto err_ioremap;
6570
6571 if ((adapter->flags & FLAG_HAS_FLASH) &&
6572 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6573 flash_start = pci_resource_start(pdev, 1);
6574 flash_len = pci_resource_len(pdev, 1);
6575 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6576 if (!adapter->hw.flash_address)
6577 goto err_flashmap;
6578 }
6579
d495bcb8
BA		 6580 /* Set default EEE advertisement */
6581 if (adapter->flags2 & FLAG2_HAS_EEE)
6582 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6583
bc7f75fa 6584 /* construct the net_device struct */
651c2466 6585 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6586 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6587 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6588 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6589 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6590
6591 netdev->mem_start = mmio_start;
6592 netdev->mem_end = mmio_start + mmio_len;
6593
6594 adapter->bd_number = cards_found++;
6595
4662e82b
BA		 6596 e1000e_check_options(adapter);
6597
bc7f75fa
AK		 6598 /* setup adapter struct */
6599 err = e1000_sw_init(adapter);
6600 if (err)
6601 goto err_sw_init;
6602
bc7f75fa
AK		 6603 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6604 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6605 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6606
69e3fd8c 6607 err = ei->get_variants(adapter);
bc7f75fa
AK		 6608 if (err)
6609 goto err_hw_init;
6610
4a770358
BA		 6611 if ((adapter->flags & FLAG_IS_ICH) &&
6612 (adapter->flags & FLAG_READ_ONLY_NVM))
6613 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6614
bc7f75fa
AK		 6615 hw->mac.ops.get_bus_info(&adapter->hw);
6616
318a94d6 6617 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6618
6619 /* Copper options */
318a94d6 6620 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6621 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6622 adapter->hw.phy.disable_polarity_correction = 0;
6623 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6624 }
6625
470a5420 6626 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6627 dev_info(&pdev->dev,
6628 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6629
dc221294
BA		 6630 /* Set initial default active device features */
6631 netdev->features = (NETIF_F_SG |
f646968f
PM		 6632 NETIF_F_HW_VLAN_CTAG_RX |
6633 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6634 NETIF_F_TSO |
6635 NETIF_F_TSO6 |
70495a50 6636 NETIF_F_RXHASH |
dc221294
BA		 6637 NETIF_F_RXCSUM |
6638 NETIF_F_HW_CSUM);
6639
6640 /* Set user-changeable features (subset of all device features) */
6641 netdev->hw_features = netdev->features;
0184039a 6642 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6643 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6644 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6645
6646 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6647 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6648
dc221294
BA		 6649 netdev->vlan_features |= (NETIF_F_SG |
6650 NETIF_F_TSO |
6651 NETIF_F_TSO6 |
6652 NETIF_F_HW_CSUM);
a5136e23 6653
ef9b965a
JB		 6654 netdev->priv_flags |= IFF_UNICAST_FLT;
6655
7b872a55 6656 if (pci_using_dac) {
bc7f75fa 6657 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6658 netdev->vlan_features |= NETIF_F_HIGHDMA;
6659 }
bc7f75fa 6660
bc7f75fa
AK		 6661 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6662 adapter->flags |= FLAG_MNG_PT_ENABLED;
6663
e921eb1a 6664 /* before reading the NVM, reset the controller to
ad68076e
BA		 6665 * put the device in a known good starting state
6666 */
bc7f75fa
AK		 6667 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6668
e921eb1a 6669 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6670 * attempt. Let's give it a few tries
6671 */
6672 for (i = 0;; i++) {
6673 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6674 break;
6675 if (i == 2) {
185095fb 6676 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6677 err = -EIO;
6678 goto err_eeprom;
6679 }
6680 }
6681
10aa4c04
AK		 6682 e1000_eeprom_checks(adapter);
6683
608f8a0d 6684 /* copy the MAC address */
bc7f75fa 6685 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6686 dev_err(&pdev->dev,
6687 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6688
6689 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6690
aaeb6cdf 6691 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6692 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6693 netdev->dev_addr);
bc7f75fa
AK		 6694 err = -EIO;
6695 goto err_eeprom;
6696 }
6697
6698 init_timer(&adapter->watchdog_timer);
c061b18d 6699 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6700 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6701
6702 init_timer(&adapter->phy_info_timer);
c061b18d 6703 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6704 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6705
6706 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6707 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6708 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6709 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6710 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6711
bc7f75fa
AK		 6712 /* Initialize link parameters. User can change them with ethtool */
6713 adapter->hw.mac.autoneg = 1;
3db1cd5c 6714 adapter->fc_autoneg = true;
5c48ef3e
BA		 6715 adapter->hw.fc.requested_mode = e1000_fc_default;
6716 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6717 adapter->hw.phy.autoneg_advertised = 0x2f;
6718
6719 /* ring size defaults */
d821a4c4
BA		 6720 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6721 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6722
e921eb1a 6723 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6724 * the EEPROM, enable the ACPI Magic Packet filter
6725 */
6726 if (adapter->flags & FLAG_APME_IN_WUC) {
6727 /* APME bit in EEPROM is mapped to WUC.APME */
6728 eeprom_data = er32(WUC);
6729 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6730 if ((hw->mac.type > e1000_ich10lan) &&
6731 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6732 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6733 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6734 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6735 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6736 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6737 1, &eeprom_data);
bc7f75fa 6738 else
3d3a1676
BA		 6739 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6740 1, &eeprom_data);
bc7f75fa
AK		 6741 }
6742
6743 /* fetch WoL from EEPROM */
6744 if (eeprom_data & eeprom_apme_mask)
6745 adapter->eeprom_wol |= E1000_WUFC_MAG;
6746
e921eb1a 6747 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6748 * where the eeprom may be wrong or the board simply won't support
6749 * wake on lan on a particular port
6750 */
6751 if (!(adapter->flags & FLAG_HAS_WOL))
6752 adapter->eeprom_wol = 0;
6753
6754 /* initialize the wol settings based on the eeprom settings */
6755 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6756
6757 /* make sure adapter isn't asleep if manageability is enabled */
6758 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6759 (hw->mac.ops.check_mng_mode(hw)))
6760 device_wakeup_enable(&pdev->dev);
bc7f75fa 6761
84527590
BA		 6762 /* save off EEPROM version number */
6763 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6764
bc7f75fa
AK		 6765 /* reset the hardware with the new settings */
6766 e1000e_reset(adapter);
6767
e921eb1a 6768 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6769 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6770 * under the control of the driver.
6771 */
c43bc57e 6772 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6773 e1000e_get_hw_control(adapter);
bc7f75fa 6774
f2315bf1 6775 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6776 err = register_netdev(netdev);
6777 if (err)
6778 goto err_register;
6779
9c563d20
JB		 6780 /* carrier off reporting is important to ethtool even BEFORE open */
6781 netif_carrier_off(netdev);
6782
d89777bf
BA		 6783 /* init PTP hardware clock */
6784 e1000e_ptp_init(adapter);
6785
bc7f75fa
AK		 6786 e1000_print_device_info(adapter);
6787
f3ec4f87
AS		 6788 if (pci_dev_run_wake(pdev))
6789 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6790
bc7f75fa
AK		 6791 return 0;
6792
6793err_register:
c43bc57e 6794 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6795 e1000e_release_hw_control(adapter);
bc7f75fa 6796err_eeprom:
470a5420 6797 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6798 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6799err_hw_init:
bc7f75fa
AK		 6800 kfree(adapter->tx_ring);
6801 kfree(adapter->rx_ring);
6802err_sw_init:
c43bc57e
JB		 6803 if (adapter->hw.flash_address)
6804 iounmap(adapter->hw.flash_address);
e82f54ba 6805 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6806err_flashmap:
bc7f75fa
AK		 6807 iounmap(adapter->hw.hw_addr);
6808err_ioremap:
6809 free_netdev(netdev);
6810err_alloc_etherdev:
f0f422e5 6811 pci_release_selected_regions(pdev,
f0ff4398 6812 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6813err_pci_reg:
6814err_dma:
6815 pci_disable_device(pdev);
6816 return err;
6817}
6818
6819/**
6820 * e1000_remove - Device Removal Routine
6821 * @pdev: PCI device information struct
6822 *
6823 * e1000_remove is called by the PCI subsystem to alert the driver
6824 * that it should release a PCI device. The could be caused by a
6825 * Hot-Plug event, or because the driver is going to be removed from
6826 * memory.
6827 **/
9f9a12f8 6828static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6829{
6830 struct net_device *netdev = pci_get_drvdata(pdev);
6831 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6832 bool down = test_bit(__E1000_DOWN, &adapter->state);
6833
d89777bf
BA		 6834 e1000e_ptp_remove(adapter);
6835
e921eb1a 6836 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6837 * from being rescheduled.
ad68076e 6838 */
23606cf5
RW		 6839 if (!down)
6840 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6841 del_timer_sync(&adapter->watchdog_timer);
6842 del_timer_sync(&adapter->phy_info_timer);
6843
41cec6f1
BA		 6844 cancel_work_sync(&adapter->reset_task);
6845 cancel_work_sync(&adapter->watchdog_task);
6846 cancel_work_sync(&adapter->downshift_task);
6847 cancel_work_sync(&adapter->update_phy_task);
6848 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6849
b67e1913
BA		 6850 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6851 cancel_work_sync(&adapter->tx_hwtstamp_work);
6852 if (adapter->tx_hwtstamp_skb) {
6853 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6854 adapter->tx_hwtstamp_skb = NULL;
6855 }
6856 }
6857
17f208de
BA		 6858 if (!(netdev->flags & IFF_UP))
6859 e1000_power_down_phy(adapter);
6860
23606cf5
RW		 6861 /* Don't lie to e1000_close() down the road. */
6862 if (!down)
6863 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6864 unregister_netdev(netdev);
6865
f3ec4f87
AS		 6866 if (pci_dev_run_wake(pdev))
6867 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6868
e921eb1a 6869 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6870 * would have already happened in close and is redundant.
6871 */
31dbe5b4 6872 e1000e_release_hw_control(adapter);
bc7f75fa 6873
4662e82b 6874 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6875 kfree(adapter->tx_ring);
6876 kfree(adapter->rx_ring);
6877
6878 iounmap(adapter->hw.hw_addr);
6879 if (adapter->hw.flash_address)
6880 iounmap(adapter->hw.flash_address);
f0f422e5 6881 pci_release_selected_regions(pdev,
f0ff4398 6882 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6883
6884 free_netdev(netdev);
6885
111b9dc5 6886 /* AER disable */
19d5afd4 6887 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6888
bc7f75fa
AK		 6889 pci_disable_device(pdev);
6890}
6891
6892/* PCI Error Recovery (ERS) */
3646f0e5 6893static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6894 .error_detected = e1000_io_error_detected,
6895 .slot_reset = e1000_io_slot_reset,
6896 .resume = e1000_io_resume,
6897};
6898
a3aa1884 6899static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 6903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
6904 board_82571 },
bc7f75fa
AK		 6905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6910
bc7f75fa
AK		 6911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6915
bc7f75fa
AK		 6916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6919
4662e82b 6920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6923
bc7f75fa
AK		 6924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6925 board_80003es2lan },
6926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6927 board_80003es2lan },
6928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6929 board_80003es2lan },
6930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6931 board_80003es2lan },
ad68076e 6932
bc7f75fa
AK		 6933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6935 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6936 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6937 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6939 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6940 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6941
bc7f75fa
AK		 6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6943 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6944 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6945 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6947 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6948 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6949 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6950 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6951
6952 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6954 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6955
f4187b56
BA		 6956 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6957 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6959
a4f58f54
BA		 6960 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6961 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6962 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6963 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6964
d3738bb8
BA		 6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6966 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6967
2fbe4526
BA		 6968 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6969 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6971 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6972
f36bb6ca 6973 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6974};
6975MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6976
aa338601 6977#ifdef CONFIG_PM
23606cf5 6978static const struct dev_pm_ops e1000_pm_ops = {
a0340162 6979 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
17e813ec
BA		 6980 SET_RUNTIME_PM_OPS(e1000_runtime_suspend, e1000_runtime_resume,
6981 e1000_idle)
23606cf5 6982};
e50208a0 6983#endif
23606cf5 6984
bc7f75fa
AK		 6985/* PCI Device API Driver */
6986static struct pci_driver e1000_driver = {
6987 .name = e1000e_driver_name,
6988 .id_table = e1000_pci_tbl,
6989 .probe = e1000_probe,
9f9a12f8 6990 .remove = e1000_remove,
aa338601 6991#ifdef CONFIG_PM
f36bb6ca
BA		 6992 .driver = {
6993 .pm = &e1000_pm_ops,
6994 },
bc7f75fa
AK		 6995#endif
6996 .shutdown = e1000_shutdown,
6997 .err_handler = &e1000_err_handler
6998};
6999
7000/**
7001 * e1000_init_module - Driver Registration Routine
7002 *
7003 * e1000_init_module is the first routine called when the driver is
7004 * loaded. All it does is register with the PCI subsystem.
7005 **/
7006static int __init e1000_init_module(void)
7007{
7008 int ret;
8544b9f7
BA		 7009 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7010 e1000e_driver_version);
bf67044b 7011 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
bc7f75fa 7012 ret = pci_register_driver(&e1000_driver);
53ec5498 7013
bc7f75fa
AK		 7014 return ret;
7015}
7016module_init(e1000_init_module);
7017
7018/**
7019 * e1000_exit_module - Driver Exit Cleanup Routine
7020 *
7021 * e1000_exit_module is called just before the driver is removed
7022 * from memory.
7023 **/
7024static void __exit e1000_exit_module(void)
7025{
7026 pci_unregister_driver(&e1000_driver);
7027}
7028module_exit(e1000_exit_module);
7029
7030
7031MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7032MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7033MODULE_LICENSE("GPL");
7034MODULE_VERSION(DRV_VERSION);
7035
06c24b91 7036/* netdev.c */
Linux kernel - Deliverables
This page took 1.524674 seconds and 5 git commands to generate.