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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
f5e261e6 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
bc7f75fa AK |
29 | #include "e1000.h" |
30 | ||
31 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
32 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
33 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); | |
34 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); | |
97ac8cae BA |
35 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); |
36 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
2b6b168d | 37 | u16 *data, bool read, bool page_set); |
a4f58f54 BA |
38 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
39 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
40 | u16 *data, bool read); | |
bc7f75fa AK |
41 | |
42 | /* Cable length tables */ | |
6480641e BA |
43 | static const u16 e1000_m88_cable_length_table[] = { |
44 | 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
eb656d45 BA |
45 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
46 | ARRAY_SIZE(e1000_m88_cable_length_table) | |
bc7f75fa | 47 | |
6480641e BA |
48 | static const u16 e1000_igp_2_cable_length_table[] = { |
49 | 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, | |
50 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, | |
51 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, | |
52 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, | |
53 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, | |
54 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, | |
55 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, | |
56 | 124}; | |
bc7f75fa | 57 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
c00acf46 | 58 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
bc7f75fa | 59 | |
a4f58f54 BA |
60 | #define BM_PHY_REG_PAGE(offset) \ |
61 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) | |
62 | #define BM_PHY_REG_NUM(offset) \ | |
63 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ | |
64 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ | |
65 | ~MAX_PHY_REG_ADDRESS))) | |
66 | ||
67 | #define HV_INTC_FC_PAGE_START 768 | |
68 | #define I82578_ADDR_REG 29 | |
69 | #define I82577_ADDR_REG 16 | |
70 | #define I82577_CFG_REG 22 | |
71 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) | |
72 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | |
73 | #define I82577_CTRL_REG 23 | |
a4f58f54 BA |
74 | |
75 | /* 82577 specific PHY registers */ | |
76 | #define I82577_PHY_CTRL_2 18 | |
77 | #define I82577_PHY_STATUS_2 26 | |
78 | #define I82577_PHY_DIAG_STATUS 31 | |
79 | ||
80 | /* I82577 PHY Status 2 */ | |
81 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 | |
82 | #define I82577_PHY_STATUS2_MDIX 0x0800 | |
83 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 | |
84 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 | |
85 | ||
86 | /* I82577 PHY Control 2 */ | |
87 | #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 | |
88 | #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 | |
89 | ||
90 | /* I82577 PHY Diagnostics Status */ | |
91 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC | |
92 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 | |
93 | ||
94 | /* BM PHY Copper Specific Control 1 */ | |
95 | #define BM_CS_CTRL1 16 | |
96 | ||
a4f58f54 BA |
97 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) |
98 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 | |
99 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 | |
100 | ||
bc7f75fa AK |
101 | /** |
102 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked | |
103 | * @hw: pointer to the HW structure | |
104 | * | |
105 | * Read the PHY management control register and check whether a PHY reset | |
106 | * is blocked. If a reset is not blocked return 0, otherwise | |
107 | * return E1000_BLK_PHY_RESET (12). | |
108 | **/ | |
109 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) | |
110 | { | |
111 | u32 manc; | |
112 | ||
113 | manc = er32(MANC); | |
114 | ||
115 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
116 | E1000_BLK_PHY_RESET : 0; | |
117 | } | |
118 | ||
119 | /** | |
120 | * e1000e_get_phy_id - Retrieve the PHY ID and revision | |
121 | * @hw: pointer to the HW structure | |
122 | * | |
123 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
124 | * revision in the hardware structure. | |
125 | **/ | |
126 | s32 e1000e_get_phy_id(struct e1000_hw *hw) | |
127 | { | |
128 | struct e1000_phy_info *phy = &hw->phy; | |
a4f58f54 | 129 | s32 ret_val = 0; |
bc7f75fa | 130 | u16 phy_id; |
a4f58f54 | 131 | u16 retry_count = 0; |
bc7f75fa | 132 | |
668018d7 | 133 | if (!phy->ops.read_reg) |
5015e53a | 134 | return 0; |
bc7f75fa | 135 | |
a4f58f54 BA |
136 | while (retry_count < 2) { |
137 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); | |
138 | if (ret_val) | |
5015e53a | 139 | return ret_val; |
bc7f75fa | 140 | |
a4f58f54 BA |
141 | phy->id = (u32)(phy_id << 16); |
142 | udelay(20); | |
143 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
144 | if (ret_val) | |
5015e53a | 145 | return ret_val; |
bc7f75fa | 146 | |
a4f58f54 BA |
147 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
148 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
149 | ||
150 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) | |
5015e53a | 151 | return 0; |
a4f58f54 | 152 | |
a4f58f54 BA |
153 | retry_count++; |
154 | } | |
5015e53a BA |
155 | |
156 | return 0; | |
bc7f75fa AK |
157 | } |
158 | ||
159 | /** | |
160 | * e1000e_phy_reset_dsp - Reset PHY DSP | |
161 | * @hw: pointer to the HW structure | |
162 | * | |
163 | * Reset the digital signal processor. | |
164 | **/ | |
165 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |
166 | { | |
167 | s32 ret_val; | |
168 | ||
169 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); | |
170 | if (ret_val) | |
171 | return ret_val; | |
172 | ||
173 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); | |
174 | } | |
175 | ||
176 | /** | |
2d9498f3 | 177 | * e1000e_read_phy_reg_mdic - Read MDI control register |
bc7f75fa AK |
178 | * @hw: pointer to the HW structure |
179 | * @offset: register offset to be read | |
180 | * @data: pointer to the read data | |
181 | * | |
489815ce | 182 | * Reads the MDI control register in the PHY at offset and stores the |
bc7f75fa AK |
183 | * information read to data. |
184 | **/ | |
2d9498f3 | 185 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
bc7f75fa AK |
186 | { |
187 | struct e1000_phy_info *phy = &hw->phy; | |
188 | u32 i, mdic = 0; | |
189 | ||
190 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 191 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
192 | return -E1000_ERR_PARAM; |
193 | } | |
194 | ||
ad68076e BA |
195 | /* |
196 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
197 | * Control register. The MAC will take care of interfacing with the |
198 | * PHY to retrieve the desired data. | |
199 | */ | |
200 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
201 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
202 | (E1000_MDIC_OP_READ)); | |
203 | ||
204 | ew32(MDIC, mdic); | |
205 | ||
ad68076e BA |
206 | /* |
207 | * Poll the ready bit to see if the MDI read completed | |
208 | * Increasing the time out as testing showed failures with | |
209 | * the lower time out | |
210 | */ | |
2d9498f3 | 211 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
bc7f75fa AK |
212 | udelay(50); |
213 | mdic = er32(MDIC); | |
214 | if (mdic & E1000_MDIC_READY) | |
215 | break; | |
216 | } | |
217 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 218 | e_dbg("MDI Read did not complete\n"); |
bc7f75fa AK |
219 | return -E1000_ERR_PHY; |
220 | } | |
221 | if (mdic & E1000_MDIC_ERROR) { | |
3bb99fe2 | 222 | e_dbg("MDI Error\n"); |
bc7f75fa AK |
223 | return -E1000_ERR_PHY; |
224 | } | |
225 | *data = (u16) mdic; | |
226 | ||
664dc878 BA |
227 | /* |
228 | * Allow some time after each MDIC transaction to avoid | |
229 | * reading duplicate data in the next MDIC transaction. | |
230 | */ | |
231 | if (hw->mac.type == e1000_pch2lan) | |
232 | udelay(100); | |
233 | ||
bc7f75fa AK |
234 | return 0; |
235 | } | |
236 | ||
237 | /** | |
2d9498f3 | 238 | * e1000e_write_phy_reg_mdic - Write MDI control register |
bc7f75fa AK |
239 | * @hw: pointer to the HW structure |
240 | * @offset: register offset to write to | |
241 | * @data: data to write to register at offset | |
242 | * | |
243 | * Writes data to MDI control register in the PHY at offset. | |
244 | **/ | |
2d9498f3 | 245 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
bc7f75fa AK |
246 | { |
247 | struct e1000_phy_info *phy = &hw->phy; | |
248 | u32 i, mdic = 0; | |
249 | ||
250 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 251 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
252 | return -E1000_ERR_PARAM; |
253 | } | |
254 | ||
ad68076e BA |
255 | /* |
256 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
257 | * Control register. The MAC will take care of interfacing with the |
258 | * PHY to retrieve the desired data. | |
259 | */ | |
260 | mdic = (((u32)data) | | |
261 | (offset << E1000_MDIC_REG_SHIFT) | | |
262 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
263 | (E1000_MDIC_OP_WRITE)); | |
264 | ||
265 | ew32(MDIC, mdic); | |
266 | ||
2d9498f3 DG |
267 | /* |
268 | * Poll the ready bit to see if the MDI read completed | |
269 | * Increasing the time out as testing showed failures with | |
270 | * the lower time out | |
271 | */ | |
272 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
273 | udelay(50); | |
bc7f75fa AK |
274 | mdic = er32(MDIC); |
275 | if (mdic & E1000_MDIC_READY) | |
276 | break; | |
277 | } | |
278 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 279 | e_dbg("MDI Write did not complete\n"); |
bc7f75fa AK |
280 | return -E1000_ERR_PHY; |
281 | } | |
2d9498f3 | 282 | if (mdic & E1000_MDIC_ERROR) { |
3bb99fe2 | 283 | e_dbg("MDI Error\n"); |
2d9498f3 DG |
284 | return -E1000_ERR_PHY; |
285 | } | |
bc7f75fa | 286 | |
664dc878 BA |
287 | /* |
288 | * Allow some time after each MDIC transaction to avoid | |
289 | * reading duplicate data in the next MDIC transaction. | |
290 | */ | |
291 | if (hw->mac.type == e1000_pch2lan) | |
292 | udelay(100); | |
293 | ||
bc7f75fa AK |
294 | return 0; |
295 | } | |
296 | ||
297 | /** | |
298 | * e1000e_read_phy_reg_m88 - Read m88 PHY register | |
299 | * @hw: pointer to the HW structure | |
300 | * @offset: register offset to be read | |
301 | * @data: pointer to the read data | |
302 | * | |
303 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
304 | * and storing the retrieved information in data. Release any acquired | |
305 | * semaphores before exiting. | |
306 | **/ | |
307 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) | |
308 | { | |
309 | s32 ret_val; | |
310 | ||
94d8186a | 311 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
312 | if (ret_val) |
313 | return ret_val; | |
314 | ||
2d9498f3 DG |
315 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
316 | data); | |
bc7f75fa | 317 | |
94d8186a | 318 | hw->phy.ops.release(hw); |
bc7f75fa AK |
319 | |
320 | return ret_val; | |
321 | } | |
322 | ||
323 | /** | |
324 | * e1000e_write_phy_reg_m88 - Write m88 PHY register | |
325 | * @hw: pointer to the HW structure | |
326 | * @offset: register offset to write to | |
327 | * @data: data to write at register offset | |
328 | * | |
329 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
330 | * at the offset. Release any acquired semaphores before exiting. | |
331 | **/ | |
332 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |
333 | { | |
334 | s32 ret_val; | |
335 | ||
94d8186a | 336 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
337 | if (ret_val) |
338 | return ret_val; | |
339 | ||
2d9498f3 DG |
340 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
341 | data); | |
bc7f75fa | 342 | |
94d8186a | 343 | hw->phy.ops.release(hw); |
bc7f75fa AK |
344 | |
345 | return ret_val; | |
346 | } | |
347 | ||
2b6b168d BA |
348 | /** |
349 | * e1000_set_page_igp - Set page as on IGP-like PHY(s) | |
350 | * @hw: pointer to the HW structure | |
351 | * @page: page to set (shifted left when necessary) | |
352 | * | |
353 | * Sets PHY page required for PHY register access. Assumes semaphore is | |
354 | * already acquired. Note, this function sets phy.addr to 1 so the caller | |
355 | * must set it appropriately (if necessary) after this function returns. | |
356 | **/ | |
357 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) | |
358 | { | |
359 | e_dbg("Setting page 0x%x\n", page); | |
360 | ||
361 | hw->phy.addr = 1; | |
362 | ||
363 | return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); | |
364 | } | |
365 | ||
bc7f75fa | 366 | /** |
5ccdcecb | 367 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
bc7f75fa AK |
368 | * @hw: pointer to the HW structure |
369 | * @offset: register offset to be read | |
370 | * @data: pointer to the read data | |
5ccdcecb | 371 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
372 | * |
373 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 374 | * and stores the retrieved information in data. Release any acquired |
bc7f75fa AK |
375 | * semaphores before exiting. |
376 | **/ | |
5ccdcecb BA |
377 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
378 | bool locked) | |
bc7f75fa | 379 | { |
5ccdcecb | 380 | s32 ret_val = 0; |
bc7f75fa | 381 | |
5ccdcecb | 382 | if (!locked) { |
668018d7 | 383 | if (!hw->phy.ops.acquire) |
5015e53a | 384 | return 0; |
5ccdcecb | 385 | |
94d8186a | 386 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 387 | if (ret_val) |
5015e53a | 388 | return ret_val; |
5ccdcecb | 389 | } |
bc7f75fa | 390 | |
5015e53a | 391 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
2d9498f3 DG |
392 | ret_val = e1000e_write_phy_reg_mdic(hw, |
393 | IGP01E1000_PHY_PAGE_SELECT, | |
394 | (u16)offset); | |
5015e53a BA |
395 | if (!ret_val) |
396 | ret_val = e1000e_read_phy_reg_mdic(hw, | |
397 | MAX_PHY_REG_ADDRESS & offset, | |
398 | data); | |
5ccdcecb | 399 | if (!locked) |
94d8186a | 400 | hw->phy.ops.release(hw); |
5015e53a | 401 | |
bc7f75fa AK |
402 | return ret_val; |
403 | } | |
404 | ||
5ccdcecb BA |
405 | /** |
406 | * e1000e_read_phy_reg_igp - Read igp PHY register | |
407 | * @hw: pointer to the HW structure | |
408 | * @offset: register offset to be read | |
409 | * @data: pointer to the read data | |
410 | * | |
411 | * Acquires semaphore then reads the PHY register at offset and stores the | |
412 | * retrieved information in data. | |
413 | * Release the acquired semaphore before exiting. | |
414 | **/ | |
415 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
416 | { | |
417 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); | |
418 | } | |
419 | ||
420 | /** | |
421 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register | |
422 | * @hw: pointer to the HW structure | |
423 | * @offset: register offset to be read | |
424 | * @data: pointer to the read data | |
425 | * | |
426 | * Reads the PHY register at offset and stores the retrieved information | |
427 | * in data. Assumes semaphore already acquired. | |
428 | **/ | |
429 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
430 | { | |
431 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); | |
432 | } | |
433 | ||
bc7f75fa AK |
434 | /** |
435 | * e1000e_write_phy_reg_igp - Write igp PHY register | |
436 | * @hw: pointer to the HW structure | |
437 | * @offset: register offset to write to | |
438 | * @data: data to write at register offset | |
5ccdcecb | 439 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
440 | * |
441 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
442 | * at the offset. Release any acquired semaphores before exiting. | |
443 | **/ | |
5ccdcecb BA |
444 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
445 | bool locked) | |
bc7f75fa | 446 | { |
5ccdcecb | 447 | s32 ret_val = 0; |
bc7f75fa | 448 | |
5ccdcecb | 449 | if (!locked) { |
668018d7 | 450 | if (!hw->phy.ops.acquire) |
5015e53a | 451 | return 0; |
5ccdcecb | 452 | |
94d8186a | 453 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 454 | if (ret_val) |
5015e53a | 455 | return ret_val; |
5ccdcecb | 456 | } |
bc7f75fa | 457 | |
5015e53a | 458 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
2d9498f3 DG |
459 | ret_val = e1000e_write_phy_reg_mdic(hw, |
460 | IGP01E1000_PHY_PAGE_SELECT, | |
461 | (u16)offset); | |
5015e53a BA |
462 | if (!ret_val) |
463 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & | |
464 | offset, | |
465 | data); | |
5ccdcecb | 466 | if (!locked) |
94d8186a | 467 | hw->phy.ops.release(hw); |
bc7f75fa AK |
468 | |
469 | return ret_val; | |
470 | } | |
471 | ||
472 | /** | |
5ccdcecb BA |
473 | * e1000e_write_phy_reg_igp - Write igp PHY register |
474 | * @hw: pointer to the HW structure | |
475 | * @offset: register offset to write to | |
476 | * @data: data to write at register offset | |
477 | * | |
478 | * Acquires semaphore then writes the data to PHY register | |
479 | * at the offset. Release any acquired semaphores before exiting. | |
480 | **/ | |
481 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
482 | { | |
483 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); | |
484 | } | |
485 | ||
486 | /** | |
487 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register | |
488 | * @hw: pointer to the HW structure | |
489 | * @offset: register offset to write to | |
490 | * @data: data to write at register offset | |
491 | * | |
492 | * Writes the data to PHY register at the offset. | |
493 | * Assumes semaphore already acquired. | |
494 | **/ | |
495 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
496 | { | |
497 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); | |
498 | } | |
499 | ||
500 | /** | |
501 | * __e1000_read_kmrn_reg - Read kumeran register | |
bc7f75fa AK |
502 | * @hw: pointer to the HW structure |
503 | * @offset: register offset to be read | |
504 | * @data: pointer to the read data | |
5ccdcecb | 505 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
506 | * |
507 | * Acquires semaphore, if necessary. Then reads the PHY register at offset | |
508 | * using the kumeran interface. The information retrieved is stored in data. | |
509 | * Release any acquired semaphores before exiting. | |
510 | **/ | |
5ccdcecb BA |
511 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
512 | bool locked) | |
bc7f75fa AK |
513 | { |
514 | u32 kmrnctrlsta; | |
bc7f75fa | 515 | |
5ccdcecb | 516 | if (!locked) { |
5015e53a BA |
517 | s32 ret_val = 0; |
518 | ||
668018d7 | 519 | if (!hw->phy.ops.acquire) |
5015e53a | 520 | return 0; |
5ccdcecb | 521 | |
94d8186a | 522 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 523 | if (ret_val) |
5015e53a | 524 | return ret_val; |
5ccdcecb | 525 | } |
bc7f75fa AK |
526 | |
527 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
528 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
529 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
945a5151 | 530 | e1e_flush(); |
bc7f75fa AK |
531 | |
532 | udelay(2); | |
533 | ||
534 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
535 | *data = (u16)kmrnctrlsta; | |
536 | ||
5ccdcecb | 537 | if (!locked) |
94d8186a | 538 | hw->phy.ops.release(hw); |
bc7f75fa | 539 | |
5015e53a | 540 | return 0; |
bc7f75fa AK |
541 | } |
542 | ||
543 | /** | |
5ccdcecb BA |
544 | * e1000e_read_kmrn_reg - Read kumeran register |
545 | * @hw: pointer to the HW structure | |
546 | * @offset: register offset to be read | |
547 | * @data: pointer to the read data | |
548 | * | |
549 | * Acquires semaphore then reads the PHY register at offset using the | |
550 | * kumeran interface. The information retrieved is stored in data. | |
551 | * Release the acquired semaphore before exiting. | |
552 | **/ | |
553 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
554 | { | |
555 | return __e1000_read_kmrn_reg(hw, offset, data, false); | |
556 | } | |
557 | ||
558 | /** | |
1d5846b9 | 559 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
5ccdcecb BA |
560 | * @hw: pointer to the HW structure |
561 | * @offset: register offset to be read | |
562 | * @data: pointer to the read data | |
563 | * | |
564 | * Reads the PHY register at offset using the kumeran interface. The | |
565 | * information retrieved is stored in data. | |
566 | * Assumes semaphore already acquired. | |
567 | **/ | |
1d5846b9 | 568 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
5ccdcecb BA |
569 | { |
570 | return __e1000_read_kmrn_reg(hw, offset, data, true); | |
571 | } | |
572 | ||
573 | /** | |
574 | * __e1000_write_kmrn_reg - Write kumeran register | |
bc7f75fa AK |
575 | * @hw: pointer to the HW structure |
576 | * @offset: register offset to write to | |
577 | * @data: data to write at register offset | |
5ccdcecb | 578 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
579 | * |
580 | * Acquires semaphore, if necessary. Then write the data to PHY register | |
581 | * at the offset using the kumeran interface. Release any acquired semaphores | |
582 | * before exiting. | |
583 | **/ | |
5ccdcecb BA |
584 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
585 | bool locked) | |
bc7f75fa AK |
586 | { |
587 | u32 kmrnctrlsta; | |
bc7f75fa | 588 | |
5ccdcecb | 589 | if (!locked) { |
5015e53a BA |
590 | s32 ret_val = 0; |
591 | ||
668018d7 | 592 | if (!hw->phy.ops.acquire) |
5015e53a | 593 | return 0; |
5ccdcecb | 594 | |
94d8186a | 595 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 596 | if (ret_val) |
5015e53a | 597 | return ret_val; |
5ccdcecb | 598 | } |
bc7f75fa AK |
599 | |
600 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
601 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
602 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
945a5151 | 603 | e1e_flush(); |
bc7f75fa AK |
604 | |
605 | udelay(2); | |
bc7f75fa | 606 | |
5ccdcecb | 607 | if (!locked) |
94d8186a | 608 | hw->phy.ops.release(hw); |
5ccdcecb | 609 | |
5015e53a | 610 | return 0; |
bc7f75fa AK |
611 | } |
612 | ||
5ccdcecb BA |
613 | /** |
614 | * e1000e_write_kmrn_reg - Write kumeran register | |
615 | * @hw: pointer to the HW structure | |
616 | * @offset: register offset to write to | |
617 | * @data: data to write at register offset | |
618 | * | |
619 | * Acquires semaphore then writes the data to the PHY register at the offset | |
620 | * using the kumeran interface. Release the acquired semaphore before exiting. | |
621 | **/ | |
622 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
623 | { | |
624 | return __e1000_write_kmrn_reg(hw, offset, data, false); | |
625 | } | |
626 | ||
627 | /** | |
1d5846b9 | 628 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
5ccdcecb BA |
629 | * @hw: pointer to the HW structure |
630 | * @offset: register offset to write to | |
631 | * @data: data to write at register offset | |
632 | * | |
633 | * Write the data to PHY register at the offset using the kumeran interface. | |
634 | * Assumes semaphore already acquired. | |
635 | **/ | |
1d5846b9 | 636 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
5ccdcecb BA |
637 | { |
638 | return __e1000_write_kmrn_reg(hw, offset, data, true); | |
639 | } | |
640 | ||
a4f58f54 BA |
641 | /** |
642 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link | |
643 | * @hw: pointer to the HW structure | |
644 | * | |
645 | * Sets up Carrier-sense on Transmit and downshift values. | |
646 | **/ | |
647 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |
648 | { | |
a4f58f54 BA |
649 | s32 ret_val; |
650 | u16 phy_data; | |
651 | ||
af667a29 | 652 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
482fed85 | 653 | ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
a4f58f54 | 654 | if (ret_val) |
5015e53a | 655 | return ret_val; |
a4f58f54 BA |
656 | |
657 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; | |
658 | ||
659 | /* Enable downshift */ | |
660 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | |
661 | ||
5015e53a | 662 | return e1e_wphy(hw, I82577_CFG_REG, phy_data); |
a4f58f54 BA |
663 | } |
664 | ||
bc7f75fa AK |
665 | /** |
666 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link | |
667 | * @hw: pointer to the HW structure | |
668 | * | |
669 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
670 | * and downshift values are set also. | |
671 | **/ | |
672 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |
673 | { | |
674 | struct e1000_phy_info *phy = &hw->phy; | |
675 | s32 ret_val; | |
676 | u16 phy_data; | |
677 | ||
ad68076e | 678 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
bc7f75fa AK |
679 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
680 | if (ret_val) | |
681 | return ret_val; | |
682 | ||
a4f58f54 BA |
683 | /* For BM PHY this bit is downshift enable */ |
684 | if (phy->type != e1000_phy_bm) | |
2d9498f3 | 685 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
bc7f75fa | 686 | |
ad68076e BA |
687 | /* |
688 | * Options: | |
bc7f75fa AK |
689 | * MDI/MDI-X = 0 (default) |
690 | * 0 - Auto for all speeds | |
691 | * 1 - MDI mode | |
692 | * 2 - MDI-X mode | |
693 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
694 | */ | |
695 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
696 | ||
697 | switch (phy->mdix) { | |
698 | case 1: | |
699 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
700 | break; | |
701 | case 2: | |
702 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
703 | break; | |
704 | case 3: | |
705 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
706 | break; | |
707 | case 0: | |
708 | default: | |
709 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
710 | break; | |
711 | } | |
712 | ||
ad68076e BA |
713 | /* |
714 | * Options: | |
bc7f75fa AK |
715 | * disable_polarity_correction = 0 (default) |
716 | * Automatic Correction for Reversed Cable Polarity | |
717 | * 0 - Disabled | |
718 | * 1 - Enabled | |
719 | */ | |
720 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
04499ec4 | 721 | if (phy->disable_polarity_correction) |
bc7f75fa AK |
722 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
723 | ||
97ac8cae | 724 | /* Enable downshift on BM (disabled by default) */ |
885fe7be MV |
725 | if (phy->type == e1000_phy_bm) { |
726 | /* For 82574/82583, first disable then enable downshift */ | |
727 | if (phy->id == BME1000_E_PHY_ID_R2) { | |
728 | phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; | |
729 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, | |
730 | phy_data); | |
731 | if (ret_val) | |
732 | return ret_val; | |
733 | /* Commit the changes. */ | |
734 | ret_val = e1000e_commit_phy(hw); | |
735 | if (ret_val) { | |
736 | e_dbg("Error committing the PHY changes\n"); | |
737 | return ret_val; | |
738 | } | |
739 | } | |
740 | ||
97ac8cae | 741 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
885fe7be | 742 | } |
97ac8cae | 743 | |
bc7f75fa AK |
744 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
745 | if (ret_val) | |
746 | return ret_val; | |
747 | ||
4662e82b BA |
748 | if ((phy->type == e1000_phy_m88) && |
749 | (phy->revision < E1000_REVISION_4) && | |
750 | (phy->id != BME1000_E_PHY_ID_R2)) { | |
ad68076e BA |
751 | /* |
752 | * Force TX_CLK in the Extended PHY Specific Control Register | |
bc7f75fa AK |
753 | * to 25MHz clock. |
754 | */ | |
755 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
756 | if (ret_val) | |
757 | return ret_val; | |
758 | ||
759 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
760 | ||
761 | if ((phy->revision == 2) && | |
762 | (phy->id == M88E1111_I_PHY_ID)) { | |
763 | /* 82573L PHY - set the downshift counter to 5x. */ | |
764 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
765 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
766 | } else { | |
767 | /* Configure Master and Slave downshift values */ | |
768 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
769 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
770 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
771 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
772 | } | |
773 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
774 | if (ret_val) | |
775 | return ret_val; | |
776 | } | |
777 | ||
4662e82b BA |
778 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
779 | /* Set PHY page 0, register 29 to 0x0003 */ | |
780 | ret_val = e1e_wphy(hw, 29, 0x0003); | |
781 | if (ret_val) | |
782 | return ret_val; | |
783 | ||
784 | /* Set PHY page 0, register 30 to 0x0000 */ | |
785 | ret_val = e1e_wphy(hw, 30, 0x0000); | |
786 | if (ret_val) | |
787 | return ret_val; | |
788 | } | |
789 | ||
bc7f75fa AK |
790 | /* Commit the changes. */ |
791 | ret_val = e1000e_commit_phy(hw); | |
a4f58f54 | 792 | if (ret_val) { |
3bb99fe2 | 793 | e_dbg("Error committing the PHY changes\n"); |
a4f58f54 BA |
794 | return ret_val; |
795 | } | |
bc7f75fa | 796 | |
a4f58f54 | 797 | if (phy->type == e1000_phy_82578) { |
482fed85 | 798 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
a4f58f54 BA |
799 | if (ret_val) |
800 | return ret_val; | |
801 | ||
802 | /* 82578 PHY - set the downshift count to 1x. */ | |
803 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; | |
804 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
482fed85 | 805 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
a4f58f54 BA |
806 | if (ret_val) |
807 | return ret_val; | |
808 | } | |
809 | ||
810 | return 0; | |
bc7f75fa AK |
811 | } |
812 | ||
813 | /** | |
814 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link | |
815 | * @hw: pointer to the HW structure | |
816 | * | |
817 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
818 | * igp PHY's. | |
819 | **/ | |
820 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) | |
821 | { | |
822 | struct e1000_phy_info *phy = &hw->phy; | |
823 | s32 ret_val; | |
824 | u16 data; | |
825 | ||
826 | ret_val = e1000_phy_hw_reset(hw); | |
827 | if (ret_val) { | |
3bb99fe2 | 828 | e_dbg("Error resetting the PHY.\n"); |
bc7f75fa AK |
829 | return ret_val; |
830 | } | |
831 | ||
2d9498f3 DG |
832 | /* |
833 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
834 | * timeout issues when LFS is enabled. | |
835 | */ | |
836 | msleep(100); | |
bc7f75fa AK |
837 | |
838 | /* disable lplu d0 during driver init */ | |
564ea9bb | 839 | ret_val = e1000_set_d0_lplu_state(hw, false); |
bc7f75fa | 840 | if (ret_val) { |
3bb99fe2 | 841 | e_dbg("Error Disabling LPLU D0\n"); |
bc7f75fa AK |
842 | return ret_val; |
843 | } | |
844 | /* Configure mdi-mdix settings */ | |
845 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); | |
846 | if (ret_val) | |
847 | return ret_val; | |
848 | ||
849 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
850 | ||
851 | switch (phy->mdix) { | |
852 | case 1: | |
853 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
854 | break; | |
855 | case 2: | |
856 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
857 | break; | |
858 | case 0: | |
859 | default: | |
860 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
861 | break; | |
862 | } | |
863 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); | |
864 | if (ret_val) | |
865 | return ret_val; | |
866 | ||
867 | /* set auto-master slave resolution settings */ | |
868 | if (hw->mac.autoneg) { | |
ad68076e BA |
869 | /* |
870 | * when autonegotiation advertisement is only 1000Mbps then we | |
bc7f75fa | 871 | * should disable SmartSpeed and enable Auto MasterSlave |
ad68076e BA |
872 | * resolution as hardware default. |
873 | */ | |
bc7f75fa AK |
874 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
875 | /* Disable SmartSpeed */ | |
876 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 877 | &data); |
bc7f75fa AK |
878 | if (ret_val) |
879 | return ret_val; | |
880 | ||
881 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
882 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 883 | data); |
bc7f75fa AK |
884 | if (ret_val) |
885 | return ret_val; | |
886 | ||
887 | /* Set auto Master/Slave resolution process */ | |
888 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
889 | if (ret_val) | |
890 | return ret_val; | |
891 | ||
892 | data &= ~CR_1000T_MS_ENABLE; | |
893 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
894 | if (ret_val) | |
895 | return ret_val; | |
896 | } | |
897 | ||
898 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
899 | if (ret_val) | |
900 | return ret_val; | |
901 | ||
902 | /* load defaults for future use */ | |
903 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
904 | ((data & CR_1000T_MS_VALUE) ? | |
905 | e1000_ms_force_master : | |
906 | e1000_ms_force_slave) : | |
907 | e1000_ms_auto; | |
908 | ||
909 | switch (phy->ms_type) { | |
910 | case e1000_ms_force_master: | |
911 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
912 | break; | |
913 | case e1000_ms_force_slave: | |
914 | data |= CR_1000T_MS_ENABLE; | |
915 | data &= ~(CR_1000T_MS_VALUE); | |
916 | break; | |
917 | case e1000_ms_auto: | |
918 | data &= ~CR_1000T_MS_ENABLE; | |
919 | default: | |
920 | break; | |
921 | } | |
922 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
923 | } | |
924 | ||
925 | return ret_val; | |
926 | } | |
927 | ||
928 | /** | |
929 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation | |
930 | * @hw: pointer to the HW structure | |
931 | * | |
932 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
933 | * register and if the PHY is already setup for auto-negotiation, then | |
934 | * return successful. Otherwise, setup advertisement and flow control to | |
935 | * the appropriate values for the wanted auto-negotiation. | |
936 | **/ | |
937 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
938 | { | |
939 | struct e1000_phy_info *phy = &hw->phy; | |
940 | s32 ret_val; | |
941 | u16 mii_autoneg_adv_reg; | |
942 | u16 mii_1000t_ctrl_reg = 0; | |
943 | ||
944 | phy->autoneg_advertised &= phy->autoneg_mask; | |
945 | ||
946 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
947 | ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
948 | if (ret_val) | |
949 | return ret_val; | |
950 | ||
951 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
952 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
953 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
954 | if (ret_val) | |
955 | return ret_val; | |
956 | } | |
957 | ||
ad68076e BA |
958 | /* |
959 | * Need to parse both autoneg_advertised and fc and set up | |
bc7f75fa AK |
960 | * the appropriate PHY registers. First we will parse for |
961 | * autoneg_advertised software override. Since we can advertise | |
962 | * a plethora of combinations, we need to check each bit | |
963 | * individually. | |
964 | */ | |
965 | ||
ad68076e BA |
966 | /* |
967 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
bc7f75fa AK |
968 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
969 | * the 1000Base-T Control Register (Address 9). | |
970 | */ | |
971 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
972 | NWAY_AR_100TX_HD_CAPS | | |
973 | NWAY_AR_10T_FD_CAPS | | |
974 | NWAY_AR_10T_HD_CAPS); | |
975 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
976 | ||
3bb99fe2 | 977 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
bc7f75fa AK |
978 | |
979 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
980 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
3bb99fe2 | 981 | e_dbg("Advertise 10mb Half duplex\n"); |
bc7f75fa AK |
982 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
983 | } | |
984 | ||
985 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
986 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
3bb99fe2 | 987 | e_dbg("Advertise 10mb Full duplex\n"); |
bc7f75fa AK |
988 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
989 | } | |
990 | ||
991 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
992 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
3bb99fe2 | 993 | e_dbg("Advertise 100mb Half duplex\n"); |
bc7f75fa AK |
994 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
995 | } | |
996 | ||
997 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
998 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
3bb99fe2 | 999 | e_dbg("Advertise 100mb Full duplex\n"); |
bc7f75fa AK |
1000 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
1001 | } | |
1002 | ||
1003 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
1004 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
3bb99fe2 | 1005 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
bc7f75fa AK |
1006 | |
1007 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
1008 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3bb99fe2 | 1009 | e_dbg("Advertise 1000mb Full duplex\n"); |
bc7f75fa AK |
1010 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
1011 | } | |
1012 | ||
ad68076e BA |
1013 | /* |
1014 | * Check for a software override of the flow control settings, and | |
bc7f75fa AK |
1015 | * setup the PHY advertisement registers accordingly. If |
1016 | * auto-negotiation is enabled, then software will have to set the | |
1017 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
1018 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
1019 | * negotiation. | |
1020 | * | |
1021 | * The possible values of the "fc" parameter are: | |
1022 | * 0: Flow control is completely disabled | |
1023 | * 1: Rx flow control is enabled (we can receive pause frames | |
3d3a1676 | 1024 | * but not send pause frames). |
bc7f75fa | 1025 | * 2: Tx flow control is enabled (we can send pause frames |
3d3a1676 | 1026 | * but we do not support receiving pause frames). |
ad68076e | 1027 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bc7f75fa | 1028 | * other: No software override. The flow control configuration |
3d3a1676 | 1029 | * in the EEPROM is used. |
bc7f75fa | 1030 | */ |
5c48ef3e | 1031 | switch (hw->fc.current_mode) { |
bc7f75fa | 1032 | case e1000_fc_none: |
ad68076e BA |
1033 | /* |
1034 | * Flow control (Rx & Tx) is completely disabled by a | |
bc7f75fa AK |
1035 | * software over-ride. |
1036 | */ | |
1037 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1038 | break; | |
1039 | case e1000_fc_rx_pause: | |
ad68076e BA |
1040 | /* |
1041 | * Rx Flow control is enabled, and Tx Flow control is | |
bc7f75fa | 1042 | * disabled, by a software over-ride. |
ad68076e BA |
1043 | * |
1044 | * Since there really isn't a way to advertise that we are | |
1045 | * capable of Rx Pause ONLY, we will advertise that we | |
1046 | * support both symmetric and asymmetric Rx PAUSE. Later | |
bc7f75fa AK |
1047 | * (in e1000e_config_fc_after_link_up) we will disable the |
1048 | * hw's ability to send PAUSE frames. | |
1049 | */ | |
1050 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1051 | break; | |
1052 | case e1000_fc_tx_pause: | |
ad68076e BA |
1053 | /* |
1054 | * Tx Flow control is enabled, and Rx Flow control is | |
bc7f75fa AK |
1055 | * disabled, by a software over-ride. |
1056 | */ | |
1057 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1058 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1059 | break; | |
1060 | case e1000_fc_full: | |
ad68076e BA |
1061 | /* |
1062 | * Flow control (both Rx and Tx) is enabled by a software | |
bc7f75fa AK |
1063 | * over-ride. |
1064 | */ | |
1065 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1066 | break; | |
1067 | default: | |
3bb99fe2 | 1068 | e_dbg("Flow control param set incorrectly\n"); |
7eb61d81 | 1069 | return -E1000_ERR_CONFIG; |
bc7f75fa AK |
1070 | } |
1071 | ||
1072 | ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
1073 | if (ret_val) | |
1074 | return ret_val; | |
1075 | ||
3bb99fe2 | 1076 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
bc7f75fa | 1077 | |
b1cdfead | 1078 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) |
bc7f75fa | 1079 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
bc7f75fa AK |
1080 | |
1081 | return ret_val; | |
1082 | } | |
1083 | ||
1084 | /** | |
1085 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link | |
1086 | * @hw: pointer to the HW structure | |
1087 | * | |
1088 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
1089 | * configure to advertise the full capability. Setup the PHY to autoneg | |
1090 | * and restart the negotiation process between the link partner. If | |
ad68076e | 1091 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
bc7f75fa AK |
1092 | **/ |
1093 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1094 | { | |
1095 | struct e1000_phy_info *phy = &hw->phy; | |
1096 | s32 ret_val; | |
1097 | u16 phy_ctrl; | |
1098 | ||
ad68076e BA |
1099 | /* |
1100 | * Perform some bounds checking on the autoneg advertisement | |
bc7f75fa AK |
1101 | * parameter. |
1102 | */ | |
1103 | phy->autoneg_advertised &= phy->autoneg_mask; | |
1104 | ||
ad68076e BA |
1105 | /* |
1106 | * If autoneg_advertised is zero, we assume it was not defaulted | |
bc7f75fa AK |
1107 | * by the calling code so we set to advertise full capability. |
1108 | */ | |
04499ec4 | 1109 | if (!phy->autoneg_advertised) |
bc7f75fa AK |
1110 | phy->autoneg_advertised = phy->autoneg_mask; |
1111 | ||
3bb99fe2 | 1112 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
bc7f75fa AK |
1113 | ret_val = e1000_phy_setup_autoneg(hw); |
1114 | if (ret_val) { | |
3bb99fe2 | 1115 | e_dbg("Error Setting up Auto-Negotiation\n"); |
bc7f75fa AK |
1116 | return ret_val; |
1117 | } | |
3bb99fe2 | 1118 | e_dbg("Restarting Auto-Neg\n"); |
bc7f75fa | 1119 | |
ad68076e BA |
1120 | /* |
1121 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
bc7f75fa AK |
1122 | * the Auto Neg Restart bit in the PHY control register. |
1123 | */ | |
1124 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
1125 | if (ret_val) | |
1126 | return ret_val; | |
1127 | ||
1128 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
1129 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
1130 | if (ret_val) | |
1131 | return ret_val; | |
1132 | ||
ad68076e BA |
1133 | /* |
1134 | * Does the user want to wait for Auto-Neg to complete here, or | |
bc7f75fa AK |
1135 | * check at a later time (for example, callback routine). |
1136 | */ | |
318a94d6 | 1137 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
1138 | ret_val = e1000_wait_autoneg(hw); |
1139 | if (ret_val) { | |
434f1392 | 1140 | e_dbg("Error while waiting for autoneg to complete\n"); |
bc7f75fa AK |
1141 | return ret_val; |
1142 | } | |
1143 | } | |
1144 | ||
f92518dd | 1145 | hw->mac.get_link_status = true; |
bc7f75fa AK |
1146 | |
1147 | return ret_val; | |
1148 | } | |
1149 | ||
1150 | /** | |
1151 | * e1000e_setup_copper_link - Configure copper link settings | |
1152 | * @hw: pointer to the HW structure | |
1153 | * | |
1154 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1155 | * speed and duplex. Then we check for link, once link is established calls | |
1156 | * to configure collision distance and flow control are called. If link is | |
1157 | * not established, we return -E1000_ERR_PHY (-2). | |
1158 | **/ | |
1159 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) | |
1160 | { | |
1161 | s32 ret_val; | |
1162 | bool link; | |
1163 | ||
1164 | if (hw->mac.autoneg) { | |
ad68076e BA |
1165 | /* |
1166 | * Setup autoneg and flow control advertisement and perform | |
1167 | * autonegotiation. | |
1168 | */ | |
bc7f75fa AK |
1169 | ret_val = e1000_copper_link_autoneg(hw); |
1170 | if (ret_val) | |
1171 | return ret_val; | |
1172 | } else { | |
ad68076e BA |
1173 | /* |
1174 | * PHY will be set to 10H, 10F, 100H or 100F | |
1175 | * depending on user settings. | |
1176 | */ | |
3bb99fe2 | 1177 | e_dbg("Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1178 | ret_val = e1000_phy_force_speed_duplex(hw); |
1179 | if (ret_val) { | |
3bb99fe2 | 1180 | e_dbg("Error Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1181 | return ret_val; |
1182 | } | |
1183 | } | |
1184 | ||
ad68076e BA |
1185 | /* |
1186 | * Check link status. Wait up to 100 microseconds for link to become | |
bc7f75fa AK |
1187 | * valid. |
1188 | */ | |
3d3a1676 BA |
1189 | ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, |
1190 | &link); | |
bc7f75fa AK |
1191 | if (ret_val) |
1192 | return ret_val; | |
1193 | ||
1194 | if (link) { | |
3bb99fe2 | 1195 | e_dbg("Valid link established!!!\n"); |
57cde763 | 1196 | hw->mac.ops.config_collision_dist(hw); |
bc7f75fa AK |
1197 | ret_val = e1000e_config_fc_after_link_up(hw); |
1198 | } else { | |
3bb99fe2 | 1199 | e_dbg("Unable to establish link!!!\n"); |
bc7f75fa AK |
1200 | } |
1201 | ||
1202 | return ret_val; | |
1203 | } | |
1204 | ||
1205 | /** | |
1206 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY | |
1207 | * @hw: pointer to the HW structure | |
1208 | * | |
1209 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1210 | * auto-crossover to force MDI manually. Waits for link and returns | |
1211 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1212 | **/ | |
1213 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1214 | { | |
1215 | struct e1000_phy_info *phy = &hw->phy; | |
1216 | s32 ret_val; | |
1217 | u16 phy_data; | |
1218 | bool link; | |
1219 | ||
1220 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1221 | if (ret_val) | |
1222 | return ret_val; | |
1223 | ||
1224 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1225 | ||
1226 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
1227 | if (ret_val) | |
1228 | return ret_val; | |
1229 | ||
ad68076e BA |
1230 | /* |
1231 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
bc7f75fa AK |
1232 | * forced whenever speed and duplex are forced. |
1233 | */ | |
1234 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1235 | if (ret_val) | |
1236 | return ret_val; | |
1237 | ||
1238 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1239 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1240 | ||
1241 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1242 | if (ret_val) | |
1243 | return ret_val; | |
1244 | ||
3bb99fe2 | 1245 | e_dbg("IGP PSCR: %X\n", phy_data); |
bc7f75fa AK |
1246 | |
1247 | udelay(1); | |
1248 | ||
318a94d6 | 1249 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1250 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
bc7f75fa | 1251 | |
3d3a1676 BA |
1252 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1253 | 100000, &link); | |
bc7f75fa AK |
1254 | if (ret_val) |
1255 | return ret_val; | |
1256 | ||
1257 | if (!link) | |
3bb99fe2 | 1258 | e_dbg("Link taking longer than expected.\n"); |
bc7f75fa AK |
1259 | |
1260 | /* Try once more */ | |
3d3a1676 BA |
1261 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1262 | 100000, &link); | |
bc7f75fa AK |
1263 | } |
1264 | ||
1265 | return ret_val; | |
1266 | } | |
1267 | ||
1268 | /** | |
1269 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY | |
1270 | * @hw: pointer to the HW structure | |
1271 | * | |
1272 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1273 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1274 | * changes. If time expires while waiting for link up, we reset the DSP. | |
ad68076e | 1275 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
bc7f75fa AK |
1276 | * successful completion, else return corresponding error code. |
1277 | **/ | |
1278 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1279 | { | |
1280 | struct e1000_phy_info *phy = &hw->phy; | |
1281 | s32 ret_val; | |
1282 | u16 phy_data; | |
1283 | bool link; | |
1284 | ||
ad68076e BA |
1285 | /* |
1286 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
1287 | * forced whenever speed and duplex are forced. |
1288 | */ | |
1289 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1290 | if (ret_val) | |
1291 | return ret_val; | |
1292 | ||
1293 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1294 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1295 | if (ret_val) | |
1296 | return ret_val; | |
1297 | ||
3bb99fe2 | 1298 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
bc7f75fa AK |
1299 | |
1300 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1301 | if (ret_val) | |
1302 | return ret_val; | |
1303 | ||
1304 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1305 | ||
bc7f75fa AK |
1306 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
1307 | if (ret_val) | |
1308 | return ret_val; | |
1309 | ||
5aa49c82 BA |
1310 | /* Reset the phy to commit changes. */ |
1311 | ret_val = e1000e_commit_phy(hw); | |
1312 | if (ret_val) | |
1313 | return ret_val; | |
bc7f75fa | 1314 | |
318a94d6 | 1315 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1316 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
bc7f75fa AK |
1317 | |
1318 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1319 | 100000, &link); | |
1320 | if (ret_val) | |
1321 | return ret_val; | |
1322 | ||
1323 | if (!link) { | |
0be84010 BA |
1324 | if (hw->phy.type != e1000_phy_m88) { |
1325 | e_dbg("Link taking longer than expected.\n"); | |
1326 | } else { | |
1327 | /* | |
1328 | * We didn't get link. | |
1329 | * Reset the DSP and cross our fingers. | |
1330 | */ | |
482fed85 BA |
1331 | ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
1332 | 0x001d); | |
0be84010 BA |
1333 | if (ret_val) |
1334 | return ret_val; | |
1335 | ret_val = e1000e_phy_reset_dsp(hw); | |
1336 | if (ret_val) | |
1337 | return ret_val; | |
1338 | } | |
bc7f75fa AK |
1339 | } |
1340 | ||
1341 | /* Try once more */ | |
1342 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1343 | 100000, &link); | |
1344 | if (ret_val) | |
1345 | return ret_val; | |
1346 | } | |
1347 | ||
0be84010 BA |
1348 | if (hw->phy.type != e1000_phy_m88) |
1349 | return 0; | |
1350 | ||
bc7f75fa AK |
1351 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
1352 | if (ret_val) | |
1353 | return ret_val; | |
1354 | ||
ad68076e BA |
1355 | /* |
1356 | * Resetting the phy means we need to re-force TX_CLK in the | |
bc7f75fa AK |
1357 | * Extended PHY Specific Control Register to 25MHz clock from |
1358 | * the reset value of 2.5MHz. | |
1359 | */ | |
1360 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1361 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1362 | if (ret_val) | |
1363 | return ret_val; | |
1364 | ||
ad68076e BA |
1365 | /* |
1366 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
1367 | * duplex. |
1368 | */ | |
1369 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1370 | if (ret_val) | |
1371 | return ret_val; | |
1372 | ||
1373 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
1374 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1375 | ||
1376 | return ret_val; | |
1377 | } | |
1378 | ||
0be84010 BA |
1379 | /** |
1380 | * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex | |
1381 | * @hw: pointer to the HW structure | |
1382 | * | |
1383 | * Forces the speed and duplex settings of the PHY. | |
1384 | * This is a function pointer entry point only called by | |
1385 | * PHY setup routines. | |
1386 | **/ | |
1387 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) | |
1388 | { | |
1389 | struct e1000_phy_info *phy = &hw->phy; | |
1390 | s32 ret_val; | |
1391 | u16 data; | |
1392 | bool link; | |
1393 | ||
1394 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | |
1395 | if (ret_val) | |
5015e53a | 1396 | return ret_val; |
0be84010 BA |
1397 | |
1398 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
1399 | ||
1400 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | |
1401 | if (ret_val) | |
5015e53a | 1402 | return ret_val; |
0be84010 BA |
1403 | |
1404 | /* Disable MDI-X support for 10/100 */ | |
1405 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
1406 | if (ret_val) | |
5015e53a | 1407 | return ret_val; |
0be84010 BA |
1408 | |
1409 | data &= ~IFE_PMC_AUTO_MDIX; | |
1410 | data &= ~IFE_PMC_FORCE_MDIX; | |
1411 | ||
1412 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
1413 | if (ret_val) | |
5015e53a | 1414 | return ret_val; |
0be84010 BA |
1415 | |
1416 | e_dbg("IFE PMC: %X\n", data); | |
1417 | ||
1418 | udelay(1); | |
1419 | ||
1420 | if (phy->autoneg_wait_to_complete) { | |
1421 | e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); | |
1422 | ||
3d3a1676 BA |
1423 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1424 | 100000, &link); | |
0be84010 | 1425 | if (ret_val) |
5015e53a | 1426 | return ret_val; |
0be84010 BA |
1427 | |
1428 | if (!link) | |
1429 | e_dbg("Link taking longer than expected.\n"); | |
1430 | ||
1431 | /* Try once more */ | |
3d3a1676 BA |
1432 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1433 | 100000, &link); | |
0be84010 | 1434 | if (ret_val) |
5015e53a | 1435 | return ret_val; |
0be84010 BA |
1436 | } |
1437 | ||
5015e53a | 1438 | return 0; |
0be84010 BA |
1439 | } |
1440 | ||
bc7f75fa AK |
1441 | /** |
1442 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex | |
1443 | * @hw: pointer to the HW structure | |
1444 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1445 | * | |
1446 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1447 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1448 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1449 | * the collision distance, write configuration to CTRL register. The | |
1450 | * caller must write to the PHY_CONTROL register for these settings to | |
1451 | * take affect. | |
1452 | **/ | |
1453 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) | |
1454 | { | |
1455 | struct e1000_mac_info *mac = &hw->mac; | |
1456 | u32 ctrl; | |
1457 | ||
1458 | /* Turn off flow control when forcing speed/duplex */ | |
5c48ef3e | 1459 | hw->fc.current_mode = e1000_fc_none; |
bc7f75fa AK |
1460 | |
1461 | /* Force speed/duplex on the mac */ | |
1462 | ctrl = er32(CTRL); | |
1463 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1464 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1465 | ||
1466 | /* Disable Auto Speed Detection */ | |
1467 | ctrl &= ~E1000_CTRL_ASDE; | |
1468 | ||
1469 | /* Disable autoneg on the phy */ | |
1470 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1471 | ||
1472 | /* Forcing Full or Half Duplex? */ | |
1473 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1474 | ctrl &= ~E1000_CTRL_FD; | |
1475 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1476 | e_dbg("Half Duplex\n"); |
bc7f75fa AK |
1477 | } else { |
1478 | ctrl |= E1000_CTRL_FD; | |
1479 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1480 | e_dbg("Full Duplex\n"); |
bc7f75fa AK |
1481 | } |
1482 | ||
1483 | /* Forcing 10mb or 100mb? */ | |
1484 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1485 | ctrl |= E1000_CTRL_SPD_100; | |
1486 | *phy_ctrl |= MII_CR_SPEED_100; | |
1487 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
3bb99fe2 | 1488 | e_dbg("Forcing 100mb\n"); |
bc7f75fa AK |
1489 | } else { |
1490 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1491 | *phy_ctrl |= MII_CR_SPEED_10; | |
1492 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
3bb99fe2 | 1493 | e_dbg("Forcing 10mb\n"); |
bc7f75fa AK |
1494 | } |
1495 | ||
57cde763 | 1496 | hw->mac.ops.config_collision_dist(hw); |
bc7f75fa AK |
1497 | |
1498 | ew32(CTRL, ctrl); | |
1499 | } | |
1500 | ||
1501 | /** | |
1502 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 | |
1503 | * @hw: pointer to the HW structure | |
1504 | * @active: boolean used to enable/disable lplu | |
1505 | * | |
1506 | * Success returns 0, Failure returns 1 | |
1507 | * | |
1508 | * The low power link up (lplu) state is set to the power management level D3 | |
1509 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1510 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1511 | * is used during Dx states where the power conservation is most important. | |
1512 | * During driver activity, SmartSpeed should be enabled so performance is | |
1513 | * maintained. | |
1514 | **/ | |
1515 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1516 | { | |
1517 | struct e1000_phy_info *phy = &hw->phy; | |
1518 | s32 ret_val; | |
1519 | u16 data; | |
1520 | ||
1521 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
1522 | if (ret_val) | |
1523 | return ret_val; | |
1524 | ||
1525 | if (!active) { | |
1526 | data &= ~IGP02E1000_PM_D3_LPLU; | |
2d9498f3 | 1527 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
bc7f75fa AK |
1528 | if (ret_val) |
1529 | return ret_val; | |
ad68076e BA |
1530 | /* |
1531 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1532 | * during Dx states where the power conservation is most |
1533 | * important. During driver activity we should enable | |
ad68076e BA |
1534 | * SmartSpeed, so performance is maintained. |
1535 | */ | |
bc7f75fa AK |
1536 | if (phy->smart_speed == e1000_smart_speed_on) { |
1537 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1538 | &data); |
bc7f75fa AK |
1539 | if (ret_val) |
1540 | return ret_val; | |
1541 | ||
1542 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
1543 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1544 | data); |
bc7f75fa AK |
1545 | if (ret_val) |
1546 | return ret_val; | |
1547 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1548 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1549 | &data); |
bc7f75fa AK |
1550 | if (ret_val) |
1551 | return ret_val; | |
1552 | ||
1553 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1554 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1555 | data); |
bc7f75fa AK |
1556 | if (ret_val) |
1557 | return ret_val; | |
1558 | } | |
1559 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1560 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1561 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1562 | data |= IGP02E1000_PM_D3_LPLU; | |
1563 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
1564 | if (ret_val) | |
1565 | return ret_val; | |
1566 | ||
1567 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
1568 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
1569 | if (ret_val) | |
1570 | return ret_val; | |
1571 | ||
1572 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1573 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
1574 | } | |
1575 | ||
1576 | return ret_val; | |
1577 | } | |
1578 | ||
1579 | /** | |
489815ce | 1580 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
bc7f75fa AK |
1581 | * @hw: pointer to the HW structure |
1582 | * | |
1583 | * Success returns 0, Failure returns 1 | |
1584 | * | |
1585 | * A downshift is detected by querying the PHY link health. | |
1586 | **/ | |
1587 | s32 e1000e_check_downshift(struct e1000_hw *hw) | |
1588 | { | |
1589 | struct e1000_phy_info *phy = &hw->phy; | |
1590 | s32 ret_val; | |
1591 | u16 phy_data, offset, mask; | |
1592 | ||
1593 | switch (phy->type) { | |
1594 | case e1000_phy_m88: | |
1595 | case e1000_phy_gg82563: | |
07f025e6 | 1596 | case e1000_phy_bm: |
a4f58f54 | 1597 | case e1000_phy_82578: |
bc7f75fa AK |
1598 | offset = M88E1000_PHY_SPEC_STATUS; |
1599 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1600 | break; | |
1601 | case e1000_phy_igp_2: | |
1602 | case e1000_phy_igp_3: | |
1603 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1604 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1605 | break; | |
1606 | default: | |
1607 | /* speed downshift not supported */ | |
564ea9bb | 1608 | phy->speed_downgraded = false; |
bc7f75fa AK |
1609 | return 0; |
1610 | } | |
1611 | ||
1612 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1613 | ||
1614 | if (!ret_val) | |
04499ec4 | 1615 | phy->speed_downgraded = !!(phy_data & mask); |
bc7f75fa AK |
1616 | |
1617 | return ret_val; | |
1618 | } | |
1619 | ||
1620 | /** | |
1621 | * e1000_check_polarity_m88 - Checks the polarity. | |
1622 | * @hw: pointer to the HW structure | |
1623 | * | |
1624 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1625 | * | |
1626 | * Polarity is determined based on the PHY specific status register. | |
1627 | **/ | |
0be84010 | 1628 | s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
bc7f75fa AK |
1629 | { |
1630 | struct e1000_phy_info *phy = &hw->phy; | |
1631 | s32 ret_val; | |
1632 | u16 data; | |
1633 | ||
1634 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); | |
1635 | ||
1636 | if (!ret_val) | |
1637 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1638 | ? e1000_rev_polarity_reversed | |
1639 | : e1000_rev_polarity_normal; | |
1640 | ||
1641 | return ret_val; | |
1642 | } | |
1643 | ||
1644 | /** | |
1645 | * e1000_check_polarity_igp - Checks the polarity. | |
1646 | * @hw: pointer to the HW structure | |
1647 | * | |
1648 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1649 | * | |
1650 | * Polarity is determined based on the PHY port status register, and the | |
1651 | * current speed (since there is no polarity at 100Mbps). | |
1652 | **/ | |
0be84010 | 1653 | s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
bc7f75fa AK |
1654 | { |
1655 | struct e1000_phy_info *phy = &hw->phy; | |
1656 | s32 ret_val; | |
1657 | u16 data, offset, mask; | |
1658 | ||
ad68076e BA |
1659 | /* |
1660 | * Polarity is determined based on the speed of | |
1661 | * our connection. | |
1662 | */ | |
bc7f75fa AK |
1663 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
1664 | if (ret_val) | |
1665 | return ret_val; | |
1666 | ||
1667 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1668 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1669 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1670 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1671 | } else { | |
ad68076e BA |
1672 | /* |
1673 | * This really only applies to 10Mbps since | |
bc7f75fa AK |
1674 | * there is no polarity for 100Mbps (always 0). |
1675 | */ | |
1676 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1677 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1678 | } | |
1679 | ||
1680 | ret_val = e1e_rphy(hw, offset, &data); | |
1681 | ||
1682 | if (!ret_val) | |
1683 | phy->cable_polarity = (data & mask) | |
1684 | ? e1000_rev_polarity_reversed | |
1685 | : e1000_rev_polarity_normal; | |
1686 | ||
1687 | return ret_val; | |
1688 | } | |
1689 | ||
0be84010 BA |
1690 | /** |
1691 | * e1000_check_polarity_ife - Check cable polarity for IFE PHY | |
1692 | * @hw: pointer to the HW structure | |
1693 | * | |
1694 | * Polarity is determined on the polarity reversal feature being enabled. | |
1695 | **/ | |
1696 | s32 e1000_check_polarity_ife(struct e1000_hw *hw) | |
1697 | { | |
1698 | struct e1000_phy_info *phy = &hw->phy; | |
1699 | s32 ret_val; | |
1700 | u16 phy_data, offset, mask; | |
1701 | ||
1702 | /* | |
1703 | * Polarity is determined based on the reversal feature being enabled. | |
1704 | */ | |
1705 | if (phy->polarity_correction) { | |
1706 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
1707 | mask = IFE_PESC_POLARITY_REVERSED; | |
1708 | } else { | |
1709 | offset = IFE_PHY_SPECIAL_CONTROL; | |
1710 | mask = IFE_PSC_FORCE_POLARITY; | |
1711 | } | |
1712 | ||
1713 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1714 | ||
1715 | if (!ret_val) | |
1716 | phy->cable_polarity = (phy_data & mask) | |
1717 | ? e1000_rev_polarity_reversed | |
1718 | : e1000_rev_polarity_normal; | |
1719 | ||
1720 | return ret_val; | |
1721 | } | |
1722 | ||
bc7f75fa | 1723 | /** |
ad68076e | 1724 | * e1000_wait_autoneg - Wait for auto-neg completion |
bc7f75fa AK |
1725 | * @hw: pointer to the HW structure |
1726 | * | |
1727 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1728 | * limit to expire, which ever happens first. | |
1729 | **/ | |
1730 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) | |
1731 | { | |
1732 | s32 ret_val = 0; | |
1733 | u16 i, phy_status; | |
1734 | ||
1735 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1736 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
1737 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1738 | if (ret_val) | |
1739 | break; | |
1740 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1741 | if (ret_val) | |
1742 | break; | |
1743 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1744 | break; | |
1745 | msleep(100); | |
1746 | } | |
1747 | ||
ad68076e BA |
1748 | /* |
1749 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
bc7f75fa AK |
1750 | * has completed. |
1751 | */ | |
1752 | return ret_val; | |
1753 | } | |
1754 | ||
1755 | /** | |
1756 | * e1000e_phy_has_link_generic - Polls PHY for link | |
1757 | * @hw: pointer to the HW structure | |
1758 | * @iterations: number of times to poll for link | |
1759 | * @usec_interval: delay between polling attempts | |
1760 | * @success: pointer to whether polling was successful or not | |
1761 | * | |
1762 | * Polls the PHY status register for link, 'iterations' number of times. | |
1763 | **/ | |
1764 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | |
1765 | u32 usec_interval, bool *success) | |
1766 | { | |
1767 | s32 ret_val = 0; | |
1768 | u16 i, phy_status; | |
1769 | ||
1770 | for (i = 0; i < iterations; i++) { | |
ad68076e BA |
1771 | /* |
1772 | * Some PHYs require the PHY_STATUS register to be read | |
bc7f75fa AK |
1773 | * twice due to the link bit being sticky. No harm doing |
1774 | * it across the board. | |
1775 | */ | |
1776 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1777 | if (ret_val) | |
906e8d97 BA |
1778 | /* |
1779 | * If the first read fails, another entity may have | |
1780 | * ownership of the resources, wait and try again to | |
1781 | * see if they have relinquished the resources yet. | |
1782 | */ | |
1783 | udelay(usec_interval); | |
bc7f75fa AK |
1784 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
1785 | if (ret_val) | |
1786 | break; | |
1787 | if (phy_status & MII_SR_LINK_STATUS) | |
1788 | break; | |
1789 | if (usec_interval >= 1000) | |
1790 | mdelay(usec_interval/1000); | |
1791 | else | |
1792 | udelay(usec_interval); | |
1793 | } | |
1794 | ||
1795 | *success = (i < iterations); | |
1796 | ||
1797 | return ret_val; | |
1798 | } | |
1799 | ||
1800 | /** | |
1801 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY | |
1802 | * @hw: pointer to the HW structure | |
1803 | * | |
1804 | * Reads the PHY specific status register to retrieve the cable length | |
1805 | * information. The cable length is determined by averaging the minimum and | |
1806 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1807 | * possible cable length values, which are: | |
1808 | * Register Value Cable Length | |
1809 | * 0 < 50 meters | |
1810 | * 1 50 - 80 meters | |
1811 | * 2 80 - 110 meters | |
1812 | * 3 110 - 140 meters | |
1813 | * 4 > 140 meters | |
1814 | **/ | |
1815 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |
1816 | { | |
1817 | struct e1000_phy_info *phy = &hw->phy; | |
1818 | s32 ret_val; | |
1819 | u16 phy_data, index; | |
1820 | ||
1821 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1822 | if (ret_val) | |
5015e53a | 1823 | return ret_val; |
bc7f75fa AK |
1824 | |
1825 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
eb656d45 | 1826 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
5015e53a BA |
1827 | |
1828 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) | |
1829 | return -E1000_ERR_PHY; | |
eb656d45 | 1830 | |
bc7f75fa | 1831 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
eb656d45 | 1832 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
bc7f75fa AK |
1833 | |
1834 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1835 | ||
5015e53a | 1836 | return 0; |
bc7f75fa AK |
1837 | } |
1838 | ||
1839 | /** | |
1840 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY | |
1841 | * @hw: pointer to the HW structure | |
1842 | * | |
1843 | * The automatic gain control (agc) normalizes the amplitude of the | |
1844 | * received signal, adjusting for the attenuation produced by the | |
489815ce | 1845 | * cable. By reading the AGC registers, which represent the |
5ff5b664 | 1846 | * combination of coarse and fine gain value, the value can be put |
bc7f75fa AK |
1847 | * into a lookup table to obtain the approximate cable length |
1848 | * for each channel. | |
1849 | **/ | |
1850 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) | |
1851 | { | |
1852 | struct e1000_phy_info *phy = &hw->phy; | |
1853 | s32 ret_val; | |
1854 | u16 phy_data, i, agc_value = 0; | |
1855 | u16 cur_agc_index, max_agc_index = 0; | |
1856 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
66744500 JK |
1857 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
1858 | IGP02E1000_PHY_AGC_A, | |
1859 | IGP02E1000_PHY_AGC_B, | |
1860 | IGP02E1000_PHY_AGC_C, | |
1861 | IGP02E1000_PHY_AGC_D | |
1862 | }; | |
bc7f75fa AK |
1863 | |
1864 | /* Read the AGC registers for all channels */ | |
1865 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
1866 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); | |
1867 | if (ret_val) | |
1868 | return ret_val; | |
1869 | ||
ad68076e BA |
1870 | /* |
1871 | * Getting bits 15:9, which represent the combination of | |
5ff5b664 | 1872 | * coarse and fine gain values. The result is a number |
bc7f75fa | 1873 | * that can be put into the lookup table to obtain the |
ad68076e BA |
1874 | * approximate cable length. |
1875 | */ | |
bc7f75fa AK |
1876 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
1877 | IGP02E1000_AGC_LENGTH_MASK; | |
1878 | ||
1879 | /* Array index bound check. */ | |
1880 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1881 | (cur_agc_index == 0)) | |
1882 | return -E1000_ERR_PHY; | |
1883 | ||
1884 | /* Remove min & max AGC values from calculation. */ | |
1885 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1886 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1887 | min_agc_index = cur_agc_index; | |
1888 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1889 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1890 | max_agc_index = cur_agc_index; | |
1891 | ||
1892 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1893 | } | |
1894 | ||
1895 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1896 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1897 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1898 | ||
1899 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1900 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1901 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1902 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1903 | ||
1904 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1905 | ||
82607255 | 1906 | return 0; |
bc7f75fa AK |
1907 | } |
1908 | ||
1909 | /** | |
1910 | * e1000e_get_phy_info_m88 - Retrieve PHY information | |
1911 | * @hw: pointer to the HW structure | |
1912 | * | |
1913 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1914 | * to verify that link is up. Read the PHY special control register to | |
1915 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1916 | * special status register to determine MDI/MDIx and current speed. If | |
1917 | * speed is 1000, then determine cable length, local and remote receiver. | |
1918 | **/ | |
1919 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) | |
1920 | { | |
1921 | struct e1000_phy_info *phy = &hw->phy; | |
1922 | s32 ret_val; | |
1923 | u16 phy_data; | |
1924 | bool link; | |
1925 | ||
0be84010 | 1926 | if (phy->media_type != e1000_media_type_copper) { |
3bb99fe2 | 1927 | e_dbg("Phy info is only valid for copper media\n"); |
bc7f75fa AK |
1928 | return -E1000_ERR_CONFIG; |
1929 | } | |
1930 | ||
1931 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1932 | if (ret_val) | |
1933 | return ret_val; | |
1934 | ||
1935 | if (!link) { | |
3bb99fe2 | 1936 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1937 | return -E1000_ERR_CONFIG; |
1938 | } | |
1939 | ||
1940 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1941 | if (ret_val) | |
1942 | return ret_val; | |
1943 | ||
04499ec4 BA |
1944 | phy->polarity_correction = !!(phy_data & |
1945 | M88E1000_PSCR_POLARITY_REVERSAL); | |
bc7f75fa AK |
1946 | |
1947 | ret_val = e1000_check_polarity_m88(hw); | |
1948 | if (ret_val) | |
1949 | return ret_val; | |
1950 | ||
1951 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1952 | if (ret_val) | |
1953 | return ret_val; | |
1954 | ||
04499ec4 | 1955 | phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); |
bc7f75fa AK |
1956 | |
1957 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
1958 | ret_val = e1000_get_cable_length(hw); | |
1959 | if (ret_val) | |
1960 | return ret_val; | |
1961 | ||
1962 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); | |
1963 | if (ret_val) | |
1964 | return ret_val; | |
1965 | ||
1966 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1967 | ? e1000_1000t_rx_status_ok | |
1968 | : e1000_1000t_rx_status_not_ok; | |
1969 | ||
1970 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1971 | ? e1000_1000t_rx_status_ok | |
1972 | : e1000_1000t_rx_status_not_ok; | |
1973 | } else { | |
1974 | /* Set values to "undefined" */ | |
1975 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1976 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1977 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1978 | } | |
1979 | ||
1980 | return ret_val; | |
1981 | } | |
1982 | ||
1983 | /** | |
1984 | * e1000e_get_phy_info_igp - Retrieve igp PHY information | |
1985 | * @hw: pointer to the HW structure | |
1986 | * | |
1987 | * Read PHY status to determine if link is up. If link is up, then | |
1988 | * set/determine 10base-T extended distance and polarity correction. Read | |
1989 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1990 | * determine on the cable length, local and remote receiver. | |
1991 | **/ | |
1992 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) | |
1993 | { | |
1994 | struct e1000_phy_info *phy = &hw->phy; | |
1995 | s32 ret_val; | |
1996 | u16 data; | |
1997 | bool link; | |
1998 | ||
1999 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
2000 | if (ret_val) | |
2001 | return ret_val; | |
2002 | ||
2003 | if (!link) { | |
3bb99fe2 | 2004 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
2005 | return -E1000_ERR_CONFIG; |
2006 | } | |
2007 | ||
564ea9bb | 2008 | phy->polarity_correction = true; |
bc7f75fa AK |
2009 | |
2010 | ret_val = e1000_check_polarity_igp(hw); | |
2011 | if (ret_val) | |
2012 | return ret_val; | |
2013 | ||
2014 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); | |
2015 | if (ret_val) | |
2016 | return ret_val; | |
2017 | ||
04499ec4 | 2018 | phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); |
bc7f75fa AK |
2019 | |
2020 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
2021 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
2022 | ret_val = e1000_get_cable_length(hw); | |
2023 | if (ret_val) | |
2024 | return ret_val; | |
2025 | ||
2026 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); | |
2027 | if (ret_val) | |
2028 | return ret_val; | |
2029 | ||
2030 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
2031 | ? e1000_1000t_rx_status_ok | |
2032 | : e1000_1000t_rx_status_not_ok; | |
2033 | ||
2034 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
2035 | ? e1000_1000t_rx_status_ok | |
2036 | : e1000_1000t_rx_status_not_ok; | |
2037 | } else { | |
2038 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2039 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2040 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2041 | } | |
2042 | ||
2043 | return ret_val; | |
2044 | } | |
2045 | ||
0be84010 BA |
2046 | /** |
2047 | * e1000_get_phy_info_ife - Retrieves various IFE PHY states | |
2048 | * @hw: pointer to the HW structure | |
2049 | * | |
2050 | * Populates "phy" structure with various feature states. | |
2051 | **/ | |
2052 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw) | |
2053 | { | |
2054 | struct e1000_phy_info *phy = &hw->phy; | |
2055 | s32 ret_val; | |
2056 | u16 data; | |
2057 | bool link; | |
2058 | ||
2059 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
2060 | if (ret_val) | |
5015e53a | 2061 | return ret_val; |
0be84010 BA |
2062 | |
2063 | if (!link) { | |
2064 | e_dbg("Phy info is only valid if link is up\n"); | |
5015e53a | 2065 | return -E1000_ERR_CONFIG; |
0be84010 BA |
2066 | } |
2067 | ||
2068 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
2069 | if (ret_val) | |
5015e53a | 2070 | return ret_val; |
04499ec4 | 2071 | phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); |
0be84010 BA |
2072 | |
2073 | if (phy->polarity_correction) { | |
2074 | ret_val = e1000_check_polarity_ife(hw); | |
2075 | if (ret_val) | |
5015e53a | 2076 | return ret_val; |
0be84010 BA |
2077 | } else { |
2078 | /* Polarity is forced */ | |
2079 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
2080 | ? e1000_rev_polarity_reversed | |
2081 | : e1000_rev_polarity_normal; | |
2082 | } | |
2083 | ||
2084 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
2085 | if (ret_val) | |
5015e53a | 2086 | return ret_val; |
0be84010 | 2087 | |
04499ec4 | 2088 | phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); |
0be84010 BA |
2089 | |
2090 | /* The following parameters are undefined for 10/100 operation. */ | |
2091 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2092 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2093 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2094 | ||
5015e53a | 2095 | return 0; |
0be84010 BA |
2096 | } |
2097 | ||
bc7f75fa AK |
2098 | /** |
2099 | * e1000e_phy_sw_reset - PHY software reset | |
2100 | * @hw: pointer to the HW structure | |
2101 | * | |
2102 | * Does a software reset of the PHY by reading the PHY control register and | |
2103 | * setting/write the control register reset bit to the PHY. | |
2104 | **/ | |
2105 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) | |
2106 | { | |
2107 | s32 ret_val; | |
2108 | u16 phy_ctrl; | |
2109 | ||
2110 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
2111 | if (ret_val) | |
2112 | return ret_val; | |
2113 | ||
2114 | phy_ctrl |= MII_CR_RESET; | |
2115 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
2116 | if (ret_val) | |
2117 | return ret_val; | |
2118 | ||
2119 | udelay(1); | |
2120 | ||
2121 | return ret_val; | |
2122 | } | |
2123 | ||
2124 | /** | |
2125 | * e1000e_phy_hw_reset_generic - PHY hardware reset | |
2126 | * @hw: pointer to the HW structure | |
2127 | * | |
2128 | * Verify the reset block is not blocking us from resetting. Acquire | |
2129 | * semaphore (if necessary) and read/set/write the device control reset | |
2130 | * bit in the PHY. Wait the appropriate delay time for the device to | |
489815ce | 2131 | * reset and release the semaphore (if necessary). |
bc7f75fa AK |
2132 | **/ |
2133 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) | |
2134 | { | |
2135 | struct e1000_phy_info *phy = &hw->phy; | |
2136 | s32 ret_val; | |
2137 | u32 ctrl; | |
2138 | ||
44abd5c1 | 2139 | ret_val = phy->ops.check_reset_block(hw); |
bc7f75fa AK |
2140 | if (ret_val) |
2141 | return 0; | |
2142 | ||
94d8186a | 2143 | ret_val = phy->ops.acquire(hw); |
bc7f75fa AK |
2144 | if (ret_val) |
2145 | return ret_val; | |
2146 | ||
2147 | ctrl = er32(CTRL); | |
2148 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | |
2149 | e1e_flush(); | |
2150 | ||
2151 | udelay(phy->reset_delay_us); | |
2152 | ||
2153 | ew32(CTRL, ctrl); | |
2154 | e1e_flush(); | |
2155 | ||
2156 | udelay(150); | |
2157 | ||
94d8186a | 2158 | phy->ops.release(hw); |
bc7f75fa AK |
2159 | |
2160 | return e1000_get_phy_cfg_done(hw); | |
2161 | } | |
2162 | ||
2163 | /** | |
2164 | * e1000e_get_cfg_done - Generic configuration done | |
2165 | * @hw: pointer to the HW structure | |
2166 | * | |
2167 | * Generic function to wait 10 milli-seconds for configuration to complete | |
2168 | * and return success. | |
2169 | **/ | |
2170 | s32 e1000e_get_cfg_done(struct e1000_hw *hw) | |
2171 | { | |
2172 | mdelay(10); | |
3d3a1676 | 2173 | |
bc7f75fa AK |
2174 | return 0; |
2175 | } | |
2176 | ||
f4187b56 BA |
2177 | /** |
2178 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY | |
2179 | * @hw: pointer to the HW structure | |
2180 | * | |
2181 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2182 | **/ | |
2183 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) | |
2184 | { | |
3bb99fe2 | 2185 | e_dbg("Running IGP 3 PHY init script\n"); |
f4187b56 BA |
2186 | |
2187 | /* PHY init IGP 3 */ | |
2188 | /* Enable rise/fall, 10-mode work in class-A */ | |
2189 | e1e_wphy(hw, 0x2F5B, 0x9018); | |
2190 | /* Remove all caps from Replica path filter */ | |
2191 | e1e_wphy(hw, 0x2F52, 0x0000); | |
2192 | /* Bias trimming for ADC, AFE and Driver (Default) */ | |
2193 | e1e_wphy(hw, 0x2FB1, 0x8B24); | |
2194 | /* Increase Hybrid poly bias */ | |
2195 | e1e_wphy(hw, 0x2FB2, 0xF8F0); | |
2196 | /* Add 4% to Tx amplitude in Gig mode */ | |
2197 | e1e_wphy(hw, 0x2010, 0x10B0); | |
2198 | /* Disable trimming (TTT) */ | |
2199 | e1e_wphy(hw, 0x2011, 0x0000); | |
2200 | /* Poly DC correction to 94.6% + 2% for all channels */ | |
2201 | e1e_wphy(hw, 0x20DD, 0x249A); | |
2202 | /* ABS DC correction to 95.9% */ | |
2203 | e1e_wphy(hw, 0x20DE, 0x00D3); | |
2204 | /* BG temp curve trim */ | |
2205 | e1e_wphy(hw, 0x28B4, 0x04CE); | |
2206 | /* Increasing ADC OPAMP stage 1 currents to max */ | |
2207 | e1e_wphy(hw, 0x2F70, 0x29E4); | |
2208 | /* Force 1000 ( required for enabling PHY regs configuration) */ | |
2209 | e1e_wphy(hw, 0x0000, 0x0140); | |
2210 | /* Set upd_freq to 6 */ | |
2211 | e1e_wphy(hw, 0x1F30, 0x1606); | |
2212 | /* Disable NPDFE */ | |
2213 | e1e_wphy(hw, 0x1F31, 0xB814); | |
2214 | /* Disable adaptive fixed FFE (Default) */ | |
2215 | e1e_wphy(hw, 0x1F35, 0x002A); | |
2216 | /* Enable FFE hysteresis */ | |
2217 | e1e_wphy(hw, 0x1F3E, 0x0067); | |
2218 | /* Fixed FFE for short cable lengths */ | |
2219 | e1e_wphy(hw, 0x1F54, 0x0065); | |
2220 | /* Fixed FFE for medium cable lengths */ | |
2221 | e1e_wphy(hw, 0x1F55, 0x002A); | |
2222 | /* Fixed FFE for long cable lengths */ | |
2223 | e1e_wphy(hw, 0x1F56, 0x002A); | |
2224 | /* Enable Adaptive Clip Threshold */ | |
2225 | e1e_wphy(hw, 0x1F72, 0x3FB0); | |
2226 | /* AHT reset limit to 1 */ | |
2227 | e1e_wphy(hw, 0x1F76, 0xC0FF); | |
2228 | /* Set AHT master delay to 127 msec */ | |
2229 | e1e_wphy(hw, 0x1F77, 0x1DEC); | |
2230 | /* Set scan bits for AHT */ | |
2231 | e1e_wphy(hw, 0x1F78, 0xF9EF); | |
2232 | /* Set AHT Preset bits */ | |
2233 | e1e_wphy(hw, 0x1F79, 0x0210); | |
2234 | /* Change integ_factor of channel A to 3 */ | |
2235 | e1e_wphy(hw, 0x1895, 0x0003); | |
2236 | /* Change prop_factor of channels BCD to 8 */ | |
2237 | e1e_wphy(hw, 0x1796, 0x0008); | |
2238 | /* Change cg_icount + enable integbp for channels BCD */ | |
2239 | e1e_wphy(hw, 0x1798, 0xD008); | |
2240 | /* | |
2241 | * Change cg_icount + enable integbp + change prop_factor_master | |
2242 | * to 8 for channel A | |
2243 | */ | |
2244 | e1e_wphy(hw, 0x1898, 0xD918); | |
2245 | /* Disable AHT in Slave mode on channel A */ | |
2246 | e1e_wphy(hw, 0x187A, 0x0800); | |
2247 | /* | |
2248 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
2249 | * Enable SPD+B2B | |
2250 | */ | |
2251 | e1e_wphy(hw, 0x0019, 0x008D); | |
2252 | /* Enable restart AN on an1000_dis change */ | |
2253 | e1e_wphy(hw, 0x001B, 0x2080); | |
2254 | /* Enable wh_fifo read clock in 10/100 modes */ | |
2255 | e1e_wphy(hw, 0x0014, 0x0045); | |
2256 | /* Restart AN, Speed selection is 1000 */ | |
2257 | e1e_wphy(hw, 0x0000, 0x1340); | |
2258 | ||
2259 | return 0; | |
2260 | } | |
2261 | ||
bc7f75fa AK |
2262 | /* Internal function pointers */ |
2263 | ||
2264 | /** | |
2265 | * e1000_get_phy_cfg_done - Generic PHY configuration done | |
2266 | * @hw: pointer to the HW structure | |
2267 | * | |
2268 | * Return success if silicon family did not implement a family specific | |
2269 | * get_cfg_done function. | |
2270 | **/ | |
2271 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
2272 | { | |
2273 | if (hw->phy.ops.get_cfg_done) | |
2274 | return hw->phy.ops.get_cfg_done(hw); | |
2275 | ||
2276 | return 0; | |
2277 | } | |
2278 | ||
2279 | /** | |
2280 | * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex | |
2281 | * @hw: pointer to the HW structure | |
2282 | * | |
2283 | * When the silicon family has not implemented a forced speed/duplex | |
2284 | * function for the PHY, simply return 0. | |
2285 | **/ | |
2286 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
2287 | { | |
2288 | if (hw->phy.ops.force_speed_duplex) | |
2289 | return hw->phy.ops.force_speed_duplex(hw); | |
2290 | ||
2291 | return 0; | |
2292 | } | |
2293 | ||
2294 | /** | |
2295 | * e1000e_get_phy_type_from_id - Get PHY type from id | |
2296 | * @phy_id: phy_id read from the phy | |
2297 | * | |
2298 | * Returns the phy type from the id. | |
2299 | **/ | |
2300 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) | |
2301 | { | |
2302 | enum e1000_phy_type phy_type = e1000_phy_unknown; | |
2303 | ||
2304 | switch (phy_id) { | |
2305 | case M88E1000_I_PHY_ID: | |
2306 | case M88E1000_E_PHY_ID: | |
2307 | case M88E1111_I_PHY_ID: | |
2308 | case M88E1011_I_PHY_ID: | |
2309 | phy_type = e1000_phy_m88; | |
2310 | break; | |
2311 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ | |
2312 | phy_type = e1000_phy_igp_2; | |
2313 | break; | |
2314 | case GG82563_E_PHY_ID: | |
2315 | phy_type = e1000_phy_gg82563; | |
2316 | break; | |
2317 | case IGP03E1000_E_PHY_ID: | |
2318 | phy_type = e1000_phy_igp_3; | |
2319 | break; | |
2320 | case IFE_E_PHY_ID: | |
2321 | case IFE_PLUS_E_PHY_ID: | |
2322 | case IFE_C_E_PHY_ID: | |
2323 | phy_type = e1000_phy_ife; | |
2324 | break; | |
97ac8cae BA |
2325 | case BME1000_E_PHY_ID: |
2326 | case BME1000_E_PHY_ID_R2: | |
2327 | phy_type = e1000_phy_bm; | |
2328 | break; | |
a4f58f54 BA |
2329 | case I82578_E_PHY_ID: |
2330 | phy_type = e1000_phy_82578; | |
2331 | break; | |
2332 | case I82577_E_PHY_ID: | |
2333 | phy_type = e1000_phy_82577; | |
2334 | break; | |
d3738bb8 BA |
2335 | case I82579_E_PHY_ID: |
2336 | phy_type = e1000_phy_82579; | |
2337 | break; | |
2fbe4526 BA |
2338 | case I217_E_PHY_ID: |
2339 | phy_type = e1000_phy_i217; | |
2340 | break; | |
bc7f75fa AK |
2341 | default: |
2342 | phy_type = e1000_phy_unknown; | |
2343 | break; | |
2344 | } | |
2345 | return phy_type; | |
2346 | } | |
2347 | ||
97ac8cae BA |
2348 | /** |
2349 | * e1000e_determine_phy_address - Determines PHY address. | |
2350 | * @hw: pointer to the HW structure | |
2351 | * | |
2352 | * This uses a trial and error method to loop through possible PHY | |
2353 | * addresses. It tests each by reading the PHY ID registers and | |
2354 | * checking for a match. | |
2355 | **/ | |
2356 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) | |
2357 | { | |
5eb6f3c7 BA |
2358 | u32 phy_addr = 0; |
2359 | u32 i; | |
97ac8cae BA |
2360 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
2361 | ||
5eb6f3c7 BA |
2362 | hw->phy.id = phy_type; |
2363 | ||
2364 | for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { | |
2365 | hw->phy.addr = phy_addr; | |
2366 | i = 0; | |
2367 | ||
2368 | do { | |
97ac8cae BA |
2369 | e1000e_get_phy_id(hw); |
2370 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); | |
2371 | ||
5eb6f3c7 | 2372 | /* |
97ac8cae BA |
2373 | * If phy_type is valid, break - we found our |
2374 | * PHY address | |
2375 | */ | |
5015e53a BA |
2376 | if (phy_type != e1000_phy_unknown) |
2377 | return 0; | |
2378 | ||
1bba4386 | 2379 | usleep_range(1000, 2000); |
5eb6f3c7 BA |
2380 | i++; |
2381 | } while (i < 10); | |
2382 | } | |
97ac8cae | 2383 | |
5015e53a | 2384 | return -E1000_ERR_PHY_TYPE; |
97ac8cae BA |
2385 | } |
2386 | ||
2387 | /** | |
2388 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address | |
2389 | * @page: page to access | |
2390 | * | |
2391 | * Returns the phy address for the page requested. | |
2392 | **/ | |
2393 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) | |
2394 | { | |
2395 | u32 phy_addr = 2; | |
2396 | ||
2397 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) | |
2398 | phy_addr = 1; | |
2399 | ||
2400 | return phy_addr; | |
2401 | } | |
2402 | ||
2403 | /** | |
2404 | * e1000e_write_phy_reg_bm - Write BM PHY register | |
2405 | * @hw: pointer to the HW structure | |
2406 | * @offset: register offset to write to | |
2407 | * @data: data to write at register offset | |
2408 | * | |
2409 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2410 | * at the offset. Release any acquired semaphores before exiting. | |
2411 | **/ | |
2412 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |
2413 | { | |
2414 | s32 ret_val; | |
97ac8cae | 2415 | u32 page = offset >> IGP_PAGE_SHIFT; |
97ac8cae | 2416 | |
94d8186a | 2417 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2418 | if (ret_val) |
2419 | return ret_val; | |
2420 | ||
97ac8cae BA |
2421 | /* Page 800 works differently than the rest so it has its own func */ |
2422 | if (page == BM_WUC_PAGE) { | |
2423 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2b6b168d | 2424 | false, false); |
75ce1532 | 2425 | goto release; |
97ac8cae BA |
2426 | } |
2427 | ||
97ac8cae BA |
2428 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2429 | ||
2430 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
90da0669 BA |
2431 | u32 page_shift, page_select; |
2432 | ||
97ac8cae BA |
2433 | /* |
2434 | * Page select is register 31 for phy address 1 and 22 for | |
2435 | * phy address 2 and 3. Page select is shifted only for | |
2436 | * phy address 1. | |
2437 | */ | |
2438 | if (hw->phy.addr == 1) { | |
2439 | page_shift = IGP_PAGE_SHIFT; | |
2440 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2441 | } else { | |
2442 | page_shift = 0; | |
2443 | page_select = BM_PHY_PAGE_SELECT; | |
2444 | } | |
2445 | ||
2446 | /* Page is shifted left, PHY expects (page x 32) */ | |
2447 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2448 | (page << page_shift)); | |
5ccdcecb | 2449 | if (ret_val) |
75ce1532 | 2450 | goto release; |
97ac8cae BA |
2451 | } |
2452 | ||
2453 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2454 | data); | |
2455 | ||
75ce1532 | 2456 | release: |
94d8186a | 2457 | hw->phy.ops.release(hw); |
97ac8cae BA |
2458 | return ret_val; |
2459 | } | |
2460 | ||
2461 | /** | |
2462 | * e1000e_read_phy_reg_bm - Read BM PHY register | |
2463 | * @hw: pointer to the HW structure | |
2464 | * @offset: register offset to be read | |
2465 | * @data: pointer to the read data | |
2466 | * | |
2467 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2468 | * and storing the retrieved information in data. Release any acquired | |
2469 | * semaphores before exiting. | |
2470 | **/ | |
2471 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |
2472 | { | |
2473 | s32 ret_val; | |
97ac8cae | 2474 | u32 page = offset >> IGP_PAGE_SHIFT; |
97ac8cae | 2475 | |
94d8186a | 2476 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2477 | if (ret_val) |
2478 | return ret_val; | |
2479 | ||
97ac8cae BA |
2480 | /* Page 800 works differently than the rest so it has its own func */ |
2481 | if (page == BM_WUC_PAGE) { | |
2482 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2b6b168d | 2483 | true, false); |
75ce1532 | 2484 | goto release; |
97ac8cae BA |
2485 | } |
2486 | ||
97ac8cae BA |
2487 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2488 | ||
2489 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
90da0669 BA |
2490 | u32 page_shift, page_select; |
2491 | ||
97ac8cae BA |
2492 | /* |
2493 | * Page select is register 31 for phy address 1 and 22 for | |
2494 | * phy address 2 and 3. Page select is shifted only for | |
2495 | * phy address 1. | |
2496 | */ | |
2497 | if (hw->phy.addr == 1) { | |
2498 | page_shift = IGP_PAGE_SHIFT; | |
2499 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2500 | } else { | |
2501 | page_shift = 0; | |
2502 | page_select = BM_PHY_PAGE_SELECT; | |
2503 | } | |
2504 | ||
2505 | /* Page is shifted left, PHY expects (page x 32) */ | |
2506 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2507 | (page << page_shift)); | |
5ccdcecb | 2508 | if (ret_val) |
75ce1532 | 2509 | goto release; |
97ac8cae BA |
2510 | } |
2511 | ||
2512 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2513 | data); | |
75ce1532 | 2514 | release: |
94d8186a | 2515 | hw->phy.ops.release(hw); |
97ac8cae BA |
2516 | return ret_val; |
2517 | } | |
2518 | ||
4662e82b BA |
2519 | /** |
2520 | * e1000e_read_phy_reg_bm2 - Read BM PHY register | |
2521 | * @hw: pointer to the HW structure | |
2522 | * @offset: register offset to be read | |
2523 | * @data: pointer to the read data | |
2524 | * | |
2525 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2526 | * and storing the retrieved information in data. Release any acquired | |
2527 | * semaphores before exiting. | |
2528 | **/ | |
2529 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |
2530 | { | |
2531 | s32 ret_val; | |
2532 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2533 | ||
94d8186a | 2534 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2535 | if (ret_val) |
2536 | return ret_val; | |
2537 | ||
4662e82b BA |
2538 | /* Page 800 works differently than the rest so it has its own func */ |
2539 | if (page == BM_WUC_PAGE) { | |
2540 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2b6b168d | 2541 | true, false); |
75ce1532 | 2542 | goto release; |
4662e82b BA |
2543 | } |
2544 | ||
4662e82b BA |
2545 | hw->phy.addr = 1; |
2546 | ||
2547 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2548 | ||
2549 | /* Page is shifted left, PHY expects (page x 32) */ | |
2550 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2551 | page); | |
2552 | ||
5ccdcecb | 2553 | if (ret_val) |
75ce1532 | 2554 | goto release; |
4662e82b BA |
2555 | } |
2556 | ||
2557 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2558 | data); | |
75ce1532 | 2559 | release: |
94d8186a | 2560 | hw->phy.ops.release(hw); |
4662e82b BA |
2561 | return ret_val; |
2562 | } | |
2563 | ||
2564 | /** | |
2565 | * e1000e_write_phy_reg_bm2 - Write BM PHY register | |
2566 | * @hw: pointer to the HW structure | |
2567 | * @offset: register offset to write to | |
2568 | * @data: data to write at register offset | |
2569 | * | |
2570 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2571 | * at the offset. Release any acquired semaphores before exiting. | |
2572 | **/ | |
2573 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |
2574 | { | |
2575 | s32 ret_val; | |
2576 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2577 | ||
94d8186a | 2578 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2579 | if (ret_val) |
2580 | return ret_val; | |
2581 | ||
4662e82b BA |
2582 | /* Page 800 works differently than the rest so it has its own func */ |
2583 | if (page == BM_WUC_PAGE) { | |
2584 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2b6b168d | 2585 | false, false); |
75ce1532 | 2586 | goto release; |
4662e82b BA |
2587 | } |
2588 | ||
4662e82b BA |
2589 | hw->phy.addr = 1; |
2590 | ||
2591 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2592 | /* Page is shifted left, PHY expects (page x 32) */ | |
2593 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2594 | page); | |
2595 | ||
5ccdcecb | 2596 | if (ret_val) |
75ce1532 | 2597 | goto release; |
4662e82b BA |
2598 | } |
2599 | ||
2600 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2601 | data); | |
2602 | ||
75ce1532 | 2603 | release: |
94d8186a | 2604 | hw->phy.ops.release(hw); |
4662e82b BA |
2605 | return ret_val; |
2606 | } | |
2607 | ||
97ac8cae | 2608 | /** |
2b6b168d | 2609 | * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers |
97ac8cae | 2610 | * @hw: pointer to the HW structure |
2b6b168d | 2611 | * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG |
97ac8cae | 2612 | * |
2b6b168d BA |
2613 | * Assumes semaphore already acquired and phy_reg points to a valid memory |
2614 | * address to store contents of the BM_WUC_ENABLE_REG register. | |
97ac8cae | 2615 | **/ |
2b6b168d | 2616 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
97ac8cae BA |
2617 | { |
2618 | s32 ret_val; | |
2b6b168d | 2619 | u16 temp; |
97ac8cae | 2620 | |
2b6b168d | 2621 | /* All page select, port ctrl and wakeup registers use phy address 1 */ |
97ac8cae BA |
2622 | hw->phy.addr = 1; |
2623 | ||
2b6b168d BA |
2624 | /* Select Port Control Registers page */ |
2625 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | |
2626 | if (ret_val) { | |
2627 | e_dbg("Could not set Port Control page\n"); | |
5015e53a | 2628 | return ret_val; |
2b6b168d | 2629 | } |
97ac8cae | 2630 | |
2b6b168d | 2631 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
9b71b419 | 2632 | if (ret_val) { |
2b6b168d BA |
2633 | e_dbg("Could not read PHY register %d.%d\n", |
2634 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | |
5015e53a | 2635 | return ret_val; |
9b71b419 | 2636 | } |
97ac8cae | 2637 | |
2b6b168d BA |
2638 | /* |
2639 | * Enable both PHY wakeup mode and Wakeup register page writes. | |
2640 | * Prevent a power state change by disabling ME and Host PHY wakeup. | |
2641 | */ | |
2642 | temp = *phy_reg; | |
2643 | temp |= BM_WUC_ENABLE_BIT; | |
2644 | temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); | |
2645 | ||
2646 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); | |
9b71b419 | 2647 | if (ret_val) { |
2b6b168d BA |
2648 | e_dbg("Could not write PHY register %d.%d\n", |
2649 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | |
5015e53a | 2650 | return ret_val; |
9b71b419 | 2651 | } |
97ac8cae | 2652 | |
5015e53a BA |
2653 | /* |
2654 | * Select Host Wakeup Registers page - caller now able to write | |
2655 | * registers on the Wakeup registers page | |
2656 | */ | |
2657 | return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); | |
2b6b168d BA |
2658 | } |
2659 | ||
2660 | /** | |
2661 | * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs | |
2662 | * @hw: pointer to the HW structure | |
2663 | * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG | |
2664 | * | |
2665 | * Restore BM_WUC_ENABLE_REG to its original value. | |
2666 | * | |
2667 | * Assumes semaphore already acquired and *phy_reg is the contents of the | |
2668 | * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by | |
2669 | * caller. | |
2670 | **/ | |
2671 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) | |
2672 | { | |
2673 | s32 ret_val = 0; | |
2674 | ||
2675 | /* Select Port Control Registers page */ | |
2676 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | |
9b71b419 | 2677 | if (ret_val) { |
2b6b168d | 2678 | e_dbg("Could not set Port Control page\n"); |
5015e53a | 2679 | return ret_val; |
9b71b419 | 2680 | } |
97ac8cae | 2681 | |
2b6b168d BA |
2682 | /* Restore 769.17 to its original value */ |
2683 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); | |
2684 | if (ret_val) | |
2685 | e_dbg("Could not restore PHY register %d.%d\n", | |
2686 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | |
5015e53a | 2687 | |
2b6b168d BA |
2688 | return ret_val; |
2689 | } | |
97ac8cae | 2690 | |
2b6b168d BA |
2691 | /** |
2692 | * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register | |
2693 | * @hw: pointer to the HW structure | |
2694 | * @offset: register offset to be read or written | |
2695 | * @data: pointer to the data to read or write | |
2696 | * @read: determines if operation is read or write | |
2697 | * @page_set: BM_WUC_PAGE already set and access enabled | |
2698 | * | |
2699 | * Read the PHY register at offset and store the retrieved information in | |
2700 | * data, or write data to PHY register at offset. Note the procedure to | |
2701 | * access the PHY wakeup registers is different than reading the other PHY | |
2702 | * registers. It works as such: | |
2703 | * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 | |
2704 | * 2) Set page to 800 for host (801 if we were manageability) | |
2705 | * 3) Write the address using the address opcode (0x11) | |
2706 | * 4) Read or write the data using the data opcode (0x12) | |
2707 | * 5) Restore 769.17.2 to its original value | |
2708 | * | |
2709 | * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and | |
2710 | * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). | |
2711 | * | |
2712 | * Assumes semaphore is already acquired. When page_set==true, assumes | |
2713 | * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack | |
2714 | * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). | |
2715 | **/ | |
2716 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
2717 | u16 *data, bool read, bool page_set) | |
2718 | { | |
2719 | s32 ret_val; | |
2720 | u16 reg = BM_PHY_REG_NUM(offset); | |
2721 | u16 page = BM_PHY_REG_PAGE(offset); | |
2722 | u16 phy_reg = 0; | |
2723 | ||
2724 | /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ | |
2725 | if ((hw->mac.type == e1000_pchlan) && | |
2726 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) | |
2727 | e_dbg("Attempting to access page %d while gig enabled.\n", | |
2728 | page); | |
2729 | ||
2730 | if (!page_set) { | |
2731 | /* Enable access to PHY wakeup registers */ | |
2732 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
2733 | if (ret_val) { | |
2734 | e_dbg("Could not enable PHY wakeup reg access\n"); | |
5015e53a | 2735 | return ret_val; |
2b6b168d BA |
2736 | } |
2737 | } | |
2738 | ||
2739 | e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); | |
2740 | ||
2741 | /* Write the Wakeup register page offset value using opcode 0x11 */ | |
97ac8cae | 2742 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
9b71b419 | 2743 | if (ret_val) { |
2b6b168d | 2744 | e_dbg("Could not write address opcode to page %d\n", page); |
5015e53a | 2745 | return ret_val; |
9b71b419 | 2746 | } |
97ac8cae BA |
2747 | |
2748 | if (read) { | |
2b6b168d | 2749 | /* Read the Wakeup register page value using opcode 0x12 */ |
97ac8cae BA |
2750 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
2751 | data); | |
2752 | } else { | |
2b6b168d | 2753 | /* Write the Wakeup register page value using opcode 0x12 */ |
97ac8cae BA |
2754 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
2755 | *data); | |
2756 | } | |
2757 | ||
9b71b419 | 2758 | if (ret_val) { |
2b6b168d | 2759 | e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
5015e53a | 2760 | return ret_val; |
9b71b419 | 2761 | } |
97ac8cae | 2762 | |
2b6b168d BA |
2763 | if (!page_set) |
2764 | ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
97ac8cae | 2765 | |
97ac8cae BA |
2766 | return ret_val; |
2767 | } | |
2768 | ||
17f208de BA |
2769 | /** |
2770 | * e1000_power_up_phy_copper - Restore copper link in case of PHY power down | |
2771 | * @hw: pointer to the HW structure | |
2772 | * | |
2773 | * In the case of a PHY power down to save power, or to turn off link during a | |
2774 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2775 | * settings. | |
2776 | **/ | |
2777 | void e1000_power_up_phy_copper(struct e1000_hw *hw) | |
2778 | { | |
2779 | u16 mii_reg = 0; | |
2780 | ||
2781 | /* The PHY will retain its settings across a power down/up cycle */ | |
2782 | e1e_rphy(hw, PHY_CONTROL, &mii_reg); | |
2783 | mii_reg &= ~MII_CR_POWER_DOWN; | |
2784 | e1e_wphy(hw, PHY_CONTROL, mii_reg); | |
2785 | } | |
2786 | ||
2787 | /** | |
2788 | * e1000_power_down_phy_copper - Restore copper link in case of PHY power down | |
2789 | * @hw: pointer to the HW structure | |
2790 | * | |
2791 | * In the case of a PHY power down to save power, or to turn off link during a | |
2792 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2793 | * settings. | |
2794 | **/ | |
2795 | void e1000_power_down_phy_copper(struct e1000_hw *hw) | |
2796 | { | |
2797 | u16 mii_reg = 0; | |
2798 | ||
2799 | /* The PHY will retain its settings across a power down/up cycle */ | |
2800 | e1e_rphy(hw, PHY_CONTROL, &mii_reg); | |
2801 | mii_reg |= MII_CR_POWER_DOWN; | |
2802 | e1e_wphy(hw, PHY_CONTROL, mii_reg); | |
1bba4386 | 2803 | usleep_range(1000, 2000); |
17f208de BA |
2804 | } |
2805 | ||
bc7f75fa AK |
2806 | /** |
2807 | * e1000e_commit_phy - Soft PHY reset | |
2808 | * @hw: pointer to the HW structure | |
2809 | * | |
2810 | * Performs a soft PHY reset on those that apply. This is a function pointer | |
2811 | * entry point called by drivers. | |
2812 | **/ | |
2813 | s32 e1000e_commit_phy(struct e1000_hw *hw) | |
2814 | { | |
94d8186a BA |
2815 | if (hw->phy.ops.commit) |
2816 | return hw->phy.ops.commit(hw); | |
bc7f75fa AK |
2817 | |
2818 | return 0; | |
2819 | } | |
2820 | ||
2821 | /** | |
2822 | * e1000_set_d0_lplu_state - Sets low power link up state for D0 | |
2823 | * @hw: pointer to the HW structure | |
2824 | * @active: boolean used to enable/disable lplu | |
2825 | * | |
2826 | * Success returns 0, Failure returns 1 | |
2827 | * | |
2828 | * The low power link up (lplu) state is set to the power management level D0 | |
2829 | * and SmartSpeed is disabled when active is true, else clear lplu for D0 | |
2830 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
2831 | * is used during Dx states where the power conservation is most important. | |
2832 | * During driver activity, SmartSpeed should be enabled so performance is | |
2833 | * maintained. This is a function pointer entry point called by drivers. | |
2834 | **/ | |
2835 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) | |
2836 | { | |
2837 | if (hw->phy.ops.set_d0_lplu_state) | |
2838 | return hw->phy.ops.set_d0_lplu_state(hw, active); | |
2839 | ||
2840 | return 0; | |
2841 | } | |
a4f58f54 | 2842 | |
a4f58f54 | 2843 | /** |
5ccdcecb | 2844 | * __e1000_read_phy_reg_hv - Read HV PHY register |
a4f58f54 BA |
2845 | * @hw: pointer to the HW structure |
2846 | * @offset: register offset to be read | |
2847 | * @data: pointer to the read data | |
5ccdcecb | 2848 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2849 | * |
2850 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 2851 | * and stores the retrieved information in data. Release any acquired |
a4f58f54 BA |
2852 | * semaphore before exiting. |
2853 | **/ | |
5ccdcecb | 2854 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
2b6b168d | 2855 | bool locked, bool page_set) |
a4f58f54 BA |
2856 | { |
2857 | s32 ret_val; | |
2858 | u16 page = BM_PHY_REG_PAGE(offset); | |
2859 | u16 reg = BM_PHY_REG_NUM(offset); | |
2b6b168d | 2860 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
a4f58f54 | 2861 | |
5ccdcecb | 2862 | if (!locked) { |
94d8186a | 2863 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2864 | if (ret_val) |
2865 | return ret_val; | |
2866 | } | |
2867 | ||
a4f58f54 BA |
2868 | /* Page 800 works differently than the rest so it has its own func */ |
2869 | if (page == BM_WUC_PAGE) { | |
2b6b168d BA |
2870 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
2871 | true, page_set); | |
a4f58f54 BA |
2872 | goto out; |
2873 | } | |
2874 | ||
2875 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2876 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2877 | data, true); | |
2878 | goto out; | |
2879 | } | |
2880 | ||
2b6b168d BA |
2881 | if (!page_set) { |
2882 | if (page == HV_INTC_FC_PAGE_START) | |
2883 | page = 0; | |
a4f58f54 | 2884 | |
2b6b168d BA |
2885 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
2886 | /* Page is shifted left, PHY expects (page x 32) */ | |
2887 | ret_val = e1000_set_page_igp(hw, | |
2888 | (page << IGP_PAGE_SHIFT)); | |
a4f58f54 | 2889 | |
2b6b168d | 2890 | hw->phy.addr = phy_addr; |
842ec8b6 | 2891 | |
2b6b168d BA |
2892 | if (ret_val) |
2893 | goto out; | |
2894 | } | |
a4f58f54 BA |
2895 | } |
2896 | ||
2b6b168d BA |
2897 | e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
2898 | page << IGP_PAGE_SHIFT, reg); | |
2899 | ||
a4f58f54 BA |
2900 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
2901 | data); | |
a4f58f54 | 2902 | out: |
5ccdcecb | 2903 | if (!locked) |
94d8186a | 2904 | hw->phy.ops.release(hw); |
5ccdcecb | 2905 | |
a4f58f54 BA |
2906 | return ret_val; |
2907 | } | |
2908 | ||
2909 | /** | |
5ccdcecb BA |
2910 | * e1000_read_phy_reg_hv - Read HV PHY register |
2911 | * @hw: pointer to the HW structure | |
2912 | * @offset: register offset to be read | |
2913 | * @data: pointer to the read data | |
2914 | * | |
2915 | * Acquires semaphore then reads the PHY register at offset and stores | |
2916 | * the retrieved information in data. Release the acquired semaphore | |
2917 | * before exiting. | |
2918 | **/ | |
2919 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2920 | { | |
2b6b168d | 2921 | return __e1000_read_phy_reg_hv(hw, offset, data, false, false); |
5ccdcecb BA |
2922 | } |
2923 | ||
2924 | /** | |
2925 | * e1000_read_phy_reg_hv_locked - Read HV PHY register | |
2926 | * @hw: pointer to the HW structure | |
2927 | * @offset: register offset to be read | |
2928 | * @data: pointer to the read data | |
2929 | * | |
2930 | * Reads the PHY register at offset and stores the retrieved information | |
2931 | * in data. Assumes semaphore already acquired. | |
2932 | **/ | |
2933 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
2934 | { | |
2b6b168d BA |
2935 | return __e1000_read_phy_reg_hv(hw, offset, data, true, false); |
2936 | } | |
2937 | ||
2938 | /** | |
2939 | * e1000_read_phy_reg_page_hv - Read HV PHY register | |
2940 | * @hw: pointer to the HW structure | |
2941 | * @offset: register offset to write to | |
2942 | * @data: data to write at register offset | |
2943 | * | |
2944 | * Reads the PHY register at offset and stores the retrieved information | |
2945 | * in data. Assumes semaphore already acquired and page already set. | |
2946 | **/ | |
2947 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2948 | { | |
2949 | return __e1000_read_phy_reg_hv(hw, offset, data, true, true); | |
5ccdcecb BA |
2950 | } |
2951 | ||
2952 | /** | |
2953 | * __e1000_write_phy_reg_hv - Write HV PHY register | |
a4f58f54 BA |
2954 | * @hw: pointer to the HW structure |
2955 | * @offset: register offset to write to | |
2956 | * @data: data to write at register offset | |
5ccdcecb | 2957 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2958 | * |
2959 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2960 | * at the offset. Release any acquired semaphores before exiting. | |
2961 | **/ | |
5ccdcecb | 2962 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
2b6b168d | 2963 | bool locked, bool page_set) |
a4f58f54 BA |
2964 | { |
2965 | s32 ret_val; | |
2966 | u16 page = BM_PHY_REG_PAGE(offset); | |
2967 | u16 reg = BM_PHY_REG_NUM(offset); | |
2b6b168d | 2968 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
a4f58f54 | 2969 | |
5ccdcecb | 2970 | if (!locked) { |
94d8186a | 2971 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2972 | if (ret_val) |
2973 | return ret_val; | |
2974 | } | |
2975 | ||
a4f58f54 BA |
2976 | /* Page 800 works differently than the rest so it has its own func */ |
2977 | if (page == BM_WUC_PAGE) { | |
2b6b168d BA |
2978 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
2979 | false, page_set); | |
a4f58f54 BA |
2980 | goto out; |
2981 | } | |
2982 | ||
2983 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2984 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2985 | &data, false); | |
2986 | goto out; | |
2987 | } | |
2988 | ||
2b6b168d BA |
2989 | if (!page_set) { |
2990 | if (page == HV_INTC_FC_PAGE_START) | |
2991 | page = 0; | |
a4f58f54 | 2992 | |
2b6b168d BA |
2993 | /* |
2994 | * Workaround MDIO accesses being disabled after entering IEEE | |
2995 | * Power Down (when bit 11 of the PHY Control register is set) | |
2996 | */ | |
2997 | if ((hw->phy.type == e1000_phy_82578) && | |
2998 | (hw->phy.revision >= 1) && | |
2999 | (hw->phy.addr == 2) && | |
04499ec4 | 3000 | !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { |
2b6b168d BA |
3001 | u16 data2 = 0x7EFF; |
3002 | ret_val = e1000_access_phy_debug_regs_hv(hw, | |
3003 | (1 << 6) | 0x3, | |
3004 | &data2, false); | |
3005 | if (ret_val) | |
3006 | goto out; | |
3007 | } | |
a4f58f54 | 3008 | |
2b6b168d BA |
3009 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
3010 | /* Page is shifted left, PHY expects (page x 32) */ | |
3011 | ret_val = e1000_set_page_igp(hw, | |
3012 | (page << IGP_PAGE_SHIFT)); | |
a4f58f54 | 3013 | |
2b6b168d | 3014 | hw->phy.addr = phy_addr; |
842ec8b6 | 3015 | |
2b6b168d BA |
3016 | if (ret_val) |
3017 | goto out; | |
3018 | } | |
a4f58f54 BA |
3019 | } |
3020 | ||
2b6b168d BA |
3021 | e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
3022 | page << IGP_PAGE_SHIFT, reg); | |
3023 | ||
a4f58f54 BA |
3024 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
3025 | data); | |
a4f58f54 BA |
3026 | |
3027 | out: | |
5ccdcecb | 3028 | if (!locked) |
94d8186a | 3029 | hw->phy.ops.release(hw); |
5ccdcecb | 3030 | |
a4f58f54 BA |
3031 | return ret_val; |
3032 | } | |
3033 | ||
5ccdcecb BA |
3034 | /** |
3035 | * e1000_write_phy_reg_hv - Write HV PHY register | |
3036 | * @hw: pointer to the HW structure | |
3037 | * @offset: register offset to write to | |
3038 | * @data: data to write at register offset | |
3039 | * | |
3040 | * Acquires semaphore then writes the data to PHY register at the offset. | |
3041 | * Release the acquired semaphores before exiting. | |
3042 | **/ | |
3043 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
3044 | { | |
2b6b168d | 3045 | return __e1000_write_phy_reg_hv(hw, offset, data, false, false); |
5ccdcecb BA |
3046 | } |
3047 | ||
3048 | /** | |
3049 | * e1000_write_phy_reg_hv_locked - Write HV PHY register | |
3050 | * @hw: pointer to the HW structure | |
3051 | * @offset: register offset to write to | |
3052 | * @data: data to write at register offset | |
3053 | * | |
3054 | * Writes the data to PHY register at the offset. Assumes semaphore | |
3055 | * already acquired. | |
3056 | **/ | |
3057 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
3058 | { | |
2b6b168d BA |
3059 | return __e1000_write_phy_reg_hv(hw, offset, data, true, false); |
3060 | } | |
3061 | ||
3062 | /** | |
3063 | * e1000_write_phy_reg_page_hv - Write HV PHY register | |
3064 | * @hw: pointer to the HW structure | |
3065 | * @offset: register offset to write to | |
3066 | * @data: data to write at register offset | |
3067 | * | |
3068 | * Writes the data to PHY register at the offset. Assumes semaphore | |
3069 | * already acquired and page already set. | |
3070 | **/ | |
3071 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
3072 | { | |
3073 | return __e1000_write_phy_reg_hv(hw, offset, data, true, true); | |
5ccdcecb BA |
3074 | } |
3075 | ||
a4f58f54 | 3076 | /** |
b595076a | 3077 | * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
a4f58f54 BA |
3078 | * @page: page to be accessed |
3079 | **/ | |
3080 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) | |
3081 | { | |
3082 | u32 phy_addr = 2; | |
3083 | ||
3084 | if (page >= HV_INTC_FC_PAGE_START) | |
3085 | phy_addr = 1; | |
3086 | ||
3087 | return phy_addr; | |
3088 | } | |
3089 | ||
3090 | /** | |
3091 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers | |
3092 | * @hw: pointer to the HW structure | |
3093 | * @offset: register offset to be read or written | |
3094 | * @data: pointer to the data to be read or written | |
2b6b168d | 3095 | * @read: determines if operation is read or write |
a4f58f54 | 3096 | * |
5ccdcecb BA |
3097 | * Reads the PHY register at offset and stores the retreived information |
3098 | * in data. Assumes semaphore already acquired. Note that the procedure | |
2b6b168d BA |
3099 | * to access these regs uses the address port and data port to read/write. |
3100 | * These accesses done with PHY address 2 and without using pages. | |
a4f58f54 BA |
3101 | **/ |
3102 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
3103 | u16 *data, bool read) | |
3104 | { | |
3105 | s32 ret_val; | |
3106 | u32 addr_reg = 0; | |
3107 | u32 data_reg = 0; | |
a4f58f54 BA |
3108 | |
3109 | /* This takes care of the difference with desktop vs mobile phy */ | |
3110 | addr_reg = (hw->phy.type == e1000_phy_82578) ? | |
3111 | I82578_ADDR_REG : I82577_ADDR_REG; | |
3112 | data_reg = addr_reg + 1; | |
3113 | ||
a4f58f54 BA |
3114 | /* All operations in this function are phy address 2 */ |
3115 | hw->phy.addr = 2; | |
3116 | ||
3117 | /* masking with 0x3F to remove the page from offset */ | |
3118 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); | |
3119 | if (ret_val) { | |
2b6b168d | 3120 | e_dbg("Could not write the Address Offset port register\n"); |
5015e53a | 3121 | return ret_val; |
a4f58f54 BA |
3122 | } |
3123 | ||
3124 | /* Read or write the data value next */ | |
3125 | if (read) | |
3126 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); | |
3127 | else | |
3128 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); | |
3129 | ||
5015e53a | 3130 | if (ret_val) |
2b6b168d | 3131 | e_dbg("Could not access the Data port register\n"); |
a4f58f54 | 3132 | |
a4f58f54 BA |
3133 | return ret_val; |
3134 | } | |
3135 | ||
3136 | /** | |
3137 | * e1000_link_stall_workaround_hv - Si workaround | |
3138 | * @hw: pointer to the HW structure | |
3139 | * | |
3140 | * This function works around a Si bug where the link partner can get | |
3141 | * a link up indication before the PHY does. If small packets are sent | |
3142 | * by the link partner they can be placed in the packet buffer without | |
3143 | * being properly accounted for by the PHY and will stall preventing | |
3144 | * further packets from being received. The workaround is to clear the | |
3145 | * packet buffer after the PHY detects link up. | |
3146 | **/ | |
3147 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |
3148 | { | |
3149 | s32 ret_val = 0; | |
3150 | u16 data; | |
3151 | ||
3152 | if (hw->phy.type != e1000_phy_82578) | |
5015e53a | 3153 | return 0; |
a4f58f54 | 3154 | |
e65fa87c | 3155 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
482fed85 | 3156 | e1e_rphy(hw, PHY_CONTROL, &data); |
e65fa87c | 3157 | if (data & PHY_CONTROL_LB) |
5015e53a | 3158 | return 0; |
e65fa87c | 3159 | |
a4f58f54 | 3160 | /* check if link is up and at 1Gbps */ |
482fed85 | 3161 | ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
a4f58f54 | 3162 | if (ret_val) |
5015e53a | 3163 | return ret_val; |
a4f58f54 | 3164 | |
3d3a1676 BA |
3165 | data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
3166 | BM_CS_STATUS_SPEED_MASK; | |
a4f58f54 | 3167 | |
3d3a1676 BA |
3168 | if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
3169 | BM_CS_STATUS_SPEED_1000)) | |
5015e53a | 3170 | return 0; |
a4f58f54 | 3171 | |
bb9c5ee1 | 3172 | msleep(200); |
a4f58f54 BA |
3173 | |
3174 | /* flush the packets in the fifo buffer */ | |
482fed85 BA |
3175 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | |
3176 | HV_MUX_DATA_CTRL_FORCE_SPEED); | |
a4f58f54 | 3177 | if (ret_val) |
5015e53a | 3178 | return ret_val; |
a4f58f54 | 3179 | |
5015e53a | 3180 | return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
a4f58f54 BA |
3181 | } |
3182 | ||
3183 | /** | |
3184 | * e1000_check_polarity_82577 - Checks the polarity. | |
3185 | * @hw: pointer to the HW structure | |
3186 | * | |
3187 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
3188 | * | |
3189 | * Polarity is determined based on the PHY specific status register. | |
3190 | **/ | |
3191 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) | |
3192 | { | |
3193 | struct e1000_phy_info *phy = &hw->phy; | |
3194 | s32 ret_val; | |
3195 | u16 data; | |
3196 | ||
482fed85 | 3197 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3198 | |
3199 | if (!ret_val) | |
3200 | phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) | |
3201 | ? e1000_rev_polarity_reversed | |
3202 | : e1000_rev_polarity_normal; | |
3203 | ||
3204 | return ret_val; | |
3205 | } | |
3206 | ||
3207 | /** | |
3208 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY | |
3209 | * @hw: pointer to the HW structure | |
3210 | * | |
eab50ffb | 3211 | * Calls the PHY setup function to force speed and duplex. |
a4f58f54 BA |
3212 | **/ |
3213 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |
3214 | { | |
3215 | struct e1000_phy_info *phy = &hw->phy; | |
3216 | s32 ret_val; | |
3217 | u16 phy_data; | |
3218 | bool link; | |
3219 | ||
482fed85 | 3220 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
a4f58f54 | 3221 | if (ret_val) |
5015e53a | 3222 | return ret_val; |
a4f58f54 BA |
3223 | |
3224 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
3225 | ||
482fed85 | 3226 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
a4f58f54 | 3227 | if (ret_val) |
5015e53a | 3228 | return ret_val; |
a4f58f54 | 3229 | |
a4f58f54 BA |
3230 | udelay(1); |
3231 | ||
3232 | if (phy->autoneg_wait_to_complete) { | |
3bb99fe2 | 3233 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
a4f58f54 | 3234 | |
3d3a1676 BA |
3235 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
3236 | 100000, &link); | |
a4f58f54 | 3237 | if (ret_val) |
5015e53a | 3238 | return ret_val; |
a4f58f54 BA |
3239 | |
3240 | if (!link) | |
3bb99fe2 | 3241 | e_dbg("Link taking longer than expected.\n"); |
a4f58f54 BA |
3242 | |
3243 | /* Try once more */ | |
3d3a1676 BA |
3244 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
3245 | 100000, &link); | |
a4f58f54 BA |
3246 | } |
3247 | ||
a4f58f54 BA |
3248 | return ret_val; |
3249 | } | |
3250 | ||
3251 | /** | |
3252 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information | |
3253 | * @hw: pointer to the HW structure | |
3254 | * | |
3255 | * Read PHY status to determine if link is up. If link is up, then | |
3256 | * set/determine 10base-T extended distance and polarity correction. Read | |
3257 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
3258 | * determine on the cable length, local and remote receiver. | |
3259 | **/ | |
3260 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |
3261 | { | |
3262 | struct e1000_phy_info *phy = &hw->phy; | |
3263 | s32 ret_val; | |
3264 | u16 data; | |
3265 | bool link; | |
3266 | ||
3267 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
3268 | if (ret_val) | |
5015e53a | 3269 | return ret_val; |
a4f58f54 BA |
3270 | |
3271 | if (!link) { | |
3bb99fe2 | 3272 | e_dbg("Phy info is only valid if link is up\n"); |
5015e53a | 3273 | return -E1000_ERR_CONFIG; |
a4f58f54 BA |
3274 | } |
3275 | ||
3276 | phy->polarity_correction = true; | |
3277 | ||
3278 | ret_val = e1000_check_polarity_82577(hw); | |
3279 | if (ret_val) | |
5015e53a | 3280 | return ret_val; |
a4f58f54 | 3281 | |
482fed85 | 3282 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 | 3283 | if (ret_val) |
5015e53a | 3284 | return ret_val; |
a4f58f54 | 3285 | |
04499ec4 | 3286 | phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); |
a4f58f54 BA |
3287 | |
3288 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == | |
3289 | I82577_PHY_STATUS2_SPEED_1000MBPS) { | |
3290 | ret_val = hw->phy.ops.get_cable_length(hw); | |
3291 | if (ret_val) | |
5015e53a | 3292 | return ret_val; |
a4f58f54 | 3293 | |
482fed85 | 3294 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); |
a4f58f54 | 3295 | if (ret_val) |
5015e53a | 3296 | return ret_val; |
a4f58f54 BA |
3297 | |
3298 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
3299 | ? e1000_1000t_rx_status_ok | |
3300 | : e1000_1000t_rx_status_not_ok; | |
3301 | ||
3302 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
3303 | ? e1000_1000t_rx_status_ok | |
3304 | : e1000_1000t_rx_status_not_ok; | |
3305 | } else { | |
3306 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
3307 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
3308 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
3309 | } | |
3310 | ||
5015e53a | 3311 | return 0; |
a4f58f54 BA |
3312 | } |
3313 | ||
3314 | /** | |
3315 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY | |
3316 | * @hw: pointer to the HW structure | |
3317 | * | |
3318 | * Reads the diagnostic status register and verifies result is valid before | |
3319 | * placing it in the phy_cable_length field. | |
3320 | **/ | |
3321 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |
3322 | { | |
3323 | struct e1000_phy_info *phy = &hw->phy; | |
3324 | s32 ret_val; | |
3325 | u16 phy_data, length; | |
3326 | ||
482fed85 | 3327 | ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
a4f58f54 | 3328 | if (ret_val) |
5015e53a | 3329 | return ret_val; |
a4f58f54 BA |
3330 | |
3331 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> | |
3332 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; | |
3333 | ||
3334 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
98086a95 | 3335 | ret_val = -E1000_ERR_PHY; |
a4f58f54 BA |
3336 | |
3337 | phy->cable_length = length; | |
3338 | ||
5015e53a | 3339 | return 0; |
a4f58f54 | 3340 | } |