[deliverable/linux.git] / drivers / net / ethernet / intel / fm10k / fm10k.h

/* Intel(R) Ethernet Switch Host Interface Driver
 * Copyright(c) 2013 - 2016 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 */

#ifndef _FM10K_H_
#define _FM10K_H_

#include <linux/types.h>
#include <linux/etherdevice.h>
#include <linux/cpumask.h>
#include <linux/rtnetlink.h>
#include <linux/if_vlan.h>
#include <linux/pci.h>

#include "fm10k_pf.h"
#include "fm10k_vf.h"

#define FM10K_MAX_JUMBO_FRAME_SIZE	15342	/* Maximum supported size 15K */

#define MAX_QUEUES	FM10K_MAX_QUEUES_PF

#define FM10K_MIN_RXD		 128
#define FM10K_MAX_RXD		4096
#define FM10K_DEFAULT_RXD	 256

#define FM10K_MIN_TXD		 128
#define FM10K_MAX_TXD		4096
#define FM10K_DEFAULT_TXD	 256
#define FM10K_DEFAULT_TX_WORK	 256

#define FM10K_RXBUFFER_256	  256
#define FM10K_RX_HDR_LEN	FM10K_RXBUFFER_256
#define FM10K_RXBUFFER_2048	 2048
#define FM10K_RX_BUFSZ		FM10K_RXBUFFER_2048

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define FM10K_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define FM10K_MAX_STATIONS	63
struct fm10k_l2_accel {
	int size;
	u16 count;
	u16 dglort;
	struct rcu_head rcu;
	struct net_device *macvlan[0];
};

enum fm10k_ring_state_t {
	__FM10K_TX_DETECT_HANG,
	__FM10K_HANG_CHECK_ARMED,
	__FM10K_TX_XPS_INIT_DONE,
};

#define check_for_tx_hang(ring) \
	test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
#define set_check_for_tx_hang(ring) \
	set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
#define clear_check_for_tx_hang(ring) \
	clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)

struct fm10k_tx_buffer {
	struct fm10k_tx_desc *next_to_watch;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	u16 tx_flags;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
};

struct fm10k_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	u32 page_offset;
};

struct fm10k_queue_stats {
	u64 packets;
	u64 bytes;
};

struct fm10k_tx_queue_stats {
	u64 restart_queue;
	u64 csum_err;
	u64 tx_busy;
	u64 tx_done_old;
	u64 csum_good;
};

struct fm10k_rx_queue_stats {
	u64 alloc_failed;
	u64 csum_err;
	u64 errors;
	u64 csum_good;
	u64 switch_errors;
	u64 drops;
	u64 pp_errors;
	u64 link_errors;
	u64 length_errors;
};

struct fm10k_ring {
	struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
	struct net_device *netdev;	/* netdev ring belongs to */
	struct device *dev;		/* device for DMA mapping */
	struct fm10k_l2_accel __rcu *l2_accel;	/* L2 acceleration list */
	void *desc;			/* descriptor ring memory */
	union {
		struct fm10k_tx_buffer *tx_buffer;
		struct fm10k_rx_buffer *rx_buffer;
	};
	u32 __iomem *tail;
	unsigned long state;
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */

	u8 queue_index;			/* needed for queue management */
	u8 reg_idx;			/* holds the special value that gets
					 * the hardware register offset
					 * associated with this ring, which is
					 * different for DCB and RSS modes
					 */
	u8 qos_pc;			/* priority class of queue */
	u16 vid;			/* default VLAN ID of queue */
	u16 count;			/* amount of descriptors */

	u16 next_to_alloc;
	u16 next_to_use;
	u16 next_to_clean;

	struct fm10k_queue_stats stats;
	struct u64_stats_sync syncp;
	union {
		/* Tx */
		struct fm10k_tx_queue_stats tx_stats;
		/* Rx */
		struct {
			struct fm10k_rx_queue_stats rx_stats;
			struct sk_buff *skb;
		};
	};
} ____cacheline_internodealigned_in_smp;

struct fm10k_ring_container {
	struct fm10k_ring *ring;	/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 work_limit;			/* total work allowed per interrupt */
	u16 itr;			/* interrupt throttle rate value */
	u8 itr_scale;			/* ITR adjustment based on PCI speed */
	u8 count;			/* total number of rings in vector */
};

#define FM10K_ITR_MAX		0x0FFF	/* maximum value for ITR */
#define FM10K_ITR_10K		100	/* 100us */
#define FM10K_ITR_20K		50	/* 50us */
#define FM10K_ITR_40K		25	/* 25us */
#define FM10K_ITR_ADAPTIVE	0x8000	/* adaptive interrupt moderation flag */

#define ITR_IS_ADAPTIVE(itr) (!!(itr & FM10K_ITR_ADAPTIVE))

#define FM10K_TX_ITR_DEFAULT	FM10K_ITR_40K
#define FM10K_RX_ITR_DEFAULT	FM10K_ITR_20K
#define FM10K_ITR_ENABLE	(FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)

static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
{
	return &ring->netdev->_tx[ring->queue_index];
}

/* iterator for handling rings in ring container */
#define fm10k_for_each_ring(pos, head) \
	for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)

#define MAX_Q_VECTORS 256
#define MIN_Q_VECTORS	1
enum fm10k_non_q_vectors {
	FM10K_MBX_VECTOR,
#define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
	NON_Q_VECTORS_PF
};

#define NON_Q_VECTORS(hw)	(((hw)->mac.type == fm10k_mac_pf) ? \
						NON_Q_VECTORS_PF : \
						NON_Q_VECTORS_VF)
#define MIN_MSIX_COUNT(hw)	(MIN_Q_VECTORS + NON_Q_VECTORS(hw))

struct fm10k_q_vector {
	struct fm10k_intfc *interface;
	u32 __iomem *itr;	/* pointer to ITR register for this vector */
	u16 v_idx;		/* index of q_vector within interface array */
	struct fm10k_ring_container rx, tx;

	struct napi_struct napi;
	cpumask_t affinity_mask;
	char name[IFNAMSIZ + 9];

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbg_q_vector;
#endif /* CONFIG_DEBUG_FS */
	struct rcu_head rcu;	/* to avoid race with update stats on free */

	/* for dynamic allocation of rings associated with this q_vector */
	struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
};

enum fm10k_ring_f_enum {
	RING_F_RSS,
	RING_F_QOS,
	RING_F_ARRAY_SIZE  /* must be last in enum set */
};

struct fm10k_ring_feature {
	u16 limit;	/* upper limit on feature indices */
	u16 indices;	/* current value of indices */
	u16 mask;	/* Mask used for feature to ring mapping */
	u16 offset;	/* offset to start of feature */
};

struct fm10k_iov_data {
	unsigned int		num_vfs;
	unsigned int		next_vf_mbx;
	struct rcu_head		rcu;
	struct fm10k_vf_info	vf_info[0];
};

struct fm10k_udp_port {
	struct list_head	list;
	sa_family_t		sa_family;
	__be16			port;
};

/* one work queue for entire driver */
extern struct workqueue_struct *fm10k_workqueue;

struct fm10k_intfc {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct net_device *netdev;
	struct fm10k_l2_accel *l2_accel; /* pointer to L2 acceleration list */
	struct pci_dev *pdev;
	unsigned long state;

	u32 flags;
#define FM10K_FLAG_RESET_REQUESTED		(u32)(BIT(0))
#define FM10K_FLAG_RSS_FIELD_IPV4_UDP		(u32)(BIT(1))
#define FM10K_FLAG_RSS_FIELD_IPV6_UDP		(u32)(BIT(2))
#define FM10K_FLAG_RX_TS_ENABLED		(u32)(BIT(3))
#define FM10K_FLAG_SWPRI_CONFIG			(u32)(BIT(4))
#define FM10K_FLAG_DEBUG_STATS			(u32)(BIT(5))
	int xcast_mode;

	/* Tx fast path data */
	int num_tx_queues;
	u16 tx_itr;

	/* Rx fast path data */
	int num_rx_queues;
	u16 rx_itr;

	/* TX */
	struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;

	u64 restart_queue;
	u64 tx_busy;
	u64 tx_csum_errors;
	u64 alloc_failed;
	u64 rx_csum_errors;

	u64 tx_bytes_nic;
	u64 tx_packets_nic;
	u64 rx_bytes_nic;
	u64 rx_packets_nic;
	u64 rx_drops_nic;
	u64 rx_overrun_pf;
	u64 rx_overrun_vf;

	/* Debug Statistics */
	u64 hw_sm_mbx_full;
	u64 hw_csum_tx_good;
	u64 hw_csum_rx_good;
	u64 rx_switch_errors;
	u64 rx_drops;
	u64 rx_pp_errors;
	u64 rx_link_errors;
	u64 rx_length_errors;

	u32 tx_timeout_count;

	/* RX */
	struct fm10k_ring *rx_ring[MAX_QUEUES];

	/* Queueing vectors */
	struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	int num_q_vectors;	/* current number of q_vectors for device */
	struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];

	/* SR-IOV information management structure */
	struct fm10k_iov_data *iov_data;

	struct fm10k_hw_stats stats;
	struct fm10k_hw hw;
	u32 __iomem *uc_addr;
	u32 __iomem *sw_addr;
	u16 msg_enable;
	u16 tx_ring_count;
	u16 rx_ring_count;
	struct timer_list service_timer;
	struct work_struct service_task;
	unsigned long next_stats_update;
	unsigned long next_tx_hang_check;
	unsigned long last_reset;
	unsigned long link_down_event;
	bool host_ready;
	bool lport_map_failed;

	u32 reta[FM10K_RETA_SIZE];
	u32 rssrk[FM10K_RSSRK_SIZE];

	/* UDP encapsulation port tracking information */
	struct list_head vxlan_port;
	struct list_head geneve_port;

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbg_intfc;
#endif /* CONFIG_DEBUG_FS */

#ifdef CONFIG_DCB
	u8 pfc_en;
#endif
	u8 rx_pause;

	/* GLORT resources in use by PF */
	u16 glort;
	u16 glort_count;

	/* VLAN ID for updating multicast/unicast lists */
	u16 vid;
};

enum fm10k_state_t {
	__FM10K_RESETTING,
	__FM10K_DOWN,
	__FM10K_SERVICE_SCHED,
	__FM10K_SERVICE_DISABLE,
	__FM10K_MBX_LOCK,
	__FM10K_LINK_DOWN,
	__FM10K_UPDATING_STATS,
};

static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
{
	/* busy loop if we cannot obtain the lock as some calls
	 * such as ndo_set_rx_mode may be made in atomic context
	 */
	while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
		udelay(20);
}

static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
{
	/* flush memory to make sure state is correct */
	smp_mb__before_atomic();
	clear_bit(__FM10K_MBX_LOCK, &interface->state);
}

static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
{
	return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
}

/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
					const u32 stat_err_bits)
{
	return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
}

/* fm10k_desc_unused - calculate if we have unused descriptors */
static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
{
	s16 unused = ring->next_to_clean - ring->next_to_use - 1;

	return likely(unused < 0) ? unused + ring->count : unused;
}

#define FM10K_TX_DESC(R, i)	\
	(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
#define FM10K_RX_DESC(R, i)	\
	 (&(((union fm10k_rx_desc *)((R)->desc))[i]))

#define FM10K_MAX_TXD_PWR	14
#define FM10K_MAX_DATA_PER_TXD	(1u << FM10K_MAX_TXD_PWR)

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
#define DESC_NEEDED	(MAX_SKB_FRAGS + 4)

enum fm10k_tx_flags {
	/* Tx offload flags */
	FM10K_TX_FLAGS_CSUM	= 0x01,
};

/* This structure is stored as little endian values as that is the native
 * format of the Rx descriptor.  The ordering of these fields is reversed
 * from the actual ftag header to allow for a single bswap to take care
 * of placing all of the values in network order
 */
union fm10k_ftag_info {
	__le64 ftag;
	struct {
		/* dglort and sglort combined into a single 32bit desc read */
		__le32 glort;
		/* upper 16 bits of VLAN are reserved 0 for swpri_type_user */
		__le32 vlan;
	} d;
	struct {
		__le16 dglort;
		__le16 sglort;
		__le16 vlan;
		__le16 swpri_type_user;
	} w;
};

struct fm10k_cb {
	union {
		__le64 tstamp;
		unsigned long ts_tx_timeout;
	};
	union fm10k_ftag_info fi;
};

#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)

/* main */
extern char fm10k_driver_name[];
extern const char fm10k_driver_version[];
int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
__be16 fm10k_tx_encap_offload(struct sk_buff *skb);
netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
				  struct fm10k_ring *tx_ring);
void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
u64 fm10k_get_tx_pending(struct fm10k_ring *ring, bool in_sw);
bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);

/* PCI */
void fm10k_mbx_free_irq(struct fm10k_intfc *);
int fm10k_mbx_request_irq(struct fm10k_intfc *);
void fm10k_qv_free_irq(struct fm10k_intfc *interface);
int fm10k_qv_request_irq(struct fm10k_intfc *interface);
int fm10k_register_pci_driver(void);
void fm10k_unregister_pci_driver(void);
void fm10k_up(struct fm10k_intfc *interface);
void fm10k_down(struct fm10k_intfc *interface);
void fm10k_update_stats(struct fm10k_intfc *interface);
void fm10k_service_event_schedule(struct fm10k_intfc *interface);
void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
#ifdef CONFIG_NET_POLL_CONTROLLER
void fm10k_netpoll(struct net_device *netdev);
#endif

/* Netdev */
struct net_device *fm10k_alloc_netdev(const struct fm10k_info *info);
int fm10k_setup_rx_resources(struct fm10k_ring *);
int fm10k_setup_tx_resources(struct fm10k_ring *);
void fm10k_free_rx_resources(struct fm10k_ring *);
void fm10k_free_tx_resources(struct fm10k_ring *);
void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
				      struct fm10k_tx_buffer *);
void fm10k_restore_rx_state(struct fm10k_intfc *);
void fm10k_reset_rx_state(struct fm10k_intfc *);
int fm10k_setup_tc(struct net_device *dev, u8 tc);
int fm10k_open(struct net_device *netdev);
int fm10k_close(struct net_device *netdev);

/* Ethtool */
void fm10k_set_ethtool_ops(struct net_device *dev);
void fm10k_write_reta(struct fm10k_intfc *interface, const u32 *indir);

/* IOV */
s32 fm10k_iov_event(struct fm10k_intfc *interface);
s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
void fm10k_iov_suspend(struct pci_dev *pdev);
int fm10k_iov_resume(struct pci_dev *pdev);
void fm10k_iov_disable(struct pci_dev *pdev);
int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
int fm10k_ndo_set_vf_mac(struct net_device *netdev, int vf_idx, u8 *mac);
int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
			  int vf_idx, u16 vid, u8 qos);
int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate,
			int unused);
int fm10k_ndo_get_vf_config(struct net_device *netdev,
			    int vf_idx, struct ifla_vf_info *ivi);

/* DebugFS */
#ifdef CONFIG_DEBUG_FS
void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
void fm10k_dbg_init(void);
void fm10k_dbg_exit(void);
#else
static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
static inline void fm10k_dbg_init(void) {}
static inline void fm10k_dbg_exit(void) {}
#endif /* CONFIG_DEBUG_FS */

/* DCB */
#ifdef CONFIG_DCB
void fm10k_dcbnl_set_ops(struct net_device *dev);
#else
static inline void fm10k_dcbnl_set_ops(struct net_device *dev) {}
#endif
#endif /* _FM10K_H_ */
Commit	Line	Data
86641094	1	/* Intel(R) Ethernet Switch Host Interface Driver
9de6a1a6	2	* Copyright(c) 2013 - 2016 Intel Corporation.
b3890e30 AD	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* The full GNU General Public License is included in this distribution in
	14	* the file called "COPYING".
	15	*
	16	* Contact Information:
	17	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	18	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	19	*/
	20
	21	#ifndef _FM10K_H_
	22	#define _FM10K_H_
	23
	24	#include <linux/types.h>
	25	#include <linux/etherdevice.h>
504b0fdf	26	#include <linux/cpumask.h>
b3890e30 AD	27	#include <linux/rtnetlink.h>
	28	#include <linux/if_vlan.h>
	29	#include <linux/pci.h>
	30
0e7b3644	31	#include "fm10k_pf.h"
5cb8db4a	32	#include "fm10k_vf.h"
0e7b3644	33
8c7ee6d2	34	#define FM10K_MAX_JUMBO_FRAME_SIZE 15342 /* Maximum supported size 15K */
0e7b3644	35
e27ef599 AD	36	#define MAX_QUEUES FM10K_MAX_QUEUES_PF
	37
	38	#define FM10K_MIN_RXD 128
	39	#define FM10K_MAX_RXD 4096
	40	#define FM10K_DEFAULT_RXD 256
	41
	42	#define FM10K_MIN_TXD 128
	43	#define FM10K_MAX_TXD 4096
	44	#define FM10K_DEFAULT_TXD 256
	45	#define FM10K_DEFAULT_TX_WORK 256
	46
	47	#define FM10K_RXBUFFER_256 256
e27ef599	48	#define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
fd333962 AD	49	#define FM10K_RXBUFFER_2048 2048
fd333962 AD	50	#define FM10K_RX_BUFSZ FM10K_RXBUFFER_2048
e27ef599 AD	51
	52	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	53	#define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	54
5cd5e2e9 AD	55	#define FM10K_MAX_STATIONS 63
	56	struct fm10k_l2_accel {
	57	int size;
	58	u16 count;
	59	u16 dglort;
	60	struct rcu_head rcu;
	61	struct net_device *macvlan[0];
	62	};
	63
e27ef599 AD	64	enum fm10k_ring_state_t {
	65	__FM10K_TX_DETECT_HANG,
	66	__FM10K_HANG_CHECK_ARMED,
504b0fdf	67	__FM10K_TX_XPS_INIT_DONE,
e27ef599 AD	68	};
	69
	70	#define check_for_tx_hang(ring) \
	71	test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	72	#define set_check_for_tx_hang(ring) \
	73	set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	74	#define clear_check_for_tx_hang(ring) \
	75	clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	76
	77	struct fm10k_tx_buffer {
	78	struct fm10k_tx_desc *next_to_watch;
	79	struct sk_buff *skb;
	80	unsigned int bytecount;
	81	u16 gso_segs;
	82	u16 tx_flags;
	83	DEFINE_DMA_UNMAP_ADDR(dma);
	84	DEFINE_DMA_UNMAP_LEN(len);
	85	};
	86
	87	struct fm10k_rx_buffer {
	88	dma_addr_t dma;
	89	struct page *page;
	90	u32 page_offset;
	91	};
	92
	93	struct fm10k_queue_stats {
	94	u64 packets;
	95	u64 bytes;
	96	};
	97
	98	struct fm10k_tx_queue_stats {
	99	u64 restart_queue;
	100	u64 csum_err;
	101	u64 tx_busy;
	102	u64 tx_done_old;
80043f3b	103	u64 csum_good;
e27ef599 AD	104	};
	105
	106	struct fm10k_rx_queue_stats {
	107	u64 alloc_failed;
	108	u64 csum_err;
	109	u64 errors;
80043f3b JK	110	u64 csum_good;
	111	u64 switch_errors;
	112	u64 drops;
	113	u64 pp_errors;
	114	u64 link_errors;
	115	u64 length_errors;
e27ef599 AD	116	};
	117
	118	struct fm10k_ring {
	119	struct fm10k_q_vector q_vector;/ backpointer to host q_vector */
	120	struct net_device netdev; / netdev ring belongs to */
	121	struct device dev; / device for DMA mapping */
5cd5e2e9	122	struct fm10k_l2_accel __rcu l2_accel; / L2 acceleration list */
e27ef599 AD	123	void desc; / descriptor ring memory */
	124	union {
	125	struct fm10k_tx_buffer *tx_buffer;
	126	struct fm10k_rx_buffer *rx_buffer;
	127	};
	128	u32 __iomem *tail;
	129	unsigned long state;
	130	dma_addr_t dma; /* phys. address of descriptor ring */
	131	unsigned int size; /* length in bytes */
	132
	133	u8 queue_index; /* needed for queue management */
	134	u8 reg_idx; /* holds the special value that gets
	135	* the hardware register offset
	136	* associated with this ring, which is
	137	* different for DCB and RSS modes
	138	*/
	139	u8 qos_pc; /* priority class of queue */
aa502b4a	140	u16 vid; /* default VLAN ID of queue */
e27ef599 AD	141	u16 count; /* amount of descriptors */
	142
	143	u16 next_to_alloc;
	144	u16 next_to_use;
	145	u16 next_to_clean;
	146
	147	struct fm10k_queue_stats stats;
	148	struct u64_stats_sync syncp;
	149	union {
	150	/* Tx */
	151	struct fm10k_tx_queue_stats tx_stats;
	152	/* Rx */
	153	struct {
	154	struct fm10k_rx_queue_stats rx_stats;
	155	struct sk_buff *skb;
	156	};
	157	};
	158	} ____cacheline_internodealigned_in_smp;
	159
18283cad	160	struct fm10k_ring_container {
e27ef599	161	struct fm10k_ring ring; / pointer to linked list of rings */
18283cad AD	162	unsigned int total_bytes; /* total bytes processed this int */
	163	unsigned int total_packets; /* total packets processed this int */
	164	u16 work_limit; /* total work allowed per interrupt */
	165	u16 itr; /* interrupt throttle rate value */
3d02b3df	166	u8 itr_scale; /* ITR adjustment based on PCI speed */
18283cad AD	167	u8 count; /* total number of rings in vector */
	168	};
	169
	170	#define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */
	171	#define FM10K_ITR_10K 100 /* 100us */
	172	#define FM10K_ITR_20K 50 /* 50us */
dbf42848	173	#define FM10K_ITR_40K 25 /* 25us */
18283cad AD	174	#define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */
18283cad AD	175
584373f5 JK	176	#define ITR_IS_ADAPTIVE(itr) (!!(itr & FM10K_ITR_ADAPTIVE))
584373f5 JK	177
dbf42848	178	#define FM10K_TX_ITR_DEFAULT FM10K_ITR_40K
436ea956	179	#define FM10K_RX_ITR_DEFAULT FM10K_ITR_20K
18283cad AD	180	#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK \| FM10K_ITR_MASK_CLEAR)
18283cad AD	181
e27ef599 AD	182	static inline struct netdev_queue txring_txq(const struct fm10k_ring ring)
	183	{
	184	return &ring->netdev->_tx[ring->queue_index];
	185	}
	186
	187	/* iterator for handling rings in ring container */
	188	#define fm10k_for_each_ring(pos, head) \
	189	for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
	190
18283cad AD	191	#define MAX_Q_VECTORS 256
	192	#define MIN_Q_VECTORS 1
	193	enum fm10k_non_q_vectors {
	194	FM10K_MBX_VECTOR,
5cb8db4a	195	#define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
18283cad AD	196	NON_Q_VECTORS_PF
	197	};
	198
	199	#define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \
	200	NON_Q_VECTORS_PF : \
5cb8db4a	201	NON_Q_VECTORS_VF)
18283cad AD	202	#define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw))
	203
	204	struct fm10k_q_vector {
	205	struct fm10k_intfc *interface;
	206	u32 __iomem itr; / pointer to ITR register for this vector */
	207	u16 v_idx; /* index of q_vector within interface array */
	208	struct fm10k_ring_container rx, tx;
	209
	210	struct napi_struct napi;
504b0fdf	211	cpumask_t affinity_mask;
18283cad AD	212	char name[IFNAMSIZ + 9];
18283cad AD	213
7461fd91 AD	214	#ifdef CONFIG_DEBUG_FS
	215	struct dentry *dbg_q_vector;
	216	#endif /* CONFIG_DEBUG_FS */
18283cad	217	struct rcu_head rcu; /* to avoid race with update stats on free */
e27ef599 AD	218
	219	/* for dynamic allocation of rings associated with this q_vector */
	220	struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
18283cad AD	221	};
18283cad AD	222
0e7b3644 AD	223	enum fm10k_ring_f_enum {
	224	RING_F_RSS,
	225	RING_F_QOS,
	226	RING_F_ARRAY_SIZE /* must be last in enum set */
	227	};
	228
	229	struct fm10k_ring_feature {
	230	u16 limit; /* upper limit on feature indices */
	231	u16 indices; /* current value of indices */
	232	u16 mask; /* Mask used for feature to ring mapping */
	233	u16 offset; /* offset to start of feature */
	234	};
	235
883a9ccb AD	236	struct fm10k_iov_data {
	237	unsigned int num_vfs;
	238	unsigned int next_vf_mbx;
	239	struct rcu_head rcu;
	240	struct fm10k_vf_info vf_info[0];
	241	};
	242
f92e0e48	243	struct fm10k_udp_port {
0e7b3644 AD	244	struct list_head list;
	245	sa_family_t sa_family;
	246	__be16 port;
	247	};
04a5aefb	248
b382bb1b JK	249	/* one work queue for entire driver */
	250	extern struct workqueue_struct *fm10k_workqueue;
	251
04a5aefb	252	struct fm10k_intfc {
0e7b3644 AD	253	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0e7b3644 AD	254	struct net_device *netdev;
5cd5e2e9	255	struct fm10k_l2_accel l2_accel; / pointer to L2 acceleration list */
04a5aefb	256	struct pci_dev *pdev;
0e7b3644 AD	257	unsigned long state;
	258
	259	u32 flags;
fcdb0a99 BA	260	#define FM10K_FLAG_RESET_REQUESTED (u32)(BIT(0))
	261	#define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(BIT(1))
	262	#define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(BIT(2))
	263	#define FM10K_FLAG_RX_TS_ENABLED (u32)(BIT(3))
	264	#define FM10K_FLAG_SWPRI_CONFIG (u32)(BIT(4))
	265	#define FM10K_FLAG_DEBUG_STATS (u32)(BIT(5))
0e7b3644 AD	266	int xcast_mode;
0e7b3644 AD	267
18283cad AD	268	/* Tx fast path data */
	269	int num_tx_queues;
	270	u16 tx_itr;
	271
	272	/* Rx fast path data */
	273	int num_rx_queues;
	274	u16 rx_itr;
	275
e27ef599 AD	276	/* TX */
	277	struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
	278
b7d8514c AD	279	u64 restart_queue;
	280	u64 tx_busy;
	281	u64 tx_csum_errors;
	282	u64 alloc_failed;
	283	u64 rx_csum_errors;
b7d8514c AD	284
	285	u64 tx_bytes_nic;
	286	u64 tx_packets_nic;
	287	u64 rx_bytes_nic;
	288	u64 rx_packets_nic;
	289	u64 rx_drops_nic;
0e7b3644 AD	290	u64 rx_overrun_pf;
0e7b3644 AD	291	u64 rx_overrun_vf;
80043f3b JK	292
	293	/* Debug Statistics */
	294	u64 hw_sm_mbx_full;
	295	u64 hw_csum_tx_good;
	296	u64 hw_csum_rx_good;
	297	u64 rx_switch_errors;
	298	u64 rx_drops;
	299	u64 rx_pp_errors;
	300	u64 rx_link_errors;
	301	u64 rx_length_errors;
	302
b7d8514c	303	u32 tx_timeout_count;
04a5aefb	304
e27ef599 AD	305	/* RX */
	306	struct fm10k_ring *rx_ring[MAX_QUEUES];
	307
18283cad AD	308	/* Queueing vectors */
	309	struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
	310	struct msix_entry *msix_entries;
	311	int num_q_vectors; /* current number of q_vectors for device */
0e7b3644 AD	312	struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];
0e7b3644 AD	313
883a9ccb AD	314	/* SR-IOV information management structure */
	315	struct fm10k_iov_data *iov_data;
	316
0e7b3644	317	struct fm10k_hw_stats stats;
04a5aefb AD	318	struct fm10k_hw hw;
04a5aefb AD	319	u32 __iomem *uc_addr;
a211e013	320	u32 __iomem *sw_addr;
0e7b3644	321	u16 msg_enable;
18283cad AD	322	u16 tx_ring_count;
18283cad AD	323	u16 rx_ring_count;
b7d8514c AD	324	struct timer_list service_timer;
	325	struct work_struct service_task;
	326	unsigned long next_stats_update;
	327	unsigned long next_tx_hang_check;
	328	unsigned long last_reset;
	329	unsigned long link_down_event;
	330	bool host_ready;
a7a7783a	331	bool lport_map_failed;
0e7b3644 AD	332
	333	u32 reta[FM10K_RETA_SIZE];
	334	u32 rssrk[FM10K_RSSRK_SIZE];
	335
f92e0e48	336	/* UDP encapsulation port tracking information */
0e7b3644	337	struct list_head vxlan_port;
1ad78292	338	struct list_head geneve_port;
0e7b3644	339
7461fd91 AD	340	#ifdef CONFIG_DEBUG_FS
7461fd91 AD	341	struct dentry *dbg_intfc;
7461fd91	342	#endif /* CONFIG_DEBUG_FS */
a211e013	343
9f801abc	344	#ifdef CONFIG_DCB
0e7b3644 AD	345	u8 pfc_en;
	346	#endif
	347	u8 rx_pause;
	348
	349	/* GLORT resources in use by PF */
	350	u16 glort;
	351	u16 glort_count;
	352
	353	/* VLAN ID for updating multicast/unicast lists */
	354	u16 vid;
	355	};
	356
	357	enum fm10k_state_t {
	358	__FM10K_RESETTING,
	359	__FM10K_DOWN,
b7d8514c AD	360	__FM10K_SERVICE_SCHED,
b7d8514c AD	361	__FM10K_SERVICE_DISABLE,
0e7b3644 AD	362	__FM10K_MBX_LOCK,
0e7b3644 AD	363	__FM10K_LINK_DOWN,
9d73edee	364	__FM10K_UPDATING_STATS,
04a5aefb	365	};
b3890e30	366
0e7b3644 AD	367	static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
	368	{
	369	/* busy loop if we cannot obtain the lock as some calls
	370	* such as ndo_set_rx_mode may be made in atomic context
	371	*/
	372	while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
	373	udelay(20);
	374	}
	375
	376	static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
	377	{
	378	/* flush memory to make sure state is correct */
	379	smp_mb__before_atomic();
	380	clear_bit(__FM10K_MBX_LOCK, &interface->state);
	381	}
	382
	383	static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
	384	{
	385	return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
	386	}
	387
e27ef599 AD	388	/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
	389	static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
	390	const u32 stat_err_bits)
	391	{
	392	return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
	393	}
	394
	395	/* fm10k_desc_unused - calculate if we have unused descriptors */
	396	static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
	397	{
	398	s16 unused = ring->next_to_clean - ring->next_to_use - 1;
	399
	400	return likely(unused < 0) ? unused + ring->count : unused;
	401	}
	402
	403	#define FM10K_TX_DESC(R, i) \
	404	(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
	405	#define FM10K_RX_DESC(R, i) \
	406	(&(((union fm10k_rx_desc *)((R)->desc))[i]))
	407
	408	#define FM10K_MAX_TXD_PWR 14
124579de	409	#define FM10K_MAX_DATA_PER_TXD (1u << FM10K_MAX_TXD_PWR)
e27ef599 AD	410
	411	/* Tx Descriptors needed, worst case */
	412	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
	413	#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
	414
	415	enum fm10k_tx_flags {
	416	/* Tx offload flags */
	417	FM10K_TX_FLAGS_CSUM = 0x01,
	418	};
	419
	420	/* This structure is stored as little endian values as that is the native
	421	* format of the Rx descriptor. The ordering of these fields is reversed
	422	* from the actual ftag header to allow for a single bswap to take care
	423	* of placing all of the values in network order
	424	*/
	425	union fm10k_ftag_info {
	426	__le64 ftag;
	427	struct {
	428	/* dglort and sglort combined into a single 32bit desc read */
	429	__le32 glort;
aa502b4a	430	/* upper 16 bits of VLAN are reserved 0 for swpri_type_user */
e27ef599 AD	431	__le32 vlan;
	432	} d;
	433	struct {
	434	__le16 dglort;
	435	__le16 sglort;
	436	__le16 vlan;
	437	__le16 swpri_type_user;
	438	} w;
	439	};
	440
	441	struct fm10k_cb {
a211e013 AD	442	union {
	443	__le64 tstamp;
	444	unsigned long ts_tx_timeout;
	445	};
e27ef599 AD	446	union fm10k_ftag_info fi;
	447	};
	448
	449	#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
	450
b3890e30 AD	451	/* main */
	452	extern char fm10k_driver_name[];
	453	extern const char fm10k_driver_version[];
18283cad AD	454	int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
18283cad AD	455	void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
5bf33dc6	456	__be16 fm10k_tx_encap_offload(struct sk_buff *skb);
b101c962 AD	457	netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
	458	struct fm10k_ring *tx_ring);
	459	void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
5b9e4432	460	u64 fm10k_get_tx_pending(struct fm10k_ring *ring, bool in_sw);
b101c962 AD	461	bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
b101c962 AD	462	void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);
b3890e30 AD	463
b3890e30 AD	464	/* PCI */
18283cad AD	465	void fm10k_mbx_free_irq(struct fm10k_intfc *);
	466	int fm10k_mbx_request_irq(struct fm10k_intfc *);
	467	void fm10k_qv_free_irq(struct fm10k_intfc *interface);
	468	int fm10k_qv_request_irq(struct fm10k_intfc *interface);
b3890e30 AD	469	int fm10k_register_pci_driver(void);
b3890e30 AD	470	void fm10k_unregister_pci_driver(void);
504c5eac AD	471	void fm10k_up(struct fm10k_intfc *interface);
504c5eac AD	472	void fm10k_down(struct fm10k_intfc *interface);
b7d8514c AD	473	void fm10k_update_stats(struct fm10k_intfc *interface);
	474	void fm10k_service_event_schedule(struct fm10k_intfc *interface);
	475	void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
8b4a98c7 JK	476	#ifdef CONFIG_NET_POLL_CONTROLLER
	477	void fm10k_netpoll(struct net_device *netdev);
	478	#endif
0e7b3644 AD	479
0e7b3644 AD	480	/* Netdev */
e0244903	481	struct net_device fm10k_alloc_netdev(const struct fm10k_info info);
3abaae42 AD	482	int fm10k_setup_rx_resources(struct fm10k_ring *);
	483	int fm10k_setup_tx_resources(struct fm10k_ring *);
	484	void fm10k_free_rx_resources(struct fm10k_ring *);
	485	void fm10k_free_tx_resources(struct fm10k_ring *);
	486	void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
	487	void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
	488	void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
	489	struct fm10k_tx_buffer *);
8f5e20d4 AD	490	void fm10k_restore_rx_state(struct fm10k_intfc *);
8f5e20d4 AD	491	void fm10k_reset_rx_state(struct fm10k_intfc *);
aa3ac822	492	int fm10k_setup_tc(struct net_device *dev, u8 tc);
504c5eac AD	493	int fm10k_open(struct net_device *netdev);
504c5eac AD	494	int fm10k_close(struct net_device *netdev);
82dd0f7e AD	495
	496	/* Ethtool */
	497	void fm10k_set_ethtool_ops(struct net_device *dev);
0ea7fae4	498	void fm10k_write_reta(struct fm10k_intfc interface, const u32 indir);
883a9ccb AD	499
	500	/* IOV */
	501	s32 fm10k_iov_event(struct fm10k_intfc *interface);
	502	s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
	503	void fm10k_iov_suspend(struct pci_dev *pdev);
	504	int fm10k_iov_resume(struct pci_dev *pdev);
	505	void fm10k_iov_disable(struct pci_dev *pdev);
	506	int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
	507	s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
	508	int fm10k_ndo_set_vf_mac(struct net_device netdev, int vf_idx, u8 mac);
	509	int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
	510	int vf_idx, u16 vid, u8 qos);
	511	int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate,
	512	int unused);
	513	int fm10k_ndo_get_vf_config(struct net_device *netdev,
	514	int vf_idx, struct ifla_vf_info *ivi);
9f801abc	515
7461fd91 AD	516	/* DebugFS */
	517	#ifdef CONFIG_DEBUG_FS
	518	void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
	519	void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
	520	void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
	521	void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
	522	void fm10k_dbg_init(void);
	523	void fm10k_dbg_exit(void);
	524	#else
	525	static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
	526	static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
	527	static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
	528	static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
	529	static inline void fm10k_dbg_init(void) {}
	530	static inline void fm10k_dbg_exit(void) {}
	531	#endif /* CONFIG_DEBUG_FS */
	532
9f801abc	533	/* DCB */
5682366c	534	#ifdef CONFIG_DCB
9f801abc	535	void fm10k_dcbnl_set_ops(struct net_device *dev);
5682366c JK	536	#else
	537	static inline void fm10k_dcbnl_set_ops(struct net_device *dev) {}
	538	#endif
b3890e30	539	#endif /* _FM10K_H_ */