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i40e: add VEB stat control and remove L2 cloud filter
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
67be6eb2 4 * Copyright(c) 2013 - 2016 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e 46 case I40E_DEV_ID_QEMU:
ab60085e
SN		 47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
ab60085e
SN		 49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
5960d33f 52 case I40E_DEV_ID_10G_BASE_T:
bc5166b9 53 case I40E_DEV_ID_10G_BASE_T4:
ae24b409 54 case I40E_DEV_ID_20G_KR2:
48a3b512 55 case I40E_DEV_ID_20G_KR2_A:
56a62fc8
JB		 56 hw->mac.type = I40E_MAC_XL710;
57 break;
35dae51d
ASJ		 58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
87e6c1d7
ASJ		 60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 hw->mac.type = I40E_MAC_X722;
64 break;
56a62fc8
JB		 65 default:
66 hw->mac.type = I40E_MAC_GENERIC;
67 break;
68 }
69 } else {
70 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
71 }
72
73 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw->mac.type, status);
75 return status;
76}
77
f1c7e72e
SN		 78/**
79 * i40e_aq_str - convert AQ err code to a string
80 * @hw: pointer to the HW structure
81 * @aq_err: the AQ error code to convert
82 **/
4e68adfe 83const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
f1c7e72e
SN		 84{
85 switch (aq_err) {
86 case I40E_AQ_RC_OK:
87 return "OK";
88 case I40E_AQ_RC_EPERM:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR:
95 return "I40E_AQ_RC_EINTR";
96 case I40E_AQ_RC_EIO:
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG:
131 return "I40E_AQ_RC_EFBIG";
132 }
133
134 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
135 return hw->err_str;
136}
137
138/**
139 * i40e_stat_str - convert status err code to a string
140 * @hw: pointer to the HW structure
141 * @stat_err: the status error code to convert
142 **/
4e68adfe 143const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
f1c7e72e
SN		 144{
145 switch (stat_err) {
146 case 0:
147 return "OK";
148 case I40E_ERR_NVM:
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM:
151 return "I40E_ERR_NVM_CHECKSUM";
152 case I40E_ERR_PHY:
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG:
155 return "I40E_ERR_CONFIG";
156 case I40E_ERR_PARAM:
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
278 }
279
280 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
281 return hw->err_str;
282}
283
56a62fc8
JB		 284/**
285 * i40e_debug_aq
286 * @hw: debug mask related to admin queue
98d44381
JK		 287 * @mask: debug mask
288 * @desc: pointer to admin queue descriptor
56a62fc8 289 * @buffer: pointer to command buffer
f905dd62 290 * @buf_len: max length of buffer
56a62fc8
JB		 291 *
292 * Dumps debug log about adminq command with descriptor contents.
293 **/
294void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 295 void *buffer, u16 buf_len)
56a62fc8
JB		 296{
297 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 298 u16 len = le16_to_cpu(aq_desc->datalen);
37a2973a
SN		 299 u8 *buf = (u8 *)buffer;
300 u16 i = 0;
56a62fc8
JB		 301
302 if ((!(mask & hw->debug_mask)) || (desc == NULL))
303 return;
304
305 i40e_debug(hw, mask,
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
f1abd7db
PSJ		 307 le16_to_cpu(aq_desc->opcode),
308 le16_to_cpu(aq_desc->flags),
309 le16_to_cpu(aq_desc->datalen),
310 le16_to_cpu(aq_desc->retval));
56a62fc8 311 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 312 le32_to_cpu(aq_desc->cookie_high),
313 le32_to_cpu(aq_desc->cookie_low));
56a62fc8 314 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 315 le32_to_cpu(aq_desc->params.internal.param0),
316 le32_to_cpu(aq_desc->params.internal.param1));
56a62fc8 317 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 318 le32_to_cpu(aq_desc->params.external.addr_high),
319 le32_to_cpu(aq_desc->params.external.addr_low));
56a62fc8
JB		 320
321 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
56a62fc8 322 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 323 if (buf_len < len)
324 len = buf_len;
37a2973a
SN		 325 /* write the full 16-byte chunks */
326 for (i = 0; i < (len - 16); i += 16)
a3524e95 327 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
37a2973a 328 /* write whatever's left over without overrunning the buffer */
a3524e95
AS		 329 if (i < len)
330 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
331 i, len - i, buf + i);
56a62fc8
JB		 332 }
333}
334
e1860d8f
ASJ		 335/**
336 * i40e_check_asq_alive
337 * @hw: pointer to the hw struct
338 *
339 * Returns true if Queue is enabled else false.
340 **/
341bool i40e_check_asq_alive(struct i40e_hw *hw)
342{
8b833b4f
KS		 343 if (hw->aq.asq.len)
344 return !!(rd32(hw, hw->aq.asq.len) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK);
346 else
347 return false;
e1860d8f
ASJ		 348}
349
350/**
351 * i40e_aq_queue_shutdown
352 * @hw: pointer to the hw struct
353 * @unloading: is the driver unloading itself
354 *
355 * Tell the Firmware that we're shutting down the AdminQ and whether
356 * or not the driver is unloading as well.
357 **/
358i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
359 bool unloading)
360{
361 struct i40e_aq_desc desc;
362 struct i40e_aqc_queue_shutdown *cmd =
363 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
364 i40e_status status;
365
366 i40e_fill_default_direct_cmd_desc(&desc,
367 i40e_aqc_opc_queue_shutdown);
368
369 if (unloading)
370 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
371 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
372
373 return status;
374}
375
e50c8d6d
ASJ		 376/**
377 * i40e_aq_get_set_rss_lut
378 * @hw: pointer to the hardware structure
379 * @vsi_id: vsi fw index
380 * @pf_lut: for PF table set true, for VSI table set false
381 * @lut: pointer to the lut buffer provided by the caller
382 * @lut_size: size of the lut buffer
383 * @set: set true to set the table, false to get the table
384 *
385 * Internal function to get or set RSS look up table
386 **/
387static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
388 u16 vsi_id, bool pf_lut,
389 u8 *lut, u16 lut_size,
390 bool set)
391{
392 i40e_status status;
393 struct i40e_aq_desc desc;
394 struct i40e_aqc_get_set_rss_lut *cmd_resp =
395 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
396
397 if (set)
398 i40e_fill_default_direct_cmd_desc(&desc,
399 i40e_aqc_opc_set_rss_lut);
400 else
401 i40e_fill_default_direct_cmd_desc(&desc,
402 i40e_aqc_opc_get_rss_lut);
403
404 /* Indirect command */
405 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
406 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
407
408 cmd_resp->vsi_id =
409 cpu_to_le16((u16)((vsi_id <<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
412 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
413
414 if (pf_lut)
415 cmd_resp->flags |= cpu_to_le16((u16)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
419 else
420 cmd_resp->flags |= cpu_to_le16((u16)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
424
e50c8d6d
ASJ		 425 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
426
427 return status;
428}
429
430/**
431 * i40e_aq_get_rss_lut
432 * @hw: pointer to the hardware structure
433 * @vsi_id: vsi fw index
434 * @pf_lut: for PF table set true, for VSI table set false
435 * @lut: pointer to the lut buffer provided by the caller
436 * @lut_size: size of the lut buffer
437 *
438 * get the RSS lookup table, PF or VSI type
439 **/
440i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
441 bool pf_lut, u8 *lut, u16 lut_size)
442{
443 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
444 false);
445}
446
447/**
448 * i40e_aq_set_rss_lut
449 * @hw: pointer to the hardware structure
450 * @vsi_id: vsi fw index
451 * @pf_lut: for PF table set true, for VSI table set false
452 * @lut: pointer to the lut buffer provided by the caller
453 * @lut_size: size of the lut buffer
454 *
455 * set the RSS lookup table, PF or VSI type
456 **/
457i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
458 bool pf_lut, u8 *lut, u16 lut_size)
459{
460 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
461}
462
463/**
464 * i40e_aq_get_set_rss_key
465 * @hw: pointer to the hw struct
466 * @vsi_id: vsi fw index
467 * @key: pointer to key info struct
468 * @set: set true to set the key, false to get the key
469 *
470 * get the RSS key per VSI
471 **/
472static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
473 u16 vsi_id,
474 struct i40e_aqc_get_set_rss_key_data *key,
475 bool set)
476{
477 i40e_status status;
478 struct i40e_aq_desc desc;
479 struct i40e_aqc_get_set_rss_key *cmd_resp =
480 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
481 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
482
483 if (set)
484 i40e_fill_default_direct_cmd_desc(&desc,
485 i40e_aqc_opc_set_rss_key);
486 else
487 i40e_fill_default_direct_cmd_desc(&desc,
488 i40e_aqc_opc_get_rss_key);
489
490 /* Indirect command */
491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
493
494 cmd_resp->vsi_id =
495 cpu_to_le16((u16)((vsi_id <<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
498 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
e50c8d6d
ASJ		 499
500 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
501
502 return status;
503}
504
505/**
506 * i40e_aq_get_rss_key
507 * @hw: pointer to the hw struct
508 * @vsi_id: vsi fw index
509 * @key: pointer to key info struct
510 *
511 **/
512i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
513 u16 vsi_id,
514 struct i40e_aqc_get_set_rss_key_data *key)
515{
516 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
517}
518
519/**
520 * i40e_aq_set_rss_key
521 * @hw: pointer to the hw struct
522 * @vsi_id: vsi fw index
523 * @key: pointer to key info struct
524 *
525 * set the RSS key per VSI
526 **/
527i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
528 u16 vsi_id,
529 struct i40e_aqc_get_set_rss_key_data *key)
530{
531 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
532}
533
206812b5
JB		 534/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
535 * hardware to a bit-field that can be used by SW to more easily determine the
536 * packet type.
537 *
538 * Macros are used to shorten the table lines and make this table human
539 * readable.
540 *
541 * We store the PTYPE in the top byte of the bit field - this is just so that
542 * we can check that the table doesn't have a row missing, as the index into
543 * the table should be the PTYPE.
544 *
545 * Typical work flow:
546 *
547 * IF NOT i40e_ptype_lookup[ptype].known
548 * THEN
549 * Packet is unknown
550 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
551 * Use the rest of the fields to look at the tunnels, inner protocols, etc
552 * ELSE
553 * Use the enum i40e_rx_l2_ptype to decode the packet type
554 * ENDIF
555 */
556
557/* macro to make the table lines short */
558#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
559 { PTYPE, \
560 1, \
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
569
570#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
572
573/* shorter macros makes the table fit but are terse */
574#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
577
578/* Lookup table mapping the HW PTYPE to the bit field for decoding */
579struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
580 /* L2 Packet types */
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
584 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
593 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603
604 /* Non Tunneled IPv4 */
605 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
610 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
611 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
612
613 /* IPv4 --> IPv4 */
614 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
621
622 /* IPv4 --> IPv6 */
623 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
630
631 /* IPv4 --> GRE/NAT */
632 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
633
634 /* IPv4 --> GRE/NAT --> IPv4 */
635 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
642
643 /* IPv4 --> GRE/NAT --> IPv6 */
644 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
651
652 /* IPv4 --> GRE/NAT --> MAC */
653 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
654
655 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
656 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
663
664 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
665 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
672
673 /* IPv4 --> GRE/NAT --> MAC/VLAN */
674 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
675
676 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
677 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
684
685 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
686 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
693
694 /* Non Tunneled IPv6 */
695 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
696 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
697 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
700 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
701 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
702
703 /* IPv6 --> IPv4 */
704 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
711
712 /* IPv6 --> IPv6 */
713 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
720
721 /* IPv6 --> GRE/NAT */
722 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
723
724 /* IPv6 --> GRE/NAT -> IPv4 */
725 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
732
733 /* IPv6 --> GRE/NAT -> IPv6 */
734 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
741
742 /* IPv6 --> GRE/NAT -> MAC */
743 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
744
745 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
746 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
753
754 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
755 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
762
763 /* IPv6 --> GRE/NAT -> MAC/VLAN */
764 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
765
766 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
767 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
774
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
776 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
783
784 /* unused entries */
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
791
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
802
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
813
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
824
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
835
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
846
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
857
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
868
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
879
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
890
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
897};
898
56a62fc8
JB		 899/**
900 * i40e_init_shared_code - Initialize the shared code
901 * @hw: pointer to hardware structure
902 *
903 * This assigns the MAC type and PHY code and inits the NVM.
904 * Does not touch the hardware. This function must be called prior to any
905 * other function in the shared code. The i40e_hw structure should be
906 * memset to 0 prior to calling this function. The following fields in
907 * hw structure should be filled in prior to calling this function:
908 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
909 * subsystem_vendor_id, and revision_id
910 **/
911i40e_status i40e_init_shared_code(struct i40e_hw *hw)
912{
913 i40e_status status = 0;
5fb11d76 914 u32 port, ari, func_rid;
56a62fc8 915
56a62fc8
JB		 916 i40e_set_mac_type(hw);
917
918 switch (hw->mac.type) {
919 case I40E_MAC_XL710:
87e6c1d7 920 case I40E_MAC_X722:
56a62fc8
JB		 921 break;
922 default:
923 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 924 }
925
af89d26c
SN		 926 hw->phy.get_link_info = true;
927
5fb11d76
SN		 928 /* Determine port number and PF number*/
929 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
931 hw->port = (u8)port;
932 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
934 func_rid = rd32(hw, I40E_PF_FUNC_RID);
935 if (ari)
936 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 937 else
5fb11d76 938 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 939
07f89be8
AS		 940 if (hw->mac.type == I40E_MAC_X722)
941 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
942
56a62fc8
JB		 943 status = i40e_init_nvm(hw);
944 return status;
945}
946
947/**
948 * i40e_aq_mac_address_read - Retrieve the MAC addresses
949 * @hw: pointer to the hw struct
950 * @flags: a return indicator of what addresses were added to the addr store
951 * @addrs: the requestor's mac addr store
952 * @cmd_details: pointer to command details structure or NULL
953 **/
954static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
955 u16 *flags,
956 struct i40e_aqc_mac_address_read_data *addrs,
957 struct i40e_asq_cmd_details *cmd_details)
958{
959 struct i40e_aq_desc desc;
960 struct i40e_aqc_mac_address_read *cmd_data =
961 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
962 i40e_status status;
963
964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
965 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
966
967 status = i40e_asq_send_command(hw, &desc, addrs,
968 sizeof(*addrs), cmd_details);
969 *flags = le16_to_cpu(cmd_data->command_flags);
970
971 return status;
972}
973
974/**
975 * i40e_aq_mac_address_write - Change the MAC addresses
976 * @hw: pointer to the hw struct
977 * @flags: indicates which MAC to be written
978 * @mac_addr: address to write
979 * @cmd_details: pointer to command details structure or NULL
980 **/
981i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
982 u16 flags, u8 *mac_addr,
983 struct i40e_asq_cmd_details *cmd_details)
984{
985 struct i40e_aq_desc desc;
986 struct i40e_aqc_mac_address_write *cmd_data =
987 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
988 i40e_status status;
989
990 i40e_fill_default_direct_cmd_desc(&desc,
991 i40e_aqc_opc_mac_address_write);
992 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 993 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
994 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
995 ((u32)mac_addr[3] << 16) |
996 ((u32)mac_addr[4] << 8) |
997 mac_addr[5]);
56a62fc8
JB		 998
999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1000
1001 return status;
1002}
1003
1004/**
1005 * i40e_get_mac_addr - get MAC address
1006 * @hw: pointer to the HW structure
1007 * @mac_addr: pointer to MAC address
1008 *
1009 * Reads the adapter's MAC address from register
1010 **/
1011i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1012{
1013 struct i40e_aqc_mac_address_read_data addrs;
1014 i40e_status status;
1015 u16 flags = 0;
1016
1017 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1018
1019 if (flags & I40E_AQC_LAN_ADDR_VALID)
6995b36c 1020 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
56a62fc8
JB		 1021
1022 return status;
1023}
1024
1f224ad2
NP		 1025/**
1026 * i40e_get_port_mac_addr - get Port MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to Port MAC address
1029 *
1030 * Reads the adapter's Port MAC address
1031 **/
1032i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1033{
1034 struct i40e_aqc_mac_address_read_data addrs;
1035 i40e_status status;
1036 u16 flags = 0;
1037
1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1039 if (status)
1040 return status;
1041
1042 if (flags & I40E_AQC_PORT_ADDR_VALID)
6995b36c 1043 ether_addr_copy(mac_addr, addrs.port_mac);
1f224ad2
NP		 1044 else
1045 status = I40E_ERR_INVALID_MAC_ADDR;
1046
1047 return status;
1048}
1049
351499ab
MJ		 1050/**
1051 * i40e_pre_tx_queue_cfg - pre tx queue configure
1052 * @hw: pointer to the HW structure
b40c82e6 1053 * @queue: target PF queue index
351499ab
MJ		 1054 * @enable: state change request
1055 *
1056 * Handles hw requirement to indicate intention to enable
1057 * or disable target queue.
1058 **/
1059void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1060{
dfb699f9 1061 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 1062 u32 reg_block = 0;
dfb699f9 1063 u32 reg_val;
351499ab 1064
24a768cf 1065 if (abs_queue_idx >= 128) {
351499ab 1066 reg_block = abs_queue_idx / 128;
24a768cf
CP		 1067 abs_queue_idx %= 128;
1068 }
351499ab
MJ		 1069
1070 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1071 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1072 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1073
1074 if (enable)
1075 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1076 else
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1078
1079 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1080}
38e00438
VD		 1081#ifdef I40E_FCOE
1082
1083/**
1084 * i40e_get_san_mac_addr - get SAN MAC address
1085 * @hw: pointer to the HW structure
1086 * @mac_addr: pointer to SAN MAC address
1087 *
1088 * Reads the adapter's SAN MAC address from NVM
1089 **/
1090i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1091{
1092 struct i40e_aqc_mac_address_read_data addrs;
1093 i40e_status status;
1094 u16 flags = 0;
1095
1096 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1097 if (status)
1098 return status;
1099
1100 if (flags & I40E_AQC_SAN_ADDR_VALID)
6995b36c 1101 ether_addr_copy(mac_addr, addrs.pf_san_mac);
38e00438
VD		 1102 else
1103 status = I40E_ERR_INVALID_MAC_ADDR;
1104
1105 return status;
1106}
1107#endif
351499ab 1108
18f680c6
KK		 1109/**
1110 * i40e_read_pba_string - Reads part number string from EEPROM
1111 * @hw: pointer to hardware structure
1112 * @pba_num: stores the part number string from the EEPROM
1113 * @pba_num_size: part number string buffer length
1114 *
1115 * Reads the part number string from the EEPROM.
1116 **/
1117i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1118 u32 pba_num_size)
1119{
1120 i40e_status status = 0;
1121 u16 pba_word = 0;
1122 u16 pba_size = 0;
1123 u16 pba_ptr = 0;
1124 u16 i = 0;
1125
1126 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1127 if (status || (pba_word != 0xFAFA)) {
1128 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1129 return status;
1130 }
1131
1132 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1133 if (status) {
1134 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1135 return status;
1136 }
1137
1138 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1139 if (status) {
1140 hw_dbg(hw, "Failed to read PBA Block size.\n");
1141 return status;
1142 }
1143
1144 /* Subtract one to get PBA word count (PBA Size word is included in
1145 * total size)
1146 */
1147 pba_size--;
1148 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1149 hw_dbg(hw, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM;
1151 }
1152
1153 for (i = 0; i < pba_size; i++) {
1154 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1155 if (status) {
1156 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1157 return status;
1158 }
1159
1160 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1161 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1162 }
1163 pba_num[(pba_size * 2)] = '\0';
1164
1165 return status;
1166}
1167
be405eb0
JB		 1168/**
1169 * i40e_get_media_type - Gets media type
1170 * @hw: pointer to the hardware structure
1171 **/
1172static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1173{
1174 enum i40e_media_type media;
1175
1176 switch (hw->phy.link_info.phy_type) {
1177 case I40E_PHY_TYPE_10GBASE_SR:
1178 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 1179 case I40E_PHY_TYPE_1000BASE_SX:
1180 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 1181 case I40E_PHY_TYPE_40GBASE_SR4:
1182 case I40E_PHY_TYPE_40GBASE_LR4:
1183 media = I40E_MEDIA_TYPE_FIBER;
1184 break;
1185 case I40E_PHY_TYPE_100BASE_TX:
1186 case I40E_PHY_TYPE_1000BASE_T:
1187 case I40E_PHY_TYPE_10GBASE_T:
1188 media = I40E_MEDIA_TYPE_BASET;
1189 break;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1192 case I40E_PHY_TYPE_10GBASE_CR1:
1193 case I40E_PHY_TYPE_40GBASE_CR4:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
180204c7
CS		 1195 case I40E_PHY_TYPE_40GBASE_AOC:
1196 case I40E_PHY_TYPE_10GBASE_AOC:
be405eb0
JB		 1197 media = I40E_MEDIA_TYPE_DA;
1198 break;
1199 case I40E_PHY_TYPE_1000BASE_KX:
1200 case I40E_PHY_TYPE_10GBASE_KX4:
1201 case I40E_PHY_TYPE_10GBASE_KR:
1202 case I40E_PHY_TYPE_40GBASE_KR4:
ae24b409 1203 case I40E_PHY_TYPE_20GBASE_KR2:
be405eb0
JB		 1204 media = I40E_MEDIA_TYPE_BACKPLANE;
1205 break;
1206 case I40E_PHY_TYPE_SGMII:
1207 case I40E_PHY_TYPE_XAUI:
1208 case I40E_PHY_TYPE_XFI:
1209 case I40E_PHY_TYPE_XLAUI:
1210 case I40E_PHY_TYPE_XLPPI:
1211 default:
1212 media = I40E_MEDIA_TYPE_UNKNOWN;
1213 break;
1214 }
1215
1216 return media;
1217}
1218
7134f9ce 1219#define I40E_PF_RESET_WAIT_COUNT_A0 200
8af580df 1220#define I40E_PF_RESET_WAIT_COUNT 200
56a62fc8
JB		 1221/**
1222 * i40e_pf_reset - Reset the PF
1223 * @hw: pointer to the hardware structure
1224 *
1225 * Assuming someone else has triggered a global reset,
1226 * assure the global reset is complete and then reset the PF
1227 **/
1228i40e_status i40e_pf_reset(struct i40e_hw *hw)
1229{
7134f9ce 1230 u32 cnt = 0;
42794bd8 1231 u32 cnt1 = 0;
56a62fc8
JB		 1232 u32 reg = 0;
1233 u32 grst_del;
1234
1235 /* Poll for Global Reset steady state in case of recent GRST.
1236 * The grst delay value is in 100ms units, and we'll wait a
1237 * couple counts longer to be sure we don't just miss the end.
1238 */
de78fc5a
SN		 1239 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
22e05bd6 1242 for (cnt = 0; cnt < grst_del + 10; cnt++) {
56a62fc8
JB		 1243 reg = rd32(hw, I40E_GLGEN_RSTAT);
1244 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1245 break;
1246 msleep(100);
1247 }
1248 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1249 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 1250 return I40E_ERR_RESET_FAILED;
1251 }
1252
1253 /* Now Wait for the FW to be ready */
1254 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1255 reg = rd32(hw, I40E_GLNVM_ULD);
1256 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1257 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1258 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1259 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1260 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1261 break;
1262 }
1263 usleep_range(10000, 20000);
1264 }
1265 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1267 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1268 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 1269 return I40E_ERR_RESET_FAILED;
1270 }
1271
56a62fc8
JB		 1272 /* If there was a Global Reset in progress when we got here,
1273 * we don't need to do the PF Reset
1274 */
7134f9ce
JB		 1275 if (!cnt) {
1276 if (hw->revision_id == 0)
1277 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1278 else
1279 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 1280 reg = rd32(hw, I40E_PFGEN_CTRL);
1281 wr32(hw, I40E_PFGEN_CTRL,
1282 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 1283 for (; cnt; cnt--) {
56a62fc8
JB		 1284 reg = rd32(hw, I40E_PFGEN_CTRL);
1285 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1286 break;
1287 usleep_range(1000, 2000);
1288 }
1289 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1290 hw_dbg(hw, "PF reset polling failed to complete.\n");
1291 return I40E_ERR_RESET_FAILED;
1292 }
1293 }
1294
1295 i40e_clear_pxe_mode(hw);
922680b9 1296
56a62fc8
JB		 1297 return 0;
1298}
1299
838d41d9
SN		 1300/**
1301 * i40e_clear_hw - clear out any left over hw state
1302 * @hw: pointer to the hw struct
1303 *
1304 * Clear queues and interrupts, typically called at init time,
1305 * but after the capabilities have been found so we know how many
1306 * queues and msix vectors have been allocated.
1307 **/
1308void i40e_clear_hw(struct i40e_hw *hw)
1309{
1310 u32 num_queues, base_queue;
1311 u32 num_pf_int;
1312 u32 num_vf_int;
1313 u32 num_vfs;
1314 u32 i, j;
1315 u32 val;
1316 u32 eol = 0x7ff;
1317
b40c82e6 1318 /* get number of interrupts, queues, and VFs */
838d41d9
SN		 1319 val = rd32(hw, I40E_GLPCI_CNF2);
1320 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1321 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1322 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1323 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1324
1325 val = rd32(hw, I40E_PFLAN_QALLOC);
1326 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1327 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1328 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1329 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1330 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1331 num_queues = (j - base_queue) + 1;
1332 else
1333 num_queues = 0;
1334
1335 val = rd32(hw, I40E_PF_VT_PFALLOC);
1336 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1337 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1338 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1339 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1340 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1341 num_vfs = (j - i) + 1;
1342 else
1343 num_vfs = 0;
1344
1345 /* stop all the interrupts */
1346 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1347 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1348 for (i = 0; i < num_pf_int - 2; i++)
1349 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1350
1351 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1352 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1353 wr32(hw, I40E_PFINT_LNKLST0, val);
1354 for (i = 0; i < num_pf_int - 2; i++)
1355 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1356 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1357 for (i = 0; i < num_vfs; i++)
1358 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1359 for (i = 0; i < num_vf_int - 2; i++)
1360 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1361
1362 /* warn the HW of the coming Tx disables */
1363 for (i = 0; i < num_queues; i++) {
1364 u32 abs_queue_idx = base_queue + i;
1365 u32 reg_block = 0;
1366
1367 if (abs_queue_idx >= 128) {
1368 reg_block = abs_queue_idx / 128;
1369 abs_queue_idx %= 128;
1370 }
1371
1372 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1373 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1374 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1375 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1376
1377 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1378 }
1379 udelay(400);
1380
1381 /* stop all the queues */
1382 for (i = 0; i < num_queues; i++) {
1383 wr32(hw, I40E_QINT_TQCTL(i), 0);
1384 wr32(hw, I40E_QTX_ENA(i), 0);
1385 wr32(hw, I40E_QINT_RQCTL(i), 0);
1386 wr32(hw, I40E_QRX_ENA(i), 0);
1387 }
1388
1389 /* short wait for all queue disables to settle */
1390 udelay(50);
1391}
1392
56a62fc8
JB		 1393/**
1394 * i40e_clear_pxe_mode - clear pxe operations mode
1395 * @hw: pointer to the hw struct
1396 *
1397 * Make sure all PXE mode settings are cleared, including things
1398 * like descriptor fetch/write-back mode.
1399 **/
1400void i40e_clear_pxe_mode(struct i40e_hw *hw)
1401{
1402 u32 reg;
1403
c9b9b0ae
SN		 1404 if (i40e_check_asq_alive(hw))
1405 i40e_aq_clear_pxe_mode(hw, NULL);
1406
56a62fc8
JB		 1407 /* Clear single descriptor fetch/write-back mode */
1408 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1409
1410 if (hw->revision_id == 0) {
1411 /* As a work around clear PXE_MODE instead of setting it */
1412 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1413 } else {
1414 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1415 }
56a62fc8
JB		 1416}
1417
0556a9e3
JB		 1418/**
1419 * i40e_led_is_mine - helper to find matching led
1420 * @hw: pointer to the hw struct
1421 * @idx: index into GPIO registers
1422 *
1423 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1424 */
1425static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1426{
1427 u32 gpio_val = 0;
1428 u32 port;
1429
1430 if (!hw->func_caps.led[idx])
1431 return 0;
1432
1433 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1434 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1435 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1436
1437 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1438 * if it is not our port then ignore
1439 */
1440 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1441 (port != hw->port))
1442 return 0;
1443
1444 return gpio_val;
1445}
1446
b84d5cd8
MJ		 1447#define I40E_COMBINED_ACTIVITY 0xA
1448#define I40E_FILTER_ACTIVITY 0xE
0556a9e3 1449#define I40E_LINK_ACTIVITY 0xC
b84d5cd8
MJ		 1450#define I40E_MAC_ACTIVITY 0xD
1451#define I40E_LED0 22
0556a9e3 1452
56a62fc8
JB		 1453/**
1454 * i40e_led_get - return current on/off mode
1455 * @hw: pointer to the hw struct
1456 *
1457 * The value returned is the 'mode' field as defined in the
1458 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1459 * values are variations of possible behaviors relating to
1460 * blink, link, and wire.
1461 **/
1462u32 i40e_led_get(struct i40e_hw *hw)
1463{
b84d5cd8 1464 u32 current_mode = 0;
56a62fc8 1465 u32 mode = 0;
56a62fc8
JB		 1466 int i;
1467
0556a9e3
JB		 1468 /* as per the documentation GPIO 22-29 are the LED
1469 * GPIO pins named LED0..LED7
1470 */
1471 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1472 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1473
0556a9e3 1474 if (!gpio_val)
56a62fc8
JB		 1475 continue;
1476
b84d5cd8
MJ		 1477 /* ignore gpio LED src mode entries related to the activity
1478 * LEDs
1479 */
1480 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1481 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1482 switch (current_mode) {
1483 case I40E_COMBINED_ACTIVITY:
1484 case I40E_FILTER_ACTIVITY:
1485 case I40E_MAC_ACTIVITY:
1486 continue;
1487 default:
1488 break;
1489 }
1490
0556a9e3
JB		 1491 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1492 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1493 break;
1494 }
1495
1496 return mode;
1497}
1498
1499/**
1500 * i40e_led_set - set new on/off mode
1501 * @hw: pointer to the hw struct
0556a9e3
JB		 1502 * @mode: 0=off, 0xf=on (else see manual for mode details)
1503 * @blink: true if the LED should blink when on, false if steady
1504 *
1505 * if this function is used to turn on the blink it should
1506 * be used to disable the blink when restoring the original state.
56a62fc8 1507 **/
0556a9e3 1508void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1509{
b84d5cd8 1510 u32 current_mode = 0;
56a62fc8
JB		 1511 int i;
1512
0556a9e3
JB		 1513 if (mode & 0xfffffff0)
1514 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1515
0556a9e3
JB		 1516 /* as per the documentation GPIO 22-29 are the LED
1517 * GPIO pins named LED0..LED7
1518 */
1519 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1520 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1521
0556a9e3 1522 if (!gpio_val)
56a62fc8
JB		 1523 continue;
1524
b84d5cd8
MJ		 1525 /* ignore gpio LED src mode entries related to the activity
1526 * LEDs
1527 */
1528 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1529 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1530 switch (current_mode) {
1531 case I40E_COMBINED_ACTIVITY:
1532 case I40E_FILTER_ACTIVITY:
1533 case I40E_MAC_ACTIVITY:
1534 continue;
1535 default:
1536 break;
1537 }
1538
56a62fc8 1539 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1540 /* this & is a bit of paranoia, but serves as a range check */
1541 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1542 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1543
1544 if (mode == I40E_LINK_ACTIVITY)
1545 blink = false;
1546
9be00d67 1547 if (blink)
41a1d04b 1548 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
9be00d67 1549 else
41a1d04b 1550 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1551
56a62fc8 1552 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1553 break;
56a62fc8
JB		 1554 }
1555}
1556
1557/* Admin command wrappers */
56a62fc8 1558
8109e123
CS		 1559/**
1560 * i40e_aq_get_phy_capabilities
1561 * @hw: pointer to the hw struct
1562 * @abilities: structure for PHY capabilities to be filled
1563 * @qualified_modules: report Qualified Modules
1564 * @report_init: report init capabilities (active are default)
1565 * @cmd_details: pointer to command details structure or NULL
1566 *
1567 * Returns the various PHY abilities supported on the Port.
1568 **/
1569i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1570 bool qualified_modules, bool report_init,
1571 struct i40e_aq_get_phy_abilities_resp *abilities,
1572 struct i40e_asq_cmd_details *cmd_details)
1573{
1574 struct i40e_aq_desc desc;
1575 i40e_status status;
1576 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1577
1578 if (!abilities)
1579 return I40E_ERR_PARAM;
1580
1581 i40e_fill_default_direct_cmd_desc(&desc,
1582 i40e_aqc_opc_get_phy_abilities);
1583
1584 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1585 if (abilities_size > I40E_AQ_LARGE_BUF)
1586 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1587
1588 if (qualified_modules)
1589 desc.params.external.param0 |=
1590 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1591
1592 if (report_init)
1593 desc.params.external.param0 |=
1594 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1595
1596 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1597 cmd_details);
1598
1599 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1600 status = I40E_ERR_UNKNOWN_PHY;
1601
3ac67d7b
KS		 1602 if (report_init)
1603 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1604
8109e123
CS		 1605 return status;
1606}
1607
c56999f9
CS		 1608/**
1609 * i40e_aq_set_phy_config
1610 * @hw: pointer to the hw struct
1611 * @config: structure with PHY configuration to be set
1612 * @cmd_details: pointer to command details structure or NULL
1613 *
1614 * Set the various PHY configuration parameters
1615 * supported on the Port.One or more of the Set PHY config parameters may be
1616 * ignored in an MFP mode as the PF may not have the privilege to set some
1617 * of the PHY Config parameters. This status will be indicated by the
1618 * command response.
1619 **/
1620enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1621 struct i40e_aq_set_phy_config *config,
1622 struct i40e_asq_cmd_details *cmd_details)
1623{
1624 struct i40e_aq_desc desc;
1625 struct i40e_aq_set_phy_config *cmd =
1626 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1627 enum i40e_status_code status;
1628
1629 if (!config)
1630 return I40E_ERR_PARAM;
1631
1632 i40e_fill_default_direct_cmd_desc(&desc,
1633 i40e_aqc_opc_set_phy_config);
1634
1635 *cmd = *config;
1636
1637 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1638
1639 return status;
1640}
1641
1642/**
1643 * i40e_set_fc
1644 * @hw: pointer to the hw struct
1645 *
1646 * Set the requested flow control mode using set_phy_config.
1647 **/
1648enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1649 bool atomic_restart)
1650{
1651 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1652 struct i40e_aq_get_phy_abilities_resp abilities;
1653 struct i40e_aq_set_phy_config config;
1654 enum i40e_status_code status;
1655 u8 pause_mask = 0x0;
1656
1657 *aq_failures = 0x0;
1658
1659 switch (fc_mode) {
1660 case I40E_FC_FULL:
1661 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1662 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1663 break;
1664 case I40E_FC_RX_PAUSE:
1665 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1666 break;
1667 case I40E_FC_TX_PAUSE:
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1669 break;
1670 default:
1671 break;
1672 }
1673
1674 /* Get the current phy config */
1675 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1676 NULL);
1677 if (status) {
1678 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1679 return status;
1680 }
1681
1682 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1683 /* clear the old pause settings */
1684 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1685 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1686 /* set the new abilities */
1687 config.abilities |= pause_mask;
1688 /* If the abilities have changed, then set the new config */
1689 if (config.abilities != abilities.abilities) {
1690 /* Auto restart link so settings take effect */
1691 if (atomic_restart)
1692 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1693 /* Copy over all the old settings */
1694 config.phy_type = abilities.phy_type;
1695 config.link_speed = abilities.link_speed;
1696 config.eee_capability = abilities.eee_capability;
1697 config.eeer = abilities.eeer_val;
1698 config.low_power_ctrl = abilities.d3_lpan;
1699 status = i40e_aq_set_phy_config(hw, &config, NULL);
1700
1701 if (status)
1702 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1703 }
1704 /* Update the link info */
0a862b43 1705 status = i40e_update_link_info(hw);
c56999f9
CS		 1706 if (status) {
1707 /* Wait a little bit (on 40G cards it sometimes takes a really
1708 * long time for link to come back from the atomic reset)
1709 * and try once more
1710 */
1711 msleep(1000);
0a862b43 1712 status = i40e_update_link_info(hw);
c56999f9
CS		 1713 }
1714 if (status)
1715 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1716
1717 return status;
1718}
1719
c9b9b0ae
SN		 1720/**
1721 * i40e_aq_clear_pxe_mode
1722 * @hw: pointer to the hw struct
1723 * @cmd_details: pointer to command details structure or NULL
1724 *
1725 * Tell the firmware that the driver is taking over from PXE
1726 **/
1727i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1728 struct i40e_asq_cmd_details *cmd_details)
1729{
1730 i40e_status status;
1731 struct i40e_aq_desc desc;
1732 struct i40e_aqc_clear_pxe *cmd =
1733 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1734
1735 i40e_fill_default_direct_cmd_desc(&desc,
1736 i40e_aqc_opc_clear_pxe_mode);
1737
1738 cmd->rx_cnt = 0x2;
1739
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1741
1742 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1743
1744 return status;
1745}
1746
56a62fc8
JB		 1747/**
1748 * i40e_aq_set_link_restart_an
1749 * @hw: pointer to the hw struct
1ac978af 1750 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1751 * @cmd_details: pointer to command details structure or NULL
1752 *
1753 * Sets up the link and restarts the Auto-Negotiation over the link.
1754 **/
1755i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1756 bool enable_link,
1757 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1758{
1759 struct i40e_aq_desc desc;
1760 struct i40e_aqc_set_link_restart_an *cmd =
1761 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1762 i40e_status status;
1763
1764 i40e_fill_default_direct_cmd_desc(&desc,
1765 i40e_aqc_opc_set_link_restart_an);
1766
1767 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1768 if (enable_link)
1769 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1770 else
1771 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1772
1773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1774
1775 return status;
1776}
1777
1778/**
1779 * i40e_aq_get_link_info
1780 * @hw: pointer to the hw struct
1781 * @enable_lse: enable/disable LinkStatusEvent reporting
1782 * @link: pointer to link status structure - optional
1783 * @cmd_details: pointer to command details structure or NULL
1784 *
1785 * Returns the link status of the adapter.
1786 **/
1787i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1788 bool enable_lse, struct i40e_link_status *link,
1789 struct i40e_asq_cmd_details *cmd_details)
1790{
1791 struct i40e_aq_desc desc;
1792 struct i40e_aqc_get_link_status *resp =
1793 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1794 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1795 i40e_status status;
c56999f9 1796 bool tx_pause, rx_pause;
56a62fc8
JB		 1797 u16 command_flags;
1798
1799 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1800
1801 if (enable_lse)
1802 command_flags = I40E_AQ_LSE_ENABLE;
1803 else
1804 command_flags = I40E_AQ_LSE_DISABLE;
1805 resp->command_flags = cpu_to_le16(command_flags);
1806
1807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1808
1809 if (status)
1810 goto aq_get_link_info_exit;
1811
1812 /* save off old link status information */
c36bd4a7 1813 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1814
1815 /* update link status */
1816 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1817 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1818 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1819 hw_link_info->link_info = resp->link_info;
1820 hw_link_info->an_info = resp->an_info;
1821 hw_link_info->ext_info = resp->ext_info;
639dc377 1822 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1823 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1824 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1825
c56999f9
CS		 1826 /* update fc info */
1827 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1828 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1829 if (tx_pause & rx_pause)
1830 hw->fc.current_mode = I40E_FC_FULL;
1831 else if (tx_pause)
1832 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1833 else if (rx_pause)
1834 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1835 else
1836 hw->fc.current_mode = I40E_FC_NONE;
1837
6bb3f23c
NP		 1838 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1839 hw_link_info->crc_enable = true;
1840 else
1841 hw_link_info->crc_enable = false;
56a62fc8
JB		 1842
1843 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1844 hw_link_info->lse_enable = true;
1845 else
1846 hw_link_info->lse_enable = false;
1847
088c4ee3
CS		 1848 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1849 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1850 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1851
56a62fc8
JB		 1852 /* save link status information */
1853 if (link)
d7595a22 1854 *link = *hw_link_info;
56a62fc8
JB		 1855
1856 /* flag cleared so helper functions don't call AQ again */
1857 hw->phy.get_link_info = false;
1858
1859aq_get_link_info_exit:
1860 return status;
1861}
1862
7e2453fe
JB		 1863/**
1864 * i40e_aq_set_phy_int_mask
1865 * @hw: pointer to the hw struct
1866 * @mask: interrupt mask to be set
1867 * @cmd_details: pointer to command details structure or NULL
1868 *
1869 * Set link interrupt mask.
1870 **/
1871i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1872 u16 mask,
1873 struct i40e_asq_cmd_details *cmd_details)
1874{
1875 struct i40e_aq_desc desc;
1876 struct i40e_aqc_set_phy_int_mask *cmd =
1877 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1878 i40e_status status;
1879
1880 i40e_fill_default_direct_cmd_desc(&desc,
1881 i40e_aqc_opc_set_phy_int_mask);
1882
1883 cmd->event_mask = cpu_to_le16(mask);
1884
1885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1886
1887 return status;
1888}
1889
56a62fc8
JB		 1890/**
1891 * i40e_aq_add_vsi
1892 * @hw: pointer to the hw struct
98d44381 1893 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1894 * @cmd_details: pointer to command details structure or NULL
1895 *
1896 * Add a VSI context to the hardware.
1897**/
1898i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1899 struct i40e_vsi_context *vsi_ctx,
1900 struct i40e_asq_cmd_details *cmd_details)
1901{
1902 struct i40e_aq_desc desc;
1903 struct i40e_aqc_add_get_update_vsi *cmd =
1904 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1905 struct i40e_aqc_add_get_update_vsi_completion *resp =
1906 (struct i40e_aqc_add_get_update_vsi_completion *)
1907 &desc.params.raw;
1908 i40e_status status;
1909
1910 i40e_fill_default_direct_cmd_desc(&desc,
1911 i40e_aqc_opc_add_vsi);
1912
1913 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1914 cmd->connection_type = vsi_ctx->connection_type;
1915 cmd->vf_id = vsi_ctx->vf_num;
1916 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1917
1918 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1919
1920 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1921 sizeof(vsi_ctx->info), cmd_details);
1922
1923 if (status)
1924 goto aq_add_vsi_exit;
1925
1926 vsi_ctx->seid = le16_to_cpu(resp->seid);
1927 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1928 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1929 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1930
1931aq_add_vsi_exit:
1932 return status;
1933}
1934
1935/**
1936 * i40e_aq_set_vsi_unicast_promiscuous
1937 * @hw: pointer to the hw struct
1938 * @seid: vsi number
1939 * @set: set unicast promiscuous enable/disable
1940 * @cmd_details: pointer to command details structure or NULL
1941 **/
1942i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1943 u16 seid, bool set,
1944 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1945{
1946 struct i40e_aq_desc desc;
1947 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1948 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1949 i40e_status status;
1950 u16 flags = 0;
1951
1952 i40e_fill_default_direct_cmd_desc(&desc,
1953 i40e_aqc_opc_set_vsi_promiscuous_modes);
1954
1955 if (set)
1956 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1957
1958 cmd->promiscuous_flags = cpu_to_le16(flags);
1959
1960 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1961
1962 cmd->seid = cpu_to_le16(seid);
1963 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1964
1965 return status;
1966}
1967
1968/**
1969 * i40e_aq_set_vsi_multicast_promiscuous
1970 * @hw: pointer to the hw struct
1971 * @seid: vsi number
1972 * @set: set multicast promiscuous enable/disable
1973 * @cmd_details: pointer to command details structure or NULL
1974 **/
1975i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1976 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1977{
1978 struct i40e_aq_desc desc;
1979 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1980 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1981 i40e_status status;
1982 u16 flags = 0;
1983
1984 i40e_fill_default_direct_cmd_desc(&desc,
1985 i40e_aqc_opc_set_vsi_promiscuous_modes);
1986
1987 if (set)
1988 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1989
1990 cmd->promiscuous_flags = cpu_to_le16(flags);
1991
1992 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1993
1994 cmd->seid = cpu_to_le16(seid);
1995 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1996
1997 return status;
1998}
1999
2000/**
2001 * i40e_aq_set_vsi_broadcast
2002 * @hw: pointer to the hw struct
2003 * @seid: vsi number
2004 * @set_filter: true to set filter, false to clear filter
2005 * @cmd_details: pointer to command details structure or NULL
2006 *
2007 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2008 **/
2009i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2010 u16 seid, bool set_filter,
2011 struct i40e_asq_cmd_details *cmd_details)
2012{
2013 struct i40e_aq_desc desc;
2014 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2015 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2016 i40e_status status;
2017
2018 i40e_fill_default_direct_cmd_desc(&desc,
2019 i40e_aqc_opc_set_vsi_promiscuous_modes);
2020
2021 if (set_filter)
2022 cmd->promiscuous_flags
2023 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2024 else
2025 cmd->promiscuous_flags
2026 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2027
2028 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2029 cmd->seid = cpu_to_le16(seid);
2030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031
2032 return status;
2033}
2034
7bd6875b
KP		 2035/**
2036 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2037 * @hw: pointer to the hw struct
2038 * @seid: vsi number
2039 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2040 * @cmd_details: pointer to command details structure or NULL
2041 **/
2042i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2043 u16 seid, bool enable,
2044 struct i40e_asq_cmd_details *cmd_details)
2045{
2046 struct i40e_aq_desc desc;
2047 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2048 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2049 i40e_status status;
2050 u16 flags = 0;
2051
2052 i40e_fill_default_direct_cmd_desc(&desc,
2053 i40e_aqc_opc_set_vsi_promiscuous_modes);
2054 if (enable)
2055 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2056
2057 cmd->promiscuous_flags = cpu_to_le16(flags);
2058 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2059 cmd->seid = cpu_to_le16(seid);
2060
2061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2062
2063 return status;
2064}
2065
56a62fc8
JB		 2066/**
2067 * i40e_get_vsi_params - get VSI configuration info
2068 * @hw: pointer to the hw struct
98d44381 2069 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2070 * @cmd_details: pointer to command details structure or NULL
2071 **/
2072i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2073 struct i40e_vsi_context *vsi_ctx,
2074 struct i40e_asq_cmd_details *cmd_details)
2075{
2076 struct i40e_aq_desc desc;
f5ac8579
SN		 2077 struct i40e_aqc_add_get_update_vsi *cmd =
2078 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2079 struct i40e_aqc_add_get_update_vsi_completion *resp =
2080 (struct i40e_aqc_add_get_update_vsi_completion *)
2081 &desc.params.raw;
2082 i40e_status status;
2083
2084 i40e_fill_default_direct_cmd_desc(&desc,
2085 i40e_aqc_opc_get_vsi_parameters);
2086
f5ac8579 2087 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2088
2089 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 2090
2091 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2092 sizeof(vsi_ctx->info), NULL);
2093
2094 if (status)
2095 goto aq_get_vsi_params_exit;
2096
2097 vsi_ctx->seid = le16_to_cpu(resp->seid);
2098 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2099 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2100 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2101
2102aq_get_vsi_params_exit:
2103 return status;
2104}
2105
2106/**
2107 * i40e_aq_update_vsi_params
2108 * @hw: pointer to the hw struct
98d44381 2109 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2110 * @cmd_details: pointer to command details structure or NULL
2111 *
2112 * Update a VSI context.
2113 **/
2114i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2115 struct i40e_vsi_context *vsi_ctx,
2116 struct i40e_asq_cmd_details *cmd_details)
2117{
2118 struct i40e_aq_desc desc;
f5ac8579
SN		 2119 struct i40e_aqc_add_get_update_vsi *cmd =
2120 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2121 i40e_status status;
2122
2123 i40e_fill_default_direct_cmd_desc(&desc,
2124 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 2125 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2126
2127 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 2128
2129 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2130 sizeof(vsi_ctx->info), cmd_details);
2131
2132 return status;
2133}
2134
2135/**
2136 * i40e_aq_get_switch_config
2137 * @hw: pointer to the hardware structure
2138 * @buf: pointer to the result buffer
2139 * @buf_size: length of input buffer
2140 * @start_seid: seid to start for the report, 0 == beginning
2141 * @cmd_details: pointer to command details structure or NULL
2142 *
2143 * Fill the buf with switch configuration returned from AdminQ command
2144 **/
2145i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2146 struct i40e_aqc_get_switch_config_resp *buf,
2147 u16 buf_size, u16 *start_seid,
2148 struct i40e_asq_cmd_details *cmd_details)
2149{
2150 struct i40e_aq_desc desc;
2151 struct i40e_aqc_switch_seid *scfg =
2152 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2153 i40e_status status;
2154
2155 i40e_fill_default_direct_cmd_desc(&desc,
2156 i40e_aqc_opc_get_switch_config);
2157 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2158 if (buf_size > I40E_AQ_LARGE_BUF)
2159 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2160 scfg->seid = cpu_to_le16(*start_seid);
2161
2162 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2163 *start_seid = le16_to_cpu(scfg->seid);
2164
2165 return status;
2166}
2167
2168/**
2169 * i40e_aq_get_firmware_version
2170 * @hw: pointer to the hw struct
2171 * @fw_major_version: firmware major version
2172 * @fw_minor_version: firmware minor version
7edf810c 2173 * @fw_build: firmware build number
56a62fc8
JB		 2174 * @api_major_version: major queue version
2175 * @api_minor_version: minor queue version
2176 * @cmd_details: pointer to command details structure or NULL
2177 *
2178 * Get the firmware version from the admin queue commands
2179 **/
2180i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2181 u16 *fw_major_version, u16 *fw_minor_version,
7edf810c 2182 u32 *fw_build,
56a62fc8
JB		 2183 u16 *api_major_version, u16 *api_minor_version,
2184 struct i40e_asq_cmd_details *cmd_details)
2185{
2186 struct i40e_aq_desc desc;
2187 struct i40e_aqc_get_version *resp =
2188 (struct i40e_aqc_get_version *)&desc.params.raw;
2189 i40e_status status;
2190
2191 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2192
2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2194
2195 if (!status) {
7edf810c 2196 if (fw_major_version)
56a62fc8 2197 *fw_major_version = le16_to_cpu(resp->fw_major);
7edf810c 2198 if (fw_minor_version)
56a62fc8 2199 *fw_minor_version = le16_to_cpu(resp->fw_minor);
7edf810c
SN		 2200 if (fw_build)
2201 *fw_build = le32_to_cpu(resp->fw_build);
2202 if (api_major_version)
56a62fc8 2203 *api_major_version = le16_to_cpu(resp->api_major);
7edf810c 2204 if (api_minor_version)
56a62fc8
JB		 2205 *api_minor_version = le16_to_cpu(resp->api_minor);
2206 }
2207
2208 return status;
2209}
2210
2211/**
2212 * i40e_aq_send_driver_version
2213 * @hw: pointer to the hw struct
56a62fc8
JB		 2214 * @dv: driver's major, minor version
2215 * @cmd_details: pointer to command details structure or NULL
2216 *
2217 * Send the driver version to the firmware
2218 **/
2219i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2220 struct i40e_driver_version *dv,
2221 struct i40e_asq_cmd_details *cmd_details)
2222{
2223 struct i40e_aq_desc desc;
2224 struct i40e_aqc_driver_version *cmd =
2225 (struct i40e_aqc_driver_version *)&desc.params.raw;
2226 i40e_status status;
9d2f98e1 2227 u16 len;
56a62fc8
JB		 2228
2229 if (dv == NULL)
2230 return I40E_ERR_PARAM;
2231
2232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2233
3b38cd17 2234 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
56a62fc8
JB		 2235 cmd->driver_major_ver = dv->major_version;
2236 cmd->driver_minor_ver = dv->minor_version;
2237 cmd->driver_build_ver = dv->build_version;
2238 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 2239
2240 len = 0;
2241 while (len < sizeof(dv->driver_string) &&
2242 (dv->driver_string[len] < 0x80) &&
2243 dv->driver_string[len])
2244 len++;
2245 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2246 len, cmd_details);
56a62fc8
JB		 2247
2248 return status;
2249}
2250
2251/**
2252 * i40e_get_link_status - get status of the HW network link
2253 * @hw: pointer to the hw struct
a72a5abc 2254 * @link_up: pointer to bool (true/false = linkup/linkdown)
56a62fc8 2255 *
a72a5abc
JB		 2256 * Variable link_up true if link is up, false if link is down.
2257 * The variable link_up is invalid if returned value of status != 0
56a62fc8
JB		 2258 *
2259 * Side effect: LinkStatusEvent reporting becomes enabled
2260 **/
a72a5abc 2261i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
56a62fc8
JB		 2262{
2263 i40e_status status = 0;
56a62fc8
JB		 2264
2265 if (hw->phy.get_link_info) {
0a862b43 2266 status = i40e_update_link_info(hw);
56a62fc8
JB		 2267
2268 if (status)
a72a5abc
JB		 2269 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2270 status);
56a62fc8
JB		 2271 }
2272
a72a5abc 2273 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
56a62fc8 2274
a72a5abc 2275 return status;
56a62fc8
JB		 2276}
2277
0a862b43
CS		 2278/**
2279 * i40e_updatelink_status - update status of the HW network link
2280 * @hw: pointer to the hw struct
2281 **/
2282i40e_status i40e_update_link_info(struct i40e_hw *hw)
2283{
2284 struct i40e_aq_get_phy_abilities_resp abilities;
2285 i40e_status status = 0;
2286
2287 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2288 if (status)
2289 return status;
2290
8589af70
CW		 2291 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2292 status = i40e_aq_get_phy_capabilities(hw, false, false,
2293 &abilities, NULL);
2294 if (status)
2295 return status;
0a862b43 2296
8589af70
CW		 2297 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2298 sizeof(hw->phy.link_info.module_type));
2299 }
0a862b43
CS		 2300
2301 return status;
2302}
2303
56a62fc8
JB		 2304/**
2305 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2306 * @hw: pointer to the hw struct
2307 * @uplink_seid: the MAC or other gizmo SEID
2308 * @downlink_seid: the VSI SEID
2309 * @enabled_tc: bitmap of TCs to be enabled
2310 * @default_port: true for default port VSI, false for control port
2311 * @veb_seid: pointer to where to put the resulting VEB SEID
8a187f44 2312 * @enable_stats: true to turn on VEB stats
56a62fc8
JB		 2313 * @cmd_details: pointer to command details structure or NULL
2314 *
2315 * This asks the FW to add a VEB between the uplink and downlink
2316 * elements. If the uplink SEID is 0, this will be a floating VEB.
2317 **/
2318i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2319 u16 downlink_seid, u8 enabled_tc,
8a187f44
SN		 2320 bool default_port, u16 *veb_seid,
2321 bool enable_stats,
56a62fc8
JB		 2322 struct i40e_asq_cmd_details *cmd_details)
2323{
2324 struct i40e_aq_desc desc;
2325 struct i40e_aqc_add_veb *cmd =
2326 (struct i40e_aqc_add_veb *)&desc.params.raw;
2327 struct i40e_aqc_add_veb_completion *resp =
2328 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2329 i40e_status status;
2330 u16 veb_flags = 0;
2331
2332 /* SEIDs need to either both be set or both be 0 for floating VEB */
2333 if (!!uplink_seid != !!downlink_seid)
2334 return I40E_ERR_PARAM;
2335
2336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2337
2338 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2339 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2340 cmd->enable_tcs = enabled_tc;
2341 if (!uplink_seid)
2342 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2343 if (default_port)
2344 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2345 else
2346 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95 2347
8a187f44
SN		 2348 /* reverse logic here: set the bitflag to disable the stats */
2349 if (!enable_stats)
2350 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
e1c51b95 2351
56a62fc8
JB		 2352 cmd->veb_flags = cpu_to_le16(veb_flags);
2353
2354 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2355
2356 if (!status && veb_seid)
2357 *veb_seid = le16_to_cpu(resp->veb_seid);
2358
2359 return status;
2360}
2361
2362/**
2363 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2364 * @hw: pointer to the hw struct
2365 * @veb_seid: the SEID of the VEB to query
2366 * @switch_id: the uplink switch id
98d44381 2367 * @floating: set to true if the VEB is floating
56a62fc8
JB		 2368 * @statistic_index: index of the stats counter block for this VEB
2369 * @vebs_used: number of VEB's used by function
98d44381 2370 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 2371 * @cmd_details: pointer to command details structure or NULL
2372 *
2373 * This retrieves the parameters for a particular VEB, specified by
2374 * uplink_seid, and returns them to the caller.
2375 **/
2376i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2377 u16 veb_seid, u16 *switch_id,
2378 bool *floating, u16 *statistic_index,
2379 u16 *vebs_used, u16 *vebs_free,
2380 struct i40e_asq_cmd_details *cmd_details)
2381{
2382 struct i40e_aq_desc desc;
2383 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2384 (struct i40e_aqc_get_veb_parameters_completion *)
2385 &desc.params.raw;
2386 i40e_status status;
2387
2388 if (veb_seid == 0)
2389 return I40E_ERR_PARAM;
2390
2391 i40e_fill_default_direct_cmd_desc(&desc,
2392 i40e_aqc_opc_get_veb_parameters);
2393 cmd_resp->seid = cpu_to_le16(veb_seid);
2394
2395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2396 if (status)
2397 goto get_veb_exit;
2398
2399 if (switch_id)
2400 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2401 if (statistic_index)
2402 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2403 if (vebs_used)
2404 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2405 if (vebs_free)
2406 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2407 if (floating) {
2408 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
6995b36c 2409
56a62fc8
JB		 2410 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2411 *floating = true;
2412 else
2413 *floating = false;
2414 }
2415
2416get_veb_exit:
2417 return status;
2418}
2419
2420/**
2421 * i40e_aq_add_macvlan
2422 * @hw: pointer to the hw struct
2423 * @seid: VSI for the mac address
2424 * @mv_list: list of macvlans to be added
2425 * @count: length of the list
2426 * @cmd_details: pointer to command details structure or NULL
2427 *
2428 * Add MAC/VLAN addresses to the HW filtering
2429 **/
2430i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2431 struct i40e_aqc_add_macvlan_element_data *mv_list,
2432 u16 count, struct i40e_asq_cmd_details *cmd_details)
2433{
2434 struct i40e_aq_desc desc;
2435 struct i40e_aqc_macvlan *cmd =
2436 (struct i40e_aqc_macvlan *)&desc.params.raw;
2437 i40e_status status;
2438 u16 buf_size;
67be6eb2 2439 int i;
56a62fc8
JB		 2440
2441 if (count == 0 || !mv_list || !hw)
2442 return I40E_ERR_PARAM;
2443
1efc80ee 2444 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2445
2446 /* prep the rest of the request */
2447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2448 cmd->num_addresses = cpu_to_le16(count);
2449 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2450 cmd->seid[1] = 0;
2451 cmd->seid[2] = 0;
2452
67be6eb2
SN		 2453 for (i = 0; i < count; i++)
2454 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2455 mv_list[i].flags |=
2456 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2457
56a62fc8
JB		 2458 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2459 if (buf_size > I40E_AQ_LARGE_BUF)
2460 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2461
2462 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
67be6eb2 2463 cmd_details);
56a62fc8
JB		 2464
2465 return status;
2466}
2467
2468/**
2469 * i40e_aq_remove_macvlan
2470 * @hw: pointer to the hw struct
2471 * @seid: VSI for the mac address
2472 * @mv_list: list of macvlans to be removed
2473 * @count: length of the list
2474 * @cmd_details: pointer to command details structure or NULL
2475 *
2476 * Remove MAC/VLAN addresses from the HW filtering
2477 **/
2478i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2479 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2480 u16 count, struct i40e_asq_cmd_details *cmd_details)
2481{
2482 struct i40e_aq_desc desc;
2483 struct i40e_aqc_macvlan *cmd =
2484 (struct i40e_aqc_macvlan *)&desc.params.raw;
2485 i40e_status status;
2486 u16 buf_size;
2487
2488 if (count == 0 || !mv_list || !hw)
2489 return I40E_ERR_PARAM;
2490
1efc80ee 2491 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2492
2493 /* prep the rest of the request */
2494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2495 cmd->num_addresses = cpu_to_le16(count);
2496 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2497 cmd->seid[1] = 0;
2498 cmd->seid[2] = 0;
2499
2500 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2501 if (buf_size > I40E_AQ_LARGE_BUF)
2502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2503
2504 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2505 cmd_details);
2506
2507 return status;
2508}
2509
7bd6875b
KP		 2510/**
2511 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2512 * @hw: pointer to the hw struct
2513 * @opcode: AQ opcode for add or delete mirror rule
2514 * @sw_seid: Switch SEID (to which rule refers)
2515 * @rule_type: Rule Type (ingress/egress/VLAN)
2516 * @id: Destination VSI SEID or Rule ID
2517 * @count: length of the list
2518 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2519 * @cmd_details: pointer to command details structure or NULL
2520 * @rule_id: Rule ID returned from FW
2521 * @rule_used: Number of rules used in internal switch
2522 * @rule_free: Number of rules free in internal switch
2523 *
2524 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2525 * VEBs/VEPA elements only
2526 **/
2527static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2528 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2529 u16 count, __le16 *mr_list,
2530 struct i40e_asq_cmd_details *cmd_details,
2531 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2532{
2533 struct i40e_aq_desc desc;
2534 struct i40e_aqc_add_delete_mirror_rule *cmd =
2535 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2536 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2537 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2538 i40e_status status;
2539 u16 buf_size;
2540
2541 buf_size = count * sizeof(*mr_list);
2542
2543 /* prep the rest of the request */
2544 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2545 cmd->seid = cpu_to_le16(sw_seid);
2546 cmd->rule_type = cpu_to_le16(rule_type &
2547 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2548 cmd->num_entries = cpu_to_le16(count);
2549 /* Dest VSI for add, rule_id for delete */
2550 cmd->destination = cpu_to_le16(id);
2551 if (mr_list) {
2552 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2553 I40E_AQ_FLAG_RD));
2554 if (buf_size > I40E_AQ_LARGE_BUF)
2555 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2556 }
2557
2558 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2559 cmd_details);
2560 if (!status ||
2561 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2562 if (rule_id)
2563 *rule_id = le16_to_cpu(resp->rule_id);
2564 if (rules_used)
2565 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2566 if (rules_free)
2567 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2568 }
2569 return status;
2570}
2571
2572/**
2573 * i40e_aq_add_mirrorrule - add a mirror rule
2574 * @hw: pointer to the hw struct
2575 * @sw_seid: Switch SEID (to which rule refers)
2576 * @rule_type: Rule Type (ingress/egress/VLAN)
2577 * @dest_vsi: SEID of VSI to which packets will be mirrored
2578 * @count: length of the list
2579 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2580 * @cmd_details: pointer to command details structure or NULL
2581 * @rule_id: Rule ID returned from FW
2582 * @rule_used: Number of rules used in internal switch
2583 * @rule_free: Number of rules free in internal switch
2584 *
2585 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2586 **/
2587i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2588 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2589 struct i40e_asq_cmd_details *cmd_details,
2590 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2591{
2592 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2593 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2594 if (count == 0 || !mr_list)
2595 return I40E_ERR_PARAM;
2596 }
2597
2598 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2599 rule_type, dest_vsi, count, mr_list,
2600 cmd_details, rule_id, rules_used, rules_free);
2601}
2602
2603/**
2604 * i40e_aq_delete_mirrorrule - delete a mirror rule
2605 * @hw: pointer to the hw struct
2606 * @sw_seid: Switch SEID (to which rule refers)
2607 * @rule_type: Rule Type (ingress/egress/VLAN)
2608 * @count: length of the list
2609 * @rule_id: Rule ID that is returned in the receive desc as part of
2610 * add_mirrorrule.
2611 * @mr_list: list of mirrored VLAN IDs to be removed
2612 * @cmd_details: pointer to command details structure or NULL
2613 * @rule_used: Number of rules used in internal switch
2614 * @rule_free: Number of rules free in internal switch
2615 *
2616 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2617 **/
2618i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2619 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2620 struct i40e_asq_cmd_details *cmd_details,
2621 u16 *rules_used, u16 *rules_free)
2622{
2623 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2624 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2625 if (!rule_id)
2626 return I40E_ERR_PARAM;
2627 } else {
2628 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2629 * mirroring. For other rule_type, count and rule_type should
2630 * not matter.
2631 */
2632 if (count == 0 || !mr_list)
2633 return I40E_ERR_PARAM;
2634 }
2635
2636 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2637 rule_type, rule_id, count, mr_list,
2638 cmd_details, NULL, rules_used, rules_free);
2639}
2640
56a62fc8
JB		 2641/**
2642 * i40e_aq_send_msg_to_vf
2643 * @hw: pointer to the hardware structure
b40c82e6 2644 * @vfid: VF id to send msg
98d44381
JK		 2645 * @v_opcode: opcodes for VF-PF communication
2646 * @v_retval: return error code
56a62fc8
JB		 2647 * @msg: pointer to the msg buffer
2648 * @msglen: msg length
2649 * @cmd_details: pointer to command details
2650 *
2651 * send msg to vf
2652 **/
2653i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2654 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2655 struct i40e_asq_cmd_details *cmd_details)
2656{
2657 struct i40e_aq_desc desc;
2658 struct i40e_aqc_pf_vf_message *cmd =
2659 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2660 i40e_status status;
2661
2662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2663 cmd->id = cpu_to_le32(vfid);
2664 desc.cookie_high = cpu_to_le32(v_opcode);
2665 desc.cookie_low = cpu_to_le32(v_retval);
2666 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2667 if (msglen) {
2668 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2669 I40E_AQ_FLAG_RD));
2670 if (msglen > I40E_AQ_LARGE_BUF)
2671 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2672 desc.datalen = cpu_to_le16(msglen);
2673 }
2674 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2675
2676 return status;
2677}
2678
9fee9db5
SN		 2679/**
2680 * i40e_aq_debug_read_register
2681 * @hw: pointer to the hw struct
2682 * @reg_addr: register address
2683 * @reg_val: register value
2684 * @cmd_details: pointer to command details structure or NULL
2685 *
2686 * Read the register using the admin queue commands
2687 **/
2688i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
7b115dd0 2689 u32 reg_addr, u64 *reg_val,
9fee9db5
SN		 2690 struct i40e_asq_cmd_details *cmd_details)
2691{
2692 struct i40e_aq_desc desc;
2693 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2694 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2695 i40e_status status;
2696
2697 if (reg_val == NULL)
2698 return I40E_ERR_PARAM;
2699
7b115dd0 2700 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
9fee9db5
SN		 2701
2702 cmd_resp->address = cpu_to_le32(reg_addr);
2703
2704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2705
2706 if (!status) {
7b115dd0
JB		 2707 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2708 (u64)le32_to_cpu(cmd_resp->value_low);
9fee9db5
SN		 2709 }
2710
2711 return status;
2712}
2713
53db45cd
SN		 2714/**
2715 * i40e_aq_debug_write_register
2716 * @hw: pointer to the hw struct
2717 * @reg_addr: register address
2718 * @reg_val: register value
2719 * @cmd_details: pointer to command details structure or NULL
2720 *
2721 * Write to a register using the admin queue commands
2722 **/
2723i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2724 u32 reg_addr, u64 reg_val,
2725 struct i40e_asq_cmd_details *cmd_details)
2726{
2727 struct i40e_aq_desc desc;
2728 struct i40e_aqc_debug_reg_read_write *cmd =
2729 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2730 i40e_status status;
2731
2732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2733
2734 cmd->address = cpu_to_le32(reg_addr);
2735 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2736 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2737
2738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2739
2740 return status;
2741}
2742
56a62fc8
JB		 2743/**
2744 * i40e_aq_set_hmc_resource_profile
2745 * @hw: pointer to the hw struct
2746 * @profile: type of profile the HMC is to be set as
2747 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2748 * @cmd_details: pointer to command details structure or NULL
2749 *
2750 * set the HMC profile of the device.
2751 **/
2752i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2753 enum i40e_aq_hmc_profile profile,
2754 u8 pe_vf_enabled_count,
2755 struct i40e_asq_cmd_details *cmd_details)
2756{
2757 struct i40e_aq_desc desc;
2758 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2759 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2760 i40e_status status;
2761
2762 i40e_fill_default_direct_cmd_desc(&desc,
2763 i40e_aqc_opc_set_hmc_resource_profile);
2764
2765 cmd->pm_profile = (u8)profile;
2766 cmd->pe_vf_enabled = pe_vf_enabled_count;
2767
2768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2769
2770 return status;
2771}
2772
2773/**
2774 * i40e_aq_request_resource
2775 * @hw: pointer to the hw struct
2776 * @resource: resource id
2777 * @access: access type
2778 * @sdp_number: resource number
2779 * @timeout: the maximum time in ms that the driver may hold the resource
2780 * @cmd_details: pointer to command details structure or NULL
2781 *
2782 * requests common resource using the admin queue commands
2783 **/
2784i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2785 enum i40e_aq_resources_ids resource,
2786 enum i40e_aq_resource_access_type access,
2787 u8 sdp_number, u64 *timeout,
2788 struct i40e_asq_cmd_details *cmd_details)
2789{
2790 struct i40e_aq_desc desc;
2791 struct i40e_aqc_request_resource *cmd_resp =
2792 (struct i40e_aqc_request_resource *)&desc.params.raw;
2793 i40e_status status;
2794
2795 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2796
2797 cmd_resp->resource_id = cpu_to_le16(resource);
2798 cmd_resp->access_type = cpu_to_le16(access);
2799 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2800
2801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2802 /* The completion specifies the maximum time in ms that the driver
2803 * may hold the resource in the Timeout field.
2804 * If the resource is held by someone else, the command completes with
2805 * busy return value and the timeout field indicates the maximum time
2806 * the current owner of the resource has to free it.
2807 */
2808 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2809 *timeout = le32_to_cpu(cmd_resp->timeout);
2810
2811 return status;
2812}
2813
2814/**
2815 * i40e_aq_release_resource
2816 * @hw: pointer to the hw struct
2817 * @resource: resource id
2818 * @sdp_number: resource number
2819 * @cmd_details: pointer to command details structure or NULL
2820 *
2821 * release common resource using the admin queue commands
2822 **/
2823i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2824 enum i40e_aq_resources_ids resource,
2825 u8 sdp_number,
2826 struct i40e_asq_cmd_details *cmd_details)
2827{
2828 struct i40e_aq_desc desc;
2829 struct i40e_aqc_request_resource *cmd =
2830 (struct i40e_aqc_request_resource *)&desc.params.raw;
2831 i40e_status status;
2832
2833 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2834
2835 cmd->resource_id = cpu_to_le16(resource);
2836 cmd->resource_number = cpu_to_le32(sdp_number);
2837
2838 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2839
2840 return status;
2841}
2842
2843/**
2844 * i40e_aq_read_nvm
2845 * @hw: pointer to the hw struct
2846 * @module_pointer: module pointer location in words from the NVM beginning
2847 * @offset: byte offset from the module beginning
2848 * @length: length of the section to be read (in bytes from the offset)
2849 * @data: command buffer (size [bytes] = length)
2850 * @last_command: tells if this is the last command in a series
2851 * @cmd_details: pointer to command details structure or NULL
2852 *
2853 * Read the NVM using the admin queue commands
2854 **/
2855i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2856 u32 offset, u16 length, void *data,
2857 bool last_command,
2858 struct i40e_asq_cmd_details *cmd_details)
2859{
2860 struct i40e_aq_desc desc;
2861 struct i40e_aqc_nvm_update *cmd =
2862 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2863 i40e_status status;
2864
2865 /* In offset the highest byte must be zeroed. */
2866 if (offset & 0xFF000000) {
2867 status = I40E_ERR_PARAM;
2868 goto i40e_aq_read_nvm_exit;
2869 }
2870
2871 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2872
2873 /* If this is the last command in a series, set the proper flag. */
2874 if (last_command)
2875 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2876 cmd->module_pointer = module_pointer;
2877 cmd->offset = cpu_to_le32(offset);
2878 cmd->length = cpu_to_le16(length);
2879
2880 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2881 if (length > I40E_AQ_LARGE_BUF)
2882 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2883
2884 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2885
2886i40e_aq_read_nvm_exit:
2887 return status;
2888}
2889
cd552cb4
SN		 2890/**
2891 * i40e_aq_erase_nvm
2892 * @hw: pointer to the hw struct
2893 * @module_pointer: module pointer location in words from the NVM beginning
2894 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2895 * @length: length of the section to be erased (expressed in 4 KB)
2896 * @last_command: tells if this is the last command in a series
2897 * @cmd_details: pointer to command details structure or NULL
2898 *
2899 * Erase the NVM sector using the admin queue commands
2900 **/
2901i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2902 u32 offset, u16 length, bool last_command,
2903 struct i40e_asq_cmd_details *cmd_details)
2904{
2905 struct i40e_aq_desc desc;
2906 struct i40e_aqc_nvm_update *cmd =
2907 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2908 i40e_status status;
2909
2910 /* In offset the highest byte must be zeroed. */
2911 if (offset & 0xFF000000) {
2912 status = I40E_ERR_PARAM;
2913 goto i40e_aq_erase_nvm_exit;
2914 }
2915
2916 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2917
2918 /* If this is the last command in a series, set the proper flag. */
2919 if (last_command)
2920 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2921 cmd->module_pointer = module_pointer;
2922 cmd->offset = cpu_to_le32(offset);
2923 cmd->length = cpu_to_le16(length);
2924
2925 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2926
2927i40e_aq_erase_nvm_exit:
2928 return status;
2929}
2930
56a62fc8
JB		 2931/**
2932 * i40e_parse_discover_capabilities
2933 * @hw: pointer to the hw struct
2934 * @buff: pointer to a buffer containing device/function capability records
2935 * @cap_count: number of capability records in the list
2936 * @list_type_opc: type of capabilities list to parse
2937 *
2938 * Parse the device/function capabilities list.
2939 **/
2940static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2941 u32 cap_count,
2942 enum i40e_admin_queue_opc list_type_opc)
2943{
2944 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 2945 u32 valid_functions, num_functions;
56a62fc8
JB		 2946 u32 number, logical_id, phys_id;
2947 struct i40e_hw_capabilities *p;
c78b953e 2948 u8 major_rev;
56a62fc8
JB		 2949 u32 i = 0;
2950 u16 id;
2951
2952 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2953
2954 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2955 p = &hw->dev_caps;
56a62fc8 2956 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2957 p = &hw->func_caps;
56a62fc8
JB		 2958 else
2959 return;
2960
2961 for (i = 0; i < cap_count; i++, cap++) {
2962 id = le16_to_cpu(cap->id);
2963 number = le32_to_cpu(cap->number);
2964 logical_id = le32_to_cpu(cap->logical_id);
2965 phys_id = le32_to_cpu(cap->phys_id);
c78b953e 2966 major_rev = cap->major_rev;
56a62fc8
JB		 2967
2968 switch (id) {
406e734a 2969 case I40E_AQ_CAP_ID_SWITCH_MODE:
56a62fc8
JB		 2970 p->switch_mode = number;
2971 break;
406e734a 2972 case I40E_AQ_CAP_ID_MNG_MODE:
56a62fc8
JB		 2973 p->management_mode = number;
2974 break;
406e734a 2975 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
56a62fc8
JB		 2976 p->npar_enable = number;
2977 break;
406e734a 2978 case I40E_AQ_CAP_ID_OS2BMC_CAP:
56a62fc8
JB		 2979 p->os2bmc = number;
2980 break;
406e734a 2981 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
56a62fc8
JB		 2982 p->valid_functions = number;
2983 break;
406e734a 2984 case I40E_AQ_CAP_ID_SRIOV:
56a62fc8
JB		 2985 if (number == 1)
2986 p->sr_iov_1_1 = true;
2987 break;
406e734a 2988 case I40E_AQ_CAP_ID_VF:
56a62fc8
JB		 2989 p->num_vfs = number;
2990 p->vf_base_id = logical_id;
2991 break;
406e734a 2992 case I40E_AQ_CAP_ID_VMDQ:
56a62fc8
JB		 2993 if (number == 1)
2994 p->vmdq = true;
2995 break;
406e734a 2996 case I40E_AQ_CAP_ID_8021QBG:
56a62fc8
JB		 2997 if (number == 1)
2998 p->evb_802_1_qbg = true;
2999 break;
406e734a 3000 case I40E_AQ_CAP_ID_8021QBR:
56a62fc8
JB		 3001 if (number == 1)
3002 p->evb_802_1_qbh = true;
3003 break;
406e734a 3004 case I40E_AQ_CAP_ID_VSI:
56a62fc8
JB		 3005 p->num_vsis = number;
3006 break;
406e734a 3007 case I40E_AQ_CAP_ID_DCB:
56a62fc8
JB		 3008 if (number == 1) {
3009 p->dcb = true;
3010 p->enabled_tcmap = logical_id;
3011 p->maxtc = phys_id;
3012 }
3013 break;
406e734a 3014 case I40E_AQ_CAP_ID_FCOE:
56a62fc8
JB		 3015 if (number == 1)
3016 p->fcoe = true;
3017 break;
406e734a 3018 case I40E_AQ_CAP_ID_ISCSI:
63d7e5a4
NP		 3019 if (number == 1)
3020 p->iscsi = true;
3021 break;
406e734a 3022 case I40E_AQ_CAP_ID_RSS:
56a62fc8 3023 p->rss = true;
e157ea30 3024 p->rss_table_size = number;
56a62fc8
JB		 3025 p->rss_table_entry_width = logical_id;
3026 break;
406e734a 3027 case I40E_AQ_CAP_ID_RXQ:
56a62fc8
JB		 3028 p->num_rx_qp = number;
3029 p->base_queue = phys_id;
3030 break;
406e734a 3031 case I40E_AQ_CAP_ID_TXQ:
56a62fc8
JB		 3032 p->num_tx_qp = number;
3033 p->base_queue = phys_id;
3034 break;
406e734a 3035 case I40E_AQ_CAP_ID_MSIX:
56a62fc8
JB		 3036 p->num_msix_vectors = number;
3037 break;
406e734a 3038 case I40E_AQ_CAP_ID_VF_MSIX:
56a62fc8
JB		 3039 p->num_msix_vectors_vf = number;
3040 break;
406e734a 3041 case I40E_AQ_CAP_ID_FLEX10:
c78b953e
PO		 3042 if (major_rev == 1) {
3043 if (number == 1) {
3044 p->flex10_enable = true;
3045 p->flex10_capable = true;
3046 }
3047 } else {
3048 /* Capability revision >= 2 */
3049 if (number & 1)
3050 p->flex10_enable = true;
3051 if (number & 2)
3052 p->flex10_capable = true;
3053 }
3054 p->flex10_mode = logical_id;
3055 p->flex10_status = phys_id;
56a62fc8 3056 break;
406e734a 3057 case I40E_AQ_CAP_ID_CEM:
56a62fc8
JB		 3058 if (number == 1)
3059 p->mgmt_cem = true;
3060 break;
406e734a 3061 case I40E_AQ_CAP_ID_IWARP:
56a62fc8
JB		 3062 if (number == 1)
3063 p->iwarp = true;
3064 break;
406e734a 3065 case I40E_AQ_CAP_ID_LED:
56a62fc8
JB		 3066 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3067 p->led[phys_id] = true;
3068 break;
406e734a 3069 case I40E_AQ_CAP_ID_SDP:
56a62fc8
JB		 3070 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3071 p->sdp[phys_id] = true;
3072 break;
406e734a 3073 case I40E_AQ_CAP_ID_MDIO:
56a62fc8
JB		 3074 if (number == 1) {
3075 p->mdio_port_num = phys_id;
3076 p->mdio_port_mode = logical_id;
3077 }
3078 break;
406e734a 3079 case I40E_AQ_CAP_ID_1588:
56a62fc8
JB		 3080 if (number == 1)
3081 p->ieee_1588 = true;
3082 break;
406e734a 3083 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
56a62fc8
JB		 3084 p->fd = true;
3085 p->fd_filters_guaranteed = number;
3086 p->fd_filters_best_effort = logical_id;
3087 break;
406e734a 3088 case I40E_AQ_CAP_ID_WSR_PROT:
73b23402
KS		 3089 p->wr_csr_prot = (u64)number;
3090 p->wr_csr_prot |= (u64)logical_id << 32;
3091 break;
56a62fc8
JB		 3092 default:
3093 break;
3094 }
3095 }
3096
f18ae100
VD		 3097 if (p->fcoe)
3098 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3099
566bb85d
VD		 3100 /* Software override ensuring FCoE is disabled if npar or mfp
3101 * mode because it is not supported in these modes.
3102 */
c78b953e 3103 if (p->npar_enable || p->flex10_enable)
566bb85d
VD		 3104 p->fcoe = false;
3105
9fee9db5
SN		 3106 /* count the enabled ports (aka the "not disabled" ports) */
3107 hw->num_ports = 0;
3108 for (i = 0; i < 4; i++) {
3109 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3110 u64 port_cfg = 0;
3111
3112 /* use AQ read to get the physical register offset instead
3113 * of the port relative offset
3114 */
3115 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3116 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3117 hw->num_ports++;
3118 }
3119
3120 valid_functions = p->valid_functions;
3121 num_functions = 0;
3122 while (valid_functions) {
3123 if (valid_functions & 1)
3124 num_functions++;
3125 valid_functions >>= 1;
3126 }
3127
3128 /* partition id is 1-based, and functions are evenly spread
3129 * across the ports as partitions
3130 */
3131 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3132 hw->num_partitions = num_functions / hw->num_ports;
3133
56a62fc8
JB		 3134 /* additional HW specific goodies that might
3135 * someday be HW version specific
3136 */
3137 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3138}
3139
3140/**
3141 * i40e_aq_discover_capabilities
3142 * @hw: pointer to the hw struct
3143 * @buff: a virtual buffer to hold the capabilities
3144 * @buff_size: Size of the virtual buffer
3145 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3146 * @list_type_opc: capabilities type to discover - pass in the command opcode
3147 * @cmd_details: pointer to command details structure or NULL
3148 *
3149 * Get the device capabilities descriptions from the firmware
3150 **/
3151i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3152 void *buff, u16 buff_size, u16 *data_size,
3153 enum i40e_admin_queue_opc list_type_opc,
3154 struct i40e_asq_cmd_details *cmd_details)
3155{
3156 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 3157 struct i40e_aq_desc desc;
8fb905b3 3158 i40e_status status = 0;
56a62fc8
JB		 3159
3160 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3161
3162 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3163 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3164 status = I40E_ERR_PARAM;
3165 goto exit;
3166 }
3167
3168 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3169
3170 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3171 if (buff_size > I40E_AQ_LARGE_BUF)
3172 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3173
3174 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3175 *data_size = le16_to_cpu(desc.datalen);
3176
3177 if (status)
3178 goto exit;
3179
3180 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3181 list_type_opc);
3182
3183exit:
3184 return status;
3185}
3186
cd552cb4
SN		 3187/**
3188 * i40e_aq_update_nvm
3189 * @hw: pointer to the hw struct
3190 * @module_pointer: module pointer location in words from the NVM beginning
3191 * @offset: byte offset from the module beginning
3192 * @length: length of the section to be written (in bytes from the offset)
3193 * @data: command buffer (size [bytes] = length)
3194 * @last_command: tells if this is the last command in a series
3195 * @cmd_details: pointer to command details structure or NULL
3196 *
3197 * Update the NVM using the admin queue commands
3198 **/
3199i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3200 u32 offset, u16 length, void *data,
3201 bool last_command,
3202 struct i40e_asq_cmd_details *cmd_details)
3203{
3204 struct i40e_aq_desc desc;
3205 struct i40e_aqc_nvm_update *cmd =
3206 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3207 i40e_status status;
3208
3209 /* In offset the highest byte must be zeroed. */
3210 if (offset & 0xFF000000) {
3211 status = I40E_ERR_PARAM;
3212 goto i40e_aq_update_nvm_exit;
3213 }
3214
3215 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3216
3217 /* If this is the last command in a series, set the proper flag. */
3218 if (last_command)
3219 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3220 cmd->module_pointer = module_pointer;
3221 cmd->offset = cpu_to_le32(offset);
3222 cmd->length = cpu_to_le16(length);
3223
3224 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3225 if (length > I40E_AQ_LARGE_BUF)
3226 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3227
3228 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3229
3230i40e_aq_update_nvm_exit:
3231 return status;
3232}
3233
56a62fc8
JB		 3234/**
3235 * i40e_aq_get_lldp_mib
3236 * @hw: pointer to the hw struct
3237 * @bridge_type: type of bridge requested
3238 * @mib_type: Local, Remote or both Local and Remote MIBs
3239 * @buff: pointer to a user supplied buffer to store the MIB block
3240 * @buff_size: size of the buffer (in bytes)
3241 * @local_len : length of the returned Local LLDP MIB
3242 * @remote_len: length of the returned Remote LLDP MIB
3243 * @cmd_details: pointer to command details structure or NULL
3244 *
3245 * Requests the complete LLDP MIB (entire packet).
3246 **/
3247i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3248 u8 mib_type, void *buff, u16 buff_size,
3249 u16 *local_len, u16 *remote_len,
3250 struct i40e_asq_cmd_details *cmd_details)
3251{
3252 struct i40e_aq_desc desc;
3253 struct i40e_aqc_lldp_get_mib *cmd =
3254 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3255 struct i40e_aqc_lldp_get_mib *resp =
3256 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3257 i40e_status status;
3258
3259 if (buff_size == 0 || !buff)
3260 return I40E_ERR_PARAM;
3261
3262 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3263 /* Indirect Command */
3264 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3265
3266 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3267 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3268 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3269
3270 desc.datalen = cpu_to_le16(buff_size);
3271
3272 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3273 if (buff_size > I40E_AQ_LARGE_BUF)
3274 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3275
3276 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3277 if (!status) {
3278 if (local_len != NULL)
3279 *local_len = le16_to_cpu(resp->local_len);
3280 if (remote_len != NULL)
3281 *remote_len = le16_to_cpu(resp->remote_len);
3282 }
3283
3284 return status;
3285}
3286
3287/**
3288 * i40e_aq_cfg_lldp_mib_change_event
3289 * @hw: pointer to the hw struct
3290 * @enable_update: Enable or Disable event posting
3291 * @cmd_details: pointer to command details structure or NULL
3292 *
3293 * Enable or Disable posting of an event on ARQ when LLDP MIB
3294 * associated with the interface changes
3295 **/
3296i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3297 bool enable_update,
3298 struct i40e_asq_cmd_details *cmd_details)
3299{
3300 struct i40e_aq_desc desc;
3301 struct i40e_aqc_lldp_update_mib *cmd =
3302 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3303 i40e_status status;
3304
3305 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3306
3307 if (!enable_update)
3308 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3309
3310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3311
3312 return status;
3313}
3314
3315/**
3316 * i40e_aq_stop_lldp
3317 * @hw: pointer to the hw struct
3318 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3319 * @cmd_details: pointer to command details structure or NULL
3320 *
3321 * Stop or Shutdown the embedded LLDP Agent
3322 **/
3323i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3324 struct i40e_asq_cmd_details *cmd_details)
3325{
3326 struct i40e_aq_desc desc;
3327 struct i40e_aqc_lldp_stop *cmd =
3328 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3329 i40e_status status;
3330
3331 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3332
3333 if (shutdown_agent)
3334 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3335
3336 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3337
3338 return status;
3339}
3340
3341/**
3342 * i40e_aq_start_lldp
3343 * @hw: pointer to the hw struct
3344 * @cmd_details: pointer to command details structure or NULL
3345 *
3346 * Start the embedded LLDP Agent on all ports.
3347 **/
3348i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3349 struct i40e_asq_cmd_details *cmd_details)
3350{
3351 struct i40e_aq_desc desc;
3352 struct i40e_aqc_lldp_start *cmd =
3353 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3354 i40e_status status;
3355
3356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3357
3358 cmd->command = I40E_AQ_LLDP_AGENT_START;
3359
3360 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3361
3362 return status;
3363}
3364
9fa61dd2
NP		 3365/**
3366 * i40e_aq_get_cee_dcb_config
3367 * @hw: pointer to the hw struct
3368 * @buff: response buffer that stores CEE operational configuration
3369 * @buff_size: size of the buffer passed
3370 * @cmd_details: pointer to command details structure or NULL
3371 *
3372 * Get CEE DCBX mode operational configuration from firmware
3373 **/
3374i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3375 void *buff, u16 buff_size,
3376 struct i40e_asq_cmd_details *cmd_details)
3377{
3378 struct i40e_aq_desc desc;
3379 i40e_status status;
3380
3381 if (buff_size == 0 || !buff)
3382 return I40E_ERR_PARAM;
3383
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3385
3386 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3387 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3388 cmd_details);
3389
3390 return status;
3391}
3392
a1c9a9d9
JK		 3393/**
3394 * i40e_aq_add_udp_tunnel
3395 * @hw: pointer to the hw struct
3396 * @udp_port: the UDP port to add
3397 * @header_len: length of the tunneling header length in DWords
3398 * @protocol_index: protocol index type
98d44381 3399 * @filter_index: pointer to filter index
a1c9a9d9
JK		 3400 * @cmd_details: pointer to command details structure or NULL
3401 **/
3402i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 3403 u16 udp_port, u8 protocol_index,
3404 u8 *filter_index,
a1c9a9d9
JK		 3405 struct i40e_asq_cmd_details *cmd_details)
3406{
3407 struct i40e_aq_desc desc;
3408 struct i40e_aqc_add_udp_tunnel *cmd =
3409 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3410 struct i40e_aqc_del_udp_tunnel_completion *resp =
3411 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3412 i40e_status status;
3413
3414 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3415
3416 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 3417 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 3418
3419 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3420
65d13461 3421 if (!status && filter_index)
a1c9a9d9
JK		 3422 *filter_index = resp->index;
3423
3424 return status;
3425}
3426
3427/**
3428 * i40e_aq_del_udp_tunnel
3429 * @hw: pointer to the hw struct
3430 * @index: filter index
3431 * @cmd_details: pointer to command details structure or NULL
3432 **/
3433i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3434 struct i40e_asq_cmd_details *cmd_details)
3435{
3436 struct i40e_aq_desc desc;
3437 struct i40e_aqc_remove_udp_tunnel *cmd =
3438 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3439 i40e_status status;
3440
3441 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3442
3443 cmd->index = index;
3444
3445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3446
3447 return status;
3448}
3449
56a62fc8
JB		 3450/**
3451 * i40e_aq_delete_element - Delete switch element
3452 * @hw: pointer to the hw struct
3453 * @seid: the SEID to delete from the switch
3454 * @cmd_details: pointer to command details structure or NULL
3455 *
3456 * This deletes a switch element from the switch.
3457 **/
3458i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3459 struct i40e_asq_cmd_details *cmd_details)
3460{
3461 struct i40e_aq_desc desc;
3462 struct i40e_aqc_switch_seid *cmd =
3463 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3464 i40e_status status;
3465
3466 if (seid == 0)
3467 return I40E_ERR_PARAM;
3468
3469 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3470
3471 cmd->seid = cpu_to_le16(seid);
3472
3473 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3474
3475 return status;
3476}
3477
afb3ff0d
NP		 3478/**
3479 * i40e_aq_dcb_updated - DCB Updated Command
3480 * @hw: pointer to the hw struct
3481 * @cmd_details: pointer to command details structure or NULL
3482 *
3483 * EMP will return when the shared RPB settings have been
3484 * recomputed and modified. The retval field in the descriptor
3485 * will be set to 0 when RPB is modified.
3486 **/
3487i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3488 struct i40e_asq_cmd_details *cmd_details)
3489{
3490 struct i40e_aq_desc desc;
3491 i40e_status status;
3492
3493 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3494
3495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3496
3497 return status;
3498}
3499
56a62fc8
JB		 3500/**
3501 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3502 * @hw: pointer to the hw struct
3503 * @seid: seid for the physical port/switching component/vsi
3504 * @buff: Indirect buffer to hold data parameters and response
3505 * @buff_size: Indirect buffer size
3506 * @opcode: Tx scheduler AQ command opcode
3507 * @cmd_details: pointer to command details structure or NULL
3508 *
3509 * Generic command handler for Tx scheduler AQ commands
3510 **/
3511static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3512 void *buff, u16 buff_size,
3513 enum i40e_admin_queue_opc opcode,
3514 struct i40e_asq_cmd_details *cmd_details)
3515{
3516 struct i40e_aq_desc desc;
3517 struct i40e_aqc_tx_sched_ind *cmd =
3518 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3519 i40e_status status;
3520 bool cmd_param_flag = false;
3521
3522 switch (opcode) {
3523 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3524 case i40e_aqc_opc_configure_vsi_tc_bw:
3525 case i40e_aqc_opc_enable_switching_comp_ets:
3526 case i40e_aqc_opc_modify_switching_comp_ets:
3527 case i40e_aqc_opc_disable_switching_comp_ets:
3528 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3529 case i40e_aqc_opc_configure_switching_comp_bw_config:
3530 cmd_param_flag = true;
3531 break;
3532 case i40e_aqc_opc_query_vsi_bw_config:
3533 case i40e_aqc_opc_query_vsi_ets_sla_config:
3534 case i40e_aqc_opc_query_switching_comp_ets_config:
3535 case i40e_aqc_opc_query_port_ets_config:
3536 case i40e_aqc_opc_query_switching_comp_bw_config:
3537 cmd_param_flag = false;
3538 break;
3539 default:
3540 return I40E_ERR_PARAM;
3541 }
3542
3543 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3544
3545 /* Indirect command */
3546 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3547 if (cmd_param_flag)
3548 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3549 if (buff_size > I40E_AQ_LARGE_BUF)
3550 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3551
3552 desc.datalen = cpu_to_le16(buff_size);
3553
3554 cmd->vsi_seid = cpu_to_le16(seid);
3555
3556 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3557
3558 return status;
3559}
3560
6b192891
MW		 3561/**
3562 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3563 * @hw: pointer to the hw struct
3564 * @seid: VSI seid
3565 * @credit: BW limit credits (0 = disabled)
3566 * @max_credit: Max BW limit credits
3567 * @cmd_details: pointer to command details structure or NULL
3568 **/
3569i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3570 u16 seid, u16 credit, u8 max_credit,
3571 struct i40e_asq_cmd_details *cmd_details)
3572{
3573 struct i40e_aq_desc desc;
3574 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3575 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3576 i40e_status status;
3577
3578 i40e_fill_default_direct_cmd_desc(&desc,
3579 i40e_aqc_opc_configure_vsi_bw_limit);
3580
3581 cmd->vsi_seid = cpu_to_le16(seid);
3582 cmd->credit = cpu_to_le16(credit);
3583 cmd->max_credit = max_credit;
3584
3585 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3586
3587 return status;
3588}
3589
56a62fc8
JB		 3590/**
3591 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3592 * @hw: pointer to the hw struct
3593 * @seid: VSI seid
3594 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3595 * @cmd_details: pointer to command details structure or NULL
3596 **/
3597i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3598 u16 seid,
3599 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3600 struct i40e_asq_cmd_details *cmd_details)
3601{
3602 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3603 i40e_aqc_opc_configure_vsi_tc_bw,
3604 cmd_details);
3605}
3606
afb3ff0d
NP		 3607/**
3608 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3609 * @hw: pointer to the hw struct
3610 * @seid: seid of the switching component connected to Physical Port
3611 * @ets_data: Buffer holding ETS parameters
3612 * @cmd_details: pointer to command details structure or NULL
3613 **/
3614i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3615 u16 seid,
3616 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3617 enum i40e_admin_queue_opc opcode,
3618 struct i40e_asq_cmd_details *cmd_details)
3619{
3620 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3621 sizeof(*ets_data), opcode, cmd_details);
3622}
3623
3624/**
3625 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3626 * @hw: pointer to the hw struct
3627 * @seid: seid of the switching component
3628 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3629 * @cmd_details: pointer to command details structure or NULL
3630 **/
3631i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3632 u16 seid,
3633 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3634 struct i40e_asq_cmd_details *cmd_details)
3635{
3636 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3637 i40e_aqc_opc_configure_switching_comp_bw_config,
3638 cmd_details);
3639}
3640
56a62fc8
JB		 3641/**
3642 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3643 * @hw: pointer to the hw struct
3644 * @seid: seid of the VSI
3645 * @bw_data: Buffer to hold VSI BW configuration
3646 * @cmd_details: pointer to command details structure or NULL
3647 **/
3648i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3649 u16 seid,
3650 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3651 struct i40e_asq_cmd_details *cmd_details)
3652{
3653 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3654 i40e_aqc_opc_query_vsi_bw_config,
3655 cmd_details);
3656}
3657
3658/**
3659 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3660 * @hw: pointer to the hw struct
3661 * @seid: seid of the VSI
3662 * @bw_data: Buffer to hold VSI BW configuration per TC
3663 * @cmd_details: pointer to command details structure or NULL
3664 **/
3665i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3666 u16 seid,
3667 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3668 struct i40e_asq_cmd_details *cmd_details)
3669{
3670 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3671 i40e_aqc_opc_query_vsi_ets_sla_config,
3672 cmd_details);
3673}
3674
3675/**
3676 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3677 * @hw: pointer to the hw struct
3678 * @seid: seid of the switching component
3679 * @bw_data: Buffer to hold switching component's per TC BW config
3680 * @cmd_details: pointer to command details structure or NULL
3681 **/
3682i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3683 u16 seid,
3684 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3685 struct i40e_asq_cmd_details *cmd_details)
3686{
3687 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3688 i40e_aqc_opc_query_switching_comp_ets_config,
3689 cmd_details);
3690}
3691
3692/**
3693 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3694 * @hw: pointer to the hw struct
3695 * @seid: seid of the VSI or switching component connected to Physical Port
3696 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3697 * @cmd_details: pointer to command details structure or NULL
3698 **/
3699i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3700 u16 seid,
3701 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3702 struct i40e_asq_cmd_details *cmd_details)
3703{
3704 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3705 i40e_aqc_opc_query_port_ets_config,
3706 cmd_details);
3707}
3708
3709/**
3710 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3711 * @hw: pointer to the hw struct
3712 * @seid: seid of the switching component
3713 * @bw_data: Buffer to hold switching component's BW configuration
3714 * @cmd_details: pointer to command details structure or NULL
3715 **/
3716i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3717 u16 seid,
3718 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3719 struct i40e_asq_cmd_details *cmd_details)
3720{
3721 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3722 i40e_aqc_opc_query_switching_comp_bw_config,
3723 cmd_details);
3724}
3725
3726/**
3727 * i40e_validate_filter_settings
3728 * @hw: pointer to the hardware structure
3729 * @settings: Filter control settings
3730 *
3731 * Check and validate the filter control settings passed.
3732 * The function checks for the valid filter/context sizes being
3733 * passed for FCoE and PE.
3734 *
3735 * Returns 0 if the values passed are valid and within
3736 * range else returns an error.
3737 **/
3738static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3739 struct i40e_filter_control_settings *settings)
3740{
3741 u32 fcoe_cntx_size, fcoe_filt_size;
3742 u32 pe_cntx_size, pe_filt_size;
467d729a 3743 u32 fcoe_fmax;
56a62fc8
JB		 3744 u32 val;
3745
3746 /* Validate FCoE settings passed */
3747 switch (settings->fcoe_filt_num) {
3748 case I40E_HASH_FILTER_SIZE_1K:
3749 case I40E_HASH_FILTER_SIZE_2K:
3750 case I40E_HASH_FILTER_SIZE_4K:
3751 case I40E_HASH_FILTER_SIZE_8K:
3752 case I40E_HASH_FILTER_SIZE_16K:
3753 case I40E_HASH_FILTER_SIZE_32K:
3754 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3755 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3756 break;
3757 default:
3758 return I40E_ERR_PARAM;
3759 }
3760
3761 switch (settings->fcoe_cntx_num) {
3762 case I40E_DMA_CNTX_SIZE_512:
3763 case I40E_DMA_CNTX_SIZE_1K:
3764 case I40E_DMA_CNTX_SIZE_2K:
3765 case I40E_DMA_CNTX_SIZE_4K:
3766 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3767 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3768 break;
3769 default:
3770 return I40E_ERR_PARAM;
3771 }
3772
3773 /* Validate PE settings passed */
3774 switch (settings->pe_filt_num) {
3775 case I40E_HASH_FILTER_SIZE_1K:
3776 case I40E_HASH_FILTER_SIZE_2K:
3777 case I40E_HASH_FILTER_SIZE_4K:
3778 case I40E_HASH_FILTER_SIZE_8K:
3779 case I40E_HASH_FILTER_SIZE_16K:
3780 case I40E_HASH_FILTER_SIZE_32K:
3781 case I40E_HASH_FILTER_SIZE_64K:
3782 case I40E_HASH_FILTER_SIZE_128K:
3783 case I40E_HASH_FILTER_SIZE_256K:
3784 case I40E_HASH_FILTER_SIZE_512K:
3785 case I40E_HASH_FILTER_SIZE_1M:
3786 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3787 pe_filt_size <<= (u32)settings->pe_filt_num;
3788 break;
3789 default:
3790 return I40E_ERR_PARAM;
3791 }
3792
3793 switch (settings->pe_cntx_num) {
3794 case I40E_DMA_CNTX_SIZE_512:
3795 case I40E_DMA_CNTX_SIZE_1K:
3796 case I40E_DMA_CNTX_SIZE_2K:
3797 case I40E_DMA_CNTX_SIZE_4K:
3798 case I40E_DMA_CNTX_SIZE_8K:
3799 case I40E_DMA_CNTX_SIZE_16K:
3800 case I40E_DMA_CNTX_SIZE_32K:
3801 case I40E_DMA_CNTX_SIZE_64K:
3802 case I40E_DMA_CNTX_SIZE_128K:
3803 case I40E_DMA_CNTX_SIZE_256K:
3804 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3805 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3806 break;
3807 default:
3808 return I40E_ERR_PARAM;
3809 }
3810
3811 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3812 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3813 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3814 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3815 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3816 return I40E_ERR_INVALID_SIZE;
3817
56a62fc8
JB		 3818 return 0;
3819}
3820
3821/**
3822 * i40e_set_filter_control
3823 * @hw: pointer to the hardware structure
3824 * @settings: Filter control settings
3825 *
3826 * Set the Queue Filters for PE/FCoE and enable filters required
3827 * for a single PF. It is expected that these settings are programmed
3828 * at the driver initialization time.
3829 **/
3830i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3831 struct i40e_filter_control_settings *settings)
3832{
3833 i40e_status ret = 0;
3834 u32 hash_lut_size = 0;
3835 u32 val;
3836
3837 if (!settings)
3838 return I40E_ERR_PARAM;
3839
3840 /* Validate the input settings */
3841 ret = i40e_validate_filter_settings(hw, settings);
3842 if (ret)
3843 return ret;
3844
3845 /* Read the PF Queue Filter control register */
3846 val = rd32(hw, I40E_PFQF_CTL_0);
3847
3848 /* Program required PE hash buckets for the PF */
3849 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3850 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3851 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3852 /* Program required PE contexts for the PF */
3853 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3854 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3855 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3856
3857 /* Program required FCoE hash buckets for the PF */
3858 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3859 val |= ((u32)settings->fcoe_filt_num <<
3860 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3861 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3862 /* Program required FCoE DDP contexts for the PF */
3863 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3864 val |= ((u32)settings->fcoe_cntx_num <<
3865 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3866 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3867
3868 /* Program Hash LUT size for the PF */
3869 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3870 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3871 hash_lut_size = 1;
3872 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3873 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3874
3875 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3876 if (settings->enable_fdir)
3877 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3878 if (settings->enable_ethtype)
3879 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3880 if (settings->enable_macvlan)
3881 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3882
3883 wr32(hw, I40E_PFQF_CTL_0, val);
3884
3885 return 0;
3886}
afb3ff0d
NP		 3887
3888/**
3889 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3890 * @hw: pointer to the hw struct
3891 * @mac_addr: MAC address to use in the filter
3892 * @ethtype: Ethertype to use in the filter
3893 * @flags: Flags that needs to be applied to the filter
3894 * @vsi_seid: seid of the control VSI
3895 * @queue: VSI queue number to send the packet to
3896 * @is_add: Add control packet filter if True else remove
3897 * @stats: Structure to hold information on control filter counts
3898 * @cmd_details: pointer to command details structure or NULL
3899 *
3900 * This command will Add or Remove control packet filter for a control VSI.
3901 * In return it will update the total number of perfect filter count in
3902 * the stats member.
3903 **/
3904i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3905 u8 *mac_addr, u16 ethtype, u16 flags,
3906 u16 vsi_seid, u16 queue, bool is_add,
3907 struct i40e_control_filter_stats *stats,
3908 struct i40e_asq_cmd_details *cmd_details)
3909{
3910 struct i40e_aq_desc desc;
3911 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3912 (struct i40e_aqc_add_remove_control_packet_filter *)
3913 &desc.params.raw;
3914 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3915 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3916 &desc.params.raw;
3917 i40e_status status;
3918
3919 if (vsi_seid == 0)
3920 return I40E_ERR_PARAM;
3921
3922 if (is_add) {
3923 i40e_fill_default_direct_cmd_desc(&desc,
3924 i40e_aqc_opc_add_control_packet_filter);
3925 cmd->queue = cpu_to_le16(queue);
3926 } else {
3927 i40e_fill_default_direct_cmd_desc(&desc,
3928 i40e_aqc_opc_remove_control_packet_filter);
3929 }
3930
3931 if (mac_addr)
6995b36c 3932 ether_addr_copy(cmd->mac, mac_addr);
afb3ff0d
NP		 3933
3934 cmd->etype = cpu_to_le16(ethtype);
3935 cmd->flags = cpu_to_le16(flags);
3936 cmd->seid = cpu_to_le16(vsi_seid);
3937
3938 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3939
3940 if (!status && stats) {
3941 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3942 stats->etype_used = le16_to_cpu(resp->etype_used);
3943 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3944 stats->etype_free = le16_to_cpu(resp->etype_free);
3945 }
3946
3947 return status;
3948}
3949
e7358f54
ASJ		 3950/**
3951 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3952 * @hw: pointer to the hw struct
3953 * @seid: VSI seid to add ethertype filter from
3954 **/
3955#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3956void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3957 u16 seid)
3958{
3959 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3960 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
3961 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
3962 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
3963 i40e_status status;
3964
3965 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
3966 seid, 0, true, NULL,
3967 NULL);
3968 if (status)
3969 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3970}
3971
f4492db1
GR		 3972/**
3973 * i40e_aq_alternate_read
3974 * @hw: pointer to the hardware structure
3975 * @reg_addr0: address of first dword to be read
3976 * @reg_val0: pointer for data read from 'reg_addr0'
3977 * @reg_addr1: address of second dword to be read
3978 * @reg_val1: pointer for data read from 'reg_addr1'
3979 *
3980 * Read one or two dwords from alternate structure. Fields are indicated
3981 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3982 * is not passed then only register at 'reg_addr0' is read.
3983 *
3984 **/
37a2973a
SN		 3985static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3986 u32 reg_addr0, u32 *reg_val0,
3987 u32 reg_addr1, u32 *reg_val1)
f4492db1
GR		 3988{
3989 struct i40e_aq_desc desc;
3990 struct i40e_aqc_alternate_write *cmd_resp =
3991 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3992 i40e_status status;
3993
3994 if (!reg_val0)
3995 return I40E_ERR_PARAM;
3996
3997 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3998 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3999 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4000
4001 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4002
4003 if (!status) {
4004 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4005
4006 if (reg_val1)
4007 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4008 }
4009
4010 return status;
4011}
4012
2fd75f31
NP		 4013/**
4014 * i40e_aq_resume_port_tx
4015 * @hw: pointer to the hardware structure
4016 * @cmd_details: pointer to command details structure or NULL
4017 *
4018 * Resume port's Tx traffic
4019 **/
4020i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4021 struct i40e_asq_cmd_details *cmd_details)
4022{
4023 struct i40e_aq_desc desc;
4024 i40e_status status;
4025
4026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4027
4028 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4029
4030 return status;
4031}
4032
d4dfb81a
CS		 4033/**
4034 * i40e_set_pci_config_data - store PCI bus info
4035 * @hw: pointer to hardware structure
4036 * @link_status: the link status word from PCI config space
4037 *
4038 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4039 **/
4040void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4041{
4042 hw->bus.type = i40e_bus_type_pci_express;
4043
4044 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4045 case PCI_EXP_LNKSTA_NLW_X1:
4046 hw->bus.width = i40e_bus_width_pcie_x1;
4047 break;
4048 case PCI_EXP_LNKSTA_NLW_X2:
4049 hw->bus.width = i40e_bus_width_pcie_x2;
4050 break;
4051 case PCI_EXP_LNKSTA_NLW_X4:
4052 hw->bus.width = i40e_bus_width_pcie_x4;
4053 break;
4054 case PCI_EXP_LNKSTA_NLW_X8:
4055 hw->bus.width = i40e_bus_width_pcie_x8;
4056 break;
4057 default:
4058 hw->bus.width = i40e_bus_width_unknown;
4059 break;
4060 }
4061
4062 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4063 case PCI_EXP_LNKSTA_CLS_2_5GB:
4064 hw->bus.speed = i40e_bus_speed_2500;
4065 break;
4066 case PCI_EXP_LNKSTA_CLS_5_0GB:
4067 hw->bus.speed = i40e_bus_speed_5000;
4068 break;
4069 case PCI_EXP_LNKSTA_CLS_8_0GB:
4070 hw->bus.speed = i40e_bus_speed_8000;
4071 break;
4072 default:
4073 hw->bus.speed = i40e_bus_speed_unknown;
4074 break;
4075 }
4076}
f4492db1 4077
3169c323
JB		 4078/**
4079 * i40e_aq_debug_dump
4080 * @hw: pointer to the hardware structure
4081 * @cluster_id: specific cluster to dump
4082 * @table_id: table id within cluster
4083 * @start_index: index of line in the block to read
4084 * @buff_size: dump buffer size
4085 * @buff: dump buffer
4086 * @ret_buff_size: actual buffer size returned
4087 * @ret_next_table: next block to read
4088 * @ret_next_index: next index to read
4089 *
4090 * Dump internal FW/HW data for debug purposes.
4091 *
4092 **/
4093i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4094 u8 table_id, u32 start_index, u16 buff_size,
4095 void *buff, u16 *ret_buff_size,
4096 u8 *ret_next_table, u32 *ret_next_index,
4097 struct i40e_asq_cmd_details *cmd_details)
4098{
4099 struct i40e_aq_desc desc;
4100 struct i40e_aqc_debug_dump_internals *cmd =
4101 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4102 struct i40e_aqc_debug_dump_internals *resp =
4103 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4104 i40e_status status;
4105
4106 if (buff_size == 0 || !buff)
4107 return I40E_ERR_PARAM;
4108
4109 i40e_fill_default_direct_cmd_desc(&desc,
4110 i40e_aqc_opc_debug_dump_internals);
4111 /* Indirect Command */
4112 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4113 if (buff_size > I40E_AQ_LARGE_BUF)
4114 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4115
4116 cmd->cluster_id = cluster_id;
4117 cmd->table_id = table_id;
4118 cmd->idx = cpu_to_le32(start_index);
4119
4120 desc.datalen = cpu_to_le16(buff_size);
4121
4122 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4123 if (!status) {
4124 if (ret_buff_size)
4125 *ret_buff_size = le16_to_cpu(desc.datalen);
4126 if (ret_next_table)
4127 *ret_next_table = resp->table_id;
4128 if (ret_next_index)
4129 *ret_next_index = le32_to_cpu(resp->idx);
4130 }
4131
4132 return status;
4133}
4134
f4492db1
GR		 4135/**
4136 * i40e_read_bw_from_alt_ram
4137 * @hw: pointer to the hardware structure
4138 * @max_bw: pointer for max_bw read
4139 * @min_bw: pointer for min_bw read
4140 * @min_valid: pointer for bool that is true if min_bw is a valid value
4141 * @max_valid: pointer for bool that is true if max_bw is a valid value
4142 *
4143 * Read bw from the alternate ram for the given pf
4144 **/
4145i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4146 u32 *max_bw, u32 *min_bw,
4147 bool *min_valid, bool *max_valid)
4148{
4149 i40e_status status;
4150 u32 max_bw_addr, min_bw_addr;
4151
4152 /* Calculate the address of the min/max bw registers */
4153 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4154 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4155 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4156 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4157 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4158 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4159
4160 /* Read the bandwidths from alt ram */
4161 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4162 min_bw_addr, min_bw);
4163
4164 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4165 *min_valid = true;
4166 else
4167 *min_valid = false;
4168
4169 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4170 *max_valid = true;
4171 else
4172 *max_valid = false;
4173
4174 return status;
4175}
4176
4177/**
4178 * i40e_aq_configure_partition_bw
4179 * @hw: pointer to the hardware structure
4180 * @bw_data: Buffer holding valid pfs and bw limits
4181 * @cmd_details: pointer to command details
4182 *
4183 * Configure partitions guaranteed/max bw
4184 **/
4185i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4186 struct i40e_aqc_configure_partition_bw_data *bw_data,
4187 struct i40e_asq_cmd_details *cmd_details)
4188{
4189 i40e_status status;
4190 struct i40e_aq_desc desc;
4191 u16 bwd_size = sizeof(*bw_data);
4192
4193 i40e_fill_default_direct_cmd_desc(&desc,
4194 i40e_aqc_opc_configure_partition_bw);
4195
4196 /* Indirect command */
4197 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4198 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4199
4200 if (bwd_size > I40E_AQ_LARGE_BUF)
4201 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4202
4203 desc.datalen = cpu_to_le16(bwd_size);
4204
4205 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4206 cmd_details);
4207
4208 return status;
4209}
Linux kernel - Deliverables
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