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mlx4_en: Convert the normal skb free path to dev_consume_skb_any()
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 53 hw->mac.type = I40E_MAC_XL710;
54 break;
ab60085e
SN		 55 case I40E_DEV_ID_VF:
56 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 57 hw->mac.type = I40E_MAC_VF;
58 break;
59 default:
60 hw->mac.type = I40E_MAC_GENERIC;
61 break;
62 }
63 } else {
64 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
65 }
66
67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw->mac.type, status);
69 return status;
70}
71
72/**
73 * i40e_debug_aq
74 * @hw: debug mask related to admin queue
98d44381
JK		 75 * @mask: debug mask
76 * @desc: pointer to admin queue descriptor
56a62fc8 77 * @buffer: pointer to command buffer
f905dd62 78 * @buf_len: max length of buffer
56a62fc8
JB		 79 *
80 * Dumps debug log about adminq command with descriptor contents.
81 **/
82void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 83 void *buffer, u16 buf_len)
56a62fc8
JB		 84{
85 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 86 u16 len = le16_to_cpu(aq_desc->datalen);
56a62fc8
JB		 87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 110 if (buf_len < len)
111 len = buf_len;
112 for (i = 0; i < len; i++) {
56a62fc8
JB		 113 data[((i % 16) / 4)] |=
114 ((u32)aq_buffer[i]) << (8 * (i % 4));
115 if ((i % 16) == 15) {
116 i40e_debug(hw, mask,
117 "\t0x%04X %08X %08X %08X %08X\n",
118 i - 15, data[0], data[1], data[2],
119 data[3]);
120 memset(data, 0, sizeof(data));
121 }
122 }
123 if ((i % 16) != 0)
124 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
125 i - (i % 16), data[0], data[1], data[2],
126 data[3]);
127 }
128}
129
e1860d8f
ASJ		 130/**
131 * i40e_check_asq_alive
132 * @hw: pointer to the hw struct
133 *
134 * Returns true if Queue is enabled else false.
135 **/
136bool i40e_check_asq_alive(struct i40e_hw *hw)
137{
8b833b4f
KS		 138 if (hw->aq.asq.len)
139 return !!(rd32(hw, hw->aq.asq.len) &
140 I40E_PF_ATQLEN_ATQENABLE_MASK);
141 else
142 return false;
e1860d8f
ASJ		 143}
144
145/**
146 * i40e_aq_queue_shutdown
147 * @hw: pointer to the hw struct
148 * @unloading: is the driver unloading itself
149 *
150 * Tell the Firmware that we're shutting down the AdminQ and whether
151 * or not the driver is unloading as well.
152 **/
153i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
154 bool unloading)
155{
156 struct i40e_aq_desc desc;
157 struct i40e_aqc_queue_shutdown *cmd =
158 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
159 i40e_status status;
160
161 i40e_fill_default_direct_cmd_desc(&desc,
162 i40e_aqc_opc_queue_shutdown);
163
164 if (unloading)
165 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
166 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
167
168 return status;
169}
170
206812b5
JB		 171/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
172 * hardware to a bit-field that can be used by SW to more easily determine the
173 * packet type.
174 *
175 * Macros are used to shorten the table lines and make this table human
176 * readable.
177 *
178 * We store the PTYPE in the top byte of the bit field - this is just so that
179 * we can check that the table doesn't have a row missing, as the index into
180 * the table should be the PTYPE.
181 *
182 * Typical work flow:
183 *
184 * IF NOT i40e_ptype_lookup[ptype].known
185 * THEN
186 * Packet is unknown
187 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
188 * Use the rest of the fields to look at the tunnels, inner protocols, etc
189 * ELSE
190 * Use the enum i40e_rx_l2_ptype to decode the packet type
191 * ENDIF
192 */
193
194/* macro to make the table lines short */
195#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
196 { PTYPE, \
197 1, \
198 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
200 I40E_RX_PTYPE_##OUTER_FRAG, \
201 I40E_RX_PTYPE_TUNNEL_##T, \
202 I40E_RX_PTYPE_TUNNEL_END_##TE, \
203 I40E_RX_PTYPE_##TEF, \
204 I40E_RX_PTYPE_INNER_PROT_##I, \
205 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
206
207#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
208 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
209
210/* shorter macros makes the table fit but are terse */
211#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
212#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
213#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
214
215/* Lookup table mapping the HW PTYPE to the bit field for decoding */
216struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
217 /* L2 Packet types */
218 I40E_PTT_UNUSED_ENTRY(0),
219 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
220 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
221 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
222 I40E_PTT_UNUSED_ENTRY(4),
223 I40E_PTT_UNUSED_ENTRY(5),
224 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
225 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
226 I40E_PTT_UNUSED_ENTRY(8),
227 I40E_PTT_UNUSED_ENTRY(9),
228 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
229 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
230 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240
241 /* Non Tunneled IPv4 */
242 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
243 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
245 I40E_PTT_UNUSED_ENTRY(25),
246 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
247 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
248 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
249
250 /* IPv4 --> IPv4 */
251 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
252 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
253 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
254 I40E_PTT_UNUSED_ENTRY(32),
255 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
256 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
257 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
258
259 /* IPv4 --> IPv6 */
260 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
261 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
262 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
263 I40E_PTT_UNUSED_ENTRY(39),
264 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
265 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
266 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
267
268 /* IPv4 --> GRE/NAT */
269 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
270
271 /* IPv4 --> GRE/NAT --> IPv4 */
272 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
273 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
274 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
275 I40E_PTT_UNUSED_ENTRY(47),
276 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
277 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
278 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
279
280 /* IPv4 --> GRE/NAT --> IPv6 */
281 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
282 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
283 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
284 I40E_PTT_UNUSED_ENTRY(54),
285 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
286 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
287 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
288
289 /* IPv4 --> GRE/NAT --> MAC */
290 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
291
292 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
293 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
294 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
295 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
296 I40E_PTT_UNUSED_ENTRY(62),
297 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
298 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
299 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
300
301 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
302 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
303 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
304 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
305 I40E_PTT_UNUSED_ENTRY(69),
306 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
307 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
308 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
309
310 /* IPv4 --> GRE/NAT --> MAC/VLAN */
311 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
312
313 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
314 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
315 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
316 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
317 I40E_PTT_UNUSED_ENTRY(77),
318 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
319 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
320 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
321
322 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
323 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
324 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
325 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
326 I40E_PTT_UNUSED_ENTRY(84),
327 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
328 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
329 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
330
331 /* Non Tunneled IPv6 */
332 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
333 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
334 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
335 I40E_PTT_UNUSED_ENTRY(91),
336 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
337 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
338 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
339
340 /* IPv6 --> IPv4 */
341 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
342 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
343 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
344 I40E_PTT_UNUSED_ENTRY(98),
345 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
346 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
347 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
348
349 /* IPv6 --> IPv6 */
350 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
351 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
352 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
353 I40E_PTT_UNUSED_ENTRY(105),
354 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
355 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
356 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
357
358 /* IPv6 --> GRE/NAT */
359 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
360
361 /* IPv6 --> GRE/NAT -> IPv4 */
362 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
363 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
364 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
365 I40E_PTT_UNUSED_ENTRY(113),
366 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
367 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
368 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
369
370 /* IPv6 --> GRE/NAT -> IPv6 */
371 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
372 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
373 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
374 I40E_PTT_UNUSED_ENTRY(120),
375 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
376 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
377 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
378
379 /* IPv6 --> GRE/NAT -> MAC */
380 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
381
382 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
383 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
384 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
385 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
386 I40E_PTT_UNUSED_ENTRY(128),
387 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
388 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
389 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
390
391 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
392 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
393 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
394 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
395 I40E_PTT_UNUSED_ENTRY(135),
396 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
397 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
398 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
399
400 /* IPv6 --> GRE/NAT -> MAC/VLAN */
401 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
402
403 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
404 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
405 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
406 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
407 I40E_PTT_UNUSED_ENTRY(143),
408 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
409 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
410 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
411
412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
413 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
414 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
415 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
416 I40E_PTT_UNUSED_ENTRY(150),
417 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
418 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
419 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
420
421 /* unused entries */
422 I40E_PTT_UNUSED_ENTRY(154),
423 I40E_PTT_UNUSED_ENTRY(155),
424 I40E_PTT_UNUSED_ENTRY(156),
425 I40E_PTT_UNUSED_ENTRY(157),
426 I40E_PTT_UNUSED_ENTRY(158),
427 I40E_PTT_UNUSED_ENTRY(159),
428
429 I40E_PTT_UNUSED_ENTRY(160),
430 I40E_PTT_UNUSED_ENTRY(161),
431 I40E_PTT_UNUSED_ENTRY(162),
432 I40E_PTT_UNUSED_ENTRY(163),
433 I40E_PTT_UNUSED_ENTRY(164),
434 I40E_PTT_UNUSED_ENTRY(165),
435 I40E_PTT_UNUSED_ENTRY(166),
436 I40E_PTT_UNUSED_ENTRY(167),
437 I40E_PTT_UNUSED_ENTRY(168),
438 I40E_PTT_UNUSED_ENTRY(169),
439
440 I40E_PTT_UNUSED_ENTRY(170),
441 I40E_PTT_UNUSED_ENTRY(171),
442 I40E_PTT_UNUSED_ENTRY(172),
443 I40E_PTT_UNUSED_ENTRY(173),
444 I40E_PTT_UNUSED_ENTRY(174),
445 I40E_PTT_UNUSED_ENTRY(175),
446 I40E_PTT_UNUSED_ENTRY(176),
447 I40E_PTT_UNUSED_ENTRY(177),
448 I40E_PTT_UNUSED_ENTRY(178),
449 I40E_PTT_UNUSED_ENTRY(179),
450
451 I40E_PTT_UNUSED_ENTRY(180),
452 I40E_PTT_UNUSED_ENTRY(181),
453 I40E_PTT_UNUSED_ENTRY(182),
454 I40E_PTT_UNUSED_ENTRY(183),
455 I40E_PTT_UNUSED_ENTRY(184),
456 I40E_PTT_UNUSED_ENTRY(185),
457 I40E_PTT_UNUSED_ENTRY(186),
458 I40E_PTT_UNUSED_ENTRY(187),
459 I40E_PTT_UNUSED_ENTRY(188),
460 I40E_PTT_UNUSED_ENTRY(189),
461
462 I40E_PTT_UNUSED_ENTRY(190),
463 I40E_PTT_UNUSED_ENTRY(191),
464 I40E_PTT_UNUSED_ENTRY(192),
465 I40E_PTT_UNUSED_ENTRY(193),
466 I40E_PTT_UNUSED_ENTRY(194),
467 I40E_PTT_UNUSED_ENTRY(195),
468 I40E_PTT_UNUSED_ENTRY(196),
469 I40E_PTT_UNUSED_ENTRY(197),
470 I40E_PTT_UNUSED_ENTRY(198),
471 I40E_PTT_UNUSED_ENTRY(199),
472
473 I40E_PTT_UNUSED_ENTRY(200),
474 I40E_PTT_UNUSED_ENTRY(201),
475 I40E_PTT_UNUSED_ENTRY(202),
476 I40E_PTT_UNUSED_ENTRY(203),
477 I40E_PTT_UNUSED_ENTRY(204),
478 I40E_PTT_UNUSED_ENTRY(205),
479 I40E_PTT_UNUSED_ENTRY(206),
480 I40E_PTT_UNUSED_ENTRY(207),
481 I40E_PTT_UNUSED_ENTRY(208),
482 I40E_PTT_UNUSED_ENTRY(209),
483
484 I40E_PTT_UNUSED_ENTRY(210),
485 I40E_PTT_UNUSED_ENTRY(211),
486 I40E_PTT_UNUSED_ENTRY(212),
487 I40E_PTT_UNUSED_ENTRY(213),
488 I40E_PTT_UNUSED_ENTRY(214),
489 I40E_PTT_UNUSED_ENTRY(215),
490 I40E_PTT_UNUSED_ENTRY(216),
491 I40E_PTT_UNUSED_ENTRY(217),
492 I40E_PTT_UNUSED_ENTRY(218),
493 I40E_PTT_UNUSED_ENTRY(219),
494
495 I40E_PTT_UNUSED_ENTRY(220),
496 I40E_PTT_UNUSED_ENTRY(221),
497 I40E_PTT_UNUSED_ENTRY(222),
498 I40E_PTT_UNUSED_ENTRY(223),
499 I40E_PTT_UNUSED_ENTRY(224),
500 I40E_PTT_UNUSED_ENTRY(225),
501 I40E_PTT_UNUSED_ENTRY(226),
502 I40E_PTT_UNUSED_ENTRY(227),
503 I40E_PTT_UNUSED_ENTRY(228),
504 I40E_PTT_UNUSED_ENTRY(229),
505
506 I40E_PTT_UNUSED_ENTRY(230),
507 I40E_PTT_UNUSED_ENTRY(231),
508 I40E_PTT_UNUSED_ENTRY(232),
509 I40E_PTT_UNUSED_ENTRY(233),
510 I40E_PTT_UNUSED_ENTRY(234),
511 I40E_PTT_UNUSED_ENTRY(235),
512 I40E_PTT_UNUSED_ENTRY(236),
513 I40E_PTT_UNUSED_ENTRY(237),
514 I40E_PTT_UNUSED_ENTRY(238),
515 I40E_PTT_UNUSED_ENTRY(239),
516
517 I40E_PTT_UNUSED_ENTRY(240),
518 I40E_PTT_UNUSED_ENTRY(241),
519 I40E_PTT_UNUSED_ENTRY(242),
520 I40E_PTT_UNUSED_ENTRY(243),
521 I40E_PTT_UNUSED_ENTRY(244),
522 I40E_PTT_UNUSED_ENTRY(245),
523 I40E_PTT_UNUSED_ENTRY(246),
524 I40E_PTT_UNUSED_ENTRY(247),
525 I40E_PTT_UNUSED_ENTRY(248),
526 I40E_PTT_UNUSED_ENTRY(249),
527
528 I40E_PTT_UNUSED_ENTRY(250),
529 I40E_PTT_UNUSED_ENTRY(251),
530 I40E_PTT_UNUSED_ENTRY(252),
531 I40E_PTT_UNUSED_ENTRY(253),
532 I40E_PTT_UNUSED_ENTRY(254),
533 I40E_PTT_UNUSED_ENTRY(255)
534};
535
536
56a62fc8
JB		 537/**
538 * i40e_init_shared_code - Initialize the shared code
539 * @hw: pointer to hardware structure
540 *
541 * This assigns the MAC type and PHY code and inits the NVM.
542 * Does not touch the hardware. This function must be called prior to any
543 * other function in the shared code. The i40e_hw structure should be
544 * memset to 0 prior to calling this function. The following fields in
545 * hw structure should be filled in prior to calling this function:
546 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
547 * subsystem_vendor_id, and revision_id
548 **/
549i40e_status i40e_init_shared_code(struct i40e_hw *hw)
550{
551 i40e_status status = 0;
552 u32 reg;
553
56a62fc8
JB		 554 i40e_set_mac_type(hw);
555
556 switch (hw->mac.type) {
557 case I40E_MAC_XL710:
558 break;
559 default:
560 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 561 }
562
af89d26c
SN		 563 hw->phy.get_link_info = true;
564
565 /* Determine port number */
566 reg = rd32(hw, I40E_PFGEN_PORTNUM);
567 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
568 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
569 hw->port = (u8)reg;
570
5f9116ac
SN		 571 /* Determine the PF number based on the PCI fn */
572 reg = rd32(hw, I40E_GLPCI_CAPSUP);
573 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
574 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
575 else
576 hw->pf_id = (u8)hw->bus.func;
577
56a62fc8
JB		 578 status = i40e_init_nvm(hw);
579 return status;
580}
581
582/**
583 * i40e_aq_mac_address_read - Retrieve the MAC addresses
584 * @hw: pointer to the hw struct
585 * @flags: a return indicator of what addresses were added to the addr store
586 * @addrs: the requestor's mac addr store
587 * @cmd_details: pointer to command details structure or NULL
588 **/
589static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
590 u16 *flags,
591 struct i40e_aqc_mac_address_read_data *addrs,
592 struct i40e_asq_cmd_details *cmd_details)
593{
594 struct i40e_aq_desc desc;
595 struct i40e_aqc_mac_address_read *cmd_data =
596 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
597 i40e_status status;
598
599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
601
602 status = i40e_asq_send_command(hw, &desc, addrs,
603 sizeof(*addrs), cmd_details);
604 *flags = le16_to_cpu(cmd_data->command_flags);
605
606 return status;
607}
608
609/**
610 * i40e_aq_mac_address_write - Change the MAC addresses
611 * @hw: pointer to the hw struct
612 * @flags: indicates which MAC to be written
613 * @mac_addr: address to write
614 * @cmd_details: pointer to command details structure or NULL
615 **/
616i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
617 u16 flags, u8 *mac_addr,
618 struct i40e_asq_cmd_details *cmd_details)
619{
620 struct i40e_aq_desc desc;
621 struct i40e_aqc_mac_address_write *cmd_data =
622 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
623 i40e_status status;
624
625 i40e_fill_default_direct_cmd_desc(&desc,
626 i40e_aqc_opc_mac_address_write);
627 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
630 ((u32)mac_addr[3] << 16) |
631 ((u32)mac_addr[4] << 8) |
632 mac_addr[5]);
56a62fc8
JB		 633
634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
635
636 return status;
637}
638
639/**
640 * i40e_get_mac_addr - get MAC address
641 * @hw: pointer to the HW structure
642 * @mac_addr: pointer to MAC address
643 *
644 * Reads the adapter's MAC address from register
645 **/
646i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
647{
648 struct i40e_aqc_mac_address_read_data addrs;
649 i40e_status status;
650 u16 flags = 0;
651
652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
653
654 if (flags & I40E_AQC_LAN_ADDR_VALID)
655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
656
657 return status;
658}
659
1f224ad2
NP		 660/**
661 * i40e_get_port_mac_addr - get Port MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to Port MAC address
664 *
665 * Reads the adapter's Port MAC address
666 **/
667i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668{
669 struct i40e_aqc_mac_address_read_data addrs;
670 i40e_status status;
671 u16 flags = 0;
672
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (status)
675 return status;
676
677 if (flags & I40E_AQC_PORT_ADDR_VALID)
678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
679 else
680 status = I40E_ERR_INVALID_MAC_ADDR;
681
682 return status;
683}
684
351499ab
MJ		 685/**
686 * i40e_pre_tx_queue_cfg - pre tx queue configure
687 * @hw: pointer to the HW structure
688 * @queue: target pf queue index
689 * @enable: state change request
690 *
691 * Handles hw requirement to indicate intention to enable
692 * or disable target queue.
693 **/
694void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
695{
dfb699f9 696 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 697 u32 reg_block = 0;
dfb699f9 698 u32 reg_val;
351499ab 699
24a768cf 700 if (abs_queue_idx >= 128) {
351499ab 701 reg_block = abs_queue_idx / 128;
24a768cf
CP		 702 abs_queue_idx %= 128;
703 }
351499ab
MJ		 704
705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
708
709 if (enable)
710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
711 else
712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
713
714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
715}
38e00438
VD		 716#ifdef I40E_FCOE
717
718/**
719 * i40e_get_san_mac_addr - get SAN MAC address
720 * @hw: pointer to the HW structure
721 * @mac_addr: pointer to SAN MAC address
722 *
723 * Reads the adapter's SAN MAC address from NVM
724 **/
725i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
726{
727 struct i40e_aqc_mac_address_read_data addrs;
728 i40e_status status;
729 u16 flags = 0;
730
731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
732 if (status)
733 return status;
734
735 if (flags & I40E_AQC_SAN_ADDR_VALID)
736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
737 else
738 status = I40E_ERR_INVALID_MAC_ADDR;
739
740 return status;
741}
742#endif
351499ab 743
be405eb0
JB		 744/**
745 * i40e_get_media_type - Gets media type
746 * @hw: pointer to the hardware structure
747 **/
748static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
749{
750 enum i40e_media_type media;
751
752 switch (hw->phy.link_info.phy_type) {
753 case I40E_PHY_TYPE_10GBASE_SR:
754 case I40E_PHY_TYPE_10GBASE_LR:
755 case I40E_PHY_TYPE_40GBASE_SR4:
756 case I40E_PHY_TYPE_40GBASE_LR4:
757 media = I40E_MEDIA_TYPE_FIBER;
758 break;
759 case I40E_PHY_TYPE_100BASE_TX:
760 case I40E_PHY_TYPE_1000BASE_T:
761 case I40E_PHY_TYPE_10GBASE_T:
762 media = I40E_MEDIA_TYPE_BASET;
763 break;
764 case I40E_PHY_TYPE_10GBASE_CR1_CU:
765 case I40E_PHY_TYPE_40GBASE_CR4_CU:
766 case I40E_PHY_TYPE_10GBASE_CR1:
767 case I40E_PHY_TYPE_40GBASE_CR4:
768 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
769 media = I40E_MEDIA_TYPE_DA;
770 break;
771 case I40E_PHY_TYPE_1000BASE_KX:
772 case I40E_PHY_TYPE_10GBASE_KX4:
773 case I40E_PHY_TYPE_10GBASE_KR:
774 case I40E_PHY_TYPE_40GBASE_KR4:
775 media = I40E_MEDIA_TYPE_BACKPLANE;
776 break;
777 case I40E_PHY_TYPE_SGMII:
778 case I40E_PHY_TYPE_XAUI:
779 case I40E_PHY_TYPE_XFI:
780 case I40E_PHY_TYPE_XLAUI:
781 case I40E_PHY_TYPE_XLPPI:
782 default:
783 media = I40E_MEDIA_TYPE_UNKNOWN;
784 break;
785 }
786
787 return media;
788}
789
7134f9ce 790#define I40E_PF_RESET_WAIT_COUNT_A0 200
d0ff5687 791#define I40E_PF_RESET_WAIT_COUNT 100
56a62fc8
JB		 792/**
793 * i40e_pf_reset - Reset the PF
794 * @hw: pointer to the hardware structure
795 *
796 * Assuming someone else has triggered a global reset,
797 * assure the global reset is complete and then reset the PF
798 **/
799i40e_status i40e_pf_reset(struct i40e_hw *hw)
800{
7134f9ce 801 u32 cnt = 0;
42794bd8 802 u32 cnt1 = 0;
56a62fc8
JB		 803 u32 reg = 0;
804 u32 grst_del;
805
806 /* Poll for Global Reset steady state in case of recent GRST.
807 * The grst delay value is in 100ms units, and we'll wait a
808 * couple counts longer to be sure we don't just miss the end.
809 */
810 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
811 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 812 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 813 reg = rd32(hw, I40E_GLGEN_RSTAT);
814 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
815 break;
816 msleep(100);
817 }
818 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
819 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 820 return I40E_ERR_RESET_FAILED;
821 }
822
823 /* Now Wait for the FW to be ready */
824 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
825 reg = rd32(hw, I40E_GLNVM_ULD);
826 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
827 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
828 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
829 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
830 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
831 break;
832 }
833 usleep_range(10000, 20000);
834 }
835 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
836 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
837 hw_dbg(hw, "wait for FW Reset complete timedout\n");
838 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 839 return I40E_ERR_RESET_FAILED;
840 }
841
56a62fc8
JB		 842 /* If there was a Global Reset in progress when we got here,
843 * we don't need to do the PF Reset
844 */
7134f9ce
JB		 845 if (!cnt) {
846 if (hw->revision_id == 0)
847 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
848 else
849 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 850 reg = rd32(hw, I40E_PFGEN_CTRL);
851 wr32(hw, I40E_PFGEN_CTRL,
852 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 853 for (; cnt; cnt--) {
56a62fc8
JB		 854 reg = rd32(hw, I40E_PFGEN_CTRL);
855 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
856 break;
857 usleep_range(1000, 2000);
858 }
859 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
860 hw_dbg(hw, "PF reset polling failed to complete.\n");
861 return I40E_ERR_RESET_FAILED;
862 }
863 }
864
865 i40e_clear_pxe_mode(hw);
922680b9 866
56a62fc8
JB		 867 return 0;
868}
869
838d41d9
SN		 870/**
871 * i40e_clear_hw - clear out any left over hw state
872 * @hw: pointer to the hw struct
873 *
874 * Clear queues and interrupts, typically called at init time,
875 * but after the capabilities have been found so we know how many
876 * queues and msix vectors have been allocated.
877 **/
878void i40e_clear_hw(struct i40e_hw *hw)
879{
880 u32 num_queues, base_queue;
881 u32 num_pf_int;
882 u32 num_vf_int;
883 u32 num_vfs;
884 u32 i, j;
885 u32 val;
886 u32 eol = 0x7ff;
887
888 /* get number of interrupts, queues, and vfs */
889 val = rd32(hw, I40E_GLPCI_CNF2);
890 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
891 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
892 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
893 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
894
895 val = rd32(hw, I40E_PFLAN_QALLOC);
896 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
897 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
898 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
899 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
900 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
901 num_queues = (j - base_queue) + 1;
902 else
903 num_queues = 0;
904
905 val = rd32(hw, I40E_PF_VT_PFALLOC);
906 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
907 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
908 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
909 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
910 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
911 num_vfs = (j - i) + 1;
912 else
913 num_vfs = 0;
914
915 /* stop all the interrupts */
916 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
917 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
918 for (i = 0; i < num_pf_int - 2; i++)
919 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
920
921 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
922 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
923 wr32(hw, I40E_PFINT_LNKLST0, val);
924 for (i = 0; i < num_pf_int - 2; i++)
925 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
926 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
927 for (i = 0; i < num_vfs; i++)
928 wr32(hw, I40E_VPINT_LNKLST0(i), val);
929 for (i = 0; i < num_vf_int - 2; i++)
930 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
931
932 /* warn the HW of the coming Tx disables */
933 for (i = 0; i < num_queues; i++) {
934 u32 abs_queue_idx = base_queue + i;
935 u32 reg_block = 0;
936
937 if (abs_queue_idx >= 128) {
938 reg_block = abs_queue_idx / 128;
939 abs_queue_idx %= 128;
940 }
941
942 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
943 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
944 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
945 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
946
947 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
948 }
949 udelay(400);
950
951 /* stop all the queues */
952 for (i = 0; i < num_queues; i++) {
953 wr32(hw, I40E_QINT_TQCTL(i), 0);
954 wr32(hw, I40E_QTX_ENA(i), 0);
955 wr32(hw, I40E_QINT_RQCTL(i), 0);
956 wr32(hw, I40E_QRX_ENA(i), 0);
957 }
958
959 /* short wait for all queue disables to settle */
960 udelay(50);
961}
962
56a62fc8
JB		 963/**
964 * i40e_clear_pxe_mode - clear pxe operations mode
965 * @hw: pointer to the hw struct
966 *
967 * Make sure all PXE mode settings are cleared, including things
968 * like descriptor fetch/write-back mode.
969 **/
970void i40e_clear_pxe_mode(struct i40e_hw *hw)
971{
972 u32 reg;
973
c9b9b0ae
SN		 974 if (i40e_check_asq_alive(hw))
975 i40e_aq_clear_pxe_mode(hw, NULL);
976
56a62fc8
JB		 977 /* Clear single descriptor fetch/write-back mode */
978 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 979
980 if (hw->revision_id == 0) {
981 /* As a work around clear PXE_MODE instead of setting it */
982 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
983 } else {
984 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
985 }
56a62fc8
JB		 986}
987
0556a9e3
JB		 988/**
989 * i40e_led_is_mine - helper to find matching led
990 * @hw: pointer to the hw struct
991 * @idx: index into GPIO registers
992 *
993 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
994 */
995static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
996{
997 u32 gpio_val = 0;
998 u32 port;
999
1000 if (!hw->func_caps.led[idx])
1001 return 0;
1002
1003 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1004 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1005 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1006
1007 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1008 * if it is not our port then ignore
1009 */
1010 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1011 (port != hw->port))
1012 return 0;
1013
1014 return gpio_val;
1015}
1016
1017#define I40E_LED0 22
1018#define I40E_LINK_ACTIVITY 0xC
1019
56a62fc8
JB		 1020/**
1021 * i40e_led_get - return current on/off mode
1022 * @hw: pointer to the hw struct
1023 *
1024 * The value returned is the 'mode' field as defined in the
1025 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1026 * values are variations of possible behaviors relating to
1027 * blink, link, and wire.
1028 **/
1029u32 i40e_led_get(struct i40e_hw *hw)
1030{
56a62fc8 1031 u32 mode = 0;
56a62fc8
JB		 1032 int i;
1033
0556a9e3
JB		 1034 /* as per the documentation GPIO 22-29 are the LED
1035 * GPIO pins named LED0..LED7
1036 */
1037 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1038 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1039
0556a9e3 1040 if (!gpio_val)
56a62fc8
JB		 1041 continue;
1042
0556a9e3
JB		 1043 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1044 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1045 break;
1046 }
1047
1048 return mode;
1049}
1050
1051/**
1052 * i40e_led_set - set new on/off mode
1053 * @hw: pointer to the hw struct
0556a9e3
JB		 1054 * @mode: 0=off, 0xf=on (else see manual for mode details)
1055 * @blink: true if the LED should blink when on, false if steady
1056 *
1057 * if this function is used to turn on the blink it should
1058 * be used to disable the blink when restoring the original state.
56a62fc8 1059 **/
0556a9e3 1060void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1061{
56a62fc8
JB		 1062 int i;
1063
0556a9e3
JB		 1064 if (mode & 0xfffffff0)
1065 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1066
0556a9e3
JB		 1067 /* as per the documentation GPIO 22-29 are the LED
1068 * GPIO pins named LED0..LED7
1069 */
1070 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1071 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1072
0556a9e3 1073 if (!gpio_val)
56a62fc8
JB		 1074 continue;
1075
56a62fc8 1076 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1077 /* this & is a bit of paranoia, but serves as a range check */
1078 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1079 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1080
1081 if (mode == I40E_LINK_ACTIVITY)
1082 blink = false;
1083
1084 gpio_val |= (blink ? 1 : 0) <<
1085 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1086
56a62fc8 1087 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1088 break;
56a62fc8
JB		 1089 }
1090}
1091
1092/* Admin command wrappers */
56a62fc8 1093
8109e123
CS		 1094/**
1095 * i40e_aq_get_phy_capabilities
1096 * @hw: pointer to the hw struct
1097 * @abilities: structure for PHY capabilities to be filled
1098 * @qualified_modules: report Qualified Modules
1099 * @report_init: report init capabilities (active are default)
1100 * @cmd_details: pointer to command details structure or NULL
1101 *
1102 * Returns the various PHY abilities supported on the Port.
1103 **/
1104i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1105 bool qualified_modules, bool report_init,
1106 struct i40e_aq_get_phy_abilities_resp *abilities,
1107 struct i40e_asq_cmd_details *cmd_details)
1108{
1109 struct i40e_aq_desc desc;
1110 i40e_status status;
1111 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1112
1113 if (!abilities)
1114 return I40E_ERR_PARAM;
1115
1116 i40e_fill_default_direct_cmd_desc(&desc,
1117 i40e_aqc_opc_get_phy_abilities);
1118
1119 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1120 if (abilities_size > I40E_AQ_LARGE_BUF)
1121 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1122
1123 if (qualified_modules)
1124 desc.params.external.param0 |=
1125 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1126
1127 if (report_init)
1128 desc.params.external.param0 |=
1129 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1130
1131 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1132 cmd_details);
1133
1134 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1135 status = I40E_ERR_UNKNOWN_PHY;
1136
1137 return status;
1138}
1139
c56999f9
CS		 1140/**
1141 * i40e_aq_set_phy_config
1142 * @hw: pointer to the hw struct
1143 * @config: structure with PHY configuration to be set
1144 * @cmd_details: pointer to command details structure or NULL
1145 *
1146 * Set the various PHY configuration parameters
1147 * supported on the Port.One or more of the Set PHY config parameters may be
1148 * ignored in an MFP mode as the PF may not have the privilege to set some
1149 * of the PHY Config parameters. This status will be indicated by the
1150 * command response.
1151 **/
1152enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1153 struct i40e_aq_set_phy_config *config,
1154 struct i40e_asq_cmd_details *cmd_details)
1155{
1156 struct i40e_aq_desc desc;
1157 struct i40e_aq_set_phy_config *cmd =
1158 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1159 enum i40e_status_code status;
1160
1161 if (!config)
1162 return I40E_ERR_PARAM;
1163
1164 i40e_fill_default_direct_cmd_desc(&desc,
1165 i40e_aqc_opc_set_phy_config);
1166
1167 *cmd = *config;
1168
1169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1170
1171 return status;
1172}
1173
1174/**
1175 * i40e_set_fc
1176 * @hw: pointer to the hw struct
1177 *
1178 * Set the requested flow control mode using set_phy_config.
1179 **/
1180enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1181 bool atomic_restart)
1182{
1183 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1184 struct i40e_aq_get_phy_abilities_resp abilities;
1185 struct i40e_aq_set_phy_config config;
1186 enum i40e_status_code status;
1187 u8 pause_mask = 0x0;
1188
1189 *aq_failures = 0x0;
1190
1191 switch (fc_mode) {
1192 case I40E_FC_FULL:
1193 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1194 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1195 break;
1196 case I40E_FC_RX_PAUSE:
1197 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1198 break;
1199 case I40E_FC_TX_PAUSE:
1200 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1201 break;
1202 default:
1203 break;
1204 }
1205
1206 /* Get the current phy config */
1207 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1208 NULL);
1209 if (status) {
1210 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1211 return status;
1212 }
1213
1214 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1215 /* clear the old pause settings */
1216 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1217 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1218 /* set the new abilities */
1219 config.abilities |= pause_mask;
1220 /* If the abilities have changed, then set the new config */
1221 if (config.abilities != abilities.abilities) {
1222 /* Auto restart link so settings take effect */
1223 if (atomic_restart)
1224 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1225 /* Copy over all the old settings */
1226 config.phy_type = abilities.phy_type;
1227 config.link_speed = abilities.link_speed;
1228 config.eee_capability = abilities.eee_capability;
1229 config.eeer = abilities.eeer_val;
1230 config.low_power_ctrl = abilities.d3_lpan;
1231 status = i40e_aq_set_phy_config(hw, &config, NULL);
1232
1233 if (status)
1234 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1235 }
1236 /* Update the link info */
1237 status = i40e_update_link_info(hw, true);
1238 if (status) {
1239 /* Wait a little bit (on 40G cards it sometimes takes a really
1240 * long time for link to come back from the atomic reset)
1241 * and try once more
1242 */
1243 msleep(1000);
1244 status = i40e_update_link_info(hw, true);
1245 }
1246 if (status)
1247 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1248
1249 return status;
1250}
1251
c9b9b0ae
SN		 1252/**
1253 * i40e_aq_clear_pxe_mode
1254 * @hw: pointer to the hw struct
1255 * @cmd_details: pointer to command details structure or NULL
1256 *
1257 * Tell the firmware that the driver is taking over from PXE
1258 **/
1259i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1260 struct i40e_asq_cmd_details *cmd_details)
1261{
1262 i40e_status status;
1263 struct i40e_aq_desc desc;
1264 struct i40e_aqc_clear_pxe *cmd =
1265 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1266
1267 i40e_fill_default_direct_cmd_desc(&desc,
1268 i40e_aqc_opc_clear_pxe_mode);
1269
1270 cmd->rx_cnt = 0x2;
1271
1272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1273
1274 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1275
1276 return status;
1277}
1278
56a62fc8
JB		 1279/**
1280 * i40e_aq_set_link_restart_an
1281 * @hw: pointer to the hw struct
1ac978af 1282 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1283 * @cmd_details: pointer to command details structure or NULL
1284 *
1285 * Sets up the link and restarts the Auto-Negotiation over the link.
1286 **/
1287i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1288 bool enable_link,
1289 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1290{
1291 struct i40e_aq_desc desc;
1292 struct i40e_aqc_set_link_restart_an *cmd =
1293 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1294 i40e_status status;
1295
1296 i40e_fill_default_direct_cmd_desc(&desc,
1297 i40e_aqc_opc_set_link_restart_an);
1298
1299 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1300 if (enable_link)
1301 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1302 else
1303 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1304
1305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1306
1307 return status;
1308}
1309
1310/**
1311 * i40e_aq_get_link_info
1312 * @hw: pointer to the hw struct
1313 * @enable_lse: enable/disable LinkStatusEvent reporting
1314 * @link: pointer to link status structure - optional
1315 * @cmd_details: pointer to command details structure or NULL
1316 *
1317 * Returns the link status of the adapter.
1318 **/
1319i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1320 bool enable_lse, struct i40e_link_status *link,
1321 struct i40e_asq_cmd_details *cmd_details)
1322{
1323 struct i40e_aq_desc desc;
1324 struct i40e_aqc_get_link_status *resp =
1325 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1326 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1327 i40e_status status;
c56999f9 1328 bool tx_pause, rx_pause;
56a62fc8
JB		 1329 u16 command_flags;
1330
1331 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1332
1333 if (enable_lse)
1334 command_flags = I40E_AQ_LSE_ENABLE;
1335 else
1336 command_flags = I40E_AQ_LSE_DISABLE;
1337 resp->command_flags = cpu_to_le16(command_flags);
1338
1339 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1340
1341 if (status)
1342 goto aq_get_link_info_exit;
1343
1344 /* save off old link status information */
c36bd4a7 1345 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1346
1347 /* update link status */
1348 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1349 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1350 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1351 hw_link_info->link_info = resp->link_info;
1352 hw_link_info->an_info = resp->an_info;
1353 hw_link_info->ext_info = resp->ext_info;
639dc377 1354 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1355 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1356 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1357
c56999f9
CS		 1358 /* update fc info */
1359 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1360 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1361 if (tx_pause & rx_pause)
1362 hw->fc.current_mode = I40E_FC_FULL;
1363 else if (tx_pause)
1364 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1365 else if (rx_pause)
1366 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1367 else
1368 hw->fc.current_mode = I40E_FC_NONE;
1369
6bb3f23c
NP		 1370 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1371 hw_link_info->crc_enable = true;
1372 else
1373 hw_link_info->crc_enable = false;
56a62fc8
JB		 1374
1375 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1376 hw_link_info->lse_enable = true;
1377 else
1378 hw_link_info->lse_enable = false;
1379
1380 /* save link status information */
1381 if (link)
d7595a22 1382 *link = *hw_link_info;
56a62fc8
JB		 1383
1384 /* flag cleared so helper functions don't call AQ again */
1385 hw->phy.get_link_info = false;
1386
1387aq_get_link_info_exit:
1388 return status;
1389}
1390
8109e123
CS		 1391/**
1392 * i40e_update_link_info
1393 * @hw: pointer to the hw struct
1394 * @enable_lse: enable/disable LinkStatusEvent reporting
1395 *
1396 * Returns the link status of the adapter
1397 **/
1398i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1399{
1400 struct i40e_aq_get_phy_abilities_resp abilities;
1401 i40e_status status;
1402
1403 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1404 if (status)
1405 return status;
1406
1407 status = i40e_aq_get_phy_capabilities(hw, false, false,
1408 &abilities, NULL);
1409 if (status)
1410 return status;
1411
1412 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1413 hw->phy.link_info.an_enabled = true;
1414 else
1415 hw->phy.link_info.an_enabled = false;
1416
1417 return status;
1418}
1419
56a62fc8
JB		 1420/**
1421 * i40e_aq_add_vsi
1422 * @hw: pointer to the hw struct
98d44381 1423 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1424 * @cmd_details: pointer to command details structure or NULL
1425 *
1426 * Add a VSI context to the hardware.
1427**/
1428i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1429 struct i40e_vsi_context *vsi_ctx,
1430 struct i40e_asq_cmd_details *cmd_details)
1431{
1432 struct i40e_aq_desc desc;
1433 struct i40e_aqc_add_get_update_vsi *cmd =
1434 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1435 struct i40e_aqc_add_get_update_vsi_completion *resp =
1436 (struct i40e_aqc_add_get_update_vsi_completion *)
1437 &desc.params.raw;
1438 i40e_status status;
1439
1440 i40e_fill_default_direct_cmd_desc(&desc,
1441 i40e_aqc_opc_add_vsi);
1442
1443 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1444 cmd->connection_type = vsi_ctx->connection_type;
1445 cmd->vf_id = vsi_ctx->vf_num;
1446 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1447
1448 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1449
1450 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1451 sizeof(vsi_ctx->info), cmd_details);
1452
1453 if (status)
1454 goto aq_add_vsi_exit;
1455
1456 vsi_ctx->seid = le16_to_cpu(resp->seid);
1457 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1458 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1459 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1460
1461aq_add_vsi_exit:
1462 return status;
1463}
1464
1465/**
1466 * i40e_aq_set_vsi_unicast_promiscuous
1467 * @hw: pointer to the hw struct
1468 * @seid: vsi number
1469 * @set: set unicast promiscuous enable/disable
1470 * @cmd_details: pointer to command details structure or NULL
1471 **/
1472i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1473 u16 seid, bool set,
1474 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1475{
1476 struct i40e_aq_desc desc;
1477 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1478 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1479 i40e_status status;
1480 u16 flags = 0;
1481
1482 i40e_fill_default_direct_cmd_desc(&desc,
1483 i40e_aqc_opc_set_vsi_promiscuous_modes);
1484
1485 if (set)
1486 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1487
1488 cmd->promiscuous_flags = cpu_to_le16(flags);
1489
1490 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1491
1492 cmd->seid = cpu_to_le16(seid);
1493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1494
1495 return status;
1496}
1497
1498/**
1499 * i40e_aq_set_vsi_multicast_promiscuous
1500 * @hw: pointer to the hw struct
1501 * @seid: vsi number
1502 * @set: set multicast promiscuous enable/disable
1503 * @cmd_details: pointer to command details structure or NULL
1504 **/
1505i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1506 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1507{
1508 struct i40e_aq_desc desc;
1509 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1510 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1511 i40e_status status;
1512 u16 flags = 0;
1513
1514 i40e_fill_default_direct_cmd_desc(&desc,
1515 i40e_aqc_opc_set_vsi_promiscuous_modes);
1516
1517 if (set)
1518 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1519
1520 cmd->promiscuous_flags = cpu_to_le16(flags);
1521
1522 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1523
1524 cmd->seid = cpu_to_le16(seid);
1525 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1526
1527 return status;
1528}
1529
1530/**
1531 * i40e_aq_set_vsi_broadcast
1532 * @hw: pointer to the hw struct
1533 * @seid: vsi number
1534 * @set_filter: true to set filter, false to clear filter
1535 * @cmd_details: pointer to command details structure or NULL
1536 *
1537 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1538 **/
1539i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1540 u16 seid, bool set_filter,
1541 struct i40e_asq_cmd_details *cmd_details)
1542{
1543 struct i40e_aq_desc desc;
1544 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1545 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1546 i40e_status status;
1547
1548 i40e_fill_default_direct_cmd_desc(&desc,
1549 i40e_aqc_opc_set_vsi_promiscuous_modes);
1550
1551 if (set_filter)
1552 cmd->promiscuous_flags
1553 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1554 else
1555 cmd->promiscuous_flags
1556 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1557
1558 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1559 cmd->seid = cpu_to_le16(seid);
1560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1561
1562 return status;
1563}
1564
1565/**
1566 * i40e_get_vsi_params - get VSI configuration info
1567 * @hw: pointer to the hw struct
98d44381 1568 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1569 * @cmd_details: pointer to command details structure or NULL
1570 **/
1571i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1572 struct i40e_vsi_context *vsi_ctx,
1573 struct i40e_asq_cmd_details *cmd_details)
1574{
1575 struct i40e_aq_desc desc;
f5ac8579
SN		 1576 struct i40e_aqc_add_get_update_vsi *cmd =
1577 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1578 struct i40e_aqc_add_get_update_vsi_completion *resp =
1579 (struct i40e_aqc_add_get_update_vsi_completion *)
1580 &desc.params.raw;
1581 i40e_status status;
1582
1583 i40e_fill_default_direct_cmd_desc(&desc,
1584 i40e_aqc_opc_get_vsi_parameters);
1585
f5ac8579 1586 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1587
1588 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 1589
1590 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1591 sizeof(vsi_ctx->info), NULL);
1592
1593 if (status)
1594 goto aq_get_vsi_params_exit;
1595
1596 vsi_ctx->seid = le16_to_cpu(resp->seid);
1597 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1598 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1599 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1600
1601aq_get_vsi_params_exit:
1602 return status;
1603}
1604
1605/**
1606 * i40e_aq_update_vsi_params
1607 * @hw: pointer to the hw struct
98d44381 1608 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1609 * @cmd_details: pointer to command details structure or NULL
1610 *
1611 * Update a VSI context.
1612 **/
1613i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1614 struct i40e_vsi_context *vsi_ctx,
1615 struct i40e_asq_cmd_details *cmd_details)
1616{
1617 struct i40e_aq_desc desc;
f5ac8579
SN		 1618 struct i40e_aqc_add_get_update_vsi *cmd =
1619 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1620 i40e_status status;
1621
1622 i40e_fill_default_direct_cmd_desc(&desc,
1623 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1624 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1625
1626 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1627
1628 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1629 sizeof(vsi_ctx->info), cmd_details);
1630
1631 return status;
1632}
1633
1634/**
1635 * i40e_aq_get_switch_config
1636 * @hw: pointer to the hardware structure
1637 * @buf: pointer to the result buffer
1638 * @buf_size: length of input buffer
1639 * @start_seid: seid to start for the report, 0 == beginning
1640 * @cmd_details: pointer to command details structure or NULL
1641 *
1642 * Fill the buf with switch configuration returned from AdminQ command
1643 **/
1644i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1645 struct i40e_aqc_get_switch_config_resp *buf,
1646 u16 buf_size, u16 *start_seid,
1647 struct i40e_asq_cmd_details *cmd_details)
1648{
1649 struct i40e_aq_desc desc;
1650 struct i40e_aqc_switch_seid *scfg =
1651 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1652 i40e_status status;
1653
1654 i40e_fill_default_direct_cmd_desc(&desc,
1655 i40e_aqc_opc_get_switch_config);
1656 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1657 if (buf_size > I40E_AQ_LARGE_BUF)
1658 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1659 scfg->seid = cpu_to_le16(*start_seid);
1660
1661 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1662 *start_seid = le16_to_cpu(scfg->seid);
1663
1664 return status;
1665}
1666
1667/**
1668 * i40e_aq_get_firmware_version
1669 * @hw: pointer to the hw struct
1670 * @fw_major_version: firmware major version
1671 * @fw_minor_version: firmware minor version
1672 * @api_major_version: major queue version
1673 * @api_minor_version: minor queue version
1674 * @cmd_details: pointer to command details structure or NULL
1675 *
1676 * Get the firmware version from the admin queue commands
1677 **/
1678i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1679 u16 *fw_major_version, u16 *fw_minor_version,
1680 u16 *api_major_version, u16 *api_minor_version,
1681 struct i40e_asq_cmd_details *cmd_details)
1682{
1683 struct i40e_aq_desc desc;
1684 struct i40e_aqc_get_version *resp =
1685 (struct i40e_aqc_get_version *)&desc.params.raw;
1686 i40e_status status;
1687
1688 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1689
1690 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1691
1692 if (!status) {
1693 if (fw_major_version != NULL)
1694 *fw_major_version = le16_to_cpu(resp->fw_major);
1695 if (fw_minor_version != NULL)
1696 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1697 if (api_major_version != NULL)
1698 *api_major_version = le16_to_cpu(resp->api_major);
1699 if (api_minor_version != NULL)
1700 *api_minor_version = le16_to_cpu(resp->api_minor);
1701 }
1702
1703 return status;
1704}
1705
1706/**
1707 * i40e_aq_send_driver_version
1708 * @hw: pointer to the hw struct
56a62fc8
JB		 1709 * @dv: driver's major, minor version
1710 * @cmd_details: pointer to command details structure or NULL
1711 *
1712 * Send the driver version to the firmware
1713 **/
1714i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1715 struct i40e_driver_version *dv,
1716 struct i40e_asq_cmd_details *cmd_details)
1717{
1718 struct i40e_aq_desc desc;
1719 struct i40e_aqc_driver_version *cmd =
1720 (struct i40e_aqc_driver_version *)&desc.params.raw;
1721 i40e_status status;
9d2f98e1 1722 u16 len;
56a62fc8
JB		 1723
1724 if (dv == NULL)
1725 return I40E_ERR_PARAM;
1726
1727 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1728
1729 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1730 cmd->driver_major_ver = dv->major_version;
1731 cmd->driver_minor_ver = dv->minor_version;
1732 cmd->driver_build_ver = dv->build_version;
1733 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1734
1735 len = 0;
1736 while (len < sizeof(dv->driver_string) &&
1737 (dv->driver_string[len] < 0x80) &&
1738 dv->driver_string[len])
1739 len++;
1740 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1741 len, cmd_details);
56a62fc8
JB		 1742
1743 return status;
1744}
1745
1746/**
1747 * i40e_get_link_status - get status of the HW network link
1748 * @hw: pointer to the hw struct
1749 *
1750 * Returns true if link is up, false if link is down.
1751 *
1752 * Side effect: LinkStatusEvent reporting becomes enabled
1753 **/
1754bool i40e_get_link_status(struct i40e_hw *hw)
1755{
1756 i40e_status status = 0;
1757 bool link_status = false;
1758
1759 if (hw->phy.get_link_info) {
1760 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1761
1762 if (status)
1763 goto i40e_get_link_status_exit;
1764 }
1765
1766 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1767
1768i40e_get_link_status_exit:
1769 return link_status;
1770}
1771
1772/**
1773 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1774 * @hw: pointer to the hw struct
1775 * @uplink_seid: the MAC or other gizmo SEID
1776 * @downlink_seid: the VSI SEID
1777 * @enabled_tc: bitmap of TCs to be enabled
1778 * @default_port: true for default port VSI, false for control port
e1c51b95 1779 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1780 * @veb_seid: pointer to where to put the resulting VEB SEID
1781 * @cmd_details: pointer to command details structure or NULL
1782 *
1783 * This asks the FW to add a VEB between the uplink and downlink
1784 * elements. If the uplink SEID is 0, this will be a floating VEB.
1785 **/
1786i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1787 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1788 bool default_port, bool enable_l2_filtering,
1789 u16 *veb_seid,
56a62fc8
JB		 1790 struct i40e_asq_cmd_details *cmd_details)
1791{
1792 struct i40e_aq_desc desc;
1793 struct i40e_aqc_add_veb *cmd =
1794 (struct i40e_aqc_add_veb *)&desc.params.raw;
1795 struct i40e_aqc_add_veb_completion *resp =
1796 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1797 i40e_status status;
1798 u16 veb_flags = 0;
1799
1800 /* SEIDs need to either both be set or both be 0 for floating VEB */
1801 if (!!uplink_seid != !!downlink_seid)
1802 return I40E_ERR_PARAM;
1803
1804 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1805
1806 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1807 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1808 cmd->enable_tcs = enabled_tc;
1809 if (!uplink_seid)
1810 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1811 if (default_port)
1812 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1813 else
1814 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1815
1816 if (enable_l2_filtering)
1817 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1818
56a62fc8
JB		 1819 cmd->veb_flags = cpu_to_le16(veb_flags);
1820
1821 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1822
1823 if (!status && veb_seid)
1824 *veb_seid = le16_to_cpu(resp->veb_seid);
1825
1826 return status;
1827}
1828
1829/**
1830 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1831 * @hw: pointer to the hw struct
1832 * @veb_seid: the SEID of the VEB to query
1833 * @switch_id: the uplink switch id
98d44381 1834 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1835 * @statistic_index: index of the stats counter block for this VEB
1836 * @vebs_used: number of VEB's used by function
98d44381 1837 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1838 * @cmd_details: pointer to command details structure or NULL
1839 *
1840 * This retrieves the parameters for a particular VEB, specified by
1841 * uplink_seid, and returns them to the caller.
1842 **/
1843i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1844 u16 veb_seid, u16 *switch_id,
1845 bool *floating, u16 *statistic_index,
1846 u16 *vebs_used, u16 *vebs_free,
1847 struct i40e_asq_cmd_details *cmd_details)
1848{
1849 struct i40e_aq_desc desc;
1850 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1851 (struct i40e_aqc_get_veb_parameters_completion *)
1852 &desc.params.raw;
1853 i40e_status status;
1854
1855 if (veb_seid == 0)
1856 return I40E_ERR_PARAM;
1857
1858 i40e_fill_default_direct_cmd_desc(&desc,
1859 i40e_aqc_opc_get_veb_parameters);
1860 cmd_resp->seid = cpu_to_le16(veb_seid);
1861
1862 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1863 if (status)
1864 goto get_veb_exit;
1865
1866 if (switch_id)
1867 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1868 if (statistic_index)
1869 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1870 if (vebs_used)
1871 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1872 if (vebs_free)
1873 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1874 if (floating) {
1875 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1876 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1877 *floating = true;
1878 else
1879 *floating = false;
1880 }
1881
1882get_veb_exit:
1883 return status;
1884}
1885
1886/**
1887 * i40e_aq_add_macvlan
1888 * @hw: pointer to the hw struct
1889 * @seid: VSI for the mac address
1890 * @mv_list: list of macvlans to be added
1891 * @count: length of the list
1892 * @cmd_details: pointer to command details structure or NULL
1893 *
1894 * Add MAC/VLAN addresses to the HW filtering
1895 **/
1896i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1897 struct i40e_aqc_add_macvlan_element_data *mv_list,
1898 u16 count, struct i40e_asq_cmd_details *cmd_details)
1899{
1900 struct i40e_aq_desc desc;
1901 struct i40e_aqc_macvlan *cmd =
1902 (struct i40e_aqc_macvlan *)&desc.params.raw;
1903 i40e_status status;
1904 u16 buf_size;
1905
1906 if (count == 0 || !mv_list || !hw)
1907 return I40E_ERR_PARAM;
1908
1909 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1910
1911 /* prep the rest of the request */
1912 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1913 cmd->num_addresses = cpu_to_le16(count);
1914 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1915 cmd->seid[1] = 0;
1916 cmd->seid[2] = 0;
1917
1918 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1919 if (buf_size > I40E_AQ_LARGE_BUF)
1920 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1921
1922 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1923 cmd_details);
1924
1925 return status;
1926}
1927
1928/**
1929 * i40e_aq_remove_macvlan
1930 * @hw: pointer to the hw struct
1931 * @seid: VSI for the mac address
1932 * @mv_list: list of macvlans to be removed
1933 * @count: length of the list
1934 * @cmd_details: pointer to command details structure or NULL
1935 *
1936 * Remove MAC/VLAN addresses from the HW filtering
1937 **/
1938i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1939 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1940 u16 count, struct i40e_asq_cmd_details *cmd_details)
1941{
1942 struct i40e_aq_desc desc;
1943 struct i40e_aqc_macvlan *cmd =
1944 (struct i40e_aqc_macvlan *)&desc.params.raw;
1945 i40e_status status;
1946 u16 buf_size;
1947
1948 if (count == 0 || !mv_list || !hw)
1949 return I40E_ERR_PARAM;
1950
1951 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1952
1953 /* prep the rest of the request */
1954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1955 cmd->num_addresses = cpu_to_le16(count);
1956 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1957 cmd->seid[1] = 0;
1958 cmd->seid[2] = 0;
1959
1960 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1961 if (buf_size > I40E_AQ_LARGE_BUF)
1962 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1963
1964 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1965 cmd_details);
1966
1967 return status;
1968}
1969
56a62fc8
JB		 1970/**
1971 * i40e_aq_send_msg_to_vf
1972 * @hw: pointer to the hardware structure
1973 * @vfid: vf id to send msg
98d44381
JK		 1974 * @v_opcode: opcodes for VF-PF communication
1975 * @v_retval: return error code
56a62fc8
JB		 1976 * @msg: pointer to the msg buffer
1977 * @msglen: msg length
1978 * @cmd_details: pointer to command details
1979 *
1980 * send msg to vf
1981 **/
1982i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1983 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1984 struct i40e_asq_cmd_details *cmd_details)
1985{
1986 struct i40e_aq_desc desc;
1987 struct i40e_aqc_pf_vf_message *cmd =
1988 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1989 i40e_status status;
1990
1991 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1992 cmd->id = cpu_to_le32(vfid);
1993 desc.cookie_high = cpu_to_le32(v_opcode);
1994 desc.cookie_low = cpu_to_le32(v_retval);
1995 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1996 if (msglen) {
1997 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1998 I40E_AQ_FLAG_RD));
1999 if (msglen > I40E_AQ_LARGE_BUF)
2000 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2001 desc.datalen = cpu_to_le16(msglen);
2002 }
2003 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2004
2005 return status;
2006}
2007
53db45cd
SN		 2008/**
2009 * i40e_aq_debug_write_register
2010 * @hw: pointer to the hw struct
2011 * @reg_addr: register address
2012 * @reg_val: register value
2013 * @cmd_details: pointer to command details structure or NULL
2014 *
2015 * Write to a register using the admin queue commands
2016 **/
2017i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2018 u32 reg_addr, u64 reg_val,
2019 struct i40e_asq_cmd_details *cmd_details)
2020{
2021 struct i40e_aq_desc desc;
2022 struct i40e_aqc_debug_reg_read_write *cmd =
2023 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2024 i40e_status status;
2025
2026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2027
2028 cmd->address = cpu_to_le32(reg_addr);
2029 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2030 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2031
2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2033
2034 return status;
2035}
2036
56a62fc8
JB		 2037/**
2038 * i40e_aq_set_hmc_resource_profile
2039 * @hw: pointer to the hw struct
2040 * @profile: type of profile the HMC is to be set as
2041 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2042 * @cmd_details: pointer to command details structure or NULL
2043 *
2044 * set the HMC profile of the device.
2045 **/
2046i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2047 enum i40e_aq_hmc_profile profile,
2048 u8 pe_vf_enabled_count,
2049 struct i40e_asq_cmd_details *cmd_details)
2050{
2051 struct i40e_aq_desc desc;
2052 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2053 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2054 i40e_status status;
2055
2056 i40e_fill_default_direct_cmd_desc(&desc,
2057 i40e_aqc_opc_set_hmc_resource_profile);
2058
2059 cmd->pm_profile = (u8)profile;
2060 cmd->pe_vf_enabled = pe_vf_enabled_count;
2061
2062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2063
2064 return status;
2065}
2066
2067/**
2068 * i40e_aq_request_resource
2069 * @hw: pointer to the hw struct
2070 * @resource: resource id
2071 * @access: access type
2072 * @sdp_number: resource number
2073 * @timeout: the maximum time in ms that the driver may hold the resource
2074 * @cmd_details: pointer to command details structure or NULL
2075 *
2076 * requests common resource using the admin queue commands
2077 **/
2078i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2079 enum i40e_aq_resources_ids resource,
2080 enum i40e_aq_resource_access_type access,
2081 u8 sdp_number, u64 *timeout,
2082 struct i40e_asq_cmd_details *cmd_details)
2083{
2084 struct i40e_aq_desc desc;
2085 struct i40e_aqc_request_resource *cmd_resp =
2086 (struct i40e_aqc_request_resource *)&desc.params.raw;
2087 i40e_status status;
2088
2089 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2090
2091 cmd_resp->resource_id = cpu_to_le16(resource);
2092 cmd_resp->access_type = cpu_to_le16(access);
2093 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2094
2095 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2096 /* The completion specifies the maximum time in ms that the driver
2097 * may hold the resource in the Timeout field.
2098 * If the resource is held by someone else, the command completes with
2099 * busy return value and the timeout field indicates the maximum time
2100 * the current owner of the resource has to free it.
2101 */
2102 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2103 *timeout = le32_to_cpu(cmd_resp->timeout);
2104
2105 return status;
2106}
2107
2108/**
2109 * i40e_aq_release_resource
2110 * @hw: pointer to the hw struct
2111 * @resource: resource id
2112 * @sdp_number: resource number
2113 * @cmd_details: pointer to command details structure or NULL
2114 *
2115 * release common resource using the admin queue commands
2116 **/
2117i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2118 enum i40e_aq_resources_ids resource,
2119 u8 sdp_number,
2120 struct i40e_asq_cmd_details *cmd_details)
2121{
2122 struct i40e_aq_desc desc;
2123 struct i40e_aqc_request_resource *cmd =
2124 (struct i40e_aqc_request_resource *)&desc.params.raw;
2125 i40e_status status;
2126
2127 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2128
2129 cmd->resource_id = cpu_to_le16(resource);
2130 cmd->resource_number = cpu_to_le32(sdp_number);
2131
2132 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2133
2134 return status;
2135}
2136
2137/**
2138 * i40e_aq_read_nvm
2139 * @hw: pointer to the hw struct
2140 * @module_pointer: module pointer location in words from the NVM beginning
2141 * @offset: byte offset from the module beginning
2142 * @length: length of the section to be read (in bytes from the offset)
2143 * @data: command buffer (size [bytes] = length)
2144 * @last_command: tells if this is the last command in a series
2145 * @cmd_details: pointer to command details structure or NULL
2146 *
2147 * Read the NVM using the admin queue commands
2148 **/
2149i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2150 u32 offset, u16 length, void *data,
2151 bool last_command,
2152 struct i40e_asq_cmd_details *cmd_details)
2153{
2154 struct i40e_aq_desc desc;
2155 struct i40e_aqc_nvm_update *cmd =
2156 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2157 i40e_status status;
2158
2159 /* In offset the highest byte must be zeroed. */
2160 if (offset & 0xFF000000) {
2161 status = I40E_ERR_PARAM;
2162 goto i40e_aq_read_nvm_exit;
2163 }
2164
2165 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2166
2167 /* If this is the last command in a series, set the proper flag. */
2168 if (last_command)
2169 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2170 cmd->module_pointer = module_pointer;
2171 cmd->offset = cpu_to_le32(offset);
2172 cmd->length = cpu_to_le16(length);
2173
2174 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2175 if (length > I40E_AQ_LARGE_BUF)
2176 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2177
2178 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2179
2180i40e_aq_read_nvm_exit:
2181 return status;
2182}
2183
cd552cb4
SN		 2184/**
2185 * i40e_aq_erase_nvm
2186 * @hw: pointer to the hw struct
2187 * @module_pointer: module pointer location in words from the NVM beginning
2188 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2189 * @length: length of the section to be erased (expressed in 4 KB)
2190 * @last_command: tells if this is the last command in a series
2191 * @cmd_details: pointer to command details structure or NULL
2192 *
2193 * Erase the NVM sector using the admin queue commands
2194 **/
2195i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2196 u32 offset, u16 length, bool last_command,
2197 struct i40e_asq_cmd_details *cmd_details)
2198{
2199 struct i40e_aq_desc desc;
2200 struct i40e_aqc_nvm_update *cmd =
2201 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2202 i40e_status status;
2203
2204 /* In offset the highest byte must be zeroed. */
2205 if (offset & 0xFF000000) {
2206 status = I40E_ERR_PARAM;
2207 goto i40e_aq_erase_nvm_exit;
2208 }
2209
2210 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2211
2212 /* If this is the last command in a series, set the proper flag. */
2213 if (last_command)
2214 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2215 cmd->module_pointer = module_pointer;
2216 cmd->offset = cpu_to_le32(offset);
2217 cmd->length = cpu_to_le16(length);
2218
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2220
2221i40e_aq_erase_nvm_exit:
2222 return status;
2223}
2224
56a62fc8
JB		 2225#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2226#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2227#define I40E_DEV_FUNC_CAP_NPAR 0x03
2228#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2229#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2230#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2231#define I40E_DEV_FUNC_CAP_VF 0x13
2232#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2233#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2234#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2235#define I40E_DEV_FUNC_CAP_VSI 0x17
2236#define I40E_DEV_FUNC_CAP_DCB 0x18
2237#define I40E_DEV_FUNC_CAP_FCOE 0x21
2238#define I40E_DEV_FUNC_CAP_RSS 0x40
2239#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2240#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2241#define I40E_DEV_FUNC_CAP_MSIX 0x43
2242#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2243#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2244#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2245#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2246#define I40E_DEV_FUNC_CAP_CEM 0xF2
2247#define I40E_DEV_FUNC_CAP_IWARP 0x51
2248#define I40E_DEV_FUNC_CAP_LED 0x61
2249#define I40E_DEV_FUNC_CAP_SDP 0x62
2250#define I40E_DEV_FUNC_CAP_MDIO 0x63
2251
2252/**
2253 * i40e_parse_discover_capabilities
2254 * @hw: pointer to the hw struct
2255 * @buff: pointer to a buffer containing device/function capability records
2256 * @cap_count: number of capability records in the list
2257 * @list_type_opc: type of capabilities list to parse
2258 *
2259 * Parse the device/function capabilities list.
2260 **/
2261static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2262 u32 cap_count,
2263 enum i40e_admin_queue_opc list_type_opc)
2264{
2265 struct i40e_aqc_list_capabilities_element_resp *cap;
2266 u32 number, logical_id, phys_id;
2267 struct i40e_hw_capabilities *p;
56a62fc8
JB		 2268 u32 i = 0;
2269 u16 id;
2270
2271 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2272
2273 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2274 p = &hw->dev_caps;
56a62fc8 2275 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2276 p = &hw->func_caps;
56a62fc8
JB		 2277 else
2278 return;
2279
2280 for (i = 0; i < cap_count; i++, cap++) {
2281 id = le16_to_cpu(cap->id);
2282 number = le32_to_cpu(cap->number);
2283 logical_id = le32_to_cpu(cap->logical_id);
2284 phys_id = le32_to_cpu(cap->phys_id);
2285
2286 switch (id) {
2287 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2288 p->switch_mode = number;
2289 break;
2290 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2291 p->management_mode = number;
2292 break;
2293 case I40E_DEV_FUNC_CAP_NPAR:
2294 p->npar_enable = number;
2295 break;
2296 case I40E_DEV_FUNC_CAP_OS2BMC:
2297 p->os2bmc = number;
2298 break;
2299 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2300 p->valid_functions = number;
2301 break;
2302 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2303 if (number == 1)
2304 p->sr_iov_1_1 = true;
2305 break;
2306 case I40E_DEV_FUNC_CAP_VF:
2307 p->num_vfs = number;
2308 p->vf_base_id = logical_id;
2309 break;
2310 case I40E_DEV_FUNC_CAP_VMDQ:
2311 if (number == 1)
2312 p->vmdq = true;
2313 break;
2314 case I40E_DEV_FUNC_CAP_802_1_QBG:
2315 if (number == 1)
2316 p->evb_802_1_qbg = true;
2317 break;
2318 case I40E_DEV_FUNC_CAP_802_1_QBH:
2319 if (number == 1)
2320 p->evb_802_1_qbh = true;
2321 break;
2322 case I40E_DEV_FUNC_CAP_VSI:
2323 p->num_vsis = number;
2324 break;
2325 case I40E_DEV_FUNC_CAP_DCB:
2326 if (number == 1) {
2327 p->dcb = true;
2328 p->enabled_tcmap = logical_id;
2329 p->maxtc = phys_id;
2330 }
2331 break;
2332 case I40E_DEV_FUNC_CAP_FCOE:
2333 if (number == 1)
2334 p->fcoe = true;
2335 break;
2336 case I40E_DEV_FUNC_CAP_RSS:
2337 p->rss = true;
e157ea30 2338 p->rss_table_size = number;
56a62fc8
JB		 2339 p->rss_table_entry_width = logical_id;
2340 break;
2341 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2342 p->num_rx_qp = number;
2343 p->base_queue = phys_id;
2344 break;
2345 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2346 p->num_tx_qp = number;
2347 p->base_queue = phys_id;
2348 break;
2349 case I40E_DEV_FUNC_CAP_MSIX:
2350 p->num_msix_vectors = number;
2351 break;
2352 case I40E_DEV_FUNC_CAP_MSIX_VF:
2353 p->num_msix_vectors_vf = number;
2354 break;
2355 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2356 if (number == 1)
2357 p->mfp_mode_1 = true;
2358 break;
2359 case I40E_DEV_FUNC_CAP_CEM:
2360 if (number == 1)
2361 p->mgmt_cem = true;
2362 break;
2363 case I40E_DEV_FUNC_CAP_IWARP:
2364 if (number == 1)
2365 p->iwarp = true;
2366 break;
2367 case I40E_DEV_FUNC_CAP_LED:
2368 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2369 p->led[phys_id] = true;
2370 break;
2371 case I40E_DEV_FUNC_CAP_SDP:
2372 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2373 p->sdp[phys_id] = true;
2374 break;
2375 case I40E_DEV_FUNC_CAP_MDIO:
2376 if (number == 1) {
2377 p->mdio_port_num = phys_id;
2378 p->mdio_port_mode = logical_id;
2379 }
2380 break;
2381 case I40E_DEV_FUNC_CAP_IEEE_1588:
2382 if (number == 1)
2383 p->ieee_1588 = true;
2384 break;
2385 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2386 p->fd = true;
2387 p->fd_filters_guaranteed = number;
2388 p->fd_filters_best_effort = logical_id;
2389 break;
2390 default:
2391 break;
2392 }
2393 }
2394
566bb85d
VD		 2395 /* Software override ensuring FCoE is disabled if npar or mfp
2396 * mode because it is not supported in these modes.
2397 */
2398 if (p->npar_enable || p->mfp_mode_1)
2399 p->fcoe = false;
2400
56a62fc8
JB		 2401 /* additional HW specific goodies that might
2402 * someday be HW version specific
2403 */
2404 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2405}
2406
2407/**
2408 * i40e_aq_discover_capabilities
2409 * @hw: pointer to the hw struct
2410 * @buff: a virtual buffer to hold the capabilities
2411 * @buff_size: Size of the virtual buffer
2412 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2413 * @list_type_opc: capabilities type to discover - pass in the command opcode
2414 * @cmd_details: pointer to command details structure or NULL
2415 *
2416 * Get the device capabilities descriptions from the firmware
2417 **/
2418i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2419 void *buff, u16 buff_size, u16 *data_size,
2420 enum i40e_admin_queue_opc list_type_opc,
2421 struct i40e_asq_cmd_details *cmd_details)
2422{
2423 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 2424 struct i40e_aq_desc desc;
8fb905b3 2425 i40e_status status = 0;
56a62fc8
JB		 2426
2427 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2428
2429 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2430 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2431 status = I40E_ERR_PARAM;
2432 goto exit;
2433 }
2434
2435 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2436
2437 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2438 if (buff_size > I40E_AQ_LARGE_BUF)
2439 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2440
2441 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2442 *data_size = le16_to_cpu(desc.datalen);
2443
2444 if (status)
2445 goto exit;
2446
2447 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2448 list_type_opc);
2449
2450exit:
2451 return status;
2452}
2453
cd552cb4
SN		 2454/**
2455 * i40e_aq_update_nvm
2456 * @hw: pointer to the hw struct
2457 * @module_pointer: module pointer location in words from the NVM beginning
2458 * @offset: byte offset from the module beginning
2459 * @length: length of the section to be written (in bytes from the offset)
2460 * @data: command buffer (size [bytes] = length)
2461 * @last_command: tells if this is the last command in a series
2462 * @cmd_details: pointer to command details structure or NULL
2463 *
2464 * Update the NVM using the admin queue commands
2465 **/
2466i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2467 u32 offset, u16 length, void *data,
2468 bool last_command,
2469 struct i40e_asq_cmd_details *cmd_details)
2470{
2471 struct i40e_aq_desc desc;
2472 struct i40e_aqc_nvm_update *cmd =
2473 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2474 i40e_status status;
2475
2476 /* In offset the highest byte must be zeroed. */
2477 if (offset & 0xFF000000) {
2478 status = I40E_ERR_PARAM;
2479 goto i40e_aq_update_nvm_exit;
2480 }
2481
2482 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2483
2484 /* If this is the last command in a series, set the proper flag. */
2485 if (last_command)
2486 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2487 cmd->module_pointer = module_pointer;
2488 cmd->offset = cpu_to_le32(offset);
2489 cmd->length = cpu_to_le16(length);
2490
2491 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2492 if (length > I40E_AQ_LARGE_BUF)
2493 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2494
2495 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2496
2497i40e_aq_update_nvm_exit:
2498 return status;
2499}
2500
56a62fc8
JB		 2501/**
2502 * i40e_aq_get_lldp_mib
2503 * @hw: pointer to the hw struct
2504 * @bridge_type: type of bridge requested
2505 * @mib_type: Local, Remote or both Local and Remote MIBs
2506 * @buff: pointer to a user supplied buffer to store the MIB block
2507 * @buff_size: size of the buffer (in bytes)
2508 * @local_len : length of the returned Local LLDP MIB
2509 * @remote_len: length of the returned Remote LLDP MIB
2510 * @cmd_details: pointer to command details structure or NULL
2511 *
2512 * Requests the complete LLDP MIB (entire packet).
2513 **/
2514i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2515 u8 mib_type, void *buff, u16 buff_size,
2516 u16 *local_len, u16 *remote_len,
2517 struct i40e_asq_cmd_details *cmd_details)
2518{
2519 struct i40e_aq_desc desc;
2520 struct i40e_aqc_lldp_get_mib *cmd =
2521 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2522 struct i40e_aqc_lldp_get_mib *resp =
2523 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2524 i40e_status status;
2525
2526 if (buff_size == 0 || !buff)
2527 return I40E_ERR_PARAM;
2528
2529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2530 /* Indirect Command */
2531 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2532
2533 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2534 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2535 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2536
2537 desc.datalen = cpu_to_le16(buff_size);
2538
2539 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2540 if (buff_size > I40E_AQ_LARGE_BUF)
2541 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2542
2543 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2544 if (!status) {
2545 if (local_len != NULL)
2546 *local_len = le16_to_cpu(resp->local_len);
2547 if (remote_len != NULL)
2548 *remote_len = le16_to_cpu(resp->remote_len);
2549 }
2550
2551 return status;
2552}
2553
2554/**
2555 * i40e_aq_cfg_lldp_mib_change_event
2556 * @hw: pointer to the hw struct
2557 * @enable_update: Enable or Disable event posting
2558 * @cmd_details: pointer to command details structure or NULL
2559 *
2560 * Enable or Disable posting of an event on ARQ when LLDP MIB
2561 * associated with the interface changes
2562 **/
2563i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2564 bool enable_update,
2565 struct i40e_asq_cmd_details *cmd_details)
2566{
2567 struct i40e_aq_desc desc;
2568 struct i40e_aqc_lldp_update_mib *cmd =
2569 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2570 i40e_status status;
2571
2572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2573
2574 if (!enable_update)
2575 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2576
2577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2578
2579 return status;
2580}
2581
2582/**
2583 * i40e_aq_stop_lldp
2584 * @hw: pointer to the hw struct
2585 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2586 * @cmd_details: pointer to command details structure or NULL
2587 *
2588 * Stop or Shutdown the embedded LLDP Agent
2589 **/
2590i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2591 struct i40e_asq_cmd_details *cmd_details)
2592{
2593 struct i40e_aq_desc desc;
2594 struct i40e_aqc_lldp_stop *cmd =
2595 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2596 i40e_status status;
2597
2598 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2599
2600 if (shutdown_agent)
2601 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2602
2603 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2604
2605 return status;
2606}
2607
2608/**
2609 * i40e_aq_start_lldp
2610 * @hw: pointer to the hw struct
2611 * @cmd_details: pointer to command details structure or NULL
2612 *
2613 * Start the embedded LLDP Agent on all ports.
2614 **/
2615i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2616 struct i40e_asq_cmd_details *cmd_details)
2617{
2618 struct i40e_aq_desc desc;
2619 struct i40e_aqc_lldp_start *cmd =
2620 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2621 i40e_status status;
2622
2623 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2624
2625 cmd->command = I40E_AQ_LLDP_AGENT_START;
2626
2627 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2628
2629 return status;
2630}
2631
a1c9a9d9
JK		 2632/**
2633 * i40e_aq_add_udp_tunnel
2634 * @hw: pointer to the hw struct
2635 * @udp_port: the UDP port to add
2636 * @header_len: length of the tunneling header length in DWords
2637 * @protocol_index: protocol index type
98d44381 2638 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2639 * @cmd_details: pointer to command details structure or NULL
2640 **/
2641i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2642 u16 udp_port, u8 protocol_index,
2643 u8 *filter_index,
a1c9a9d9
JK		 2644 struct i40e_asq_cmd_details *cmd_details)
2645{
2646 struct i40e_aq_desc desc;
2647 struct i40e_aqc_add_udp_tunnel *cmd =
2648 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2649 struct i40e_aqc_del_udp_tunnel_completion *resp =
2650 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2651 i40e_status status;
2652
2653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2654
2655 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2656 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2657
2658 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2659
2660 if (!status)
2661 *filter_index = resp->index;
2662
2663 return status;
2664}
2665
2666/**
2667 * i40e_aq_del_udp_tunnel
2668 * @hw: pointer to the hw struct
2669 * @index: filter index
2670 * @cmd_details: pointer to command details structure or NULL
2671 **/
2672i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2673 struct i40e_asq_cmd_details *cmd_details)
2674{
2675 struct i40e_aq_desc desc;
2676 struct i40e_aqc_remove_udp_tunnel *cmd =
2677 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2678 i40e_status status;
2679
2680 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2681
2682 cmd->index = index;
2683
2684 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2685
2686 return status;
2687}
2688
56a62fc8
JB		 2689/**
2690 * i40e_aq_delete_element - Delete switch element
2691 * @hw: pointer to the hw struct
2692 * @seid: the SEID to delete from the switch
2693 * @cmd_details: pointer to command details structure or NULL
2694 *
2695 * This deletes a switch element from the switch.
2696 **/
2697i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2698 struct i40e_asq_cmd_details *cmd_details)
2699{
2700 struct i40e_aq_desc desc;
2701 struct i40e_aqc_switch_seid *cmd =
2702 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2703 i40e_status status;
2704
2705 if (seid == 0)
2706 return I40E_ERR_PARAM;
2707
2708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2709
2710 cmd->seid = cpu_to_le16(seid);
2711
2712 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2713
2714 return status;
2715}
2716
afb3ff0d
NP		 2717/**
2718 * i40e_aq_dcb_updated - DCB Updated Command
2719 * @hw: pointer to the hw struct
2720 * @cmd_details: pointer to command details structure or NULL
2721 *
2722 * EMP will return when the shared RPB settings have been
2723 * recomputed and modified. The retval field in the descriptor
2724 * will be set to 0 when RPB is modified.
2725 **/
2726i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2727 struct i40e_asq_cmd_details *cmd_details)
2728{
2729 struct i40e_aq_desc desc;
2730 i40e_status status;
2731
2732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2733
2734 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2735
2736 return status;
2737}
2738
56a62fc8
JB		 2739/**
2740 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2741 * @hw: pointer to the hw struct
2742 * @seid: seid for the physical port/switching component/vsi
2743 * @buff: Indirect buffer to hold data parameters and response
2744 * @buff_size: Indirect buffer size
2745 * @opcode: Tx scheduler AQ command opcode
2746 * @cmd_details: pointer to command details structure or NULL
2747 *
2748 * Generic command handler for Tx scheduler AQ commands
2749 **/
2750static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2751 void *buff, u16 buff_size,
2752 enum i40e_admin_queue_opc opcode,
2753 struct i40e_asq_cmd_details *cmd_details)
2754{
2755 struct i40e_aq_desc desc;
2756 struct i40e_aqc_tx_sched_ind *cmd =
2757 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2758 i40e_status status;
2759 bool cmd_param_flag = false;
2760
2761 switch (opcode) {
2762 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2763 case i40e_aqc_opc_configure_vsi_tc_bw:
2764 case i40e_aqc_opc_enable_switching_comp_ets:
2765 case i40e_aqc_opc_modify_switching_comp_ets:
2766 case i40e_aqc_opc_disable_switching_comp_ets:
2767 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2768 case i40e_aqc_opc_configure_switching_comp_bw_config:
2769 cmd_param_flag = true;
2770 break;
2771 case i40e_aqc_opc_query_vsi_bw_config:
2772 case i40e_aqc_opc_query_vsi_ets_sla_config:
2773 case i40e_aqc_opc_query_switching_comp_ets_config:
2774 case i40e_aqc_opc_query_port_ets_config:
2775 case i40e_aqc_opc_query_switching_comp_bw_config:
2776 cmd_param_flag = false;
2777 break;
2778 default:
2779 return I40E_ERR_PARAM;
2780 }
2781
2782 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2783
2784 /* Indirect command */
2785 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2786 if (cmd_param_flag)
2787 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2788 if (buff_size > I40E_AQ_LARGE_BUF)
2789 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2790
2791 desc.datalen = cpu_to_le16(buff_size);
2792
2793 cmd->vsi_seid = cpu_to_le16(seid);
2794
2795 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2796
2797 return status;
2798}
2799
6b192891
MW		 2800/**
2801 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2802 * @hw: pointer to the hw struct
2803 * @seid: VSI seid
2804 * @credit: BW limit credits (0 = disabled)
2805 * @max_credit: Max BW limit credits
2806 * @cmd_details: pointer to command details structure or NULL
2807 **/
2808i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2809 u16 seid, u16 credit, u8 max_credit,
2810 struct i40e_asq_cmd_details *cmd_details)
2811{
2812 struct i40e_aq_desc desc;
2813 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2814 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2815 i40e_status status;
2816
2817 i40e_fill_default_direct_cmd_desc(&desc,
2818 i40e_aqc_opc_configure_vsi_bw_limit);
2819
2820 cmd->vsi_seid = cpu_to_le16(seid);
2821 cmd->credit = cpu_to_le16(credit);
2822 cmd->max_credit = max_credit;
2823
2824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2825
2826 return status;
2827}
2828
56a62fc8
JB		 2829/**
2830 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2831 * @hw: pointer to the hw struct
2832 * @seid: VSI seid
2833 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2834 * @cmd_details: pointer to command details structure or NULL
2835 **/
2836i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2837 u16 seid,
2838 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2839 struct i40e_asq_cmd_details *cmd_details)
2840{
2841 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2842 i40e_aqc_opc_configure_vsi_tc_bw,
2843 cmd_details);
2844}
2845
afb3ff0d
NP		 2846/**
2847 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2848 * @hw: pointer to the hw struct
2849 * @seid: seid of the switching component connected to Physical Port
2850 * @ets_data: Buffer holding ETS parameters
2851 * @cmd_details: pointer to command details structure or NULL
2852 **/
2853i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2854 u16 seid,
2855 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2856 enum i40e_admin_queue_opc opcode,
2857 struct i40e_asq_cmd_details *cmd_details)
2858{
2859 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2860 sizeof(*ets_data), opcode, cmd_details);
2861}
2862
2863/**
2864 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2865 * @hw: pointer to the hw struct
2866 * @seid: seid of the switching component
2867 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2868 * @cmd_details: pointer to command details structure or NULL
2869 **/
2870i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2871 u16 seid,
2872 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2873 struct i40e_asq_cmd_details *cmd_details)
2874{
2875 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2876 i40e_aqc_opc_configure_switching_comp_bw_config,
2877 cmd_details);
2878}
2879
56a62fc8
JB		 2880/**
2881 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2882 * @hw: pointer to the hw struct
2883 * @seid: seid of the VSI
2884 * @bw_data: Buffer to hold VSI BW configuration
2885 * @cmd_details: pointer to command details structure or NULL
2886 **/
2887i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2888 u16 seid,
2889 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2890 struct i40e_asq_cmd_details *cmd_details)
2891{
2892 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2893 i40e_aqc_opc_query_vsi_bw_config,
2894 cmd_details);
2895}
2896
2897/**
2898 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2899 * @hw: pointer to the hw struct
2900 * @seid: seid of the VSI
2901 * @bw_data: Buffer to hold VSI BW configuration per TC
2902 * @cmd_details: pointer to command details structure or NULL
2903 **/
2904i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2905 u16 seid,
2906 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2907 struct i40e_asq_cmd_details *cmd_details)
2908{
2909 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2910 i40e_aqc_opc_query_vsi_ets_sla_config,
2911 cmd_details);
2912}
2913
2914/**
2915 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2916 * @hw: pointer to the hw struct
2917 * @seid: seid of the switching component
2918 * @bw_data: Buffer to hold switching component's per TC BW config
2919 * @cmd_details: pointer to command details structure or NULL
2920 **/
2921i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2922 u16 seid,
2923 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2924 struct i40e_asq_cmd_details *cmd_details)
2925{
2926 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2927 i40e_aqc_opc_query_switching_comp_ets_config,
2928 cmd_details);
2929}
2930
2931/**
2932 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2933 * @hw: pointer to the hw struct
2934 * @seid: seid of the VSI or switching component connected to Physical Port
2935 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2936 * @cmd_details: pointer to command details structure or NULL
2937 **/
2938i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2939 u16 seid,
2940 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2941 struct i40e_asq_cmd_details *cmd_details)
2942{
2943 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2944 i40e_aqc_opc_query_port_ets_config,
2945 cmd_details);
2946}
2947
2948/**
2949 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2950 * @hw: pointer to the hw struct
2951 * @seid: seid of the switching component
2952 * @bw_data: Buffer to hold switching component's BW configuration
2953 * @cmd_details: pointer to command details structure or NULL
2954 **/
2955i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2956 u16 seid,
2957 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2958 struct i40e_asq_cmd_details *cmd_details)
2959{
2960 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2961 i40e_aqc_opc_query_switching_comp_bw_config,
2962 cmd_details);
2963}
2964
2965/**
2966 * i40e_validate_filter_settings
2967 * @hw: pointer to the hardware structure
2968 * @settings: Filter control settings
2969 *
2970 * Check and validate the filter control settings passed.
2971 * The function checks for the valid filter/context sizes being
2972 * passed for FCoE and PE.
2973 *
2974 * Returns 0 if the values passed are valid and within
2975 * range else returns an error.
2976 **/
2977static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2978 struct i40e_filter_control_settings *settings)
2979{
2980 u32 fcoe_cntx_size, fcoe_filt_size;
2981 u32 pe_cntx_size, pe_filt_size;
467d729a 2982 u32 fcoe_fmax;
56a62fc8
JB		 2983 u32 val;
2984
2985 /* Validate FCoE settings passed */
2986 switch (settings->fcoe_filt_num) {
2987 case I40E_HASH_FILTER_SIZE_1K:
2988 case I40E_HASH_FILTER_SIZE_2K:
2989 case I40E_HASH_FILTER_SIZE_4K:
2990 case I40E_HASH_FILTER_SIZE_8K:
2991 case I40E_HASH_FILTER_SIZE_16K:
2992 case I40E_HASH_FILTER_SIZE_32K:
2993 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2994 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2995 break;
2996 default:
2997 return I40E_ERR_PARAM;
2998 }
2999
3000 switch (settings->fcoe_cntx_num) {
3001 case I40E_DMA_CNTX_SIZE_512:
3002 case I40E_DMA_CNTX_SIZE_1K:
3003 case I40E_DMA_CNTX_SIZE_2K:
3004 case I40E_DMA_CNTX_SIZE_4K:
3005 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3006 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3007 break;
3008 default:
3009 return I40E_ERR_PARAM;
3010 }
3011
3012 /* Validate PE settings passed */
3013 switch (settings->pe_filt_num) {
3014 case I40E_HASH_FILTER_SIZE_1K:
3015 case I40E_HASH_FILTER_SIZE_2K:
3016 case I40E_HASH_FILTER_SIZE_4K:
3017 case I40E_HASH_FILTER_SIZE_8K:
3018 case I40E_HASH_FILTER_SIZE_16K:
3019 case I40E_HASH_FILTER_SIZE_32K:
3020 case I40E_HASH_FILTER_SIZE_64K:
3021 case I40E_HASH_FILTER_SIZE_128K:
3022 case I40E_HASH_FILTER_SIZE_256K:
3023 case I40E_HASH_FILTER_SIZE_512K:
3024 case I40E_HASH_FILTER_SIZE_1M:
3025 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3026 pe_filt_size <<= (u32)settings->pe_filt_num;
3027 break;
3028 default:
3029 return I40E_ERR_PARAM;
3030 }
3031
3032 switch (settings->pe_cntx_num) {
3033 case I40E_DMA_CNTX_SIZE_512:
3034 case I40E_DMA_CNTX_SIZE_1K:
3035 case I40E_DMA_CNTX_SIZE_2K:
3036 case I40E_DMA_CNTX_SIZE_4K:
3037 case I40E_DMA_CNTX_SIZE_8K:
3038 case I40E_DMA_CNTX_SIZE_16K:
3039 case I40E_DMA_CNTX_SIZE_32K:
3040 case I40E_DMA_CNTX_SIZE_64K:
3041 case I40E_DMA_CNTX_SIZE_128K:
3042 case I40E_DMA_CNTX_SIZE_256K:
3043 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3044 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3045 break;
3046 default:
3047 return I40E_ERR_PARAM;
3048 }
3049
3050 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3051 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3052 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3053 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3054 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3055 return I40E_ERR_INVALID_SIZE;
3056
56a62fc8
JB		 3057 return 0;
3058}
3059
3060/**
3061 * i40e_set_filter_control
3062 * @hw: pointer to the hardware structure
3063 * @settings: Filter control settings
3064 *
3065 * Set the Queue Filters for PE/FCoE and enable filters required
3066 * for a single PF. It is expected that these settings are programmed
3067 * at the driver initialization time.
3068 **/
3069i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3070 struct i40e_filter_control_settings *settings)
3071{
3072 i40e_status ret = 0;
3073 u32 hash_lut_size = 0;
3074 u32 val;
3075
3076 if (!settings)
3077 return I40E_ERR_PARAM;
3078
3079 /* Validate the input settings */
3080 ret = i40e_validate_filter_settings(hw, settings);
3081 if (ret)
3082 return ret;
3083
3084 /* Read the PF Queue Filter control register */
3085 val = rd32(hw, I40E_PFQF_CTL_0);
3086
3087 /* Program required PE hash buckets for the PF */
3088 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3089 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3090 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3091 /* Program required PE contexts for the PF */
3092 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3093 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3094 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3095
3096 /* Program required FCoE hash buckets for the PF */
3097 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3098 val |= ((u32)settings->fcoe_filt_num <<
3099 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3100 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3101 /* Program required FCoE DDP contexts for the PF */
3102 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3103 val |= ((u32)settings->fcoe_cntx_num <<
3104 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3105 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3106
3107 /* Program Hash LUT size for the PF */
3108 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3109 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3110 hash_lut_size = 1;
3111 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3112 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3113
3114 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3115 if (settings->enable_fdir)
3116 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3117 if (settings->enable_ethtype)
3118 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3119 if (settings->enable_macvlan)
3120 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3121
3122 wr32(hw, I40E_PFQF_CTL_0, val);
3123
3124 return 0;
3125}
afb3ff0d
NP		 3126
3127/**
3128 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3129 * @hw: pointer to the hw struct
3130 * @mac_addr: MAC address to use in the filter
3131 * @ethtype: Ethertype to use in the filter
3132 * @flags: Flags that needs to be applied to the filter
3133 * @vsi_seid: seid of the control VSI
3134 * @queue: VSI queue number to send the packet to
3135 * @is_add: Add control packet filter if True else remove
3136 * @stats: Structure to hold information on control filter counts
3137 * @cmd_details: pointer to command details structure or NULL
3138 *
3139 * This command will Add or Remove control packet filter for a control VSI.
3140 * In return it will update the total number of perfect filter count in
3141 * the stats member.
3142 **/
3143i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3144 u8 *mac_addr, u16 ethtype, u16 flags,
3145 u16 vsi_seid, u16 queue, bool is_add,
3146 struct i40e_control_filter_stats *stats,
3147 struct i40e_asq_cmd_details *cmd_details)
3148{
3149 struct i40e_aq_desc desc;
3150 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3151 (struct i40e_aqc_add_remove_control_packet_filter *)
3152 &desc.params.raw;
3153 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3154 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3155 &desc.params.raw;
3156 i40e_status status;
3157
3158 if (vsi_seid == 0)
3159 return I40E_ERR_PARAM;
3160
3161 if (is_add) {
3162 i40e_fill_default_direct_cmd_desc(&desc,
3163 i40e_aqc_opc_add_control_packet_filter);
3164 cmd->queue = cpu_to_le16(queue);
3165 } else {
3166 i40e_fill_default_direct_cmd_desc(&desc,
3167 i40e_aqc_opc_remove_control_packet_filter);
3168 }
3169
3170 if (mac_addr)
3171 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3172
3173 cmd->etype = cpu_to_le16(ethtype);
3174 cmd->flags = cpu_to_le16(flags);
3175 cmd->seid = cpu_to_le16(vsi_seid);
3176
3177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3178
3179 if (!status && stats) {
3180 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3181 stats->etype_used = le16_to_cpu(resp->etype_used);
3182 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3183 stats->etype_free = le16_to_cpu(resp->etype_free);
3184 }
3185
3186 return status;
3187}
3188
d4dfb81a
CS		 3189/**
3190 * i40e_set_pci_config_data - store PCI bus info
3191 * @hw: pointer to hardware structure
3192 * @link_status: the link status word from PCI config space
3193 *
3194 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3195 **/
3196void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3197{
3198 hw->bus.type = i40e_bus_type_pci_express;
3199
3200 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3201 case PCI_EXP_LNKSTA_NLW_X1:
3202 hw->bus.width = i40e_bus_width_pcie_x1;
3203 break;
3204 case PCI_EXP_LNKSTA_NLW_X2:
3205 hw->bus.width = i40e_bus_width_pcie_x2;
3206 break;
3207 case PCI_EXP_LNKSTA_NLW_X4:
3208 hw->bus.width = i40e_bus_width_pcie_x4;
3209 break;
3210 case PCI_EXP_LNKSTA_NLW_X8:
3211 hw->bus.width = i40e_bus_width_pcie_x8;
3212 break;
3213 default:
3214 hw->bus.width = i40e_bus_width_unknown;
3215 break;
3216 }
3217
3218 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3219 case PCI_EXP_LNKSTA_CLS_2_5GB:
3220 hw->bus.speed = i40e_bus_speed_2500;
3221 break;
3222 case PCI_EXP_LNKSTA_CLS_5_0GB:
3223 hw->bus.speed = i40e_bus_speed_5000;
3224 break;
3225 case PCI_EXP_LNKSTA_CLS_8_0GB:
3226 hw->bus.speed = i40e_bus_speed_8000;
3227 break;
3228 default:
3229 hw->bus.speed = i40e_bus_speed_unknown;
3230 break;
3231 }
3232}
Linux kernel - Deliverables
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