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i40evf: remove debugging message
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e
SN		 45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_SFP_X710:
47 case I40E_DEV_ID_QEMU:
48 case I40E_DEV_ID_KX_A:
49 case I40E_DEV_ID_KX_B:
50 case I40E_DEV_ID_KX_C:
51 case I40E_DEV_ID_KX_D:
52 case I40E_DEV_ID_QSFP_A:
53 case I40E_DEV_ID_QSFP_B:
54 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 55 hw->mac.type = I40E_MAC_XL710;
56 break;
ab60085e
SN		 57 case I40E_DEV_ID_VF:
58 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 59 hw->mac.type = I40E_MAC_VF;
60 break;
61 default:
62 hw->mac.type = I40E_MAC_GENERIC;
63 break;
64 }
65 } else {
66 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
67 }
68
69 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
70 hw->mac.type, status);
71 return status;
72}
73
74/**
75 * i40e_debug_aq
76 * @hw: debug mask related to admin queue
98d44381
JK		 77 * @mask: debug mask
78 * @desc: pointer to admin queue descriptor
56a62fc8
JB		 79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
e1860d8f
ASJ		 128/**
129 * i40e_check_asq_alive
130 * @hw: pointer to the hw struct
131 *
132 * Returns true if Queue is enabled else false.
133 **/
134bool i40e_check_asq_alive(struct i40e_hw *hw)
135{
136 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
137}
138
139/**
140 * i40e_aq_queue_shutdown
141 * @hw: pointer to the hw struct
142 * @unloading: is the driver unloading itself
143 *
144 * Tell the Firmware that we're shutting down the AdminQ and whether
145 * or not the driver is unloading as well.
146 **/
147i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
148 bool unloading)
149{
150 struct i40e_aq_desc desc;
151 struct i40e_aqc_queue_shutdown *cmd =
152 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
153 i40e_status status;
154
155 i40e_fill_default_direct_cmd_desc(&desc,
156 i40e_aqc_opc_queue_shutdown);
157
158 if (unloading)
159 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
160 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
161
162 return status;
163}
164
206812b5
JB		 165/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
166 * hardware to a bit-field that can be used by SW to more easily determine the
167 * packet type.
168 *
169 * Macros are used to shorten the table lines and make this table human
170 * readable.
171 *
172 * We store the PTYPE in the top byte of the bit field - this is just so that
173 * we can check that the table doesn't have a row missing, as the index into
174 * the table should be the PTYPE.
175 *
176 * Typical work flow:
177 *
178 * IF NOT i40e_ptype_lookup[ptype].known
179 * THEN
180 * Packet is unknown
181 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
182 * Use the rest of the fields to look at the tunnels, inner protocols, etc
183 * ELSE
184 * Use the enum i40e_rx_l2_ptype to decode the packet type
185 * ENDIF
186 */
187
188/* macro to make the table lines short */
189#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
190 { PTYPE, \
191 1, \
192 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
193 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
194 I40E_RX_PTYPE_##OUTER_FRAG, \
195 I40E_RX_PTYPE_TUNNEL_##T, \
196 I40E_RX_PTYPE_TUNNEL_END_##TE, \
197 I40E_RX_PTYPE_##TEF, \
198 I40E_RX_PTYPE_INNER_PROT_##I, \
199 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
200
201#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
202 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
203
204/* shorter macros makes the table fit but are terse */
205#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
206#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
207#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
208
209/* Lookup table mapping the HW PTYPE to the bit field for decoding */
210struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
211 /* L2 Packet types */
212 I40E_PTT_UNUSED_ENTRY(0),
213 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
214 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
215 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT_UNUSED_ENTRY(4),
217 I40E_PTT_UNUSED_ENTRY(5),
218 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
219 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
220 I40E_PTT_UNUSED_ENTRY(8),
221 I40E_PTT_UNUSED_ENTRY(9),
222 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
224 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
225 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
226 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234
235 /* Non Tunneled IPv4 */
236 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
239 I40E_PTT_UNUSED_ENTRY(25),
240 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
241 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
242 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
243
244 /* IPv4 --> IPv4 */
245 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
246 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
247 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
248 I40E_PTT_UNUSED_ENTRY(32),
249 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
250 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
251 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
252
253 /* IPv4 --> IPv6 */
254 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
255 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
256 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
257 I40E_PTT_UNUSED_ENTRY(39),
258 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
259 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
260 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
261
262 /* IPv4 --> GRE/NAT */
263 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
264
265 /* IPv4 --> GRE/NAT --> IPv4 */
266 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
267 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
268 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
269 I40E_PTT_UNUSED_ENTRY(47),
270 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
271 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
272 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
273
274 /* IPv4 --> GRE/NAT --> IPv6 */
275 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
276 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
277 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
278 I40E_PTT_UNUSED_ENTRY(54),
279 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
280 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
281 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
282
283 /* IPv4 --> GRE/NAT --> MAC */
284 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
285
286 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
287 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
288 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
289 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
290 I40E_PTT_UNUSED_ENTRY(62),
291 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
292 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
293 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
294
295 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
296 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
297 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
298 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
299 I40E_PTT_UNUSED_ENTRY(69),
300 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
301 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
302 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
303
304 /* IPv4 --> GRE/NAT --> MAC/VLAN */
305 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
306
307 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
308 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
309 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
310 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
311 I40E_PTT_UNUSED_ENTRY(77),
312 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
313 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
314 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
315
316 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
317 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
318 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
319 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
320 I40E_PTT_UNUSED_ENTRY(84),
321 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
322 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
323 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
324
325 /* Non Tunneled IPv6 */
326 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
327 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
328 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
329 I40E_PTT_UNUSED_ENTRY(91),
330 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
331 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
332 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
333
334 /* IPv6 --> IPv4 */
335 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
336 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
337 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
338 I40E_PTT_UNUSED_ENTRY(98),
339 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
340 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
341 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
342
343 /* IPv6 --> IPv6 */
344 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
345 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
346 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
347 I40E_PTT_UNUSED_ENTRY(105),
348 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
349 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
350 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
351
352 /* IPv6 --> GRE/NAT */
353 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
354
355 /* IPv6 --> GRE/NAT -> IPv4 */
356 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
357 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
358 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
359 I40E_PTT_UNUSED_ENTRY(113),
360 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
361 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
362 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
363
364 /* IPv6 --> GRE/NAT -> IPv6 */
365 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
366 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
367 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
368 I40E_PTT_UNUSED_ENTRY(120),
369 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
370 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
371 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
372
373 /* IPv6 --> GRE/NAT -> MAC */
374 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
375
376 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
377 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
378 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
379 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
380 I40E_PTT_UNUSED_ENTRY(128),
381 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
382 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
383 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
384
385 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
386 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
387 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
388 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
389 I40E_PTT_UNUSED_ENTRY(135),
390 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
391 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
392 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
393
394 /* IPv6 --> GRE/NAT -> MAC/VLAN */
395 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
396
397 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
398 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
399 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
400 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
401 I40E_PTT_UNUSED_ENTRY(143),
402 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
403 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
404 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
405
406 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
407 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
408 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
409 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
410 I40E_PTT_UNUSED_ENTRY(150),
411 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
412 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
413 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
414
415 /* unused entries */
416 I40E_PTT_UNUSED_ENTRY(154),
417 I40E_PTT_UNUSED_ENTRY(155),
418 I40E_PTT_UNUSED_ENTRY(156),
419 I40E_PTT_UNUSED_ENTRY(157),
420 I40E_PTT_UNUSED_ENTRY(158),
421 I40E_PTT_UNUSED_ENTRY(159),
422
423 I40E_PTT_UNUSED_ENTRY(160),
424 I40E_PTT_UNUSED_ENTRY(161),
425 I40E_PTT_UNUSED_ENTRY(162),
426 I40E_PTT_UNUSED_ENTRY(163),
427 I40E_PTT_UNUSED_ENTRY(164),
428 I40E_PTT_UNUSED_ENTRY(165),
429 I40E_PTT_UNUSED_ENTRY(166),
430 I40E_PTT_UNUSED_ENTRY(167),
431 I40E_PTT_UNUSED_ENTRY(168),
432 I40E_PTT_UNUSED_ENTRY(169),
433
434 I40E_PTT_UNUSED_ENTRY(170),
435 I40E_PTT_UNUSED_ENTRY(171),
436 I40E_PTT_UNUSED_ENTRY(172),
437 I40E_PTT_UNUSED_ENTRY(173),
438 I40E_PTT_UNUSED_ENTRY(174),
439 I40E_PTT_UNUSED_ENTRY(175),
440 I40E_PTT_UNUSED_ENTRY(176),
441 I40E_PTT_UNUSED_ENTRY(177),
442 I40E_PTT_UNUSED_ENTRY(178),
443 I40E_PTT_UNUSED_ENTRY(179),
444
445 I40E_PTT_UNUSED_ENTRY(180),
446 I40E_PTT_UNUSED_ENTRY(181),
447 I40E_PTT_UNUSED_ENTRY(182),
448 I40E_PTT_UNUSED_ENTRY(183),
449 I40E_PTT_UNUSED_ENTRY(184),
450 I40E_PTT_UNUSED_ENTRY(185),
451 I40E_PTT_UNUSED_ENTRY(186),
452 I40E_PTT_UNUSED_ENTRY(187),
453 I40E_PTT_UNUSED_ENTRY(188),
454 I40E_PTT_UNUSED_ENTRY(189),
455
456 I40E_PTT_UNUSED_ENTRY(190),
457 I40E_PTT_UNUSED_ENTRY(191),
458 I40E_PTT_UNUSED_ENTRY(192),
459 I40E_PTT_UNUSED_ENTRY(193),
460 I40E_PTT_UNUSED_ENTRY(194),
461 I40E_PTT_UNUSED_ENTRY(195),
462 I40E_PTT_UNUSED_ENTRY(196),
463 I40E_PTT_UNUSED_ENTRY(197),
464 I40E_PTT_UNUSED_ENTRY(198),
465 I40E_PTT_UNUSED_ENTRY(199),
466
467 I40E_PTT_UNUSED_ENTRY(200),
468 I40E_PTT_UNUSED_ENTRY(201),
469 I40E_PTT_UNUSED_ENTRY(202),
470 I40E_PTT_UNUSED_ENTRY(203),
471 I40E_PTT_UNUSED_ENTRY(204),
472 I40E_PTT_UNUSED_ENTRY(205),
473 I40E_PTT_UNUSED_ENTRY(206),
474 I40E_PTT_UNUSED_ENTRY(207),
475 I40E_PTT_UNUSED_ENTRY(208),
476 I40E_PTT_UNUSED_ENTRY(209),
477
478 I40E_PTT_UNUSED_ENTRY(210),
479 I40E_PTT_UNUSED_ENTRY(211),
480 I40E_PTT_UNUSED_ENTRY(212),
481 I40E_PTT_UNUSED_ENTRY(213),
482 I40E_PTT_UNUSED_ENTRY(214),
483 I40E_PTT_UNUSED_ENTRY(215),
484 I40E_PTT_UNUSED_ENTRY(216),
485 I40E_PTT_UNUSED_ENTRY(217),
486 I40E_PTT_UNUSED_ENTRY(218),
487 I40E_PTT_UNUSED_ENTRY(219),
488
489 I40E_PTT_UNUSED_ENTRY(220),
490 I40E_PTT_UNUSED_ENTRY(221),
491 I40E_PTT_UNUSED_ENTRY(222),
492 I40E_PTT_UNUSED_ENTRY(223),
493 I40E_PTT_UNUSED_ENTRY(224),
494 I40E_PTT_UNUSED_ENTRY(225),
495 I40E_PTT_UNUSED_ENTRY(226),
496 I40E_PTT_UNUSED_ENTRY(227),
497 I40E_PTT_UNUSED_ENTRY(228),
498 I40E_PTT_UNUSED_ENTRY(229),
499
500 I40E_PTT_UNUSED_ENTRY(230),
501 I40E_PTT_UNUSED_ENTRY(231),
502 I40E_PTT_UNUSED_ENTRY(232),
503 I40E_PTT_UNUSED_ENTRY(233),
504 I40E_PTT_UNUSED_ENTRY(234),
505 I40E_PTT_UNUSED_ENTRY(235),
506 I40E_PTT_UNUSED_ENTRY(236),
507 I40E_PTT_UNUSED_ENTRY(237),
508 I40E_PTT_UNUSED_ENTRY(238),
509 I40E_PTT_UNUSED_ENTRY(239),
510
511 I40E_PTT_UNUSED_ENTRY(240),
512 I40E_PTT_UNUSED_ENTRY(241),
513 I40E_PTT_UNUSED_ENTRY(242),
514 I40E_PTT_UNUSED_ENTRY(243),
515 I40E_PTT_UNUSED_ENTRY(244),
516 I40E_PTT_UNUSED_ENTRY(245),
517 I40E_PTT_UNUSED_ENTRY(246),
518 I40E_PTT_UNUSED_ENTRY(247),
519 I40E_PTT_UNUSED_ENTRY(248),
520 I40E_PTT_UNUSED_ENTRY(249),
521
522 I40E_PTT_UNUSED_ENTRY(250),
523 I40E_PTT_UNUSED_ENTRY(251),
524 I40E_PTT_UNUSED_ENTRY(252),
525 I40E_PTT_UNUSED_ENTRY(253),
526 I40E_PTT_UNUSED_ENTRY(254),
527 I40E_PTT_UNUSED_ENTRY(255)
528};
529
530
56a62fc8
JB		 531/**
532 * i40e_init_shared_code - Initialize the shared code
533 * @hw: pointer to hardware structure
534 *
535 * This assigns the MAC type and PHY code and inits the NVM.
536 * Does not touch the hardware. This function must be called prior to any
537 * other function in the shared code. The i40e_hw structure should be
538 * memset to 0 prior to calling this function. The following fields in
539 * hw structure should be filled in prior to calling this function:
540 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
541 * subsystem_vendor_id, and revision_id
542 **/
543i40e_status i40e_init_shared_code(struct i40e_hw *hw)
544{
545 i40e_status status = 0;
546 u32 reg;
547
56a62fc8
JB		 548 i40e_set_mac_type(hw);
549
550 switch (hw->mac.type) {
551 case I40E_MAC_XL710:
552 break;
553 default:
554 return I40E_ERR_DEVICE_NOT_SUPPORTED;
555 break;
556 }
557
af89d26c
SN		 558 hw->phy.get_link_info = true;
559
560 /* Determine port number */
561 reg = rd32(hw, I40E_PFGEN_PORTNUM);
562 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
563 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
564 hw->port = (u8)reg;
565
5f9116ac
SN		 566 /* Determine the PF number based on the PCI fn */
567 reg = rd32(hw, I40E_GLPCI_CAPSUP);
568 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
569 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
570 else
571 hw->pf_id = (u8)hw->bus.func;
572
56a62fc8
JB		 573 status = i40e_init_nvm(hw);
574 return status;
575}
576
577/**
578 * i40e_aq_mac_address_read - Retrieve the MAC addresses
579 * @hw: pointer to the hw struct
580 * @flags: a return indicator of what addresses were added to the addr store
581 * @addrs: the requestor's mac addr store
582 * @cmd_details: pointer to command details structure or NULL
583 **/
584static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
585 u16 *flags,
586 struct i40e_aqc_mac_address_read_data *addrs,
587 struct i40e_asq_cmd_details *cmd_details)
588{
589 struct i40e_aq_desc desc;
590 struct i40e_aqc_mac_address_read *cmd_data =
591 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
592 i40e_status status;
593
594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
595 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
596
597 status = i40e_asq_send_command(hw, &desc, addrs,
598 sizeof(*addrs), cmd_details);
599 *flags = le16_to_cpu(cmd_data->command_flags);
600
601 return status;
602}
603
604/**
605 * i40e_aq_mac_address_write - Change the MAC addresses
606 * @hw: pointer to the hw struct
607 * @flags: indicates which MAC to be written
608 * @mac_addr: address to write
609 * @cmd_details: pointer to command details structure or NULL
610 **/
611i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
612 u16 flags, u8 *mac_addr,
613 struct i40e_asq_cmd_details *cmd_details)
614{
615 struct i40e_aq_desc desc;
616 struct i40e_aqc_mac_address_write *cmd_data =
617 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
618 i40e_status status;
619
620 i40e_fill_default_direct_cmd_desc(&desc,
621 i40e_aqc_opc_mac_address_write);
622 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 623 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
624 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
625 ((u32)mac_addr[3] << 16) |
626 ((u32)mac_addr[4] << 8) |
627 mac_addr[5]);
56a62fc8
JB		 628
629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
630
631 return status;
632}
633
634/**
635 * i40e_get_mac_addr - get MAC address
636 * @hw: pointer to the HW structure
637 * @mac_addr: pointer to MAC address
638 *
639 * Reads the adapter's MAC address from register
640 **/
641i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
642{
643 struct i40e_aqc_mac_address_read_data addrs;
644 i40e_status status;
645 u16 flags = 0;
646
647 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
648
649 if (flags & I40E_AQC_LAN_ADDR_VALID)
650 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
651
652 return status;
653}
654
be405eb0
JB		 655/**
656 * i40e_get_media_type - Gets media type
657 * @hw: pointer to the hardware structure
658 **/
659static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
660{
661 enum i40e_media_type media;
662
663 switch (hw->phy.link_info.phy_type) {
664 case I40E_PHY_TYPE_10GBASE_SR:
665 case I40E_PHY_TYPE_10GBASE_LR:
666 case I40E_PHY_TYPE_40GBASE_SR4:
667 case I40E_PHY_TYPE_40GBASE_LR4:
668 media = I40E_MEDIA_TYPE_FIBER;
669 break;
670 case I40E_PHY_TYPE_100BASE_TX:
671 case I40E_PHY_TYPE_1000BASE_T:
672 case I40E_PHY_TYPE_10GBASE_T:
673 media = I40E_MEDIA_TYPE_BASET;
674 break;
675 case I40E_PHY_TYPE_10GBASE_CR1_CU:
676 case I40E_PHY_TYPE_40GBASE_CR4_CU:
677 case I40E_PHY_TYPE_10GBASE_CR1:
678 case I40E_PHY_TYPE_40GBASE_CR4:
679 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
680 media = I40E_MEDIA_TYPE_DA;
681 break;
682 case I40E_PHY_TYPE_1000BASE_KX:
683 case I40E_PHY_TYPE_10GBASE_KX4:
684 case I40E_PHY_TYPE_10GBASE_KR:
685 case I40E_PHY_TYPE_40GBASE_KR4:
686 media = I40E_MEDIA_TYPE_BACKPLANE;
687 break;
688 case I40E_PHY_TYPE_SGMII:
689 case I40E_PHY_TYPE_XAUI:
690 case I40E_PHY_TYPE_XFI:
691 case I40E_PHY_TYPE_XLAUI:
692 case I40E_PHY_TYPE_XLPPI:
693 default:
694 media = I40E_MEDIA_TYPE_UNKNOWN;
695 break;
696 }
697
698 return media;
699}
700
7134f9ce
JB		 701#define I40E_PF_RESET_WAIT_COUNT_A0 200
702#define I40E_PF_RESET_WAIT_COUNT 10
56a62fc8
JB		 703/**
704 * i40e_pf_reset - Reset the PF
705 * @hw: pointer to the hardware structure
706 *
707 * Assuming someone else has triggered a global reset,
708 * assure the global reset is complete and then reset the PF
709 **/
710i40e_status i40e_pf_reset(struct i40e_hw *hw)
711{
7134f9ce 712 u32 cnt = 0;
42794bd8 713 u32 cnt1 = 0;
56a62fc8
JB		 714 u32 reg = 0;
715 u32 grst_del;
716
717 /* Poll for Global Reset steady state in case of recent GRST.
718 * The grst delay value is in 100ms units, and we'll wait a
719 * couple counts longer to be sure we don't just miss the end.
720 */
721 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
722 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 723 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 724 reg = rd32(hw, I40E_GLGEN_RSTAT);
725 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
726 break;
727 msleep(100);
728 }
729 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
730 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 731 return I40E_ERR_RESET_FAILED;
732 }
733
734 /* Now Wait for the FW to be ready */
735 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
736 reg = rd32(hw, I40E_GLNVM_ULD);
737 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
738 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
739 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
740 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
741 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
742 break;
743 }
744 usleep_range(10000, 20000);
745 }
746 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
747 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
748 hw_dbg(hw, "wait for FW Reset complete timedout\n");
749 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 750 return I40E_ERR_RESET_FAILED;
751 }
752
56a62fc8
JB		 753 /* If there was a Global Reset in progress when we got here,
754 * we don't need to do the PF Reset
755 */
7134f9ce
JB		 756 if (!cnt) {
757 if (hw->revision_id == 0)
758 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
759 else
760 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 761 reg = rd32(hw, I40E_PFGEN_CTRL);
762 wr32(hw, I40E_PFGEN_CTRL,
763 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 764 for (; cnt; cnt--) {
56a62fc8
JB		 765 reg = rd32(hw, I40E_PFGEN_CTRL);
766 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
767 break;
768 usleep_range(1000, 2000);
769 }
770 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
771 hw_dbg(hw, "PF reset polling failed to complete.\n");
772 return I40E_ERR_RESET_FAILED;
773 }
774 }
775
776 i40e_clear_pxe_mode(hw);
922680b9 777
56a62fc8
JB		 778 return 0;
779}
780
781/**
782 * i40e_clear_pxe_mode - clear pxe operations mode
783 * @hw: pointer to the hw struct
784 *
785 * Make sure all PXE mode settings are cleared, including things
786 * like descriptor fetch/write-back mode.
787 **/
788void i40e_clear_pxe_mode(struct i40e_hw *hw)
789{
790 u32 reg;
791
792 /* Clear single descriptor fetch/write-back mode */
793 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 794
795 if (hw->revision_id == 0) {
796 /* As a work around clear PXE_MODE instead of setting it */
797 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
798 } else {
799 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
800 }
56a62fc8
JB		 801}
802
0556a9e3
JB		 803/**
804 * i40e_led_is_mine - helper to find matching led
805 * @hw: pointer to the hw struct
806 * @idx: index into GPIO registers
807 *
808 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
809 */
810static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
811{
812 u32 gpio_val = 0;
813 u32 port;
814
815 if (!hw->func_caps.led[idx])
816 return 0;
817
818 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
819 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
820 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
821
822 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
823 * if it is not our port then ignore
824 */
825 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
826 (port != hw->port))
827 return 0;
828
829 return gpio_val;
830}
831
832#define I40E_LED0 22
833#define I40E_LINK_ACTIVITY 0xC
834
56a62fc8
JB		 835/**
836 * i40e_led_get - return current on/off mode
837 * @hw: pointer to the hw struct
838 *
839 * The value returned is the 'mode' field as defined in the
840 * GPIO register definitions: 0x0 = off, 0xf = on, and other
841 * values are variations of possible behaviors relating to
842 * blink, link, and wire.
843 **/
844u32 i40e_led_get(struct i40e_hw *hw)
845{
56a62fc8 846 u32 mode = 0;
56a62fc8
JB		 847 int i;
848
0556a9e3
JB		 849 /* as per the documentation GPIO 22-29 are the LED
850 * GPIO pins named LED0..LED7
851 */
852 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
853 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 854
0556a9e3 855 if (!gpio_val)
56a62fc8
JB		 856 continue;
857
0556a9e3
JB		 858 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
859 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 860 break;
861 }
862
863 return mode;
864}
865
866/**
867 * i40e_led_set - set new on/off mode
868 * @hw: pointer to the hw struct
0556a9e3
JB		 869 * @mode: 0=off, 0xf=on (else see manual for mode details)
870 * @blink: true if the LED should blink when on, false if steady
871 *
872 * if this function is used to turn on the blink it should
873 * be used to disable the blink when restoring the original state.
56a62fc8 874 **/
0556a9e3 875void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 876{
56a62fc8
JB		 877 int i;
878
0556a9e3
JB		 879 if (mode & 0xfffffff0)
880 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 881
0556a9e3
JB		 882 /* as per the documentation GPIO 22-29 are the LED
883 * GPIO pins named LED0..LED7
884 */
885 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
886 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 887
0556a9e3 888 if (!gpio_val)
56a62fc8
JB		 889 continue;
890
56a62fc8 891 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 892 /* this & is a bit of paranoia, but serves as a range check */
893 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
894 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
895
896 if (mode == I40E_LINK_ACTIVITY)
897 blink = false;
898
899 gpio_val |= (blink ? 1 : 0) <<
900 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
901
56a62fc8 902 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 903 break;
56a62fc8
JB		 904 }
905}
906
907/* Admin command wrappers */
56a62fc8
JB		 908
909/**
910 * i40e_aq_set_link_restart_an
911 * @hw: pointer to the hw struct
912 * @cmd_details: pointer to command details structure or NULL
913 *
914 * Sets up the link and restarts the Auto-Negotiation over the link.
915 **/
916i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
917 struct i40e_asq_cmd_details *cmd_details)
918{
919 struct i40e_aq_desc desc;
920 struct i40e_aqc_set_link_restart_an *cmd =
921 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
922 i40e_status status;
923
924 i40e_fill_default_direct_cmd_desc(&desc,
925 i40e_aqc_opc_set_link_restart_an);
926
927 cmd->command = I40E_AQ_PHY_RESTART_AN;
928
929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
930
931 return status;
932}
933
934/**
935 * i40e_aq_get_link_info
936 * @hw: pointer to the hw struct
937 * @enable_lse: enable/disable LinkStatusEvent reporting
938 * @link: pointer to link status structure - optional
939 * @cmd_details: pointer to command details structure or NULL
940 *
941 * Returns the link status of the adapter.
942 **/
943i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
944 bool enable_lse, struct i40e_link_status *link,
945 struct i40e_asq_cmd_details *cmd_details)
946{
947 struct i40e_aq_desc desc;
948 struct i40e_aqc_get_link_status *resp =
949 (struct i40e_aqc_get_link_status *)&desc.params.raw;
950 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
951 i40e_status status;
952 u16 command_flags;
953
954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
955
956 if (enable_lse)
957 command_flags = I40E_AQ_LSE_ENABLE;
958 else
959 command_flags = I40E_AQ_LSE_DISABLE;
960 resp->command_flags = cpu_to_le16(command_flags);
961
962 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
963
964 if (status)
965 goto aq_get_link_info_exit;
966
967 /* save off old link status information */
c36bd4a7 968 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 969
970 /* update link status */
971 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 972 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 973 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
974 hw_link_info->link_info = resp->link_info;
975 hw_link_info->an_info = resp->an_info;
976 hw_link_info->ext_info = resp->ext_info;
639dc377 977 hw_link_info->loopback = resp->loopback;
56a62fc8
JB		 978
979 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
980 hw_link_info->lse_enable = true;
981 else
982 hw_link_info->lse_enable = false;
983
984 /* save link status information */
985 if (link)
d7595a22 986 *link = *hw_link_info;
56a62fc8
JB		 987
988 /* flag cleared so helper functions don't call AQ again */
989 hw->phy.get_link_info = false;
990
991aq_get_link_info_exit:
992 return status;
993}
994
995/**
996 * i40e_aq_add_vsi
997 * @hw: pointer to the hw struct
98d44381 998 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 999 * @cmd_details: pointer to command details structure or NULL
1000 *
1001 * Add a VSI context to the hardware.
1002**/
1003i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1004 struct i40e_vsi_context *vsi_ctx,
1005 struct i40e_asq_cmd_details *cmd_details)
1006{
1007 struct i40e_aq_desc desc;
1008 struct i40e_aqc_add_get_update_vsi *cmd =
1009 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1010 struct i40e_aqc_add_get_update_vsi_completion *resp =
1011 (struct i40e_aqc_add_get_update_vsi_completion *)
1012 &desc.params.raw;
1013 i40e_status status;
1014
1015 i40e_fill_default_direct_cmd_desc(&desc,
1016 i40e_aqc_opc_add_vsi);
1017
1018 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1019 cmd->connection_type = vsi_ctx->connection_type;
1020 cmd->vf_id = vsi_ctx->vf_num;
1021 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1022
1023 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1024 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1025 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1026
1027 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1028 sizeof(vsi_ctx->info), cmd_details);
1029
1030 if (status)
1031 goto aq_add_vsi_exit;
1032
1033 vsi_ctx->seid = le16_to_cpu(resp->seid);
1034 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1035 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1036 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1037
1038aq_add_vsi_exit:
1039 return status;
1040}
1041
1042/**
1043 * i40e_aq_set_vsi_unicast_promiscuous
1044 * @hw: pointer to the hw struct
1045 * @seid: vsi number
1046 * @set: set unicast promiscuous enable/disable
1047 * @cmd_details: pointer to command details structure or NULL
1048 **/
1049i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1050 u16 seid, bool set,
1051 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1052{
1053 struct i40e_aq_desc desc;
1054 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1055 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1056 i40e_status status;
1057 u16 flags = 0;
1058
1059 i40e_fill_default_direct_cmd_desc(&desc,
1060 i40e_aqc_opc_set_vsi_promiscuous_modes);
1061
1062 if (set)
1063 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1064
1065 cmd->promiscuous_flags = cpu_to_le16(flags);
1066
1067 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1068
1069 cmd->seid = cpu_to_le16(seid);
1070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1071
1072 return status;
1073}
1074
1075/**
1076 * i40e_aq_set_vsi_multicast_promiscuous
1077 * @hw: pointer to the hw struct
1078 * @seid: vsi number
1079 * @set: set multicast promiscuous enable/disable
1080 * @cmd_details: pointer to command details structure or NULL
1081 **/
1082i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1083 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1084{
1085 struct i40e_aq_desc desc;
1086 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1087 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1088 i40e_status status;
1089 u16 flags = 0;
1090
1091 i40e_fill_default_direct_cmd_desc(&desc,
1092 i40e_aqc_opc_set_vsi_promiscuous_modes);
1093
1094 if (set)
1095 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1096
1097 cmd->promiscuous_flags = cpu_to_le16(flags);
1098
1099 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1100
1101 cmd->seid = cpu_to_le16(seid);
1102 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1103
1104 return status;
1105}
1106
1107/**
1108 * i40e_aq_set_vsi_broadcast
1109 * @hw: pointer to the hw struct
1110 * @seid: vsi number
1111 * @set_filter: true to set filter, false to clear filter
1112 * @cmd_details: pointer to command details structure or NULL
1113 *
1114 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1115 **/
1116i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1117 u16 seid, bool set_filter,
1118 struct i40e_asq_cmd_details *cmd_details)
1119{
1120 struct i40e_aq_desc desc;
1121 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1122 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1123 i40e_status status;
1124
1125 i40e_fill_default_direct_cmd_desc(&desc,
1126 i40e_aqc_opc_set_vsi_promiscuous_modes);
1127
1128 if (set_filter)
1129 cmd->promiscuous_flags
1130 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1131 else
1132 cmd->promiscuous_flags
1133 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1134
1135 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1136 cmd->seid = cpu_to_le16(seid);
1137 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1138
1139 return status;
1140}
1141
1142/**
1143 * i40e_get_vsi_params - get VSI configuration info
1144 * @hw: pointer to the hw struct
98d44381 1145 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1146 * @cmd_details: pointer to command details structure or NULL
1147 **/
1148i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1149 struct i40e_vsi_context *vsi_ctx,
1150 struct i40e_asq_cmd_details *cmd_details)
1151{
1152 struct i40e_aq_desc desc;
f5ac8579
SN		 1153 struct i40e_aqc_add_get_update_vsi *cmd =
1154 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1155 struct i40e_aqc_add_get_update_vsi_completion *resp =
1156 (struct i40e_aqc_add_get_update_vsi_completion *)
1157 &desc.params.raw;
1158 i40e_status status;
1159
1160 i40e_fill_default_direct_cmd_desc(&desc,
1161 i40e_aqc_opc_get_vsi_parameters);
1162
f5ac8579 1163 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1164
1165 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1166 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1167 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1168
1169 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1170 sizeof(vsi_ctx->info), NULL);
1171
1172 if (status)
1173 goto aq_get_vsi_params_exit;
1174
1175 vsi_ctx->seid = le16_to_cpu(resp->seid);
1176 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1177 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1178 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1179
1180aq_get_vsi_params_exit:
1181 return status;
1182}
1183
1184/**
1185 * i40e_aq_update_vsi_params
1186 * @hw: pointer to the hw struct
98d44381 1187 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1188 * @cmd_details: pointer to command details structure or NULL
1189 *
1190 * Update a VSI context.
1191 **/
1192i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1193 struct i40e_vsi_context *vsi_ctx,
1194 struct i40e_asq_cmd_details *cmd_details)
1195{
1196 struct i40e_aq_desc desc;
f5ac8579
SN		 1197 struct i40e_aqc_add_get_update_vsi *cmd =
1198 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1199 i40e_status status;
1200
1201 i40e_fill_default_direct_cmd_desc(&desc,
1202 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1203 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1204
1205 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1206 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1207 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1208
1209 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1210 sizeof(vsi_ctx->info), cmd_details);
1211
1212 return status;
1213}
1214
1215/**
1216 * i40e_aq_get_switch_config
1217 * @hw: pointer to the hardware structure
1218 * @buf: pointer to the result buffer
1219 * @buf_size: length of input buffer
1220 * @start_seid: seid to start for the report, 0 == beginning
1221 * @cmd_details: pointer to command details structure or NULL
1222 *
1223 * Fill the buf with switch configuration returned from AdminQ command
1224 **/
1225i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1226 struct i40e_aqc_get_switch_config_resp *buf,
1227 u16 buf_size, u16 *start_seid,
1228 struct i40e_asq_cmd_details *cmd_details)
1229{
1230 struct i40e_aq_desc desc;
1231 struct i40e_aqc_switch_seid *scfg =
1232 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1233 i40e_status status;
1234
1235 i40e_fill_default_direct_cmd_desc(&desc,
1236 i40e_aqc_opc_get_switch_config);
1237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1238 if (buf_size > I40E_AQ_LARGE_BUF)
1239 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1240 scfg->seid = cpu_to_le16(*start_seid);
1241
1242 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1243 *start_seid = le16_to_cpu(scfg->seid);
1244
1245 return status;
1246}
1247
1248/**
1249 * i40e_aq_get_firmware_version
1250 * @hw: pointer to the hw struct
1251 * @fw_major_version: firmware major version
1252 * @fw_minor_version: firmware minor version
1253 * @api_major_version: major queue version
1254 * @api_minor_version: minor queue version
1255 * @cmd_details: pointer to command details structure or NULL
1256 *
1257 * Get the firmware version from the admin queue commands
1258 **/
1259i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1260 u16 *fw_major_version, u16 *fw_minor_version,
1261 u16 *api_major_version, u16 *api_minor_version,
1262 struct i40e_asq_cmd_details *cmd_details)
1263{
1264 struct i40e_aq_desc desc;
1265 struct i40e_aqc_get_version *resp =
1266 (struct i40e_aqc_get_version *)&desc.params.raw;
1267 i40e_status status;
1268
1269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1270
1271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1272
1273 if (!status) {
1274 if (fw_major_version != NULL)
1275 *fw_major_version = le16_to_cpu(resp->fw_major);
1276 if (fw_minor_version != NULL)
1277 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1278 if (api_major_version != NULL)
1279 *api_major_version = le16_to_cpu(resp->api_major);
1280 if (api_minor_version != NULL)
1281 *api_minor_version = le16_to_cpu(resp->api_minor);
1282 }
1283
1284 return status;
1285}
1286
1287/**
1288 * i40e_aq_send_driver_version
1289 * @hw: pointer to the hw struct
56a62fc8
JB		 1290 * @dv: driver's major, minor version
1291 * @cmd_details: pointer to command details structure or NULL
1292 *
1293 * Send the driver version to the firmware
1294 **/
1295i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1296 struct i40e_driver_version *dv,
1297 struct i40e_asq_cmd_details *cmd_details)
1298{
1299 struct i40e_aq_desc desc;
1300 struct i40e_aqc_driver_version *cmd =
1301 (struct i40e_aqc_driver_version *)&desc.params.raw;
1302 i40e_status status;
d2466013 1303 int len;
56a62fc8
JB		 1304
1305 if (dv == NULL)
1306 return I40E_ERR_PARAM;
1307
1308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1309
1310 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1311 cmd->driver_major_ver = dv->major_version;
1312 cmd->driver_minor_ver = dv->minor_version;
1313 cmd->driver_build_ver = dv->build_version;
1314 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1315
1316 len = 0;
1317 while (len < sizeof(dv->driver_string) &&
1318 (dv->driver_string[len] < 0x80) &&
1319 dv->driver_string[len])
1320 len++;
1321 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1322 len, cmd_details);
56a62fc8
JB		 1323
1324 return status;
1325}
1326
1327/**
1328 * i40e_get_link_status - get status of the HW network link
1329 * @hw: pointer to the hw struct
1330 *
1331 * Returns true if link is up, false if link is down.
1332 *
1333 * Side effect: LinkStatusEvent reporting becomes enabled
1334 **/
1335bool i40e_get_link_status(struct i40e_hw *hw)
1336{
1337 i40e_status status = 0;
1338 bool link_status = false;
1339
1340 if (hw->phy.get_link_info) {
1341 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1342
1343 if (status)
1344 goto i40e_get_link_status_exit;
1345 }
1346
1347 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1348
1349i40e_get_link_status_exit:
1350 return link_status;
1351}
1352
1353/**
1354 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1355 * @hw: pointer to the hw struct
1356 * @uplink_seid: the MAC or other gizmo SEID
1357 * @downlink_seid: the VSI SEID
1358 * @enabled_tc: bitmap of TCs to be enabled
1359 * @default_port: true for default port VSI, false for control port
e1c51b95 1360 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1361 * @veb_seid: pointer to where to put the resulting VEB SEID
1362 * @cmd_details: pointer to command details structure or NULL
1363 *
1364 * This asks the FW to add a VEB between the uplink and downlink
1365 * elements. If the uplink SEID is 0, this will be a floating VEB.
1366 **/
1367i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1368 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1369 bool default_port, bool enable_l2_filtering,
1370 u16 *veb_seid,
56a62fc8
JB		 1371 struct i40e_asq_cmd_details *cmd_details)
1372{
1373 struct i40e_aq_desc desc;
1374 struct i40e_aqc_add_veb *cmd =
1375 (struct i40e_aqc_add_veb *)&desc.params.raw;
1376 struct i40e_aqc_add_veb_completion *resp =
1377 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1378 i40e_status status;
1379 u16 veb_flags = 0;
1380
1381 /* SEIDs need to either both be set or both be 0 for floating VEB */
1382 if (!!uplink_seid != !!downlink_seid)
1383 return I40E_ERR_PARAM;
1384
1385 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1386
1387 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1388 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1389 cmd->enable_tcs = enabled_tc;
1390 if (!uplink_seid)
1391 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1392 if (default_port)
1393 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1394 else
1395 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1396
1397 if (enable_l2_filtering)
1398 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1399
56a62fc8
JB		 1400 cmd->veb_flags = cpu_to_le16(veb_flags);
1401
1402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1403
1404 if (!status && veb_seid)
1405 *veb_seid = le16_to_cpu(resp->veb_seid);
1406
1407 return status;
1408}
1409
1410/**
1411 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1412 * @hw: pointer to the hw struct
1413 * @veb_seid: the SEID of the VEB to query
1414 * @switch_id: the uplink switch id
98d44381 1415 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1416 * @statistic_index: index of the stats counter block for this VEB
1417 * @vebs_used: number of VEB's used by function
98d44381 1418 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1419 * @cmd_details: pointer to command details structure or NULL
1420 *
1421 * This retrieves the parameters for a particular VEB, specified by
1422 * uplink_seid, and returns them to the caller.
1423 **/
1424i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1425 u16 veb_seid, u16 *switch_id,
1426 bool *floating, u16 *statistic_index,
1427 u16 *vebs_used, u16 *vebs_free,
1428 struct i40e_asq_cmd_details *cmd_details)
1429{
1430 struct i40e_aq_desc desc;
1431 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1432 (struct i40e_aqc_get_veb_parameters_completion *)
1433 &desc.params.raw;
1434 i40e_status status;
1435
1436 if (veb_seid == 0)
1437 return I40E_ERR_PARAM;
1438
1439 i40e_fill_default_direct_cmd_desc(&desc,
1440 i40e_aqc_opc_get_veb_parameters);
1441 cmd_resp->seid = cpu_to_le16(veb_seid);
1442
1443 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1444 if (status)
1445 goto get_veb_exit;
1446
1447 if (switch_id)
1448 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1449 if (statistic_index)
1450 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1451 if (vebs_used)
1452 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1453 if (vebs_free)
1454 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1455 if (floating) {
1456 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1457 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1458 *floating = true;
1459 else
1460 *floating = false;
1461 }
1462
1463get_veb_exit:
1464 return status;
1465}
1466
1467/**
1468 * i40e_aq_add_macvlan
1469 * @hw: pointer to the hw struct
1470 * @seid: VSI for the mac address
1471 * @mv_list: list of macvlans to be added
1472 * @count: length of the list
1473 * @cmd_details: pointer to command details structure or NULL
1474 *
1475 * Add MAC/VLAN addresses to the HW filtering
1476 **/
1477i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1478 struct i40e_aqc_add_macvlan_element_data *mv_list,
1479 u16 count, struct i40e_asq_cmd_details *cmd_details)
1480{
1481 struct i40e_aq_desc desc;
1482 struct i40e_aqc_macvlan *cmd =
1483 (struct i40e_aqc_macvlan *)&desc.params.raw;
1484 i40e_status status;
1485 u16 buf_size;
1486
1487 if (count == 0 || !mv_list || !hw)
1488 return I40E_ERR_PARAM;
1489
1490 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1491
1492 /* prep the rest of the request */
1493 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1494 cmd->num_addresses = cpu_to_le16(count);
1495 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1496 cmd->seid[1] = 0;
1497 cmd->seid[2] = 0;
1498
1499 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1500 if (buf_size > I40E_AQ_LARGE_BUF)
1501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1502
1503 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1504 cmd_details);
1505
1506 return status;
1507}
1508
1509/**
1510 * i40e_aq_remove_macvlan
1511 * @hw: pointer to the hw struct
1512 * @seid: VSI for the mac address
1513 * @mv_list: list of macvlans to be removed
1514 * @count: length of the list
1515 * @cmd_details: pointer to command details structure or NULL
1516 *
1517 * Remove MAC/VLAN addresses from the HW filtering
1518 **/
1519i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1520 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1521 u16 count, struct i40e_asq_cmd_details *cmd_details)
1522{
1523 struct i40e_aq_desc desc;
1524 struct i40e_aqc_macvlan *cmd =
1525 (struct i40e_aqc_macvlan *)&desc.params.raw;
1526 i40e_status status;
1527 u16 buf_size;
1528
1529 if (count == 0 || !mv_list || !hw)
1530 return I40E_ERR_PARAM;
1531
1532 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1533
1534 /* prep the rest of the request */
1535 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1536 cmd->num_addresses = cpu_to_le16(count);
1537 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1538 cmd->seid[1] = 0;
1539 cmd->seid[2] = 0;
1540
1541 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1542 if (buf_size > I40E_AQ_LARGE_BUF)
1543 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1544
1545 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1546 cmd_details);
1547
1548 return status;
1549}
1550
56a62fc8
JB		 1551/**
1552 * i40e_aq_send_msg_to_vf
1553 * @hw: pointer to the hardware structure
1554 * @vfid: vf id to send msg
98d44381
JK		 1555 * @v_opcode: opcodes for VF-PF communication
1556 * @v_retval: return error code
56a62fc8
JB		 1557 * @msg: pointer to the msg buffer
1558 * @msglen: msg length
1559 * @cmd_details: pointer to command details
1560 *
1561 * send msg to vf
1562 **/
1563i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1564 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1565 struct i40e_asq_cmd_details *cmd_details)
1566{
1567 struct i40e_aq_desc desc;
1568 struct i40e_aqc_pf_vf_message *cmd =
1569 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1570 i40e_status status;
1571
1572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1573 cmd->id = cpu_to_le32(vfid);
1574 desc.cookie_high = cpu_to_le32(v_opcode);
1575 desc.cookie_low = cpu_to_le32(v_retval);
1576 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1577 if (msglen) {
1578 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1579 I40E_AQ_FLAG_RD));
1580 if (msglen > I40E_AQ_LARGE_BUF)
1581 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1582 desc.datalen = cpu_to_le16(msglen);
1583 }
1584 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1585
1586 return status;
1587}
1588
1589/**
1590 * i40e_aq_set_hmc_resource_profile
1591 * @hw: pointer to the hw struct
1592 * @profile: type of profile the HMC is to be set as
1593 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1594 * @cmd_details: pointer to command details structure or NULL
1595 *
1596 * set the HMC profile of the device.
1597 **/
1598i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1599 enum i40e_aq_hmc_profile profile,
1600 u8 pe_vf_enabled_count,
1601 struct i40e_asq_cmd_details *cmd_details)
1602{
1603 struct i40e_aq_desc desc;
1604 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1605 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1606 i40e_status status;
1607
1608 i40e_fill_default_direct_cmd_desc(&desc,
1609 i40e_aqc_opc_set_hmc_resource_profile);
1610
1611 cmd->pm_profile = (u8)profile;
1612 cmd->pe_vf_enabled = pe_vf_enabled_count;
1613
1614 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1615
1616 return status;
1617}
1618
1619/**
1620 * i40e_aq_request_resource
1621 * @hw: pointer to the hw struct
1622 * @resource: resource id
1623 * @access: access type
1624 * @sdp_number: resource number
1625 * @timeout: the maximum time in ms that the driver may hold the resource
1626 * @cmd_details: pointer to command details structure or NULL
1627 *
1628 * requests common resource using the admin queue commands
1629 **/
1630i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1631 enum i40e_aq_resources_ids resource,
1632 enum i40e_aq_resource_access_type access,
1633 u8 sdp_number, u64 *timeout,
1634 struct i40e_asq_cmd_details *cmd_details)
1635{
1636 struct i40e_aq_desc desc;
1637 struct i40e_aqc_request_resource *cmd_resp =
1638 (struct i40e_aqc_request_resource *)&desc.params.raw;
1639 i40e_status status;
1640
1641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1642
1643 cmd_resp->resource_id = cpu_to_le16(resource);
1644 cmd_resp->access_type = cpu_to_le16(access);
1645 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1646
1647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1648 /* The completion specifies the maximum time in ms that the driver
1649 * may hold the resource in the Timeout field.
1650 * If the resource is held by someone else, the command completes with
1651 * busy return value and the timeout field indicates the maximum time
1652 * the current owner of the resource has to free it.
1653 */
1654 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1655 *timeout = le32_to_cpu(cmd_resp->timeout);
1656
1657 return status;
1658}
1659
1660/**
1661 * i40e_aq_release_resource
1662 * @hw: pointer to the hw struct
1663 * @resource: resource id
1664 * @sdp_number: resource number
1665 * @cmd_details: pointer to command details structure or NULL
1666 *
1667 * release common resource using the admin queue commands
1668 **/
1669i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1670 enum i40e_aq_resources_ids resource,
1671 u8 sdp_number,
1672 struct i40e_asq_cmd_details *cmd_details)
1673{
1674 struct i40e_aq_desc desc;
1675 struct i40e_aqc_request_resource *cmd =
1676 (struct i40e_aqc_request_resource *)&desc.params.raw;
1677 i40e_status status;
1678
1679 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1680
1681 cmd->resource_id = cpu_to_le16(resource);
1682 cmd->resource_number = cpu_to_le32(sdp_number);
1683
1684 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1685
1686 return status;
1687}
1688
1689/**
1690 * i40e_aq_read_nvm
1691 * @hw: pointer to the hw struct
1692 * @module_pointer: module pointer location in words from the NVM beginning
1693 * @offset: byte offset from the module beginning
1694 * @length: length of the section to be read (in bytes from the offset)
1695 * @data: command buffer (size [bytes] = length)
1696 * @last_command: tells if this is the last command in a series
1697 * @cmd_details: pointer to command details structure or NULL
1698 *
1699 * Read the NVM using the admin queue commands
1700 **/
1701i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1702 u32 offset, u16 length, void *data,
1703 bool last_command,
1704 struct i40e_asq_cmd_details *cmd_details)
1705{
1706 struct i40e_aq_desc desc;
1707 struct i40e_aqc_nvm_update *cmd =
1708 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1709 i40e_status status;
1710
1711 /* In offset the highest byte must be zeroed. */
1712 if (offset & 0xFF000000) {
1713 status = I40E_ERR_PARAM;
1714 goto i40e_aq_read_nvm_exit;
1715 }
1716
1717 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1718
1719 /* If this is the last command in a series, set the proper flag. */
1720 if (last_command)
1721 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1722 cmd->module_pointer = module_pointer;
1723 cmd->offset = cpu_to_le32(offset);
1724 cmd->length = cpu_to_le16(length);
1725
1726 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1727 if (length > I40E_AQ_LARGE_BUF)
1728 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1729
1730 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1731
1732i40e_aq_read_nvm_exit:
1733 return status;
1734}
1735
1736#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1737#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1738#define I40E_DEV_FUNC_CAP_NPAR 0x03
1739#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1740#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1741#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1742#define I40E_DEV_FUNC_CAP_VF 0x13
1743#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1744#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1745#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1746#define I40E_DEV_FUNC_CAP_VSI 0x17
1747#define I40E_DEV_FUNC_CAP_DCB 0x18
1748#define I40E_DEV_FUNC_CAP_FCOE 0x21
1749#define I40E_DEV_FUNC_CAP_RSS 0x40
1750#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1751#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1752#define I40E_DEV_FUNC_CAP_MSIX 0x43
1753#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1754#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1755#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1756#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1757#define I40E_DEV_FUNC_CAP_CEM 0xF2
1758#define I40E_DEV_FUNC_CAP_IWARP 0x51
1759#define I40E_DEV_FUNC_CAP_LED 0x61
1760#define I40E_DEV_FUNC_CAP_SDP 0x62
1761#define I40E_DEV_FUNC_CAP_MDIO 0x63
1762
1763/**
1764 * i40e_parse_discover_capabilities
1765 * @hw: pointer to the hw struct
1766 * @buff: pointer to a buffer containing device/function capability records
1767 * @cap_count: number of capability records in the list
1768 * @list_type_opc: type of capabilities list to parse
1769 *
1770 * Parse the device/function capabilities list.
1771 **/
1772static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1773 u32 cap_count,
1774 enum i40e_admin_queue_opc list_type_opc)
1775{
1776 struct i40e_aqc_list_capabilities_element_resp *cap;
1777 u32 number, logical_id, phys_id;
1778 struct i40e_hw_capabilities *p;
1779 u32 reg_val;
1780 u32 i = 0;
1781 u16 id;
1782
1783 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1784
1785 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 1786 p = &hw->dev_caps;
56a62fc8 1787 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 1788 p = &hw->func_caps;
56a62fc8
JB		 1789 else
1790 return;
1791
1792 for (i = 0; i < cap_count; i++, cap++) {
1793 id = le16_to_cpu(cap->id);
1794 number = le32_to_cpu(cap->number);
1795 logical_id = le32_to_cpu(cap->logical_id);
1796 phys_id = le32_to_cpu(cap->phys_id);
1797
1798 switch (id) {
1799 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1800 p->switch_mode = number;
1801 break;
1802 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1803 p->management_mode = number;
1804 break;
1805 case I40E_DEV_FUNC_CAP_NPAR:
1806 p->npar_enable = number;
1807 break;
1808 case I40E_DEV_FUNC_CAP_OS2BMC:
1809 p->os2bmc = number;
1810 break;
1811 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1812 p->valid_functions = number;
1813 break;
1814 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1815 if (number == 1)
1816 p->sr_iov_1_1 = true;
1817 break;
1818 case I40E_DEV_FUNC_CAP_VF:
1819 p->num_vfs = number;
1820 p->vf_base_id = logical_id;
1821 break;
1822 case I40E_DEV_FUNC_CAP_VMDQ:
1823 if (number == 1)
1824 p->vmdq = true;
1825 break;
1826 case I40E_DEV_FUNC_CAP_802_1_QBG:
1827 if (number == 1)
1828 p->evb_802_1_qbg = true;
1829 break;
1830 case I40E_DEV_FUNC_CAP_802_1_QBH:
1831 if (number == 1)
1832 p->evb_802_1_qbh = true;
1833 break;
1834 case I40E_DEV_FUNC_CAP_VSI:
1835 p->num_vsis = number;
1836 break;
1837 case I40E_DEV_FUNC_CAP_DCB:
1838 if (number == 1) {
1839 p->dcb = true;
1840 p->enabled_tcmap = logical_id;
1841 p->maxtc = phys_id;
1842 }
1843 break;
1844 case I40E_DEV_FUNC_CAP_FCOE:
1845 if (number == 1)
1846 p->fcoe = true;
1847 break;
1848 case I40E_DEV_FUNC_CAP_RSS:
1849 p->rss = true;
1850 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1851 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1852 p->rss_table_size = number;
1853 else
1854 p->rss_table_size = 128;
1855 p->rss_table_entry_width = logical_id;
1856 break;
1857 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1858 p->num_rx_qp = number;
1859 p->base_queue = phys_id;
1860 break;
1861 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1862 p->num_tx_qp = number;
1863 p->base_queue = phys_id;
1864 break;
1865 case I40E_DEV_FUNC_CAP_MSIX:
1866 p->num_msix_vectors = number;
1867 break;
1868 case I40E_DEV_FUNC_CAP_MSIX_VF:
1869 p->num_msix_vectors_vf = number;
1870 break;
1871 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1872 if (number == 1)
1873 p->mfp_mode_1 = true;
1874 break;
1875 case I40E_DEV_FUNC_CAP_CEM:
1876 if (number == 1)
1877 p->mgmt_cem = true;
1878 break;
1879 case I40E_DEV_FUNC_CAP_IWARP:
1880 if (number == 1)
1881 p->iwarp = true;
1882 break;
1883 case I40E_DEV_FUNC_CAP_LED:
1884 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1885 p->led[phys_id] = true;
1886 break;
1887 case I40E_DEV_FUNC_CAP_SDP:
1888 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1889 p->sdp[phys_id] = true;
1890 break;
1891 case I40E_DEV_FUNC_CAP_MDIO:
1892 if (number == 1) {
1893 p->mdio_port_num = phys_id;
1894 p->mdio_port_mode = logical_id;
1895 }
1896 break;
1897 case I40E_DEV_FUNC_CAP_IEEE_1588:
1898 if (number == 1)
1899 p->ieee_1588 = true;
1900 break;
1901 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1902 p->fd = true;
1903 p->fd_filters_guaranteed = number;
1904 p->fd_filters_best_effort = logical_id;
1905 break;
1906 default:
1907 break;
1908 }
1909 }
1910
1911 /* additional HW specific goodies that might
1912 * someday be HW version specific
1913 */
1914 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1915}
1916
1917/**
1918 * i40e_aq_discover_capabilities
1919 * @hw: pointer to the hw struct
1920 * @buff: a virtual buffer to hold the capabilities
1921 * @buff_size: Size of the virtual buffer
1922 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1923 * @list_type_opc: capabilities type to discover - pass in the command opcode
1924 * @cmd_details: pointer to command details structure or NULL
1925 *
1926 * Get the device capabilities descriptions from the firmware
1927 **/
1928i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1929 void *buff, u16 buff_size, u16 *data_size,
1930 enum i40e_admin_queue_opc list_type_opc,
1931 struct i40e_asq_cmd_details *cmd_details)
1932{
1933 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 1934 struct i40e_aq_desc desc;
8fb905b3 1935 i40e_status status = 0;
56a62fc8
JB		 1936
1937 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1938
1939 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1940 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1941 status = I40E_ERR_PARAM;
1942 goto exit;
1943 }
1944
1945 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1946
1947 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1948 if (buff_size > I40E_AQ_LARGE_BUF)
1949 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1950
1951 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1952 *data_size = le16_to_cpu(desc.datalen);
1953
1954 if (status)
1955 goto exit;
1956
1957 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1958 list_type_opc);
1959
1960exit:
1961 return status;
1962}
1963
1964/**
1965 * i40e_aq_get_lldp_mib
1966 * @hw: pointer to the hw struct
1967 * @bridge_type: type of bridge requested
1968 * @mib_type: Local, Remote or both Local and Remote MIBs
1969 * @buff: pointer to a user supplied buffer to store the MIB block
1970 * @buff_size: size of the buffer (in bytes)
1971 * @local_len : length of the returned Local LLDP MIB
1972 * @remote_len: length of the returned Remote LLDP MIB
1973 * @cmd_details: pointer to command details structure or NULL
1974 *
1975 * Requests the complete LLDP MIB (entire packet).
1976 **/
1977i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1978 u8 mib_type, void *buff, u16 buff_size,
1979 u16 *local_len, u16 *remote_len,
1980 struct i40e_asq_cmd_details *cmd_details)
1981{
1982 struct i40e_aq_desc desc;
1983 struct i40e_aqc_lldp_get_mib *cmd =
1984 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1985 struct i40e_aqc_lldp_get_mib *resp =
1986 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1987 i40e_status status;
1988
1989 if (buff_size == 0 || !buff)
1990 return I40E_ERR_PARAM;
1991
1992 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1993 /* Indirect Command */
1994 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1995
1996 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1997 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1998 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1999
2000 desc.datalen = cpu_to_le16(buff_size);
2001
2002 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2003 if (buff_size > I40E_AQ_LARGE_BUF)
2004 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2005
2006 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2007 if (!status) {
2008 if (local_len != NULL)
2009 *local_len = le16_to_cpu(resp->local_len);
2010 if (remote_len != NULL)
2011 *remote_len = le16_to_cpu(resp->remote_len);
2012 }
2013
2014 return status;
2015}
2016
2017/**
2018 * i40e_aq_cfg_lldp_mib_change_event
2019 * @hw: pointer to the hw struct
2020 * @enable_update: Enable or Disable event posting
2021 * @cmd_details: pointer to command details structure or NULL
2022 *
2023 * Enable or Disable posting of an event on ARQ when LLDP MIB
2024 * associated with the interface changes
2025 **/
2026i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2027 bool enable_update,
2028 struct i40e_asq_cmd_details *cmd_details)
2029{
2030 struct i40e_aq_desc desc;
2031 struct i40e_aqc_lldp_update_mib *cmd =
2032 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2033 i40e_status status;
2034
2035 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2036
2037 if (!enable_update)
2038 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2039
2040 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2041
2042 return status;
2043}
2044
2045/**
2046 * i40e_aq_stop_lldp
2047 * @hw: pointer to the hw struct
2048 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2049 * @cmd_details: pointer to command details structure or NULL
2050 *
2051 * Stop or Shutdown the embedded LLDP Agent
2052 **/
2053i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2054 struct i40e_asq_cmd_details *cmd_details)
2055{
2056 struct i40e_aq_desc desc;
2057 struct i40e_aqc_lldp_stop *cmd =
2058 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2059 i40e_status status;
2060
2061 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2062
2063 if (shutdown_agent)
2064 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2065
2066 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2067
2068 return status;
2069}
2070
2071/**
2072 * i40e_aq_start_lldp
2073 * @hw: pointer to the hw struct
2074 * @cmd_details: pointer to command details structure or NULL
2075 *
2076 * Start the embedded LLDP Agent on all ports.
2077 **/
2078i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2079 struct i40e_asq_cmd_details *cmd_details)
2080{
2081 struct i40e_aq_desc desc;
2082 struct i40e_aqc_lldp_start *cmd =
2083 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2084 i40e_status status;
2085
2086 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2087
2088 cmd->command = I40E_AQ_LLDP_AGENT_START;
2089
2090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091
2092 return status;
2093}
2094
a1c9a9d9
JK		 2095/**
2096 * i40e_aq_add_udp_tunnel
2097 * @hw: pointer to the hw struct
2098 * @udp_port: the UDP port to add
2099 * @header_len: length of the tunneling header length in DWords
2100 * @protocol_index: protocol index type
98d44381 2101 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2102 * @cmd_details: pointer to command details structure or NULL
2103 **/
2104i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2105 u16 udp_port, u8 header_len,
2106 u8 protocol_index, u8 *filter_index,
2107 struct i40e_asq_cmd_details *cmd_details)
2108{
2109 struct i40e_aq_desc desc;
2110 struct i40e_aqc_add_udp_tunnel *cmd =
2111 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2112 struct i40e_aqc_del_udp_tunnel_completion *resp =
2113 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2114 i40e_status status;
2115
2116 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2117
2118 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2119 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2120
2121 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2122
2123 if (!status)
2124 *filter_index = resp->index;
2125
2126 return status;
2127}
2128
2129/**
2130 * i40e_aq_del_udp_tunnel
2131 * @hw: pointer to the hw struct
2132 * @index: filter index
2133 * @cmd_details: pointer to command details structure or NULL
2134 **/
2135i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2136 struct i40e_asq_cmd_details *cmd_details)
2137{
2138 struct i40e_aq_desc desc;
2139 struct i40e_aqc_remove_udp_tunnel *cmd =
2140 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2141 i40e_status status;
2142
2143 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2144
2145 cmd->index = index;
2146
2147 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2148
2149 return status;
2150}
2151
56a62fc8
JB		 2152/**
2153 * i40e_aq_delete_element - Delete switch element
2154 * @hw: pointer to the hw struct
2155 * @seid: the SEID to delete from the switch
2156 * @cmd_details: pointer to command details structure or NULL
2157 *
2158 * This deletes a switch element from the switch.
2159 **/
2160i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2161 struct i40e_asq_cmd_details *cmd_details)
2162{
2163 struct i40e_aq_desc desc;
2164 struct i40e_aqc_switch_seid *cmd =
2165 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2166 i40e_status status;
2167
2168 if (seid == 0)
2169 return I40E_ERR_PARAM;
2170
2171 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2172
2173 cmd->seid = cpu_to_le16(seid);
2174
2175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2176
2177 return status;
2178}
2179
afb3ff0d
NP		 2180/**
2181 * i40e_aq_dcb_updated - DCB Updated Command
2182 * @hw: pointer to the hw struct
2183 * @cmd_details: pointer to command details structure or NULL
2184 *
2185 * EMP will return when the shared RPB settings have been
2186 * recomputed and modified. The retval field in the descriptor
2187 * will be set to 0 when RPB is modified.
2188 **/
2189i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2190 struct i40e_asq_cmd_details *cmd_details)
2191{
2192 struct i40e_aq_desc desc;
2193 i40e_status status;
2194
2195 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2196
2197 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2198
2199 return status;
2200}
2201
56a62fc8
JB		 2202/**
2203 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2204 * @hw: pointer to the hw struct
2205 * @seid: seid for the physical port/switching component/vsi
2206 * @buff: Indirect buffer to hold data parameters and response
2207 * @buff_size: Indirect buffer size
2208 * @opcode: Tx scheduler AQ command opcode
2209 * @cmd_details: pointer to command details structure or NULL
2210 *
2211 * Generic command handler for Tx scheduler AQ commands
2212 **/
2213static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2214 void *buff, u16 buff_size,
2215 enum i40e_admin_queue_opc opcode,
2216 struct i40e_asq_cmd_details *cmd_details)
2217{
2218 struct i40e_aq_desc desc;
2219 struct i40e_aqc_tx_sched_ind *cmd =
2220 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2221 i40e_status status;
2222 bool cmd_param_flag = false;
2223
2224 switch (opcode) {
2225 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2226 case i40e_aqc_opc_configure_vsi_tc_bw:
2227 case i40e_aqc_opc_enable_switching_comp_ets:
2228 case i40e_aqc_opc_modify_switching_comp_ets:
2229 case i40e_aqc_opc_disable_switching_comp_ets:
2230 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2231 case i40e_aqc_opc_configure_switching_comp_bw_config:
2232 cmd_param_flag = true;
2233 break;
2234 case i40e_aqc_opc_query_vsi_bw_config:
2235 case i40e_aqc_opc_query_vsi_ets_sla_config:
2236 case i40e_aqc_opc_query_switching_comp_ets_config:
2237 case i40e_aqc_opc_query_port_ets_config:
2238 case i40e_aqc_opc_query_switching_comp_bw_config:
2239 cmd_param_flag = false;
2240 break;
2241 default:
2242 return I40E_ERR_PARAM;
2243 }
2244
2245 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2246
2247 /* Indirect command */
2248 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2249 if (cmd_param_flag)
2250 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2251 if (buff_size > I40E_AQ_LARGE_BUF)
2252 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2253
2254 desc.datalen = cpu_to_le16(buff_size);
2255
2256 cmd->vsi_seid = cpu_to_le16(seid);
2257
2258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2259
2260 return status;
2261}
2262
6b192891
MW		 2263/**
2264 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2265 * @hw: pointer to the hw struct
2266 * @seid: VSI seid
2267 * @credit: BW limit credits (0 = disabled)
2268 * @max_credit: Max BW limit credits
2269 * @cmd_details: pointer to command details structure or NULL
2270 **/
2271i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2272 u16 seid, u16 credit, u8 max_credit,
2273 struct i40e_asq_cmd_details *cmd_details)
2274{
2275 struct i40e_aq_desc desc;
2276 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2277 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2278 i40e_status status;
2279
2280 i40e_fill_default_direct_cmd_desc(&desc,
2281 i40e_aqc_opc_configure_vsi_bw_limit);
2282
2283 cmd->vsi_seid = cpu_to_le16(seid);
2284 cmd->credit = cpu_to_le16(credit);
2285 cmd->max_credit = max_credit;
2286
2287 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2288
2289 return status;
2290}
2291
56a62fc8
JB		 2292/**
2293 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2294 * @hw: pointer to the hw struct
2295 * @seid: VSI seid
2296 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2297 * @cmd_details: pointer to command details structure or NULL
2298 **/
2299i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2300 u16 seid,
2301 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2302 struct i40e_asq_cmd_details *cmd_details)
2303{
2304 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2305 i40e_aqc_opc_configure_vsi_tc_bw,
2306 cmd_details);
2307}
2308
afb3ff0d
NP		 2309/**
2310 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2311 * @hw: pointer to the hw struct
2312 * @seid: seid of the switching component connected to Physical Port
2313 * @ets_data: Buffer holding ETS parameters
2314 * @cmd_details: pointer to command details structure or NULL
2315 **/
2316i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2317 u16 seid,
2318 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2319 enum i40e_admin_queue_opc opcode,
2320 struct i40e_asq_cmd_details *cmd_details)
2321{
2322 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2323 sizeof(*ets_data), opcode, cmd_details);
2324}
2325
2326/**
2327 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2328 * @hw: pointer to the hw struct
2329 * @seid: seid of the switching component
2330 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2331 * @cmd_details: pointer to command details structure or NULL
2332 **/
2333i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2334 u16 seid,
2335 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2336 struct i40e_asq_cmd_details *cmd_details)
2337{
2338 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2339 i40e_aqc_opc_configure_switching_comp_bw_config,
2340 cmd_details);
2341}
2342
56a62fc8
JB		 2343/**
2344 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2345 * @hw: pointer to the hw struct
2346 * @seid: seid of the VSI
2347 * @bw_data: Buffer to hold VSI BW configuration
2348 * @cmd_details: pointer to command details structure or NULL
2349 **/
2350i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2351 u16 seid,
2352 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2353 struct i40e_asq_cmd_details *cmd_details)
2354{
2355 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2356 i40e_aqc_opc_query_vsi_bw_config,
2357 cmd_details);
2358}
2359
2360/**
2361 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2362 * @hw: pointer to the hw struct
2363 * @seid: seid of the VSI
2364 * @bw_data: Buffer to hold VSI BW configuration per TC
2365 * @cmd_details: pointer to command details structure or NULL
2366 **/
2367i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2368 u16 seid,
2369 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2370 struct i40e_asq_cmd_details *cmd_details)
2371{
2372 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2373 i40e_aqc_opc_query_vsi_ets_sla_config,
2374 cmd_details);
2375}
2376
2377/**
2378 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2379 * @hw: pointer to the hw struct
2380 * @seid: seid of the switching component
2381 * @bw_data: Buffer to hold switching component's per TC BW config
2382 * @cmd_details: pointer to command details structure or NULL
2383 **/
2384i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2385 u16 seid,
2386 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2387 struct i40e_asq_cmd_details *cmd_details)
2388{
2389 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2390 i40e_aqc_opc_query_switching_comp_ets_config,
2391 cmd_details);
2392}
2393
2394/**
2395 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2396 * @hw: pointer to the hw struct
2397 * @seid: seid of the VSI or switching component connected to Physical Port
2398 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2399 * @cmd_details: pointer to command details structure or NULL
2400 **/
2401i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2402 u16 seid,
2403 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2404 struct i40e_asq_cmd_details *cmd_details)
2405{
2406 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2407 i40e_aqc_opc_query_port_ets_config,
2408 cmd_details);
2409}
2410
2411/**
2412 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2413 * @hw: pointer to the hw struct
2414 * @seid: seid of the switching component
2415 * @bw_data: Buffer to hold switching component's BW configuration
2416 * @cmd_details: pointer to command details structure or NULL
2417 **/
2418i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2419 u16 seid,
2420 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2421 struct i40e_asq_cmd_details *cmd_details)
2422{
2423 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2424 i40e_aqc_opc_query_switching_comp_bw_config,
2425 cmd_details);
2426}
2427
2428/**
2429 * i40e_validate_filter_settings
2430 * @hw: pointer to the hardware structure
2431 * @settings: Filter control settings
2432 *
2433 * Check and validate the filter control settings passed.
2434 * The function checks for the valid filter/context sizes being
2435 * passed for FCoE and PE.
2436 *
2437 * Returns 0 if the values passed are valid and within
2438 * range else returns an error.
2439 **/
2440static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2441 struct i40e_filter_control_settings *settings)
2442{
2443 u32 fcoe_cntx_size, fcoe_filt_size;
2444 u32 pe_cntx_size, pe_filt_size;
2445 u32 fcoe_fmax, pe_fmax;
2446 u32 val;
2447
2448 /* Validate FCoE settings passed */
2449 switch (settings->fcoe_filt_num) {
2450 case I40E_HASH_FILTER_SIZE_1K:
2451 case I40E_HASH_FILTER_SIZE_2K:
2452 case I40E_HASH_FILTER_SIZE_4K:
2453 case I40E_HASH_FILTER_SIZE_8K:
2454 case I40E_HASH_FILTER_SIZE_16K:
2455 case I40E_HASH_FILTER_SIZE_32K:
2456 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2457 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2458 break;
2459 default:
2460 return I40E_ERR_PARAM;
2461 }
2462
2463 switch (settings->fcoe_cntx_num) {
2464 case I40E_DMA_CNTX_SIZE_512:
2465 case I40E_DMA_CNTX_SIZE_1K:
2466 case I40E_DMA_CNTX_SIZE_2K:
2467 case I40E_DMA_CNTX_SIZE_4K:
2468 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2469 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2470 break;
2471 default:
2472 return I40E_ERR_PARAM;
2473 }
2474
2475 /* Validate PE settings passed */
2476 switch (settings->pe_filt_num) {
2477 case I40E_HASH_FILTER_SIZE_1K:
2478 case I40E_HASH_FILTER_SIZE_2K:
2479 case I40E_HASH_FILTER_SIZE_4K:
2480 case I40E_HASH_FILTER_SIZE_8K:
2481 case I40E_HASH_FILTER_SIZE_16K:
2482 case I40E_HASH_FILTER_SIZE_32K:
2483 case I40E_HASH_FILTER_SIZE_64K:
2484 case I40E_HASH_FILTER_SIZE_128K:
2485 case I40E_HASH_FILTER_SIZE_256K:
2486 case I40E_HASH_FILTER_SIZE_512K:
2487 case I40E_HASH_FILTER_SIZE_1M:
2488 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2489 pe_filt_size <<= (u32)settings->pe_filt_num;
2490 break;
2491 default:
2492 return I40E_ERR_PARAM;
2493 }
2494
2495 switch (settings->pe_cntx_num) {
2496 case I40E_DMA_CNTX_SIZE_512:
2497 case I40E_DMA_CNTX_SIZE_1K:
2498 case I40E_DMA_CNTX_SIZE_2K:
2499 case I40E_DMA_CNTX_SIZE_4K:
2500 case I40E_DMA_CNTX_SIZE_8K:
2501 case I40E_DMA_CNTX_SIZE_16K:
2502 case I40E_DMA_CNTX_SIZE_32K:
2503 case I40E_DMA_CNTX_SIZE_64K:
2504 case I40E_DMA_CNTX_SIZE_128K:
2505 case I40E_DMA_CNTX_SIZE_256K:
2506 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2507 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2508 break;
2509 default:
2510 return I40E_ERR_PARAM;
2511 }
2512
2513 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2514 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2515 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2516 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2517 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2518 return I40E_ERR_INVALID_SIZE;
2519
2520 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2521 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2522 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2523 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2524 if (pe_filt_size + pe_cntx_size > pe_fmax)
2525 return I40E_ERR_INVALID_SIZE;
2526
2527 return 0;
2528}
2529
2530/**
2531 * i40e_set_filter_control
2532 * @hw: pointer to the hardware structure
2533 * @settings: Filter control settings
2534 *
2535 * Set the Queue Filters for PE/FCoE and enable filters required
2536 * for a single PF. It is expected that these settings are programmed
2537 * at the driver initialization time.
2538 **/
2539i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2540 struct i40e_filter_control_settings *settings)
2541{
2542 i40e_status ret = 0;
2543 u32 hash_lut_size = 0;
2544 u32 val;
2545
2546 if (!settings)
2547 return I40E_ERR_PARAM;
2548
2549 /* Validate the input settings */
2550 ret = i40e_validate_filter_settings(hw, settings);
2551 if (ret)
2552 return ret;
2553
2554 /* Read the PF Queue Filter control register */
2555 val = rd32(hw, I40E_PFQF_CTL_0);
2556
2557 /* Program required PE hash buckets for the PF */
2558 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2559 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2560 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2561 /* Program required PE contexts for the PF */
2562 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2563 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2564 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2565
2566 /* Program required FCoE hash buckets for the PF */
2567 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2568 val |= ((u32)settings->fcoe_filt_num <<
2569 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2570 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2571 /* Program required FCoE DDP contexts for the PF */
2572 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2573 val |= ((u32)settings->fcoe_cntx_num <<
2574 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2575 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2576
2577 /* Program Hash LUT size for the PF */
2578 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2579 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2580 hash_lut_size = 1;
2581 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2582 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2583
2584 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2585 if (settings->enable_fdir)
2586 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2587 if (settings->enable_ethtype)
2588 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2589 if (settings->enable_macvlan)
2590 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2591
2592 wr32(hw, I40E_PFQF_CTL_0, val);
2593
2594 return 0;
2595}
afb3ff0d
NP		 2596
2597/**
2598 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2599 * @hw: pointer to the hw struct
2600 * @mac_addr: MAC address to use in the filter
2601 * @ethtype: Ethertype to use in the filter
2602 * @flags: Flags that needs to be applied to the filter
2603 * @vsi_seid: seid of the control VSI
2604 * @queue: VSI queue number to send the packet to
2605 * @is_add: Add control packet filter if True else remove
2606 * @stats: Structure to hold information on control filter counts
2607 * @cmd_details: pointer to command details structure or NULL
2608 *
2609 * This command will Add or Remove control packet filter for a control VSI.
2610 * In return it will update the total number of perfect filter count in
2611 * the stats member.
2612 **/
2613i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2614 u8 *mac_addr, u16 ethtype, u16 flags,
2615 u16 vsi_seid, u16 queue, bool is_add,
2616 struct i40e_control_filter_stats *stats,
2617 struct i40e_asq_cmd_details *cmd_details)
2618{
2619 struct i40e_aq_desc desc;
2620 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2621 (struct i40e_aqc_add_remove_control_packet_filter *)
2622 &desc.params.raw;
2623 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2624 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2625 &desc.params.raw;
2626 i40e_status status;
2627
2628 if (vsi_seid == 0)
2629 return I40E_ERR_PARAM;
2630
2631 if (is_add) {
2632 i40e_fill_default_direct_cmd_desc(&desc,
2633 i40e_aqc_opc_add_control_packet_filter);
2634 cmd->queue = cpu_to_le16(queue);
2635 } else {
2636 i40e_fill_default_direct_cmd_desc(&desc,
2637 i40e_aqc_opc_remove_control_packet_filter);
2638 }
2639
2640 if (mac_addr)
2641 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2642
2643 cmd->etype = cpu_to_le16(ethtype);
2644 cmd->flags = cpu_to_le16(flags);
2645 cmd->seid = cpu_to_le16(vsi_seid);
2646
2647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2648
2649 if (!status && stats) {
2650 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2651 stats->etype_used = le16_to_cpu(resp->etype_used);
2652 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2653 stats->etype_free = le16_to_cpu(resp->etype_free);
2654 }
2655
2656 return status;
2657}
2658
d4dfb81a
CS		 2659/**
2660 * i40e_set_pci_config_data - store PCI bus info
2661 * @hw: pointer to hardware structure
2662 * @link_status: the link status word from PCI config space
2663 *
2664 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2665 **/
2666void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2667{
2668 hw->bus.type = i40e_bus_type_pci_express;
2669
2670 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2671 case PCI_EXP_LNKSTA_NLW_X1:
2672 hw->bus.width = i40e_bus_width_pcie_x1;
2673 break;
2674 case PCI_EXP_LNKSTA_NLW_X2:
2675 hw->bus.width = i40e_bus_width_pcie_x2;
2676 break;
2677 case PCI_EXP_LNKSTA_NLW_X4:
2678 hw->bus.width = i40e_bus_width_pcie_x4;
2679 break;
2680 case PCI_EXP_LNKSTA_NLW_X8:
2681 hw->bus.width = i40e_bus_width_pcie_x8;
2682 break;
2683 default:
2684 hw->bus.width = i40e_bus_width_unknown;
2685 break;
2686 }
2687
2688 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2689 case PCI_EXP_LNKSTA_CLS_2_5GB:
2690 hw->bus.speed = i40e_bus_speed_2500;
2691 break;
2692 case PCI_EXP_LNKSTA_CLS_5_0GB:
2693 hw->bus.speed = i40e_bus_speed_5000;
2694 break;
2695 case PCI_EXP_LNKSTA_CLS_8_0GB:
2696 hw->bus.speed = i40e_bus_speed_8000;
2697 break;
2698 default:
2699 hw->bus.speed = i40e_bus_speed_unknown;
2700 break;
2701 }
2702}
Linux kernel - Deliverables
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