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i40e/i40evf: remove rx_errors and rx_missed
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
ded7b9a3 42#define DRV_VERSION_BUILD 46
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
274static void i40e_tx_timeout(struct net_device *netdev)
275{
276 struct i40e_netdev_priv *np = netdev_priv(netdev);
277 struct i40e_vsi *vsi = np->vsi;
278 struct i40e_pf *pf = vsi->back;
279
280 pf->tx_timeout_count++;
281
282 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
283 pf->tx_timeout_recovery_level = 0;
284 pf->tx_timeout_last_recovery = jiffies;
285 netdev_info(netdev, "tx_timeout recovery level %d\n",
286 pf->tx_timeout_recovery_level);
287
288 switch (pf->tx_timeout_recovery_level) {
289 case 0:
290 /* disable and re-enable queues for the VSI */
291 if (in_interrupt()) {
292 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
293 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
294 } else {
295 i40e_vsi_reinit_locked(vsi);
296 }
297 break;
298 case 1:
299 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
300 break;
301 case 2:
302 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
303 break;
304 case 3:
305 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
306 break;
307 default:
308 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 309 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 310 i40e_down(vsi);
311 break;
312 }
313 i40e_service_event_schedule(pf);
314 pf->tx_timeout_recovery_level++;
315}
316
317/**
318 * i40e_release_rx_desc - Store the new tail and head values
319 * @rx_ring: ring to bump
320 * @val: new head index
321 **/
322static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
323{
324 rx_ring->next_to_use = val;
325
326 /* Force memory writes to complete before letting h/w
327 * know there are new descriptors to fetch. (Only
328 * applicable for weak-ordered memory model archs,
329 * such as IA-64).
330 */
331 wmb();
332 writel(val, rx_ring->tail);
333}
334
335/**
336 * i40e_get_vsi_stats_struct - Get System Network Statistics
337 * @vsi: the VSI we care about
338 *
339 * Returns the address of the device statistics structure.
340 * The statistics are actually updated from the service task.
341 **/
342struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
343{
344 return &vsi->net_stats;
345}
346
347/**
348 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
349 * @netdev: network interface device structure
350 *
351 * Returns the address of the device statistics structure.
352 * The statistics are actually updated from the service task.
353 **/
354static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
355 struct net_device *netdev,
980e9b11 356 struct rtnl_link_stats64 *stats)
41c445ff
JB		 357{
358 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 359 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 360 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 361 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
362 int i;
363
bc7d338f
ASJ		 364 if (test_bit(__I40E_DOWN, &vsi->state))
365 return stats;
366
3c325ced
JB		 367 if (!vsi->tx_rings)
368 return stats;
369
980e9b11
AD		 370 rcu_read_lock();
371 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 372 u64 bytes, packets;
373 unsigned int start;
374
375 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
376 if (!tx_ring)
377 continue;
378
379 do {
57a7744e 380 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 381 packets = tx_ring->stats.packets;
382 bytes = tx_ring->stats.bytes;
57a7744e 383 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 384
385 stats->tx_packets += packets;
386 stats->tx_bytes += bytes;
387 rx_ring = &tx_ring[1];
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 391 packets = rx_ring->stats.packets;
392 bytes = rx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 394
980e9b11
AD		 395 stats->rx_packets += packets;
396 stats->rx_bytes += bytes;
397 }
398 rcu_read_unlock();
399
400 /* following stats updated by ixgbe_watchdog_task() */
401 stats->multicast = vsi_stats->multicast;
402 stats->tx_errors = vsi_stats->tx_errors;
403 stats->tx_dropped = vsi_stats->tx_dropped;
404 stats->rx_errors = vsi_stats->rx_errors;
405 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
406 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 407
980e9b11 408 return stats;
41c445ff
JB		 409}
410
411/**
412 * i40e_vsi_reset_stats - Resets all stats of the given vsi
413 * @vsi: the VSI to have its stats reset
414 **/
415void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
416{
417 struct rtnl_link_stats64 *ns;
418 int i;
419
420 if (!vsi)
421 return;
422
423 ns = i40e_get_vsi_stats_struct(vsi);
424 memset(ns, 0, sizeof(*ns));
425 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
426 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
427 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 428 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 429 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 430 memset(&vsi->rx_rings[i]->stats, 0 ,
431 sizeof(vsi->rx_rings[i]->stats));
432 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
433 sizeof(vsi->rx_rings[i]->rx_stats));
434 memset(&vsi->tx_rings[i]->stats, 0 ,
435 sizeof(vsi->tx_rings[i]->stats));
436 memset(&vsi->tx_rings[i]->tx_stats, 0,
437 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 438 }
8e9dca53 439 }
41c445ff
JB		 440 vsi->stat_offsets_loaded = false;
441}
442
443/**
444 * i40e_pf_reset_stats - Reset all of the stats for the given pf
445 * @pf: the PF to be reset
446 **/
447void i40e_pf_reset_stats(struct i40e_pf *pf)
448{
449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
452}
453
454/**
455 * i40e_stat_update48 - read and update a 48 bit stat from the chip
456 * @hw: ptr to the hardware info
457 * @hireg: the high 32 bit reg to read
458 * @loreg: the low 32 bit reg to read
459 * @offset_loaded: has the initial offset been loaded yet
460 * @offset: ptr to current offset value
461 * @stat: ptr to the stat
462 *
463 * Since the device stats are not reset at PFReset, they likely will not
464 * be zeroed when the driver starts. We'll save the first values read
465 * and use them as offsets to be subtracted from the raw values in order
466 * to report stats that count from zero. In the process, we also manage
467 * the potential roll-over.
468 **/
469static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
470 bool offset_loaded, u64 *offset, u64 *stat)
471{
472 u64 new_data;
473
ab60085e 474 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 475 new_data = rd32(hw, loreg);
476 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
477 } else {
478 new_data = rd64(hw, loreg);
479 }
480 if (!offset_loaded)
481 *offset = new_data;
482 if (likely(new_data >= *offset))
483 *stat = new_data - *offset;
484 else
485 *stat = (new_data + ((u64)1 << 48)) - *offset;
486 *stat &= 0xFFFFFFFFFFFFULL;
487}
488
489/**
490 * i40e_stat_update32 - read and update a 32 bit stat from the chip
491 * @hw: ptr to the hardware info
492 * @reg: the hw reg to read
493 * @offset_loaded: has the initial offset been loaded yet
494 * @offset: ptr to current offset value
495 * @stat: ptr to the stat
496 **/
497static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
498 bool offset_loaded, u64 *offset, u64 *stat)
499{
500 u32 new_data;
501
502 new_data = rd32(hw, reg);
503 if (!offset_loaded)
504 *offset = new_data;
505 if (likely(new_data >= *offset))
506 *stat = (u32)(new_data - *offset);
507 else
508 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
509}
510
511/**
512 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
513 * @vsi: the VSI to be updated
514 **/
515void i40e_update_eth_stats(struct i40e_vsi *vsi)
516{
517 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
518 struct i40e_pf *pf = vsi->back;
519 struct i40e_hw *hw = &pf->hw;
520 struct i40e_eth_stats *oes;
521 struct i40e_eth_stats *es; /* device's eth stats */
522
523 es = &vsi->eth_stats;
524 oes = &vsi->eth_stats_offsets;
525
526 /* Gather up the stats that the hw collects */
527 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->tx_errors, &es->tx_errors);
530 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_discards, &es->rx_discards);
533
534 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
535 I40E_GLV_GORCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_bytes, &es->rx_bytes);
538 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
539 I40E_GLV_UPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_unicast, &es->rx_unicast);
542 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
543 I40E_GLV_MPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_multicast, &es->rx_multicast);
546 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
547 I40E_GLV_BPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_broadcast, &es->rx_broadcast);
550
551 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
552 I40E_GLV_GOTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_bytes, &es->tx_bytes);
555 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
556 I40E_GLV_UPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_unicast, &es->tx_unicast);
559 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
560 I40E_GLV_MPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_multicast, &es->tx_multicast);
563 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
564 I40E_GLV_BPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_broadcast, &es->tx_broadcast);
567 vsi->stat_offsets_loaded = true;
568}
569
570/**
571 * i40e_update_veb_stats - Update Switch component statistics
572 * @veb: the VEB being updated
573 **/
574static void i40e_update_veb_stats(struct i40e_veb *veb)
575{
576 struct i40e_pf *pf = veb->pf;
577 struct i40e_hw *hw = &pf->hw;
578 struct i40e_eth_stats *oes;
579 struct i40e_eth_stats *es; /* device's eth stats */
580 int idx = 0;
581
582 idx = veb->stats_idx;
583 es = &veb->stats;
584 oes = &veb->stats_offsets;
585
586 /* Gather up the stats that the hw collects */
587 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
588 veb->stat_offsets_loaded,
589 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 590 if (hw->revision_id > 0)
591 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_unknown_protocol,
594 &es->rx_unknown_protocol);
41c445ff
JB		 595 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_bytes, &es->rx_bytes);
598 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_unicast, &es->rx_unicast);
601 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_multicast, &es->rx_multicast);
604 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->rx_broadcast, &es->rx_broadcast);
607
608 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_bytes, &es->tx_bytes);
611 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_unicast, &es->tx_unicast);
614 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_multicast, &es->tx_multicast);
617 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->tx_broadcast, &es->tx_broadcast);
620 veb->stat_offsets_loaded = true;
621}
622
623/**
624 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
625 * @pf: the corresponding PF
626 *
627 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
628 **/
629static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
630{
631 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
632 struct i40e_hw_port_stats *nsd = &pf->stats;
633 struct i40e_hw *hw = &pf->hw;
634 u64 xoff = 0;
635 u16 i, v;
636
637 if ((hw->fc.current_mode != I40E_FC_FULL) &&
638 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
639 return;
640
641 xoff = nsd->link_xoff_rx;
642 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
643 pf->stat_offsets_loaded,
644 &osd->link_xoff_rx, &nsd->link_xoff_rx);
645
646 /* No new LFC xoff rx */
647 if (!(nsd->link_xoff_rx - xoff))
648 return;
649
650 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
651 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
652 struct i40e_vsi *vsi = pf->vsi[v];
653
654 if (!vsi)
655 continue;
656
657 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 658 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 659 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
660 }
661 }
662}
663
664/**
665 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
666 * @pf: the corresponding PF
667 *
668 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
669 **/
670static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
671{
672 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
673 struct i40e_hw_port_stats *nsd = &pf->stats;
674 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
675 struct i40e_dcbx_config *dcb_cfg;
676 struct i40e_hw *hw = &pf->hw;
677 u16 i, v;
678 u8 tc;
679
680 dcb_cfg = &hw->local_dcbx_config;
681
682 /* See if DCB enabled with PFC TC */
683 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
684 !(dcb_cfg->pfc.pfcenable)) {
685 i40e_update_link_xoff_rx(pf);
686 return;
687 }
688
689 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
690 u64 prio_xoff = nsd->priority_xoff_rx[i];
691 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
692 pf->stat_offsets_loaded,
693 &osd->priority_xoff_rx[i],
694 &nsd->priority_xoff_rx[i]);
695
696 /* No new PFC xoff rx */
697 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
698 continue;
699 /* Get the TC for given priority */
700 tc = dcb_cfg->etscfg.prioritytable[i];
701 xoff[tc] = true;
702 }
703
704 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
705 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
706 struct i40e_vsi *vsi = pf->vsi[v];
707
708 if (!vsi)
709 continue;
710
711 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 712 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 713
714 tc = ring->dcb_tc;
715 if (xoff[tc])
716 clear_bit(__I40E_HANG_CHECK_ARMED,
717 &ring->state);
718 }
719 }
720}
721
722/**
7812fddc 723 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 724 * @vsi: the VSI to be updated
725 *
726 * There are a few instances where we store the same stat in a
727 * couple of different structs. This is partly because we have
728 * the netdev stats that need to be filled out, which is slightly
729 * different from the "eth_stats" defined by the chip and used in
7812fddc 730 * VF communications. We sort it out here.
41c445ff 731 **/
7812fddc 732static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 733{
734 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 735 struct rtnl_link_stats64 *ons;
736 struct rtnl_link_stats64 *ns; /* netdev stats */
737 struct i40e_eth_stats *oes;
738 struct i40e_eth_stats *es; /* device's eth stats */
739 u32 tx_restart, tx_busy;
740 u32 rx_page, rx_buf;
741 u64 rx_p, rx_b;
742 u64 tx_p, tx_b;
41c445ff
JB		 743 u16 q;
744
745 if (test_bit(__I40E_DOWN, &vsi->state) ||
746 test_bit(__I40E_CONFIG_BUSY, &pf->state))
747 return;
748
749 ns = i40e_get_vsi_stats_struct(vsi);
750 ons = &vsi->net_stats_offsets;
751 es = &vsi->eth_stats;
752 oes = &vsi->eth_stats_offsets;
753
754 /* Gather up the netdev and vsi stats that the driver collects
755 * on the fly during packet processing
756 */
757 rx_b = rx_p = 0;
758 tx_b = tx_p = 0;
759 tx_restart = tx_busy = 0;
760 rx_page = 0;
761 rx_buf = 0;
980e9b11 762 rcu_read_lock();
41c445ff
JB		 763 for (q = 0; q < vsi->num_queue_pairs; q++) {
764 struct i40e_ring *p;
980e9b11
AD		 765 u64 bytes, packets;
766 unsigned int start;
767
768 /* locate Tx ring */
769 p = ACCESS_ONCE(vsi->tx_rings[q]);
770
771 do {
57a7744e 772 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 773 packets = p->stats.packets;
774 bytes = p->stats.bytes;
57a7744e 775 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 776 tx_b += bytes;
777 tx_p += packets;
778 tx_restart += p->tx_stats.restart_queue;
779 tx_busy += p->tx_stats.tx_busy;
41c445ff 780
980e9b11
AD		 781 /* Rx queue is part of the same block as Tx queue */
782 p = &p[1];
783 do {
57a7744e 784 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 785 packets = p->stats.packets;
786 bytes = p->stats.bytes;
57a7744e 787 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 788 rx_b += bytes;
789 rx_p += packets;
420136cc
MW		 790 rx_buf += p->rx_stats.alloc_buff_failed;
791 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 792 }
980e9b11 793 rcu_read_unlock();
41c445ff
JB		 794 vsi->tx_restart = tx_restart;
795 vsi->tx_busy = tx_busy;
796 vsi->rx_page_failed = rx_page;
797 vsi->rx_buf_failed = rx_buf;
798
799 ns->rx_packets = rx_p;
800 ns->rx_bytes = rx_b;
801 ns->tx_packets = tx_p;
802 ns->tx_bytes = tx_b;
803
41c445ff 804 /* update netdev stats from eth stats */
7812fddc 805 i40e_update_eth_stats(vsi);
41c445ff
JB		 806 ons->tx_errors = oes->tx_errors;
807 ns->tx_errors = es->tx_errors;
808 ons->multicast = oes->rx_multicast;
809 ns->multicast = es->rx_multicast;
810 ons->tx_dropped = oes->tx_discards;
811 ns->tx_dropped = es->tx_discards;
812
7812fddc 813 /* pull in a couple PF stats if this is the main vsi */
41c445ff 814 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 815 ns->rx_crc_errors = pf->stats.crc_errors;
816 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
817 ns->rx_length_errors = pf->stats.rx_length_errors;
818 }
819}
41c445ff 820
7812fddc
SN		 821/**
822 * i40e_update_pf_stats - Update the pf statistics counters.
823 * @pf: the PF to be updated
824 **/
825static void i40e_update_pf_stats(struct i40e_pf *pf)
826{
827 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
828 struct i40e_hw_port_stats *nsd = &pf->stats;
829 struct i40e_hw *hw = &pf->hw;
830 u32 val;
831 int i;
41c445ff 832
7812fddc
SN		 833 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
834 I40E_GLPRT_GORCL(hw->port),
835 pf->stat_offsets_loaded,
836 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
837 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
838 I40E_GLPRT_GOTCL(hw->port),
839 pf->stat_offsets_loaded,
840 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
841 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->eth.rx_discards,
844 &nsd->eth.rx_discards);
845 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->eth.tx_discards,
848 &nsd->eth.tx_discards);
849 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
850 I40E_GLPRT_MPRCL(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->eth.rx_multicast,
853 &nsd->eth.rx_multicast);
41c445ff 854
7812fddc
SN		 855 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
856 pf->stat_offsets_loaded,
857 &osd->tx_dropped_link_down,
858 &nsd->tx_dropped_link_down);
41c445ff 859
7812fddc
SN		 860 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
861 pf->stat_offsets_loaded,
862 &osd->crc_errors, &nsd->crc_errors);
41c445ff 863
7812fddc
SN		 864 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
865 pf->stat_offsets_loaded,
866 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 867
7812fddc
SN		 868 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
869 pf->stat_offsets_loaded,
870 &osd->mac_local_faults,
871 &nsd->mac_local_faults);
872 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->mac_remote_faults,
875 &nsd->mac_remote_faults);
41c445ff 876
7812fddc
SN		 877 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
878 pf->stat_offsets_loaded,
879 &osd->rx_length_errors,
880 &nsd->rx_length_errors);
41c445ff 881
7812fddc
SN		 882 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
883 pf->stat_offsets_loaded,
884 &osd->link_xon_rx, &nsd->link_xon_rx);
885 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
886 pf->stat_offsets_loaded,
887 &osd->link_xon_tx, &nsd->link_xon_tx);
888 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
889 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
890 pf->stat_offsets_loaded,
891 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 892
7812fddc
SN		 893 for (i = 0; i < 8; i++) {
894 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 895 pf->stat_offsets_loaded,
7812fddc
SN		 896 &osd->priority_xon_rx[i],
897 &nsd->priority_xon_rx[i]);
898 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 899 pf->stat_offsets_loaded,
7812fddc
SN		 900 &osd->priority_xon_tx[i],
901 &nsd->priority_xon_tx[i]);
902 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 903 pf->stat_offsets_loaded,
7812fddc
SN		 904 &osd->priority_xoff_tx[i],
905 &nsd->priority_xoff_tx[i]);
906 i40e_stat_update32(hw,
907 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
41c445ff 908 pf->stat_offsets_loaded,
7812fddc
SN		 909 &osd->priority_xon_2_xoff[i],
910 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 911 }
912
7812fddc
SN		 913 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
914 I40E_GLPRT_PRC64L(hw->port),
915 pf->stat_offsets_loaded,
916 &osd->rx_size_64, &nsd->rx_size_64);
917 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
918 I40E_GLPRT_PRC127L(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->rx_size_127, &nsd->rx_size_127);
921 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
922 I40E_GLPRT_PRC255L(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->rx_size_255, &nsd->rx_size_255);
925 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
926 I40E_GLPRT_PRC511L(hw->port),
927 pf->stat_offsets_loaded,
928 &osd->rx_size_511, &nsd->rx_size_511);
929 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
930 I40E_GLPRT_PRC1023L(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->rx_size_1023, &nsd->rx_size_1023);
933 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
934 I40E_GLPRT_PRC1522L(hw->port),
935 pf->stat_offsets_loaded,
936 &osd->rx_size_1522, &nsd->rx_size_1522);
937 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
938 I40E_GLPRT_PRC9522L(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->rx_size_big, &nsd->rx_size_big);
941
942 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
943 I40E_GLPRT_PTC64L(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->tx_size_64, &nsd->tx_size_64);
946 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
947 I40E_GLPRT_PTC127L(hw->port),
948 pf->stat_offsets_loaded,
949 &osd->tx_size_127, &nsd->tx_size_127);
950 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
951 I40E_GLPRT_PTC255L(hw->port),
952 pf->stat_offsets_loaded,
953 &osd->tx_size_255, &nsd->tx_size_255);
954 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
955 I40E_GLPRT_PTC511L(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->tx_size_511, &nsd->tx_size_511);
958 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
959 I40E_GLPRT_PTC1023L(hw->port),
960 pf->stat_offsets_loaded,
961 &osd->tx_size_1023, &nsd->tx_size_1023);
962 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
963 I40E_GLPRT_PTC1522L(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->tx_size_1522, &nsd->tx_size_1522);
966 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
967 I40E_GLPRT_PTC9522L(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->tx_size_big, &nsd->tx_size_big);
970
971 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->rx_undersize, &nsd->rx_undersize);
974 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_fragments, &nsd->rx_fragments);
977 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->rx_oversize, &nsd->rx_oversize);
980 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_jabber, &nsd->rx_jabber);
983
984 val = rd32(hw, I40E_PRTPM_EEE_STAT);
985 nsd->tx_lpi_status =
986 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
987 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
988 nsd->rx_lpi_status =
989 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
990 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
991 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
992 pf->stat_offsets_loaded,
993 &osd->tx_lpi_count, &nsd->tx_lpi_count);
994 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
995 pf->stat_offsets_loaded,
996 &osd->rx_lpi_count, &nsd->rx_lpi_count);
997
41c445ff
JB		 998 pf->stat_offsets_loaded = true;
999}
1000
7812fddc
SN		 1001/**
1002 * i40e_update_stats - Update the various statistics counters.
1003 * @vsi: the VSI to be updated
1004 *
1005 * Update the various stats for this VSI and its related entities.
1006 **/
1007void i40e_update_stats(struct i40e_vsi *vsi)
1008{
1009 struct i40e_pf *pf = vsi->back;
1010
1011 if (vsi == pf->vsi[pf->lan_vsi])
1012 i40e_update_pf_stats(pf);
1013
1014 i40e_update_vsi_stats(vsi);
1015}
1016
41c445ff
JB		 1017/**
1018 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1019 * @vsi: the VSI to be searched
1020 * @macaddr: the MAC address
1021 * @vlan: the vlan
1022 * @is_vf: make sure its a vf filter, else doesn't matter
1023 * @is_netdev: make sure its a netdev filter, else doesn't matter
1024 *
1025 * Returns ptr to the filter object or NULL
1026 **/
1027static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1028 u8 *macaddr, s16 vlan,
1029 bool is_vf, bool is_netdev)
1030{
1031 struct i40e_mac_filter *f;
1032
1033 if (!vsi || !macaddr)
1034 return NULL;
1035
1036 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1037 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1038 (vlan == f->vlan) &&
1039 (!is_vf || f->is_vf) &&
1040 (!is_netdev || f->is_netdev))
1041 return f;
1042 }
1043 return NULL;
1044}
1045
1046/**
1047 * i40e_find_mac - Find a mac addr in the macvlan filters list
1048 * @vsi: the VSI to be searched
1049 * @macaddr: the MAC address we are searching for
1050 * @is_vf: make sure its a vf filter, else doesn't matter
1051 * @is_netdev: make sure its a netdev filter, else doesn't matter
1052 *
1053 * Returns the first filter with the provided MAC address or NULL if
1054 * MAC address was not found
1055 **/
1056struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1057 bool is_vf, bool is_netdev)
1058{
1059 struct i40e_mac_filter *f;
1060
1061 if (!vsi || !macaddr)
1062 return NULL;
1063
1064 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1065 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1066 (!is_vf || f->is_vf) &&
1067 (!is_netdev || f->is_netdev))
1068 return f;
1069 }
1070 return NULL;
1071}
1072
1073/**
1074 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1075 * @vsi: the VSI to be searched
1076 *
1077 * Returns true if VSI is in vlan mode or false otherwise
1078 **/
1079bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1080{
1081 struct i40e_mac_filter *f;
1082
1083 /* Only -1 for all the filters denotes not in vlan mode
1084 * so we have to go through all the list in order to make sure
1085 */
1086 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1087 if (f->vlan >= 0)
1088 return true;
1089 }
1090
1091 return false;
1092}
1093
1094/**
1095 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1096 * @vsi: the VSI to be searched
1097 * @macaddr: the mac address to be filtered
1098 * @is_vf: true if it is a vf
1099 * @is_netdev: true if it is a netdev
1100 *
1101 * Goes through all the macvlan filters and adds a
1102 * macvlan filter for each unique vlan that already exists
1103 *
1104 * Returns first filter found on success, else NULL
1105 **/
1106struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1107 bool is_vf, bool is_netdev)
1108{
1109 struct i40e_mac_filter *f;
1110
1111 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1112 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1113 is_vf, is_netdev)) {
1114 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1115 is_vf, is_netdev))
41c445ff
JB		 1116 return NULL;
1117 }
1118 }
1119
1120 return list_first_entry_or_null(&vsi->mac_filter_list,
1121 struct i40e_mac_filter, list);
1122}
1123
1124/**
1125 * i40e_add_filter - Add a mac/vlan filter to the VSI
1126 * @vsi: the VSI to be searched
1127 * @macaddr: the MAC address
1128 * @vlan: the vlan
1129 * @is_vf: make sure its a vf filter, else doesn't matter
1130 * @is_netdev: make sure its a netdev filter, else doesn't matter
1131 *
1132 * Returns ptr to the filter object or NULL when no memory available.
1133 **/
1134struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1135 u8 *macaddr, s16 vlan,
1136 bool is_vf, bool is_netdev)
1137{
1138 struct i40e_mac_filter *f;
1139
1140 if (!vsi || !macaddr)
1141 return NULL;
1142
1143 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1144 if (!f) {
1145 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1146 if (!f)
1147 goto add_filter_out;
1148
1149 memcpy(f->macaddr, macaddr, ETH_ALEN);
1150 f->vlan = vlan;
1151 f->changed = true;
1152
1153 INIT_LIST_HEAD(&f->list);
1154 list_add(&f->list, &vsi->mac_filter_list);
1155 }
1156
1157 /* increment counter and add a new flag if needed */
1158 if (is_vf) {
1159 if (!f->is_vf) {
1160 f->is_vf = true;
1161 f->counter++;
1162 }
1163 } else if (is_netdev) {
1164 if (!f->is_netdev) {
1165 f->is_netdev = true;
1166 f->counter++;
1167 }
1168 } else {
1169 f->counter++;
1170 }
1171
1172 /* changed tells sync_filters_subtask to
1173 * push the filter down to the firmware
1174 */
1175 if (f->changed) {
1176 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1177 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1178 }
1179
1180add_filter_out:
1181 return f;
1182}
1183
1184/**
1185 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1186 * @vsi: the VSI to be searched
1187 * @macaddr: the MAC address
1188 * @vlan: the vlan
1189 * @is_vf: make sure it's a vf filter, else doesn't matter
1190 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1191 **/
1192void i40e_del_filter(struct i40e_vsi *vsi,
1193 u8 *macaddr, s16 vlan,
1194 bool is_vf, bool is_netdev)
1195{
1196 struct i40e_mac_filter *f;
1197
1198 if (!vsi || !macaddr)
1199 return;
1200
1201 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1202 if (!f || f->counter == 0)
1203 return;
1204
1205 if (is_vf) {
1206 if (f->is_vf) {
1207 f->is_vf = false;
1208 f->counter--;
1209 }
1210 } else if (is_netdev) {
1211 if (f->is_netdev) {
1212 f->is_netdev = false;
1213 f->counter--;
1214 }
1215 } else {
1216 /* make sure we don't remove a filter in use by vf or netdev */
1217 int min_f = 0;
1218 min_f += (f->is_vf ? 1 : 0);
1219 min_f += (f->is_netdev ? 1 : 0);
1220
1221 if (f->counter > min_f)
1222 f->counter--;
1223 }
1224
1225 /* counter == 0 tells sync_filters_subtask to
1226 * remove the filter from the firmware's list
1227 */
1228 if (f->counter == 0) {
1229 f->changed = true;
1230 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1231 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1232 }
1233}
1234
1235/**
1236 * i40e_set_mac - NDO callback to set mac address
1237 * @netdev: network interface device structure
1238 * @p: pointer to an address structure
1239 *
1240 * Returns 0 on success, negative on failure
1241 **/
1242static int i40e_set_mac(struct net_device *netdev, void *p)
1243{
1244 struct i40e_netdev_priv *np = netdev_priv(netdev);
1245 struct i40e_vsi *vsi = np->vsi;
1246 struct sockaddr *addr = p;
1247 struct i40e_mac_filter *f;
1248
1249 if (!is_valid_ether_addr(addr->sa_data))
1250 return -EADDRNOTAVAIL;
1251
1252 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1253
1254 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1255 return 0;
1256
80f6428f
ASJ		 1257 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1258 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1259 return -EADDRNOTAVAIL;
1260
41c445ff
JB		 1261 if (vsi->type == I40E_VSI_MAIN) {
1262 i40e_status ret;
1263 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1264 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1265 addr->sa_data, NULL);
1266 if (ret) {
1267 netdev_info(netdev,
1268 "Addr change for Main VSI failed: %d\n",
1269 ret);
1270 return -EADDRNOTAVAIL;
1271 }
1272
1273 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1274 }
1275
1276 /* In order to be sure to not drop any packets, add the new address
1277 * then delete the old one.
1278 */
1279 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1280 if (!f)
1281 return -ENOMEM;
1282
1283 i40e_sync_vsi_filters(vsi);
1284 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1285 i40e_sync_vsi_filters(vsi);
1286
1287 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1288
1289 return 0;
1290}
1291
1292/**
1293 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1294 * @vsi: the VSI being setup
1295 * @ctxt: VSI context structure
1296 * @enabled_tc: Enabled TCs bitmap
1297 * @is_add: True if called before Add VSI
1298 *
1299 * Setup VSI queue mapping for enabled traffic classes.
1300 **/
1301static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1302 struct i40e_vsi_context *ctxt,
1303 u8 enabled_tc,
1304 bool is_add)
1305{
1306 struct i40e_pf *pf = vsi->back;
1307 u16 sections = 0;
1308 u8 netdev_tc = 0;
1309 u16 numtc = 0;
1310 u16 qcount;
1311 u8 offset;
1312 u16 qmap;
1313 int i;
4e3b35b0 1314 u16 num_tc_qps = 0;
41c445ff
JB		 1315
1316 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1317 offset = 0;
1318
1319 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1320 /* Find numtc from enabled TC bitmap */
1321 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1322 if (enabled_tc & (1 << i)) /* TC is enabled */
1323 numtc++;
1324 }
1325 if (!numtc) {
1326 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1327 numtc = 1;
1328 }
1329 } else {
1330 /* At least TC0 is enabled in case of non-DCB case */
1331 numtc = 1;
1332 }
1333
1334 vsi->tc_config.numtc = numtc;
1335 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1336 /* Number of queues per enabled TC */
1337 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1338 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1339
1340 /* Setup queue offset/count for all TCs for given VSI */
1341 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1342 /* See if the given TC is enabled for the given VSI */
1343 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1344 int pow, num_qps;
1345
41c445ff
JB		 1346 switch (vsi->type) {
1347 case I40E_VSI_MAIN:
4e3b35b0 1348 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1349 break;
1350 case I40E_VSI_FDIR:
1351 case I40E_VSI_SRIOV:
1352 case I40E_VSI_VMDQ2:
1353 default:
4e3b35b0 1354 qcount = num_tc_qps;
41c445ff
JB		 1355 WARN_ON(i != 0);
1356 break;
1357 }
4e3b35b0
NP		 1358 vsi->tc_config.tc_info[i].qoffset = offset;
1359 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1360
1361 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1362 num_qps = qcount;
41c445ff 1363 pow = 0;
4e3b35b0 1364 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1365 pow++;
1366 num_qps >>= 1;
1367 }
1368
1369 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1370 qmap =
1371 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1372 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1373
4e3b35b0 1374 offset += qcount;
41c445ff
JB		 1375 } else {
1376 /* TC is not enabled so set the offset to
1377 * default queue and allocate one queue
1378 * for the given TC.
1379 */
1380 vsi->tc_config.tc_info[i].qoffset = 0;
1381 vsi->tc_config.tc_info[i].qcount = 1;
1382 vsi->tc_config.tc_info[i].netdev_tc = 0;
1383
1384 qmap = 0;
1385 }
1386 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1387 }
1388
1389 /* Set actual Tx/Rx queue pairs */
1390 vsi->num_queue_pairs = offset;
1391
1392 /* Scheduler section valid can only be set for ADD VSI */
1393 if (is_add) {
1394 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1395
1396 ctxt->info.up_enable_bits = enabled_tc;
1397 }
1398 if (vsi->type == I40E_VSI_SRIOV) {
1399 ctxt->info.mapping_flags |=
1400 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1401 for (i = 0; i < vsi->num_queue_pairs; i++)
1402 ctxt->info.queue_mapping[i] =
1403 cpu_to_le16(vsi->base_queue + i);
1404 } else {
1405 ctxt->info.mapping_flags |=
1406 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1407 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1408 }
1409 ctxt->info.valid_sections |= cpu_to_le16(sections);
1410}
1411
1412/**
1413 * i40e_set_rx_mode - NDO callback to set the netdev filters
1414 * @netdev: network interface device structure
1415 **/
1416static void i40e_set_rx_mode(struct net_device *netdev)
1417{
1418 struct i40e_netdev_priv *np = netdev_priv(netdev);
1419 struct i40e_mac_filter *f, *ftmp;
1420 struct i40e_vsi *vsi = np->vsi;
1421 struct netdev_hw_addr *uca;
1422 struct netdev_hw_addr *mca;
1423 struct netdev_hw_addr *ha;
1424
1425 /* add addr if not already in the filter list */
1426 netdev_for_each_uc_addr(uca, netdev) {
1427 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1428 if (i40e_is_vsi_in_vlan(vsi))
1429 i40e_put_mac_in_vlan(vsi, uca->addr,
1430 false, true);
1431 else
1432 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1433 false, true);
1434 }
1435 }
1436
1437 netdev_for_each_mc_addr(mca, netdev) {
1438 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1439 if (i40e_is_vsi_in_vlan(vsi))
1440 i40e_put_mac_in_vlan(vsi, mca->addr,
1441 false, true);
1442 else
1443 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1444 false, true);
1445 }
1446 }
1447
1448 /* remove filter if not in netdev list */
1449 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1450 bool found = false;
1451
1452 if (!f->is_netdev)
1453 continue;
1454
1455 if (is_multicast_ether_addr(f->macaddr)) {
1456 netdev_for_each_mc_addr(mca, netdev) {
1457 if (ether_addr_equal(mca->addr, f->macaddr)) {
1458 found = true;
1459 break;
1460 }
1461 }
1462 } else {
1463 netdev_for_each_uc_addr(uca, netdev) {
1464 if (ether_addr_equal(uca->addr, f->macaddr)) {
1465 found = true;
1466 break;
1467 }
1468 }
1469
1470 for_each_dev_addr(netdev, ha) {
1471 if (ether_addr_equal(ha->addr, f->macaddr)) {
1472 found = true;
1473 break;
1474 }
1475 }
1476 }
1477 if (!found)
1478 i40e_del_filter(
1479 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1480 }
1481
1482 /* check for other flag changes */
1483 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1484 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1485 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1486 }
1487}
1488
1489/**
1490 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1491 * @vsi: ptr to the VSI
1492 *
1493 * Push any outstanding VSI filter changes through the AdminQ.
1494 *
1495 * Returns 0 or error value
1496 **/
1497int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1498{
1499 struct i40e_mac_filter *f, *ftmp;
1500 bool promisc_forced_on = false;
1501 bool add_happened = false;
1502 int filter_list_len = 0;
1503 u32 changed_flags = 0;
dcae29be 1504 i40e_status aq_ret = 0;
41c445ff
JB		 1505 struct i40e_pf *pf;
1506 int num_add = 0;
1507 int num_del = 0;
1508 u16 cmd_flags;
1509
1510 /* empty array typed pointers, kcalloc later */
1511 struct i40e_aqc_add_macvlan_element_data *add_list;
1512 struct i40e_aqc_remove_macvlan_element_data *del_list;
1513
1514 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1515 usleep_range(1000, 2000);
1516 pf = vsi->back;
1517
1518 if (vsi->netdev) {
1519 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1520 vsi->current_netdev_flags = vsi->netdev->flags;
1521 }
1522
1523 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1524 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1525
1526 filter_list_len = pf->hw.aq.asq_buf_size /
1527 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1528 del_list = kcalloc(filter_list_len,
1529 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1530 GFP_KERNEL);
1531 if (!del_list)
1532 return -ENOMEM;
1533
1534 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1535 if (!f->changed)
1536 continue;
1537
1538 if (f->counter != 0)
1539 continue;
1540 f->changed = false;
1541 cmd_flags = 0;
1542
1543 /* add to delete list */
1544 memcpy(del_list[num_del].mac_addr,
1545 f->macaddr, ETH_ALEN);
1546 del_list[num_del].vlan_tag =
1547 cpu_to_le16((u16)(f->vlan ==
1548 I40E_VLAN_ANY ? 0 : f->vlan));
1549
41c445ff
JB		 1550 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1551 del_list[num_del].flags = cmd_flags;
1552 num_del++;
1553
1554 /* unlink from filter list */
1555 list_del(&f->list);
1556 kfree(f);
1557
1558 /* flush a full buffer */
1559 if (num_del == filter_list_len) {
dcae29be 1560 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1561 vsi->seid, del_list, num_del,
1562 NULL);
1563 num_del = 0;
1564 memset(del_list, 0, sizeof(*del_list));
1565
dcae29be 1566 if (aq_ret)
41c445ff
JB		 1567 dev_info(&pf->pdev->dev,
1568 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1569 aq_ret,
41c445ff
JB		 1570 pf->hw.aq.asq_last_status);
1571 }
1572 }
1573 if (num_del) {
dcae29be 1574 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1575 del_list, num_del, NULL);
1576 num_del = 0;
1577
dcae29be 1578 if (aq_ret)
41c445ff
JB		 1579 dev_info(&pf->pdev->dev,
1580 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1581 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1582 }
1583
1584 kfree(del_list);
1585 del_list = NULL;
1586
1587 /* do all the adds now */
1588 filter_list_len = pf->hw.aq.asq_buf_size /
1589 sizeof(struct i40e_aqc_add_macvlan_element_data),
1590 add_list = kcalloc(filter_list_len,
1591 sizeof(struct i40e_aqc_add_macvlan_element_data),
1592 GFP_KERNEL);
1593 if (!add_list)
1594 return -ENOMEM;
1595
1596 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1597 if (!f->changed)
1598 continue;
1599
1600 if (f->counter == 0)
1601 continue;
1602 f->changed = false;
1603 add_happened = true;
1604 cmd_flags = 0;
1605
1606 /* add to add array */
1607 memcpy(add_list[num_add].mac_addr,
1608 f->macaddr, ETH_ALEN);
1609 add_list[num_add].vlan_tag =
1610 cpu_to_le16(
1611 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1612 add_list[num_add].queue_number = 0;
1613
1614 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1615 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1616 num_add++;
1617
1618 /* flush a full buffer */
1619 if (num_add == filter_list_len) {
dcae29be
JB		 1620 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1621 add_list, num_add,
1622 NULL);
41c445ff
JB		 1623 num_add = 0;
1624
dcae29be 1625 if (aq_ret)
41c445ff
JB		 1626 break;
1627 memset(add_list, 0, sizeof(*add_list));
1628 }
1629 }
1630 if (num_add) {
dcae29be
JB		 1631 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1632 add_list, num_add, NULL);
41c445ff
JB		 1633 num_add = 0;
1634 }
1635 kfree(add_list);
1636 add_list = NULL;
1637
dcae29be 1638 if (add_happened && (!aq_ret)) {
41c445ff 1639 /* do nothing */;
dcae29be 1640 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1641 dev_info(&pf->pdev->dev,
1642 "add filter failed, err %d, aq_err %d\n",
dcae29be 1643 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1644 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1645 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1646 &vsi->state)) {
1647 promisc_forced_on = true;
1648 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1649 &vsi->state);
1650 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1651 }
1652 }
1653 }
1654
1655 /* check for changes in promiscuous modes */
1656 if (changed_flags & IFF_ALLMULTI) {
1657 bool cur_multipromisc;
1658 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1659 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1660 vsi->seid,
1661 cur_multipromisc,
1662 NULL);
1663 if (aq_ret)
41c445ff
JB		 1664 dev_info(&pf->pdev->dev,
1665 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1666 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1667 }
1668 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1669 bool cur_promisc;
1670 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1671 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1672 &vsi->state));
dcae29be
JB		 1673 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1674 vsi->seid,
1675 cur_promisc, NULL);
1676 if (aq_ret)
41c445ff
JB		 1677 dev_info(&pf->pdev->dev,
1678 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1679 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1680 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1681 vsi->seid,
1682 cur_promisc, NULL);
1683 if (aq_ret)
1684 dev_info(&pf->pdev->dev,
1685 "set brdcast promisc failed, err %d, aq_err %d\n",
1686 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1687 }
1688
1689 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1690 return 0;
1691}
1692
1693/**
1694 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1695 * @pf: board private structure
1696 **/
1697static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1698{
1699 int v;
1700
1701 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1702 return;
1703 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1704
1705 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1706 if (pf->vsi[v] &&
1707 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1708 i40e_sync_vsi_filters(pf->vsi[v]);
1709 }
1710}
1711
1712/**
1713 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1714 * @netdev: network interface device structure
1715 * @new_mtu: new value for maximum frame size
1716 *
1717 * Returns 0 on success, negative on failure
1718 **/
1719static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1720{
1721 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1722 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1723 struct i40e_vsi *vsi = np->vsi;
1724
1725 /* MTU < 68 is an error and causes problems on some kernels */
1726 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1727 return -EINVAL;
1728
1729 netdev_info(netdev, "changing MTU from %d to %d\n",
1730 netdev->mtu, new_mtu);
1731 netdev->mtu = new_mtu;
1732 if (netif_running(netdev))
1733 i40e_vsi_reinit_locked(vsi);
1734
1735 return 0;
1736}
1737
beb0dff1
JK		 1738/**
1739 * i40e_ioctl - Access the hwtstamp interface
1740 * @netdev: network interface device structure
1741 * @ifr: interface request data
1742 * @cmd: ioctl command
1743 **/
1744int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1745{
1746 struct i40e_netdev_priv *np = netdev_priv(netdev);
1747 struct i40e_pf *pf = np->vsi->back;
1748
1749 switch (cmd) {
1750 case SIOCGHWTSTAMP:
1751 return i40e_ptp_get_ts_config(pf, ifr);
1752 case SIOCSHWTSTAMP:
1753 return i40e_ptp_set_ts_config(pf, ifr);
1754 default:
1755 return -EOPNOTSUPP;
1756 }
1757}
1758
41c445ff
JB		 1759/**
1760 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1761 * @vsi: the vsi being adjusted
1762 **/
1763void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1764{
1765 struct i40e_vsi_context ctxt;
1766 i40e_status ret;
1767
1768 if ((vsi->info.valid_sections &
1769 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1770 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1771 return; /* already enabled */
1772
1773 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1774 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1775 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1776
1777 ctxt.seid = vsi->seid;
1778 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1779 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1780 if (ret) {
1781 dev_info(&vsi->back->pdev->dev,
1782 "%s: update vsi failed, aq_err=%d\n",
1783 __func__, vsi->back->hw.aq.asq_last_status);
1784 }
1785}
1786
1787/**
1788 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1789 * @vsi: the vsi being adjusted
1790 **/
1791void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1792{
1793 struct i40e_vsi_context ctxt;
1794 i40e_status ret;
1795
1796 if ((vsi->info.valid_sections &
1797 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1798 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1799 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1800 return; /* already disabled */
1801
1802 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1803 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1804 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1805
1806 ctxt.seid = vsi->seid;
1807 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1808 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1809 if (ret) {
1810 dev_info(&vsi->back->pdev->dev,
1811 "%s: update vsi failed, aq_err=%d\n",
1812 __func__, vsi->back->hw.aq.asq_last_status);
1813 }
1814}
1815
1816/**
1817 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1818 * @netdev: network interface to be adjusted
1819 * @features: netdev features to test if VLAN offload is enabled or not
1820 **/
1821static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1822{
1823 struct i40e_netdev_priv *np = netdev_priv(netdev);
1824 struct i40e_vsi *vsi = np->vsi;
1825
1826 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1827 i40e_vlan_stripping_enable(vsi);
1828 else
1829 i40e_vlan_stripping_disable(vsi);
1830}
1831
1832/**
1833 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1834 * @vsi: the vsi being configured
1835 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1836 **/
1837int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1838{
1839 struct i40e_mac_filter *f, *add_f;
1840 bool is_netdev, is_vf;
41c445ff
JB		 1841
1842 is_vf = (vsi->type == I40E_VSI_SRIOV);
1843 is_netdev = !!(vsi->netdev);
1844
1845 if (is_netdev) {
1846 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1847 is_vf, is_netdev);
1848 if (!add_f) {
1849 dev_info(&vsi->back->pdev->dev,
1850 "Could not add vlan filter %d for %pM\n",
1851 vid, vsi->netdev->dev_addr);
1852 return -ENOMEM;
1853 }
1854 }
1855
1856 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1857 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1858 if (!add_f) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "Could not add vlan filter %d for %pM\n",
1861 vid, f->macaddr);
1862 return -ENOMEM;
1863 }
1864 }
1865
41c445ff
JB		 1866 /* Now if we add a vlan tag, make sure to check if it is the first
1867 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1868 * with 0, so we now accept untagged and specified tagged traffic
1869 * (and not any taged and untagged)
1870 */
1871 if (vid > 0) {
1872 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1873 I40E_VLAN_ANY,
1874 is_vf, is_netdev)) {
1875 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1876 I40E_VLAN_ANY, is_vf, is_netdev);
1877 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1878 is_vf, is_netdev);
1879 if (!add_f) {
1880 dev_info(&vsi->back->pdev->dev,
1881 "Could not add filter 0 for %pM\n",
1882 vsi->netdev->dev_addr);
1883 return -ENOMEM;
1884 }
1885 }
8d82a7c5 1886 }
41c445ff 1887
8d82a7c5
GR		 1888 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1889 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1890 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1891 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1892 is_vf, is_netdev)) {
1893 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1894 is_vf, is_netdev);
1895 add_f = i40e_add_filter(vsi, f->macaddr,
1896 0, is_vf, is_netdev);
1897 if (!add_f) {
1898 dev_info(&vsi->back->pdev->dev,
1899 "Could not add filter 0 for %pM\n",
1900 f->macaddr);
1901 return -ENOMEM;
1902 }
1903 }
1904 }
41c445ff
JB		 1905 }
1906
80f6428f
ASJ		 1907 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1908 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1909 return 0;
1910
1911 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1912}
1913
1914/**
1915 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1916 * @vsi: the vsi being configured
1917 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1918 *
1919 * Return: 0 on success or negative otherwise
41c445ff
JB		 1920 **/
1921int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1922{
1923 struct net_device *netdev = vsi->netdev;
1924 struct i40e_mac_filter *f, *add_f;
1925 bool is_vf, is_netdev;
1926 int filter_count = 0;
41c445ff
JB		 1927
1928 is_vf = (vsi->type == I40E_VSI_SRIOV);
1929 is_netdev = !!(netdev);
1930
1931 if (is_netdev)
1932 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1933
1934 list_for_each_entry(f, &vsi->mac_filter_list, list)
1935 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1936
41c445ff
JB		 1937 /* go through all the filters for this VSI and if there is only
1938 * vid == 0 it means there are no other filters, so vid 0 must
1939 * be replaced with -1. This signifies that we should from now
1940 * on accept any traffic (with any tag present, or untagged)
1941 */
1942 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1943 if (is_netdev) {
1944 if (f->vlan &&
1945 ether_addr_equal(netdev->dev_addr, f->macaddr))
1946 filter_count++;
1947 }
1948
1949 if (f->vlan)
1950 filter_count++;
1951 }
1952
1953 if (!filter_count && is_netdev) {
1954 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1955 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1956 is_vf, is_netdev);
1957 if (!f) {
1958 dev_info(&vsi->back->pdev->dev,
1959 "Could not add filter %d for %pM\n",
1960 I40E_VLAN_ANY, netdev->dev_addr);
1961 return -ENOMEM;
1962 }
1963 }
1964
1965 if (!filter_count) {
1966 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1967 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1968 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1969 is_vf, is_netdev);
1970 if (!add_f) {
1971 dev_info(&vsi->back->pdev->dev,
1972 "Could not add filter %d for %pM\n",
1973 I40E_VLAN_ANY, f->macaddr);
1974 return -ENOMEM;
1975 }
1976 }
1977 }
1978
80f6428f
ASJ		 1979 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1980 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1981 return 0;
1982
41c445ff
JB		 1983 return i40e_sync_vsi_filters(vsi);
1984}
1985
1986/**
1987 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1988 * @netdev: network interface to be adjusted
1989 * @vid: vlan id to be added
078b5876
JB		 1990 *
1991 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1992 **/
1993static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1994 __always_unused __be16 proto, u16 vid)
1995{
1996 struct i40e_netdev_priv *np = netdev_priv(netdev);
1997 struct i40e_vsi *vsi = np->vsi;
078b5876 1998 int ret = 0;
41c445ff
JB		 1999
2000 if (vid > 4095)
078b5876
JB		 2001 return -EINVAL;
2002
2003 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2004
6982d429
ASJ		 2005 /* If the network stack called us with vid = 0 then
2006 * it is asking to receive priority tagged packets with
2007 * vlan id 0. Our HW receives them by default when configured
2008 * to receive untagged packets so there is no need to add an
2009 * extra filter for vlan 0 tagged packets.
41c445ff 2010 */
6982d429
ASJ		 2011 if (vid)
2012 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2013
078b5876
JB		 2014 if (!ret && (vid < VLAN_N_VID))
2015 set_bit(vid, vsi->active_vlans);
41c445ff 2016
078b5876 2017 return ret;
41c445ff
JB		 2018}
2019
2020/**
2021 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2022 * @netdev: network interface to be adjusted
2023 * @vid: vlan id to be removed
078b5876 2024 *
fdfd943e 2025 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2026 **/
2027static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2028 __always_unused __be16 proto, u16 vid)
2029{
2030 struct i40e_netdev_priv *np = netdev_priv(netdev);
2031 struct i40e_vsi *vsi = np->vsi;
2032
078b5876
JB		 2033 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2034
41c445ff
JB		 2035 /* return code is ignored as there is nothing a user
2036 * can do about failure to remove and a log message was
078b5876 2037 * already printed from the other function
41c445ff
JB		 2038 */
2039 i40e_vsi_kill_vlan(vsi, vid);
2040
2041 clear_bit(vid, vsi->active_vlans);
078b5876 2042
41c445ff
JB		 2043 return 0;
2044}
2045
2046/**
2047 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2048 * @vsi: the vsi being brought back up
2049 **/
2050static void i40e_restore_vlan(struct i40e_vsi *vsi)
2051{
2052 u16 vid;
2053
2054 if (!vsi->netdev)
2055 return;
2056
2057 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2058
2059 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2060 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2061 vid);
2062}
2063
2064/**
2065 * i40e_vsi_add_pvid - Add pvid for the VSI
2066 * @vsi: the vsi being adjusted
2067 * @vid: the vlan id to set as a PVID
2068 **/
dcae29be 2069int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2070{
2071 struct i40e_vsi_context ctxt;
dcae29be 2072 i40e_status aq_ret;
41c445ff
JB		 2073
2074 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2075 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2076 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2077 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2078 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2079
2080 ctxt.seid = vsi->seid;
2081 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2082 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2083 if (aq_ret) {
41c445ff
JB		 2084 dev_info(&vsi->back->pdev->dev,
2085 "%s: update vsi failed, aq_err=%d\n",
2086 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2087 return -ENOENT;
41c445ff
JB		 2088 }
2089
dcae29be 2090 return 0;
41c445ff
JB		 2091}
2092
2093/**
2094 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2095 * @vsi: the vsi being adjusted
2096 *
2097 * Just use the vlan_rx_register() service to put it back to normal
2098 **/
2099void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2100{
6c12fcbf
GR		 2101 i40e_vlan_stripping_disable(vsi);
2102
41c445ff 2103 vsi->info.pvid = 0;
41c445ff
JB		 2104}
2105
2106/**
2107 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2108 * @vsi: ptr to the VSI
2109 *
2110 * If this function returns with an error, then it's possible one or
2111 * more of the rings is populated (while the rest are not). It is the
2112 * callers duty to clean those orphaned rings.
2113 *
2114 * Return 0 on success, negative on failure
2115 **/
2116static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2117{
2118 int i, err = 0;
2119
2120 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2121 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2122
2123 return err;
2124}
2125
2126/**
2127 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2128 * @vsi: ptr to the VSI
2129 *
2130 * Free VSI's transmit software resources
2131 **/
2132static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2133{
2134 int i;
2135
8e9dca53
GR		 2136 if (!vsi->tx_rings)
2137 return;
2138
41c445ff 2139 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2140 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2141 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2142}
2143
2144/**
2145 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2146 * @vsi: ptr to the VSI
2147 *
2148 * If this function returns with an error, then it's possible one or
2149 * more of the rings is populated (while the rest are not). It is the
2150 * callers duty to clean those orphaned rings.
2151 *
2152 * Return 0 on success, negative on failure
2153 **/
2154static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2155{
2156 int i, err = 0;
2157
2158 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2159 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2160 return err;
2161}
2162
2163/**
2164 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2165 * @vsi: ptr to the VSI
2166 *
2167 * Free all receive software resources
2168 **/
2169static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2170{
2171 int i;
2172
8e9dca53
GR		 2173 if (!vsi->rx_rings)
2174 return;
2175
41c445ff 2176 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2177 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2178 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2179}
2180
2181/**
2182 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2183 * @ring: The Tx ring to configure
2184 *
2185 * Configure the Tx descriptor ring in the HMC context.
2186 **/
2187static int i40e_configure_tx_ring(struct i40e_ring *ring)
2188{
2189 struct i40e_vsi *vsi = ring->vsi;
2190 u16 pf_q = vsi->base_queue + ring->queue_index;
2191 struct i40e_hw *hw = &vsi->back->hw;
2192 struct i40e_hmc_obj_txq tx_ctx;
2193 i40e_status err = 0;
2194 u32 qtx_ctl = 0;
2195
2196 /* some ATR related tx ring init */
60ea5f83 2197 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2198 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2199 ring->atr_count = 0;
2200 } else {
2201 ring->atr_sample_rate = 0;
2202 }
2203
2204 /* initialize XPS */
2205 if (ring->q_vector && ring->netdev &&
4e3b35b0 2206 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2207 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2208 netif_set_xps_queue(ring->netdev,
2209 &ring->q_vector->affinity_mask,
2210 ring->queue_index);
2211
2212 /* clear the context structure first */
2213 memset(&tx_ctx, 0, sizeof(tx_ctx));
2214
2215 tx_ctx.new_context = 1;
2216 tx_ctx.base = (ring->dma / 128);
2217 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2218 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2219 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2220 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2221 /* FDIR VSI tx ring can still use RS bit and writebacks */
2222 if (vsi->type != I40E_VSI_FDIR)
2223 tx_ctx.head_wb_ena = 1;
2224 tx_ctx.head_wb_addr = ring->dma +
2225 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2226
2227 /* As part of VSI creation/update, FW allocates certain
2228 * Tx arbitration queue sets for each TC enabled for
2229 * the VSI. The FW returns the handles to these queue
2230 * sets as part of the response buffer to Add VSI,
2231 * Update VSI, etc. AQ commands. It is expected that
2232 * these queue set handles be associated with the Tx
2233 * queues by the driver as part of the TX queue context
2234 * initialization. This has to be done regardless of
2235 * DCB as by default everything is mapped to TC0.
2236 */
2237 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2238 tx_ctx.rdylist_act = 0;
2239
2240 /* clear the context in the HMC */
2241 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2242 if (err) {
2243 dev_info(&vsi->back->pdev->dev,
2244 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2245 ring->queue_index, pf_q, err);
2246 return -ENOMEM;
2247 }
2248
2249 /* set the context in the HMC */
2250 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2251 if (err) {
2252 dev_info(&vsi->back->pdev->dev,
2253 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2254 ring->queue_index, pf_q, err);
2255 return -ENOMEM;
2256 }
2257
2258 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2259 if (vsi->type == I40E_VSI_VMDQ2)
2260 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2261 else
2262 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2263 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2264 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2265 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2266 i40e_flush(hw);
2267
2268 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2269
2270 /* cache tail off for easier writes later */
2271 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2272
2273 return 0;
2274}
2275
2276/**
2277 * i40e_configure_rx_ring - Configure a receive ring context
2278 * @ring: The Rx ring to configure
2279 *
2280 * Configure the Rx descriptor ring in the HMC context.
2281 **/
2282static int i40e_configure_rx_ring(struct i40e_ring *ring)
2283{
2284 struct i40e_vsi *vsi = ring->vsi;
2285 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2286 u16 pf_q = vsi->base_queue + ring->queue_index;
2287 struct i40e_hw *hw = &vsi->back->hw;
2288 struct i40e_hmc_obj_rxq rx_ctx;
2289 i40e_status err = 0;
2290
2291 ring->state = 0;
2292
2293 /* clear the context structure first */
2294 memset(&rx_ctx, 0, sizeof(rx_ctx));
2295
2296 ring->rx_buf_len = vsi->rx_buf_len;
2297 ring->rx_hdr_len = vsi->rx_hdr_len;
2298
2299 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2300 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2301
2302 rx_ctx.base = (ring->dma / 128);
2303 rx_ctx.qlen = ring->count;
2304
2305 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2306 set_ring_16byte_desc_enabled(ring);
2307 rx_ctx.dsize = 0;
2308 } else {
2309 rx_ctx.dsize = 1;
2310 }
2311
2312 rx_ctx.dtype = vsi->dtype;
2313 if (vsi->dtype) {
2314 set_ring_ps_enabled(ring);
2315 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2316 I40E_RX_SPLIT_IP |
2317 I40E_RX_SPLIT_TCP_UDP |
2318 I40E_RX_SPLIT_SCTP;
2319 } else {
2320 rx_ctx.hsplit_0 = 0;
2321 }
2322
2323 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2324 (chain_len * ring->rx_buf_len));
2325 rx_ctx.tphrdesc_ena = 1;
2326 rx_ctx.tphwdesc_ena = 1;
2327 rx_ctx.tphdata_ena = 1;
2328 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2329 if (hw->revision_id == 0)
2330 rx_ctx.lrxqthresh = 0;
2331 else
2332 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2333 rx_ctx.crcstrip = 1;
2334 rx_ctx.l2tsel = 1;
2335 rx_ctx.showiv = 1;
acb3676b
CS		 2336 /* set the prefena field to 1 because the manual says to */
2337 rx_ctx.prefena = 1;
41c445ff
JB		 2338
2339 /* clear the context in the HMC */
2340 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2341 if (err) {
2342 dev_info(&vsi->back->pdev->dev,
2343 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2344 ring->queue_index, pf_q, err);
2345 return -ENOMEM;
2346 }
2347
2348 /* set the context in the HMC */
2349 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2350 if (err) {
2351 dev_info(&vsi->back->pdev->dev,
2352 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2353 ring->queue_index, pf_q, err);
2354 return -ENOMEM;
2355 }
2356
2357 /* cache tail for quicker writes, and clear the reg before use */
2358 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2359 writel(0, ring->tail);
2360
2361 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2362
2363 return 0;
2364}
2365
2366/**
2367 * i40e_vsi_configure_tx - Configure the VSI for Tx
2368 * @vsi: VSI structure describing this set of rings and resources
2369 *
2370 * Configure the Tx VSI for operation.
2371 **/
2372static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2373{
2374 int err = 0;
2375 u16 i;
2376
9f65e15b
AD		 2377 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2378 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2379
2380 return err;
2381}
2382
2383/**
2384 * i40e_vsi_configure_rx - Configure the VSI for Rx
2385 * @vsi: the VSI being configured
2386 *
2387 * Configure the Rx VSI for operation.
2388 **/
2389static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2390{
2391 int err = 0;
2392 u16 i;
2393
2394 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2395 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2396 + ETH_FCS_LEN + VLAN_HLEN;
2397 else
2398 vsi->max_frame = I40E_RXBUFFER_2048;
2399
2400 /* figure out correct receive buffer length */
2401 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2402 I40E_FLAG_RX_PS_ENABLED)) {
2403 case I40E_FLAG_RX_1BUF_ENABLED:
2404 vsi->rx_hdr_len = 0;
2405 vsi->rx_buf_len = vsi->max_frame;
2406 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2407 break;
2408 case I40E_FLAG_RX_PS_ENABLED:
2409 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2410 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2411 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2412 break;
2413 default:
2414 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2415 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2416 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2417 break;
2418 }
2419
2420 /* round up for the chip's needs */
2421 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2422 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2423 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2424 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2425
2426 /* set up individual rings */
2427 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2428 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2429
2430 return err;
2431}
2432
2433/**
2434 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2435 * @vsi: ptr to the VSI
2436 **/
2437static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2438{
e7046ee1 2439 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2440 u16 qoffset, qcount;
2441 int i, n;
2442
2443 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2444 return;
2445
2446 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2447 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2448 continue;
2449
2450 qoffset = vsi->tc_config.tc_info[n].qoffset;
2451 qcount = vsi->tc_config.tc_info[n].qcount;
2452 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2453 rx_ring = vsi->rx_rings[i];
2454 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2455 rx_ring->dcb_tc = n;
2456 tx_ring->dcb_tc = n;
2457 }
2458 }
2459}
2460
2461/**
2462 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2463 * @vsi: ptr to the VSI
2464 **/
2465static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2466{
2467 if (vsi->netdev)
2468 i40e_set_rx_mode(vsi->netdev);
2469}
2470
17a73f6b
JG		 2471/**
2472 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2473 * @vsi: Pointer to the targeted VSI
2474 *
2475 * This function replays the hlist on the hw where all the SB Flow Director
2476 * filters were saved.
2477 **/
2478static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2479{
2480 struct i40e_fdir_filter *filter;
2481 struct i40e_pf *pf = vsi->back;
2482 struct hlist_node *node;
2483
55a5e60b
ASJ		 2484 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2485 return;
2486
17a73f6b
JG		 2487 hlist_for_each_entry_safe(filter, node,
2488 &pf->fdir_filter_list, fdir_node) {
2489 i40e_add_del_fdir(vsi, filter, true);
2490 }
2491}
2492
41c445ff
JB		 2493/**
2494 * i40e_vsi_configure - Set up the VSI for action
2495 * @vsi: the VSI being configured
2496 **/
2497static int i40e_vsi_configure(struct i40e_vsi *vsi)
2498{
2499 int err;
2500
2501 i40e_set_vsi_rx_mode(vsi);
2502 i40e_restore_vlan(vsi);
2503 i40e_vsi_config_dcb_rings(vsi);
2504 err = i40e_vsi_configure_tx(vsi);
2505 if (!err)
2506 err = i40e_vsi_configure_rx(vsi);
2507
2508 return err;
2509}
2510
2511/**
2512 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2513 * @vsi: the VSI being configured
2514 **/
2515static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2516{
2517 struct i40e_pf *pf = vsi->back;
2518 struct i40e_q_vector *q_vector;
2519 struct i40e_hw *hw = &pf->hw;
2520 u16 vector;
2521 int i, q;
2522 u32 val;
2523 u32 qp;
2524
2525 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2526 * and PFINT_LNKLSTn registers, e.g.:
2527 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2528 */
2529 qp = vsi->base_queue;
2530 vector = vsi->base_vector;
493fb300
AD		 2531 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2532 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2533 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2534 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2535 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2536 q_vector->rx.itr);
2537 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2538 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2539 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2540 q_vector->tx.itr);
2541
2542 /* Linked list for the queuepairs assigned to this vector */
2543 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2544 for (q = 0; q < q_vector->num_ringpairs; q++) {
2545 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2546 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2547 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2548 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2549 (I40E_QUEUE_TYPE_TX
2550 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2551
2552 wr32(hw, I40E_QINT_RQCTL(qp), val);
2553
2554 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2555 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2556 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2557 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2558 (I40E_QUEUE_TYPE_RX
2559 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2560
2561 /* Terminate the linked list */
2562 if (q == (q_vector->num_ringpairs - 1))
2563 val |= (I40E_QUEUE_END_OF_LIST
2564 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2565
2566 wr32(hw, I40E_QINT_TQCTL(qp), val);
2567 qp++;
2568 }
2569 }
2570
2571 i40e_flush(hw);
2572}
2573
2574/**
2575 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2576 * @hw: ptr to the hardware info
2577 **/
2578static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2579{
2580 u32 val;
2581
2582 /* clear things first */
2583 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2584 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2585
2586 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2587 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2588 I40E_PFINT_ICR0_ENA_GRST_MASK |
2589 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2590 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2591 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2592 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2593 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2594 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2595
2596 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2597
2598 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2599 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2600 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2601
2602 /* OTHER_ITR_IDX = 0 */
2603 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2604}
2605
2606/**
2607 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2608 * @vsi: the VSI being configured
2609 **/
2610static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2611{
493fb300 2612 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2613 struct i40e_pf *pf = vsi->back;
2614 struct i40e_hw *hw = &pf->hw;
2615 u32 val;
2616
2617 /* set the ITR configuration */
2618 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2619 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2620 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2621 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2622 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2623 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2624
2625 i40e_enable_misc_int_causes(hw);
2626
2627 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2628 wr32(hw, I40E_PFINT_LNKLST0, 0);
2629
f29eaa3d 2630 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2631 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2632 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2633 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2634
2635 wr32(hw, I40E_QINT_RQCTL(0), val);
2636
2637 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2638 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2639 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2640
2641 wr32(hw, I40E_QINT_TQCTL(0), val);
2642 i40e_flush(hw);
2643}
2644
2ef28cfb
MW		 2645/**
2646 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2647 * @pf: board private structure
2648 **/
2649void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2650{
2651 struct i40e_hw *hw = &pf->hw;
2652
2653 wr32(hw, I40E_PFINT_DYN_CTL0,
2654 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2655 i40e_flush(hw);
2656}
2657
41c445ff
JB		 2658/**
2659 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2660 * @pf: board private structure
2661 **/
116a57d4 2662void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2663{
2664 struct i40e_hw *hw = &pf->hw;
2665 u32 val;
2666
2667 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2668 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2669 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2670
2671 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2672 i40e_flush(hw);
2673}
2674
2675/**
2676 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2677 * @vsi: pointer to a vsi
2678 * @vector: enable a particular Hw Interrupt vector
2679 **/
2680void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2681{
2682 struct i40e_pf *pf = vsi->back;
2683 struct i40e_hw *hw = &pf->hw;
2684 u32 val;
2685
2686 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2687 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2688 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2689 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2690 /* skip the flush */
41c445ff
JB		 2691}
2692
2693/**
2694 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2695 * @irq: interrupt number
2696 * @data: pointer to a q_vector
2697 **/
2698static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2699{
2700 struct i40e_q_vector *q_vector = data;
2701
cd0b6fa6 2702 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2703 return IRQ_HANDLED;
2704
2705 napi_schedule(&q_vector->napi);
2706
2707 return IRQ_HANDLED;
2708}
2709
41c445ff
JB		 2710/**
2711 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2712 * @vsi: the VSI being configured
2713 * @basename: name for the vector
2714 *
2715 * Allocates MSI-X vectors and requests interrupts from the kernel.
2716 **/
2717static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2718{
2719 int q_vectors = vsi->num_q_vectors;
2720 struct i40e_pf *pf = vsi->back;
2721 int base = vsi->base_vector;
2722 int rx_int_idx = 0;
2723 int tx_int_idx = 0;
2724 int vector, err;
2725
2726 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2727 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2728
cd0b6fa6 2729 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2730 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2731 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2732 tx_int_idx++;
cd0b6fa6 2733 } else if (q_vector->rx.ring) {
41c445ff
JB		 2734 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2735 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2736 } else if (q_vector->tx.ring) {
41c445ff
JB		 2737 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2738 "%s-%s-%d", basename, "tx", tx_int_idx++);
2739 } else {
2740 /* skip this unused q_vector */
2741 continue;
2742 }
2743 err = request_irq(pf->msix_entries[base + vector].vector,
2744 vsi->irq_handler,
2745 0,
2746 q_vector->name,
2747 q_vector);
2748 if (err) {
2749 dev_info(&pf->pdev->dev,
2750 "%s: request_irq failed, error: %d\n",
2751 __func__, err);
2752 goto free_queue_irqs;
2753 }
2754 /* assign the mask for this irq */
2755 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2756 &q_vector->affinity_mask);
2757 }
2758
2759 return 0;
2760
2761free_queue_irqs:
2762 while (vector) {
2763 vector--;
2764 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2765 NULL);
2766 free_irq(pf->msix_entries[base + vector].vector,
2767 &(vsi->q_vectors[vector]));
2768 }
2769 return err;
2770}
2771
2772/**
2773 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2774 * @vsi: the VSI being un-configured
2775 **/
2776static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2777{
2778 struct i40e_pf *pf = vsi->back;
2779 struct i40e_hw *hw = &pf->hw;
2780 int base = vsi->base_vector;
2781 int i;
2782
2783 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2784 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2785 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2786 }
2787
2788 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2789 for (i = vsi->base_vector;
2790 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2791 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2792
2793 i40e_flush(hw);
2794 for (i = 0; i < vsi->num_q_vectors; i++)
2795 synchronize_irq(pf->msix_entries[i + base].vector);
2796 } else {
2797 /* Legacy and MSI mode - this stops all interrupt handling */
2798 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2799 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2800 i40e_flush(hw);
2801 synchronize_irq(pf->pdev->irq);
2802 }
2803}
2804
2805/**
2806 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2807 * @vsi: the VSI being configured
2808 **/
2809static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2810{
2811 struct i40e_pf *pf = vsi->back;
2812 int i;
2813
2814 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2815 for (i = vsi->base_vector;
2816 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2817 i40e_irq_dynamic_enable(vsi, i);
2818 } else {
2819 i40e_irq_dynamic_enable_icr0(pf);
2820 }
2821
1022cb6c 2822 i40e_flush(&pf->hw);
41c445ff
JB		 2823 return 0;
2824}
2825
2826/**
2827 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2828 * @pf: board private structure
2829 **/
2830static void i40e_stop_misc_vector(struct i40e_pf *pf)
2831{
2832 /* Disable ICR 0 */
2833 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2834 i40e_flush(&pf->hw);
2835}
2836
2837/**
2838 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2839 * @irq: interrupt number
2840 * @data: pointer to a q_vector
2841 *
2842 * This is the handler used for all MSI/Legacy interrupts, and deals
2843 * with both queue and non-queue interrupts. This is also used in
2844 * MSIX mode to handle the non-queue interrupts.
2845 **/
2846static irqreturn_t i40e_intr(int irq, void *data)
2847{
2848 struct i40e_pf *pf = (struct i40e_pf *)data;
2849 struct i40e_hw *hw = &pf->hw;
5e823066 2850 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2851 u32 icr0, icr0_remaining;
2852 u32 val, ena_mask;
2853
2854 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2855 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2856
116a57d4
SN		 2857 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2858 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2859 goto enable_intr;
41c445ff 2860
cd92e72f
SN		 2861 /* if interrupt but no bits showing, must be SWINT */
2862 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2863 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2864 pf->sw_int_count++;
2865
41c445ff
JB		 2866 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2867 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2868
2869 /* temporarily disable queue cause for NAPI processing */
2870 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2871 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2872 wr32(hw, I40E_QINT_RQCTL(0), qval);
2873
2874 qval = rd32(hw, I40E_QINT_TQCTL(0));
2875 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2876 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2877
2878 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2879 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2880 }
2881
2882 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2883 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2884 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2885 }
2886
2887 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2888 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2889 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2890 }
2891
2892 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2893 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2894 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2895 }
2896
2897 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2898 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2899 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2900 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2901 val = rd32(hw, I40E_GLGEN_RSTAT);
2902 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2903 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2904 if (val == I40E_RESET_CORER) {
41c445ff 2905 pf->corer_count++;
4eb3f768 2906 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2907 pf->globr_count++;
4eb3f768 2908 } else if (val == I40E_RESET_EMPR) {
41c445ff 2909 pf->empr_count++;
4eb3f768
SN		 2910 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2911 }
41c445ff
JB		 2912 }
2913
9c010ee0
ASJ		 2914 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2915 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2916 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2917 }
2918
beb0dff1
JK		 2919 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2920 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2921
2922 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 2923 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 2924 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 2925 }
beb0dff1
JK		 2926 }
2927
41c445ff
JB		 2928 /* If a critical error is pending we have no choice but to reset the
2929 * device.
2930 * Report and mask out any remaining unexpected interrupts.
2931 */
2932 icr0_remaining = icr0 & ena_mask;
2933 if (icr0_remaining) {
2934 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2935 icr0_remaining);
9c010ee0 2936 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2937 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2938 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2939 dev_info(&pf->pdev->dev, "device will be reset\n");
2940 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2941 i40e_service_event_schedule(pf);
41c445ff
JB		 2942 }
2943 ena_mask &= ~icr0_remaining;
2944 }
5e823066 2945 ret = IRQ_HANDLED;
41c445ff 2946
5e823066 2947enable_intr:
41c445ff
JB		 2948 /* re-enable interrupt causes */
2949 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2950 if (!test_bit(__I40E_DOWN, &pf->state)) {
2951 i40e_service_event_schedule(pf);
2952 i40e_irq_dynamic_enable_icr0(pf);
2953 }
2954
5e823066 2955 return ret;
41c445ff
JB		 2956}
2957
cbf61325
ASJ		 2958/**
2959 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2960 * @tx_ring: tx ring to clean
2961 * @budget: how many cleans we're allowed
2962 *
2963 * Returns true if there's any budget left (e.g. the clean is finished)
2964 **/
2965static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2966{
2967 struct i40e_vsi *vsi = tx_ring->vsi;
2968 u16 i = tx_ring->next_to_clean;
2969 struct i40e_tx_buffer *tx_buf;
2970 struct i40e_tx_desc *tx_desc;
2971
2972 tx_buf = &tx_ring->tx_bi[i];
2973 tx_desc = I40E_TX_DESC(tx_ring, i);
2974 i -= tx_ring->count;
2975
2976 do {
2977 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2978
2979 /* if next_to_watch is not set then there is no work pending */
2980 if (!eop_desc)
2981 break;
2982
2983 /* prevent any other reads prior to eop_desc */
2984 read_barrier_depends();
2985
2986 /* if the descriptor isn't done, no work yet to do */
2987 if (!(eop_desc->cmd_type_offset_bsz &
2988 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2989 break;
2990
2991 /* clear next_to_watch to prevent false hangs */
2992 tx_buf->next_to_watch = NULL;
2993
2994 /* unmap skb header data */
2995 dma_unmap_single(tx_ring->dev,
2996 dma_unmap_addr(tx_buf, dma),
2997 dma_unmap_len(tx_buf, len),
2998 DMA_TO_DEVICE);
2999
3000 dma_unmap_len_set(tx_buf, len, 0);
3001
3002
3003 /* move to the next desc and buffer to clean */
3004 tx_buf++;
3005 tx_desc++;
3006 i++;
3007 if (unlikely(!i)) {
3008 i -= tx_ring->count;
3009 tx_buf = tx_ring->tx_bi;
3010 tx_desc = I40E_TX_DESC(tx_ring, 0);
3011 }
3012
3013 /* update budget accounting */
3014 budget--;
3015 } while (likely(budget));
3016
3017 i += tx_ring->count;
3018 tx_ring->next_to_clean = i;
3019
3020 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3021 i40e_irq_dynamic_enable(vsi,
3022 tx_ring->q_vector->v_idx + vsi->base_vector);
3023 }
3024 return budget > 0;
3025}
3026
3027/**
3028 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3029 * @irq: interrupt number
3030 * @data: pointer to a q_vector
3031 **/
3032static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3033{
3034 struct i40e_q_vector *q_vector = data;
3035 struct i40e_vsi *vsi;
3036
3037 if (!q_vector->tx.ring)
3038 return IRQ_HANDLED;
3039
3040 vsi = q_vector->tx.ring->vsi;
3041 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3042
3043 return IRQ_HANDLED;
3044}
3045
41c445ff 3046/**
cd0b6fa6 3047 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3048 * @vsi: the VSI being configured
3049 * @v_idx: vector index
cd0b6fa6 3050 * @qp_idx: queue pair index
41c445ff 3051 **/
cd0b6fa6 3052static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3053{
493fb300 3054 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3055 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3056 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3057
3058 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3059 tx_ring->next = q_vector->tx.ring;
3060 q_vector->tx.ring = tx_ring;
41c445ff 3061 q_vector->tx.count++;
cd0b6fa6
AD		 3062
3063 rx_ring->q_vector = q_vector;
3064 rx_ring->next = q_vector->rx.ring;
3065 q_vector->rx.ring = rx_ring;
3066 q_vector->rx.count++;
41c445ff
JB		 3067}
3068
3069/**
3070 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3071 * @vsi: the VSI being configured
3072 *
3073 * This function maps descriptor rings to the queue-specific vectors
3074 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3075 * one vector per queue pair, but on a constrained vector budget, we
3076 * group the queue pairs as "efficiently" as possible.
3077 **/
3078static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3079{
3080 int qp_remaining = vsi->num_queue_pairs;
3081 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3082 int num_ringpairs;
41c445ff
JB		 3083 int v_start = 0;
3084 int qp_idx = 0;
3085
3086 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3087 * group them so there are multiple queues per vector.
3088 */
3089 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3090 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3091
3092 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3093
3094 q_vector->num_ringpairs = num_ringpairs;
3095
3096 q_vector->rx.count = 0;
3097 q_vector->tx.count = 0;
3098 q_vector->rx.ring = NULL;
3099 q_vector->tx.ring = NULL;
3100
3101 while (num_ringpairs--) {
3102 map_vector_to_qp(vsi, v_start, qp_idx);
3103 qp_idx++;
3104 qp_remaining--;
41c445ff
JB		 3105 }
3106 }
3107}
3108
3109/**
3110 * i40e_vsi_request_irq - Request IRQ from the OS
3111 * @vsi: the VSI being configured
3112 * @basename: name for the vector
3113 **/
3114static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3115{
3116 struct i40e_pf *pf = vsi->back;
3117 int err;
3118
3119 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3120 err = i40e_vsi_request_irq_msix(vsi, basename);
3121 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3122 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3123 pf->misc_int_name, pf);
3124 else
3125 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3126 pf->misc_int_name, pf);
3127
3128 if (err)
3129 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3130
3131 return err;
3132}
3133
3134#ifdef CONFIG_NET_POLL_CONTROLLER
3135/**
3136 * i40e_netpoll - A Polling 'interrupt'handler
3137 * @netdev: network interface device structure
3138 *
3139 * This is used by netconsole to send skbs without having to re-enable
3140 * interrupts. It's not called while the normal interrupt routine is executing.
3141 **/
3142static void i40e_netpoll(struct net_device *netdev)
3143{
3144 struct i40e_netdev_priv *np = netdev_priv(netdev);
3145 struct i40e_vsi *vsi = np->vsi;
3146 struct i40e_pf *pf = vsi->back;
3147 int i;
3148
3149 /* if interface is down do nothing */
3150 if (test_bit(__I40E_DOWN, &vsi->state))
3151 return;
3152
3153 pf->flags |= I40E_FLAG_IN_NETPOLL;
3154 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3155 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3156 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3157 } else {
3158 i40e_intr(pf->pdev->irq, netdev);
3159 }
3160 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3161}
3162#endif
3163
3164/**
3165 * i40e_vsi_control_tx - Start or stop a VSI's rings
3166 * @vsi: the VSI being configured
3167 * @enable: start or stop the rings
3168 **/
3169static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3170{
3171 struct i40e_pf *pf = vsi->back;
3172 struct i40e_hw *hw = &pf->hw;
3173 int i, j, pf_q;
3174 u32 tx_reg;
3175
3176 pf_q = vsi->base_queue;
3177 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3178 for (j = 0; j < 50; j++) {
41c445ff 3179 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3180 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3181 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3182 break;
3183 usleep_range(1000, 2000);
3184 }
fda972f6 3185 /* Skip if the queue is already in the requested state */
7c122007 3186 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3187 continue;
41c445ff
JB		 3188
3189 /* turn on/off the queue */
c5c9eb9e
SN		 3190 if (enable) {
3191 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3192 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3193 } else {
41c445ff 3194 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3195 }
41c445ff
JB		 3196
3197 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3198
3199 /* wait for the change to finish */
3200 for (j = 0; j < 10; j++) {
3201 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
7c122007
CS		 3202 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3203 break;
41c445ff
JB		 3204
3205 udelay(10);
3206 }
3207 if (j >= 10) {
3208 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3209 pf_q, (enable ? "en" : "dis"));
3210 return -ETIMEDOUT;
3211 }
3212 }
3213
7134f9ce
JB		 3214 if (hw->revision_id == 0)
3215 mdelay(50);
3216
41c445ff
JB		 3217 return 0;
3218}
3219
3220/**
3221 * i40e_vsi_control_rx - Start or stop a VSI's rings
3222 * @vsi: the VSI being configured
3223 * @enable: start or stop the rings
3224 **/
3225static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3226{
3227 struct i40e_pf *pf = vsi->back;
3228 struct i40e_hw *hw = &pf->hw;
3229 int i, j, pf_q;
3230 u32 rx_reg;
3231
3232 pf_q = vsi->base_queue;
3233 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3234 for (j = 0; j < 50; j++) {
41c445ff 3235 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3236 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3237 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3238 break;
3239 usleep_range(1000, 2000);
3240 }
41c445ff 3241
7c122007
CS		 3242 /* Skip if the queue is already in the requested state */
3243 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3244 continue;
41c445ff
JB		 3245
3246 /* turn on/off the queue */
3247 if (enable)
6c5ef620 3248 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3249 else
6c5ef620 3250 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3251 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3252
3253 /* wait for the change to finish */
3254 for (j = 0; j < 10; j++) {
3255 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3256
7c122007
CS		 3257 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3258 break;
41c445ff
JB		 3259
3260 udelay(10);
3261 }
3262 if (j >= 10) {
3263 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3264 pf_q, (enable ? "en" : "dis"));
3265 return -ETIMEDOUT;
3266 }
3267 }
3268
3269 return 0;
3270}
3271
3272/**
3273 * i40e_vsi_control_rings - Start or stop a VSI's rings
3274 * @vsi: the VSI being configured
3275 * @enable: start or stop the rings
3276 **/
fc18eaa0 3277int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3278{
3b867b28 3279 int ret = 0;
41c445ff
JB		 3280
3281 /* do rx first for enable and last for disable */
3282 if (request) {
3283 ret = i40e_vsi_control_rx(vsi, request);
3284 if (ret)
3285 return ret;
3286 ret = i40e_vsi_control_tx(vsi, request);
3287 } else {
3b867b28
ASJ		 3288 /* Ignore return value, we need to shutdown whatever we can */
3289 i40e_vsi_control_tx(vsi, request);
3290 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3291 }
3292
3293 return ret;
3294}
3295
3296/**
3297 * i40e_vsi_free_irq - Free the irq association with the OS
3298 * @vsi: the VSI being configured
3299 **/
3300static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3301{
3302 struct i40e_pf *pf = vsi->back;
3303 struct i40e_hw *hw = &pf->hw;
3304 int base = vsi->base_vector;
3305 u32 val, qp;
3306 int i;
3307
3308 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3309 if (!vsi->q_vectors)
3310 return;
3311
3312 for (i = 0; i < vsi->num_q_vectors; i++) {
3313 u16 vector = i + base;
3314
3315 /* free only the irqs that were actually requested */
78681b1f
SN		 3316 if (!vsi->q_vectors[i] ||
3317 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3318 continue;
3319
3320 /* clear the affinity_mask in the IRQ descriptor */
3321 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3322 NULL);
3323 free_irq(pf->msix_entries[vector].vector,
493fb300 3324 vsi->q_vectors[i]);
41c445ff
JB		 3325
3326 /* Tear down the interrupt queue link list
3327 *
3328 * We know that they come in pairs and always
3329 * the Rx first, then the Tx. To clear the
3330 * link list, stick the EOL value into the
3331 * next_q field of the registers.
3332 */
3333 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3334 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3335 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3336 val |= I40E_QUEUE_END_OF_LIST
3337 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3338 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3339
3340 while (qp != I40E_QUEUE_END_OF_LIST) {
3341 u32 next;
3342
3343 val = rd32(hw, I40E_QINT_RQCTL(qp));
3344
3345 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3346 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3347 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3348 I40E_QINT_RQCTL_INTEVENT_MASK);
3349
3350 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3351 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3352
3353 wr32(hw, I40E_QINT_RQCTL(qp), val);
3354
3355 val = rd32(hw, I40E_QINT_TQCTL(qp));
3356
3357 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3358 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3359
3360 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3361 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3362 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3363 I40E_QINT_TQCTL_INTEVENT_MASK);
3364
3365 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3366 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3367
3368 wr32(hw, I40E_QINT_TQCTL(qp), val);
3369 qp = next;
3370 }
3371 }
3372 } else {
3373 free_irq(pf->pdev->irq, pf);
3374
3375 val = rd32(hw, I40E_PFINT_LNKLST0);
3376 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3377 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3378 val |= I40E_QUEUE_END_OF_LIST
3379 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3380 wr32(hw, I40E_PFINT_LNKLST0, val);
3381
3382 val = rd32(hw, I40E_QINT_RQCTL(qp));
3383 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3384 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3385 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3386 I40E_QINT_RQCTL_INTEVENT_MASK);
3387
3388 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3389 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3390
3391 wr32(hw, I40E_QINT_RQCTL(qp), val);
3392
3393 val = rd32(hw, I40E_QINT_TQCTL(qp));
3394
3395 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3396 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3397 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3398 I40E_QINT_TQCTL_INTEVENT_MASK);
3399
3400 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3401 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3402
3403 wr32(hw, I40E_QINT_TQCTL(qp), val);
3404 }
3405}
3406
493fb300
AD		 3407/**
3408 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3409 * @vsi: the VSI being configured
3410 * @v_idx: Index of vector to be freed
3411 *
3412 * This function frees the memory allocated to the q_vector. In addition if
3413 * NAPI is enabled it will delete any references to the NAPI struct prior
3414 * to freeing the q_vector.
3415 **/
3416static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3417{
3418 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3419 struct i40e_ring *ring;
493fb300
AD		 3420
3421 if (!q_vector)
3422 return;
3423
3424 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3425 i40e_for_each_ring(ring, q_vector->tx)
3426 ring->q_vector = NULL;
3427
3428 i40e_for_each_ring(ring, q_vector->rx)
3429 ring->q_vector = NULL;
493fb300
AD		 3430
3431 /* only VSI w/ an associated netdev is set up w/ NAPI */
3432 if (vsi->netdev)
3433 netif_napi_del(&q_vector->napi);
3434
3435 vsi->q_vectors[v_idx] = NULL;
3436
3437 kfree_rcu(q_vector, rcu);
3438}
3439
41c445ff
JB		 3440/**
3441 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3442 * @vsi: the VSI being un-configured
3443 *
3444 * This frees the memory allocated to the q_vectors and
3445 * deletes references to the NAPI struct.
3446 **/
3447static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3448{
3449 int v_idx;
3450
493fb300
AD		 3451 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3452 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3453}
3454
3455/**
3456 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3457 * @pf: board private structure
3458 **/
3459static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3460{
3461 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3462 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3463 pci_disable_msix(pf->pdev);
3464 kfree(pf->msix_entries);
3465 pf->msix_entries = NULL;
3466 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3467 pci_disable_msi(pf->pdev);
3468 }
3469 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3470}
3471
3472/**
3473 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3474 * @pf: board private structure
3475 *
3476 * We go through and clear interrupt specific resources and reset the structure
3477 * to pre-load conditions
3478 **/
3479static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3480{
3481 int i;
3482
3483 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3484 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3485 if (pf->vsi[i])
3486 i40e_vsi_free_q_vectors(pf->vsi[i]);
3487 i40e_reset_interrupt_capability(pf);
3488}
3489
3490/**
3491 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3492 * @vsi: the VSI being configured
3493 **/
3494static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3495{
3496 int q_idx;
3497
3498 if (!vsi->netdev)
3499 return;
3500
3501 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3502 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3503}
3504
3505/**
3506 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3507 * @vsi: the VSI being configured
3508 **/
3509static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3510{
3511 int q_idx;
3512
3513 if (!vsi->netdev)
3514 return;
3515
3516 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3517 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3518}
3519
90ef8d47
SN		 3520/**
3521 * i40e_vsi_close - Shut down a VSI
3522 * @vsi: the vsi to be quelled
3523 **/
3524static void i40e_vsi_close(struct i40e_vsi *vsi)
3525{
3526 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3527 i40e_down(vsi);
3528 i40e_vsi_free_irq(vsi);
3529 i40e_vsi_free_tx_resources(vsi);
3530 i40e_vsi_free_rx_resources(vsi);
3531}
3532
41c445ff
JB		 3533/**
3534 * i40e_quiesce_vsi - Pause a given VSI
3535 * @vsi: the VSI being paused
3536 **/
3537static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3538{
3539 if (test_bit(__I40E_DOWN, &vsi->state))
3540 return;
3541
3542 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3543 if (vsi->netdev && netif_running(vsi->netdev)) {
3544 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3545 } else {
90ef8d47 3546 i40e_vsi_close(vsi);
41c445ff
JB		 3547 }
3548}
3549
3550/**
3551 * i40e_unquiesce_vsi - Resume a given VSI
3552 * @vsi: the VSI being resumed
3553 **/
3554static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3555{
3556 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3557 return;
3558
3559 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3560 if (vsi->netdev && netif_running(vsi->netdev))
3561 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3562 else
8276f757 3563 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3564}
3565
3566/**
3567 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3568 * @pf: the PF
3569 **/
3570static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3571{
3572 int v;
3573
3574 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3575 if (pf->vsi[v])
3576 i40e_quiesce_vsi(pf->vsi[v]);
3577 }
3578}
3579
3580/**
3581 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3582 * @pf: the PF
3583 **/
3584static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3585{
3586 int v;
3587
3588 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3589 if (pf->vsi[v])
3590 i40e_unquiesce_vsi(pf->vsi[v]);
3591 }
3592}
3593
3594/**
3595 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3596 * @dcbcfg: the corresponding DCBx configuration structure
3597 *
3598 * Return the number of TCs from given DCBx configuration
3599 **/
3600static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3601{
078b5876
JB		 3602 u8 num_tc = 0;
3603 int i;
41c445ff
JB		 3604
3605 /* Scan the ETS Config Priority Table to find
3606 * traffic class enabled for a given priority
3607 * and use the traffic class index to get the
3608 * number of traffic classes enabled
3609 */
3610 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3611 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3612 num_tc = dcbcfg->etscfg.prioritytable[i];
3613 }
3614
3615 /* Traffic class index starts from zero so
3616 * increment to return the actual count
3617 */
078b5876 3618 return num_tc + 1;
41c445ff
JB		 3619}
3620
3621/**
3622 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3623 * @dcbcfg: the corresponding DCBx configuration structure
3624 *
3625 * Query the current DCB configuration and return the number of
3626 * traffic classes enabled from the given DCBX config
3627 **/
3628static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3629{
3630 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3631 u8 enabled_tc = 1;
3632 u8 i;
3633
3634 for (i = 0; i < num_tc; i++)
3635 enabled_tc |= 1 << i;
3636
3637 return enabled_tc;
3638}
3639
3640/**
3641 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3642 * @pf: PF being queried
3643 *
3644 * Return number of traffic classes enabled for the given PF
3645 **/
3646static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3647{
3648 struct i40e_hw *hw = &pf->hw;
3649 u8 i, enabled_tc;
3650 u8 num_tc = 0;
3651 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3652
3653 /* If DCB is not enabled then always in single TC */
3654 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3655 return 1;
3656
3657 /* MFP mode return count of enabled TCs for this PF */
3658 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3659 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3660 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3661 if (enabled_tc & (1 << i))
3662 num_tc++;
3663 }
3664 return num_tc;
3665 }
3666
3667 /* SFP mode will be enabled for all TCs on port */
3668 return i40e_dcb_get_num_tc(dcbcfg);
3669}
3670
3671/**
3672 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3673 * @pf: PF being queried
3674 *
3675 * Return a bitmap for first enabled traffic class for this PF.
3676 **/
3677static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3678{
3679 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3680 u8 i = 0;
3681
3682 if (!enabled_tc)
3683 return 0x1; /* TC0 */
3684
3685 /* Find the first enabled TC */
3686 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3687 if (enabled_tc & (1 << i))
3688 break;
3689 }
3690
3691 return 1 << i;
3692}
3693
3694/**
3695 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3696 * @pf: PF being queried
3697 *
3698 * Return a bitmap for enabled traffic classes for this PF.
3699 **/
3700static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3701{
3702 /* If DCB is not enabled for this PF then just return default TC */
3703 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3704 return i40e_pf_get_default_tc(pf);
3705
3706 /* MFP mode will have enabled TCs set by FW */
3707 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3708 return pf->hw.func_caps.enabled_tcmap;
3709
3710 /* SFP mode we want PF to be enabled for all TCs */
3711 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3712}
3713
3714/**
3715 * i40e_vsi_get_bw_info - Query VSI BW Information
3716 * @vsi: the VSI being queried
3717 *
3718 * Returns 0 on success, negative value on failure
3719 **/
3720static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3721{
3722 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3723 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3724 struct i40e_pf *pf = vsi->back;
3725 struct i40e_hw *hw = &pf->hw;
dcae29be 3726 i40e_status aq_ret;
41c445ff 3727 u32 tc_bw_max;
41c445ff
JB		 3728 int i;
3729
3730 /* Get the VSI level BW configuration */
dcae29be
JB		 3731 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3732 if (aq_ret) {
41c445ff
JB		 3733 dev_info(&pf->pdev->dev,
3734 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3735 aq_ret, pf->hw.aq.asq_last_status);
3736 return -EINVAL;
41c445ff
JB		 3737 }
3738
3739 /* Get the VSI level BW configuration per TC */
dcae29be 3740 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3741 NULL);
dcae29be 3742 if (aq_ret) {
41c445ff
JB		 3743 dev_info(&pf->pdev->dev,
3744 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3745 aq_ret, pf->hw.aq.asq_last_status);
3746 return -EINVAL;
41c445ff
JB		 3747 }
3748
3749 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3750 dev_info(&pf->pdev->dev,
3751 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3752 bw_config.tc_valid_bits,
3753 bw_ets_config.tc_valid_bits);
3754 /* Still continuing */
3755 }
3756
3757 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3758 vsi->bw_max_quanta = bw_config.max_bw;
3759 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3760 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3761 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3762 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3763 vsi->bw_ets_limit_credits[i] =
3764 le16_to_cpu(bw_ets_config.credits[i]);
3765 /* 3 bits out of 4 for each TC */
3766 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3767 }
078b5876 3768
dcae29be 3769 return 0;
41c445ff
JB		 3770}
3771
3772/**
3773 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3774 * @vsi: the VSI being configured
3775 * @enabled_tc: TC bitmap
3776 * @bw_credits: BW shared credits per TC
3777 *
3778 * Returns 0 on success, negative value on failure
3779 **/
dcae29be 3780static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3781 u8 *bw_share)
3782{
3783 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3784 i40e_status aq_ret;
3785 int i;
41c445ff
JB		 3786
3787 bw_data.tc_valid_bits = enabled_tc;
3788 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3789 bw_data.tc_bw_credits[i] = bw_share[i];
3790
dcae29be
JB		 3791 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3792 NULL);
3793 if (aq_ret) {
41c445ff 3794 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3795 "AQ command Config VSI BW allocation per TC failed = %d\n",
3796 vsi->back->hw.aq.asq_last_status);
dcae29be 3797 return -EINVAL;
41c445ff
JB		 3798 }
3799
3800 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3801 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3802
dcae29be 3803 return 0;
41c445ff
JB		 3804}
3805
3806/**
3807 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3808 * @vsi: the VSI being configured
3809 * @enabled_tc: TC map to be enabled
3810 *
3811 **/
3812static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3813{
3814 struct net_device *netdev = vsi->netdev;
3815 struct i40e_pf *pf = vsi->back;
3816 struct i40e_hw *hw = &pf->hw;
3817 u8 netdev_tc = 0;
3818 int i;
3819 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3820
3821 if (!netdev)
3822 return;
3823
3824 if (!enabled_tc) {
3825 netdev_reset_tc(netdev);
3826 return;
3827 }
3828
3829 /* Set up actual enabled TCs on the VSI */
3830 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3831 return;
3832
3833 /* set per TC queues for the VSI */
3834 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3835 /* Only set TC queues for enabled tcs
3836 *
3837 * e.g. For a VSI that has TC0 and TC3 enabled the
3838 * enabled_tc bitmap would be 0x00001001; the driver
3839 * will set the numtc for netdev as 2 that will be
3840 * referenced by the netdev layer as TC 0 and 1.
3841 */
3842 if (vsi->tc_config.enabled_tc & (1 << i))
3843 netdev_set_tc_queue(netdev,
3844 vsi->tc_config.tc_info[i].netdev_tc,
3845 vsi->tc_config.tc_info[i].qcount,
3846 vsi->tc_config.tc_info[i].qoffset);
3847 }
3848
3849 /* Assign UP2TC map for the VSI */
3850 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3851 /* Get the actual TC# for the UP */
3852 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3853 /* Get the mapped netdev TC# for the UP */
3854 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3855 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3856 }
3857}
3858
3859/**
3860 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3861 * @vsi: the VSI being configured
3862 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3863 **/
3864static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3865 struct i40e_vsi_context *ctxt)
3866{
3867 /* copy just the sections touched not the entire info
3868 * since not all sections are valid as returned by
3869 * update vsi params
3870 */
3871 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3872 memcpy(&vsi->info.queue_mapping,
3873 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3874 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3875 sizeof(vsi->info.tc_mapping));
3876}
3877
3878/**
3879 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3880 * @vsi: VSI to be configured
3881 * @enabled_tc: TC bitmap
3882 *
3883 * This configures a particular VSI for TCs that are mapped to the
3884 * given TC bitmap. It uses default bandwidth share for TCs across
3885 * VSIs to configure TC for a particular VSI.
3886 *
3887 * NOTE:
3888 * It is expected that the VSI queues have been quisced before calling
3889 * this function.
3890 **/
3891static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3892{
3893 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3894 struct i40e_vsi_context ctxt;
3895 int ret = 0;
3896 int i;
3897
3898 /* Check if enabled_tc is same as existing or new TCs */
3899 if (vsi->tc_config.enabled_tc == enabled_tc)
3900 return ret;
3901
3902 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3903 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3904 if (enabled_tc & (1 << i))
3905 bw_share[i] = 1;
3906 }
3907
3908 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3909 if (ret) {
3910 dev_info(&vsi->back->pdev->dev,
3911 "Failed configuring TC map %d for VSI %d\n",
3912 enabled_tc, vsi->seid);
3913 goto out;
3914 }
3915
3916 /* Update Queue Pairs Mapping for currently enabled UPs */
3917 ctxt.seid = vsi->seid;
3918 ctxt.pf_num = vsi->back->hw.pf_id;
3919 ctxt.vf_num = 0;
3920 ctxt.uplink_seid = vsi->uplink_seid;
3921 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3922 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3923
3924 /* Update the VSI after updating the VSI queue-mapping information */
3925 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3926 if (ret) {
3927 dev_info(&vsi->back->pdev->dev,
3928 "update vsi failed, aq_err=%d\n",
3929 vsi->back->hw.aq.asq_last_status);
3930 goto out;
3931 }
3932 /* update the local VSI info with updated queue map */
3933 i40e_vsi_update_queue_map(vsi, &ctxt);
3934 vsi->info.valid_sections = 0;
3935
3936 /* Update current VSI BW information */
3937 ret = i40e_vsi_get_bw_info(vsi);
3938 if (ret) {
3939 dev_info(&vsi->back->pdev->dev,
3940 "Failed updating vsi bw info, aq_err=%d\n",
3941 vsi->back->hw.aq.asq_last_status);
3942 goto out;
3943 }
3944
3945 /* Update the netdev TC setup */
3946 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3947out:
3948 return ret;
3949}
3950
4e3b35b0
NP		 3951/**
3952 * i40e_veb_config_tc - Configure TCs for given VEB
3953 * @veb: given VEB
3954 * @enabled_tc: TC bitmap
3955 *
3956 * Configures given TC bitmap for VEB (switching) element
3957 **/
3958int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3959{
3960 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3961 struct i40e_pf *pf = veb->pf;
3962 int ret = 0;
3963 int i;
3964
3965 /* No TCs or already enabled TCs just return */
3966 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3967 return ret;
3968
3969 bw_data.tc_valid_bits = enabled_tc;
3970 /* bw_data.absolute_credits is not set (relative) */
3971
3972 /* Enable ETS TCs with equal BW Share for now */
3973 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3974 if (enabled_tc & (1 << i))
3975 bw_data.tc_bw_share_credits[i] = 1;
3976 }
3977
3978 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3979 &bw_data, NULL);
3980 if (ret) {
3981 dev_info(&pf->pdev->dev,
3982 "veb bw config failed, aq_err=%d\n",
3983 pf->hw.aq.asq_last_status);
3984 goto out;
3985 }
3986
3987 /* Update the BW information */
3988 ret = i40e_veb_get_bw_info(veb);
3989 if (ret) {
3990 dev_info(&pf->pdev->dev,
3991 "Failed getting veb bw config, aq_err=%d\n",
3992 pf->hw.aq.asq_last_status);
3993 }
3994
3995out:
3996 return ret;
3997}
3998
3999#ifdef CONFIG_I40E_DCB
4000/**
4001 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4002 * @pf: PF struct
4003 *
4004 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4005 * the caller would've quiesce all the VSIs before calling
4006 * this function
4007 **/
4008static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4009{
4010 u8 tc_map = 0;
4011 int ret;
4012 u8 v;
4013
4014 /* Enable the TCs available on PF to all VEBs */
4015 tc_map = i40e_pf_get_tc_map(pf);
4016 for (v = 0; v < I40E_MAX_VEB; v++) {
4017 if (!pf->veb[v])
4018 continue;
4019 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4020 if (ret) {
4021 dev_info(&pf->pdev->dev,
4022 "Failed configuring TC for VEB seid=%d\n",
4023 pf->veb[v]->seid);
4024 /* Will try to configure as many components */
4025 }
4026 }
4027
4028 /* Update each VSI */
4029 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4030 if (!pf->vsi[v])
4031 continue;
4032
4033 /* - Enable all TCs for the LAN VSI
4034 * - For all others keep them at TC0 for now
4035 */
4036 if (v == pf->lan_vsi)
4037 tc_map = i40e_pf_get_tc_map(pf);
4038 else
4039 tc_map = i40e_pf_get_default_tc(pf);
4040
4041 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4042 if (ret) {
4043 dev_info(&pf->pdev->dev,
4044 "Failed configuring TC for VSI seid=%d\n",
4045 pf->vsi[v]->seid);
4046 /* Will try to configure as many components */
4047 } else {
0672a091
NP		 4048 /* Re-configure VSI vectors based on updated TC map */
4049 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4050 if (pf->vsi[v]->netdev)
4051 i40e_dcbnl_set_all(pf->vsi[v]);
4052 }
4053 }
4054}
4055
4056/**
4057 * i40e_init_pf_dcb - Initialize DCB configuration
4058 * @pf: PF being configured
4059 *
4060 * Query the current DCB configuration and cache it
4061 * in the hardware structure
4062 **/
4063static int i40e_init_pf_dcb(struct i40e_pf *pf)
4064{
4065 struct i40e_hw *hw = &pf->hw;
4066 int err = 0;
4067
4068 if (pf->hw.func_caps.npar_enable)
4069 goto out;
4070
4071 /* Get the initial DCB configuration */
4072 err = i40e_init_dcb(hw);
4073 if (!err) {
4074 /* Device/Function is not DCBX capable */
4075 if ((!hw->func_caps.dcb) ||
4076 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4077 dev_info(&pf->pdev->dev,
4078 "DCBX offload is not supported or is disabled for this PF.\n");
4079
4080 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4081 goto out;
4082
4083 } else {
4084 /* When status is not DISABLED then DCBX in FW */
4085 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4086 DCB_CAP_DCBX_VER_IEEE;
4087 pf->flags |= I40E_FLAG_DCB_ENABLED;
4088 }
014269ff
NP		 4089 } else {
4090 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4091 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4092 }
4093
4094out:
4095 return err;
4096}
4097#endif /* CONFIG_I40E_DCB */
4098
41c445ff
JB		 4099/**
4100 * i40e_up_complete - Finish the last steps of bringing up a connection
4101 * @vsi: the VSI being configured
4102 **/
4103static int i40e_up_complete(struct i40e_vsi *vsi)
4104{
4105 struct i40e_pf *pf = vsi->back;
4106 int err;
4107
4108 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4109 i40e_vsi_configure_msix(vsi);
4110 else
4111 i40e_configure_msi_and_legacy(vsi);
4112
4113 /* start rings */
4114 err = i40e_vsi_control_rings(vsi, true);
4115 if (err)
4116 return err;
4117
4118 clear_bit(__I40E_DOWN, &vsi->state);
4119 i40e_napi_enable_all(vsi);
4120 i40e_vsi_enable_irq(vsi);
4121
4122 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4123 (vsi->netdev)) {
6d779b41 4124 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4125 netif_tx_start_all_queues(vsi->netdev);
4126 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4127 } else if (vsi->netdev) {
4128 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff 4129 }
ca64fa4e
ASJ		 4130
4131 /* replay FDIR SB filters */
4132 if (vsi->type == I40E_VSI_FDIR)
4133 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4134 i40e_service_event_schedule(pf);
4135
4136 return 0;
4137}
4138
4139/**
4140 * i40e_vsi_reinit_locked - Reset the VSI
4141 * @vsi: the VSI being configured
4142 *
4143 * Rebuild the ring structs after some configuration
4144 * has changed, e.g. MTU size.
4145 **/
4146static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4147{
4148 struct i40e_pf *pf = vsi->back;
4149
4150 WARN_ON(in_interrupt());
4151 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4152 usleep_range(1000, 2000);
4153 i40e_down(vsi);
4154
4155 /* Give a VF some time to respond to the reset. The
4156 * two second wait is based upon the watchdog cycle in
4157 * the VF driver.
4158 */
4159 if (vsi->type == I40E_VSI_SRIOV)
4160 msleep(2000);
4161 i40e_up(vsi);
4162 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4163}
4164
4165/**
4166 * i40e_up - Bring the connection back up after being down
4167 * @vsi: the VSI being configured
4168 **/
4169int i40e_up(struct i40e_vsi *vsi)
4170{
4171 int err;
4172
4173 err = i40e_vsi_configure(vsi);
4174 if (!err)
4175 err = i40e_up_complete(vsi);
4176
4177 return err;
4178}
4179
4180/**
4181 * i40e_down - Shutdown the connection processing
4182 * @vsi: the VSI being stopped
4183 **/
4184void i40e_down(struct i40e_vsi *vsi)
4185{
4186 int i;
4187
4188 /* It is assumed that the caller of this function
4189 * sets the vsi->state __I40E_DOWN bit.
4190 */
4191 if (vsi->netdev) {
4192 netif_carrier_off(vsi->netdev);
4193 netif_tx_disable(vsi->netdev);
4194 }
4195 i40e_vsi_disable_irq(vsi);
4196 i40e_vsi_control_rings(vsi, false);
4197 i40e_napi_disable_all(vsi);
4198
4199 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4200 i40e_clean_tx_ring(vsi->tx_rings[i]);
4201 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4202 }
4203}
4204
4205/**
4206 * i40e_setup_tc - configure multiple traffic classes
4207 * @netdev: net device to configure
4208 * @tc: number of traffic classes to enable
4209 **/
4210static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4211{
4212 struct i40e_netdev_priv *np = netdev_priv(netdev);
4213 struct i40e_vsi *vsi = np->vsi;
4214 struct i40e_pf *pf = vsi->back;
4215 u8 enabled_tc = 0;
4216 int ret = -EINVAL;
4217 int i;
4218
4219 /* Check if DCB enabled to continue */
4220 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4221 netdev_info(netdev, "DCB is not enabled for adapter\n");
4222 goto exit;
4223 }
4224
4225 /* Check if MFP enabled */
4226 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4227 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4228 goto exit;
4229 }
4230
4231 /* Check whether tc count is within enabled limit */
4232 if (tc > i40e_pf_get_num_tc(pf)) {
4233 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4234 goto exit;
4235 }
4236
4237 /* Generate TC map for number of tc requested */
4238 for (i = 0; i < tc; i++)
4239 enabled_tc |= (1 << i);
4240
4241 /* Requesting same TC configuration as already enabled */
4242 if (enabled_tc == vsi->tc_config.enabled_tc)
4243 return 0;
4244
4245 /* Quiesce VSI queues */
4246 i40e_quiesce_vsi(vsi);
4247
4248 /* Configure VSI for enabled TCs */
4249 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4250 if (ret) {
4251 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4252 vsi->seid);
4253 goto exit;
4254 }
4255
4256 /* Unquiesce VSI */
4257 i40e_unquiesce_vsi(vsi);
4258
4259exit:
4260 return ret;
4261}
4262
4263/**
4264 * i40e_open - Called when a network interface is made active
4265 * @netdev: network interface device structure
4266 *
4267 * The open entry point is called when a network interface is made
4268 * active by the system (IFF_UP). At this point all resources needed
4269 * for transmit and receive operations are allocated, the interrupt
4270 * handler is registered with the OS, the netdev watchdog subtask is
4271 * enabled, and the stack is notified that the interface is ready.
4272 *
4273 * Returns 0 on success, negative value on failure
4274 **/
4275static int i40e_open(struct net_device *netdev)
4276{
4277 struct i40e_netdev_priv *np = netdev_priv(netdev);
4278 struct i40e_vsi *vsi = np->vsi;
4279 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4280 int err;
4281
4eb3f768
SN		 4282 /* disallow open during test or if eeprom is broken */
4283 if (test_bit(__I40E_TESTING, &pf->state) ||
4284 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4285 return -EBUSY;
4286
4287 netif_carrier_off(netdev);
4288
6c167f58
EK		 4289 err = i40e_vsi_open(vsi);
4290 if (err)
4291 return err;
4292
059dab69
JB		 4293 /* configure global TSO hardware offload settings */
4294 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4295 TCP_FLAG_FIN) >> 16);
4296 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4297 TCP_FLAG_FIN |
4298 TCP_FLAG_CWR) >> 16);
4299 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4300
6c167f58
EK		 4301#ifdef CONFIG_I40E_VXLAN
4302 vxlan_get_rx_port(netdev);
4303#endif
4304
4305 return 0;
4306}
4307
4308/**
4309 * i40e_vsi_open -
4310 * @vsi: the VSI to open
4311 *
4312 * Finish initialization of the VSI.
4313 *
4314 * Returns 0 on success, negative value on failure
4315 **/
4316int i40e_vsi_open(struct i40e_vsi *vsi)
4317{
4318 struct i40e_pf *pf = vsi->back;
4319 char int_name[IFNAMSIZ];
4320 int err;
4321
41c445ff
JB		 4322 /* allocate descriptors */
4323 err = i40e_vsi_setup_tx_resources(vsi);
4324 if (err)
4325 goto err_setup_tx;
4326 err = i40e_vsi_setup_rx_resources(vsi);
4327 if (err)
4328 goto err_setup_rx;
4329
4330 err = i40e_vsi_configure(vsi);
4331 if (err)
4332 goto err_setup_rx;
4333
c22e3c6c
SN		 4334 if (vsi->netdev) {
4335 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4336 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4337 err = i40e_vsi_request_irq(vsi, int_name);
4338 if (err)
4339 goto err_setup_rx;
4340
4341 /* Notify the stack of the actual queue counts. */
4342 err = netif_set_real_num_tx_queues(vsi->netdev,
4343 vsi->num_queue_pairs);
4344 if (err)
4345 goto err_set_queues;
4346
4347 err = netif_set_real_num_rx_queues(vsi->netdev,
4348 vsi->num_queue_pairs);
4349 if (err)
4350 goto err_set_queues;
8a9eb7d3
SN		 4351
4352 } else if (vsi->type == I40E_VSI_FDIR) {
4353 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4354 dev_driver_string(&pf->pdev->dev));
4355 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4356 } else {
ce9ccb17 4357 err = -EINVAL;
6c167f58
EK		 4358 goto err_setup_rx;
4359 }
25946ddb 4360
41c445ff
JB		 4361 err = i40e_up_complete(vsi);
4362 if (err)
4363 goto err_up_complete;
4364
41c445ff
JB		 4365 return 0;
4366
4367err_up_complete:
4368 i40e_down(vsi);
25946ddb 4369err_set_queues:
41c445ff
JB		 4370 i40e_vsi_free_irq(vsi);
4371err_setup_rx:
4372 i40e_vsi_free_rx_resources(vsi);
4373err_setup_tx:
4374 i40e_vsi_free_tx_resources(vsi);
4375 if (vsi == pf->vsi[pf->lan_vsi])
4376 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4377
4378 return err;
4379}
4380
17a73f6b
JG		 4381/**
4382 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4383 * @pf: Pointer to pf
4384 *
4385 * This function destroys the hlist where all the Flow Director
4386 * filters were saved.
4387 **/
4388static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4389{
4390 struct i40e_fdir_filter *filter;
4391 struct hlist_node *node2;
4392
4393 hlist_for_each_entry_safe(filter, node2,
4394 &pf->fdir_filter_list, fdir_node) {
4395 hlist_del(&filter->fdir_node);
4396 kfree(filter);
4397 }
4398 pf->fdir_pf_active_filters = 0;
4399}
4400
41c445ff
JB		 4401/**
4402 * i40e_close - Disables a network interface
4403 * @netdev: network interface device structure
4404 *
4405 * The close entry point is called when an interface is de-activated
4406 * by the OS. The hardware is still under the driver's control, but
4407 * this netdev interface is disabled.
4408 *
4409 * Returns 0, this is not allowed to fail
4410 **/
4411static int i40e_close(struct net_device *netdev)
4412{
4413 struct i40e_netdev_priv *np = netdev_priv(netdev);
4414 struct i40e_vsi *vsi = np->vsi;
4415
90ef8d47 4416 i40e_vsi_close(vsi);
41c445ff
JB		 4417
4418 return 0;
4419}
4420
4421/**
4422 * i40e_do_reset - Start a PF or Core Reset sequence
4423 * @pf: board private structure
4424 * @reset_flags: which reset is requested
4425 *
4426 * The essential difference in resets is that the PF Reset
4427 * doesn't clear the packet buffers, doesn't reset the PE
4428 * firmware, and doesn't bother the other PFs on the chip.
4429 **/
4430void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4431{
4432 u32 val;
4433
4434 WARN_ON(in_interrupt());
4435
263fc48f
MW		 4436 if (i40e_check_asq_alive(&pf->hw))
4437 i40e_vc_notify_reset(pf);
4438
41c445ff
JB		 4439 /* do the biggest reset indicated */
4440 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4441
4442 /* Request a Global Reset
4443 *
4444 * This will start the chip's countdown to the actual full
4445 * chip reset event, and a warning interrupt to be sent
4446 * to all PFs, including the requestor. Our handler
4447 * for the warning interrupt will deal with the shutdown
4448 * and recovery of the switch setup.
4449 */
69bfb110 4450 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4451 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4452 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4453 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4454
4455 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4456
4457 /* Request a Core Reset
4458 *
4459 * Same as Global Reset, except does *not* include the MAC/PHY
4460 */
69bfb110 4461 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4462 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4463 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4464 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4465 i40e_flush(&pf->hw);
4466
7823fe34
SN		 4467 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4468
4469 /* Request a Firmware Reset
4470 *
4471 * Same as Global reset, plus restarting the
4472 * embedded firmware engine.
4473 */
4474 /* enable EMP Reset */
4475 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4476 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4477 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4478
4479 /* force the reset */
4480 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4481 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4482 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4483 i40e_flush(&pf->hw);
4484
41c445ff
JB		 4485 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4486
4487 /* Request a PF Reset
4488 *
4489 * Resets only the PF-specific registers
4490 *
4491 * This goes directly to the tear-down and rebuild of
4492 * the switch, since we need to do all the recovery as
4493 * for the Core Reset.
4494 */
69bfb110 4495 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4496 i40e_handle_reset_warning(pf);
4497
4498 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4499 int v;
4500
4501 /* Find the VSI(s) that requested a re-init */
4502 dev_info(&pf->pdev->dev,
4503 "VSI reinit requested\n");
4504 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4505 struct i40e_vsi *vsi = pf->vsi[v];
4506 if (vsi != NULL &&
4507 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4508 i40e_vsi_reinit_locked(pf->vsi[v]);
4509 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4510 }
4511 }
4512
4513 /* no further action needed, so return now */
4514 return;
4515 } else {
4516 dev_info(&pf->pdev->dev,
4517 "bad reset request 0x%08x\n", reset_flags);
4518 return;
4519 }
4520}
4521
4e3b35b0
NP		 4522#ifdef CONFIG_I40E_DCB
4523/**
4524 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4525 * @pf: board private structure
4526 * @old_cfg: current DCB config
4527 * @new_cfg: new DCB config
4528 **/
4529bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4530 struct i40e_dcbx_config *old_cfg,
4531 struct i40e_dcbx_config *new_cfg)
4532{
4533 bool need_reconfig = false;
4534
4535 /* Check if ETS configuration has changed */
4536 if (memcmp(&new_cfg->etscfg,
4537 &old_cfg->etscfg,
4538 sizeof(new_cfg->etscfg))) {
4539 /* If Priority Table has changed reconfig is needed */
4540 if (memcmp(&new_cfg->etscfg.prioritytable,
4541 &old_cfg->etscfg.prioritytable,
4542 sizeof(new_cfg->etscfg.prioritytable))) {
4543 need_reconfig = true;
69bfb110 4544 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4545 }
4546
4547 if (memcmp(&new_cfg->etscfg.tcbwtable,
4548 &old_cfg->etscfg.tcbwtable,
4549 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4550 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4551
4552 if (memcmp(&new_cfg->etscfg.tsatable,
4553 &old_cfg->etscfg.tsatable,
4554 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4555 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4556 }
4557
4558 /* Check if PFC configuration has changed */
4559 if (memcmp(&new_cfg->pfc,
4560 &old_cfg->pfc,
4561 sizeof(new_cfg->pfc))) {
4562 need_reconfig = true;
69bfb110 4563 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4564 }
4565
4566 /* Check if APP Table has changed */
4567 if (memcmp(&new_cfg->app,
4568 &old_cfg->app,
3d9667a9 4569 sizeof(new_cfg->app))) {
4e3b35b0 4570 need_reconfig = true;
69bfb110 4571 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4572 }
4e3b35b0
NP		 4573
4574 return need_reconfig;
4575}
4576
4577/**
4578 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4579 * @pf: board private structure
4580 * @e: event info posted on ARQ
4581 **/
4582static int i40e_handle_lldp_event(struct i40e_pf *pf,
4583 struct i40e_arq_event_info *e)
4584{
4585 struct i40e_aqc_lldp_get_mib *mib =
4586 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4587 struct i40e_hw *hw = &pf->hw;
4588 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4589 struct i40e_dcbx_config tmp_dcbx_cfg;
4590 bool need_reconfig = false;
4591 int ret = 0;
4592 u8 type;
4593
4594 /* Ignore if event is not for Nearest Bridge */
4595 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4596 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4597 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4598 return ret;
4599
4600 /* Check MIB Type and return if event for Remote MIB update */
4601 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4602 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4603 /* Update the remote cached instance and return */
4604 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4605 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4606 &hw->remote_dcbx_config);
4607 goto exit;
4608 }
4609
4610 /* Convert/store the DCBX data from LLDPDU temporarily */
4611 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4612 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4613 if (ret) {
4614 /* Error in LLDPDU parsing return */
4615 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4616 goto exit;
4617 }
4618
4619 /* No change detected in DCBX configs */
4620 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4621 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4622 goto exit;
4623 }
4624
4625 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4626
4627 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4628
4629 /* Overwrite the new configuration */
4630 *dcbx_cfg = tmp_dcbx_cfg;
4631
4632 if (!need_reconfig)
4633 goto exit;
4634
4635 /* Reconfiguration needed quiesce all VSIs */
4636 i40e_pf_quiesce_all_vsi(pf);
4637
4638 /* Changes in configuration update VEB/VSI */
4639 i40e_dcb_reconfigure(pf);
4640
4641 i40e_pf_unquiesce_all_vsi(pf);
4642exit:
4643 return ret;
4644}
4645#endif /* CONFIG_I40E_DCB */
4646
23326186
ASJ		 4647/**
4648 * i40e_do_reset_safe - Protected reset path for userland calls.
4649 * @pf: board private structure
4650 * @reset_flags: which reset is requested
4651 *
4652 **/
4653void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4654{
4655 rtnl_lock();
4656 i40e_do_reset(pf, reset_flags);
4657 rtnl_unlock();
4658}
4659
41c445ff
JB		 4660/**
4661 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4662 * @pf: board private structure
4663 * @e: event info posted on ARQ
4664 *
4665 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4666 * and VF queues
4667 **/
4668static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4669 struct i40e_arq_event_info *e)
4670{
4671 struct i40e_aqc_lan_overflow *data =
4672 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4673 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4674 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4675 struct i40e_hw *hw = &pf->hw;
4676 struct i40e_vf *vf;
4677 u16 vf_id;
4678
69bfb110
JB		 4679 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4680 queue, qtx_ctl);
41c445ff
JB		 4681
4682 /* Queue belongs to VF, find the VF and issue VF reset */
4683 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4684 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4685 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4686 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4687 vf_id -= hw->func_caps.vf_base_id;
4688 vf = &pf->vf[vf_id];
4689 i40e_vc_notify_vf_reset(vf);
4690 /* Allow VF to process pending reset notification */
4691 msleep(20);
4692 i40e_reset_vf(vf, false);
4693 }
4694}
4695
4696/**
4697 * i40e_service_event_complete - Finish up the service event
4698 * @pf: board private structure
4699 **/
4700static void i40e_service_event_complete(struct i40e_pf *pf)
4701{
4702 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4703
4704 /* flush memory to make sure state is correct before next watchog */
4705 smp_mb__before_clear_bit();
4706 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4707}
4708
55a5e60b
ASJ		 4709/**
4710 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4711 * @pf: board private structure
4712 **/
4713int i40e_get_current_fd_count(struct i40e_pf *pf)
4714{
4715 int val, fcnt_prog;
4716 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4717 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4718 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4719 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4720 return fcnt_prog;
4721}
4722
4723/**
4724 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4725 * @pf: board private structure
4726 **/
4727void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4728{
4729 u32 fcnt_prog, fcnt_avail;
4730
4731 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4732 * to re-enable
4733 */
4734 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4735 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4736 return;
4737 fcnt_prog = i40e_get_current_fd_count(pf);
89132783 4738 fcnt_avail = i40e_get_fd_cnt_all(pf);
55a5e60b
ASJ		 4739 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4740 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4741 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4742 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4743 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4744 }
4745 }
4746 /* Wait for some more space to be available to turn on ATR */
4747 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4748 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4749 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4750 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4751 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4752 }
4753 }
4754}
4755
41c445ff
JB		 4756/**
4757 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4758 * @pf: board private structure
4759 **/
4760static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4761{
4762 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4763 return;
4764
41c445ff
JB		 4765 /* if interface is down do nothing */
4766 if (test_bit(__I40E_DOWN, &pf->state))
4767 return;
55a5e60b
ASJ		 4768 i40e_fdir_check_and_reenable(pf);
4769
4770 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4771 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4772 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4773}
4774
4775/**
4776 * i40e_vsi_link_event - notify VSI of a link event
4777 * @vsi: vsi to be notified
4778 * @link_up: link up or down
4779 **/
4780static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4781{
4782 if (!vsi)
4783 return;
4784
4785 switch (vsi->type) {
4786 case I40E_VSI_MAIN:
4787 if (!vsi->netdev || !vsi->netdev_registered)
4788 break;
4789
4790 if (link_up) {
4791 netif_carrier_on(vsi->netdev);
4792 netif_tx_wake_all_queues(vsi->netdev);
4793 } else {
4794 netif_carrier_off(vsi->netdev);
4795 netif_tx_stop_all_queues(vsi->netdev);
4796 }
4797 break;
4798
4799 case I40E_VSI_SRIOV:
4800 break;
4801
4802 case I40E_VSI_VMDQ2:
4803 case I40E_VSI_CTRL:
4804 case I40E_VSI_MIRROR:
4805 default:
4806 /* there is no notification for other VSIs */
4807 break;
4808 }
4809}
4810
4811/**
4812 * i40e_veb_link_event - notify elements on the veb of a link event
4813 * @veb: veb to be notified
4814 * @link_up: link up or down
4815 **/
4816static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4817{
4818 struct i40e_pf *pf;
4819 int i;
4820
4821 if (!veb || !veb->pf)
4822 return;
4823 pf = veb->pf;
4824
4825 /* depth first... */
4826 for (i = 0; i < I40E_MAX_VEB; i++)
4827 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4828 i40e_veb_link_event(pf->veb[i], link_up);
4829
4830 /* ... now the local VSIs */
4831 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4832 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4833 i40e_vsi_link_event(pf->vsi[i], link_up);
4834}
4835
4836/**
4837 * i40e_link_event - Update netif_carrier status
4838 * @pf: board private structure
4839 **/
4840static void i40e_link_event(struct i40e_pf *pf)
4841{
4842 bool new_link, old_link;
4843
4844 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4845 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4846
4847 if (new_link == old_link)
4848 return;
4849
6d779b41
AS		 4850 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4851 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4852 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4853
4854 /* Notify the base of the switch tree connected to
4855 * the link. Floating VEBs are not notified.
4856 */
4857 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4858 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4859 else
4860 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4861
4862 if (pf->vf)
4863 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4864
4865 if (pf->flags & I40E_FLAG_PTP)
4866 i40e_ptp_set_increment(pf);
41c445ff
JB		 4867}
4868
4869/**
4870 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4871 * @pf: board private structure
4872 *
4873 * Set the per-queue flags to request a check for stuck queues in the irq
4874 * clean functions, then force interrupts to be sure the irq clean is called.
4875 **/
4876static void i40e_check_hang_subtask(struct i40e_pf *pf)
4877{
4878 int i, v;
4879
4880 /* If we're down or resetting, just bail */
4881 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4882 return;
4883
4884 /* for each VSI/netdev
4885 * for each Tx queue
4886 * set the check flag
4887 * for each q_vector
4888 * force an interrupt
4889 */
4890 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4891 struct i40e_vsi *vsi = pf->vsi[v];
4892 int armed = 0;
4893
4894 if (!pf->vsi[v] ||
4895 test_bit(__I40E_DOWN, &vsi->state) ||
4896 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4897 continue;
4898
4899 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4900 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4901 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4902 &vsi->tx_rings[i]->state))
41c445ff
JB		 4903 armed++;
4904 }
4905
4906 if (armed) {
4907 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4908 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4909 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4910 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4911 } else {
4912 u16 vec = vsi->base_vector - 1;
4913 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4914 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4915 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4916 wr32(&vsi->back->hw,
4917 I40E_PFINT_DYN_CTLN(vec), val);
4918 }
4919 i40e_flush(&vsi->back->hw);
4920 }
4921 }
4922}
4923
4924/**
4925 * i40e_watchdog_subtask - Check and bring link up
4926 * @pf: board private structure
4927 **/
4928static void i40e_watchdog_subtask(struct i40e_pf *pf)
4929{
4930 int i;
4931
4932 /* if interface is down do nothing */
4933 if (test_bit(__I40E_DOWN, &pf->state) ||
4934 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4935 return;
4936
4937 /* Update the stats for active netdevs so the network stack
4938 * can look at updated numbers whenever it cares to
4939 */
4940 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4941 if (pf->vsi[i] && pf->vsi[i]->netdev)
4942 i40e_update_stats(pf->vsi[i]);
4943
4944 /* Update the stats for the active switching components */
4945 for (i = 0; i < I40E_MAX_VEB; i++)
4946 if (pf->veb[i])
4947 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4948
4949 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4950}
4951
4952/**
4953 * i40e_reset_subtask - Set up for resetting the device and driver
4954 * @pf: board private structure
4955 **/
4956static void i40e_reset_subtask(struct i40e_pf *pf)
4957{
4958 u32 reset_flags = 0;
4959
23326186 4960 rtnl_lock();
41c445ff
JB		 4961 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4962 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4963 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4964 }
4965 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4966 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4967 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4968 }
4969 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4970 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4971 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4972 }
4973 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4974 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4975 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4976 }
4977
4978 /* If there's a recovery already waiting, it takes
4979 * precedence before starting a new reset sequence.
4980 */
4981 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4982 i40e_handle_reset_warning(pf);
23326186 4983 goto unlock;
41c445ff
JB		 4984 }
4985
4986 /* If we're already down or resetting, just bail */
4987 if (reset_flags &&
4988 !test_bit(__I40E_DOWN, &pf->state) &&
4989 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4990 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4991
4992unlock:
4993 rtnl_unlock();
41c445ff
JB		 4994}
4995
4996/**
4997 * i40e_handle_link_event - Handle link event
4998 * @pf: board private structure
4999 * @e: event info posted on ARQ
5000 **/
5001static void i40e_handle_link_event(struct i40e_pf *pf,
5002 struct i40e_arq_event_info *e)
5003{
5004 struct i40e_hw *hw = &pf->hw;
5005 struct i40e_aqc_get_link_status *status =
5006 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5007 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5008
5009 /* save off old link status information */
5010 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5011 sizeof(pf->hw.phy.link_info_old));
5012
5013 /* update link status */
5014 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5015 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5016 hw_link_info->link_info = status->link_info;
5017 hw_link_info->an_info = status->an_info;
5018 hw_link_info->ext_info = status->ext_info;
5019 hw_link_info->lse_enable =
5020 le16_to_cpu(status->command_flags) &
5021 I40E_AQ_LSE_ENABLE;
5022
5023 /* process the event */
5024 i40e_link_event(pf);
5025
5026 /* Do a new status request to re-enable LSE reporting
5027 * and load new status information into the hw struct,
5028 * then see if the status changed while processing the
5029 * initial event.
5030 */
5031 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5032 i40e_link_event(pf);
5033}
5034
5035/**
5036 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5037 * @pf: board private structure
5038 **/
5039static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5040{
5041 struct i40e_arq_event_info event;
5042 struct i40e_hw *hw = &pf->hw;
5043 u16 pending, i = 0;
5044 i40e_status ret;
5045 u16 opcode;
5046 u32 val;
5047
5048 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5049 return;
5050
3197ce22 5051 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5052 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5053 if (!event.msg_buf)
5054 return;
5055
5056 do {
2f019123 5057 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5058 ret = i40e_clean_arq_element(hw, &event, &pending);
5059 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5060 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5061 break;
5062 } else if (ret) {
5063 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5064 break;
5065 }
5066
5067 opcode = le16_to_cpu(event.desc.opcode);
5068 switch (opcode) {
5069
5070 case i40e_aqc_opc_get_link_status:
5071 i40e_handle_link_event(pf, &event);
5072 break;
5073 case i40e_aqc_opc_send_msg_to_pf:
5074 ret = i40e_vc_process_vf_msg(pf,
5075 le16_to_cpu(event.desc.retval),
5076 le32_to_cpu(event.desc.cookie_high),
5077 le32_to_cpu(event.desc.cookie_low),
5078 event.msg_buf,
5079 event.msg_size);
5080 break;
5081 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5082 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5083#ifdef CONFIG_I40E_DCB
5084 rtnl_lock();
5085 ret = i40e_handle_lldp_event(pf, &event);
5086 rtnl_unlock();
5087#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5088 break;
5089 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5090 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5091 i40e_handle_lan_overflow_event(pf, &event);
5092 break;
0467bc91
SN		 5093 case i40e_aqc_opc_send_msg_to_peer:
5094 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5095 break;
41c445ff
JB		 5096 default:
5097 dev_info(&pf->pdev->dev,
0467bc91
SN		 5098 "ARQ Error: Unknown event 0x%04x received\n",
5099 opcode);
41c445ff
JB		 5100 break;
5101 }
5102 } while (pending && (i++ < pf->adminq_work_limit));
5103
5104 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5105 /* re-enable Admin queue interrupt cause */
5106 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5107 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5108 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5109 i40e_flush(hw);
5110
5111 kfree(event.msg_buf);
5112}
5113
4eb3f768
SN		 5114/**
5115 * i40e_verify_eeprom - make sure eeprom is good to use
5116 * @pf: board private structure
5117 **/
5118static void i40e_verify_eeprom(struct i40e_pf *pf)
5119{
5120 int err;
5121
5122 err = i40e_diag_eeprom_test(&pf->hw);
5123 if (err) {
5124 /* retry in case of garbage read */
5125 err = i40e_diag_eeprom_test(&pf->hw);
5126 if (err) {
5127 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5128 err);
5129 set_bit(__I40E_BAD_EEPROM, &pf->state);
5130 }
5131 }
5132
5133 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5134 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5135 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5136 }
5137}
5138
41c445ff
JB		 5139/**
5140 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5141 * @veb: pointer to the VEB instance
5142 *
5143 * This is a recursive function that first builds the attached VSIs then
5144 * recurses in to build the next layer of VEB. We track the connections
5145 * through our own index numbers because the seid's from the HW could
5146 * change across the reset.
5147 **/
5148static int i40e_reconstitute_veb(struct i40e_veb *veb)
5149{
5150 struct i40e_vsi *ctl_vsi = NULL;
5151 struct i40e_pf *pf = veb->pf;
5152 int v, veb_idx;
5153 int ret;
5154
5155 /* build VSI that owns this VEB, temporarily attached to base VEB */
5156 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5157 if (pf->vsi[v] &&
5158 pf->vsi[v]->veb_idx == veb->idx &&
5159 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5160 ctl_vsi = pf->vsi[v];
5161 break;
5162 }
5163 }
5164 if (!ctl_vsi) {
5165 dev_info(&pf->pdev->dev,
5166 "missing owner VSI for veb_idx %d\n", veb->idx);
5167 ret = -ENOENT;
5168 goto end_reconstitute;
5169 }
5170 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5171 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5172 ret = i40e_add_vsi(ctl_vsi);
5173 if (ret) {
5174 dev_info(&pf->pdev->dev,
5175 "rebuild of owner VSI failed: %d\n", ret);
5176 goto end_reconstitute;
5177 }
5178 i40e_vsi_reset_stats(ctl_vsi);
5179
5180 /* create the VEB in the switch and move the VSI onto the VEB */
5181 ret = i40e_add_veb(veb, ctl_vsi);
5182 if (ret)
5183 goto end_reconstitute;
5184
5185 /* create the remaining VSIs attached to this VEB */
5186 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5187 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5188 continue;
5189
5190 if (pf->vsi[v]->veb_idx == veb->idx) {
5191 struct i40e_vsi *vsi = pf->vsi[v];
5192 vsi->uplink_seid = veb->seid;
5193 ret = i40e_add_vsi(vsi);
5194 if (ret) {
5195 dev_info(&pf->pdev->dev,
5196 "rebuild of vsi_idx %d failed: %d\n",
5197 v, ret);
5198 goto end_reconstitute;
5199 }
5200 i40e_vsi_reset_stats(vsi);
5201 }
5202 }
5203
5204 /* create any VEBs attached to this VEB - RECURSION */
5205 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5206 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5207 pf->veb[veb_idx]->uplink_seid = veb->seid;
5208 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5209 if (ret)
5210 break;
5211 }
5212 }
5213
5214end_reconstitute:
5215 return ret;
5216}
5217
5218/**
5219 * i40e_get_capabilities - get info about the HW
5220 * @pf: the PF struct
5221 **/
5222static int i40e_get_capabilities(struct i40e_pf *pf)
5223{
5224 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5225 u16 data_size;
5226 int buf_len;
5227 int err;
5228
5229 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5230 do {
5231 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5232 if (!cap_buf)
5233 return -ENOMEM;
5234
5235 /* this loads the data into the hw struct for us */
5236 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5237 &data_size,
5238 i40e_aqc_opc_list_func_capabilities,
5239 NULL);
5240 /* data loaded, buffer no longer needed */
5241 kfree(cap_buf);
5242
5243 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5244 /* retry with a larger buffer */
5245 buf_len = data_size;
5246 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5247 dev_info(&pf->pdev->dev,
5248 "capability discovery failed: aq=%d\n",
5249 pf->hw.aq.asq_last_status);
5250 return -ENODEV;
5251 }
5252 } while (err);
5253
ac71b7ba
ASJ		 5254 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5255 (pf->hw.aq.fw_maj_ver < 2)) {
5256 pf->hw.func_caps.num_msix_vectors++;
5257 pf->hw.func_caps.num_msix_vectors_vf++;
5258 }
5259
41c445ff
JB		 5260 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5261 dev_info(&pf->pdev->dev,
5262 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5263 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5264 pf->hw.func_caps.num_msix_vectors,
5265 pf->hw.func_caps.num_msix_vectors_vf,
5266 pf->hw.func_caps.fd_filters_guaranteed,
5267 pf->hw.func_caps.fd_filters_best_effort,
5268 pf->hw.func_caps.num_tx_qp,
5269 pf->hw.func_caps.num_vsis);
5270
7134f9ce
JB		 5271#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5272 + pf->hw.func_caps.num_vfs)
5273 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5274 dev_info(&pf->pdev->dev,
5275 "got num_vsis %d, setting num_vsis to %d\n",
5276 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5277 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5278 }
5279
41c445ff
JB		 5280 return 0;
5281}
5282
cbf61325
ASJ		 5283static int i40e_vsi_clear(struct i40e_vsi *vsi);
5284
41c445ff 5285/**
cbf61325 5286 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5287 * @pf: board private structure
5288 **/
cbf61325 5289static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5290{
5291 struct i40e_vsi *vsi;
8a9eb7d3 5292 int i;
41c445ff 5293
cbf61325 5294 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5295 return;
5296
cbf61325 5297 /* find existing VSI and see if it needs configuring */
41c445ff 5298 vsi = NULL;
cbf61325
ASJ		 5299 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5300 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5301 vsi = pf->vsi[i];
cbf61325
ASJ		 5302 break;
5303 }
5304 }
5305
5306 /* create a new VSI if none exists */
41c445ff 5307 if (!vsi) {
cbf61325
ASJ		 5308 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5309 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5310 if (!vsi) {
5311 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5312 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5313 return;
41c445ff 5314 }
41c445ff 5315 }
cbf61325 5316
8a9eb7d3 5317 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5318}
5319
5320/**
5321 * i40e_fdir_teardown - release the Flow Director resources
5322 * @pf: board private structure
5323 **/
5324static void i40e_fdir_teardown(struct i40e_pf *pf)
5325{
5326 int i;
5327
17a73f6b 5328 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5329 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5330 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5331 i40e_vsi_release(pf->vsi[i]);
5332 break;
5333 }
5334 }
5335}
5336
5337/**
f650a38b 5338 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5339 * @pf: board private structure
5340 *
f650a38b
ASJ		 5341 * Close up the VFs and other things in prep for pf Reset.
5342 **/
5343static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5344{
41c445ff
JB		 5345 struct i40e_hw *hw = &pf->hw;
5346 i40e_status ret;
5347 u32 v;
5348
5349 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5350 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5351 return 0;
41c445ff 5352
69bfb110 5353 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5354
41c445ff
JB		 5355 /* quiesce the VSIs and their queues that are not already DOWN */
5356 i40e_pf_quiesce_all_vsi(pf);
5357
5358 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5359 if (pf->vsi[v])
5360 pf->vsi[v]->seid = 0;
5361 }
5362
5363 i40e_shutdown_adminq(&pf->hw);
5364
f650a38b
ASJ		 5365 /* call shutdown HMC */
5366 ret = i40e_shutdown_lan_hmc(hw);
5367 if (ret) {
5368 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5369 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5370 }
5371 return ret;
5372}
5373
44033fac
JB		 5374/**
5375 * i40e_send_version - update firmware with driver version
5376 * @pf: PF struct
5377 */
5378static void i40e_send_version(struct i40e_pf *pf)
5379{
5380 struct i40e_driver_version dv;
5381
5382 dv.major_version = DRV_VERSION_MAJOR;
5383 dv.minor_version = DRV_VERSION_MINOR;
5384 dv.build_version = DRV_VERSION_BUILD;
5385 dv.subbuild_version = 0;
5386 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5387 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5388}
5389
f650a38b 5390/**
4dda12e6 5391 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5392 * @pf: board private structure
bc7d338f 5393 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5394 **/
bc7d338f 5395static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5396{
f650a38b
ASJ		 5397 struct i40e_hw *hw = &pf->hw;
5398 i40e_status ret;
5399 u32 v;
5400
41c445ff
JB		 5401 /* Now we wait for GRST to settle out.
5402 * We don't have to delete the VEBs or VSIs from the hw switch
5403 * because the reset will make them disappear.
5404 */
5405 ret = i40e_pf_reset(hw);
b5565400 5406 if (ret) {
41c445ff 5407 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5408 goto end_core_reset;
5409 }
41c445ff
JB		 5410 pf->pfr_count++;
5411
5412 if (test_bit(__I40E_DOWN, &pf->state))
5413 goto end_core_reset;
69bfb110 5414 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5415
5416 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5417 ret = i40e_init_adminq(&pf->hw);
5418 if (ret) {
5419 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5420 goto end_core_reset;
5421 }
5422
4eb3f768
SN		 5423 /* re-verify the eeprom if we just had an EMP reset */
5424 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5425 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5426 i40e_verify_eeprom(pf);
5427 }
5428
41c445ff
JB		 5429 ret = i40e_get_capabilities(pf);
5430 if (ret) {
5431 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5432 ret);
5433 goto end_core_reset;
5434 }
5435
41c445ff
JB		 5436 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5437 hw->func_caps.num_rx_qp,
5438 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5439 if (ret) {
5440 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5441 goto end_core_reset;
5442 }
5443 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5444 if (ret) {
5445 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5446 goto end_core_reset;
5447 }
5448
4e3b35b0
NP		 5449#ifdef CONFIG_I40E_DCB
5450 ret = i40e_init_pf_dcb(pf);
5451 if (ret) {
5452 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5453 goto end_core_reset;
5454 }
5455#endif /* CONFIG_I40E_DCB */
5456
41c445ff 5457 /* do basic switch setup */
bc7d338f 5458 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5459 if (ret)
5460 goto end_core_reset;
5461
5462 /* Rebuild the VSIs and VEBs that existed before reset.
5463 * They are still in our local switch element arrays, so only
5464 * need to rebuild the switch model in the HW.
5465 *
5466 * If there were VEBs but the reconstitution failed, we'll try
5467 * try to recover minimal use by getting the basic PF VSI working.
5468 */
5469 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5470 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5471 /* find the one VEB connected to the MAC, and find orphans */
5472 for (v = 0; v < I40E_MAX_VEB; v++) {
5473 if (!pf->veb[v])
5474 continue;
5475
5476 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5477 pf->veb[v]->uplink_seid == 0) {
5478 ret = i40e_reconstitute_veb(pf->veb[v]);
5479
5480 if (!ret)
5481 continue;
5482
5483 /* If Main VEB failed, we're in deep doodoo,
5484 * so give up rebuilding the switch and set up
5485 * for minimal rebuild of PF VSI.
5486 * If orphan failed, we'll report the error
5487 * but try to keep going.
5488 */
5489 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5490 dev_info(&pf->pdev->dev,
5491 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5492 ret);
5493 pf->vsi[pf->lan_vsi]->uplink_seid
5494 = pf->mac_seid;
5495 break;
5496 } else if (pf->veb[v]->uplink_seid == 0) {
5497 dev_info(&pf->pdev->dev,
5498 "rebuild of orphan VEB failed: %d\n",
5499 ret);
5500 }
5501 }
5502 }
5503 }
5504
5505 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5506 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5507 /* no VEB, so rebuild only the Main VSI */
5508 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5509 if (ret) {
5510 dev_info(&pf->pdev->dev,
5511 "rebuild of Main VSI failed: %d\n", ret);
5512 goto end_core_reset;
5513 }
5514 }
5515
5516 /* reinit the misc interrupt */
5517 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5518 ret = i40e_setup_misc_vector(pf);
5519
5520 /* restart the VSIs that were rebuilt and running before the reset */
5521 i40e_pf_unquiesce_all_vsi(pf);
5522
69f64b2b
MW		 5523 if (pf->num_alloc_vfs) {
5524 for (v = 0; v < pf->num_alloc_vfs; v++)
5525 i40e_reset_vf(&pf->vf[v], true);
5526 }
5527
41c445ff 5528 /* tell the firmware that we're starting */
44033fac 5529 i40e_send_version(pf);
41c445ff 5530
69bfb110 5531 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5532
5533end_core_reset:
5534 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5535}
5536
f650a38b
ASJ		 5537/**
5538 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5539 * @pf: board private structure
5540 *
5541 * Close up the VFs and other things in prep for a Core Reset,
5542 * then get ready to rebuild the world.
5543 **/
5544static void i40e_handle_reset_warning(struct i40e_pf *pf)
5545{
5546 i40e_status ret;
5547
5548 ret = i40e_prep_for_reset(pf);
5549 if (!ret)
bc7d338f 5550 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5551}
5552
41c445ff
JB		 5553/**
5554 * i40e_handle_mdd_event
5555 * @pf: pointer to the pf structure
5556 *
5557 * Called from the MDD irq handler to identify possibly malicious vfs
5558 **/
5559static void i40e_handle_mdd_event(struct i40e_pf *pf)
5560{
5561 struct i40e_hw *hw = &pf->hw;
5562 bool mdd_detected = false;
5563 struct i40e_vf *vf;
5564 u32 reg;
5565 int i;
5566
5567 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5568 return;
5569
5570 /* find what triggered the MDD event */
5571 reg = rd32(hw, I40E_GL_MDET_TX);
5572 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5573 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5574 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5575 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5576 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5577 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5578 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5579 dev_info(&pf->pdev->dev,
f29eaa3d 5580 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5581 event, queue, func);
5582 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5583 mdd_detected = true;
5584 }
5585 reg = rd32(hw, I40E_GL_MDET_RX);
5586 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5587 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5588 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5589 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5590 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5591 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5592 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5593 dev_info(&pf->pdev->dev,
f29eaa3d 5594 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5595 event, queue, func);
5596 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5597 mdd_detected = true;
5598 }
5599
5600 /* see if one of the VFs needs its hand slapped */
5601 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5602 vf = &(pf->vf[i]);
5603 reg = rd32(hw, I40E_VP_MDET_TX(i));
5604 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5605 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5606 vf->num_mdd_events++;
5607 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5608 }
5609
5610 reg = rd32(hw, I40E_VP_MDET_RX(i));
5611 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5612 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5613 vf->num_mdd_events++;
5614 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5615 }
5616
5617 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5618 dev_info(&pf->pdev->dev,
5619 "Too many MDD events on VF %d, disabled\n", i);
5620 dev_info(&pf->pdev->dev,
5621 "Use PF Control I/F to re-enable the VF\n");
5622 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5623 }
5624 }
5625
5626 /* re-enable mdd interrupt cause */
5627 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5628 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5629 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5630 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5631 i40e_flush(hw);
5632}
5633
a1c9a9d9
JK		 5634#ifdef CONFIG_I40E_VXLAN
5635/**
5636 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5637 * @pf: board private structure
5638 **/
5639static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5640{
a1c9a9d9
JK		 5641 struct i40e_hw *hw = &pf->hw;
5642 i40e_status ret;
5643 u8 filter_index;
5644 __be16 port;
5645 int i;
5646
5647 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5648 return;
5649
5650 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5651
5652 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5653 if (pf->pending_vxlan_bitmap & (1 << i)) {
5654 pf->pending_vxlan_bitmap &= ~(1 << i);
5655 port = pf->vxlan_ports[i];
5656 ret = port ?
5657 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5658 I40E_AQC_TUNNEL_TYPE_VXLAN,
5659 &filter_index, NULL)
5660 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5661
5662 if (ret) {
5663 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5664 port ? "adding" : "deleting",
5665 ntohs(port), port ? i : i);
5666
5667 pf->vxlan_ports[i] = 0;
5668 } else {
5669 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5670 port ? "Added" : "Deleted",
5671 ntohs(port), port ? i : filter_index);
5672 }
5673 }
5674 }
5675}
5676
5677#endif
41c445ff
JB		 5678/**
5679 * i40e_service_task - Run the driver's async subtasks
5680 * @work: pointer to work_struct containing our data
5681 **/
5682static void i40e_service_task(struct work_struct *work)
5683{
5684 struct i40e_pf *pf = container_of(work,
5685 struct i40e_pf,
5686 service_task);
5687 unsigned long start_time = jiffies;
5688
5689 i40e_reset_subtask(pf);
5690 i40e_handle_mdd_event(pf);
5691 i40e_vc_process_vflr_event(pf);
5692 i40e_watchdog_subtask(pf);
5693 i40e_fdir_reinit_subtask(pf);
5694 i40e_check_hang_subtask(pf);
5695 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5696#ifdef CONFIG_I40E_VXLAN
5697 i40e_sync_vxlan_filters_subtask(pf);
5698#endif
41c445ff
JB		 5699 i40e_clean_adminq_subtask(pf);
5700
5701 i40e_service_event_complete(pf);
5702
5703 /* If the tasks have taken longer than one timer cycle or there
5704 * is more work to be done, reschedule the service task now
5705 * rather than wait for the timer to tick again.
5706 */
5707 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5708 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5709 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5710 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5711 i40e_service_event_schedule(pf);
5712}
5713
5714/**
5715 * i40e_service_timer - timer callback
5716 * @data: pointer to PF struct
5717 **/
5718static void i40e_service_timer(unsigned long data)
5719{
5720 struct i40e_pf *pf = (struct i40e_pf *)data;
5721
5722 mod_timer(&pf->service_timer,
5723 round_jiffies(jiffies + pf->service_timer_period));
5724 i40e_service_event_schedule(pf);
5725}
5726
5727/**
5728 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5729 * @vsi: the VSI being configured
5730 **/
5731static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5732{
5733 struct i40e_pf *pf = vsi->back;
5734
5735 switch (vsi->type) {
5736 case I40E_VSI_MAIN:
5737 vsi->alloc_queue_pairs = pf->num_lan_qps;
5738 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5739 I40E_REQ_DESCRIPTOR_MULTIPLE);
5740 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5741 vsi->num_q_vectors = pf->num_lan_msix;
5742 else
5743 vsi->num_q_vectors = 1;
5744
5745 break;
5746
5747 case I40E_VSI_FDIR:
5748 vsi->alloc_queue_pairs = 1;
5749 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5750 I40E_REQ_DESCRIPTOR_MULTIPLE);
5751 vsi->num_q_vectors = 1;
5752 break;
5753
5754 case I40E_VSI_VMDQ2:
5755 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5756 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5757 I40E_REQ_DESCRIPTOR_MULTIPLE);
5758 vsi->num_q_vectors = pf->num_vmdq_msix;
5759 break;
5760
5761 case I40E_VSI_SRIOV:
5762 vsi->alloc_queue_pairs = pf->num_vf_qps;
5763 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5764 I40E_REQ_DESCRIPTOR_MULTIPLE);
5765 break;
5766
5767 default:
5768 WARN_ON(1);
5769 return -ENODATA;
5770 }
5771
5772 return 0;
5773}
5774
f650a38b
ASJ		 5775/**
5776 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5777 * @type: VSI pointer
bc7d338f 5778 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5779 *
5780 * On error: returns error code (negative)
5781 * On success: returns 0
5782 **/
bc7d338f 5783static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5784{
5785 int size;
5786 int ret = 0;
5787
ac6c5e3d 5788 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5789 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5790 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5791 if (!vsi->tx_rings)
5792 return -ENOMEM;
f650a38b
ASJ		 5793 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5794
bc7d338f
ASJ		 5795 if (alloc_qvectors) {
5796 /* allocate memory for q_vector pointers */
5797 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5798 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5799 if (!vsi->q_vectors) {
5800 ret = -ENOMEM;
5801 goto err_vectors;
5802 }
f650a38b
ASJ		 5803 }
5804 return ret;
5805
5806err_vectors:
5807 kfree(vsi->tx_rings);
5808 return ret;
5809}
5810
41c445ff
JB		 5811/**
5812 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5813 * @pf: board private structure
5814 * @type: type of VSI
5815 *
5816 * On error: returns error code (negative)
5817 * On success: returns vsi index in PF (positive)
5818 **/
5819static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5820{
5821 int ret = -ENODEV;
5822 struct i40e_vsi *vsi;
5823 int vsi_idx;
5824 int i;
5825
5826 /* Need to protect the allocation of the VSIs at the PF level */
5827 mutex_lock(&pf->switch_mutex);
5828
5829 /* VSI list may be fragmented if VSI creation/destruction has
5830 * been happening. We can afford to do a quick scan to look
5831 * for any free VSIs in the list.
5832 *
5833 * find next empty vsi slot, looping back around if necessary
5834 */
5835 i = pf->next_vsi;
5836 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5837 i++;
5838 if (i >= pf->hw.func_caps.num_vsis) {
5839 i = 0;
5840 while (i < pf->next_vsi && pf->vsi[i])
5841 i++;
5842 }
5843
5844 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5845 vsi_idx = i; /* Found one! */
5846 } else {
5847 ret = -ENODEV;
493fb300 5848 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5849 }
5850 pf->next_vsi = ++i;
5851
5852 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5853 if (!vsi) {
5854 ret = -ENOMEM;
493fb300 5855 goto unlock_pf;
41c445ff
JB		 5856 }
5857 vsi->type = type;
5858 vsi->back = pf;
5859 set_bit(__I40E_DOWN, &vsi->state);
5860 vsi->flags = 0;
5861 vsi->idx = vsi_idx;
5862 vsi->rx_itr_setting = pf->rx_itr_default;
5863 vsi->tx_itr_setting = pf->tx_itr_default;
5864 vsi->netdev_registered = false;
5865 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5866 INIT_LIST_HEAD(&vsi->mac_filter_list);
5867
9f65e15b
AD		 5868 ret = i40e_set_num_rings_in_vsi(vsi);
5869 if (ret)
5870 goto err_rings;
5871
bc7d338f 5872 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5873 if (ret)
9f65e15b 5874 goto err_rings;
493fb300 5875
41c445ff
JB		 5876 /* Setup default MSIX irq handler for VSI */
5877 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5878
5879 pf->vsi[vsi_idx] = vsi;
5880 ret = vsi_idx;
493fb300
AD		 5881 goto unlock_pf;
5882
9f65e15b 5883err_rings:
493fb300
AD		 5884 pf->next_vsi = i - 1;
5885 kfree(vsi);
5886unlock_pf:
41c445ff
JB		 5887 mutex_unlock(&pf->switch_mutex);
5888 return ret;
5889}
5890
f650a38b
ASJ		 5891/**
5892 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5893 * @type: VSI pointer
bc7d338f 5894 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5895 *
5896 * On error: returns error code (negative)
5897 * On success: returns 0
5898 **/
bc7d338f 5899static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5900{
5901 /* free the ring and vector containers */
bc7d338f
ASJ		 5902 if (free_qvectors) {
5903 kfree(vsi->q_vectors);
5904 vsi->q_vectors = NULL;
5905 }
f650a38b
ASJ		 5906 kfree(vsi->tx_rings);
5907 vsi->tx_rings = NULL;
5908 vsi->rx_rings = NULL;
5909}
5910
41c445ff
JB		 5911/**
5912 * i40e_vsi_clear - Deallocate the VSI provided
5913 * @vsi: the VSI being un-configured
5914 **/
5915static int i40e_vsi_clear(struct i40e_vsi *vsi)
5916{
5917 struct i40e_pf *pf;
5918
5919 if (!vsi)
5920 return 0;
5921
5922 if (!vsi->back)
5923 goto free_vsi;
5924 pf = vsi->back;
5925
5926 mutex_lock(&pf->switch_mutex);
5927 if (!pf->vsi[vsi->idx]) {
5928 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5929 vsi->idx, vsi->idx, vsi, vsi->type);
5930 goto unlock_vsi;
5931 }
5932
5933 if (pf->vsi[vsi->idx] != vsi) {
5934 dev_err(&pf->pdev->dev,
5935 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5936 pf->vsi[vsi->idx]->idx,
5937 pf->vsi[vsi->idx],
5938 pf->vsi[vsi->idx]->type,
5939 vsi->idx, vsi, vsi->type);
5940 goto unlock_vsi;
5941 }
5942
5943 /* updates the pf for this cleared vsi */
5944 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5945 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5946
bc7d338f 5947 i40e_vsi_free_arrays(vsi, true);
493fb300 5948
41c445ff
JB		 5949 pf->vsi[vsi->idx] = NULL;
5950 if (vsi->idx < pf->next_vsi)
5951 pf->next_vsi = vsi->idx;
5952
5953unlock_vsi:
5954 mutex_unlock(&pf->switch_mutex);
5955free_vsi:
5956 kfree(vsi);
5957
5958 return 0;
5959}
5960
9f65e15b
AD		 5961/**
5962 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5963 * @vsi: the VSI being cleaned
5964 **/
be1d5eea 5965static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5966{
5967 int i;
5968
8e9dca53 5969 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5970 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5971 kfree_rcu(vsi->tx_rings[i], rcu);
5972 vsi->tx_rings[i] = NULL;
5973 vsi->rx_rings[i] = NULL;
5974 }
be1d5eea 5975 }
9f65e15b
AD		 5976}
5977
41c445ff
JB		 5978/**
5979 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5980 * @vsi: the VSI being configured
5981 **/
5982static int i40e_alloc_rings(struct i40e_vsi *vsi)
5983{
e7046ee1 5984 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 5985 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5986 int i;
5987
41c445ff 5988 /* Set basic values in the rings to be used later during open() */
d7397644 5989 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 5990 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5991 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5992 if (!tx_ring)
5993 goto err_out;
41c445ff
JB		 5994
5995 tx_ring->queue_index = i;
5996 tx_ring->reg_idx = vsi->base_queue + i;
5997 tx_ring->ring_active = false;
5998 tx_ring->vsi = vsi;
5999 tx_ring->netdev = vsi->netdev;
6000 tx_ring->dev = &pf->pdev->dev;
6001 tx_ring->count = vsi->num_desc;
6002 tx_ring->size = 0;
6003 tx_ring->dcb_tc = 0;
9f65e15b 6004 vsi->tx_rings[i] = tx_ring;
41c445ff 6005
9f65e15b 6006 rx_ring = &tx_ring[1];
41c445ff
JB		 6007 rx_ring->queue_index = i;
6008 rx_ring->reg_idx = vsi->base_queue + i;
6009 rx_ring->ring_active = false;
6010 rx_ring->vsi = vsi;
6011 rx_ring->netdev = vsi->netdev;
6012 rx_ring->dev = &pf->pdev->dev;
6013 rx_ring->count = vsi->num_desc;
6014 rx_ring->size = 0;
6015 rx_ring->dcb_tc = 0;
6016 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6017 set_ring_16byte_desc_enabled(rx_ring);
6018 else
6019 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6020 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6021 }
6022
6023 return 0;
9f65e15b
AD		 6024
6025err_out:
6026 i40e_vsi_clear_rings(vsi);
6027 return -ENOMEM;
41c445ff
JB		 6028}
6029
6030/**
6031 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6032 * @pf: board private structure
6033 * @vectors: the number of MSI-X vectors to request
6034 *
6035 * Returns the number of vectors reserved, or error
6036 **/
6037static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6038{
7b37f376
AG		 6039 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6040 I40E_MIN_MSIX, vectors);
6041 if (vectors < 0) {
41c445ff 6042 dev_info(&pf->pdev->dev,
7b37f376 6043 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6044 vectors = 0;
6045 }
6046
7b37f376
AG		 6047 pf->num_msix_entries = vectors;
6048
41c445ff
JB		 6049 return vectors;
6050}
6051
6052/**
6053 * i40e_init_msix - Setup the MSIX capability
6054 * @pf: board private structure
6055 *
6056 * Work with the OS to set up the MSIX vectors needed.
6057 *
6058 * Returns 0 on success, negative on failure
6059 **/
6060static int i40e_init_msix(struct i40e_pf *pf)
6061{
6062 i40e_status err = 0;
6063 struct i40e_hw *hw = &pf->hw;
6064 int v_budget, i;
6065 int vec;
6066
6067 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6068 return -ENODEV;
6069
6070 /* The number of vectors we'll request will be comprised of:
6071 * - Add 1 for "other" cause for Admin Queue events, etc.
6072 * - The number of LAN queue pairs
f8ff1464
ASJ		 6073 * - Queues being used for RSS.
6074 * We don't need as many as max_rss_size vectors.
6075 * use rss_size instead in the calculation since that
6076 * is governed by number of cpus in the system.
6077 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6078 * - The number of VMDq pairs
6079 * Once we count this up, try the request.
6080 *
6081 * If we can't get what we want, we'll simplify to nearly nothing
6082 * and try again. If that still fails, we punt.
6083 */
f8ff1464 6084 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6085 pf->num_vmdq_msix = pf->num_vmdq_qps;
6086 v_budget = 1 + pf->num_lan_msix;
6087 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6088 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6089 v_budget++;
6090
6091 /* Scale down if necessary, and the rings will share vectors */
6092 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6093
6094 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6095 GFP_KERNEL);
6096 if (!pf->msix_entries)
6097 return -ENOMEM;
6098
6099 for (i = 0; i < v_budget; i++)
6100 pf->msix_entries[i].entry = i;
6101 vec = i40e_reserve_msix_vectors(pf, v_budget);
6102 if (vec < I40E_MIN_MSIX) {
6103 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6104 kfree(pf->msix_entries);
6105 pf->msix_entries = NULL;
6106 return -ENODEV;
6107
6108 } else if (vec == I40E_MIN_MSIX) {
6109 /* Adjust for minimal MSIX use */
77fa28be 6110 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6111 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6112 pf->num_vmdq_vsis = 0;
6113 pf->num_vmdq_qps = 0;
6114 pf->num_vmdq_msix = 0;
6115 pf->num_lan_qps = 1;
6116 pf->num_lan_msix = 1;
6117
6118 } else if (vec != v_budget) {
6119 /* Scale vector usage down */
6120 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6121 vec--; /* reserve the misc vector */
6122
6123 /* partition out the remaining vectors */
6124 switch (vec) {
6125 case 2:
6126 pf->num_vmdq_vsis = 1;
6127 pf->num_lan_msix = 1;
6128 break;
6129 case 3:
6130 pf->num_vmdq_vsis = 1;
6131 pf->num_lan_msix = 2;
6132 break;
6133 default:
6134 pf->num_lan_msix = min_t(int, (vec / 2),
6135 pf->num_lan_qps);
6136 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6137 I40E_DEFAULT_NUM_VMDQ_VSI);
6138 break;
6139 }
6140 }
6141
6142 return err;
6143}
6144
493fb300 6145/**
90e04070 6146 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6147 * @vsi: the VSI being configured
6148 * @v_idx: index of the vector in the vsi struct
6149 *
6150 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6151 **/
90e04070 6152static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6153{
6154 struct i40e_q_vector *q_vector;
6155
6156 /* allocate q_vector */
6157 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6158 if (!q_vector)
6159 return -ENOMEM;
6160
6161 q_vector->vsi = vsi;
6162 q_vector->v_idx = v_idx;
6163 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6164 if (vsi->netdev)
6165 netif_napi_add(vsi->netdev, &q_vector->napi,
6166 i40e_napi_poll, vsi->work_limit);
6167
cd0b6fa6
AD		 6168 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6169 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6170
493fb300
AD		 6171 /* tie q_vector and vsi together */
6172 vsi->q_vectors[v_idx] = q_vector;
6173
6174 return 0;
6175}
6176
41c445ff 6177/**
90e04070 6178 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6179 * @vsi: the VSI being configured
6180 *
6181 * We allocate one q_vector per queue interrupt. If allocation fails we
6182 * return -ENOMEM.
6183 **/
90e04070 6184static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6185{
6186 struct i40e_pf *pf = vsi->back;
6187 int v_idx, num_q_vectors;
493fb300 6188 int err;
41c445ff
JB		 6189
6190 /* if not MSIX, give the one vector only to the LAN VSI */
6191 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6192 num_q_vectors = vsi->num_q_vectors;
6193 else if (vsi == pf->vsi[pf->lan_vsi])
6194 num_q_vectors = 1;
6195 else
6196 return -EINVAL;
6197
41c445ff 6198 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6199 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6200 if (err)
6201 goto err_out;
41c445ff
JB		 6202 }
6203
6204 return 0;
493fb300
AD		 6205
6206err_out:
6207 while (v_idx--)
6208 i40e_free_q_vector(vsi, v_idx);
6209
6210 return err;
41c445ff
JB		 6211}
6212
6213/**
6214 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6215 * @pf: board private structure to initialize
6216 **/
6217static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6218{
6219 int err = 0;
6220
6221 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6222 err = i40e_init_msix(pf);
6223 if (err) {
60ea5f83
JB		 6224 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6225 I40E_FLAG_RSS_ENABLED |
6226 I40E_FLAG_DCB_ENABLED |
6227 I40E_FLAG_SRIOV_ENABLED |
6228 I40E_FLAG_FD_SB_ENABLED |
6229 I40E_FLAG_FD_ATR_ENABLED |
6230 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6231
6232 /* rework the queue expectations without MSIX */
6233 i40e_determine_queue_usage(pf);
6234 }
6235 }
6236
6237 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6238 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6239 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6240 err = pci_enable_msi(pf->pdev);
6241 if (err) {
958a3e3b 6242 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6243 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6244 }
6245 }
6246
958a3e3b 6247 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6248 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6249
41c445ff
JB		 6250 /* track first vector for misc interrupts */
6251 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6252}
6253
6254/**
6255 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6256 * @pf: board private structure
6257 *
6258 * This sets up the handler for MSIX 0, which is used to manage the
6259 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6260 * when in MSI or Legacy interrupt mode.
6261 **/
6262static int i40e_setup_misc_vector(struct i40e_pf *pf)
6263{
6264 struct i40e_hw *hw = &pf->hw;
6265 int err = 0;
6266
6267 /* Only request the irq if this is the first time through, and
6268 * not when we're rebuilding after a Reset
6269 */
6270 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6271 err = request_irq(pf->msix_entries[0].vector,
6272 i40e_intr, 0, pf->misc_int_name, pf);
6273 if (err) {
6274 dev_info(&pf->pdev->dev,
77fa28be
CS		 6275 "request_irq for %s failed: %d\n",
6276 pf->misc_int_name, err);
41c445ff
JB		 6277 return -EFAULT;
6278 }
6279 }
6280
6281 i40e_enable_misc_int_causes(hw);
6282
6283 /* associate no queues to the misc vector */
6284 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6285 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6286
6287 i40e_flush(hw);
6288
6289 i40e_irq_dynamic_enable_icr0(pf);
6290
6291 return err;
6292}
6293
6294/**
6295 * i40e_config_rss - Prepare for RSS if used
6296 * @pf: board private structure
6297 **/
6298static int i40e_config_rss(struct i40e_pf *pf)
6299{
41c445ff
JB		 6300 /* Set of random keys generated using kernel random number generator */
6301 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6302 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6303 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6304 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6305 struct i40e_hw *hw = &pf->hw;
6306 u32 lut = 0;
6307 int i, j;
6308 u64 hena;
41c445ff
JB		 6309
6310 /* Fill out hash function seed */
6311 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6312 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6313
6314 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6315 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6316 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6317 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6318 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6319 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6320
6321 /* Populate the LUT with max no. of queues in round robin fashion */
6322 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6323
6324 /* The assumption is that lan qp count will be the highest
6325 * qp count for any PF VSI that needs RSS.
6326 * If multiple VSIs need RSS support, all the qp counts
6327 * for those VSIs should be a power of 2 for RSS to work.
6328 * If LAN VSI is the only consumer for RSS then this requirement
6329 * is not necessary.
6330 */
6331 if (j == pf->rss_size)
6332 j = 0;
6333 /* lut = 4-byte sliding window of 4 lut entries */
6334 lut = (lut << 8) | (j &
6335 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6336 /* On i = 3, we have 4 entries in lut; write to the register */
6337 if ((i & 3) == 3)
6338 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6339 }
6340 i40e_flush(hw);
6341
6342 return 0;
6343}
6344
f8ff1464
ASJ		 6345/**
6346 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6347 * @pf: board private structure
6348 * @queue_count: the requested queue count for rss.
6349 *
6350 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6351 * count which may be different from the requested queue count.
6352 **/
6353int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6354{
6355 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6356 return 0;
6357
6358 queue_count = min_t(int, queue_count, pf->rss_size_max);
6359 queue_count = rounddown_pow_of_two(queue_count);
6360
6361 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6362 i40e_prep_for_reset(pf);
6363
f8ff1464
ASJ		 6364 pf->rss_size = queue_count;
6365
6366 i40e_reset_and_rebuild(pf, true);
6367 i40e_config_rss(pf);
6368 }
6369 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6370 return pf->rss_size;
6371}
6372
41c445ff
JB		 6373/**
6374 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6375 * @pf: board private structure to initialize
6376 *
6377 * i40e_sw_init initializes the Adapter private data structure.
6378 * Fields are initialized based on PCI device information and
6379 * OS network device settings (MTU size).
6380 **/
6381static int i40e_sw_init(struct i40e_pf *pf)
6382{
6383 int err = 0;
6384 int size;
6385
6386 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6387 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6388 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6389 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6390 if (I40E_DEBUG_USER & debug)
6391 pf->hw.debug_mask = debug;
6392 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6393 I40E_DEFAULT_MSG_ENABLE);
6394 }
6395
6396 /* Set default capability flags */
6397 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6398 I40E_FLAG_MSI_ENABLED |
6399 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6400 I40E_FLAG_RX_1BUF_ENABLED;
6401
ca99eb99
MW		 6402 /* Set default ITR */
6403 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6404 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6405
7134f9ce
JB		 6406 /* Depending on PF configurations, it is possible that the RSS
6407 * maximum might end up larger than the available queues
6408 */
41c445ff 6409 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6410 pf->rss_size_max = min_t(int, pf->rss_size_max,
6411 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6412 if (pf->hw.func_caps.rss) {
6413 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6414 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6415 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6416 } else {
6417 pf->rss_size = 1;
6418 }
6419
2050bc65
CS		 6420 /* MFP mode enabled */
6421 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6422 pf->flags |= I40E_FLAG_MFP_ENABLED;
6423 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6424 }
6425
cbf61325
ASJ		 6426 /* FW/NVM is not yet fixed in this regard */
6427 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6428 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6429 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6430 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6431 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6432 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6433 } else {
6434 dev_info(&pf->pdev->dev,
0b67584f 6435 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6436 }
cbf61325
ASJ		 6437 pf->fdir_pf_filter_count =
6438 pf->hw.func_caps.fd_filters_guaranteed;
6439 pf->hw.fdir_shared_filter_count =
6440 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6441 }
6442
6443 if (pf->hw.func_caps.vmdq) {
6444 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6445 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6446 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6447 }
6448
41c445ff
JB		 6449#ifdef CONFIG_PCI_IOV
6450 if (pf->hw.func_caps.num_vfs) {
6451 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6452 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6453 pf->num_req_vfs = min_t(int,
6454 pf->hw.func_caps.num_vfs,
6455 I40E_MAX_VF_COUNT);
6456 }
6457#endif /* CONFIG_PCI_IOV */
6458 pf->eeprom_version = 0xDEAD;
6459 pf->lan_veb = I40E_NO_VEB;
6460 pf->lan_vsi = I40E_NO_VSI;
6461
6462 /* set up queue assignment tracking */
6463 size = sizeof(struct i40e_lump_tracking)
6464 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6465 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6466 if (!pf->qp_pile) {
6467 err = -ENOMEM;
6468 goto sw_init_done;
6469 }
6470 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6471 pf->qp_pile->search_hint = 0;
6472
6473 /* set up vector assignment tracking */
6474 size = sizeof(struct i40e_lump_tracking)
6475 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6476 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6477 if (!pf->irq_pile) {
6478 kfree(pf->qp_pile);
6479 err = -ENOMEM;
6480 goto sw_init_done;
6481 }
6482 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6483 pf->irq_pile->search_hint = 0;
6484
6485 mutex_init(&pf->switch_mutex);
6486
6487sw_init_done:
6488 return err;
6489}
6490
7c3c288b
ASJ		 6491/**
6492 * i40e_set_ntuple - set the ntuple feature flag and take action
6493 * @pf: board private structure to initialize
6494 * @features: the feature set that the stack is suggesting
6495 *
6496 * returns a bool to indicate if reset needs to happen
6497 **/
6498bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6499{
6500 bool need_reset = false;
6501
6502 /* Check if Flow Director n-tuple support was enabled or disabled. If
6503 * the state changed, we need to reset.
6504 */
6505 if (features & NETIF_F_NTUPLE) {
6506 /* Enable filters and mark for reset */
6507 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6508 need_reset = true;
6509 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6510 } else {
6511 /* turn off filters, mark for reset and clear SW filter list */
6512 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6513 need_reset = true;
6514 i40e_fdir_filter_exit(pf);
6515 }
6516 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6517 /* if ATR was disabled it can be re-enabled. */
6518 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6519 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6520 }
6521 return need_reset;
6522}
6523
41c445ff
JB		 6524/**
6525 * i40e_set_features - set the netdev feature flags
6526 * @netdev: ptr to the netdev being adjusted
6527 * @features: the feature set that the stack is suggesting
6528 **/
6529static int i40e_set_features(struct net_device *netdev,
6530 netdev_features_t features)
6531{
6532 struct i40e_netdev_priv *np = netdev_priv(netdev);
6533 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6534 struct i40e_pf *pf = vsi->back;
6535 bool need_reset;
41c445ff
JB		 6536
6537 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6538 i40e_vlan_stripping_enable(vsi);
6539 else
6540 i40e_vlan_stripping_disable(vsi);
6541
7c3c288b
ASJ		 6542 need_reset = i40e_set_ntuple(pf, features);
6543
6544 if (need_reset)
6545 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6546
41c445ff
JB		 6547 return 0;
6548}
6549
a1c9a9d9
JK		 6550#ifdef CONFIG_I40E_VXLAN
6551/**
6552 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6553 * @pf: board private structure
6554 * @port: The UDP port to look up
6555 *
6556 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6557 **/
6558static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6559{
6560 u8 i;
6561
6562 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6563 if (pf->vxlan_ports[i] == port)
6564 return i;
6565 }
6566
6567 return i;
6568}
6569
6570/**
6571 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6572 * @netdev: This physical port's netdev
6573 * @sa_family: Socket Family that VXLAN is notifying us about
6574 * @port: New UDP port number that VXLAN started listening to
6575 **/
6576static void i40e_add_vxlan_port(struct net_device *netdev,
6577 sa_family_t sa_family, __be16 port)
6578{
6579 struct i40e_netdev_priv *np = netdev_priv(netdev);
6580 struct i40e_vsi *vsi = np->vsi;
6581 struct i40e_pf *pf = vsi->back;
6582 u8 next_idx;
6583 u8 idx;
6584
6585 if (sa_family == AF_INET6)
6586 return;
6587
6588 idx = i40e_get_vxlan_port_idx(pf, port);
6589
6590 /* Check if port already exists */
6591 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6592 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6593 return;
6594 }
6595
6596 /* Now check if there is space to add the new port */
6597 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6598
6599 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6600 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6601 ntohs(port));
6602 return;
6603 }
6604
6605 /* New port: add it and mark its index in the bitmap */
6606 pf->vxlan_ports[next_idx] = port;
6607 pf->pending_vxlan_bitmap |= (1 << next_idx);
6608
6609 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6610}
6611
6612/**
6613 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6614 * @netdev: This physical port's netdev
6615 * @sa_family: Socket Family that VXLAN is notifying us about
6616 * @port: UDP port number that VXLAN stopped listening to
6617 **/
6618static void i40e_del_vxlan_port(struct net_device *netdev,
6619 sa_family_t sa_family, __be16 port)
6620{
6621 struct i40e_netdev_priv *np = netdev_priv(netdev);
6622 struct i40e_vsi *vsi = np->vsi;
6623 struct i40e_pf *pf = vsi->back;
6624 u8 idx;
6625
6626 if (sa_family == AF_INET6)
6627 return;
6628
6629 idx = i40e_get_vxlan_port_idx(pf, port);
6630
6631 /* Check if port already exists */
6632 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6633 /* if port exists, set it to 0 (mark for deletion)
6634 * and make it pending
6635 */
6636 pf->vxlan_ports[idx] = 0;
6637
6638 pf->pending_vxlan_bitmap |= (1 << idx);
6639
6640 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6641 } else {
6642 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6643 ntohs(port));
6644 }
6645}
6646
6647#endif
4ba0dea5
GR		 6648#ifdef HAVE_FDB_OPS
6649#ifdef USE_CONST_DEV_UC_CHAR
6650static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6651 struct net_device *dev,
6652 const unsigned char *addr,
6653 u16 flags)
6654#else
6655static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6656 struct net_device *dev,
6657 unsigned char *addr,
6658 u16 flags)
6659#endif
6660{
6661 struct i40e_netdev_priv *np = netdev_priv(dev);
6662 struct i40e_pf *pf = np->vsi->back;
6663 int err = 0;
6664
6665 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6666 return -EOPNOTSUPP;
6667
6668 /* Hardware does not support aging addresses so if a
6669 * ndm_state is given only allow permanent addresses
6670 */
6671 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6672 netdev_info(dev, "FDB only supports static addresses\n");
6673 return -EINVAL;
6674 }
6675
6676 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6677 err = dev_uc_add_excl(dev, addr);
6678 else if (is_multicast_ether_addr(addr))
6679 err = dev_mc_add_excl(dev, addr);
6680 else
6681 err = -EINVAL;
6682
6683 /* Only return duplicate errors if NLM_F_EXCL is set */
6684 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6685 err = 0;
6686
6687 return err;
6688}
6689
6690#ifndef USE_DEFAULT_FDB_DEL_DUMP
6691#ifdef USE_CONST_DEV_UC_CHAR
6692static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6693 struct net_device *dev,
6694 const unsigned char *addr)
6695#else
6696static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6697 struct net_device *dev,
6698 unsigned char *addr)
6699#endif
6700{
6701 struct i40e_netdev_priv *np = netdev_priv(dev);
6702 struct i40e_pf *pf = np->vsi->back;
6703 int err = -EOPNOTSUPP;
6704
6705 if (ndm->ndm_state & NUD_PERMANENT) {
6706 netdev_info(dev, "FDB only supports static addresses\n");
6707 return -EINVAL;
6708 }
6709
6710 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6711 if (is_unicast_ether_addr(addr))
6712 err = dev_uc_del(dev, addr);
6713 else if (is_multicast_ether_addr(addr))
6714 err = dev_mc_del(dev, addr);
6715 else
6716 err = -EINVAL;
6717 }
6718
6719 return err;
6720}
6721
6722static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6723 struct netlink_callback *cb,
6724 struct net_device *dev,
6725 int idx)
6726{
6727 struct i40e_netdev_priv *np = netdev_priv(dev);
6728 struct i40e_pf *pf = np->vsi->back;
6729
6730 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6731 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6732
6733 return idx;
6734}
6735
6736#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6737#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6738static const struct net_device_ops i40e_netdev_ops = {
6739 .ndo_open = i40e_open,
6740 .ndo_stop = i40e_close,
6741 .ndo_start_xmit = i40e_lan_xmit_frame,
6742 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6743 .ndo_set_rx_mode = i40e_set_rx_mode,
6744 .ndo_validate_addr = eth_validate_addr,
6745 .ndo_set_mac_address = i40e_set_mac,
6746 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6747 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6748 .ndo_tx_timeout = i40e_tx_timeout,
6749 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6750 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6751#ifdef CONFIG_NET_POLL_CONTROLLER
6752 .ndo_poll_controller = i40e_netpoll,
6753#endif
6754 .ndo_setup_tc = i40e_setup_tc,
6755 .ndo_set_features = i40e_set_features,
6756 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6757 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 6758 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 6759 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6760 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6761#ifdef CONFIG_I40E_VXLAN
6762 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6763 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6764#endif
4ba0dea5
GR		 6765#ifdef HAVE_FDB_OPS
6766 .ndo_fdb_add = i40e_ndo_fdb_add,
6767#ifndef USE_DEFAULT_FDB_DEL_DUMP
6768 .ndo_fdb_del = i40e_ndo_fdb_del,
6769 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6770#endif
6771#endif
41c445ff
JB		 6772};
6773
6774/**
6775 * i40e_config_netdev - Setup the netdev flags
6776 * @vsi: the VSI being configured
6777 *
6778 * Returns 0 on success, negative value on failure
6779 **/
6780static int i40e_config_netdev(struct i40e_vsi *vsi)
6781{
1a10370a 6782 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6783 struct i40e_pf *pf = vsi->back;
6784 struct i40e_hw *hw = &pf->hw;
6785 struct i40e_netdev_priv *np;
6786 struct net_device *netdev;
6787 u8 mac_addr[ETH_ALEN];
6788 int etherdev_size;
6789
6790 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6791 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6792 if (!netdev)
6793 return -ENOMEM;
6794
6795 vsi->netdev = netdev;
6796 np = netdev_priv(netdev);
6797 np->vsi = vsi;
6798
d70e941b 6799 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6800 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6801 NETIF_F_TSO;
41c445ff
JB		 6802
6803 netdev->features = NETIF_F_SG |
6804 NETIF_F_IP_CSUM |
6805 NETIF_F_SCTP_CSUM |
6806 NETIF_F_HIGHDMA |
6807 NETIF_F_GSO_UDP_TUNNEL |
6808 NETIF_F_HW_VLAN_CTAG_TX |
6809 NETIF_F_HW_VLAN_CTAG_RX |
6810 NETIF_F_HW_VLAN_CTAG_FILTER |
6811 NETIF_F_IPV6_CSUM |
6812 NETIF_F_TSO |
059dab69 6813 NETIF_F_TSO_ECN |
41c445ff
JB		 6814 NETIF_F_TSO6 |
6815 NETIF_F_RXCSUM |
6816 NETIF_F_RXHASH |
6817 0;
6818
2e86a0b6
ASJ		 6819 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
6820 netdev->features |= NETIF_F_NTUPLE;
6821
41c445ff
JB		 6822 /* copy netdev features into list of user selectable features */
6823 netdev->hw_features |= netdev->features;
6824
6825 if (vsi->type == I40E_VSI_MAIN) {
6826 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6827 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6828 } else {
6829 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6830 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6831 pf->vsi[pf->lan_vsi]->netdev->name);
6832 random_ether_addr(mac_addr);
6833 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6834 }
1a10370a 6835 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6836
6837 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6838 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6839 /* vlan gets same features (except vlan offload)
6840 * after any tweaks for specific VSI types
6841 */
6842 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6843 NETIF_F_HW_VLAN_CTAG_RX |
6844 NETIF_F_HW_VLAN_CTAG_FILTER);
6845 netdev->priv_flags |= IFF_UNICAST_FLT;
6846 netdev->priv_flags |= IFF_SUPP_NOFCS;
6847 /* Setup netdev TC information */
6848 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6849
6850 netdev->netdev_ops = &i40e_netdev_ops;
6851 netdev->watchdog_timeo = 5 * HZ;
6852 i40e_set_ethtool_ops(netdev);
6853
6854 return 0;
6855}
6856
6857/**
6858 * i40e_vsi_delete - Delete a VSI from the switch
6859 * @vsi: the VSI being removed
6860 *
6861 * Returns 0 on success, negative value on failure
6862 **/
6863static void i40e_vsi_delete(struct i40e_vsi *vsi)
6864{
6865 /* remove default VSI is not allowed */
6866 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6867 return;
6868
41c445ff 6869 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 6870}
6871
6872/**
6873 * i40e_add_vsi - Add a VSI to the switch
6874 * @vsi: the VSI being configured
6875 *
6876 * This initializes a VSI context depending on the VSI type to be added and
6877 * passes it down to the add_vsi aq command.
6878 **/
6879static int i40e_add_vsi(struct i40e_vsi *vsi)
6880{
6881 int ret = -ENODEV;
6882 struct i40e_mac_filter *f, *ftmp;
6883 struct i40e_pf *pf = vsi->back;
6884 struct i40e_hw *hw = &pf->hw;
6885 struct i40e_vsi_context ctxt;
6886 u8 enabled_tc = 0x1; /* TC0 enabled */
6887 int f_count = 0;
6888
6889 memset(&ctxt, 0, sizeof(ctxt));
6890 switch (vsi->type) {
6891 case I40E_VSI_MAIN:
6892 /* The PF's main VSI is already setup as part of the
6893 * device initialization, so we'll not bother with
6894 * the add_vsi call, but we will retrieve the current
6895 * VSI context.
6896 */
6897 ctxt.seid = pf->main_vsi_seid;
6898 ctxt.pf_num = pf->hw.pf_id;
6899 ctxt.vf_num = 0;
6900 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6901 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6902 if (ret) {
6903 dev_info(&pf->pdev->dev,
6904 "couldn't get pf vsi config, err %d, aq_err %d\n",
6905 ret, pf->hw.aq.asq_last_status);
6906 return -ENOENT;
6907 }
6908 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6909 vsi->info.valid_sections = 0;
6910
6911 vsi->seid = ctxt.seid;
6912 vsi->id = ctxt.vsi_number;
6913
6914 enabled_tc = i40e_pf_get_tc_map(pf);
6915
6916 /* MFP mode setup queue map and update VSI */
6917 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6918 memset(&ctxt, 0, sizeof(ctxt));
6919 ctxt.seid = pf->main_vsi_seid;
6920 ctxt.pf_num = pf->hw.pf_id;
6921 ctxt.vf_num = 0;
6922 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6923 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6924 if (ret) {
6925 dev_info(&pf->pdev->dev,
6926 "update vsi failed, aq_err=%d\n",
6927 pf->hw.aq.asq_last_status);
6928 ret = -ENOENT;
6929 goto err;
6930 }
6931 /* update the local VSI info queue map */
6932 i40e_vsi_update_queue_map(vsi, &ctxt);
6933 vsi->info.valid_sections = 0;
6934 } else {
6935 /* Default/Main VSI is only enabled for TC0
6936 * reconfigure it to enable all TCs that are
6937 * available on the port in SFP mode.
6938 */
6939 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6940 if (ret) {
6941 dev_info(&pf->pdev->dev,
6942 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6943 enabled_tc, ret,
6944 pf->hw.aq.asq_last_status);
6945 ret = -ENOENT;
6946 }
6947 }
6948 break;
6949
6950 case I40E_VSI_FDIR:
cbf61325
ASJ		 6951 ctxt.pf_num = hw->pf_id;
6952 ctxt.vf_num = 0;
6953 ctxt.uplink_seid = vsi->uplink_seid;
6954 ctxt.connection_type = 0x1; /* regular data port */
6955 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6956 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6957 break;
6958
6959 case I40E_VSI_VMDQ2:
6960 ctxt.pf_num = hw->pf_id;
6961 ctxt.vf_num = 0;
6962 ctxt.uplink_seid = vsi->uplink_seid;
6963 ctxt.connection_type = 0x1; /* regular data port */
6964 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6965
6966 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6967
6968 /* This VSI is connected to VEB so the switch_id
6969 * should be set to zero by default.
6970 */
6971 ctxt.info.switch_id = 0;
6972 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6973 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6974
6975 /* Setup the VSI tx/rx queue map for TC0 only for now */
6976 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6977 break;
6978
6979 case I40E_VSI_SRIOV:
6980 ctxt.pf_num = hw->pf_id;
6981 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6982 ctxt.uplink_seid = vsi->uplink_seid;
6983 ctxt.connection_type = 0x1; /* regular data port */
6984 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6985
6986 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6987
6988 /* This VSI is connected to VEB so the switch_id
6989 * should be set to zero by default.
6990 */
6991 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6992
6993 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6994 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6995 /* Setup the VSI tx/rx queue map for TC0 only for now */
6996 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6997 break;
6998
6999 default:
7000 return -ENODEV;
7001 }
7002
7003 if (vsi->type != I40E_VSI_MAIN) {
7004 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7005 if (ret) {
7006 dev_info(&vsi->back->pdev->dev,
7007 "add vsi failed, aq_err=%d\n",
7008 vsi->back->hw.aq.asq_last_status);
7009 ret = -ENOENT;
7010 goto err;
7011 }
7012 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7013 vsi->info.valid_sections = 0;
7014 vsi->seid = ctxt.seid;
7015 vsi->id = ctxt.vsi_number;
7016 }
7017
7018 /* If macvlan filters already exist, force them to get loaded */
7019 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7020 f->changed = true;
7021 f_count++;
7022 }
7023 if (f_count) {
7024 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7025 pf->flags |= I40E_FLAG_FILTER_SYNC;
7026 }
7027
7028 /* Update VSI BW information */
7029 ret = i40e_vsi_get_bw_info(vsi);
7030 if (ret) {
7031 dev_info(&pf->pdev->dev,
7032 "couldn't get vsi bw info, err %d, aq_err %d\n",
7033 ret, pf->hw.aq.asq_last_status);
7034 /* VSI is already added so not tearing that up */
7035 ret = 0;
7036 }
7037
7038err:
7039 return ret;
7040}
7041
7042/**
7043 * i40e_vsi_release - Delete a VSI and free its resources
7044 * @vsi: the VSI being removed
7045 *
7046 * Returns 0 on success or < 0 on error
7047 **/
7048int i40e_vsi_release(struct i40e_vsi *vsi)
7049{
7050 struct i40e_mac_filter *f, *ftmp;
7051 struct i40e_veb *veb = NULL;
7052 struct i40e_pf *pf;
7053 u16 uplink_seid;
7054 int i, n;
7055
7056 pf = vsi->back;
7057
7058 /* release of a VEB-owner or last VSI is not allowed */
7059 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7060 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7061 vsi->seid, vsi->uplink_seid);
7062 return -ENODEV;
7063 }
7064 if (vsi == pf->vsi[pf->lan_vsi] &&
7065 !test_bit(__I40E_DOWN, &pf->state)) {
7066 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7067 return -ENODEV;
7068 }
7069
7070 uplink_seid = vsi->uplink_seid;
7071 if (vsi->type != I40E_VSI_SRIOV) {
7072 if (vsi->netdev_registered) {
7073 vsi->netdev_registered = false;
7074 if (vsi->netdev) {
7075 /* results in a call to i40e_close() */
7076 unregister_netdev(vsi->netdev);
41c445ff
JB		 7077 }
7078 } else {
90ef8d47 7079 i40e_vsi_close(vsi);
41c445ff
JB		 7080 }
7081 i40e_vsi_disable_irq(vsi);
7082 }
7083
7084 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7085 i40e_del_filter(vsi, f->macaddr, f->vlan,
7086 f->is_vf, f->is_netdev);
7087 i40e_sync_vsi_filters(vsi);
7088
7089 i40e_vsi_delete(vsi);
7090 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7091 if (vsi->netdev) {
7092 free_netdev(vsi->netdev);
7093 vsi->netdev = NULL;
7094 }
41c445ff
JB		 7095 i40e_vsi_clear_rings(vsi);
7096 i40e_vsi_clear(vsi);
7097
7098 /* If this was the last thing on the VEB, except for the
7099 * controlling VSI, remove the VEB, which puts the controlling
7100 * VSI onto the next level down in the switch.
7101 *
7102 * Well, okay, there's one more exception here: don't remove
7103 * the orphan VEBs yet. We'll wait for an explicit remove request
7104 * from up the network stack.
7105 */
7106 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7107 if (pf->vsi[i] &&
7108 pf->vsi[i]->uplink_seid == uplink_seid &&
7109 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7110 n++; /* count the VSIs */
7111 }
7112 }
7113 for (i = 0; i < I40E_MAX_VEB; i++) {
7114 if (!pf->veb[i])
7115 continue;
7116 if (pf->veb[i]->uplink_seid == uplink_seid)
7117 n++; /* count the VEBs */
7118 if (pf->veb[i]->seid == uplink_seid)
7119 veb = pf->veb[i];
7120 }
7121 if (n == 0 && veb && veb->uplink_seid != 0)
7122 i40e_veb_release(veb);
7123
7124 return 0;
7125}
7126
7127/**
7128 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7129 * @vsi: ptr to the VSI
7130 *
7131 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7132 * corresponding SW VSI structure and initializes num_queue_pairs for the
7133 * newly allocated VSI.
7134 *
7135 * Returns 0 on success or negative on failure
7136 **/
7137static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7138{
7139 int ret = -ENOENT;
7140 struct i40e_pf *pf = vsi->back;
7141
493fb300 7142 if (vsi->q_vectors[0]) {
41c445ff
JB		 7143 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7144 vsi->seid);
7145 return -EEXIST;
7146 }
7147
7148 if (vsi->base_vector) {
f29eaa3d 7149 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7150 vsi->seid, vsi->base_vector);
7151 return -EEXIST;
7152 }
7153
90e04070 7154 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7155 if (ret) {
7156 dev_info(&pf->pdev->dev,
7157 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7158 vsi->num_q_vectors, vsi->seid, ret);
7159 vsi->num_q_vectors = 0;
7160 goto vector_setup_out;
7161 }
7162
958a3e3b
SN		 7163 if (vsi->num_q_vectors)
7164 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7165 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7166 if (vsi->base_vector < 0) {
7167 dev_info(&pf->pdev->dev,
f29eaa3d 7168 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7169 vsi->seid, vsi->base_vector);
7170 i40e_vsi_free_q_vectors(vsi);
7171 ret = -ENOENT;
7172 goto vector_setup_out;
7173 }
7174
7175vector_setup_out:
7176 return ret;
7177}
7178
bc7d338f
ASJ		 7179/**
7180 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7181 * @vsi: pointer to the vsi.
7182 *
7183 * This re-allocates a vsi's queue resources.
7184 *
7185 * Returns pointer to the successfully allocated and configured VSI sw struct
7186 * on success, otherwise returns NULL on failure.
7187 **/
7188static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7189{
7190 struct i40e_pf *pf = vsi->back;
7191 u8 enabled_tc;
7192 int ret;
7193
7194 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7195 i40e_vsi_clear_rings(vsi);
7196
7197 i40e_vsi_free_arrays(vsi, false);
7198 i40e_set_num_rings_in_vsi(vsi);
7199 ret = i40e_vsi_alloc_arrays(vsi, false);
7200 if (ret)
7201 goto err_vsi;
7202
7203 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7204 if (ret < 0) {
7205 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7206 vsi->seid, ret);
7207 goto err_vsi;
7208 }
7209 vsi->base_queue = ret;
7210
7211 /* Update the FW view of the VSI. Force a reset of TC and queue
7212 * layout configurations.
7213 */
7214 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7215 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7216 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7217 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7218
7219 /* assign it some queues */
7220 ret = i40e_alloc_rings(vsi);
7221 if (ret)
7222 goto err_rings;
7223
7224 /* map all of the rings to the q_vectors */
7225 i40e_vsi_map_rings_to_vectors(vsi);
7226 return vsi;
7227
7228err_rings:
7229 i40e_vsi_free_q_vectors(vsi);
7230 if (vsi->netdev_registered) {
7231 vsi->netdev_registered = false;
7232 unregister_netdev(vsi->netdev);
7233 free_netdev(vsi->netdev);
7234 vsi->netdev = NULL;
7235 }
7236 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7237err_vsi:
7238 i40e_vsi_clear(vsi);
7239 return NULL;
7240}
7241
41c445ff
JB		 7242/**
7243 * i40e_vsi_setup - Set up a VSI by a given type
7244 * @pf: board private structure
7245 * @type: VSI type
7246 * @uplink_seid: the switch element to link to
7247 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7248 *
7249 * This allocates the sw VSI structure and its queue resources, then add a VSI
7250 * to the identified VEB.
7251 *
7252 * Returns pointer to the successfully allocated and configure VSI sw struct on
7253 * success, otherwise returns NULL on failure.
7254 **/
7255struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7256 u16 uplink_seid, u32 param1)
7257{
7258 struct i40e_vsi *vsi = NULL;
7259 struct i40e_veb *veb = NULL;
7260 int ret, i;
7261 int v_idx;
7262
7263 /* The requested uplink_seid must be either
7264 * - the PF's port seid
7265 * no VEB is needed because this is the PF
7266 * or this is a Flow Director special case VSI
7267 * - seid of an existing VEB
7268 * - seid of a VSI that owns an existing VEB
7269 * - seid of a VSI that doesn't own a VEB
7270 * a new VEB is created and the VSI becomes the owner
7271 * - seid of the PF VSI, which is what creates the first VEB
7272 * this is a special case of the previous
7273 *
7274 * Find which uplink_seid we were given and create a new VEB if needed
7275 */
7276 for (i = 0; i < I40E_MAX_VEB; i++) {
7277 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7278 veb = pf->veb[i];
7279 break;
7280 }
7281 }
7282
7283 if (!veb && uplink_seid != pf->mac_seid) {
7284
7285 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7286 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7287 vsi = pf->vsi[i];
7288 break;
7289 }
7290 }
7291 if (!vsi) {
7292 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7293 uplink_seid);
7294 return NULL;
7295 }
7296
7297 if (vsi->uplink_seid == pf->mac_seid)
7298 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7299 vsi->tc_config.enabled_tc);
7300 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7301 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7302 vsi->tc_config.enabled_tc);
7303
7304 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7305 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7306 veb = pf->veb[i];
7307 }
7308 if (!veb) {
7309 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7310 return NULL;
7311 }
7312
7313 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7314 uplink_seid = veb->seid;
7315 }
7316
7317 /* get vsi sw struct */
7318 v_idx = i40e_vsi_mem_alloc(pf, type);
7319 if (v_idx < 0)
7320 goto err_alloc;
7321 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7322 if (!vsi)
7323 goto err_alloc;
41c445ff
JB		 7324 vsi->type = type;
7325 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7326
7327 if (type == I40E_VSI_MAIN)
7328 pf->lan_vsi = v_idx;
7329 else if (type == I40E_VSI_SRIOV)
7330 vsi->vf_id = param1;
7331 /* assign it some queues */
cbf61325
ASJ		 7332 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7333 vsi->idx);
41c445ff
JB		 7334 if (ret < 0) {
7335 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7336 vsi->seid, ret);
7337 goto err_vsi;
7338 }
7339 vsi->base_queue = ret;
7340
7341 /* get a VSI from the hardware */
7342 vsi->uplink_seid = uplink_seid;
7343 ret = i40e_add_vsi(vsi);
7344 if (ret)
7345 goto err_vsi;
7346
7347 switch (vsi->type) {
7348 /* setup the netdev if needed */
7349 case I40E_VSI_MAIN:
7350 case I40E_VSI_VMDQ2:
7351 ret = i40e_config_netdev(vsi);
7352 if (ret)
7353 goto err_netdev;
7354 ret = register_netdev(vsi->netdev);
7355 if (ret)
7356 goto err_netdev;
7357 vsi->netdev_registered = true;
7358 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7359#ifdef CONFIG_I40E_DCB
7360 /* Setup DCB netlink interface */
7361 i40e_dcbnl_setup(vsi);
7362#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7363 /* fall through */
7364
7365 case I40E_VSI_FDIR:
7366 /* set up vectors and rings if needed */
7367 ret = i40e_vsi_setup_vectors(vsi);
7368 if (ret)
7369 goto err_msix;
7370
7371 ret = i40e_alloc_rings(vsi);
7372 if (ret)
7373 goto err_rings;
7374
7375 /* map all of the rings to the q_vectors */
7376 i40e_vsi_map_rings_to_vectors(vsi);
7377
7378 i40e_vsi_reset_stats(vsi);
7379 break;
7380
7381 default:
7382 /* no netdev or rings for the other VSI types */
7383 break;
7384 }
7385
7386 return vsi;
7387
7388err_rings:
7389 i40e_vsi_free_q_vectors(vsi);
7390err_msix:
7391 if (vsi->netdev_registered) {
7392 vsi->netdev_registered = false;
7393 unregister_netdev(vsi->netdev);
7394 free_netdev(vsi->netdev);
7395 vsi->netdev = NULL;
7396 }
7397err_netdev:
7398 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7399err_vsi:
7400 i40e_vsi_clear(vsi);
7401err_alloc:
7402 return NULL;
7403}
7404
7405/**
7406 * i40e_veb_get_bw_info - Query VEB BW information
7407 * @veb: the veb to query
7408 *
7409 * Query the Tx scheduler BW configuration data for given VEB
7410 **/
7411static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7412{
7413 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7414 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7415 struct i40e_pf *pf = veb->pf;
7416 struct i40e_hw *hw = &pf->hw;
7417 u32 tc_bw_max;
7418 int ret = 0;
7419 int i;
7420
7421 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7422 &bw_data, NULL);
7423 if (ret) {
7424 dev_info(&pf->pdev->dev,
7425 "query veb bw config failed, aq_err=%d\n",
7426 hw->aq.asq_last_status);
7427 goto out;
7428 }
7429
7430 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7431 &ets_data, NULL);
7432 if (ret) {
7433 dev_info(&pf->pdev->dev,
7434 "query veb bw ets config failed, aq_err=%d\n",
7435 hw->aq.asq_last_status);
7436 goto out;
7437 }
7438
7439 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7440 veb->bw_max_quanta = ets_data.tc_bw_max;
7441 veb->is_abs_credits = bw_data.absolute_credits_enable;
7442 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7443 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7444 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7445 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7446 veb->bw_tc_limit_credits[i] =
7447 le16_to_cpu(bw_data.tc_bw_limits[i]);
7448 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7449 }
7450
7451out:
7452 return ret;
7453}
7454
7455/**
7456 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7457 * @pf: board private structure
7458 *
7459 * On error: returns error code (negative)
7460 * On success: returns vsi index in PF (positive)
7461 **/
7462static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7463{
7464 int ret = -ENOENT;
7465 struct i40e_veb *veb;
7466 int i;
7467
7468 /* Need to protect the allocation of switch elements at the PF level */
7469 mutex_lock(&pf->switch_mutex);
7470
7471 /* VEB list may be fragmented if VEB creation/destruction has
7472 * been happening. We can afford to do a quick scan to look
7473 * for any free slots in the list.
7474 *
7475 * find next empty veb slot, looping back around if necessary
7476 */
7477 i = 0;
7478 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7479 i++;
7480 if (i >= I40E_MAX_VEB) {
7481 ret = -ENOMEM;
7482 goto err_alloc_veb; /* out of VEB slots! */
7483 }
7484
7485 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7486 if (!veb) {
7487 ret = -ENOMEM;
7488 goto err_alloc_veb;
7489 }
7490 veb->pf = pf;
7491 veb->idx = i;
7492 veb->enabled_tc = 1;
7493
7494 pf->veb[i] = veb;
7495 ret = i;
7496err_alloc_veb:
7497 mutex_unlock(&pf->switch_mutex);
7498 return ret;
7499}
7500
7501/**
7502 * i40e_switch_branch_release - Delete a branch of the switch tree
7503 * @branch: where to start deleting
7504 *
7505 * This uses recursion to find the tips of the branch to be
7506 * removed, deleting until we get back to and can delete this VEB.
7507 **/
7508static void i40e_switch_branch_release(struct i40e_veb *branch)
7509{
7510 struct i40e_pf *pf = branch->pf;
7511 u16 branch_seid = branch->seid;
7512 u16 veb_idx = branch->idx;
7513 int i;
7514
7515 /* release any VEBs on this VEB - RECURSION */
7516 for (i = 0; i < I40E_MAX_VEB; i++) {
7517 if (!pf->veb[i])
7518 continue;
7519 if (pf->veb[i]->uplink_seid == branch->seid)
7520 i40e_switch_branch_release(pf->veb[i]);
7521 }
7522
7523 /* Release the VSIs on this VEB, but not the owner VSI.
7524 *
7525 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7526 * the VEB itself, so don't use (*branch) after this loop.
7527 */
7528 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7529 if (!pf->vsi[i])
7530 continue;
7531 if (pf->vsi[i]->uplink_seid == branch_seid &&
7532 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7533 i40e_vsi_release(pf->vsi[i]);
7534 }
7535 }
7536
7537 /* There's one corner case where the VEB might not have been
7538 * removed, so double check it here and remove it if needed.
7539 * This case happens if the veb was created from the debugfs
7540 * commands and no VSIs were added to it.
7541 */
7542 if (pf->veb[veb_idx])
7543 i40e_veb_release(pf->veb[veb_idx]);
7544}
7545
7546/**
7547 * i40e_veb_clear - remove veb struct
7548 * @veb: the veb to remove
7549 **/
7550static void i40e_veb_clear(struct i40e_veb *veb)
7551{
7552 if (!veb)
7553 return;
7554
7555 if (veb->pf) {
7556 struct i40e_pf *pf = veb->pf;
7557
7558 mutex_lock(&pf->switch_mutex);
7559 if (pf->veb[veb->idx] == veb)
7560 pf->veb[veb->idx] = NULL;
7561 mutex_unlock(&pf->switch_mutex);
7562 }
7563
7564 kfree(veb);
7565}
7566
7567/**
7568 * i40e_veb_release - Delete a VEB and free its resources
7569 * @veb: the VEB being removed
7570 **/
7571void i40e_veb_release(struct i40e_veb *veb)
7572{
7573 struct i40e_vsi *vsi = NULL;
7574 struct i40e_pf *pf;
7575 int i, n = 0;
7576
7577 pf = veb->pf;
7578
7579 /* find the remaining VSI and check for extras */
7580 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7581 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7582 n++;
7583 vsi = pf->vsi[i];
7584 }
7585 }
7586 if (n != 1) {
7587 dev_info(&pf->pdev->dev,
7588 "can't remove VEB %d with %d VSIs left\n",
7589 veb->seid, n);
7590 return;
7591 }
7592
7593 /* move the remaining VSI to uplink veb */
7594 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7595 if (veb->uplink_seid) {
7596 vsi->uplink_seid = veb->uplink_seid;
7597 if (veb->uplink_seid == pf->mac_seid)
7598 vsi->veb_idx = I40E_NO_VEB;
7599 else
7600 vsi->veb_idx = veb->veb_idx;
7601 } else {
7602 /* floating VEB */
7603 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7604 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7605 }
7606
7607 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7608 i40e_veb_clear(veb);
41c445ff
JB		 7609}
7610
7611/**
7612 * i40e_add_veb - create the VEB in the switch
7613 * @veb: the VEB to be instantiated
7614 * @vsi: the controlling VSI
7615 **/
7616static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7617{
56747264 7618 bool is_default = false;
e1c51b95 7619 bool is_cloud = false;
41c445ff
JB		 7620 int ret;
7621
7622 /* get a VEB from the hardware */
7623 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7624 veb->enabled_tc, is_default,
7625 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7626 if (ret) {
7627 dev_info(&veb->pf->pdev->dev,
7628 "couldn't add VEB, err %d, aq_err %d\n",
7629 ret, veb->pf->hw.aq.asq_last_status);
7630 return -EPERM;
7631 }
7632
7633 /* get statistics counter */
7634 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7635 &veb->stats_idx, NULL, NULL, NULL);
7636 if (ret) {
7637 dev_info(&veb->pf->pdev->dev,
7638 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7639 ret, veb->pf->hw.aq.asq_last_status);
7640 return -EPERM;
7641 }
7642 ret = i40e_veb_get_bw_info(veb);
7643 if (ret) {
7644 dev_info(&veb->pf->pdev->dev,
7645 "couldn't get VEB bw info, err %d, aq_err %d\n",
7646 ret, veb->pf->hw.aq.asq_last_status);
7647 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7648 return -ENOENT;
7649 }
7650
7651 vsi->uplink_seid = veb->seid;
7652 vsi->veb_idx = veb->idx;
7653 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7654
7655 return 0;
7656}
7657
7658/**
7659 * i40e_veb_setup - Set up a VEB
7660 * @pf: board private structure
7661 * @flags: VEB setup flags
7662 * @uplink_seid: the switch element to link to
7663 * @vsi_seid: the initial VSI seid
7664 * @enabled_tc: Enabled TC bit-map
7665 *
7666 * This allocates the sw VEB structure and links it into the switch
7667 * It is possible and legal for this to be a duplicate of an already
7668 * existing VEB. It is also possible for both uplink and vsi seids
7669 * to be zero, in order to create a floating VEB.
7670 *
7671 * Returns pointer to the successfully allocated VEB sw struct on
7672 * success, otherwise returns NULL on failure.
7673 **/
7674struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7675 u16 uplink_seid, u16 vsi_seid,
7676 u8 enabled_tc)
7677{
7678 struct i40e_veb *veb, *uplink_veb = NULL;
7679 int vsi_idx, veb_idx;
7680 int ret;
7681
7682 /* if one seid is 0, the other must be 0 to create a floating relay */
7683 if ((uplink_seid == 0 || vsi_seid == 0) &&
7684 (uplink_seid + vsi_seid != 0)) {
7685 dev_info(&pf->pdev->dev,
7686 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7687 uplink_seid, vsi_seid);
7688 return NULL;
7689 }
7690
7691 /* make sure there is such a vsi and uplink */
7692 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7693 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7694 break;
7695 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7696 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7697 vsi_seid);
7698 return NULL;
7699 }
7700
7701 if (uplink_seid && uplink_seid != pf->mac_seid) {
7702 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7703 if (pf->veb[veb_idx] &&
7704 pf->veb[veb_idx]->seid == uplink_seid) {
7705 uplink_veb = pf->veb[veb_idx];
7706 break;
7707 }
7708 }
7709 if (!uplink_veb) {
7710 dev_info(&pf->pdev->dev,
7711 "uplink seid %d not found\n", uplink_seid);
7712 return NULL;
7713 }
7714 }
7715
7716 /* get veb sw struct */
7717 veb_idx = i40e_veb_mem_alloc(pf);
7718 if (veb_idx < 0)
7719 goto err_alloc;
7720 veb = pf->veb[veb_idx];
7721 veb->flags = flags;
7722 veb->uplink_seid = uplink_seid;
7723 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7724 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7725
7726 /* create the VEB in the switch */
7727 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7728 if (ret)
7729 goto err_veb;
7730
7731 return veb;
7732
7733err_veb:
7734 i40e_veb_clear(veb);
7735err_alloc:
7736 return NULL;
7737}
7738
7739/**
7740 * i40e_setup_pf_switch_element - set pf vars based on switch type
7741 * @pf: board private structure
7742 * @ele: element we are building info from
7743 * @num_reported: total number of elements
7744 * @printconfig: should we print the contents
7745 *
7746 * helper function to assist in extracting a few useful SEID values.
7747 **/
7748static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7749 struct i40e_aqc_switch_config_element_resp *ele,
7750 u16 num_reported, bool printconfig)
7751{
7752 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7753 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7754 u8 element_type = ele->element_type;
7755 u16 seid = le16_to_cpu(ele->seid);
7756
7757 if (printconfig)
7758 dev_info(&pf->pdev->dev,
7759 "type=%d seid=%d uplink=%d downlink=%d\n",
7760 element_type, seid, uplink_seid, downlink_seid);
7761
7762 switch (element_type) {
7763 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7764 pf->mac_seid = seid;
7765 break;
7766 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7767 /* Main VEB? */
7768 if (uplink_seid != pf->mac_seid)
7769 break;
7770 if (pf->lan_veb == I40E_NO_VEB) {
7771 int v;
7772
7773 /* find existing or else empty VEB */
7774 for (v = 0; v < I40E_MAX_VEB; v++) {
7775 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7776 pf->lan_veb = v;
7777 break;
7778 }
7779 }
7780 if (pf->lan_veb == I40E_NO_VEB) {
7781 v = i40e_veb_mem_alloc(pf);
7782 if (v < 0)
7783 break;
7784 pf->lan_veb = v;
7785 }
7786 }
7787
7788 pf->veb[pf->lan_veb]->seid = seid;
7789 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7790 pf->veb[pf->lan_veb]->pf = pf;
7791 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7792 break;
7793 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7794 if (num_reported != 1)
7795 break;
7796 /* This is immediately after a reset so we can assume this is
7797 * the PF's VSI
7798 */
7799 pf->mac_seid = uplink_seid;
7800 pf->pf_seid = downlink_seid;
7801 pf->main_vsi_seid = seid;
7802 if (printconfig)
7803 dev_info(&pf->pdev->dev,
7804 "pf_seid=%d main_vsi_seid=%d\n",
7805 pf->pf_seid, pf->main_vsi_seid);
7806 break;
7807 case I40E_SWITCH_ELEMENT_TYPE_PF:
7808 case I40E_SWITCH_ELEMENT_TYPE_VF:
7809 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7810 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7811 case I40E_SWITCH_ELEMENT_TYPE_PE:
7812 case I40E_SWITCH_ELEMENT_TYPE_PA:
7813 /* ignore these for now */
7814 break;
7815 default:
7816 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7817 element_type, seid);
7818 break;
7819 }
7820}
7821
7822/**
7823 * i40e_fetch_switch_configuration - Get switch config from firmware
7824 * @pf: board private structure
7825 * @printconfig: should we print the contents
7826 *
7827 * Get the current switch configuration from the device and
7828 * extract a few useful SEID values.
7829 **/
7830int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7831{
7832 struct i40e_aqc_get_switch_config_resp *sw_config;
7833 u16 next_seid = 0;
7834 int ret = 0;
7835 u8 *aq_buf;
7836 int i;
7837
7838 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7839 if (!aq_buf)
7840 return -ENOMEM;
7841
7842 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7843 do {
7844 u16 num_reported, num_total;
7845
7846 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7847 I40E_AQ_LARGE_BUF,
7848 &next_seid, NULL);
7849 if (ret) {
7850 dev_info(&pf->pdev->dev,
7851 "get switch config failed %d aq_err=%x\n",
7852 ret, pf->hw.aq.asq_last_status);
7853 kfree(aq_buf);
7854 return -ENOENT;
7855 }
7856
7857 num_reported = le16_to_cpu(sw_config->header.num_reported);
7858 num_total = le16_to_cpu(sw_config->header.num_total);
7859
7860 if (printconfig)
7861 dev_info(&pf->pdev->dev,
7862 "header: %d reported %d total\n",
7863 num_reported, num_total);
7864
7865 if (num_reported) {
7866 int sz = sizeof(*sw_config) * num_reported;
7867
7868 kfree(pf->sw_config);
7869 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7870 if (pf->sw_config)
7871 memcpy(pf->sw_config, sw_config, sz);
7872 }
7873
7874 for (i = 0; i < num_reported; i++) {
7875 struct i40e_aqc_switch_config_element_resp *ele =
7876 &sw_config->element[i];
7877
7878 i40e_setup_pf_switch_element(pf, ele, num_reported,
7879 printconfig);
7880 }
7881 } while (next_seid != 0);
7882
7883 kfree(aq_buf);
7884 return ret;
7885}
7886
7887/**
7888 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7889 * @pf: board private structure
bc7d338f 7890 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7891 *
7892 * Returns 0 on success, negative value on failure
7893 **/
bc7d338f 7894static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7895{
895106a5 7896 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7897 int ret;
7898
7899 /* find out what's out there already */
7900 ret = i40e_fetch_switch_configuration(pf, false);
7901 if (ret) {
7902 dev_info(&pf->pdev->dev,
7903 "couldn't fetch switch config, err %d, aq_err %d\n",
7904 ret, pf->hw.aq.asq_last_status);
7905 return ret;
7906 }
7907 i40e_pf_reset_stats(pf);
7908
41c445ff 7909 /* first time setup */
bc7d338f 7910 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7911 struct i40e_vsi *vsi = NULL;
7912 u16 uplink_seid;
7913
7914 /* Set up the PF VSI associated with the PF's main VSI
7915 * that is already in the HW switch
7916 */
7917 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7918 uplink_seid = pf->veb[pf->lan_veb]->seid;
7919 else
7920 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7921 if (pf->lan_vsi == I40E_NO_VSI)
7922 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7923 else if (reinit)
7924 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7925 if (!vsi) {
7926 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7927 i40e_fdir_teardown(pf);
7928 return -EAGAIN;
7929 }
41c445ff
JB		 7930 } else {
7931 /* force a reset of TC and queue layout configurations */
7932 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7933 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7934 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7935 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7936 }
7937 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7938
cbf61325
ASJ		 7939 i40e_fdir_sb_setup(pf);
7940
41c445ff
JB		 7941 /* Setup static PF queue filter control settings */
7942 ret = i40e_setup_pf_filter_control(pf);
7943 if (ret) {
7944 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7945 ret);
7946 /* Failure here should not stop continuing other steps */
7947 }
7948
7949 /* enable RSS in the HW, even for only one queue, as the stack can use
7950 * the hash
7951 */
7952 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7953 i40e_config_rss(pf);
7954
7955 /* fill in link information and enable LSE reporting */
7956 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7957 i40e_link_event(pf);
7958
d52c20b7 7959 /* Initialize user-specific link properties */
41c445ff
JB		 7960 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7961 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7962 /* requested_mode is set in probe or by ethtool */
7963 if (!pf->fc_autoneg_status)
7964 goto no_autoneg;
7965
7966 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7967 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7968 pf->hw.fc.current_mode = I40E_FC_FULL;
7969 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7970 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7971 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7972 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7973 else
d52c20b7
JB		 7974 pf->hw.fc.current_mode = I40E_FC_NONE;
7975
7976 /* sync the flow control settings with the auto-neg values */
7977 switch (pf->hw.fc.current_mode) {
7978 case I40E_FC_FULL:
7979 txfc = 1;
7980 rxfc = 1;
7981 break;
7982 case I40E_FC_TX_PAUSE:
7983 txfc = 1;
7984 rxfc = 0;
7985 break;
7986 case I40E_FC_RX_PAUSE:
7987 txfc = 0;
7988 rxfc = 1;
7989 break;
7990 case I40E_FC_NONE:
7991 case I40E_FC_DEFAULT:
7992 txfc = 0;
7993 rxfc = 0;
7994 break;
7995 case I40E_FC_PFC:
7996 /* TBD */
7997 break;
7998 /* no default case, we have to handle all possibilities here */
7999 }
8000
8001 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8002
8003 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8004 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8005 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8006
8007 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8008
d52c20b7
JB		 8009 goto fc_complete;
8010
8011no_autoneg:
8012 /* disable L2 flow control, user can turn it on if they wish */
8013 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8014 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8015 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8016
8017fc_complete:
beb0dff1
JK		 8018 i40e_ptp_init(pf);
8019
41c445ff
JB		 8020 return ret;
8021}
8022
41c445ff
JB		 8023/**
8024 * i40e_determine_queue_usage - Work out queue distribution
8025 * @pf: board private structure
8026 **/
8027static void i40e_determine_queue_usage(struct i40e_pf *pf)
8028{
41c445ff
JB		 8029 int queues_left;
8030
8031 pf->num_lan_qps = 0;
41c445ff
JB		 8032
8033 /* Find the max queues to be put into basic use. We'll always be
8034 * using TC0, whether or not DCB is running, and TC0 will get the
8035 * big RSS set.
8036 */
8037 queues_left = pf->hw.func_caps.num_tx_qp;
8038
cbf61325
ASJ		 8039 if ((queues_left == 1) ||
8040 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8041 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8042 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8043 /* one qp for PF, no queues for anything else */
8044 queues_left = 0;
8045 pf->rss_size = pf->num_lan_qps = 1;
8046
8047 /* make sure all the fancies are disabled */
60ea5f83
JB		 8048 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8049 I40E_FLAG_FD_SB_ENABLED |
8050 I40E_FLAG_FD_ATR_ENABLED |
8051 I40E_FLAG_DCB_ENABLED |
8052 I40E_FLAG_SRIOV_ENABLED |
8053 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8054 } else {
cbf61325
ASJ		 8055 /* Not enough queues for all TCs */
8056 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8057 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8058 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8059 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8060 }
8061 pf->num_lan_qps = pf->rss_size_max;
8062 queues_left -= pf->num_lan_qps;
8063 }
8064
8065 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8066 if (queues_left > 1) {
8067 queues_left -= 1; /* save 1 queue for FD */
8068 } else {
8069 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8070 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8071 }
41c445ff
JB		 8072 }
8073
8074 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8075 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8076 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8077 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8078 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8079 }
8080
8081 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8082 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8083 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8084 (queues_left / pf->num_vmdq_qps));
8085 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8086 }
8087
f8ff1464 8088 pf->queues_left = queues_left;
41c445ff
JB		 8089}
8090
8091/**
8092 * i40e_setup_pf_filter_control - Setup PF static filter control
8093 * @pf: PF to be setup
8094 *
8095 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8096 * settings. If PE/FCoE are enabled then it will also set the per PF
8097 * based filter sizes required for them. It also enables Flow director,
8098 * ethertype and macvlan type filter settings for the pf.
8099 *
8100 * Returns 0 on success, negative on failure
8101 **/
8102static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8103{
8104 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8105
8106 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8107
8108 /* Flow Director is enabled */
60ea5f83 8109 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8110 settings->enable_fdir = true;
8111
8112 /* Ethtype and MACVLAN filters enabled for PF */
8113 settings->enable_ethtype = true;
8114 settings->enable_macvlan = true;
8115
8116 if (i40e_set_filter_control(&pf->hw, settings))
8117 return -ENOENT;
8118
8119 return 0;
8120}
8121
0c22b3dd
JB		 8122#define INFO_STRING_LEN 255
8123static void i40e_print_features(struct i40e_pf *pf)
8124{
8125 struct i40e_hw *hw = &pf->hw;
8126 char *buf, *string;
8127
8128 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8129 if (!string) {
8130 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8131 return;
8132 }
8133
8134 buf = string;
8135
8136 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8137#ifdef CONFIG_PCI_IOV
8138 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8139#endif
8140 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8141 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8142
8143 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8144 buf += sprintf(buf, "RSS ");
8145 buf += sprintf(buf, "FDir ");
8146 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8147 buf += sprintf(buf, "ATR ");
8148 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8149 buf += sprintf(buf, "NTUPLE ");
8150 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8151 buf += sprintf(buf, "DCB ");
8152 if (pf->flags & I40E_FLAG_PTP)
8153 buf += sprintf(buf, "PTP ");
8154
8155 BUG_ON(buf > (string + INFO_STRING_LEN));
8156 dev_info(&pf->pdev->dev, "%s\n", string);
8157 kfree(string);
8158}
8159
41c445ff
JB		 8160/**
8161 * i40e_probe - Device initialization routine
8162 * @pdev: PCI device information struct
8163 * @ent: entry in i40e_pci_tbl
8164 *
8165 * i40e_probe initializes a pf identified by a pci_dev structure.
8166 * The OS initialization, configuring of the pf private structure,
8167 * and a hardware reset occur.
8168 *
8169 * Returns 0 on success, negative on failure
8170 **/
8171static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8172{
41c445ff
JB		 8173 struct i40e_pf *pf;
8174 struct i40e_hw *hw;
93cd765b 8175 static u16 pfs_found;
d4dfb81a 8176 u16 link_status;
41c445ff
JB		 8177 int err = 0;
8178 u32 len;
8a9eb7d3 8179 u32 i;
41c445ff
JB		 8180
8181 err = pci_enable_device_mem(pdev);
8182 if (err)
8183 return err;
8184
8185 /* set up for high or low dma */
6494294f 8186 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8187 if (err) {
e3e3bfdd
JS		 8188 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8189 if (err) {
8190 dev_err(&pdev->dev,
8191 "DMA configuration failed: 0x%x\n", err);
8192 goto err_dma;
8193 }
41c445ff
JB		 8194 }
8195
8196 /* set up pci connections */
8197 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8198 IORESOURCE_MEM), i40e_driver_name);
8199 if (err) {
8200 dev_info(&pdev->dev,
8201 "pci_request_selected_regions failed %d\n", err);
8202 goto err_pci_reg;
8203 }
8204
8205 pci_enable_pcie_error_reporting(pdev);
8206 pci_set_master(pdev);
8207
8208 /* Now that we have a PCI connection, we need to do the
8209 * low level device setup. This is primarily setting up
8210 * the Admin Queue structures and then querying for the
8211 * device's current profile information.
8212 */
8213 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8214 if (!pf) {
8215 err = -ENOMEM;
8216 goto err_pf_alloc;
8217 }
8218 pf->next_vsi = 0;
8219 pf->pdev = pdev;
8220 set_bit(__I40E_DOWN, &pf->state);
8221
8222 hw = &pf->hw;
8223 hw->back = pf;
8224 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8225 pci_resource_len(pdev, 0));
8226 if (!hw->hw_addr) {
8227 err = -EIO;
8228 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8229 (unsigned int)pci_resource_start(pdev, 0),
8230 (unsigned int)pci_resource_len(pdev, 0), err);
8231 goto err_ioremap;
8232 }
8233 hw->vendor_id = pdev->vendor;
8234 hw->device_id = pdev->device;
8235 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8236 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8237 hw->subsystem_device_id = pdev->subsystem_device;
8238 hw->bus.device = PCI_SLOT(pdev->devfn);
8239 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8240 pf->instance = pfs_found;
41c445ff 8241
7134f9ce
JB		 8242 /* do a special CORER for clearing PXE mode once at init */
8243 if (hw->revision_id == 0 &&
8244 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8245 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8246 i40e_flush(hw);
8247 msleep(200);
8248 pf->corer_count++;
8249
8250 i40e_clear_pxe_mode(hw);
8251 }
8252
41c445ff
JB		 8253 /* Reset here to make sure all is clean and to define PF 'n' */
8254 err = i40e_pf_reset(hw);
8255 if (err) {
8256 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8257 goto err_pf_reset;
8258 }
8259 pf->pfr_count++;
8260
8261 hw->aq.num_arq_entries = I40E_AQ_LEN;
8262 hw->aq.num_asq_entries = I40E_AQ_LEN;
8263 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8264 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8265 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8266 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8267 "%s-pf%d:misc",
8268 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8269
8270 err = i40e_init_shared_code(hw);
8271 if (err) {
8272 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8273 goto err_pf_reset;
8274 }
8275
d52c20b7
JB		 8276 /* set up a default setting for link flow control */
8277 pf->hw.fc.requested_mode = I40E_FC_NONE;
8278
41c445ff
JB		 8279 err = i40e_init_adminq(hw);
8280 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8281 if (err) {
8282 dev_info(&pdev->dev,
8283 "init_adminq failed: %d expecting API %02x.%02x\n",
8284 err,
8285 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8286 goto err_pf_reset;
8287 }
8288
4eb3f768
SN		 8289 i40e_verify_eeprom(pf);
8290
6ff4ef86 8291 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8292 err = i40e_get_capabilities(pf);
8293 if (err)
8294 goto err_adminq_setup;
8295
8296 err = i40e_sw_init(pf);
8297 if (err) {
8298 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8299 goto err_sw_init;
8300 }
8301
8302 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8303 hw->func_caps.num_rx_qp,
8304 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8305 if (err) {
8306 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8307 goto err_init_lan_hmc;
8308 }
8309
8310 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8311 if (err) {
8312 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8313 err = -ENOENT;
8314 goto err_configure_lan_hmc;
8315 }
8316
8317 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8318 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8319 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8320 err = -EIO;
8321 goto err_mac_addr;
8322 }
8323 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8324 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8325
8326 pci_set_drvdata(pdev, pf);
8327 pci_save_state(pdev);
4e3b35b0
NP		 8328#ifdef CONFIG_I40E_DCB
8329 err = i40e_init_pf_dcb(pf);
8330 if (err) {
8331 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8332 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
014269ff 8333 /* Continue without DCB enabled */
4e3b35b0
NP		 8334 }
8335#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8336
8337 /* set up periodic task facility */
8338 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8339 pf->service_timer_period = HZ;
8340
8341 INIT_WORK(&pf->service_task, i40e_service_task);
8342 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8343 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8344 pf->link_check_timeout = jiffies;
8345
8e2773ae
SN		 8346 /* WoL defaults to disabled */
8347 pf->wol_en = false;
8348 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8349
41c445ff
JB		 8350 /* set up the main switch operations */
8351 i40e_determine_queue_usage(pf);
8352 i40e_init_interrupt_scheme(pf);
8353
8354 /* Set up the *vsi struct based on the number of VSIs in the HW,
8355 * and set up our local tracking of the MAIN PF vsi.
8356 */
8357 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8358 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8359 if (!pf->vsi) {
8360 err = -ENOMEM;
41c445ff 8361 goto err_switch_setup;
ed87ac09 8362 }
41c445ff 8363
bc7d338f 8364 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8365 if (err) {
8366 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8367 goto err_vsis;
8368 }
8a9eb7d3
SN		 8369 /* if FDIR VSI was set up, start it now */
8370 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8371 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8372 i40e_vsi_open(pf->vsi[i]);
8373 break;
8374 }
8375 }
41c445ff
JB		 8376
8377 /* The main driver is (mostly) up and happy. We need to set this state
8378 * before setting up the misc vector or we get a race and the vector
8379 * ends up disabled forever.
8380 */
8381 clear_bit(__I40E_DOWN, &pf->state);
8382
8383 /* In case of MSIX we are going to setup the misc vector right here
8384 * to handle admin queue events etc. In case of legacy and MSI
8385 * the misc functionality and queue processing is combined in
8386 * the same vector and that gets setup at open.
8387 */
8388 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8389 err = i40e_setup_misc_vector(pf);
8390 if (err) {
8391 dev_info(&pdev->dev,
8392 "setup of misc vector failed: %d\n", err);
8393 goto err_vsis;
8394 }
8395 }
8396
df805f62 8397#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8398 /* prep for VF support */
8399 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8400 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8401 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8402 u32 val;
8403
8404 /* disable link interrupts for VFs */
8405 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8406 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8407 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8408 i40e_flush(hw);
4aeec010
MW		 8409
8410 if (pci_num_vf(pdev)) {
8411 dev_info(&pdev->dev,
8412 "Active VFs found, allocating resources.\n");
8413 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8414 if (err)
8415 dev_info(&pdev->dev,
8416 "Error %d allocating resources for existing VFs\n",
8417 err);
8418 }
41c445ff 8419 }
df805f62 8420#endif /* CONFIG_PCI_IOV */
41c445ff 8421
93cd765b
ASJ		 8422 pfs_found++;
8423
41c445ff
JB		 8424 i40e_dbg_pf_init(pf);
8425
8426 /* tell the firmware that we're starting */
44033fac 8427 i40e_send_version(pf);
41c445ff
JB		 8428
8429 /* since everything's happy, start the service_task timer */
8430 mod_timer(&pf->service_timer,
8431 round_jiffies(jiffies + pf->service_timer_period));
8432
d4dfb81a
CS		 8433 /* Get the negotiated link width and speed from PCI config space */
8434 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8435
8436 i40e_set_pci_config_data(hw, link_status);
8437
69bfb110 8438 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8439 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8440 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8441 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8442 "Unknown"),
8443 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8444 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8445 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8446 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8447 "Unknown"));
8448
8449 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8450 hw->bus.speed < i40e_bus_speed_8000) {
8451 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8452 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8453 }
8454
0c22b3dd
JB		 8455 /* print a string summarizing features */
8456 i40e_print_features(pf);
8457
41c445ff
JB		 8458 return 0;
8459
8460 /* Unwind what we've done if something failed in the setup */
8461err_vsis:
8462 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8463 i40e_clear_interrupt_scheme(pf);
8464 kfree(pf->vsi);
04b03013
SN		 8465err_switch_setup:
8466 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8467 del_timer_sync(&pf->service_timer);
8468err_mac_addr:
8469err_configure_lan_hmc:
8470 (void)i40e_shutdown_lan_hmc(hw);
8471err_init_lan_hmc:
8472 kfree(pf->qp_pile);
8473 kfree(pf->irq_pile);
8474err_sw_init:
8475err_adminq_setup:
8476 (void)i40e_shutdown_adminq(hw);
8477err_pf_reset:
8478 iounmap(hw->hw_addr);
8479err_ioremap:
8480 kfree(pf);
8481err_pf_alloc:
8482 pci_disable_pcie_error_reporting(pdev);
8483 pci_release_selected_regions(pdev,
8484 pci_select_bars(pdev, IORESOURCE_MEM));
8485err_pci_reg:
8486err_dma:
8487 pci_disable_device(pdev);
8488 return err;
8489}
8490
8491/**
8492 * i40e_remove - Device removal routine
8493 * @pdev: PCI device information struct
8494 *
8495 * i40e_remove is called by the PCI subsystem to alert the driver
8496 * that is should release a PCI device. This could be caused by a
8497 * Hot-Plug event, or because the driver is going to be removed from
8498 * memory.
8499 **/
8500static void i40e_remove(struct pci_dev *pdev)
8501{
8502 struct i40e_pf *pf = pci_get_drvdata(pdev);
8503 i40e_status ret_code;
8504 u32 reg;
8505 int i;
8506
8507 i40e_dbg_pf_exit(pf);
8508
beb0dff1
JK		 8509 i40e_ptp_stop(pf);
8510
41c445ff
JB		 8511 /* no more scheduling of any task */
8512 set_bit(__I40E_DOWN, &pf->state);
8513 del_timer_sync(&pf->service_timer);
8514 cancel_work_sync(&pf->service_task);
8515
eb2d80bc
MW		 8516 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8517 i40e_free_vfs(pf);
8518 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8519 }
8520
41c445ff
JB		 8521 i40e_fdir_teardown(pf);
8522
8523 /* If there is a switch structure or any orphans, remove them.
8524 * This will leave only the PF's VSI remaining.
8525 */
8526 for (i = 0; i < I40E_MAX_VEB; i++) {
8527 if (!pf->veb[i])
8528 continue;
8529
8530 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8531 pf->veb[i]->uplink_seid == 0)
8532 i40e_switch_branch_release(pf->veb[i]);
8533 }
8534
8535 /* Now we can shutdown the PF's VSI, just before we kill
8536 * adminq and hmc.
8537 */
8538 if (pf->vsi[pf->lan_vsi])
8539 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8540
8541 i40e_stop_misc_vector(pf);
8542 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8543 synchronize_irq(pf->msix_entries[0].vector);
8544 free_irq(pf->msix_entries[0].vector, pf);
8545 }
8546
8547 /* shutdown and destroy the HMC */
8548 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8549 if (ret_code)
8550 dev_warn(&pdev->dev,
8551 "Failed to destroy the HMC resources: %d\n", ret_code);
8552
8553 /* shutdown the adminq */
41c445ff
JB		 8554 ret_code = i40e_shutdown_adminq(&pf->hw);
8555 if (ret_code)
8556 dev_warn(&pdev->dev,
8557 "Failed to destroy the Admin Queue resources: %d\n",
8558 ret_code);
8559
8560 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8561 i40e_clear_interrupt_scheme(pf);
8562 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8563 if (pf->vsi[i]) {
8564 i40e_vsi_clear_rings(pf->vsi[i]);
8565 i40e_vsi_clear(pf->vsi[i]);
8566 pf->vsi[i] = NULL;
8567 }
8568 }
8569
8570 for (i = 0; i < I40E_MAX_VEB; i++) {
8571 kfree(pf->veb[i]);
8572 pf->veb[i] = NULL;
8573 }
8574
8575 kfree(pf->qp_pile);
8576 kfree(pf->irq_pile);
8577 kfree(pf->sw_config);
8578 kfree(pf->vsi);
8579
8580 /* force a PF reset to clean anything leftover */
8581 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8582 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8583 i40e_flush(&pf->hw);
8584
8585 iounmap(pf->hw.hw_addr);
8586 kfree(pf);
8587 pci_release_selected_regions(pdev,
8588 pci_select_bars(pdev, IORESOURCE_MEM));
8589
8590 pci_disable_pcie_error_reporting(pdev);
8591 pci_disable_device(pdev);
8592}
8593
8594/**
8595 * i40e_pci_error_detected - warning that something funky happened in PCI land
8596 * @pdev: PCI device information struct
8597 *
8598 * Called to warn that something happened and the error handling steps
8599 * are in progress. Allows the driver to quiesce things, be ready for
8600 * remediation.
8601 **/
8602static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8603 enum pci_channel_state error)
8604{
8605 struct i40e_pf *pf = pci_get_drvdata(pdev);
8606
8607 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8608
8609 /* shutdown all operations */
9007bccd
SN		 8610 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8611 rtnl_lock();
8612 i40e_prep_for_reset(pf);
8613 rtnl_unlock();
8614 }
41c445ff
JB		 8615
8616 /* Request a slot reset */
8617 return PCI_ERS_RESULT_NEED_RESET;
8618}
8619
8620/**
8621 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8622 * @pdev: PCI device information struct
8623 *
8624 * Called to find if the driver can work with the device now that
8625 * the pci slot has been reset. If a basic connection seems good
8626 * (registers are readable and have sane content) then return a
8627 * happy little PCI_ERS_RESULT_xxx.
8628 **/
8629static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8630{
8631 struct i40e_pf *pf = pci_get_drvdata(pdev);
8632 pci_ers_result_t result;
8633 int err;
8634 u32 reg;
8635
8636 dev_info(&pdev->dev, "%s\n", __func__);
8637 if (pci_enable_device_mem(pdev)) {
8638 dev_info(&pdev->dev,
8639 "Cannot re-enable PCI device after reset.\n");
8640 result = PCI_ERS_RESULT_DISCONNECT;
8641 } else {
8642 pci_set_master(pdev);
8643 pci_restore_state(pdev);
8644 pci_save_state(pdev);
8645 pci_wake_from_d3(pdev, false);
8646
8647 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8648 if (reg == 0)
8649 result = PCI_ERS_RESULT_RECOVERED;
8650 else
8651 result = PCI_ERS_RESULT_DISCONNECT;
8652 }
8653
8654 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8655 if (err) {
8656 dev_info(&pdev->dev,
8657 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8658 err);
8659 /* non-fatal, continue */
8660 }
8661
8662 return result;
8663}
8664
8665/**
8666 * i40e_pci_error_resume - restart operations after PCI error recovery
8667 * @pdev: PCI device information struct
8668 *
8669 * Called to allow the driver to bring things back up after PCI error
8670 * and/or reset recovery has finished.
8671 **/
8672static void i40e_pci_error_resume(struct pci_dev *pdev)
8673{
8674 struct i40e_pf *pf = pci_get_drvdata(pdev);
8675
8676 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8677 if (test_bit(__I40E_SUSPENDED, &pf->state))
8678 return;
8679
8680 rtnl_lock();
41c445ff 8681 i40e_handle_reset_warning(pf);
9007bccd
SN		 8682 rtnl_lock();
8683}
8684
8685/**
8686 * i40e_shutdown - PCI callback for shutting down
8687 * @pdev: PCI device information struct
8688 **/
8689static void i40e_shutdown(struct pci_dev *pdev)
8690{
8691 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8692 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8693
8694 set_bit(__I40E_SUSPENDED, &pf->state);
8695 set_bit(__I40E_DOWN, &pf->state);
8696 rtnl_lock();
8697 i40e_prep_for_reset(pf);
8698 rtnl_unlock();
8699
8e2773ae
SN		 8700 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8701 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8702
9007bccd 8703 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8704 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8705 pci_set_power_state(pdev, PCI_D3hot);
8706 }
8707}
8708
8709#ifdef CONFIG_PM
8710/**
8711 * i40e_suspend - PCI callback for moving to D3
8712 * @pdev: PCI device information struct
8713 **/
8714static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8715{
8716 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8717 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8718
8719 set_bit(__I40E_SUSPENDED, &pf->state);
8720 set_bit(__I40E_DOWN, &pf->state);
8721 rtnl_lock();
8722 i40e_prep_for_reset(pf);
8723 rtnl_unlock();
8724
8e2773ae
SN		 8725 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8726 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8727
8728 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8729 pci_set_power_state(pdev, PCI_D3hot);
8730
8731 return 0;
41c445ff
JB		 8732}
8733
9007bccd
SN		 8734/**
8735 * i40e_resume - PCI callback for waking up from D3
8736 * @pdev: PCI device information struct
8737 **/
8738static int i40e_resume(struct pci_dev *pdev)
8739{
8740 struct i40e_pf *pf = pci_get_drvdata(pdev);
8741 u32 err;
8742
8743 pci_set_power_state(pdev, PCI_D0);
8744 pci_restore_state(pdev);
8745 /* pci_restore_state() clears dev->state_saves, so
8746 * call pci_save_state() again to restore it.
8747 */
8748 pci_save_state(pdev);
8749
8750 err = pci_enable_device_mem(pdev);
8751 if (err) {
8752 dev_err(&pdev->dev,
8753 "%s: Cannot enable PCI device from suspend\n",
8754 __func__);
8755 return err;
8756 }
8757 pci_set_master(pdev);
8758
8759 /* no wakeup events while running */
8760 pci_wake_from_d3(pdev, false);
8761
8762 /* handling the reset will rebuild the device state */
8763 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8764 clear_bit(__I40E_DOWN, &pf->state);
8765 rtnl_lock();
8766 i40e_reset_and_rebuild(pf, false);
8767 rtnl_unlock();
8768 }
8769
8770 return 0;
8771}
8772
8773#endif
41c445ff
JB		 8774static const struct pci_error_handlers i40e_err_handler = {
8775 .error_detected = i40e_pci_error_detected,
8776 .slot_reset = i40e_pci_error_slot_reset,
8777 .resume = i40e_pci_error_resume,
8778};
8779
8780static struct pci_driver i40e_driver = {
8781 .name = i40e_driver_name,
8782 .id_table = i40e_pci_tbl,
8783 .probe = i40e_probe,
8784 .remove = i40e_remove,
9007bccd
SN		 8785#ifdef CONFIG_PM
8786 .suspend = i40e_suspend,
8787 .resume = i40e_resume,
8788#endif
8789 .shutdown = i40e_shutdown,
41c445ff
JB		 8790 .err_handler = &i40e_err_handler,
8791 .sriov_configure = i40e_pci_sriov_configure,
8792};
8793
8794/**
8795 * i40e_init_module - Driver registration routine
8796 *
8797 * i40e_init_module is the first routine called when the driver is
8798 * loaded. All it does is register with the PCI subsystem.
8799 **/
8800static int __init i40e_init_module(void)
8801{
8802 pr_info("%s: %s - version %s\n", i40e_driver_name,
8803 i40e_driver_string, i40e_driver_version_str);
8804 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8805 i40e_dbg_init();
8806 return pci_register_driver(&i40e_driver);
8807}
8808module_init(i40e_init_module);
8809
8810/**
8811 * i40e_exit_module - Driver exit cleanup routine
8812 *
8813 * i40e_exit_module is called just before the driver is removed
8814 * from memory.
8815 **/
8816static void __exit i40e_exit_module(void)
8817{
8818 pci_unregister_driver(&i40e_driver);
8819 i40e_dbg_exit();
8820}
8821module_exit(i40e_exit_module);
Linux kernel - Deliverables
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