projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i40e/i40evf: Add a stat to track how many times we have to do a force WB
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
0e320516 42#define DRV_VERSION_BUILD 46
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 85 /* required last entry */
86 {0, }
87};
88MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
89
90#define I40E_MAX_VF_COUNT 128
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
96MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100/**
101 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
102 * @hw: pointer to the HW structure
103 * @mem: ptr to mem struct to fill out
104 * @size: size of memory requested
105 * @alignment: what to align the allocation to
106 **/
107int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
108 u64 size, u32 alignment)
109{
110 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
111
112 mem->size = ALIGN(size, alignment);
113 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
114 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 115 if (!mem->va)
116 return -ENOMEM;
41c445ff 117
93bc73b8 118 return 0;
41c445ff
JB		 119}
120
121/**
122 * i40e_free_dma_mem_d - OS specific memory free for shared code
123 * @hw: pointer to the HW structure
124 * @mem: ptr to mem struct to free
125 **/
126int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
127{
128 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
129
130 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
131 mem->va = NULL;
132 mem->pa = 0;
133 mem->size = 0;
134
135 return 0;
136}
137
138/**
139 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to fill out
142 * @size: size of memory requested
143 **/
144int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
145 u32 size)
146{
147 mem->size = size;
148 mem->va = kzalloc(size, GFP_KERNEL);
149
93bc73b8
JB		 150 if (!mem->va)
151 return -ENOMEM;
41c445ff 152
93bc73b8 153 return 0;
41c445ff
JB		 154}
155
156/**
157 * i40e_free_virt_mem_d - OS specific memory free for shared code
158 * @hw: pointer to the HW structure
159 * @mem: ptr to mem struct to free
160 **/
161int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
162{
163 /* it's ok to kfree a NULL pointer */
164 kfree(mem->va);
165 mem->va = NULL;
166 mem->size = 0;
167
168 return 0;
169}
170
171/**
172 * i40e_get_lump - find a lump of free generic resource
173 * @pf: board private structure
174 * @pile: the pile of resource to search
175 * @needed: the number of items needed
176 * @id: an owner id to stick on the items assigned
177 *
178 * Returns the base item index of the lump, or negative for error
179 *
180 * The search_hint trick and lack of advanced fit-finding only work
181 * because we're highly likely to have all the same size lump requests.
182 * Linear search time and any fragmentation should be minimal.
183 **/
184static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
185 u16 needed, u16 id)
186{
187 int ret = -ENOMEM;
ddf434ac 188 int i, j;
41c445ff
JB		 189
190 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
191 dev_info(&pf->pdev->dev,
192 "param err: pile=%p needed=%d id=0x%04x\n",
193 pile, needed, id);
194 return -EINVAL;
195 }
196
197 /* start the linear search with an imperfect hint */
198 i = pile->search_hint;
ddf434ac 199 while (i < pile->num_entries) {
41c445ff
JB		 200 /* skip already allocated entries */
201 if (pile->list[i] & I40E_PILE_VALID_BIT) {
202 i++;
203 continue;
204 }
205
206 /* do we have enough in this lump? */
207 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
208 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
209 break;
210 }
211
212 if (j == needed) {
213 /* there was enough, so assign it to the requestor */
214 for (j = 0; j < needed; j++)
215 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
216 ret = i;
217 pile->search_hint = i + j;
ddf434ac 218 break;
41c445ff 219 }
6995b36c
JB		 220
221 /* not enough, so skip over it and continue looking */
222 i += j;
41c445ff
JB		 223 }
224
225 return ret;
226}
227
228/**
229 * i40e_put_lump - return a lump of generic resource
230 * @pile: the pile of resource to search
231 * @index: the base item index
232 * @id: the owner id of the items assigned
233 *
234 * Returns the count of items in the lump
235 **/
236static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
237{
238 int valid_id = (id | I40E_PILE_VALID_BIT);
239 int count = 0;
240 int i;
241
242 if (!pile || index >= pile->num_entries)
243 return -EINVAL;
244
245 for (i = index;
246 i < pile->num_entries && pile->list[i] == valid_id;
247 i++) {
248 pile->list[i] = 0;
249 count++;
250 }
251
252 if (count && index < pile->search_hint)
253 pile->search_hint = index;
254
255 return count;
256}
257
fdf0e0bf
ASJ		 258/**
259 * i40e_find_vsi_from_id - searches for the vsi with the given id
260 * @pf - the pf structure to search for the vsi
261 * @id - id of the vsi it is searching for
262 **/
263struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
264{
265 int i;
266
267 for (i = 0; i < pf->num_alloc_vsi; i++)
268 if (pf->vsi[i] && (pf->vsi[i]->id == id))
269 return pf->vsi[i];
270
271 return NULL;
272}
273
41c445ff
JB		 274/**
275 * i40e_service_event_schedule - Schedule the service task to wake up
276 * @pf: board private structure
277 *
278 * If not already scheduled, this puts the task into the work queue
279 **/
280static void i40e_service_event_schedule(struct i40e_pf *pf)
281{
282 if (!test_bit(__I40E_DOWN, &pf->state) &&
283 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
284 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
285 schedule_work(&pf->service_task);
286}
287
288/**
289 * i40e_tx_timeout - Respond to a Tx Hang
290 * @netdev: network interface device structure
291 *
292 * If any port has noticed a Tx timeout, it is likely that the whole
293 * device is munged, not just the one netdev port, so go for the full
294 * reset.
295 **/
38e00438
VD		 296#ifdef I40E_FCOE
297void i40e_tx_timeout(struct net_device *netdev)
298#else
41c445ff 299static void i40e_tx_timeout(struct net_device *netdev)
38e00438 300#endif
41c445ff
JB		 301{
302 struct i40e_netdev_priv *np = netdev_priv(netdev);
303 struct i40e_vsi *vsi = np->vsi;
304 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 305 struct i40e_ring *tx_ring = NULL;
306 unsigned int i, hung_queue = 0;
307 u32 head, val;
41c445ff
JB		 308
309 pf->tx_timeout_count++;
310
b03a8c1f
KP		 311 /* find the stopped queue the same way the stack does */
312 for (i = 0; i < netdev->num_tx_queues; i++) {
313 struct netdev_queue *q;
314 unsigned long trans_start;
315
316 q = netdev_get_tx_queue(netdev, i);
317 trans_start = q->trans_start ? : netdev->trans_start;
318 if (netif_xmit_stopped(q) &&
319 time_after(jiffies,
320 (trans_start + netdev->watchdog_timeo))) {
321 hung_queue = i;
322 break;
323 }
324 }
325
326 if (i == netdev->num_tx_queues) {
327 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
328 } else {
329 /* now that we have an index, find the tx_ring struct */
330 for (i = 0; i < vsi->num_queue_pairs; i++) {
331 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
332 if (hung_queue ==
333 vsi->tx_rings[i]->queue_index) {
334 tx_ring = vsi->tx_rings[i];
335 break;
336 }
337 }
338 }
339 }
340
41c445ff 341 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 342 pf->tx_timeout_recovery_level = 1; /* reset after some time */
343 else if (time_before(jiffies,
344 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
345 return; /* don't do any new action before the next timeout */
346
347 if (tx_ring) {
348 head = i40e_get_head(tx_ring);
349 /* Read interrupt register */
350 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
351 val = rd32(&pf->hw,
352 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
353 tx_ring->vsi->base_vector - 1));
354 else
355 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
356
357 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
358 vsi->seid, hung_queue, tx_ring->next_to_clean,
359 head, tx_ring->next_to_use,
360 readl(tx_ring->tail), val);
361 }
362
41c445ff 363 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 364 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
365 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 366
367 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 368 case 1:
369 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
370 break;
371 case 2:
372 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
373 break;
374 case 3:
375 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
376 break;
377 default:
378 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 379 break;
380 }
b03a8c1f 381
41c445ff
JB		 382 i40e_service_event_schedule(pf);
383 pf->tx_timeout_recovery_level++;
384}
385
386/**
387 * i40e_release_rx_desc - Store the new tail and head values
388 * @rx_ring: ring to bump
389 * @val: new head index
390 **/
391static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
392{
393 rx_ring->next_to_use = val;
394
395 /* Force memory writes to complete before letting h/w
396 * know there are new descriptors to fetch. (Only
397 * applicable for weak-ordered memory model archs,
398 * such as IA-64).
399 */
400 wmb();
401 writel(val, rx_ring->tail);
402}
403
404/**
405 * i40e_get_vsi_stats_struct - Get System Network Statistics
406 * @vsi: the VSI we care about
407 *
408 * Returns the address of the device statistics structure.
409 * The statistics are actually updated from the service task.
410 **/
411struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
412{
413 return &vsi->net_stats;
414}
415
416/**
417 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
418 * @netdev: network interface device structure
419 *
420 * Returns the address of the device statistics structure.
421 * The statistics are actually updated from the service task.
422 **/
38e00438
VD		 423#ifdef I40E_FCOE
424struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
425 struct net_device *netdev,
426 struct rtnl_link_stats64 *stats)
427#else
41c445ff
JB		 428static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
429 struct net_device *netdev,
980e9b11 430 struct rtnl_link_stats64 *stats)
38e00438 431#endif
41c445ff
JB		 432{
433 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 434 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 435 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 436 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
437 int i;
438
bc7d338f
ASJ		 439 if (test_bit(__I40E_DOWN, &vsi->state))
440 return stats;
441
3c325ced
JB		 442 if (!vsi->tx_rings)
443 return stats;
444
980e9b11
AD		 445 rcu_read_lock();
446 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 447 u64 bytes, packets;
448 unsigned int start;
449
450 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
451 if (!tx_ring)
452 continue;
453
454 do {
57a7744e 455 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 456 packets = tx_ring->stats.packets;
457 bytes = tx_ring->stats.bytes;
57a7744e 458 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 459
460 stats->tx_packets += packets;
461 stats->tx_bytes += bytes;
462 rx_ring = &tx_ring[1];
463
464 do {
57a7744e 465 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 466 packets = rx_ring->stats.packets;
467 bytes = rx_ring->stats.bytes;
57a7744e 468 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 469
980e9b11
AD		 470 stats->rx_packets += packets;
471 stats->rx_bytes += bytes;
472 }
473 rcu_read_unlock();
474
a5282f44 475 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 476 stats->multicast = vsi_stats->multicast;
477 stats->tx_errors = vsi_stats->tx_errors;
478 stats->tx_dropped = vsi_stats->tx_dropped;
479 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 480 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 481 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
482 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 483
980e9b11 484 return stats;
41c445ff
JB		 485}
486
487/**
488 * i40e_vsi_reset_stats - Resets all stats of the given vsi
489 * @vsi: the VSI to have its stats reset
490 **/
491void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
492{
493 struct rtnl_link_stats64 *ns;
494 int i;
495
496 if (!vsi)
497 return;
498
499 ns = i40e_get_vsi_stats_struct(vsi);
500 memset(ns, 0, sizeof(*ns));
501 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
502 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
503 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 504 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 505 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 506 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 507 sizeof(vsi->rx_rings[i]->stats));
6995b36c 508 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 510 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 511 sizeof(vsi->tx_rings[i]->stats));
512 memset(&vsi->tx_rings[i]->tx_stats, 0,
513 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 514 }
8e9dca53 515 }
41c445ff
JB		 516 vsi->stat_offsets_loaded = false;
517}
518
519/**
b40c82e6 520 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 521 * @pf: the PF to be reset
522 **/
523void i40e_pf_reset_stats(struct i40e_pf *pf)
524{
e91fdf76
SN		 525 int i;
526
41c445ff
JB		 527 memset(&pf->stats, 0, sizeof(pf->stats));
528 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
529 pf->stat_offsets_loaded = false;
e91fdf76
SN		 530
531 for (i = 0; i < I40E_MAX_VEB; i++) {
532 if (pf->veb[i]) {
533 memset(&pf->veb[i]->stats, 0,
534 sizeof(pf->veb[i]->stats));
535 memset(&pf->veb[i]->stats_offsets, 0,
536 sizeof(pf->veb[i]->stats_offsets));
537 pf->veb[i]->stat_offsets_loaded = false;
538 }
539 }
41c445ff
JB		 540}
541
542/**
543 * i40e_stat_update48 - read and update a 48 bit stat from the chip
544 * @hw: ptr to the hardware info
545 * @hireg: the high 32 bit reg to read
546 * @loreg: the low 32 bit reg to read
547 * @offset_loaded: has the initial offset been loaded yet
548 * @offset: ptr to current offset value
549 * @stat: ptr to the stat
550 *
551 * Since the device stats are not reset at PFReset, they likely will not
552 * be zeroed when the driver starts. We'll save the first values read
553 * and use them as offsets to be subtracted from the raw values in order
554 * to report stats that count from zero. In the process, we also manage
555 * the potential roll-over.
556 **/
557static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
558 bool offset_loaded, u64 *offset, u64 *stat)
559{
560 u64 new_data;
561
ab60085e 562 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 563 new_data = rd32(hw, loreg);
564 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
565 } else {
566 new_data = rd64(hw, loreg);
567 }
568 if (!offset_loaded)
569 *offset = new_data;
570 if (likely(new_data >= *offset))
571 *stat = new_data - *offset;
572 else
41a1d04b 573 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 574 *stat &= 0xFFFFFFFFFFFFULL;
575}
576
577/**
578 * i40e_stat_update32 - read and update a 32 bit stat from the chip
579 * @hw: ptr to the hardware info
580 * @reg: the hw reg to read
581 * @offset_loaded: has the initial offset been loaded yet
582 * @offset: ptr to current offset value
583 * @stat: ptr to the stat
584 **/
585static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
586 bool offset_loaded, u64 *offset, u64 *stat)
587{
588 u32 new_data;
589
590 new_data = rd32(hw, reg);
591 if (!offset_loaded)
592 *offset = new_data;
593 if (likely(new_data >= *offset))
594 *stat = (u32)(new_data - *offset);
595 else
41a1d04b 596 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 597}
598
599/**
600 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
601 * @vsi: the VSI to be updated
602 **/
603void i40e_update_eth_stats(struct i40e_vsi *vsi)
604{
605 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
606 struct i40e_pf *pf = vsi->back;
607 struct i40e_hw *hw = &pf->hw;
608 struct i40e_eth_stats *oes;
609 struct i40e_eth_stats *es; /* device's eth stats */
610
611 es = &vsi->eth_stats;
612 oes = &vsi->eth_stats_offsets;
613
614 /* Gather up the stats that the hw collects */
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
618 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
619 vsi->stat_offsets_loaded,
620 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 621 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
622 vsi->stat_offsets_loaded,
623 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
624 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 627
628 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
629 I40E_GLV_GORCL(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->rx_bytes, &es->rx_bytes);
632 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
633 I40E_GLV_UPRCL(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_unicast, &es->rx_unicast);
636 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
637 I40E_GLV_MPRCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->rx_multicast, &es->rx_multicast);
640 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
641 I40E_GLV_BPRCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->rx_broadcast, &es->rx_broadcast);
644
645 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
646 I40E_GLV_GOTCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->tx_bytes, &es->tx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
650 I40E_GLV_UPTCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->tx_unicast, &es->tx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
654 I40E_GLV_MPTCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->tx_multicast, &es->tx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
658 I40E_GLV_BPTCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->tx_broadcast, &es->tx_broadcast);
661 vsi->stat_offsets_loaded = true;
662}
663
664/**
665 * i40e_update_veb_stats - Update Switch component statistics
666 * @veb: the VEB being updated
667 **/
668static void i40e_update_veb_stats(struct i40e_veb *veb)
669{
670 struct i40e_pf *pf = veb->pf;
671 struct i40e_hw *hw = &pf->hw;
672 struct i40e_eth_stats *oes;
673 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 674 struct i40e_veb_tc_stats *veb_oes;
675 struct i40e_veb_tc_stats *veb_es;
676 int i, idx = 0;
41c445ff
JB		 677
678 idx = veb->stats_idx;
679 es = &veb->stats;
680 oes = &veb->stats_offsets;
fe860afb
NP		 681 veb_es = &veb->tc_stats;
682 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 683
684 /* Gather up the stats that the hw collects */
685 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
686 veb->stat_offsets_loaded,
687 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 688 if (hw->revision_id > 0)
689 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_unknown_protocol,
692 &es->rx_unknown_protocol);
41c445ff
JB		 693 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_bytes, &es->rx_bytes);
696 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->rx_unicast, &es->rx_unicast);
699 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->rx_multicast, &es->rx_multicast);
702 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->rx_broadcast, &es->rx_broadcast);
705
706 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_bytes, &es->tx_bytes);
709 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->tx_unicast, &es->tx_unicast);
712 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->tx_multicast, &es->tx_multicast);
715 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
716 veb->stat_offsets_loaded,
717 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 718 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
719 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
720 I40E_GLVEBTC_RPCL(i, idx),
721 veb->stat_offsets_loaded,
722 &veb_oes->tc_rx_packets[i],
723 &veb_es->tc_rx_packets[i]);
724 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
725 I40E_GLVEBTC_RBCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_rx_bytes[i],
728 &veb_es->tc_rx_bytes[i]);
729 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
730 I40E_GLVEBTC_TPCL(i, idx),
731 veb->stat_offsets_loaded,
732 &veb_oes->tc_tx_packets[i],
733 &veb_es->tc_tx_packets[i]);
734 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
735 I40E_GLVEBTC_TBCL(i, idx),
736 veb->stat_offsets_loaded,
737 &veb_oes->tc_tx_bytes[i],
738 &veb_es->tc_tx_bytes[i]);
739 }
41c445ff
JB		 740 veb->stat_offsets_loaded = true;
741}
742
38e00438
VD		 743#ifdef I40E_FCOE
744/**
745 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
746 * @vsi: the VSI that is capable of doing FCoE
747 **/
748static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
749{
750 struct i40e_pf *pf = vsi->back;
751 struct i40e_hw *hw = &pf->hw;
752 struct i40e_fcoe_stats *ofs;
753 struct i40e_fcoe_stats *fs; /* device's eth stats */
754 int idx;
755
756 if (vsi->type != I40E_VSI_FCOE)
757 return;
758
759 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
760 fs = &vsi->fcoe_stats;
761 ofs = &vsi->fcoe_stats_offsets;
762
763 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
772 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
775 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
778 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
781 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->fcoe_last_error, &fs->fcoe_last_error);
784 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
785 vsi->fcoe_stat_offsets_loaded,
786 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
787
788 vsi->fcoe_stat_offsets_loaded = true;
789}
790
791#endif
41c445ff
JB		 792/**
793 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
794 * @pf: the corresponding PF
795 *
796 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
797 **/
798static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
799{
800 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
801 struct i40e_hw_port_stats *nsd = &pf->stats;
802 struct i40e_hw *hw = &pf->hw;
803 u64 xoff = 0;
41c445ff
JB		 804
805 if ((hw->fc.current_mode != I40E_FC_FULL) &&
806 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
807 return;
808
809 xoff = nsd->link_xoff_rx;
810 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
811 pf->stat_offsets_loaded,
812 &osd->link_xoff_rx, &nsd->link_xoff_rx);
813
814 /* No new LFC xoff rx */
815 if (!(nsd->link_xoff_rx - xoff))
816 return;
817
41c445ff
JB		 818}
819
820/**
821 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
822 * @pf: the corresponding PF
823 *
824 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
825 **/
826static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
827{
828 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
829 struct i40e_hw_port_stats *nsd = &pf->stats;
830 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
831 struct i40e_dcbx_config *dcb_cfg;
832 struct i40e_hw *hw = &pf->hw;
b03a8c1f 833 u16 i;
41c445ff
JB		 834 u8 tc;
835
836 dcb_cfg = &hw->local_dcbx_config;
837
e120814d
NP		 838 /* Collect Link XOFF stats when PFC is disabled */
839 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 840 i40e_update_link_xoff_rx(pf);
841 return;
842 }
843
844 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
845 u64 prio_xoff = nsd->priority_xoff_rx[i];
6995b36c 846
41c445ff
JB		 847 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
848 pf->stat_offsets_loaded,
849 &osd->priority_xoff_rx[i],
850 &nsd->priority_xoff_rx[i]);
851
852 /* No new PFC xoff rx */
853 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
854 continue;
855 /* Get the TC for given priority */
856 tc = dcb_cfg->etscfg.prioritytable[i];
857 xoff[tc] = true;
858 }
41c445ff
JB		 859}
860
861/**
7812fddc 862 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 863 * @vsi: the VSI to be updated
864 *
865 * There are a few instances where we store the same stat in a
866 * couple of different structs. This is partly because we have
867 * the netdev stats that need to be filled out, which is slightly
868 * different from the "eth_stats" defined by the chip and used in
7812fddc 869 * VF communications. We sort it out here.
41c445ff 870 **/
7812fddc 871static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 872{
873 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 874 struct rtnl_link_stats64 *ons;
875 struct rtnl_link_stats64 *ns; /* netdev stats */
876 struct i40e_eth_stats *oes;
877 struct i40e_eth_stats *es; /* device's eth stats */
878 u32 tx_restart, tx_busy;
bf00b376 879 struct i40e_ring *p;
41c445ff 880 u32 rx_page, rx_buf;
bf00b376
AA		 881 u64 bytes, packets;
882 unsigned int start;
2fc3d715 883 u64 tx_linearize;
164c9f54 884 u64 tx_force_wb;
41c445ff
JB		 885 u64 rx_p, rx_b;
886 u64 tx_p, tx_b;
41c445ff
JB		 887 u16 q;
888
889 if (test_bit(__I40E_DOWN, &vsi->state) ||
890 test_bit(__I40E_CONFIG_BUSY, &pf->state))
891 return;
892
893 ns = i40e_get_vsi_stats_struct(vsi);
894 ons = &vsi->net_stats_offsets;
895 es = &vsi->eth_stats;
896 oes = &vsi->eth_stats_offsets;
897
898 /* Gather up the netdev and vsi stats that the driver collects
899 * on the fly during packet processing
900 */
901 rx_b = rx_p = 0;
902 tx_b = tx_p = 0;
164c9f54 903 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 904 rx_page = 0;
905 rx_buf = 0;
980e9b11 906 rcu_read_lock();
41c445ff 907 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 908 /* locate Tx ring */
909 p = ACCESS_ONCE(vsi->tx_rings[q]);
910
911 do {
57a7744e 912 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 913 packets = p->stats.packets;
914 bytes = p->stats.bytes;
57a7744e 915 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 916 tx_b += bytes;
917 tx_p += packets;
918 tx_restart += p->tx_stats.restart_queue;
919 tx_busy += p->tx_stats.tx_busy;
2fc3d715 920 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 921 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 922
980e9b11
AD		 923 /* Rx queue is part of the same block as Tx queue */
924 p = &p[1];
925 do {
57a7744e 926 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 927 packets = p->stats.packets;
928 bytes = p->stats.bytes;
57a7744e 929 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 930 rx_b += bytes;
931 rx_p += packets;
420136cc
MW		 932 rx_buf += p->rx_stats.alloc_buff_failed;
933 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 934 }
980e9b11 935 rcu_read_unlock();
41c445ff
JB		 936 vsi->tx_restart = tx_restart;
937 vsi->tx_busy = tx_busy;
2fc3d715 938 vsi->tx_linearize = tx_linearize;
164c9f54 939 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 940 vsi->rx_page_failed = rx_page;
941 vsi->rx_buf_failed = rx_buf;
942
943 ns->rx_packets = rx_p;
944 ns->rx_bytes = rx_b;
945 ns->tx_packets = tx_p;
946 ns->tx_bytes = tx_b;
947
41c445ff 948 /* update netdev stats from eth stats */
7812fddc 949 i40e_update_eth_stats(vsi);
41c445ff
JB		 950 ons->tx_errors = oes->tx_errors;
951 ns->tx_errors = es->tx_errors;
952 ons->multicast = oes->rx_multicast;
953 ns->multicast = es->rx_multicast;
41a9e55c
SN		 954 ons->rx_dropped = oes->rx_discards;
955 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 956 ons->tx_dropped = oes->tx_discards;
957 ns->tx_dropped = es->tx_discards;
958
7812fddc 959 /* pull in a couple PF stats if this is the main vsi */
41c445ff 960 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 961 ns->rx_crc_errors = pf->stats.crc_errors;
962 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
963 ns->rx_length_errors = pf->stats.rx_length_errors;
964 }
965}
41c445ff 966
7812fddc 967/**
b40c82e6 968 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 969 * @pf: the PF to be updated
970 **/
971static void i40e_update_pf_stats(struct i40e_pf *pf)
972{
973 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
974 struct i40e_hw_port_stats *nsd = &pf->stats;
975 struct i40e_hw *hw = &pf->hw;
976 u32 val;
977 int i;
41c445ff 978
7812fddc
SN		 979 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
980 I40E_GLPRT_GORCL(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
983 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
984 I40E_GLPRT_GOTCL(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
987 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->eth.rx_discards,
990 &nsd->eth.rx_discards);
532d283d
SN		 991 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
992 I40E_GLPRT_UPRCL(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->eth.rx_unicast,
995 &nsd->eth.rx_unicast);
7812fddc
SN		 996 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
997 I40E_GLPRT_MPRCL(hw->port),
998 pf->stat_offsets_loaded,
999 &osd->eth.rx_multicast,
1000 &nsd->eth.rx_multicast);
532d283d
SN		 1001 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
1002 I40E_GLPRT_BPRCL(hw->port),
1003 pf->stat_offsets_loaded,
1004 &osd->eth.rx_broadcast,
1005 &nsd->eth.rx_broadcast);
1006 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1007 I40E_GLPRT_UPTCL(hw->port),
1008 pf->stat_offsets_loaded,
1009 &osd->eth.tx_unicast,
1010 &nsd->eth.tx_unicast);
1011 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1012 I40E_GLPRT_MPTCL(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->eth.tx_multicast,
1015 &nsd->eth.tx_multicast);
1016 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1017 I40E_GLPRT_BPTCL(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->eth.tx_broadcast,
1020 &nsd->eth.tx_broadcast);
41c445ff 1021
7812fddc
SN		 1022 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1023 pf->stat_offsets_loaded,
1024 &osd->tx_dropped_link_down,
1025 &nsd->tx_dropped_link_down);
41c445ff 1026
7812fddc
SN		 1027 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1028 pf->stat_offsets_loaded,
1029 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1030
7812fddc
SN		 1031 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1032 pf->stat_offsets_loaded,
1033 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1034
7812fddc
SN		 1035 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->mac_local_faults,
1038 &nsd->mac_local_faults);
1039 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->mac_remote_faults,
1042 &nsd->mac_remote_faults);
41c445ff 1043
7812fddc
SN		 1044 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1045 pf->stat_offsets_loaded,
1046 &osd->rx_length_errors,
1047 &nsd->rx_length_errors);
41c445ff 1048
7812fddc
SN		 1049 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->link_xon_rx, &nsd->link_xon_rx);
1052 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1053 pf->stat_offsets_loaded,
1054 &osd->link_xon_tx, &nsd->link_xon_tx);
1055 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1056 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1057 pf->stat_offsets_loaded,
1058 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1059
7812fddc
SN		 1060 for (i = 0; i < 8; i++) {
1061 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1062 pf->stat_offsets_loaded,
7812fddc
SN		 1063 &osd->priority_xon_rx[i],
1064 &nsd->priority_xon_rx[i]);
1065 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1066 pf->stat_offsets_loaded,
7812fddc
SN		 1067 &osd->priority_xon_tx[i],
1068 &nsd->priority_xon_tx[i]);
1069 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1070 pf->stat_offsets_loaded,
7812fddc
SN		 1071 &osd->priority_xoff_tx[i],
1072 &nsd->priority_xoff_tx[i]);
1073 i40e_stat_update32(hw,
1074 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1075 pf->stat_offsets_loaded,
7812fddc
SN		 1076 &osd->priority_xon_2_xoff[i],
1077 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1078 }
1079
7812fddc
SN		 1080 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1081 I40E_GLPRT_PRC64L(hw->port),
1082 pf->stat_offsets_loaded,
1083 &osd->rx_size_64, &nsd->rx_size_64);
1084 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1085 I40E_GLPRT_PRC127L(hw->port),
1086 pf->stat_offsets_loaded,
1087 &osd->rx_size_127, &nsd->rx_size_127);
1088 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1089 I40E_GLPRT_PRC255L(hw->port),
1090 pf->stat_offsets_loaded,
1091 &osd->rx_size_255, &nsd->rx_size_255);
1092 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1093 I40E_GLPRT_PRC511L(hw->port),
1094 pf->stat_offsets_loaded,
1095 &osd->rx_size_511, &nsd->rx_size_511);
1096 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1097 I40E_GLPRT_PRC1023L(hw->port),
1098 pf->stat_offsets_loaded,
1099 &osd->rx_size_1023, &nsd->rx_size_1023);
1100 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1101 I40E_GLPRT_PRC1522L(hw->port),
1102 pf->stat_offsets_loaded,
1103 &osd->rx_size_1522, &nsd->rx_size_1522);
1104 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1105 I40E_GLPRT_PRC9522L(hw->port),
1106 pf->stat_offsets_loaded,
1107 &osd->rx_size_big, &nsd->rx_size_big);
1108
1109 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1110 I40E_GLPRT_PTC64L(hw->port),
1111 pf->stat_offsets_loaded,
1112 &osd->tx_size_64, &nsd->tx_size_64);
1113 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1114 I40E_GLPRT_PTC127L(hw->port),
1115 pf->stat_offsets_loaded,
1116 &osd->tx_size_127, &nsd->tx_size_127);
1117 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1118 I40E_GLPRT_PTC255L(hw->port),
1119 pf->stat_offsets_loaded,
1120 &osd->tx_size_255, &nsd->tx_size_255);
1121 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1122 I40E_GLPRT_PTC511L(hw->port),
1123 pf->stat_offsets_loaded,
1124 &osd->tx_size_511, &nsd->tx_size_511);
1125 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1126 I40E_GLPRT_PTC1023L(hw->port),
1127 pf->stat_offsets_loaded,
1128 &osd->tx_size_1023, &nsd->tx_size_1023);
1129 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1130 I40E_GLPRT_PTC1522L(hw->port),
1131 pf->stat_offsets_loaded,
1132 &osd->tx_size_1522, &nsd->tx_size_1522);
1133 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1134 I40E_GLPRT_PTC9522L(hw->port),
1135 pf->stat_offsets_loaded,
1136 &osd->tx_size_big, &nsd->tx_size_big);
1137
1138 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1139 pf->stat_offsets_loaded,
1140 &osd->rx_undersize, &nsd->rx_undersize);
1141 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1142 pf->stat_offsets_loaded,
1143 &osd->rx_fragments, &nsd->rx_fragments);
1144 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1145 pf->stat_offsets_loaded,
1146 &osd->rx_oversize, &nsd->rx_oversize);
1147 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1148 pf->stat_offsets_loaded,
1149 &osd->rx_jabber, &nsd->rx_jabber);
1150
433c47de 1151 /* FDIR stats */
0bf4b1b0
ASJ		 1152 i40e_stat_update32(hw,
1153 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1154 pf->stat_offsets_loaded,
1155 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1156 i40e_stat_update32(hw,
1157 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1158 pf->stat_offsets_loaded,
1159 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1160 i40e_stat_update32(hw,
1161 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1162 pf->stat_offsets_loaded,
1163 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1164
7812fddc
SN		 1165 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1166 nsd->tx_lpi_status =
1167 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1168 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1169 nsd->rx_lpi_status =
1170 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1171 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1172 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1173 pf->stat_offsets_loaded,
1174 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1175 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1176 pf->stat_offsets_loaded,
1177 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1178
d0389e51
ASJ		 1179 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1180 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1181 nsd->fd_sb_status = true;
1182 else
1183 nsd->fd_sb_status = false;
1184
1185 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1186 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1187 nsd->fd_atr_status = true;
1188 else
1189 nsd->fd_atr_status = false;
1190
41c445ff
JB		 1191 pf->stat_offsets_loaded = true;
1192}
1193
7812fddc
SN		 1194/**
1195 * i40e_update_stats - Update the various statistics counters.
1196 * @vsi: the VSI to be updated
1197 *
1198 * Update the various stats for this VSI and its related entities.
1199 **/
1200void i40e_update_stats(struct i40e_vsi *vsi)
1201{
1202 struct i40e_pf *pf = vsi->back;
1203
1204 if (vsi == pf->vsi[pf->lan_vsi])
1205 i40e_update_pf_stats(pf);
1206
1207 i40e_update_vsi_stats(vsi);
38e00438
VD		 1208#ifdef I40E_FCOE
1209 i40e_update_fcoe_stats(vsi);
1210#endif
7812fddc
SN		 1211}
1212
41c445ff
JB		 1213/**
1214 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1215 * @vsi: the VSI to be searched
1216 * @macaddr: the MAC address
1217 * @vlan: the vlan
b40c82e6 1218 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1219 * @is_netdev: make sure its a netdev filter, else doesn't matter
1220 *
1221 * Returns ptr to the filter object or NULL
1222 **/
1223static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1224 u8 *macaddr, s16 vlan,
1225 bool is_vf, bool is_netdev)
1226{
1227 struct i40e_mac_filter *f;
1228
1229 if (!vsi || !macaddr)
1230 return NULL;
1231
1232 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1233 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1234 (vlan == f->vlan) &&
1235 (!is_vf || f->is_vf) &&
1236 (!is_netdev || f->is_netdev))
1237 return f;
1238 }
1239 return NULL;
1240}
1241
1242/**
1243 * i40e_find_mac - Find a mac addr in the macvlan filters list
1244 * @vsi: the VSI to be searched
1245 * @macaddr: the MAC address we are searching for
b40c82e6 1246 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1247 * @is_netdev: make sure its a netdev filter, else doesn't matter
1248 *
1249 * Returns the first filter with the provided MAC address or NULL if
1250 * MAC address was not found
1251 **/
1252struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1253 bool is_vf, bool is_netdev)
1254{
1255 struct i40e_mac_filter *f;
1256
1257 if (!vsi || !macaddr)
1258 return NULL;
1259
1260 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1261 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1262 (!is_vf || f->is_vf) &&
1263 (!is_netdev || f->is_netdev))
1264 return f;
1265 }
1266 return NULL;
1267}
1268
1269/**
1270 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1271 * @vsi: the VSI to be searched
1272 *
1273 * Returns true if VSI is in vlan mode or false otherwise
1274 **/
1275bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1276{
1277 struct i40e_mac_filter *f;
1278
1279 /* Only -1 for all the filters denotes not in vlan mode
1280 * so we have to go through all the list in order to make sure
1281 */
1282 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1283 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1284 return true;
1285 }
1286
1287 return false;
1288}
1289
1290/**
1291 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1292 * @vsi: the VSI to be searched
1293 * @macaddr: the mac address to be filtered
b40c82e6 1294 * @is_vf: true if it is a VF
41c445ff
JB		 1295 * @is_netdev: true if it is a netdev
1296 *
1297 * Goes through all the macvlan filters and adds a
1298 * macvlan filter for each unique vlan that already exists
1299 *
1300 * Returns first filter found on success, else NULL
1301 **/
1302struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1303 bool is_vf, bool is_netdev)
1304{
1305 struct i40e_mac_filter *f;
1306
1307 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1308 if (vsi->info.pvid)
1309 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1310 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1311 is_vf, is_netdev)) {
1312 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1313 is_vf, is_netdev))
41c445ff
JB		 1314 return NULL;
1315 }
1316 }
1317
1318 return list_first_entry_or_null(&vsi->mac_filter_list,
1319 struct i40e_mac_filter, list);
1320}
1321
8c27d42e
GR		 1322/**
1323 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1324 * @vsi: the PF Main VSI - inappropriate for any other VSI
1325 * @macaddr: the MAC address
30650cc5
SN		 1326 *
1327 * Some older firmware configurations set up a default promiscuous VLAN
1328 * filter that needs to be removed.
8c27d42e 1329 **/
30650cc5 1330static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1331{
1332 struct i40e_aqc_remove_macvlan_element_data element;
1333 struct i40e_pf *pf = vsi->back;
f1c7e72e 1334 i40e_status ret;
8c27d42e
GR		 1335
1336 /* Only appropriate for the PF main VSI */
1337 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1338 return -EINVAL;
8c27d42e 1339
30650cc5 1340 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1341 ether_addr_copy(element.mac_addr, macaddr);
1342 element.vlan_tag = 0;
1343 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1344 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1345 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1346 if (ret)
30650cc5
SN		 1347 return -ENOENT;
1348
1349 return 0;
8c27d42e
GR		 1350}
1351
41c445ff
JB		 1352/**
1353 * i40e_add_filter - Add a mac/vlan filter to the VSI
1354 * @vsi: the VSI to be searched
1355 * @macaddr: the MAC address
1356 * @vlan: the vlan
b40c82e6 1357 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1358 * @is_netdev: make sure its a netdev filter, else doesn't matter
1359 *
1360 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1361 *
1362 * NOTE: This function is expected to be called with mac_filter_list_lock
1363 * being held.
41c445ff
JB		 1364 **/
1365struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1366 u8 *macaddr, s16 vlan,
1367 bool is_vf, bool is_netdev)
1368{
1369 struct i40e_mac_filter *f;
1370
1371 if (!vsi || !macaddr)
1372 return NULL;
1373
1374 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1375 if (!f) {
1376 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1377 if (!f)
1378 goto add_filter_out;
1379
9a173901 1380 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1381 f->vlan = vlan;
1382 f->changed = true;
1383
1384 INIT_LIST_HEAD(&f->list);
1385 list_add(&f->list, &vsi->mac_filter_list);
1386 }
1387
1388 /* increment counter and add a new flag if needed */
1389 if (is_vf) {
1390 if (!f->is_vf) {
1391 f->is_vf = true;
1392 f->counter++;
1393 }
1394 } else if (is_netdev) {
1395 if (!f->is_netdev) {
1396 f->is_netdev = true;
1397 f->counter++;
1398 }
1399 } else {
1400 f->counter++;
1401 }
1402
1403 /* changed tells sync_filters_subtask to
1404 * push the filter down to the firmware
1405 */
1406 if (f->changed) {
1407 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1408 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1409 }
1410
1411add_filter_out:
1412 return f;
1413}
1414
1415/**
1416 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1417 * @vsi: the VSI to be searched
1418 * @macaddr: the MAC address
1419 * @vlan: the vlan
b40c82e6 1420 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1421 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1422 *
1423 * NOTE: This function is expected to be called with mac_filter_list_lock
1424 * being held.
41c445ff
JB		 1425 **/
1426void i40e_del_filter(struct i40e_vsi *vsi,
1427 u8 *macaddr, s16 vlan,
1428 bool is_vf, bool is_netdev)
1429{
1430 struct i40e_mac_filter *f;
1431
1432 if (!vsi || !macaddr)
1433 return;
1434
1435 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1436 if (!f || f->counter == 0)
1437 return;
1438
1439 if (is_vf) {
1440 if (f->is_vf) {
1441 f->is_vf = false;
1442 f->counter--;
1443 }
1444 } else if (is_netdev) {
1445 if (f->is_netdev) {
1446 f->is_netdev = false;
1447 f->counter--;
1448 }
1449 } else {
b40c82e6 1450 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1451 int min_f = 0;
6995b36c 1452
41c445ff
JB		 1453 min_f += (f->is_vf ? 1 : 0);
1454 min_f += (f->is_netdev ? 1 : 0);
1455
1456 if (f->counter > min_f)
1457 f->counter--;
1458 }
1459
1460 /* counter == 0 tells sync_filters_subtask to
1461 * remove the filter from the firmware's list
1462 */
1463 if (f->counter == 0) {
1464 f->changed = true;
1465 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1466 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1467 }
1468}
1469
1470/**
1471 * i40e_set_mac - NDO callback to set mac address
1472 * @netdev: network interface device structure
1473 * @p: pointer to an address structure
1474 *
1475 * Returns 0 on success, negative on failure
1476 **/
38e00438
VD		 1477#ifdef I40E_FCOE
1478int i40e_set_mac(struct net_device *netdev, void *p)
1479#else
41c445ff 1480static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1481#endif
41c445ff
JB		 1482{
1483 struct i40e_netdev_priv *np = netdev_priv(netdev);
1484 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1485 struct i40e_pf *pf = vsi->back;
1486 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1487 struct sockaddr *addr = p;
1488 struct i40e_mac_filter *f;
1489
1490 if (!is_valid_ether_addr(addr->sa_data))
1491 return -EADDRNOTAVAIL;
1492
30650cc5
SN		 1493 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1494 netdev_info(netdev, "already using mac address %pM\n",
1495 addr->sa_data);
1496 return 0;
1497 }
41c445ff 1498
80f6428f
ASJ		 1499 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1500 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1501 return -EADDRNOTAVAIL;
1502
30650cc5
SN		 1503 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1504 netdev_info(netdev, "returning to hw mac address %pM\n",
1505 hw->mac.addr);
1506 else
1507 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1508
41c445ff
JB		 1509 if (vsi->type == I40E_VSI_MAIN) {
1510 i40e_status ret;
6995b36c 1511
41c445ff 1512 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1513 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1514 addr->sa_data, NULL);
1515 if (ret) {
1516 netdev_info(netdev,
1517 "Addr change for Main VSI failed: %d\n",
1518 ret);
1519 return -EADDRNOTAVAIL;
1520 }
41c445ff
JB		 1521 }
1522
30650cc5
SN		 1523 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1524 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1525
30650cc5
SN		 1526 memset(&element, 0, sizeof(element));
1527 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1528 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1529 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1530 } else {
21659035 1531 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1532 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1533 false, false);
21659035 1534 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1535 }
41c445ff 1536
30650cc5
SN		 1537 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1538 struct i40e_aqc_add_macvlan_element_data element;
1539
1540 memset(&element, 0, sizeof(element));
1541 ether_addr_copy(element.mac_addr, hw->mac.addr);
1542 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1543 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1544 } else {
21659035 1545 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1546 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1547 false, false);
1548 if (f)
1549 f->is_laa = true;
21659035 1550 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1551 }
1552
30e2561b 1553 i40e_sync_vsi_filters(vsi, false);
30650cc5 1554 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1555
1556 return 0;
1557}
1558
1559/**
1560 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1561 * @vsi: the VSI being setup
1562 * @ctxt: VSI context structure
1563 * @enabled_tc: Enabled TCs bitmap
1564 * @is_add: True if called before Add VSI
1565 *
1566 * Setup VSI queue mapping for enabled traffic classes.
1567 **/
38e00438
VD		 1568#ifdef I40E_FCOE
1569void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1570 struct i40e_vsi_context *ctxt,
1571 u8 enabled_tc,
1572 bool is_add)
1573#else
41c445ff
JB		 1574static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1575 struct i40e_vsi_context *ctxt,
1576 u8 enabled_tc,
1577 bool is_add)
38e00438 1578#endif
41c445ff
JB		 1579{
1580 struct i40e_pf *pf = vsi->back;
1581 u16 sections = 0;
1582 u8 netdev_tc = 0;
1583 u16 numtc = 0;
1584 u16 qcount;
1585 u8 offset;
1586 u16 qmap;
1587 int i;
4e3b35b0 1588 u16 num_tc_qps = 0;
41c445ff
JB		 1589
1590 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1591 offset = 0;
1592
1593 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1594 /* Find numtc from enabled TC bitmap */
1595 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1596 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1597 numtc++;
1598 }
1599 if (!numtc) {
1600 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1601 numtc = 1;
1602 }
1603 } else {
1604 /* At least TC0 is enabled in case of non-DCB case */
1605 numtc = 1;
1606 }
1607
1608 vsi->tc_config.numtc = numtc;
1609 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1610 /* Number of queues per enabled TC */
7f9ff476
AS		 1611 /* In MFP case we can have a much lower count of MSIx
1612 * vectors available and so we need to lower the used
1613 * q count.
1614 */
26cdc443
ASJ		 1615 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1616 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1617 else
1618 qcount = vsi->alloc_queue_pairs;
7f9ff476 1619 num_tc_qps = qcount / numtc;
e25d00b8 1620 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1621
1622 /* Setup queue offset/count for all TCs for given VSI */
1623 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1624 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1625 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1626 /* TC is enabled */
41c445ff
JB		 1627 int pow, num_qps;
1628
41c445ff
JB		 1629 switch (vsi->type) {
1630 case I40E_VSI_MAIN:
4e3b35b0 1631 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1632 break;
38e00438
VD		 1633#ifdef I40E_FCOE
1634 case I40E_VSI_FCOE:
1635 qcount = num_tc_qps;
1636 break;
1637#endif
41c445ff
JB		 1638 case I40E_VSI_FDIR:
1639 case I40E_VSI_SRIOV:
1640 case I40E_VSI_VMDQ2:
1641 default:
4e3b35b0 1642 qcount = num_tc_qps;
41c445ff
JB		 1643 WARN_ON(i != 0);
1644 break;
1645 }
4e3b35b0
NP		 1646 vsi->tc_config.tc_info[i].qoffset = offset;
1647 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1648
1e200e4a 1649 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1650 num_qps = qcount;
41c445ff 1651 pow = 0;
41a1d04b 1652 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1653 pow++;
1654 num_qps >>= 1;
1655 }
1656
1657 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1658 qmap =
1659 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1660 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1661
4e3b35b0 1662 offset += qcount;
41c445ff
JB		 1663 } else {
1664 /* TC is not enabled so set the offset to
1665 * default queue and allocate one queue
1666 * for the given TC.
1667 */
1668 vsi->tc_config.tc_info[i].qoffset = 0;
1669 vsi->tc_config.tc_info[i].qcount = 1;
1670 vsi->tc_config.tc_info[i].netdev_tc = 0;
1671
1672 qmap = 0;
1673 }
1674 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1675 }
1676
1677 /* Set actual Tx/Rx queue pairs */
1678 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1679 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1680 if (vsi->req_queue_pairs > 0)
1681 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1682 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1683 vsi->num_queue_pairs = pf->num_lan_msix;
1684 }
41c445ff
JB		 1685
1686 /* Scheduler section valid can only be set for ADD VSI */
1687 if (is_add) {
1688 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1689
1690 ctxt->info.up_enable_bits = enabled_tc;
1691 }
1692 if (vsi->type == I40E_VSI_SRIOV) {
1693 ctxt->info.mapping_flags |=
1694 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1695 for (i = 0; i < vsi->num_queue_pairs; i++)
1696 ctxt->info.queue_mapping[i] =
1697 cpu_to_le16(vsi->base_queue + i);
1698 } else {
1699 ctxt->info.mapping_flags |=
1700 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1701 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1702 }
1703 ctxt->info.valid_sections |= cpu_to_le16(sections);
1704}
1705
1706/**
1707 * i40e_set_rx_mode - NDO callback to set the netdev filters
1708 * @netdev: network interface device structure
1709 **/
38e00438
VD		 1710#ifdef I40E_FCOE
1711void i40e_set_rx_mode(struct net_device *netdev)
1712#else
41c445ff 1713static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1714#endif
41c445ff
JB		 1715{
1716 struct i40e_netdev_priv *np = netdev_priv(netdev);
1717 struct i40e_mac_filter *f, *ftmp;
1718 struct i40e_vsi *vsi = np->vsi;
1719 struct netdev_hw_addr *uca;
1720 struct netdev_hw_addr *mca;
1721 struct netdev_hw_addr *ha;
1722
21659035
KP		 1723 spin_lock_bh(&vsi->mac_filter_list_lock);
1724
41c445ff
JB		 1725 /* add addr if not already in the filter list */
1726 netdev_for_each_uc_addr(uca, netdev) {
1727 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1728 if (i40e_is_vsi_in_vlan(vsi))
1729 i40e_put_mac_in_vlan(vsi, uca->addr,
1730 false, true);
1731 else
1732 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1733 false, true);
1734 }
1735 }
1736
1737 netdev_for_each_mc_addr(mca, netdev) {
1738 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1739 if (i40e_is_vsi_in_vlan(vsi))
1740 i40e_put_mac_in_vlan(vsi, mca->addr,
1741 false, true);
1742 else
1743 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1744 false, true);
1745 }
1746 }
1747
1748 /* remove filter if not in netdev list */
1749 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1750
1751 if (!f->is_netdev)
1752 continue;
1753
2f41f335
SN		 1754 netdev_for_each_mc_addr(mca, netdev)
1755 if (ether_addr_equal(mca->addr, f->macaddr))
1756 goto bottom_of_search_loop;
41c445ff 1757
2f41f335
SN		 1758 netdev_for_each_uc_addr(uca, netdev)
1759 if (ether_addr_equal(uca->addr, f->macaddr))
1760 goto bottom_of_search_loop;
1761
1762 for_each_dev_addr(netdev, ha)
1763 if (ether_addr_equal(ha->addr, f->macaddr))
1764 goto bottom_of_search_loop;
1765
1766 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1767 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1768
1769bottom_of_search_loop:
1770 continue;
41c445ff 1771 }
21659035 1772 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1773
1774 /* check for other flag changes */
1775 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1776 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1777 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1778 }
1779}
1780
21659035
KP		 1781/**
1782 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1783 * @src: source MAC filter entry to be clones
1784 *
1785 * Returns the pointer to newly cloned MAC filter entry or NULL
1786 * in case of error
1787 **/
1788static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1789 struct i40e_mac_filter *src)
1790{
1791 struct i40e_mac_filter *f;
1792
1793 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1794 if (!f)
1795 return NULL;
1796 *f = *src;
1797
1798 INIT_LIST_HEAD(&f->list);
1799
1800 return f;
1801}
1802
1803/**
1804 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1805 * @vsi: pointer to vsi struct
1806 * @from: Pointer to list which contains MAC filter entries - changes to
1807 * those entries needs to be undone.
1808 *
1809 * MAC filter entries from list were slated to be removed from device.
1810 **/
1811static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1812 struct list_head *from)
1813{
1814 struct i40e_mac_filter *f, *ftmp;
1815
1816 list_for_each_entry_safe(f, ftmp, from, list) {
1817 f->changed = true;
1818 /* Move the element back into MAC filter list*/
1819 list_move_tail(&f->list, &vsi->mac_filter_list);
1820 }
1821}
1822
1823/**
1824 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1825 * @vsi: pointer to vsi struct
1826 *
1827 * MAC filter entries from list were slated to be added from device.
1828 **/
1829static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1830{
1831 struct i40e_mac_filter *f, *ftmp;
1832
1833 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1834 if (!f->changed && f->counter)
1835 f->changed = true;
1836 }
1837}
1838
1839/**
1840 * i40e_cleanup_add_list - Deletes the element from add list and release
1841 * memory
1842 * @add_list: Pointer to list which contains MAC filter entries
1843 **/
1844static void i40e_cleanup_add_list(struct list_head *add_list)
1845{
1846 struct i40e_mac_filter *f, *ftmp;
1847
1848 list_for_each_entry_safe(f, ftmp, add_list, list) {
1849 list_del(&f->list);
1850 kfree(f);
1851 }
1852}
1853
41c445ff
JB		 1854/**
1855 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1856 * @vsi: ptr to the VSI
30e2561b 1857 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1858 *
1859 * Push any outstanding VSI filter changes through the AdminQ.
1860 *
1861 * Returns 0 or error value
1862 **/
30e2561b 1863int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff 1864{
21659035
KP		 1865 struct list_head tmp_del_list, tmp_add_list;
1866 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1867 bool promisc_forced_on = false;
1868 bool add_happened = false;
1869 int filter_list_len = 0;
1870 u32 changed_flags = 0;
21659035 1871 bool err_cond = false;
f1c7e72e 1872 i40e_status ret = 0;
41c445ff
JB		 1873 struct i40e_pf *pf;
1874 int num_add = 0;
1875 int num_del = 0;
f1c7e72e 1876 int aq_err = 0;
41c445ff
JB		 1877 u16 cmd_flags;
1878
1879 /* empty array typed pointers, kcalloc later */
1880 struct i40e_aqc_add_macvlan_element_data *add_list;
1881 struct i40e_aqc_remove_macvlan_element_data *del_list;
1882
1883 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1884 usleep_range(1000, 2000);
1885 pf = vsi->back;
1886
1887 if (vsi->netdev) {
1888 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1889 vsi->current_netdev_flags = vsi->netdev->flags;
1890 }
1891
21659035
KP		 1892 INIT_LIST_HEAD(&tmp_del_list);
1893 INIT_LIST_HEAD(&tmp_add_list);
1894
41c445ff
JB		 1895 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1896 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1897
21659035 1898 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1899 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1900 if (!f->changed)
1901 continue;
1902
1903 if (f->counter != 0)
1904 continue;
1905 f->changed = false;
21659035
KP		 1906
1907 /* Move the element into temporary del_list */
1908 list_move_tail(&f->list, &tmp_del_list);
1909 }
1910
1911 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1912 if (!f->changed)
1913 continue;
1914
1915 if (f->counter == 0)
1916 continue;
1917 f->changed = false;
1918
1919 /* Clone MAC filter entry and add into temporary list */
1920 fclone = i40e_mac_filter_entry_clone(f);
1921 if (!fclone) {
1922 err_cond = true;
1923 break;
1924 }
1925 list_add_tail(&fclone->list, &tmp_add_list);
1926 }
1927
1928 /* if failed to clone MAC filter entry - undo */
1929 if (err_cond) {
1930 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1931 i40e_undo_add_filter_entries(vsi);
1932 }
1933 spin_unlock_bh(&vsi->mac_filter_list_lock);
1934
1935 if (err_cond)
1936 i40e_cleanup_add_list(&tmp_add_list);
1937 }
1938
1939 /* Now process 'del_list' outside the lock */
1940 if (!list_empty(&tmp_del_list)) {
1941 filter_list_len = pf->hw.aq.asq_buf_size /
1942 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1943 del_list = kcalloc(filter_list_len,
1944 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1945 GFP_KERNEL);
1946 if (!del_list) {
1947 i40e_cleanup_add_list(&tmp_add_list);
1948
1949 /* Undo VSI's MAC filter entry element updates */
1950 spin_lock_bh(&vsi->mac_filter_list_lock);
1951 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1952 i40e_undo_add_filter_entries(vsi);
1953 spin_unlock_bh(&vsi->mac_filter_list_lock);
1954 return -ENOMEM;
1955 }
1956
1957 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1958 cmd_flags = 0;
1959
1960 /* add to delete list */
9a173901 1961 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1962 del_list[num_del].vlan_tag =
1963 cpu_to_le16((u16)(f->vlan ==
1964 I40E_VLAN_ANY ? 0 : f->vlan));
1965
41c445ff
JB		 1966 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1967 del_list[num_del].flags = cmd_flags;
1968 num_del++;
1969
41c445ff
JB		 1970 /* flush a full buffer */
1971 if (num_del == filter_list_len) {
f1c7e72e
SN		 1972 ret = i40e_aq_remove_macvlan(&pf->hw,
1973 vsi->seid, del_list, num_del,
1974 NULL);
1975 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1976 num_del = 0;
1977 memset(del_list, 0, sizeof(*del_list));
1978
f1c7e72e 1979 if (ret && aq_err != I40E_AQ_RC_ENOENT)
21659035
KP		 1980 dev_err(&pf->pdev->dev,
1981 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1982 i40e_stat_str(&pf->hw, ret),
1983 i40e_aq_str(&pf->hw, aq_err));
41c445ff 1984 }
21659035
KP		 1985 /* Release memory for MAC filter entries which were
1986 * synced up with HW.
1987 */
1988 list_del(&f->list);
1989 kfree(f);
41c445ff 1990 }
21659035 1991
41c445ff 1992 if (num_del) {
f1c7e72e 1993 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1994 del_list, num_del, NULL);
f1c7e72e 1995 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1996 num_del = 0;
1997
f1c7e72e 1998 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1999 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2000 "ignoring delete macvlan error, err %s aq_err %s\n",
2001 i40e_stat_str(&pf->hw, ret),
2002 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2003 }
2004
2005 kfree(del_list);
2006 del_list = NULL;
21659035
KP		 2007 }
2008
2009 if (!list_empty(&tmp_add_list)) {
41c445ff
JB		 2010
2011 /* do all the adds now */
2012 filter_list_len = pf->hw.aq.asq_buf_size /
2013 sizeof(struct i40e_aqc_add_macvlan_element_data),
2014 add_list = kcalloc(filter_list_len,
2015 sizeof(struct i40e_aqc_add_macvlan_element_data),
2016 GFP_KERNEL);
21659035
KP		 2017 if (!add_list) {
2018 /* Purge element from temporary lists */
2019 i40e_cleanup_add_list(&tmp_add_list);
2020
2021 /* Undo add filter entries from VSI MAC filter list */
2022 spin_lock_bh(&vsi->mac_filter_list_lock);
2023 i40e_undo_add_filter_entries(vsi);
2024 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 2025 return -ENOMEM;
21659035 2026 }
41c445ff 2027
21659035 2028 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2029
41c445ff
JB		 2030 add_happened = true;
2031 cmd_flags = 0;
2032
2033 /* add to add array */
9a173901 2034 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2035 add_list[num_add].vlan_tag =
2036 cpu_to_le16(
2037 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2038 add_list[num_add].queue_number = 0;
2039
2040 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2041 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2042 num_add++;
2043
2044 /* flush a full buffer */
2045 if (num_add == filter_list_len) {
f1c7e72e
SN		 2046 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2047 add_list, num_add,
2048 NULL);
2049 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2050 num_add = 0;
2051
f1c7e72e 2052 if (ret)
41c445ff
JB		 2053 break;
2054 memset(add_list, 0, sizeof(*add_list));
2055 }
21659035
KP		 2056 /* Entries from tmp_add_list were cloned from MAC
2057 * filter list, hence clean those cloned entries
2058 */
2059 list_del(&f->list);
2060 kfree(f);
41c445ff 2061 }
21659035 2062
41c445ff 2063 if (num_add) {
f1c7e72e
SN		 2064 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2065 add_list, num_add, NULL);
2066 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2067 num_add = 0;
2068 }
2069 kfree(add_list);
2070 add_list = NULL;
2071
f1c7e72e 2072 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 2073 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2074 "add filter failed, err %s aq_err %s\n",
2075 i40e_stat_str(&pf->hw, ret),
2076 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2077 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2078 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2079 &vsi->state)) {
2080 promisc_forced_on = true;
2081 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2082 &vsi->state);
2083 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2084 }
2085 }
2086 }
2087
2088 /* check for changes in promiscuous modes */
2089 if (changed_flags & IFF_ALLMULTI) {
2090 bool cur_multipromisc;
6995b36c 2091
41c445ff 2092 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 2093 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2094 vsi->seid,
2095 cur_multipromisc,
2096 NULL);
2097 if (ret)
41c445ff 2098 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2099 "set multi promisc failed, err %s aq_err %s\n",
2100 i40e_stat_str(&pf->hw, ret),
2101 i40e_aq_str(&pf->hw,
2102 pf->hw.aq.asq_last_status));
41c445ff
JB		 2103 }
2104 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2105 bool cur_promisc;
6995b36c 2106
41c445ff
JB		 2107 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2108 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2109 &vsi->state));
92faef85
ASJ		 2110 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2111 /* set defport ON for Main VSI instead of true promisc
2112 * this way we will get all unicast/multicast and VLAN
2113 * promisc behavior but will not get VF or VMDq traffic
2114 * replicated on the Main VSI.
2115 */
2116 if (pf->cur_promisc != cur_promisc) {
2117 pf->cur_promisc = cur_promisc;
30e2561b
AS		 2118 if (grab_rtnl)
2119 i40e_do_reset_safe(pf,
2120 BIT(__I40E_PF_RESET_REQUESTED));
2121 else
2122 i40e_do_reset(pf,
92faef85
ASJ		 2123 BIT(__I40E_PF_RESET_REQUESTED));
2124 }
2125 } else {
2126 ret = i40e_aq_set_vsi_unicast_promiscuous(
2127 &vsi->back->hw,
f1c7e72e
SN		 2128 vsi->seid,
2129 cur_promisc, NULL);
92faef85
ASJ		 2130 if (ret)
2131 dev_info(&pf->pdev->dev,
2132 "set unicast promisc failed, err %d, aq_err %d\n",
2133 ret, pf->hw.aq.asq_last_status);
2134 ret = i40e_aq_set_vsi_multicast_promiscuous(
2135 &vsi->back->hw,
2136 vsi->seid,
2137 cur_promisc, NULL);
2138 if (ret)
2139 dev_info(&pf->pdev->dev,
2140 "set multicast promisc failed, err %d, aq_err %d\n",
2141 ret, pf->hw.aq.asq_last_status);
2142 }
f1c7e72e
SN		 2143 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2144 vsi->seid,
2145 cur_promisc, NULL);
2146 if (ret)
1a10370a 2147 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2148 "set brdcast promisc failed, err %s, aq_err %s\n",
2149 i40e_stat_str(&pf->hw, ret),
2150 i40e_aq_str(&pf->hw,
2151 pf->hw.aq.asq_last_status));
41c445ff
JB		 2152 }
2153
2154 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2155 return 0;
2156}
2157
2158/**
2159 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2160 * @pf: board private structure
2161 **/
2162static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2163{
2164 int v;
2165
2166 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2167 return;
2168 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2169
505682cd 2170 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2171 if (pf->vsi[v] &&
2172 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2173 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2174 }
2175}
2176
2177/**
2178 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2179 * @netdev: network interface device structure
2180 * @new_mtu: new value for maximum frame size
2181 *
2182 * Returns 0 on success, negative on failure
2183 **/
2184static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2185{
2186 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2187 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2188 struct i40e_vsi *vsi = np->vsi;
2189
2190 /* MTU < 68 is an error and causes problems on some kernels */
2191 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2192 return -EINVAL;
2193
2194 netdev_info(netdev, "changing MTU from %d to %d\n",
2195 netdev->mtu, new_mtu);
2196 netdev->mtu = new_mtu;
2197 if (netif_running(netdev))
2198 i40e_vsi_reinit_locked(vsi);
2199
2200 return 0;
2201}
2202
beb0dff1
JK		 2203/**
2204 * i40e_ioctl - Access the hwtstamp interface
2205 * @netdev: network interface device structure
2206 * @ifr: interface request data
2207 * @cmd: ioctl command
2208 **/
2209int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2210{
2211 struct i40e_netdev_priv *np = netdev_priv(netdev);
2212 struct i40e_pf *pf = np->vsi->back;
2213
2214 switch (cmd) {
2215 case SIOCGHWTSTAMP:
2216 return i40e_ptp_get_ts_config(pf, ifr);
2217 case SIOCSHWTSTAMP:
2218 return i40e_ptp_set_ts_config(pf, ifr);
2219 default:
2220 return -EOPNOTSUPP;
2221 }
2222}
2223
41c445ff
JB		 2224/**
2225 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2226 * @vsi: the vsi being adjusted
2227 **/
2228void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2229{
2230 struct i40e_vsi_context ctxt;
2231 i40e_status ret;
2232
2233 if ((vsi->info.valid_sections &
2234 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2235 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2236 return; /* already enabled */
2237
2238 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2239 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2240 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2241
2242 ctxt.seid = vsi->seid;
1a2f6248 2243 ctxt.info = vsi->info;
41c445ff
JB		 2244 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2245 if (ret) {
2246 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2247 "update vlan stripping failed, err %s aq_err %s\n",
2248 i40e_stat_str(&vsi->back->hw, ret),
2249 i40e_aq_str(&vsi->back->hw,
2250 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2251 }
2252}
2253
2254/**
2255 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2256 * @vsi: the vsi being adjusted
2257 **/
2258void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2259{
2260 struct i40e_vsi_context ctxt;
2261 i40e_status ret;
2262
2263 if ((vsi->info.valid_sections &
2264 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2265 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2266 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2267 return; /* already disabled */
2268
2269 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2270 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2271 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2272
2273 ctxt.seid = vsi->seid;
1a2f6248 2274 ctxt.info = vsi->info;
41c445ff
JB		 2275 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2276 if (ret) {
2277 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2278 "update vlan stripping failed, err %s aq_err %s\n",
2279 i40e_stat_str(&vsi->back->hw, ret),
2280 i40e_aq_str(&vsi->back->hw,
2281 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2282 }
2283}
2284
2285/**
2286 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2287 * @netdev: network interface to be adjusted
2288 * @features: netdev features to test if VLAN offload is enabled or not
2289 **/
2290static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2291{
2292 struct i40e_netdev_priv *np = netdev_priv(netdev);
2293 struct i40e_vsi *vsi = np->vsi;
2294
2295 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2296 i40e_vlan_stripping_enable(vsi);
2297 else
2298 i40e_vlan_stripping_disable(vsi);
2299}
2300
2301/**
2302 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2303 * @vsi: the vsi being configured
2304 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2305 **/
2306int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2307{
2308 struct i40e_mac_filter *f, *add_f;
2309 bool is_netdev, is_vf;
41c445ff
JB		 2310
2311 is_vf = (vsi->type == I40E_VSI_SRIOV);
2312 is_netdev = !!(vsi->netdev);
2313
21659035
KP		 2314 /* Locked once because all functions invoked below iterates list*/
2315 spin_lock_bh(&vsi->mac_filter_list_lock);
2316
41c445ff
JB		 2317 if (is_netdev) {
2318 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2319 is_vf, is_netdev);
2320 if (!add_f) {
2321 dev_info(&vsi->back->pdev->dev,
2322 "Could not add vlan filter %d for %pM\n",
2323 vid, vsi->netdev->dev_addr);
21659035 2324 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2325 return -ENOMEM;
2326 }
2327 }
2328
2329 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2330 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2331 if (!add_f) {
2332 dev_info(&vsi->back->pdev->dev,
2333 "Could not add vlan filter %d for %pM\n",
2334 vid, f->macaddr);
21659035 2335 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2336 return -ENOMEM;
2337 }
2338 }
2339
41c445ff
JB		 2340 /* Now if we add a vlan tag, make sure to check if it is the first
2341 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2342 * with 0, so we now accept untagged and specified tagged traffic
2343 * (and not any taged and untagged)
2344 */
2345 if (vid > 0) {
2346 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2347 I40E_VLAN_ANY,
2348 is_vf, is_netdev)) {
2349 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2350 I40E_VLAN_ANY, is_vf, is_netdev);
2351 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2352 is_vf, is_netdev);
2353 if (!add_f) {
2354 dev_info(&vsi->back->pdev->dev,
2355 "Could not add filter 0 for %pM\n",
2356 vsi->netdev->dev_addr);
21659035 2357 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2358 return -ENOMEM;
2359 }
2360 }
8d82a7c5 2361 }
41c445ff 2362
8d82a7c5
GR		 2363 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2364 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2365 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2366 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2367 is_vf, is_netdev))
2368 continue;
2369 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2370 is_vf, is_netdev);
2371 add_f = i40e_add_filter(vsi, f->macaddr,
2372 0, is_vf, is_netdev);
2373 if (!add_f) {
2374 dev_info(&vsi->back->pdev->dev,
2375 "Could not add filter 0 for %pM\n",
2376 f->macaddr);
2377 spin_unlock_bh(&vsi->mac_filter_list_lock);
2378 return -ENOMEM;
41c445ff
JB		 2379 }
2380 }
41c445ff
JB		 2381 }
2382
21659035
KP		 2383 /* Make sure to release before sync_vsi_filter because that
2384 * function will lock/unlock as necessary
2385 */
2386 spin_unlock_bh(&vsi->mac_filter_list_lock);
2387
80f6428f
ASJ		 2388 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2389 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2390 return 0;
2391
30e2561b 2392 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2393}
2394
2395/**
2396 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2397 * @vsi: the vsi being configured
2398 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2399 *
2400 * Return: 0 on success or negative otherwise
41c445ff
JB		 2401 **/
2402int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2403{
2404 struct net_device *netdev = vsi->netdev;
2405 struct i40e_mac_filter *f, *add_f;
2406 bool is_vf, is_netdev;
2407 int filter_count = 0;
41c445ff
JB		 2408
2409 is_vf = (vsi->type == I40E_VSI_SRIOV);
2410 is_netdev = !!(netdev);
2411
21659035
KP		 2412 /* Locked once because all functions invoked below iterates list */
2413 spin_lock_bh(&vsi->mac_filter_list_lock);
2414
41c445ff
JB		 2415 if (is_netdev)
2416 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2417
2418 list_for_each_entry(f, &vsi->mac_filter_list, list)
2419 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2420
41c445ff
JB		 2421 /* go through all the filters for this VSI and if there is only
2422 * vid == 0 it means there are no other filters, so vid 0 must
2423 * be replaced with -1. This signifies that we should from now
2424 * on accept any traffic (with any tag present, or untagged)
2425 */
2426 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2427 if (is_netdev) {
2428 if (f->vlan &&
2429 ether_addr_equal(netdev->dev_addr, f->macaddr))
2430 filter_count++;
2431 }
2432
2433 if (f->vlan)
2434 filter_count++;
2435 }
2436
2437 if (!filter_count && is_netdev) {
2438 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2439 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2440 is_vf, is_netdev);
2441 if (!f) {
2442 dev_info(&vsi->back->pdev->dev,
2443 "Could not add filter %d for %pM\n",
2444 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2445 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2446 return -ENOMEM;
2447 }
2448 }
2449
2450 if (!filter_count) {
2451 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2452 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2453 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2454 is_vf, is_netdev);
41c445ff
JB		 2455 if (!add_f) {
2456 dev_info(&vsi->back->pdev->dev,
2457 "Could not add filter %d for %pM\n",
2458 I40E_VLAN_ANY, f->macaddr);
21659035 2459 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2460 return -ENOMEM;
2461 }
2462 }
2463 }
2464
21659035
KP		 2465 /* Make sure to release before sync_vsi_filter because that
2466 * function with lock/unlock as necessary
2467 */
2468 spin_unlock_bh(&vsi->mac_filter_list_lock);
2469
80f6428f
ASJ		 2470 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2471 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2472 return 0;
2473
30e2561b 2474 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2475}
2476
2477/**
2478 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2479 * @netdev: network interface to be adjusted
2480 * @vid: vlan id to be added
078b5876
JB		 2481 *
2482 * net_device_ops implementation for adding vlan ids
41c445ff 2483 **/
38e00438
VD		 2484#ifdef I40E_FCOE
2485int i40e_vlan_rx_add_vid(struct net_device *netdev,
2486 __always_unused __be16 proto, u16 vid)
2487#else
41c445ff
JB		 2488static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2489 __always_unused __be16 proto, u16 vid)
38e00438 2490#endif
41c445ff
JB		 2491{
2492 struct i40e_netdev_priv *np = netdev_priv(netdev);
2493 struct i40e_vsi *vsi = np->vsi;
078b5876 2494 int ret = 0;
41c445ff
JB		 2495
2496 if (vid > 4095)
078b5876
JB		 2497 return -EINVAL;
2498
2499 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2500
6982d429
ASJ		 2501 /* If the network stack called us with vid = 0 then
2502 * it is asking to receive priority tagged packets with
2503 * vlan id 0. Our HW receives them by default when configured
2504 * to receive untagged packets so there is no need to add an
2505 * extra filter for vlan 0 tagged packets.
41c445ff 2506 */
6982d429
ASJ		 2507 if (vid)
2508 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2509
078b5876
JB		 2510 if (!ret && (vid < VLAN_N_VID))
2511 set_bit(vid, vsi->active_vlans);
41c445ff 2512
078b5876 2513 return ret;
41c445ff
JB		 2514}
2515
2516/**
2517 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2518 * @netdev: network interface to be adjusted
2519 * @vid: vlan id to be removed
078b5876 2520 *
fdfd943e 2521 * net_device_ops implementation for removing vlan ids
41c445ff 2522 **/
38e00438
VD		 2523#ifdef I40E_FCOE
2524int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2525 __always_unused __be16 proto, u16 vid)
2526#else
41c445ff
JB		 2527static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2528 __always_unused __be16 proto, u16 vid)
38e00438 2529#endif
41c445ff
JB		 2530{
2531 struct i40e_netdev_priv *np = netdev_priv(netdev);
2532 struct i40e_vsi *vsi = np->vsi;
2533
078b5876
JB		 2534 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2535
41c445ff
JB		 2536 /* return code is ignored as there is nothing a user
2537 * can do about failure to remove and a log message was
078b5876 2538 * already printed from the other function
41c445ff
JB		 2539 */
2540 i40e_vsi_kill_vlan(vsi, vid);
2541
2542 clear_bit(vid, vsi->active_vlans);
078b5876 2543
41c445ff
JB		 2544 return 0;
2545}
2546
2547/**
2548 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2549 * @vsi: the vsi being brought back up
2550 **/
2551static void i40e_restore_vlan(struct i40e_vsi *vsi)
2552{
2553 u16 vid;
2554
2555 if (!vsi->netdev)
2556 return;
2557
2558 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2559
2560 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2561 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2562 vid);
2563}
2564
2565/**
2566 * i40e_vsi_add_pvid - Add pvid for the VSI
2567 * @vsi: the vsi being adjusted
2568 * @vid: the vlan id to set as a PVID
2569 **/
dcae29be 2570int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2571{
2572 struct i40e_vsi_context ctxt;
f1c7e72e 2573 i40e_status ret;
41c445ff
JB		 2574
2575 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2576 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2577 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2578 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2579 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2580
2581 ctxt.seid = vsi->seid;
1a2f6248 2582 ctxt.info = vsi->info;
f1c7e72e
SN		 2583 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2584 if (ret) {
41c445ff 2585 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2586 "add pvid failed, err %s aq_err %s\n",
2587 i40e_stat_str(&vsi->back->hw, ret),
2588 i40e_aq_str(&vsi->back->hw,
2589 vsi->back->hw.aq.asq_last_status));
dcae29be 2590 return -ENOENT;
41c445ff
JB		 2591 }
2592
dcae29be 2593 return 0;
41c445ff
JB		 2594}
2595
2596/**
2597 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2598 * @vsi: the vsi being adjusted
2599 *
2600 * Just use the vlan_rx_register() service to put it back to normal
2601 **/
2602void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2603{
6c12fcbf
GR		 2604 i40e_vlan_stripping_disable(vsi);
2605
41c445ff 2606 vsi->info.pvid = 0;
41c445ff
JB		 2607}
2608
2609/**
2610 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2611 * @vsi: ptr to the VSI
2612 *
2613 * If this function returns with an error, then it's possible one or
2614 * more of the rings is populated (while the rest are not). It is the
2615 * callers duty to clean those orphaned rings.
2616 *
2617 * Return 0 on success, negative on failure
2618 **/
2619static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2620{
2621 int i, err = 0;
2622
2623 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2624 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2625
2626 return err;
2627}
2628
2629/**
2630 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2631 * @vsi: ptr to the VSI
2632 *
2633 * Free VSI's transmit software resources
2634 **/
2635static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2636{
2637 int i;
2638
8e9dca53
GR		 2639 if (!vsi->tx_rings)
2640 return;
2641
41c445ff 2642 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2643 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2644 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2645}
2646
2647/**
2648 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2649 * @vsi: ptr to the VSI
2650 *
2651 * If this function returns with an error, then it's possible one or
2652 * more of the rings is populated (while the rest are not). It is the
2653 * callers duty to clean those orphaned rings.
2654 *
2655 * Return 0 on success, negative on failure
2656 **/
2657static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2658{
2659 int i, err = 0;
2660
2661 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2662 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2663#ifdef I40E_FCOE
2664 i40e_fcoe_setup_ddp_resources(vsi);
2665#endif
41c445ff
JB		 2666 return err;
2667}
2668
2669/**
2670 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2671 * @vsi: ptr to the VSI
2672 *
2673 * Free all receive software resources
2674 **/
2675static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2676{
2677 int i;
2678
8e9dca53
GR		 2679 if (!vsi->rx_rings)
2680 return;
2681
41c445ff 2682 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2683 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2684 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2685#ifdef I40E_FCOE
2686 i40e_fcoe_free_ddp_resources(vsi);
2687#endif
41c445ff
JB		 2688}
2689
3ffa037d
NP		 2690/**
2691 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2692 * @ring: The Tx ring to configure
2693 *
2694 * This enables/disables XPS for a given Tx descriptor ring
2695 * based on the TCs enabled for the VSI that ring belongs to.
2696 **/
2697static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2698{
2699 struct i40e_vsi *vsi = ring->vsi;
2700 cpumask_var_t mask;
2701
9a660eea
JB		 2702 if (!ring->q_vector || !ring->netdev)
2703 return;
2704
2705 /* Single TC mode enable XPS */
2706 if (vsi->tc_config.numtc <= 1) {
2707 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2708 netif_set_xps_queue(ring->netdev,
2709 &ring->q_vector->affinity_mask,
2710 ring->queue_index);
9a660eea
JB		 2711 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2712 /* Disable XPS to allow selection based on TC */
2713 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2714 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2715 free_cpumask_var(mask);
3ffa037d
NP		 2716 }
2717}
2718
41c445ff
JB		 2719/**
2720 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2721 * @ring: The Tx ring to configure
2722 *
2723 * Configure the Tx descriptor ring in the HMC context.
2724 **/
2725static int i40e_configure_tx_ring(struct i40e_ring *ring)
2726{
2727 struct i40e_vsi *vsi = ring->vsi;
2728 u16 pf_q = vsi->base_queue + ring->queue_index;
2729 struct i40e_hw *hw = &vsi->back->hw;
2730 struct i40e_hmc_obj_txq tx_ctx;
2731 i40e_status err = 0;
2732 u32 qtx_ctl = 0;
2733
2734 /* some ATR related tx ring init */
60ea5f83 2735 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2736 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2737 ring->atr_count = 0;
2738 } else {
2739 ring->atr_sample_rate = 0;
2740 }
2741
3ffa037d
NP		 2742 /* configure XPS */
2743 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2744
2745 /* clear the context structure first */
2746 memset(&tx_ctx, 0, sizeof(tx_ctx));
2747
2748 tx_ctx.new_context = 1;
2749 tx_ctx.base = (ring->dma / 128);
2750 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2751 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2752 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2753#ifdef I40E_FCOE
2754 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2755#endif
beb0dff1 2756 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2757 /* FDIR VSI tx ring can still use RS bit and writebacks */
2758 if (vsi->type != I40E_VSI_FDIR)
2759 tx_ctx.head_wb_ena = 1;
2760 tx_ctx.head_wb_addr = ring->dma +
2761 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2762
2763 /* As part of VSI creation/update, FW allocates certain
2764 * Tx arbitration queue sets for each TC enabled for
2765 * the VSI. The FW returns the handles to these queue
2766 * sets as part of the response buffer to Add VSI,
2767 * Update VSI, etc. AQ commands. It is expected that
2768 * these queue set handles be associated with the Tx
2769 * queues by the driver as part of the TX queue context
2770 * initialization. This has to be done regardless of
2771 * DCB as by default everything is mapped to TC0.
2772 */
2773 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2774 tx_ctx.rdylist_act = 0;
2775
2776 /* clear the context in the HMC */
2777 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2778 if (err) {
2779 dev_info(&vsi->back->pdev->dev,
2780 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2781 ring->queue_index, pf_q, err);
2782 return -ENOMEM;
2783 }
2784
2785 /* set the context in the HMC */
2786 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2787 if (err) {
2788 dev_info(&vsi->back->pdev->dev,
2789 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2790 ring->queue_index, pf_q, err);
2791 return -ENOMEM;
2792 }
2793
2794 /* Now associate this queue with this PCI function */
7a28d885 2795 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2796 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2797 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2798 I40E_QTX_CTL_VFVM_INDX_MASK;
2799 } else {
9d8bf547 2800 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2801 }
2802
13fd9774
SN		 2803 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2804 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2805 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2806 i40e_flush(hw);
2807
41c445ff
JB		 2808 /* cache tail off for easier writes later */
2809 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2810
2811 return 0;
2812}
2813
2814/**
2815 * i40e_configure_rx_ring - Configure a receive ring context
2816 * @ring: The Rx ring to configure
2817 *
2818 * Configure the Rx descriptor ring in the HMC context.
2819 **/
2820static int i40e_configure_rx_ring(struct i40e_ring *ring)
2821{
2822 struct i40e_vsi *vsi = ring->vsi;
2823 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2824 u16 pf_q = vsi->base_queue + ring->queue_index;
2825 struct i40e_hw *hw = &vsi->back->hw;
2826 struct i40e_hmc_obj_rxq rx_ctx;
2827 i40e_status err = 0;
2828
2829 ring->state = 0;
2830
2831 /* clear the context structure first */
2832 memset(&rx_ctx, 0, sizeof(rx_ctx));
2833
2834 ring->rx_buf_len = vsi->rx_buf_len;
2835 ring->rx_hdr_len = vsi->rx_hdr_len;
2836
2837 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2838 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2839
2840 rx_ctx.base = (ring->dma / 128);
2841 rx_ctx.qlen = ring->count;
2842
2843 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2844 set_ring_16byte_desc_enabled(ring);
2845 rx_ctx.dsize = 0;
2846 } else {
2847 rx_ctx.dsize = 1;
2848 }
2849
2850 rx_ctx.dtype = vsi->dtype;
2851 if (vsi->dtype) {
2852 set_ring_ps_enabled(ring);
2853 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2854 I40E_RX_SPLIT_IP |
2855 I40E_RX_SPLIT_TCP_UDP |
2856 I40E_RX_SPLIT_SCTP;
2857 } else {
2858 rx_ctx.hsplit_0 = 0;
2859 }
2860
2861 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2862 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2863 if (hw->revision_id == 0)
2864 rx_ctx.lrxqthresh = 0;
2865 else
2866 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2867 rx_ctx.crcstrip = 1;
2868 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2869 /* this controls whether VLAN is stripped from inner headers */
2870 rx_ctx.showiv = 0;
38e00438
VD		 2871#ifdef I40E_FCOE
2872 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2873#endif
acb3676b
CS		 2874 /* set the prefena field to 1 because the manual says to */
2875 rx_ctx.prefena = 1;
41c445ff
JB		 2876
2877 /* clear the context in the HMC */
2878 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2879 if (err) {
2880 dev_info(&vsi->back->pdev->dev,
2881 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2882 ring->queue_index, pf_q, err);
2883 return -ENOMEM;
2884 }
2885
2886 /* set the context in the HMC */
2887 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2888 if (err) {
2889 dev_info(&vsi->back->pdev->dev,
2890 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2891 ring->queue_index, pf_q, err);
2892 return -ENOMEM;
2893 }
2894
2895 /* cache tail for quicker writes, and clear the reg before use */
2896 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2897 writel(0, ring->tail);
2898
a132af24
MW		 2899 if (ring_is_ps_enabled(ring)) {
2900 i40e_alloc_rx_headers(ring);
2901 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2902 } else {
2903 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2904 }
41c445ff
JB		 2905
2906 return 0;
2907}
2908
2909/**
2910 * i40e_vsi_configure_tx - Configure the VSI for Tx
2911 * @vsi: VSI structure describing this set of rings and resources
2912 *
2913 * Configure the Tx VSI for operation.
2914 **/
2915static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2916{
2917 int err = 0;
2918 u16 i;
2919
9f65e15b
AD		 2920 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2921 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2922
2923 return err;
2924}
2925
2926/**
2927 * i40e_vsi_configure_rx - Configure the VSI for Rx
2928 * @vsi: the VSI being configured
2929 *
2930 * Configure the Rx VSI for operation.
2931 **/
2932static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2933{
2934 int err = 0;
2935 u16 i;
2936
2937 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2938 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2939 + ETH_FCS_LEN + VLAN_HLEN;
2940 else
2941 vsi->max_frame = I40E_RXBUFFER_2048;
2942
2943 /* figure out correct receive buffer length */
2944 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2945 I40E_FLAG_RX_PS_ENABLED)) {
2946 case I40E_FLAG_RX_1BUF_ENABLED:
2947 vsi->rx_hdr_len = 0;
2948 vsi->rx_buf_len = vsi->max_frame;
2949 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2950 break;
2951 case I40E_FLAG_RX_PS_ENABLED:
2952 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2953 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2954 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2955 break;
2956 default:
2957 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2958 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2959 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2960 break;
2961 }
2962
38e00438
VD		 2963#ifdef I40E_FCOE
2964 /* setup rx buffer for FCoE */
2965 if ((vsi->type == I40E_VSI_FCOE) &&
2966 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2967 vsi->rx_hdr_len = 0;
2968 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2969 vsi->max_frame = I40E_RXBUFFER_3072;
2970 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2971 }
2972
2973#endif /* I40E_FCOE */
41c445ff
JB		 2974 /* round up for the chip's needs */
2975 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2976 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2977 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2978 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2979
2980 /* set up individual rings */
2981 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2982 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2983
2984 return err;
2985}
2986
2987/**
2988 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2989 * @vsi: ptr to the VSI
2990 **/
2991static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2992{
e7046ee1 2993 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2994 u16 qoffset, qcount;
2995 int i, n;
2996
cd238a3e
PN		 2997 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2998 /* Reset the TC information */
2999 for (i = 0; i < vsi->num_queue_pairs; i++) {
3000 rx_ring = vsi->rx_rings[i];
3001 tx_ring = vsi->tx_rings[i];
3002 rx_ring->dcb_tc = 0;
3003 tx_ring->dcb_tc = 0;
3004 }
3005 }
41c445ff
JB		 3006
3007 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3008 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3009 continue;
3010
3011 qoffset = vsi->tc_config.tc_info[n].qoffset;
3012 qcount = vsi->tc_config.tc_info[n].qcount;
3013 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3014 rx_ring = vsi->rx_rings[i];
3015 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3016 rx_ring->dcb_tc = n;
3017 tx_ring->dcb_tc = n;
3018 }
3019 }
3020}
3021
3022/**
3023 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3024 * @vsi: ptr to the VSI
3025 **/
3026static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3027{
3028 if (vsi->netdev)
3029 i40e_set_rx_mode(vsi->netdev);
3030}
3031
17a73f6b
JG		 3032/**
3033 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3034 * @vsi: Pointer to the targeted VSI
3035 *
3036 * This function replays the hlist on the hw where all the SB Flow Director
3037 * filters were saved.
3038 **/
3039static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3040{
3041 struct i40e_fdir_filter *filter;
3042 struct i40e_pf *pf = vsi->back;
3043 struct hlist_node *node;
3044
55a5e60b
ASJ		 3045 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3046 return;
3047
17a73f6b
JG		 3048 hlist_for_each_entry_safe(filter, node,
3049 &pf->fdir_filter_list, fdir_node) {
3050 i40e_add_del_fdir(vsi, filter, true);
3051 }
3052}
3053
41c445ff
JB		 3054/**
3055 * i40e_vsi_configure - Set up the VSI for action
3056 * @vsi: the VSI being configured
3057 **/
3058static int i40e_vsi_configure(struct i40e_vsi *vsi)
3059{
3060 int err;
3061
3062 i40e_set_vsi_rx_mode(vsi);
3063 i40e_restore_vlan(vsi);
3064 i40e_vsi_config_dcb_rings(vsi);
3065 err = i40e_vsi_configure_tx(vsi);
3066 if (!err)
3067 err = i40e_vsi_configure_rx(vsi);
3068
3069 return err;
3070}
3071
3072/**
3073 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3074 * @vsi: the VSI being configured
3075 **/
3076static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3077{
3078 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3079 struct i40e_hw *hw = &pf->hw;
3080 u16 vector;
3081 int i, q;
41c445ff
JB		 3082 u32 qp;
3083
3084 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3085 * and PFINT_LNKLSTn registers, e.g.:
3086 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3087 */
3088 qp = vsi->base_queue;
3089 vector = vsi->base_vector;
493fb300 3090 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3091 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3092
ee2319cf 3093 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3094 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3095 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3096 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3097 q_vector->rx.itr);
3098 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3099 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3100 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3101 q_vector->tx.itr);
ac26fc13
JB		 3102 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3103 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3104
3105 /* Linked list for the queuepairs assigned to this vector */
3106 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3107 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3108 u32 val;
3109
41c445ff
JB		 3110 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3111 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3112 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3113 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3114 (I40E_QUEUE_TYPE_TX
3115 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3116
3117 wr32(hw, I40E_QINT_RQCTL(qp), val);
3118
3119 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3120 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3121 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3122 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3123 (I40E_QUEUE_TYPE_RX
3124 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3125
3126 /* Terminate the linked list */
3127 if (q == (q_vector->num_ringpairs - 1))
3128 val |= (I40E_QUEUE_END_OF_LIST
3129 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3130
3131 wr32(hw, I40E_QINT_TQCTL(qp), val);
3132 qp++;
3133 }
3134 }
3135
3136 i40e_flush(hw);
3137}
3138
3139/**
3140 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3141 * @hw: ptr to the hardware info
3142 **/
ab437b5a 3143static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3144{
ab437b5a 3145 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3146 u32 val;
3147
3148 /* clear things first */
3149 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3150 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3151
3152 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3153 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3154 I40E_PFINT_ICR0_ENA_GRST_MASK |
3155 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3156 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3157 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3158 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3159 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3160
0d8e1439
ASJ		 3161 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3162 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3163
ab437b5a
JK		 3164 if (pf->flags & I40E_FLAG_PTP)
3165 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3166
41c445ff
JB		 3167 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3168
3169 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3170 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3171 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3172
3173 /* OTHER_ITR_IDX = 0 */
3174 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3175}
3176
3177/**
3178 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3179 * @vsi: the VSI being configured
3180 **/
3181static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3182{
493fb300 3183 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3184 struct i40e_pf *pf = vsi->back;
3185 struct i40e_hw *hw = &pf->hw;
3186 u32 val;
3187
3188 /* set the ITR configuration */
ee2319cf 3189 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3190 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3191 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3192 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3193 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3194 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3195 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3196
ab437b5a 3197 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3198
3199 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3200 wr32(hw, I40E_PFINT_LNKLST0, 0);
3201
f29eaa3d 3202 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3203 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3204 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3205 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3206
3207 wr32(hw, I40E_QINT_RQCTL(0), val);
3208
3209 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3210 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3211 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3212
3213 wr32(hw, I40E_QINT_TQCTL(0), val);
3214 i40e_flush(hw);
3215}
3216
2ef28cfb
MW		 3217/**
3218 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3219 * @pf: board private structure
3220 **/
3221void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3222{
3223 struct i40e_hw *hw = &pf->hw;
3224
3225 wr32(hw, I40E_PFINT_DYN_CTL0,
3226 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3227 i40e_flush(hw);
3228}
3229
41c445ff
JB		 3230/**
3231 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3232 * @pf: board private structure
3233 **/
116a57d4 3234void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3235{
3236 struct i40e_hw *hw = &pf->hw;
3237 u32 val;
3238
3239 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3240 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3241 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3242
3243 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3244 i40e_flush(hw);
3245}
3246
5c2cebda
CW		 3247/**
3248 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3249 * @vsi: pointer to a vsi
03147773 3250 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3251 **/
3252void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3253{
3254 struct i40e_pf *pf = vsi->back;
3255 struct i40e_hw *hw = &pf->hw;
3256 u32 val;
3257
3258 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3259 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3260 i40e_flush(hw);
3261}
3262
41c445ff
JB		 3263/**
3264 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3265 * @irq: interrupt number
3266 * @data: pointer to a q_vector
3267 **/
3268static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3269{
3270 struct i40e_q_vector *q_vector = data;
3271
cd0b6fa6 3272 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3273 return IRQ_HANDLED;
3274
5d3465a1 3275 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3276
3277 return IRQ_HANDLED;
3278}
3279
41c445ff
JB		 3280/**
3281 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3282 * @vsi: the VSI being configured
3283 * @basename: name for the vector
3284 *
3285 * Allocates MSI-X vectors and requests interrupts from the kernel.
3286 **/
3287static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3288{
3289 int q_vectors = vsi->num_q_vectors;
3290 struct i40e_pf *pf = vsi->back;
3291 int base = vsi->base_vector;
3292 int rx_int_idx = 0;
3293 int tx_int_idx = 0;
3294 int vector, err;
3295
3296 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3297 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3298
cd0b6fa6 3299 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3300 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3301 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3302 tx_int_idx++;
cd0b6fa6 3303 } else if (q_vector->rx.ring) {
41c445ff
JB		 3304 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3305 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3306 } else if (q_vector->tx.ring) {
41c445ff
JB		 3307 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3308 "%s-%s-%d", basename, "tx", tx_int_idx++);
3309 } else {
3310 /* skip this unused q_vector */
3311 continue;
3312 }
3313 err = request_irq(pf->msix_entries[base + vector].vector,
3314 vsi->irq_handler,
3315 0,
3316 q_vector->name,
3317 q_vector);
3318 if (err) {
3319 dev_info(&pf->pdev->dev,
fb43201f 3320 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3321 goto free_queue_irqs;
3322 }
3323 /* assign the mask for this irq */
3324 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3325 &q_vector->affinity_mask);
3326 }
3327
63741846 3328 vsi->irqs_ready = true;
41c445ff
JB		 3329 return 0;
3330
3331free_queue_irqs:
3332 while (vector) {
3333 vector--;
3334 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3335 NULL);
3336 free_irq(pf->msix_entries[base + vector].vector,
3337 &(vsi->q_vectors[vector]));
3338 }
3339 return err;
3340}
3341
3342/**
3343 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3344 * @vsi: the VSI being un-configured
3345 **/
3346static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3347{
3348 struct i40e_pf *pf = vsi->back;
3349 struct i40e_hw *hw = &pf->hw;
3350 int base = vsi->base_vector;
3351 int i;
3352
3353 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3354 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3355 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3356 }
3357
3358 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3359 for (i = vsi->base_vector;
3360 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3361 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3362
3363 i40e_flush(hw);
3364 for (i = 0; i < vsi->num_q_vectors; i++)
3365 synchronize_irq(pf->msix_entries[i + base].vector);
3366 } else {
3367 /* Legacy and MSI mode - this stops all interrupt handling */
3368 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3369 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3370 i40e_flush(hw);
3371 synchronize_irq(pf->pdev->irq);
3372 }
3373}
3374
3375/**
3376 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3377 * @vsi: the VSI being configured
3378 **/
3379static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3380{
3381 struct i40e_pf *pf = vsi->back;
3382 int i;
3383
3384 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3385 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3386 i40e_irq_dynamic_enable(vsi, i);
3387 } else {
3388 i40e_irq_dynamic_enable_icr0(pf);
3389 }
3390
1022cb6c 3391 i40e_flush(&pf->hw);
41c445ff
JB		 3392 return 0;
3393}
3394
3395/**
3396 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3397 * @pf: board private structure
3398 **/
3399static void i40e_stop_misc_vector(struct i40e_pf *pf)
3400{
3401 /* Disable ICR 0 */
3402 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3403 i40e_flush(&pf->hw);
3404}
3405
3406/**
3407 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3408 * @irq: interrupt number
3409 * @data: pointer to a q_vector
3410 *
3411 * This is the handler used for all MSI/Legacy interrupts, and deals
3412 * with both queue and non-queue interrupts. This is also used in
3413 * MSIX mode to handle the non-queue interrupts.
3414 **/
3415static irqreturn_t i40e_intr(int irq, void *data)
3416{
3417 struct i40e_pf *pf = (struct i40e_pf *)data;
3418 struct i40e_hw *hw = &pf->hw;
5e823066 3419 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3420 u32 icr0, icr0_remaining;
3421 u32 val, ena_mask;
3422
3423 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3424 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3425
116a57d4
SN		 3426 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3427 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3428 goto enable_intr;
41c445ff 3429
cd92e72f
SN		 3430 /* if interrupt but no bits showing, must be SWINT */
3431 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3432 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3433 pf->sw_int_count++;
3434
0d8e1439
ASJ		 3435 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3436 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3437 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3438 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3439 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3440 }
3441
41c445ff
JB		 3442 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3443 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3444 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3445 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3446
3447 /* temporarily disable queue cause for NAPI processing */
3448 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3449
41c445ff
JB		 3450 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3451 wr32(hw, I40E_QINT_RQCTL(0), qval);
3452
3453 qval = rd32(hw, I40E_QINT_TQCTL(0));
3454 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3455 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3456
3457 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3458 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3459 }
3460
3461 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3462 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3463 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3464 }
3465
3466 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3467 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3468 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3469 }
3470
3471 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3472 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3473 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3474 }
3475
3476 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3477 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3478 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3479 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3480 val = rd32(hw, I40E_GLGEN_RSTAT);
3481 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3482 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3483 if (val == I40E_RESET_CORER) {
41c445ff 3484 pf->corer_count++;
4eb3f768 3485 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3486 pf->globr_count++;
4eb3f768 3487 } else if (val == I40E_RESET_EMPR) {
41c445ff 3488 pf->empr_count++;
9df42d1a 3489 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3490 }
41c445ff
JB		 3491 }
3492
9c010ee0
ASJ		 3493 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3494 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3495 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3496 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3497 rd32(hw, I40E_PFHMC_ERRORINFO),
3498 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3499 }
3500
beb0dff1
JK		 3501 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3502 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3503
3504 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3505 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3506 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3507 }
beb0dff1
JK		 3508 }
3509
41c445ff
JB		 3510 /* If a critical error is pending we have no choice but to reset the
3511 * device.
3512 * Report and mask out any remaining unexpected interrupts.
3513 */
3514 icr0_remaining = icr0 & ena_mask;
3515 if (icr0_remaining) {
3516 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3517 icr0_remaining);
9c010ee0 3518 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3519 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3520 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3521 dev_info(&pf->pdev->dev, "device will be reset\n");
3522 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3523 i40e_service_event_schedule(pf);
41c445ff
JB		 3524 }
3525 ena_mask &= ~icr0_remaining;
3526 }
5e823066 3527 ret = IRQ_HANDLED;
41c445ff 3528
5e823066 3529enable_intr:
41c445ff
JB		 3530 /* re-enable interrupt causes */
3531 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3532 if (!test_bit(__I40E_DOWN, &pf->state)) {
3533 i40e_service_event_schedule(pf);
3534 i40e_irq_dynamic_enable_icr0(pf);
3535 }
3536
5e823066 3537 return ret;
41c445ff
JB		 3538}
3539
cbf61325
ASJ		 3540/**
3541 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3542 * @tx_ring: tx ring to clean
3543 * @budget: how many cleans we're allowed
3544 *
3545 * Returns true if there's any budget left (e.g. the clean is finished)
3546 **/
3547static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3548{
3549 struct i40e_vsi *vsi = tx_ring->vsi;
3550 u16 i = tx_ring->next_to_clean;
3551 struct i40e_tx_buffer *tx_buf;
3552 struct i40e_tx_desc *tx_desc;
3553
3554 tx_buf = &tx_ring->tx_bi[i];
3555 tx_desc = I40E_TX_DESC(tx_ring, i);
3556 i -= tx_ring->count;
3557
3558 do {
3559 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3560
3561 /* if next_to_watch is not set then there is no work pending */
3562 if (!eop_desc)
3563 break;
3564
3565 /* prevent any other reads prior to eop_desc */
3566 read_barrier_depends();
3567
3568 /* if the descriptor isn't done, no work yet to do */
3569 if (!(eop_desc->cmd_type_offset_bsz &
3570 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3571 break;
3572
3573 /* clear next_to_watch to prevent false hangs */
3574 tx_buf->next_to_watch = NULL;
3575
49d7d933
ASJ		 3576 tx_desc->buffer_addr = 0;
3577 tx_desc->cmd_type_offset_bsz = 0;
3578 /* move past filter desc */
3579 tx_buf++;
3580 tx_desc++;
3581 i++;
3582 if (unlikely(!i)) {
3583 i -= tx_ring->count;
3584 tx_buf = tx_ring->tx_bi;
3585 tx_desc = I40E_TX_DESC(tx_ring, 0);
3586 }
cbf61325
ASJ		 3587 /* unmap skb header data */
3588 dma_unmap_single(tx_ring->dev,
3589 dma_unmap_addr(tx_buf, dma),
3590 dma_unmap_len(tx_buf, len),
3591 DMA_TO_DEVICE);
49d7d933
ASJ		 3592 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3593 kfree(tx_buf->raw_buf);
cbf61325 3594
49d7d933
ASJ		 3595 tx_buf->raw_buf = NULL;
3596 tx_buf->tx_flags = 0;
3597 tx_buf->next_to_watch = NULL;
cbf61325 3598 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3599 tx_desc->buffer_addr = 0;
3600 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3601
49d7d933 3602 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3603 tx_buf++;
3604 tx_desc++;
3605 i++;
3606 if (unlikely(!i)) {
3607 i -= tx_ring->count;
3608 tx_buf = tx_ring->tx_bi;
3609 tx_desc = I40E_TX_DESC(tx_ring, 0);
3610 }
3611
3612 /* update budget accounting */
3613 budget--;
3614 } while (likely(budget));
3615
3616 i += tx_ring->count;
3617 tx_ring->next_to_clean = i;
3618
6995b36c 3619 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3620 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3621
cbf61325
ASJ		 3622 return budget > 0;
3623}
3624
3625/**
3626 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3627 * @irq: interrupt number
3628 * @data: pointer to a q_vector
3629 **/
3630static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3631{
3632 struct i40e_q_vector *q_vector = data;
3633 struct i40e_vsi *vsi;
3634
3635 if (!q_vector->tx.ring)
3636 return IRQ_HANDLED;
3637
3638 vsi = q_vector->tx.ring->vsi;
3639 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3640
3641 return IRQ_HANDLED;
3642}
3643
41c445ff 3644/**
cd0b6fa6 3645 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3646 * @vsi: the VSI being configured
3647 * @v_idx: vector index
cd0b6fa6 3648 * @qp_idx: queue pair index
41c445ff 3649 **/
26cdc443 3650static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3651{
493fb300 3652 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3653 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3654 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3655
3656 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3657 tx_ring->next = q_vector->tx.ring;
3658 q_vector->tx.ring = tx_ring;
41c445ff 3659 q_vector->tx.count++;
cd0b6fa6
AD		 3660
3661 rx_ring->q_vector = q_vector;
3662 rx_ring->next = q_vector->rx.ring;
3663 q_vector->rx.ring = rx_ring;
3664 q_vector->rx.count++;
41c445ff
JB		 3665}
3666
3667/**
3668 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3669 * @vsi: the VSI being configured
3670 *
3671 * This function maps descriptor rings to the queue-specific vectors
3672 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3673 * one vector per queue pair, but on a constrained vector budget, we
3674 * group the queue pairs as "efficiently" as possible.
3675 **/
3676static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3677{
3678 int qp_remaining = vsi->num_queue_pairs;
3679 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3680 int num_ringpairs;
41c445ff
JB		 3681 int v_start = 0;
3682 int qp_idx = 0;
3683
3684 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3685 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3686 * It is also important to go through all the vectors available to be
3687 * sure that if we don't use all the vectors, that the remaining vectors
3688 * are cleared. This is especially important when decreasing the
3689 * number of queues in use.
41c445ff 3690 */
70114ec4 3691 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3692 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3693
3694 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3695
3696 q_vector->num_ringpairs = num_ringpairs;
3697
3698 q_vector->rx.count = 0;
3699 q_vector->tx.count = 0;
3700 q_vector->rx.ring = NULL;
3701 q_vector->tx.ring = NULL;
3702
3703 while (num_ringpairs--) {
26cdc443 3704 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3705 qp_idx++;
3706 qp_remaining--;
41c445ff
JB		 3707 }
3708 }
3709}
3710
3711/**
3712 * i40e_vsi_request_irq - Request IRQ from the OS
3713 * @vsi: the VSI being configured
3714 * @basename: name for the vector
3715 **/
3716static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3717{
3718 struct i40e_pf *pf = vsi->back;
3719 int err;
3720
3721 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3722 err = i40e_vsi_request_irq_msix(vsi, basename);
3723 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3724 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3725 pf->int_name, pf);
41c445ff
JB		 3726 else
3727 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3728 pf->int_name, pf);
41c445ff
JB		 3729
3730 if (err)
3731 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3732
3733 return err;
3734}
3735
3736#ifdef CONFIG_NET_POLL_CONTROLLER
3737/**
3738 * i40e_netpoll - A Polling 'interrupt'handler
3739 * @netdev: network interface device structure
3740 *
3741 * This is used by netconsole to send skbs without having to re-enable
3742 * interrupts. It's not called while the normal interrupt routine is executing.
3743 **/
38e00438
VD		 3744#ifdef I40E_FCOE
3745void i40e_netpoll(struct net_device *netdev)
3746#else
41c445ff 3747static void i40e_netpoll(struct net_device *netdev)
38e00438 3748#endif
41c445ff
JB		 3749{
3750 struct i40e_netdev_priv *np = netdev_priv(netdev);
3751 struct i40e_vsi *vsi = np->vsi;
3752 struct i40e_pf *pf = vsi->back;
3753 int i;
3754
3755 /* if interface is down do nothing */
3756 if (test_bit(__I40E_DOWN, &vsi->state))
3757 return;
3758
41c445ff
JB		 3759 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3760 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3761 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3762 } else {
3763 i40e_intr(pf->pdev->irq, netdev);
3764 }
41c445ff
JB		 3765}
3766#endif
3767
23527308
NP		 3768/**
3769 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3770 * @pf: the PF being configured
3771 * @pf_q: the PF queue
3772 * @enable: enable or disable state of the queue
3773 *
3774 * This routine will wait for the given Tx queue of the PF to reach the
3775 * enabled or disabled state.
3776 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3777 * multiple retries; else will return 0 in case of success.
3778 **/
3779static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3780{
3781 int i;
3782 u32 tx_reg;
3783
3784 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3785 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3786 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3787 break;
3788
f98a2006 3789 usleep_range(10, 20);
23527308
NP		 3790 }
3791 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3792 return -ETIMEDOUT;
3793
3794 return 0;
3795}
3796
41c445ff
JB		 3797/**
3798 * i40e_vsi_control_tx - Start or stop a VSI's rings
3799 * @vsi: the VSI being configured
3800 * @enable: start or stop the rings
3801 **/
3802static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3803{
3804 struct i40e_pf *pf = vsi->back;
3805 struct i40e_hw *hw = &pf->hw;
23527308 3806 int i, j, pf_q, ret = 0;
41c445ff
JB		 3807 u32 tx_reg;
3808
3809 pf_q = vsi->base_queue;
3810 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3811
3812 /* warn the TX unit of coming changes */
3813 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3814 if (!enable)
f98a2006 3815 usleep_range(10, 20);
351499ab 3816
6c5ef620 3817 for (j = 0; j < 50; j++) {
41c445ff 3818 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3819 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3820 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3821 break;
3822 usleep_range(1000, 2000);
3823 }
fda972f6 3824 /* Skip if the queue is already in the requested state */
7c122007 3825 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3826 continue;
41c445ff
JB		 3827
3828 /* turn on/off the queue */
c5c9eb9e
SN		 3829 if (enable) {
3830 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3831 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3832 } else {
41c445ff 3833 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3834 }
41c445ff
JB		 3835
3836 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3837 /* No waiting for the Tx queue to disable */
3838 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3839 continue;
41c445ff
JB		 3840
3841 /* wait for the change to finish */
23527308
NP		 3842 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3843 if (ret) {
3844 dev_info(&pf->pdev->dev,
fb43201f
SN		 3845 "VSI seid %d Tx ring %d %sable timeout\n",
3846 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3847 break;
41c445ff
JB		 3848 }
3849 }
3850
7134f9ce
JB		 3851 if (hw->revision_id == 0)
3852 mdelay(50);
23527308
NP		 3853 return ret;
3854}
3855
3856/**
3857 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3858 * @pf: the PF being configured
3859 * @pf_q: the PF queue
3860 * @enable: enable or disable state of the queue
3861 *
3862 * This routine will wait for the given Rx queue of the PF to reach the
3863 * enabled or disabled state.
3864 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3865 * multiple retries; else will return 0 in case of success.
3866 **/
3867static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3868{
3869 int i;
3870 u32 rx_reg;
3871
3872 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3873 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3874 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3875 break;
3876
f98a2006 3877 usleep_range(10, 20);
23527308
NP		 3878 }
3879 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3880 return -ETIMEDOUT;
7134f9ce 3881
41c445ff
JB		 3882 return 0;
3883}
3884
3885/**
3886 * i40e_vsi_control_rx - Start or stop a VSI's rings
3887 * @vsi: the VSI being configured
3888 * @enable: start or stop the rings
3889 **/
3890static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3891{
3892 struct i40e_pf *pf = vsi->back;
3893 struct i40e_hw *hw = &pf->hw;
23527308 3894 int i, j, pf_q, ret = 0;
41c445ff
JB		 3895 u32 rx_reg;
3896
3897 pf_q = vsi->base_queue;
3898 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3899 for (j = 0; j < 50; j++) {
41c445ff 3900 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3901 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3902 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3903 break;
3904 usleep_range(1000, 2000);
3905 }
41c445ff 3906
7c122007
CS		 3907 /* Skip if the queue is already in the requested state */
3908 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3909 continue;
41c445ff
JB		 3910
3911 /* turn on/off the queue */
3912 if (enable)
6c5ef620 3913 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3914 else
6c5ef620 3915 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3916 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3917
3918 /* wait for the change to finish */
23527308
NP		 3919 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3920 if (ret) {
3921 dev_info(&pf->pdev->dev,
fb43201f
SN		 3922 "VSI seid %d Rx ring %d %sable timeout\n",
3923 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3924 break;
41c445ff
JB		 3925 }
3926 }
3927
23527308 3928 return ret;
41c445ff
JB		 3929}
3930
3931/**
3932 * i40e_vsi_control_rings - Start or stop a VSI's rings
3933 * @vsi: the VSI being configured
3934 * @enable: start or stop the rings
3935 **/
fc18eaa0 3936int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3937{
3b867b28 3938 int ret = 0;
41c445ff
JB		 3939
3940 /* do rx first for enable and last for disable */
3941 if (request) {
3942 ret = i40e_vsi_control_rx(vsi, request);
3943 if (ret)
3944 return ret;
3945 ret = i40e_vsi_control_tx(vsi, request);
3946 } else {
3b867b28
ASJ		 3947 /* Ignore return value, we need to shutdown whatever we can */
3948 i40e_vsi_control_tx(vsi, request);
3949 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3950 }
3951
3952 return ret;
3953}
3954
3955/**
3956 * i40e_vsi_free_irq - Free the irq association with the OS
3957 * @vsi: the VSI being configured
3958 **/
3959static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3960{
3961 struct i40e_pf *pf = vsi->back;
3962 struct i40e_hw *hw = &pf->hw;
3963 int base = vsi->base_vector;
3964 u32 val, qp;
3965 int i;
3966
3967 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3968 if (!vsi->q_vectors)
3969 return;
3970
63741846
SN		 3971 if (!vsi->irqs_ready)
3972 return;
3973
3974 vsi->irqs_ready = false;
41c445ff
JB		 3975 for (i = 0; i < vsi->num_q_vectors; i++) {
3976 u16 vector = i + base;
3977
3978 /* free only the irqs that were actually requested */
78681b1f
SN		 3979 if (!vsi->q_vectors[i] ||
3980 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3981 continue;
3982
3983 /* clear the affinity_mask in the IRQ descriptor */
3984 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3985 NULL);
3986 free_irq(pf->msix_entries[vector].vector,
493fb300 3987 vsi->q_vectors[i]);
41c445ff
JB		 3988
3989 /* Tear down the interrupt queue link list
3990 *
3991 * We know that they come in pairs and always
3992 * the Rx first, then the Tx. To clear the
3993 * link list, stick the EOL value into the
3994 * next_q field of the registers.
3995 */
3996 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3997 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3998 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3999 val |= I40E_QUEUE_END_OF_LIST
4000 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4001 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4002
4003 while (qp != I40E_QUEUE_END_OF_LIST) {
4004 u32 next;
4005
4006 val = rd32(hw, I40E_QINT_RQCTL(qp));
4007
4008 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4009 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4010 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4011 I40E_QINT_RQCTL_INTEVENT_MASK);
4012
4013 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4014 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4015
4016 wr32(hw, I40E_QINT_RQCTL(qp), val);
4017
4018 val = rd32(hw, I40E_QINT_TQCTL(qp));
4019
4020 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4021 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4022
4023 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4024 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4025 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4026 I40E_QINT_TQCTL_INTEVENT_MASK);
4027
4028 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4029 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4030
4031 wr32(hw, I40E_QINT_TQCTL(qp), val);
4032 qp = next;
4033 }
4034 }
4035 } else {
4036 free_irq(pf->pdev->irq, pf);
4037
4038 val = rd32(hw, I40E_PFINT_LNKLST0);
4039 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4040 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4041 val |= I40E_QUEUE_END_OF_LIST
4042 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4043 wr32(hw, I40E_PFINT_LNKLST0, val);
4044
4045 val = rd32(hw, I40E_QINT_RQCTL(qp));
4046 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4047 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4048 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4049 I40E_QINT_RQCTL_INTEVENT_MASK);
4050
4051 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4052 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4053
4054 wr32(hw, I40E_QINT_RQCTL(qp), val);
4055
4056 val = rd32(hw, I40E_QINT_TQCTL(qp));
4057
4058 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4059 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4060 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4061 I40E_QINT_TQCTL_INTEVENT_MASK);
4062
4063 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4064 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4065
4066 wr32(hw, I40E_QINT_TQCTL(qp), val);
4067 }
4068}
4069
493fb300
AD		 4070/**
4071 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4072 * @vsi: the VSI being configured
4073 * @v_idx: Index of vector to be freed
4074 *
4075 * This function frees the memory allocated to the q_vector. In addition if
4076 * NAPI is enabled it will delete any references to the NAPI struct prior
4077 * to freeing the q_vector.
4078 **/
4079static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4080{
4081 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4082 struct i40e_ring *ring;
493fb300
AD		 4083
4084 if (!q_vector)
4085 return;
4086
4087 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4088 i40e_for_each_ring(ring, q_vector->tx)
4089 ring->q_vector = NULL;
4090
4091 i40e_for_each_ring(ring, q_vector->rx)
4092 ring->q_vector = NULL;
493fb300
AD		 4093
4094 /* only VSI w/ an associated netdev is set up w/ NAPI */
4095 if (vsi->netdev)
4096 netif_napi_del(&q_vector->napi);
4097
4098 vsi->q_vectors[v_idx] = NULL;
4099
4100 kfree_rcu(q_vector, rcu);
4101}
4102
41c445ff
JB		 4103/**
4104 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4105 * @vsi: the VSI being un-configured
4106 *
4107 * This frees the memory allocated to the q_vectors and
4108 * deletes references to the NAPI struct.
4109 **/
4110static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4111{
4112 int v_idx;
4113
493fb300
AD		 4114 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4115 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4116}
4117
4118/**
4119 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4120 * @pf: board private structure
4121 **/
4122static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4123{
4124 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4125 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4126 pci_disable_msix(pf->pdev);
4127 kfree(pf->msix_entries);
4128 pf->msix_entries = NULL;
3b444399
SN		 4129 kfree(pf->irq_pile);
4130 pf->irq_pile = NULL;
41c445ff
JB		 4131 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4132 pci_disable_msi(pf->pdev);
4133 }
4134 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4135}
4136
4137/**
4138 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4139 * @pf: board private structure
4140 *
4141 * We go through and clear interrupt specific resources and reset the structure
4142 * to pre-load conditions
4143 **/
4144static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4145{
4146 int i;
4147
e147758d
SN		 4148 i40e_stop_misc_vector(pf);
4149 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4150 synchronize_irq(pf->msix_entries[0].vector);
4151 free_irq(pf->msix_entries[0].vector, pf);
4152 }
4153
41c445ff 4154 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4155 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4156 if (pf->vsi[i])
4157 i40e_vsi_free_q_vectors(pf->vsi[i]);
4158 i40e_reset_interrupt_capability(pf);
4159}
4160
4161/**
4162 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4163 * @vsi: the VSI being configured
4164 **/
4165static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4166{
4167 int q_idx;
4168
4169 if (!vsi->netdev)
4170 return;
4171
4172 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4173 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4174}
4175
4176/**
4177 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4178 * @vsi: the VSI being configured
4179 **/
4180static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4181{
4182 int q_idx;
4183
4184 if (!vsi->netdev)
4185 return;
4186
4187 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4188 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4189}
4190
90ef8d47
SN		 4191/**
4192 * i40e_vsi_close - Shut down a VSI
4193 * @vsi: the vsi to be quelled
4194 **/
4195static void i40e_vsi_close(struct i40e_vsi *vsi)
4196{
4197 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4198 i40e_down(vsi);
4199 i40e_vsi_free_irq(vsi);
4200 i40e_vsi_free_tx_resources(vsi);
4201 i40e_vsi_free_rx_resources(vsi);
92faef85 4202 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4203}
4204
41c445ff
JB		 4205/**
4206 * i40e_quiesce_vsi - Pause a given VSI
4207 * @vsi: the VSI being paused
4208 **/
4209static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4210{
4211 if (test_bit(__I40E_DOWN, &vsi->state))
4212 return;
4213
d341b7a5
NP		 4214 /* No need to disable FCoE VSI when Tx suspended */
4215 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4216 vsi->type == I40E_VSI_FCOE) {
4217 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4218 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4219 return;
4220 }
4221
41c445ff 4222 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4223 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4224 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4225 else
90ef8d47 4226 i40e_vsi_close(vsi);
41c445ff
JB		 4227}
4228
4229/**
4230 * i40e_unquiesce_vsi - Resume a given VSI
4231 * @vsi: the VSI being resumed
4232 **/
4233static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4234{
4235 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4236 return;
4237
4238 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4239 if (vsi->netdev && netif_running(vsi->netdev))
4240 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4241 else
8276f757 4242 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4243}
4244
4245/**
4246 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4247 * @pf: the PF
4248 **/
4249static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4250{
4251 int v;
4252
505682cd 4253 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4254 if (pf->vsi[v])
4255 i40e_quiesce_vsi(pf->vsi[v]);
4256 }
4257}
4258
4259/**
4260 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4261 * @pf: the PF
4262 **/
4263static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4264{
4265 int v;
4266
505682cd 4267 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4268 if (pf->vsi[v])
4269 i40e_unquiesce_vsi(pf->vsi[v]);
4270 }
4271}
4272
69129dc3
NP		 4273#ifdef CONFIG_I40E_DCB
4274/**
4275 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4276 * @vsi: the VSI being configured
4277 *
4278 * This function waits for the given VSI's Tx queues to be disabled.
4279 **/
4280static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4281{
4282 struct i40e_pf *pf = vsi->back;
4283 int i, pf_q, ret;
4284
4285 pf_q = vsi->base_queue;
4286 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4287 /* Check and wait for the disable status of the queue */
4288 ret = i40e_pf_txq_wait(pf, pf_q, false);
4289 if (ret) {
4290 dev_info(&pf->pdev->dev,
fb43201f
SN		 4291 "VSI seid %d Tx ring %d disable timeout\n",
4292 vsi->seid, pf_q);
69129dc3
NP		 4293 return ret;
4294 }
4295 }
4296
4297 return 0;
4298}
4299
4300/**
4301 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4302 * @pf: the PF
4303 *
4304 * This function waits for the Tx queues to be in disabled state for all the
4305 * VSIs that are managed by this PF.
4306 **/
4307static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4308{
4309 int v, ret = 0;
4310
4311 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4312 /* No need to wait for FCoE VSI queues */
4313 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4314 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4315 if (ret)
4316 break;
4317 }
4318 }
4319
4320 return ret;
4321}
4322
4323#endif
b03a8c1f
KP		 4324
4325/**
4326 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4327 * @q_idx: TX queue number
4328 * @vsi: Pointer to VSI struct
4329 *
4330 * This function checks specified queue for given VSI. Detects hung condition.
4331 * Sets hung bit since it is two step process. Before next run of service task
4332 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4333 * hung condition remain unchanged and during subsequent run, this function
4334 * issues SW interrupt to recover from hung condition.
4335 **/
4336static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4337{
4338 struct i40e_ring *tx_ring = NULL;
4339 struct i40e_pf *pf;
4340 u32 head, val, tx_pending;
4341 int i;
4342
4343 pf = vsi->back;
4344
4345 /* now that we have an index, find the tx_ring struct */
4346 for (i = 0; i < vsi->num_queue_pairs; i++) {
4347 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4348 if (q_idx == vsi->tx_rings[i]->queue_index) {
4349 tx_ring = vsi->tx_rings[i];
4350 break;
4351 }
4352 }
4353 }
4354
4355 if (!tx_ring)
4356 return;
4357
4358 /* Read interrupt register */
4359 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4360 val = rd32(&pf->hw,
4361 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4362 tx_ring->vsi->base_vector - 1));
4363 else
4364 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4365
4366 head = i40e_get_head(tx_ring);
4367
4368 tx_pending = i40e_get_tx_pending(tx_ring);
4369
4370 /* Interrupts are disabled and TX pending is non-zero,
4371 * trigger the SW interrupt (don't wait). Worst case
4372 * there will be one extra interrupt which may result
4373 * into not cleaning any queues because queues are cleaned.
4374 */
4375 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4376 i40e_force_wb(vsi, tx_ring->q_vector);
4377}
4378
4379/**
4380 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4381 * @pf: pointer to PF struct
4382 *
4383 * LAN VSI has netdev and netdev has TX queues. This function is to check
4384 * each of those TX queues if they are hung, trigger recovery by issuing
4385 * SW interrupt.
4386 **/
4387static void i40e_detect_recover_hung(struct i40e_pf *pf)
4388{
4389 struct net_device *netdev;
4390 struct i40e_vsi *vsi;
4391 int i;
4392
4393 /* Only for LAN VSI */
4394 vsi = pf->vsi[pf->lan_vsi];
4395
4396 if (!vsi)
4397 return;
4398
4399 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4400 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4401 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4402 return;
4403
4404 /* Make sure type is MAIN VSI */
4405 if (vsi->type != I40E_VSI_MAIN)
4406 return;
4407
4408 netdev = vsi->netdev;
4409 if (!netdev)
4410 return;
4411
4412 /* Bail out if netif_carrier is not OK */
4413 if (!netif_carrier_ok(netdev))
4414 return;
4415
4416 /* Go thru' TX queues for netdev */
4417 for (i = 0; i < netdev->num_tx_queues; i++) {
4418 struct netdev_queue *q;
4419
4420 q = netdev_get_tx_queue(netdev, i);
4421 if (q)
4422 i40e_detect_recover_hung_queue(i, vsi);
4423 }
4424}
4425
63d7e5a4
NP		 4426/**
4427 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4428 * @pf: pointer to PF
63d7e5a4
NP		 4429 *
4430 * Get TC map for ISCSI PF type that will include iSCSI TC
4431 * and LAN TC.
4432 **/
4433static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4434{
4435 struct i40e_dcb_app_priority_table app;
4436 struct i40e_hw *hw = &pf->hw;
4437 u8 enabled_tc = 1; /* TC0 is always enabled */
4438 u8 tc, i;
4439 /* Get the iSCSI APP TLV */
4440 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4441
4442 for (i = 0; i < dcbcfg->numapps; i++) {
4443 app = dcbcfg->app[i];
4444 if (app.selector == I40E_APP_SEL_TCPIP &&
4445 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4446 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4447 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4448 break;
4449 }
4450 }
4451
4452 return enabled_tc;
4453}
4454
41c445ff
JB		 4455/**
4456 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4457 * @dcbcfg: the corresponding DCBx configuration structure
4458 *
4459 * Return the number of TCs from given DCBx configuration
4460 **/
4461static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4462{
078b5876
JB		 4463 u8 num_tc = 0;
4464 int i;
41c445ff
JB		 4465
4466 /* Scan the ETS Config Priority Table to find
4467 * traffic class enabled for a given priority
4468 * and use the traffic class index to get the
4469 * number of traffic classes enabled
4470 */
4471 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4472 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4473 num_tc = dcbcfg->etscfg.prioritytable[i];
4474 }
4475
4476 /* Traffic class index starts from zero so
4477 * increment to return the actual count
4478 */
078b5876 4479 return num_tc + 1;
41c445ff
JB		 4480}
4481
4482/**
4483 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4484 * @dcbcfg: the corresponding DCBx configuration structure
4485 *
4486 * Query the current DCB configuration and return the number of
4487 * traffic classes enabled from the given DCBX config
4488 **/
4489static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4490{
4491 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4492 u8 enabled_tc = 1;
4493 u8 i;
4494
4495 for (i = 0; i < num_tc; i++)
41a1d04b 4496 enabled_tc |= BIT(i);
41c445ff
JB		 4497
4498 return enabled_tc;
4499}
4500
4501/**
4502 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4503 * @pf: PF being queried
4504 *
4505 * Return number of traffic classes enabled for the given PF
4506 **/
4507static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4508{
4509 struct i40e_hw *hw = &pf->hw;
4510 u8 i, enabled_tc;
4511 u8 num_tc = 0;
4512 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4513
4514 /* If DCB is not enabled then always in single TC */
4515 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4516 return 1;
4517
63d7e5a4
NP		 4518 /* SFP mode will be enabled for all TCs on port */
4519 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4520 return i40e_dcb_get_num_tc(dcbcfg);
4521
41c445ff 4522 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4523 if (pf->hw.func_caps.iscsi)
4524 enabled_tc = i40e_get_iscsi_tc_map(pf);
4525 else
fc51de96 4526 return 1; /* Only TC0 */
41c445ff 4527
63d7e5a4
NP		 4528 /* At least have TC0 */
4529 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4530 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4531 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4532 num_tc++;
4533 }
4534 return num_tc;
41c445ff
JB		 4535}
4536
4537/**
4538 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4539 * @pf: PF being queried
4540 *
4541 * Return a bitmap for first enabled traffic class for this PF.
4542 **/
4543static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4544{
4545 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4546 u8 i = 0;
4547
4548 if (!enabled_tc)
4549 return 0x1; /* TC0 */
4550
4551 /* Find the first enabled TC */
4552 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4553 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4554 break;
4555 }
4556
41a1d04b 4557 return BIT(i);
41c445ff
JB		 4558}
4559
4560/**
4561 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4562 * @pf: PF being queried
4563 *
4564 * Return a bitmap for enabled traffic classes for this PF.
4565 **/
4566static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4567{
4568 /* If DCB is not enabled for this PF then just return default TC */
4569 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4570 return i40e_pf_get_default_tc(pf);
4571
41c445ff 4572 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4573 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4574 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4575
fc51de96 4576 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4577 if (pf->hw.func_caps.iscsi)
4578 return i40e_get_iscsi_tc_map(pf);
4579 else
fc51de96 4580 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4581}
4582
4583/**
4584 * i40e_vsi_get_bw_info - Query VSI BW Information
4585 * @vsi: the VSI being queried
4586 *
4587 * Returns 0 on success, negative value on failure
4588 **/
4589static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4590{
4591 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4592 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4593 struct i40e_pf *pf = vsi->back;
4594 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4595 i40e_status ret;
41c445ff 4596 u32 tc_bw_max;
41c445ff
JB		 4597 int i;
4598
4599 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4600 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4601 if (ret) {
41c445ff 4602 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4603 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4604 i40e_stat_str(&pf->hw, ret),
4605 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4606 return -EINVAL;
41c445ff
JB		 4607 }
4608
4609 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4610 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4611 NULL);
4612 if (ret) {
41c445ff 4613 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4614 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4615 i40e_stat_str(&pf->hw, ret),
4616 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4617 return -EINVAL;
41c445ff
JB		 4618 }
4619
4620 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4621 dev_info(&pf->pdev->dev,
4622 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4623 bw_config.tc_valid_bits,
4624 bw_ets_config.tc_valid_bits);
4625 /* Still continuing */
4626 }
4627
4628 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4629 vsi->bw_max_quanta = bw_config.max_bw;
4630 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4631 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4632 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4633 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4634 vsi->bw_ets_limit_credits[i] =
4635 le16_to_cpu(bw_ets_config.credits[i]);
4636 /* 3 bits out of 4 for each TC */
4637 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4638 }
078b5876 4639
dcae29be 4640 return 0;
41c445ff
JB		 4641}
4642
4643/**
4644 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4645 * @vsi: the VSI being configured
4646 * @enabled_tc: TC bitmap
4647 * @bw_credits: BW shared credits per TC
4648 *
4649 * Returns 0 on success, negative value on failure
4650 **/
dcae29be 4651static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4652 u8 *bw_share)
4653{
4654 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4655 i40e_status ret;
dcae29be 4656 int i;
41c445ff
JB		 4657
4658 bw_data.tc_valid_bits = enabled_tc;
4659 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4660 bw_data.tc_bw_credits[i] = bw_share[i];
4661
f1c7e72e
SN		 4662 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4663 NULL);
4664 if (ret) {
41c445ff 4665 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4666 "AQ command Config VSI BW allocation per TC failed = %d\n",
4667 vsi->back->hw.aq.asq_last_status);
dcae29be 4668 return -EINVAL;
41c445ff
JB		 4669 }
4670
4671 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4672 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4673
dcae29be 4674 return 0;
41c445ff
JB		 4675}
4676
4677/**
4678 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4679 * @vsi: the VSI being configured
4680 * @enabled_tc: TC map to be enabled
4681 *
4682 **/
4683static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4684{
4685 struct net_device *netdev = vsi->netdev;
4686 struct i40e_pf *pf = vsi->back;
4687 struct i40e_hw *hw = &pf->hw;
4688 u8 netdev_tc = 0;
4689 int i;
4690 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4691
4692 if (!netdev)
4693 return;
4694
4695 if (!enabled_tc) {
4696 netdev_reset_tc(netdev);
4697 return;
4698 }
4699
4700 /* Set up actual enabled TCs on the VSI */
4701 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4702 return;
4703
4704 /* set per TC queues for the VSI */
4705 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4706 /* Only set TC queues for enabled tcs
4707 *
4708 * e.g. For a VSI that has TC0 and TC3 enabled the
4709 * enabled_tc bitmap would be 0x00001001; the driver
4710 * will set the numtc for netdev as 2 that will be
4711 * referenced by the netdev layer as TC 0 and 1.
4712 */
41a1d04b 4713 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4714 netdev_set_tc_queue(netdev,
4715 vsi->tc_config.tc_info[i].netdev_tc,
4716 vsi->tc_config.tc_info[i].qcount,
4717 vsi->tc_config.tc_info[i].qoffset);
4718 }
4719
4720 /* Assign UP2TC map for the VSI */
4721 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4722 /* Get the actual TC# for the UP */
4723 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4724 /* Get the mapped netdev TC# for the UP */
4725 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4726 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4727 }
4728}
4729
4730/**
4731 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4732 * @vsi: the VSI being configured
4733 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4734 **/
4735static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4736 struct i40e_vsi_context *ctxt)
4737{
4738 /* copy just the sections touched not the entire info
4739 * since not all sections are valid as returned by
4740 * update vsi params
4741 */
4742 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4743 memcpy(&vsi->info.queue_mapping,
4744 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4745 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4746 sizeof(vsi->info.tc_mapping));
4747}
4748
4749/**
4750 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4751 * @vsi: VSI to be configured
4752 * @enabled_tc: TC bitmap
4753 *
4754 * This configures a particular VSI for TCs that are mapped to the
4755 * given TC bitmap. It uses default bandwidth share for TCs across
4756 * VSIs to configure TC for a particular VSI.
4757 *
4758 * NOTE:
4759 * It is expected that the VSI queues have been quisced before calling
4760 * this function.
4761 **/
4762static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4763{
4764 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4765 struct i40e_vsi_context ctxt;
4766 int ret = 0;
4767 int i;
4768
4769 /* Check if enabled_tc is same as existing or new TCs */
4770 if (vsi->tc_config.enabled_tc == enabled_tc)
4771 return ret;
4772
4773 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4774 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4775 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4776 bw_share[i] = 1;
4777 }
4778
4779 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4780 if (ret) {
4781 dev_info(&vsi->back->pdev->dev,
4782 "Failed configuring TC map %d for VSI %d\n",
4783 enabled_tc, vsi->seid);
4784 goto out;
4785 }
4786
4787 /* Update Queue Pairs Mapping for currently enabled UPs */
4788 ctxt.seid = vsi->seid;
4789 ctxt.pf_num = vsi->back->hw.pf_id;
4790 ctxt.vf_num = 0;
4791 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4792 ctxt.info = vsi->info;
41c445ff
JB		 4793 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4794
4795 /* Update the VSI after updating the VSI queue-mapping information */
4796 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4797 if (ret) {
4798 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4799 "Update vsi tc config failed, err %s aq_err %s\n",
4800 i40e_stat_str(&vsi->back->hw, ret),
4801 i40e_aq_str(&vsi->back->hw,
4802 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4803 goto out;
4804 }
4805 /* update the local VSI info with updated queue map */
4806 i40e_vsi_update_queue_map(vsi, &ctxt);
4807 vsi->info.valid_sections = 0;
4808
4809 /* Update current VSI BW information */
4810 ret = i40e_vsi_get_bw_info(vsi);
4811 if (ret) {
4812 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4813 "Failed updating vsi bw info, err %s aq_err %s\n",
4814 i40e_stat_str(&vsi->back->hw, ret),
4815 i40e_aq_str(&vsi->back->hw,
4816 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4817 goto out;
4818 }
4819
4820 /* Update the netdev TC setup */
4821 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4822out:
4823 return ret;
4824}
4825
4e3b35b0
NP		 4826/**
4827 * i40e_veb_config_tc - Configure TCs for given VEB
4828 * @veb: given VEB
4829 * @enabled_tc: TC bitmap
4830 *
4831 * Configures given TC bitmap for VEB (switching) element
4832 **/
4833int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4834{
4835 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4836 struct i40e_pf *pf = veb->pf;
4837 int ret = 0;
4838 int i;
4839
4840 /* No TCs or already enabled TCs just return */
4841 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4842 return ret;
4843
4844 bw_data.tc_valid_bits = enabled_tc;
4845 /* bw_data.absolute_credits is not set (relative) */
4846
4847 /* Enable ETS TCs with equal BW Share for now */
4848 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4849 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4850 bw_data.tc_bw_share_credits[i] = 1;
4851 }
4852
4853 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4854 &bw_data, NULL);
4855 if (ret) {
4856 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4857 "VEB bw config failed, err %s aq_err %s\n",
4858 i40e_stat_str(&pf->hw, ret),
4859 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4860 goto out;
4861 }
4862
4863 /* Update the BW information */
4864 ret = i40e_veb_get_bw_info(veb);
4865 if (ret) {
4866 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4867 "Failed getting veb bw config, err %s aq_err %s\n",
4868 i40e_stat_str(&pf->hw, ret),
4869 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4870 }
4871
4872out:
4873 return ret;
4874}
4875
4876#ifdef CONFIG_I40E_DCB
4877/**
4878 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4879 * @pf: PF struct
4880 *
4881 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4882 * the caller would've quiesce all the VSIs before calling
4883 * this function
4884 **/
4885static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4886{
4887 u8 tc_map = 0;
4888 int ret;
4889 u8 v;
4890
4891 /* Enable the TCs available on PF to all VEBs */
4892 tc_map = i40e_pf_get_tc_map(pf);
4893 for (v = 0; v < I40E_MAX_VEB; v++) {
4894 if (!pf->veb[v])
4895 continue;
4896 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4897 if (ret) {
4898 dev_info(&pf->pdev->dev,
4899 "Failed configuring TC for VEB seid=%d\n",
4900 pf->veb[v]->seid);
4901 /* Will try to configure as many components */
4902 }
4903 }
4904
4905 /* Update each VSI */
505682cd 4906 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4907 if (!pf->vsi[v])
4908 continue;
4909
4910 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4911#ifdef I40E_FCOE
4912 * - For FCoE VSI only enable the TC configured
4913 * as per the APP TLV
4914#endif
4e3b35b0
NP		 4915 * - For all others keep them at TC0 for now
4916 */
4917 if (v == pf->lan_vsi)
4918 tc_map = i40e_pf_get_tc_map(pf);
4919 else
4920 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4921#ifdef I40E_FCOE
4922 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4923 tc_map = i40e_get_fcoe_tc_map(pf);
4924#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4925
4926 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4927 if (ret) {
4928 dev_info(&pf->pdev->dev,
4929 "Failed configuring TC for VSI seid=%d\n",
4930 pf->vsi[v]->seid);
4931 /* Will try to configure as many components */
4932 } else {
0672a091
NP		 4933 /* Re-configure VSI vectors based on updated TC map */
4934 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4935 if (pf->vsi[v]->netdev)
4936 i40e_dcbnl_set_all(pf->vsi[v]);
4937 }
4938 }
4939}
4940
2fd75f31
NP		 4941/**
4942 * i40e_resume_port_tx - Resume port Tx
4943 * @pf: PF struct
4944 *
4945 * Resume a port's Tx and issue a PF reset in case of failure to
4946 * resume.
4947 **/
4948static int i40e_resume_port_tx(struct i40e_pf *pf)
4949{
4950 struct i40e_hw *hw = &pf->hw;
4951 int ret;
4952
4953 ret = i40e_aq_resume_port_tx(hw, NULL);
4954 if (ret) {
4955 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4956 "Resume Port Tx failed, err %s aq_err %s\n",
4957 i40e_stat_str(&pf->hw, ret),
4958 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4959 /* Schedule PF reset to recover */
4960 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4961 i40e_service_event_schedule(pf);
4962 }
4963
4964 return ret;
4965}
4966
4e3b35b0
NP		 4967/**
4968 * i40e_init_pf_dcb - Initialize DCB configuration
4969 * @pf: PF being configured
4970 *
4971 * Query the current DCB configuration and cache it
4972 * in the hardware structure
4973 **/
4974static int i40e_init_pf_dcb(struct i40e_pf *pf)
4975{
4976 struct i40e_hw *hw = &pf->hw;
4977 int err = 0;
4978
025b4a54
ASJ		 4979 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4980 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4981 (pf->hw.aq.fw_maj_ver < 4))
4982 goto out;
4983
4e3b35b0
NP		 4984 /* Get the initial DCB configuration */
4985 err = i40e_init_dcb(hw);
4986 if (!err) {
4987 /* Device/Function is not DCBX capable */
4988 if ((!hw->func_caps.dcb) ||
4989 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4990 dev_info(&pf->pdev->dev,
4991 "DCBX offload is not supported or is disabled for this PF.\n");
4992
4993 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4994 goto out;
4995
4996 } else {
4997 /* When status is not DISABLED then DCBX in FW */
4998 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4999 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5000
5001 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5002 /* Enable DCB tagging only when more than one TC */
5003 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5004 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5005 dev_dbg(&pf->pdev->dev,
5006 "DCBX offload is supported for this PF.\n");
4e3b35b0 5007 }
014269ff 5008 } else {
aebfc816 5009 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5010 "Query for DCB configuration failed, err %s aq_err %s\n",
5011 i40e_stat_str(&pf->hw, err),
5012 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5013 }
5014
5015out:
5016 return err;
5017}
5018#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5019#define SPEED_SIZE 14
5020#define FC_SIZE 8
5021/**
5022 * i40e_print_link_message - print link up or down
5023 * @vsi: the VSI for which link needs a message
5024 */
c156f856 5025void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5026{
a9165490
SN		 5027 char *speed = "Unknown";
5028 char *fc = "Unknown";
cf05ed08 5029
c156f856
MJ		 5030 if (vsi->current_isup == isup)
5031 return;
5032 vsi->current_isup = isup;
cf05ed08
JB		 5033 if (!isup) {
5034 netdev_info(vsi->netdev, "NIC Link is Down\n");
5035 return;
5036 }
5037
148c2d80
GR		 5038 /* Warn user if link speed on NPAR enabled partition is not at
5039 * least 10GB
5040 */
5041 if (vsi->back->hw.func_caps.npar_enable &&
5042 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5043 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5044 netdev_warn(vsi->netdev,
5045 "The partition detected link speed that is less than 10Gbps\n");
5046
cf05ed08
JB		 5047 switch (vsi->back->hw.phy.link_info.link_speed) {
5048 case I40E_LINK_SPEED_40GB:
a9165490 5049 speed = "40 G";
cf05ed08 5050 break;
ae24b409 5051 case I40E_LINK_SPEED_20GB:
a9165490 5052 speed = "20 G";
ae24b409 5053 break;
cf05ed08 5054 case I40E_LINK_SPEED_10GB:
a9165490 5055 speed = "10 G";
cf05ed08
JB		 5056 break;
5057 case I40E_LINK_SPEED_1GB:
a9165490 5058 speed = "1000 M";
cf05ed08 5059 break;
5960d33f 5060 case I40E_LINK_SPEED_100MB:
a9165490 5061 speed = "100 M";
5960d33f 5062 break;
cf05ed08
JB		 5063 default:
5064 break;
5065 }
5066
5067 switch (vsi->back->hw.fc.current_mode) {
5068 case I40E_FC_FULL:
a9165490 5069 fc = "RX/TX";
cf05ed08
JB		 5070 break;
5071 case I40E_FC_TX_PAUSE:
a9165490 5072 fc = "TX";
cf05ed08
JB		 5073 break;
5074 case I40E_FC_RX_PAUSE:
a9165490 5075 fc = "RX";
cf05ed08
JB		 5076 break;
5077 default:
a9165490 5078 fc = "None";
cf05ed08
JB		 5079 break;
5080 }
5081
a9165490 5082 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5083 speed, fc);
5084}
4e3b35b0 5085
41c445ff
JB		 5086/**
5087 * i40e_up_complete - Finish the last steps of bringing up a connection
5088 * @vsi: the VSI being configured
5089 **/
5090static int i40e_up_complete(struct i40e_vsi *vsi)
5091{
5092 struct i40e_pf *pf = vsi->back;
5093 int err;
5094
5095 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5096 i40e_vsi_configure_msix(vsi);
5097 else
5098 i40e_configure_msi_and_legacy(vsi);
5099
5100 /* start rings */
5101 err = i40e_vsi_control_rings(vsi, true);
5102 if (err)
5103 return err;
5104
5105 clear_bit(__I40E_DOWN, &vsi->state);
5106 i40e_napi_enable_all(vsi);
5107 i40e_vsi_enable_irq(vsi);
5108
5109 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5110 (vsi->netdev)) {
cf05ed08 5111 i40e_print_link_message(vsi, true);
41c445ff
JB		 5112 netif_tx_start_all_queues(vsi->netdev);
5113 netif_carrier_on(vsi->netdev);
6d779b41 5114 } else if (vsi->netdev) {
cf05ed08 5115 i40e_print_link_message(vsi, false);
7b592f61
CW		 5116 /* need to check for qualified module here*/
5117 if ((pf->hw.phy.link_info.link_info &
5118 I40E_AQ_MEDIA_AVAILABLE) &&
5119 (!(pf->hw.phy.link_info.an_info &
5120 I40E_AQ_QUALIFIED_MODULE)))
5121 netdev_err(vsi->netdev,
5122 "the driver failed to link because an unqualified module was detected.");
41c445ff 5123 }
ca64fa4e
ASJ		 5124
5125 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5126 if (vsi->type == I40E_VSI_FDIR) {
5127 /* reset fd counters */
5128 pf->fd_add_err = pf->fd_atr_cnt = 0;
5129 if (pf->fd_tcp_rule > 0) {
5130 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5131 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5132 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5133 pf->fd_tcp_rule = 0;
5134 }
ca64fa4e 5135 i40e_fdir_filter_restore(vsi);
1e1be8f6 5136 }
41c445ff
JB		 5137 i40e_service_event_schedule(pf);
5138
5139 return 0;
5140}
5141
5142/**
5143 * i40e_vsi_reinit_locked - Reset the VSI
5144 * @vsi: the VSI being configured
5145 *
5146 * Rebuild the ring structs after some configuration
5147 * has changed, e.g. MTU size.
5148 **/
5149static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5150{
5151 struct i40e_pf *pf = vsi->back;
5152
5153 WARN_ON(in_interrupt());
5154 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5155 usleep_range(1000, 2000);
5156 i40e_down(vsi);
5157
5158 /* Give a VF some time to respond to the reset. The
5159 * two second wait is based upon the watchdog cycle in
5160 * the VF driver.
5161 */
5162 if (vsi->type == I40E_VSI_SRIOV)
5163 msleep(2000);
5164 i40e_up(vsi);
5165 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5166}
5167
5168/**
5169 * i40e_up - Bring the connection back up after being down
5170 * @vsi: the VSI being configured
5171 **/
5172int i40e_up(struct i40e_vsi *vsi)
5173{
5174 int err;
5175
5176 err = i40e_vsi_configure(vsi);
5177 if (!err)
5178 err = i40e_up_complete(vsi);
5179
5180 return err;
5181}
5182
5183/**
5184 * i40e_down - Shutdown the connection processing
5185 * @vsi: the VSI being stopped
5186 **/
5187void i40e_down(struct i40e_vsi *vsi)
5188{
5189 int i;
5190
5191 /* It is assumed that the caller of this function
5192 * sets the vsi->state __I40E_DOWN bit.
5193 */
5194 if (vsi->netdev) {
5195 netif_carrier_off(vsi->netdev);
5196 netif_tx_disable(vsi->netdev);
5197 }
5198 i40e_vsi_disable_irq(vsi);
5199 i40e_vsi_control_rings(vsi, false);
5200 i40e_napi_disable_all(vsi);
5201
5202 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5203 i40e_clean_tx_ring(vsi->tx_rings[i]);
5204 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5205 }
5206}
5207
5208/**
5209 * i40e_setup_tc - configure multiple traffic classes
5210 * @netdev: net device to configure
5211 * @tc: number of traffic classes to enable
5212 **/
38e00438
VD		 5213#ifdef I40E_FCOE
5214int i40e_setup_tc(struct net_device *netdev, u8 tc)
5215#else
41c445ff 5216static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5217#endif
41c445ff
JB		 5218{
5219 struct i40e_netdev_priv *np = netdev_priv(netdev);
5220 struct i40e_vsi *vsi = np->vsi;
5221 struct i40e_pf *pf = vsi->back;
5222 u8 enabled_tc = 0;
5223 int ret = -EINVAL;
5224 int i;
5225
5226 /* Check if DCB enabled to continue */
5227 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5228 netdev_info(netdev, "DCB is not enabled for adapter\n");
5229 goto exit;
5230 }
5231
5232 /* Check if MFP enabled */
5233 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5234 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5235 goto exit;
5236 }
5237
5238 /* Check whether tc count is within enabled limit */
5239 if (tc > i40e_pf_get_num_tc(pf)) {
5240 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5241 goto exit;
5242 }
5243
5244 /* Generate TC map for number of tc requested */
5245 for (i = 0; i < tc; i++)
41a1d04b 5246 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5247
5248 /* Requesting same TC configuration as already enabled */
5249 if (enabled_tc == vsi->tc_config.enabled_tc)
5250 return 0;
5251
5252 /* Quiesce VSI queues */
5253 i40e_quiesce_vsi(vsi);
5254
5255 /* Configure VSI for enabled TCs */
5256 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5257 if (ret) {
5258 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5259 vsi->seid);
5260 goto exit;
5261 }
5262
5263 /* Unquiesce VSI */
5264 i40e_unquiesce_vsi(vsi);
5265
5266exit:
5267 return ret;
5268}
5269
5270/**
5271 * i40e_open - Called when a network interface is made active
5272 * @netdev: network interface device structure
5273 *
5274 * The open entry point is called when a network interface is made
5275 * active by the system (IFF_UP). At this point all resources needed
5276 * for transmit and receive operations are allocated, the interrupt
5277 * handler is registered with the OS, the netdev watchdog subtask is
5278 * enabled, and the stack is notified that the interface is ready.
5279 *
5280 * Returns 0 on success, negative value on failure
5281 **/
38e00438 5282int i40e_open(struct net_device *netdev)
41c445ff
JB		 5283{
5284 struct i40e_netdev_priv *np = netdev_priv(netdev);
5285 struct i40e_vsi *vsi = np->vsi;
5286 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5287 int err;
5288
4eb3f768
SN		 5289 /* disallow open during test or if eeprom is broken */
5290 if (test_bit(__I40E_TESTING, &pf->state) ||
5291 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5292 return -EBUSY;
5293
5294 netif_carrier_off(netdev);
5295
6c167f58
EK		 5296 err = i40e_vsi_open(vsi);
5297 if (err)
5298 return err;
5299
059dab69
JB		 5300 /* configure global TSO hardware offload settings */
5301 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5302 TCP_FLAG_FIN) >> 16);
5303 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5304 TCP_FLAG_FIN |
5305 TCP_FLAG_CWR) >> 16);
5306 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5307
6c167f58
EK		 5308#ifdef CONFIG_I40E_VXLAN
5309 vxlan_get_rx_port(netdev);
5310#endif
5311
5312 return 0;
5313}
5314
5315/**
5316 * i40e_vsi_open -
5317 * @vsi: the VSI to open
5318 *
5319 * Finish initialization of the VSI.
5320 *
5321 * Returns 0 on success, negative value on failure
5322 **/
5323int i40e_vsi_open(struct i40e_vsi *vsi)
5324{
5325 struct i40e_pf *pf = vsi->back;
b294ac70 5326 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5327 int err;
5328
41c445ff
JB		 5329 /* allocate descriptors */
5330 err = i40e_vsi_setup_tx_resources(vsi);
5331 if (err)
5332 goto err_setup_tx;
5333 err = i40e_vsi_setup_rx_resources(vsi);
5334 if (err)
5335 goto err_setup_rx;
5336
5337 err = i40e_vsi_configure(vsi);
5338 if (err)
5339 goto err_setup_rx;
5340
c22e3c6c
SN		 5341 if (vsi->netdev) {
5342 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5343 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5344 err = i40e_vsi_request_irq(vsi, int_name);
5345 if (err)
5346 goto err_setup_rx;
41c445ff 5347
c22e3c6c
SN		 5348 /* Notify the stack of the actual queue counts. */
5349 err = netif_set_real_num_tx_queues(vsi->netdev,
5350 vsi->num_queue_pairs);
5351 if (err)
5352 goto err_set_queues;
25946ddb 5353
c22e3c6c
SN		 5354 err = netif_set_real_num_rx_queues(vsi->netdev,
5355 vsi->num_queue_pairs);
5356 if (err)
5357 goto err_set_queues;
8a9eb7d3
SN		 5358
5359 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5360 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5361 dev_driver_string(&pf->pdev->dev),
5362 dev_name(&pf->pdev->dev));
8a9eb7d3 5363 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5364
c22e3c6c 5365 } else {
ce9ccb17 5366 err = -EINVAL;
6c167f58
EK		 5367 goto err_setup_rx;
5368 }
25946ddb 5369
41c445ff
JB		 5370 err = i40e_up_complete(vsi);
5371 if (err)
5372 goto err_up_complete;
5373
41c445ff
JB		 5374 return 0;
5375
5376err_up_complete:
5377 i40e_down(vsi);
25946ddb 5378err_set_queues:
41c445ff
JB		 5379 i40e_vsi_free_irq(vsi);
5380err_setup_rx:
5381 i40e_vsi_free_rx_resources(vsi);
5382err_setup_tx:
5383 i40e_vsi_free_tx_resources(vsi);
5384 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5385 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5386
5387 return err;
5388}
5389
17a73f6b
JG		 5390/**
5391 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5392 * @pf: Pointer to PF
17a73f6b
JG		 5393 *
5394 * This function destroys the hlist where all the Flow Director
5395 * filters were saved.
5396 **/
5397static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5398{
5399 struct i40e_fdir_filter *filter;
5400 struct hlist_node *node2;
5401
5402 hlist_for_each_entry_safe(filter, node2,
5403 &pf->fdir_filter_list, fdir_node) {
5404 hlist_del(&filter->fdir_node);
5405 kfree(filter);
5406 }
5407 pf->fdir_pf_active_filters = 0;
5408}
5409
41c445ff
JB		 5410/**
5411 * i40e_close - Disables a network interface
5412 * @netdev: network interface device structure
5413 *
5414 * The close entry point is called when an interface is de-activated
5415 * by the OS. The hardware is still under the driver's control, but
5416 * this netdev interface is disabled.
5417 *
5418 * Returns 0, this is not allowed to fail
5419 **/
38e00438
VD		 5420#ifdef I40E_FCOE
5421int i40e_close(struct net_device *netdev)
5422#else
41c445ff 5423static int i40e_close(struct net_device *netdev)
38e00438 5424#endif
41c445ff
JB		 5425{
5426 struct i40e_netdev_priv *np = netdev_priv(netdev);
5427 struct i40e_vsi *vsi = np->vsi;
5428
90ef8d47 5429 i40e_vsi_close(vsi);
41c445ff
JB		 5430
5431 return 0;
5432}
5433
5434/**
5435 * i40e_do_reset - Start a PF or Core Reset sequence
5436 * @pf: board private structure
5437 * @reset_flags: which reset is requested
5438 *
5439 * The essential difference in resets is that the PF Reset
5440 * doesn't clear the packet buffers, doesn't reset the PE
5441 * firmware, and doesn't bother the other PFs on the chip.
5442 **/
5443void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5444{
5445 u32 val;
5446
5447 WARN_ON(in_interrupt());
5448
263fc48f
MW		 5449 if (i40e_check_asq_alive(&pf->hw))
5450 i40e_vc_notify_reset(pf);
5451
41c445ff 5452 /* do the biggest reset indicated */
41a1d04b 5453 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5454
5455 /* Request a Global Reset
5456 *
5457 * This will start the chip's countdown to the actual full
5458 * chip reset event, and a warning interrupt to be sent
5459 * to all PFs, including the requestor. Our handler
5460 * for the warning interrupt will deal with the shutdown
5461 * and recovery of the switch setup.
5462 */
69bfb110 5463 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5464 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5465 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5466 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5467
41a1d04b 5468 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5469
5470 /* Request a Core Reset
5471 *
5472 * Same as Global Reset, except does *not* include the MAC/PHY
5473 */
69bfb110 5474 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5475 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5476 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5477 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5478 i40e_flush(&pf->hw);
5479
41a1d04b 5480 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5481
5482 /* Request a PF Reset
5483 *
5484 * Resets only the PF-specific registers
5485 *
5486 * This goes directly to the tear-down and rebuild of
5487 * the switch, since we need to do all the recovery as
5488 * for the Core Reset.
5489 */
69bfb110 5490 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5491 i40e_handle_reset_warning(pf);
5492
41a1d04b 5493 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5494 int v;
5495
5496 /* Find the VSI(s) that requested a re-init */
5497 dev_info(&pf->pdev->dev,
5498 "VSI reinit requested\n");
505682cd 5499 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5500 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5501
41c445ff
JB		 5502 if (vsi != NULL &&
5503 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5504 i40e_vsi_reinit_locked(pf->vsi[v]);
5505 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5506 }
5507 }
41a1d04b 5508 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5509 int v;
5510
5511 /* Find the VSI(s) that needs to be brought down */
5512 dev_info(&pf->pdev->dev, "VSI down requested\n");
5513 for (v = 0; v < pf->num_alloc_vsi; v++) {
5514 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5515
b5d06f05
NP		 5516 if (vsi != NULL &&
5517 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5518 set_bit(__I40E_DOWN, &vsi->state);
5519 i40e_down(vsi);
5520 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5521 }
5522 }
41c445ff
JB		 5523 } else {
5524 dev_info(&pf->pdev->dev,
5525 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5526 }
5527}
5528
4e3b35b0
NP		 5529#ifdef CONFIG_I40E_DCB
5530/**
5531 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5532 * @pf: board private structure
5533 * @old_cfg: current DCB config
5534 * @new_cfg: new DCB config
5535 **/
5536bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5537 struct i40e_dcbx_config *old_cfg,
5538 struct i40e_dcbx_config *new_cfg)
5539{
5540 bool need_reconfig = false;
5541
5542 /* Check if ETS configuration has changed */
5543 if (memcmp(&new_cfg->etscfg,
5544 &old_cfg->etscfg,
5545 sizeof(new_cfg->etscfg))) {
5546 /* If Priority Table has changed reconfig is needed */
5547 if (memcmp(&new_cfg->etscfg.prioritytable,
5548 &old_cfg->etscfg.prioritytable,
5549 sizeof(new_cfg->etscfg.prioritytable))) {
5550 need_reconfig = true;
69bfb110 5551 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5552 }
5553
5554 if (memcmp(&new_cfg->etscfg.tcbwtable,
5555 &old_cfg->etscfg.tcbwtable,
5556 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5557 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5558
5559 if (memcmp(&new_cfg->etscfg.tsatable,
5560 &old_cfg->etscfg.tsatable,
5561 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5562 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5563 }
5564
5565 /* Check if PFC configuration has changed */
5566 if (memcmp(&new_cfg->pfc,
5567 &old_cfg->pfc,
5568 sizeof(new_cfg->pfc))) {
5569 need_reconfig = true;
69bfb110 5570 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5571 }
5572
5573 /* Check if APP Table has changed */
5574 if (memcmp(&new_cfg->app,
5575 &old_cfg->app,
3d9667a9 5576 sizeof(new_cfg->app))) {
4e3b35b0 5577 need_reconfig = true;
69bfb110 5578 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5579 }
4e3b35b0 5580
fb43201f 5581 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5582 return need_reconfig;
5583}
5584
5585/**
5586 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5587 * @pf: board private structure
5588 * @e: event info posted on ARQ
5589 **/
5590static int i40e_handle_lldp_event(struct i40e_pf *pf,
5591 struct i40e_arq_event_info *e)
5592{
5593 struct i40e_aqc_lldp_get_mib *mib =
5594 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5595 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5596 struct i40e_dcbx_config tmp_dcbx_cfg;
5597 bool need_reconfig = false;
5598 int ret = 0;
5599 u8 type;
5600
4d9b6043
NP		 5601 /* Not DCB capable or capability disabled */
5602 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5603 return ret;
5604
4e3b35b0
NP		 5605 /* Ignore if event is not for Nearest Bridge */
5606 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5607 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5608 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5609 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5610 return ret;
5611
5612 /* Check MIB Type and return if event for Remote MIB update */
5613 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5614 dev_dbg(&pf->pdev->dev,
fb43201f 5615 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5616 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5617 /* Update the remote cached instance and return */
5618 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5619 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5620 &hw->remote_dcbx_config);
5621 goto exit;
5622 }
5623
9fa61dd2 5624 /* Store the old configuration */
1a2f6248 5625 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5626
750fcbcf
NP		 5627 /* Reset the old DCBx configuration data */
5628 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5629 /* Get updated DCBX data from firmware */
5630 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5631 if (ret) {
f1c7e72e
SN		 5632 dev_info(&pf->pdev->dev,
5633 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5634 i40e_stat_str(&pf->hw, ret),
5635 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5636 goto exit;
5637 }
5638
5639 /* No change detected in DCBX configs */
750fcbcf
NP		 5640 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5641 sizeof(tmp_dcbx_cfg))) {
69bfb110 5642 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5643 goto exit;
5644 }
5645
750fcbcf
NP		 5646 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5647 &hw->local_dcbx_config);
4e3b35b0 5648
750fcbcf 5649 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5650
5651 if (!need_reconfig)
5652 goto exit;
5653
4d9b6043 5654 /* Enable DCB tagging only when more than one TC */
750fcbcf 5655 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5656 pf->flags |= I40E_FLAG_DCB_ENABLED;
5657 else
5658 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5659
69129dc3 5660 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5661 /* Reconfiguration needed quiesce all VSIs */
5662 i40e_pf_quiesce_all_vsi(pf);
5663
5664 /* Changes in configuration update VEB/VSI */
5665 i40e_dcb_reconfigure(pf);
5666
2fd75f31
NP		 5667 ret = i40e_resume_port_tx(pf);
5668
69129dc3 5669 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5670 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5671 if (ret)
5672 goto exit;
5673
5674 /* Wait for the PF's Tx queues to be disabled */
5675 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5676 if (ret) {
5677 /* Schedule PF reset to recover */
5678 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5679 i40e_service_event_schedule(pf);
5680 } else {
2fd75f31 5681 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5682 }
5683
4e3b35b0
NP		 5684exit:
5685 return ret;
5686}
5687#endif /* CONFIG_I40E_DCB */
5688
23326186
ASJ		 5689/**
5690 * i40e_do_reset_safe - Protected reset path for userland calls.
5691 * @pf: board private structure
5692 * @reset_flags: which reset is requested
5693 *
5694 **/
5695void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5696{
5697 rtnl_lock();
5698 i40e_do_reset(pf, reset_flags);
5699 rtnl_unlock();
5700}
5701
41c445ff
JB		 5702/**
5703 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5704 * @pf: board private structure
5705 * @e: event info posted on ARQ
5706 *
5707 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5708 * and VF queues
5709 **/
5710static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5711 struct i40e_arq_event_info *e)
5712{
5713 struct i40e_aqc_lan_overflow *data =
5714 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5715 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5716 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5717 struct i40e_hw *hw = &pf->hw;
5718 struct i40e_vf *vf;
5719 u16 vf_id;
5720
69bfb110
JB		 5721 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5722 queue, qtx_ctl);
41c445ff
JB		 5723
5724 /* Queue belongs to VF, find the VF and issue VF reset */
5725 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5726 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5727 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5728 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5729 vf_id -= hw->func_caps.vf_base_id;
5730 vf = &pf->vf[vf_id];
5731 i40e_vc_notify_vf_reset(vf);
5732 /* Allow VF to process pending reset notification */
5733 msleep(20);
5734 i40e_reset_vf(vf, false);
5735 }
5736}
5737
5738/**
5739 * i40e_service_event_complete - Finish up the service event
5740 * @pf: board private structure
5741 **/
5742static void i40e_service_event_complete(struct i40e_pf *pf)
5743{
b875f99b 5744 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5745
5746 /* flush memory to make sure state is correct before next watchog */
4e857c58 5747 smp_mb__before_atomic();
41c445ff
JB		 5748 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5749}
5750
55a5e60b 5751/**
12957388
ASJ		 5752 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5753 * @pf: board private structure
5754 **/
04294e38 5755u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5756{
04294e38 5757 u32 val, fcnt_prog;
12957388
ASJ		 5758
5759 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5760 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5761 return fcnt_prog;
5762}
5763
5764/**
04294e38 5765 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5766 * @pf: board private structure
5767 **/
04294e38 5768u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5769{
04294e38
ASJ		 5770 u32 val, fcnt_prog;
5771
55a5e60b
ASJ		 5772 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5773 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5774 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5775 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5776 return fcnt_prog;
5777}
1e1be8f6 5778
04294e38
ASJ		 5779/**
5780 * i40e_get_global_fd_count - Get total FD filters programmed on device
5781 * @pf: board private structure
5782 **/
5783u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5784{
5785 u32 val, fcnt_prog;
5786
5787 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5788 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5789 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5790 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5791 return fcnt_prog;
5792}
5793
55a5e60b
ASJ		 5794/**
5795 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5796 * @pf: board private structure
5797 **/
5798void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5799{
3487b6c3 5800 struct i40e_fdir_filter *filter;
55a5e60b 5801 u32 fcnt_prog, fcnt_avail;
3487b6c3 5802 struct hlist_node *node;
55a5e60b 5803
1e1be8f6
ASJ		 5804 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5805 return;
5806
55a5e60b
ASJ		 5807 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5808 * to re-enable
5809 */
04294e38 5810 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5811 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5812 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5813 (pf->fd_add_err == 0) ||
5814 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5815 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5816 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5817 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5818 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5819 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5820 }
5821 }
5822 /* Wait for some more space to be available to turn on ATR */
5823 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5824 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5825 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5826 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5827 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5828 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5829 }
5830 }
3487b6c3
CW		 5831
5832 /* if hw had a problem adding a filter, delete it */
5833 if (pf->fd_inv > 0) {
5834 hlist_for_each_entry_safe(filter, node,
5835 &pf->fdir_filter_list, fdir_node) {
5836 if (filter->fd_id == pf->fd_inv) {
5837 hlist_del(&filter->fdir_node);
5838 kfree(filter);
5839 pf->fdir_pf_active_filters--;
5840 }
5841 }
5842 }
55a5e60b
ASJ		 5843}
5844
1e1be8f6 5845#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5846#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5847/**
5848 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5849 * @pf: board private structure
5850 **/
5851static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5852{
04294e38 5853 unsigned long min_flush_time;
1e1be8f6 5854 int flush_wait_retry = 50;
04294e38
ASJ		 5855 bool disable_atr = false;
5856 int fd_room;
1e1be8f6
ASJ		 5857 int reg;
5858
1790ed0c
AA		 5859 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5860 return;
5861
a5fdaf34
JB		 5862 if (!time_after(jiffies, pf->fd_flush_timestamp +
5863 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5864 return;
04294e38 5865
a5fdaf34
JB		 5866 /* If the flush is happening too quick and we have mostly SB rules we
5867 * should not re-enable ATR for some time.
5868 */
5869 min_flush_time = pf->fd_flush_timestamp +
5870 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5871 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5872
5873 if (!(time_after(jiffies, min_flush_time)) &&
5874 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5875 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5876 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5877 disable_atr = true;
5878 }
5879
5880 pf->fd_flush_timestamp = jiffies;
5881 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5882 /* flush all filters */
5883 wr32(&pf->hw, I40E_PFQF_CTL_1,
5884 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5885 i40e_flush(&pf->hw);
5886 pf->fd_flush_cnt++;
5887 pf->fd_add_err = 0;
5888 do {
5889 /* Check FD flush status every 5-6msec */
5890 usleep_range(5000, 6000);
5891 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5892 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5893 break;
5894 } while (flush_wait_retry--);
5895 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5896 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5897 } else {
5898 /* replay sideband filters */
5899 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5900 if (!disable_atr)
5901 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5902 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5903 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5904 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5905 }
a5fdaf34 5906
1e1be8f6
ASJ		 5907}
5908
5909/**
5910 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5911 * @pf: board private structure
5912 **/
04294e38 5913u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5914{
5915 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5916}
5917
5918/* We can see up to 256 filter programming desc in transit if the filters are
5919 * being applied really fast; before we see the first
5920 * filter miss error on Rx queue 0. Accumulating enough error messages before
5921 * reacting will make sure we don't cause flush too often.
5922 */
5923#define I40E_MAX_FD_PROGRAM_ERROR 256
5924
41c445ff
JB		 5925/**
5926 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5927 * @pf: board private structure
5928 **/
5929static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5930{
41c445ff 5931
41c445ff
JB		 5932 /* if interface is down do nothing */
5933 if (test_bit(__I40E_DOWN, &pf->state))
5934 return;
1e1be8f6 5935
1790ed0c
AA		 5936 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5937 return;
5938
04294e38 5939 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5940 i40e_fdir_flush_and_replay(pf);
5941
55a5e60b
ASJ		 5942 i40e_fdir_check_and_reenable(pf);
5943
41c445ff
JB		 5944}
5945
5946/**
5947 * i40e_vsi_link_event - notify VSI of a link event
5948 * @vsi: vsi to be notified
5949 * @link_up: link up or down
5950 **/
5951static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5952{
32b5b811 5953 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5954 return;
5955
5956 switch (vsi->type) {
5957 case I40E_VSI_MAIN:
38e00438
VD		 5958#ifdef I40E_FCOE
5959 case I40E_VSI_FCOE:
5960#endif
41c445ff
JB		 5961 if (!vsi->netdev || !vsi->netdev_registered)
5962 break;
5963
5964 if (link_up) {
5965 netif_carrier_on(vsi->netdev);
5966 netif_tx_wake_all_queues(vsi->netdev);
5967 } else {
5968 netif_carrier_off(vsi->netdev);
5969 netif_tx_stop_all_queues(vsi->netdev);
5970 }
5971 break;
5972
5973 case I40E_VSI_SRIOV:
41c445ff
JB		 5974 case I40E_VSI_VMDQ2:
5975 case I40E_VSI_CTRL:
5976 case I40E_VSI_MIRROR:
5977 default:
5978 /* there is no notification for other VSIs */
5979 break;
5980 }
5981}
5982
5983/**
5984 * i40e_veb_link_event - notify elements on the veb of a link event
5985 * @veb: veb to be notified
5986 * @link_up: link up or down
5987 **/
5988static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5989{
5990 struct i40e_pf *pf;
5991 int i;
5992
5993 if (!veb || !veb->pf)
5994 return;
5995 pf = veb->pf;
5996
5997 /* depth first... */
5998 for (i = 0; i < I40E_MAX_VEB; i++)
5999 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6000 i40e_veb_link_event(pf->veb[i], link_up);
6001
6002 /* ... now the local VSIs */
505682cd 6003 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6004 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6005 i40e_vsi_link_event(pf->vsi[i], link_up);
6006}
6007
6008/**
6009 * i40e_link_event - Update netif_carrier status
6010 * @pf: board private structure
6011 **/
6012static void i40e_link_event(struct i40e_pf *pf)
6013{
320684cd 6014 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6015 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6016 i40e_status status;
6017 bool new_link, old_link;
41c445ff 6018
1e701e09
JB		 6019 /* set this to force the get_link_status call to refresh state */
6020 pf->hw.phy.get_link_info = true;
6021
41c445ff 6022 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6023
6024 status = i40e_get_link_status(&pf->hw, &new_link);
6025 if (status) {
6026 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6027 status);
6028 return;
6029 }
6030
fef59ddf
CS		 6031 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6032 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6033
1e701e09 6034 if (new_link == old_link &&
fef59ddf 6035 new_link_speed == old_link_speed &&
320684cd
MW		 6036 (test_bit(__I40E_DOWN, &vsi->state) ||
6037 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6038 return;
320684cd
MW		 6039
6040 if (!test_bit(__I40E_DOWN, &vsi->state))
6041 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6042
6043 /* Notify the base of the switch tree connected to
6044 * the link. Floating VEBs are not notified.
6045 */
6046 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6047 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6048 else
320684cd 6049 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6050
6051 if (pf->vf)
6052 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6053
6054 if (pf->flags & I40E_FLAG_PTP)
6055 i40e_ptp_set_increment(pf);
41c445ff
JB		 6056}
6057
41c445ff 6058/**
21536717 6059 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6060 * @pf: board private structure
6061 **/
6062static void i40e_watchdog_subtask(struct i40e_pf *pf)
6063{
6064 int i;
6065
6066 /* if interface is down do nothing */
6067 if (test_bit(__I40E_DOWN, &pf->state) ||
6068 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6069 return;
6070
21536717
SN		 6071 /* make sure we don't do these things too often */
6072 if (time_before(jiffies, (pf->service_timer_previous +
6073 pf->service_timer_period)))
6074 return;
6075 pf->service_timer_previous = jiffies;
6076
9ac77266
SN		 6077 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6078 i40e_link_event(pf);
21536717 6079
41c445ff
JB		 6080 /* Update the stats for active netdevs so the network stack
6081 * can look at updated numbers whenever it cares to
6082 */
505682cd 6083 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6084 if (pf->vsi[i] && pf->vsi[i]->netdev)
6085 i40e_update_stats(pf->vsi[i]);
6086
d1a8d275
ASJ		 6087 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6088 /* Update the stats for the active switching components */
6089 for (i = 0; i < I40E_MAX_VEB; i++)
6090 if (pf->veb[i])
6091 i40e_update_veb_stats(pf->veb[i]);
6092 }
beb0dff1
JK		 6093
6094 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6095}
6096
6097/**
6098 * i40e_reset_subtask - Set up for resetting the device and driver
6099 * @pf: board private structure
6100 **/
6101static void i40e_reset_subtask(struct i40e_pf *pf)
6102{
6103 u32 reset_flags = 0;
6104
23326186 6105 rtnl_lock();
41c445ff 6106 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 6107 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6108 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6109 }
6110 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 6111 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6112 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6113 }
6114 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 6115 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6116 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6117 }
6118 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 6119 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6120 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6121 }
b5d06f05 6122 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 6123 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6124 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6125 }
41c445ff
JB		 6126
6127 /* If there's a recovery already waiting, it takes
6128 * precedence before starting a new reset sequence.
6129 */
6130 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6131 i40e_handle_reset_warning(pf);
23326186 6132 goto unlock;
41c445ff
JB		 6133 }
6134
6135 /* If we're already down or resetting, just bail */
6136 if (reset_flags &&
6137 !test_bit(__I40E_DOWN, &pf->state) &&
6138 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6139 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6140
6141unlock:
6142 rtnl_unlock();
41c445ff
JB		 6143}
6144
6145/**
6146 * i40e_handle_link_event - Handle link event
6147 * @pf: board private structure
6148 * @e: event info posted on ARQ
6149 **/
6150static void i40e_handle_link_event(struct i40e_pf *pf,
6151 struct i40e_arq_event_info *e)
6152{
6153 struct i40e_hw *hw = &pf->hw;
6154 struct i40e_aqc_get_link_status *status =
6155 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 6156
6157 /* save off old link status information */
1a2f6248 6158 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 6159
1e701e09
JB		 6160 /* Do a new status request to re-enable LSE reporting
6161 * and load new status information into the hw struct
6162 * This completely ignores any state information
6163 * in the ARQ event info, instead choosing to always
6164 * issue the AQ update link status command.
6165 */
6166 i40e_link_event(pf);
6167
7b592f61
CW		 6168 /* check for unqualified module, if link is down */
6169 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6170 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6171 (!(status->link_info & I40E_AQ_LINK_UP)))
6172 dev_err(&pf->pdev->dev,
6173 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6174}
6175
6176/**
6177 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6178 * @pf: board private structure
6179 **/
6180static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6181{
6182 struct i40e_arq_event_info event;
6183 struct i40e_hw *hw = &pf->hw;
6184 u16 pending, i = 0;
6185 i40e_status ret;
6186 u16 opcode;
86df242b 6187 u32 oldval;
41c445ff
JB		 6188 u32 val;
6189
a316f651
ASJ		 6190 /* Do not run clean AQ when PF reset fails */
6191 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6192 return;
6193
86df242b
SN		 6194 /* check for error indications */
6195 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6196 oldval = val;
6197 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6198 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6199 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6200 }
6201 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6202 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6203 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6204 }
6205 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6206 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6207 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6208 }
6209 if (oldval != val)
6210 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6211
6212 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6213 oldval = val;
6214 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6215 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6216 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6217 }
6218 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6219 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6220 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6221 }
6222 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6223 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6224 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6225 }
6226 if (oldval != val)
6227 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6228
1001dc37
MW		 6229 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6230 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6231 if (!event.msg_buf)
6232 return;
6233
6234 do {
6235 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6236 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6237 break;
56497978 6238 else if (ret) {
41c445ff
JB		 6239 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6240 break;
6241 }
6242
6243 opcode = le16_to_cpu(event.desc.opcode);
6244 switch (opcode) {
6245
6246 case i40e_aqc_opc_get_link_status:
6247 i40e_handle_link_event(pf, &event);
6248 break;
6249 case i40e_aqc_opc_send_msg_to_pf:
6250 ret = i40e_vc_process_vf_msg(pf,
6251 le16_to_cpu(event.desc.retval),
6252 le32_to_cpu(event.desc.cookie_high),
6253 le32_to_cpu(event.desc.cookie_low),
6254 event.msg_buf,
1001dc37 6255 event.msg_len);
41c445ff
JB		 6256 break;
6257 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6258 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6259#ifdef CONFIG_I40E_DCB
6260 rtnl_lock();
6261 ret = i40e_handle_lldp_event(pf, &event);
6262 rtnl_unlock();
6263#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6264 break;
6265 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6266 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6267 i40e_handle_lan_overflow_event(pf, &event);
6268 break;
0467bc91
SN		 6269 case i40e_aqc_opc_send_msg_to_peer:
6270 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6271 break;
91a0f930
SN		 6272 case i40e_aqc_opc_nvm_erase:
6273 case i40e_aqc_opc_nvm_update:
6274 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6275 break;
41c445ff
JB		 6276 default:
6277 dev_info(&pf->pdev->dev,
0467bc91
SN		 6278 "ARQ Error: Unknown event 0x%04x received\n",
6279 opcode);
41c445ff
JB		 6280 break;
6281 }
6282 } while (pending && (i++ < pf->adminq_work_limit));
6283
6284 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6285 /* re-enable Admin queue interrupt cause */
6286 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6287 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6288 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6289 i40e_flush(hw);
6290
6291 kfree(event.msg_buf);
6292}
6293
4eb3f768
SN		 6294/**
6295 * i40e_verify_eeprom - make sure eeprom is good to use
6296 * @pf: board private structure
6297 **/
6298static void i40e_verify_eeprom(struct i40e_pf *pf)
6299{
6300 int err;
6301
6302 err = i40e_diag_eeprom_test(&pf->hw);
6303 if (err) {
6304 /* retry in case of garbage read */
6305 err = i40e_diag_eeprom_test(&pf->hw);
6306 if (err) {
6307 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6308 err);
6309 set_bit(__I40E_BAD_EEPROM, &pf->state);
6310 }
6311 }
6312
6313 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6314 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6315 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6316 }
6317}
6318
386a0afa
AA		 6319/**
6320 * i40e_enable_pf_switch_lb
b40c82e6 6321 * @pf: pointer to the PF structure
386a0afa
AA		 6322 *
6323 * enable switch loop back or die - no point in a return value
6324 **/
6325static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6326{
6327 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6328 struct i40e_vsi_context ctxt;
f1c7e72e 6329 int ret;
386a0afa
AA		 6330
6331 ctxt.seid = pf->main_vsi_seid;
6332 ctxt.pf_num = pf->hw.pf_id;
6333 ctxt.vf_num = 0;
f1c7e72e
SN		 6334 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6335 if (ret) {
386a0afa 6336 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6337 "couldn't get PF vsi config, err %s aq_err %s\n",
6338 i40e_stat_str(&pf->hw, ret),
6339 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6340 return;
6341 }
6342 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6343 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6344 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6345
f1c7e72e
SN		 6346 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6347 if (ret) {
386a0afa 6348 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6349 "update vsi switch failed, err %s aq_err %s\n",
6350 i40e_stat_str(&pf->hw, ret),
6351 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6352 }
6353}
6354
6355/**
6356 * i40e_disable_pf_switch_lb
b40c82e6 6357 * @pf: pointer to the PF structure
386a0afa
AA		 6358 *
6359 * disable switch loop back or die - no point in a return value
6360 **/
6361static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6362{
6363 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6364 struct i40e_vsi_context ctxt;
f1c7e72e 6365 int ret;
386a0afa
AA		 6366
6367 ctxt.seid = pf->main_vsi_seid;
6368 ctxt.pf_num = pf->hw.pf_id;
6369 ctxt.vf_num = 0;
f1c7e72e
SN		 6370 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6371 if (ret) {
386a0afa 6372 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6373 "couldn't get PF vsi config, err %s aq_err %s\n",
6374 i40e_stat_str(&pf->hw, ret),
6375 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6376 return;
6377 }
6378 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6379 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6380 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6381
f1c7e72e
SN		 6382 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6383 if (ret) {
386a0afa 6384 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6385 "update vsi switch failed, err %s aq_err %s\n",
6386 i40e_stat_str(&pf->hw, ret),
6387 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6388 }
6389}
6390
51616018
NP		 6391/**
6392 * i40e_config_bridge_mode - Configure the HW bridge mode
6393 * @veb: pointer to the bridge instance
6394 *
6395 * Configure the loop back mode for the LAN VSI that is downlink to the
6396 * specified HW bridge instance. It is expected this function is called
6397 * when a new HW bridge is instantiated.
6398 **/
6399static void i40e_config_bridge_mode(struct i40e_veb *veb)
6400{
6401 struct i40e_pf *pf = veb->pf;
6402
6dec1017
SN		 6403 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6404 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6405 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6406 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6407 i40e_disable_pf_switch_lb(pf);
6408 else
6409 i40e_enable_pf_switch_lb(pf);
6410}
6411
41c445ff
JB		 6412/**
6413 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6414 * @veb: pointer to the VEB instance
6415 *
6416 * This is a recursive function that first builds the attached VSIs then
6417 * recurses in to build the next layer of VEB. We track the connections
6418 * through our own index numbers because the seid's from the HW could
6419 * change across the reset.
6420 **/
6421static int i40e_reconstitute_veb(struct i40e_veb *veb)
6422{
6423 struct i40e_vsi *ctl_vsi = NULL;
6424 struct i40e_pf *pf = veb->pf;
6425 int v, veb_idx;
6426 int ret;
6427
6428 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6429 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6430 if (pf->vsi[v] &&
6431 pf->vsi[v]->veb_idx == veb->idx &&
6432 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6433 ctl_vsi = pf->vsi[v];
6434 break;
6435 }
6436 }
6437 if (!ctl_vsi) {
6438 dev_info(&pf->pdev->dev,
6439 "missing owner VSI for veb_idx %d\n", veb->idx);
6440 ret = -ENOENT;
6441 goto end_reconstitute;
6442 }
6443 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6444 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6445 ret = i40e_add_vsi(ctl_vsi);
6446 if (ret) {
6447 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6448 "rebuild of veb_idx %d owner VSI failed: %d\n",
6449 veb->idx, ret);
41c445ff
JB		 6450 goto end_reconstitute;
6451 }
6452 i40e_vsi_reset_stats(ctl_vsi);
6453
6454 /* create the VEB in the switch and move the VSI onto the VEB */
6455 ret = i40e_add_veb(veb, ctl_vsi);
6456 if (ret)
6457 goto end_reconstitute;
6458
fc60861e
ASJ		 6459 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6460 veb->bridge_mode = BRIDGE_MODE_VEB;
6461 else
6462 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6463 i40e_config_bridge_mode(veb);
b64ba084 6464
41c445ff 6465 /* create the remaining VSIs attached to this VEB */
505682cd 6466 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6467 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6468 continue;
6469
6470 if (pf->vsi[v]->veb_idx == veb->idx) {
6471 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6472
41c445ff
JB		 6473 vsi->uplink_seid = veb->seid;
6474 ret = i40e_add_vsi(vsi);
6475 if (ret) {
6476 dev_info(&pf->pdev->dev,
6477 "rebuild of vsi_idx %d failed: %d\n",
6478 v, ret);
6479 goto end_reconstitute;
6480 }
6481 i40e_vsi_reset_stats(vsi);
6482 }
6483 }
6484
6485 /* create any VEBs attached to this VEB - RECURSION */
6486 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6487 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6488 pf->veb[veb_idx]->uplink_seid = veb->seid;
6489 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6490 if (ret)
6491 break;
6492 }
6493 }
6494
6495end_reconstitute:
6496 return ret;
6497}
6498
6499/**
6500 * i40e_get_capabilities - get info about the HW
6501 * @pf: the PF struct
6502 **/
6503static int i40e_get_capabilities(struct i40e_pf *pf)
6504{
6505 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6506 u16 data_size;
6507 int buf_len;
6508 int err;
6509
6510 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6511 do {
6512 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6513 if (!cap_buf)
6514 return -ENOMEM;
6515
6516 /* this loads the data into the hw struct for us */
6517 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6518 &data_size,
6519 i40e_aqc_opc_list_func_capabilities,
6520 NULL);
6521 /* data loaded, buffer no longer needed */
6522 kfree(cap_buf);
6523
6524 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6525 /* retry with a larger buffer */
6526 buf_len = data_size;
6527 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6528 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6529 "capability discovery failed, err %s aq_err %s\n",
6530 i40e_stat_str(&pf->hw, err),
6531 i40e_aq_str(&pf->hw,
6532 pf->hw.aq.asq_last_status));
41c445ff
JB		 6533 return -ENODEV;
6534 }
6535 } while (err);
6536
6537 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6538 dev_info(&pf->pdev->dev,
6539 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6540 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6541 pf->hw.func_caps.num_msix_vectors,
6542 pf->hw.func_caps.num_msix_vectors_vf,
6543 pf->hw.func_caps.fd_filters_guaranteed,
6544 pf->hw.func_caps.fd_filters_best_effort,
6545 pf->hw.func_caps.num_tx_qp,
6546 pf->hw.func_caps.num_vsis);
6547
7134f9ce
JB		 6548#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6549 + pf->hw.func_caps.num_vfs)
6550 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6551 dev_info(&pf->pdev->dev,
6552 "got num_vsis %d, setting num_vsis to %d\n",
6553 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6554 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6555 }
6556
41c445ff
JB		 6557 return 0;
6558}
6559
cbf61325
ASJ		 6560static int i40e_vsi_clear(struct i40e_vsi *vsi);
6561
41c445ff 6562/**
cbf61325 6563 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6564 * @pf: board private structure
6565 **/
cbf61325 6566static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6567{
6568 struct i40e_vsi *vsi;
8a9eb7d3 6569 int i;
41c445ff 6570
407e063c
JB		 6571 /* quick workaround for an NVM issue that leaves a critical register
6572 * uninitialized
6573 */
6574 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6575 static const u32 hkey[] = {
6576 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6577 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6578 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6579 0x95b3a76d};
6580
6581 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6582 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6583 }
6584
cbf61325 6585 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6586 return;
6587
cbf61325 6588 /* find existing VSI and see if it needs configuring */
41c445ff 6589 vsi = NULL;
505682cd 6590 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6591 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6592 vsi = pf->vsi[i];
cbf61325
ASJ		 6593 break;
6594 }
6595 }
6596
6597 /* create a new VSI if none exists */
41c445ff 6598 if (!vsi) {
cbf61325
ASJ		 6599 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6600 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6601 if (!vsi) {
6602 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6603 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6604 return;
41c445ff 6605 }
cbf61325 6606 }
41c445ff 6607
8a9eb7d3 6608 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6609}
6610
6611/**
6612 * i40e_fdir_teardown - release the Flow Director resources
6613 * @pf: board private structure
6614 **/
6615static void i40e_fdir_teardown(struct i40e_pf *pf)
6616{
6617 int i;
6618
17a73f6b 6619 i40e_fdir_filter_exit(pf);
505682cd 6620 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6621 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6622 i40e_vsi_release(pf->vsi[i]);
6623 break;
6624 }
6625 }
6626}
6627
6628/**
f650a38b 6629 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6630 * @pf: board private structure
6631 *
b40c82e6 6632 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6633 **/
23cfbe07 6634static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6635{
41c445ff 6636 struct i40e_hw *hw = &pf->hw;
60442dea 6637 i40e_status ret = 0;
41c445ff
JB		 6638 u32 v;
6639
6640 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6641 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6642 return;
41c445ff 6643
69bfb110 6644 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6645
41c445ff
JB		 6646 /* quiesce the VSIs and their queues that are not already DOWN */
6647 i40e_pf_quiesce_all_vsi(pf);
6648
505682cd 6649 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6650 if (pf->vsi[v])
6651 pf->vsi[v]->seid = 0;
6652 }
6653
6654 i40e_shutdown_adminq(&pf->hw);
6655
f650a38b 6656 /* call shutdown HMC */
60442dea
SN		 6657 if (hw->hmc.hmc_obj) {
6658 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6659 if (ret)
60442dea
SN		 6660 dev_warn(&pf->pdev->dev,
6661 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6662 }
f650a38b
ASJ		 6663}
6664
44033fac
JB		 6665/**
6666 * i40e_send_version - update firmware with driver version
6667 * @pf: PF struct
6668 */
6669static void i40e_send_version(struct i40e_pf *pf)
6670{
6671 struct i40e_driver_version dv;
6672
6673 dv.major_version = DRV_VERSION_MAJOR;
6674 dv.minor_version = DRV_VERSION_MINOR;
6675 dv.build_version = DRV_VERSION_BUILD;
6676 dv.subbuild_version = 0;
35a7d804 6677 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6678 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6679}
6680
f650a38b 6681/**
4dda12e6 6682 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6683 * @pf: board private structure
bc7d338f 6684 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6685 **/
bc7d338f 6686static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6687{
f650a38b 6688 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6689 u8 set_fc_aq_fail = 0;
f650a38b 6690 i40e_status ret;
4f2f017c 6691 u32 val;
f650a38b
ASJ		 6692 u32 v;
6693
41c445ff
JB		 6694 /* Now we wait for GRST to settle out.
6695 * We don't have to delete the VEBs or VSIs from the hw switch
6696 * because the reset will make them disappear.
6697 */
6698 ret = i40e_pf_reset(hw);
b5565400 6699 if (ret) {
41c445ff 6700 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6701 set_bit(__I40E_RESET_FAILED, &pf->state);
6702 goto clear_recovery;
b5565400 6703 }
41c445ff
JB		 6704 pf->pfr_count++;
6705
6706 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6707 goto clear_recovery;
69bfb110 6708 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6709
6710 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6711 ret = i40e_init_adminq(&pf->hw);
6712 if (ret) {
f1c7e72e
SN		 6713 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6714 i40e_stat_str(&pf->hw, ret),
6715 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6716 goto clear_recovery;
41c445ff
JB		 6717 }
6718
4eb3f768 6719 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6720 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6721 i40e_verify_eeprom(pf);
4eb3f768 6722
e78ac4bf 6723 i40e_clear_pxe_mode(hw);
41c445ff 6724 ret = i40e_get_capabilities(pf);
f1c7e72e 6725 if (ret)
41c445ff 6726 goto end_core_reset;
41c445ff 6727
41c445ff
JB		 6728 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6729 hw->func_caps.num_rx_qp,
6730 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6731 if (ret) {
6732 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6733 goto end_core_reset;
6734 }
6735 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6736 if (ret) {
6737 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6738 goto end_core_reset;
6739 }
6740
4e3b35b0
NP		 6741#ifdef CONFIG_I40E_DCB
6742 ret = i40e_init_pf_dcb(pf);
6743 if (ret) {
aebfc816
SN		 6744 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6745 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6746 /* Continue without DCB enabled */
4e3b35b0
NP		 6747 }
6748#endif /* CONFIG_I40E_DCB */
38e00438 6749#ifdef I40E_FCOE
21364bcf 6750 i40e_init_pf_fcoe(pf);
4e3b35b0 6751
38e00438 6752#endif
41c445ff 6753 /* do basic switch setup */
bc7d338f 6754 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6755 if (ret)
6756 goto end_core_reset;
6757
7e2453fe
JB		 6758 /* driver is only interested in link up/down and module qualification
6759 * reports from firmware
6760 */
6761 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6762 I40E_AQ_EVENT_LINK_UPDOWN |
6763 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6764 if (ret)
f1c7e72e
SN		 6765 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6766 i40e_stat_str(&pf->hw, ret),
6767 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6768
cafa2ee6
ASJ		 6769 /* make sure our flow control settings are restored */
6770 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6771 if (ret)
8279e495
NP		 6772 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6773 i40e_stat_str(&pf->hw, ret),
6774 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6775
41c445ff
JB		 6776 /* Rebuild the VSIs and VEBs that existed before reset.
6777 * They are still in our local switch element arrays, so only
6778 * need to rebuild the switch model in the HW.
6779 *
6780 * If there were VEBs but the reconstitution failed, we'll try
6781 * try to recover minimal use by getting the basic PF VSI working.
6782 */
6783 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6784 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6785 /* find the one VEB connected to the MAC, and find orphans */
6786 for (v = 0; v < I40E_MAX_VEB; v++) {
6787 if (!pf->veb[v])
6788 continue;
6789
6790 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6791 pf->veb[v]->uplink_seid == 0) {
6792 ret = i40e_reconstitute_veb(pf->veb[v]);
6793
6794 if (!ret)
6795 continue;
6796
6797 /* If Main VEB failed, we're in deep doodoo,
6798 * so give up rebuilding the switch and set up
6799 * for minimal rebuild of PF VSI.
6800 * If orphan failed, we'll report the error
6801 * but try to keep going.
6802 */
6803 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6804 dev_info(&pf->pdev->dev,
6805 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6806 ret);
6807 pf->vsi[pf->lan_vsi]->uplink_seid
6808 = pf->mac_seid;
6809 break;
6810 } else if (pf->veb[v]->uplink_seid == 0) {
6811 dev_info(&pf->pdev->dev,
6812 "rebuild of orphan VEB failed: %d\n",
6813 ret);
6814 }
6815 }
6816 }
6817 }
6818
6819 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6820 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6821 /* no VEB, so rebuild only the Main VSI */
6822 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6823 if (ret) {
6824 dev_info(&pf->pdev->dev,
6825 "rebuild of Main VSI failed: %d\n", ret);
6826 goto end_core_reset;
6827 }
6828 }
6829
4f2f017c
ASJ		 6830 /* Reconfigure hardware for allowing smaller MSS in the case
6831 * of TSO, so that we avoid the MDD being fired and causing
6832 * a reset in the case of small MSS+TSO.
6833 */
6834#define I40E_REG_MSS 0x000E64DC
6835#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6836#define I40E_64BYTE_MSS 0x400000
6837 val = rd32(hw, I40E_REG_MSS);
6838 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6839 val &= ~I40E_REG_MSS_MIN_MASK;
6840 val |= I40E_64BYTE_MSS;
6841 wr32(hw, I40E_REG_MSS, val);
6842 }
6843
025b4a54
ASJ		 6844 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6845 (pf->hw.aq.fw_maj_ver < 4)) {
6846 msleep(75);
6847 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6848 if (ret)
f1c7e72e
SN		 6849 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6850 i40e_stat_str(&pf->hw, ret),
6851 i40e_aq_str(&pf->hw,
6852 pf->hw.aq.asq_last_status));
cafa2ee6 6853 }
41c445ff
JB		 6854 /* reinit the misc interrupt */
6855 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6856 ret = i40e_setup_misc_vector(pf);
6857
e7358f54
ASJ		 6858 /* Add a filter to drop all Flow control frames from any VSI from being
6859 * transmitted. By doing so we stop a malicious VF from sending out
6860 * PAUSE or PFC frames and potentially controlling traffic for other
6861 * PF/VF VSIs.
6862 * The FW can still send Flow control frames if enabled.
6863 */
6864 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6865 pf->main_vsi_seid);
6866
41c445ff
JB		 6867 /* restart the VSIs that were rebuilt and running before the reset */
6868 i40e_pf_unquiesce_all_vsi(pf);
6869
69f64b2b
MW		 6870 if (pf->num_alloc_vfs) {
6871 for (v = 0; v < pf->num_alloc_vfs; v++)
6872 i40e_reset_vf(&pf->vf[v], true);
6873 }
6874
41c445ff 6875 /* tell the firmware that we're starting */
44033fac 6876 i40e_send_version(pf);
41c445ff
JB		 6877
6878end_core_reset:
a316f651
ASJ		 6879 clear_bit(__I40E_RESET_FAILED, &pf->state);
6880clear_recovery:
41c445ff
JB		 6881 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6882}
6883
f650a38b 6884/**
b40c82e6 6885 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6886 * @pf: board private structure
6887 *
6888 * Close up the VFs and other things in prep for a Core Reset,
6889 * then get ready to rebuild the world.
6890 **/
6891static void i40e_handle_reset_warning(struct i40e_pf *pf)
6892{
23cfbe07
SN		 6893 i40e_prep_for_reset(pf);
6894 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6895}
6896
41c445ff
JB		 6897/**
6898 * i40e_handle_mdd_event
b40c82e6 6899 * @pf: pointer to the PF structure
41c445ff
JB		 6900 *
6901 * Called from the MDD irq handler to identify possibly malicious vfs
6902 **/
6903static void i40e_handle_mdd_event(struct i40e_pf *pf)
6904{
6905 struct i40e_hw *hw = &pf->hw;
6906 bool mdd_detected = false;
df430b12 6907 bool pf_mdd_detected = false;
41c445ff
JB		 6908 struct i40e_vf *vf;
6909 u32 reg;
6910 int i;
6911
6912 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6913 return;
6914
6915 /* find what triggered the MDD event */
6916 reg = rd32(hw, I40E_GL_MDET_TX);
6917 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6918 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6919 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6920 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6921 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6922 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6923 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6924 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6925 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6926 pf->hw.func_caps.base_queue;
faf32978 6927 if (netif_msg_tx_err(pf))
b40c82e6 6928 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6929 event, queue, pf_num, vf_num);
41c445ff
JB		 6930 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6931 mdd_detected = true;
6932 }
6933 reg = rd32(hw, I40E_GL_MDET_RX);
6934 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6935 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6936 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6937 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6938 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6939 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6940 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6941 pf->hw.func_caps.base_queue;
faf32978
JB		 6942 if (netif_msg_rx_err(pf))
6943 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6944 event, queue, func);
41c445ff
JB		 6945 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6946 mdd_detected = true;
6947 }
6948
df430b12
NP		 6949 if (mdd_detected) {
6950 reg = rd32(hw, I40E_PF_MDET_TX);
6951 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6952 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6953 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6954 pf_mdd_detected = true;
6955 }
6956 reg = rd32(hw, I40E_PF_MDET_RX);
6957 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6958 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6959 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6960 pf_mdd_detected = true;
6961 }
6962 /* Queue belongs to the PF, initiate a reset */
6963 if (pf_mdd_detected) {
6964 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6965 i40e_service_event_schedule(pf);
6966 }
6967 }
6968
41c445ff
JB		 6969 /* see if one of the VFs needs its hand slapped */
6970 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6971 vf = &(pf->vf[i]);
6972 reg = rd32(hw, I40E_VP_MDET_TX(i));
6973 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6974 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6975 vf->num_mdd_events++;
faf32978
JB		 6976 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6977 i);
41c445ff
JB		 6978 }
6979
6980 reg = rd32(hw, I40E_VP_MDET_RX(i));
6981 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6982 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6983 vf->num_mdd_events++;
faf32978
JB		 6984 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6985 i);
41c445ff
JB		 6986 }
6987
6988 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6989 dev_info(&pf->pdev->dev,
6990 "Too many MDD events on VF %d, disabled\n", i);
6991 dev_info(&pf->pdev->dev,
6992 "Use PF Control I/F to re-enable the VF\n");
6993 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6994 }
6995 }
6996
6997 /* re-enable mdd interrupt cause */
6998 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6999 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7000 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7001 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7002 i40e_flush(hw);
7003}
7004
a1c9a9d9
JK		 7005#ifdef CONFIG_I40E_VXLAN
7006/**
7007 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
7008 * @pf: board private structure
7009 **/
7010static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
7011{
a1c9a9d9
JK		 7012 struct i40e_hw *hw = &pf->hw;
7013 i40e_status ret;
a1c9a9d9
JK		 7014 __be16 port;
7015 int i;
7016
7017 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
7018 return;
7019
7020 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
7021
7022 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 7023 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
7024 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 7025 port = pf->vxlan_ports[i];
c22c06c8
SN		 7026 if (port)
7027 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 7028 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 7029 NULL, NULL);
7030 else
7031 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7032
7033 if (ret) {
c22c06c8 7034 dev_info(&pf->pdev->dev,
f1c7e72e 7035 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7036 port ? "add" : "delete",
f1c7e72e
SN		 7037 ntohs(port), i,
7038 i40e_stat_str(&pf->hw, ret),
7039 i40e_aq_str(&pf->hw,
7040 pf->hw.aq.asq_last_status));
a1c9a9d9 7041 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 7042 }
7043 }
7044 }
7045}
7046
7047#endif
41c445ff
JB		 7048/**
7049 * i40e_service_task - Run the driver's async subtasks
7050 * @work: pointer to work_struct containing our data
7051 **/
7052static void i40e_service_task(struct work_struct *work)
7053{
7054 struct i40e_pf *pf = container_of(work,
7055 struct i40e_pf,
7056 service_task);
7057 unsigned long start_time = jiffies;
7058
e57a2fea
SN		 7059 /* don't bother with service tasks if a reset is in progress */
7060 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7061 i40e_service_event_complete(pf);
7062 return;
7063 }
7064
b03a8c1f 7065 i40e_detect_recover_hung(pf);
41c445ff
JB		 7066 i40e_reset_subtask(pf);
7067 i40e_handle_mdd_event(pf);
7068 i40e_vc_process_vflr_event(pf);
7069 i40e_watchdog_subtask(pf);
7070 i40e_fdir_reinit_subtask(pf);
41c445ff 7071 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 7072#ifdef CONFIG_I40E_VXLAN
7073 i40e_sync_vxlan_filters_subtask(pf);
7074#endif
41c445ff
JB		 7075 i40e_clean_adminq_subtask(pf);
7076
7077 i40e_service_event_complete(pf);
7078
7079 /* If the tasks have taken longer than one timer cycle or there
7080 * is more work to be done, reschedule the service task now
7081 * rather than wait for the timer to tick again.
7082 */
7083 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7084 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7085 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7086 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7087 i40e_service_event_schedule(pf);
7088}
7089
7090/**
7091 * i40e_service_timer - timer callback
7092 * @data: pointer to PF struct
7093 **/
7094static void i40e_service_timer(unsigned long data)
7095{
7096 struct i40e_pf *pf = (struct i40e_pf *)data;
7097
7098 mod_timer(&pf->service_timer,
7099 round_jiffies(jiffies + pf->service_timer_period));
7100 i40e_service_event_schedule(pf);
7101}
7102
7103/**
7104 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7105 * @vsi: the VSI being configured
7106 **/
7107static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7108{
7109 struct i40e_pf *pf = vsi->back;
7110
7111 switch (vsi->type) {
7112 case I40E_VSI_MAIN:
7113 vsi->alloc_queue_pairs = pf->num_lan_qps;
7114 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7115 I40E_REQ_DESCRIPTOR_MULTIPLE);
7116 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7117 vsi->num_q_vectors = pf->num_lan_msix;
7118 else
7119 vsi->num_q_vectors = 1;
7120
7121 break;
7122
7123 case I40E_VSI_FDIR:
7124 vsi->alloc_queue_pairs = 1;
7125 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7126 I40E_REQ_DESCRIPTOR_MULTIPLE);
7127 vsi->num_q_vectors = 1;
7128 break;
7129
7130 case I40E_VSI_VMDQ2:
7131 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7132 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7133 I40E_REQ_DESCRIPTOR_MULTIPLE);
7134 vsi->num_q_vectors = pf->num_vmdq_msix;
7135 break;
7136
7137 case I40E_VSI_SRIOV:
7138 vsi->alloc_queue_pairs = pf->num_vf_qps;
7139 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7140 I40E_REQ_DESCRIPTOR_MULTIPLE);
7141 break;
7142
38e00438
VD		 7143#ifdef I40E_FCOE
7144 case I40E_VSI_FCOE:
7145 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7146 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7147 I40E_REQ_DESCRIPTOR_MULTIPLE);
7148 vsi->num_q_vectors = pf->num_fcoe_msix;
7149 break;
7150
7151#endif /* I40E_FCOE */
41c445ff
JB		 7152 default:
7153 WARN_ON(1);
7154 return -ENODATA;
7155 }
7156
7157 return 0;
7158}
7159
f650a38b
ASJ		 7160/**
7161 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7162 * @type: VSI pointer
bc7d338f 7163 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7164 *
7165 * On error: returns error code (negative)
7166 * On success: returns 0
7167 **/
bc7d338f 7168static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7169{
7170 int size;
7171 int ret = 0;
7172
ac6c5e3d 7173 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7174 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7175 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7176 if (!vsi->tx_rings)
7177 return -ENOMEM;
f650a38b
ASJ		 7178 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7179
bc7d338f
ASJ		 7180 if (alloc_qvectors) {
7181 /* allocate memory for q_vector pointers */
f57e4fbd 7182 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7183 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7184 if (!vsi->q_vectors) {
7185 ret = -ENOMEM;
7186 goto err_vectors;
7187 }
f650a38b
ASJ		 7188 }
7189 return ret;
7190
7191err_vectors:
7192 kfree(vsi->tx_rings);
7193 return ret;
7194}
7195
41c445ff
JB		 7196/**
7197 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7198 * @pf: board private structure
7199 * @type: type of VSI
7200 *
7201 * On error: returns error code (negative)
7202 * On success: returns vsi index in PF (positive)
7203 **/
7204static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7205{
7206 int ret = -ENODEV;
7207 struct i40e_vsi *vsi;
7208 int vsi_idx;
7209 int i;
7210
7211 /* Need to protect the allocation of the VSIs at the PF level */
7212 mutex_lock(&pf->switch_mutex);
7213
7214 /* VSI list may be fragmented if VSI creation/destruction has
7215 * been happening. We can afford to do a quick scan to look
7216 * for any free VSIs in the list.
7217 *
7218 * find next empty vsi slot, looping back around if necessary
7219 */
7220 i = pf->next_vsi;
505682cd 7221 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7222 i++;
505682cd 7223 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7224 i = 0;
7225 while (i < pf->next_vsi && pf->vsi[i])
7226 i++;
7227 }
7228
505682cd 7229 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7230 vsi_idx = i; /* Found one! */
7231 } else {
7232 ret = -ENODEV;
493fb300 7233 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7234 }
7235 pf->next_vsi = ++i;
7236
7237 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7238 if (!vsi) {
7239 ret = -ENOMEM;
493fb300 7240 goto unlock_pf;
41c445ff
JB		 7241 }
7242 vsi->type = type;
7243 vsi->back = pf;
7244 set_bit(__I40E_DOWN, &vsi->state);
7245 vsi->flags = 0;
7246 vsi->idx = vsi_idx;
7247 vsi->rx_itr_setting = pf->rx_itr_default;
7248 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7249 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7250 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7251 pf->rss_table_size : 64;
41c445ff
JB		 7252 vsi->netdev_registered = false;
7253 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7254 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7255 vsi->irqs_ready = false;
41c445ff 7256
9f65e15b
AD		 7257 ret = i40e_set_num_rings_in_vsi(vsi);
7258 if (ret)
7259 goto err_rings;
7260
bc7d338f 7261 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7262 if (ret)
9f65e15b 7263 goto err_rings;
493fb300 7264
41c445ff
JB		 7265 /* Setup default MSIX irq handler for VSI */
7266 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7267
21659035
KP		 7268 /* Initialize VSI lock */
7269 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7270 pf->vsi[vsi_idx] = vsi;
7271 ret = vsi_idx;
493fb300
AD		 7272 goto unlock_pf;
7273
9f65e15b 7274err_rings:
493fb300
AD		 7275 pf->next_vsi = i - 1;
7276 kfree(vsi);
7277unlock_pf:
41c445ff
JB		 7278 mutex_unlock(&pf->switch_mutex);
7279 return ret;
7280}
7281
f650a38b
ASJ		 7282/**
7283 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7284 * @type: VSI pointer
bc7d338f 7285 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7286 *
7287 * On error: returns error code (negative)
7288 * On success: returns 0
7289 **/
bc7d338f 7290static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7291{
7292 /* free the ring and vector containers */
bc7d338f
ASJ		 7293 if (free_qvectors) {
7294 kfree(vsi->q_vectors);
7295 vsi->q_vectors = NULL;
7296 }
f650a38b
ASJ		 7297 kfree(vsi->tx_rings);
7298 vsi->tx_rings = NULL;
7299 vsi->rx_rings = NULL;
7300}
7301
41c445ff
JB		 7302/**
7303 * i40e_vsi_clear - Deallocate the VSI provided
7304 * @vsi: the VSI being un-configured
7305 **/
7306static int i40e_vsi_clear(struct i40e_vsi *vsi)
7307{
7308 struct i40e_pf *pf;
7309
7310 if (!vsi)
7311 return 0;
7312
7313 if (!vsi->back)
7314 goto free_vsi;
7315 pf = vsi->back;
7316
7317 mutex_lock(&pf->switch_mutex);
7318 if (!pf->vsi[vsi->idx]) {
7319 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7320 vsi->idx, vsi->idx, vsi, vsi->type);
7321 goto unlock_vsi;
7322 }
7323
7324 if (pf->vsi[vsi->idx] != vsi) {
7325 dev_err(&pf->pdev->dev,
7326 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7327 pf->vsi[vsi->idx]->idx,
7328 pf->vsi[vsi->idx],
7329 pf->vsi[vsi->idx]->type,
7330 vsi->idx, vsi, vsi->type);
7331 goto unlock_vsi;
7332 }
7333
b40c82e6 7334 /* updates the PF for this cleared vsi */
41c445ff
JB		 7335 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7336 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7337
bc7d338f 7338 i40e_vsi_free_arrays(vsi, true);
493fb300 7339
41c445ff
JB		 7340 pf->vsi[vsi->idx] = NULL;
7341 if (vsi->idx < pf->next_vsi)
7342 pf->next_vsi = vsi->idx;
7343
7344unlock_vsi:
7345 mutex_unlock(&pf->switch_mutex);
7346free_vsi:
7347 kfree(vsi);
7348
7349 return 0;
7350}
7351
9f65e15b
AD		 7352/**
7353 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7354 * @vsi: the VSI being cleaned
7355 **/
be1d5eea 7356static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7357{
7358 int i;
7359
8e9dca53 7360 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7361 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7362 kfree_rcu(vsi->tx_rings[i], rcu);
7363 vsi->tx_rings[i] = NULL;
7364 vsi->rx_rings[i] = NULL;
7365 }
be1d5eea 7366 }
9f65e15b
AD		 7367}
7368
41c445ff
JB		 7369/**
7370 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7371 * @vsi: the VSI being configured
7372 **/
7373static int i40e_alloc_rings(struct i40e_vsi *vsi)
7374{
e7046ee1 7375 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7376 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7377 int i;
7378
41c445ff 7379 /* Set basic values in the rings to be used later during open() */
d7397644 7380 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7381 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7382 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7383 if (!tx_ring)
7384 goto err_out;
41c445ff
JB		 7385
7386 tx_ring->queue_index = i;
7387 tx_ring->reg_idx = vsi->base_queue + i;
7388 tx_ring->ring_active = false;
7389 tx_ring->vsi = vsi;
7390 tx_ring->netdev = vsi->netdev;
7391 tx_ring->dev = &pf->pdev->dev;
7392 tx_ring->count = vsi->num_desc;
7393 tx_ring->size = 0;
7394 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7395 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7396 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7397 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7398 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7399 vsi->tx_rings[i] = tx_ring;
41c445ff 7400
9f65e15b 7401 rx_ring = &tx_ring[1];
41c445ff
JB		 7402 rx_ring->queue_index = i;
7403 rx_ring->reg_idx = vsi->base_queue + i;
7404 rx_ring->ring_active = false;
7405 rx_ring->vsi = vsi;
7406 rx_ring->netdev = vsi->netdev;
7407 rx_ring->dev = &pf->pdev->dev;
7408 rx_ring->count = vsi->num_desc;
7409 rx_ring->size = 0;
7410 rx_ring->dcb_tc = 0;
7411 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7412 set_ring_16byte_desc_enabled(rx_ring);
7413 else
7414 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7415 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7416 }
7417
7418 return 0;
9f65e15b
AD		 7419
7420err_out:
7421 i40e_vsi_clear_rings(vsi);
7422 return -ENOMEM;
41c445ff
JB		 7423}
7424
7425/**
7426 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7427 * @pf: board private structure
7428 * @vectors: the number of MSI-X vectors to request
7429 *
7430 * Returns the number of vectors reserved, or error
7431 **/
7432static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7433{
7b37f376
AG		 7434 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7435 I40E_MIN_MSIX, vectors);
7436 if (vectors < 0) {
41c445ff 7437 dev_info(&pf->pdev->dev,
7b37f376 7438 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7439 vectors = 0;
7440 }
7441
7442 return vectors;
7443}
7444
7445/**
7446 * i40e_init_msix - Setup the MSIX capability
7447 * @pf: board private structure
7448 *
7449 * Work with the OS to set up the MSIX vectors needed.
7450 *
3b444399 7451 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7452 **/
7453static int i40e_init_msix(struct i40e_pf *pf)
7454{
41c445ff 7455 struct i40e_hw *hw = &pf->hw;
1e200e4a 7456 int vectors_left;
41c445ff 7457 int v_budget, i;
3b444399 7458 int v_actual;
41c445ff
JB		 7459
7460 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7461 return -ENODEV;
7462
7463 /* The number of vectors we'll request will be comprised of:
7464 * - Add 1 for "other" cause for Admin Queue events, etc.
7465 * - The number of LAN queue pairs
f8ff1464
ASJ		 7466 * - Queues being used for RSS.
7467 * We don't need as many as max_rss_size vectors.
7468 * use rss_size instead in the calculation since that
7469 * is governed by number of cpus in the system.
7470 * - assumes symmetric Tx/Rx pairing
41c445ff 7471 * - The number of VMDq pairs
38e00438
VD		 7472#ifdef I40E_FCOE
7473 * - The number of FCOE qps.
7474#endif
41c445ff
JB		 7475 * Once we count this up, try the request.
7476 *
7477 * If we can't get what we want, we'll simplify to nearly nothing
7478 * and try again. If that still fails, we punt.
7479 */
1e200e4a
SN		 7480 vectors_left = hw->func_caps.num_msix_vectors;
7481 v_budget = 0;
7482
7483 /* reserve one vector for miscellaneous handler */
7484 if (vectors_left) {
7485 v_budget++;
7486 vectors_left--;
7487 }
7488
7489 /* reserve vectors for the main PF traffic queues */
7490 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7491 vectors_left -= pf->num_lan_msix;
7492 v_budget += pf->num_lan_msix;
7493
7494 /* reserve one vector for sideband flow director */
7495 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7496 if (vectors_left) {
7497 v_budget++;
7498 vectors_left--;
7499 } else {
7500 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7501 }
7502 }
83840e4b 7503
38e00438 7504#ifdef I40E_FCOE
1e200e4a 7505 /* can we reserve enough for FCoE? */
38e00438 7506 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7507 if (!vectors_left)
7508 pf->num_fcoe_msix = 0;
7509 else if (vectors_left >= pf->num_fcoe_qps)
7510 pf->num_fcoe_msix = pf->num_fcoe_qps;
7511 else
7512 pf->num_fcoe_msix = 1;
38e00438 7513 v_budget += pf->num_fcoe_msix;
1e200e4a 7514 vectors_left -= pf->num_fcoe_msix;
38e00438 7515 }
1e200e4a 7516
38e00438 7517#endif
1e200e4a
SN		 7518 /* any vectors left over go for VMDq support */
7519 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7520 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7521 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7522
7523 /* if we're short on vectors for what's desired, we limit
7524 * the queues per vmdq. If this is still more than are
7525 * available, the user will need to change the number of
7526 * queues/vectors used by the PF later with the ethtool
7527 * channels command
7528 */
7529 if (vmdq_vecs < vmdq_vecs_wanted)
7530 pf->num_vmdq_qps = 1;
7531 pf->num_vmdq_msix = pf->num_vmdq_qps;
7532
7533 v_budget += vmdq_vecs;
7534 vectors_left -= vmdq_vecs;
7535 }
41c445ff
JB		 7536
7537 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7538 GFP_KERNEL);
7539 if (!pf->msix_entries)
7540 return -ENOMEM;
7541
7542 for (i = 0; i < v_budget; i++)
7543 pf->msix_entries[i].entry = i;
3b444399 7544 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7545
3b444399 7546 if (v_actual != v_budget) {
a34977ba
ASJ		 7547 /* If we have limited resources, we will start with no vectors
7548 * for the special features and then allocate vectors to some
7549 * of these features based on the policy and at the end disable
7550 * the features that did not get any vectors.
7551 */
38e00438
VD		 7552#ifdef I40E_FCOE
7553 pf->num_fcoe_qps = 0;
7554 pf->num_fcoe_msix = 0;
7555#endif
a34977ba
ASJ		 7556 pf->num_vmdq_msix = 0;
7557 }
7558
3b444399 7559 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7560 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7561 kfree(pf->msix_entries);
7562 pf->msix_entries = NULL;
7563 return -ENODEV;
7564
3b444399 7565 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7566 /* Adjust for minimal MSIX use */
41c445ff
JB		 7567 pf->num_vmdq_vsis = 0;
7568 pf->num_vmdq_qps = 0;
41c445ff
JB		 7569 pf->num_lan_qps = 1;
7570 pf->num_lan_msix = 1;
7571
3b444399
SN		 7572 } else if (v_actual != v_budget) {
7573 int vec;
7574
a34977ba 7575 /* reserve the misc vector */
3b444399 7576 vec = v_actual - 1;
a34977ba 7577
41c445ff
JB		 7578 /* Scale vector usage down */
7579 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7580 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7581 pf->num_vmdq_qps = 1;
7582 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7583
7584 /* partition out the remaining vectors */
7585 switch (vec) {
7586 case 2:
41c445ff
JB		 7587 pf->num_lan_msix = 1;
7588 break;
7589 case 3:
38e00438
VD		 7590#ifdef I40E_FCOE
7591 /* give one vector to FCoE */
7592 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7593 pf->num_lan_msix = 1;
7594 pf->num_fcoe_msix = 1;
7595 }
7596#else
41c445ff 7597 pf->num_lan_msix = 2;
38e00438 7598#endif
41c445ff
JB		 7599 break;
7600 default:
38e00438
VD		 7601#ifdef I40E_FCOE
7602 /* give one vector to FCoE */
7603 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7604 pf->num_fcoe_msix = 1;
7605 vec--;
7606 }
7607#endif
1e200e4a
SN		 7608 /* give the rest to the PF */
7609 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7610 break;
7611 }
7612 }
7613
a34977ba
ASJ		 7614 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7615 (pf->num_vmdq_msix == 0)) {
7616 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7617 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7618 }
38e00438
VD		 7619#ifdef I40E_FCOE
7620
7621 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7622 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7623 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7624 }
7625#endif
3b444399 7626 return v_actual;
41c445ff
JB		 7627}
7628
493fb300 7629/**
90e04070 7630 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7631 * @vsi: the VSI being configured
7632 * @v_idx: index of the vector in the vsi struct
7633 *
7634 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7635 **/
90e04070 7636static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7637{
7638 struct i40e_q_vector *q_vector;
7639
7640 /* allocate q_vector */
7641 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7642 if (!q_vector)
7643 return -ENOMEM;
7644
7645 q_vector->vsi = vsi;
7646 q_vector->v_idx = v_idx;
7647 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7648 if (vsi->netdev)
7649 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7650 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7651
cd0b6fa6
AD		 7652 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7653 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7654
493fb300
AD		 7655 /* tie q_vector and vsi together */
7656 vsi->q_vectors[v_idx] = q_vector;
7657
7658 return 0;
7659}
7660
41c445ff 7661/**
90e04070 7662 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7663 * @vsi: the VSI being configured
7664 *
7665 * We allocate one q_vector per queue interrupt. If allocation fails we
7666 * return -ENOMEM.
7667 **/
90e04070 7668static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7669{
7670 struct i40e_pf *pf = vsi->back;
7671 int v_idx, num_q_vectors;
493fb300 7672 int err;
41c445ff
JB		 7673
7674 /* if not MSIX, give the one vector only to the LAN VSI */
7675 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7676 num_q_vectors = vsi->num_q_vectors;
7677 else if (vsi == pf->vsi[pf->lan_vsi])
7678 num_q_vectors = 1;
7679 else
7680 return -EINVAL;
7681
41c445ff 7682 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7683 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7684 if (err)
7685 goto err_out;
41c445ff
JB		 7686 }
7687
7688 return 0;
493fb300
AD		 7689
7690err_out:
7691 while (v_idx--)
7692 i40e_free_q_vector(vsi, v_idx);
7693
7694 return err;
41c445ff
JB		 7695}
7696
7697/**
7698 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7699 * @pf: board private structure to initialize
7700 **/
c1147280 7701static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7702{
3b444399
SN		 7703 int vectors = 0;
7704 ssize_t size;
41c445ff
JB		 7705
7706 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7707 vectors = i40e_init_msix(pf);
7708 if (vectors < 0) {
60ea5f83 7709 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7710#ifdef I40E_FCOE
7711 I40E_FLAG_FCOE_ENABLED |
7712#endif
60ea5f83 7713 I40E_FLAG_RSS_ENABLED |
4d9b6043 7714 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7715 I40E_FLAG_SRIOV_ENABLED |
7716 I40E_FLAG_FD_SB_ENABLED |
7717 I40E_FLAG_FD_ATR_ENABLED |
7718 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7719
7720 /* rework the queue expectations without MSIX */
7721 i40e_determine_queue_usage(pf);
7722 }
7723 }
7724
7725 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7726 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7727 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7728 vectors = pci_enable_msi(pf->pdev);
7729 if (vectors < 0) {
7730 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7731 vectors);
41c445ff
JB		 7732 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7733 }
3b444399 7734 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7735 }
7736
958a3e3b 7737 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7738 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7739
3b444399
SN		 7740 /* set up vector assignment tracking */
7741 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7742 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7743 if (!pf->irq_pile) {
7744 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7745 return -ENOMEM;
7746 }
3b444399
SN		 7747 pf->irq_pile->num_entries = vectors;
7748 pf->irq_pile->search_hint = 0;
7749
c1147280 7750 /* track first vector for misc interrupts, ignore return */
3b444399 7751 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7752
7753 return 0;
41c445ff
JB		 7754}
7755
7756/**
7757 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7758 * @pf: board private structure
7759 *
7760 * This sets up the handler for MSIX 0, which is used to manage the
7761 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7762 * when in MSI or Legacy interrupt mode.
7763 **/
7764static int i40e_setup_misc_vector(struct i40e_pf *pf)
7765{
7766 struct i40e_hw *hw = &pf->hw;
7767 int err = 0;
7768
7769 /* Only request the irq if this is the first time through, and
7770 * not when we're rebuilding after a Reset
7771 */
7772 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7773 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7774 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7775 if (err) {
7776 dev_info(&pf->pdev->dev,
77fa28be 7777 "request_irq for %s failed: %d\n",
b294ac70 7778 pf->int_name, err);
41c445ff
JB		 7779 return -EFAULT;
7780 }
7781 }
7782
ab437b5a 7783 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7784
7785 /* associate no queues to the misc vector */
7786 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7787 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7788
7789 i40e_flush(hw);
7790
7791 i40e_irq_dynamic_enable_icr0(pf);
7792
7793 return err;
7794}
7795
7796/**
e25d00b8
ASJ		 7797 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7798 * @vsi: vsi structure
7799 * @seed: RSS hash seed
7800 **/
7801static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7802{
7803 struct i40e_aqc_get_set_rss_key_data rss_key;
7804 struct i40e_pf *pf = vsi->back;
7805 struct i40e_hw *hw = &pf->hw;
7806 bool pf_lut = false;
7807 u8 *rss_lut;
7808 int ret, i;
7809
7810 memset(&rss_key, 0, sizeof(rss_key));
7811 memcpy(&rss_key, seed, sizeof(rss_key));
7812
7813 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7814 if (!rss_lut)
7815 return -ENOMEM;
7816
7817 /* Populate the LUT with max no. of queues in round robin fashion */
7818 for (i = 0; i < vsi->rss_table_size; i++)
7819 rss_lut[i] = i % vsi->rss_size;
7820
7821 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7822 if (ret) {
7823 dev_info(&pf->pdev->dev,
7824 "Cannot set RSS key, err %s aq_err %s\n",
7825 i40e_stat_str(&pf->hw, ret),
7826 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7827 goto config_rss_aq_out;
e25d00b8
ASJ		 7828 }
7829
7830 if (vsi->type == I40E_VSI_MAIN)
7831 pf_lut = true;
7832
7833 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7834 vsi->rss_table_size);
7835 if (ret)
7836 dev_info(&pf->pdev->dev,
7837 "Cannot set RSS lut, err %s aq_err %s\n",
7838 i40e_stat_str(&pf->hw, ret),
7839 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7840
126b63d9
AS		 7841config_rss_aq_out:
7842 kfree(rss_lut);
e25d00b8
ASJ		 7843 return ret;
7844}
7845
7846/**
7847 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7848 * @vsi: VSI structure
7849 **/
7850static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7851{
7852 u8 seed[I40E_HKEY_ARRAY_SIZE];
7853 struct i40e_pf *pf = vsi->back;
7854
7855 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7856 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7857
7858 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7859 return i40e_config_rss_aq(vsi, seed);
7860
7861 return 0;
7862}
7863
7864/**
7865 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7866 * @pf: board private structure
e25d00b8 7867 * @seed: RSS hash seed
41c445ff 7868 **/
e25d00b8 7869static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7870{
66ddcffb 7871 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7872 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7873 u32 *seed_dw = (u32 *)seed;
7874 u32 current_queue = 0;
4617e8c0
ASJ		 7875 u32 lut = 0;
7876 int i, j;
41c445ff 7877
e25d00b8 7878 /* Fill out hash function seed */
41c445ff 7879 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7880 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7881
7882 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7883 lut = 0;
7884 for (j = 0; j < 4; j++) {
7885 if (current_queue == vsi->rss_size)
7886 current_queue = 0;
7887 lut |= ((current_queue) << (8 * j));
7888 current_queue++;
7889 }
7890 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7891 }
7892 i40e_flush(hw);
7893
7894 return 0;
7895}
7896
7897/**
7898 * i40e_config_rss - Prepare for RSS if used
7899 * @pf: board private structure
7900 **/
7901static int i40e_config_rss(struct i40e_pf *pf)
7902{
7903 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7904 u8 seed[I40E_HKEY_ARRAY_SIZE];
7905 struct i40e_hw *hw = &pf->hw;
7906 u32 reg_val;
7907 u64 hena;
7908
7909 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7910
7911 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7912 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7913 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7914 hena |= i40e_pf_get_default_rss_hena(pf);
7915
41c445ff
JB		 7916 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7917 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7918
66ddcffb
ASJ		 7919 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7920
e25d00b8 7921 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7922 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7923 reg_val = (pf->rss_table_size == 512) ?
7924 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7925 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7926 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7927
e25d00b8
ASJ		 7928 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7929 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7930 else
7931 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7932}
7933
f8ff1464
ASJ		 7934/**
7935 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7936 * @pf: board private structure
7937 * @queue_count: the requested queue count for rss.
7938 *
7939 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7940 * count which may be different from the requested queue count.
7941 **/
7942int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7943{
9a3bd2f1
ASJ		 7944 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7945 int new_rss_size;
7946
f8ff1464
ASJ		 7947 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7948 return 0;
7949
9a3bd2f1 7950 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7951
9a3bd2f1
ASJ		 7952 if (queue_count != vsi->num_queue_pairs) {
7953 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7954 i40e_prep_for_reset(pf);
7955
9a3bd2f1 7956 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7957
7958 i40e_reset_and_rebuild(pf, true);
7959 i40e_config_rss(pf);
7960 }
7961 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7962 return pf->rss_size;
7963}
7964
f4492db1
GR		 7965/**
7966 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7967 * @pf: board private structure
7968 **/
7969i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7970{
7971 i40e_status status;
7972 bool min_valid, max_valid;
7973 u32 max_bw, min_bw;
7974
7975 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7976 &min_valid, &max_valid);
7977
7978 if (!status) {
7979 if (min_valid)
7980 pf->npar_min_bw = min_bw;
7981 if (max_valid)
7982 pf->npar_max_bw = max_bw;
7983 }
7984
7985 return status;
7986}
7987
7988/**
7989 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7990 * @pf: board private structure
7991 **/
7992i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7993{
7994 struct i40e_aqc_configure_partition_bw_data bw_data;
7995 i40e_status status;
7996
b40c82e6 7997 /* Set the valid bit for this PF */
41a1d04b 7998 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7999 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8000 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8001
8002 /* Set the new bandwidths */
8003 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8004
8005 return status;
8006}
8007
8008/**
8009 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8010 * @pf: board private structure
8011 **/
8012i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8013{
8014 /* Commit temporary BW setting to permanent NVM image */
8015 enum i40e_admin_queue_err last_aq_status;
8016 i40e_status ret;
8017 u16 nvm_word;
8018
8019 if (pf->hw.partition_id != 1) {
8020 dev_info(&pf->pdev->dev,
8021 "Commit BW only works on partition 1! This is partition %d",
8022 pf->hw.partition_id);
8023 ret = I40E_NOT_SUPPORTED;
8024 goto bw_commit_out;
8025 }
8026
8027 /* Acquire NVM for read access */
8028 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8029 last_aq_status = pf->hw.aq.asq_last_status;
8030 if (ret) {
8031 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8032 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8033 i40e_stat_str(&pf->hw, ret),
8034 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8035 goto bw_commit_out;
8036 }
8037
8038 /* Read word 0x10 of NVM - SW compatibility word 1 */
8039 ret = i40e_aq_read_nvm(&pf->hw,
8040 I40E_SR_NVM_CONTROL_WORD,
8041 0x10, sizeof(nvm_word), &nvm_word,
8042 false, NULL);
8043 /* Save off last admin queue command status before releasing
8044 * the NVM
8045 */
8046 last_aq_status = pf->hw.aq.asq_last_status;
8047 i40e_release_nvm(&pf->hw);
8048 if (ret) {
f1c7e72e
SN		 8049 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8050 i40e_stat_str(&pf->hw, ret),
8051 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8052 goto bw_commit_out;
8053 }
8054
8055 /* Wait a bit for NVM release to complete */
8056 msleep(50);
8057
8058 /* Acquire NVM for write access */
8059 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8060 last_aq_status = pf->hw.aq.asq_last_status;
8061 if (ret) {
8062 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8063 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8064 i40e_stat_str(&pf->hw, ret),
8065 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8066 goto bw_commit_out;
8067 }
8068 /* Write it back out unchanged to initiate update NVM,
8069 * which will force a write of the shadow (alt) RAM to
8070 * the NVM - thus storing the bandwidth values permanently.
8071 */
8072 ret = i40e_aq_update_nvm(&pf->hw,
8073 I40E_SR_NVM_CONTROL_WORD,
8074 0x10, sizeof(nvm_word),
8075 &nvm_word, true, NULL);
8076 /* Save off last admin queue command status before releasing
8077 * the NVM
8078 */
8079 last_aq_status = pf->hw.aq.asq_last_status;
8080 i40e_release_nvm(&pf->hw);
8081 if (ret)
8082 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8083 "BW settings NOT SAVED, err %s aq_err %s\n",
8084 i40e_stat_str(&pf->hw, ret),
8085 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8086bw_commit_out:
8087
8088 return ret;
8089}
8090
41c445ff
JB		 8091/**
8092 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8093 * @pf: board private structure to initialize
8094 *
8095 * i40e_sw_init initializes the Adapter private data structure.
8096 * Fields are initialized based on PCI device information and
8097 * OS network device settings (MTU size).
8098 **/
8099static int i40e_sw_init(struct i40e_pf *pf)
8100{
8101 int err = 0;
8102 int size;
8103
8104 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8105 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8106 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8107 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8108 if (I40E_DEBUG_USER & debug)
8109 pf->hw.debug_mask = debug;
8110 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8111 I40E_DEFAULT_MSG_ENABLE);
8112 }
8113
8114 /* Set default capability flags */
8115 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8116 I40E_FLAG_MSI_ENABLED |
9ac77266 8117 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8118 I40E_FLAG_MSIX_ENABLED;
8119
8120 if (iommu_present(&pci_bus_type))
8121 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8122 else
8123 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8124
ca99eb99
MW		 8125 /* Set default ITR */
8126 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8127 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8128
7134f9ce
JB		 8129 /* Depending on PF configurations, it is possible that the RSS
8130 * maximum might end up larger than the available queues
8131 */
41a1d04b 8132 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 8133 pf->rss_size = 1;
5db4cb59 8134 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8135 pf->rss_size_max = min_t(int, pf->rss_size_max,
8136 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8137 if (pf->hw.func_caps.rss) {
8138 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 8139 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 8140 }
8141
2050bc65 8142 /* MFP mode enabled */
c78b953e 8143 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8144 pf->flags |= I40E_FLAG_MFP_ENABLED;
8145 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8146 if (i40e_get_npar_bw_setting(pf))
8147 dev_warn(&pf->pdev->dev,
8148 "Could not get NPAR bw settings\n");
8149 else
8150 dev_info(&pf->pdev->dev,
8151 "Min BW = %8.8x, Max BW = %8.8x\n",
8152 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8153 }
8154
cbf61325
ASJ		 8155 /* FW/NVM is not yet fixed in this regard */
8156 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8157 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8158 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8159 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8160 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8161 pf->hw.num_partitions > 1)
cbf61325 8162 dev_info(&pf->pdev->dev,
0b67584f 8163 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8164 else
8165 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8166 pf->fdir_pf_filter_count =
8167 pf->hw.func_caps.fd_filters_guaranteed;
8168 pf->hw.fdir_shared_filter_count =
8169 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8170 }
8171
8172 if (pf->hw.func_caps.vmdq) {
41c445ff 8173 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8174 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8175 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8176 }
8177
38e00438 8178#ifdef I40E_FCOE
21364bcf 8179 i40e_init_pf_fcoe(pf);
38e00438
VD		 8180
8181#endif /* I40E_FCOE */
41c445ff 8182#ifdef CONFIG_PCI_IOV
ba252f13 8183 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8184 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8185 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8186 pf->num_req_vfs = min_t(int,
8187 pf->hw.func_caps.num_vfs,
8188 I40E_MAX_VF_COUNT);
8189 }
8190#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8191 if (pf->hw.mac.type == I40E_MAC_X722) {
8192 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8193 I40E_FLAG_128_QP_RSS_CAPABLE |
8194 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8195 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8196 I40E_FLAG_WB_ON_ITR_CAPABLE |
8197 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
8198 }
41c445ff
JB		 8199 pf->eeprom_version = 0xDEAD;
8200 pf->lan_veb = I40E_NO_VEB;
8201 pf->lan_vsi = I40E_NO_VSI;
8202
d1a8d275
ASJ		 8203 /* By default FW has this off for performance reasons */
8204 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8205
41c445ff
JB		 8206 /* set up queue assignment tracking */
8207 size = sizeof(struct i40e_lump_tracking)
8208 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8209 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8210 if (!pf->qp_pile) {
8211 err = -ENOMEM;
8212 goto sw_init_done;
8213 }
8214 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8215 pf->qp_pile->search_hint = 0;
8216
327fe04b
ASJ		 8217 pf->tx_timeout_recovery_level = 1;
8218
41c445ff
JB		 8219 mutex_init(&pf->switch_mutex);
8220
c668a12c
GR		 8221 /* If NPAR is enabled nudge the Tx scheduler */
8222 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8223 i40e_set_npar_bw_setting(pf);
8224
41c445ff
JB		 8225sw_init_done:
8226 return err;
8227}
8228
7c3c288b
ASJ		 8229/**
8230 * i40e_set_ntuple - set the ntuple feature flag and take action
8231 * @pf: board private structure to initialize
8232 * @features: the feature set that the stack is suggesting
8233 *
8234 * returns a bool to indicate if reset needs to happen
8235 **/
8236bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8237{
8238 bool need_reset = false;
8239
8240 /* Check if Flow Director n-tuple support was enabled or disabled. If
8241 * the state changed, we need to reset.
8242 */
8243 if (features & NETIF_F_NTUPLE) {
8244 /* Enable filters and mark for reset */
8245 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8246 need_reset = true;
8247 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8248 } else {
8249 /* turn off filters, mark for reset and clear SW filter list */
8250 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8251 need_reset = true;
8252 i40e_fdir_filter_exit(pf);
8253 }
8254 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8255 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8256 /* reset fd counters */
8257 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8258 pf->fdir_pf_active_filters = 0;
8259 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8260 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8261 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8262 /* if ATR was auto disabled it can be re-enabled. */
8263 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8264 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8265 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8266 }
8267 return need_reset;
8268}
8269
41c445ff
JB		 8270/**
8271 * i40e_set_features - set the netdev feature flags
8272 * @netdev: ptr to the netdev being adjusted
8273 * @features: the feature set that the stack is suggesting
8274 **/
8275static int i40e_set_features(struct net_device *netdev,
8276 netdev_features_t features)
8277{
8278 struct i40e_netdev_priv *np = netdev_priv(netdev);
8279 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8280 struct i40e_pf *pf = vsi->back;
8281 bool need_reset;
41c445ff
JB		 8282
8283 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8284 i40e_vlan_stripping_enable(vsi);
8285 else
8286 i40e_vlan_stripping_disable(vsi);
8287
7c3c288b
ASJ		 8288 need_reset = i40e_set_ntuple(pf, features);
8289
8290 if (need_reset)
41a1d04b 8291 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8292
41c445ff
JB		 8293 return 0;
8294}
8295
a1c9a9d9
JK		 8296#ifdef CONFIG_I40E_VXLAN
8297/**
8298 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8299 * @pf: board private structure
8300 * @port: The UDP port to look up
8301 *
8302 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8303 **/
8304static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8305{
8306 u8 i;
8307
8308 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8309 if (pf->vxlan_ports[i] == port)
8310 return i;
8311 }
8312
8313 return i;
8314}
8315
8316/**
8317 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8318 * @netdev: This physical port's netdev
8319 * @sa_family: Socket Family that VXLAN is notifying us about
8320 * @port: New UDP port number that VXLAN started listening to
8321 **/
8322static void i40e_add_vxlan_port(struct net_device *netdev,
8323 sa_family_t sa_family, __be16 port)
8324{
8325 struct i40e_netdev_priv *np = netdev_priv(netdev);
8326 struct i40e_vsi *vsi = np->vsi;
8327 struct i40e_pf *pf = vsi->back;
8328 u8 next_idx;
8329 u8 idx;
8330
8331 if (sa_family == AF_INET6)
8332 return;
8333
8334 idx = i40e_get_vxlan_port_idx(pf, port);
8335
8336 /* Check if port already exists */
8337 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8338 netdev_info(netdev, "vxlan port %d already offloaded\n",
8339 ntohs(port));
a1c9a9d9
JK		 8340 return;
8341 }
8342
8343 /* Now check if there is space to add the new port */
8344 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8345
8346 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8347 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8348 ntohs(port));
8349 return;
8350 }
8351
8352 /* New port: add it and mark its index in the bitmap */
8353 pf->vxlan_ports[next_idx] = port;
41a1d04b 8354 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8355 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8356}
8357
8358/**
8359 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8360 * @netdev: This physical port's netdev
8361 * @sa_family: Socket Family that VXLAN is notifying us about
8362 * @port: UDP port number that VXLAN stopped listening to
8363 **/
8364static void i40e_del_vxlan_port(struct net_device *netdev,
8365 sa_family_t sa_family, __be16 port)
8366{
8367 struct i40e_netdev_priv *np = netdev_priv(netdev);
8368 struct i40e_vsi *vsi = np->vsi;
8369 struct i40e_pf *pf = vsi->back;
8370 u8 idx;
8371
8372 if (sa_family == AF_INET6)
8373 return;
8374
8375 idx = i40e_get_vxlan_port_idx(pf, port);
8376
8377 /* Check if port already exists */
8378 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8379 /* if port exists, set it to 0 (mark for deletion)
8380 * and make it pending
8381 */
8382 pf->vxlan_ports[idx] = 0;
41a1d04b 8383 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8384 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8385 } else {
c22c06c8 8386 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8387 ntohs(port));
8388 }
8389}
8390
8391#endif
1f224ad2 8392static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8393 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8394{
8395 struct i40e_netdev_priv *np = netdev_priv(netdev);
8396 struct i40e_pf *pf = np->vsi->back;
8397 struct i40e_hw *hw = &pf->hw;
8398
8399 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8400 return -EOPNOTSUPP;
8401
8402 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8403 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8404
8405 return 0;
8406}
8407
2f90ade6
JB		 8408/**
8409 * i40e_ndo_fdb_add - add an entry to the hardware database
8410 * @ndm: the input from the stack
8411 * @tb: pointer to array of nladdr (unused)
8412 * @dev: the net device pointer
8413 * @addr: the MAC address entry being added
8414 * @flags: instructions from stack about fdb operation
8415 */
4ba0dea5
GR		 8416static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8417 struct net_device *dev,
f6f6424b 8418 const unsigned char *addr, u16 vid,
4ba0dea5 8419 u16 flags)
4ba0dea5
GR		 8420{
8421 struct i40e_netdev_priv *np = netdev_priv(dev);
8422 struct i40e_pf *pf = np->vsi->back;
8423 int err = 0;
8424
8425 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8426 return -EOPNOTSUPP;
8427
65891fea
OG		 8428 if (vid) {
8429 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8430 return -EINVAL;
8431 }
8432
4ba0dea5
GR		 8433 /* Hardware does not support aging addresses so if a
8434 * ndm_state is given only allow permanent addresses
8435 */
8436 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8437 netdev_info(dev, "FDB only supports static addresses\n");
8438 return -EINVAL;
8439 }
8440
8441 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8442 err = dev_uc_add_excl(dev, addr);
8443 else if (is_multicast_ether_addr(addr))
8444 err = dev_mc_add_excl(dev, addr);
8445 else
8446 err = -EINVAL;
8447
8448 /* Only return duplicate errors if NLM_F_EXCL is set */
8449 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8450 err = 0;
8451
8452 return err;
8453}
8454
51616018
NP		 8455/**
8456 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8457 * @dev: the netdev being configured
8458 * @nlh: RTNL message
8459 *
8460 * Inserts a new hardware bridge if not already created and
8461 * enables the bridging mode requested (VEB or VEPA). If the
8462 * hardware bridge has already been inserted and the request
8463 * is to change the mode then that requires a PF reset to
8464 * allow rebuild of the components with required hardware
8465 * bridge mode enabled.
8466 **/
8467static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8468 struct nlmsghdr *nlh,
8469 u16 flags)
51616018
NP		 8470{
8471 struct i40e_netdev_priv *np = netdev_priv(dev);
8472 struct i40e_vsi *vsi = np->vsi;
8473 struct i40e_pf *pf = vsi->back;
8474 struct i40e_veb *veb = NULL;
8475 struct nlattr *attr, *br_spec;
8476 int i, rem;
8477
8478 /* Only for PF VSI for now */
8479 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8480 return -EOPNOTSUPP;
8481
8482 /* Find the HW bridge for PF VSI */
8483 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8484 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8485 veb = pf->veb[i];
8486 }
8487
8488 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8489
8490 nla_for_each_nested(attr, br_spec, rem) {
8491 __u16 mode;
8492
8493 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8494 continue;
8495
8496 mode = nla_get_u16(attr);
8497 if ((mode != BRIDGE_MODE_VEPA) &&
8498 (mode != BRIDGE_MODE_VEB))
8499 return -EINVAL;
8500
8501 /* Insert a new HW bridge */
8502 if (!veb) {
8503 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8504 vsi->tc_config.enabled_tc);
8505 if (veb) {
8506 veb->bridge_mode = mode;
8507 i40e_config_bridge_mode(veb);
8508 } else {
8509 /* No Bridge HW offload available */
8510 return -ENOENT;
8511 }
8512 break;
8513 } else if (mode != veb->bridge_mode) {
8514 /* Existing HW bridge but different mode needs reset */
8515 veb->bridge_mode = mode;
fc60861e
ASJ		 8516 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8517 if (mode == BRIDGE_MODE_VEB)
8518 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8519 else
8520 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8521 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8522 break;
8523 }
8524 }
8525
8526 return 0;
8527}
8528
8529/**
8530 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8531 * @skb: skb buff
8532 * @pid: process id
8533 * @seq: RTNL message seq #
8534 * @dev: the netdev being configured
8535 * @filter_mask: unused
d4b2f9fe 8536 * @nlflags: netlink flags passed in
51616018
NP		 8537 *
8538 * Return the mode in which the hardware bridge is operating in
8539 * i.e VEB or VEPA.
8540 **/
51616018
NP		 8541static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8542 struct net_device *dev,
9f4ffc44
CW		 8543 u32 __always_unused filter_mask,
8544 int nlflags)
51616018
NP		 8545{
8546 struct i40e_netdev_priv *np = netdev_priv(dev);
8547 struct i40e_vsi *vsi = np->vsi;
8548 struct i40e_pf *pf = vsi->back;
8549 struct i40e_veb *veb = NULL;
8550 int i;
8551
8552 /* Only for PF VSI for now */
8553 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8554 return -EOPNOTSUPP;
8555
8556 /* Find the HW bridge for the PF VSI */
8557 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8558 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8559 veb = pf->veb[i];
8560 }
8561
8562 if (!veb)
8563 return 0;
8564
46c264da 8565 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8566 nlflags, 0, 0, filter_mask, NULL);
51616018 8567}
51616018 8568
f44a75e2
JS		 8569#define I40E_MAX_TUNNEL_HDR_LEN 80
8570/**
8571 * i40e_features_check - Validate encapsulated packet conforms to limits
8572 * @skb: skb buff
2bc11c63 8573 * @dev: This physical port's netdev
f44a75e2
JS		 8574 * @features: Offload features that the stack believes apply
8575 **/
8576static netdev_features_t i40e_features_check(struct sk_buff *skb,
8577 struct net_device *dev,
8578 netdev_features_t features)
8579{
8580 if (skb->encapsulation &&
8581 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8582 I40E_MAX_TUNNEL_HDR_LEN))
8583 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8584
8585 return features;
8586}
8587
37a2973a 8588static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8589 .ndo_open = i40e_open,
8590 .ndo_stop = i40e_close,
8591 .ndo_start_xmit = i40e_lan_xmit_frame,
8592 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8593 .ndo_set_rx_mode = i40e_set_rx_mode,
8594 .ndo_validate_addr = eth_validate_addr,
8595 .ndo_set_mac_address = i40e_set_mac,
8596 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8597 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8598 .ndo_tx_timeout = i40e_tx_timeout,
8599 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8600 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8601#ifdef CONFIG_NET_POLL_CONTROLLER
8602 .ndo_poll_controller = i40e_netpoll,
8603#endif
8604 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8605#ifdef I40E_FCOE
8606 .ndo_fcoe_enable = i40e_fcoe_enable,
8607 .ndo_fcoe_disable = i40e_fcoe_disable,
8608#endif
41c445ff
JB		 8609 .ndo_set_features = i40e_set_features,
8610 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8611 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8612 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8613 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8614 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8615 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8616#ifdef CONFIG_I40E_VXLAN
8617 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8618 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8619#endif
1f224ad2 8620 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8621 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8622 .ndo_features_check = i40e_features_check,
51616018
NP		 8623 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8624 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8625};
8626
8627/**
8628 * i40e_config_netdev - Setup the netdev flags
8629 * @vsi: the VSI being configured
8630 *
8631 * Returns 0 on success, negative value on failure
8632 **/
8633static int i40e_config_netdev(struct i40e_vsi *vsi)
8634{
1a10370a 8635 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8636 struct i40e_pf *pf = vsi->back;
8637 struct i40e_hw *hw = &pf->hw;
8638 struct i40e_netdev_priv *np;
8639 struct net_device *netdev;
8640 u8 mac_addr[ETH_ALEN];
8641 int etherdev_size;
8642
8643 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8644 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8645 if (!netdev)
8646 return -ENOMEM;
8647
8648 vsi->netdev = netdev;
8649 np = netdev_priv(netdev);
8650 np->vsi = vsi;
8651
d70e941b 8652 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8653 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8654 NETIF_F_GSO_GRE |
d70e941b 8655 NETIF_F_TSO;
41c445ff
JB		 8656
8657 netdev->features = NETIF_F_SG |
8658 NETIF_F_IP_CSUM |
8659 NETIF_F_SCTP_CSUM |
8660 NETIF_F_HIGHDMA |
8661 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8662 NETIF_F_GSO_GRE |
41c445ff
JB		 8663 NETIF_F_HW_VLAN_CTAG_TX |
8664 NETIF_F_HW_VLAN_CTAG_RX |
8665 NETIF_F_HW_VLAN_CTAG_FILTER |
8666 NETIF_F_IPV6_CSUM |
8667 NETIF_F_TSO |
059dab69 8668 NETIF_F_TSO_ECN |
41c445ff
JB		 8669 NETIF_F_TSO6 |
8670 NETIF_F_RXCSUM |
8671 NETIF_F_RXHASH |
8672 0;
8673
2e86a0b6
ASJ		 8674 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8675 netdev->features |= NETIF_F_NTUPLE;
8676
41c445ff
JB		 8677 /* copy netdev features into list of user selectable features */
8678 netdev->hw_features |= netdev->features;
8679
8680 if (vsi->type == I40E_VSI_MAIN) {
8681 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8682 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8683 /* The following steps are necessary to prevent reception
8684 * of tagged packets - some older NVM configurations load a
8685 * default a MAC-VLAN filter that accepts any tagged packet
8686 * which must be replaced by a normal filter.
8c27d42e 8687 */
21659035
KP		 8688 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
8689 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 8690 i40e_add_filter(vsi, mac_addr,
8691 I40E_VLAN_ANY, false, true);
21659035
KP		 8692 spin_unlock_bh(&vsi->mac_filter_list_lock);
8693 }
41c445ff
JB		 8694 } else {
8695 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8696 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8697 pf->vsi[pf->lan_vsi]->netdev->name);
8698 random_ether_addr(mac_addr);
21659035
KP		 8699
8700 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 8701 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 8702 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8703 }
21659035
KP		 8704
8705 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 8706 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 8707 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8708
9a173901
GR		 8709 ether_addr_copy(netdev->dev_addr, mac_addr);
8710 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8711 /* vlan gets same features (except vlan offload)
8712 * after any tweaks for specific VSI types
8713 */
8714 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8715 NETIF_F_HW_VLAN_CTAG_RX |
8716 NETIF_F_HW_VLAN_CTAG_FILTER);
8717 netdev->priv_flags |= IFF_UNICAST_FLT;
8718 netdev->priv_flags |= IFF_SUPP_NOFCS;
8719 /* Setup netdev TC information */
8720 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8721
8722 netdev->netdev_ops = &i40e_netdev_ops;
8723 netdev->watchdog_timeo = 5 * HZ;
8724 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8725#ifdef I40E_FCOE
8726 i40e_fcoe_config_netdev(netdev, vsi);
8727#endif
41c445ff
JB		 8728
8729 return 0;
8730}
8731
8732/**
8733 * i40e_vsi_delete - Delete a VSI from the switch
8734 * @vsi: the VSI being removed
8735 *
8736 * Returns 0 on success, negative value on failure
8737 **/
8738static void i40e_vsi_delete(struct i40e_vsi *vsi)
8739{
8740 /* remove default VSI is not allowed */
8741 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8742 return;
8743
41c445ff 8744 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8745}
8746
51616018
NP		 8747/**
8748 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8749 * @vsi: the VSI being queried
8750 *
8751 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8752 **/
8753int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8754{
8755 struct i40e_veb *veb;
8756 struct i40e_pf *pf = vsi->back;
8757
8758 /* Uplink is not a bridge so default to VEB */
8759 if (vsi->veb_idx == I40E_NO_VEB)
8760 return 1;
8761
8762 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 8763 if (!veb) {
8764 dev_info(&pf->pdev->dev,
8765 "There is no veb associated with the bridge\n");
8766 return -ENOENT;
8767 }
8768
51616018 8769 /* Uplink is a bridge in VEPA mode */
09603eaa 8770 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 8771 return 0;
09603eaa
AA		 8772 } else {
8773 /* Uplink is a bridge in VEB mode */
8774 return 1;
8775 }
51616018 8776
09603eaa
AA		 8777 /* VEPA is now default bridge, so return 0 */
8778 return 0;
51616018
NP		 8779}
8780
41c445ff
JB		 8781/**
8782 * i40e_add_vsi - Add a VSI to the switch
8783 * @vsi: the VSI being configured
8784 *
8785 * This initializes a VSI context depending on the VSI type to be added and
8786 * passes it down to the add_vsi aq command.
8787 **/
8788static int i40e_add_vsi(struct i40e_vsi *vsi)
8789{
8790 int ret = -ENODEV;
21659035
KP		 8791 u8 laa_macaddr[ETH_ALEN];
8792 bool found_laa_mac_filter = false;
41c445ff
JB		 8793 struct i40e_pf *pf = vsi->back;
8794 struct i40e_hw *hw = &pf->hw;
8795 struct i40e_vsi_context ctxt;
21659035
KP		 8796 struct i40e_mac_filter *f, *ftmp;
8797
41c445ff
JB		 8798 u8 enabled_tc = 0x1; /* TC0 enabled */
8799 int f_count = 0;
8800
8801 memset(&ctxt, 0, sizeof(ctxt));
8802 switch (vsi->type) {
8803 case I40E_VSI_MAIN:
8804 /* The PF's main VSI is already setup as part of the
8805 * device initialization, so we'll not bother with
8806 * the add_vsi call, but we will retrieve the current
8807 * VSI context.
8808 */
8809 ctxt.seid = pf->main_vsi_seid;
8810 ctxt.pf_num = pf->hw.pf_id;
8811 ctxt.vf_num = 0;
8812 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8813 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8814 if (ret) {
8815 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8816 "couldn't get PF vsi config, err %s aq_err %s\n",
8817 i40e_stat_str(&pf->hw, ret),
8818 i40e_aq_str(&pf->hw,
8819 pf->hw.aq.asq_last_status));
41c445ff
JB		 8820 return -ENOENT;
8821 }
1a2f6248 8822 vsi->info = ctxt.info;
41c445ff
JB		 8823 vsi->info.valid_sections = 0;
8824
8825 vsi->seid = ctxt.seid;
8826 vsi->id = ctxt.vsi_number;
8827
8828 enabled_tc = i40e_pf_get_tc_map(pf);
8829
8830 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8831 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8832 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8833 memset(&ctxt, 0, sizeof(ctxt));
8834 ctxt.seid = pf->main_vsi_seid;
8835 ctxt.pf_num = pf->hw.pf_id;
8836 ctxt.vf_num = 0;
8837 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8838 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8839 if (ret) {
8840 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8841 "update vsi failed, err %s aq_err %s\n",
8842 i40e_stat_str(&pf->hw, ret),
8843 i40e_aq_str(&pf->hw,
8844 pf->hw.aq.asq_last_status));
41c445ff
JB		 8845 ret = -ENOENT;
8846 goto err;
8847 }
8848 /* update the local VSI info queue map */
8849 i40e_vsi_update_queue_map(vsi, &ctxt);
8850 vsi->info.valid_sections = 0;
8851 } else {
8852 /* Default/Main VSI is only enabled for TC0
8853 * reconfigure it to enable all TCs that are
8854 * available on the port in SFP mode.
63d7e5a4
NP		 8855 * For MFP case the iSCSI PF would use this
8856 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8857 */
8858 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8859 if (ret) {
8860 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8861 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8862 enabled_tc,
8863 i40e_stat_str(&pf->hw, ret),
8864 i40e_aq_str(&pf->hw,
8865 pf->hw.aq.asq_last_status));
41c445ff
JB		 8866 ret = -ENOENT;
8867 }
8868 }
8869 break;
8870
8871 case I40E_VSI_FDIR:
cbf61325
ASJ		 8872 ctxt.pf_num = hw->pf_id;
8873 ctxt.vf_num = 0;
8874 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8875 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8876 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8877 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8878 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8879 ctxt.info.valid_sections |=
fc60861e 8880 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8881 ctxt.info.switch_id =
fc60861e 8882 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8883 }
41c445ff 8884 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8885 break;
8886
8887 case I40E_VSI_VMDQ2:
8888 ctxt.pf_num = hw->pf_id;
8889 ctxt.vf_num = 0;
8890 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8891 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8892 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8893
41c445ff
JB		 8894 /* This VSI is connected to VEB so the switch_id
8895 * should be set to zero by default.
8896 */
51616018
NP		 8897 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8898 ctxt.info.valid_sections |=
8899 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8900 ctxt.info.switch_id =
8901 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8902 }
41c445ff
JB		 8903
8904 /* Setup the VSI tx/rx queue map for TC0 only for now */
8905 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8906 break;
8907
8908 case I40E_VSI_SRIOV:
8909 ctxt.pf_num = hw->pf_id;
8910 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8911 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8912 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8913 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8914
41c445ff
JB		 8915 /* This VSI is connected to VEB so the switch_id
8916 * should be set to zero by default.
8917 */
51616018
NP		 8918 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8919 ctxt.info.valid_sections |=
8920 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8921 ctxt.info.switch_id =
8922 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8923 }
41c445ff
JB		 8924
8925 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8926 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8927 if (pf->vf[vsi->vf_id].spoofchk) {
8928 ctxt.info.valid_sections |=
8929 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8930 ctxt.info.sec_flags |=
8931 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8932 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8933 }
41c445ff
JB		 8934 /* Setup the VSI tx/rx queue map for TC0 only for now */
8935 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8936 break;
8937
38e00438
VD		 8938#ifdef I40E_FCOE
8939 case I40E_VSI_FCOE:
8940 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8941 if (ret) {
8942 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8943 return ret;
8944 }
8945 break;
8946
8947#endif /* I40E_FCOE */
41c445ff
JB		 8948 default:
8949 return -ENODEV;
8950 }
8951
8952 if (vsi->type != I40E_VSI_MAIN) {
8953 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8954 if (ret) {
8955 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8956 "add vsi failed, err %s aq_err %s\n",
8957 i40e_stat_str(&pf->hw, ret),
8958 i40e_aq_str(&pf->hw,
8959 pf->hw.aq.asq_last_status));
41c445ff
JB		 8960 ret = -ENOENT;
8961 goto err;
8962 }
1a2f6248 8963 vsi->info = ctxt.info;
41c445ff
JB		 8964 vsi->info.valid_sections = 0;
8965 vsi->seid = ctxt.seid;
8966 vsi->id = ctxt.vsi_number;
8967 }
8968
21659035 8969 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 8970 /* If macvlan filters already exist, force them to get loaded */
8971 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8972 f->changed = true;
8973 f_count++;
6252c7e4 8974
21659035 8975 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 8976 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 8977 ether_addr_copy(laa_macaddr, f->macaddr);
8978 found_laa_mac_filter = true;
8979 }
8980 }
8981 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 8982
21659035
KP		 8983 if (found_laa_mac_filter) {
8984 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 8985
21659035
KP		 8986 memset(&element, 0, sizeof(element));
8987 ether_addr_copy(element.mac_addr, laa_macaddr);
8988 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8989 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8990 &element, 1, NULL);
8991 if (ret) {
8992 /* some older FW has a different default */
8993 element.flags |=
8994 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8995 i40e_aq_remove_macvlan(hw, vsi->seid,
8996 &element, 1, NULL);
6252c7e4 8997 }
21659035
KP		 8998
8999 i40e_aq_mac_address_write(hw,
9000 I40E_AQC_WRITE_TYPE_LAA_WOL,
9001 laa_macaddr, NULL);
41c445ff 9002 }
21659035 9003
41c445ff
JB		 9004 if (f_count) {
9005 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9006 pf->flags |= I40E_FLAG_FILTER_SYNC;
9007 }
9008
9009 /* Update VSI BW information */
9010 ret = i40e_vsi_get_bw_info(vsi);
9011 if (ret) {
9012 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9013 "couldn't get vsi bw info, err %s aq_err %s\n",
9014 i40e_stat_str(&pf->hw, ret),
9015 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9016 /* VSI is already added so not tearing that up */
9017 ret = 0;
9018 }
9019
9020err:
9021 return ret;
9022}
9023
9024/**
9025 * i40e_vsi_release - Delete a VSI and free its resources
9026 * @vsi: the VSI being removed
9027 *
9028 * Returns 0 on success or < 0 on error
9029 **/
9030int i40e_vsi_release(struct i40e_vsi *vsi)
9031{
9032 struct i40e_mac_filter *f, *ftmp;
9033 struct i40e_veb *veb = NULL;
9034 struct i40e_pf *pf;
9035 u16 uplink_seid;
9036 int i, n;
9037
9038 pf = vsi->back;
9039
9040 /* release of a VEB-owner or last VSI is not allowed */
9041 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9042 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9043 vsi->seid, vsi->uplink_seid);
9044 return -ENODEV;
9045 }
9046 if (vsi == pf->vsi[pf->lan_vsi] &&
9047 !test_bit(__I40E_DOWN, &pf->state)) {
9048 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9049 return -ENODEV;
9050 }
9051
9052 uplink_seid = vsi->uplink_seid;
9053 if (vsi->type != I40E_VSI_SRIOV) {
9054 if (vsi->netdev_registered) {
9055 vsi->netdev_registered = false;
9056 if (vsi->netdev) {
9057 /* results in a call to i40e_close() */
9058 unregister_netdev(vsi->netdev);
41c445ff
JB		 9059 }
9060 } else {
90ef8d47 9061 i40e_vsi_close(vsi);
41c445ff
JB		 9062 }
9063 i40e_vsi_disable_irq(vsi);
9064 }
9065
21659035 9066 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9067 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9068 i40e_del_filter(vsi, f->macaddr, f->vlan,
9069 f->is_vf, f->is_netdev);
21659035
KP		 9070 spin_unlock_bh(&vsi->mac_filter_list_lock);
9071
30e2561b 9072 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 9073
9074 i40e_vsi_delete(vsi);
9075 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9076 if (vsi->netdev) {
9077 free_netdev(vsi->netdev);
9078 vsi->netdev = NULL;
9079 }
41c445ff
JB		 9080 i40e_vsi_clear_rings(vsi);
9081 i40e_vsi_clear(vsi);
9082
9083 /* If this was the last thing on the VEB, except for the
9084 * controlling VSI, remove the VEB, which puts the controlling
9085 * VSI onto the next level down in the switch.
9086 *
9087 * Well, okay, there's one more exception here: don't remove
9088 * the orphan VEBs yet. We'll wait for an explicit remove request
9089 * from up the network stack.
9090 */
505682cd 9091 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9092 if (pf->vsi[i] &&
9093 pf->vsi[i]->uplink_seid == uplink_seid &&
9094 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9095 n++; /* count the VSIs */
9096 }
9097 }
9098 for (i = 0; i < I40E_MAX_VEB; i++) {
9099 if (!pf->veb[i])
9100 continue;
9101 if (pf->veb[i]->uplink_seid == uplink_seid)
9102 n++; /* count the VEBs */
9103 if (pf->veb[i]->seid == uplink_seid)
9104 veb = pf->veb[i];
9105 }
9106 if (n == 0 && veb && veb->uplink_seid != 0)
9107 i40e_veb_release(veb);
9108
9109 return 0;
9110}
9111
9112/**
9113 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9114 * @vsi: ptr to the VSI
9115 *
9116 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9117 * corresponding SW VSI structure and initializes num_queue_pairs for the
9118 * newly allocated VSI.
9119 *
9120 * Returns 0 on success or negative on failure
9121 **/
9122static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9123{
9124 int ret = -ENOENT;
9125 struct i40e_pf *pf = vsi->back;
9126
493fb300 9127 if (vsi->q_vectors[0]) {
41c445ff
JB		 9128 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9129 vsi->seid);
9130 return -EEXIST;
9131 }
9132
9133 if (vsi->base_vector) {
f29eaa3d 9134 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9135 vsi->seid, vsi->base_vector);
9136 return -EEXIST;
9137 }
9138
90e04070 9139 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9140 if (ret) {
9141 dev_info(&pf->pdev->dev,
9142 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9143 vsi->num_q_vectors, vsi->seid, ret);
9144 vsi->num_q_vectors = 0;
9145 goto vector_setup_out;
9146 }
9147
26cdc443
ASJ		 9148 /* In Legacy mode, we do not have to get any other vector since we
9149 * piggyback on the misc/ICR0 for queue interrupts.
9150 */
9151 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9152 return ret;
958a3e3b
SN		 9153 if (vsi->num_q_vectors)
9154 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9155 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9156 if (vsi->base_vector < 0) {
9157 dev_info(&pf->pdev->dev,
049a2be8
SN		 9158 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9159 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9160 i40e_vsi_free_q_vectors(vsi);
9161 ret = -ENOENT;
9162 goto vector_setup_out;
9163 }
9164
9165vector_setup_out:
9166 return ret;
9167}
9168
bc7d338f
ASJ		 9169/**
9170 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9171 * @vsi: pointer to the vsi.
9172 *
9173 * This re-allocates a vsi's queue resources.
9174 *
9175 * Returns pointer to the successfully allocated and configured VSI sw struct
9176 * on success, otherwise returns NULL on failure.
9177 **/
9178static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9179{
9180 struct i40e_pf *pf = vsi->back;
9181 u8 enabled_tc;
9182 int ret;
9183
9184 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9185 i40e_vsi_clear_rings(vsi);
9186
9187 i40e_vsi_free_arrays(vsi, false);
9188 i40e_set_num_rings_in_vsi(vsi);
9189 ret = i40e_vsi_alloc_arrays(vsi, false);
9190 if (ret)
9191 goto err_vsi;
9192
9193 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9194 if (ret < 0) {
049a2be8 9195 dev_info(&pf->pdev->dev,
f1c7e72e 9196 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9197 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9198 goto err_vsi;
9199 }
9200 vsi->base_queue = ret;
9201
9202 /* Update the FW view of the VSI. Force a reset of TC and queue
9203 * layout configurations.
9204 */
9205 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9206 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9207 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9208 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9209
9210 /* assign it some queues */
9211 ret = i40e_alloc_rings(vsi);
9212 if (ret)
9213 goto err_rings;
9214
9215 /* map all of the rings to the q_vectors */
9216 i40e_vsi_map_rings_to_vectors(vsi);
9217 return vsi;
9218
9219err_rings:
9220 i40e_vsi_free_q_vectors(vsi);
9221 if (vsi->netdev_registered) {
9222 vsi->netdev_registered = false;
9223 unregister_netdev(vsi->netdev);
9224 free_netdev(vsi->netdev);
9225 vsi->netdev = NULL;
9226 }
9227 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9228err_vsi:
9229 i40e_vsi_clear(vsi);
9230 return NULL;
9231}
9232
41c445ff
JB		 9233/**
9234 * i40e_vsi_setup - Set up a VSI by a given type
9235 * @pf: board private structure
9236 * @type: VSI type
9237 * @uplink_seid: the switch element to link to
9238 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9239 *
9240 * This allocates the sw VSI structure and its queue resources, then add a VSI
9241 * to the identified VEB.
9242 *
9243 * Returns pointer to the successfully allocated and configure VSI sw struct on
9244 * success, otherwise returns NULL on failure.
9245 **/
9246struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9247 u16 uplink_seid, u32 param1)
9248{
9249 struct i40e_vsi *vsi = NULL;
9250 struct i40e_veb *veb = NULL;
9251 int ret, i;
9252 int v_idx;
9253
9254 /* The requested uplink_seid must be either
9255 * - the PF's port seid
9256 * no VEB is needed because this is the PF
9257 * or this is a Flow Director special case VSI
9258 * - seid of an existing VEB
9259 * - seid of a VSI that owns an existing VEB
9260 * - seid of a VSI that doesn't own a VEB
9261 * a new VEB is created and the VSI becomes the owner
9262 * - seid of the PF VSI, which is what creates the first VEB
9263 * this is a special case of the previous
9264 *
9265 * Find which uplink_seid we were given and create a new VEB if needed
9266 */
9267 for (i = 0; i < I40E_MAX_VEB; i++) {
9268 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9269 veb = pf->veb[i];
9270 break;
9271 }
9272 }
9273
9274 if (!veb && uplink_seid != pf->mac_seid) {
9275
505682cd 9276 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9277 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9278 vsi = pf->vsi[i];
9279 break;
9280 }
9281 }
9282 if (!vsi) {
9283 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9284 uplink_seid);
9285 return NULL;
9286 }
9287
9288 if (vsi->uplink_seid == pf->mac_seid)
9289 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9290 vsi->tc_config.enabled_tc);
9291 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9292 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9293 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9294 if (veb) {
9295 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9296 dev_info(&vsi->back->pdev->dev,
fb43201f 9297 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9298 return NULL;
9299 }
fa11cb3d
ASJ		 9300 /* We come up by default in VEPA mode if SRIOV is not
9301 * already enabled, in which case we can't force VEPA
9302 * mode.
9303 */
9304 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9305 veb->bridge_mode = BRIDGE_MODE_VEPA;
9306 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9307 }
51616018 9308 i40e_config_bridge_mode(veb);
79c21a82 9309 }
41c445ff
JB		 9310 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9311 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9312 veb = pf->veb[i];
9313 }
9314 if (!veb) {
9315 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9316 return NULL;
9317 }
9318
9319 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9320 uplink_seid = veb->seid;
9321 }
9322
9323 /* get vsi sw struct */
9324 v_idx = i40e_vsi_mem_alloc(pf, type);
9325 if (v_idx < 0)
9326 goto err_alloc;
9327 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9328 if (!vsi)
9329 goto err_alloc;
41c445ff
JB		 9330 vsi->type = type;
9331 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9332
9333 if (type == I40E_VSI_MAIN)
9334 pf->lan_vsi = v_idx;
9335 else if (type == I40E_VSI_SRIOV)
9336 vsi->vf_id = param1;
9337 /* assign it some queues */
cbf61325
ASJ		 9338 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9339 vsi->idx);
41c445ff 9340 if (ret < 0) {
049a2be8
SN		 9341 dev_info(&pf->pdev->dev,
9342 "failed to get tracking for %d queues for VSI %d err=%d\n",
9343 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9344 goto err_vsi;
9345 }
9346 vsi->base_queue = ret;
9347
9348 /* get a VSI from the hardware */
9349 vsi->uplink_seid = uplink_seid;
9350 ret = i40e_add_vsi(vsi);
9351 if (ret)
9352 goto err_vsi;
9353
9354 switch (vsi->type) {
9355 /* setup the netdev if needed */
9356 case I40E_VSI_MAIN:
9357 case I40E_VSI_VMDQ2:
38e00438 9358 case I40E_VSI_FCOE:
41c445ff
JB		 9359 ret = i40e_config_netdev(vsi);
9360 if (ret)
9361 goto err_netdev;
9362 ret = register_netdev(vsi->netdev);
9363 if (ret)
9364 goto err_netdev;
9365 vsi->netdev_registered = true;
9366 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9367#ifdef CONFIG_I40E_DCB
9368 /* Setup DCB netlink interface */
9369 i40e_dcbnl_setup(vsi);
9370#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9371 /* fall through */
9372
9373 case I40E_VSI_FDIR:
9374 /* set up vectors and rings if needed */
9375 ret = i40e_vsi_setup_vectors(vsi);
9376 if (ret)
9377 goto err_msix;
9378
9379 ret = i40e_alloc_rings(vsi);
9380 if (ret)
9381 goto err_rings;
9382
9383 /* map all of the rings to the q_vectors */
9384 i40e_vsi_map_rings_to_vectors(vsi);
9385
9386 i40e_vsi_reset_stats(vsi);
9387 break;
9388
9389 default:
9390 /* no netdev or rings for the other VSI types */
9391 break;
9392 }
9393
e25d00b8
ASJ		 9394 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9395 (vsi->type == I40E_VSI_VMDQ2)) {
9396 ret = i40e_vsi_config_rss(vsi);
9397 }
41c445ff
JB		 9398 return vsi;
9399
9400err_rings:
9401 i40e_vsi_free_q_vectors(vsi);
9402err_msix:
9403 if (vsi->netdev_registered) {
9404 vsi->netdev_registered = false;
9405 unregister_netdev(vsi->netdev);
9406 free_netdev(vsi->netdev);
9407 vsi->netdev = NULL;
9408 }
9409err_netdev:
9410 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9411err_vsi:
9412 i40e_vsi_clear(vsi);
9413err_alloc:
9414 return NULL;
9415}
9416
9417/**
9418 * i40e_veb_get_bw_info - Query VEB BW information
9419 * @veb: the veb to query
9420 *
9421 * Query the Tx scheduler BW configuration data for given VEB
9422 **/
9423static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9424{
9425 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9426 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9427 struct i40e_pf *pf = veb->pf;
9428 struct i40e_hw *hw = &pf->hw;
9429 u32 tc_bw_max;
9430 int ret = 0;
9431 int i;
9432
9433 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9434 &bw_data, NULL);
9435 if (ret) {
9436 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9437 "query veb bw config failed, err %s aq_err %s\n",
9438 i40e_stat_str(&pf->hw, ret),
9439 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9440 goto out;
9441 }
9442
9443 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9444 &ets_data, NULL);
9445 if (ret) {
9446 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9447 "query veb bw ets config failed, err %s aq_err %s\n",
9448 i40e_stat_str(&pf->hw, ret),
9449 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9450 goto out;
9451 }
9452
9453 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9454 veb->bw_max_quanta = ets_data.tc_bw_max;
9455 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9456 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9457 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9458 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9459 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9460 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9461 veb->bw_tc_limit_credits[i] =
9462 le16_to_cpu(bw_data.tc_bw_limits[i]);
9463 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9464 }
9465
9466out:
9467 return ret;
9468}
9469
9470/**
9471 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9472 * @pf: board private structure
9473 *
9474 * On error: returns error code (negative)
9475 * On success: returns vsi index in PF (positive)
9476 **/
9477static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9478{
9479 int ret = -ENOENT;
9480 struct i40e_veb *veb;
9481 int i;
9482
9483 /* Need to protect the allocation of switch elements at the PF level */
9484 mutex_lock(&pf->switch_mutex);
9485
9486 /* VEB list may be fragmented if VEB creation/destruction has
9487 * been happening. We can afford to do a quick scan to look
9488 * for any free slots in the list.
9489 *
9490 * find next empty veb slot, looping back around if necessary
9491 */
9492 i = 0;
9493 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9494 i++;
9495 if (i >= I40E_MAX_VEB) {
9496 ret = -ENOMEM;
9497 goto err_alloc_veb; /* out of VEB slots! */
9498 }
9499
9500 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9501 if (!veb) {
9502 ret = -ENOMEM;
9503 goto err_alloc_veb;
9504 }
9505 veb->pf = pf;
9506 veb->idx = i;
9507 veb->enabled_tc = 1;
9508
9509 pf->veb[i] = veb;
9510 ret = i;
9511err_alloc_veb:
9512 mutex_unlock(&pf->switch_mutex);
9513 return ret;
9514}
9515
9516/**
9517 * i40e_switch_branch_release - Delete a branch of the switch tree
9518 * @branch: where to start deleting
9519 *
9520 * This uses recursion to find the tips of the branch to be
9521 * removed, deleting until we get back to and can delete this VEB.
9522 **/
9523static void i40e_switch_branch_release(struct i40e_veb *branch)
9524{
9525 struct i40e_pf *pf = branch->pf;
9526 u16 branch_seid = branch->seid;
9527 u16 veb_idx = branch->idx;
9528 int i;
9529
9530 /* release any VEBs on this VEB - RECURSION */
9531 for (i = 0; i < I40E_MAX_VEB; i++) {
9532 if (!pf->veb[i])
9533 continue;
9534 if (pf->veb[i]->uplink_seid == branch->seid)
9535 i40e_switch_branch_release(pf->veb[i]);
9536 }
9537
9538 /* Release the VSIs on this VEB, but not the owner VSI.
9539 *
9540 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9541 * the VEB itself, so don't use (*branch) after this loop.
9542 */
505682cd 9543 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9544 if (!pf->vsi[i])
9545 continue;
9546 if (pf->vsi[i]->uplink_seid == branch_seid &&
9547 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9548 i40e_vsi_release(pf->vsi[i]);
9549 }
9550 }
9551
9552 /* There's one corner case where the VEB might not have been
9553 * removed, so double check it here and remove it if needed.
9554 * This case happens if the veb was created from the debugfs
9555 * commands and no VSIs were added to it.
9556 */
9557 if (pf->veb[veb_idx])
9558 i40e_veb_release(pf->veb[veb_idx]);
9559}
9560
9561/**
9562 * i40e_veb_clear - remove veb struct
9563 * @veb: the veb to remove
9564 **/
9565static void i40e_veb_clear(struct i40e_veb *veb)
9566{
9567 if (!veb)
9568 return;
9569
9570 if (veb->pf) {
9571 struct i40e_pf *pf = veb->pf;
9572
9573 mutex_lock(&pf->switch_mutex);
9574 if (pf->veb[veb->idx] == veb)
9575 pf->veb[veb->idx] = NULL;
9576 mutex_unlock(&pf->switch_mutex);
9577 }
9578
9579 kfree(veb);
9580}
9581
9582/**
9583 * i40e_veb_release - Delete a VEB and free its resources
9584 * @veb: the VEB being removed
9585 **/
9586void i40e_veb_release(struct i40e_veb *veb)
9587{
9588 struct i40e_vsi *vsi = NULL;
9589 struct i40e_pf *pf;
9590 int i, n = 0;
9591
9592 pf = veb->pf;
9593
9594 /* find the remaining VSI and check for extras */
505682cd 9595 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9596 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9597 n++;
9598 vsi = pf->vsi[i];
9599 }
9600 }
9601 if (n != 1) {
9602 dev_info(&pf->pdev->dev,
9603 "can't remove VEB %d with %d VSIs left\n",
9604 veb->seid, n);
9605 return;
9606 }
9607
9608 /* move the remaining VSI to uplink veb */
9609 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9610 if (veb->uplink_seid) {
9611 vsi->uplink_seid = veb->uplink_seid;
9612 if (veb->uplink_seid == pf->mac_seid)
9613 vsi->veb_idx = I40E_NO_VEB;
9614 else
9615 vsi->veb_idx = veb->veb_idx;
9616 } else {
9617 /* floating VEB */
9618 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9619 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9620 }
9621
9622 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9623 i40e_veb_clear(veb);
41c445ff
JB		 9624}
9625
9626/**
9627 * i40e_add_veb - create the VEB in the switch
9628 * @veb: the VEB to be instantiated
9629 * @vsi: the controlling VSI
9630 **/
9631static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9632{
f1c7e72e 9633 struct i40e_pf *pf = veb->pf;
92faef85 9634 bool is_default = veb->pf->cur_promisc;
e1c51b95 9635 bool is_cloud = false;
41c445ff
JB		 9636 int ret;
9637
9638 /* get a VEB from the hardware */
f1c7e72e 9639 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9640 veb->enabled_tc, is_default,
9641 is_cloud, &veb->seid, NULL);
41c445ff 9642 if (ret) {
f1c7e72e
SN		 9643 dev_info(&pf->pdev->dev,
9644 "couldn't add VEB, err %s aq_err %s\n",
9645 i40e_stat_str(&pf->hw, ret),
9646 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9647 return -EPERM;
9648 }
9649
9650 /* get statistics counter */
f1c7e72e 9651 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9652 &veb->stats_idx, NULL, NULL, NULL);
9653 if (ret) {
f1c7e72e
SN		 9654 dev_info(&pf->pdev->dev,
9655 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9656 i40e_stat_str(&pf->hw, ret),
9657 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9658 return -EPERM;
9659 }
9660 ret = i40e_veb_get_bw_info(veb);
9661 if (ret) {
f1c7e72e
SN		 9662 dev_info(&pf->pdev->dev,
9663 "couldn't get VEB bw info, err %s aq_err %s\n",
9664 i40e_stat_str(&pf->hw, ret),
9665 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9666 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9667 return -ENOENT;
9668 }
9669
9670 vsi->uplink_seid = veb->seid;
9671 vsi->veb_idx = veb->idx;
9672 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9673
9674 return 0;
9675}
9676
9677/**
9678 * i40e_veb_setup - Set up a VEB
9679 * @pf: board private structure
9680 * @flags: VEB setup flags
9681 * @uplink_seid: the switch element to link to
9682 * @vsi_seid: the initial VSI seid
9683 * @enabled_tc: Enabled TC bit-map
9684 *
9685 * This allocates the sw VEB structure and links it into the switch
9686 * It is possible and legal for this to be a duplicate of an already
9687 * existing VEB. It is also possible for both uplink and vsi seids
9688 * to be zero, in order to create a floating VEB.
9689 *
9690 * Returns pointer to the successfully allocated VEB sw struct on
9691 * success, otherwise returns NULL on failure.
9692 **/
9693struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9694 u16 uplink_seid, u16 vsi_seid,
9695 u8 enabled_tc)
9696{
9697 struct i40e_veb *veb, *uplink_veb = NULL;
9698 int vsi_idx, veb_idx;
9699 int ret;
9700
9701 /* if one seid is 0, the other must be 0 to create a floating relay */
9702 if ((uplink_seid == 0 || vsi_seid == 0) &&
9703 (uplink_seid + vsi_seid != 0)) {
9704 dev_info(&pf->pdev->dev,
9705 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9706 uplink_seid, vsi_seid);
9707 return NULL;
9708 }
9709
9710 /* make sure there is such a vsi and uplink */
505682cd 9711 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9712 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9713 break;
505682cd 9714 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9715 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9716 vsi_seid);
9717 return NULL;
9718 }
9719
9720 if (uplink_seid && uplink_seid != pf->mac_seid) {
9721 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9722 if (pf->veb[veb_idx] &&
9723 pf->veb[veb_idx]->seid == uplink_seid) {
9724 uplink_veb = pf->veb[veb_idx];
9725 break;
9726 }
9727 }
9728 if (!uplink_veb) {
9729 dev_info(&pf->pdev->dev,
9730 "uplink seid %d not found\n", uplink_seid);
9731 return NULL;
9732 }
9733 }
9734
9735 /* get veb sw struct */
9736 veb_idx = i40e_veb_mem_alloc(pf);
9737 if (veb_idx < 0)
9738 goto err_alloc;
9739 veb = pf->veb[veb_idx];
9740 veb->flags = flags;
9741 veb->uplink_seid = uplink_seid;
9742 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9743 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9744
9745 /* create the VEB in the switch */
9746 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9747 if (ret)
9748 goto err_veb;
1bb8b935
SN		 9749 if (vsi_idx == pf->lan_vsi)
9750 pf->lan_veb = veb->idx;
41c445ff
JB		 9751
9752 return veb;
9753
9754err_veb:
9755 i40e_veb_clear(veb);
9756err_alloc:
9757 return NULL;
9758}
9759
9760/**
b40c82e6 9761 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9762 * @pf: board private structure
9763 * @ele: element we are building info from
9764 * @num_reported: total number of elements
9765 * @printconfig: should we print the contents
9766 *
9767 * helper function to assist in extracting a few useful SEID values.
9768 **/
9769static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9770 struct i40e_aqc_switch_config_element_resp *ele,
9771 u16 num_reported, bool printconfig)
9772{
9773 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9774 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9775 u8 element_type = ele->element_type;
9776 u16 seid = le16_to_cpu(ele->seid);
9777
9778 if (printconfig)
9779 dev_info(&pf->pdev->dev,
9780 "type=%d seid=%d uplink=%d downlink=%d\n",
9781 element_type, seid, uplink_seid, downlink_seid);
9782
9783 switch (element_type) {
9784 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9785 pf->mac_seid = seid;
9786 break;
9787 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9788 /* Main VEB? */
9789 if (uplink_seid != pf->mac_seid)
9790 break;
9791 if (pf->lan_veb == I40E_NO_VEB) {
9792 int v;
9793
9794 /* find existing or else empty VEB */
9795 for (v = 0; v < I40E_MAX_VEB; v++) {
9796 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9797 pf->lan_veb = v;
9798 break;
9799 }
9800 }
9801 if (pf->lan_veb == I40E_NO_VEB) {
9802 v = i40e_veb_mem_alloc(pf);
9803 if (v < 0)
9804 break;
9805 pf->lan_veb = v;
9806 }
9807 }
9808
9809 pf->veb[pf->lan_veb]->seid = seid;
9810 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9811 pf->veb[pf->lan_veb]->pf = pf;
9812 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9813 break;
9814 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9815 if (num_reported != 1)
9816 break;
9817 /* This is immediately after a reset so we can assume this is
9818 * the PF's VSI
9819 */
9820 pf->mac_seid = uplink_seid;
9821 pf->pf_seid = downlink_seid;
9822 pf->main_vsi_seid = seid;
9823 if (printconfig)
9824 dev_info(&pf->pdev->dev,
9825 "pf_seid=%d main_vsi_seid=%d\n",
9826 pf->pf_seid, pf->main_vsi_seid);
9827 break;
9828 case I40E_SWITCH_ELEMENT_TYPE_PF:
9829 case I40E_SWITCH_ELEMENT_TYPE_VF:
9830 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9831 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9832 case I40E_SWITCH_ELEMENT_TYPE_PE:
9833 case I40E_SWITCH_ELEMENT_TYPE_PA:
9834 /* ignore these for now */
9835 break;
9836 default:
9837 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9838 element_type, seid);
9839 break;
9840 }
9841}
9842
9843/**
9844 * i40e_fetch_switch_configuration - Get switch config from firmware
9845 * @pf: board private structure
9846 * @printconfig: should we print the contents
9847 *
9848 * Get the current switch configuration from the device and
9849 * extract a few useful SEID values.
9850 **/
9851int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9852{
9853 struct i40e_aqc_get_switch_config_resp *sw_config;
9854 u16 next_seid = 0;
9855 int ret = 0;
9856 u8 *aq_buf;
9857 int i;
9858
9859 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9860 if (!aq_buf)
9861 return -ENOMEM;
9862
9863 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9864 do {
9865 u16 num_reported, num_total;
9866
9867 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9868 I40E_AQ_LARGE_BUF,
9869 &next_seid, NULL);
9870 if (ret) {
9871 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9872 "get switch config failed err %s aq_err %s\n",
9873 i40e_stat_str(&pf->hw, ret),
9874 i40e_aq_str(&pf->hw,
9875 pf->hw.aq.asq_last_status));
41c445ff
JB		 9876 kfree(aq_buf);
9877 return -ENOENT;
9878 }
9879
9880 num_reported = le16_to_cpu(sw_config->header.num_reported);
9881 num_total = le16_to_cpu(sw_config->header.num_total);
9882
9883 if (printconfig)
9884 dev_info(&pf->pdev->dev,
9885 "header: %d reported %d total\n",
9886 num_reported, num_total);
9887
41c445ff
JB		 9888 for (i = 0; i < num_reported; i++) {
9889 struct i40e_aqc_switch_config_element_resp *ele =
9890 &sw_config->element[i];
9891
9892 i40e_setup_pf_switch_element(pf, ele, num_reported,
9893 printconfig);
9894 }
9895 } while (next_seid != 0);
9896
9897 kfree(aq_buf);
9898 return ret;
9899}
9900
9901/**
9902 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9903 * @pf: board private structure
bc7d338f 9904 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9905 *
9906 * Returns 0 on success, negative value on failure
9907 **/
bc7d338f 9908static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9909{
9910 int ret;
9911
9912 /* find out what's out there already */
9913 ret = i40e_fetch_switch_configuration(pf, false);
9914 if (ret) {
9915 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9916 "couldn't fetch switch config, err %s aq_err %s\n",
9917 i40e_stat_str(&pf->hw, ret),
9918 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9919 return ret;
9920 }
9921 i40e_pf_reset_stats(pf);
9922
41c445ff 9923 /* first time setup */
bc7d338f 9924 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9925 struct i40e_vsi *vsi = NULL;
9926 u16 uplink_seid;
9927
9928 /* Set up the PF VSI associated with the PF's main VSI
9929 * that is already in the HW switch
9930 */
9931 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9932 uplink_seid = pf->veb[pf->lan_veb]->seid;
9933 else
9934 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9935 if (pf->lan_vsi == I40E_NO_VSI)
9936 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9937 else if (reinit)
9938 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9939 if (!vsi) {
9940 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9941 i40e_fdir_teardown(pf);
9942 return -EAGAIN;
9943 }
41c445ff
JB		 9944 } else {
9945 /* force a reset of TC and queue layout configurations */
9946 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 9947
41c445ff
JB		 9948 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9949 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9950 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9951 }
9952 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9953
cbf61325
ASJ		 9954 i40e_fdir_sb_setup(pf);
9955
41c445ff
JB		 9956 /* Setup static PF queue filter control settings */
9957 ret = i40e_setup_pf_filter_control(pf);
9958 if (ret) {
9959 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9960 ret);
9961 /* Failure here should not stop continuing other steps */
9962 }
9963
9964 /* enable RSS in the HW, even for only one queue, as the stack can use
9965 * the hash
9966 */
9967 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9968 i40e_config_rss(pf);
9969
9970 /* fill in link information and enable LSE reporting */
0a862b43 9971 i40e_update_link_info(&pf->hw);
a34a6711
MW		 9972 i40e_link_event(pf);
9973
d52c20b7 9974 /* Initialize user-specific link properties */
41c445ff
JB		 9975 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9976 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9977
beb0dff1
JK		 9978 i40e_ptp_init(pf);
9979
41c445ff
JB		 9980 return ret;
9981}
9982
41c445ff
JB		 9983/**
9984 * i40e_determine_queue_usage - Work out queue distribution
9985 * @pf: board private structure
9986 **/
9987static void i40e_determine_queue_usage(struct i40e_pf *pf)
9988{
41c445ff
JB		 9989 int queues_left;
9990
9991 pf->num_lan_qps = 0;
38e00438
VD		 9992#ifdef I40E_FCOE
9993 pf->num_fcoe_qps = 0;
9994#endif
41c445ff
JB		 9995
9996 /* Find the max queues to be put into basic use. We'll always be
9997 * using TC0, whether or not DCB is running, and TC0 will get the
9998 * big RSS set.
9999 */
10000 queues_left = pf->hw.func_caps.num_tx_qp;
10001
cbf61325 10002 if ((queues_left == 1) ||
9aa7e935 10003 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10004 /* one qp for PF, no queues for anything else */
10005 queues_left = 0;
10006 pf->rss_size = pf->num_lan_qps = 1;
10007
10008 /* make sure all the fancies are disabled */
60ea5f83 10009 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10010#ifdef I40E_FCOE
10011 I40E_FLAG_FCOE_ENABLED |
10012#endif
60ea5f83
JB		 10013 I40E_FLAG_FD_SB_ENABLED |
10014 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10015 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10016 I40E_FLAG_SRIOV_ENABLED |
10017 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10018 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10019 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10020 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10021 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 10022 /* one qp for PF */
10023 pf->rss_size = pf->num_lan_qps = 1;
10024 queues_left -= pf->num_lan_qps;
10025
10026 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10027#ifdef I40E_FCOE
10028 I40E_FLAG_FCOE_ENABLED |
10029#endif
9aa7e935
FZ		 10030 I40E_FLAG_FD_SB_ENABLED |
10031 I40E_FLAG_FD_ATR_ENABLED |
10032 I40E_FLAG_DCB_ENABLED |
10033 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10034 } else {
cbf61325 10035 /* Not enough queues for all TCs */
4d9b6043 10036 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10037 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10038 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10039 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10040 }
9a3bd2f1
ASJ		 10041 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10042 num_online_cpus());
10043 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10044 pf->hw.func_caps.num_tx_qp);
10045
cbf61325
ASJ		 10046 queues_left -= pf->num_lan_qps;
10047 }
10048
38e00438
VD		 10049#ifdef I40E_FCOE
10050 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10051 if (I40E_DEFAULT_FCOE <= queues_left) {
10052 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10053 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10054 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10055 } else {
10056 pf->num_fcoe_qps = 0;
10057 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10058 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10059 }
10060
10061 queues_left -= pf->num_fcoe_qps;
10062 }
10063
10064#endif
cbf61325
ASJ		 10065 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10066 if (queues_left > 1) {
10067 queues_left -= 1; /* save 1 queue for FD */
10068 } else {
10069 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10070 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10071 }
41c445ff
JB		 10072 }
10073
10074 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10075 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10076 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10077 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10078 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10079 }
10080
10081 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10082 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10083 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10084 (queues_left / pf->num_vmdq_qps));
10085 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10086 }
10087
f8ff1464 10088 pf->queues_left = queues_left;
8279e495
NP		 10089 dev_dbg(&pf->pdev->dev,
10090 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10091 pf->hw.func_caps.num_tx_qp,
10092 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
10093 pf->num_lan_qps, pf->rss_size, pf->num_req_vfs, pf->num_vf_qps,
10094 pf->num_vmdq_vsis, pf->num_vmdq_qps, queues_left);
38e00438 10095#ifdef I40E_FCOE
8279e495 10096 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10097#endif
41c445ff
JB		 10098}
10099
10100/**
10101 * i40e_setup_pf_filter_control - Setup PF static filter control
10102 * @pf: PF to be setup
10103 *
b40c82e6 10104 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10105 * settings. If PE/FCoE are enabled then it will also set the per PF
10106 * based filter sizes required for them. It also enables Flow director,
10107 * ethertype and macvlan type filter settings for the pf.
10108 *
10109 * Returns 0 on success, negative on failure
10110 **/
10111static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10112{
10113 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10114
10115 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10116
10117 /* Flow Director is enabled */
60ea5f83 10118 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10119 settings->enable_fdir = true;
10120
10121 /* Ethtype and MACVLAN filters enabled for PF */
10122 settings->enable_ethtype = true;
10123 settings->enable_macvlan = true;
10124
10125 if (i40e_set_filter_control(&pf->hw, settings))
10126 return -ENOENT;
10127
10128 return 0;
10129}
10130
0c22b3dd 10131#define INFO_STRING_LEN 255
7fd89545 10132#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10133static void i40e_print_features(struct i40e_pf *pf)
10134{
10135 struct i40e_hw *hw = &pf->hw;
10136 char *buf, *string;
7fd89545 10137 int i = 0;
0c22b3dd
JB		 10138
10139 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
10140 if (!string) {
10141 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
10142 return;
10143 }
10144
10145 buf = string;
10146
7fd89545 10147 i += snprintf(&buf[i], REMAIN(i), "Features: PF-id[%d] ", hw->pf_id);
0c22b3dd 10148#ifdef CONFIG_PCI_IOV
7fd89545 10149 i += snprintf(&buf[i], REMAIN(i), "VFs: %d ", pf->num_req_vfs);
0c22b3dd 10150#endif
7fd89545
SN		 10151 i += snprintf(&buf[i], REMAIN(i), "VSIs: %d QP: %d RX: %s ",
10152 pf->hw.func_caps.num_vsis,
10153 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10154 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10155
10156 if (pf->flags & I40E_FLAG_RSS_ENABLED)
7fd89545 10157 i += snprintf(&buf[i], REMAIN(i), "RSS ");
0c22b3dd 10158 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
7fd89545 10159 i += snprintf(&buf[i], REMAIN(i), "FD_ATR ");
c6423ff1 10160 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7fd89545
SN		 10161 i += snprintf(&buf[i], REMAIN(i), "FD_SB ");
10162 i += snprintf(&buf[i], REMAIN(i), "NTUPLE ");
c6423ff1 10163 }
4d9b6043 10164 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
7fd89545 10165 i += snprintf(&buf[i], REMAIN(i), "DCB ");
ce6fcb3f 10166#if IS_ENABLED(CONFIG_VXLAN)
7fd89545 10167 i += snprintf(&buf[i], REMAIN(i), "VxLAN ");
ce6fcb3f 10168#endif
0c22b3dd 10169 if (pf->flags & I40E_FLAG_PTP)
7fd89545 10170 i += snprintf(&buf[i], REMAIN(i), "PTP ");
38e00438
VD		 10171#ifdef I40E_FCOE
10172 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
7fd89545 10173 i += snprintf(&buf[i], REMAIN(i), "FCOE ");
38e00438 10174#endif
6dec1017 10175 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
7fd89545 10176 i += snprintf(&buf[i], REMAIN(i), "VEPA ");
6dec1017
SN		 10177 else
10178 buf += sprintf(buf, "VEPA ");
0c22b3dd 10179
0c22b3dd
JB		 10180 dev_info(&pf->pdev->dev, "%s\n", string);
10181 kfree(string);
7fd89545 10182 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10183}
10184
41c445ff
JB		 10185/**
10186 * i40e_probe - Device initialization routine
10187 * @pdev: PCI device information struct
10188 * @ent: entry in i40e_pci_tbl
10189 *
b40c82e6
JK		 10190 * i40e_probe initializes a PF identified by a pci_dev structure.
10191 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10192 * and a hardware reset occur.
10193 *
10194 * Returns 0 on success, negative on failure
10195 **/
10196static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10197{
e827845c 10198 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10199 struct i40e_pf *pf;
10200 struct i40e_hw *hw;
93cd765b 10201 static u16 pfs_found;
1d5109d1 10202 u16 wol_nvm_bits;
d4dfb81a 10203 u16 link_status;
6f66a484 10204 int err;
41c445ff 10205 u32 len;
4f2f017c 10206 u32 val;
8a9eb7d3 10207 u32 i;
58fc3267 10208 u8 set_fc_aq_fail;
41c445ff
JB		 10209
10210 err = pci_enable_device_mem(pdev);
10211 if (err)
10212 return err;
10213
10214 /* set up for high or low dma */
6494294f 10215 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10216 if (err) {
e3e3bfdd
JS		 10217 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10218 if (err) {
10219 dev_err(&pdev->dev,
10220 "DMA configuration failed: 0x%x\n", err);
10221 goto err_dma;
10222 }
41c445ff
JB		 10223 }
10224
10225 /* set up pci connections */
10226 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10227 IORESOURCE_MEM), i40e_driver_name);
10228 if (err) {
10229 dev_info(&pdev->dev,
10230 "pci_request_selected_regions failed %d\n", err);
10231 goto err_pci_reg;
10232 }
10233
10234 pci_enable_pcie_error_reporting(pdev);
10235 pci_set_master(pdev);
10236
10237 /* Now that we have a PCI connection, we need to do the
10238 * low level device setup. This is primarily setting up
10239 * the Admin Queue structures and then querying for the
10240 * device's current profile information.
10241 */
10242 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10243 if (!pf) {
10244 err = -ENOMEM;
10245 goto err_pf_alloc;
10246 }
10247 pf->next_vsi = 0;
10248 pf->pdev = pdev;
10249 set_bit(__I40E_DOWN, &pf->state);
10250
10251 hw = &pf->hw;
10252 hw->back = pf;
232f4706 10253
2ac8b675
SN		 10254 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10255 I40E_MAX_CSR_SPACE);
232f4706 10256
2ac8b675 10257 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10258 if (!hw->hw_addr) {
10259 err = -EIO;
10260 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10261 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10262 pf->ioremap_len, err);
41c445ff
JB		 10263 goto err_ioremap;
10264 }
10265 hw->vendor_id = pdev->vendor;
10266 hw->device_id = pdev->device;
10267 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10268 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10269 hw->subsystem_device_id = pdev->subsystem_device;
10270 hw->bus.device = PCI_SLOT(pdev->devfn);
10271 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10272 pf->instance = pfs_found;
41c445ff 10273
5b5faa43
SN		 10274 if (debug != -1) {
10275 pf->msg_enable = pf->hw.debug_mask;
10276 pf->msg_enable = debug;
10277 }
10278
7134f9ce
JB		 10279 /* do a special CORER for clearing PXE mode once at init */
10280 if (hw->revision_id == 0 &&
10281 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10282 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10283 i40e_flush(hw);
10284 msleep(200);
10285 pf->corer_count++;
10286
10287 i40e_clear_pxe_mode(hw);
10288 }
10289
41c445ff 10290 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10291 i40e_clear_hw(hw);
41c445ff
JB		 10292 err = i40e_pf_reset(hw);
10293 if (err) {
10294 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10295 goto err_pf_reset;
10296 }
10297 pf->pfr_count++;
10298
10299 hw->aq.num_arq_entries = I40E_AQ_LEN;
10300 hw->aq.num_asq_entries = I40E_AQ_LEN;
10301 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10302 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10303 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10304
b294ac70 10305 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10306 "%s-%s:misc",
10307 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10308
10309 err = i40e_init_shared_code(hw);
10310 if (err) {
b2a75c58
ASJ		 10311 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10312 err);
41c445ff
JB		 10313 goto err_pf_reset;
10314 }
10315
d52c20b7
JB		 10316 /* set up a default setting for link flow control */
10317 pf->hw.fc.requested_mode = I40E_FC_NONE;
10318
41c445ff 10319 err = i40e_init_adminq(hw);
f0b44440 10320
6dec1017
SN		 10321 /* provide nvm, fw, api versions */
10322 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10323 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10324 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10325 i40e_nvm_version_str(hw));
f0b44440 10326
41c445ff
JB		 10327 if (err) {
10328 dev_info(&pdev->dev,
7aa67613 10329 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10330 goto err_pf_reset;
10331 }
10332
7aa67613
CS		 10333 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10334 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10335 dev_info(&pdev->dev,
7aa67613
CS		 10336 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10337 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10338 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10339 dev_info(&pdev->dev,
7aa67613 10340 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10341
4eb3f768
SN		 10342 i40e_verify_eeprom(pf);
10343
2c5fe33b
JB		 10344 /* Rev 0 hardware was never productized */
10345 if (hw->revision_id < 1)
10346 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10347
6ff4ef86 10348 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10349 err = i40e_get_capabilities(pf);
10350 if (err)
10351 goto err_adminq_setup;
10352
10353 err = i40e_sw_init(pf);
10354 if (err) {
10355 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10356 goto err_sw_init;
10357 }
10358
10359 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10360 hw->func_caps.num_rx_qp,
10361 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10362 if (err) {
10363 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10364 goto err_init_lan_hmc;
10365 }
10366
10367 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10368 if (err) {
10369 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10370 err = -ENOENT;
10371 goto err_configure_lan_hmc;
10372 }
10373
b686ece5
NP		 10374 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10375 * Ignore error return codes because if it was already disabled via
10376 * hardware settings this will fail
10377 */
10378 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10379 (pf->hw.aq.fw_maj_ver < 4)) {
10380 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10381 i40e_aq_stop_lldp(hw, true, NULL);
10382 }
10383
41c445ff 10384 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10385 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10386 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10387 err = -EIO;
10388 goto err_mac_addr;
10389 }
10390 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10391 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10392 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10393 if (is_valid_ether_addr(hw->mac.port_addr))
10394 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10395#ifdef I40E_FCOE
10396 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10397 if (err)
10398 dev_info(&pdev->dev,
10399 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10400 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10401 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10402 hw->mac.san_addr);
10403 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10404 }
10405 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10406#endif /* I40E_FCOE */
41c445ff
JB		 10407
10408 pci_set_drvdata(pdev, pf);
10409 pci_save_state(pdev);
4e3b35b0
NP		 10410#ifdef CONFIG_I40E_DCB
10411 err = i40e_init_pf_dcb(pf);
10412 if (err) {
aebfc816 10413 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10414 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10415 /* Continue without DCB enabled */
4e3b35b0
NP		 10416 }
10417#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10418
10419 /* set up periodic task facility */
10420 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10421 pf->service_timer_period = HZ;
10422
10423 INIT_WORK(&pf->service_task, i40e_service_task);
10424 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10425 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10426
1d5109d1
SN		 10427 /* NVM bit on means WoL disabled for the port */
10428 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10429 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10430 pf->wol_en = false;
10431 else
10432 pf->wol_en = true;
8e2773ae
SN		 10433 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10434
41c445ff
JB		 10435 /* set up the main switch operations */
10436 i40e_determine_queue_usage(pf);
c1147280
JB		 10437 err = i40e_init_interrupt_scheme(pf);
10438 if (err)
10439 goto err_switch_setup;
41c445ff 10440
505682cd
MW		 10441 /* The number of VSIs reported by the FW is the minimum guaranteed
10442 * to us; HW supports far more and we share the remaining pool with
10443 * the other PFs. We allocate space for more than the guarantee with
10444 * the understanding that we might not get them all later.
41c445ff 10445 */
505682cd
MW		 10446 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10447 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10448 else
10449 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10450
10451 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10452 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10453 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10454 if (!pf->vsi) {
10455 err = -ENOMEM;
41c445ff 10456 goto err_switch_setup;
ed87ac09 10457 }
41c445ff 10458
fa11cb3d
ASJ		 10459#ifdef CONFIG_PCI_IOV
10460 /* prep for VF support */
10461 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10462 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10463 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10464 if (pci_num_vf(pdev))
10465 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10466 }
10467#endif
bc7d338f 10468 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10469 if (err) {
10470 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10471 goto err_vsis;
10472 }
58fc3267
HZ		 10473
10474 /* Make sure flow control is set according to current settings */
10475 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10476 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10477 dev_dbg(&pf->pdev->dev,
10478 "Set fc with err %s aq_err %s on get_phy_cap\n",
10479 i40e_stat_str(hw, err),
10480 i40e_aq_str(hw, hw->aq.asq_last_status));
10481 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10482 dev_dbg(&pf->pdev->dev,
10483 "Set fc with err %s aq_err %s on set_phy_config\n",
10484 i40e_stat_str(hw, err),
10485 i40e_aq_str(hw, hw->aq.asq_last_status));
10486 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10487 dev_dbg(&pf->pdev->dev,
10488 "Set fc with err %s aq_err %s on get_link_info\n",
10489 i40e_stat_str(hw, err),
10490 i40e_aq_str(hw, hw->aq.asq_last_status));
10491
8a9eb7d3 10492 /* if FDIR VSI was set up, start it now */
505682cd 10493 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10494 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10495 i40e_vsi_open(pf->vsi[i]);
10496 break;
10497 }
10498 }
41c445ff 10499
7e2453fe
JB		 10500 /* driver is only interested in link up/down and module qualification
10501 * reports from firmware
10502 */
10503 err = i40e_aq_set_phy_int_mask(&pf->hw,
10504 I40E_AQ_EVENT_LINK_UPDOWN |
10505 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10506 if (err)
f1c7e72e
SN		 10507 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10508 i40e_stat_str(&pf->hw, err),
10509 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10510
4f2f017c
ASJ		 10511 /* Reconfigure hardware for allowing smaller MSS in the case
10512 * of TSO, so that we avoid the MDD being fired and causing
10513 * a reset in the case of small MSS+TSO.
10514 */
10515 val = rd32(hw, I40E_REG_MSS);
10516 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10517 val &= ~I40E_REG_MSS_MIN_MASK;
10518 val |= I40E_64BYTE_MSS;
10519 wr32(hw, I40E_REG_MSS, val);
10520 }
10521
025b4a54
ASJ		 10522 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10523 (pf->hw.aq.fw_maj_ver < 4)) {
10524 msleep(75);
10525 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10526 if (err)
f1c7e72e
SN		 10527 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10528 i40e_stat_str(&pf->hw, err),
10529 i40e_aq_str(&pf->hw,
10530 pf->hw.aq.asq_last_status));
cafa2ee6 10531 }
41c445ff
JB		 10532 /* The main driver is (mostly) up and happy. We need to set this state
10533 * before setting up the misc vector or we get a race and the vector
10534 * ends up disabled forever.
10535 */
10536 clear_bit(__I40E_DOWN, &pf->state);
10537
10538 /* In case of MSIX we are going to setup the misc vector right here
10539 * to handle admin queue events etc. In case of legacy and MSI
10540 * the misc functionality and queue processing is combined in
10541 * the same vector and that gets setup at open.
10542 */
10543 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10544 err = i40e_setup_misc_vector(pf);
10545 if (err) {
10546 dev_info(&pdev->dev,
10547 "setup of misc vector failed: %d\n", err);
10548 goto err_vsis;
10549 }
10550 }
10551
df805f62 10552#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10553 /* prep for VF support */
10554 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10555 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10556 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10557 u32 val;
10558
10559 /* disable link interrupts for VFs */
10560 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10561 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10562 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10563 i40e_flush(hw);
4aeec010
MW		 10564
10565 if (pci_num_vf(pdev)) {
10566 dev_info(&pdev->dev,
10567 "Active VFs found, allocating resources.\n");
10568 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10569 if (err)
10570 dev_info(&pdev->dev,
10571 "Error %d allocating resources for existing VFs\n",
10572 err);
10573 }
41c445ff 10574 }
df805f62 10575#endif /* CONFIG_PCI_IOV */
41c445ff 10576
93cd765b
ASJ		 10577 pfs_found++;
10578
41c445ff
JB		 10579 i40e_dbg_pf_init(pf);
10580
10581 /* tell the firmware that we're starting */
44033fac 10582 i40e_send_version(pf);
41c445ff
JB		 10583
10584 /* since everything's happy, start the service_task timer */
10585 mod_timer(&pf->service_timer,
10586 round_jiffies(jiffies + pf->service_timer_period));
10587
38e00438
VD		 10588#ifdef I40E_FCOE
10589 /* create FCoE interface */
10590 i40e_fcoe_vsi_setup(pf);
10591
10592#endif
3fced535
ASJ		 10593#define PCI_SPEED_SIZE 8
10594#define PCI_WIDTH_SIZE 8
10595 /* Devices on the IOSF bus do not have this information
10596 * and will report PCI Gen 1 x 1 by default so don't bother
10597 * checking them.
10598 */
10599 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10600 char speed[PCI_SPEED_SIZE] = "Unknown";
10601 char width[PCI_WIDTH_SIZE] = "Unknown";
10602
10603 /* Get the negotiated link width and speed from PCI config
10604 * space
10605 */
10606 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10607 &link_status);
10608
10609 i40e_set_pci_config_data(hw, link_status);
10610
10611 switch (hw->bus.speed) {
10612 case i40e_bus_speed_8000:
10613 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10614 case i40e_bus_speed_5000:
10615 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10616 case i40e_bus_speed_2500:
10617 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10618 default:
10619 break;
10620 }
10621 switch (hw->bus.width) {
10622 case i40e_bus_width_pcie_x8:
10623 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10624 case i40e_bus_width_pcie_x4:
10625 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10626 case i40e_bus_width_pcie_x2:
10627 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10628 case i40e_bus_width_pcie_x1:
10629 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10630 default:
10631 break;
10632 }
10633
10634 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10635 speed, width);
10636
10637 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10638 hw->bus.speed < i40e_bus_speed_8000) {
10639 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10640 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10641 }
d4dfb81a
CS		 10642 }
10643
e827845c
CS		 10644 /* get the requested speeds from the fw */
10645 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10646 if (err)
8279e495
NP		 10647 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10648 i40e_stat_str(&pf->hw, err),
10649 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10650 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10651
fc72dbce
CS		 10652 /* get the supported phy types from the fw */
10653 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10654 if (err)
10655 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10656 i40e_stat_str(&pf->hw, err),
10657 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10658 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10659
e7358f54
ASJ		 10660 /* Add a filter to drop all Flow control frames from any VSI from being
10661 * transmitted. By doing so we stop a malicious VF from sending out
10662 * PAUSE or PFC frames and potentially controlling traffic for other
10663 * PF/VF VSIs.
10664 * The FW can still send Flow control frames if enabled.
10665 */
10666 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
10667 pf->main_vsi_seid);
10668
0c22b3dd
JB		 10669 /* print a string summarizing features */
10670 i40e_print_features(pf);
10671
41c445ff
JB		 10672 return 0;
10673
10674 /* Unwind what we've done if something failed in the setup */
10675err_vsis:
10676 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10677 i40e_clear_interrupt_scheme(pf);
10678 kfree(pf->vsi);
04b03013
SN		 10679err_switch_setup:
10680 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10681 del_timer_sync(&pf->service_timer);
10682err_mac_addr:
10683err_configure_lan_hmc:
10684 (void)i40e_shutdown_lan_hmc(hw);
10685err_init_lan_hmc:
10686 kfree(pf->qp_pile);
41c445ff
JB		 10687err_sw_init:
10688err_adminq_setup:
10689 (void)i40e_shutdown_adminq(hw);
10690err_pf_reset:
10691 iounmap(hw->hw_addr);
10692err_ioremap:
10693 kfree(pf);
10694err_pf_alloc:
10695 pci_disable_pcie_error_reporting(pdev);
10696 pci_release_selected_regions(pdev,
10697 pci_select_bars(pdev, IORESOURCE_MEM));
10698err_pci_reg:
10699err_dma:
10700 pci_disable_device(pdev);
10701 return err;
10702}
10703
10704/**
10705 * i40e_remove - Device removal routine
10706 * @pdev: PCI device information struct
10707 *
10708 * i40e_remove is called by the PCI subsystem to alert the driver
10709 * that is should release a PCI device. This could be caused by a
10710 * Hot-Plug event, or because the driver is going to be removed from
10711 * memory.
10712 **/
10713static void i40e_remove(struct pci_dev *pdev)
10714{
10715 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 10716 struct i40e_hw *hw = &pf->hw;
41c445ff 10717 i40e_status ret_code;
41c445ff
JB		 10718 int i;
10719
10720 i40e_dbg_pf_exit(pf);
10721
beb0dff1
JK		 10722 i40e_ptp_stop(pf);
10723
bcab2db9
CW		 10724 /* Disable RSS in hw */
10725 wr32(hw, I40E_PFQF_HENA(0), 0);
10726 wr32(hw, I40E_PFQF_HENA(1), 0);
10727
41c445ff
JB		 10728 /* no more scheduling of any task */
10729 set_bit(__I40E_DOWN, &pf->state);
10730 del_timer_sync(&pf->service_timer);
10731 cancel_work_sync(&pf->service_task);
33c62b34 10732 i40e_fdir_teardown(pf);
41c445ff 10733
eb2d80bc
MW		 10734 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10735 i40e_free_vfs(pf);
10736 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10737 }
10738
41c445ff
JB		 10739 i40e_fdir_teardown(pf);
10740
10741 /* If there is a switch structure or any orphans, remove them.
10742 * This will leave only the PF's VSI remaining.
10743 */
10744 for (i = 0; i < I40E_MAX_VEB; i++) {
10745 if (!pf->veb[i])
10746 continue;
10747
10748 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10749 pf->veb[i]->uplink_seid == 0)
10750 i40e_switch_branch_release(pf->veb[i]);
10751 }
10752
10753 /* Now we can shutdown the PF's VSI, just before we kill
10754 * adminq and hmc.
10755 */
10756 if (pf->vsi[pf->lan_vsi])
10757 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10758
41c445ff 10759 /* shutdown and destroy the HMC */
60442dea
SN		 10760 if (pf->hw.hmc.hmc_obj) {
10761 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10762 if (ret_code)
10763 dev_warn(&pdev->dev,
10764 "Failed to destroy the HMC resources: %d\n",
10765 ret_code);
10766 }
41c445ff
JB		 10767
10768 /* shutdown the adminq */
41c445ff
JB		 10769 ret_code = i40e_shutdown_adminq(&pf->hw);
10770 if (ret_code)
10771 dev_warn(&pdev->dev,
10772 "Failed to destroy the Admin Queue resources: %d\n",
10773 ret_code);
10774
10775 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10776 i40e_clear_interrupt_scheme(pf);
505682cd 10777 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10778 if (pf->vsi[i]) {
10779 i40e_vsi_clear_rings(pf->vsi[i]);
10780 i40e_vsi_clear(pf->vsi[i]);
10781 pf->vsi[i] = NULL;
10782 }
10783 }
10784
10785 for (i = 0; i < I40E_MAX_VEB; i++) {
10786 kfree(pf->veb[i]);
10787 pf->veb[i] = NULL;
10788 }
10789
10790 kfree(pf->qp_pile);
41c445ff
JB		 10791 kfree(pf->vsi);
10792
41c445ff
JB		 10793 iounmap(pf->hw.hw_addr);
10794 kfree(pf);
10795 pci_release_selected_regions(pdev,
10796 pci_select_bars(pdev, IORESOURCE_MEM));
10797
10798 pci_disable_pcie_error_reporting(pdev);
10799 pci_disable_device(pdev);
10800}
10801
10802/**
10803 * i40e_pci_error_detected - warning that something funky happened in PCI land
10804 * @pdev: PCI device information struct
10805 *
10806 * Called to warn that something happened and the error handling steps
10807 * are in progress. Allows the driver to quiesce things, be ready for
10808 * remediation.
10809 **/
10810static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10811 enum pci_channel_state error)
10812{
10813 struct i40e_pf *pf = pci_get_drvdata(pdev);
10814
10815 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10816
10817 /* shutdown all operations */
9007bccd
SN		 10818 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10819 rtnl_lock();
10820 i40e_prep_for_reset(pf);
10821 rtnl_unlock();
10822 }
41c445ff
JB		 10823
10824 /* Request a slot reset */
10825 return PCI_ERS_RESULT_NEED_RESET;
10826}
10827
10828/**
10829 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10830 * @pdev: PCI device information struct
10831 *
10832 * Called to find if the driver can work with the device now that
10833 * the pci slot has been reset. If a basic connection seems good
10834 * (registers are readable and have sane content) then return a
10835 * happy little PCI_ERS_RESULT_xxx.
10836 **/
10837static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10838{
10839 struct i40e_pf *pf = pci_get_drvdata(pdev);
10840 pci_ers_result_t result;
10841 int err;
10842 u32 reg;
10843
fb43201f 10844 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 10845 if (pci_enable_device_mem(pdev)) {
10846 dev_info(&pdev->dev,
10847 "Cannot re-enable PCI device after reset.\n");
10848 result = PCI_ERS_RESULT_DISCONNECT;
10849 } else {
10850 pci_set_master(pdev);
10851 pci_restore_state(pdev);
10852 pci_save_state(pdev);
10853 pci_wake_from_d3(pdev, false);
10854
10855 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10856 if (reg == 0)
10857 result = PCI_ERS_RESULT_RECOVERED;
10858 else
10859 result = PCI_ERS_RESULT_DISCONNECT;
10860 }
10861
10862 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10863 if (err) {
10864 dev_info(&pdev->dev,
10865 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10866 err);
10867 /* non-fatal, continue */
10868 }
10869
10870 return result;
10871}
10872
10873/**
10874 * i40e_pci_error_resume - restart operations after PCI error recovery
10875 * @pdev: PCI device information struct
10876 *
10877 * Called to allow the driver to bring things back up after PCI error
10878 * and/or reset recovery has finished.
10879 **/
10880static void i40e_pci_error_resume(struct pci_dev *pdev)
10881{
10882 struct i40e_pf *pf = pci_get_drvdata(pdev);
10883
fb43201f 10884 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10885 if (test_bit(__I40E_SUSPENDED, &pf->state))
10886 return;
10887
10888 rtnl_lock();
41c445ff 10889 i40e_handle_reset_warning(pf);
4c4935a9 10890 rtnl_unlock();
9007bccd
SN		 10891}
10892
10893/**
10894 * i40e_shutdown - PCI callback for shutting down
10895 * @pdev: PCI device information struct
10896 **/
10897static void i40e_shutdown(struct pci_dev *pdev)
10898{
10899 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10900 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10901
10902 set_bit(__I40E_SUSPENDED, &pf->state);
10903 set_bit(__I40E_DOWN, &pf->state);
10904 rtnl_lock();
10905 i40e_prep_for_reset(pf);
10906 rtnl_unlock();
10907
8e2773ae
SN		 10908 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10909 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10910
02b42498
CS		 10911 del_timer_sync(&pf->service_timer);
10912 cancel_work_sync(&pf->service_task);
10913 i40e_fdir_teardown(pf);
10914
10915 rtnl_lock();
10916 i40e_prep_for_reset(pf);
10917 rtnl_unlock();
10918
10919 wr32(hw, I40E_PFPM_APM,
10920 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10921 wr32(hw, I40E_PFPM_WUFC,
10922 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10923
e147758d
SN		 10924 i40e_clear_interrupt_scheme(pf);
10925
9007bccd 10926 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10927 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10928 pci_set_power_state(pdev, PCI_D3hot);
10929 }
10930}
10931
10932#ifdef CONFIG_PM
10933/**
10934 * i40e_suspend - PCI callback for moving to D3
10935 * @pdev: PCI device information struct
10936 **/
10937static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10938{
10939 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10940 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10941
10942 set_bit(__I40E_SUSPENDED, &pf->state);
10943 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10944
9007bccd
SN		 10945 rtnl_lock();
10946 i40e_prep_for_reset(pf);
10947 rtnl_unlock();
10948
8e2773ae
SN		 10949 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10950 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10951
10952 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10953 pci_set_power_state(pdev, PCI_D3hot);
10954
10955 return 0;
41c445ff
JB		 10956}
10957
9007bccd
SN		 10958/**
10959 * i40e_resume - PCI callback for waking up from D3
10960 * @pdev: PCI device information struct
10961 **/
10962static int i40e_resume(struct pci_dev *pdev)
10963{
10964 struct i40e_pf *pf = pci_get_drvdata(pdev);
10965 u32 err;
10966
10967 pci_set_power_state(pdev, PCI_D0);
10968 pci_restore_state(pdev);
10969 /* pci_restore_state() clears dev->state_saves, so
10970 * call pci_save_state() again to restore it.
10971 */
10972 pci_save_state(pdev);
10973
10974 err = pci_enable_device_mem(pdev);
10975 if (err) {
fb43201f 10976 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 10977 return err;
10978 }
10979 pci_set_master(pdev);
10980
10981 /* no wakeup events while running */
10982 pci_wake_from_d3(pdev, false);
10983
10984 /* handling the reset will rebuild the device state */
10985 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10986 clear_bit(__I40E_DOWN, &pf->state);
10987 rtnl_lock();
10988 i40e_reset_and_rebuild(pf, false);
10989 rtnl_unlock();
10990 }
10991
10992 return 0;
10993}
10994
10995#endif
41c445ff
JB		 10996static const struct pci_error_handlers i40e_err_handler = {
10997 .error_detected = i40e_pci_error_detected,
10998 .slot_reset = i40e_pci_error_slot_reset,
10999 .resume = i40e_pci_error_resume,
11000};
11001
11002static struct pci_driver i40e_driver = {
11003 .name = i40e_driver_name,
11004 .id_table = i40e_pci_tbl,
11005 .probe = i40e_probe,
11006 .remove = i40e_remove,
9007bccd
SN		 11007#ifdef CONFIG_PM
11008 .suspend = i40e_suspend,
11009 .resume = i40e_resume,
11010#endif
11011 .shutdown = i40e_shutdown,
41c445ff
JB		 11012 .err_handler = &i40e_err_handler,
11013 .sriov_configure = i40e_pci_sriov_configure,
11014};
11015
11016/**
11017 * i40e_init_module - Driver registration routine
11018 *
11019 * i40e_init_module is the first routine called when the driver is
11020 * loaded. All it does is register with the PCI subsystem.
11021 **/
11022static int __init i40e_init_module(void)
11023{
11024 pr_info("%s: %s - version %s\n", i40e_driver_name,
11025 i40e_driver_string, i40e_driver_version_str);
11026 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11027
41c445ff
JB		 11028 i40e_dbg_init();
11029 return pci_register_driver(&i40e_driver);
11030}
11031module_init(i40e_init_module);
11032
11033/**
11034 * i40e_exit_module - Driver exit cleanup routine
11035 *
11036 * i40e_exit_module is called just before the driver is removed
11037 * from memory.
11038 **/
11039static void __exit i40e_exit_module(void)
11040{
11041 pci_unregister_driver(&i40e_driver);
11042 i40e_dbg_exit();
11043}
11044module_exit(i40e_exit_module);
Linux kernel - Deliverables
This page took 2.281114 seconds and 5 git commands to generate.