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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-next
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
d1d39516 42#define DRV_VERSION_BUILD 34
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 85 /* required last entry */
86 {0, }
87};
88MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
89
90#define I40E_MAX_VF_COUNT 128
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
96MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100/**
101 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
102 * @hw: pointer to the HW structure
103 * @mem: ptr to mem struct to fill out
104 * @size: size of memory requested
105 * @alignment: what to align the allocation to
106 **/
107int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
108 u64 size, u32 alignment)
109{
110 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
111
112 mem->size = ALIGN(size, alignment);
113 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
114 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 115 if (!mem->va)
116 return -ENOMEM;
41c445ff 117
93bc73b8 118 return 0;
41c445ff
JB		 119}
120
121/**
122 * i40e_free_dma_mem_d - OS specific memory free for shared code
123 * @hw: pointer to the HW structure
124 * @mem: ptr to mem struct to free
125 **/
126int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
127{
128 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
129
130 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
131 mem->va = NULL;
132 mem->pa = 0;
133 mem->size = 0;
134
135 return 0;
136}
137
138/**
139 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to fill out
142 * @size: size of memory requested
143 **/
144int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
145 u32 size)
146{
147 mem->size = size;
148 mem->va = kzalloc(size, GFP_KERNEL);
149
93bc73b8
JB		 150 if (!mem->va)
151 return -ENOMEM;
41c445ff 152
93bc73b8 153 return 0;
41c445ff
JB		 154}
155
156/**
157 * i40e_free_virt_mem_d - OS specific memory free for shared code
158 * @hw: pointer to the HW structure
159 * @mem: ptr to mem struct to free
160 **/
161int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
162{
163 /* it's ok to kfree a NULL pointer */
164 kfree(mem->va);
165 mem->va = NULL;
166 mem->size = 0;
167
168 return 0;
169}
170
171/**
172 * i40e_get_lump - find a lump of free generic resource
173 * @pf: board private structure
174 * @pile: the pile of resource to search
175 * @needed: the number of items needed
176 * @id: an owner id to stick on the items assigned
177 *
178 * Returns the base item index of the lump, or negative for error
179 *
180 * The search_hint trick and lack of advanced fit-finding only work
181 * because we're highly likely to have all the same size lump requests.
182 * Linear search time and any fragmentation should be minimal.
183 **/
184static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
185 u16 needed, u16 id)
186{
187 int ret = -ENOMEM;
ddf434ac 188 int i, j;
41c445ff
JB		 189
190 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
191 dev_info(&pf->pdev->dev,
192 "param err: pile=%p needed=%d id=0x%04x\n",
193 pile, needed, id);
194 return -EINVAL;
195 }
196
197 /* start the linear search with an imperfect hint */
198 i = pile->search_hint;
ddf434ac 199 while (i < pile->num_entries) {
41c445ff
JB		 200 /* skip already allocated entries */
201 if (pile->list[i] & I40E_PILE_VALID_BIT) {
202 i++;
203 continue;
204 }
205
206 /* do we have enough in this lump? */
207 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
208 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
209 break;
210 }
211
212 if (j == needed) {
213 /* there was enough, so assign it to the requestor */
214 for (j = 0; j < needed; j++)
215 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
216 ret = i;
217 pile->search_hint = i + j;
ddf434ac 218 break;
41c445ff 219 }
6995b36c
JB		 220
221 /* not enough, so skip over it and continue looking */
222 i += j;
41c445ff
JB		 223 }
224
225 return ret;
226}
227
228/**
229 * i40e_put_lump - return a lump of generic resource
230 * @pile: the pile of resource to search
231 * @index: the base item index
232 * @id: the owner id of the items assigned
233 *
234 * Returns the count of items in the lump
235 **/
236static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
237{
238 int valid_id = (id | I40E_PILE_VALID_BIT);
239 int count = 0;
240 int i;
241
242 if (!pile || index >= pile->num_entries)
243 return -EINVAL;
244
245 for (i = index;
246 i < pile->num_entries && pile->list[i] == valid_id;
247 i++) {
248 pile->list[i] = 0;
249 count++;
250 }
251
252 if (count && index < pile->search_hint)
253 pile->search_hint = index;
254
255 return count;
256}
257
fdf0e0bf
ASJ		 258/**
259 * i40e_find_vsi_from_id - searches for the vsi with the given id
260 * @pf - the pf structure to search for the vsi
261 * @id - id of the vsi it is searching for
262 **/
263struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
264{
265 int i;
266
267 for (i = 0; i < pf->num_alloc_vsi; i++)
268 if (pf->vsi[i] && (pf->vsi[i]->id == id))
269 return pf->vsi[i];
270
271 return NULL;
272}
273
41c445ff
JB		 274/**
275 * i40e_service_event_schedule - Schedule the service task to wake up
276 * @pf: board private structure
277 *
278 * If not already scheduled, this puts the task into the work queue
279 **/
280static void i40e_service_event_schedule(struct i40e_pf *pf)
281{
282 if (!test_bit(__I40E_DOWN, &pf->state) &&
283 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
284 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
285 schedule_work(&pf->service_task);
286}
287
288/**
289 * i40e_tx_timeout - Respond to a Tx Hang
290 * @netdev: network interface device structure
291 *
292 * If any port has noticed a Tx timeout, it is likely that the whole
293 * device is munged, not just the one netdev port, so go for the full
294 * reset.
295 **/
38e00438
VD		 296#ifdef I40E_FCOE
297void i40e_tx_timeout(struct net_device *netdev)
298#else
41c445ff 299static void i40e_tx_timeout(struct net_device *netdev)
38e00438 300#endif
41c445ff
JB		 301{
302 struct i40e_netdev_priv *np = netdev_priv(netdev);
303 struct i40e_vsi *vsi = np->vsi;
304 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 305 struct i40e_ring *tx_ring = NULL;
306 unsigned int i, hung_queue = 0;
307 u32 head, val;
41c445ff
JB		 308
309 pf->tx_timeout_count++;
310
b03a8c1f
KP		 311 /* find the stopped queue the same way the stack does */
312 for (i = 0; i < netdev->num_tx_queues; i++) {
313 struct netdev_queue *q;
314 unsigned long trans_start;
315
316 q = netdev_get_tx_queue(netdev, i);
317 trans_start = q->trans_start ? : netdev->trans_start;
318 if (netif_xmit_stopped(q) &&
319 time_after(jiffies,
320 (trans_start + netdev->watchdog_timeo))) {
321 hung_queue = i;
322 break;
323 }
324 }
325
326 if (i == netdev->num_tx_queues) {
327 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
328 } else {
329 /* now that we have an index, find the tx_ring struct */
330 for (i = 0; i < vsi->num_queue_pairs; i++) {
331 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
332 if (hung_queue ==
333 vsi->tx_rings[i]->queue_index) {
334 tx_ring = vsi->tx_rings[i];
335 break;
336 }
337 }
338 }
339 }
340
41c445ff 341 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 342 pf->tx_timeout_recovery_level = 1; /* reset after some time */
343 else if (time_before(jiffies,
344 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
345 return; /* don't do any new action before the next timeout */
346
347 if (tx_ring) {
348 head = i40e_get_head(tx_ring);
349 /* Read interrupt register */
350 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
351 val = rd32(&pf->hw,
352 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
353 tx_ring->vsi->base_vector - 1));
354 else
355 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
356
357 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
358 vsi->seid, hung_queue, tx_ring->next_to_clean,
359 head, tx_ring->next_to_use,
360 readl(tx_ring->tail), val);
361 }
362
41c445ff 363 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 364 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
365 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 366
367 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 368 case 1:
369 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
370 break;
371 case 2:
372 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
373 break;
374 case 3:
375 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
376 break;
377 default:
378 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 379 break;
380 }
b03a8c1f 381
41c445ff
JB		 382 i40e_service_event_schedule(pf);
383 pf->tx_timeout_recovery_level++;
384}
385
386/**
387 * i40e_release_rx_desc - Store the new tail and head values
388 * @rx_ring: ring to bump
389 * @val: new head index
390 **/
391static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
392{
393 rx_ring->next_to_use = val;
394
395 /* Force memory writes to complete before letting h/w
396 * know there are new descriptors to fetch. (Only
397 * applicable for weak-ordered memory model archs,
398 * such as IA-64).
399 */
400 wmb();
401 writel(val, rx_ring->tail);
402}
403
404/**
405 * i40e_get_vsi_stats_struct - Get System Network Statistics
406 * @vsi: the VSI we care about
407 *
408 * Returns the address of the device statistics structure.
409 * The statistics are actually updated from the service task.
410 **/
411struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
412{
413 return &vsi->net_stats;
414}
415
416/**
417 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
418 * @netdev: network interface device structure
419 *
420 * Returns the address of the device statistics structure.
421 * The statistics are actually updated from the service task.
422 **/
38e00438
VD		 423#ifdef I40E_FCOE
424struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
425 struct net_device *netdev,
426 struct rtnl_link_stats64 *stats)
427#else
41c445ff
JB		 428static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
429 struct net_device *netdev,
980e9b11 430 struct rtnl_link_stats64 *stats)
38e00438 431#endif
41c445ff
JB		 432{
433 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 434 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 435 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 436 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
437 int i;
438
bc7d338f
ASJ		 439 if (test_bit(__I40E_DOWN, &vsi->state))
440 return stats;
441
3c325ced
JB		 442 if (!vsi->tx_rings)
443 return stats;
444
980e9b11
AD		 445 rcu_read_lock();
446 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 447 u64 bytes, packets;
448 unsigned int start;
449
450 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
451 if (!tx_ring)
452 continue;
453
454 do {
57a7744e 455 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 456 packets = tx_ring->stats.packets;
457 bytes = tx_ring->stats.bytes;
57a7744e 458 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 459
460 stats->tx_packets += packets;
461 stats->tx_bytes += bytes;
462 rx_ring = &tx_ring[1];
463
464 do {
57a7744e 465 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 466 packets = rx_ring->stats.packets;
467 bytes = rx_ring->stats.bytes;
57a7744e 468 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 469
980e9b11
AD		 470 stats->rx_packets += packets;
471 stats->rx_bytes += bytes;
472 }
473 rcu_read_unlock();
474
a5282f44 475 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 476 stats->multicast = vsi_stats->multicast;
477 stats->tx_errors = vsi_stats->tx_errors;
478 stats->tx_dropped = vsi_stats->tx_dropped;
479 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 480 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 481 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
482 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 483
980e9b11 484 return stats;
41c445ff
JB		 485}
486
487/**
488 * i40e_vsi_reset_stats - Resets all stats of the given vsi
489 * @vsi: the VSI to have its stats reset
490 **/
491void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
492{
493 struct rtnl_link_stats64 *ns;
494 int i;
495
496 if (!vsi)
497 return;
498
499 ns = i40e_get_vsi_stats_struct(vsi);
500 memset(ns, 0, sizeof(*ns));
501 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
502 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
503 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 504 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 505 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 506 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 507 sizeof(vsi->rx_rings[i]->stats));
6995b36c 508 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 510 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 511 sizeof(vsi->tx_rings[i]->stats));
512 memset(&vsi->tx_rings[i]->tx_stats, 0,
513 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 514 }
8e9dca53 515 }
41c445ff
JB		 516 vsi->stat_offsets_loaded = false;
517}
518
519/**
b40c82e6 520 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 521 * @pf: the PF to be reset
522 **/
523void i40e_pf_reset_stats(struct i40e_pf *pf)
524{
e91fdf76
SN		 525 int i;
526
41c445ff
JB		 527 memset(&pf->stats, 0, sizeof(pf->stats));
528 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
529 pf->stat_offsets_loaded = false;
e91fdf76
SN		 530
531 for (i = 0; i < I40E_MAX_VEB; i++) {
532 if (pf->veb[i]) {
533 memset(&pf->veb[i]->stats, 0,
534 sizeof(pf->veb[i]->stats));
535 memset(&pf->veb[i]->stats_offsets, 0,
536 sizeof(pf->veb[i]->stats_offsets));
537 pf->veb[i]->stat_offsets_loaded = false;
538 }
539 }
41c445ff
JB		 540}
541
542/**
543 * i40e_stat_update48 - read and update a 48 bit stat from the chip
544 * @hw: ptr to the hardware info
545 * @hireg: the high 32 bit reg to read
546 * @loreg: the low 32 bit reg to read
547 * @offset_loaded: has the initial offset been loaded yet
548 * @offset: ptr to current offset value
549 * @stat: ptr to the stat
550 *
551 * Since the device stats are not reset at PFReset, they likely will not
552 * be zeroed when the driver starts. We'll save the first values read
553 * and use them as offsets to be subtracted from the raw values in order
554 * to report stats that count from zero. In the process, we also manage
555 * the potential roll-over.
556 **/
557static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
558 bool offset_loaded, u64 *offset, u64 *stat)
559{
560 u64 new_data;
561
ab60085e 562 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 563 new_data = rd32(hw, loreg);
564 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
565 } else {
566 new_data = rd64(hw, loreg);
567 }
568 if (!offset_loaded)
569 *offset = new_data;
570 if (likely(new_data >= *offset))
571 *stat = new_data - *offset;
572 else
41a1d04b 573 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 574 *stat &= 0xFFFFFFFFFFFFULL;
575}
576
577/**
578 * i40e_stat_update32 - read and update a 32 bit stat from the chip
579 * @hw: ptr to the hardware info
580 * @reg: the hw reg to read
581 * @offset_loaded: has the initial offset been loaded yet
582 * @offset: ptr to current offset value
583 * @stat: ptr to the stat
584 **/
585static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
586 bool offset_loaded, u64 *offset, u64 *stat)
587{
588 u32 new_data;
589
590 new_data = rd32(hw, reg);
591 if (!offset_loaded)
592 *offset = new_data;
593 if (likely(new_data >= *offset))
594 *stat = (u32)(new_data - *offset);
595 else
41a1d04b 596 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 597}
598
599/**
600 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
601 * @vsi: the VSI to be updated
602 **/
603void i40e_update_eth_stats(struct i40e_vsi *vsi)
604{
605 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
606 struct i40e_pf *pf = vsi->back;
607 struct i40e_hw *hw = &pf->hw;
608 struct i40e_eth_stats *oes;
609 struct i40e_eth_stats *es; /* device's eth stats */
610
611 es = &vsi->eth_stats;
612 oes = &vsi->eth_stats_offsets;
613
614 /* Gather up the stats that the hw collects */
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
618 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
619 vsi->stat_offsets_loaded,
620 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 621 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
622 vsi->stat_offsets_loaded,
623 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
624 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 627
628 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
629 I40E_GLV_GORCL(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->rx_bytes, &es->rx_bytes);
632 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
633 I40E_GLV_UPRCL(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_unicast, &es->rx_unicast);
636 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
637 I40E_GLV_MPRCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->rx_multicast, &es->rx_multicast);
640 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
641 I40E_GLV_BPRCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->rx_broadcast, &es->rx_broadcast);
644
645 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
646 I40E_GLV_GOTCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->tx_bytes, &es->tx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
650 I40E_GLV_UPTCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->tx_unicast, &es->tx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
654 I40E_GLV_MPTCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->tx_multicast, &es->tx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
658 I40E_GLV_BPTCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->tx_broadcast, &es->tx_broadcast);
661 vsi->stat_offsets_loaded = true;
662}
663
664/**
665 * i40e_update_veb_stats - Update Switch component statistics
666 * @veb: the VEB being updated
667 **/
668static void i40e_update_veb_stats(struct i40e_veb *veb)
669{
670 struct i40e_pf *pf = veb->pf;
671 struct i40e_hw *hw = &pf->hw;
672 struct i40e_eth_stats *oes;
673 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 674 struct i40e_veb_tc_stats *veb_oes;
675 struct i40e_veb_tc_stats *veb_es;
676 int i, idx = 0;
41c445ff
JB		 677
678 idx = veb->stats_idx;
679 es = &veb->stats;
680 oes = &veb->stats_offsets;
fe860afb
NP		 681 veb_es = &veb->tc_stats;
682 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 683
684 /* Gather up the stats that the hw collects */
685 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
686 veb->stat_offsets_loaded,
687 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 688 if (hw->revision_id > 0)
689 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_unknown_protocol,
692 &es->rx_unknown_protocol);
41c445ff
JB		 693 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_bytes, &es->rx_bytes);
696 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->rx_unicast, &es->rx_unicast);
699 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->rx_multicast, &es->rx_multicast);
702 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->rx_broadcast, &es->rx_broadcast);
705
706 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_bytes, &es->tx_bytes);
709 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->tx_unicast, &es->tx_unicast);
712 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->tx_multicast, &es->tx_multicast);
715 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
716 veb->stat_offsets_loaded,
717 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 718 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
719 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
720 I40E_GLVEBTC_RPCL(i, idx),
721 veb->stat_offsets_loaded,
722 &veb_oes->tc_rx_packets[i],
723 &veb_es->tc_rx_packets[i]);
724 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
725 I40E_GLVEBTC_RBCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_rx_bytes[i],
728 &veb_es->tc_rx_bytes[i]);
729 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
730 I40E_GLVEBTC_TPCL(i, idx),
731 veb->stat_offsets_loaded,
732 &veb_oes->tc_tx_packets[i],
733 &veb_es->tc_tx_packets[i]);
734 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
735 I40E_GLVEBTC_TBCL(i, idx),
736 veb->stat_offsets_loaded,
737 &veb_oes->tc_tx_bytes[i],
738 &veb_es->tc_tx_bytes[i]);
739 }
41c445ff
JB		 740 veb->stat_offsets_loaded = true;
741}
742
38e00438
VD		 743#ifdef I40E_FCOE
744/**
745 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
746 * @vsi: the VSI that is capable of doing FCoE
747 **/
748static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
749{
750 struct i40e_pf *pf = vsi->back;
751 struct i40e_hw *hw = &pf->hw;
752 struct i40e_fcoe_stats *ofs;
753 struct i40e_fcoe_stats *fs; /* device's eth stats */
754 int idx;
755
756 if (vsi->type != I40E_VSI_FCOE)
757 return;
758
759 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
760 fs = &vsi->fcoe_stats;
761 ofs = &vsi->fcoe_stats_offsets;
762
763 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
772 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
775 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
778 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
781 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->fcoe_last_error, &fs->fcoe_last_error);
784 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
785 vsi->fcoe_stat_offsets_loaded,
786 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
787
788 vsi->fcoe_stat_offsets_loaded = true;
789}
790
791#endif
41c445ff
JB		 792/**
793 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
794 * @pf: the corresponding PF
795 *
796 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
797 **/
798static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
799{
800 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
801 struct i40e_hw_port_stats *nsd = &pf->stats;
802 struct i40e_hw *hw = &pf->hw;
803 u64 xoff = 0;
41c445ff
JB		 804
805 if ((hw->fc.current_mode != I40E_FC_FULL) &&
806 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
807 return;
808
809 xoff = nsd->link_xoff_rx;
810 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
811 pf->stat_offsets_loaded,
812 &osd->link_xoff_rx, &nsd->link_xoff_rx);
813
814 /* No new LFC xoff rx */
815 if (!(nsd->link_xoff_rx - xoff))
816 return;
817
41c445ff
JB		 818}
819
820/**
821 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
822 * @pf: the corresponding PF
823 *
824 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
825 **/
826static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
827{
828 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
829 struct i40e_hw_port_stats *nsd = &pf->stats;
830 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
831 struct i40e_dcbx_config *dcb_cfg;
832 struct i40e_hw *hw = &pf->hw;
b03a8c1f 833 u16 i;
41c445ff
JB		 834 u8 tc;
835
836 dcb_cfg = &hw->local_dcbx_config;
837
e120814d
NP		 838 /* Collect Link XOFF stats when PFC is disabled */
839 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 840 i40e_update_link_xoff_rx(pf);
841 return;
842 }
843
844 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
845 u64 prio_xoff = nsd->priority_xoff_rx[i];
6995b36c 846
41c445ff
JB		 847 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
848 pf->stat_offsets_loaded,
849 &osd->priority_xoff_rx[i],
850 &nsd->priority_xoff_rx[i]);
851
852 /* No new PFC xoff rx */
853 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
854 continue;
855 /* Get the TC for given priority */
856 tc = dcb_cfg->etscfg.prioritytable[i];
857 xoff[tc] = true;
858 }
41c445ff
JB		 859}
860
861/**
7812fddc 862 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 863 * @vsi: the VSI to be updated
864 *
865 * There are a few instances where we store the same stat in a
866 * couple of different structs. This is partly because we have
867 * the netdev stats that need to be filled out, which is slightly
868 * different from the "eth_stats" defined by the chip and used in
7812fddc 869 * VF communications. We sort it out here.
41c445ff 870 **/
7812fddc 871static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 872{
873 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 874 struct rtnl_link_stats64 *ons;
875 struct rtnl_link_stats64 *ns; /* netdev stats */
876 struct i40e_eth_stats *oes;
877 struct i40e_eth_stats *es; /* device's eth stats */
878 u32 tx_restart, tx_busy;
bf00b376 879 struct i40e_ring *p;
41c445ff 880 u32 rx_page, rx_buf;
bf00b376
AA		 881 u64 bytes, packets;
882 unsigned int start;
2fc3d715 883 u64 tx_linearize;
41c445ff
JB		 884 u64 rx_p, rx_b;
885 u64 tx_p, tx_b;
41c445ff
JB		 886 u16 q;
887
888 if (test_bit(__I40E_DOWN, &vsi->state) ||
889 test_bit(__I40E_CONFIG_BUSY, &pf->state))
890 return;
891
892 ns = i40e_get_vsi_stats_struct(vsi);
893 ons = &vsi->net_stats_offsets;
894 es = &vsi->eth_stats;
895 oes = &vsi->eth_stats_offsets;
896
897 /* Gather up the netdev and vsi stats that the driver collects
898 * on the fly during packet processing
899 */
900 rx_b = rx_p = 0;
901 tx_b = tx_p = 0;
2fc3d715 902 tx_restart = tx_busy = tx_linearize = 0;
41c445ff
JB		 903 rx_page = 0;
904 rx_buf = 0;
980e9b11 905 rcu_read_lock();
41c445ff 906 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 907 /* locate Tx ring */
908 p = ACCESS_ONCE(vsi->tx_rings[q]);
909
910 do {
57a7744e 911 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 912 packets = p->stats.packets;
913 bytes = p->stats.bytes;
57a7744e 914 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 915 tx_b += bytes;
916 tx_p += packets;
917 tx_restart += p->tx_stats.restart_queue;
918 tx_busy += p->tx_stats.tx_busy;
2fc3d715 919 tx_linearize += p->tx_stats.tx_linearize;
41c445ff 920
980e9b11
AD		 921 /* Rx queue is part of the same block as Tx queue */
922 p = &p[1];
923 do {
57a7744e 924 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 925 packets = p->stats.packets;
926 bytes = p->stats.bytes;
57a7744e 927 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 928 rx_b += bytes;
929 rx_p += packets;
420136cc
MW		 930 rx_buf += p->rx_stats.alloc_buff_failed;
931 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 932 }
980e9b11 933 rcu_read_unlock();
41c445ff
JB		 934 vsi->tx_restart = tx_restart;
935 vsi->tx_busy = tx_busy;
2fc3d715 936 vsi->tx_linearize = tx_linearize;
41c445ff
JB		 937 vsi->rx_page_failed = rx_page;
938 vsi->rx_buf_failed = rx_buf;
939
940 ns->rx_packets = rx_p;
941 ns->rx_bytes = rx_b;
942 ns->tx_packets = tx_p;
943 ns->tx_bytes = tx_b;
944
41c445ff 945 /* update netdev stats from eth stats */
7812fddc 946 i40e_update_eth_stats(vsi);
41c445ff
JB		 947 ons->tx_errors = oes->tx_errors;
948 ns->tx_errors = es->tx_errors;
949 ons->multicast = oes->rx_multicast;
950 ns->multicast = es->rx_multicast;
41a9e55c
SN		 951 ons->rx_dropped = oes->rx_discards;
952 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 953 ons->tx_dropped = oes->tx_discards;
954 ns->tx_dropped = es->tx_discards;
955
7812fddc 956 /* pull in a couple PF stats if this is the main vsi */
41c445ff 957 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 958 ns->rx_crc_errors = pf->stats.crc_errors;
959 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
960 ns->rx_length_errors = pf->stats.rx_length_errors;
961 }
962}
41c445ff 963
7812fddc 964/**
b40c82e6 965 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 966 * @pf: the PF to be updated
967 **/
968static void i40e_update_pf_stats(struct i40e_pf *pf)
969{
970 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
971 struct i40e_hw_port_stats *nsd = &pf->stats;
972 struct i40e_hw *hw = &pf->hw;
973 u32 val;
974 int i;
41c445ff 975
7812fddc
SN		 976 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
977 I40E_GLPRT_GORCL(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
980 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
981 I40E_GLPRT_GOTCL(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
984 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->eth.rx_discards,
987 &nsd->eth.rx_discards);
532d283d
SN		 988 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
989 I40E_GLPRT_UPRCL(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->eth.rx_unicast,
992 &nsd->eth.rx_unicast);
7812fddc
SN		 993 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
994 I40E_GLPRT_MPRCL(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->eth.rx_multicast,
997 &nsd->eth.rx_multicast);
532d283d
SN		 998 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
999 I40E_GLPRT_BPRCL(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->eth.rx_broadcast,
1002 &nsd->eth.rx_broadcast);
1003 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1004 I40E_GLPRT_UPTCL(hw->port),
1005 pf->stat_offsets_loaded,
1006 &osd->eth.tx_unicast,
1007 &nsd->eth.tx_unicast);
1008 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1009 I40E_GLPRT_MPTCL(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->eth.tx_multicast,
1012 &nsd->eth.tx_multicast);
1013 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1014 I40E_GLPRT_BPTCL(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->eth.tx_broadcast,
1017 &nsd->eth.tx_broadcast);
41c445ff 1018
7812fddc
SN		 1019 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->tx_dropped_link_down,
1022 &nsd->tx_dropped_link_down);
41c445ff 1023
7812fddc
SN		 1024 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1027
7812fddc
SN		 1028 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1031
7812fddc
SN		 1032 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->mac_local_faults,
1035 &nsd->mac_local_faults);
1036 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->mac_remote_faults,
1039 &nsd->mac_remote_faults);
41c445ff 1040
7812fddc
SN		 1041 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_length_errors,
1044 &nsd->rx_length_errors);
41c445ff 1045
7812fddc
SN		 1046 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->link_xon_rx, &nsd->link_xon_rx);
1049 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->link_xon_tx, &nsd->link_xon_tx);
1052 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1053 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1056
7812fddc
SN		 1057 for (i = 0; i < 8; i++) {
1058 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1059 pf->stat_offsets_loaded,
7812fddc
SN		 1060 &osd->priority_xon_rx[i],
1061 &nsd->priority_xon_rx[i]);
1062 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1063 pf->stat_offsets_loaded,
7812fddc
SN		 1064 &osd->priority_xon_tx[i],
1065 &nsd->priority_xon_tx[i]);
1066 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1067 pf->stat_offsets_loaded,
7812fddc
SN		 1068 &osd->priority_xoff_tx[i],
1069 &nsd->priority_xoff_tx[i]);
1070 i40e_stat_update32(hw,
1071 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1072 pf->stat_offsets_loaded,
7812fddc
SN		 1073 &osd->priority_xon_2_xoff[i],
1074 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1075 }
1076
7812fddc
SN		 1077 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1078 I40E_GLPRT_PRC64L(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_size_64, &nsd->rx_size_64);
1081 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1082 I40E_GLPRT_PRC127L(hw->port),
1083 pf->stat_offsets_loaded,
1084 &osd->rx_size_127, &nsd->rx_size_127);
1085 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1086 I40E_GLPRT_PRC255L(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_size_255, &nsd->rx_size_255);
1089 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1090 I40E_GLPRT_PRC511L(hw->port),
1091 pf->stat_offsets_loaded,
1092 &osd->rx_size_511, &nsd->rx_size_511);
1093 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1094 I40E_GLPRT_PRC1023L(hw->port),
1095 pf->stat_offsets_loaded,
1096 &osd->rx_size_1023, &nsd->rx_size_1023);
1097 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1098 I40E_GLPRT_PRC1522L(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_size_1522, &nsd->rx_size_1522);
1101 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1102 I40E_GLPRT_PRC9522L(hw->port),
1103 pf->stat_offsets_loaded,
1104 &osd->rx_size_big, &nsd->rx_size_big);
1105
1106 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1107 I40E_GLPRT_PTC64L(hw->port),
1108 pf->stat_offsets_loaded,
1109 &osd->tx_size_64, &nsd->tx_size_64);
1110 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1111 I40E_GLPRT_PTC127L(hw->port),
1112 pf->stat_offsets_loaded,
1113 &osd->tx_size_127, &nsd->tx_size_127);
1114 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1115 I40E_GLPRT_PTC255L(hw->port),
1116 pf->stat_offsets_loaded,
1117 &osd->tx_size_255, &nsd->tx_size_255);
1118 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1119 I40E_GLPRT_PTC511L(hw->port),
1120 pf->stat_offsets_loaded,
1121 &osd->tx_size_511, &nsd->tx_size_511);
1122 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1123 I40E_GLPRT_PTC1023L(hw->port),
1124 pf->stat_offsets_loaded,
1125 &osd->tx_size_1023, &nsd->tx_size_1023);
1126 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1127 I40E_GLPRT_PTC1522L(hw->port),
1128 pf->stat_offsets_loaded,
1129 &osd->tx_size_1522, &nsd->tx_size_1522);
1130 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1131 I40E_GLPRT_PTC9522L(hw->port),
1132 pf->stat_offsets_loaded,
1133 &osd->tx_size_big, &nsd->tx_size_big);
1134
1135 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1136 pf->stat_offsets_loaded,
1137 &osd->rx_undersize, &nsd->rx_undersize);
1138 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1139 pf->stat_offsets_loaded,
1140 &osd->rx_fragments, &nsd->rx_fragments);
1141 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1142 pf->stat_offsets_loaded,
1143 &osd->rx_oversize, &nsd->rx_oversize);
1144 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1145 pf->stat_offsets_loaded,
1146 &osd->rx_jabber, &nsd->rx_jabber);
1147
433c47de 1148 /* FDIR stats */
0bf4b1b0
ASJ		 1149 i40e_stat_update32(hw,
1150 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1151 pf->stat_offsets_loaded,
1152 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1153 i40e_stat_update32(hw,
1154 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1155 pf->stat_offsets_loaded,
1156 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1157 i40e_stat_update32(hw,
1158 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1159 pf->stat_offsets_loaded,
1160 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1161
7812fddc
SN		 1162 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1163 nsd->tx_lpi_status =
1164 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1165 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1166 nsd->rx_lpi_status =
1167 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1168 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1169 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1170 pf->stat_offsets_loaded,
1171 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1172 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1173 pf->stat_offsets_loaded,
1174 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1175
d0389e51
ASJ		 1176 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1177 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1178 nsd->fd_sb_status = true;
1179 else
1180 nsd->fd_sb_status = false;
1181
1182 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1183 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1184 nsd->fd_atr_status = true;
1185 else
1186 nsd->fd_atr_status = false;
1187
41c445ff
JB		 1188 pf->stat_offsets_loaded = true;
1189}
1190
7812fddc
SN		 1191/**
1192 * i40e_update_stats - Update the various statistics counters.
1193 * @vsi: the VSI to be updated
1194 *
1195 * Update the various stats for this VSI and its related entities.
1196 **/
1197void i40e_update_stats(struct i40e_vsi *vsi)
1198{
1199 struct i40e_pf *pf = vsi->back;
1200
1201 if (vsi == pf->vsi[pf->lan_vsi])
1202 i40e_update_pf_stats(pf);
1203
1204 i40e_update_vsi_stats(vsi);
38e00438
VD		 1205#ifdef I40E_FCOE
1206 i40e_update_fcoe_stats(vsi);
1207#endif
7812fddc
SN		 1208}
1209
41c445ff
JB		 1210/**
1211 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1212 * @vsi: the VSI to be searched
1213 * @macaddr: the MAC address
1214 * @vlan: the vlan
b40c82e6 1215 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1216 * @is_netdev: make sure its a netdev filter, else doesn't matter
1217 *
1218 * Returns ptr to the filter object or NULL
1219 **/
1220static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1221 u8 *macaddr, s16 vlan,
1222 bool is_vf, bool is_netdev)
1223{
1224 struct i40e_mac_filter *f;
1225
1226 if (!vsi || !macaddr)
1227 return NULL;
1228
1229 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1230 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1231 (vlan == f->vlan) &&
1232 (!is_vf || f->is_vf) &&
1233 (!is_netdev || f->is_netdev))
1234 return f;
1235 }
1236 return NULL;
1237}
1238
1239/**
1240 * i40e_find_mac - Find a mac addr in the macvlan filters list
1241 * @vsi: the VSI to be searched
1242 * @macaddr: the MAC address we are searching for
b40c82e6 1243 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1244 * @is_netdev: make sure its a netdev filter, else doesn't matter
1245 *
1246 * Returns the first filter with the provided MAC address or NULL if
1247 * MAC address was not found
1248 **/
1249struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1250 bool is_vf, bool is_netdev)
1251{
1252 struct i40e_mac_filter *f;
1253
1254 if (!vsi || !macaddr)
1255 return NULL;
1256
1257 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1258 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1259 (!is_vf || f->is_vf) &&
1260 (!is_netdev || f->is_netdev))
1261 return f;
1262 }
1263 return NULL;
1264}
1265
1266/**
1267 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1268 * @vsi: the VSI to be searched
1269 *
1270 * Returns true if VSI is in vlan mode or false otherwise
1271 **/
1272bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1273{
1274 struct i40e_mac_filter *f;
1275
1276 /* Only -1 for all the filters denotes not in vlan mode
1277 * so we have to go through all the list in order to make sure
1278 */
1279 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1280 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1281 return true;
1282 }
1283
1284 return false;
1285}
1286
1287/**
1288 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1289 * @vsi: the VSI to be searched
1290 * @macaddr: the mac address to be filtered
b40c82e6 1291 * @is_vf: true if it is a VF
41c445ff
JB		 1292 * @is_netdev: true if it is a netdev
1293 *
1294 * Goes through all the macvlan filters and adds a
1295 * macvlan filter for each unique vlan that already exists
1296 *
1297 * Returns first filter found on success, else NULL
1298 **/
1299struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1300 bool is_vf, bool is_netdev)
1301{
1302 struct i40e_mac_filter *f;
1303
1304 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1305 if (vsi->info.pvid)
1306 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1307 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1308 is_vf, is_netdev)) {
1309 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1310 is_vf, is_netdev))
41c445ff
JB		 1311 return NULL;
1312 }
1313 }
1314
1315 return list_first_entry_or_null(&vsi->mac_filter_list,
1316 struct i40e_mac_filter, list);
1317}
1318
8c27d42e
GR		 1319/**
1320 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1321 * @vsi: the PF Main VSI - inappropriate for any other VSI
1322 * @macaddr: the MAC address
30650cc5
SN		 1323 *
1324 * Some older firmware configurations set up a default promiscuous VLAN
1325 * filter that needs to be removed.
8c27d42e 1326 **/
30650cc5 1327static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1328{
1329 struct i40e_aqc_remove_macvlan_element_data element;
1330 struct i40e_pf *pf = vsi->back;
f1c7e72e 1331 i40e_status ret;
8c27d42e
GR		 1332
1333 /* Only appropriate for the PF main VSI */
1334 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1335 return -EINVAL;
8c27d42e 1336
30650cc5 1337 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1338 ether_addr_copy(element.mac_addr, macaddr);
1339 element.vlan_tag = 0;
1340 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1341 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1342 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1343 if (ret)
30650cc5
SN		 1344 return -ENOENT;
1345
1346 return 0;
8c27d42e
GR		 1347}
1348
41c445ff
JB		 1349/**
1350 * i40e_add_filter - Add a mac/vlan filter to the VSI
1351 * @vsi: the VSI to be searched
1352 * @macaddr: the MAC address
1353 * @vlan: the vlan
b40c82e6 1354 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1355 * @is_netdev: make sure its a netdev filter, else doesn't matter
1356 *
1357 * Returns ptr to the filter object or NULL when no memory available.
1358 **/
1359struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1360 u8 *macaddr, s16 vlan,
1361 bool is_vf, bool is_netdev)
1362{
1363 struct i40e_mac_filter *f;
1364
1365 if (!vsi || !macaddr)
1366 return NULL;
1367
1368 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1369 if (!f) {
1370 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1371 if (!f)
1372 goto add_filter_out;
1373
9a173901 1374 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1375 f->vlan = vlan;
1376 f->changed = true;
1377
1378 INIT_LIST_HEAD(&f->list);
1379 list_add(&f->list, &vsi->mac_filter_list);
1380 }
1381
1382 /* increment counter and add a new flag if needed */
1383 if (is_vf) {
1384 if (!f->is_vf) {
1385 f->is_vf = true;
1386 f->counter++;
1387 }
1388 } else if (is_netdev) {
1389 if (!f->is_netdev) {
1390 f->is_netdev = true;
1391 f->counter++;
1392 }
1393 } else {
1394 f->counter++;
1395 }
1396
1397 /* changed tells sync_filters_subtask to
1398 * push the filter down to the firmware
1399 */
1400 if (f->changed) {
1401 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1402 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1403 }
1404
1405add_filter_out:
1406 return f;
1407}
1408
1409/**
1410 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1411 * @vsi: the VSI to be searched
1412 * @macaddr: the MAC address
1413 * @vlan: the vlan
b40c82e6 1414 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1415 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1416 **/
1417void i40e_del_filter(struct i40e_vsi *vsi,
1418 u8 *macaddr, s16 vlan,
1419 bool is_vf, bool is_netdev)
1420{
1421 struct i40e_mac_filter *f;
1422
1423 if (!vsi || !macaddr)
1424 return;
1425
1426 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1427 if (!f || f->counter == 0)
1428 return;
1429
1430 if (is_vf) {
1431 if (f->is_vf) {
1432 f->is_vf = false;
1433 f->counter--;
1434 }
1435 } else if (is_netdev) {
1436 if (f->is_netdev) {
1437 f->is_netdev = false;
1438 f->counter--;
1439 }
1440 } else {
b40c82e6 1441 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1442 int min_f = 0;
6995b36c 1443
41c445ff
JB		 1444 min_f += (f->is_vf ? 1 : 0);
1445 min_f += (f->is_netdev ? 1 : 0);
1446
1447 if (f->counter > min_f)
1448 f->counter--;
1449 }
1450
1451 /* counter == 0 tells sync_filters_subtask to
1452 * remove the filter from the firmware's list
1453 */
1454 if (f->counter == 0) {
1455 f->changed = true;
1456 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1457 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1458 }
1459}
1460
1461/**
1462 * i40e_set_mac - NDO callback to set mac address
1463 * @netdev: network interface device structure
1464 * @p: pointer to an address structure
1465 *
1466 * Returns 0 on success, negative on failure
1467 **/
38e00438
VD		 1468#ifdef I40E_FCOE
1469int i40e_set_mac(struct net_device *netdev, void *p)
1470#else
41c445ff 1471static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1472#endif
41c445ff
JB		 1473{
1474 struct i40e_netdev_priv *np = netdev_priv(netdev);
1475 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1476 struct i40e_pf *pf = vsi->back;
1477 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1478 struct sockaddr *addr = p;
1479 struct i40e_mac_filter *f;
1480
1481 if (!is_valid_ether_addr(addr->sa_data))
1482 return -EADDRNOTAVAIL;
1483
30650cc5
SN		 1484 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1485 netdev_info(netdev, "already using mac address %pM\n",
1486 addr->sa_data);
1487 return 0;
1488 }
41c445ff 1489
80f6428f
ASJ		 1490 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1491 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1492 return -EADDRNOTAVAIL;
1493
30650cc5
SN		 1494 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1495 netdev_info(netdev, "returning to hw mac address %pM\n",
1496 hw->mac.addr);
1497 else
1498 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1499
41c445ff
JB		 1500 if (vsi->type == I40E_VSI_MAIN) {
1501 i40e_status ret;
6995b36c 1502
41c445ff 1503 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1504 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1505 addr->sa_data, NULL);
1506 if (ret) {
1507 netdev_info(netdev,
1508 "Addr change for Main VSI failed: %d\n",
1509 ret);
1510 return -EADDRNOTAVAIL;
1511 }
41c445ff
JB		 1512 }
1513
30650cc5
SN		 1514 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1515 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1516
30650cc5
SN		 1517 memset(&element, 0, sizeof(element));
1518 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1519 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1520 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1521 } else {
6c8ad1ba
SN		 1522 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1523 false, false);
6c8ad1ba 1524 }
41c445ff 1525
30650cc5
SN		 1526 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1527 struct i40e_aqc_add_macvlan_element_data element;
1528
1529 memset(&element, 0, sizeof(element));
1530 ether_addr_copy(element.mac_addr, hw->mac.addr);
1531 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1532 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1533 } else {
1534 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1535 false, false);
1536 if (f)
1537 f->is_laa = true;
1538 }
1539
30e2561b 1540 i40e_sync_vsi_filters(vsi, false);
30650cc5 1541 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1542
1543 return 0;
1544}
1545
1546/**
1547 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1548 * @vsi: the VSI being setup
1549 * @ctxt: VSI context structure
1550 * @enabled_tc: Enabled TCs bitmap
1551 * @is_add: True if called before Add VSI
1552 *
1553 * Setup VSI queue mapping for enabled traffic classes.
1554 **/
38e00438
VD		 1555#ifdef I40E_FCOE
1556void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1557 struct i40e_vsi_context *ctxt,
1558 u8 enabled_tc,
1559 bool is_add)
1560#else
41c445ff
JB		 1561static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1562 struct i40e_vsi_context *ctxt,
1563 u8 enabled_tc,
1564 bool is_add)
38e00438 1565#endif
41c445ff
JB		 1566{
1567 struct i40e_pf *pf = vsi->back;
1568 u16 sections = 0;
1569 u8 netdev_tc = 0;
1570 u16 numtc = 0;
1571 u16 qcount;
1572 u8 offset;
1573 u16 qmap;
1574 int i;
4e3b35b0 1575 u16 num_tc_qps = 0;
41c445ff
JB		 1576
1577 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1578 offset = 0;
1579
1580 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1581 /* Find numtc from enabled TC bitmap */
1582 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1583 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1584 numtc++;
1585 }
1586 if (!numtc) {
1587 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1588 numtc = 1;
1589 }
1590 } else {
1591 /* At least TC0 is enabled in case of non-DCB case */
1592 numtc = 1;
1593 }
1594
1595 vsi->tc_config.numtc = numtc;
1596 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1597 /* Number of queues per enabled TC */
7f9ff476
AS		 1598 /* In MFP case we can have a much lower count of MSIx
1599 * vectors available and so we need to lower the used
1600 * q count.
1601 */
26cdc443
ASJ		 1602 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1603 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1604 else
1605 qcount = vsi->alloc_queue_pairs;
7f9ff476 1606 num_tc_qps = qcount / numtc;
e25d00b8 1607 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1608
1609 /* Setup queue offset/count for all TCs for given VSI */
1610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1611 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1612 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1613 /* TC is enabled */
41c445ff
JB		 1614 int pow, num_qps;
1615
41c445ff
JB		 1616 switch (vsi->type) {
1617 case I40E_VSI_MAIN:
4e3b35b0 1618 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1619 break;
38e00438
VD		 1620#ifdef I40E_FCOE
1621 case I40E_VSI_FCOE:
1622 qcount = num_tc_qps;
1623 break;
1624#endif
41c445ff
JB		 1625 case I40E_VSI_FDIR:
1626 case I40E_VSI_SRIOV:
1627 case I40E_VSI_VMDQ2:
1628 default:
4e3b35b0 1629 qcount = num_tc_qps;
41c445ff
JB		 1630 WARN_ON(i != 0);
1631 break;
1632 }
4e3b35b0
NP		 1633 vsi->tc_config.tc_info[i].qoffset = offset;
1634 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1635
1e200e4a 1636 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1637 num_qps = qcount;
41c445ff 1638 pow = 0;
41a1d04b 1639 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1640 pow++;
1641 num_qps >>= 1;
1642 }
1643
1644 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1645 qmap =
1646 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1647 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1648
4e3b35b0 1649 offset += qcount;
41c445ff
JB		 1650 } else {
1651 /* TC is not enabled so set the offset to
1652 * default queue and allocate one queue
1653 * for the given TC.
1654 */
1655 vsi->tc_config.tc_info[i].qoffset = 0;
1656 vsi->tc_config.tc_info[i].qcount = 1;
1657 vsi->tc_config.tc_info[i].netdev_tc = 0;
1658
1659 qmap = 0;
1660 }
1661 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1662 }
1663
1664 /* Set actual Tx/Rx queue pairs */
1665 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1666 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1667 if (vsi->req_queue_pairs > 0)
1668 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1669 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1670 vsi->num_queue_pairs = pf->num_lan_msix;
1671 }
41c445ff
JB		 1672
1673 /* Scheduler section valid can only be set for ADD VSI */
1674 if (is_add) {
1675 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1676
1677 ctxt->info.up_enable_bits = enabled_tc;
1678 }
1679 if (vsi->type == I40E_VSI_SRIOV) {
1680 ctxt->info.mapping_flags |=
1681 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1682 for (i = 0; i < vsi->num_queue_pairs; i++)
1683 ctxt->info.queue_mapping[i] =
1684 cpu_to_le16(vsi->base_queue + i);
1685 } else {
1686 ctxt->info.mapping_flags |=
1687 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1688 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1689 }
1690 ctxt->info.valid_sections |= cpu_to_le16(sections);
1691}
1692
1693/**
1694 * i40e_set_rx_mode - NDO callback to set the netdev filters
1695 * @netdev: network interface device structure
1696 **/
38e00438
VD		 1697#ifdef I40E_FCOE
1698void i40e_set_rx_mode(struct net_device *netdev)
1699#else
41c445ff 1700static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1701#endif
41c445ff
JB		 1702{
1703 struct i40e_netdev_priv *np = netdev_priv(netdev);
1704 struct i40e_mac_filter *f, *ftmp;
1705 struct i40e_vsi *vsi = np->vsi;
1706 struct netdev_hw_addr *uca;
1707 struct netdev_hw_addr *mca;
1708 struct netdev_hw_addr *ha;
1709
1710 /* add addr if not already in the filter list */
1711 netdev_for_each_uc_addr(uca, netdev) {
1712 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1713 if (i40e_is_vsi_in_vlan(vsi))
1714 i40e_put_mac_in_vlan(vsi, uca->addr,
1715 false, true);
1716 else
1717 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1718 false, true);
1719 }
1720 }
1721
1722 netdev_for_each_mc_addr(mca, netdev) {
1723 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1724 if (i40e_is_vsi_in_vlan(vsi))
1725 i40e_put_mac_in_vlan(vsi, mca->addr,
1726 false, true);
1727 else
1728 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1729 false, true);
1730 }
1731 }
1732
1733 /* remove filter if not in netdev list */
1734 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1735
1736 if (!f->is_netdev)
1737 continue;
1738
2f41f335
SN		 1739 netdev_for_each_mc_addr(mca, netdev)
1740 if (ether_addr_equal(mca->addr, f->macaddr))
1741 goto bottom_of_search_loop;
41c445ff 1742
2f41f335
SN		 1743 netdev_for_each_uc_addr(uca, netdev)
1744 if (ether_addr_equal(uca->addr, f->macaddr))
1745 goto bottom_of_search_loop;
1746
1747 for_each_dev_addr(netdev, ha)
1748 if (ether_addr_equal(ha->addr, f->macaddr))
1749 goto bottom_of_search_loop;
1750
1751 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1752 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1753
1754bottom_of_search_loop:
1755 continue;
41c445ff
JB		 1756 }
1757
1758 /* check for other flag changes */
1759 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1760 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1761 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1762 }
1763}
1764
1765/**
1766 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1767 * @vsi: ptr to the VSI
30e2561b 1768 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1769 *
1770 * Push any outstanding VSI filter changes through the AdminQ.
1771 *
1772 * Returns 0 or error value
1773 **/
30e2561b 1774int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff
JB		 1775{
1776 struct i40e_mac_filter *f, *ftmp;
1777 bool promisc_forced_on = false;
1778 bool add_happened = false;
1779 int filter_list_len = 0;
1780 u32 changed_flags = 0;
f1c7e72e 1781 i40e_status ret = 0;
41c445ff
JB		 1782 struct i40e_pf *pf;
1783 int num_add = 0;
1784 int num_del = 0;
f1c7e72e 1785 int aq_err = 0;
41c445ff
JB		 1786 u16 cmd_flags;
1787
1788 /* empty array typed pointers, kcalloc later */
1789 struct i40e_aqc_add_macvlan_element_data *add_list;
1790 struct i40e_aqc_remove_macvlan_element_data *del_list;
1791
1792 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1793 usleep_range(1000, 2000);
1794 pf = vsi->back;
1795
1796 if (vsi->netdev) {
1797 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1798 vsi->current_netdev_flags = vsi->netdev->flags;
1799 }
1800
1801 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1802 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1803
1804 filter_list_len = pf->hw.aq.asq_buf_size /
1805 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1806 del_list = kcalloc(filter_list_len,
1807 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1808 GFP_KERNEL);
1809 if (!del_list)
1810 return -ENOMEM;
1811
1812 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1813 if (!f->changed)
1814 continue;
1815
1816 if (f->counter != 0)
1817 continue;
1818 f->changed = false;
1819 cmd_flags = 0;
1820
1821 /* add to delete list */
9a173901 1822 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1823 del_list[num_del].vlan_tag =
1824 cpu_to_le16((u16)(f->vlan ==
1825 I40E_VLAN_ANY ? 0 : f->vlan));
1826
41c445ff
JB		 1827 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1828 del_list[num_del].flags = cmd_flags;
1829 num_del++;
1830
1831 /* unlink from filter list */
1832 list_del(&f->list);
1833 kfree(f);
1834
1835 /* flush a full buffer */
1836 if (num_del == filter_list_len) {
f1c7e72e
SN		 1837 ret = i40e_aq_remove_macvlan(&pf->hw,
1838 vsi->seid, del_list, num_del,
1839 NULL);
1840 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1841 num_del = 0;
1842 memset(del_list, 0, sizeof(*del_list));
1843
f1c7e72e 1844 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1845 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1846 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1847 i40e_stat_str(&pf->hw, ret),
1848 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1849 }
1850 }
1851 if (num_del) {
f1c7e72e 1852 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1853 del_list, num_del, NULL);
f1c7e72e 1854 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1855 num_del = 0;
1856
f1c7e72e 1857 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1859 "ignoring delete macvlan error, err %s aq_err %s\n",
1860 i40e_stat_str(&pf->hw, ret),
1861 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1862 }
1863
1864 kfree(del_list);
1865 del_list = NULL;
1866
1867 /* do all the adds now */
1868 filter_list_len = pf->hw.aq.asq_buf_size /
1869 sizeof(struct i40e_aqc_add_macvlan_element_data),
1870 add_list = kcalloc(filter_list_len,
1871 sizeof(struct i40e_aqc_add_macvlan_element_data),
1872 GFP_KERNEL);
1873 if (!add_list)
1874 return -ENOMEM;
1875
1876 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1877 if (!f->changed)
1878 continue;
1879
1880 if (f->counter == 0)
1881 continue;
1882 f->changed = false;
1883 add_happened = true;
1884 cmd_flags = 0;
1885
1886 /* add to add array */
9a173901 1887 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1888 add_list[num_add].vlan_tag =
1889 cpu_to_le16(
1890 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1891 add_list[num_add].queue_number = 0;
1892
1893 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1894 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1895 num_add++;
1896
1897 /* flush a full buffer */
1898 if (num_add == filter_list_len) {
f1c7e72e
SN		 1899 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1900 add_list, num_add,
1901 NULL);
1902 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1903 num_add = 0;
1904
f1c7e72e 1905 if (ret)
41c445ff
JB		 1906 break;
1907 memset(add_list, 0, sizeof(*add_list));
1908 }
1909 }
1910 if (num_add) {
f1c7e72e
SN		 1911 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1912 add_list, num_add, NULL);
1913 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1914 num_add = 0;
1915 }
1916 kfree(add_list);
1917 add_list = NULL;
1918
f1c7e72e 1919 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1920 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1921 "add filter failed, err %s aq_err %s\n",
1922 i40e_stat_str(&pf->hw, ret),
1923 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1924 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1925 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1926 &vsi->state)) {
1927 promisc_forced_on = true;
1928 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1929 &vsi->state);
1930 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1931 }
1932 }
1933 }
1934
1935 /* check for changes in promiscuous modes */
1936 if (changed_flags & IFF_ALLMULTI) {
1937 bool cur_multipromisc;
6995b36c 1938
41c445ff 1939 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1940 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1941 vsi->seid,
1942 cur_multipromisc,
1943 NULL);
1944 if (ret)
41c445ff 1945 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1946 "set multi promisc failed, err %s aq_err %s\n",
1947 i40e_stat_str(&pf->hw, ret),
1948 i40e_aq_str(&pf->hw,
1949 pf->hw.aq.asq_last_status));
41c445ff
JB		 1950 }
1951 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1952 bool cur_promisc;
6995b36c 1953
41c445ff
JB		 1954 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1955 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1956 &vsi->state));
92faef85
ASJ		 1957 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
1958 /* set defport ON for Main VSI instead of true promisc
1959 * this way we will get all unicast/multicast and VLAN
1960 * promisc behavior but will not get VF or VMDq traffic
1961 * replicated on the Main VSI.
1962 */
1963 if (pf->cur_promisc != cur_promisc) {
1964 pf->cur_promisc = cur_promisc;
30e2561b
AS		 1965 if (grab_rtnl)
1966 i40e_do_reset_safe(pf,
1967 BIT(__I40E_PF_RESET_REQUESTED));
1968 else
1969 i40e_do_reset(pf,
92faef85
ASJ		 1970 BIT(__I40E_PF_RESET_REQUESTED));
1971 }
1972 } else {
1973 ret = i40e_aq_set_vsi_unicast_promiscuous(
1974 &vsi->back->hw,
f1c7e72e
SN		 1975 vsi->seid,
1976 cur_promisc, NULL);
92faef85
ASJ		 1977 if (ret)
1978 dev_info(&pf->pdev->dev,
1979 "set unicast promisc failed, err %d, aq_err %d\n",
1980 ret, pf->hw.aq.asq_last_status);
1981 ret = i40e_aq_set_vsi_multicast_promiscuous(
1982 &vsi->back->hw,
1983 vsi->seid,
1984 cur_promisc, NULL);
1985 if (ret)
1986 dev_info(&pf->pdev->dev,
1987 "set multicast promisc failed, err %d, aq_err %d\n",
1988 ret, pf->hw.aq.asq_last_status);
1989 }
f1c7e72e
SN		 1990 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1991 vsi->seid,
1992 cur_promisc, NULL);
1993 if (ret)
1a10370a 1994 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1995 "set brdcast promisc failed, err %s, aq_err %s\n",
1996 i40e_stat_str(&pf->hw, ret),
1997 i40e_aq_str(&pf->hw,
1998 pf->hw.aq.asq_last_status));
41c445ff
JB		 1999 }
2000
2001 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2002 return 0;
2003}
2004
2005/**
2006 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2007 * @pf: board private structure
2008 **/
2009static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2010{
2011 int v;
2012
2013 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2014 return;
2015 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2016
505682cd 2017 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2018 if (pf->vsi[v] &&
2019 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2020 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2021 }
2022}
2023
2024/**
2025 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2026 * @netdev: network interface device structure
2027 * @new_mtu: new value for maximum frame size
2028 *
2029 * Returns 0 on success, negative on failure
2030 **/
2031static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2032{
2033 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2034 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2035 struct i40e_vsi *vsi = np->vsi;
2036
2037 /* MTU < 68 is an error and causes problems on some kernels */
2038 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2039 return -EINVAL;
2040
2041 netdev_info(netdev, "changing MTU from %d to %d\n",
2042 netdev->mtu, new_mtu);
2043 netdev->mtu = new_mtu;
2044 if (netif_running(netdev))
2045 i40e_vsi_reinit_locked(vsi);
2046
2047 return 0;
2048}
2049
beb0dff1
JK		 2050/**
2051 * i40e_ioctl - Access the hwtstamp interface
2052 * @netdev: network interface device structure
2053 * @ifr: interface request data
2054 * @cmd: ioctl command
2055 **/
2056int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2057{
2058 struct i40e_netdev_priv *np = netdev_priv(netdev);
2059 struct i40e_pf *pf = np->vsi->back;
2060
2061 switch (cmd) {
2062 case SIOCGHWTSTAMP:
2063 return i40e_ptp_get_ts_config(pf, ifr);
2064 case SIOCSHWTSTAMP:
2065 return i40e_ptp_set_ts_config(pf, ifr);
2066 default:
2067 return -EOPNOTSUPP;
2068 }
2069}
2070
41c445ff
JB		 2071/**
2072 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2073 * @vsi: the vsi being adjusted
2074 **/
2075void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2076{
2077 struct i40e_vsi_context ctxt;
2078 i40e_status ret;
2079
2080 if ((vsi->info.valid_sections &
2081 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2082 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2083 return; /* already enabled */
2084
2085 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2086 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2087 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2088
2089 ctxt.seid = vsi->seid;
1a2f6248 2090 ctxt.info = vsi->info;
41c445ff
JB		 2091 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2092 if (ret) {
2093 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2094 "update vlan stripping failed, err %s aq_err %s\n",
2095 i40e_stat_str(&vsi->back->hw, ret),
2096 i40e_aq_str(&vsi->back->hw,
2097 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2098 }
2099}
2100
2101/**
2102 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2103 * @vsi: the vsi being adjusted
2104 **/
2105void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2106{
2107 struct i40e_vsi_context ctxt;
2108 i40e_status ret;
2109
2110 if ((vsi->info.valid_sections &
2111 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2112 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2113 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2114 return; /* already disabled */
2115
2116 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2117 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2118 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2119
2120 ctxt.seid = vsi->seid;
1a2f6248 2121 ctxt.info = vsi->info;
41c445ff
JB		 2122 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2123 if (ret) {
2124 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2125 "update vlan stripping failed, err %s aq_err %s\n",
2126 i40e_stat_str(&vsi->back->hw, ret),
2127 i40e_aq_str(&vsi->back->hw,
2128 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2129 }
2130}
2131
2132/**
2133 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2134 * @netdev: network interface to be adjusted
2135 * @features: netdev features to test if VLAN offload is enabled or not
2136 **/
2137static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2138{
2139 struct i40e_netdev_priv *np = netdev_priv(netdev);
2140 struct i40e_vsi *vsi = np->vsi;
2141
2142 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2143 i40e_vlan_stripping_enable(vsi);
2144 else
2145 i40e_vlan_stripping_disable(vsi);
2146}
2147
2148/**
2149 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2150 * @vsi: the vsi being configured
2151 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2152 **/
2153int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2154{
2155 struct i40e_mac_filter *f, *add_f;
2156 bool is_netdev, is_vf;
41c445ff
JB		 2157
2158 is_vf = (vsi->type == I40E_VSI_SRIOV);
2159 is_netdev = !!(vsi->netdev);
2160
2161 if (is_netdev) {
2162 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2163 is_vf, is_netdev);
2164 if (!add_f) {
2165 dev_info(&vsi->back->pdev->dev,
2166 "Could not add vlan filter %d for %pM\n",
2167 vid, vsi->netdev->dev_addr);
2168 return -ENOMEM;
2169 }
2170 }
2171
2172 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2173 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2174 if (!add_f) {
2175 dev_info(&vsi->back->pdev->dev,
2176 "Could not add vlan filter %d for %pM\n",
2177 vid, f->macaddr);
2178 return -ENOMEM;
2179 }
2180 }
2181
41c445ff
JB		 2182 /* Now if we add a vlan tag, make sure to check if it is the first
2183 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2184 * with 0, so we now accept untagged and specified tagged traffic
2185 * (and not any taged and untagged)
2186 */
2187 if (vid > 0) {
2188 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2189 I40E_VLAN_ANY,
2190 is_vf, is_netdev)) {
2191 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2192 I40E_VLAN_ANY, is_vf, is_netdev);
2193 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2194 is_vf, is_netdev);
2195 if (!add_f) {
2196 dev_info(&vsi->back->pdev->dev,
2197 "Could not add filter 0 for %pM\n",
2198 vsi->netdev->dev_addr);
2199 return -ENOMEM;
2200 }
2201 }
8d82a7c5 2202 }
41c445ff 2203
8d82a7c5
GR		 2204 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2205 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2206 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2207 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2208 is_vf, is_netdev)) {
2209 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2210 is_vf, is_netdev);
2211 add_f = i40e_add_filter(vsi, f->macaddr,
2212 0, is_vf, is_netdev);
2213 if (!add_f) {
2214 dev_info(&vsi->back->pdev->dev,
2215 "Could not add filter 0 for %pM\n",
2216 f->macaddr);
2217 return -ENOMEM;
2218 }
2219 }
2220 }
41c445ff
JB		 2221 }
2222
80f6428f
ASJ		 2223 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2224 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2225 return 0;
2226
30e2561b 2227 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2228}
2229
2230/**
2231 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2232 * @vsi: the vsi being configured
2233 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2234 *
2235 * Return: 0 on success or negative otherwise
41c445ff
JB		 2236 **/
2237int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2238{
2239 struct net_device *netdev = vsi->netdev;
2240 struct i40e_mac_filter *f, *add_f;
2241 bool is_vf, is_netdev;
2242 int filter_count = 0;
41c445ff
JB		 2243
2244 is_vf = (vsi->type == I40E_VSI_SRIOV);
2245 is_netdev = !!(netdev);
2246
2247 if (is_netdev)
2248 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2249
2250 list_for_each_entry(f, &vsi->mac_filter_list, list)
2251 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2252
41c445ff
JB		 2253 /* go through all the filters for this VSI and if there is only
2254 * vid == 0 it means there are no other filters, so vid 0 must
2255 * be replaced with -1. This signifies that we should from now
2256 * on accept any traffic (with any tag present, or untagged)
2257 */
2258 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2259 if (is_netdev) {
2260 if (f->vlan &&
2261 ether_addr_equal(netdev->dev_addr, f->macaddr))
2262 filter_count++;
2263 }
2264
2265 if (f->vlan)
2266 filter_count++;
2267 }
2268
2269 if (!filter_count && is_netdev) {
2270 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2271 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2272 is_vf, is_netdev);
2273 if (!f) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Could not add filter %d for %pM\n",
2276 I40E_VLAN_ANY, netdev->dev_addr);
2277 return -ENOMEM;
2278 }
2279 }
2280
2281 if (!filter_count) {
2282 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2283 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2284 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2285 is_vf, is_netdev);
2286 if (!add_f) {
2287 dev_info(&vsi->back->pdev->dev,
2288 "Could not add filter %d for %pM\n",
2289 I40E_VLAN_ANY, f->macaddr);
2290 return -ENOMEM;
2291 }
2292 }
2293 }
2294
80f6428f
ASJ		 2295 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2296 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2297 return 0;
2298
30e2561b 2299 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2300}
2301
2302/**
2303 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2304 * @netdev: network interface to be adjusted
2305 * @vid: vlan id to be added
078b5876
JB		 2306 *
2307 * net_device_ops implementation for adding vlan ids
41c445ff 2308 **/
38e00438
VD		 2309#ifdef I40E_FCOE
2310int i40e_vlan_rx_add_vid(struct net_device *netdev,
2311 __always_unused __be16 proto, u16 vid)
2312#else
41c445ff
JB		 2313static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2314 __always_unused __be16 proto, u16 vid)
38e00438 2315#endif
41c445ff
JB		 2316{
2317 struct i40e_netdev_priv *np = netdev_priv(netdev);
2318 struct i40e_vsi *vsi = np->vsi;
078b5876 2319 int ret = 0;
41c445ff
JB		 2320
2321 if (vid > 4095)
078b5876
JB		 2322 return -EINVAL;
2323
2324 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2325
6982d429
ASJ		 2326 /* If the network stack called us with vid = 0 then
2327 * it is asking to receive priority tagged packets with
2328 * vlan id 0. Our HW receives them by default when configured
2329 * to receive untagged packets so there is no need to add an
2330 * extra filter for vlan 0 tagged packets.
41c445ff 2331 */
6982d429
ASJ		 2332 if (vid)
2333 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2334
078b5876
JB		 2335 if (!ret && (vid < VLAN_N_VID))
2336 set_bit(vid, vsi->active_vlans);
41c445ff 2337
078b5876 2338 return ret;
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2343 * @netdev: network interface to be adjusted
2344 * @vid: vlan id to be removed
078b5876 2345 *
fdfd943e 2346 * net_device_ops implementation for removing vlan ids
41c445ff 2347 **/
38e00438
VD		 2348#ifdef I40E_FCOE
2349int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2350 __always_unused __be16 proto, u16 vid)
2351#else
41c445ff
JB		 2352static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2353 __always_unused __be16 proto, u16 vid)
38e00438 2354#endif
41c445ff
JB		 2355{
2356 struct i40e_netdev_priv *np = netdev_priv(netdev);
2357 struct i40e_vsi *vsi = np->vsi;
2358
078b5876
JB		 2359 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2360
41c445ff
JB		 2361 /* return code is ignored as there is nothing a user
2362 * can do about failure to remove and a log message was
078b5876 2363 * already printed from the other function
41c445ff
JB		 2364 */
2365 i40e_vsi_kill_vlan(vsi, vid);
2366
2367 clear_bit(vid, vsi->active_vlans);
078b5876 2368
41c445ff
JB		 2369 return 0;
2370}
2371
2372/**
2373 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2374 * @vsi: the vsi being brought back up
2375 **/
2376static void i40e_restore_vlan(struct i40e_vsi *vsi)
2377{
2378 u16 vid;
2379
2380 if (!vsi->netdev)
2381 return;
2382
2383 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2384
2385 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2386 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2387 vid);
2388}
2389
2390/**
2391 * i40e_vsi_add_pvid - Add pvid for the VSI
2392 * @vsi: the vsi being adjusted
2393 * @vid: the vlan id to set as a PVID
2394 **/
dcae29be 2395int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2396{
2397 struct i40e_vsi_context ctxt;
f1c7e72e 2398 i40e_status ret;
41c445ff
JB		 2399
2400 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2401 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2402 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2403 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2404 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2405
2406 ctxt.seid = vsi->seid;
1a2f6248 2407 ctxt.info = vsi->info;
f1c7e72e
SN		 2408 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2409 if (ret) {
41c445ff 2410 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2411 "add pvid failed, err %s aq_err %s\n",
2412 i40e_stat_str(&vsi->back->hw, ret),
2413 i40e_aq_str(&vsi->back->hw,
2414 vsi->back->hw.aq.asq_last_status));
dcae29be 2415 return -ENOENT;
41c445ff
JB		 2416 }
2417
dcae29be 2418 return 0;
41c445ff
JB		 2419}
2420
2421/**
2422 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2423 * @vsi: the vsi being adjusted
2424 *
2425 * Just use the vlan_rx_register() service to put it back to normal
2426 **/
2427void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2428{
6c12fcbf
GR		 2429 i40e_vlan_stripping_disable(vsi);
2430
41c445ff 2431 vsi->info.pvid = 0;
41c445ff
JB		 2432}
2433
2434/**
2435 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2436 * @vsi: ptr to the VSI
2437 *
2438 * If this function returns with an error, then it's possible one or
2439 * more of the rings is populated (while the rest are not). It is the
2440 * callers duty to clean those orphaned rings.
2441 *
2442 * Return 0 on success, negative on failure
2443 **/
2444static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2445{
2446 int i, err = 0;
2447
2448 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2449 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2450
2451 return err;
2452}
2453
2454/**
2455 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2456 * @vsi: ptr to the VSI
2457 *
2458 * Free VSI's transmit software resources
2459 **/
2460static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2461{
2462 int i;
2463
8e9dca53
GR		 2464 if (!vsi->tx_rings)
2465 return;
2466
41c445ff 2467 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2468 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2469 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2470}
2471
2472/**
2473 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2474 * @vsi: ptr to the VSI
2475 *
2476 * If this function returns with an error, then it's possible one or
2477 * more of the rings is populated (while the rest are not). It is the
2478 * callers duty to clean those orphaned rings.
2479 *
2480 * Return 0 on success, negative on failure
2481 **/
2482static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2483{
2484 int i, err = 0;
2485
2486 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2487 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2488#ifdef I40E_FCOE
2489 i40e_fcoe_setup_ddp_resources(vsi);
2490#endif
41c445ff
JB		 2491 return err;
2492}
2493
2494/**
2495 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2496 * @vsi: ptr to the VSI
2497 *
2498 * Free all receive software resources
2499 **/
2500static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2501{
2502 int i;
2503
8e9dca53
GR		 2504 if (!vsi->rx_rings)
2505 return;
2506
41c445ff 2507 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2508 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2509 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2510#ifdef I40E_FCOE
2511 i40e_fcoe_free_ddp_resources(vsi);
2512#endif
41c445ff
JB		 2513}
2514
3ffa037d
NP		 2515/**
2516 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2517 * @ring: The Tx ring to configure
2518 *
2519 * This enables/disables XPS for a given Tx descriptor ring
2520 * based on the TCs enabled for the VSI that ring belongs to.
2521 **/
2522static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2523{
2524 struct i40e_vsi *vsi = ring->vsi;
2525 cpumask_var_t mask;
2526
9a660eea
JB		 2527 if (!ring->q_vector || !ring->netdev)
2528 return;
2529
2530 /* Single TC mode enable XPS */
2531 if (vsi->tc_config.numtc <= 1) {
2532 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2533 netif_set_xps_queue(ring->netdev,
2534 &ring->q_vector->affinity_mask,
2535 ring->queue_index);
9a660eea
JB		 2536 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2537 /* Disable XPS to allow selection based on TC */
2538 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2539 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2540 free_cpumask_var(mask);
3ffa037d
NP		 2541 }
2542}
2543
41c445ff
JB		 2544/**
2545 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2546 * @ring: The Tx ring to configure
2547 *
2548 * Configure the Tx descriptor ring in the HMC context.
2549 **/
2550static int i40e_configure_tx_ring(struct i40e_ring *ring)
2551{
2552 struct i40e_vsi *vsi = ring->vsi;
2553 u16 pf_q = vsi->base_queue + ring->queue_index;
2554 struct i40e_hw *hw = &vsi->back->hw;
2555 struct i40e_hmc_obj_txq tx_ctx;
2556 i40e_status err = 0;
2557 u32 qtx_ctl = 0;
2558
2559 /* some ATR related tx ring init */
60ea5f83 2560 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2561 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2562 ring->atr_count = 0;
2563 } else {
2564 ring->atr_sample_rate = 0;
2565 }
2566
3ffa037d
NP		 2567 /* configure XPS */
2568 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2569
2570 /* clear the context structure first */
2571 memset(&tx_ctx, 0, sizeof(tx_ctx));
2572
2573 tx_ctx.new_context = 1;
2574 tx_ctx.base = (ring->dma / 128);
2575 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2576 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2577 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2578#ifdef I40E_FCOE
2579 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2580#endif
beb0dff1 2581 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2582 /* FDIR VSI tx ring can still use RS bit and writebacks */
2583 if (vsi->type != I40E_VSI_FDIR)
2584 tx_ctx.head_wb_ena = 1;
2585 tx_ctx.head_wb_addr = ring->dma +
2586 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2587
2588 /* As part of VSI creation/update, FW allocates certain
2589 * Tx arbitration queue sets for each TC enabled for
2590 * the VSI. The FW returns the handles to these queue
2591 * sets as part of the response buffer to Add VSI,
2592 * Update VSI, etc. AQ commands. It is expected that
2593 * these queue set handles be associated with the Tx
2594 * queues by the driver as part of the TX queue context
2595 * initialization. This has to be done regardless of
2596 * DCB as by default everything is mapped to TC0.
2597 */
2598 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2599 tx_ctx.rdylist_act = 0;
2600
2601 /* clear the context in the HMC */
2602 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2603 if (err) {
2604 dev_info(&vsi->back->pdev->dev,
2605 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2606 ring->queue_index, pf_q, err);
2607 return -ENOMEM;
2608 }
2609
2610 /* set the context in the HMC */
2611 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2612 if (err) {
2613 dev_info(&vsi->back->pdev->dev,
2614 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2615 ring->queue_index, pf_q, err);
2616 return -ENOMEM;
2617 }
2618
2619 /* Now associate this queue with this PCI function */
7a28d885 2620 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2621 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2622 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2623 I40E_QTX_CTL_VFVM_INDX_MASK;
2624 } else {
9d8bf547 2625 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2626 }
2627
13fd9774
SN		 2628 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2629 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2630 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2631 i40e_flush(hw);
2632
41c445ff
JB		 2633 /* cache tail off for easier writes later */
2634 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2635
2636 return 0;
2637}
2638
2639/**
2640 * i40e_configure_rx_ring - Configure a receive ring context
2641 * @ring: The Rx ring to configure
2642 *
2643 * Configure the Rx descriptor ring in the HMC context.
2644 **/
2645static int i40e_configure_rx_ring(struct i40e_ring *ring)
2646{
2647 struct i40e_vsi *vsi = ring->vsi;
2648 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2649 u16 pf_q = vsi->base_queue + ring->queue_index;
2650 struct i40e_hw *hw = &vsi->back->hw;
2651 struct i40e_hmc_obj_rxq rx_ctx;
2652 i40e_status err = 0;
2653
2654 ring->state = 0;
2655
2656 /* clear the context structure first */
2657 memset(&rx_ctx, 0, sizeof(rx_ctx));
2658
2659 ring->rx_buf_len = vsi->rx_buf_len;
2660 ring->rx_hdr_len = vsi->rx_hdr_len;
2661
2662 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2663 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2664
2665 rx_ctx.base = (ring->dma / 128);
2666 rx_ctx.qlen = ring->count;
2667
2668 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2669 set_ring_16byte_desc_enabled(ring);
2670 rx_ctx.dsize = 0;
2671 } else {
2672 rx_ctx.dsize = 1;
2673 }
2674
2675 rx_ctx.dtype = vsi->dtype;
2676 if (vsi->dtype) {
2677 set_ring_ps_enabled(ring);
2678 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2679 I40E_RX_SPLIT_IP |
2680 I40E_RX_SPLIT_TCP_UDP |
2681 I40E_RX_SPLIT_SCTP;
2682 } else {
2683 rx_ctx.hsplit_0 = 0;
2684 }
2685
2686 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2687 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2688 if (hw->revision_id == 0)
2689 rx_ctx.lrxqthresh = 0;
2690 else
2691 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2692 rx_ctx.crcstrip = 1;
2693 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2694 /* this controls whether VLAN is stripped from inner headers */
2695 rx_ctx.showiv = 0;
38e00438
VD		 2696#ifdef I40E_FCOE
2697 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2698#endif
acb3676b
CS		 2699 /* set the prefena field to 1 because the manual says to */
2700 rx_ctx.prefena = 1;
41c445ff
JB		 2701
2702 /* clear the context in the HMC */
2703 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2704 if (err) {
2705 dev_info(&vsi->back->pdev->dev,
2706 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2707 ring->queue_index, pf_q, err);
2708 return -ENOMEM;
2709 }
2710
2711 /* set the context in the HMC */
2712 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2713 if (err) {
2714 dev_info(&vsi->back->pdev->dev,
2715 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2716 ring->queue_index, pf_q, err);
2717 return -ENOMEM;
2718 }
2719
2720 /* cache tail for quicker writes, and clear the reg before use */
2721 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2722 writel(0, ring->tail);
2723
a132af24
MW		 2724 if (ring_is_ps_enabled(ring)) {
2725 i40e_alloc_rx_headers(ring);
2726 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2727 } else {
2728 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2729 }
41c445ff
JB		 2730
2731 return 0;
2732}
2733
2734/**
2735 * i40e_vsi_configure_tx - Configure the VSI for Tx
2736 * @vsi: VSI structure describing this set of rings and resources
2737 *
2738 * Configure the Tx VSI for operation.
2739 **/
2740static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2741{
2742 int err = 0;
2743 u16 i;
2744
9f65e15b
AD		 2745 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2746 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2747
2748 return err;
2749}
2750
2751/**
2752 * i40e_vsi_configure_rx - Configure the VSI for Rx
2753 * @vsi: the VSI being configured
2754 *
2755 * Configure the Rx VSI for operation.
2756 **/
2757static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2758{
2759 int err = 0;
2760 u16 i;
2761
2762 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2763 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2764 + ETH_FCS_LEN + VLAN_HLEN;
2765 else
2766 vsi->max_frame = I40E_RXBUFFER_2048;
2767
2768 /* figure out correct receive buffer length */
2769 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2770 I40E_FLAG_RX_PS_ENABLED)) {
2771 case I40E_FLAG_RX_1BUF_ENABLED:
2772 vsi->rx_hdr_len = 0;
2773 vsi->rx_buf_len = vsi->max_frame;
2774 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2775 break;
2776 case I40E_FLAG_RX_PS_ENABLED:
2777 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2778 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2779 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2780 break;
2781 default:
2782 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2783 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2784 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2785 break;
2786 }
2787
38e00438
VD		 2788#ifdef I40E_FCOE
2789 /* setup rx buffer for FCoE */
2790 if ((vsi->type == I40E_VSI_FCOE) &&
2791 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2792 vsi->rx_hdr_len = 0;
2793 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2794 vsi->max_frame = I40E_RXBUFFER_3072;
2795 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2796 }
2797
2798#endif /* I40E_FCOE */
41c445ff
JB		 2799 /* round up for the chip's needs */
2800 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2801 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2802 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2803 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2804
2805 /* set up individual rings */
2806 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2807 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2808
2809 return err;
2810}
2811
2812/**
2813 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2814 * @vsi: ptr to the VSI
2815 **/
2816static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2817{
e7046ee1 2818 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2819 u16 qoffset, qcount;
2820 int i, n;
2821
cd238a3e
PN		 2822 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2823 /* Reset the TC information */
2824 for (i = 0; i < vsi->num_queue_pairs; i++) {
2825 rx_ring = vsi->rx_rings[i];
2826 tx_ring = vsi->tx_rings[i];
2827 rx_ring->dcb_tc = 0;
2828 tx_ring->dcb_tc = 0;
2829 }
2830 }
41c445ff
JB		 2831
2832 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2833 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2834 continue;
2835
2836 qoffset = vsi->tc_config.tc_info[n].qoffset;
2837 qcount = vsi->tc_config.tc_info[n].qcount;
2838 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2839 rx_ring = vsi->rx_rings[i];
2840 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2841 rx_ring->dcb_tc = n;
2842 tx_ring->dcb_tc = n;
2843 }
2844 }
2845}
2846
2847/**
2848 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2849 * @vsi: ptr to the VSI
2850 **/
2851static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2852{
2853 if (vsi->netdev)
2854 i40e_set_rx_mode(vsi->netdev);
2855}
2856
17a73f6b
JG		 2857/**
2858 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2859 * @vsi: Pointer to the targeted VSI
2860 *
2861 * This function replays the hlist on the hw where all the SB Flow Director
2862 * filters were saved.
2863 **/
2864static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2865{
2866 struct i40e_fdir_filter *filter;
2867 struct i40e_pf *pf = vsi->back;
2868 struct hlist_node *node;
2869
55a5e60b
ASJ		 2870 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2871 return;
2872
17a73f6b
JG		 2873 hlist_for_each_entry_safe(filter, node,
2874 &pf->fdir_filter_list, fdir_node) {
2875 i40e_add_del_fdir(vsi, filter, true);
2876 }
2877}
2878
41c445ff
JB		 2879/**
2880 * i40e_vsi_configure - Set up the VSI for action
2881 * @vsi: the VSI being configured
2882 **/
2883static int i40e_vsi_configure(struct i40e_vsi *vsi)
2884{
2885 int err;
2886
2887 i40e_set_vsi_rx_mode(vsi);
2888 i40e_restore_vlan(vsi);
2889 i40e_vsi_config_dcb_rings(vsi);
2890 err = i40e_vsi_configure_tx(vsi);
2891 if (!err)
2892 err = i40e_vsi_configure_rx(vsi);
2893
2894 return err;
2895}
2896
2897/**
2898 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2899 * @vsi: the VSI being configured
2900 **/
2901static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2902{
2903 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 2904 struct i40e_hw *hw = &pf->hw;
2905 u16 vector;
2906 int i, q;
41c445ff
JB		 2907 u32 qp;
2908
2909 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2910 * and PFINT_LNKLSTn registers, e.g.:
2911 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2912 */
2913 qp = vsi->base_queue;
2914 vector = vsi->base_vector;
493fb300 2915 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 2916 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
2917
41c445ff
JB		 2918 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2919 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2920 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2921 q_vector->rx.itr);
2922 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2923 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2924 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2925 q_vector->tx.itr);
ac26fc13
JB		 2926 wr32(hw, I40E_PFINT_RATEN(vector - 1),
2927 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 2928
2929 /* Linked list for the queuepairs assigned to this vector */
2930 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2931 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 2932 u32 val;
2933
41c445ff
JB		 2934 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2935 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2936 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2937 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2938 (I40E_QUEUE_TYPE_TX
2939 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2940
2941 wr32(hw, I40E_QINT_RQCTL(qp), val);
2942
2943 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2944 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2945 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2946 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2947 (I40E_QUEUE_TYPE_RX
2948 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2949
2950 /* Terminate the linked list */
2951 if (q == (q_vector->num_ringpairs - 1))
2952 val |= (I40E_QUEUE_END_OF_LIST
2953 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2954
2955 wr32(hw, I40E_QINT_TQCTL(qp), val);
2956 qp++;
2957 }
2958 }
2959
2960 i40e_flush(hw);
2961}
2962
2963/**
2964 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2965 * @hw: ptr to the hardware info
2966 **/
ab437b5a 2967static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2968{
ab437b5a 2969 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2970 u32 val;
2971
2972 /* clear things first */
2973 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2974 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2975
2976 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2977 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2978 I40E_PFINT_ICR0_ENA_GRST_MASK |
2979 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2980 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2981 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2982 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2983 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2984
0d8e1439
ASJ		 2985 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
2986 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
2987
ab437b5a
JK		 2988 if (pf->flags & I40E_FLAG_PTP)
2989 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2990
41c445ff
JB		 2991 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2992
2993 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2994 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2995 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2996
2997 /* OTHER_ITR_IDX = 0 */
2998 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2999}
3000
3001/**
3002 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3003 * @vsi: the VSI being configured
3004 **/
3005static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3006{
493fb300 3007 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3008 struct i40e_pf *pf = vsi->back;
3009 struct i40e_hw *hw = &pf->hw;
3010 u32 val;
3011
3012 /* set the ITR configuration */
3013 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3014 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3015 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3016 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3017 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3018 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3019
ab437b5a 3020 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3021
3022 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3023 wr32(hw, I40E_PFINT_LNKLST0, 0);
3024
f29eaa3d 3025 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3026 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3027 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3028 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3029
3030 wr32(hw, I40E_QINT_RQCTL(0), val);
3031
3032 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3033 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3034 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3035
3036 wr32(hw, I40E_QINT_TQCTL(0), val);
3037 i40e_flush(hw);
3038}
3039
2ef28cfb
MW		 3040/**
3041 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3042 * @pf: board private structure
3043 **/
3044void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3045{
3046 struct i40e_hw *hw = &pf->hw;
3047
3048 wr32(hw, I40E_PFINT_DYN_CTL0,
3049 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3050 i40e_flush(hw);
3051}
3052
41c445ff
JB		 3053/**
3054 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3055 * @pf: board private structure
3056 **/
116a57d4 3057void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3058{
3059 struct i40e_hw *hw = &pf->hw;
3060 u32 val;
3061
3062 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3063 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3064 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3065
3066 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3067 i40e_flush(hw);
3068}
3069
5c2cebda
CW		 3070/**
3071 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3072 * @vsi: pointer to a vsi
03147773 3073 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3074 **/
3075void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3076{
3077 struct i40e_pf *pf = vsi->back;
3078 struct i40e_hw *hw = &pf->hw;
3079 u32 val;
3080
3081 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3082 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3083 i40e_flush(hw);
3084}
3085
41c445ff
JB		 3086/**
3087 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3088 * @irq: interrupt number
3089 * @data: pointer to a q_vector
3090 **/
3091static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3092{
3093 struct i40e_q_vector *q_vector = data;
3094
cd0b6fa6 3095 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3096 return IRQ_HANDLED;
3097
3098 napi_schedule(&q_vector->napi);
3099
3100 return IRQ_HANDLED;
3101}
3102
41c445ff
JB		 3103/**
3104 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3105 * @vsi: the VSI being configured
3106 * @basename: name for the vector
3107 *
3108 * Allocates MSI-X vectors and requests interrupts from the kernel.
3109 **/
3110static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3111{
3112 int q_vectors = vsi->num_q_vectors;
3113 struct i40e_pf *pf = vsi->back;
3114 int base = vsi->base_vector;
3115 int rx_int_idx = 0;
3116 int tx_int_idx = 0;
3117 int vector, err;
3118
3119 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3120 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3121
cd0b6fa6 3122 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3123 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3124 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3125 tx_int_idx++;
cd0b6fa6 3126 } else if (q_vector->rx.ring) {
41c445ff
JB		 3127 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3128 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3129 } else if (q_vector->tx.ring) {
41c445ff
JB		 3130 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3131 "%s-%s-%d", basename, "tx", tx_int_idx++);
3132 } else {
3133 /* skip this unused q_vector */
3134 continue;
3135 }
3136 err = request_irq(pf->msix_entries[base + vector].vector,
3137 vsi->irq_handler,
3138 0,
3139 q_vector->name,
3140 q_vector);
3141 if (err) {
3142 dev_info(&pf->pdev->dev,
fb43201f 3143 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3144 goto free_queue_irqs;
3145 }
3146 /* assign the mask for this irq */
3147 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3148 &q_vector->affinity_mask);
3149 }
3150
63741846 3151 vsi->irqs_ready = true;
41c445ff
JB		 3152 return 0;
3153
3154free_queue_irqs:
3155 while (vector) {
3156 vector--;
3157 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3158 NULL);
3159 free_irq(pf->msix_entries[base + vector].vector,
3160 &(vsi->q_vectors[vector]));
3161 }
3162 return err;
3163}
3164
3165/**
3166 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3167 * @vsi: the VSI being un-configured
3168 **/
3169static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3170{
3171 struct i40e_pf *pf = vsi->back;
3172 struct i40e_hw *hw = &pf->hw;
3173 int base = vsi->base_vector;
3174 int i;
3175
3176 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3177 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3178 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3179 }
3180
3181 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3182 for (i = vsi->base_vector;
3183 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3184 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3185
3186 i40e_flush(hw);
3187 for (i = 0; i < vsi->num_q_vectors; i++)
3188 synchronize_irq(pf->msix_entries[i + base].vector);
3189 } else {
3190 /* Legacy and MSI mode - this stops all interrupt handling */
3191 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3192 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3193 i40e_flush(hw);
3194 synchronize_irq(pf->pdev->irq);
3195 }
3196}
3197
3198/**
3199 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3200 * @vsi: the VSI being configured
3201 **/
3202static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3203{
3204 struct i40e_pf *pf = vsi->back;
3205 int i;
3206
3207 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3208 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3209 i40e_irq_dynamic_enable(vsi, i);
3210 } else {
3211 i40e_irq_dynamic_enable_icr0(pf);
3212 }
3213
1022cb6c 3214 i40e_flush(&pf->hw);
41c445ff
JB		 3215 return 0;
3216}
3217
3218/**
3219 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3220 * @pf: board private structure
3221 **/
3222static void i40e_stop_misc_vector(struct i40e_pf *pf)
3223{
3224 /* Disable ICR 0 */
3225 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3226 i40e_flush(&pf->hw);
3227}
3228
3229/**
3230 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3231 * @irq: interrupt number
3232 * @data: pointer to a q_vector
3233 *
3234 * This is the handler used for all MSI/Legacy interrupts, and deals
3235 * with both queue and non-queue interrupts. This is also used in
3236 * MSIX mode to handle the non-queue interrupts.
3237 **/
3238static irqreturn_t i40e_intr(int irq, void *data)
3239{
3240 struct i40e_pf *pf = (struct i40e_pf *)data;
3241 struct i40e_hw *hw = &pf->hw;
5e823066 3242 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3243 u32 icr0, icr0_remaining;
3244 u32 val, ena_mask;
3245
3246 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3247 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3248
116a57d4
SN		 3249 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3250 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3251 goto enable_intr;
41c445ff 3252
cd92e72f
SN		 3253 /* if interrupt but no bits showing, must be SWINT */
3254 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3255 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3256 pf->sw_int_count++;
3257
0d8e1439
ASJ		 3258 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3259 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3260 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3261 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3262 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3263 }
3264
41c445ff
JB		 3265 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3266 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3267
3268 /* temporarily disable queue cause for NAPI processing */
3269 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3270
41c445ff
JB		 3271 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3272 wr32(hw, I40E_QINT_RQCTL(0), qval);
3273
3274 qval = rd32(hw, I40E_QINT_TQCTL(0));
3275 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3276 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3277
3278 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3279 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3280 }
3281
3282 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3283 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3284 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3285 }
3286
3287 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3288 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3289 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3290 }
3291
3292 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3293 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3294 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3295 }
3296
3297 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3298 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3299 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3300 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3301 val = rd32(hw, I40E_GLGEN_RSTAT);
3302 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3303 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3304 if (val == I40E_RESET_CORER) {
41c445ff 3305 pf->corer_count++;
4eb3f768 3306 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3307 pf->globr_count++;
4eb3f768 3308 } else if (val == I40E_RESET_EMPR) {
41c445ff 3309 pf->empr_count++;
9df42d1a 3310 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3311 }
41c445ff
JB		 3312 }
3313
9c010ee0
ASJ		 3314 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3315 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3316 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3317 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3318 rd32(hw, I40E_PFHMC_ERRORINFO),
3319 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3320 }
3321
beb0dff1
JK		 3322 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3323 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3324
3325 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3326 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3327 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3328 }
beb0dff1
JK		 3329 }
3330
41c445ff
JB		 3331 /* If a critical error is pending we have no choice but to reset the
3332 * device.
3333 * Report and mask out any remaining unexpected interrupts.
3334 */
3335 icr0_remaining = icr0 & ena_mask;
3336 if (icr0_remaining) {
3337 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3338 icr0_remaining);
9c010ee0 3339 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3340 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3341 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3342 dev_info(&pf->pdev->dev, "device will be reset\n");
3343 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3344 i40e_service_event_schedule(pf);
41c445ff
JB		 3345 }
3346 ena_mask &= ~icr0_remaining;
3347 }
5e823066 3348 ret = IRQ_HANDLED;
41c445ff 3349
5e823066 3350enable_intr:
41c445ff
JB		 3351 /* re-enable interrupt causes */
3352 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3353 if (!test_bit(__I40E_DOWN, &pf->state)) {
3354 i40e_service_event_schedule(pf);
3355 i40e_irq_dynamic_enable_icr0(pf);
3356 }
3357
5e823066 3358 return ret;
41c445ff
JB		 3359}
3360
cbf61325
ASJ		 3361/**
3362 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3363 * @tx_ring: tx ring to clean
3364 * @budget: how many cleans we're allowed
3365 *
3366 * Returns true if there's any budget left (e.g. the clean is finished)
3367 **/
3368static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3369{
3370 struct i40e_vsi *vsi = tx_ring->vsi;
3371 u16 i = tx_ring->next_to_clean;
3372 struct i40e_tx_buffer *tx_buf;
3373 struct i40e_tx_desc *tx_desc;
3374
3375 tx_buf = &tx_ring->tx_bi[i];
3376 tx_desc = I40E_TX_DESC(tx_ring, i);
3377 i -= tx_ring->count;
3378
3379 do {
3380 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3381
3382 /* if next_to_watch is not set then there is no work pending */
3383 if (!eop_desc)
3384 break;
3385
3386 /* prevent any other reads prior to eop_desc */
3387 read_barrier_depends();
3388
3389 /* if the descriptor isn't done, no work yet to do */
3390 if (!(eop_desc->cmd_type_offset_bsz &
3391 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3392 break;
3393
3394 /* clear next_to_watch to prevent false hangs */
3395 tx_buf->next_to_watch = NULL;
3396
49d7d933
ASJ		 3397 tx_desc->buffer_addr = 0;
3398 tx_desc->cmd_type_offset_bsz = 0;
3399 /* move past filter desc */
3400 tx_buf++;
3401 tx_desc++;
3402 i++;
3403 if (unlikely(!i)) {
3404 i -= tx_ring->count;
3405 tx_buf = tx_ring->tx_bi;
3406 tx_desc = I40E_TX_DESC(tx_ring, 0);
3407 }
cbf61325
ASJ		 3408 /* unmap skb header data */
3409 dma_unmap_single(tx_ring->dev,
3410 dma_unmap_addr(tx_buf, dma),
3411 dma_unmap_len(tx_buf, len),
3412 DMA_TO_DEVICE);
49d7d933
ASJ		 3413 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3414 kfree(tx_buf->raw_buf);
cbf61325 3415
49d7d933
ASJ		 3416 tx_buf->raw_buf = NULL;
3417 tx_buf->tx_flags = 0;
3418 tx_buf->next_to_watch = NULL;
cbf61325 3419 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3420 tx_desc->buffer_addr = 0;
3421 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3422
49d7d933 3423 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3424 tx_buf++;
3425 tx_desc++;
3426 i++;
3427 if (unlikely(!i)) {
3428 i -= tx_ring->count;
3429 tx_buf = tx_ring->tx_bi;
3430 tx_desc = I40E_TX_DESC(tx_ring, 0);
3431 }
3432
3433 /* update budget accounting */
3434 budget--;
3435 } while (likely(budget));
3436
3437 i += tx_ring->count;
3438 tx_ring->next_to_clean = i;
3439
6995b36c 3440 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3441 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3442
cbf61325
ASJ		 3443 return budget > 0;
3444}
3445
3446/**
3447 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3448 * @irq: interrupt number
3449 * @data: pointer to a q_vector
3450 **/
3451static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3452{
3453 struct i40e_q_vector *q_vector = data;
3454 struct i40e_vsi *vsi;
3455
3456 if (!q_vector->tx.ring)
3457 return IRQ_HANDLED;
3458
3459 vsi = q_vector->tx.ring->vsi;
3460 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3461
3462 return IRQ_HANDLED;
3463}
3464
41c445ff 3465/**
cd0b6fa6 3466 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3467 * @vsi: the VSI being configured
3468 * @v_idx: vector index
cd0b6fa6 3469 * @qp_idx: queue pair index
41c445ff 3470 **/
26cdc443 3471static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3472{
493fb300 3473 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3474 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3475 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3476
3477 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3478 tx_ring->next = q_vector->tx.ring;
3479 q_vector->tx.ring = tx_ring;
41c445ff 3480 q_vector->tx.count++;
cd0b6fa6
AD		 3481
3482 rx_ring->q_vector = q_vector;
3483 rx_ring->next = q_vector->rx.ring;
3484 q_vector->rx.ring = rx_ring;
3485 q_vector->rx.count++;
41c445ff
JB		 3486}
3487
3488/**
3489 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3490 * @vsi: the VSI being configured
3491 *
3492 * This function maps descriptor rings to the queue-specific vectors
3493 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3494 * one vector per queue pair, but on a constrained vector budget, we
3495 * group the queue pairs as "efficiently" as possible.
3496 **/
3497static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3498{
3499 int qp_remaining = vsi->num_queue_pairs;
3500 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3501 int num_ringpairs;
41c445ff
JB		 3502 int v_start = 0;
3503 int qp_idx = 0;
3504
3505 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3506 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3507 * It is also important to go through all the vectors available to be
3508 * sure that if we don't use all the vectors, that the remaining vectors
3509 * are cleared. This is especially important when decreasing the
3510 * number of queues in use.
41c445ff 3511 */
70114ec4 3512 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3513 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3514
3515 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3516
3517 q_vector->num_ringpairs = num_ringpairs;
3518
3519 q_vector->rx.count = 0;
3520 q_vector->tx.count = 0;
3521 q_vector->rx.ring = NULL;
3522 q_vector->tx.ring = NULL;
3523
3524 while (num_ringpairs--) {
26cdc443 3525 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3526 qp_idx++;
3527 qp_remaining--;
41c445ff
JB		 3528 }
3529 }
3530}
3531
3532/**
3533 * i40e_vsi_request_irq - Request IRQ from the OS
3534 * @vsi: the VSI being configured
3535 * @basename: name for the vector
3536 **/
3537static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3538{
3539 struct i40e_pf *pf = vsi->back;
3540 int err;
3541
3542 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3543 err = i40e_vsi_request_irq_msix(vsi, basename);
3544 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3545 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3546 pf->int_name, pf);
41c445ff
JB		 3547 else
3548 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3549 pf->int_name, pf);
41c445ff
JB		 3550
3551 if (err)
3552 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3553
3554 return err;
3555}
3556
3557#ifdef CONFIG_NET_POLL_CONTROLLER
3558/**
3559 * i40e_netpoll - A Polling 'interrupt'handler
3560 * @netdev: network interface device structure
3561 *
3562 * This is used by netconsole to send skbs without having to re-enable
3563 * interrupts. It's not called while the normal interrupt routine is executing.
3564 **/
38e00438
VD		 3565#ifdef I40E_FCOE
3566void i40e_netpoll(struct net_device *netdev)
3567#else
41c445ff 3568static void i40e_netpoll(struct net_device *netdev)
38e00438 3569#endif
41c445ff
JB		 3570{
3571 struct i40e_netdev_priv *np = netdev_priv(netdev);
3572 struct i40e_vsi *vsi = np->vsi;
3573 struct i40e_pf *pf = vsi->back;
3574 int i;
3575
3576 /* if interface is down do nothing */
3577 if (test_bit(__I40E_DOWN, &vsi->state))
3578 return;
3579
41c445ff
JB		 3580 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3581 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3582 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3583 } else {
3584 i40e_intr(pf->pdev->irq, netdev);
3585 }
41c445ff
JB		 3586}
3587#endif
3588
23527308
NP		 3589/**
3590 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3591 * @pf: the PF being configured
3592 * @pf_q: the PF queue
3593 * @enable: enable or disable state of the queue
3594 *
3595 * This routine will wait for the given Tx queue of the PF to reach the
3596 * enabled or disabled state.
3597 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3598 * multiple retries; else will return 0 in case of success.
3599 **/
3600static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3601{
3602 int i;
3603 u32 tx_reg;
3604
3605 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3606 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3607 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3608 break;
3609
f98a2006 3610 usleep_range(10, 20);
23527308
NP		 3611 }
3612 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3613 return -ETIMEDOUT;
3614
3615 return 0;
3616}
3617
41c445ff
JB		 3618/**
3619 * i40e_vsi_control_tx - Start or stop a VSI's rings
3620 * @vsi: the VSI being configured
3621 * @enable: start or stop the rings
3622 **/
3623static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3624{
3625 struct i40e_pf *pf = vsi->back;
3626 struct i40e_hw *hw = &pf->hw;
23527308 3627 int i, j, pf_q, ret = 0;
41c445ff
JB		 3628 u32 tx_reg;
3629
3630 pf_q = vsi->base_queue;
3631 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3632
3633 /* warn the TX unit of coming changes */
3634 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3635 if (!enable)
f98a2006 3636 usleep_range(10, 20);
351499ab 3637
6c5ef620 3638 for (j = 0; j < 50; j++) {
41c445ff 3639 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3640 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3641 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3642 break;
3643 usleep_range(1000, 2000);
3644 }
fda972f6 3645 /* Skip if the queue is already in the requested state */
7c122007 3646 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3647 continue;
41c445ff
JB		 3648
3649 /* turn on/off the queue */
c5c9eb9e
SN		 3650 if (enable) {
3651 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3652 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3653 } else {
41c445ff 3654 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3655 }
41c445ff
JB		 3656
3657 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3658 /* No waiting for the Tx queue to disable */
3659 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3660 continue;
41c445ff
JB		 3661
3662 /* wait for the change to finish */
23527308
NP		 3663 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3664 if (ret) {
3665 dev_info(&pf->pdev->dev,
fb43201f
SN		 3666 "VSI seid %d Tx ring %d %sable timeout\n",
3667 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3668 break;
41c445ff
JB		 3669 }
3670 }
3671
7134f9ce
JB		 3672 if (hw->revision_id == 0)
3673 mdelay(50);
23527308
NP		 3674 return ret;
3675}
3676
3677/**
3678 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3679 * @pf: the PF being configured
3680 * @pf_q: the PF queue
3681 * @enable: enable or disable state of the queue
3682 *
3683 * This routine will wait for the given Rx queue of the PF to reach the
3684 * enabled or disabled state.
3685 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3686 * multiple retries; else will return 0 in case of success.
3687 **/
3688static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3689{
3690 int i;
3691 u32 rx_reg;
3692
3693 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3694 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3695 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3696 break;
3697
f98a2006 3698 usleep_range(10, 20);
23527308
NP		 3699 }
3700 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3701 return -ETIMEDOUT;
7134f9ce 3702
41c445ff
JB		 3703 return 0;
3704}
3705
3706/**
3707 * i40e_vsi_control_rx - Start or stop a VSI's rings
3708 * @vsi: the VSI being configured
3709 * @enable: start or stop the rings
3710 **/
3711static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3712{
3713 struct i40e_pf *pf = vsi->back;
3714 struct i40e_hw *hw = &pf->hw;
23527308 3715 int i, j, pf_q, ret = 0;
41c445ff
JB		 3716 u32 rx_reg;
3717
3718 pf_q = vsi->base_queue;
3719 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3720 for (j = 0; j < 50; j++) {
41c445ff 3721 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3722 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3723 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3724 break;
3725 usleep_range(1000, 2000);
3726 }
41c445ff 3727
7c122007
CS		 3728 /* Skip if the queue is already in the requested state */
3729 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3730 continue;
41c445ff
JB		 3731
3732 /* turn on/off the queue */
3733 if (enable)
6c5ef620 3734 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3735 else
6c5ef620 3736 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3737 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3738
3739 /* wait for the change to finish */
23527308
NP		 3740 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3741 if (ret) {
3742 dev_info(&pf->pdev->dev,
fb43201f
SN		 3743 "VSI seid %d Rx ring %d %sable timeout\n",
3744 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3745 break;
41c445ff
JB		 3746 }
3747 }
3748
23527308 3749 return ret;
41c445ff
JB		 3750}
3751
3752/**
3753 * i40e_vsi_control_rings - Start or stop a VSI's rings
3754 * @vsi: the VSI being configured
3755 * @enable: start or stop the rings
3756 **/
fc18eaa0 3757int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3758{
3b867b28 3759 int ret = 0;
41c445ff
JB		 3760
3761 /* do rx first for enable and last for disable */
3762 if (request) {
3763 ret = i40e_vsi_control_rx(vsi, request);
3764 if (ret)
3765 return ret;
3766 ret = i40e_vsi_control_tx(vsi, request);
3767 } else {
3b867b28
ASJ		 3768 /* Ignore return value, we need to shutdown whatever we can */
3769 i40e_vsi_control_tx(vsi, request);
3770 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3771 }
3772
3773 return ret;
3774}
3775
3776/**
3777 * i40e_vsi_free_irq - Free the irq association with the OS
3778 * @vsi: the VSI being configured
3779 **/
3780static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3781{
3782 struct i40e_pf *pf = vsi->back;
3783 struct i40e_hw *hw = &pf->hw;
3784 int base = vsi->base_vector;
3785 u32 val, qp;
3786 int i;
3787
3788 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3789 if (!vsi->q_vectors)
3790 return;
3791
63741846
SN		 3792 if (!vsi->irqs_ready)
3793 return;
3794
3795 vsi->irqs_ready = false;
41c445ff
JB		 3796 for (i = 0; i < vsi->num_q_vectors; i++) {
3797 u16 vector = i + base;
3798
3799 /* free only the irqs that were actually requested */
78681b1f
SN		 3800 if (!vsi->q_vectors[i] ||
3801 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3802 continue;
3803
3804 /* clear the affinity_mask in the IRQ descriptor */
3805 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3806 NULL);
3807 free_irq(pf->msix_entries[vector].vector,
493fb300 3808 vsi->q_vectors[i]);
41c445ff
JB		 3809
3810 /* Tear down the interrupt queue link list
3811 *
3812 * We know that they come in pairs and always
3813 * the Rx first, then the Tx. To clear the
3814 * link list, stick the EOL value into the
3815 * next_q field of the registers.
3816 */
3817 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3818 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3819 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3820 val |= I40E_QUEUE_END_OF_LIST
3821 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3822 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3823
3824 while (qp != I40E_QUEUE_END_OF_LIST) {
3825 u32 next;
3826
3827 val = rd32(hw, I40E_QINT_RQCTL(qp));
3828
3829 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3830 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3831 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3832 I40E_QINT_RQCTL_INTEVENT_MASK);
3833
3834 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3835 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3836
3837 wr32(hw, I40E_QINT_RQCTL(qp), val);
3838
3839 val = rd32(hw, I40E_QINT_TQCTL(qp));
3840
3841 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3842 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3843
3844 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3845 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3846 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3847 I40E_QINT_TQCTL_INTEVENT_MASK);
3848
3849 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3850 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3851
3852 wr32(hw, I40E_QINT_TQCTL(qp), val);
3853 qp = next;
3854 }
3855 }
3856 } else {
3857 free_irq(pf->pdev->irq, pf);
3858
3859 val = rd32(hw, I40E_PFINT_LNKLST0);
3860 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3861 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3862 val |= I40E_QUEUE_END_OF_LIST
3863 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3864 wr32(hw, I40E_PFINT_LNKLST0, val);
3865
3866 val = rd32(hw, I40E_QINT_RQCTL(qp));
3867 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3868 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3869 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3870 I40E_QINT_RQCTL_INTEVENT_MASK);
3871
3872 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3873 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3874
3875 wr32(hw, I40E_QINT_RQCTL(qp), val);
3876
3877 val = rd32(hw, I40E_QINT_TQCTL(qp));
3878
3879 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3880 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3881 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3882 I40E_QINT_TQCTL_INTEVENT_MASK);
3883
3884 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3885 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3886
3887 wr32(hw, I40E_QINT_TQCTL(qp), val);
3888 }
3889}
3890
493fb300
AD		 3891/**
3892 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3893 * @vsi: the VSI being configured
3894 * @v_idx: Index of vector to be freed
3895 *
3896 * This function frees the memory allocated to the q_vector. In addition if
3897 * NAPI is enabled it will delete any references to the NAPI struct prior
3898 * to freeing the q_vector.
3899 **/
3900static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3901{
3902 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3903 struct i40e_ring *ring;
493fb300
AD		 3904
3905 if (!q_vector)
3906 return;
3907
3908 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3909 i40e_for_each_ring(ring, q_vector->tx)
3910 ring->q_vector = NULL;
3911
3912 i40e_for_each_ring(ring, q_vector->rx)
3913 ring->q_vector = NULL;
493fb300
AD		 3914
3915 /* only VSI w/ an associated netdev is set up w/ NAPI */
3916 if (vsi->netdev)
3917 netif_napi_del(&q_vector->napi);
3918
3919 vsi->q_vectors[v_idx] = NULL;
3920
3921 kfree_rcu(q_vector, rcu);
3922}
3923
41c445ff
JB		 3924/**
3925 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3926 * @vsi: the VSI being un-configured
3927 *
3928 * This frees the memory allocated to the q_vectors and
3929 * deletes references to the NAPI struct.
3930 **/
3931static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3932{
3933 int v_idx;
3934
493fb300
AD		 3935 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3936 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3937}
3938
3939/**
3940 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3941 * @pf: board private structure
3942 **/
3943static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3944{
3945 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3946 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3947 pci_disable_msix(pf->pdev);
3948 kfree(pf->msix_entries);
3949 pf->msix_entries = NULL;
3b444399
SN		 3950 kfree(pf->irq_pile);
3951 pf->irq_pile = NULL;
41c445ff
JB		 3952 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3953 pci_disable_msi(pf->pdev);
3954 }
3955 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3956}
3957
3958/**
3959 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3960 * @pf: board private structure
3961 *
3962 * We go through and clear interrupt specific resources and reset the structure
3963 * to pre-load conditions
3964 **/
3965static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3966{
3967 int i;
3968
e147758d
SN		 3969 i40e_stop_misc_vector(pf);
3970 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3971 synchronize_irq(pf->msix_entries[0].vector);
3972 free_irq(pf->msix_entries[0].vector, pf);
3973 }
3974
41c445ff 3975 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3976 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3977 if (pf->vsi[i])
3978 i40e_vsi_free_q_vectors(pf->vsi[i]);
3979 i40e_reset_interrupt_capability(pf);
3980}
3981
3982/**
3983 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3984 * @vsi: the VSI being configured
3985 **/
3986static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3987{
3988 int q_idx;
3989
3990 if (!vsi->netdev)
3991 return;
3992
3993 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3994 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3995}
3996
3997/**
3998 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3999 * @vsi: the VSI being configured
4000 **/
4001static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4002{
4003 int q_idx;
4004
4005 if (!vsi->netdev)
4006 return;
4007
4008 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4009 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4010}
4011
90ef8d47
SN		 4012/**
4013 * i40e_vsi_close - Shut down a VSI
4014 * @vsi: the vsi to be quelled
4015 **/
4016static void i40e_vsi_close(struct i40e_vsi *vsi)
4017{
4018 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4019 i40e_down(vsi);
4020 i40e_vsi_free_irq(vsi);
4021 i40e_vsi_free_tx_resources(vsi);
4022 i40e_vsi_free_rx_resources(vsi);
92faef85 4023 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4024}
4025
41c445ff
JB		 4026/**
4027 * i40e_quiesce_vsi - Pause a given VSI
4028 * @vsi: the VSI being paused
4029 **/
4030static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4031{
4032 if (test_bit(__I40E_DOWN, &vsi->state))
4033 return;
4034
d341b7a5
NP		 4035 /* No need to disable FCoE VSI when Tx suspended */
4036 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4037 vsi->type == I40E_VSI_FCOE) {
4038 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4039 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4040 return;
4041 }
4042
41c445ff 4043 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4044 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4045 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4046 else
90ef8d47 4047 i40e_vsi_close(vsi);
41c445ff
JB		 4048}
4049
4050/**
4051 * i40e_unquiesce_vsi - Resume a given VSI
4052 * @vsi: the VSI being resumed
4053 **/
4054static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4055{
4056 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4057 return;
4058
4059 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4060 if (vsi->netdev && netif_running(vsi->netdev))
4061 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4062 else
8276f757 4063 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4064}
4065
4066/**
4067 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4068 * @pf: the PF
4069 **/
4070static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4071{
4072 int v;
4073
505682cd 4074 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4075 if (pf->vsi[v])
4076 i40e_quiesce_vsi(pf->vsi[v]);
4077 }
4078}
4079
4080/**
4081 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4082 * @pf: the PF
4083 **/
4084static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4085{
4086 int v;
4087
505682cd 4088 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4089 if (pf->vsi[v])
4090 i40e_unquiesce_vsi(pf->vsi[v]);
4091 }
4092}
4093
69129dc3
NP		 4094#ifdef CONFIG_I40E_DCB
4095/**
4096 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4097 * @vsi: the VSI being configured
4098 *
4099 * This function waits for the given VSI's Tx queues to be disabled.
4100 **/
4101static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4102{
4103 struct i40e_pf *pf = vsi->back;
4104 int i, pf_q, ret;
4105
4106 pf_q = vsi->base_queue;
4107 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4108 /* Check and wait for the disable status of the queue */
4109 ret = i40e_pf_txq_wait(pf, pf_q, false);
4110 if (ret) {
4111 dev_info(&pf->pdev->dev,
fb43201f
SN		 4112 "VSI seid %d Tx ring %d disable timeout\n",
4113 vsi->seid, pf_q);
69129dc3
NP		 4114 return ret;
4115 }
4116 }
4117
4118 return 0;
4119}
4120
4121/**
4122 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4123 * @pf: the PF
4124 *
4125 * This function waits for the Tx queues to be in disabled state for all the
4126 * VSIs that are managed by this PF.
4127 **/
4128static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4129{
4130 int v, ret = 0;
4131
4132 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4133 /* No need to wait for FCoE VSI queues */
4134 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4135 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4136 if (ret)
4137 break;
4138 }
4139 }
4140
4141 return ret;
4142}
4143
4144#endif
b03a8c1f
KP		 4145
4146/**
4147 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4148 * @q_idx: TX queue number
4149 * @vsi: Pointer to VSI struct
4150 *
4151 * This function checks specified queue for given VSI. Detects hung condition.
4152 * Sets hung bit since it is two step process. Before next run of service task
4153 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4154 * hung condition remain unchanged and during subsequent run, this function
4155 * issues SW interrupt to recover from hung condition.
4156 **/
4157static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4158{
4159 struct i40e_ring *tx_ring = NULL;
4160 struct i40e_pf *pf;
4161 u32 head, val, tx_pending;
4162 int i;
4163
4164 pf = vsi->back;
4165
4166 /* now that we have an index, find the tx_ring struct */
4167 for (i = 0; i < vsi->num_queue_pairs; i++) {
4168 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4169 if (q_idx == vsi->tx_rings[i]->queue_index) {
4170 tx_ring = vsi->tx_rings[i];
4171 break;
4172 }
4173 }
4174 }
4175
4176 if (!tx_ring)
4177 return;
4178
4179 /* Read interrupt register */
4180 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4181 val = rd32(&pf->hw,
4182 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4183 tx_ring->vsi->base_vector - 1));
4184 else
4185 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4186
4187 head = i40e_get_head(tx_ring);
4188
4189 tx_pending = i40e_get_tx_pending(tx_ring);
4190
4191 /* Interrupts are disabled and TX pending is non-zero,
4192 * trigger the SW interrupt (don't wait). Worst case
4193 * there will be one extra interrupt which may result
4194 * into not cleaning any queues because queues are cleaned.
4195 */
4196 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4197 i40e_force_wb(vsi, tx_ring->q_vector);
4198}
4199
4200/**
4201 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4202 * @pf: pointer to PF struct
4203 *
4204 * LAN VSI has netdev and netdev has TX queues. This function is to check
4205 * each of those TX queues if they are hung, trigger recovery by issuing
4206 * SW interrupt.
4207 **/
4208static void i40e_detect_recover_hung(struct i40e_pf *pf)
4209{
4210 struct net_device *netdev;
4211 struct i40e_vsi *vsi;
4212 int i;
4213
4214 /* Only for LAN VSI */
4215 vsi = pf->vsi[pf->lan_vsi];
4216
4217 if (!vsi)
4218 return;
4219
4220 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4221 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4222 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4223 return;
4224
4225 /* Make sure type is MAIN VSI */
4226 if (vsi->type != I40E_VSI_MAIN)
4227 return;
4228
4229 netdev = vsi->netdev;
4230 if (!netdev)
4231 return;
4232
4233 /* Bail out if netif_carrier is not OK */
4234 if (!netif_carrier_ok(netdev))
4235 return;
4236
4237 /* Go thru' TX queues for netdev */
4238 for (i = 0; i < netdev->num_tx_queues; i++) {
4239 struct netdev_queue *q;
4240
4241 q = netdev_get_tx_queue(netdev, i);
4242 if (q)
4243 i40e_detect_recover_hung_queue(i, vsi);
4244 }
4245}
4246
63d7e5a4
NP		 4247/**
4248 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4249 * @pf: pointer to PF
63d7e5a4
NP		 4250 *
4251 * Get TC map for ISCSI PF type that will include iSCSI TC
4252 * and LAN TC.
4253 **/
4254static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4255{
4256 struct i40e_dcb_app_priority_table app;
4257 struct i40e_hw *hw = &pf->hw;
4258 u8 enabled_tc = 1; /* TC0 is always enabled */
4259 u8 tc, i;
4260 /* Get the iSCSI APP TLV */
4261 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4262
4263 for (i = 0; i < dcbcfg->numapps; i++) {
4264 app = dcbcfg->app[i];
4265 if (app.selector == I40E_APP_SEL_TCPIP &&
4266 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4267 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4268 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4269 break;
4270 }
4271 }
4272
4273 return enabled_tc;
4274}
4275
41c445ff
JB		 4276/**
4277 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4278 * @dcbcfg: the corresponding DCBx configuration structure
4279 *
4280 * Return the number of TCs from given DCBx configuration
4281 **/
4282static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4283{
078b5876
JB		 4284 u8 num_tc = 0;
4285 int i;
41c445ff
JB		 4286
4287 /* Scan the ETS Config Priority Table to find
4288 * traffic class enabled for a given priority
4289 * and use the traffic class index to get the
4290 * number of traffic classes enabled
4291 */
4292 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4293 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4294 num_tc = dcbcfg->etscfg.prioritytable[i];
4295 }
4296
4297 /* Traffic class index starts from zero so
4298 * increment to return the actual count
4299 */
078b5876 4300 return num_tc + 1;
41c445ff
JB		 4301}
4302
4303/**
4304 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4305 * @dcbcfg: the corresponding DCBx configuration structure
4306 *
4307 * Query the current DCB configuration and return the number of
4308 * traffic classes enabled from the given DCBX config
4309 **/
4310static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4311{
4312 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4313 u8 enabled_tc = 1;
4314 u8 i;
4315
4316 for (i = 0; i < num_tc; i++)
41a1d04b 4317 enabled_tc |= BIT(i);
41c445ff
JB		 4318
4319 return enabled_tc;
4320}
4321
4322/**
4323 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4324 * @pf: PF being queried
4325 *
4326 * Return number of traffic classes enabled for the given PF
4327 **/
4328static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4329{
4330 struct i40e_hw *hw = &pf->hw;
4331 u8 i, enabled_tc;
4332 u8 num_tc = 0;
4333 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4334
4335 /* If DCB is not enabled then always in single TC */
4336 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4337 return 1;
4338
63d7e5a4
NP		 4339 /* SFP mode will be enabled for all TCs on port */
4340 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4341 return i40e_dcb_get_num_tc(dcbcfg);
4342
41c445ff 4343 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4344 if (pf->hw.func_caps.iscsi)
4345 enabled_tc = i40e_get_iscsi_tc_map(pf);
4346 else
fc51de96 4347 return 1; /* Only TC0 */
41c445ff 4348
63d7e5a4
NP		 4349 /* At least have TC0 */
4350 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4351 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4352 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4353 num_tc++;
4354 }
4355 return num_tc;
41c445ff
JB		 4356}
4357
4358/**
4359 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4360 * @pf: PF being queried
4361 *
4362 * Return a bitmap for first enabled traffic class for this PF.
4363 **/
4364static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4365{
4366 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4367 u8 i = 0;
4368
4369 if (!enabled_tc)
4370 return 0x1; /* TC0 */
4371
4372 /* Find the first enabled TC */
4373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4374 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4375 break;
4376 }
4377
41a1d04b 4378 return BIT(i);
41c445ff
JB		 4379}
4380
4381/**
4382 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4383 * @pf: PF being queried
4384 *
4385 * Return a bitmap for enabled traffic classes for this PF.
4386 **/
4387static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4388{
4389 /* If DCB is not enabled for this PF then just return default TC */
4390 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4391 return i40e_pf_get_default_tc(pf);
4392
41c445ff 4393 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4394 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4395 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4396
fc51de96 4397 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4398 if (pf->hw.func_caps.iscsi)
4399 return i40e_get_iscsi_tc_map(pf);
4400 else
fc51de96 4401 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4402}
4403
4404/**
4405 * i40e_vsi_get_bw_info - Query VSI BW Information
4406 * @vsi: the VSI being queried
4407 *
4408 * Returns 0 on success, negative value on failure
4409 **/
4410static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4411{
4412 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4413 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4414 struct i40e_pf *pf = vsi->back;
4415 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4416 i40e_status ret;
41c445ff 4417 u32 tc_bw_max;
41c445ff
JB		 4418 int i;
4419
4420 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4421 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4422 if (ret) {
41c445ff 4423 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4424 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4425 i40e_stat_str(&pf->hw, ret),
4426 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4427 return -EINVAL;
41c445ff
JB		 4428 }
4429
4430 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4431 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4432 NULL);
4433 if (ret) {
41c445ff 4434 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4435 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4436 i40e_stat_str(&pf->hw, ret),
4437 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4438 return -EINVAL;
41c445ff
JB		 4439 }
4440
4441 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4442 dev_info(&pf->pdev->dev,
4443 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4444 bw_config.tc_valid_bits,
4445 bw_ets_config.tc_valid_bits);
4446 /* Still continuing */
4447 }
4448
4449 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4450 vsi->bw_max_quanta = bw_config.max_bw;
4451 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4452 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4453 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4454 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4455 vsi->bw_ets_limit_credits[i] =
4456 le16_to_cpu(bw_ets_config.credits[i]);
4457 /* 3 bits out of 4 for each TC */
4458 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4459 }
078b5876 4460
dcae29be 4461 return 0;
41c445ff
JB		 4462}
4463
4464/**
4465 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4466 * @vsi: the VSI being configured
4467 * @enabled_tc: TC bitmap
4468 * @bw_credits: BW shared credits per TC
4469 *
4470 * Returns 0 on success, negative value on failure
4471 **/
dcae29be 4472static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4473 u8 *bw_share)
4474{
4475 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4476 i40e_status ret;
dcae29be 4477 int i;
41c445ff
JB		 4478
4479 bw_data.tc_valid_bits = enabled_tc;
4480 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4481 bw_data.tc_bw_credits[i] = bw_share[i];
4482
f1c7e72e
SN		 4483 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4484 NULL);
4485 if (ret) {
41c445ff 4486 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4487 "AQ command Config VSI BW allocation per TC failed = %d\n",
4488 vsi->back->hw.aq.asq_last_status);
dcae29be 4489 return -EINVAL;
41c445ff
JB		 4490 }
4491
4492 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4493 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4494
dcae29be 4495 return 0;
41c445ff
JB		 4496}
4497
4498/**
4499 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4500 * @vsi: the VSI being configured
4501 * @enabled_tc: TC map to be enabled
4502 *
4503 **/
4504static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4505{
4506 struct net_device *netdev = vsi->netdev;
4507 struct i40e_pf *pf = vsi->back;
4508 struct i40e_hw *hw = &pf->hw;
4509 u8 netdev_tc = 0;
4510 int i;
4511 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4512
4513 if (!netdev)
4514 return;
4515
4516 if (!enabled_tc) {
4517 netdev_reset_tc(netdev);
4518 return;
4519 }
4520
4521 /* Set up actual enabled TCs on the VSI */
4522 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4523 return;
4524
4525 /* set per TC queues for the VSI */
4526 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4527 /* Only set TC queues for enabled tcs
4528 *
4529 * e.g. For a VSI that has TC0 and TC3 enabled the
4530 * enabled_tc bitmap would be 0x00001001; the driver
4531 * will set the numtc for netdev as 2 that will be
4532 * referenced by the netdev layer as TC 0 and 1.
4533 */
41a1d04b 4534 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4535 netdev_set_tc_queue(netdev,
4536 vsi->tc_config.tc_info[i].netdev_tc,
4537 vsi->tc_config.tc_info[i].qcount,
4538 vsi->tc_config.tc_info[i].qoffset);
4539 }
4540
4541 /* Assign UP2TC map for the VSI */
4542 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4543 /* Get the actual TC# for the UP */
4544 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4545 /* Get the mapped netdev TC# for the UP */
4546 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4547 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4548 }
4549}
4550
4551/**
4552 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4553 * @vsi: the VSI being configured
4554 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4555 **/
4556static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4557 struct i40e_vsi_context *ctxt)
4558{
4559 /* copy just the sections touched not the entire info
4560 * since not all sections are valid as returned by
4561 * update vsi params
4562 */
4563 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4564 memcpy(&vsi->info.queue_mapping,
4565 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4566 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4567 sizeof(vsi->info.tc_mapping));
4568}
4569
4570/**
4571 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4572 * @vsi: VSI to be configured
4573 * @enabled_tc: TC bitmap
4574 *
4575 * This configures a particular VSI for TCs that are mapped to the
4576 * given TC bitmap. It uses default bandwidth share for TCs across
4577 * VSIs to configure TC for a particular VSI.
4578 *
4579 * NOTE:
4580 * It is expected that the VSI queues have been quisced before calling
4581 * this function.
4582 **/
4583static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4584{
4585 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4586 struct i40e_vsi_context ctxt;
4587 int ret = 0;
4588 int i;
4589
4590 /* Check if enabled_tc is same as existing or new TCs */
4591 if (vsi->tc_config.enabled_tc == enabled_tc)
4592 return ret;
4593
4594 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4595 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4596 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4597 bw_share[i] = 1;
4598 }
4599
4600 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4601 if (ret) {
4602 dev_info(&vsi->back->pdev->dev,
4603 "Failed configuring TC map %d for VSI %d\n",
4604 enabled_tc, vsi->seid);
4605 goto out;
4606 }
4607
4608 /* Update Queue Pairs Mapping for currently enabled UPs */
4609 ctxt.seid = vsi->seid;
4610 ctxt.pf_num = vsi->back->hw.pf_id;
4611 ctxt.vf_num = 0;
4612 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4613 ctxt.info = vsi->info;
41c445ff
JB		 4614 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4615
4616 /* Update the VSI after updating the VSI queue-mapping information */
4617 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4618 if (ret) {
4619 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4620 "Update vsi tc config failed, err %s aq_err %s\n",
4621 i40e_stat_str(&vsi->back->hw, ret),
4622 i40e_aq_str(&vsi->back->hw,
4623 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4624 goto out;
4625 }
4626 /* update the local VSI info with updated queue map */
4627 i40e_vsi_update_queue_map(vsi, &ctxt);
4628 vsi->info.valid_sections = 0;
4629
4630 /* Update current VSI BW information */
4631 ret = i40e_vsi_get_bw_info(vsi);
4632 if (ret) {
4633 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4634 "Failed updating vsi bw info, err %s aq_err %s\n",
4635 i40e_stat_str(&vsi->back->hw, ret),
4636 i40e_aq_str(&vsi->back->hw,
4637 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4638 goto out;
4639 }
4640
4641 /* Update the netdev TC setup */
4642 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4643out:
4644 return ret;
4645}
4646
4e3b35b0
NP		 4647/**
4648 * i40e_veb_config_tc - Configure TCs for given VEB
4649 * @veb: given VEB
4650 * @enabled_tc: TC bitmap
4651 *
4652 * Configures given TC bitmap for VEB (switching) element
4653 **/
4654int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4655{
4656 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4657 struct i40e_pf *pf = veb->pf;
4658 int ret = 0;
4659 int i;
4660
4661 /* No TCs or already enabled TCs just return */
4662 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4663 return ret;
4664
4665 bw_data.tc_valid_bits = enabled_tc;
4666 /* bw_data.absolute_credits is not set (relative) */
4667
4668 /* Enable ETS TCs with equal BW Share for now */
4669 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4670 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4671 bw_data.tc_bw_share_credits[i] = 1;
4672 }
4673
4674 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4675 &bw_data, NULL);
4676 if (ret) {
4677 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4678 "VEB bw config failed, err %s aq_err %s\n",
4679 i40e_stat_str(&pf->hw, ret),
4680 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4681 goto out;
4682 }
4683
4684 /* Update the BW information */
4685 ret = i40e_veb_get_bw_info(veb);
4686 if (ret) {
4687 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4688 "Failed getting veb bw config, err %s aq_err %s\n",
4689 i40e_stat_str(&pf->hw, ret),
4690 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4691 }
4692
4693out:
4694 return ret;
4695}
4696
4697#ifdef CONFIG_I40E_DCB
4698/**
4699 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4700 * @pf: PF struct
4701 *
4702 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4703 * the caller would've quiesce all the VSIs before calling
4704 * this function
4705 **/
4706static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4707{
4708 u8 tc_map = 0;
4709 int ret;
4710 u8 v;
4711
4712 /* Enable the TCs available on PF to all VEBs */
4713 tc_map = i40e_pf_get_tc_map(pf);
4714 for (v = 0; v < I40E_MAX_VEB; v++) {
4715 if (!pf->veb[v])
4716 continue;
4717 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4718 if (ret) {
4719 dev_info(&pf->pdev->dev,
4720 "Failed configuring TC for VEB seid=%d\n",
4721 pf->veb[v]->seid);
4722 /* Will try to configure as many components */
4723 }
4724 }
4725
4726 /* Update each VSI */
505682cd 4727 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4728 if (!pf->vsi[v])
4729 continue;
4730
4731 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4732#ifdef I40E_FCOE
4733 * - For FCoE VSI only enable the TC configured
4734 * as per the APP TLV
4735#endif
4e3b35b0
NP		 4736 * - For all others keep them at TC0 for now
4737 */
4738 if (v == pf->lan_vsi)
4739 tc_map = i40e_pf_get_tc_map(pf);
4740 else
4741 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4742#ifdef I40E_FCOE
4743 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4744 tc_map = i40e_get_fcoe_tc_map(pf);
4745#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4746
4747 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4748 if (ret) {
4749 dev_info(&pf->pdev->dev,
4750 "Failed configuring TC for VSI seid=%d\n",
4751 pf->vsi[v]->seid);
4752 /* Will try to configure as many components */
4753 } else {
0672a091
NP		 4754 /* Re-configure VSI vectors based on updated TC map */
4755 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4756 if (pf->vsi[v]->netdev)
4757 i40e_dcbnl_set_all(pf->vsi[v]);
4758 }
4759 }
4760}
4761
2fd75f31
NP		 4762/**
4763 * i40e_resume_port_tx - Resume port Tx
4764 * @pf: PF struct
4765 *
4766 * Resume a port's Tx and issue a PF reset in case of failure to
4767 * resume.
4768 **/
4769static int i40e_resume_port_tx(struct i40e_pf *pf)
4770{
4771 struct i40e_hw *hw = &pf->hw;
4772 int ret;
4773
4774 ret = i40e_aq_resume_port_tx(hw, NULL);
4775 if (ret) {
4776 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4777 "Resume Port Tx failed, err %s aq_err %s\n",
4778 i40e_stat_str(&pf->hw, ret),
4779 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4780 /* Schedule PF reset to recover */
4781 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4782 i40e_service_event_schedule(pf);
4783 }
4784
4785 return ret;
4786}
4787
4e3b35b0
NP		 4788/**
4789 * i40e_init_pf_dcb - Initialize DCB configuration
4790 * @pf: PF being configured
4791 *
4792 * Query the current DCB configuration and cache it
4793 * in the hardware structure
4794 **/
4795static int i40e_init_pf_dcb(struct i40e_pf *pf)
4796{
4797 struct i40e_hw *hw = &pf->hw;
4798 int err = 0;
4799
025b4a54
ASJ		 4800 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4801 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4802 (pf->hw.aq.fw_maj_ver < 4))
4803 goto out;
4804
4e3b35b0
NP		 4805 /* Get the initial DCB configuration */
4806 err = i40e_init_dcb(hw);
4807 if (!err) {
4808 /* Device/Function is not DCBX capable */
4809 if ((!hw->func_caps.dcb) ||
4810 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4811 dev_info(&pf->pdev->dev,
4812 "DCBX offload is not supported or is disabled for this PF.\n");
4813
4814 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4815 goto out;
4816
4817 } else {
4818 /* When status is not DISABLED then DCBX in FW */
4819 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4820 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4821
4822 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4823 /* Enable DCB tagging only when more than one TC */
4824 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4825 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4826 dev_dbg(&pf->pdev->dev,
4827 "DCBX offload is supported for this PF.\n");
4e3b35b0 4828 }
014269ff 4829 } else {
aebfc816 4830 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4831 "Query for DCB configuration failed, err %s aq_err %s\n",
4832 i40e_stat_str(&pf->hw, err),
4833 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4834 }
4835
4836out:
4837 return err;
4838}
4839#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4840#define SPEED_SIZE 14
4841#define FC_SIZE 8
4842/**
4843 * i40e_print_link_message - print link up or down
4844 * @vsi: the VSI for which link needs a message
4845 */
c156f856 4846void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 4847{
a9165490
SN		 4848 char *speed = "Unknown";
4849 char *fc = "Unknown";
cf05ed08 4850
c156f856
MJ		 4851 if (vsi->current_isup == isup)
4852 return;
4853 vsi->current_isup = isup;
cf05ed08
JB		 4854 if (!isup) {
4855 netdev_info(vsi->netdev, "NIC Link is Down\n");
4856 return;
4857 }
4858
148c2d80
GR		 4859 /* Warn user if link speed on NPAR enabled partition is not at
4860 * least 10GB
4861 */
4862 if (vsi->back->hw.func_caps.npar_enable &&
4863 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4864 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4865 netdev_warn(vsi->netdev,
4866 "The partition detected link speed that is less than 10Gbps\n");
4867
cf05ed08
JB		 4868 switch (vsi->back->hw.phy.link_info.link_speed) {
4869 case I40E_LINK_SPEED_40GB:
a9165490 4870 speed = "40 G";
cf05ed08 4871 break;
ae24b409 4872 case I40E_LINK_SPEED_20GB:
a9165490 4873 speed = "20 G";
ae24b409 4874 break;
cf05ed08 4875 case I40E_LINK_SPEED_10GB:
a9165490 4876 speed = "10 G";
cf05ed08
JB		 4877 break;
4878 case I40E_LINK_SPEED_1GB:
a9165490 4879 speed = "1000 M";
cf05ed08 4880 break;
5960d33f 4881 case I40E_LINK_SPEED_100MB:
a9165490 4882 speed = "100 M";
5960d33f 4883 break;
cf05ed08
JB		 4884 default:
4885 break;
4886 }
4887
4888 switch (vsi->back->hw.fc.current_mode) {
4889 case I40E_FC_FULL:
a9165490 4890 fc = "RX/TX";
cf05ed08
JB		 4891 break;
4892 case I40E_FC_TX_PAUSE:
a9165490 4893 fc = "TX";
cf05ed08
JB		 4894 break;
4895 case I40E_FC_RX_PAUSE:
a9165490 4896 fc = "RX";
cf05ed08
JB		 4897 break;
4898 default:
a9165490 4899 fc = "None";
cf05ed08
JB		 4900 break;
4901 }
4902
a9165490 4903 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 4904 speed, fc);
4905}
4e3b35b0 4906
41c445ff
JB		 4907/**
4908 * i40e_up_complete - Finish the last steps of bringing up a connection
4909 * @vsi: the VSI being configured
4910 **/
4911static int i40e_up_complete(struct i40e_vsi *vsi)
4912{
4913 struct i40e_pf *pf = vsi->back;
4914 int err;
4915
4916 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4917 i40e_vsi_configure_msix(vsi);
4918 else
4919 i40e_configure_msi_and_legacy(vsi);
4920
4921 /* start rings */
4922 err = i40e_vsi_control_rings(vsi, true);
4923 if (err)
4924 return err;
4925
4926 clear_bit(__I40E_DOWN, &vsi->state);
4927 i40e_napi_enable_all(vsi);
4928 i40e_vsi_enable_irq(vsi);
4929
4930 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4931 (vsi->netdev)) {
cf05ed08 4932 i40e_print_link_message(vsi, true);
41c445ff
JB		 4933 netif_tx_start_all_queues(vsi->netdev);
4934 netif_carrier_on(vsi->netdev);
6d779b41 4935 } else if (vsi->netdev) {
cf05ed08 4936 i40e_print_link_message(vsi, false);
7b592f61
CW		 4937 /* need to check for qualified module here*/
4938 if ((pf->hw.phy.link_info.link_info &
4939 I40E_AQ_MEDIA_AVAILABLE) &&
4940 (!(pf->hw.phy.link_info.an_info &
4941 I40E_AQ_QUALIFIED_MODULE)))
4942 netdev_err(vsi->netdev,
4943 "the driver failed to link because an unqualified module was detected.");
41c445ff 4944 }
ca64fa4e
ASJ		 4945
4946 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4947 if (vsi->type == I40E_VSI_FDIR) {
4948 /* reset fd counters */
4949 pf->fd_add_err = pf->fd_atr_cnt = 0;
4950 if (pf->fd_tcp_rule > 0) {
4951 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4952 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4953 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4954 pf->fd_tcp_rule = 0;
4955 }
ca64fa4e 4956 i40e_fdir_filter_restore(vsi);
1e1be8f6 4957 }
41c445ff
JB		 4958 i40e_service_event_schedule(pf);
4959
4960 return 0;
4961}
4962
4963/**
4964 * i40e_vsi_reinit_locked - Reset the VSI
4965 * @vsi: the VSI being configured
4966 *
4967 * Rebuild the ring structs after some configuration
4968 * has changed, e.g. MTU size.
4969 **/
4970static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4971{
4972 struct i40e_pf *pf = vsi->back;
4973
4974 WARN_ON(in_interrupt());
4975 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4976 usleep_range(1000, 2000);
4977 i40e_down(vsi);
4978
4979 /* Give a VF some time to respond to the reset. The
4980 * two second wait is based upon the watchdog cycle in
4981 * the VF driver.
4982 */
4983 if (vsi->type == I40E_VSI_SRIOV)
4984 msleep(2000);
4985 i40e_up(vsi);
4986 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4987}
4988
4989/**
4990 * i40e_up - Bring the connection back up after being down
4991 * @vsi: the VSI being configured
4992 **/
4993int i40e_up(struct i40e_vsi *vsi)
4994{
4995 int err;
4996
4997 err = i40e_vsi_configure(vsi);
4998 if (!err)
4999 err = i40e_up_complete(vsi);
5000
5001 return err;
5002}
5003
5004/**
5005 * i40e_down - Shutdown the connection processing
5006 * @vsi: the VSI being stopped
5007 **/
5008void i40e_down(struct i40e_vsi *vsi)
5009{
5010 int i;
5011
5012 /* It is assumed that the caller of this function
5013 * sets the vsi->state __I40E_DOWN bit.
5014 */
5015 if (vsi->netdev) {
5016 netif_carrier_off(vsi->netdev);
5017 netif_tx_disable(vsi->netdev);
5018 }
5019 i40e_vsi_disable_irq(vsi);
5020 i40e_vsi_control_rings(vsi, false);
5021 i40e_napi_disable_all(vsi);
5022
5023 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5024 i40e_clean_tx_ring(vsi->tx_rings[i]);
5025 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5026 }
5027}
5028
5029/**
5030 * i40e_setup_tc - configure multiple traffic classes
5031 * @netdev: net device to configure
5032 * @tc: number of traffic classes to enable
5033 **/
38e00438
VD		 5034#ifdef I40E_FCOE
5035int i40e_setup_tc(struct net_device *netdev, u8 tc)
5036#else
41c445ff 5037static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5038#endif
41c445ff
JB		 5039{
5040 struct i40e_netdev_priv *np = netdev_priv(netdev);
5041 struct i40e_vsi *vsi = np->vsi;
5042 struct i40e_pf *pf = vsi->back;
5043 u8 enabled_tc = 0;
5044 int ret = -EINVAL;
5045 int i;
5046
5047 /* Check if DCB enabled to continue */
5048 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5049 netdev_info(netdev, "DCB is not enabled for adapter\n");
5050 goto exit;
5051 }
5052
5053 /* Check if MFP enabled */
5054 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5055 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5056 goto exit;
5057 }
5058
5059 /* Check whether tc count is within enabled limit */
5060 if (tc > i40e_pf_get_num_tc(pf)) {
5061 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5062 goto exit;
5063 }
5064
5065 /* Generate TC map for number of tc requested */
5066 for (i = 0; i < tc; i++)
41a1d04b 5067 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5068
5069 /* Requesting same TC configuration as already enabled */
5070 if (enabled_tc == vsi->tc_config.enabled_tc)
5071 return 0;
5072
5073 /* Quiesce VSI queues */
5074 i40e_quiesce_vsi(vsi);
5075
5076 /* Configure VSI for enabled TCs */
5077 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5078 if (ret) {
5079 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5080 vsi->seid);
5081 goto exit;
5082 }
5083
5084 /* Unquiesce VSI */
5085 i40e_unquiesce_vsi(vsi);
5086
5087exit:
5088 return ret;
5089}
5090
5091/**
5092 * i40e_open - Called when a network interface is made active
5093 * @netdev: network interface device structure
5094 *
5095 * The open entry point is called when a network interface is made
5096 * active by the system (IFF_UP). At this point all resources needed
5097 * for transmit and receive operations are allocated, the interrupt
5098 * handler is registered with the OS, the netdev watchdog subtask is
5099 * enabled, and the stack is notified that the interface is ready.
5100 *
5101 * Returns 0 on success, negative value on failure
5102 **/
38e00438 5103int i40e_open(struct net_device *netdev)
41c445ff
JB		 5104{
5105 struct i40e_netdev_priv *np = netdev_priv(netdev);
5106 struct i40e_vsi *vsi = np->vsi;
5107 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5108 int err;
5109
4eb3f768
SN		 5110 /* disallow open during test or if eeprom is broken */
5111 if (test_bit(__I40E_TESTING, &pf->state) ||
5112 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5113 return -EBUSY;
5114
5115 netif_carrier_off(netdev);
5116
6c167f58
EK		 5117 err = i40e_vsi_open(vsi);
5118 if (err)
5119 return err;
5120
059dab69
JB		 5121 /* configure global TSO hardware offload settings */
5122 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5123 TCP_FLAG_FIN) >> 16);
5124 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5125 TCP_FLAG_FIN |
5126 TCP_FLAG_CWR) >> 16);
5127 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5128
6c167f58
EK		 5129#ifdef CONFIG_I40E_VXLAN
5130 vxlan_get_rx_port(netdev);
5131#endif
5132
5133 return 0;
5134}
5135
5136/**
5137 * i40e_vsi_open -
5138 * @vsi: the VSI to open
5139 *
5140 * Finish initialization of the VSI.
5141 *
5142 * Returns 0 on success, negative value on failure
5143 **/
5144int i40e_vsi_open(struct i40e_vsi *vsi)
5145{
5146 struct i40e_pf *pf = vsi->back;
b294ac70 5147 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5148 int err;
5149
41c445ff
JB		 5150 /* allocate descriptors */
5151 err = i40e_vsi_setup_tx_resources(vsi);
5152 if (err)
5153 goto err_setup_tx;
5154 err = i40e_vsi_setup_rx_resources(vsi);
5155 if (err)
5156 goto err_setup_rx;
5157
5158 err = i40e_vsi_configure(vsi);
5159 if (err)
5160 goto err_setup_rx;
5161
c22e3c6c
SN		 5162 if (vsi->netdev) {
5163 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5164 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5165 err = i40e_vsi_request_irq(vsi, int_name);
5166 if (err)
5167 goto err_setup_rx;
41c445ff 5168
c22e3c6c
SN		 5169 /* Notify the stack of the actual queue counts. */
5170 err = netif_set_real_num_tx_queues(vsi->netdev,
5171 vsi->num_queue_pairs);
5172 if (err)
5173 goto err_set_queues;
25946ddb 5174
c22e3c6c
SN		 5175 err = netif_set_real_num_rx_queues(vsi->netdev,
5176 vsi->num_queue_pairs);
5177 if (err)
5178 goto err_set_queues;
8a9eb7d3
SN		 5179
5180 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5181 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5182 dev_driver_string(&pf->pdev->dev),
5183 dev_name(&pf->pdev->dev));
8a9eb7d3 5184 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5185
c22e3c6c 5186 } else {
ce9ccb17 5187 err = -EINVAL;
6c167f58
EK		 5188 goto err_setup_rx;
5189 }
25946ddb 5190
41c445ff
JB		 5191 err = i40e_up_complete(vsi);
5192 if (err)
5193 goto err_up_complete;
5194
41c445ff
JB		 5195 return 0;
5196
5197err_up_complete:
5198 i40e_down(vsi);
25946ddb 5199err_set_queues:
41c445ff
JB		 5200 i40e_vsi_free_irq(vsi);
5201err_setup_rx:
5202 i40e_vsi_free_rx_resources(vsi);
5203err_setup_tx:
5204 i40e_vsi_free_tx_resources(vsi);
5205 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5206 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5207
5208 return err;
5209}
5210
17a73f6b
JG		 5211/**
5212 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5213 * @pf: Pointer to PF
17a73f6b
JG		 5214 *
5215 * This function destroys the hlist where all the Flow Director
5216 * filters were saved.
5217 **/
5218static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5219{
5220 struct i40e_fdir_filter *filter;
5221 struct hlist_node *node2;
5222
5223 hlist_for_each_entry_safe(filter, node2,
5224 &pf->fdir_filter_list, fdir_node) {
5225 hlist_del(&filter->fdir_node);
5226 kfree(filter);
5227 }
5228 pf->fdir_pf_active_filters = 0;
5229}
5230
41c445ff
JB		 5231/**
5232 * i40e_close - Disables a network interface
5233 * @netdev: network interface device structure
5234 *
5235 * The close entry point is called when an interface is de-activated
5236 * by the OS. The hardware is still under the driver's control, but
5237 * this netdev interface is disabled.
5238 *
5239 * Returns 0, this is not allowed to fail
5240 **/
38e00438
VD		 5241#ifdef I40E_FCOE
5242int i40e_close(struct net_device *netdev)
5243#else
41c445ff 5244static int i40e_close(struct net_device *netdev)
38e00438 5245#endif
41c445ff
JB		 5246{
5247 struct i40e_netdev_priv *np = netdev_priv(netdev);
5248 struct i40e_vsi *vsi = np->vsi;
5249
90ef8d47 5250 i40e_vsi_close(vsi);
41c445ff
JB		 5251
5252 return 0;
5253}
5254
5255/**
5256 * i40e_do_reset - Start a PF or Core Reset sequence
5257 * @pf: board private structure
5258 * @reset_flags: which reset is requested
5259 *
5260 * The essential difference in resets is that the PF Reset
5261 * doesn't clear the packet buffers, doesn't reset the PE
5262 * firmware, and doesn't bother the other PFs on the chip.
5263 **/
5264void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5265{
5266 u32 val;
5267
5268 WARN_ON(in_interrupt());
5269
263fc48f
MW		 5270 if (i40e_check_asq_alive(&pf->hw))
5271 i40e_vc_notify_reset(pf);
5272
41c445ff 5273 /* do the biggest reset indicated */
41a1d04b 5274 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5275
5276 /* Request a Global Reset
5277 *
5278 * This will start the chip's countdown to the actual full
5279 * chip reset event, and a warning interrupt to be sent
5280 * to all PFs, including the requestor. Our handler
5281 * for the warning interrupt will deal with the shutdown
5282 * and recovery of the switch setup.
5283 */
69bfb110 5284 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5285 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5286 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5287 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5288
41a1d04b 5289 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5290
5291 /* Request a Core Reset
5292 *
5293 * Same as Global Reset, except does *not* include the MAC/PHY
5294 */
69bfb110 5295 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5296 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5297 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5298 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5299 i40e_flush(&pf->hw);
5300
41a1d04b 5301 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5302
5303 /* Request a PF Reset
5304 *
5305 * Resets only the PF-specific registers
5306 *
5307 * This goes directly to the tear-down and rebuild of
5308 * the switch, since we need to do all the recovery as
5309 * for the Core Reset.
5310 */
69bfb110 5311 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5312 i40e_handle_reset_warning(pf);
5313
41a1d04b 5314 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5315 int v;
5316
5317 /* Find the VSI(s) that requested a re-init */
5318 dev_info(&pf->pdev->dev,
5319 "VSI reinit requested\n");
505682cd 5320 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5321 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5322
41c445ff
JB		 5323 if (vsi != NULL &&
5324 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5325 i40e_vsi_reinit_locked(pf->vsi[v]);
5326 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5327 }
5328 }
41a1d04b 5329 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5330 int v;
5331
5332 /* Find the VSI(s) that needs to be brought down */
5333 dev_info(&pf->pdev->dev, "VSI down requested\n");
5334 for (v = 0; v < pf->num_alloc_vsi; v++) {
5335 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5336
b5d06f05
NP		 5337 if (vsi != NULL &&
5338 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5339 set_bit(__I40E_DOWN, &vsi->state);
5340 i40e_down(vsi);
5341 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5342 }
5343 }
41c445ff
JB		 5344 } else {
5345 dev_info(&pf->pdev->dev,
5346 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5347 }
5348}
5349
4e3b35b0
NP		 5350#ifdef CONFIG_I40E_DCB
5351/**
5352 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5353 * @pf: board private structure
5354 * @old_cfg: current DCB config
5355 * @new_cfg: new DCB config
5356 **/
5357bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5358 struct i40e_dcbx_config *old_cfg,
5359 struct i40e_dcbx_config *new_cfg)
5360{
5361 bool need_reconfig = false;
5362
5363 /* Check if ETS configuration has changed */
5364 if (memcmp(&new_cfg->etscfg,
5365 &old_cfg->etscfg,
5366 sizeof(new_cfg->etscfg))) {
5367 /* If Priority Table has changed reconfig is needed */
5368 if (memcmp(&new_cfg->etscfg.prioritytable,
5369 &old_cfg->etscfg.prioritytable,
5370 sizeof(new_cfg->etscfg.prioritytable))) {
5371 need_reconfig = true;
69bfb110 5372 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5373 }
5374
5375 if (memcmp(&new_cfg->etscfg.tcbwtable,
5376 &old_cfg->etscfg.tcbwtable,
5377 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5378 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5379
5380 if (memcmp(&new_cfg->etscfg.tsatable,
5381 &old_cfg->etscfg.tsatable,
5382 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5383 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5384 }
5385
5386 /* Check if PFC configuration has changed */
5387 if (memcmp(&new_cfg->pfc,
5388 &old_cfg->pfc,
5389 sizeof(new_cfg->pfc))) {
5390 need_reconfig = true;
69bfb110 5391 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5392 }
5393
5394 /* Check if APP Table has changed */
5395 if (memcmp(&new_cfg->app,
5396 &old_cfg->app,
3d9667a9 5397 sizeof(new_cfg->app))) {
4e3b35b0 5398 need_reconfig = true;
69bfb110 5399 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5400 }
4e3b35b0 5401
fb43201f 5402 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5403 return need_reconfig;
5404}
5405
5406/**
5407 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5408 * @pf: board private structure
5409 * @e: event info posted on ARQ
5410 **/
5411static int i40e_handle_lldp_event(struct i40e_pf *pf,
5412 struct i40e_arq_event_info *e)
5413{
5414 struct i40e_aqc_lldp_get_mib *mib =
5415 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5416 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5417 struct i40e_dcbx_config tmp_dcbx_cfg;
5418 bool need_reconfig = false;
5419 int ret = 0;
5420 u8 type;
5421
4d9b6043
NP		 5422 /* Not DCB capable or capability disabled */
5423 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5424 return ret;
5425
4e3b35b0
NP		 5426 /* Ignore if event is not for Nearest Bridge */
5427 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5428 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5429 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5430 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5431 return ret;
5432
5433 /* Check MIB Type and return if event for Remote MIB update */
5434 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5435 dev_dbg(&pf->pdev->dev,
fb43201f 5436 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5437 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5438 /* Update the remote cached instance and return */
5439 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5440 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5441 &hw->remote_dcbx_config);
5442 goto exit;
5443 }
5444
9fa61dd2 5445 /* Store the old configuration */
1a2f6248 5446 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5447
750fcbcf
NP		 5448 /* Reset the old DCBx configuration data */
5449 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5450 /* Get updated DCBX data from firmware */
5451 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5452 if (ret) {
f1c7e72e
SN		 5453 dev_info(&pf->pdev->dev,
5454 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5455 i40e_stat_str(&pf->hw, ret),
5456 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5457 goto exit;
5458 }
5459
5460 /* No change detected in DCBX configs */
750fcbcf
NP		 5461 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5462 sizeof(tmp_dcbx_cfg))) {
69bfb110 5463 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5464 goto exit;
5465 }
5466
750fcbcf
NP		 5467 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5468 &hw->local_dcbx_config);
4e3b35b0 5469
750fcbcf 5470 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5471
5472 if (!need_reconfig)
5473 goto exit;
5474
4d9b6043 5475 /* Enable DCB tagging only when more than one TC */
750fcbcf 5476 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5477 pf->flags |= I40E_FLAG_DCB_ENABLED;
5478 else
5479 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5480
69129dc3 5481 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5482 /* Reconfiguration needed quiesce all VSIs */
5483 i40e_pf_quiesce_all_vsi(pf);
5484
5485 /* Changes in configuration update VEB/VSI */
5486 i40e_dcb_reconfigure(pf);
5487
2fd75f31
NP		 5488 ret = i40e_resume_port_tx(pf);
5489
69129dc3 5490 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5491 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5492 if (ret)
5493 goto exit;
5494
5495 /* Wait for the PF's Tx queues to be disabled */
5496 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5497 if (ret) {
5498 /* Schedule PF reset to recover */
5499 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5500 i40e_service_event_schedule(pf);
5501 } else {
2fd75f31 5502 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5503 }
5504
4e3b35b0
NP		 5505exit:
5506 return ret;
5507}
5508#endif /* CONFIG_I40E_DCB */
5509
23326186
ASJ		 5510/**
5511 * i40e_do_reset_safe - Protected reset path for userland calls.
5512 * @pf: board private structure
5513 * @reset_flags: which reset is requested
5514 *
5515 **/
5516void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5517{
5518 rtnl_lock();
5519 i40e_do_reset(pf, reset_flags);
5520 rtnl_unlock();
5521}
5522
41c445ff
JB		 5523/**
5524 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5525 * @pf: board private structure
5526 * @e: event info posted on ARQ
5527 *
5528 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5529 * and VF queues
5530 **/
5531static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5532 struct i40e_arq_event_info *e)
5533{
5534 struct i40e_aqc_lan_overflow *data =
5535 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5536 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5537 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5538 struct i40e_hw *hw = &pf->hw;
5539 struct i40e_vf *vf;
5540 u16 vf_id;
5541
69bfb110
JB		 5542 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5543 queue, qtx_ctl);
41c445ff
JB		 5544
5545 /* Queue belongs to VF, find the VF and issue VF reset */
5546 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5547 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5548 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5549 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5550 vf_id -= hw->func_caps.vf_base_id;
5551 vf = &pf->vf[vf_id];
5552 i40e_vc_notify_vf_reset(vf);
5553 /* Allow VF to process pending reset notification */
5554 msleep(20);
5555 i40e_reset_vf(vf, false);
5556 }
5557}
5558
5559/**
5560 * i40e_service_event_complete - Finish up the service event
5561 * @pf: board private structure
5562 **/
5563static void i40e_service_event_complete(struct i40e_pf *pf)
5564{
5565 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5566
5567 /* flush memory to make sure state is correct before next watchog */
4e857c58 5568 smp_mb__before_atomic();
41c445ff
JB		 5569 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5570}
5571
55a5e60b 5572/**
12957388
ASJ		 5573 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5574 * @pf: board private structure
5575 **/
04294e38 5576u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5577{
04294e38 5578 u32 val, fcnt_prog;
12957388
ASJ		 5579
5580 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5581 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5582 return fcnt_prog;
5583}
5584
5585/**
04294e38 5586 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5587 * @pf: board private structure
5588 **/
04294e38 5589u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5590{
04294e38
ASJ		 5591 u32 val, fcnt_prog;
5592
55a5e60b
ASJ		 5593 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5594 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5595 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5596 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5597 return fcnt_prog;
5598}
1e1be8f6 5599
04294e38
ASJ		 5600/**
5601 * i40e_get_global_fd_count - Get total FD filters programmed on device
5602 * @pf: board private structure
5603 **/
5604u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5605{
5606 u32 val, fcnt_prog;
5607
5608 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5609 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5610 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5611 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5612 return fcnt_prog;
5613}
5614
55a5e60b
ASJ		 5615/**
5616 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5617 * @pf: board private structure
5618 **/
5619void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5620{
3487b6c3 5621 struct i40e_fdir_filter *filter;
55a5e60b 5622 u32 fcnt_prog, fcnt_avail;
3487b6c3 5623 struct hlist_node *node;
55a5e60b 5624
1e1be8f6
ASJ		 5625 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5626 return;
5627
55a5e60b
ASJ		 5628 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5629 * to re-enable
5630 */
04294e38 5631 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5632 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5633 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5634 (pf->fd_add_err == 0) ||
5635 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5636 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5637 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5638 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5639 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5640 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5641 }
5642 }
5643 /* Wait for some more space to be available to turn on ATR */
5644 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5645 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5646 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5647 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5648 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5649 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5650 }
5651 }
3487b6c3
CW		 5652
5653 /* if hw had a problem adding a filter, delete it */
5654 if (pf->fd_inv > 0) {
5655 hlist_for_each_entry_safe(filter, node,
5656 &pf->fdir_filter_list, fdir_node) {
5657 if (filter->fd_id == pf->fd_inv) {
5658 hlist_del(&filter->fdir_node);
5659 kfree(filter);
5660 pf->fdir_pf_active_filters--;
5661 }
5662 }
5663 }
55a5e60b
ASJ		 5664}
5665
1e1be8f6 5666#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5667#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5668/**
5669 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5670 * @pf: board private structure
5671 **/
5672static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5673{
04294e38 5674 unsigned long min_flush_time;
1e1be8f6 5675 int flush_wait_retry = 50;
04294e38
ASJ		 5676 bool disable_atr = false;
5677 int fd_room;
1e1be8f6
ASJ		 5678 int reg;
5679
1790ed0c
AA		 5680 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5681 return;
5682
a5fdaf34
JB		 5683 if (!time_after(jiffies, pf->fd_flush_timestamp +
5684 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5685 return;
04294e38 5686
a5fdaf34
JB		 5687 /* If the flush is happening too quick and we have mostly SB rules we
5688 * should not re-enable ATR for some time.
5689 */
5690 min_flush_time = pf->fd_flush_timestamp +
5691 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5692 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5693
5694 if (!(time_after(jiffies, min_flush_time)) &&
5695 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5696 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5697 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5698 disable_atr = true;
5699 }
5700
5701 pf->fd_flush_timestamp = jiffies;
5702 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5703 /* flush all filters */
5704 wr32(&pf->hw, I40E_PFQF_CTL_1,
5705 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5706 i40e_flush(&pf->hw);
5707 pf->fd_flush_cnt++;
5708 pf->fd_add_err = 0;
5709 do {
5710 /* Check FD flush status every 5-6msec */
5711 usleep_range(5000, 6000);
5712 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5713 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5714 break;
5715 } while (flush_wait_retry--);
5716 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5717 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5718 } else {
5719 /* replay sideband filters */
5720 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5721 if (!disable_atr)
5722 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5723 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5724 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5725 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5726 }
a5fdaf34 5727
1e1be8f6
ASJ		 5728}
5729
5730/**
5731 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5732 * @pf: board private structure
5733 **/
04294e38 5734u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5735{
5736 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5737}
5738
5739/* We can see up to 256 filter programming desc in transit if the filters are
5740 * being applied really fast; before we see the first
5741 * filter miss error on Rx queue 0. Accumulating enough error messages before
5742 * reacting will make sure we don't cause flush too often.
5743 */
5744#define I40E_MAX_FD_PROGRAM_ERROR 256
5745
41c445ff
JB		 5746/**
5747 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5748 * @pf: board private structure
5749 **/
5750static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5751{
41c445ff 5752
41c445ff
JB		 5753 /* if interface is down do nothing */
5754 if (test_bit(__I40E_DOWN, &pf->state))
5755 return;
1e1be8f6 5756
1790ed0c
AA		 5757 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5758 return;
5759
04294e38 5760 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5761 i40e_fdir_flush_and_replay(pf);
5762
55a5e60b
ASJ		 5763 i40e_fdir_check_and_reenable(pf);
5764
41c445ff
JB		 5765}
5766
5767/**
5768 * i40e_vsi_link_event - notify VSI of a link event
5769 * @vsi: vsi to be notified
5770 * @link_up: link up or down
5771 **/
5772static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5773{
32b5b811 5774 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5775 return;
5776
5777 switch (vsi->type) {
5778 case I40E_VSI_MAIN:
38e00438
VD		 5779#ifdef I40E_FCOE
5780 case I40E_VSI_FCOE:
5781#endif
41c445ff
JB		 5782 if (!vsi->netdev || !vsi->netdev_registered)
5783 break;
5784
5785 if (link_up) {
5786 netif_carrier_on(vsi->netdev);
5787 netif_tx_wake_all_queues(vsi->netdev);
5788 } else {
5789 netif_carrier_off(vsi->netdev);
5790 netif_tx_stop_all_queues(vsi->netdev);
5791 }
5792 break;
5793
5794 case I40E_VSI_SRIOV:
41c445ff
JB		 5795 case I40E_VSI_VMDQ2:
5796 case I40E_VSI_CTRL:
5797 case I40E_VSI_MIRROR:
5798 default:
5799 /* there is no notification for other VSIs */
5800 break;
5801 }
5802}
5803
5804/**
5805 * i40e_veb_link_event - notify elements on the veb of a link event
5806 * @veb: veb to be notified
5807 * @link_up: link up or down
5808 **/
5809static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5810{
5811 struct i40e_pf *pf;
5812 int i;
5813
5814 if (!veb || !veb->pf)
5815 return;
5816 pf = veb->pf;
5817
5818 /* depth first... */
5819 for (i = 0; i < I40E_MAX_VEB; i++)
5820 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5821 i40e_veb_link_event(pf->veb[i], link_up);
5822
5823 /* ... now the local VSIs */
505682cd 5824 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5825 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5826 i40e_vsi_link_event(pf->vsi[i], link_up);
5827}
5828
5829/**
5830 * i40e_link_event - Update netif_carrier status
5831 * @pf: board private structure
5832 **/
5833static void i40e_link_event(struct i40e_pf *pf)
5834{
320684cd 5835 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5836 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 5837 i40e_status status;
5838 bool new_link, old_link;
41c445ff 5839
1e701e09
JB		 5840 /* set this to force the get_link_status call to refresh state */
5841 pf->hw.phy.get_link_info = true;
5842
41c445ff 5843 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 5844
5845 status = i40e_get_link_status(&pf->hw, &new_link);
5846 if (status) {
5847 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
5848 status);
5849 return;
5850 }
5851
fef59ddf
CS		 5852 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5853 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5854
1e701e09 5855 if (new_link == old_link &&
fef59ddf 5856 new_link_speed == old_link_speed &&
320684cd
MW		 5857 (test_bit(__I40E_DOWN, &vsi->state) ||
5858 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5859 return;
320684cd
MW		 5860
5861 if (!test_bit(__I40E_DOWN, &vsi->state))
5862 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5863
5864 /* Notify the base of the switch tree connected to
5865 * the link. Floating VEBs are not notified.
5866 */
5867 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5868 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5869 else
320684cd 5870 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5871
5872 if (pf->vf)
5873 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5874
5875 if (pf->flags & I40E_FLAG_PTP)
5876 i40e_ptp_set_increment(pf);
41c445ff
JB		 5877}
5878
41c445ff 5879/**
21536717 5880 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5881 * @pf: board private structure
5882 **/
5883static void i40e_watchdog_subtask(struct i40e_pf *pf)
5884{
5885 int i;
5886
5887 /* if interface is down do nothing */
5888 if (test_bit(__I40E_DOWN, &pf->state) ||
5889 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5890 return;
5891
21536717
SN		 5892 /* make sure we don't do these things too often */
5893 if (time_before(jiffies, (pf->service_timer_previous +
5894 pf->service_timer_period)))
5895 return;
5896 pf->service_timer_previous = jiffies;
5897
9ac77266
SN		 5898 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
5899 i40e_link_event(pf);
21536717 5900
41c445ff
JB		 5901 /* Update the stats for active netdevs so the network stack
5902 * can look at updated numbers whenever it cares to
5903 */
505682cd 5904 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5905 if (pf->vsi[i] && pf->vsi[i]->netdev)
5906 i40e_update_stats(pf->vsi[i]);
5907
d1a8d275
ASJ		 5908 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
5909 /* Update the stats for the active switching components */
5910 for (i = 0; i < I40E_MAX_VEB; i++)
5911 if (pf->veb[i])
5912 i40e_update_veb_stats(pf->veb[i]);
5913 }
beb0dff1
JK		 5914
5915 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5916}
5917
5918/**
5919 * i40e_reset_subtask - Set up for resetting the device and driver
5920 * @pf: board private structure
5921 **/
5922static void i40e_reset_subtask(struct i40e_pf *pf)
5923{
5924 u32 reset_flags = 0;
5925
23326186 5926 rtnl_lock();
41c445ff 5927 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5928 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5929 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5930 }
5931 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5932 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5933 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5934 }
5935 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5936 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5937 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5938 }
5939 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5940 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5941 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5942 }
b5d06f05 5943 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5944 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5945 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5946 }
41c445ff
JB		 5947
5948 /* If there's a recovery already waiting, it takes
5949 * precedence before starting a new reset sequence.
5950 */
5951 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5952 i40e_handle_reset_warning(pf);
23326186 5953 goto unlock;
41c445ff
JB		 5954 }
5955
5956 /* If we're already down or resetting, just bail */
5957 if (reset_flags &&
5958 !test_bit(__I40E_DOWN, &pf->state) &&
5959 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5960 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5961
5962unlock:
5963 rtnl_unlock();
41c445ff
JB		 5964}
5965
5966/**
5967 * i40e_handle_link_event - Handle link event
5968 * @pf: board private structure
5969 * @e: event info posted on ARQ
5970 **/
5971static void i40e_handle_link_event(struct i40e_pf *pf,
5972 struct i40e_arq_event_info *e)
5973{
5974 struct i40e_hw *hw = &pf->hw;
5975 struct i40e_aqc_get_link_status *status =
5976 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5977
5978 /* save off old link status information */
1a2f6248 5979 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5980
1e701e09
JB		 5981 /* Do a new status request to re-enable LSE reporting
5982 * and load new status information into the hw struct
5983 * This completely ignores any state information
5984 * in the ARQ event info, instead choosing to always
5985 * issue the AQ update link status command.
5986 */
5987 i40e_link_event(pf);
5988
7b592f61
CW		 5989 /* check for unqualified module, if link is down */
5990 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5991 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5992 (!(status->link_info & I40E_AQ_LINK_UP)))
5993 dev_err(&pf->pdev->dev,
5994 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5995}
5996
5997/**
5998 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5999 * @pf: board private structure
6000 **/
6001static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6002{
6003 struct i40e_arq_event_info event;
6004 struct i40e_hw *hw = &pf->hw;
6005 u16 pending, i = 0;
6006 i40e_status ret;
6007 u16 opcode;
86df242b 6008 u32 oldval;
41c445ff
JB		 6009 u32 val;
6010
a316f651
ASJ		 6011 /* Do not run clean AQ when PF reset fails */
6012 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6013 return;
6014
86df242b
SN		 6015 /* check for error indications */
6016 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6017 oldval = val;
6018 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6019 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6020 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6021 }
6022 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6023 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6024 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6025 }
6026 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6027 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6028 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6029 }
6030 if (oldval != val)
6031 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6032
6033 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6034 oldval = val;
6035 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6036 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6037 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6038 }
6039 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6040 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6041 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6042 }
6043 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6044 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6045 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6046 }
6047 if (oldval != val)
6048 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6049
1001dc37
MW		 6050 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6051 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6052 if (!event.msg_buf)
6053 return;
6054
6055 do {
6056 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6057 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6058 break;
56497978 6059 else if (ret) {
41c445ff
JB		 6060 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6061 break;
6062 }
6063
6064 opcode = le16_to_cpu(event.desc.opcode);
6065 switch (opcode) {
6066
6067 case i40e_aqc_opc_get_link_status:
6068 i40e_handle_link_event(pf, &event);
6069 break;
6070 case i40e_aqc_opc_send_msg_to_pf:
6071 ret = i40e_vc_process_vf_msg(pf,
6072 le16_to_cpu(event.desc.retval),
6073 le32_to_cpu(event.desc.cookie_high),
6074 le32_to_cpu(event.desc.cookie_low),
6075 event.msg_buf,
1001dc37 6076 event.msg_len);
41c445ff
JB		 6077 break;
6078 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6079 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6080#ifdef CONFIG_I40E_DCB
6081 rtnl_lock();
6082 ret = i40e_handle_lldp_event(pf, &event);
6083 rtnl_unlock();
6084#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6085 break;
6086 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6087 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6088 i40e_handle_lan_overflow_event(pf, &event);
6089 break;
0467bc91
SN		 6090 case i40e_aqc_opc_send_msg_to_peer:
6091 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6092 break;
91a0f930
SN		 6093 case i40e_aqc_opc_nvm_erase:
6094 case i40e_aqc_opc_nvm_update:
6095 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6096 break;
41c445ff
JB		 6097 default:
6098 dev_info(&pf->pdev->dev,
0467bc91
SN		 6099 "ARQ Error: Unknown event 0x%04x received\n",
6100 opcode);
41c445ff
JB		 6101 break;
6102 }
6103 } while (pending && (i++ < pf->adminq_work_limit));
6104
6105 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6106 /* re-enable Admin queue interrupt cause */
6107 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6108 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6109 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6110 i40e_flush(hw);
6111
6112 kfree(event.msg_buf);
6113}
6114
4eb3f768
SN		 6115/**
6116 * i40e_verify_eeprom - make sure eeprom is good to use
6117 * @pf: board private structure
6118 **/
6119static void i40e_verify_eeprom(struct i40e_pf *pf)
6120{
6121 int err;
6122
6123 err = i40e_diag_eeprom_test(&pf->hw);
6124 if (err) {
6125 /* retry in case of garbage read */
6126 err = i40e_diag_eeprom_test(&pf->hw);
6127 if (err) {
6128 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6129 err);
6130 set_bit(__I40E_BAD_EEPROM, &pf->state);
6131 }
6132 }
6133
6134 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6135 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6136 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6137 }
6138}
6139
386a0afa
AA		 6140/**
6141 * i40e_enable_pf_switch_lb
b40c82e6 6142 * @pf: pointer to the PF structure
386a0afa
AA		 6143 *
6144 * enable switch loop back or die - no point in a return value
6145 **/
6146static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6147{
6148 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6149 struct i40e_vsi_context ctxt;
f1c7e72e 6150 int ret;
386a0afa
AA		 6151
6152 ctxt.seid = pf->main_vsi_seid;
6153 ctxt.pf_num = pf->hw.pf_id;
6154 ctxt.vf_num = 0;
f1c7e72e
SN		 6155 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6156 if (ret) {
386a0afa 6157 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6158 "couldn't get PF vsi config, err %s aq_err %s\n",
6159 i40e_stat_str(&pf->hw, ret),
6160 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6161 return;
6162 }
6163 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6164 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6165 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6166
f1c7e72e
SN		 6167 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6168 if (ret) {
386a0afa 6169 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6170 "update vsi switch failed, err %s aq_err %s\n",
6171 i40e_stat_str(&pf->hw, ret),
6172 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6173 }
6174}
6175
6176/**
6177 * i40e_disable_pf_switch_lb
b40c82e6 6178 * @pf: pointer to the PF structure
386a0afa
AA		 6179 *
6180 * disable switch loop back or die - no point in a return value
6181 **/
6182static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6183{
6184 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6185 struct i40e_vsi_context ctxt;
f1c7e72e 6186 int ret;
386a0afa
AA		 6187
6188 ctxt.seid = pf->main_vsi_seid;
6189 ctxt.pf_num = pf->hw.pf_id;
6190 ctxt.vf_num = 0;
f1c7e72e
SN		 6191 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6192 if (ret) {
386a0afa 6193 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6194 "couldn't get PF vsi config, err %s aq_err %s\n",
6195 i40e_stat_str(&pf->hw, ret),
6196 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6197 return;
6198 }
6199 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6200 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6201 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6202
f1c7e72e
SN		 6203 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6204 if (ret) {
386a0afa 6205 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6206 "update vsi switch failed, err %s aq_err %s\n",
6207 i40e_stat_str(&pf->hw, ret),
6208 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6209 }
6210}
6211
51616018
NP		 6212/**
6213 * i40e_config_bridge_mode - Configure the HW bridge mode
6214 * @veb: pointer to the bridge instance
6215 *
6216 * Configure the loop back mode for the LAN VSI that is downlink to the
6217 * specified HW bridge instance. It is expected this function is called
6218 * when a new HW bridge is instantiated.
6219 **/
6220static void i40e_config_bridge_mode(struct i40e_veb *veb)
6221{
6222 struct i40e_pf *pf = veb->pf;
6223
6dec1017
SN		 6224 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6225 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6226 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6227 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6228 i40e_disable_pf_switch_lb(pf);
6229 else
6230 i40e_enable_pf_switch_lb(pf);
6231}
6232
41c445ff
JB		 6233/**
6234 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6235 * @veb: pointer to the VEB instance
6236 *
6237 * This is a recursive function that first builds the attached VSIs then
6238 * recurses in to build the next layer of VEB. We track the connections
6239 * through our own index numbers because the seid's from the HW could
6240 * change across the reset.
6241 **/
6242static int i40e_reconstitute_veb(struct i40e_veb *veb)
6243{
6244 struct i40e_vsi *ctl_vsi = NULL;
6245 struct i40e_pf *pf = veb->pf;
6246 int v, veb_idx;
6247 int ret;
6248
6249 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6250 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6251 if (pf->vsi[v] &&
6252 pf->vsi[v]->veb_idx == veb->idx &&
6253 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6254 ctl_vsi = pf->vsi[v];
6255 break;
6256 }
6257 }
6258 if (!ctl_vsi) {
6259 dev_info(&pf->pdev->dev,
6260 "missing owner VSI for veb_idx %d\n", veb->idx);
6261 ret = -ENOENT;
6262 goto end_reconstitute;
6263 }
6264 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6265 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6266 ret = i40e_add_vsi(ctl_vsi);
6267 if (ret) {
6268 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6269 "rebuild of veb_idx %d owner VSI failed: %d\n",
6270 veb->idx, ret);
41c445ff
JB		 6271 goto end_reconstitute;
6272 }
6273 i40e_vsi_reset_stats(ctl_vsi);
6274
6275 /* create the VEB in the switch and move the VSI onto the VEB */
6276 ret = i40e_add_veb(veb, ctl_vsi);
6277 if (ret)
6278 goto end_reconstitute;
6279
fc60861e
ASJ		 6280 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6281 veb->bridge_mode = BRIDGE_MODE_VEB;
6282 else
6283 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6284 i40e_config_bridge_mode(veb);
b64ba084 6285
41c445ff 6286 /* create the remaining VSIs attached to this VEB */
505682cd 6287 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6288 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6289 continue;
6290
6291 if (pf->vsi[v]->veb_idx == veb->idx) {
6292 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6293
41c445ff
JB		 6294 vsi->uplink_seid = veb->seid;
6295 ret = i40e_add_vsi(vsi);
6296 if (ret) {
6297 dev_info(&pf->pdev->dev,
6298 "rebuild of vsi_idx %d failed: %d\n",
6299 v, ret);
6300 goto end_reconstitute;
6301 }
6302 i40e_vsi_reset_stats(vsi);
6303 }
6304 }
6305
6306 /* create any VEBs attached to this VEB - RECURSION */
6307 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6308 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6309 pf->veb[veb_idx]->uplink_seid = veb->seid;
6310 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6311 if (ret)
6312 break;
6313 }
6314 }
6315
6316end_reconstitute:
6317 return ret;
6318}
6319
6320/**
6321 * i40e_get_capabilities - get info about the HW
6322 * @pf: the PF struct
6323 **/
6324static int i40e_get_capabilities(struct i40e_pf *pf)
6325{
6326 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6327 u16 data_size;
6328 int buf_len;
6329 int err;
6330
6331 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6332 do {
6333 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6334 if (!cap_buf)
6335 return -ENOMEM;
6336
6337 /* this loads the data into the hw struct for us */
6338 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6339 &data_size,
6340 i40e_aqc_opc_list_func_capabilities,
6341 NULL);
6342 /* data loaded, buffer no longer needed */
6343 kfree(cap_buf);
6344
6345 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6346 /* retry with a larger buffer */
6347 buf_len = data_size;
6348 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6349 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6350 "capability discovery failed, err %s aq_err %s\n",
6351 i40e_stat_str(&pf->hw, err),
6352 i40e_aq_str(&pf->hw,
6353 pf->hw.aq.asq_last_status));
41c445ff
JB		 6354 return -ENODEV;
6355 }
6356 } while (err);
6357
6358 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6359 dev_info(&pf->pdev->dev,
6360 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6361 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6362 pf->hw.func_caps.num_msix_vectors,
6363 pf->hw.func_caps.num_msix_vectors_vf,
6364 pf->hw.func_caps.fd_filters_guaranteed,
6365 pf->hw.func_caps.fd_filters_best_effort,
6366 pf->hw.func_caps.num_tx_qp,
6367 pf->hw.func_caps.num_vsis);
6368
7134f9ce
JB		 6369#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6370 + pf->hw.func_caps.num_vfs)
6371 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6372 dev_info(&pf->pdev->dev,
6373 "got num_vsis %d, setting num_vsis to %d\n",
6374 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6375 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6376 }
6377
41c445ff
JB		 6378 return 0;
6379}
6380
cbf61325
ASJ		 6381static int i40e_vsi_clear(struct i40e_vsi *vsi);
6382
41c445ff 6383/**
cbf61325 6384 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6385 * @pf: board private structure
6386 **/
cbf61325 6387static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6388{
6389 struct i40e_vsi *vsi;
8a9eb7d3 6390 int i;
41c445ff 6391
407e063c
JB		 6392 /* quick workaround for an NVM issue that leaves a critical register
6393 * uninitialized
6394 */
6395 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6396 static const u32 hkey[] = {
6397 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6398 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6399 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6400 0x95b3a76d};
6401
6402 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6403 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6404 }
6405
cbf61325 6406 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6407 return;
6408
cbf61325 6409 /* find existing VSI and see if it needs configuring */
41c445ff 6410 vsi = NULL;
505682cd 6411 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6412 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6413 vsi = pf->vsi[i];
cbf61325
ASJ		 6414 break;
6415 }
6416 }
6417
6418 /* create a new VSI if none exists */
41c445ff 6419 if (!vsi) {
cbf61325
ASJ		 6420 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6421 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6422 if (!vsi) {
6423 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6424 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6425 return;
41c445ff 6426 }
cbf61325 6427 }
41c445ff 6428
8a9eb7d3 6429 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6430}
6431
6432/**
6433 * i40e_fdir_teardown - release the Flow Director resources
6434 * @pf: board private structure
6435 **/
6436static void i40e_fdir_teardown(struct i40e_pf *pf)
6437{
6438 int i;
6439
17a73f6b 6440 i40e_fdir_filter_exit(pf);
505682cd 6441 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6442 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6443 i40e_vsi_release(pf->vsi[i]);
6444 break;
6445 }
6446 }
6447}
6448
6449/**
f650a38b 6450 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6451 * @pf: board private structure
6452 *
b40c82e6 6453 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6454 **/
23cfbe07 6455static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6456{
41c445ff 6457 struct i40e_hw *hw = &pf->hw;
60442dea 6458 i40e_status ret = 0;
41c445ff
JB		 6459 u32 v;
6460
6461 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6462 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6463 return;
41c445ff 6464
69bfb110 6465 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6466
41c445ff
JB		 6467 /* quiesce the VSIs and their queues that are not already DOWN */
6468 i40e_pf_quiesce_all_vsi(pf);
6469
505682cd 6470 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6471 if (pf->vsi[v])
6472 pf->vsi[v]->seid = 0;
6473 }
6474
6475 i40e_shutdown_adminq(&pf->hw);
6476
f650a38b 6477 /* call shutdown HMC */
60442dea
SN		 6478 if (hw->hmc.hmc_obj) {
6479 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6480 if (ret)
60442dea
SN		 6481 dev_warn(&pf->pdev->dev,
6482 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6483 }
f650a38b
ASJ		 6484}
6485
44033fac
JB		 6486/**
6487 * i40e_send_version - update firmware with driver version
6488 * @pf: PF struct
6489 */
6490static void i40e_send_version(struct i40e_pf *pf)
6491{
6492 struct i40e_driver_version dv;
6493
6494 dv.major_version = DRV_VERSION_MAJOR;
6495 dv.minor_version = DRV_VERSION_MINOR;
6496 dv.build_version = DRV_VERSION_BUILD;
6497 dv.subbuild_version = 0;
35a7d804 6498 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6499 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6500}
6501
f650a38b 6502/**
4dda12e6 6503 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6504 * @pf: board private structure
bc7d338f 6505 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6506 **/
bc7d338f 6507static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6508{
f650a38b 6509 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6510 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6511 i40e_status ret;
6512 u32 v;
6513
41c445ff
JB		 6514 /* Now we wait for GRST to settle out.
6515 * We don't have to delete the VEBs or VSIs from the hw switch
6516 * because the reset will make them disappear.
6517 */
6518 ret = i40e_pf_reset(hw);
b5565400 6519 if (ret) {
41c445ff 6520 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6521 set_bit(__I40E_RESET_FAILED, &pf->state);
6522 goto clear_recovery;
b5565400 6523 }
41c445ff
JB		 6524 pf->pfr_count++;
6525
6526 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6527 goto clear_recovery;
69bfb110 6528 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6529
6530 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6531 ret = i40e_init_adminq(&pf->hw);
6532 if (ret) {
f1c7e72e
SN		 6533 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6534 i40e_stat_str(&pf->hw, ret),
6535 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6536 goto clear_recovery;
41c445ff
JB		 6537 }
6538
4eb3f768 6539 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6540 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6541 i40e_verify_eeprom(pf);
4eb3f768 6542
e78ac4bf 6543 i40e_clear_pxe_mode(hw);
41c445ff 6544 ret = i40e_get_capabilities(pf);
f1c7e72e 6545 if (ret)
41c445ff 6546 goto end_core_reset;
41c445ff 6547
41c445ff
JB		 6548 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6549 hw->func_caps.num_rx_qp,
6550 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6551 if (ret) {
6552 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6553 goto end_core_reset;
6554 }
6555 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6556 if (ret) {
6557 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6558 goto end_core_reset;
6559 }
6560
4e3b35b0
NP		 6561#ifdef CONFIG_I40E_DCB
6562 ret = i40e_init_pf_dcb(pf);
6563 if (ret) {
aebfc816
SN		 6564 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6565 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6566 /* Continue without DCB enabled */
4e3b35b0
NP		 6567 }
6568#endif /* CONFIG_I40E_DCB */
38e00438 6569#ifdef I40E_FCOE
21364bcf 6570 i40e_init_pf_fcoe(pf);
4e3b35b0 6571
38e00438 6572#endif
41c445ff 6573 /* do basic switch setup */
bc7d338f 6574 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6575 if (ret)
6576 goto end_core_reset;
6577
7e2453fe
JB		 6578 /* driver is only interested in link up/down and module qualification
6579 * reports from firmware
6580 */
6581 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6582 I40E_AQ_EVENT_LINK_UPDOWN |
6583 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6584 if (ret)
f1c7e72e
SN		 6585 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6586 i40e_stat_str(&pf->hw, ret),
6587 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6588
cafa2ee6
ASJ		 6589 /* make sure our flow control settings are restored */
6590 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6591 if (ret)
8279e495
NP		 6592 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6593 i40e_stat_str(&pf->hw, ret),
6594 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6595
41c445ff
JB		 6596 /* Rebuild the VSIs and VEBs that existed before reset.
6597 * They are still in our local switch element arrays, so only
6598 * need to rebuild the switch model in the HW.
6599 *
6600 * If there were VEBs but the reconstitution failed, we'll try
6601 * try to recover minimal use by getting the basic PF VSI working.
6602 */
6603 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6604 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6605 /* find the one VEB connected to the MAC, and find orphans */
6606 for (v = 0; v < I40E_MAX_VEB; v++) {
6607 if (!pf->veb[v])
6608 continue;
6609
6610 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6611 pf->veb[v]->uplink_seid == 0) {
6612 ret = i40e_reconstitute_veb(pf->veb[v]);
6613
6614 if (!ret)
6615 continue;
6616
6617 /* If Main VEB failed, we're in deep doodoo,
6618 * so give up rebuilding the switch and set up
6619 * for minimal rebuild of PF VSI.
6620 * If orphan failed, we'll report the error
6621 * but try to keep going.
6622 */
6623 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6624 dev_info(&pf->pdev->dev,
6625 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6626 ret);
6627 pf->vsi[pf->lan_vsi]->uplink_seid
6628 = pf->mac_seid;
6629 break;
6630 } else if (pf->veb[v]->uplink_seid == 0) {
6631 dev_info(&pf->pdev->dev,
6632 "rebuild of orphan VEB failed: %d\n",
6633 ret);
6634 }
6635 }
6636 }
6637 }
6638
6639 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6640 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6641 /* no VEB, so rebuild only the Main VSI */
6642 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6643 if (ret) {
6644 dev_info(&pf->pdev->dev,
6645 "rebuild of Main VSI failed: %d\n", ret);
6646 goto end_core_reset;
6647 }
6648 }
6649
025b4a54
ASJ		 6650 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6651 (pf->hw.aq.fw_maj_ver < 4)) {
6652 msleep(75);
6653 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6654 if (ret)
f1c7e72e
SN		 6655 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6656 i40e_stat_str(&pf->hw, ret),
6657 i40e_aq_str(&pf->hw,
6658 pf->hw.aq.asq_last_status));
cafa2ee6 6659 }
41c445ff
JB		 6660 /* reinit the misc interrupt */
6661 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6662 ret = i40e_setup_misc_vector(pf);
6663
6664 /* restart the VSIs that were rebuilt and running before the reset */
6665 i40e_pf_unquiesce_all_vsi(pf);
6666
69f64b2b
MW		 6667 if (pf->num_alloc_vfs) {
6668 for (v = 0; v < pf->num_alloc_vfs; v++)
6669 i40e_reset_vf(&pf->vf[v], true);
6670 }
6671
41c445ff 6672 /* tell the firmware that we're starting */
44033fac 6673 i40e_send_version(pf);
41c445ff
JB		 6674
6675end_core_reset:
a316f651
ASJ		 6676 clear_bit(__I40E_RESET_FAILED, &pf->state);
6677clear_recovery:
41c445ff
JB		 6678 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6679}
6680
f650a38b 6681/**
b40c82e6 6682 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6683 * @pf: board private structure
6684 *
6685 * Close up the VFs and other things in prep for a Core Reset,
6686 * then get ready to rebuild the world.
6687 **/
6688static void i40e_handle_reset_warning(struct i40e_pf *pf)
6689{
23cfbe07
SN		 6690 i40e_prep_for_reset(pf);
6691 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6692}
6693
41c445ff
JB		 6694/**
6695 * i40e_handle_mdd_event
b40c82e6 6696 * @pf: pointer to the PF structure
41c445ff
JB		 6697 *
6698 * Called from the MDD irq handler to identify possibly malicious vfs
6699 **/
6700static void i40e_handle_mdd_event(struct i40e_pf *pf)
6701{
6702 struct i40e_hw *hw = &pf->hw;
6703 bool mdd_detected = false;
df430b12 6704 bool pf_mdd_detected = false;
41c445ff
JB		 6705 struct i40e_vf *vf;
6706 u32 reg;
6707 int i;
6708
6709 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6710 return;
6711
6712 /* find what triggered the MDD event */
6713 reg = rd32(hw, I40E_GL_MDET_TX);
6714 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6715 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6716 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6717 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6718 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6719 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6720 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6721 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6722 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6723 pf->hw.func_caps.base_queue;
faf32978 6724 if (netif_msg_tx_err(pf))
b40c82e6 6725 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6726 event, queue, pf_num, vf_num);
41c445ff
JB		 6727 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6728 mdd_detected = true;
6729 }
6730 reg = rd32(hw, I40E_GL_MDET_RX);
6731 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6732 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6733 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6734 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6735 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6736 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6737 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6738 pf->hw.func_caps.base_queue;
faf32978
JB		 6739 if (netif_msg_rx_err(pf))
6740 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6741 event, queue, func);
41c445ff
JB		 6742 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6743 mdd_detected = true;
6744 }
6745
df430b12
NP		 6746 if (mdd_detected) {
6747 reg = rd32(hw, I40E_PF_MDET_TX);
6748 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6749 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6750 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6751 pf_mdd_detected = true;
6752 }
6753 reg = rd32(hw, I40E_PF_MDET_RX);
6754 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6755 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6756 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6757 pf_mdd_detected = true;
6758 }
6759 /* Queue belongs to the PF, initiate a reset */
6760 if (pf_mdd_detected) {
6761 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6762 i40e_service_event_schedule(pf);
6763 }
6764 }
6765
41c445ff
JB		 6766 /* see if one of the VFs needs its hand slapped */
6767 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6768 vf = &(pf->vf[i]);
6769 reg = rd32(hw, I40E_VP_MDET_TX(i));
6770 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6771 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6772 vf->num_mdd_events++;
faf32978
JB		 6773 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6774 i);
41c445ff
JB		 6775 }
6776
6777 reg = rd32(hw, I40E_VP_MDET_RX(i));
6778 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6779 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6780 vf->num_mdd_events++;
faf32978
JB		 6781 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6782 i);
41c445ff
JB		 6783 }
6784
6785 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6786 dev_info(&pf->pdev->dev,
6787 "Too many MDD events on VF %d, disabled\n", i);
6788 dev_info(&pf->pdev->dev,
6789 "Use PF Control I/F to re-enable the VF\n");
6790 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6791 }
6792 }
6793
6794 /* re-enable mdd interrupt cause */
6795 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6796 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6797 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6798 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6799 i40e_flush(hw);
6800}
6801
a1c9a9d9
JK		 6802#ifdef CONFIG_I40E_VXLAN
6803/**
6804 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6805 * @pf: board private structure
6806 **/
6807static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6808{
a1c9a9d9
JK		 6809 struct i40e_hw *hw = &pf->hw;
6810 i40e_status ret;
a1c9a9d9
JK		 6811 __be16 port;
6812 int i;
6813
6814 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6815 return;
6816
6817 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6818
6819 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6820 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6821 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6822 port = pf->vxlan_ports[i];
c22c06c8
SN		 6823 if (port)
6824 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6825 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6826 NULL, NULL);
6827 else
6828 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6829
6830 if (ret) {
c22c06c8 6831 dev_info(&pf->pdev->dev,
f1c7e72e 6832 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6833 port ? "add" : "delete",
f1c7e72e
SN		 6834 ntohs(port), i,
6835 i40e_stat_str(&pf->hw, ret),
6836 i40e_aq_str(&pf->hw,
6837 pf->hw.aq.asq_last_status));
a1c9a9d9 6838 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6839 }
6840 }
6841 }
6842}
6843
6844#endif
41c445ff
JB		 6845/**
6846 * i40e_service_task - Run the driver's async subtasks
6847 * @work: pointer to work_struct containing our data
6848 **/
6849static void i40e_service_task(struct work_struct *work)
6850{
6851 struct i40e_pf *pf = container_of(work,
6852 struct i40e_pf,
6853 service_task);
6854 unsigned long start_time = jiffies;
6855
e57a2fea
SN		 6856 /* don't bother with service tasks if a reset is in progress */
6857 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6858 i40e_service_event_complete(pf);
6859 return;
6860 }
6861
b03a8c1f 6862 i40e_detect_recover_hung(pf);
41c445ff
JB		 6863 i40e_reset_subtask(pf);
6864 i40e_handle_mdd_event(pf);
6865 i40e_vc_process_vflr_event(pf);
6866 i40e_watchdog_subtask(pf);
6867 i40e_fdir_reinit_subtask(pf);
41c445ff 6868 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6869#ifdef CONFIG_I40E_VXLAN
6870 i40e_sync_vxlan_filters_subtask(pf);
6871#endif
41c445ff
JB		 6872 i40e_clean_adminq_subtask(pf);
6873
6874 i40e_service_event_complete(pf);
6875
6876 /* If the tasks have taken longer than one timer cycle or there
6877 * is more work to be done, reschedule the service task now
6878 * rather than wait for the timer to tick again.
6879 */
6880 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6881 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6882 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6883 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6884 i40e_service_event_schedule(pf);
6885}
6886
6887/**
6888 * i40e_service_timer - timer callback
6889 * @data: pointer to PF struct
6890 **/
6891static void i40e_service_timer(unsigned long data)
6892{
6893 struct i40e_pf *pf = (struct i40e_pf *)data;
6894
6895 mod_timer(&pf->service_timer,
6896 round_jiffies(jiffies + pf->service_timer_period));
6897 i40e_service_event_schedule(pf);
6898}
6899
6900/**
6901 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6902 * @vsi: the VSI being configured
6903 **/
6904static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6905{
6906 struct i40e_pf *pf = vsi->back;
6907
6908 switch (vsi->type) {
6909 case I40E_VSI_MAIN:
6910 vsi->alloc_queue_pairs = pf->num_lan_qps;
6911 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6912 I40E_REQ_DESCRIPTOR_MULTIPLE);
6913 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6914 vsi->num_q_vectors = pf->num_lan_msix;
6915 else
6916 vsi->num_q_vectors = 1;
6917
6918 break;
6919
6920 case I40E_VSI_FDIR:
6921 vsi->alloc_queue_pairs = 1;
6922 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6923 I40E_REQ_DESCRIPTOR_MULTIPLE);
6924 vsi->num_q_vectors = 1;
6925 break;
6926
6927 case I40E_VSI_VMDQ2:
6928 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6929 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6930 I40E_REQ_DESCRIPTOR_MULTIPLE);
6931 vsi->num_q_vectors = pf->num_vmdq_msix;
6932 break;
6933
6934 case I40E_VSI_SRIOV:
6935 vsi->alloc_queue_pairs = pf->num_vf_qps;
6936 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6937 I40E_REQ_DESCRIPTOR_MULTIPLE);
6938 break;
6939
38e00438
VD		 6940#ifdef I40E_FCOE
6941 case I40E_VSI_FCOE:
6942 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6943 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6944 I40E_REQ_DESCRIPTOR_MULTIPLE);
6945 vsi->num_q_vectors = pf->num_fcoe_msix;
6946 break;
6947
6948#endif /* I40E_FCOE */
41c445ff
JB		 6949 default:
6950 WARN_ON(1);
6951 return -ENODATA;
6952 }
6953
6954 return 0;
6955}
6956
f650a38b
ASJ		 6957/**
6958 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6959 * @type: VSI pointer
bc7d338f 6960 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6961 *
6962 * On error: returns error code (negative)
6963 * On success: returns 0
6964 **/
bc7d338f 6965static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6966{
6967 int size;
6968 int ret = 0;
6969
ac6c5e3d 6970 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6971 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6972 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6973 if (!vsi->tx_rings)
6974 return -ENOMEM;
f650a38b
ASJ		 6975 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6976
bc7d338f
ASJ		 6977 if (alloc_qvectors) {
6978 /* allocate memory for q_vector pointers */
f57e4fbd 6979 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6980 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6981 if (!vsi->q_vectors) {
6982 ret = -ENOMEM;
6983 goto err_vectors;
6984 }
f650a38b
ASJ		 6985 }
6986 return ret;
6987
6988err_vectors:
6989 kfree(vsi->tx_rings);
6990 return ret;
6991}
6992
41c445ff
JB		 6993/**
6994 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6995 * @pf: board private structure
6996 * @type: type of VSI
6997 *
6998 * On error: returns error code (negative)
6999 * On success: returns vsi index in PF (positive)
7000 **/
7001static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7002{
7003 int ret = -ENODEV;
7004 struct i40e_vsi *vsi;
7005 int vsi_idx;
7006 int i;
7007
7008 /* Need to protect the allocation of the VSIs at the PF level */
7009 mutex_lock(&pf->switch_mutex);
7010
7011 /* VSI list may be fragmented if VSI creation/destruction has
7012 * been happening. We can afford to do a quick scan to look
7013 * for any free VSIs in the list.
7014 *
7015 * find next empty vsi slot, looping back around if necessary
7016 */
7017 i = pf->next_vsi;
505682cd 7018 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7019 i++;
505682cd 7020 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7021 i = 0;
7022 while (i < pf->next_vsi && pf->vsi[i])
7023 i++;
7024 }
7025
505682cd 7026 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7027 vsi_idx = i; /* Found one! */
7028 } else {
7029 ret = -ENODEV;
493fb300 7030 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7031 }
7032 pf->next_vsi = ++i;
7033
7034 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7035 if (!vsi) {
7036 ret = -ENOMEM;
493fb300 7037 goto unlock_pf;
41c445ff
JB		 7038 }
7039 vsi->type = type;
7040 vsi->back = pf;
7041 set_bit(__I40E_DOWN, &vsi->state);
7042 vsi->flags = 0;
7043 vsi->idx = vsi_idx;
7044 vsi->rx_itr_setting = pf->rx_itr_default;
7045 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7046 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7047 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7048 pf->rss_table_size : 64;
41c445ff
JB		 7049 vsi->netdev_registered = false;
7050 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7051 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7052 vsi->irqs_ready = false;
41c445ff 7053
9f65e15b
AD		 7054 ret = i40e_set_num_rings_in_vsi(vsi);
7055 if (ret)
7056 goto err_rings;
7057
bc7d338f 7058 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7059 if (ret)
9f65e15b 7060 goto err_rings;
493fb300 7061
41c445ff
JB		 7062 /* Setup default MSIX irq handler for VSI */
7063 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7064
7065 pf->vsi[vsi_idx] = vsi;
7066 ret = vsi_idx;
493fb300
AD		 7067 goto unlock_pf;
7068
9f65e15b 7069err_rings:
493fb300
AD		 7070 pf->next_vsi = i - 1;
7071 kfree(vsi);
7072unlock_pf:
41c445ff
JB		 7073 mutex_unlock(&pf->switch_mutex);
7074 return ret;
7075}
7076
f650a38b
ASJ		 7077/**
7078 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7079 * @type: VSI pointer
bc7d338f 7080 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7081 *
7082 * On error: returns error code (negative)
7083 * On success: returns 0
7084 **/
bc7d338f 7085static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7086{
7087 /* free the ring and vector containers */
bc7d338f
ASJ		 7088 if (free_qvectors) {
7089 kfree(vsi->q_vectors);
7090 vsi->q_vectors = NULL;
7091 }
f650a38b
ASJ		 7092 kfree(vsi->tx_rings);
7093 vsi->tx_rings = NULL;
7094 vsi->rx_rings = NULL;
7095}
7096
41c445ff
JB		 7097/**
7098 * i40e_vsi_clear - Deallocate the VSI provided
7099 * @vsi: the VSI being un-configured
7100 **/
7101static int i40e_vsi_clear(struct i40e_vsi *vsi)
7102{
7103 struct i40e_pf *pf;
7104
7105 if (!vsi)
7106 return 0;
7107
7108 if (!vsi->back)
7109 goto free_vsi;
7110 pf = vsi->back;
7111
7112 mutex_lock(&pf->switch_mutex);
7113 if (!pf->vsi[vsi->idx]) {
7114 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7115 vsi->idx, vsi->idx, vsi, vsi->type);
7116 goto unlock_vsi;
7117 }
7118
7119 if (pf->vsi[vsi->idx] != vsi) {
7120 dev_err(&pf->pdev->dev,
7121 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7122 pf->vsi[vsi->idx]->idx,
7123 pf->vsi[vsi->idx],
7124 pf->vsi[vsi->idx]->type,
7125 vsi->idx, vsi, vsi->type);
7126 goto unlock_vsi;
7127 }
7128
b40c82e6 7129 /* updates the PF for this cleared vsi */
41c445ff
JB		 7130 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7131 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7132
bc7d338f 7133 i40e_vsi_free_arrays(vsi, true);
493fb300 7134
41c445ff
JB		 7135 pf->vsi[vsi->idx] = NULL;
7136 if (vsi->idx < pf->next_vsi)
7137 pf->next_vsi = vsi->idx;
7138
7139unlock_vsi:
7140 mutex_unlock(&pf->switch_mutex);
7141free_vsi:
7142 kfree(vsi);
7143
7144 return 0;
7145}
7146
9f65e15b
AD		 7147/**
7148 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7149 * @vsi: the VSI being cleaned
7150 **/
be1d5eea 7151static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7152{
7153 int i;
7154
8e9dca53 7155 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7156 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7157 kfree_rcu(vsi->tx_rings[i], rcu);
7158 vsi->tx_rings[i] = NULL;
7159 vsi->rx_rings[i] = NULL;
7160 }
be1d5eea 7161 }
9f65e15b
AD		 7162}
7163
41c445ff
JB		 7164/**
7165 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7166 * @vsi: the VSI being configured
7167 **/
7168static int i40e_alloc_rings(struct i40e_vsi *vsi)
7169{
e7046ee1 7170 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7171 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7172 int i;
7173
41c445ff 7174 /* Set basic values in the rings to be used later during open() */
d7397644 7175 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7176 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7177 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7178 if (!tx_ring)
7179 goto err_out;
41c445ff
JB		 7180
7181 tx_ring->queue_index = i;
7182 tx_ring->reg_idx = vsi->base_queue + i;
7183 tx_ring->ring_active = false;
7184 tx_ring->vsi = vsi;
7185 tx_ring->netdev = vsi->netdev;
7186 tx_ring->dev = &pf->pdev->dev;
7187 tx_ring->count = vsi->num_desc;
7188 tx_ring->size = 0;
7189 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7190 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7191 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7192 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7193 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7194 vsi->tx_rings[i] = tx_ring;
41c445ff 7195
9f65e15b 7196 rx_ring = &tx_ring[1];
41c445ff
JB		 7197 rx_ring->queue_index = i;
7198 rx_ring->reg_idx = vsi->base_queue + i;
7199 rx_ring->ring_active = false;
7200 rx_ring->vsi = vsi;
7201 rx_ring->netdev = vsi->netdev;
7202 rx_ring->dev = &pf->pdev->dev;
7203 rx_ring->count = vsi->num_desc;
7204 rx_ring->size = 0;
7205 rx_ring->dcb_tc = 0;
7206 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7207 set_ring_16byte_desc_enabled(rx_ring);
7208 else
7209 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7210 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7211 }
7212
7213 return 0;
9f65e15b
AD		 7214
7215err_out:
7216 i40e_vsi_clear_rings(vsi);
7217 return -ENOMEM;
41c445ff
JB		 7218}
7219
7220/**
7221 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7222 * @pf: board private structure
7223 * @vectors: the number of MSI-X vectors to request
7224 *
7225 * Returns the number of vectors reserved, or error
7226 **/
7227static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7228{
7b37f376
AG		 7229 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7230 I40E_MIN_MSIX, vectors);
7231 if (vectors < 0) {
41c445ff 7232 dev_info(&pf->pdev->dev,
7b37f376 7233 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7234 vectors = 0;
7235 }
7236
7237 return vectors;
7238}
7239
7240/**
7241 * i40e_init_msix - Setup the MSIX capability
7242 * @pf: board private structure
7243 *
7244 * Work with the OS to set up the MSIX vectors needed.
7245 *
3b444399 7246 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7247 **/
7248static int i40e_init_msix(struct i40e_pf *pf)
7249{
41c445ff 7250 struct i40e_hw *hw = &pf->hw;
1e200e4a 7251 int vectors_left;
41c445ff 7252 int v_budget, i;
3b444399 7253 int v_actual;
41c445ff
JB		 7254
7255 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7256 return -ENODEV;
7257
7258 /* The number of vectors we'll request will be comprised of:
7259 * - Add 1 for "other" cause for Admin Queue events, etc.
7260 * - The number of LAN queue pairs
f8ff1464
ASJ		 7261 * - Queues being used for RSS.
7262 * We don't need as many as max_rss_size vectors.
7263 * use rss_size instead in the calculation since that
7264 * is governed by number of cpus in the system.
7265 * - assumes symmetric Tx/Rx pairing
41c445ff 7266 * - The number of VMDq pairs
38e00438
VD		 7267#ifdef I40E_FCOE
7268 * - The number of FCOE qps.
7269#endif
41c445ff
JB		 7270 * Once we count this up, try the request.
7271 *
7272 * If we can't get what we want, we'll simplify to nearly nothing
7273 * and try again. If that still fails, we punt.
7274 */
1e200e4a
SN		 7275 vectors_left = hw->func_caps.num_msix_vectors;
7276 v_budget = 0;
7277
7278 /* reserve one vector for miscellaneous handler */
7279 if (vectors_left) {
7280 v_budget++;
7281 vectors_left--;
7282 }
7283
7284 /* reserve vectors for the main PF traffic queues */
7285 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7286 vectors_left -= pf->num_lan_msix;
7287 v_budget += pf->num_lan_msix;
7288
7289 /* reserve one vector for sideband flow director */
7290 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7291 if (vectors_left) {
7292 v_budget++;
7293 vectors_left--;
7294 } else {
7295 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7296 }
7297 }
83840e4b 7298
38e00438 7299#ifdef I40E_FCOE
1e200e4a 7300 /* can we reserve enough for FCoE? */
38e00438 7301 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7302 if (!vectors_left)
7303 pf->num_fcoe_msix = 0;
7304 else if (vectors_left >= pf->num_fcoe_qps)
7305 pf->num_fcoe_msix = pf->num_fcoe_qps;
7306 else
7307 pf->num_fcoe_msix = 1;
38e00438 7308 v_budget += pf->num_fcoe_msix;
1e200e4a 7309 vectors_left -= pf->num_fcoe_msix;
38e00438 7310 }
1e200e4a 7311
38e00438 7312#endif
1e200e4a
SN		 7313 /* any vectors left over go for VMDq support */
7314 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7315 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7316 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7317
7318 /* if we're short on vectors for what's desired, we limit
7319 * the queues per vmdq. If this is still more than are
7320 * available, the user will need to change the number of
7321 * queues/vectors used by the PF later with the ethtool
7322 * channels command
7323 */
7324 if (vmdq_vecs < vmdq_vecs_wanted)
7325 pf->num_vmdq_qps = 1;
7326 pf->num_vmdq_msix = pf->num_vmdq_qps;
7327
7328 v_budget += vmdq_vecs;
7329 vectors_left -= vmdq_vecs;
7330 }
41c445ff
JB		 7331
7332 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7333 GFP_KERNEL);
7334 if (!pf->msix_entries)
7335 return -ENOMEM;
7336
7337 for (i = 0; i < v_budget; i++)
7338 pf->msix_entries[i].entry = i;
3b444399 7339 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7340
3b444399 7341 if (v_actual != v_budget) {
a34977ba
ASJ		 7342 /* If we have limited resources, we will start with no vectors
7343 * for the special features and then allocate vectors to some
7344 * of these features based on the policy and at the end disable
7345 * the features that did not get any vectors.
7346 */
38e00438
VD		 7347#ifdef I40E_FCOE
7348 pf->num_fcoe_qps = 0;
7349 pf->num_fcoe_msix = 0;
7350#endif
a34977ba
ASJ		 7351 pf->num_vmdq_msix = 0;
7352 }
7353
3b444399 7354 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7355 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7356 kfree(pf->msix_entries);
7357 pf->msix_entries = NULL;
7358 return -ENODEV;
7359
3b444399 7360 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7361 /* Adjust for minimal MSIX use */
41c445ff
JB		 7362 pf->num_vmdq_vsis = 0;
7363 pf->num_vmdq_qps = 0;
41c445ff
JB		 7364 pf->num_lan_qps = 1;
7365 pf->num_lan_msix = 1;
7366
3b444399
SN		 7367 } else if (v_actual != v_budget) {
7368 int vec;
7369
a34977ba 7370 /* reserve the misc vector */
3b444399 7371 vec = v_actual - 1;
a34977ba 7372
41c445ff
JB		 7373 /* Scale vector usage down */
7374 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7375 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7376 pf->num_vmdq_qps = 1;
7377 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7378
7379 /* partition out the remaining vectors */
7380 switch (vec) {
7381 case 2:
41c445ff
JB		 7382 pf->num_lan_msix = 1;
7383 break;
7384 case 3:
38e00438
VD		 7385#ifdef I40E_FCOE
7386 /* give one vector to FCoE */
7387 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7388 pf->num_lan_msix = 1;
7389 pf->num_fcoe_msix = 1;
7390 }
7391#else
41c445ff 7392 pf->num_lan_msix = 2;
38e00438 7393#endif
41c445ff
JB		 7394 break;
7395 default:
38e00438
VD		 7396#ifdef I40E_FCOE
7397 /* give one vector to FCoE */
7398 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7399 pf->num_fcoe_msix = 1;
7400 vec--;
7401 }
7402#endif
1e200e4a
SN		 7403 /* give the rest to the PF */
7404 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7405 break;
7406 }
7407 }
7408
a34977ba
ASJ		 7409 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7410 (pf->num_vmdq_msix == 0)) {
7411 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7412 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7413 }
38e00438
VD		 7414#ifdef I40E_FCOE
7415
7416 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7417 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7418 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7419 }
7420#endif
3b444399 7421 return v_actual;
41c445ff
JB		 7422}
7423
493fb300 7424/**
90e04070 7425 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7426 * @vsi: the VSI being configured
7427 * @v_idx: index of the vector in the vsi struct
7428 *
7429 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7430 **/
90e04070 7431static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7432{
7433 struct i40e_q_vector *q_vector;
7434
7435 /* allocate q_vector */
7436 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7437 if (!q_vector)
7438 return -ENOMEM;
7439
7440 q_vector->vsi = vsi;
7441 q_vector->v_idx = v_idx;
7442 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7443 if (vsi->netdev)
7444 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7445 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7446
cd0b6fa6
AD		 7447 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7448 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7449
493fb300
AD		 7450 /* tie q_vector and vsi together */
7451 vsi->q_vectors[v_idx] = q_vector;
7452
7453 return 0;
7454}
7455
41c445ff 7456/**
90e04070 7457 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7458 * @vsi: the VSI being configured
7459 *
7460 * We allocate one q_vector per queue interrupt. If allocation fails we
7461 * return -ENOMEM.
7462 **/
90e04070 7463static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7464{
7465 struct i40e_pf *pf = vsi->back;
7466 int v_idx, num_q_vectors;
493fb300 7467 int err;
41c445ff
JB		 7468
7469 /* if not MSIX, give the one vector only to the LAN VSI */
7470 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7471 num_q_vectors = vsi->num_q_vectors;
7472 else if (vsi == pf->vsi[pf->lan_vsi])
7473 num_q_vectors = 1;
7474 else
7475 return -EINVAL;
7476
41c445ff 7477 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7478 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7479 if (err)
7480 goto err_out;
41c445ff
JB		 7481 }
7482
7483 return 0;
493fb300
AD		 7484
7485err_out:
7486 while (v_idx--)
7487 i40e_free_q_vector(vsi, v_idx);
7488
7489 return err;
41c445ff
JB		 7490}
7491
7492/**
7493 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7494 * @pf: board private structure to initialize
7495 **/
c1147280 7496static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7497{
3b444399
SN		 7498 int vectors = 0;
7499 ssize_t size;
41c445ff
JB		 7500
7501 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7502 vectors = i40e_init_msix(pf);
7503 if (vectors < 0) {
60ea5f83 7504 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7505#ifdef I40E_FCOE
7506 I40E_FLAG_FCOE_ENABLED |
7507#endif
60ea5f83 7508 I40E_FLAG_RSS_ENABLED |
4d9b6043 7509 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7510 I40E_FLAG_SRIOV_ENABLED |
7511 I40E_FLAG_FD_SB_ENABLED |
7512 I40E_FLAG_FD_ATR_ENABLED |
7513 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7514
7515 /* rework the queue expectations without MSIX */
7516 i40e_determine_queue_usage(pf);
7517 }
7518 }
7519
7520 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7521 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7522 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7523 vectors = pci_enable_msi(pf->pdev);
7524 if (vectors < 0) {
7525 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7526 vectors);
41c445ff
JB		 7527 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7528 }
3b444399 7529 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7530 }
7531
958a3e3b 7532 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7533 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7534
3b444399
SN		 7535 /* set up vector assignment tracking */
7536 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7537 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7538 if (!pf->irq_pile) {
7539 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7540 return -ENOMEM;
7541 }
3b444399
SN		 7542 pf->irq_pile->num_entries = vectors;
7543 pf->irq_pile->search_hint = 0;
7544
c1147280 7545 /* track first vector for misc interrupts, ignore return */
3b444399 7546 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7547
7548 return 0;
41c445ff
JB		 7549}
7550
7551/**
7552 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7553 * @pf: board private structure
7554 *
7555 * This sets up the handler for MSIX 0, which is used to manage the
7556 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7557 * when in MSI or Legacy interrupt mode.
7558 **/
7559static int i40e_setup_misc_vector(struct i40e_pf *pf)
7560{
7561 struct i40e_hw *hw = &pf->hw;
7562 int err = 0;
7563
7564 /* Only request the irq if this is the first time through, and
7565 * not when we're rebuilding after a Reset
7566 */
7567 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7568 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7569 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7570 if (err) {
7571 dev_info(&pf->pdev->dev,
77fa28be 7572 "request_irq for %s failed: %d\n",
b294ac70 7573 pf->int_name, err);
41c445ff
JB		 7574 return -EFAULT;
7575 }
7576 }
7577
ab437b5a 7578 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7579
7580 /* associate no queues to the misc vector */
7581 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7582 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7583
7584 i40e_flush(hw);
7585
7586 i40e_irq_dynamic_enable_icr0(pf);
7587
7588 return err;
7589}
7590
7591/**
e25d00b8
ASJ		 7592 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7593 * @vsi: vsi structure
7594 * @seed: RSS hash seed
7595 **/
7596static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7597{
7598 struct i40e_aqc_get_set_rss_key_data rss_key;
7599 struct i40e_pf *pf = vsi->back;
7600 struct i40e_hw *hw = &pf->hw;
7601 bool pf_lut = false;
7602 u8 *rss_lut;
7603 int ret, i;
7604
7605 memset(&rss_key, 0, sizeof(rss_key));
7606 memcpy(&rss_key, seed, sizeof(rss_key));
7607
7608 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7609 if (!rss_lut)
7610 return -ENOMEM;
7611
7612 /* Populate the LUT with max no. of queues in round robin fashion */
7613 for (i = 0; i < vsi->rss_table_size; i++)
7614 rss_lut[i] = i % vsi->rss_size;
7615
7616 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7617 if (ret) {
7618 dev_info(&pf->pdev->dev,
7619 "Cannot set RSS key, err %s aq_err %s\n",
7620 i40e_stat_str(&pf->hw, ret),
7621 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7622 goto config_rss_aq_out;
e25d00b8
ASJ		 7623 }
7624
7625 if (vsi->type == I40E_VSI_MAIN)
7626 pf_lut = true;
7627
7628 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7629 vsi->rss_table_size);
7630 if (ret)
7631 dev_info(&pf->pdev->dev,
7632 "Cannot set RSS lut, err %s aq_err %s\n",
7633 i40e_stat_str(&pf->hw, ret),
7634 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7635
126b63d9
AS		 7636config_rss_aq_out:
7637 kfree(rss_lut);
e25d00b8
ASJ		 7638 return ret;
7639}
7640
7641/**
7642 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7643 * @vsi: VSI structure
7644 **/
7645static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7646{
7647 u8 seed[I40E_HKEY_ARRAY_SIZE];
7648 struct i40e_pf *pf = vsi->back;
7649
7650 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7651 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7652
7653 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7654 return i40e_config_rss_aq(vsi, seed);
7655
7656 return 0;
7657}
7658
7659/**
7660 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7661 * @pf: board private structure
e25d00b8 7662 * @seed: RSS hash seed
41c445ff 7663 **/
e25d00b8 7664static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7665{
66ddcffb 7666 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7667 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7668 u32 *seed_dw = (u32 *)seed;
7669 u32 current_queue = 0;
4617e8c0
ASJ		 7670 u32 lut = 0;
7671 int i, j;
41c445ff 7672
e25d00b8 7673 /* Fill out hash function seed */
41c445ff 7674 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7675 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7676
7677 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7678 lut = 0;
7679 for (j = 0; j < 4; j++) {
7680 if (current_queue == vsi->rss_size)
7681 current_queue = 0;
7682 lut |= ((current_queue) << (8 * j));
7683 current_queue++;
7684 }
7685 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7686 }
7687 i40e_flush(hw);
7688
7689 return 0;
7690}
7691
7692/**
7693 * i40e_config_rss - Prepare for RSS if used
7694 * @pf: board private structure
7695 **/
7696static int i40e_config_rss(struct i40e_pf *pf)
7697{
7698 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7699 u8 seed[I40E_HKEY_ARRAY_SIZE];
7700 struct i40e_hw *hw = &pf->hw;
7701 u32 reg_val;
7702 u64 hena;
7703
7704 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7705
7706 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7707 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7708 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7709 hena |= i40e_pf_get_default_rss_hena(pf);
7710
41c445ff
JB		 7711 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7712 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7713
66ddcffb
ASJ		 7714 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7715
e25d00b8 7716 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7717 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7718 reg_val = (pf->rss_table_size == 512) ?
7719 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7720 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7721 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7722
e25d00b8
ASJ		 7723 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7724 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7725 else
7726 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7727}
7728
f8ff1464
ASJ		 7729/**
7730 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7731 * @pf: board private structure
7732 * @queue_count: the requested queue count for rss.
7733 *
7734 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7735 * count which may be different from the requested queue count.
7736 **/
7737int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7738{
9a3bd2f1
ASJ		 7739 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7740 int new_rss_size;
7741
f8ff1464
ASJ		 7742 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7743 return 0;
7744
9a3bd2f1 7745 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7746
9a3bd2f1
ASJ		 7747 if (queue_count != vsi->num_queue_pairs) {
7748 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7749 i40e_prep_for_reset(pf);
7750
9a3bd2f1 7751 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7752
7753 i40e_reset_and_rebuild(pf, true);
7754 i40e_config_rss(pf);
7755 }
7756 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7757 return pf->rss_size;
7758}
7759
f4492db1
GR		 7760/**
7761 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7762 * @pf: board private structure
7763 **/
7764i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7765{
7766 i40e_status status;
7767 bool min_valid, max_valid;
7768 u32 max_bw, min_bw;
7769
7770 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7771 &min_valid, &max_valid);
7772
7773 if (!status) {
7774 if (min_valid)
7775 pf->npar_min_bw = min_bw;
7776 if (max_valid)
7777 pf->npar_max_bw = max_bw;
7778 }
7779
7780 return status;
7781}
7782
7783/**
7784 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7785 * @pf: board private structure
7786 **/
7787i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7788{
7789 struct i40e_aqc_configure_partition_bw_data bw_data;
7790 i40e_status status;
7791
b40c82e6 7792 /* Set the valid bit for this PF */
41a1d04b 7793 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7794 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7795 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7796
7797 /* Set the new bandwidths */
7798 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7799
7800 return status;
7801}
7802
7803/**
7804 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7805 * @pf: board private structure
7806 **/
7807i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7808{
7809 /* Commit temporary BW setting to permanent NVM image */
7810 enum i40e_admin_queue_err last_aq_status;
7811 i40e_status ret;
7812 u16 nvm_word;
7813
7814 if (pf->hw.partition_id != 1) {
7815 dev_info(&pf->pdev->dev,
7816 "Commit BW only works on partition 1! This is partition %d",
7817 pf->hw.partition_id);
7818 ret = I40E_NOT_SUPPORTED;
7819 goto bw_commit_out;
7820 }
7821
7822 /* Acquire NVM for read access */
7823 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7824 last_aq_status = pf->hw.aq.asq_last_status;
7825 if (ret) {
7826 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7827 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7828 i40e_stat_str(&pf->hw, ret),
7829 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7830 goto bw_commit_out;
7831 }
7832
7833 /* Read word 0x10 of NVM - SW compatibility word 1 */
7834 ret = i40e_aq_read_nvm(&pf->hw,
7835 I40E_SR_NVM_CONTROL_WORD,
7836 0x10, sizeof(nvm_word), &nvm_word,
7837 false, NULL);
7838 /* Save off last admin queue command status before releasing
7839 * the NVM
7840 */
7841 last_aq_status = pf->hw.aq.asq_last_status;
7842 i40e_release_nvm(&pf->hw);
7843 if (ret) {
f1c7e72e
SN		 7844 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7845 i40e_stat_str(&pf->hw, ret),
7846 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7847 goto bw_commit_out;
7848 }
7849
7850 /* Wait a bit for NVM release to complete */
7851 msleep(50);
7852
7853 /* Acquire NVM for write access */
7854 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7855 last_aq_status = pf->hw.aq.asq_last_status;
7856 if (ret) {
7857 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7858 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7859 i40e_stat_str(&pf->hw, ret),
7860 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7861 goto bw_commit_out;
7862 }
7863 /* Write it back out unchanged to initiate update NVM,
7864 * which will force a write of the shadow (alt) RAM to
7865 * the NVM - thus storing the bandwidth values permanently.
7866 */
7867 ret = i40e_aq_update_nvm(&pf->hw,
7868 I40E_SR_NVM_CONTROL_WORD,
7869 0x10, sizeof(nvm_word),
7870 &nvm_word, true, NULL);
7871 /* Save off last admin queue command status before releasing
7872 * the NVM
7873 */
7874 last_aq_status = pf->hw.aq.asq_last_status;
7875 i40e_release_nvm(&pf->hw);
7876 if (ret)
7877 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7878 "BW settings NOT SAVED, err %s aq_err %s\n",
7879 i40e_stat_str(&pf->hw, ret),
7880 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7881bw_commit_out:
7882
7883 return ret;
7884}
7885
41c445ff
JB		 7886/**
7887 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7888 * @pf: board private structure to initialize
7889 *
7890 * i40e_sw_init initializes the Adapter private data structure.
7891 * Fields are initialized based on PCI device information and
7892 * OS network device settings (MTU size).
7893 **/
7894static int i40e_sw_init(struct i40e_pf *pf)
7895{
7896 int err = 0;
7897 int size;
7898
7899 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7900 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7901 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7902 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7903 if (I40E_DEBUG_USER & debug)
7904 pf->hw.debug_mask = debug;
7905 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7906 I40E_DEFAULT_MSG_ENABLE);
7907 }
7908
7909 /* Set default capability flags */
7910 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7911 I40E_FLAG_MSI_ENABLED |
9ac77266 7912 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 7913 I40E_FLAG_MSIX_ENABLED;
7914
7915 if (iommu_present(&pci_bus_type))
7916 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7917 else
7918 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7919
ca99eb99
MW		 7920 /* Set default ITR */
7921 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7922 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7923
7134f9ce
JB		 7924 /* Depending on PF configurations, it is possible that the RSS
7925 * maximum might end up larger than the available queues
7926 */
41a1d04b 7927 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7928 pf->rss_size = 1;
5db4cb59 7929 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7930 pf->rss_size_max = min_t(int, pf->rss_size_max,
7931 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7932 if (pf->hw.func_caps.rss) {
7933 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7934 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7935 }
7936
2050bc65 7937 /* MFP mode enabled */
c78b953e 7938 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7939 pf->flags |= I40E_FLAG_MFP_ENABLED;
7940 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7941 if (i40e_get_npar_bw_setting(pf))
7942 dev_warn(&pf->pdev->dev,
7943 "Could not get NPAR bw settings\n");
7944 else
7945 dev_info(&pf->pdev->dev,
7946 "Min BW = %8.8x, Max BW = %8.8x\n",
7947 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7948 }
7949
cbf61325
ASJ		 7950 /* FW/NVM is not yet fixed in this regard */
7951 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7952 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7953 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7954 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 7955 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
7956 pf->hw.num_partitions > 1)
cbf61325 7957 dev_info(&pf->pdev->dev,
0b67584f 7958 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 7959 else
7960 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7961 pf->fdir_pf_filter_count =
7962 pf->hw.func_caps.fd_filters_guaranteed;
7963 pf->hw.fdir_shared_filter_count =
7964 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7965 }
7966
7967 if (pf->hw.func_caps.vmdq) {
41c445ff 7968 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 7969 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
41c445ff
JB		 7970 }
7971
38e00438 7972#ifdef I40E_FCOE
21364bcf 7973 i40e_init_pf_fcoe(pf);
38e00438
VD		 7974
7975#endif /* I40E_FCOE */
41c445ff 7976#ifdef CONFIG_PCI_IOV
ba252f13 7977 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7978 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7979 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7980 pf->num_req_vfs = min_t(int,
7981 pf->hw.func_caps.num_vfs,
7982 I40E_MAX_VF_COUNT);
7983 }
7984#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7985 if (pf->hw.mac.type == I40E_MAC_X722) {
7986 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7987 I40E_FLAG_128_QP_RSS_CAPABLE |
7988 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7989 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7990 I40E_FLAG_WB_ON_ITR_CAPABLE |
7991 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
7992 }
41c445ff
JB		 7993 pf->eeprom_version = 0xDEAD;
7994 pf->lan_veb = I40E_NO_VEB;
7995 pf->lan_vsi = I40E_NO_VSI;
7996
d1a8d275
ASJ		 7997 /* By default FW has this off for performance reasons */
7998 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
7999
41c445ff
JB		 8000 /* set up queue assignment tracking */
8001 size = sizeof(struct i40e_lump_tracking)
8002 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8003 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8004 if (!pf->qp_pile) {
8005 err = -ENOMEM;
8006 goto sw_init_done;
8007 }
8008 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8009 pf->qp_pile->search_hint = 0;
8010
327fe04b
ASJ		 8011 pf->tx_timeout_recovery_level = 1;
8012
41c445ff
JB		 8013 mutex_init(&pf->switch_mutex);
8014
c668a12c
GR		 8015 /* If NPAR is enabled nudge the Tx scheduler */
8016 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8017 i40e_set_npar_bw_setting(pf);
8018
41c445ff
JB		 8019sw_init_done:
8020 return err;
8021}
8022
7c3c288b
ASJ		 8023/**
8024 * i40e_set_ntuple - set the ntuple feature flag and take action
8025 * @pf: board private structure to initialize
8026 * @features: the feature set that the stack is suggesting
8027 *
8028 * returns a bool to indicate if reset needs to happen
8029 **/
8030bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8031{
8032 bool need_reset = false;
8033
8034 /* Check if Flow Director n-tuple support was enabled or disabled. If
8035 * the state changed, we need to reset.
8036 */
8037 if (features & NETIF_F_NTUPLE) {
8038 /* Enable filters and mark for reset */
8039 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8040 need_reset = true;
8041 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8042 } else {
8043 /* turn off filters, mark for reset and clear SW filter list */
8044 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8045 need_reset = true;
8046 i40e_fdir_filter_exit(pf);
8047 }
8048 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8049 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8050 /* reset fd counters */
8051 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8052 pf->fdir_pf_active_filters = 0;
8053 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8054 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8055 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8056 /* if ATR was auto disabled it can be re-enabled. */
8057 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8058 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8059 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8060 }
8061 return need_reset;
8062}
8063
41c445ff
JB		 8064/**
8065 * i40e_set_features - set the netdev feature flags
8066 * @netdev: ptr to the netdev being adjusted
8067 * @features: the feature set that the stack is suggesting
8068 **/
8069static int i40e_set_features(struct net_device *netdev,
8070 netdev_features_t features)
8071{
8072 struct i40e_netdev_priv *np = netdev_priv(netdev);
8073 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8074 struct i40e_pf *pf = vsi->back;
8075 bool need_reset;
41c445ff
JB		 8076
8077 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8078 i40e_vlan_stripping_enable(vsi);
8079 else
8080 i40e_vlan_stripping_disable(vsi);
8081
7c3c288b
ASJ		 8082 need_reset = i40e_set_ntuple(pf, features);
8083
8084 if (need_reset)
41a1d04b 8085 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8086
41c445ff
JB		 8087 return 0;
8088}
8089
a1c9a9d9
JK		 8090#ifdef CONFIG_I40E_VXLAN
8091/**
8092 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8093 * @pf: board private structure
8094 * @port: The UDP port to look up
8095 *
8096 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8097 **/
8098static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8099{
8100 u8 i;
8101
8102 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8103 if (pf->vxlan_ports[i] == port)
8104 return i;
8105 }
8106
8107 return i;
8108}
8109
8110/**
8111 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8112 * @netdev: This physical port's netdev
8113 * @sa_family: Socket Family that VXLAN is notifying us about
8114 * @port: New UDP port number that VXLAN started listening to
8115 **/
8116static void i40e_add_vxlan_port(struct net_device *netdev,
8117 sa_family_t sa_family, __be16 port)
8118{
8119 struct i40e_netdev_priv *np = netdev_priv(netdev);
8120 struct i40e_vsi *vsi = np->vsi;
8121 struct i40e_pf *pf = vsi->back;
8122 u8 next_idx;
8123 u8 idx;
8124
8125 if (sa_family == AF_INET6)
8126 return;
8127
8128 idx = i40e_get_vxlan_port_idx(pf, port);
8129
8130 /* Check if port already exists */
8131 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8132 netdev_info(netdev, "vxlan port %d already offloaded\n",
8133 ntohs(port));
a1c9a9d9
JK		 8134 return;
8135 }
8136
8137 /* Now check if there is space to add the new port */
8138 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8139
8140 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8141 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8142 ntohs(port));
8143 return;
8144 }
8145
8146 /* New port: add it and mark its index in the bitmap */
8147 pf->vxlan_ports[next_idx] = port;
41a1d04b 8148 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8149 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8150}
8151
8152/**
8153 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8154 * @netdev: This physical port's netdev
8155 * @sa_family: Socket Family that VXLAN is notifying us about
8156 * @port: UDP port number that VXLAN stopped listening to
8157 **/
8158static void i40e_del_vxlan_port(struct net_device *netdev,
8159 sa_family_t sa_family, __be16 port)
8160{
8161 struct i40e_netdev_priv *np = netdev_priv(netdev);
8162 struct i40e_vsi *vsi = np->vsi;
8163 struct i40e_pf *pf = vsi->back;
8164 u8 idx;
8165
8166 if (sa_family == AF_INET6)
8167 return;
8168
8169 idx = i40e_get_vxlan_port_idx(pf, port);
8170
8171 /* Check if port already exists */
8172 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8173 /* if port exists, set it to 0 (mark for deletion)
8174 * and make it pending
8175 */
8176 pf->vxlan_ports[idx] = 0;
41a1d04b 8177 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8178 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8179 } else {
c22c06c8 8180 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8181 ntohs(port));
8182 }
8183}
8184
8185#endif
1f224ad2 8186static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8187 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8188{
8189 struct i40e_netdev_priv *np = netdev_priv(netdev);
8190 struct i40e_pf *pf = np->vsi->back;
8191 struct i40e_hw *hw = &pf->hw;
8192
8193 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8194 return -EOPNOTSUPP;
8195
8196 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8197 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8198
8199 return 0;
8200}
8201
2f90ade6
JB		 8202/**
8203 * i40e_ndo_fdb_add - add an entry to the hardware database
8204 * @ndm: the input from the stack
8205 * @tb: pointer to array of nladdr (unused)
8206 * @dev: the net device pointer
8207 * @addr: the MAC address entry being added
8208 * @flags: instructions from stack about fdb operation
8209 */
4ba0dea5
GR		 8210static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8211 struct net_device *dev,
f6f6424b 8212 const unsigned char *addr, u16 vid,
4ba0dea5 8213 u16 flags)
4ba0dea5
GR		 8214{
8215 struct i40e_netdev_priv *np = netdev_priv(dev);
8216 struct i40e_pf *pf = np->vsi->back;
8217 int err = 0;
8218
8219 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8220 return -EOPNOTSUPP;
8221
65891fea
OG		 8222 if (vid) {
8223 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8224 return -EINVAL;
8225 }
8226
4ba0dea5
GR		 8227 /* Hardware does not support aging addresses so if a
8228 * ndm_state is given only allow permanent addresses
8229 */
8230 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8231 netdev_info(dev, "FDB only supports static addresses\n");
8232 return -EINVAL;
8233 }
8234
8235 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8236 err = dev_uc_add_excl(dev, addr);
8237 else if (is_multicast_ether_addr(addr))
8238 err = dev_mc_add_excl(dev, addr);
8239 else
8240 err = -EINVAL;
8241
8242 /* Only return duplicate errors if NLM_F_EXCL is set */
8243 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8244 err = 0;
8245
8246 return err;
8247}
8248
51616018
NP		 8249/**
8250 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8251 * @dev: the netdev being configured
8252 * @nlh: RTNL message
8253 *
8254 * Inserts a new hardware bridge if not already created and
8255 * enables the bridging mode requested (VEB or VEPA). If the
8256 * hardware bridge has already been inserted and the request
8257 * is to change the mode then that requires a PF reset to
8258 * allow rebuild of the components with required hardware
8259 * bridge mode enabled.
8260 **/
8261static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8262 struct nlmsghdr *nlh,
8263 u16 flags)
51616018
NP		 8264{
8265 struct i40e_netdev_priv *np = netdev_priv(dev);
8266 struct i40e_vsi *vsi = np->vsi;
8267 struct i40e_pf *pf = vsi->back;
8268 struct i40e_veb *veb = NULL;
8269 struct nlattr *attr, *br_spec;
8270 int i, rem;
8271
8272 /* Only for PF VSI for now */
8273 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8274 return -EOPNOTSUPP;
8275
8276 /* Find the HW bridge for PF VSI */
8277 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8278 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8279 veb = pf->veb[i];
8280 }
8281
8282 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8283
8284 nla_for_each_nested(attr, br_spec, rem) {
8285 __u16 mode;
8286
8287 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8288 continue;
8289
8290 mode = nla_get_u16(attr);
8291 if ((mode != BRIDGE_MODE_VEPA) &&
8292 (mode != BRIDGE_MODE_VEB))
8293 return -EINVAL;
8294
8295 /* Insert a new HW bridge */
8296 if (!veb) {
8297 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8298 vsi->tc_config.enabled_tc);
8299 if (veb) {
8300 veb->bridge_mode = mode;
8301 i40e_config_bridge_mode(veb);
8302 } else {
8303 /* No Bridge HW offload available */
8304 return -ENOENT;
8305 }
8306 break;
8307 } else if (mode != veb->bridge_mode) {
8308 /* Existing HW bridge but different mode needs reset */
8309 veb->bridge_mode = mode;
fc60861e
ASJ		 8310 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8311 if (mode == BRIDGE_MODE_VEB)
8312 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8313 else
8314 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8315 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8316 break;
8317 }
8318 }
8319
8320 return 0;
8321}
8322
8323/**
8324 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8325 * @skb: skb buff
8326 * @pid: process id
8327 * @seq: RTNL message seq #
8328 * @dev: the netdev being configured
8329 * @filter_mask: unused
d4b2f9fe 8330 * @nlflags: netlink flags passed in
51616018
NP		 8331 *
8332 * Return the mode in which the hardware bridge is operating in
8333 * i.e VEB or VEPA.
8334 **/
51616018
NP		 8335static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8336 struct net_device *dev,
9f4ffc44
CW		 8337 u32 __always_unused filter_mask,
8338 int nlflags)
51616018
NP		 8339{
8340 struct i40e_netdev_priv *np = netdev_priv(dev);
8341 struct i40e_vsi *vsi = np->vsi;
8342 struct i40e_pf *pf = vsi->back;
8343 struct i40e_veb *veb = NULL;
8344 int i;
8345
8346 /* Only for PF VSI for now */
8347 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8348 return -EOPNOTSUPP;
8349
8350 /* Find the HW bridge for the PF VSI */
8351 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8352 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8353 veb = pf->veb[i];
8354 }
8355
8356 if (!veb)
8357 return 0;
8358
46c264da 8359 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8360 nlflags, 0, 0, filter_mask, NULL);
51616018 8361}
51616018 8362
f44a75e2
JS		 8363#define I40E_MAX_TUNNEL_HDR_LEN 80
8364/**
8365 * i40e_features_check - Validate encapsulated packet conforms to limits
8366 * @skb: skb buff
8367 * @netdev: This physical port's netdev
8368 * @features: Offload features that the stack believes apply
8369 **/
8370static netdev_features_t i40e_features_check(struct sk_buff *skb,
8371 struct net_device *dev,
8372 netdev_features_t features)
8373{
8374 if (skb->encapsulation &&
8375 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8376 I40E_MAX_TUNNEL_HDR_LEN))
8377 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8378
8379 return features;
8380}
8381
37a2973a 8382static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8383 .ndo_open = i40e_open,
8384 .ndo_stop = i40e_close,
8385 .ndo_start_xmit = i40e_lan_xmit_frame,
8386 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8387 .ndo_set_rx_mode = i40e_set_rx_mode,
8388 .ndo_validate_addr = eth_validate_addr,
8389 .ndo_set_mac_address = i40e_set_mac,
8390 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8391 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8392 .ndo_tx_timeout = i40e_tx_timeout,
8393 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8394 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8395#ifdef CONFIG_NET_POLL_CONTROLLER
8396 .ndo_poll_controller = i40e_netpoll,
8397#endif
8398 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8399#ifdef I40E_FCOE
8400 .ndo_fcoe_enable = i40e_fcoe_enable,
8401 .ndo_fcoe_disable = i40e_fcoe_disable,
8402#endif
41c445ff
JB		 8403 .ndo_set_features = i40e_set_features,
8404 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8405 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8406 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8407 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8408 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8409 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8410#ifdef CONFIG_I40E_VXLAN
8411 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8412 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8413#endif
1f224ad2 8414 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8415 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8416 .ndo_features_check = i40e_features_check,
51616018
NP		 8417 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8418 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8419};
8420
8421/**
8422 * i40e_config_netdev - Setup the netdev flags
8423 * @vsi: the VSI being configured
8424 *
8425 * Returns 0 on success, negative value on failure
8426 **/
8427static int i40e_config_netdev(struct i40e_vsi *vsi)
8428{
1a10370a 8429 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8430 struct i40e_pf *pf = vsi->back;
8431 struct i40e_hw *hw = &pf->hw;
8432 struct i40e_netdev_priv *np;
8433 struct net_device *netdev;
8434 u8 mac_addr[ETH_ALEN];
8435 int etherdev_size;
8436
8437 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8438 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8439 if (!netdev)
8440 return -ENOMEM;
8441
8442 vsi->netdev = netdev;
8443 np = netdev_priv(netdev);
8444 np->vsi = vsi;
8445
d70e941b 8446 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8447 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8448 NETIF_F_TSO;
41c445ff
JB		 8449
8450 netdev->features = NETIF_F_SG |
8451 NETIF_F_IP_CSUM |
8452 NETIF_F_SCTP_CSUM |
8453 NETIF_F_HIGHDMA |
8454 NETIF_F_GSO_UDP_TUNNEL |
8455 NETIF_F_HW_VLAN_CTAG_TX |
8456 NETIF_F_HW_VLAN_CTAG_RX |
8457 NETIF_F_HW_VLAN_CTAG_FILTER |
8458 NETIF_F_IPV6_CSUM |
8459 NETIF_F_TSO |
059dab69 8460 NETIF_F_TSO_ECN |
41c445ff
JB		 8461 NETIF_F_TSO6 |
8462 NETIF_F_RXCSUM |
8463 NETIF_F_RXHASH |
8464 0;
8465
2e86a0b6
ASJ		 8466 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8467 netdev->features |= NETIF_F_NTUPLE;
8468
41c445ff
JB		 8469 /* copy netdev features into list of user selectable features */
8470 netdev->hw_features |= netdev->features;
8471
8472 if (vsi->type == I40E_VSI_MAIN) {
8473 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8474 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8475 /* The following steps are necessary to prevent reception
8476 * of tagged packets - some older NVM configurations load a
8477 * default a MAC-VLAN filter that accepts any tagged packet
8478 * which must be replaced by a normal filter.
8c27d42e 8479 */
30650cc5
SN		 8480 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8481 i40e_add_filter(vsi, mac_addr,
8482 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8483 } else {
8484 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8485 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8486 pf->vsi[pf->lan_vsi]->netdev->name);
8487 random_ether_addr(mac_addr);
8488 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8489 }
1a10370a 8490 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8491
9a173901
GR		 8492 ether_addr_copy(netdev->dev_addr, mac_addr);
8493 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8494 /* vlan gets same features (except vlan offload)
8495 * after any tweaks for specific VSI types
8496 */
8497 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8498 NETIF_F_HW_VLAN_CTAG_RX |
8499 NETIF_F_HW_VLAN_CTAG_FILTER);
8500 netdev->priv_flags |= IFF_UNICAST_FLT;
8501 netdev->priv_flags |= IFF_SUPP_NOFCS;
8502 /* Setup netdev TC information */
8503 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8504
8505 netdev->netdev_ops = &i40e_netdev_ops;
8506 netdev->watchdog_timeo = 5 * HZ;
8507 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8508#ifdef I40E_FCOE
8509 i40e_fcoe_config_netdev(netdev, vsi);
8510#endif
41c445ff
JB		 8511
8512 return 0;
8513}
8514
8515/**
8516 * i40e_vsi_delete - Delete a VSI from the switch
8517 * @vsi: the VSI being removed
8518 *
8519 * Returns 0 on success, negative value on failure
8520 **/
8521static void i40e_vsi_delete(struct i40e_vsi *vsi)
8522{
8523 /* remove default VSI is not allowed */
8524 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8525 return;
8526
41c445ff 8527 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8528}
8529
51616018
NP		 8530/**
8531 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8532 * @vsi: the VSI being queried
8533 *
8534 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8535 **/
8536int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8537{
8538 struct i40e_veb *veb;
8539 struct i40e_pf *pf = vsi->back;
8540
8541 /* Uplink is not a bridge so default to VEB */
8542 if (vsi->veb_idx == I40E_NO_VEB)
8543 return 1;
8544
8545 veb = pf->veb[vsi->veb_idx];
8546 /* Uplink is a bridge in VEPA mode */
8547 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8548 return 0;
8549
8550 /* Uplink is a bridge in VEB mode */
8551 return 1;
8552}
8553
41c445ff
JB		 8554/**
8555 * i40e_add_vsi - Add a VSI to the switch
8556 * @vsi: the VSI being configured
8557 *
8558 * This initializes a VSI context depending on the VSI type to be added and
8559 * passes it down to the add_vsi aq command.
8560 **/
8561static int i40e_add_vsi(struct i40e_vsi *vsi)
8562{
8563 int ret = -ENODEV;
8564 struct i40e_mac_filter *f, *ftmp;
8565 struct i40e_pf *pf = vsi->back;
8566 struct i40e_hw *hw = &pf->hw;
8567 struct i40e_vsi_context ctxt;
8568 u8 enabled_tc = 0x1; /* TC0 enabled */
8569 int f_count = 0;
8570
8571 memset(&ctxt, 0, sizeof(ctxt));
8572 switch (vsi->type) {
8573 case I40E_VSI_MAIN:
8574 /* The PF's main VSI is already setup as part of the
8575 * device initialization, so we'll not bother with
8576 * the add_vsi call, but we will retrieve the current
8577 * VSI context.
8578 */
8579 ctxt.seid = pf->main_vsi_seid;
8580 ctxt.pf_num = pf->hw.pf_id;
8581 ctxt.vf_num = 0;
8582 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8583 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8584 if (ret) {
8585 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8586 "couldn't get PF vsi config, err %s aq_err %s\n",
8587 i40e_stat_str(&pf->hw, ret),
8588 i40e_aq_str(&pf->hw,
8589 pf->hw.aq.asq_last_status));
41c445ff
JB		 8590 return -ENOENT;
8591 }
1a2f6248 8592 vsi->info = ctxt.info;
41c445ff
JB		 8593 vsi->info.valid_sections = 0;
8594
8595 vsi->seid = ctxt.seid;
8596 vsi->id = ctxt.vsi_number;
8597
8598 enabled_tc = i40e_pf_get_tc_map(pf);
8599
8600 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8601 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8602 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8603 memset(&ctxt, 0, sizeof(ctxt));
8604 ctxt.seid = pf->main_vsi_seid;
8605 ctxt.pf_num = pf->hw.pf_id;
8606 ctxt.vf_num = 0;
8607 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8608 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8609 if (ret) {
8610 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8611 "update vsi failed, err %s aq_err %s\n",
8612 i40e_stat_str(&pf->hw, ret),
8613 i40e_aq_str(&pf->hw,
8614 pf->hw.aq.asq_last_status));
41c445ff
JB		 8615 ret = -ENOENT;
8616 goto err;
8617 }
8618 /* update the local VSI info queue map */
8619 i40e_vsi_update_queue_map(vsi, &ctxt);
8620 vsi->info.valid_sections = 0;
8621 } else {
8622 /* Default/Main VSI is only enabled for TC0
8623 * reconfigure it to enable all TCs that are
8624 * available on the port in SFP mode.
63d7e5a4
NP		 8625 * For MFP case the iSCSI PF would use this
8626 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8627 */
8628 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8629 if (ret) {
8630 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8631 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8632 enabled_tc,
8633 i40e_stat_str(&pf->hw, ret),
8634 i40e_aq_str(&pf->hw,
8635 pf->hw.aq.asq_last_status));
41c445ff
JB		 8636 ret = -ENOENT;
8637 }
8638 }
8639 break;
8640
8641 case I40E_VSI_FDIR:
cbf61325
ASJ		 8642 ctxt.pf_num = hw->pf_id;
8643 ctxt.vf_num = 0;
8644 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8645 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8646 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8647 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8648 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8649 ctxt.info.valid_sections |=
fc60861e 8650 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8651 ctxt.info.switch_id =
fc60861e 8652 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8653 }
41c445ff 8654 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8655 break;
8656
8657 case I40E_VSI_VMDQ2:
8658 ctxt.pf_num = hw->pf_id;
8659 ctxt.vf_num = 0;
8660 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8661 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8662 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8663
41c445ff
JB		 8664 /* This VSI is connected to VEB so the switch_id
8665 * should be set to zero by default.
8666 */
51616018
NP		 8667 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8668 ctxt.info.valid_sections |=
8669 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8670 ctxt.info.switch_id =
8671 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8672 }
41c445ff
JB		 8673
8674 /* Setup the VSI tx/rx queue map for TC0 only for now */
8675 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8676 break;
8677
8678 case I40E_VSI_SRIOV:
8679 ctxt.pf_num = hw->pf_id;
8680 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8681 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8682 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8683 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8684
41c445ff
JB		 8685 /* This VSI is connected to VEB so the switch_id
8686 * should be set to zero by default.
8687 */
51616018
NP		 8688 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8689 ctxt.info.valid_sections |=
8690 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8691 ctxt.info.switch_id =
8692 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8693 }
41c445ff
JB		 8694
8695 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8696 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8697 if (pf->vf[vsi->vf_id].spoofchk) {
8698 ctxt.info.valid_sections |=
8699 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8700 ctxt.info.sec_flags |=
8701 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8702 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8703 }
41c445ff
JB		 8704 /* Setup the VSI tx/rx queue map for TC0 only for now */
8705 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8706 break;
8707
38e00438
VD		 8708#ifdef I40E_FCOE
8709 case I40E_VSI_FCOE:
8710 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8711 if (ret) {
8712 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8713 return ret;
8714 }
8715 break;
8716
8717#endif /* I40E_FCOE */
41c445ff
JB		 8718 default:
8719 return -ENODEV;
8720 }
8721
8722 if (vsi->type != I40E_VSI_MAIN) {
8723 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8724 if (ret) {
8725 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8726 "add vsi failed, err %s aq_err %s\n",
8727 i40e_stat_str(&pf->hw, ret),
8728 i40e_aq_str(&pf->hw,
8729 pf->hw.aq.asq_last_status));
41c445ff
JB		 8730 ret = -ENOENT;
8731 goto err;
8732 }
1a2f6248 8733 vsi->info = ctxt.info;
41c445ff
JB		 8734 vsi->info.valid_sections = 0;
8735 vsi->seid = ctxt.seid;
8736 vsi->id = ctxt.vsi_number;
8737 }
8738
8739 /* If macvlan filters already exist, force them to get loaded */
8740 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8741 f->changed = true;
8742 f_count++;
6252c7e4
SN		 8743
8744 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8745 struct i40e_aqc_remove_macvlan_element_data element;
8746
8747 memset(&element, 0, sizeof(element));
8748 ether_addr_copy(element.mac_addr, f->macaddr);
8749 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8750 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8751 &element, 1, NULL);
8752 if (ret) {
8753 /* some older FW has a different default */
8754 element.flags |=
8755 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8756 i40e_aq_remove_macvlan(hw, vsi->seid,
8757 &element, 1, NULL);
8758 }
8759
8760 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8761 I40E_AQC_WRITE_TYPE_LAA_WOL,
8762 f->macaddr, NULL);
8763 }
41c445ff
JB		 8764 }
8765 if (f_count) {
8766 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8767 pf->flags |= I40E_FLAG_FILTER_SYNC;
8768 }
8769
8770 /* Update VSI BW information */
8771 ret = i40e_vsi_get_bw_info(vsi);
8772 if (ret) {
8773 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8774 "couldn't get vsi bw info, err %s aq_err %s\n",
8775 i40e_stat_str(&pf->hw, ret),
8776 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8777 /* VSI is already added so not tearing that up */
8778 ret = 0;
8779 }
8780
8781err:
8782 return ret;
8783}
8784
8785/**
8786 * i40e_vsi_release - Delete a VSI and free its resources
8787 * @vsi: the VSI being removed
8788 *
8789 * Returns 0 on success or < 0 on error
8790 **/
8791int i40e_vsi_release(struct i40e_vsi *vsi)
8792{
8793 struct i40e_mac_filter *f, *ftmp;
8794 struct i40e_veb *veb = NULL;
8795 struct i40e_pf *pf;
8796 u16 uplink_seid;
8797 int i, n;
8798
8799 pf = vsi->back;
8800
8801 /* release of a VEB-owner or last VSI is not allowed */
8802 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8803 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8804 vsi->seid, vsi->uplink_seid);
8805 return -ENODEV;
8806 }
8807 if (vsi == pf->vsi[pf->lan_vsi] &&
8808 !test_bit(__I40E_DOWN, &pf->state)) {
8809 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8810 return -ENODEV;
8811 }
8812
8813 uplink_seid = vsi->uplink_seid;
8814 if (vsi->type != I40E_VSI_SRIOV) {
8815 if (vsi->netdev_registered) {
8816 vsi->netdev_registered = false;
8817 if (vsi->netdev) {
8818 /* results in a call to i40e_close() */
8819 unregister_netdev(vsi->netdev);
41c445ff
JB		 8820 }
8821 } else {
90ef8d47 8822 i40e_vsi_close(vsi);
41c445ff
JB		 8823 }
8824 i40e_vsi_disable_irq(vsi);
8825 }
8826
8827 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8828 i40e_del_filter(vsi, f->macaddr, f->vlan,
8829 f->is_vf, f->is_netdev);
30e2561b 8830 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 8831
8832 i40e_vsi_delete(vsi);
8833 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8834 if (vsi->netdev) {
8835 free_netdev(vsi->netdev);
8836 vsi->netdev = NULL;
8837 }
41c445ff
JB		 8838 i40e_vsi_clear_rings(vsi);
8839 i40e_vsi_clear(vsi);
8840
8841 /* If this was the last thing on the VEB, except for the
8842 * controlling VSI, remove the VEB, which puts the controlling
8843 * VSI onto the next level down in the switch.
8844 *
8845 * Well, okay, there's one more exception here: don't remove
8846 * the orphan VEBs yet. We'll wait for an explicit remove request
8847 * from up the network stack.
8848 */
505682cd 8849 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8850 if (pf->vsi[i] &&
8851 pf->vsi[i]->uplink_seid == uplink_seid &&
8852 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8853 n++; /* count the VSIs */
8854 }
8855 }
8856 for (i = 0; i < I40E_MAX_VEB; i++) {
8857 if (!pf->veb[i])
8858 continue;
8859 if (pf->veb[i]->uplink_seid == uplink_seid)
8860 n++; /* count the VEBs */
8861 if (pf->veb[i]->seid == uplink_seid)
8862 veb = pf->veb[i];
8863 }
8864 if (n == 0 && veb && veb->uplink_seid != 0)
8865 i40e_veb_release(veb);
8866
8867 return 0;
8868}
8869
8870/**
8871 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8872 * @vsi: ptr to the VSI
8873 *
8874 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8875 * corresponding SW VSI structure and initializes num_queue_pairs for the
8876 * newly allocated VSI.
8877 *
8878 * Returns 0 on success or negative on failure
8879 **/
8880static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8881{
8882 int ret = -ENOENT;
8883 struct i40e_pf *pf = vsi->back;
8884
493fb300 8885 if (vsi->q_vectors[0]) {
41c445ff
JB		 8886 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8887 vsi->seid);
8888 return -EEXIST;
8889 }
8890
8891 if (vsi->base_vector) {
f29eaa3d 8892 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8893 vsi->seid, vsi->base_vector);
8894 return -EEXIST;
8895 }
8896
90e04070 8897 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8898 if (ret) {
8899 dev_info(&pf->pdev->dev,
8900 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8901 vsi->num_q_vectors, vsi->seid, ret);
8902 vsi->num_q_vectors = 0;
8903 goto vector_setup_out;
8904 }
8905
26cdc443
ASJ		 8906 /* In Legacy mode, we do not have to get any other vector since we
8907 * piggyback on the misc/ICR0 for queue interrupts.
8908 */
8909 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
8910 return ret;
958a3e3b
SN		 8911 if (vsi->num_q_vectors)
8912 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8913 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8914 if (vsi->base_vector < 0) {
8915 dev_info(&pf->pdev->dev,
049a2be8
SN		 8916 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8917 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8918 i40e_vsi_free_q_vectors(vsi);
8919 ret = -ENOENT;
8920 goto vector_setup_out;
8921 }
8922
8923vector_setup_out:
8924 return ret;
8925}
8926
bc7d338f
ASJ		 8927/**
8928 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8929 * @vsi: pointer to the vsi.
8930 *
8931 * This re-allocates a vsi's queue resources.
8932 *
8933 * Returns pointer to the successfully allocated and configured VSI sw struct
8934 * on success, otherwise returns NULL on failure.
8935 **/
8936static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8937{
8938 struct i40e_pf *pf = vsi->back;
8939 u8 enabled_tc;
8940 int ret;
8941
8942 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8943 i40e_vsi_clear_rings(vsi);
8944
8945 i40e_vsi_free_arrays(vsi, false);
8946 i40e_set_num_rings_in_vsi(vsi);
8947 ret = i40e_vsi_alloc_arrays(vsi, false);
8948 if (ret)
8949 goto err_vsi;
8950
8951 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8952 if (ret < 0) {
049a2be8 8953 dev_info(&pf->pdev->dev,
f1c7e72e 8954 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8955 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8956 goto err_vsi;
8957 }
8958 vsi->base_queue = ret;
8959
8960 /* Update the FW view of the VSI. Force a reset of TC and queue
8961 * layout configurations.
8962 */
8963 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8964 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8965 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8966 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8967
8968 /* assign it some queues */
8969 ret = i40e_alloc_rings(vsi);
8970 if (ret)
8971 goto err_rings;
8972
8973 /* map all of the rings to the q_vectors */
8974 i40e_vsi_map_rings_to_vectors(vsi);
8975 return vsi;
8976
8977err_rings:
8978 i40e_vsi_free_q_vectors(vsi);
8979 if (vsi->netdev_registered) {
8980 vsi->netdev_registered = false;
8981 unregister_netdev(vsi->netdev);
8982 free_netdev(vsi->netdev);
8983 vsi->netdev = NULL;
8984 }
8985 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8986err_vsi:
8987 i40e_vsi_clear(vsi);
8988 return NULL;
8989}
8990
41c445ff
JB		 8991/**
8992 * i40e_vsi_setup - Set up a VSI by a given type
8993 * @pf: board private structure
8994 * @type: VSI type
8995 * @uplink_seid: the switch element to link to
8996 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8997 *
8998 * This allocates the sw VSI structure and its queue resources, then add a VSI
8999 * to the identified VEB.
9000 *
9001 * Returns pointer to the successfully allocated and configure VSI sw struct on
9002 * success, otherwise returns NULL on failure.
9003 **/
9004struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9005 u16 uplink_seid, u32 param1)
9006{
9007 struct i40e_vsi *vsi = NULL;
9008 struct i40e_veb *veb = NULL;
9009 int ret, i;
9010 int v_idx;
9011
9012 /* The requested uplink_seid must be either
9013 * - the PF's port seid
9014 * no VEB is needed because this is the PF
9015 * or this is a Flow Director special case VSI
9016 * - seid of an existing VEB
9017 * - seid of a VSI that owns an existing VEB
9018 * - seid of a VSI that doesn't own a VEB
9019 * a new VEB is created and the VSI becomes the owner
9020 * - seid of the PF VSI, which is what creates the first VEB
9021 * this is a special case of the previous
9022 *
9023 * Find which uplink_seid we were given and create a new VEB if needed
9024 */
9025 for (i = 0; i < I40E_MAX_VEB; i++) {
9026 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9027 veb = pf->veb[i];
9028 break;
9029 }
9030 }
9031
9032 if (!veb && uplink_seid != pf->mac_seid) {
9033
505682cd 9034 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9035 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9036 vsi = pf->vsi[i];
9037 break;
9038 }
9039 }
9040 if (!vsi) {
9041 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9042 uplink_seid);
9043 return NULL;
9044 }
9045
9046 if (vsi->uplink_seid == pf->mac_seid)
9047 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9048 vsi->tc_config.enabled_tc);
9049 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9050 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9051 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9052 if (veb) {
9053 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9054 dev_info(&vsi->back->pdev->dev,
fb43201f 9055 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9056 return NULL;
9057 }
fa11cb3d
ASJ		 9058 /* We come up by default in VEPA mode if SRIOV is not
9059 * already enabled, in which case we can't force VEPA
9060 * mode.
9061 */
9062 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9063 veb->bridge_mode = BRIDGE_MODE_VEPA;
9064 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9065 }
51616018 9066 i40e_config_bridge_mode(veb);
79c21a82 9067 }
41c445ff
JB		 9068 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9069 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9070 veb = pf->veb[i];
9071 }
9072 if (!veb) {
9073 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9074 return NULL;
9075 }
9076
9077 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9078 uplink_seid = veb->seid;
9079 }
9080
9081 /* get vsi sw struct */
9082 v_idx = i40e_vsi_mem_alloc(pf, type);
9083 if (v_idx < 0)
9084 goto err_alloc;
9085 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9086 if (!vsi)
9087 goto err_alloc;
41c445ff
JB		 9088 vsi->type = type;
9089 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9090
9091 if (type == I40E_VSI_MAIN)
9092 pf->lan_vsi = v_idx;
9093 else if (type == I40E_VSI_SRIOV)
9094 vsi->vf_id = param1;
9095 /* assign it some queues */
cbf61325
ASJ		 9096 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9097 vsi->idx);
41c445ff 9098 if (ret < 0) {
049a2be8
SN		 9099 dev_info(&pf->pdev->dev,
9100 "failed to get tracking for %d queues for VSI %d err=%d\n",
9101 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9102 goto err_vsi;
9103 }
9104 vsi->base_queue = ret;
9105
9106 /* get a VSI from the hardware */
9107 vsi->uplink_seid = uplink_seid;
9108 ret = i40e_add_vsi(vsi);
9109 if (ret)
9110 goto err_vsi;
9111
9112 switch (vsi->type) {
9113 /* setup the netdev if needed */
9114 case I40E_VSI_MAIN:
9115 case I40E_VSI_VMDQ2:
38e00438 9116 case I40E_VSI_FCOE:
41c445ff
JB		 9117 ret = i40e_config_netdev(vsi);
9118 if (ret)
9119 goto err_netdev;
9120 ret = register_netdev(vsi->netdev);
9121 if (ret)
9122 goto err_netdev;
9123 vsi->netdev_registered = true;
9124 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9125#ifdef CONFIG_I40E_DCB
9126 /* Setup DCB netlink interface */
9127 i40e_dcbnl_setup(vsi);
9128#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9129 /* fall through */
9130
9131 case I40E_VSI_FDIR:
9132 /* set up vectors and rings if needed */
9133 ret = i40e_vsi_setup_vectors(vsi);
9134 if (ret)
9135 goto err_msix;
9136
9137 ret = i40e_alloc_rings(vsi);
9138 if (ret)
9139 goto err_rings;
9140
9141 /* map all of the rings to the q_vectors */
9142 i40e_vsi_map_rings_to_vectors(vsi);
9143
9144 i40e_vsi_reset_stats(vsi);
9145 break;
9146
9147 default:
9148 /* no netdev or rings for the other VSI types */
9149 break;
9150 }
9151
e25d00b8
ASJ		 9152 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9153 (vsi->type == I40E_VSI_VMDQ2)) {
9154 ret = i40e_vsi_config_rss(vsi);
9155 }
41c445ff
JB		 9156 return vsi;
9157
9158err_rings:
9159 i40e_vsi_free_q_vectors(vsi);
9160err_msix:
9161 if (vsi->netdev_registered) {
9162 vsi->netdev_registered = false;
9163 unregister_netdev(vsi->netdev);
9164 free_netdev(vsi->netdev);
9165 vsi->netdev = NULL;
9166 }
9167err_netdev:
9168 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9169err_vsi:
9170 i40e_vsi_clear(vsi);
9171err_alloc:
9172 return NULL;
9173}
9174
9175/**
9176 * i40e_veb_get_bw_info - Query VEB BW information
9177 * @veb: the veb to query
9178 *
9179 * Query the Tx scheduler BW configuration data for given VEB
9180 **/
9181static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9182{
9183 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9184 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9185 struct i40e_pf *pf = veb->pf;
9186 struct i40e_hw *hw = &pf->hw;
9187 u32 tc_bw_max;
9188 int ret = 0;
9189 int i;
9190
9191 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9192 &bw_data, NULL);
9193 if (ret) {
9194 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9195 "query veb bw config failed, err %s aq_err %s\n",
9196 i40e_stat_str(&pf->hw, ret),
9197 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9198 goto out;
9199 }
9200
9201 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9202 &ets_data, NULL);
9203 if (ret) {
9204 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9205 "query veb bw ets config failed, err %s aq_err %s\n",
9206 i40e_stat_str(&pf->hw, ret),
9207 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9208 goto out;
9209 }
9210
9211 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9212 veb->bw_max_quanta = ets_data.tc_bw_max;
9213 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9214 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9215 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9216 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9217 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9218 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9219 veb->bw_tc_limit_credits[i] =
9220 le16_to_cpu(bw_data.tc_bw_limits[i]);
9221 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9222 }
9223
9224out:
9225 return ret;
9226}
9227
9228/**
9229 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9230 * @pf: board private structure
9231 *
9232 * On error: returns error code (negative)
9233 * On success: returns vsi index in PF (positive)
9234 **/
9235static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9236{
9237 int ret = -ENOENT;
9238 struct i40e_veb *veb;
9239 int i;
9240
9241 /* Need to protect the allocation of switch elements at the PF level */
9242 mutex_lock(&pf->switch_mutex);
9243
9244 /* VEB list may be fragmented if VEB creation/destruction has
9245 * been happening. We can afford to do a quick scan to look
9246 * for any free slots in the list.
9247 *
9248 * find next empty veb slot, looping back around if necessary
9249 */
9250 i = 0;
9251 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9252 i++;
9253 if (i >= I40E_MAX_VEB) {
9254 ret = -ENOMEM;
9255 goto err_alloc_veb; /* out of VEB slots! */
9256 }
9257
9258 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9259 if (!veb) {
9260 ret = -ENOMEM;
9261 goto err_alloc_veb;
9262 }
9263 veb->pf = pf;
9264 veb->idx = i;
9265 veb->enabled_tc = 1;
9266
9267 pf->veb[i] = veb;
9268 ret = i;
9269err_alloc_veb:
9270 mutex_unlock(&pf->switch_mutex);
9271 return ret;
9272}
9273
9274/**
9275 * i40e_switch_branch_release - Delete a branch of the switch tree
9276 * @branch: where to start deleting
9277 *
9278 * This uses recursion to find the tips of the branch to be
9279 * removed, deleting until we get back to and can delete this VEB.
9280 **/
9281static void i40e_switch_branch_release(struct i40e_veb *branch)
9282{
9283 struct i40e_pf *pf = branch->pf;
9284 u16 branch_seid = branch->seid;
9285 u16 veb_idx = branch->idx;
9286 int i;
9287
9288 /* release any VEBs on this VEB - RECURSION */
9289 for (i = 0; i < I40E_MAX_VEB; i++) {
9290 if (!pf->veb[i])
9291 continue;
9292 if (pf->veb[i]->uplink_seid == branch->seid)
9293 i40e_switch_branch_release(pf->veb[i]);
9294 }
9295
9296 /* Release the VSIs on this VEB, but not the owner VSI.
9297 *
9298 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9299 * the VEB itself, so don't use (*branch) after this loop.
9300 */
505682cd 9301 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9302 if (!pf->vsi[i])
9303 continue;
9304 if (pf->vsi[i]->uplink_seid == branch_seid &&
9305 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9306 i40e_vsi_release(pf->vsi[i]);
9307 }
9308 }
9309
9310 /* There's one corner case where the VEB might not have been
9311 * removed, so double check it here and remove it if needed.
9312 * This case happens if the veb was created from the debugfs
9313 * commands and no VSIs were added to it.
9314 */
9315 if (pf->veb[veb_idx])
9316 i40e_veb_release(pf->veb[veb_idx]);
9317}
9318
9319/**
9320 * i40e_veb_clear - remove veb struct
9321 * @veb: the veb to remove
9322 **/
9323static void i40e_veb_clear(struct i40e_veb *veb)
9324{
9325 if (!veb)
9326 return;
9327
9328 if (veb->pf) {
9329 struct i40e_pf *pf = veb->pf;
9330
9331 mutex_lock(&pf->switch_mutex);
9332 if (pf->veb[veb->idx] == veb)
9333 pf->veb[veb->idx] = NULL;
9334 mutex_unlock(&pf->switch_mutex);
9335 }
9336
9337 kfree(veb);
9338}
9339
9340/**
9341 * i40e_veb_release - Delete a VEB and free its resources
9342 * @veb: the VEB being removed
9343 **/
9344void i40e_veb_release(struct i40e_veb *veb)
9345{
9346 struct i40e_vsi *vsi = NULL;
9347 struct i40e_pf *pf;
9348 int i, n = 0;
9349
9350 pf = veb->pf;
9351
9352 /* find the remaining VSI and check for extras */
505682cd 9353 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9354 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9355 n++;
9356 vsi = pf->vsi[i];
9357 }
9358 }
9359 if (n != 1) {
9360 dev_info(&pf->pdev->dev,
9361 "can't remove VEB %d with %d VSIs left\n",
9362 veb->seid, n);
9363 return;
9364 }
9365
9366 /* move the remaining VSI to uplink veb */
9367 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9368 if (veb->uplink_seid) {
9369 vsi->uplink_seid = veb->uplink_seid;
9370 if (veb->uplink_seid == pf->mac_seid)
9371 vsi->veb_idx = I40E_NO_VEB;
9372 else
9373 vsi->veb_idx = veb->veb_idx;
9374 } else {
9375 /* floating VEB */
9376 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9377 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9378 }
9379
9380 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9381 i40e_veb_clear(veb);
41c445ff
JB		 9382}
9383
9384/**
9385 * i40e_add_veb - create the VEB in the switch
9386 * @veb: the VEB to be instantiated
9387 * @vsi: the controlling VSI
9388 **/
9389static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9390{
f1c7e72e 9391 struct i40e_pf *pf = veb->pf;
92faef85 9392 bool is_default = veb->pf->cur_promisc;
e1c51b95 9393 bool is_cloud = false;
41c445ff
JB		 9394 int ret;
9395
9396 /* get a VEB from the hardware */
f1c7e72e 9397 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9398 veb->enabled_tc, is_default,
9399 is_cloud, &veb->seid, NULL);
41c445ff 9400 if (ret) {
f1c7e72e
SN		 9401 dev_info(&pf->pdev->dev,
9402 "couldn't add VEB, err %s aq_err %s\n",
9403 i40e_stat_str(&pf->hw, ret),
9404 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9405 return -EPERM;
9406 }
9407
9408 /* get statistics counter */
f1c7e72e 9409 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9410 &veb->stats_idx, NULL, NULL, NULL);
9411 if (ret) {
f1c7e72e
SN		 9412 dev_info(&pf->pdev->dev,
9413 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9414 i40e_stat_str(&pf->hw, ret),
9415 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9416 return -EPERM;
9417 }
9418 ret = i40e_veb_get_bw_info(veb);
9419 if (ret) {
f1c7e72e
SN		 9420 dev_info(&pf->pdev->dev,
9421 "couldn't get VEB bw info, err %s aq_err %s\n",
9422 i40e_stat_str(&pf->hw, ret),
9423 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9424 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9425 return -ENOENT;
9426 }
9427
9428 vsi->uplink_seid = veb->seid;
9429 vsi->veb_idx = veb->idx;
9430 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9431
9432 return 0;
9433}
9434
9435/**
9436 * i40e_veb_setup - Set up a VEB
9437 * @pf: board private structure
9438 * @flags: VEB setup flags
9439 * @uplink_seid: the switch element to link to
9440 * @vsi_seid: the initial VSI seid
9441 * @enabled_tc: Enabled TC bit-map
9442 *
9443 * This allocates the sw VEB structure and links it into the switch
9444 * It is possible and legal for this to be a duplicate of an already
9445 * existing VEB. It is also possible for both uplink and vsi seids
9446 * to be zero, in order to create a floating VEB.
9447 *
9448 * Returns pointer to the successfully allocated VEB sw struct on
9449 * success, otherwise returns NULL on failure.
9450 **/
9451struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9452 u16 uplink_seid, u16 vsi_seid,
9453 u8 enabled_tc)
9454{
9455 struct i40e_veb *veb, *uplink_veb = NULL;
9456 int vsi_idx, veb_idx;
9457 int ret;
9458
9459 /* if one seid is 0, the other must be 0 to create a floating relay */
9460 if ((uplink_seid == 0 || vsi_seid == 0) &&
9461 (uplink_seid + vsi_seid != 0)) {
9462 dev_info(&pf->pdev->dev,
9463 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9464 uplink_seid, vsi_seid);
9465 return NULL;
9466 }
9467
9468 /* make sure there is such a vsi and uplink */
505682cd 9469 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9470 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9471 break;
505682cd 9472 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9473 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9474 vsi_seid);
9475 return NULL;
9476 }
9477
9478 if (uplink_seid && uplink_seid != pf->mac_seid) {
9479 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9480 if (pf->veb[veb_idx] &&
9481 pf->veb[veb_idx]->seid == uplink_seid) {
9482 uplink_veb = pf->veb[veb_idx];
9483 break;
9484 }
9485 }
9486 if (!uplink_veb) {
9487 dev_info(&pf->pdev->dev,
9488 "uplink seid %d not found\n", uplink_seid);
9489 return NULL;
9490 }
9491 }
9492
9493 /* get veb sw struct */
9494 veb_idx = i40e_veb_mem_alloc(pf);
9495 if (veb_idx < 0)
9496 goto err_alloc;
9497 veb = pf->veb[veb_idx];
9498 veb->flags = flags;
9499 veb->uplink_seid = uplink_seid;
9500 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9501 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9502
9503 /* create the VEB in the switch */
9504 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9505 if (ret)
9506 goto err_veb;
1bb8b935
SN		 9507 if (vsi_idx == pf->lan_vsi)
9508 pf->lan_veb = veb->idx;
41c445ff
JB		 9509
9510 return veb;
9511
9512err_veb:
9513 i40e_veb_clear(veb);
9514err_alloc:
9515 return NULL;
9516}
9517
9518/**
b40c82e6 9519 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9520 * @pf: board private structure
9521 * @ele: element we are building info from
9522 * @num_reported: total number of elements
9523 * @printconfig: should we print the contents
9524 *
9525 * helper function to assist in extracting a few useful SEID values.
9526 **/
9527static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9528 struct i40e_aqc_switch_config_element_resp *ele,
9529 u16 num_reported, bool printconfig)
9530{
9531 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9532 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9533 u8 element_type = ele->element_type;
9534 u16 seid = le16_to_cpu(ele->seid);
9535
9536 if (printconfig)
9537 dev_info(&pf->pdev->dev,
9538 "type=%d seid=%d uplink=%d downlink=%d\n",
9539 element_type, seid, uplink_seid, downlink_seid);
9540
9541 switch (element_type) {
9542 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9543 pf->mac_seid = seid;
9544 break;
9545 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9546 /* Main VEB? */
9547 if (uplink_seid != pf->mac_seid)
9548 break;
9549 if (pf->lan_veb == I40E_NO_VEB) {
9550 int v;
9551
9552 /* find existing or else empty VEB */
9553 for (v = 0; v < I40E_MAX_VEB; v++) {
9554 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9555 pf->lan_veb = v;
9556 break;
9557 }
9558 }
9559 if (pf->lan_veb == I40E_NO_VEB) {
9560 v = i40e_veb_mem_alloc(pf);
9561 if (v < 0)
9562 break;
9563 pf->lan_veb = v;
9564 }
9565 }
9566
9567 pf->veb[pf->lan_veb]->seid = seid;
9568 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9569 pf->veb[pf->lan_veb]->pf = pf;
9570 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9571 break;
9572 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9573 if (num_reported != 1)
9574 break;
9575 /* This is immediately after a reset so we can assume this is
9576 * the PF's VSI
9577 */
9578 pf->mac_seid = uplink_seid;
9579 pf->pf_seid = downlink_seid;
9580 pf->main_vsi_seid = seid;
9581 if (printconfig)
9582 dev_info(&pf->pdev->dev,
9583 "pf_seid=%d main_vsi_seid=%d\n",
9584 pf->pf_seid, pf->main_vsi_seid);
9585 break;
9586 case I40E_SWITCH_ELEMENT_TYPE_PF:
9587 case I40E_SWITCH_ELEMENT_TYPE_VF:
9588 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9589 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9590 case I40E_SWITCH_ELEMENT_TYPE_PE:
9591 case I40E_SWITCH_ELEMENT_TYPE_PA:
9592 /* ignore these for now */
9593 break;
9594 default:
9595 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9596 element_type, seid);
9597 break;
9598 }
9599}
9600
9601/**
9602 * i40e_fetch_switch_configuration - Get switch config from firmware
9603 * @pf: board private structure
9604 * @printconfig: should we print the contents
9605 *
9606 * Get the current switch configuration from the device and
9607 * extract a few useful SEID values.
9608 **/
9609int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9610{
9611 struct i40e_aqc_get_switch_config_resp *sw_config;
9612 u16 next_seid = 0;
9613 int ret = 0;
9614 u8 *aq_buf;
9615 int i;
9616
9617 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9618 if (!aq_buf)
9619 return -ENOMEM;
9620
9621 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9622 do {
9623 u16 num_reported, num_total;
9624
9625 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9626 I40E_AQ_LARGE_BUF,
9627 &next_seid, NULL);
9628 if (ret) {
9629 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9630 "get switch config failed err %s aq_err %s\n",
9631 i40e_stat_str(&pf->hw, ret),
9632 i40e_aq_str(&pf->hw,
9633 pf->hw.aq.asq_last_status));
41c445ff
JB		 9634 kfree(aq_buf);
9635 return -ENOENT;
9636 }
9637
9638 num_reported = le16_to_cpu(sw_config->header.num_reported);
9639 num_total = le16_to_cpu(sw_config->header.num_total);
9640
9641 if (printconfig)
9642 dev_info(&pf->pdev->dev,
9643 "header: %d reported %d total\n",
9644 num_reported, num_total);
9645
41c445ff
JB		 9646 for (i = 0; i < num_reported; i++) {
9647 struct i40e_aqc_switch_config_element_resp *ele =
9648 &sw_config->element[i];
9649
9650 i40e_setup_pf_switch_element(pf, ele, num_reported,
9651 printconfig);
9652 }
9653 } while (next_seid != 0);
9654
9655 kfree(aq_buf);
9656 return ret;
9657}
9658
9659/**
9660 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9661 * @pf: board private structure
bc7d338f 9662 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9663 *
9664 * Returns 0 on success, negative value on failure
9665 **/
bc7d338f 9666static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9667{
9668 int ret;
9669
9670 /* find out what's out there already */
9671 ret = i40e_fetch_switch_configuration(pf, false);
9672 if (ret) {
9673 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9674 "couldn't fetch switch config, err %s aq_err %s\n",
9675 i40e_stat_str(&pf->hw, ret),
9676 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9677 return ret;
9678 }
9679 i40e_pf_reset_stats(pf);
9680
41c445ff 9681 /* first time setup */
bc7d338f 9682 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9683 struct i40e_vsi *vsi = NULL;
9684 u16 uplink_seid;
9685
9686 /* Set up the PF VSI associated with the PF's main VSI
9687 * that is already in the HW switch
9688 */
9689 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9690 uplink_seid = pf->veb[pf->lan_veb]->seid;
9691 else
9692 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9693 if (pf->lan_vsi == I40E_NO_VSI)
9694 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9695 else if (reinit)
9696 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9697 if (!vsi) {
9698 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9699 i40e_fdir_teardown(pf);
9700 return -EAGAIN;
9701 }
41c445ff
JB		 9702 } else {
9703 /* force a reset of TC and queue layout configurations */
9704 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 9705
41c445ff
JB		 9706 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9707 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9708 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9709 }
9710 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9711
cbf61325
ASJ		 9712 i40e_fdir_sb_setup(pf);
9713
41c445ff
JB		 9714 /* Setup static PF queue filter control settings */
9715 ret = i40e_setup_pf_filter_control(pf);
9716 if (ret) {
9717 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9718 ret);
9719 /* Failure here should not stop continuing other steps */
9720 }
9721
9722 /* enable RSS in the HW, even for only one queue, as the stack can use
9723 * the hash
9724 */
9725 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9726 i40e_config_rss(pf);
9727
9728 /* fill in link information and enable LSE reporting */
0a862b43 9729 i40e_update_link_info(&pf->hw);
a34a6711
MW		 9730 i40e_link_event(pf);
9731
d52c20b7 9732 /* Initialize user-specific link properties */
41c445ff
JB		 9733 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9734 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9735
beb0dff1
JK		 9736 i40e_ptp_init(pf);
9737
41c445ff
JB		 9738 return ret;
9739}
9740
41c445ff
JB		 9741/**
9742 * i40e_determine_queue_usage - Work out queue distribution
9743 * @pf: board private structure
9744 **/
9745static void i40e_determine_queue_usage(struct i40e_pf *pf)
9746{
41c445ff
JB		 9747 int queues_left;
9748
9749 pf->num_lan_qps = 0;
38e00438
VD		 9750#ifdef I40E_FCOE
9751 pf->num_fcoe_qps = 0;
9752#endif
41c445ff
JB		 9753
9754 /* Find the max queues to be put into basic use. We'll always be
9755 * using TC0, whether or not DCB is running, and TC0 will get the
9756 * big RSS set.
9757 */
9758 queues_left = pf->hw.func_caps.num_tx_qp;
9759
cbf61325 9760 if ((queues_left == 1) ||
9aa7e935 9761 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9762 /* one qp for PF, no queues for anything else */
9763 queues_left = 0;
9764 pf->rss_size = pf->num_lan_qps = 1;
9765
9766 /* make sure all the fancies are disabled */
60ea5f83 9767 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9768#ifdef I40E_FCOE
9769 I40E_FLAG_FCOE_ENABLED |
9770#endif
60ea5f83
JB		 9771 I40E_FLAG_FD_SB_ENABLED |
9772 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9773 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9774 I40E_FLAG_SRIOV_ENABLED |
9775 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9776 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9777 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9778 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9779 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9780 /* one qp for PF */
9781 pf->rss_size = pf->num_lan_qps = 1;
9782 queues_left -= pf->num_lan_qps;
9783
9784 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9785#ifdef I40E_FCOE
9786 I40E_FLAG_FCOE_ENABLED |
9787#endif
9aa7e935
FZ		 9788 I40E_FLAG_FD_SB_ENABLED |
9789 I40E_FLAG_FD_ATR_ENABLED |
9790 I40E_FLAG_DCB_ENABLED |
9791 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9792 } else {
cbf61325 9793 /* Not enough queues for all TCs */
4d9b6043 9794 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9795 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9796 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9797 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9798 }
9a3bd2f1
ASJ		 9799 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9800 num_online_cpus());
9801 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9802 pf->hw.func_caps.num_tx_qp);
9803
cbf61325
ASJ		 9804 queues_left -= pf->num_lan_qps;
9805 }
9806
38e00438
VD		 9807#ifdef I40E_FCOE
9808 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9809 if (I40E_DEFAULT_FCOE <= queues_left) {
9810 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9811 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9812 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9813 } else {
9814 pf->num_fcoe_qps = 0;
9815 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9816 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9817 }
9818
9819 queues_left -= pf->num_fcoe_qps;
9820 }
9821
9822#endif
cbf61325
ASJ		 9823 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9824 if (queues_left > 1) {
9825 queues_left -= 1; /* save 1 queue for FD */
9826 } else {
9827 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9828 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9829 }
41c445ff
JB		 9830 }
9831
9832 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9833 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9834 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9835 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9836 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9837 }
9838
9839 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9840 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9841 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9842 (queues_left / pf->num_vmdq_qps));
9843 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9844 }
9845
f8ff1464 9846 pf->queues_left = queues_left;
8279e495
NP		 9847 dev_dbg(&pf->pdev->dev,
9848 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
9849 pf->hw.func_caps.num_tx_qp,
9850 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
9851 pf->num_lan_qps, pf->rss_size, pf->num_req_vfs, pf->num_vf_qps,
9852 pf->num_vmdq_vsis, pf->num_vmdq_qps, queues_left);
38e00438 9853#ifdef I40E_FCOE
8279e495 9854 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 9855#endif
41c445ff
JB		 9856}
9857
9858/**
9859 * i40e_setup_pf_filter_control - Setup PF static filter control
9860 * @pf: PF to be setup
9861 *
b40c82e6 9862 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9863 * settings. If PE/FCoE are enabled then it will also set the per PF
9864 * based filter sizes required for them. It also enables Flow director,
9865 * ethertype and macvlan type filter settings for the pf.
9866 *
9867 * Returns 0 on success, negative on failure
9868 **/
9869static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9870{
9871 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9872
9873 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9874
9875 /* Flow Director is enabled */
60ea5f83 9876 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9877 settings->enable_fdir = true;
9878
9879 /* Ethtype and MACVLAN filters enabled for PF */
9880 settings->enable_ethtype = true;
9881 settings->enable_macvlan = true;
9882
9883 if (i40e_set_filter_control(&pf->hw, settings))
9884 return -ENOENT;
9885
9886 return 0;
9887}
9888
0c22b3dd
JB		 9889#define INFO_STRING_LEN 255
9890static void i40e_print_features(struct i40e_pf *pf)
9891{
9892 struct i40e_hw *hw = &pf->hw;
9893 char *buf, *string;
9894
9895 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9896 if (!string) {
9897 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9898 return;
9899 }
9900
9901 buf = string;
9902
9903 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9904#ifdef CONFIG_PCI_IOV
9905 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9906#endif
aba237d1
MW		 9907 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9908 pf->hw.func_caps.num_vsis,
9909 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9910 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9911
9912 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9913 buf += sprintf(buf, "RSS ");
0c22b3dd 9914 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9915 buf += sprintf(buf, "FD_ATR ");
9916 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9917 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9918 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9919 }
4d9b6043 9920 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd 9921 buf += sprintf(buf, "DCB ");
ce6fcb3f
JB		 9922#if IS_ENABLED(CONFIG_VXLAN)
9923 buf += sprintf(buf, "VxLAN ");
9924#endif
0c22b3dd
JB		 9925 if (pf->flags & I40E_FLAG_PTP)
9926 buf += sprintf(buf, "PTP ");
38e00438
VD		 9927#ifdef I40E_FCOE
9928 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9929 buf += sprintf(buf, "FCOE ");
9930#endif
6dec1017
SN		 9931 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
9932 buf += sprintf(buf, "VEB ");
9933 else
9934 buf += sprintf(buf, "VEPA ");
0c22b3dd
JB		 9935
9936 BUG_ON(buf > (string + INFO_STRING_LEN));
9937 dev_info(&pf->pdev->dev, "%s\n", string);
9938 kfree(string);
9939}
9940
41c445ff
JB		 9941/**
9942 * i40e_probe - Device initialization routine
9943 * @pdev: PCI device information struct
9944 * @ent: entry in i40e_pci_tbl
9945 *
b40c82e6
JK		 9946 * i40e_probe initializes a PF identified by a pci_dev structure.
9947 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9948 * and a hardware reset occur.
9949 *
9950 * Returns 0 on success, negative on failure
9951 **/
9952static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9953{
e827845c 9954 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9955 struct i40e_pf *pf;
9956 struct i40e_hw *hw;
93cd765b 9957 static u16 pfs_found;
1d5109d1 9958 u16 wol_nvm_bits;
d4dfb81a 9959 u16 link_status;
41c445ff
JB		 9960 int err = 0;
9961 u32 len;
8a9eb7d3 9962 u32 i;
41c445ff
JB		 9963
9964 err = pci_enable_device_mem(pdev);
9965 if (err)
9966 return err;
9967
9968 /* set up for high or low dma */
6494294f 9969 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9970 if (err) {
e3e3bfdd
JS		 9971 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9972 if (err) {
9973 dev_err(&pdev->dev,
9974 "DMA configuration failed: 0x%x\n", err);
9975 goto err_dma;
9976 }
41c445ff
JB		 9977 }
9978
9979 /* set up pci connections */
9980 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9981 IORESOURCE_MEM), i40e_driver_name);
9982 if (err) {
9983 dev_info(&pdev->dev,
9984 "pci_request_selected_regions failed %d\n", err);
9985 goto err_pci_reg;
9986 }
9987
9988 pci_enable_pcie_error_reporting(pdev);
9989 pci_set_master(pdev);
9990
9991 /* Now that we have a PCI connection, we need to do the
9992 * low level device setup. This is primarily setting up
9993 * the Admin Queue structures and then querying for the
9994 * device's current profile information.
9995 */
9996 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9997 if (!pf) {
9998 err = -ENOMEM;
9999 goto err_pf_alloc;
10000 }
10001 pf->next_vsi = 0;
10002 pf->pdev = pdev;
10003 set_bit(__I40E_DOWN, &pf->state);
10004
10005 hw = &pf->hw;
10006 hw->back = pf;
232f4706 10007
2ac8b675
SN		 10008 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10009 I40E_MAX_CSR_SPACE);
232f4706 10010
2ac8b675 10011 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10012 if (!hw->hw_addr) {
10013 err = -EIO;
10014 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10015 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10016 pf->ioremap_len, err);
41c445ff
JB		 10017 goto err_ioremap;
10018 }
10019 hw->vendor_id = pdev->vendor;
10020 hw->device_id = pdev->device;
10021 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10022 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10023 hw->subsystem_device_id = pdev->subsystem_device;
10024 hw->bus.device = PCI_SLOT(pdev->devfn);
10025 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10026 pf->instance = pfs_found;
41c445ff 10027
5b5faa43
SN		 10028 if (debug != -1) {
10029 pf->msg_enable = pf->hw.debug_mask;
10030 pf->msg_enable = debug;
10031 }
10032
7134f9ce
JB		 10033 /* do a special CORER for clearing PXE mode once at init */
10034 if (hw->revision_id == 0 &&
10035 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10036 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10037 i40e_flush(hw);
10038 msleep(200);
10039 pf->corer_count++;
10040
10041 i40e_clear_pxe_mode(hw);
10042 }
10043
41c445ff 10044 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10045 i40e_clear_hw(hw);
41c445ff
JB		 10046 err = i40e_pf_reset(hw);
10047 if (err) {
10048 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10049 goto err_pf_reset;
10050 }
10051 pf->pfr_count++;
10052
10053 hw->aq.num_arq_entries = I40E_AQ_LEN;
10054 hw->aq.num_asq_entries = I40E_AQ_LEN;
10055 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10056 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10057 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10058
b294ac70 10059 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10060 "%s-%s:misc",
10061 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10062
10063 err = i40e_init_shared_code(hw);
10064 if (err) {
b2a75c58
ASJ		 10065 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10066 err);
41c445ff
JB		 10067 goto err_pf_reset;
10068 }
10069
d52c20b7
JB		 10070 /* set up a default setting for link flow control */
10071 pf->hw.fc.requested_mode = I40E_FC_NONE;
10072
41c445ff 10073 err = i40e_init_adminq(hw);
f0b44440 10074
6dec1017
SN		 10075 /* provide nvm, fw, api versions */
10076 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10077 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10078 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10079 i40e_nvm_version_str(hw));
f0b44440 10080
41c445ff
JB		 10081 if (err) {
10082 dev_info(&pdev->dev,
7aa67613 10083 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10084 goto err_pf_reset;
10085 }
10086
7aa67613
CS		 10087 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10088 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10089 dev_info(&pdev->dev,
7aa67613
CS		 10090 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10091 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10092 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10093 dev_info(&pdev->dev,
7aa67613 10094 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10095
4eb3f768
SN		 10096 i40e_verify_eeprom(pf);
10097
2c5fe33b
JB		 10098 /* Rev 0 hardware was never productized */
10099 if (hw->revision_id < 1)
10100 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10101
6ff4ef86 10102 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10103 err = i40e_get_capabilities(pf);
10104 if (err)
10105 goto err_adminq_setup;
10106
10107 err = i40e_sw_init(pf);
10108 if (err) {
10109 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10110 goto err_sw_init;
10111 }
10112
10113 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10114 hw->func_caps.num_rx_qp,
10115 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10116 if (err) {
10117 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10118 goto err_init_lan_hmc;
10119 }
10120
10121 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10122 if (err) {
10123 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10124 err = -ENOENT;
10125 goto err_configure_lan_hmc;
10126 }
10127
b686ece5
NP		 10128 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10129 * Ignore error return codes because if it was already disabled via
10130 * hardware settings this will fail
10131 */
10132 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10133 (pf->hw.aq.fw_maj_ver < 4)) {
10134 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10135 i40e_aq_stop_lldp(hw, true, NULL);
10136 }
10137
41c445ff 10138 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10139 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10140 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10141 err = -EIO;
10142 goto err_mac_addr;
10143 }
10144 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10145 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10146 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10147 if (is_valid_ether_addr(hw->mac.port_addr))
10148 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10149#ifdef I40E_FCOE
10150 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10151 if (err)
10152 dev_info(&pdev->dev,
10153 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10154 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10155 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10156 hw->mac.san_addr);
10157 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10158 }
10159 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10160#endif /* I40E_FCOE */
41c445ff
JB		 10161
10162 pci_set_drvdata(pdev, pf);
10163 pci_save_state(pdev);
4e3b35b0
NP		 10164#ifdef CONFIG_I40E_DCB
10165 err = i40e_init_pf_dcb(pf);
10166 if (err) {
aebfc816 10167 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10168 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10169 /* Continue without DCB enabled */
4e3b35b0
NP		 10170 }
10171#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10172
10173 /* set up periodic task facility */
10174 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10175 pf->service_timer_period = HZ;
10176
10177 INIT_WORK(&pf->service_task, i40e_service_task);
10178 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10179 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10180
1d5109d1
SN		 10181 /* NVM bit on means WoL disabled for the port */
10182 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10183 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10184 pf->wol_en = false;
10185 else
10186 pf->wol_en = true;
8e2773ae
SN		 10187 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10188
41c445ff
JB		 10189 /* set up the main switch operations */
10190 i40e_determine_queue_usage(pf);
c1147280
JB		 10191 err = i40e_init_interrupt_scheme(pf);
10192 if (err)
10193 goto err_switch_setup;
41c445ff 10194
505682cd
MW		 10195 /* The number of VSIs reported by the FW is the minimum guaranteed
10196 * to us; HW supports far more and we share the remaining pool with
10197 * the other PFs. We allocate space for more than the guarantee with
10198 * the understanding that we might not get them all later.
41c445ff 10199 */
505682cd
MW		 10200 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10201 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10202 else
10203 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10204
10205 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10206 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10207 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10208 if (!pf->vsi) {
10209 err = -ENOMEM;
41c445ff 10210 goto err_switch_setup;
ed87ac09 10211 }
41c445ff 10212
fa11cb3d
ASJ		 10213#ifdef CONFIG_PCI_IOV
10214 /* prep for VF support */
10215 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10216 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10217 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10218 if (pci_num_vf(pdev))
10219 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10220 }
10221#endif
bc7d338f 10222 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10223 if (err) {
10224 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10225 goto err_vsis;
10226 }
8a9eb7d3 10227 /* if FDIR VSI was set up, start it now */
505682cd 10228 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10229 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10230 i40e_vsi_open(pf->vsi[i]);
10231 break;
10232 }
10233 }
41c445ff 10234
7e2453fe
JB		 10235 /* driver is only interested in link up/down and module qualification
10236 * reports from firmware
10237 */
10238 err = i40e_aq_set_phy_int_mask(&pf->hw,
10239 I40E_AQ_EVENT_LINK_UPDOWN |
10240 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10241 if (err)
f1c7e72e
SN		 10242 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10243 i40e_stat_str(&pf->hw, err),
10244 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10245
025b4a54
ASJ		 10246 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10247 (pf->hw.aq.fw_maj_ver < 4)) {
10248 msleep(75);
10249 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10250 if (err)
f1c7e72e
SN		 10251 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10252 i40e_stat_str(&pf->hw, err),
10253 i40e_aq_str(&pf->hw,
10254 pf->hw.aq.asq_last_status));
cafa2ee6 10255 }
41c445ff
JB		 10256 /* The main driver is (mostly) up and happy. We need to set this state
10257 * before setting up the misc vector or we get a race and the vector
10258 * ends up disabled forever.
10259 */
10260 clear_bit(__I40E_DOWN, &pf->state);
10261
10262 /* In case of MSIX we are going to setup the misc vector right here
10263 * to handle admin queue events etc. In case of legacy and MSI
10264 * the misc functionality and queue processing is combined in
10265 * the same vector and that gets setup at open.
10266 */
10267 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10268 err = i40e_setup_misc_vector(pf);
10269 if (err) {
10270 dev_info(&pdev->dev,
10271 "setup of misc vector failed: %d\n", err);
10272 goto err_vsis;
10273 }
10274 }
10275
df805f62 10276#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10277 /* prep for VF support */
10278 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10279 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10280 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10281 u32 val;
10282
10283 /* disable link interrupts for VFs */
10284 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10285 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10286 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10287 i40e_flush(hw);
4aeec010
MW		 10288
10289 if (pci_num_vf(pdev)) {
10290 dev_info(&pdev->dev,
10291 "Active VFs found, allocating resources.\n");
10292 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10293 if (err)
10294 dev_info(&pdev->dev,
10295 "Error %d allocating resources for existing VFs\n",
10296 err);
10297 }
41c445ff 10298 }
df805f62 10299#endif /* CONFIG_PCI_IOV */
41c445ff 10300
93cd765b
ASJ		 10301 pfs_found++;
10302
41c445ff
JB		 10303 i40e_dbg_pf_init(pf);
10304
10305 /* tell the firmware that we're starting */
44033fac 10306 i40e_send_version(pf);
41c445ff
JB		 10307
10308 /* since everything's happy, start the service_task timer */
10309 mod_timer(&pf->service_timer,
10310 round_jiffies(jiffies + pf->service_timer_period));
10311
38e00438
VD		 10312#ifdef I40E_FCOE
10313 /* create FCoE interface */
10314 i40e_fcoe_vsi_setup(pf);
10315
10316#endif
3fced535
ASJ		 10317#define PCI_SPEED_SIZE 8
10318#define PCI_WIDTH_SIZE 8
10319 /* Devices on the IOSF bus do not have this information
10320 * and will report PCI Gen 1 x 1 by default so don't bother
10321 * checking them.
10322 */
10323 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10324 char speed[PCI_SPEED_SIZE] = "Unknown";
10325 char width[PCI_WIDTH_SIZE] = "Unknown";
10326
10327 /* Get the negotiated link width and speed from PCI config
10328 * space
10329 */
10330 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10331 &link_status);
10332
10333 i40e_set_pci_config_data(hw, link_status);
10334
10335 switch (hw->bus.speed) {
10336 case i40e_bus_speed_8000:
10337 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10338 case i40e_bus_speed_5000:
10339 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10340 case i40e_bus_speed_2500:
10341 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10342 default:
10343 break;
10344 }
10345 switch (hw->bus.width) {
10346 case i40e_bus_width_pcie_x8:
10347 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10348 case i40e_bus_width_pcie_x4:
10349 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10350 case i40e_bus_width_pcie_x2:
10351 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10352 case i40e_bus_width_pcie_x1:
10353 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10354 default:
10355 break;
10356 }
10357
10358 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10359 speed, width);
10360
10361 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10362 hw->bus.speed < i40e_bus_speed_8000) {
10363 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10364 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10365 }
d4dfb81a
CS		 10366 }
10367
e827845c
CS		 10368 /* get the requested speeds from the fw */
10369 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10370 if (err)
8279e495
NP		 10371 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10372 i40e_stat_str(&pf->hw, err),
10373 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10374 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10375
fc72dbce
CS		 10376 /* get the supported phy types from the fw */
10377 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10378 if (err)
10379 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10380 i40e_stat_str(&pf->hw, err),
10381 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10382 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10383
0c22b3dd
JB		 10384 /* print a string summarizing features */
10385 i40e_print_features(pf);
10386
41c445ff
JB		 10387 return 0;
10388
10389 /* Unwind what we've done if something failed in the setup */
10390err_vsis:
10391 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10392 i40e_clear_interrupt_scheme(pf);
10393 kfree(pf->vsi);
04b03013
SN		 10394err_switch_setup:
10395 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10396 del_timer_sync(&pf->service_timer);
10397err_mac_addr:
10398err_configure_lan_hmc:
10399 (void)i40e_shutdown_lan_hmc(hw);
10400err_init_lan_hmc:
10401 kfree(pf->qp_pile);
41c445ff
JB		 10402err_sw_init:
10403err_adminq_setup:
10404 (void)i40e_shutdown_adminq(hw);
10405err_pf_reset:
10406 iounmap(hw->hw_addr);
10407err_ioremap:
10408 kfree(pf);
10409err_pf_alloc:
10410 pci_disable_pcie_error_reporting(pdev);
10411 pci_release_selected_regions(pdev,
10412 pci_select_bars(pdev, IORESOURCE_MEM));
10413err_pci_reg:
10414err_dma:
10415 pci_disable_device(pdev);
10416 return err;
10417}
10418
10419/**
10420 * i40e_remove - Device removal routine
10421 * @pdev: PCI device information struct
10422 *
10423 * i40e_remove is called by the PCI subsystem to alert the driver
10424 * that is should release a PCI device. This could be caused by a
10425 * Hot-Plug event, or because the driver is going to be removed from
10426 * memory.
10427 **/
10428static void i40e_remove(struct pci_dev *pdev)
10429{
10430 struct i40e_pf *pf = pci_get_drvdata(pdev);
10431 i40e_status ret_code;
41c445ff
JB		 10432 int i;
10433
10434 i40e_dbg_pf_exit(pf);
10435
beb0dff1
JK		 10436 i40e_ptp_stop(pf);
10437
41c445ff
JB		 10438 /* no more scheduling of any task */
10439 set_bit(__I40E_DOWN, &pf->state);
10440 del_timer_sync(&pf->service_timer);
10441 cancel_work_sync(&pf->service_task);
33c62b34 10442 i40e_fdir_teardown(pf);
41c445ff 10443
eb2d80bc
MW		 10444 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10445 i40e_free_vfs(pf);
10446 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10447 }
10448
41c445ff
JB		 10449 i40e_fdir_teardown(pf);
10450
10451 /* If there is a switch structure or any orphans, remove them.
10452 * This will leave only the PF's VSI remaining.
10453 */
10454 for (i = 0; i < I40E_MAX_VEB; i++) {
10455 if (!pf->veb[i])
10456 continue;
10457
10458 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10459 pf->veb[i]->uplink_seid == 0)
10460 i40e_switch_branch_release(pf->veb[i]);
10461 }
10462
10463 /* Now we can shutdown the PF's VSI, just before we kill
10464 * adminq and hmc.
10465 */
10466 if (pf->vsi[pf->lan_vsi])
10467 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10468
41c445ff 10469 /* shutdown and destroy the HMC */
60442dea
SN		 10470 if (pf->hw.hmc.hmc_obj) {
10471 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10472 if (ret_code)
10473 dev_warn(&pdev->dev,
10474 "Failed to destroy the HMC resources: %d\n",
10475 ret_code);
10476 }
41c445ff
JB		 10477
10478 /* shutdown the adminq */
41c445ff
JB		 10479 ret_code = i40e_shutdown_adminq(&pf->hw);
10480 if (ret_code)
10481 dev_warn(&pdev->dev,
10482 "Failed to destroy the Admin Queue resources: %d\n",
10483 ret_code);
10484
10485 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10486 i40e_clear_interrupt_scheme(pf);
505682cd 10487 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10488 if (pf->vsi[i]) {
10489 i40e_vsi_clear_rings(pf->vsi[i]);
10490 i40e_vsi_clear(pf->vsi[i]);
10491 pf->vsi[i] = NULL;
10492 }
10493 }
10494
10495 for (i = 0; i < I40E_MAX_VEB; i++) {
10496 kfree(pf->veb[i]);
10497 pf->veb[i] = NULL;
10498 }
10499
10500 kfree(pf->qp_pile);
41c445ff
JB		 10501 kfree(pf->vsi);
10502
41c445ff
JB		 10503 iounmap(pf->hw.hw_addr);
10504 kfree(pf);
10505 pci_release_selected_regions(pdev,
10506 pci_select_bars(pdev, IORESOURCE_MEM));
10507
10508 pci_disable_pcie_error_reporting(pdev);
10509 pci_disable_device(pdev);
10510}
10511
10512/**
10513 * i40e_pci_error_detected - warning that something funky happened in PCI land
10514 * @pdev: PCI device information struct
10515 *
10516 * Called to warn that something happened and the error handling steps
10517 * are in progress. Allows the driver to quiesce things, be ready for
10518 * remediation.
10519 **/
10520static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10521 enum pci_channel_state error)
10522{
10523 struct i40e_pf *pf = pci_get_drvdata(pdev);
10524
10525 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10526
10527 /* shutdown all operations */
9007bccd
SN		 10528 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10529 rtnl_lock();
10530 i40e_prep_for_reset(pf);
10531 rtnl_unlock();
10532 }
41c445ff
JB		 10533
10534 /* Request a slot reset */
10535 return PCI_ERS_RESULT_NEED_RESET;
10536}
10537
10538/**
10539 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10540 * @pdev: PCI device information struct
10541 *
10542 * Called to find if the driver can work with the device now that
10543 * the pci slot has been reset. If a basic connection seems good
10544 * (registers are readable and have sane content) then return a
10545 * happy little PCI_ERS_RESULT_xxx.
10546 **/
10547static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10548{
10549 struct i40e_pf *pf = pci_get_drvdata(pdev);
10550 pci_ers_result_t result;
10551 int err;
10552 u32 reg;
10553
fb43201f 10554 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 10555 if (pci_enable_device_mem(pdev)) {
10556 dev_info(&pdev->dev,
10557 "Cannot re-enable PCI device after reset.\n");
10558 result = PCI_ERS_RESULT_DISCONNECT;
10559 } else {
10560 pci_set_master(pdev);
10561 pci_restore_state(pdev);
10562 pci_save_state(pdev);
10563 pci_wake_from_d3(pdev, false);
10564
10565 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10566 if (reg == 0)
10567 result = PCI_ERS_RESULT_RECOVERED;
10568 else
10569 result = PCI_ERS_RESULT_DISCONNECT;
10570 }
10571
10572 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10573 if (err) {
10574 dev_info(&pdev->dev,
10575 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10576 err);
10577 /* non-fatal, continue */
10578 }
10579
10580 return result;
10581}
10582
10583/**
10584 * i40e_pci_error_resume - restart operations after PCI error recovery
10585 * @pdev: PCI device information struct
10586 *
10587 * Called to allow the driver to bring things back up after PCI error
10588 * and/or reset recovery has finished.
10589 **/
10590static void i40e_pci_error_resume(struct pci_dev *pdev)
10591{
10592 struct i40e_pf *pf = pci_get_drvdata(pdev);
10593
fb43201f 10594 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10595 if (test_bit(__I40E_SUSPENDED, &pf->state))
10596 return;
10597
10598 rtnl_lock();
41c445ff 10599 i40e_handle_reset_warning(pf);
4c4935a9 10600 rtnl_unlock();
9007bccd
SN		 10601}
10602
10603/**
10604 * i40e_shutdown - PCI callback for shutting down
10605 * @pdev: PCI device information struct
10606 **/
10607static void i40e_shutdown(struct pci_dev *pdev)
10608{
10609 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10610 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10611
10612 set_bit(__I40E_SUSPENDED, &pf->state);
10613 set_bit(__I40E_DOWN, &pf->state);
10614 rtnl_lock();
10615 i40e_prep_for_reset(pf);
10616 rtnl_unlock();
10617
8e2773ae
SN		 10618 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10619 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10620
02b42498
CS		 10621 del_timer_sync(&pf->service_timer);
10622 cancel_work_sync(&pf->service_task);
10623 i40e_fdir_teardown(pf);
10624
10625 rtnl_lock();
10626 i40e_prep_for_reset(pf);
10627 rtnl_unlock();
10628
10629 wr32(hw, I40E_PFPM_APM,
10630 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10631 wr32(hw, I40E_PFPM_WUFC,
10632 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10633
e147758d
SN		 10634 i40e_clear_interrupt_scheme(pf);
10635
9007bccd 10636 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10637 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10638 pci_set_power_state(pdev, PCI_D3hot);
10639 }
10640}
10641
10642#ifdef CONFIG_PM
10643/**
10644 * i40e_suspend - PCI callback for moving to D3
10645 * @pdev: PCI device information struct
10646 **/
10647static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10648{
10649 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10650 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10651
10652 set_bit(__I40E_SUSPENDED, &pf->state);
10653 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10654
9007bccd
SN		 10655 rtnl_lock();
10656 i40e_prep_for_reset(pf);
10657 rtnl_unlock();
10658
8e2773ae
SN		 10659 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10660 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10661
10662 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10663 pci_set_power_state(pdev, PCI_D3hot);
10664
10665 return 0;
41c445ff
JB		 10666}
10667
9007bccd
SN		 10668/**
10669 * i40e_resume - PCI callback for waking up from D3
10670 * @pdev: PCI device information struct
10671 **/
10672static int i40e_resume(struct pci_dev *pdev)
10673{
10674 struct i40e_pf *pf = pci_get_drvdata(pdev);
10675 u32 err;
10676
10677 pci_set_power_state(pdev, PCI_D0);
10678 pci_restore_state(pdev);
10679 /* pci_restore_state() clears dev->state_saves, so
10680 * call pci_save_state() again to restore it.
10681 */
10682 pci_save_state(pdev);
10683
10684 err = pci_enable_device_mem(pdev);
10685 if (err) {
fb43201f 10686 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 10687 return err;
10688 }
10689 pci_set_master(pdev);
10690
10691 /* no wakeup events while running */
10692 pci_wake_from_d3(pdev, false);
10693
10694 /* handling the reset will rebuild the device state */
10695 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10696 clear_bit(__I40E_DOWN, &pf->state);
10697 rtnl_lock();
10698 i40e_reset_and_rebuild(pf, false);
10699 rtnl_unlock();
10700 }
10701
10702 return 0;
10703}
10704
10705#endif
41c445ff
JB		 10706static const struct pci_error_handlers i40e_err_handler = {
10707 .error_detected = i40e_pci_error_detected,
10708 .slot_reset = i40e_pci_error_slot_reset,
10709 .resume = i40e_pci_error_resume,
10710};
10711
10712static struct pci_driver i40e_driver = {
10713 .name = i40e_driver_name,
10714 .id_table = i40e_pci_tbl,
10715 .probe = i40e_probe,
10716 .remove = i40e_remove,
9007bccd
SN		 10717#ifdef CONFIG_PM
10718 .suspend = i40e_suspend,
10719 .resume = i40e_resume,
10720#endif
10721 .shutdown = i40e_shutdown,
41c445ff
JB		 10722 .err_handler = &i40e_err_handler,
10723 .sriov_configure = i40e_pci_sriov_configure,
10724};
10725
10726/**
10727 * i40e_init_module - Driver registration routine
10728 *
10729 * i40e_init_module is the first routine called when the driver is
10730 * loaded. All it does is register with the PCI subsystem.
10731 **/
10732static int __init i40e_init_module(void)
10733{
10734 pr_info("%s: %s - version %s\n", i40e_driver_name,
10735 i40e_driver_string, i40e_driver_version_str);
10736 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10737
41c445ff
JB		 10738 i40e_dbg_init();
10739 return pci_register_driver(&i40e_driver);
10740}
10741module_init(i40e_init_module);
10742
10743/**
10744 * i40e_exit_module - Driver exit cleanup routine
10745 *
10746 * i40e_exit_module is called just before the driver is removed
10747 * from memory.
10748 **/
10749static void __exit i40e_exit_module(void)
10750{
10751 pci_unregister_driver(&i40e_driver);
10752 i40e_dbg_exit();
10753}
10754module_exit(i40e_exit_module);
Linux kernel - Deliverables
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