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i40e/i40evf: add new device id 1588
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
f91638af 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
ae24b409 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 84 /* required last entry */
85 {0, }
86};
87MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
88
89#define I40E_MAX_VF_COUNT 128
90static int debug = -1;
91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
94MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
95MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRV_VERSION);
98
99/**
100 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
101 * @hw: pointer to the HW structure
102 * @mem: ptr to mem struct to fill out
103 * @size: size of memory requested
104 * @alignment: what to align the allocation to
105 **/
106int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
107 u64 size, u32 alignment)
108{
109 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
110
111 mem->size = ALIGN(size, alignment);
112 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
113 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 114 if (!mem->va)
115 return -ENOMEM;
41c445ff 116
93bc73b8 117 return 0;
41c445ff
JB		 118}
119
120/**
121 * i40e_free_dma_mem_d - OS specific memory free for shared code
122 * @hw: pointer to the HW structure
123 * @mem: ptr to mem struct to free
124 **/
125int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
126{
127 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
128
129 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
130 mem->va = NULL;
131 mem->pa = 0;
132 mem->size = 0;
133
134 return 0;
135}
136
137/**
138 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
139 * @hw: pointer to the HW structure
140 * @mem: ptr to mem struct to fill out
141 * @size: size of memory requested
142 **/
143int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
144 u32 size)
145{
146 mem->size = size;
147 mem->va = kzalloc(size, GFP_KERNEL);
148
93bc73b8
JB		 149 if (!mem->va)
150 return -ENOMEM;
41c445ff 151
93bc73b8 152 return 0;
41c445ff
JB		 153}
154
155/**
156 * i40e_free_virt_mem_d - OS specific memory free for shared code
157 * @hw: pointer to the HW structure
158 * @mem: ptr to mem struct to free
159 **/
160int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
161{
162 /* it's ok to kfree a NULL pointer */
163 kfree(mem->va);
164 mem->va = NULL;
165 mem->size = 0;
166
167 return 0;
168}
169
170/**
171 * i40e_get_lump - find a lump of free generic resource
172 * @pf: board private structure
173 * @pile: the pile of resource to search
174 * @needed: the number of items needed
175 * @id: an owner id to stick on the items assigned
176 *
177 * Returns the base item index of the lump, or negative for error
178 *
179 * The search_hint trick and lack of advanced fit-finding only work
180 * because we're highly likely to have all the same size lump requests.
181 * Linear search time and any fragmentation should be minimal.
182 **/
183static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
184 u16 needed, u16 id)
185{
186 int ret = -ENOMEM;
ddf434ac 187 int i, j;
41c445ff
JB		 188
189 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
190 dev_info(&pf->pdev->dev,
191 "param err: pile=%p needed=%d id=0x%04x\n",
192 pile, needed, id);
193 return -EINVAL;
194 }
195
196 /* start the linear search with an imperfect hint */
197 i = pile->search_hint;
ddf434ac 198 while (i < pile->num_entries) {
41c445ff
JB		 199 /* skip already allocated entries */
200 if (pile->list[i] & I40E_PILE_VALID_BIT) {
201 i++;
202 continue;
203 }
204
205 /* do we have enough in this lump? */
206 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
207 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
208 break;
209 }
210
211 if (j == needed) {
212 /* there was enough, so assign it to the requestor */
213 for (j = 0; j < needed; j++)
214 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
215 ret = i;
216 pile->search_hint = i + j;
ddf434ac 217 break;
41c445ff
JB		 218 } else {
219 /* not enough, so skip over it and continue looking */
220 i += j;
221 }
222 }
223
224 return ret;
225}
226
227/**
228 * i40e_put_lump - return a lump of generic resource
229 * @pile: the pile of resource to search
230 * @index: the base item index
231 * @id: the owner id of the items assigned
232 *
233 * Returns the count of items in the lump
234 **/
235static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
236{
237 int valid_id = (id | I40E_PILE_VALID_BIT);
238 int count = 0;
239 int i;
240
241 if (!pile || index >= pile->num_entries)
242 return -EINVAL;
243
244 for (i = index;
245 i < pile->num_entries && pile->list[i] == valid_id;
246 i++) {
247 pile->list[i] = 0;
248 count++;
249 }
250
251 if (count && index < pile->search_hint)
252 pile->search_hint = index;
253
254 return count;
255}
256
fdf0e0bf
ASJ		 257/**
258 * i40e_find_vsi_from_id - searches for the vsi with the given id
259 * @pf - the pf structure to search for the vsi
260 * @id - id of the vsi it is searching for
261 **/
262struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
263{
264 int i;
265
266 for (i = 0; i < pf->num_alloc_vsi; i++)
267 if (pf->vsi[i] && (pf->vsi[i]->id == id))
268 return pf->vsi[i];
269
270 return NULL;
271}
272
41c445ff
JB		 273/**
274 * i40e_service_event_schedule - Schedule the service task to wake up
275 * @pf: board private structure
276 *
277 * If not already scheduled, this puts the task into the work queue
278 **/
279static void i40e_service_event_schedule(struct i40e_pf *pf)
280{
281 if (!test_bit(__I40E_DOWN, &pf->state) &&
282 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
283 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
284 schedule_work(&pf->service_task);
285}
286
287/**
288 * i40e_tx_timeout - Respond to a Tx Hang
289 * @netdev: network interface device structure
290 *
291 * If any port has noticed a Tx timeout, it is likely that the whole
292 * device is munged, not just the one netdev port, so go for the full
293 * reset.
294 **/
38e00438
VD		 295#ifdef I40E_FCOE
296void i40e_tx_timeout(struct net_device *netdev)
297#else
41c445ff 298static void i40e_tx_timeout(struct net_device *netdev)
38e00438 299#endif
41c445ff
JB		 300{
301 struct i40e_netdev_priv *np = netdev_priv(netdev);
302 struct i40e_vsi *vsi = np->vsi;
303 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 304 struct i40e_ring *tx_ring = NULL;
305 unsigned int i, hung_queue = 0;
306 u32 head, val;
41c445ff
JB		 307
308 pf->tx_timeout_count++;
309
b03a8c1f
KP		 310 /* find the stopped queue the same way the stack does */
311 for (i = 0; i < netdev->num_tx_queues; i++) {
312 struct netdev_queue *q;
313 unsigned long trans_start;
314
315 q = netdev_get_tx_queue(netdev, i);
316 trans_start = q->trans_start ? : netdev->trans_start;
317 if (netif_xmit_stopped(q) &&
318 time_after(jiffies,
319 (trans_start + netdev->watchdog_timeo))) {
320 hung_queue = i;
321 break;
322 }
323 }
324
325 if (i == netdev->num_tx_queues) {
326 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
327 } else {
328 /* now that we have an index, find the tx_ring struct */
329 for (i = 0; i < vsi->num_queue_pairs; i++) {
330 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
331 if (hung_queue ==
332 vsi->tx_rings[i]->queue_index) {
333 tx_ring = vsi->tx_rings[i];
334 break;
335 }
336 }
337 }
338 }
339
41c445ff 340 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 341 pf->tx_timeout_recovery_level = 1; /* reset after some time */
342 else if (time_before(jiffies,
343 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
344 return; /* don't do any new action before the next timeout */
345
346 if (tx_ring) {
347 head = i40e_get_head(tx_ring);
348 /* Read interrupt register */
349 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
350 val = rd32(&pf->hw,
351 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
352 tx_ring->vsi->base_vector - 1));
353 else
354 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
355
356 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
357 vsi->seid, hung_queue, tx_ring->next_to_clean,
358 head, tx_ring->next_to_use,
359 readl(tx_ring->tail), val);
360 }
361
41c445ff 362 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 363 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
364 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 365
366 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 367 case 1:
368 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
369 break;
370 case 2:
371 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
372 break;
373 case 3:
374 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
375 break;
376 default:
377 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 378 break;
379 }
b03a8c1f 380
41c445ff
JB		 381 i40e_service_event_schedule(pf);
382 pf->tx_timeout_recovery_level++;
383}
384
385/**
386 * i40e_release_rx_desc - Store the new tail and head values
387 * @rx_ring: ring to bump
388 * @val: new head index
389 **/
390static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
391{
392 rx_ring->next_to_use = val;
393
394 /* Force memory writes to complete before letting h/w
395 * know there are new descriptors to fetch. (Only
396 * applicable for weak-ordered memory model archs,
397 * such as IA-64).
398 */
399 wmb();
400 writel(val, rx_ring->tail);
401}
402
403/**
404 * i40e_get_vsi_stats_struct - Get System Network Statistics
405 * @vsi: the VSI we care about
406 *
407 * Returns the address of the device statistics structure.
408 * The statistics are actually updated from the service task.
409 **/
410struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
411{
412 return &vsi->net_stats;
413}
414
415/**
416 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
417 * @netdev: network interface device structure
418 *
419 * Returns the address of the device statistics structure.
420 * The statistics are actually updated from the service task.
421 **/
38e00438
VD		 422#ifdef I40E_FCOE
423struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
424 struct net_device *netdev,
425 struct rtnl_link_stats64 *stats)
426#else
41c445ff
JB		 427static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
428 struct net_device *netdev,
980e9b11 429 struct rtnl_link_stats64 *stats)
38e00438 430#endif
41c445ff
JB		 431{
432 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 433 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 434 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 435 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
436 int i;
437
bc7d338f
ASJ		 438 if (test_bit(__I40E_DOWN, &vsi->state))
439 return stats;
440
3c325ced
JB		 441 if (!vsi->tx_rings)
442 return stats;
443
980e9b11
AD		 444 rcu_read_lock();
445 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 446 u64 bytes, packets;
447 unsigned int start;
448
449 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
450 if (!tx_ring)
451 continue;
452
453 do {
57a7744e 454 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 455 packets = tx_ring->stats.packets;
456 bytes = tx_ring->stats.bytes;
57a7744e 457 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 458
459 stats->tx_packets += packets;
460 stats->tx_bytes += bytes;
461 rx_ring = &tx_ring[1];
462
463 do {
57a7744e 464 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 465 packets = rx_ring->stats.packets;
466 bytes = rx_ring->stats.bytes;
57a7744e 467 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 468
980e9b11
AD		 469 stats->rx_packets += packets;
470 stats->rx_bytes += bytes;
471 }
472 rcu_read_unlock();
473
a5282f44 474 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 475 stats->multicast = vsi_stats->multicast;
476 stats->tx_errors = vsi_stats->tx_errors;
477 stats->tx_dropped = vsi_stats->tx_dropped;
478 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 479 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 480 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
481 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 482
980e9b11 483 return stats;
41c445ff
JB		 484}
485
486/**
487 * i40e_vsi_reset_stats - Resets all stats of the given vsi
488 * @vsi: the VSI to have its stats reset
489 **/
490void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
491{
492 struct rtnl_link_stats64 *ns;
493 int i;
494
495 if (!vsi)
496 return;
497
498 ns = i40e_get_vsi_stats_struct(vsi);
499 memset(ns, 0, sizeof(*ns));
500 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
501 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
502 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 503 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 504 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 505 memset(&vsi->rx_rings[i]->stats, 0 ,
506 sizeof(vsi->rx_rings[i]->stats));
507 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
508 sizeof(vsi->rx_rings[i]->rx_stats));
509 memset(&vsi->tx_rings[i]->stats, 0 ,
510 sizeof(vsi->tx_rings[i]->stats));
511 memset(&vsi->tx_rings[i]->tx_stats, 0,
512 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 513 }
8e9dca53 514 }
41c445ff
JB		 515 vsi->stat_offsets_loaded = false;
516}
517
518/**
b40c82e6 519 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 520 * @pf: the PF to be reset
521 **/
522void i40e_pf_reset_stats(struct i40e_pf *pf)
523{
e91fdf76
SN		 524 int i;
525
41c445ff
JB		 526 memset(&pf->stats, 0, sizeof(pf->stats));
527 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
528 pf->stat_offsets_loaded = false;
e91fdf76
SN		 529
530 for (i = 0; i < I40E_MAX_VEB; i++) {
531 if (pf->veb[i]) {
532 memset(&pf->veb[i]->stats, 0,
533 sizeof(pf->veb[i]->stats));
534 memset(&pf->veb[i]->stats_offsets, 0,
535 sizeof(pf->veb[i]->stats_offsets));
536 pf->veb[i]->stat_offsets_loaded = false;
537 }
538 }
41c445ff
JB		 539}
540
541/**
542 * i40e_stat_update48 - read and update a 48 bit stat from the chip
543 * @hw: ptr to the hardware info
544 * @hireg: the high 32 bit reg to read
545 * @loreg: the low 32 bit reg to read
546 * @offset_loaded: has the initial offset been loaded yet
547 * @offset: ptr to current offset value
548 * @stat: ptr to the stat
549 *
550 * Since the device stats are not reset at PFReset, they likely will not
551 * be zeroed when the driver starts. We'll save the first values read
552 * and use them as offsets to be subtracted from the raw values in order
553 * to report stats that count from zero. In the process, we also manage
554 * the potential roll-over.
555 **/
556static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
557 bool offset_loaded, u64 *offset, u64 *stat)
558{
559 u64 new_data;
560
ab60085e 561 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 562 new_data = rd32(hw, loreg);
563 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
564 } else {
565 new_data = rd64(hw, loreg);
566 }
567 if (!offset_loaded)
568 *offset = new_data;
569 if (likely(new_data >= *offset))
570 *stat = new_data - *offset;
571 else
41a1d04b 572 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 573 *stat &= 0xFFFFFFFFFFFFULL;
574}
575
576/**
577 * i40e_stat_update32 - read and update a 32 bit stat from the chip
578 * @hw: ptr to the hardware info
579 * @reg: the hw reg to read
580 * @offset_loaded: has the initial offset been loaded yet
581 * @offset: ptr to current offset value
582 * @stat: ptr to the stat
583 **/
584static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
585 bool offset_loaded, u64 *offset, u64 *stat)
586{
587 u32 new_data;
588
589 new_data = rd32(hw, reg);
590 if (!offset_loaded)
591 *offset = new_data;
592 if (likely(new_data >= *offset))
593 *stat = (u32)(new_data - *offset);
594 else
41a1d04b 595 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 596}
597
598/**
599 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
600 * @vsi: the VSI to be updated
601 **/
602void i40e_update_eth_stats(struct i40e_vsi *vsi)
603{
604 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
605 struct i40e_pf *pf = vsi->back;
606 struct i40e_hw *hw = &pf->hw;
607 struct i40e_eth_stats *oes;
608 struct i40e_eth_stats *es; /* device's eth stats */
609
610 es = &vsi->eth_stats;
611 oes = &vsi->eth_stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
615 vsi->stat_offsets_loaded,
616 &oes->tx_errors, &es->tx_errors);
617 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
618 vsi->stat_offsets_loaded,
619 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 620 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
623 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 626
627 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
628 I40E_GLV_GORCL(stat_idx),
629 vsi->stat_offsets_loaded,
630 &oes->rx_bytes, &es->rx_bytes);
631 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
632 I40E_GLV_UPRCL(stat_idx),
633 vsi->stat_offsets_loaded,
634 &oes->rx_unicast, &es->rx_unicast);
635 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
636 I40E_GLV_MPRCL(stat_idx),
637 vsi->stat_offsets_loaded,
638 &oes->rx_multicast, &es->rx_multicast);
639 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
640 I40E_GLV_BPRCL(stat_idx),
641 vsi->stat_offsets_loaded,
642 &oes->rx_broadcast, &es->rx_broadcast);
643
644 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
645 I40E_GLV_GOTCL(stat_idx),
646 vsi->stat_offsets_loaded,
647 &oes->tx_bytes, &es->tx_bytes);
648 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
649 I40E_GLV_UPTCL(stat_idx),
650 vsi->stat_offsets_loaded,
651 &oes->tx_unicast, &es->tx_unicast);
652 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
653 I40E_GLV_MPTCL(stat_idx),
654 vsi->stat_offsets_loaded,
655 &oes->tx_multicast, &es->tx_multicast);
656 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
657 I40E_GLV_BPTCL(stat_idx),
658 vsi->stat_offsets_loaded,
659 &oes->tx_broadcast, &es->tx_broadcast);
660 vsi->stat_offsets_loaded = true;
661}
662
663/**
664 * i40e_update_veb_stats - Update Switch component statistics
665 * @veb: the VEB being updated
666 **/
667static void i40e_update_veb_stats(struct i40e_veb *veb)
668{
669 struct i40e_pf *pf = veb->pf;
670 struct i40e_hw *hw = &pf->hw;
671 struct i40e_eth_stats *oes;
672 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 673 struct i40e_veb_tc_stats *veb_oes;
674 struct i40e_veb_tc_stats *veb_es;
675 int i, idx = 0;
41c445ff
JB		 676
677 idx = veb->stats_idx;
678 es = &veb->stats;
679 oes = &veb->stats_offsets;
fe860afb
NP		 680 veb_es = &veb->tc_stats;
681 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 682
683 /* Gather up the stats that the hw collects */
684 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
685 veb->stat_offsets_loaded,
686 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 687 if (hw->revision_id > 0)
688 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
689 veb->stat_offsets_loaded,
690 &oes->rx_unknown_protocol,
691 &es->rx_unknown_protocol);
41c445ff
JB		 692 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
693 veb->stat_offsets_loaded,
694 &oes->rx_bytes, &es->rx_bytes);
695 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
696 veb->stat_offsets_loaded,
697 &oes->rx_unicast, &es->rx_unicast);
698 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_multicast, &es->rx_multicast);
701 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_broadcast, &es->rx_broadcast);
704
705 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
706 veb->stat_offsets_loaded,
707 &oes->tx_bytes, &es->tx_bytes);
708 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->tx_unicast, &es->tx_unicast);
711 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_multicast, &es->tx_multicast);
714 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 717 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
718 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
719 I40E_GLVEBTC_RPCL(i, idx),
720 veb->stat_offsets_loaded,
721 &veb_oes->tc_rx_packets[i],
722 &veb_es->tc_rx_packets[i]);
723 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
724 I40E_GLVEBTC_RBCL(i, idx),
725 veb->stat_offsets_loaded,
726 &veb_oes->tc_rx_bytes[i],
727 &veb_es->tc_rx_bytes[i]);
728 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
729 I40E_GLVEBTC_TPCL(i, idx),
730 veb->stat_offsets_loaded,
731 &veb_oes->tc_tx_packets[i],
732 &veb_es->tc_tx_packets[i]);
733 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
734 I40E_GLVEBTC_TBCL(i, idx),
735 veb->stat_offsets_loaded,
736 &veb_oes->tc_tx_bytes[i],
737 &veb_es->tc_tx_bytes[i]);
738 }
41c445ff
JB		 739 veb->stat_offsets_loaded = true;
740}
741
38e00438
VD		 742#ifdef I40E_FCOE
743/**
744 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
745 * @vsi: the VSI that is capable of doing FCoE
746 **/
747static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
748{
749 struct i40e_pf *pf = vsi->back;
750 struct i40e_hw *hw = &pf->hw;
751 struct i40e_fcoe_stats *ofs;
752 struct i40e_fcoe_stats *fs; /* device's eth stats */
753 int idx;
754
755 if (vsi->type != I40E_VSI_FCOE)
756 return;
757
758 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
759 fs = &vsi->fcoe_stats;
760 ofs = &vsi->fcoe_stats_offsets;
761
762 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
763 vsi->fcoe_stat_offsets_loaded,
764 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
765 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
768 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
771 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
774 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
777 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
780 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->fcoe_last_error, &fs->fcoe_last_error);
783 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
786
787 vsi->fcoe_stat_offsets_loaded = true;
788}
789
790#endif
41c445ff
JB		 791/**
792 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
793 * @pf: the corresponding PF
794 *
795 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
796 **/
797static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
798{
799 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
800 struct i40e_hw_port_stats *nsd = &pf->stats;
801 struct i40e_hw *hw = &pf->hw;
802 u64 xoff = 0;
41c445ff
JB		 803
804 if ((hw->fc.current_mode != I40E_FC_FULL) &&
805 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
806 return;
807
808 xoff = nsd->link_xoff_rx;
809 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
810 pf->stat_offsets_loaded,
811 &osd->link_xoff_rx, &nsd->link_xoff_rx);
812
813 /* No new LFC xoff rx */
814 if (!(nsd->link_xoff_rx - xoff))
815 return;
816
41c445ff
JB		 817}
818
819/**
820 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
821 * @pf: the corresponding PF
822 *
823 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
824 **/
825static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
826{
827 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
828 struct i40e_hw_port_stats *nsd = &pf->stats;
829 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
830 struct i40e_dcbx_config *dcb_cfg;
831 struct i40e_hw *hw = &pf->hw;
b03a8c1f 832 u16 i;
41c445ff
JB		 833 u8 tc;
834
835 dcb_cfg = &hw->local_dcbx_config;
836
e120814d
NP		 837 /* Collect Link XOFF stats when PFC is disabled */
838 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 839 i40e_update_link_xoff_rx(pf);
840 return;
841 }
842
843 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
844 u64 prio_xoff = nsd->priority_xoff_rx[i];
845 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
846 pf->stat_offsets_loaded,
847 &osd->priority_xoff_rx[i],
848 &nsd->priority_xoff_rx[i]);
849
850 /* No new PFC xoff rx */
851 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
852 continue;
853 /* Get the TC for given priority */
854 tc = dcb_cfg->etscfg.prioritytable[i];
855 xoff[tc] = true;
856 }
41c445ff
JB		 857}
858
859/**
7812fddc 860 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 861 * @vsi: the VSI to be updated
862 *
863 * There are a few instances where we store the same stat in a
864 * couple of different structs. This is partly because we have
865 * the netdev stats that need to be filled out, which is slightly
866 * different from the "eth_stats" defined by the chip and used in
7812fddc 867 * VF communications. We sort it out here.
41c445ff 868 **/
7812fddc 869static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 870{
871 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 872 struct rtnl_link_stats64 *ons;
873 struct rtnl_link_stats64 *ns; /* netdev stats */
874 struct i40e_eth_stats *oes;
875 struct i40e_eth_stats *es; /* device's eth stats */
876 u32 tx_restart, tx_busy;
bf00b376 877 struct i40e_ring *p;
41c445ff 878 u32 rx_page, rx_buf;
bf00b376
AA		 879 u64 bytes, packets;
880 unsigned int start;
41c445ff
JB		 881 u64 rx_p, rx_b;
882 u64 tx_p, tx_b;
41c445ff
JB		 883 u16 q;
884
885 if (test_bit(__I40E_DOWN, &vsi->state) ||
886 test_bit(__I40E_CONFIG_BUSY, &pf->state))
887 return;
888
889 ns = i40e_get_vsi_stats_struct(vsi);
890 ons = &vsi->net_stats_offsets;
891 es = &vsi->eth_stats;
892 oes = &vsi->eth_stats_offsets;
893
894 /* Gather up the netdev and vsi stats that the driver collects
895 * on the fly during packet processing
896 */
897 rx_b = rx_p = 0;
898 tx_b = tx_p = 0;
899 tx_restart = tx_busy = 0;
900 rx_page = 0;
901 rx_buf = 0;
980e9b11 902 rcu_read_lock();
41c445ff 903 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 904 /* locate Tx ring */
905 p = ACCESS_ONCE(vsi->tx_rings[q]);
906
907 do {
57a7744e 908 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 909 packets = p->stats.packets;
910 bytes = p->stats.bytes;
57a7744e 911 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 912 tx_b += bytes;
913 tx_p += packets;
914 tx_restart += p->tx_stats.restart_queue;
915 tx_busy += p->tx_stats.tx_busy;
41c445ff 916
980e9b11
AD		 917 /* Rx queue is part of the same block as Tx queue */
918 p = &p[1];
919 do {
57a7744e 920 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 921 packets = p->stats.packets;
922 bytes = p->stats.bytes;
57a7744e 923 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 924 rx_b += bytes;
925 rx_p += packets;
420136cc
MW		 926 rx_buf += p->rx_stats.alloc_buff_failed;
927 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 928 }
980e9b11 929 rcu_read_unlock();
41c445ff
JB		 930 vsi->tx_restart = tx_restart;
931 vsi->tx_busy = tx_busy;
932 vsi->rx_page_failed = rx_page;
933 vsi->rx_buf_failed = rx_buf;
934
935 ns->rx_packets = rx_p;
936 ns->rx_bytes = rx_b;
937 ns->tx_packets = tx_p;
938 ns->tx_bytes = tx_b;
939
41c445ff 940 /* update netdev stats from eth stats */
7812fddc 941 i40e_update_eth_stats(vsi);
41c445ff
JB		 942 ons->tx_errors = oes->tx_errors;
943 ns->tx_errors = es->tx_errors;
944 ons->multicast = oes->rx_multicast;
945 ns->multicast = es->rx_multicast;
41a9e55c
SN		 946 ons->rx_dropped = oes->rx_discards;
947 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 948 ons->tx_dropped = oes->tx_discards;
949 ns->tx_dropped = es->tx_discards;
950
7812fddc 951 /* pull in a couple PF stats if this is the main vsi */
41c445ff 952 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 953 ns->rx_crc_errors = pf->stats.crc_errors;
954 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
955 ns->rx_length_errors = pf->stats.rx_length_errors;
956 }
957}
41c445ff 958
7812fddc 959/**
b40c82e6 960 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 961 * @pf: the PF to be updated
962 **/
963static void i40e_update_pf_stats(struct i40e_pf *pf)
964{
965 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
966 struct i40e_hw_port_stats *nsd = &pf->stats;
967 struct i40e_hw *hw = &pf->hw;
968 u32 val;
969 int i;
41c445ff 970
7812fddc
SN		 971 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
972 I40E_GLPRT_GORCL(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
975 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
976 I40E_GLPRT_GOTCL(hw->port),
977 pf->stat_offsets_loaded,
978 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
979 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->eth.rx_discards,
982 &nsd->eth.rx_discards);
532d283d
SN		 983 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
984 I40E_GLPRT_UPRCL(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->eth.rx_unicast,
987 &nsd->eth.rx_unicast);
7812fddc
SN		 988 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
989 I40E_GLPRT_MPRCL(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->eth.rx_multicast,
992 &nsd->eth.rx_multicast);
532d283d
SN		 993 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
994 I40E_GLPRT_BPRCL(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->eth.rx_broadcast,
997 &nsd->eth.rx_broadcast);
998 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
999 I40E_GLPRT_UPTCL(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->eth.tx_unicast,
1002 &nsd->eth.tx_unicast);
1003 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1004 I40E_GLPRT_MPTCL(hw->port),
1005 pf->stat_offsets_loaded,
1006 &osd->eth.tx_multicast,
1007 &nsd->eth.tx_multicast);
1008 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1009 I40E_GLPRT_BPTCL(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->eth.tx_broadcast,
1012 &nsd->eth.tx_broadcast);
41c445ff 1013
7812fddc
SN		 1014 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->tx_dropped_link_down,
1017 &nsd->tx_dropped_link_down);
41c445ff 1018
7812fddc
SN		 1019 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1022
7812fddc
SN		 1023 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1024 pf->stat_offsets_loaded,
1025 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1026
7812fddc
SN		 1027 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1028 pf->stat_offsets_loaded,
1029 &osd->mac_local_faults,
1030 &nsd->mac_local_faults);
1031 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1032 pf->stat_offsets_loaded,
1033 &osd->mac_remote_faults,
1034 &nsd->mac_remote_faults);
41c445ff 1035
7812fddc
SN		 1036 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_length_errors,
1039 &nsd->rx_length_errors);
41c445ff 1040
7812fddc
SN		 1041 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->link_xon_rx, &nsd->link_xon_rx);
1044 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1045 pf->stat_offsets_loaded,
1046 &osd->link_xon_tx, &nsd->link_xon_tx);
1047 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1048 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1049 pf->stat_offsets_loaded,
1050 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1051
7812fddc
SN		 1052 for (i = 0; i < 8; i++) {
1053 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1054 pf->stat_offsets_loaded,
7812fddc
SN		 1055 &osd->priority_xon_rx[i],
1056 &nsd->priority_xon_rx[i]);
1057 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1058 pf->stat_offsets_loaded,
7812fddc
SN		 1059 &osd->priority_xon_tx[i],
1060 &nsd->priority_xon_tx[i]);
1061 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1062 pf->stat_offsets_loaded,
7812fddc
SN		 1063 &osd->priority_xoff_tx[i],
1064 &nsd->priority_xoff_tx[i]);
1065 i40e_stat_update32(hw,
1066 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1067 pf->stat_offsets_loaded,
7812fddc
SN		 1068 &osd->priority_xon_2_xoff[i],
1069 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1070 }
1071
7812fddc
SN		 1072 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1073 I40E_GLPRT_PRC64L(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->rx_size_64, &nsd->rx_size_64);
1076 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1077 I40E_GLPRT_PRC127L(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_size_127, &nsd->rx_size_127);
1080 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1081 I40E_GLPRT_PRC255L(hw->port),
1082 pf->stat_offsets_loaded,
1083 &osd->rx_size_255, &nsd->rx_size_255);
1084 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1085 I40E_GLPRT_PRC511L(hw->port),
1086 pf->stat_offsets_loaded,
1087 &osd->rx_size_511, &nsd->rx_size_511);
1088 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1089 I40E_GLPRT_PRC1023L(hw->port),
1090 pf->stat_offsets_loaded,
1091 &osd->rx_size_1023, &nsd->rx_size_1023);
1092 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1093 I40E_GLPRT_PRC1522L(hw->port),
1094 pf->stat_offsets_loaded,
1095 &osd->rx_size_1522, &nsd->rx_size_1522);
1096 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1097 I40E_GLPRT_PRC9522L(hw->port),
1098 pf->stat_offsets_loaded,
1099 &osd->rx_size_big, &nsd->rx_size_big);
1100
1101 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1102 I40E_GLPRT_PTC64L(hw->port),
1103 pf->stat_offsets_loaded,
1104 &osd->tx_size_64, &nsd->tx_size_64);
1105 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1106 I40E_GLPRT_PTC127L(hw->port),
1107 pf->stat_offsets_loaded,
1108 &osd->tx_size_127, &nsd->tx_size_127);
1109 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1110 I40E_GLPRT_PTC255L(hw->port),
1111 pf->stat_offsets_loaded,
1112 &osd->tx_size_255, &nsd->tx_size_255);
1113 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1114 I40E_GLPRT_PTC511L(hw->port),
1115 pf->stat_offsets_loaded,
1116 &osd->tx_size_511, &nsd->tx_size_511);
1117 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1118 I40E_GLPRT_PTC1023L(hw->port),
1119 pf->stat_offsets_loaded,
1120 &osd->tx_size_1023, &nsd->tx_size_1023);
1121 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1122 I40E_GLPRT_PTC1522L(hw->port),
1123 pf->stat_offsets_loaded,
1124 &osd->tx_size_1522, &nsd->tx_size_1522);
1125 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1126 I40E_GLPRT_PTC9522L(hw->port),
1127 pf->stat_offsets_loaded,
1128 &osd->tx_size_big, &nsd->tx_size_big);
1129
1130 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1131 pf->stat_offsets_loaded,
1132 &osd->rx_undersize, &nsd->rx_undersize);
1133 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1134 pf->stat_offsets_loaded,
1135 &osd->rx_fragments, &nsd->rx_fragments);
1136 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1137 pf->stat_offsets_loaded,
1138 &osd->rx_oversize, &nsd->rx_oversize);
1139 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1140 pf->stat_offsets_loaded,
1141 &osd->rx_jabber, &nsd->rx_jabber);
1142
433c47de 1143 /* FDIR stats */
0bf4b1b0
ASJ		 1144 i40e_stat_update32(hw,
1145 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1146 pf->stat_offsets_loaded,
1147 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1148 i40e_stat_update32(hw,
1149 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1150 pf->stat_offsets_loaded,
1151 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1152 i40e_stat_update32(hw,
1153 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1154 pf->stat_offsets_loaded,
1155 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1156
7812fddc
SN		 1157 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1158 nsd->tx_lpi_status =
1159 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1160 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1161 nsd->rx_lpi_status =
1162 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1163 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1164 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1165 pf->stat_offsets_loaded,
1166 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1167 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1168 pf->stat_offsets_loaded,
1169 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1170
d0389e51
ASJ		 1171 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1172 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1173 nsd->fd_sb_status = true;
1174 else
1175 nsd->fd_sb_status = false;
1176
1177 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1178 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1179 nsd->fd_atr_status = true;
1180 else
1181 nsd->fd_atr_status = false;
1182
41c445ff
JB		 1183 pf->stat_offsets_loaded = true;
1184}
1185
7812fddc
SN		 1186/**
1187 * i40e_update_stats - Update the various statistics counters.
1188 * @vsi: the VSI to be updated
1189 *
1190 * Update the various stats for this VSI and its related entities.
1191 **/
1192void i40e_update_stats(struct i40e_vsi *vsi)
1193{
1194 struct i40e_pf *pf = vsi->back;
1195
1196 if (vsi == pf->vsi[pf->lan_vsi])
1197 i40e_update_pf_stats(pf);
1198
1199 i40e_update_vsi_stats(vsi);
38e00438
VD		 1200#ifdef I40E_FCOE
1201 i40e_update_fcoe_stats(vsi);
1202#endif
7812fddc
SN		 1203}
1204
41c445ff
JB		 1205/**
1206 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1207 * @vsi: the VSI to be searched
1208 * @macaddr: the MAC address
1209 * @vlan: the vlan
b40c82e6 1210 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1211 * @is_netdev: make sure its a netdev filter, else doesn't matter
1212 *
1213 * Returns ptr to the filter object or NULL
1214 **/
1215static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1216 u8 *macaddr, s16 vlan,
1217 bool is_vf, bool is_netdev)
1218{
1219 struct i40e_mac_filter *f;
1220
1221 if (!vsi || !macaddr)
1222 return NULL;
1223
1224 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1225 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1226 (vlan == f->vlan) &&
1227 (!is_vf || f->is_vf) &&
1228 (!is_netdev || f->is_netdev))
1229 return f;
1230 }
1231 return NULL;
1232}
1233
1234/**
1235 * i40e_find_mac - Find a mac addr in the macvlan filters list
1236 * @vsi: the VSI to be searched
1237 * @macaddr: the MAC address we are searching for
b40c82e6 1238 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1239 * @is_netdev: make sure its a netdev filter, else doesn't matter
1240 *
1241 * Returns the first filter with the provided MAC address or NULL if
1242 * MAC address was not found
1243 **/
1244struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1245 bool is_vf, bool is_netdev)
1246{
1247 struct i40e_mac_filter *f;
1248
1249 if (!vsi || !macaddr)
1250 return NULL;
1251
1252 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1253 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1254 (!is_vf || f->is_vf) &&
1255 (!is_netdev || f->is_netdev))
1256 return f;
1257 }
1258 return NULL;
1259}
1260
1261/**
1262 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1263 * @vsi: the VSI to be searched
1264 *
1265 * Returns true if VSI is in vlan mode or false otherwise
1266 **/
1267bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1268{
1269 struct i40e_mac_filter *f;
1270
1271 /* Only -1 for all the filters denotes not in vlan mode
1272 * so we have to go through all the list in order to make sure
1273 */
1274 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1275 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1276 return true;
1277 }
1278
1279 return false;
1280}
1281
1282/**
1283 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1284 * @vsi: the VSI to be searched
1285 * @macaddr: the mac address to be filtered
b40c82e6 1286 * @is_vf: true if it is a VF
41c445ff
JB		 1287 * @is_netdev: true if it is a netdev
1288 *
1289 * Goes through all the macvlan filters and adds a
1290 * macvlan filter for each unique vlan that already exists
1291 *
1292 * Returns first filter found on success, else NULL
1293 **/
1294struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1295 bool is_vf, bool is_netdev)
1296{
1297 struct i40e_mac_filter *f;
1298
1299 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1300 if (vsi->info.pvid)
1301 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1302 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1303 is_vf, is_netdev)) {
1304 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1305 is_vf, is_netdev))
41c445ff
JB		 1306 return NULL;
1307 }
1308 }
1309
1310 return list_first_entry_or_null(&vsi->mac_filter_list,
1311 struct i40e_mac_filter, list);
1312}
1313
8c27d42e
GR		 1314/**
1315 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1316 * @vsi: the PF Main VSI - inappropriate for any other VSI
1317 * @macaddr: the MAC address
30650cc5
SN		 1318 *
1319 * Some older firmware configurations set up a default promiscuous VLAN
1320 * filter that needs to be removed.
8c27d42e 1321 **/
30650cc5 1322static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1323{
1324 struct i40e_aqc_remove_macvlan_element_data element;
1325 struct i40e_pf *pf = vsi->back;
f1c7e72e 1326 i40e_status ret;
8c27d42e
GR		 1327
1328 /* Only appropriate for the PF main VSI */
1329 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1330 return -EINVAL;
8c27d42e 1331
30650cc5 1332 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1333 ether_addr_copy(element.mac_addr, macaddr);
1334 element.vlan_tag = 0;
1335 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1336 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1337 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1338 if (ret)
30650cc5
SN		 1339 return -ENOENT;
1340
1341 return 0;
8c27d42e
GR		 1342}
1343
41c445ff
JB		 1344/**
1345 * i40e_add_filter - Add a mac/vlan filter to the VSI
1346 * @vsi: the VSI to be searched
1347 * @macaddr: the MAC address
1348 * @vlan: the vlan
b40c82e6 1349 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1350 * @is_netdev: make sure its a netdev filter, else doesn't matter
1351 *
1352 * Returns ptr to the filter object or NULL when no memory available.
1353 **/
1354struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1355 u8 *macaddr, s16 vlan,
1356 bool is_vf, bool is_netdev)
1357{
1358 struct i40e_mac_filter *f;
1359
1360 if (!vsi || !macaddr)
1361 return NULL;
1362
1363 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1364 if (!f) {
1365 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1366 if (!f)
1367 goto add_filter_out;
1368
9a173901 1369 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1370 f->vlan = vlan;
1371 f->changed = true;
1372
1373 INIT_LIST_HEAD(&f->list);
1374 list_add(&f->list, &vsi->mac_filter_list);
1375 }
1376
1377 /* increment counter and add a new flag if needed */
1378 if (is_vf) {
1379 if (!f->is_vf) {
1380 f->is_vf = true;
1381 f->counter++;
1382 }
1383 } else if (is_netdev) {
1384 if (!f->is_netdev) {
1385 f->is_netdev = true;
1386 f->counter++;
1387 }
1388 } else {
1389 f->counter++;
1390 }
1391
1392 /* changed tells sync_filters_subtask to
1393 * push the filter down to the firmware
1394 */
1395 if (f->changed) {
1396 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1397 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1398 }
1399
1400add_filter_out:
1401 return f;
1402}
1403
1404/**
1405 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1406 * @vsi: the VSI to be searched
1407 * @macaddr: the MAC address
1408 * @vlan: the vlan
b40c82e6 1409 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1410 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1411 **/
1412void i40e_del_filter(struct i40e_vsi *vsi,
1413 u8 *macaddr, s16 vlan,
1414 bool is_vf, bool is_netdev)
1415{
1416 struct i40e_mac_filter *f;
1417
1418 if (!vsi || !macaddr)
1419 return;
1420
1421 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1422 if (!f || f->counter == 0)
1423 return;
1424
1425 if (is_vf) {
1426 if (f->is_vf) {
1427 f->is_vf = false;
1428 f->counter--;
1429 }
1430 } else if (is_netdev) {
1431 if (f->is_netdev) {
1432 f->is_netdev = false;
1433 f->counter--;
1434 }
1435 } else {
b40c82e6 1436 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff
JB		 1437 int min_f = 0;
1438 min_f += (f->is_vf ? 1 : 0);
1439 min_f += (f->is_netdev ? 1 : 0);
1440
1441 if (f->counter > min_f)
1442 f->counter--;
1443 }
1444
1445 /* counter == 0 tells sync_filters_subtask to
1446 * remove the filter from the firmware's list
1447 */
1448 if (f->counter == 0) {
1449 f->changed = true;
1450 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1451 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1452 }
1453}
1454
1455/**
1456 * i40e_set_mac - NDO callback to set mac address
1457 * @netdev: network interface device structure
1458 * @p: pointer to an address structure
1459 *
1460 * Returns 0 on success, negative on failure
1461 **/
38e00438
VD		 1462#ifdef I40E_FCOE
1463int i40e_set_mac(struct net_device *netdev, void *p)
1464#else
41c445ff 1465static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1466#endif
41c445ff
JB		 1467{
1468 struct i40e_netdev_priv *np = netdev_priv(netdev);
1469 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1470 struct i40e_pf *pf = vsi->back;
1471 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1472 struct sockaddr *addr = p;
1473 struct i40e_mac_filter *f;
1474
1475 if (!is_valid_ether_addr(addr->sa_data))
1476 return -EADDRNOTAVAIL;
1477
30650cc5
SN		 1478 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1479 netdev_info(netdev, "already using mac address %pM\n",
1480 addr->sa_data);
1481 return 0;
1482 }
41c445ff 1483
80f6428f
ASJ		 1484 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1485 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1486 return -EADDRNOTAVAIL;
1487
30650cc5
SN		 1488 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1489 netdev_info(netdev, "returning to hw mac address %pM\n",
1490 hw->mac.addr);
1491 else
1492 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1493
41c445ff
JB		 1494 if (vsi->type == I40E_VSI_MAIN) {
1495 i40e_status ret;
1496 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1497 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1498 addr->sa_data, NULL);
1499 if (ret) {
1500 netdev_info(netdev,
1501 "Addr change for Main VSI failed: %d\n",
1502 ret);
1503 return -EADDRNOTAVAIL;
1504 }
41c445ff
JB		 1505 }
1506
30650cc5
SN		 1507 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1508 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1509
30650cc5
SN		 1510 memset(&element, 0, sizeof(element));
1511 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1512 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1513 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1514 } else {
6c8ad1ba
SN		 1515 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1516 false, false);
6c8ad1ba 1517 }
41c445ff 1518
30650cc5
SN		 1519 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1520 struct i40e_aqc_add_macvlan_element_data element;
1521
1522 memset(&element, 0, sizeof(element));
1523 ether_addr_copy(element.mac_addr, hw->mac.addr);
1524 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1525 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1526 } else {
1527 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1528 false, false);
1529 if (f)
1530 f->is_laa = true;
1531 }
1532
30e2561b 1533 i40e_sync_vsi_filters(vsi, false);
30650cc5 1534 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1535
1536 return 0;
1537}
1538
1539/**
1540 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1541 * @vsi: the VSI being setup
1542 * @ctxt: VSI context structure
1543 * @enabled_tc: Enabled TCs bitmap
1544 * @is_add: True if called before Add VSI
1545 *
1546 * Setup VSI queue mapping for enabled traffic classes.
1547 **/
38e00438
VD		 1548#ifdef I40E_FCOE
1549void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1550 struct i40e_vsi_context *ctxt,
1551 u8 enabled_tc,
1552 bool is_add)
1553#else
41c445ff
JB		 1554static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1555 struct i40e_vsi_context *ctxt,
1556 u8 enabled_tc,
1557 bool is_add)
38e00438 1558#endif
41c445ff
JB		 1559{
1560 struct i40e_pf *pf = vsi->back;
1561 u16 sections = 0;
1562 u8 netdev_tc = 0;
1563 u16 numtc = 0;
1564 u16 qcount;
1565 u8 offset;
1566 u16 qmap;
1567 int i;
4e3b35b0 1568 u16 num_tc_qps = 0;
41c445ff
JB		 1569
1570 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1571 offset = 0;
1572
1573 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1574 /* Find numtc from enabled TC bitmap */
1575 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1576 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1577 numtc++;
1578 }
1579 if (!numtc) {
1580 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1581 numtc = 1;
1582 }
1583 } else {
1584 /* At least TC0 is enabled in case of non-DCB case */
1585 numtc = 1;
1586 }
1587
1588 vsi->tc_config.numtc = numtc;
1589 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1590 /* Number of queues per enabled TC */
7f9ff476
AS		 1591 /* In MFP case we can have a much lower count of MSIx
1592 * vectors available and so we need to lower the used
1593 * q count.
1594 */
26cdc443
ASJ		 1595 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1596 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1597 else
1598 qcount = vsi->alloc_queue_pairs;
7f9ff476 1599 num_tc_qps = qcount / numtc;
e25d00b8 1600 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1601
1602 /* Setup queue offset/count for all TCs for given VSI */
1603 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1604 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1605 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1606 /* TC is enabled */
41c445ff
JB		 1607 int pow, num_qps;
1608
41c445ff
JB		 1609 switch (vsi->type) {
1610 case I40E_VSI_MAIN:
4e3b35b0 1611 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1612 break;
38e00438
VD		 1613#ifdef I40E_FCOE
1614 case I40E_VSI_FCOE:
1615 qcount = num_tc_qps;
1616 break;
1617#endif
41c445ff
JB		 1618 case I40E_VSI_FDIR:
1619 case I40E_VSI_SRIOV:
1620 case I40E_VSI_VMDQ2:
1621 default:
4e3b35b0 1622 qcount = num_tc_qps;
41c445ff
JB		 1623 WARN_ON(i != 0);
1624 break;
1625 }
4e3b35b0
NP		 1626 vsi->tc_config.tc_info[i].qoffset = offset;
1627 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1628
1e200e4a 1629 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1630 num_qps = qcount;
41c445ff 1631 pow = 0;
41a1d04b 1632 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1633 pow++;
1634 num_qps >>= 1;
1635 }
1636
1637 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1638 qmap =
1639 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1640 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1641
4e3b35b0 1642 offset += qcount;
41c445ff
JB		 1643 } else {
1644 /* TC is not enabled so set the offset to
1645 * default queue and allocate one queue
1646 * for the given TC.
1647 */
1648 vsi->tc_config.tc_info[i].qoffset = 0;
1649 vsi->tc_config.tc_info[i].qcount = 1;
1650 vsi->tc_config.tc_info[i].netdev_tc = 0;
1651
1652 qmap = 0;
1653 }
1654 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1655 }
1656
1657 /* Set actual Tx/Rx queue pairs */
1658 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1659 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1660 if (vsi->req_queue_pairs > 0)
1661 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1662 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1663 vsi->num_queue_pairs = pf->num_lan_msix;
1664 }
41c445ff
JB		 1665
1666 /* Scheduler section valid can only be set for ADD VSI */
1667 if (is_add) {
1668 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1669
1670 ctxt->info.up_enable_bits = enabled_tc;
1671 }
1672 if (vsi->type == I40E_VSI_SRIOV) {
1673 ctxt->info.mapping_flags |=
1674 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1675 for (i = 0; i < vsi->num_queue_pairs; i++)
1676 ctxt->info.queue_mapping[i] =
1677 cpu_to_le16(vsi->base_queue + i);
1678 } else {
1679 ctxt->info.mapping_flags |=
1680 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1681 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1682 }
1683 ctxt->info.valid_sections |= cpu_to_le16(sections);
1684}
1685
1686/**
1687 * i40e_set_rx_mode - NDO callback to set the netdev filters
1688 * @netdev: network interface device structure
1689 **/
38e00438
VD		 1690#ifdef I40E_FCOE
1691void i40e_set_rx_mode(struct net_device *netdev)
1692#else
41c445ff 1693static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1694#endif
41c445ff
JB		 1695{
1696 struct i40e_netdev_priv *np = netdev_priv(netdev);
1697 struct i40e_mac_filter *f, *ftmp;
1698 struct i40e_vsi *vsi = np->vsi;
1699 struct netdev_hw_addr *uca;
1700 struct netdev_hw_addr *mca;
1701 struct netdev_hw_addr *ha;
1702
1703 /* add addr if not already in the filter list */
1704 netdev_for_each_uc_addr(uca, netdev) {
1705 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1706 if (i40e_is_vsi_in_vlan(vsi))
1707 i40e_put_mac_in_vlan(vsi, uca->addr,
1708 false, true);
1709 else
1710 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1711 false, true);
1712 }
1713 }
1714
1715 netdev_for_each_mc_addr(mca, netdev) {
1716 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1717 if (i40e_is_vsi_in_vlan(vsi))
1718 i40e_put_mac_in_vlan(vsi, mca->addr,
1719 false, true);
1720 else
1721 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1722 false, true);
1723 }
1724 }
1725
1726 /* remove filter if not in netdev list */
1727 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1728 bool found = false;
1729
1730 if (!f->is_netdev)
1731 continue;
1732
1733 if (is_multicast_ether_addr(f->macaddr)) {
1734 netdev_for_each_mc_addr(mca, netdev) {
1735 if (ether_addr_equal(mca->addr, f->macaddr)) {
1736 found = true;
1737 break;
1738 }
1739 }
1740 } else {
1741 netdev_for_each_uc_addr(uca, netdev) {
1742 if (ether_addr_equal(uca->addr, f->macaddr)) {
1743 found = true;
1744 break;
1745 }
1746 }
1747
1748 for_each_dev_addr(netdev, ha) {
1749 if (ether_addr_equal(ha->addr, f->macaddr)) {
1750 found = true;
1751 break;
1752 }
1753 }
1754 }
1755 if (!found)
1756 i40e_del_filter(
1757 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1758 }
1759
1760 /* check for other flag changes */
1761 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1762 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1763 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1764 }
1765}
1766
1767/**
1768 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1769 * @vsi: ptr to the VSI
30e2561b 1770 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1771 *
1772 * Push any outstanding VSI filter changes through the AdminQ.
1773 *
1774 * Returns 0 or error value
1775 **/
30e2561b 1776int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff
JB		 1777{
1778 struct i40e_mac_filter *f, *ftmp;
1779 bool promisc_forced_on = false;
1780 bool add_happened = false;
1781 int filter_list_len = 0;
1782 u32 changed_flags = 0;
f1c7e72e 1783 i40e_status ret = 0;
41c445ff
JB		 1784 struct i40e_pf *pf;
1785 int num_add = 0;
1786 int num_del = 0;
f1c7e72e 1787 int aq_err = 0;
41c445ff
JB		 1788 u16 cmd_flags;
1789
1790 /* empty array typed pointers, kcalloc later */
1791 struct i40e_aqc_add_macvlan_element_data *add_list;
1792 struct i40e_aqc_remove_macvlan_element_data *del_list;
1793
1794 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1795 usleep_range(1000, 2000);
1796 pf = vsi->back;
1797
1798 if (vsi->netdev) {
1799 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1800 vsi->current_netdev_flags = vsi->netdev->flags;
1801 }
1802
1803 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1804 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1805
1806 filter_list_len = pf->hw.aq.asq_buf_size /
1807 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1808 del_list = kcalloc(filter_list_len,
1809 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1810 GFP_KERNEL);
1811 if (!del_list)
1812 return -ENOMEM;
1813
1814 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1815 if (!f->changed)
1816 continue;
1817
1818 if (f->counter != 0)
1819 continue;
1820 f->changed = false;
1821 cmd_flags = 0;
1822
1823 /* add to delete list */
9a173901 1824 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1825 del_list[num_del].vlan_tag =
1826 cpu_to_le16((u16)(f->vlan ==
1827 I40E_VLAN_ANY ? 0 : f->vlan));
1828
41c445ff
JB		 1829 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1830 del_list[num_del].flags = cmd_flags;
1831 num_del++;
1832
1833 /* unlink from filter list */
1834 list_del(&f->list);
1835 kfree(f);
1836
1837 /* flush a full buffer */
1838 if (num_del == filter_list_len) {
f1c7e72e
SN		 1839 ret = i40e_aq_remove_macvlan(&pf->hw,
1840 vsi->seid, del_list, num_del,
1841 NULL);
1842 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1843 num_del = 0;
1844 memset(del_list, 0, sizeof(*del_list));
1845
f1c7e72e 1846 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1847 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1848 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1849 i40e_stat_str(&pf->hw, ret),
1850 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1851 }
1852 }
1853 if (num_del) {
f1c7e72e 1854 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1855 del_list, num_del, NULL);
f1c7e72e 1856 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1857 num_del = 0;
1858
f1c7e72e 1859 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1860 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1861 "ignoring delete macvlan error, err %s aq_err %s\n",
1862 i40e_stat_str(&pf->hw, ret),
1863 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1864 }
1865
1866 kfree(del_list);
1867 del_list = NULL;
1868
1869 /* do all the adds now */
1870 filter_list_len = pf->hw.aq.asq_buf_size /
1871 sizeof(struct i40e_aqc_add_macvlan_element_data),
1872 add_list = kcalloc(filter_list_len,
1873 sizeof(struct i40e_aqc_add_macvlan_element_data),
1874 GFP_KERNEL);
1875 if (!add_list)
1876 return -ENOMEM;
1877
1878 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1879 if (!f->changed)
1880 continue;
1881
1882 if (f->counter == 0)
1883 continue;
1884 f->changed = false;
1885 add_happened = true;
1886 cmd_flags = 0;
1887
1888 /* add to add array */
9a173901 1889 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1890 add_list[num_add].vlan_tag =
1891 cpu_to_le16(
1892 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1893 add_list[num_add].queue_number = 0;
1894
1895 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1896 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1897 num_add++;
1898
1899 /* flush a full buffer */
1900 if (num_add == filter_list_len) {
f1c7e72e
SN		 1901 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1902 add_list, num_add,
1903 NULL);
1904 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1905 num_add = 0;
1906
f1c7e72e 1907 if (ret)
41c445ff
JB		 1908 break;
1909 memset(add_list, 0, sizeof(*add_list));
1910 }
1911 }
1912 if (num_add) {
f1c7e72e
SN		 1913 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1914 add_list, num_add, NULL);
1915 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1916 num_add = 0;
1917 }
1918 kfree(add_list);
1919 add_list = NULL;
1920
f1c7e72e 1921 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1922 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1923 "add filter failed, err %s aq_err %s\n",
1924 i40e_stat_str(&pf->hw, ret),
1925 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1926 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1927 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1928 &vsi->state)) {
1929 promisc_forced_on = true;
1930 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1931 &vsi->state);
1932 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1933 }
1934 }
1935 }
1936
1937 /* check for changes in promiscuous modes */
1938 if (changed_flags & IFF_ALLMULTI) {
1939 bool cur_multipromisc;
1940 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1941 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1942 vsi->seid,
1943 cur_multipromisc,
1944 NULL);
1945 if (ret)
41c445ff 1946 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1947 "set multi promisc failed, err %s aq_err %s\n",
1948 i40e_stat_str(&pf->hw, ret),
1949 i40e_aq_str(&pf->hw,
1950 pf->hw.aq.asq_last_status));
41c445ff
JB		 1951 }
1952 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1953 bool cur_promisc;
1954 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1955 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1956 &vsi->state));
92faef85
ASJ		 1957 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
1958 /* set defport ON for Main VSI instead of true promisc
1959 * this way we will get all unicast/multicast and VLAN
1960 * promisc behavior but will not get VF or VMDq traffic
1961 * replicated on the Main VSI.
1962 */
1963 if (pf->cur_promisc != cur_promisc) {
1964 pf->cur_promisc = cur_promisc;
30e2561b
AS		 1965 if (grab_rtnl)
1966 i40e_do_reset_safe(pf,
1967 BIT(__I40E_PF_RESET_REQUESTED));
1968 else
1969 i40e_do_reset(pf,
92faef85
ASJ		 1970 BIT(__I40E_PF_RESET_REQUESTED));
1971 }
1972 } else {
1973 ret = i40e_aq_set_vsi_unicast_promiscuous(
1974 &vsi->back->hw,
f1c7e72e
SN		 1975 vsi->seid,
1976 cur_promisc, NULL);
92faef85
ASJ		 1977 if (ret)
1978 dev_info(&pf->pdev->dev,
1979 "set unicast promisc failed, err %d, aq_err %d\n",
1980 ret, pf->hw.aq.asq_last_status);
1981 ret = i40e_aq_set_vsi_multicast_promiscuous(
1982 &vsi->back->hw,
1983 vsi->seid,
1984 cur_promisc, NULL);
1985 if (ret)
1986 dev_info(&pf->pdev->dev,
1987 "set multicast promisc failed, err %d, aq_err %d\n",
1988 ret, pf->hw.aq.asq_last_status);
1989 }
f1c7e72e
SN		 1990 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1991 vsi->seid,
1992 cur_promisc, NULL);
1993 if (ret)
1a10370a 1994 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1995 "set brdcast promisc failed, err %s, aq_err %s\n",
1996 i40e_stat_str(&pf->hw, ret),
1997 i40e_aq_str(&pf->hw,
1998 pf->hw.aq.asq_last_status));
41c445ff
JB		 1999 }
2000
2001 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2002 return 0;
2003}
2004
2005/**
2006 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2007 * @pf: board private structure
2008 **/
2009static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2010{
2011 int v;
2012
2013 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2014 return;
2015 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2016
505682cd 2017 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2018 if (pf->vsi[v] &&
2019 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2020 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2021 }
2022}
2023
2024/**
2025 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2026 * @netdev: network interface device structure
2027 * @new_mtu: new value for maximum frame size
2028 *
2029 * Returns 0 on success, negative on failure
2030 **/
2031static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2032{
2033 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2034 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2035 struct i40e_vsi *vsi = np->vsi;
2036
2037 /* MTU < 68 is an error and causes problems on some kernels */
2038 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2039 return -EINVAL;
2040
2041 netdev_info(netdev, "changing MTU from %d to %d\n",
2042 netdev->mtu, new_mtu);
2043 netdev->mtu = new_mtu;
2044 if (netif_running(netdev))
2045 i40e_vsi_reinit_locked(vsi);
2046
2047 return 0;
2048}
2049
beb0dff1
JK		 2050/**
2051 * i40e_ioctl - Access the hwtstamp interface
2052 * @netdev: network interface device structure
2053 * @ifr: interface request data
2054 * @cmd: ioctl command
2055 **/
2056int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2057{
2058 struct i40e_netdev_priv *np = netdev_priv(netdev);
2059 struct i40e_pf *pf = np->vsi->back;
2060
2061 switch (cmd) {
2062 case SIOCGHWTSTAMP:
2063 return i40e_ptp_get_ts_config(pf, ifr);
2064 case SIOCSHWTSTAMP:
2065 return i40e_ptp_set_ts_config(pf, ifr);
2066 default:
2067 return -EOPNOTSUPP;
2068 }
2069}
2070
41c445ff
JB		 2071/**
2072 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2073 * @vsi: the vsi being adjusted
2074 **/
2075void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2076{
2077 struct i40e_vsi_context ctxt;
2078 i40e_status ret;
2079
2080 if ((vsi->info.valid_sections &
2081 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2082 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2083 return; /* already enabled */
2084
2085 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2086 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2087 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2088
2089 ctxt.seid = vsi->seid;
1a2f6248 2090 ctxt.info = vsi->info;
41c445ff
JB		 2091 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2092 if (ret) {
2093 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2094 "update vlan stripping failed, err %s aq_err %s\n",
2095 i40e_stat_str(&vsi->back->hw, ret),
2096 i40e_aq_str(&vsi->back->hw,
2097 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2098 }
2099}
2100
2101/**
2102 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2103 * @vsi: the vsi being adjusted
2104 **/
2105void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2106{
2107 struct i40e_vsi_context ctxt;
2108 i40e_status ret;
2109
2110 if ((vsi->info.valid_sections &
2111 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2112 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2113 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2114 return; /* already disabled */
2115
2116 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2117 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2118 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2119
2120 ctxt.seid = vsi->seid;
1a2f6248 2121 ctxt.info = vsi->info;
41c445ff
JB		 2122 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2123 if (ret) {
2124 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2125 "update vlan stripping failed, err %s aq_err %s\n",
2126 i40e_stat_str(&vsi->back->hw, ret),
2127 i40e_aq_str(&vsi->back->hw,
2128 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2129 }
2130}
2131
2132/**
2133 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2134 * @netdev: network interface to be adjusted
2135 * @features: netdev features to test if VLAN offload is enabled or not
2136 **/
2137static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2138{
2139 struct i40e_netdev_priv *np = netdev_priv(netdev);
2140 struct i40e_vsi *vsi = np->vsi;
2141
2142 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2143 i40e_vlan_stripping_enable(vsi);
2144 else
2145 i40e_vlan_stripping_disable(vsi);
2146}
2147
2148/**
2149 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2150 * @vsi: the vsi being configured
2151 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2152 **/
2153int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2154{
2155 struct i40e_mac_filter *f, *add_f;
2156 bool is_netdev, is_vf;
41c445ff
JB		 2157
2158 is_vf = (vsi->type == I40E_VSI_SRIOV);
2159 is_netdev = !!(vsi->netdev);
2160
2161 if (is_netdev) {
2162 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2163 is_vf, is_netdev);
2164 if (!add_f) {
2165 dev_info(&vsi->back->pdev->dev,
2166 "Could not add vlan filter %d for %pM\n",
2167 vid, vsi->netdev->dev_addr);
2168 return -ENOMEM;
2169 }
2170 }
2171
2172 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2173 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2174 if (!add_f) {
2175 dev_info(&vsi->back->pdev->dev,
2176 "Could not add vlan filter %d for %pM\n",
2177 vid, f->macaddr);
2178 return -ENOMEM;
2179 }
2180 }
2181
41c445ff
JB		 2182 /* Now if we add a vlan tag, make sure to check if it is the first
2183 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2184 * with 0, so we now accept untagged and specified tagged traffic
2185 * (and not any taged and untagged)
2186 */
2187 if (vid > 0) {
2188 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2189 I40E_VLAN_ANY,
2190 is_vf, is_netdev)) {
2191 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2192 I40E_VLAN_ANY, is_vf, is_netdev);
2193 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2194 is_vf, is_netdev);
2195 if (!add_f) {
2196 dev_info(&vsi->back->pdev->dev,
2197 "Could not add filter 0 for %pM\n",
2198 vsi->netdev->dev_addr);
2199 return -ENOMEM;
2200 }
2201 }
8d82a7c5 2202 }
41c445ff 2203
8d82a7c5
GR		 2204 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2205 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2206 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2207 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2208 is_vf, is_netdev)) {
2209 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2210 is_vf, is_netdev);
2211 add_f = i40e_add_filter(vsi, f->macaddr,
2212 0, is_vf, is_netdev);
2213 if (!add_f) {
2214 dev_info(&vsi->back->pdev->dev,
2215 "Could not add filter 0 for %pM\n",
2216 f->macaddr);
2217 return -ENOMEM;
2218 }
2219 }
2220 }
41c445ff
JB		 2221 }
2222
80f6428f
ASJ		 2223 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2224 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2225 return 0;
2226
30e2561b 2227 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2228}
2229
2230/**
2231 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2232 * @vsi: the vsi being configured
2233 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2234 *
2235 * Return: 0 on success or negative otherwise
41c445ff
JB		 2236 **/
2237int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2238{
2239 struct net_device *netdev = vsi->netdev;
2240 struct i40e_mac_filter *f, *add_f;
2241 bool is_vf, is_netdev;
2242 int filter_count = 0;
41c445ff
JB		 2243
2244 is_vf = (vsi->type == I40E_VSI_SRIOV);
2245 is_netdev = !!(netdev);
2246
2247 if (is_netdev)
2248 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2249
2250 list_for_each_entry(f, &vsi->mac_filter_list, list)
2251 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2252
41c445ff
JB		 2253 /* go through all the filters for this VSI and if there is only
2254 * vid == 0 it means there are no other filters, so vid 0 must
2255 * be replaced with -1. This signifies that we should from now
2256 * on accept any traffic (with any tag present, or untagged)
2257 */
2258 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2259 if (is_netdev) {
2260 if (f->vlan &&
2261 ether_addr_equal(netdev->dev_addr, f->macaddr))
2262 filter_count++;
2263 }
2264
2265 if (f->vlan)
2266 filter_count++;
2267 }
2268
2269 if (!filter_count && is_netdev) {
2270 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2271 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2272 is_vf, is_netdev);
2273 if (!f) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Could not add filter %d for %pM\n",
2276 I40E_VLAN_ANY, netdev->dev_addr);
2277 return -ENOMEM;
2278 }
2279 }
2280
2281 if (!filter_count) {
2282 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2283 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2284 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2285 is_vf, is_netdev);
2286 if (!add_f) {
2287 dev_info(&vsi->back->pdev->dev,
2288 "Could not add filter %d for %pM\n",
2289 I40E_VLAN_ANY, f->macaddr);
2290 return -ENOMEM;
2291 }
2292 }
2293 }
2294
80f6428f
ASJ		 2295 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2296 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2297 return 0;
2298
30e2561b 2299 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2300}
2301
2302/**
2303 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2304 * @netdev: network interface to be adjusted
2305 * @vid: vlan id to be added
078b5876
JB		 2306 *
2307 * net_device_ops implementation for adding vlan ids
41c445ff 2308 **/
38e00438
VD		 2309#ifdef I40E_FCOE
2310int i40e_vlan_rx_add_vid(struct net_device *netdev,
2311 __always_unused __be16 proto, u16 vid)
2312#else
41c445ff
JB		 2313static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2314 __always_unused __be16 proto, u16 vid)
38e00438 2315#endif
41c445ff
JB		 2316{
2317 struct i40e_netdev_priv *np = netdev_priv(netdev);
2318 struct i40e_vsi *vsi = np->vsi;
078b5876 2319 int ret = 0;
41c445ff
JB		 2320
2321 if (vid > 4095)
078b5876
JB		 2322 return -EINVAL;
2323
2324 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2325
6982d429
ASJ		 2326 /* If the network stack called us with vid = 0 then
2327 * it is asking to receive priority tagged packets with
2328 * vlan id 0. Our HW receives them by default when configured
2329 * to receive untagged packets so there is no need to add an
2330 * extra filter for vlan 0 tagged packets.
41c445ff 2331 */
6982d429
ASJ		 2332 if (vid)
2333 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2334
078b5876
JB		 2335 if (!ret && (vid < VLAN_N_VID))
2336 set_bit(vid, vsi->active_vlans);
41c445ff 2337
078b5876 2338 return ret;
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2343 * @netdev: network interface to be adjusted
2344 * @vid: vlan id to be removed
078b5876 2345 *
fdfd943e 2346 * net_device_ops implementation for removing vlan ids
41c445ff 2347 **/
38e00438
VD		 2348#ifdef I40E_FCOE
2349int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2350 __always_unused __be16 proto, u16 vid)
2351#else
41c445ff
JB		 2352static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2353 __always_unused __be16 proto, u16 vid)
38e00438 2354#endif
41c445ff
JB		 2355{
2356 struct i40e_netdev_priv *np = netdev_priv(netdev);
2357 struct i40e_vsi *vsi = np->vsi;
2358
078b5876
JB		 2359 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2360
41c445ff
JB		 2361 /* return code is ignored as there is nothing a user
2362 * can do about failure to remove and a log message was
078b5876 2363 * already printed from the other function
41c445ff
JB		 2364 */
2365 i40e_vsi_kill_vlan(vsi, vid);
2366
2367 clear_bit(vid, vsi->active_vlans);
078b5876 2368
41c445ff
JB		 2369 return 0;
2370}
2371
2372/**
2373 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2374 * @vsi: the vsi being brought back up
2375 **/
2376static void i40e_restore_vlan(struct i40e_vsi *vsi)
2377{
2378 u16 vid;
2379
2380 if (!vsi->netdev)
2381 return;
2382
2383 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2384
2385 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2386 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2387 vid);
2388}
2389
2390/**
2391 * i40e_vsi_add_pvid - Add pvid for the VSI
2392 * @vsi: the vsi being adjusted
2393 * @vid: the vlan id to set as a PVID
2394 **/
dcae29be 2395int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2396{
2397 struct i40e_vsi_context ctxt;
f1c7e72e 2398 i40e_status ret;
41c445ff
JB		 2399
2400 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2401 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2402 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2403 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2404 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2405
2406 ctxt.seid = vsi->seid;
1a2f6248 2407 ctxt.info = vsi->info;
f1c7e72e
SN		 2408 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2409 if (ret) {
41c445ff 2410 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2411 "add pvid failed, err %s aq_err %s\n",
2412 i40e_stat_str(&vsi->back->hw, ret),
2413 i40e_aq_str(&vsi->back->hw,
2414 vsi->back->hw.aq.asq_last_status));
dcae29be 2415 return -ENOENT;
41c445ff
JB		 2416 }
2417
dcae29be 2418 return 0;
41c445ff
JB		 2419}
2420
2421/**
2422 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2423 * @vsi: the vsi being adjusted
2424 *
2425 * Just use the vlan_rx_register() service to put it back to normal
2426 **/
2427void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2428{
6c12fcbf
GR		 2429 i40e_vlan_stripping_disable(vsi);
2430
41c445ff 2431 vsi->info.pvid = 0;
41c445ff
JB		 2432}
2433
2434/**
2435 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2436 * @vsi: ptr to the VSI
2437 *
2438 * If this function returns with an error, then it's possible one or
2439 * more of the rings is populated (while the rest are not). It is the
2440 * callers duty to clean those orphaned rings.
2441 *
2442 * Return 0 on success, negative on failure
2443 **/
2444static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2445{
2446 int i, err = 0;
2447
2448 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2449 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2450
2451 return err;
2452}
2453
2454/**
2455 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2456 * @vsi: ptr to the VSI
2457 *
2458 * Free VSI's transmit software resources
2459 **/
2460static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2461{
2462 int i;
2463
8e9dca53
GR		 2464 if (!vsi->tx_rings)
2465 return;
2466
41c445ff 2467 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2468 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2469 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2470}
2471
2472/**
2473 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2474 * @vsi: ptr to the VSI
2475 *
2476 * If this function returns with an error, then it's possible one or
2477 * more of the rings is populated (while the rest are not). It is the
2478 * callers duty to clean those orphaned rings.
2479 *
2480 * Return 0 on success, negative on failure
2481 **/
2482static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2483{
2484 int i, err = 0;
2485
2486 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2487 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2488#ifdef I40E_FCOE
2489 i40e_fcoe_setup_ddp_resources(vsi);
2490#endif
41c445ff
JB		 2491 return err;
2492}
2493
2494/**
2495 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2496 * @vsi: ptr to the VSI
2497 *
2498 * Free all receive software resources
2499 **/
2500static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2501{
2502 int i;
2503
8e9dca53
GR		 2504 if (!vsi->rx_rings)
2505 return;
2506
41c445ff 2507 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2508 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2509 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2510#ifdef I40E_FCOE
2511 i40e_fcoe_free_ddp_resources(vsi);
2512#endif
41c445ff
JB		 2513}
2514
3ffa037d
NP		 2515/**
2516 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2517 * @ring: The Tx ring to configure
2518 *
2519 * This enables/disables XPS for a given Tx descriptor ring
2520 * based on the TCs enabled for the VSI that ring belongs to.
2521 **/
2522static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2523{
2524 struct i40e_vsi *vsi = ring->vsi;
2525 cpumask_var_t mask;
2526
9a660eea
JB		 2527 if (!ring->q_vector || !ring->netdev)
2528 return;
2529
2530 /* Single TC mode enable XPS */
2531 if (vsi->tc_config.numtc <= 1) {
2532 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2533 netif_set_xps_queue(ring->netdev,
2534 &ring->q_vector->affinity_mask,
2535 ring->queue_index);
9a660eea
JB		 2536 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2537 /* Disable XPS to allow selection based on TC */
2538 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2539 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2540 free_cpumask_var(mask);
3ffa037d
NP		 2541 }
2542}
2543
41c445ff
JB		 2544/**
2545 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2546 * @ring: The Tx ring to configure
2547 *
2548 * Configure the Tx descriptor ring in the HMC context.
2549 **/
2550static int i40e_configure_tx_ring(struct i40e_ring *ring)
2551{
2552 struct i40e_vsi *vsi = ring->vsi;
2553 u16 pf_q = vsi->base_queue + ring->queue_index;
2554 struct i40e_hw *hw = &vsi->back->hw;
2555 struct i40e_hmc_obj_txq tx_ctx;
2556 i40e_status err = 0;
2557 u32 qtx_ctl = 0;
2558
2559 /* some ATR related tx ring init */
60ea5f83 2560 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2561 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2562 ring->atr_count = 0;
2563 } else {
2564 ring->atr_sample_rate = 0;
2565 }
2566
3ffa037d
NP		 2567 /* configure XPS */
2568 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2569
2570 /* clear the context structure first */
2571 memset(&tx_ctx, 0, sizeof(tx_ctx));
2572
2573 tx_ctx.new_context = 1;
2574 tx_ctx.base = (ring->dma / 128);
2575 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2576 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2577 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2578#ifdef I40E_FCOE
2579 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2580#endif
beb0dff1 2581 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2582 /* FDIR VSI tx ring can still use RS bit and writebacks */
2583 if (vsi->type != I40E_VSI_FDIR)
2584 tx_ctx.head_wb_ena = 1;
2585 tx_ctx.head_wb_addr = ring->dma +
2586 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2587
2588 /* As part of VSI creation/update, FW allocates certain
2589 * Tx arbitration queue sets for each TC enabled for
2590 * the VSI. The FW returns the handles to these queue
2591 * sets as part of the response buffer to Add VSI,
2592 * Update VSI, etc. AQ commands. It is expected that
2593 * these queue set handles be associated with the Tx
2594 * queues by the driver as part of the TX queue context
2595 * initialization. This has to be done regardless of
2596 * DCB as by default everything is mapped to TC0.
2597 */
2598 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2599 tx_ctx.rdylist_act = 0;
2600
2601 /* clear the context in the HMC */
2602 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2603 if (err) {
2604 dev_info(&vsi->back->pdev->dev,
2605 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2606 ring->queue_index, pf_q, err);
2607 return -ENOMEM;
2608 }
2609
2610 /* set the context in the HMC */
2611 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2612 if (err) {
2613 dev_info(&vsi->back->pdev->dev,
2614 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2615 ring->queue_index, pf_q, err);
2616 return -ENOMEM;
2617 }
2618
2619 /* Now associate this queue with this PCI function */
7a28d885 2620 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2621 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2622 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2623 I40E_QTX_CTL_VFVM_INDX_MASK;
2624 } else {
9d8bf547 2625 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2626 }
2627
13fd9774
SN		 2628 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2629 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2630 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2631 i40e_flush(hw);
2632
41c445ff
JB		 2633 /* cache tail off for easier writes later */
2634 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2635
2636 return 0;
2637}
2638
2639/**
2640 * i40e_configure_rx_ring - Configure a receive ring context
2641 * @ring: The Rx ring to configure
2642 *
2643 * Configure the Rx descriptor ring in the HMC context.
2644 **/
2645static int i40e_configure_rx_ring(struct i40e_ring *ring)
2646{
2647 struct i40e_vsi *vsi = ring->vsi;
2648 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2649 u16 pf_q = vsi->base_queue + ring->queue_index;
2650 struct i40e_hw *hw = &vsi->back->hw;
2651 struct i40e_hmc_obj_rxq rx_ctx;
2652 i40e_status err = 0;
2653
2654 ring->state = 0;
2655
2656 /* clear the context structure first */
2657 memset(&rx_ctx, 0, sizeof(rx_ctx));
2658
2659 ring->rx_buf_len = vsi->rx_buf_len;
2660 ring->rx_hdr_len = vsi->rx_hdr_len;
2661
2662 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2663 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2664
2665 rx_ctx.base = (ring->dma / 128);
2666 rx_ctx.qlen = ring->count;
2667
2668 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2669 set_ring_16byte_desc_enabled(ring);
2670 rx_ctx.dsize = 0;
2671 } else {
2672 rx_ctx.dsize = 1;
2673 }
2674
2675 rx_ctx.dtype = vsi->dtype;
2676 if (vsi->dtype) {
2677 set_ring_ps_enabled(ring);
2678 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2679 I40E_RX_SPLIT_IP |
2680 I40E_RX_SPLIT_TCP_UDP |
2681 I40E_RX_SPLIT_SCTP;
2682 } else {
2683 rx_ctx.hsplit_0 = 0;
2684 }
2685
2686 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2687 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2688 if (hw->revision_id == 0)
2689 rx_ctx.lrxqthresh = 0;
2690 else
2691 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2692 rx_ctx.crcstrip = 1;
2693 rx_ctx.l2tsel = 1;
2694 rx_ctx.showiv = 1;
38e00438
VD		 2695#ifdef I40E_FCOE
2696 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2697#endif
acb3676b
CS		 2698 /* set the prefena field to 1 because the manual says to */
2699 rx_ctx.prefena = 1;
41c445ff
JB		 2700
2701 /* clear the context in the HMC */
2702 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2703 if (err) {
2704 dev_info(&vsi->back->pdev->dev,
2705 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2706 ring->queue_index, pf_q, err);
2707 return -ENOMEM;
2708 }
2709
2710 /* set the context in the HMC */
2711 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2712 if (err) {
2713 dev_info(&vsi->back->pdev->dev,
2714 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2715 ring->queue_index, pf_q, err);
2716 return -ENOMEM;
2717 }
2718
2719 /* cache tail for quicker writes, and clear the reg before use */
2720 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2721 writel(0, ring->tail);
2722
a132af24
MW		 2723 if (ring_is_ps_enabled(ring)) {
2724 i40e_alloc_rx_headers(ring);
2725 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2726 } else {
2727 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2728 }
41c445ff
JB		 2729
2730 return 0;
2731}
2732
2733/**
2734 * i40e_vsi_configure_tx - Configure the VSI for Tx
2735 * @vsi: VSI structure describing this set of rings and resources
2736 *
2737 * Configure the Tx VSI for operation.
2738 **/
2739static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2740{
2741 int err = 0;
2742 u16 i;
2743
9f65e15b
AD		 2744 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2745 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2746
2747 return err;
2748}
2749
2750/**
2751 * i40e_vsi_configure_rx - Configure the VSI for Rx
2752 * @vsi: the VSI being configured
2753 *
2754 * Configure the Rx VSI for operation.
2755 **/
2756static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2757{
2758 int err = 0;
2759 u16 i;
2760
2761 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2762 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2763 + ETH_FCS_LEN + VLAN_HLEN;
2764 else
2765 vsi->max_frame = I40E_RXBUFFER_2048;
2766
2767 /* figure out correct receive buffer length */
2768 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2769 I40E_FLAG_RX_PS_ENABLED)) {
2770 case I40E_FLAG_RX_1BUF_ENABLED:
2771 vsi->rx_hdr_len = 0;
2772 vsi->rx_buf_len = vsi->max_frame;
2773 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2774 break;
2775 case I40E_FLAG_RX_PS_ENABLED:
2776 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2777 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2778 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2779 break;
2780 default:
2781 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2782 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2783 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2784 break;
2785 }
2786
38e00438
VD		 2787#ifdef I40E_FCOE
2788 /* setup rx buffer for FCoE */
2789 if ((vsi->type == I40E_VSI_FCOE) &&
2790 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2791 vsi->rx_hdr_len = 0;
2792 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2793 vsi->max_frame = I40E_RXBUFFER_3072;
2794 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2795 }
2796
2797#endif /* I40E_FCOE */
41c445ff
JB		 2798 /* round up for the chip's needs */
2799 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2800 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2801 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2802 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2803
2804 /* set up individual rings */
2805 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2806 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2807
2808 return err;
2809}
2810
2811/**
2812 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2813 * @vsi: ptr to the VSI
2814 **/
2815static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2816{
e7046ee1 2817 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2818 u16 qoffset, qcount;
2819 int i, n;
2820
cd238a3e
PN		 2821 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2822 /* Reset the TC information */
2823 for (i = 0; i < vsi->num_queue_pairs; i++) {
2824 rx_ring = vsi->rx_rings[i];
2825 tx_ring = vsi->tx_rings[i];
2826 rx_ring->dcb_tc = 0;
2827 tx_ring->dcb_tc = 0;
2828 }
2829 }
41c445ff
JB		 2830
2831 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2832 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2833 continue;
2834
2835 qoffset = vsi->tc_config.tc_info[n].qoffset;
2836 qcount = vsi->tc_config.tc_info[n].qcount;
2837 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2838 rx_ring = vsi->rx_rings[i];
2839 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2840 rx_ring->dcb_tc = n;
2841 tx_ring->dcb_tc = n;
2842 }
2843 }
2844}
2845
2846/**
2847 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2848 * @vsi: ptr to the VSI
2849 **/
2850static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2851{
2852 if (vsi->netdev)
2853 i40e_set_rx_mode(vsi->netdev);
2854}
2855
17a73f6b
JG		 2856/**
2857 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2858 * @vsi: Pointer to the targeted VSI
2859 *
2860 * This function replays the hlist on the hw where all the SB Flow Director
2861 * filters were saved.
2862 **/
2863static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2864{
2865 struct i40e_fdir_filter *filter;
2866 struct i40e_pf *pf = vsi->back;
2867 struct hlist_node *node;
2868
55a5e60b
ASJ		 2869 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2870 return;
2871
17a73f6b
JG		 2872 hlist_for_each_entry_safe(filter, node,
2873 &pf->fdir_filter_list, fdir_node) {
2874 i40e_add_del_fdir(vsi, filter, true);
2875 }
2876}
2877
41c445ff
JB		 2878/**
2879 * i40e_vsi_configure - Set up the VSI for action
2880 * @vsi: the VSI being configured
2881 **/
2882static int i40e_vsi_configure(struct i40e_vsi *vsi)
2883{
2884 int err;
2885
2886 i40e_set_vsi_rx_mode(vsi);
2887 i40e_restore_vlan(vsi);
2888 i40e_vsi_config_dcb_rings(vsi);
2889 err = i40e_vsi_configure_tx(vsi);
2890 if (!err)
2891 err = i40e_vsi_configure_rx(vsi);
2892
2893 return err;
2894}
2895
2896/**
2897 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2898 * @vsi: the VSI being configured
2899 **/
2900static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2901{
2902 struct i40e_pf *pf = vsi->back;
2903 struct i40e_q_vector *q_vector;
2904 struct i40e_hw *hw = &pf->hw;
2905 u16 vector;
2906 int i, q;
2907 u32 val;
2908 u32 qp;
2909
2910 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2911 * and PFINT_LNKLSTn registers, e.g.:
2912 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2913 */
2914 qp = vsi->base_queue;
2915 vector = vsi->base_vector;
493fb300
AD		 2916 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2917 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2918 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2919 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2920 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2921 q_vector->rx.itr);
2922 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2923 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2924 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2925 q_vector->tx.itr);
2926
2927 /* Linked list for the queuepairs assigned to this vector */
2928 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2929 for (q = 0; q < q_vector->num_ringpairs; q++) {
2930 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2931 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2932 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2933 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2934 (I40E_QUEUE_TYPE_TX
2935 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2936
2937 wr32(hw, I40E_QINT_RQCTL(qp), val);
2938
2939 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2940 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2941 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2942 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2943 (I40E_QUEUE_TYPE_RX
2944 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2945
2946 /* Terminate the linked list */
2947 if (q == (q_vector->num_ringpairs - 1))
2948 val |= (I40E_QUEUE_END_OF_LIST
2949 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2950
2951 wr32(hw, I40E_QINT_TQCTL(qp), val);
2952 qp++;
2953 }
2954 }
2955
2956 i40e_flush(hw);
2957}
2958
2959/**
2960 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2961 * @hw: ptr to the hardware info
2962 **/
ab437b5a 2963static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2964{
ab437b5a 2965 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2966 u32 val;
2967
2968 /* clear things first */
2969 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2970 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2971
2972 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2973 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2974 I40E_PFINT_ICR0_ENA_GRST_MASK |
2975 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2976 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2977 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2978 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2979 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2980
0d8e1439
ASJ		 2981 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
2982 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
2983
ab437b5a
JK		 2984 if (pf->flags & I40E_FLAG_PTP)
2985 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2986
41c445ff
JB		 2987 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2988
2989 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2990 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2991 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2992
2993 /* OTHER_ITR_IDX = 0 */
2994 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2995}
2996
2997/**
2998 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2999 * @vsi: the VSI being configured
3000 **/
3001static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3002{
493fb300 3003 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3004 struct i40e_pf *pf = vsi->back;
3005 struct i40e_hw *hw = &pf->hw;
3006 u32 val;
3007
3008 /* set the ITR configuration */
3009 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3010 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3011 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3012 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3013 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3014 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3015
ab437b5a 3016 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3017
3018 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3019 wr32(hw, I40E_PFINT_LNKLST0, 0);
3020
f29eaa3d 3021 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3022 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3023 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3024 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3025
3026 wr32(hw, I40E_QINT_RQCTL(0), val);
3027
3028 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3029 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3030 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3031
3032 wr32(hw, I40E_QINT_TQCTL(0), val);
3033 i40e_flush(hw);
3034}
3035
2ef28cfb
MW		 3036/**
3037 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3038 * @pf: board private structure
3039 **/
3040void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3041{
3042 struct i40e_hw *hw = &pf->hw;
3043
3044 wr32(hw, I40E_PFINT_DYN_CTL0,
3045 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3046 i40e_flush(hw);
3047}
3048
41c445ff
JB		 3049/**
3050 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3051 * @pf: board private structure
3052 **/
116a57d4 3053void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3054{
3055 struct i40e_hw *hw = &pf->hw;
3056 u32 val;
3057
3058 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3059 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3060 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3061
3062 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3063 i40e_flush(hw);
3064}
3065
3066/**
3067 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
3068 * @vsi: pointer to a vsi
3069 * @vector: enable a particular Hw Interrupt vector
3070 **/
3071void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
3072{
3073 struct i40e_pf *pf = vsi->back;
3074 struct i40e_hw *hw = &pf->hw;
3075 u32 val;
3076
3077 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
3078 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
3079 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3080 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 3081 /* skip the flush */
41c445ff
JB		 3082}
3083
5c2cebda
CW		 3084/**
3085 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3086 * @vsi: pointer to a vsi
03147773 3087 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3088 **/
3089void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3090{
3091 struct i40e_pf *pf = vsi->back;
3092 struct i40e_hw *hw = &pf->hw;
3093 u32 val;
3094
3095 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3096 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3097 i40e_flush(hw);
3098}
3099
41c445ff
JB		 3100/**
3101 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3102 * @irq: interrupt number
3103 * @data: pointer to a q_vector
3104 **/
3105static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3106{
3107 struct i40e_q_vector *q_vector = data;
3108
cd0b6fa6 3109 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3110 return IRQ_HANDLED;
3111
3112 napi_schedule(&q_vector->napi);
3113
3114 return IRQ_HANDLED;
3115}
3116
41c445ff
JB		 3117/**
3118 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3119 * @vsi: the VSI being configured
3120 * @basename: name for the vector
3121 *
3122 * Allocates MSI-X vectors and requests interrupts from the kernel.
3123 **/
3124static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3125{
3126 int q_vectors = vsi->num_q_vectors;
3127 struct i40e_pf *pf = vsi->back;
3128 int base = vsi->base_vector;
3129 int rx_int_idx = 0;
3130 int tx_int_idx = 0;
3131 int vector, err;
3132
3133 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3134 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3135
cd0b6fa6 3136 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3137 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3138 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3139 tx_int_idx++;
cd0b6fa6 3140 } else if (q_vector->rx.ring) {
41c445ff
JB		 3141 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3142 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3143 } else if (q_vector->tx.ring) {
41c445ff
JB		 3144 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3145 "%s-%s-%d", basename, "tx", tx_int_idx++);
3146 } else {
3147 /* skip this unused q_vector */
3148 continue;
3149 }
3150 err = request_irq(pf->msix_entries[base + vector].vector,
3151 vsi->irq_handler,
3152 0,
3153 q_vector->name,
3154 q_vector);
3155 if (err) {
3156 dev_info(&pf->pdev->dev,
3157 "%s: request_irq failed, error: %d\n",
3158 __func__, err);
3159 goto free_queue_irqs;
3160 }
3161 /* assign the mask for this irq */
3162 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3163 &q_vector->affinity_mask);
3164 }
3165
63741846 3166 vsi->irqs_ready = true;
41c445ff
JB		 3167 return 0;
3168
3169free_queue_irqs:
3170 while (vector) {
3171 vector--;
3172 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3173 NULL);
3174 free_irq(pf->msix_entries[base + vector].vector,
3175 &(vsi->q_vectors[vector]));
3176 }
3177 return err;
3178}
3179
3180/**
3181 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3182 * @vsi: the VSI being un-configured
3183 **/
3184static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3185{
3186 struct i40e_pf *pf = vsi->back;
3187 struct i40e_hw *hw = &pf->hw;
3188 int base = vsi->base_vector;
3189 int i;
3190
3191 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3192 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3193 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3194 }
3195
3196 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3197 for (i = vsi->base_vector;
3198 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3199 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3200
3201 i40e_flush(hw);
3202 for (i = 0; i < vsi->num_q_vectors; i++)
3203 synchronize_irq(pf->msix_entries[i + base].vector);
3204 } else {
3205 /* Legacy and MSI mode - this stops all interrupt handling */
3206 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3207 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3208 i40e_flush(hw);
3209 synchronize_irq(pf->pdev->irq);
3210 }
3211}
3212
3213/**
3214 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3215 * @vsi: the VSI being configured
3216 **/
3217static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3218{
3219 struct i40e_pf *pf = vsi->back;
3220 int i;
3221
3222 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3223 for (i = vsi->base_vector;
3224 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3225 i40e_irq_dynamic_enable(vsi, i);
3226 } else {
3227 i40e_irq_dynamic_enable_icr0(pf);
3228 }
3229
1022cb6c 3230 i40e_flush(&pf->hw);
41c445ff
JB		 3231 return 0;
3232}
3233
3234/**
3235 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3236 * @pf: board private structure
3237 **/
3238static void i40e_stop_misc_vector(struct i40e_pf *pf)
3239{
3240 /* Disable ICR 0 */
3241 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3242 i40e_flush(&pf->hw);
3243}
3244
3245/**
3246 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3247 * @irq: interrupt number
3248 * @data: pointer to a q_vector
3249 *
3250 * This is the handler used for all MSI/Legacy interrupts, and deals
3251 * with both queue and non-queue interrupts. This is also used in
3252 * MSIX mode to handle the non-queue interrupts.
3253 **/
3254static irqreturn_t i40e_intr(int irq, void *data)
3255{
3256 struct i40e_pf *pf = (struct i40e_pf *)data;
3257 struct i40e_hw *hw = &pf->hw;
5e823066 3258 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3259 u32 icr0, icr0_remaining;
3260 u32 val, ena_mask;
3261
3262 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3263 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3264
116a57d4
SN		 3265 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3266 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3267 goto enable_intr;
41c445ff 3268
cd92e72f
SN		 3269 /* if interrupt but no bits showing, must be SWINT */
3270 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3271 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3272 pf->sw_int_count++;
3273
0d8e1439
ASJ		 3274 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3275 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3276 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3277 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3278 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3279 }
3280
41c445ff
JB		 3281 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3282 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3283
3284 /* temporarily disable queue cause for NAPI processing */
3285 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3286 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3287 wr32(hw, I40E_QINT_RQCTL(0), qval);
3288
3289 qval = rd32(hw, I40E_QINT_TQCTL(0));
3290 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3291 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3292
3293 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3294 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3295 }
3296
3297 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3298 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3299 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3300 }
3301
3302 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3303 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3304 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3305 }
3306
3307 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3308 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3309 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3310 }
3311
3312 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3313 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3314 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3315 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3316 val = rd32(hw, I40E_GLGEN_RSTAT);
3317 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3318 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3319 if (val == I40E_RESET_CORER) {
41c445ff 3320 pf->corer_count++;
4eb3f768 3321 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3322 pf->globr_count++;
4eb3f768 3323 } else if (val == I40E_RESET_EMPR) {
41c445ff 3324 pf->empr_count++;
9df42d1a 3325 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3326 }
41c445ff
JB		 3327 }
3328
9c010ee0
ASJ		 3329 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3330 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3331 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3332 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3333 rd32(hw, I40E_PFHMC_ERRORINFO),
3334 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3335 }
3336
beb0dff1
JK		 3337 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3338 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3339
3340 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3341 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3342 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3343 }
beb0dff1
JK		 3344 }
3345
41c445ff
JB		 3346 /* If a critical error is pending we have no choice but to reset the
3347 * device.
3348 * Report and mask out any remaining unexpected interrupts.
3349 */
3350 icr0_remaining = icr0 & ena_mask;
3351 if (icr0_remaining) {
3352 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3353 icr0_remaining);
9c010ee0 3354 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3355 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3356 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3357 dev_info(&pf->pdev->dev, "device will be reset\n");
3358 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3359 i40e_service_event_schedule(pf);
41c445ff
JB		 3360 }
3361 ena_mask &= ~icr0_remaining;
3362 }
5e823066 3363 ret = IRQ_HANDLED;
41c445ff 3364
5e823066 3365enable_intr:
41c445ff
JB		 3366 /* re-enable interrupt causes */
3367 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3368 if (!test_bit(__I40E_DOWN, &pf->state)) {
3369 i40e_service_event_schedule(pf);
3370 i40e_irq_dynamic_enable_icr0(pf);
3371 }
3372
5e823066 3373 return ret;
41c445ff
JB		 3374}
3375
cbf61325
ASJ		 3376/**
3377 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3378 * @tx_ring: tx ring to clean
3379 * @budget: how many cleans we're allowed
3380 *
3381 * Returns true if there's any budget left (e.g. the clean is finished)
3382 **/
3383static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3384{
3385 struct i40e_vsi *vsi = tx_ring->vsi;
3386 u16 i = tx_ring->next_to_clean;
3387 struct i40e_tx_buffer *tx_buf;
3388 struct i40e_tx_desc *tx_desc;
3389
3390 tx_buf = &tx_ring->tx_bi[i];
3391 tx_desc = I40E_TX_DESC(tx_ring, i);
3392 i -= tx_ring->count;
3393
3394 do {
3395 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3396
3397 /* if next_to_watch is not set then there is no work pending */
3398 if (!eop_desc)
3399 break;
3400
3401 /* prevent any other reads prior to eop_desc */
3402 read_barrier_depends();
3403
3404 /* if the descriptor isn't done, no work yet to do */
3405 if (!(eop_desc->cmd_type_offset_bsz &
3406 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3407 break;
3408
3409 /* clear next_to_watch to prevent false hangs */
3410 tx_buf->next_to_watch = NULL;
3411
49d7d933
ASJ		 3412 tx_desc->buffer_addr = 0;
3413 tx_desc->cmd_type_offset_bsz = 0;
3414 /* move past filter desc */
3415 tx_buf++;
3416 tx_desc++;
3417 i++;
3418 if (unlikely(!i)) {
3419 i -= tx_ring->count;
3420 tx_buf = tx_ring->tx_bi;
3421 tx_desc = I40E_TX_DESC(tx_ring, 0);
3422 }
cbf61325
ASJ		 3423 /* unmap skb header data */
3424 dma_unmap_single(tx_ring->dev,
3425 dma_unmap_addr(tx_buf, dma),
3426 dma_unmap_len(tx_buf, len),
3427 DMA_TO_DEVICE);
49d7d933
ASJ		 3428 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3429 kfree(tx_buf->raw_buf);
cbf61325 3430
49d7d933
ASJ		 3431 tx_buf->raw_buf = NULL;
3432 tx_buf->tx_flags = 0;
3433 tx_buf->next_to_watch = NULL;
cbf61325 3434 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3435 tx_desc->buffer_addr = 0;
3436 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3437
49d7d933 3438 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3439 tx_buf++;
3440 tx_desc++;
3441 i++;
3442 if (unlikely(!i)) {
3443 i -= tx_ring->count;
3444 tx_buf = tx_ring->tx_bi;
3445 tx_desc = I40E_TX_DESC(tx_ring, 0);
3446 }
3447
3448 /* update budget accounting */
3449 budget--;
3450 } while (likely(budget));
3451
3452 i += tx_ring->count;
3453 tx_ring->next_to_clean = i;
3454
3455 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3456 i40e_irq_dynamic_enable(vsi,
3457 tx_ring->q_vector->v_idx + vsi->base_vector);
3458 }
3459 return budget > 0;
3460}
3461
3462/**
3463 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3464 * @irq: interrupt number
3465 * @data: pointer to a q_vector
3466 **/
3467static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3468{
3469 struct i40e_q_vector *q_vector = data;
3470 struct i40e_vsi *vsi;
3471
3472 if (!q_vector->tx.ring)
3473 return IRQ_HANDLED;
3474
3475 vsi = q_vector->tx.ring->vsi;
3476 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3477
3478 return IRQ_HANDLED;
3479}
3480
41c445ff 3481/**
cd0b6fa6 3482 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3483 * @vsi: the VSI being configured
3484 * @v_idx: vector index
cd0b6fa6 3485 * @qp_idx: queue pair index
41c445ff 3486 **/
26cdc443 3487static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3488{
493fb300 3489 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3490 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3491 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3492
3493 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3494 tx_ring->next = q_vector->tx.ring;
3495 q_vector->tx.ring = tx_ring;
41c445ff 3496 q_vector->tx.count++;
cd0b6fa6
AD		 3497
3498 rx_ring->q_vector = q_vector;
3499 rx_ring->next = q_vector->rx.ring;
3500 q_vector->rx.ring = rx_ring;
3501 q_vector->rx.count++;
41c445ff
JB		 3502}
3503
3504/**
3505 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3506 * @vsi: the VSI being configured
3507 *
3508 * This function maps descriptor rings to the queue-specific vectors
3509 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3510 * one vector per queue pair, but on a constrained vector budget, we
3511 * group the queue pairs as "efficiently" as possible.
3512 **/
3513static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3514{
3515 int qp_remaining = vsi->num_queue_pairs;
3516 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3517 int num_ringpairs;
41c445ff
JB		 3518 int v_start = 0;
3519 int qp_idx = 0;
3520
3521 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3522 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3523 * It is also important to go through all the vectors available to be
3524 * sure that if we don't use all the vectors, that the remaining vectors
3525 * are cleared. This is especially important when decreasing the
3526 * number of queues in use.
41c445ff 3527 */
70114ec4 3528 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3529 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3530
3531 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3532
3533 q_vector->num_ringpairs = num_ringpairs;
3534
3535 q_vector->rx.count = 0;
3536 q_vector->tx.count = 0;
3537 q_vector->rx.ring = NULL;
3538 q_vector->tx.ring = NULL;
3539
3540 while (num_ringpairs--) {
26cdc443 3541 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3542 qp_idx++;
3543 qp_remaining--;
41c445ff
JB		 3544 }
3545 }
3546}
3547
3548/**
3549 * i40e_vsi_request_irq - Request IRQ from the OS
3550 * @vsi: the VSI being configured
3551 * @basename: name for the vector
3552 **/
3553static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3554{
3555 struct i40e_pf *pf = vsi->back;
3556 int err;
3557
3558 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3559 err = i40e_vsi_request_irq_msix(vsi, basename);
3560 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3561 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3562 pf->int_name, pf);
41c445ff
JB		 3563 else
3564 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3565 pf->int_name, pf);
41c445ff
JB		 3566
3567 if (err)
3568 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3569
3570 return err;
3571}
3572
3573#ifdef CONFIG_NET_POLL_CONTROLLER
3574/**
3575 * i40e_netpoll - A Polling 'interrupt'handler
3576 * @netdev: network interface device structure
3577 *
3578 * This is used by netconsole to send skbs without having to re-enable
3579 * interrupts. It's not called while the normal interrupt routine is executing.
3580 **/
38e00438
VD		 3581#ifdef I40E_FCOE
3582void i40e_netpoll(struct net_device *netdev)
3583#else
41c445ff 3584static void i40e_netpoll(struct net_device *netdev)
38e00438 3585#endif
41c445ff
JB		 3586{
3587 struct i40e_netdev_priv *np = netdev_priv(netdev);
3588 struct i40e_vsi *vsi = np->vsi;
3589 struct i40e_pf *pf = vsi->back;
3590 int i;
3591
3592 /* if interface is down do nothing */
3593 if (test_bit(__I40E_DOWN, &vsi->state))
3594 return;
3595
3596 pf->flags |= I40E_FLAG_IN_NETPOLL;
3597 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3598 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3599 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3600 } else {
3601 i40e_intr(pf->pdev->irq, netdev);
3602 }
3603 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3604}
3605#endif
3606
23527308
NP		 3607/**
3608 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3609 * @pf: the PF being configured
3610 * @pf_q: the PF queue
3611 * @enable: enable or disable state of the queue
3612 *
3613 * This routine will wait for the given Tx queue of the PF to reach the
3614 * enabled or disabled state.
3615 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3616 * multiple retries; else will return 0 in case of success.
3617 **/
3618static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3619{
3620 int i;
3621 u32 tx_reg;
3622
3623 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3624 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3625 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3626 break;
3627
f98a2006 3628 usleep_range(10, 20);
23527308
NP		 3629 }
3630 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3631 return -ETIMEDOUT;
3632
3633 return 0;
3634}
3635
41c445ff
JB		 3636/**
3637 * i40e_vsi_control_tx - Start or stop a VSI's rings
3638 * @vsi: the VSI being configured
3639 * @enable: start or stop the rings
3640 **/
3641static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3642{
3643 struct i40e_pf *pf = vsi->back;
3644 struct i40e_hw *hw = &pf->hw;
23527308 3645 int i, j, pf_q, ret = 0;
41c445ff
JB		 3646 u32 tx_reg;
3647
3648 pf_q = vsi->base_queue;
3649 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3650
3651 /* warn the TX unit of coming changes */
3652 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3653 if (!enable)
f98a2006 3654 usleep_range(10, 20);
351499ab 3655
6c5ef620 3656 for (j = 0; j < 50; j++) {
41c445ff 3657 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3658 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3659 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3660 break;
3661 usleep_range(1000, 2000);
3662 }
fda972f6 3663 /* Skip if the queue is already in the requested state */
7c122007 3664 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3665 continue;
41c445ff
JB		 3666
3667 /* turn on/off the queue */
c5c9eb9e
SN		 3668 if (enable) {
3669 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3670 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3671 } else {
41c445ff 3672 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3673 }
41c445ff
JB		 3674
3675 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3676 /* No waiting for the Tx queue to disable */
3677 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3678 continue;
41c445ff
JB		 3679
3680 /* wait for the change to finish */
23527308
NP		 3681 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3682 if (ret) {
3683 dev_info(&pf->pdev->dev,
3684 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3685 __func__, vsi->seid, pf_q,
3686 (enable ? "en" : "dis"));
3687 break;
41c445ff
JB		 3688 }
3689 }
3690
7134f9ce
JB		 3691 if (hw->revision_id == 0)
3692 mdelay(50);
23527308
NP		 3693 return ret;
3694}
3695
3696/**
3697 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3698 * @pf: the PF being configured
3699 * @pf_q: the PF queue
3700 * @enable: enable or disable state of the queue
3701 *
3702 * This routine will wait for the given Rx queue of the PF to reach the
3703 * enabled or disabled state.
3704 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3705 * multiple retries; else will return 0 in case of success.
3706 **/
3707static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3708{
3709 int i;
3710 u32 rx_reg;
3711
3712 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3713 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3714 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3715 break;
3716
f98a2006 3717 usleep_range(10, 20);
23527308
NP		 3718 }
3719 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3720 return -ETIMEDOUT;
7134f9ce 3721
41c445ff
JB		 3722 return 0;
3723}
3724
3725/**
3726 * i40e_vsi_control_rx - Start or stop a VSI's rings
3727 * @vsi: the VSI being configured
3728 * @enable: start or stop the rings
3729 **/
3730static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3731{
3732 struct i40e_pf *pf = vsi->back;
3733 struct i40e_hw *hw = &pf->hw;
23527308 3734 int i, j, pf_q, ret = 0;
41c445ff
JB		 3735 u32 rx_reg;
3736
3737 pf_q = vsi->base_queue;
3738 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3739 for (j = 0; j < 50; j++) {
41c445ff 3740 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3741 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3742 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3743 break;
3744 usleep_range(1000, 2000);
3745 }
41c445ff 3746
7c122007
CS		 3747 /* Skip if the queue is already in the requested state */
3748 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3749 continue;
41c445ff
JB		 3750
3751 /* turn on/off the queue */
3752 if (enable)
6c5ef620 3753 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3754 else
6c5ef620 3755 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3756 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3757
3758 /* wait for the change to finish */
23527308
NP		 3759 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3760 if (ret) {
3761 dev_info(&pf->pdev->dev,
3762 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3763 __func__, vsi->seid, pf_q,
3764 (enable ? "en" : "dis"));
3765 break;
41c445ff
JB		 3766 }
3767 }
3768
23527308 3769 return ret;
41c445ff
JB		 3770}
3771
3772/**
3773 * i40e_vsi_control_rings - Start or stop a VSI's rings
3774 * @vsi: the VSI being configured
3775 * @enable: start or stop the rings
3776 **/
fc18eaa0 3777int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3778{
3b867b28 3779 int ret = 0;
41c445ff
JB		 3780
3781 /* do rx first for enable and last for disable */
3782 if (request) {
3783 ret = i40e_vsi_control_rx(vsi, request);
3784 if (ret)
3785 return ret;
3786 ret = i40e_vsi_control_tx(vsi, request);
3787 } else {
3b867b28
ASJ		 3788 /* Ignore return value, we need to shutdown whatever we can */
3789 i40e_vsi_control_tx(vsi, request);
3790 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3791 }
3792
3793 return ret;
3794}
3795
3796/**
3797 * i40e_vsi_free_irq - Free the irq association with the OS
3798 * @vsi: the VSI being configured
3799 **/
3800static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3801{
3802 struct i40e_pf *pf = vsi->back;
3803 struct i40e_hw *hw = &pf->hw;
3804 int base = vsi->base_vector;
3805 u32 val, qp;
3806 int i;
3807
3808 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3809 if (!vsi->q_vectors)
3810 return;
3811
63741846
SN		 3812 if (!vsi->irqs_ready)
3813 return;
3814
3815 vsi->irqs_ready = false;
41c445ff
JB		 3816 for (i = 0; i < vsi->num_q_vectors; i++) {
3817 u16 vector = i + base;
3818
3819 /* free only the irqs that were actually requested */
78681b1f
SN		 3820 if (!vsi->q_vectors[i] ||
3821 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3822 continue;
3823
3824 /* clear the affinity_mask in the IRQ descriptor */
3825 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3826 NULL);
3827 free_irq(pf->msix_entries[vector].vector,
493fb300 3828 vsi->q_vectors[i]);
41c445ff
JB		 3829
3830 /* Tear down the interrupt queue link list
3831 *
3832 * We know that they come in pairs and always
3833 * the Rx first, then the Tx. To clear the
3834 * link list, stick the EOL value into the
3835 * next_q field of the registers.
3836 */
3837 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3838 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3839 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3840 val |= I40E_QUEUE_END_OF_LIST
3841 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3842 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3843
3844 while (qp != I40E_QUEUE_END_OF_LIST) {
3845 u32 next;
3846
3847 val = rd32(hw, I40E_QINT_RQCTL(qp));
3848
3849 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3850 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3851 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3852 I40E_QINT_RQCTL_INTEVENT_MASK);
3853
3854 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3855 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3856
3857 wr32(hw, I40E_QINT_RQCTL(qp), val);
3858
3859 val = rd32(hw, I40E_QINT_TQCTL(qp));
3860
3861 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3862 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3863
3864 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3865 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3866 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3867 I40E_QINT_TQCTL_INTEVENT_MASK);
3868
3869 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3870 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3871
3872 wr32(hw, I40E_QINT_TQCTL(qp), val);
3873 qp = next;
3874 }
3875 }
3876 } else {
3877 free_irq(pf->pdev->irq, pf);
3878
3879 val = rd32(hw, I40E_PFINT_LNKLST0);
3880 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3881 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3882 val |= I40E_QUEUE_END_OF_LIST
3883 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3884 wr32(hw, I40E_PFINT_LNKLST0, val);
3885
3886 val = rd32(hw, I40E_QINT_RQCTL(qp));
3887 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3888 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3889 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3890 I40E_QINT_RQCTL_INTEVENT_MASK);
3891
3892 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3893 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3894
3895 wr32(hw, I40E_QINT_RQCTL(qp), val);
3896
3897 val = rd32(hw, I40E_QINT_TQCTL(qp));
3898
3899 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3900 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3901 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3902 I40E_QINT_TQCTL_INTEVENT_MASK);
3903
3904 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3905 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3906
3907 wr32(hw, I40E_QINT_TQCTL(qp), val);
3908 }
3909}
3910
493fb300
AD		 3911/**
3912 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3913 * @vsi: the VSI being configured
3914 * @v_idx: Index of vector to be freed
3915 *
3916 * This function frees the memory allocated to the q_vector. In addition if
3917 * NAPI is enabled it will delete any references to the NAPI struct prior
3918 * to freeing the q_vector.
3919 **/
3920static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3921{
3922 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3923 struct i40e_ring *ring;
493fb300
AD		 3924
3925 if (!q_vector)
3926 return;
3927
3928 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3929 i40e_for_each_ring(ring, q_vector->tx)
3930 ring->q_vector = NULL;
3931
3932 i40e_for_each_ring(ring, q_vector->rx)
3933 ring->q_vector = NULL;
493fb300
AD		 3934
3935 /* only VSI w/ an associated netdev is set up w/ NAPI */
3936 if (vsi->netdev)
3937 netif_napi_del(&q_vector->napi);
3938
3939 vsi->q_vectors[v_idx] = NULL;
3940
3941 kfree_rcu(q_vector, rcu);
3942}
3943
41c445ff
JB		 3944/**
3945 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3946 * @vsi: the VSI being un-configured
3947 *
3948 * This frees the memory allocated to the q_vectors and
3949 * deletes references to the NAPI struct.
3950 **/
3951static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3952{
3953 int v_idx;
3954
493fb300
AD		 3955 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3956 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3957}
3958
3959/**
3960 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3961 * @pf: board private structure
3962 **/
3963static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3964{
3965 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3966 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3967 pci_disable_msix(pf->pdev);
3968 kfree(pf->msix_entries);
3969 pf->msix_entries = NULL;
3b444399
SN		 3970 kfree(pf->irq_pile);
3971 pf->irq_pile = NULL;
41c445ff
JB		 3972 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3973 pci_disable_msi(pf->pdev);
3974 }
3975 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3976}
3977
3978/**
3979 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3980 * @pf: board private structure
3981 *
3982 * We go through and clear interrupt specific resources and reset the structure
3983 * to pre-load conditions
3984 **/
3985static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3986{
3987 int i;
3988
e147758d
SN		 3989 i40e_stop_misc_vector(pf);
3990 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3991 synchronize_irq(pf->msix_entries[0].vector);
3992 free_irq(pf->msix_entries[0].vector, pf);
3993 }
3994
41c445ff 3995 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3996 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3997 if (pf->vsi[i])
3998 i40e_vsi_free_q_vectors(pf->vsi[i]);
3999 i40e_reset_interrupt_capability(pf);
4000}
4001
4002/**
4003 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4004 * @vsi: the VSI being configured
4005 **/
4006static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4007{
4008 int q_idx;
4009
4010 if (!vsi->netdev)
4011 return;
4012
4013 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4014 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4015}
4016
4017/**
4018 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4019 * @vsi: the VSI being configured
4020 **/
4021static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4022{
4023 int q_idx;
4024
4025 if (!vsi->netdev)
4026 return;
4027
4028 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4029 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4030}
4031
90ef8d47
SN		 4032/**
4033 * i40e_vsi_close - Shut down a VSI
4034 * @vsi: the vsi to be quelled
4035 **/
4036static void i40e_vsi_close(struct i40e_vsi *vsi)
4037{
4038 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4039 i40e_down(vsi);
4040 i40e_vsi_free_irq(vsi);
4041 i40e_vsi_free_tx_resources(vsi);
4042 i40e_vsi_free_rx_resources(vsi);
92faef85 4043 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4044}
4045
41c445ff
JB		 4046/**
4047 * i40e_quiesce_vsi - Pause a given VSI
4048 * @vsi: the VSI being paused
4049 **/
4050static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4051{
4052 if (test_bit(__I40E_DOWN, &vsi->state))
4053 return;
4054
d341b7a5
NP		 4055 /* No need to disable FCoE VSI when Tx suspended */
4056 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4057 vsi->type == I40E_VSI_FCOE) {
4058 dev_dbg(&vsi->back->pdev->dev,
4059 "%s: VSI seid %d skipping FCoE VSI disable\n",
4060 __func__, vsi->seid);
4061 return;
4062 }
4063
41c445ff
JB		 4064 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
4065 if (vsi->netdev && netif_running(vsi->netdev)) {
4066 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
4067 } else {
90ef8d47 4068 i40e_vsi_close(vsi);
41c445ff
JB		 4069 }
4070}
4071
4072/**
4073 * i40e_unquiesce_vsi - Resume a given VSI
4074 * @vsi: the VSI being resumed
4075 **/
4076static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4077{
4078 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4079 return;
4080
4081 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4082 if (vsi->netdev && netif_running(vsi->netdev))
4083 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4084 else
8276f757 4085 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4086}
4087
4088/**
4089 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4090 * @pf: the PF
4091 **/
4092static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4093{
4094 int v;
4095
505682cd 4096 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4097 if (pf->vsi[v])
4098 i40e_quiesce_vsi(pf->vsi[v]);
4099 }
4100}
4101
4102/**
4103 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4104 * @pf: the PF
4105 **/
4106static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4107{
4108 int v;
4109
505682cd 4110 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4111 if (pf->vsi[v])
4112 i40e_unquiesce_vsi(pf->vsi[v]);
4113 }
4114}
4115
69129dc3
NP		 4116#ifdef CONFIG_I40E_DCB
4117/**
4118 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4119 * @vsi: the VSI being configured
4120 *
4121 * This function waits for the given VSI's Tx queues to be disabled.
4122 **/
4123static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4124{
4125 struct i40e_pf *pf = vsi->back;
4126 int i, pf_q, ret;
4127
4128 pf_q = vsi->base_queue;
4129 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4130 /* Check and wait for the disable status of the queue */
4131 ret = i40e_pf_txq_wait(pf, pf_q, false);
4132 if (ret) {
4133 dev_info(&pf->pdev->dev,
4134 "%s: VSI seid %d Tx ring %d disable timeout\n",
4135 __func__, vsi->seid, pf_q);
4136 return ret;
4137 }
4138 }
4139
4140 return 0;
4141}
4142
4143/**
4144 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4145 * @pf: the PF
4146 *
4147 * This function waits for the Tx queues to be in disabled state for all the
4148 * VSIs that are managed by this PF.
4149 **/
4150static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4151{
4152 int v, ret = 0;
4153
4154 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4155 /* No need to wait for FCoE VSI queues */
4156 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4157 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4158 if (ret)
4159 break;
4160 }
4161 }
4162
4163 return ret;
4164}
4165
4166#endif
b03a8c1f
KP		 4167
4168/**
4169 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4170 * @q_idx: TX queue number
4171 * @vsi: Pointer to VSI struct
4172 *
4173 * This function checks specified queue for given VSI. Detects hung condition.
4174 * Sets hung bit since it is two step process. Before next run of service task
4175 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4176 * hung condition remain unchanged and during subsequent run, this function
4177 * issues SW interrupt to recover from hung condition.
4178 **/
4179static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4180{
4181 struct i40e_ring *tx_ring = NULL;
4182 struct i40e_pf *pf;
4183 u32 head, val, tx_pending;
4184 int i;
4185
4186 pf = vsi->back;
4187
4188 /* now that we have an index, find the tx_ring struct */
4189 for (i = 0; i < vsi->num_queue_pairs; i++) {
4190 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4191 if (q_idx == vsi->tx_rings[i]->queue_index) {
4192 tx_ring = vsi->tx_rings[i];
4193 break;
4194 }
4195 }
4196 }
4197
4198 if (!tx_ring)
4199 return;
4200
4201 /* Read interrupt register */
4202 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4203 val = rd32(&pf->hw,
4204 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4205 tx_ring->vsi->base_vector - 1));
4206 else
4207 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4208
4209 head = i40e_get_head(tx_ring);
4210
4211 tx_pending = i40e_get_tx_pending(tx_ring);
4212
4213 /* Interrupts are disabled and TX pending is non-zero,
4214 * trigger the SW interrupt (don't wait). Worst case
4215 * there will be one extra interrupt which may result
4216 * into not cleaning any queues because queues are cleaned.
4217 */
4218 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4219 i40e_force_wb(vsi, tx_ring->q_vector);
4220}
4221
4222/**
4223 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4224 * @pf: pointer to PF struct
4225 *
4226 * LAN VSI has netdev and netdev has TX queues. This function is to check
4227 * each of those TX queues if they are hung, trigger recovery by issuing
4228 * SW interrupt.
4229 **/
4230static void i40e_detect_recover_hung(struct i40e_pf *pf)
4231{
4232 struct net_device *netdev;
4233 struct i40e_vsi *vsi;
4234 int i;
4235
4236 /* Only for LAN VSI */
4237 vsi = pf->vsi[pf->lan_vsi];
4238
4239 if (!vsi)
4240 return;
4241
4242 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4243 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4244 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4245 return;
4246
4247 /* Make sure type is MAIN VSI */
4248 if (vsi->type != I40E_VSI_MAIN)
4249 return;
4250
4251 netdev = vsi->netdev;
4252 if (!netdev)
4253 return;
4254
4255 /* Bail out if netif_carrier is not OK */
4256 if (!netif_carrier_ok(netdev))
4257 return;
4258
4259 /* Go thru' TX queues for netdev */
4260 for (i = 0; i < netdev->num_tx_queues; i++) {
4261 struct netdev_queue *q;
4262
4263 q = netdev_get_tx_queue(netdev, i);
4264 if (q)
4265 i40e_detect_recover_hung_queue(i, vsi);
4266 }
4267}
4268
63d7e5a4
NP		 4269/**
4270 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4271 * @pf: pointer to PF
63d7e5a4
NP		 4272 *
4273 * Get TC map for ISCSI PF type that will include iSCSI TC
4274 * and LAN TC.
4275 **/
4276static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4277{
4278 struct i40e_dcb_app_priority_table app;
4279 struct i40e_hw *hw = &pf->hw;
4280 u8 enabled_tc = 1; /* TC0 is always enabled */
4281 u8 tc, i;
4282 /* Get the iSCSI APP TLV */
4283 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4284
4285 for (i = 0; i < dcbcfg->numapps; i++) {
4286 app = dcbcfg->app[i];
4287 if (app.selector == I40E_APP_SEL_TCPIP &&
4288 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4289 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4290 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4291 break;
4292 }
4293 }
4294
4295 return enabled_tc;
4296}
4297
41c445ff
JB		 4298/**
4299 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4300 * @dcbcfg: the corresponding DCBx configuration structure
4301 *
4302 * Return the number of TCs from given DCBx configuration
4303 **/
4304static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4305{
078b5876
JB		 4306 u8 num_tc = 0;
4307 int i;
41c445ff
JB		 4308
4309 /* Scan the ETS Config Priority Table to find
4310 * traffic class enabled for a given priority
4311 * and use the traffic class index to get the
4312 * number of traffic classes enabled
4313 */
4314 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4315 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4316 num_tc = dcbcfg->etscfg.prioritytable[i];
4317 }
4318
4319 /* Traffic class index starts from zero so
4320 * increment to return the actual count
4321 */
078b5876 4322 return num_tc + 1;
41c445ff
JB		 4323}
4324
4325/**
4326 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4327 * @dcbcfg: the corresponding DCBx configuration structure
4328 *
4329 * Query the current DCB configuration and return the number of
4330 * traffic classes enabled from the given DCBX config
4331 **/
4332static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4333{
4334 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4335 u8 enabled_tc = 1;
4336 u8 i;
4337
4338 for (i = 0; i < num_tc; i++)
41a1d04b 4339 enabled_tc |= BIT(i);
41c445ff
JB		 4340
4341 return enabled_tc;
4342}
4343
4344/**
4345 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4346 * @pf: PF being queried
4347 *
4348 * Return number of traffic classes enabled for the given PF
4349 **/
4350static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4351{
4352 struct i40e_hw *hw = &pf->hw;
4353 u8 i, enabled_tc;
4354 u8 num_tc = 0;
4355 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4356
4357 /* If DCB is not enabled then always in single TC */
4358 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4359 return 1;
4360
63d7e5a4
NP		 4361 /* SFP mode will be enabled for all TCs on port */
4362 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4363 return i40e_dcb_get_num_tc(dcbcfg);
4364
41c445ff 4365 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4366 if (pf->hw.func_caps.iscsi)
4367 enabled_tc = i40e_get_iscsi_tc_map(pf);
4368 else
fc51de96 4369 return 1; /* Only TC0 */
41c445ff 4370
63d7e5a4
NP		 4371 /* At least have TC0 */
4372 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4374 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4375 num_tc++;
4376 }
4377 return num_tc;
41c445ff
JB		 4378}
4379
4380/**
4381 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4382 * @pf: PF being queried
4383 *
4384 * Return a bitmap for first enabled traffic class for this PF.
4385 **/
4386static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4387{
4388 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4389 u8 i = 0;
4390
4391 if (!enabled_tc)
4392 return 0x1; /* TC0 */
4393
4394 /* Find the first enabled TC */
4395 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4396 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4397 break;
4398 }
4399
41a1d04b 4400 return BIT(i);
41c445ff
JB		 4401}
4402
4403/**
4404 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4405 * @pf: PF being queried
4406 *
4407 * Return a bitmap for enabled traffic classes for this PF.
4408 **/
4409static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4410{
4411 /* If DCB is not enabled for this PF then just return default TC */
4412 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4413 return i40e_pf_get_default_tc(pf);
4414
41c445ff 4415 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4416 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4417 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4418
fc51de96 4419 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4420 if (pf->hw.func_caps.iscsi)
4421 return i40e_get_iscsi_tc_map(pf);
4422 else
fc51de96 4423 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4424}
4425
4426/**
4427 * i40e_vsi_get_bw_info - Query VSI BW Information
4428 * @vsi: the VSI being queried
4429 *
4430 * Returns 0 on success, negative value on failure
4431 **/
4432static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4433{
4434 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4435 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4436 struct i40e_pf *pf = vsi->back;
4437 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4438 i40e_status ret;
41c445ff 4439 u32 tc_bw_max;
41c445ff
JB		 4440 int i;
4441
4442 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4443 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4444 if (ret) {
41c445ff 4445 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4446 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4447 i40e_stat_str(&pf->hw, ret),
4448 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4449 return -EINVAL;
41c445ff
JB		 4450 }
4451
4452 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4453 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4454 NULL);
4455 if (ret) {
41c445ff 4456 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4457 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4458 i40e_stat_str(&pf->hw, ret),
4459 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4460 return -EINVAL;
41c445ff
JB		 4461 }
4462
4463 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4464 dev_info(&pf->pdev->dev,
4465 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4466 bw_config.tc_valid_bits,
4467 bw_ets_config.tc_valid_bits);
4468 /* Still continuing */
4469 }
4470
4471 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4472 vsi->bw_max_quanta = bw_config.max_bw;
4473 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4474 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4475 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4476 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4477 vsi->bw_ets_limit_credits[i] =
4478 le16_to_cpu(bw_ets_config.credits[i]);
4479 /* 3 bits out of 4 for each TC */
4480 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4481 }
078b5876 4482
dcae29be 4483 return 0;
41c445ff
JB		 4484}
4485
4486/**
4487 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4488 * @vsi: the VSI being configured
4489 * @enabled_tc: TC bitmap
4490 * @bw_credits: BW shared credits per TC
4491 *
4492 * Returns 0 on success, negative value on failure
4493 **/
dcae29be 4494static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4495 u8 *bw_share)
4496{
4497 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4498 i40e_status ret;
dcae29be 4499 int i;
41c445ff
JB		 4500
4501 bw_data.tc_valid_bits = enabled_tc;
4502 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4503 bw_data.tc_bw_credits[i] = bw_share[i];
4504
f1c7e72e
SN		 4505 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4506 NULL);
4507 if (ret) {
41c445ff 4508 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4509 "AQ command Config VSI BW allocation per TC failed = %d\n",
4510 vsi->back->hw.aq.asq_last_status);
dcae29be 4511 return -EINVAL;
41c445ff
JB		 4512 }
4513
4514 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4515 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4516
dcae29be 4517 return 0;
41c445ff
JB		 4518}
4519
4520/**
4521 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4522 * @vsi: the VSI being configured
4523 * @enabled_tc: TC map to be enabled
4524 *
4525 **/
4526static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4527{
4528 struct net_device *netdev = vsi->netdev;
4529 struct i40e_pf *pf = vsi->back;
4530 struct i40e_hw *hw = &pf->hw;
4531 u8 netdev_tc = 0;
4532 int i;
4533 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4534
4535 if (!netdev)
4536 return;
4537
4538 if (!enabled_tc) {
4539 netdev_reset_tc(netdev);
4540 return;
4541 }
4542
4543 /* Set up actual enabled TCs on the VSI */
4544 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4545 return;
4546
4547 /* set per TC queues for the VSI */
4548 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4549 /* Only set TC queues for enabled tcs
4550 *
4551 * e.g. For a VSI that has TC0 and TC3 enabled the
4552 * enabled_tc bitmap would be 0x00001001; the driver
4553 * will set the numtc for netdev as 2 that will be
4554 * referenced by the netdev layer as TC 0 and 1.
4555 */
41a1d04b 4556 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4557 netdev_set_tc_queue(netdev,
4558 vsi->tc_config.tc_info[i].netdev_tc,
4559 vsi->tc_config.tc_info[i].qcount,
4560 vsi->tc_config.tc_info[i].qoffset);
4561 }
4562
4563 /* Assign UP2TC map for the VSI */
4564 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4565 /* Get the actual TC# for the UP */
4566 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4567 /* Get the mapped netdev TC# for the UP */
4568 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4569 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4570 }
4571}
4572
4573/**
4574 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4575 * @vsi: the VSI being configured
4576 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4577 **/
4578static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4579 struct i40e_vsi_context *ctxt)
4580{
4581 /* copy just the sections touched not the entire info
4582 * since not all sections are valid as returned by
4583 * update vsi params
4584 */
4585 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4586 memcpy(&vsi->info.queue_mapping,
4587 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4588 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4589 sizeof(vsi->info.tc_mapping));
4590}
4591
4592/**
4593 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4594 * @vsi: VSI to be configured
4595 * @enabled_tc: TC bitmap
4596 *
4597 * This configures a particular VSI for TCs that are mapped to the
4598 * given TC bitmap. It uses default bandwidth share for TCs across
4599 * VSIs to configure TC for a particular VSI.
4600 *
4601 * NOTE:
4602 * It is expected that the VSI queues have been quisced before calling
4603 * this function.
4604 **/
4605static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4606{
4607 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4608 struct i40e_vsi_context ctxt;
4609 int ret = 0;
4610 int i;
4611
4612 /* Check if enabled_tc is same as existing or new TCs */
4613 if (vsi->tc_config.enabled_tc == enabled_tc)
4614 return ret;
4615
4616 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4617 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4618 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4619 bw_share[i] = 1;
4620 }
4621
4622 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4623 if (ret) {
4624 dev_info(&vsi->back->pdev->dev,
4625 "Failed configuring TC map %d for VSI %d\n",
4626 enabled_tc, vsi->seid);
4627 goto out;
4628 }
4629
4630 /* Update Queue Pairs Mapping for currently enabled UPs */
4631 ctxt.seid = vsi->seid;
4632 ctxt.pf_num = vsi->back->hw.pf_id;
4633 ctxt.vf_num = 0;
4634 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4635 ctxt.info = vsi->info;
41c445ff
JB		 4636 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4637
4638 /* Update the VSI after updating the VSI queue-mapping information */
4639 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4640 if (ret) {
4641 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4642 "Update vsi tc config failed, err %s aq_err %s\n",
4643 i40e_stat_str(&vsi->back->hw, ret),
4644 i40e_aq_str(&vsi->back->hw,
4645 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4646 goto out;
4647 }
4648 /* update the local VSI info with updated queue map */
4649 i40e_vsi_update_queue_map(vsi, &ctxt);
4650 vsi->info.valid_sections = 0;
4651
4652 /* Update current VSI BW information */
4653 ret = i40e_vsi_get_bw_info(vsi);
4654 if (ret) {
4655 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4656 "Failed updating vsi bw info, err %s aq_err %s\n",
4657 i40e_stat_str(&vsi->back->hw, ret),
4658 i40e_aq_str(&vsi->back->hw,
4659 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4660 goto out;
4661 }
4662
4663 /* Update the netdev TC setup */
4664 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4665out:
4666 return ret;
4667}
4668
4e3b35b0
NP		 4669/**
4670 * i40e_veb_config_tc - Configure TCs for given VEB
4671 * @veb: given VEB
4672 * @enabled_tc: TC bitmap
4673 *
4674 * Configures given TC bitmap for VEB (switching) element
4675 **/
4676int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4677{
4678 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4679 struct i40e_pf *pf = veb->pf;
4680 int ret = 0;
4681 int i;
4682
4683 /* No TCs or already enabled TCs just return */
4684 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4685 return ret;
4686
4687 bw_data.tc_valid_bits = enabled_tc;
4688 /* bw_data.absolute_credits is not set (relative) */
4689
4690 /* Enable ETS TCs with equal BW Share for now */
4691 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4692 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4693 bw_data.tc_bw_share_credits[i] = 1;
4694 }
4695
4696 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4697 &bw_data, NULL);
4698 if (ret) {
4699 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4700 "VEB bw config failed, err %s aq_err %s\n",
4701 i40e_stat_str(&pf->hw, ret),
4702 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4703 goto out;
4704 }
4705
4706 /* Update the BW information */
4707 ret = i40e_veb_get_bw_info(veb);
4708 if (ret) {
4709 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4710 "Failed getting veb bw config, err %s aq_err %s\n",
4711 i40e_stat_str(&pf->hw, ret),
4712 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4713 }
4714
4715out:
4716 return ret;
4717}
4718
4719#ifdef CONFIG_I40E_DCB
4720/**
4721 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4722 * @pf: PF struct
4723 *
4724 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4725 * the caller would've quiesce all the VSIs before calling
4726 * this function
4727 **/
4728static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4729{
4730 u8 tc_map = 0;
4731 int ret;
4732 u8 v;
4733
4734 /* Enable the TCs available on PF to all VEBs */
4735 tc_map = i40e_pf_get_tc_map(pf);
4736 for (v = 0; v < I40E_MAX_VEB; v++) {
4737 if (!pf->veb[v])
4738 continue;
4739 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4740 if (ret) {
4741 dev_info(&pf->pdev->dev,
4742 "Failed configuring TC for VEB seid=%d\n",
4743 pf->veb[v]->seid);
4744 /* Will try to configure as many components */
4745 }
4746 }
4747
4748 /* Update each VSI */
505682cd 4749 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4750 if (!pf->vsi[v])
4751 continue;
4752
4753 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4754#ifdef I40E_FCOE
4755 * - For FCoE VSI only enable the TC configured
4756 * as per the APP TLV
4757#endif
4e3b35b0
NP		 4758 * - For all others keep them at TC0 for now
4759 */
4760 if (v == pf->lan_vsi)
4761 tc_map = i40e_pf_get_tc_map(pf);
4762 else
4763 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4764#ifdef I40E_FCOE
4765 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4766 tc_map = i40e_get_fcoe_tc_map(pf);
4767#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4768
4769 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4770 if (ret) {
4771 dev_info(&pf->pdev->dev,
4772 "Failed configuring TC for VSI seid=%d\n",
4773 pf->vsi[v]->seid);
4774 /* Will try to configure as many components */
4775 } else {
0672a091
NP		 4776 /* Re-configure VSI vectors based on updated TC map */
4777 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4778 if (pf->vsi[v]->netdev)
4779 i40e_dcbnl_set_all(pf->vsi[v]);
4780 }
4781 }
4782}
4783
2fd75f31
NP		 4784/**
4785 * i40e_resume_port_tx - Resume port Tx
4786 * @pf: PF struct
4787 *
4788 * Resume a port's Tx and issue a PF reset in case of failure to
4789 * resume.
4790 **/
4791static int i40e_resume_port_tx(struct i40e_pf *pf)
4792{
4793 struct i40e_hw *hw = &pf->hw;
4794 int ret;
4795
4796 ret = i40e_aq_resume_port_tx(hw, NULL);
4797 if (ret) {
4798 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4799 "Resume Port Tx failed, err %s aq_err %s\n",
4800 i40e_stat_str(&pf->hw, ret),
4801 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4802 /* Schedule PF reset to recover */
4803 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4804 i40e_service_event_schedule(pf);
4805 }
4806
4807 return ret;
4808}
4809
4e3b35b0
NP		 4810/**
4811 * i40e_init_pf_dcb - Initialize DCB configuration
4812 * @pf: PF being configured
4813 *
4814 * Query the current DCB configuration and cache it
4815 * in the hardware structure
4816 **/
4817static int i40e_init_pf_dcb(struct i40e_pf *pf)
4818{
4819 struct i40e_hw *hw = &pf->hw;
4820 int err = 0;
4821
025b4a54
ASJ		 4822 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4823 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4824 (pf->hw.aq.fw_maj_ver < 4))
4825 goto out;
4826
4e3b35b0
NP		 4827 /* Get the initial DCB configuration */
4828 err = i40e_init_dcb(hw);
4829 if (!err) {
4830 /* Device/Function is not DCBX capable */
4831 if ((!hw->func_caps.dcb) ||
4832 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4833 dev_info(&pf->pdev->dev,
4834 "DCBX offload is not supported or is disabled for this PF.\n");
4835
4836 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4837 goto out;
4838
4839 } else {
4840 /* When status is not DISABLED then DCBX in FW */
4841 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4842 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4843
4844 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4845 /* Enable DCB tagging only when more than one TC */
4846 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4847 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4848 dev_dbg(&pf->pdev->dev,
4849 "DCBX offload is supported for this PF.\n");
4e3b35b0 4850 }
014269ff 4851 } else {
aebfc816 4852 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4853 "Query for DCB configuration failed, err %s aq_err %s\n",
4854 i40e_stat_str(&pf->hw, err),
4855 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4856 }
4857
4858out:
4859 return err;
4860}
4861#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4862#define SPEED_SIZE 14
4863#define FC_SIZE 8
4864/**
4865 * i40e_print_link_message - print link up or down
4866 * @vsi: the VSI for which link needs a message
4867 */
4868static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4869{
4870 char speed[SPEED_SIZE] = "Unknown";
4871 char fc[FC_SIZE] = "RX/TX";
4872
4873 if (!isup) {
4874 netdev_info(vsi->netdev, "NIC Link is Down\n");
4875 return;
4876 }
4877
148c2d80
GR		 4878 /* Warn user if link speed on NPAR enabled partition is not at
4879 * least 10GB
4880 */
4881 if (vsi->back->hw.func_caps.npar_enable &&
4882 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4883 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4884 netdev_warn(vsi->netdev,
4885 "The partition detected link speed that is less than 10Gbps\n");
4886
cf05ed08
JB		 4887 switch (vsi->back->hw.phy.link_info.link_speed) {
4888 case I40E_LINK_SPEED_40GB:
35a7d804 4889 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08 4890 break;
ae24b409
JB		 4891 case I40E_LINK_SPEED_20GB:
4892 strncpy(speed, "20 Gbps", SPEED_SIZE);
4893 break;
cf05ed08 4894 case I40E_LINK_SPEED_10GB:
35a7d804 4895 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4896 break;
4897 case I40E_LINK_SPEED_1GB:
35a7d804 4898 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4899 break;
5960d33f
MW		 4900 case I40E_LINK_SPEED_100MB:
4901 strncpy(speed, "100 Mbps", SPEED_SIZE);
4902 break;
cf05ed08
JB		 4903 default:
4904 break;
4905 }
4906
4907 switch (vsi->back->hw.fc.current_mode) {
4908 case I40E_FC_FULL:
35a7d804 4909 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4910 break;
4911 case I40E_FC_TX_PAUSE:
35a7d804 4912 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4913 break;
4914 case I40E_FC_RX_PAUSE:
35a7d804 4915 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4916 break;
4917 default:
35a7d804 4918 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4919 break;
4920 }
4921
4922 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4923 speed, fc);
4924}
4e3b35b0 4925
41c445ff
JB		 4926/**
4927 * i40e_up_complete - Finish the last steps of bringing up a connection
4928 * @vsi: the VSI being configured
4929 **/
4930static int i40e_up_complete(struct i40e_vsi *vsi)
4931{
4932 struct i40e_pf *pf = vsi->back;
4933 int err;
4934
4935 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4936 i40e_vsi_configure_msix(vsi);
4937 else
4938 i40e_configure_msi_and_legacy(vsi);
4939
4940 /* start rings */
4941 err = i40e_vsi_control_rings(vsi, true);
4942 if (err)
4943 return err;
4944
4945 clear_bit(__I40E_DOWN, &vsi->state);
4946 i40e_napi_enable_all(vsi);
4947 i40e_vsi_enable_irq(vsi);
4948
4949 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4950 (vsi->netdev)) {
cf05ed08 4951 i40e_print_link_message(vsi, true);
41c445ff
JB		 4952 netif_tx_start_all_queues(vsi->netdev);
4953 netif_carrier_on(vsi->netdev);
6d779b41 4954 } else if (vsi->netdev) {
cf05ed08 4955 i40e_print_link_message(vsi, false);
7b592f61
CW		 4956 /* need to check for qualified module here*/
4957 if ((pf->hw.phy.link_info.link_info &
4958 I40E_AQ_MEDIA_AVAILABLE) &&
4959 (!(pf->hw.phy.link_info.an_info &
4960 I40E_AQ_QUALIFIED_MODULE)))
4961 netdev_err(vsi->netdev,
4962 "the driver failed to link because an unqualified module was detected.");
41c445ff 4963 }
ca64fa4e
ASJ		 4964
4965 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4966 if (vsi->type == I40E_VSI_FDIR) {
4967 /* reset fd counters */
4968 pf->fd_add_err = pf->fd_atr_cnt = 0;
4969 if (pf->fd_tcp_rule > 0) {
4970 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4971 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4972 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4973 pf->fd_tcp_rule = 0;
4974 }
ca64fa4e 4975 i40e_fdir_filter_restore(vsi);
1e1be8f6 4976 }
41c445ff
JB		 4977 i40e_service_event_schedule(pf);
4978
4979 return 0;
4980}
4981
4982/**
4983 * i40e_vsi_reinit_locked - Reset the VSI
4984 * @vsi: the VSI being configured
4985 *
4986 * Rebuild the ring structs after some configuration
4987 * has changed, e.g. MTU size.
4988 **/
4989static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4990{
4991 struct i40e_pf *pf = vsi->back;
4992
4993 WARN_ON(in_interrupt());
4994 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4995 usleep_range(1000, 2000);
4996 i40e_down(vsi);
4997
4998 /* Give a VF some time to respond to the reset. The
4999 * two second wait is based upon the watchdog cycle in
5000 * the VF driver.
5001 */
5002 if (vsi->type == I40E_VSI_SRIOV)
5003 msleep(2000);
5004 i40e_up(vsi);
5005 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5006}
5007
5008/**
5009 * i40e_up - Bring the connection back up after being down
5010 * @vsi: the VSI being configured
5011 **/
5012int i40e_up(struct i40e_vsi *vsi)
5013{
5014 int err;
5015
5016 err = i40e_vsi_configure(vsi);
5017 if (!err)
5018 err = i40e_up_complete(vsi);
5019
5020 return err;
5021}
5022
5023/**
5024 * i40e_down - Shutdown the connection processing
5025 * @vsi: the VSI being stopped
5026 **/
5027void i40e_down(struct i40e_vsi *vsi)
5028{
5029 int i;
5030
5031 /* It is assumed that the caller of this function
5032 * sets the vsi->state __I40E_DOWN bit.
5033 */
5034 if (vsi->netdev) {
5035 netif_carrier_off(vsi->netdev);
5036 netif_tx_disable(vsi->netdev);
5037 }
5038 i40e_vsi_disable_irq(vsi);
5039 i40e_vsi_control_rings(vsi, false);
5040 i40e_napi_disable_all(vsi);
5041
5042 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5043 i40e_clean_tx_ring(vsi->tx_rings[i]);
5044 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5045 }
5046}
5047
5048/**
5049 * i40e_setup_tc - configure multiple traffic classes
5050 * @netdev: net device to configure
5051 * @tc: number of traffic classes to enable
5052 **/
38e00438
VD		 5053#ifdef I40E_FCOE
5054int i40e_setup_tc(struct net_device *netdev, u8 tc)
5055#else
41c445ff 5056static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5057#endif
41c445ff
JB		 5058{
5059 struct i40e_netdev_priv *np = netdev_priv(netdev);
5060 struct i40e_vsi *vsi = np->vsi;
5061 struct i40e_pf *pf = vsi->back;
5062 u8 enabled_tc = 0;
5063 int ret = -EINVAL;
5064 int i;
5065
5066 /* Check if DCB enabled to continue */
5067 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5068 netdev_info(netdev, "DCB is not enabled for adapter\n");
5069 goto exit;
5070 }
5071
5072 /* Check if MFP enabled */
5073 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5074 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5075 goto exit;
5076 }
5077
5078 /* Check whether tc count is within enabled limit */
5079 if (tc > i40e_pf_get_num_tc(pf)) {
5080 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5081 goto exit;
5082 }
5083
5084 /* Generate TC map for number of tc requested */
5085 for (i = 0; i < tc; i++)
41a1d04b 5086 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5087
5088 /* Requesting same TC configuration as already enabled */
5089 if (enabled_tc == vsi->tc_config.enabled_tc)
5090 return 0;
5091
5092 /* Quiesce VSI queues */
5093 i40e_quiesce_vsi(vsi);
5094
5095 /* Configure VSI for enabled TCs */
5096 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5097 if (ret) {
5098 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5099 vsi->seid);
5100 goto exit;
5101 }
5102
5103 /* Unquiesce VSI */
5104 i40e_unquiesce_vsi(vsi);
5105
5106exit:
5107 return ret;
5108}
5109
5110/**
5111 * i40e_open - Called when a network interface is made active
5112 * @netdev: network interface device structure
5113 *
5114 * The open entry point is called when a network interface is made
5115 * active by the system (IFF_UP). At this point all resources needed
5116 * for transmit and receive operations are allocated, the interrupt
5117 * handler is registered with the OS, the netdev watchdog subtask is
5118 * enabled, and the stack is notified that the interface is ready.
5119 *
5120 * Returns 0 on success, negative value on failure
5121 **/
38e00438 5122int i40e_open(struct net_device *netdev)
41c445ff
JB		 5123{
5124 struct i40e_netdev_priv *np = netdev_priv(netdev);
5125 struct i40e_vsi *vsi = np->vsi;
5126 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5127 int err;
5128
4eb3f768
SN		 5129 /* disallow open during test or if eeprom is broken */
5130 if (test_bit(__I40E_TESTING, &pf->state) ||
5131 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5132 return -EBUSY;
5133
5134 netif_carrier_off(netdev);
5135
6c167f58
EK		 5136 err = i40e_vsi_open(vsi);
5137 if (err)
5138 return err;
5139
059dab69
JB		 5140 /* configure global TSO hardware offload settings */
5141 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5142 TCP_FLAG_FIN) >> 16);
5143 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5144 TCP_FLAG_FIN |
5145 TCP_FLAG_CWR) >> 16);
5146 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5147
6c167f58
EK		 5148#ifdef CONFIG_I40E_VXLAN
5149 vxlan_get_rx_port(netdev);
5150#endif
5151
5152 return 0;
5153}
5154
5155/**
5156 * i40e_vsi_open -
5157 * @vsi: the VSI to open
5158 *
5159 * Finish initialization of the VSI.
5160 *
5161 * Returns 0 on success, negative value on failure
5162 **/
5163int i40e_vsi_open(struct i40e_vsi *vsi)
5164{
5165 struct i40e_pf *pf = vsi->back;
b294ac70 5166 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5167 int err;
5168
41c445ff
JB		 5169 /* allocate descriptors */
5170 err = i40e_vsi_setup_tx_resources(vsi);
5171 if (err)
5172 goto err_setup_tx;
5173 err = i40e_vsi_setup_rx_resources(vsi);
5174 if (err)
5175 goto err_setup_rx;
5176
5177 err = i40e_vsi_configure(vsi);
5178 if (err)
5179 goto err_setup_rx;
5180
c22e3c6c
SN		 5181 if (vsi->netdev) {
5182 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5183 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5184 err = i40e_vsi_request_irq(vsi, int_name);
5185 if (err)
5186 goto err_setup_rx;
41c445ff 5187
c22e3c6c
SN		 5188 /* Notify the stack of the actual queue counts. */
5189 err = netif_set_real_num_tx_queues(vsi->netdev,
5190 vsi->num_queue_pairs);
5191 if (err)
5192 goto err_set_queues;
25946ddb 5193
c22e3c6c
SN		 5194 err = netif_set_real_num_rx_queues(vsi->netdev,
5195 vsi->num_queue_pairs);
5196 if (err)
5197 goto err_set_queues;
8a9eb7d3
SN		 5198
5199 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5200 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5201 dev_driver_string(&pf->pdev->dev),
5202 dev_name(&pf->pdev->dev));
8a9eb7d3 5203 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5204
c22e3c6c 5205 } else {
ce9ccb17 5206 err = -EINVAL;
6c167f58
EK		 5207 goto err_setup_rx;
5208 }
25946ddb 5209
41c445ff
JB		 5210 err = i40e_up_complete(vsi);
5211 if (err)
5212 goto err_up_complete;
5213
41c445ff
JB		 5214 return 0;
5215
5216err_up_complete:
5217 i40e_down(vsi);
25946ddb 5218err_set_queues:
41c445ff
JB		 5219 i40e_vsi_free_irq(vsi);
5220err_setup_rx:
5221 i40e_vsi_free_rx_resources(vsi);
5222err_setup_tx:
5223 i40e_vsi_free_tx_resources(vsi);
5224 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5225 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5226
5227 return err;
5228}
5229
17a73f6b
JG		 5230/**
5231 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5232 * @pf: Pointer to PF
17a73f6b
JG		 5233 *
5234 * This function destroys the hlist where all the Flow Director
5235 * filters were saved.
5236 **/
5237static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5238{
5239 struct i40e_fdir_filter *filter;
5240 struct hlist_node *node2;
5241
5242 hlist_for_each_entry_safe(filter, node2,
5243 &pf->fdir_filter_list, fdir_node) {
5244 hlist_del(&filter->fdir_node);
5245 kfree(filter);
5246 }
5247 pf->fdir_pf_active_filters = 0;
5248}
5249
41c445ff
JB		 5250/**
5251 * i40e_close - Disables a network interface
5252 * @netdev: network interface device structure
5253 *
5254 * The close entry point is called when an interface is de-activated
5255 * by the OS. The hardware is still under the driver's control, but
5256 * this netdev interface is disabled.
5257 *
5258 * Returns 0, this is not allowed to fail
5259 **/
38e00438
VD		 5260#ifdef I40E_FCOE
5261int i40e_close(struct net_device *netdev)
5262#else
41c445ff 5263static int i40e_close(struct net_device *netdev)
38e00438 5264#endif
41c445ff
JB		 5265{
5266 struct i40e_netdev_priv *np = netdev_priv(netdev);
5267 struct i40e_vsi *vsi = np->vsi;
5268
90ef8d47 5269 i40e_vsi_close(vsi);
41c445ff
JB		 5270
5271 return 0;
5272}
5273
5274/**
5275 * i40e_do_reset - Start a PF or Core Reset sequence
5276 * @pf: board private structure
5277 * @reset_flags: which reset is requested
5278 *
5279 * The essential difference in resets is that the PF Reset
5280 * doesn't clear the packet buffers, doesn't reset the PE
5281 * firmware, and doesn't bother the other PFs on the chip.
5282 **/
5283void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5284{
5285 u32 val;
5286
5287 WARN_ON(in_interrupt());
5288
263fc48f
MW		 5289 if (i40e_check_asq_alive(&pf->hw))
5290 i40e_vc_notify_reset(pf);
5291
41c445ff 5292 /* do the biggest reset indicated */
41a1d04b 5293 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5294
5295 /* Request a Global Reset
5296 *
5297 * This will start the chip's countdown to the actual full
5298 * chip reset event, and a warning interrupt to be sent
5299 * to all PFs, including the requestor. Our handler
5300 * for the warning interrupt will deal with the shutdown
5301 * and recovery of the switch setup.
5302 */
69bfb110 5303 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5304 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5305 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5306 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5307
41a1d04b 5308 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5309
5310 /* Request a Core Reset
5311 *
5312 * Same as Global Reset, except does *not* include the MAC/PHY
5313 */
69bfb110 5314 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5315 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5316 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5317 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5318 i40e_flush(&pf->hw);
5319
41a1d04b 5320 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5321
5322 /* Request a PF Reset
5323 *
5324 * Resets only the PF-specific registers
5325 *
5326 * This goes directly to the tear-down and rebuild of
5327 * the switch, since we need to do all the recovery as
5328 * for the Core Reset.
5329 */
69bfb110 5330 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5331 i40e_handle_reset_warning(pf);
5332
41a1d04b 5333 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5334 int v;
5335
5336 /* Find the VSI(s) that requested a re-init */
5337 dev_info(&pf->pdev->dev,
5338 "VSI reinit requested\n");
505682cd 5339 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5340 struct i40e_vsi *vsi = pf->vsi[v];
5341 if (vsi != NULL &&
5342 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5343 i40e_vsi_reinit_locked(pf->vsi[v]);
5344 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5345 }
5346 }
5347
b5d06f05
NP		 5348 /* no further action needed, so return now */
5349 return;
41a1d04b 5350 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5351 int v;
5352
5353 /* Find the VSI(s) that needs to be brought down */
5354 dev_info(&pf->pdev->dev, "VSI down requested\n");
5355 for (v = 0; v < pf->num_alloc_vsi; v++) {
5356 struct i40e_vsi *vsi = pf->vsi[v];
5357 if (vsi != NULL &&
5358 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5359 set_bit(__I40E_DOWN, &vsi->state);
5360 i40e_down(vsi);
5361 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5362 }
5363 }
5364
41c445ff
JB		 5365 /* no further action needed, so return now */
5366 return;
5367 } else {
5368 dev_info(&pf->pdev->dev,
5369 "bad reset request 0x%08x\n", reset_flags);
5370 return;
5371 }
5372}
5373
4e3b35b0
NP		 5374#ifdef CONFIG_I40E_DCB
5375/**
5376 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5377 * @pf: board private structure
5378 * @old_cfg: current DCB config
5379 * @new_cfg: new DCB config
5380 **/
5381bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5382 struct i40e_dcbx_config *old_cfg,
5383 struct i40e_dcbx_config *new_cfg)
5384{
5385 bool need_reconfig = false;
5386
5387 /* Check if ETS configuration has changed */
5388 if (memcmp(&new_cfg->etscfg,
5389 &old_cfg->etscfg,
5390 sizeof(new_cfg->etscfg))) {
5391 /* If Priority Table has changed reconfig is needed */
5392 if (memcmp(&new_cfg->etscfg.prioritytable,
5393 &old_cfg->etscfg.prioritytable,
5394 sizeof(new_cfg->etscfg.prioritytable))) {
5395 need_reconfig = true;
69bfb110 5396 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5397 }
5398
5399 if (memcmp(&new_cfg->etscfg.tcbwtable,
5400 &old_cfg->etscfg.tcbwtable,
5401 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5402 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5403
5404 if (memcmp(&new_cfg->etscfg.tsatable,
5405 &old_cfg->etscfg.tsatable,
5406 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5407 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5408 }
5409
5410 /* Check if PFC configuration has changed */
5411 if (memcmp(&new_cfg->pfc,
5412 &old_cfg->pfc,
5413 sizeof(new_cfg->pfc))) {
5414 need_reconfig = true;
69bfb110 5415 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5416 }
5417
5418 /* Check if APP Table has changed */
5419 if (memcmp(&new_cfg->app,
5420 &old_cfg->app,
3d9667a9 5421 sizeof(new_cfg->app))) {
4e3b35b0 5422 need_reconfig = true;
69bfb110 5423 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5424 }
4e3b35b0 5425
9fa61dd2
NP		 5426 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5427 need_reconfig);
4e3b35b0
NP		 5428 return need_reconfig;
5429}
5430
5431/**
5432 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5433 * @pf: board private structure
5434 * @e: event info posted on ARQ
5435 **/
5436static int i40e_handle_lldp_event(struct i40e_pf *pf,
5437 struct i40e_arq_event_info *e)
5438{
5439 struct i40e_aqc_lldp_get_mib *mib =
5440 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5441 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5442 struct i40e_dcbx_config tmp_dcbx_cfg;
5443 bool need_reconfig = false;
5444 int ret = 0;
5445 u8 type;
5446
4d9b6043
NP		 5447 /* Not DCB capable or capability disabled */
5448 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5449 return ret;
5450
4e3b35b0
NP		 5451 /* Ignore if event is not for Nearest Bridge */
5452 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5453 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5454 dev_dbg(&pf->pdev->dev,
5455 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5456 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5457 return ret;
5458
5459 /* Check MIB Type and return if event for Remote MIB update */
5460 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5461 dev_dbg(&pf->pdev->dev,
5462 "%s: LLDP event mib type %s\n", __func__,
5463 type ? "remote" : "local");
4e3b35b0
NP		 5464 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5465 /* Update the remote cached instance and return */
5466 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5467 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5468 &hw->remote_dcbx_config);
5469 goto exit;
5470 }
5471
9fa61dd2 5472 /* Store the old configuration */
1a2f6248 5473 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5474
750fcbcf
NP		 5475 /* Reset the old DCBx configuration data */
5476 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5477 /* Get updated DCBX data from firmware */
5478 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5479 if (ret) {
f1c7e72e
SN		 5480 dev_info(&pf->pdev->dev,
5481 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5482 i40e_stat_str(&pf->hw, ret),
5483 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5484 goto exit;
5485 }
5486
5487 /* No change detected in DCBX configs */
750fcbcf
NP		 5488 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5489 sizeof(tmp_dcbx_cfg))) {
69bfb110 5490 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5491 goto exit;
5492 }
5493
750fcbcf
NP		 5494 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5495 &hw->local_dcbx_config);
4e3b35b0 5496
750fcbcf 5497 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5498
5499 if (!need_reconfig)
5500 goto exit;
5501
4d9b6043 5502 /* Enable DCB tagging only when more than one TC */
750fcbcf 5503 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5504 pf->flags |= I40E_FLAG_DCB_ENABLED;
5505 else
5506 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5507
69129dc3 5508 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5509 /* Reconfiguration needed quiesce all VSIs */
5510 i40e_pf_quiesce_all_vsi(pf);
5511
5512 /* Changes in configuration update VEB/VSI */
5513 i40e_dcb_reconfigure(pf);
5514
2fd75f31
NP		 5515 ret = i40e_resume_port_tx(pf);
5516
69129dc3 5517 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5518 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5519 if (ret)
5520 goto exit;
5521
5522 /* Wait for the PF's Tx queues to be disabled */
5523 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5524 if (ret) {
5525 /* Schedule PF reset to recover */
5526 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5527 i40e_service_event_schedule(pf);
5528 } else {
2fd75f31 5529 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5530 }
5531
4e3b35b0
NP		 5532exit:
5533 return ret;
5534}
5535#endif /* CONFIG_I40E_DCB */
5536
23326186
ASJ		 5537/**
5538 * i40e_do_reset_safe - Protected reset path for userland calls.
5539 * @pf: board private structure
5540 * @reset_flags: which reset is requested
5541 *
5542 **/
5543void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5544{
5545 rtnl_lock();
5546 i40e_do_reset(pf, reset_flags);
5547 rtnl_unlock();
5548}
5549
41c445ff
JB		 5550/**
5551 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5552 * @pf: board private structure
5553 * @e: event info posted on ARQ
5554 *
5555 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5556 * and VF queues
5557 **/
5558static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5559 struct i40e_arq_event_info *e)
5560{
5561 struct i40e_aqc_lan_overflow *data =
5562 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5563 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5564 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5565 struct i40e_hw *hw = &pf->hw;
5566 struct i40e_vf *vf;
5567 u16 vf_id;
5568
69bfb110
JB		 5569 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5570 queue, qtx_ctl);
41c445ff
JB		 5571
5572 /* Queue belongs to VF, find the VF and issue VF reset */
5573 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5574 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5575 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5576 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5577 vf_id -= hw->func_caps.vf_base_id;
5578 vf = &pf->vf[vf_id];
5579 i40e_vc_notify_vf_reset(vf);
5580 /* Allow VF to process pending reset notification */
5581 msleep(20);
5582 i40e_reset_vf(vf, false);
5583 }
5584}
5585
5586/**
5587 * i40e_service_event_complete - Finish up the service event
5588 * @pf: board private structure
5589 **/
5590static void i40e_service_event_complete(struct i40e_pf *pf)
5591{
5592 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5593
5594 /* flush memory to make sure state is correct before next watchog */
4e857c58 5595 smp_mb__before_atomic();
41c445ff
JB		 5596 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5597}
5598
55a5e60b 5599/**
12957388
ASJ		 5600 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5601 * @pf: board private structure
5602 **/
04294e38 5603u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5604{
04294e38 5605 u32 val, fcnt_prog;
12957388
ASJ		 5606
5607 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5608 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5609 return fcnt_prog;
5610}
5611
5612/**
04294e38 5613 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5614 * @pf: board private structure
5615 **/
04294e38 5616u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5617{
04294e38
ASJ		 5618 u32 val, fcnt_prog;
5619
55a5e60b
ASJ		 5620 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5621 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5622 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5623 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5624 return fcnt_prog;
5625}
1e1be8f6 5626
04294e38
ASJ		 5627/**
5628 * i40e_get_global_fd_count - Get total FD filters programmed on device
5629 * @pf: board private structure
5630 **/
5631u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5632{
5633 u32 val, fcnt_prog;
5634
5635 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5636 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5637 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5638 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5639 return fcnt_prog;
5640}
5641
55a5e60b
ASJ		 5642/**
5643 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5644 * @pf: board private structure
5645 **/
5646void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5647{
5648 u32 fcnt_prog, fcnt_avail;
5649
1e1be8f6
ASJ		 5650 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5651 return;
5652
55a5e60b
ASJ		 5653 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5654 * to re-enable
5655 */
04294e38 5656 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5657 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5658 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5659 (pf->fd_add_err == 0) ||
5660 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5661 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5662 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5663 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5664 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5665 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5666 }
5667 }
5668 /* Wait for some more space to be available to turn on ATR */
5669 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5670 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5671 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5672 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5673 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5674 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5675 }
5676 }
5677}
5678
1e1be8f6 5679#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5680#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5681/**
5682 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5683 * @pf: board private structure
5684 **/
5685static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5686{
04294e38 5687 unsigned long min_flush_time;
1e1be8f6 5688 int flush_wait_retry = 50;
04294e38
ASJ		 5689 bool disable_atr = false;
5690 int fd_room;
1e1be8f6
ASJ		 5691 int reg;
5692
1790ed0c
AA		 5693 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5694 return;
5695
1e1be8f6
ASJ		 5696 if (time_after(jiffies, pf->fd_flush_timestamp +
5697 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5698 /* If the flush is happening too quick and we have mostly
5699 * SB rules we should not re-enable ATR for some time.
5700 */
5701 min_flush_time = pf->fd_flush_timestamp
5702 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5703 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5704
5705 if (!(time_after(jiffies, min_flush_time)) &&
5706 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
2e4875e3
ASJ		 5707 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5708 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
04294e38
ASJ		 5709 disable_atr = true;
5710 }
5711
1e1be8f6 5712 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5713 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5714 /* flush all filters */
5715 wr32(&pf->hw, I40E_PFQF_CTL_1,
5716 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5717 i40e_flush(&pf->hw);
60793f4a 5718 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5719 pf->fd_add_err = 0;
5720 do {
5721 /* Check FD flush status every 5-6msec */
5722 usleep_range(5000, 6000);
5723 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5724 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5725 break;
5726 } while (flush_wait_retry--);
5727 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5728 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5729 } else {
5730 /* replay sideband filters */
5731 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5732 if (!disable_atr)
5733 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6 5734 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
2e4875e3
ASJ		 5735 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5736 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5737 }
5738 }
5739}
5740
5741/**
5742 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5743 * @pf: board private structure
5744 **/
04294e38 5745u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5746{
5747 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5748}
5749
5750/* We can see up to 256 filter programming desc in transit if the filters are
5751 * being applied really fast; before we see the first
5752 * filter miss error on Rx queue 0. Accumulating enough error messages before
5753 * reacting will make sure we don't cause flush too often.
5754 */
5755#define I40E_MAX_FD_PROGRAM_ERROR 256
5756
41c445ff
JB		 5757/**
5758 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5759 * @pf: board private structure
5760 **/
5761static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5762{
41c445ff 5763
41c445ff
JB		 5764 /* if interface is down do nothing */
5765 if (test_bit(__I40E_DOWN, &pf->state))
5766 return;
1e1be8f6 5767
1790ed0c
AA		 5768 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5769 return;
5770
04294e38 5771 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5772 i40e_fdir_flush_and_replay(pf);
5773
55a5e60b
ASJ		 5774 i40e_fdir_check_and_reenable(pf);
5775
41c445ff
JB		 5776}
5777
5778/**
5779 * i40e_vsi_link_event - notify VSI of a link event
5780 * @vsi: vsi to be notified
5781 * @link_up: link up or down
5782 **/
5783static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5784{
32b5b811 5785 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5786 return;
5787
5788 switch (vsi->type) {
5789 case I40E_VSI_MAIN:
38e00438
VD		 5790#ifdef I40E_FCOE
5791 case I40E_VSI_FCOE:
5792#endif
41c445ff
JB		 5793 if (!vsi->netdev || !vsi->netdev_registered)
5794 break;
5795
5796 if (link_up) {
5797 netif_carrier_on(vsi->netdev);
5798 netif_tx_wake_all_queues(vsi->netdev);
5799 } else {
5800 netif_carrier_off(vsi->netdev);
5801 netif_tx_stop_all_queues(vsi->netdev);
5802 }
5803 break;
5804
5805 case I40E_VSI_SRIOV:
41c445ff
JB		 5806 case I40E_VSI_VMDQ2:
5807 case I40E_VSI_CTRL:
5808 case I40E_VSI_MIRROR:
5809 default:
5810 /* there is no notification for other VSIs */
5811 break;
5812 }
5813}
5814
5815/**
5816 * i40e_veb_link_event - notify elements on the veb of a link event
5817 * @veb: veb to be notified
5818 * @link_up: link up or down
5819 **/
5820static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5821{
5822 struct i40e_pf *pf;
5823 int i;
5824
5825 if (!veb || !veb->pf)
5826 return;
5827 pf = veb->pf;
5828
5829 /* depth first... */
5830 for (i = 0; i < I40E_MAX_VEB; i++)
5831 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5832 i40e_veb_link_event(pf->veb[i], link_up);
5833
5834 /* ... now the local VSIs */
505682cd 5835 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5836 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5837 i40e_vsi_link_event(pf->vsi[i], link_up);
5838}
5839
5840/**
5841 * i40e_link_event - Update netif_carrier status
5842 * @pf: board private structure
5843 **/
5844static void i40e_link_event(struct i40e_pf *pf)
5845{
5846 bool new_link, old_link;
320684cd 5847 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5848 u8 new_link_speed, old_link_speed;
41c445ff 5849
1e701e09
JB		 5850 /* set this to force the get_link_status call to refresh state */
5851 pf->hw.phy.get_link_info = true;
5852
41c445ff 5853 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5854 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5855 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5856 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5857
1e701e09 5858 if (new_link == old_link &&
fef59ddf 5859 new_link_speed == old_link_speed &&
320684cd
MW		 5860 (test_bit(__I40E_DOWN, &vsi->state) ||
5861 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5862 return;
320684cd
MW		 5863
5864 if (!test_bit(__I40E_DOWN, &vsi->state))
5865 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5866
5867 /* Notify the base of the switch tree connected to
5868 * the link. Floating VEBs are not notified.
5869 */
5870 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5871 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5872 else
320684cd 5873 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5874
5875 if (pf->vf)
5876 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5877
5878 if (pf->flags & I40E_FLAG_PTP)
5879 i40e_ptp_set_increment(pf);
41c445ff
JB		 5880}
5881
41c445ff 5882/**
21536717 5883 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5884 * @pf: board private structure
5885 **/
5886static void i40e_watchdog_subtask(struct i40e_pf *pf)
5887{
5888 int i;
5889
5890 /* if interface is down do nothing */
5891 if (test_bit(__I40E_DOWN, &pf->state) ||
5892 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5893 return;
5894
21536717
SN		 5895 /* make sure we don't do these things too often */
5896 if (time_before(jiffies, (pf->service_timer_previous +
5897 pf->service_timer_period)))
5898 return;
5899 pf->service_timer_previous = jiffies;
5900
21536717
SN		 5901 i40e_link_event(pf);
5902
41c445ff
JB		 5903 /* Update the stats for active netdevs so the network stack
5904 * can look at updated numbers whenever it cares to
5905 */
505682cd 5906 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5907 if (pf->vsi[i] && pf->vsi[i]->netdev)
5908 i40e_update_stats(pf->vsi[i]);
5909
5910 /* Update the stats for the active switching components */
5911 for (i = 0; i < I40E_MAX_VEB; i++)
5912 if (pf->veb[i])
5913 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5914
5915 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5916}
5917
5918/**
5919 * i40e_reset_subtask - Set up for resetting the device and driver
5920 * @pf: board private structure
5921 **/
5922static void i40e_reset_subtask(struct i40e_pf *pf)
5923{
5924 u32 reset_flags = 0;
5925
23326186 5926 rtnl_lock();
41c445ff 5927 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5928 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5929 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5930 }
5931 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5932 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5933 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5934 }
5935 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5936 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5937 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5938 }
5939 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5940 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5941 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5942 }
b5d06f05 5943 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5944 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5945 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5946 }
41c445ff
JB		 5947
5948 /* If there's a recovery already waiting, it takes
5949 * precedence before starting a new reset sequence.
5950 */
5951 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5952 i40e_handle_reset_warning(pf);
23326186 5953 goto unlock;
41c445ff
JB		 5954 }
5955
5956 /* If we're already down or resetting, just bail */
5957 if (reset_flags &&
5958 !test_bit(__I40E_DOWN, &pf->state) &&
5959 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5960 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5961
5962unlock:
5963 rtnl_unlock();
41c445ff
JB		 5964}
5965
5966/**
5967 * i40e_handle_link_event - Handle link event
5968 * @pf: board private structure
5969 * @e: event info posted on ARQ
5970 **/
5971static void i40e_handle_link_event(struct i40e_pf *pf,
5972 struct i40e_arq_event_info *e)
5973{
5974 struct i40e_hw *hw = &pf->hw;
5975 struct i40e_aqc_get_link_status *status =
5976 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5977
5978 /* save off old link status information */
1a2f6248 5979 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5980
1e701e09
JB		 5981 /* Do a new status request to re-enable LSE reporting
5982 * and load new status information into the hw struct
5983 * This completely ignores any state information
5984 * in the ARQ event info, instead choosing to always
5985 * issue the AQ update link status command.
5986 */
5987 i40e_link_event(pf);
5988
7b592f61
CW		 5989 /* check for unqualified module, if link is down */
5990 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5991 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5992 (!(status->link_info & I40E_AQ_LINK_UP)))
5993 dev_err(&pf->pdev->dev,
5994 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5995}
5996
5997/**
5998 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5999 * @pf: board private structure
6000 **/
6001static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6002{
6003 struct i40e_arq_event_info event;
6004 struct i40e_hw *hw = &pf->hw;
6005 u16 pending, i = 0;
6006 i40e_status ret;
6007 u16 opcode;
86df242b 6008 u32 oldval;
41c445ff
JB		 6009 u32 val;
6010
a316f651
ASJ		 6011 /* Do not run clean AQ when PF reset fails */
6012 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6013 return;
6014
86df242b
SN		 6015 /* check for error indications */
6016 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6017 oldval = val;
6018 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6019 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6020 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6021 }
6022 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6023 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6024 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6025 }
6026 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6027 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6028 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6029 }
6030 if (oldval != val)
6031 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6032
6033 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6034 oldval = val;
6035 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6036 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6037 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6038 }
6039 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6040 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6041 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6042 }
6043 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6044 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6045 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6046 }
6047 if (oldval != val)
6048 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6049
1001dc37
MW		 6050 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6051 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6052 if (!event.msg_buf)
6053 return;
6054
6055 do {
6056 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6057 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6058 break;
56497978 6059 else if (ret) {
41c445ff
JB		 6060 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6061 break;
6062 }
6063
6064 opcode = le16_to_cpu(event.desc.opcode);
6065 switch (opcode) {
6066
6067 case i40e_aqc_opc_get_link_status:
6068 i40e_handle_link_event(pf, &event);
6069 break;
6070 case i40e_aqc_opc_send_msg_to_pf:
6071 ret = i40e_vc_process_vf_msg(pf,
6072 le16_to_cpu(event.desc.retval),
6073 le32_to_cpu(event.desc.cookie_high),
6074 le32_to_cpu(event.desc.cookie_low),
6075 event.msg_buf,
1001dc37 6076 event.msg_len);
41c445ff
JB		 6077 break;
6078 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6079 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6080#ifdef CONFIG_I40E_DCB
6081 rtnl_lock();
6082 ret = i40e_handle_lldp_event(pf, &event);
6083 rtnl_unlock();
6084#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6085 break;
6086 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6087 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6088 i40e_handle_lan_overflow_event(pf, &event);
6089 break;
0467bc91
SN		 6090 case i40e_aqc_opc_send_msg_to_peer:
6091 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6092 break;
91a0f930
SN		 6093 case i40e_aqc_opc_nvm_erase:
6094 case i40e_aqc_opc_nvm_update:
6095 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6096 break;
41c445ff
JB		 6097 default:
6098 dev_info(&pf->pdev->dev,
0467bc91
SN		 6099 "ARQ Error: Unknown event 0x%04x received\n",
6100 opcode);
41c445ff
JB		 6101 break;
6102 }
6103 } while (pending && (i++ < pf->adminq_work_limit));
6104
6105 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6106 /* re-enable Admin queue interrupt cause */
6107 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6108 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6109 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6110 i40e_flush(hw);
6111
6112 kfree(event.msg_buf);
6113}
6114
4eb3f768
SN		 6115/**
6116 * i40e_verify_eeprom - make sure eeprom is good to use
6117 * @pf: board private structure
6118 **/
6119static void i40e_verify_eeprom(struct i40e_pf *pf)
6120{
6121 int err;
6122
6123 err = i40e_diag_eeprom_test(&pf->hw);
6124 if (err) {
6125 /* retry in case of garbage read */
6126 err = i40e_diag_eeprom_test(&pf->hw);
6127 if (err) {
6128 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6129 err);
6130 set_bit(__I40E_BAD_EEPROM, &pf->state);
6131 }
6132 }
6133
6134 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6135 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6136 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6137 }
6138}
6139
386a0afa
AA		 6140/**
6141 * i40e_enable_pf_switch_lb
b40c82e6 6142 * @pf: pointer to the PF structure
386a0afa
AA		 6143 *
6144 * enable switch loop back or die - no point in a return value
6145 **/
6146static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6147{
6148 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6149 struct i40e_vsi_context ctxt;
f1c7e72e 6150 int ret;
386a0afa
AA		 6151
6152 ctxt.seid = pf->main_vsi_seid;
6153 ctxt.pf_num = pf->hw.pf_id;
6154 ctxt.vf_num = 0;
f1c7e72e
SN		 6155 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6156 if (ret) {
386a0afa 6157 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6158 "couldn't get PF vsi config, err %s aq_err %s\n",
6159 i40e_stat_str(&pf->hw, ret),
6160 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6161 return;
6162 }
6163 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6164 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6165 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6166
f1c7e72e
SN		 6167 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6168 if (ret) {
386a0afa 6169 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6170 "update vsi switch failed, err %s aq_err %s\n",
6171 i40e_stat_str(&pf->hw, ret),
6172 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6173 }
6174}
6175
6176/**
6177 * i40e_disable_pf_switch_lb
b40c82e6 6178 * @pf: pointer to the PF structure
386a0afa
AA		 6179 *
6180 * disable switch loop back or die - no point in a return value
6181 **/
6182static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6183{
6184 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6185 struct i40e_vsi_context ctxt;
f1c7e72e 6186 int ret;
386a0afa
AA		 6187
6188 ctxt.seid = pf->main_vsi_seid;
6189 ctxt.pf_num = pf->hw.pf_id;
6190 ctxt.vf_num = 0;
f1c7e72e
SN		 6191 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6192 if (ret) {
386a0afa 6193 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6194 "couldn't get PF vsi config, err %s aq_err %s\n",
6195 i40e_stat_str(&pf->hw, ret),
6196 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6197 return;
6198 }
6199 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6200 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6201 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6202
f1c7e72e
SN		 6203 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6204 if (ret) {
386a0afa 6205 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6206 "update vsi switch failed, err %s aq_err %s\n",
6207 i40e_stat_str(&pf->hw, ret),
6208 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6209 }
6210}
6211
51616018
NP		 6212/**
6213 * i40e_config_bridge_mode - Configure the HW bridge mode
6214 * @veb: pointer to the bridge instance
6215 *
6216 * Configure the loop back mode for the LAN VSI that is downlink to the
6217 * specified HW bridge instance. It is expected this function is called
6218 * when a new HW bridge is instantiated.
6219 **/
6220static void i40e_config_bridge_mode(struct i40e_veb *veb)
6221{
6222 struct i40e_pf *pf = veb->pf;
6223
6224 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6225 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6226 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6227 i40e_disable_pf_switch_lb(pf);
6228 else
6229 i40e_enable_pf_switch_lb(pf);
6230}
6231
41c445ff
JB		 6232/**
6233 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6234 * @veb: pointer to the VEB instance
6235 *
6236 * This is a recursive function that first builds the attached VSIs then
6237 * recurses in to build the next layer of VEB. We track the connections
6238 * through our own index numbers because the seid's from the HW could
6239 * change across the reset.
6240 **/
6241static int i40e_reconstitute_veb(struct i40e_veb *veb)
6242{
6243 struct i40e_vsi *ctl_vsi = NULL;
6244 struct i40e_pf *pf = veb->pf;
6245 int v, veb_idx;
6246 int ret;
6247
6248 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6249 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6250 if (pf->vsi[v] &&
6251 pf->vsi[v]->veb_idx == veb->idx &&
6252 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6253 ctl_vsi = pf->vsi[v];
6254 break;
6255 }
6256 }
6257 if (!ctl_vsi) {
6258 dev_info(&pf->pdev->dev,
6259 "missing owner VSI for veb_idx %d\n", veb->idx);
6260 ret = -ENOENT;
6261 goto end_reconstitute;
6262 }
6263 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6264 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6265 ret = i40e_add_vsi(ctl_vsi);
6266 if (ret) {
6267 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6268 "rebuild of veb_idx %d owner VSI failed: %d\n",
6269 veb->idx, ret);
41c445ff
JB		 6270 goto end_reconstitute;
6271 }
6272 i40e_vsi_reset_stats(ctl_vsi);
6273
6274 /* create the VEB in the switch and move the VSI onto the VEB */
6275 ret = i40e_add_veb(veb, ctl_vsi);
6276 if (ret)
6277 goto end_reconstitute;
6278
fc60861e
ASJ		 6279 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6280 veb->bridge_mode = BRIDGE_MODE_VEB;
6281 else
6282 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6283 i40e_config_bridge_mode(veb);
b64ba084 6284
41c445ff 6285 /* create the remaining VSIs attached to this VEB */
505682cd 6286 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6287 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6288 continue;
6289
6290 if (pf->vsi[v]->veb_idx == veb->idx) {
6291 struct i40e_vsi *vsi = pf->vsi[v];
6292 vsi->uplink_seid = veb->seid;
6293 ret = i40e_add_vsi(vsi);
6294 if (ret) {
6295 dev_info(&pf->pdev->dev,
6296 "rebuild of vsi_idx %d failed: %d\n",
6297 v, ret);
6298 goto end_reconstitute;
6299 }
6300 i40e_vsi_reset_stats(vsi);
6301 }
6302 }
6303
6304 /* create any VEBs attached to this VEB - RECURSION */
6305 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6306 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6307 pf->veb[veb_idx]->uplink_seid = veb->seid;
6308 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6309 if (ret)
6310 break;
6311 }
6312 }
6313
6314end_reconstitute:
6315 return ret;
6316}
6317
6318/**
6319 * i40e_get_capabilities - get info about the HW
6320 * @pf: the PF struct
6321 **/
6322static int i40e_get_capabilities(struct i40e_pf *pf)
6323{
6324 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6325 u16 data_size;
6326 int buf_len;
6327 int err;
6328
6329 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6330 do {
6331 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6332 if (!cap_buf)
6333 return -ENOMEM;
6334
6335 /* this loads the data into the hw struct for us */
6336 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6337 &data_size,
6338 i40e_aqc_opc_list_func_capabilities,
6339 NULL);
6340 /* data loaded, buffer no longer needed */
6341 kfree(cap_buf);
6342
6343 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6344 /* retry with a larger buffer */
6345 buf_len = data_size;
6346 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6347 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6348 "capability discovery failed, err %s aq_err %s\n",
6349 i40e_stat_str(&pf->hw, err),
6350 i40e_aq_str(&pf->hw,
6351 pf->hw.aq.asq_last_status));
41c445ff
JB		 6352 return -ENODEV;
6353 }
6354 } while (err);
6355
ac71b7ba
ASJ		 6356 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6357 (pf->hw.aq.fw_maj_ver < 2)) {
6358 pf->hw.func_caps.num_msix_vectors++;
6359 pf->hw.func_caps.num_msix_vectors_vf++;
6360 }
6361
41c445ff
JB		 6362 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6363 dev_info(&pf->pdev->dev,
6364 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6365 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6366 pf->hw.func_caps.num_msix_vectors,
6367 pf->hw.func_caps.num_msix_vectors_vf,
6368 pf->hw.func_caps.fd_filters_guaranteed,
6369 pf->hw.func_caps.fd_filters_best_effort,
6370 pf->hw.func_caps.num_tx_qp,
6371 pf->hw.func_caps.num_vsis);
6372
7134f9ce
JB		 6373#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6374 + pf->hw.func_caps.num_vfs)
6375 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6376 dev_info(&pf->pdev->dev,
6377 "got num_vsis %d, setting num_vsis to %d\n",
6378 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6379 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6380 }
6381
41c445ff
JB		 6382 return 0;
6383}
6384
cbf61325
ASJ		 6385static int i40e_vsi_clear(struct i40e_vsi *vsi);
6386
41c445ff 6387/**
cbf61325 6388 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6389 * @pf: board private structure
6390 **/
cbf61325 6391static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6392{
6393 struct i40e_vsi *vsi;
8a9eb7d3 6394 int i;
41c445ff 6395
407e063c
JB		 6396 /* quick workaround for an NVM issue that leaves a critical register
6397 * uninitialized
6398 */
6399 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6400 static const u32 hkey[] = {
6401 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6402 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6403 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6404 0x95b3a76d};
6405
6406 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6407 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6408 }
6409
cbf61325 6410 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6411 return;
6412
cbf61325 6413 /* find existing VSI and see if it needs configuring */
41c445ff 6414 vsi = NULL;
505682cd 6415 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6416 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6417 vsi = pf->vsi[i];
cbf61325
ASJ		 6418 break;
6419 }
6420 }
6421
6422 /* create a new VSI if none exists */
41c445ff 6423 if (!vsi) {
cbf61325
ASJ		 6424 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6425 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6426 if (!vsi) {
6427 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6428 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6429 return;
41c445ff 6430 }
cbf61325 6431 }
41c445ff 6432
8a9eb7d3 6433 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6434}
6435
6436/**
6437 * i40e_fdir_teardown - release the Flow Director resources
6438 * @pf: board private structure
6439 **/
6440static void i40e_fdir_teardown(struct i40e_pf *pf)
6441{
6442 int i;
6443
17a73f6b 6444 i40e_fdir_filter_exit(pf);
505682cd 6445 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6446 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6447 i40e_vsi_release(pf->vsi[i]);
6448 break;
6449 }
6450 }
6451}
6452
6453/**
f650a38b 6454 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6455 * @pf: board private structure
6456 *
b40c82e6 6457 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6458 **/
23cfbe07 6459static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6460{
41c445ff 6461 struct i40e_hw *hw = &pf->hw;
60442dea 6462 i40e_status ret = 0;
41c445ff
JB		 6463 u32 v;
6464
6465 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6466 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6467 return;
41c445ff 6468
69bfb110 6469 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6470
41c445ff
JB		 6471 /* quiesce the VSIs and their queues that are not already DOWN */
6472 i40e_pf_quiesce_all_vsi(pf);
6473
505682cd 6474 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6475 if (pf->vsi[v])
6476 pf->vsi[v]->seid = 0;
6477 }
6478
6479 i40e_shutdown_adminq(&pf->hw);
6480
f650a38b 6481 /* call shutdown HMC */
60442dea
SN		 6482 if (hw->hmc.hmc_obj) {
6483 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6484 if (ret)
60442dea
SN		 6485 dev_warn(&pf->pdev->dev,
6486 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6487 }
f650a38b
ASJ		 6488}
6489
44033fac
JB		 6490/**
6491 * i40e_send_version - update firmware with driver version
6492 * @pf: PF struct
6493 */
6494static void i40e_send_version(struct i40e_pf *pf)
6495{
6496 struct i40e_driver_version dv;
6497
6498 dv.major_version = DRV_VERSION_MAJOR;
6499 dv.minor_version = DRV_VERSION_MINOR;
6500 dv.build_version = DRV_VERSION_BUILD;
6501 dv.subbuild_version = 0;
35a7d804 6502 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6503 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6504}
6505
f650a38b 6506/**
4dda12e6 6507 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6508 * @pf: board private structure
bc7d338f 6509 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6510 **/
bc7d338f 6511static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6512{
f650a38b 6513 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6514 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6515 i40e_status ret;
6516 u32 v;
6517
41c445ff
JB		 6518 /* Now we wait for GRST to settle out.
6519 * We don't have to delete the VEBs or VSIs from the hw switch
6520 * because the reset will make them disappear.
6521 */
6522 ret = i40e_pf_reset(hw);
b5565400 6523 if (ret) {
41c445ff 6524 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6525 set_bit(__I40E_RESET_FAILED, &pf->state);
6526 goto clear_recovery;
b5565400 6527 }
41c445ff
JB		 6528 pf->pfr_count++;
6529
6530 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6531 goto clear_recovery;
69bfb110 6532 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6533
6534 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6535 ret = i40e_init_adminq(&pf->hw);
6536 if (ret) {
f1c7e72e
SN		 6537 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6538 i40e_stat_str(&pf->hw, ret),
6539 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6540 goto clear_recovery;
41c445ff
JB		 6541 }
6542
4eb3f768 6543 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6544 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6545 i40e_verify_eeprom(pf);
4eb3f768 6546
e78ac4bf 6547 i40e_clear_pxe_mode(hw);
41c445ff 6548 ret = i40e_get_capabilities(pf);
f1c7e72e 6549 if (ret)
41c445ff 6550 goto end_core_reset;
41c445ff 6551
41c445ff
JB		 6552 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6553 hw->func_caps.num_rx_qp,
6554 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6555 if (ret) {
6556 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6557 goto end_core_reset;
6558 }
6559 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6560 if (ret) {
6561 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6562 goto end_core_reset;
6563 }
6564
4e3b35b0
NP		 6565#ifdef CONFIG_I40E_DCB
6566 ret = i40e_init_pf_dcb(pf);
6567 if (ret) {
aebfc816
SN		 6568 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6569 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6570 /* Continue without DCB enabled */
4e3b35b0
NP		 6571 }
6572#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6573#ifdef I40E_FCOE
6574 ret = i40e_init_pf_fcoe(pf);
6575 if (ret)
6576 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6577
38e00438 6578#endif
41c445ff 6579 /* do basic switch setup */
bc7d338f 6580 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6581 if (ret)
6582 goto end_core_reset;
6583
7e2453fe
JB		 6584 /* driver is only interested in link up/down and module qualification
6585 * reports from firmware
6586 */
6587 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6588 I40E_AQ_EVENT_LINK_UPDOWN |
6589 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6590 if (ret)
f1c7e72e
SN		 6591 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6592 i40e_stat_str(&pf->hw, ret),
6593 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6594
cafa2ee6
ASJ		 6595 /* make sure our flow control settings are restored */
6596 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6597 if (ret)
f1c7e72e
SN		 6598 dev_info(&pf->pdev->dev, "set fc fail, err %s aq_err %s\n",
6599 i40e_stat_str(&pf->hw, ret),
6600 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6601
41c445ff
JB		 6602 /* Rebuild the VSIs and VEBs that existed before reset.
6603 * They are still in our local switch element arrays, so only
6604 * need to rebuild the switch model in the HW.
6605 *
6606 * If there were VEBs but the reconstitution failed, we'll try
6607 * try to recover minimal use by getting the basic PF VSI working.
6608 */
6609 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6610 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6611 /* find the one VEB connected to the MAC, and find orphans */
6612 for (v = 0; v < I40E_MAX_VEB; v++) {
6613 if (!pf->veb[v])
6614 continue;
6615
6616 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6617 pf->veb[v]->uplink_seid == 0) {
6618 ret = i40e_reconstitute_veb(pf->veb[v]);
6619
6620 if (!ret)
6621 continue;
6622
6623 /* If Main VEB failed, we're in deep doodoo,
6624 * so give up rebuilding the switch and set up
6625 * for minimal rebuild of PF VSI.
6626 * If orphan failed, we'll report the error
6627 * but try to keep going.
6628 */
6629 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6630 dev_info(&pf->pdev->dev,
6631 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6632 ret);
6633 pf->vsi[pf->lan_vsi]->uplink_seid
6634 = pf->mac_seid;
6635 break;
6636 } else if (pf->veb[v]->uplink_seid == 0) {
6637 dev_info(&pf->pdev->dev,
6638 "rebuild of orphan VEB failed: %d\n",
6639 ret);
6640 }
6641 }
6642 }
6643 }
6644
6645 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6646 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6647 /* no VEB, so rebuild only the Main VSI */
6648 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6649 if (ret) {
6650 dev_info(&pf->pdev->dev,
6651 "rebuild of Main VSI failed: %d\n", ret);
6652 goto end_core_reset;
6653 }
6654 }
6655
025b4a54
ASJ		 6656 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6657 (pf->hw.aq.fw_maj_ver < 4)) {
6658 msleep(75);
6659 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6660 if (ret)
f1c7e72e
SN		 6661 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6662 i40e_stat_str(&pf->hw, ret),
6663 i40e_aq_str(&pf->hw,
6664 pf->hw.aq.asq_last_status));
cafa2ee6 6665 }
41c445ff
JB		 6666 /* reinit the misc interrupt */
6667 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6668 ret = i40e_setup_misc_vector(pf);
6669
6670 /* restart the VSIs that were rebuilt and running before the reset */
6671 i40e_pf_unquiesce_all_vsi(pf);
6672
69f64b2b
MW		 6673 if (pf->num_alloc_vfs) {
6674 for (v = 0; v < pf->num_alloc_vfs; v++)
6675 i40e_reset_vf(&pf->vf[v], true);
6676 }
6677
41c445ff 6678 /* tell the firmware that we're starting */
44033fac 6679 i40e_send_version(pf);
41c445ff
JB		 6680
6681end_core_reset:
a316f651
ASJ		 6682 clear_bit(__I40E_RESET_FAILED, &pf->state);
6683clear_recovery:
41c445ff
JB		 6684 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6685}
6686
f650a38b 6687/**
b40c82e6 6688 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6689 * @pf: board private structure
6690 *
6691 * Close up the VFs and other things in prep for a Core Reset,
6692 * then get ready to rebuild the world.
6693 **/
6694static void i40e_handle_reset_warning(struct i40e_pf *pf)
6695{
23cfbe07
SN		 6696 i40e_prep_for_reset(pf);
6697 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6698}
6699
41c445ff
JB		 6700/**
6701 * i40e_handle_mdd_event
b40c82e6 6702 * @pf: pointer to the PF structure
41c445ff
JB		 6703 *
6704 * Called from the MDD irq handler to identify possibly malicious vfs
6705 **/
6706static void i40e_handle_mdd_event(struct i40e_pf *pf)
6707{
6708 struct i40e_hw *hw = &pf->hw;
6709 bool mdd_detected = false;
df430b12 6710 bool pf_mdd_detected = false;
41c445ff
JB		 6711 struct i40e_vf *vf;
6712 u32 reg;
6713 int i;
6714
6715 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6716 return;
6717
6718 /* find what triggered the MDD event */
6719 reg = rd32(hw, I40E_GL_MDET_TX);
6720 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6721 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6722 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6723 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6724 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6725 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6726 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6727 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6728 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6729 pf->hw.func_caps.base_queue;
faf32978 6730 if (netif_msg_tx_err(pf))
b40c82e6 6731 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6732 event, queue, pf_num, vf_num);
41c445ff
JB		 6733 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6734 mdd_detected = true;
6735 }
6736 reg = rd32(hw, I40E_GL_MDET_RX);
6737 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6738 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6739 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6740 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6741 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6742 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6743 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6744 pf->hw.func_caps.base_queue;
faf32978
JB		 6745 if (netif_msg_rx_err(pf))
6746 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6747 event, queue, func);
41c445ff
JB		 6748 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6749 mdd_detected = true;
6750 }
6751
df430b12
NP		 6752 if (mdd_detected) {
6753 reg = rd32(hw, I40E_PF_MDET_TX);
6754 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6755 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6756 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6757 pf_mdd_detected = true;
6758 }
6759 reg = rd32(hw, I40E_PF_MDET_RX);
6760 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6761 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6762 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6763 pf_mdd_detected = true;
6764 }
6765 /* Queue belongs to the PF, initiate a reset */
6766 if (pf_mdd_detected) {
6767 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6768 i40e_service_event_schedule(pf);
6769 }
6770 }
6771
41c445ff
JB		 6772 /* see if one of the VFs needs its hand slapped */
6773 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6774 vf = &(pf->vf[i]);
6775 reg = rd32(hw, I40E_VP_MDET_TX(i));
6776 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6777 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6778 vf->num_mdd_events++;
faf32978
JB		 6779 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6780 i);
41c445ff
JB		 6781 }
6782
6783 reg = rd32(hw, I40E_VP_MDET_RX(i));
6784 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6785 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6786 vf->num_mdd_events++;
faf32978
JB		 6787 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6788 i);
41c445ff
JB		 6789 }
6790
6791 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6792 dev_info(&pf->pdev->dev,
6793 "Too many MDD events on VF %d, disabled\n", i);
6794 dev_info(&pf->pdev->dev,
6795 "Use PF Control I/F to re-enable the VF\n");
6796 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6797 }
6798 }
6799
6800 /* re-enable mdd interrupt cause */
6801 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6802 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6803 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6804 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6805 i40e_flush(hw);
6806}
6807
a1c9a9d9
JK		 6808#ifdef CONFIG_I40E_VXLAN
6809/**
6810 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6811 * @pf: board private structure
6812 **/
6813static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6814{
a1c9a9d9
JK		 6815 struct i40e_hw *hw = &pf->hw;
6816 i40e_status ret;
a1c9a9d9
JK		 6817 __be16 port;
6818 int i;
6819
6820 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6821 return;
6822
6823 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6824
6825 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6826 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6827 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6828 port = pf->vxlan_ports[i];
c22c06c8
SN		 6829 if (port)
6830 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6831 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6832 NULL, NULL);
6833 else
6834 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6835
6836 if (ret) {
c22c06c8 6837 dev_info(&pf->pdev->dev,
f1c7e72e 6838 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6839 port ? "add" : "delete",
f1c7e72e
SN		 6840 ntohs(port), i,
6841 i40e_stat_str(&pf->hw, ret),
6842 i40e_aq_str(&pf->hw,
6843 pf->hw.aq.asq_last_status));
a1c9a9d9 6844 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6845 }
6846 }
6847 }
6848}
6849
6850#endif
41c445ff
JB		 6851/**
6852 * i40e_service_task - Run the driver's async subtasks
6853 * @work: pointer to work_struct containing our data
6854 **/
6855static void i40e_service_task(struct work_struct *work)
6856{
6857 struct i40e_pf *pf = container_of(work,
6858 struct i40e_pf,
6859 service_task);
6860 unsigned long start_time = jiffies;
6861
e57a2fea
SN		 6862 /* don't bother with service tasks if a reset is in progress */
6863 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6864 i40e_service_event_complete(pf);
6865 return;
6866 }
6867
b03a8c1f 6868 i40e_detect_recover_hung(pf);
41c445ff
JB		 6869 i40e_reset_subtask(pf);
6870 i40e_handle_mdd_event(pf);
6871 i40e_vc_process_vflr_event(pf);
6872 i40e_watchdog_subtask(pf);
6873 i40e_fdir_reinit_subtask(pf);
41c445ff 6874 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6875#ifdef CONFIG_I40E_VXLAN
6876 i40e_sync_vxlan_filters_subtask(pf);
6877#endif
41c445ff
JB		 6878 i40e_clean_adminq_subtask(pf);
6879
6880 i40e_service_event_complete(pf);
6881
6882 /* If the tasks have taken longer than one timer cycle or there
6883 * is more work to be done, reschedule the service task now
6884 * rather than wait for the timer to tick again.
6885 */
6886 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6887 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6888 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6889 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6890 i40e_service_event_schedule(pf);
6891}
6892
6893/**
6894 * i40e_service_timer - timer callback
6895 * @data: pointer to PF struct
6896 **/
6897static void i40e_service_timer(unsigned long data)
6898{
6899 struct i40e_pf *pf = (struct i40e_pf *)data;
6900
6901 mod_timer(&pf->service_timer,
6902 round_jiffies(jiffies + pf->service_timer_period));
6903 i40e_service_event_schedule(pf);
6904}
6905
6906/**
6907 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6908 * @vsi: the VSI being configured
6909 **/
6910static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6911{
6912 struct i40e_pf *pf = vsi->back;
6913
6914 switch (vsi->type) {
6915 case I40E_VSI_MAIN:
6916 vsi->alloc_queue_pairs = pf->num_lan_qps;
6917 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6918 I40E_REQ_DESCRIPTOR_MULTIPLE);
6919 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6920 vsi->num_q_vectors = pf->num_lan_msix;
6921 else
6922 vsi->num_q_vectors = 1;
6923
6924 break;
6925
6926 case I40E_VSI_FDIR:
6927 vsi->alloc_queue_pairs = 1;
6928 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6929 I40E_REQ_DESCRIPTOR_MULTIPLE);
6930 vsi->num_q_vectors = 1;
6931 break;
6932
6933 case I40E_VSI_VMDQ2:
6934 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6935 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6936 I40E_REQ_DESCRIPTOR_MULTIPLE);
6937 vsi->num_q_vectors = pf->num_vmdq_msix;
6938 break;
6939
6940 case I40E_VSI_SRIOV:
6941 vsi->alloc_queue_pairs = pf->num_vf_qps;
6942 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6943 I40E_REQ_DESCRIPTOR_MULTIPLE);
6944 break;
6945
38e00438
VD		 6946#ifdef I40E_FCOE
6947 case I40E_VSI_FCOE:
6948 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6949 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6950 I40E_REQ_DESCRIPTOR_MULTIPLE);
6951 vsi->num_q_vectors = pf->num_fcoe_msix;
6952 break;
6953
6954#endif /* I40E_FCOE */
41c445ff
JB		 6955 default:
6956 WARN_ON(1);
6957 return -ENODATA;
6958 }
6959
6960 return 0;
6961}
6962
f650a38b
ASJ		 6963/**
6964 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6965 * @type: VSI pointer
bc7d338f 6966 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6967 *
6968 * On error: returns error code (negative)
6969 * On success: returns 0
6970 **/
bc7d338f 6971static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6972{
6973 int size;
6974 int ret = 0;
6975
ac6c5e3d 6976 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6977 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6978 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6979 if (!vsi->tx_rings)
6980 return -ENOMEM;
f650a38b
ASJ		 6981 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6982
bc7d338f
ASJ		 6983 if (alloc_qvectors) {
6984 /* allocate memory for q_vector pointers */
f57e4fbd 6985 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6986 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6987 if (!vsi->q_vectors) {
6988 ret = -ENOMEM;
6989 goto err_vectors;
6990 }
f650a38b
ASJ		 6991 }
6992 return ret;
6993
6994err_vectors:
6995 kfree(vsi->tx_rings);
6996 return ret;
6997}
6998
41c445ff
JB		 6999/**
7000 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7001 * @pf: board private structure
7002 * @type: type of VSI
7003 *
7004 * On error: returns error code (negative)
7005 * On success: returns vsi index in PF (positive)
7006 **/
7007static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7008{
7009 int ret = -ENODEV;
7010 struct i40e_vsi *vsi;
7011 int vsi_idx;
7012 int i;
7013
7014 /* Need to protect the allocation of the VSIs at the PF level */
7015 mutex_lock(&pf->switch_mutex);
7016
7017 /* VSI list may be fragmented if VSI creation/destruction has
7018 * been happening. We can afford to do a quick scan to look
7019 * for any free VSIs in the list.
7020 *
7021 * find next empty vsi slot, looping back around if necessary
7022 */
7023 i = pf->next_vsi;
505682cd 7024 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7025 i++;
505682cd 7026 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7027 i = 0;
7028 while (i < pf->next_vsi && pf->vsi[i])
7029 i++;
7030 }
7031
505682cd 7032 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7033 vsi_idx = i; /* Found one! */
7034 } else {
7035 ret = -ENODEV;
493fb300 7036 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7037 }
7038 pf->next_vsi = ++i;
7039
7040 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7041 if (!vsi) {
7042 ret = -ENOMEM;
493fb300 7043 goto unlock_pf;
41c445ff
JB		 7044 }
7045 vsi->type = type;
7046 vsi->back = pf;
7047 set_bit(__I40E_DOWN, &vsi->state);
7048 vsi->flags = 0;
7049 vsi->idx = vsi_idx;
7050 vsi->rx_itr_setting = pf->rx_itr_default;
7051 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 7052 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7053 pf->rss_table_size : 64;
41c445ff
JB		 7054 vsi->netdev_registered = false;
7055 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7056 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7057 vsi->irqs_ready = false;
41c445ff 7058
9f65e15b
AD		 7059 ret = i40e_set_num_rings_in_vsi(vsi);
7060 if (ret)
7061 goto err_rings;
7062
bc7d338f 7063 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7064 if (ret)
9f65e15b 7065 goto err_rings;
493fb300 7066
41c445ff
JB		 7067 /* Setup default MSIX irq handler for VSI */
7068 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7069
7070 pf->vsi[vsi_idx] = vsi;
7071 ret = vsi_idx;
493fb300
AD		 7072 goto unlock_pf;
7073
9f65e15b 7074err_rings:
493fb300
AD		 7075 pf->next_vsi = i - 1;
7076 kfree(vsi);
7077unlock_pf:
41c445ff
JB		 7078 mutex_unlock(&pf->switch_mutex);
7079 return ret;
7080}
7081
f650a38b
ASJ		 7082/**
7083 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7084 * @type: VSI pointer
bc7d338f 7085 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7086 *
7087 * On error: returns error code (negative)
7088 * On success: returns 0
7089 **/
bc7d338f 7090static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7091{
7092 /* free the ring and vector containers */
bc7d338f
ASJ		 7093 if (free_qvectors) {
7094 kfree(vsi->q_vectors);
7095 vsi->q_vectors = NULL;
7096 }
f650a38b
ASJ		 7097 kfree(vsi->tx_rings);
7098 vsi->tx_rings = NULL;
7099 vsi->rx_rings = NULL;
7100}
7101
41c445ff
JB		 7102/**
7103 * i40e_vsi_clear - Deallocate the VSI provided
7104 * @vsi: the VSI being un-configured
7105 **/
7106static int i40e_vsi_clear(struct i40e_vsi *vsi)
7107{
7108 struct i40e_pf *pf;
7109
7110 if (!vsi)
7111 return 0;
7112
7113 if (!vsi->back)
7114 goto free_vsi;
7115 pf = vsi->back;
7116
7117 mutex_lock(&pf->switch_mutex);
7118 if (!pf->vsi[vsi->idx]) {
7119 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7120 vsi->idx, vsi->idx, vsi, vsi->type);
7121 goto unlock_vsi;
7122 }
7123
7124 if (pf->vsi[vsi->idx] != vsi) {
7125 dev_err(&pf->pdev->dev,
7126 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7127 pf->vsi[vsi->idx]->idx,
7128 pf->vsi[vsi->idx],
7129 pf->vsi[vsi->idx]->type,
7130 vsi->idx, vsi, vsi->type);
7131 goto unlock_vsi;
7132 }
7133
b40c82e6 7134 /* updates the PF for this cleared vsi */
41c445ff
JB		 7135 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7136 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7137
bc7d338f 7138 i40e_vsi_free_arrays(vsi, true);
493fb300 7139
41c445ff
JB		 7140 pf->vsi[vsi->idx] = NULL;
7141 if (vsi->idx < pf->next_vsi)
7142 pf->next_vsi = vsi->idx;
7143
7144unlock_vsi:
7145 mutex_unlock(&pf->switch_mutex);
7146free_vsi:
7147 kfree(vsi);
7148
7149 return 0;
7150}
7151
9f65e15b
AD		 7152/**
7153 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7154 * @vsi: the VSI being cleaned
7155 **/
be1d5eea 7156static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7157{
7158 int i;
7159
8e9dca53 7160 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7161 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7162 kfree_rcu(vsi->tx_rings[i], rcu);
7163 vsi->tx_rings[i] = NULL;
7164 vsi->rx_rings[i] = NULL;
7165 }
be1d5eea 7166 }
9f65e15b
AD		 7167}
7168
41c445ff
JB		 7169/**
7170 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7171 * @vsi: the VSI being configured
7172 **/
7173static int i40e_alloc_rings(struct i40e_vsi *vsi)
7174{
e7046ee1 7175 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7176 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7177 int i;
7178
41c445ff 7179 /* Set basic values in the rings to be used later during open() */
d7397644 7180 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7181 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7182 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7183 if (!tx_ring)
7184 goto err_out;
41c445ff
JB		 7185
7186 tx_ring->queue_index = i;
7187 tx_ring->reg_idx = vsi->base_queue + i;
7188 tx_ring->ring_active = false;
7189 tx_ring->vsi = vsi;
7190 tx_ring->netdev = vsi->netdev;
7191 tx_ring->dev = &pf->pdev->dev;
7192 tx_ring->count = vsi->num_desc;
7193 tx_ring->size = 0;
7194 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7195 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7196 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7197 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7198 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7199 vsi->tx_rings[i] = tx_ring;
41c445ff 7200
9f65e15b 7201 rx_ring = &tx_ring[1];
41c445ff
JB		 7202 rx_ring->queue_index = i;
7203 rx_ring->reg_idx = vsi->base_queue + i;
7204 rx_ring->ring_active = false;
7205 rx_ring->vsi = vsi;
7206 rx_ring->netdev = vsi->netdev;
7207 rx_ring->dev = &pf->pdev->dev;
7208 rx_ring->count = vsi->num_desc;
7209 rx_ring->size = 0;
7210 rx_ring->dcb_tc = 0;
7211 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7212 set_ring_16byte_desc_enabled(rx_ring);
7213 else
7214 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7215 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7216 }
7217
7218 return 0;
9f65e15b
AD		 7219
7220err_out:
7221 i40e_vsi_clear_rings(vsi);
7222 return -ENOMEM;
41c445ff
JB		 7223}
7224
7225/**
7226 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7227 * @pf: board private structure
7228 * @vectors: the number of MSI-X vectors to request
7229 *
7230 * Returns the number of vectors reserved, or error
7231 **/
7232static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7233{
7b37f376
AG		 7234 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7235 I40E_MIN_MSIX, vectors);
7236 if (vectors < 0) {
41c445ff 7237 dev_info(&pf->pdev->dev,
7b37f376 7238 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7239 vectors = 0;
7240 }
7241
7242 return vectors;
7243}
7244
7245/**
7246 * i40e_init_msix - Setup the MSIX capability
7247 * @pf: board private structure
7248 *
7249 * Work with the OS to set up the MSIX vectors needed.
7250 *
3b444399 7251 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7252 **/
7253static int i40e_init_msix(struct i40e_pf *pf)
7254{
41c445ff 7255 struct i40e_hw *hw = &pf->hw;
1e200e4a 7256 int vectors_left;
41c445ff 7257 int v_budget, i;
3b444399 7258 int v_actual;
41c445ff
JB		 7259
7260 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7261 return -ENODEV;
7262
7263 /* The number of vectors we'll request will be comprised of:
7264 * - Add 1 for "other" cause for Admin Queue events, etc.
7265 * - The number of LAN queue pairs
f8ff1464
ASJ		 7266 * - Queues being used for RSS.
7267 * We don't need as many as max_rss_size vectors.
7268 * use rss_size instead in the calculation since that
7269 * is governed by number of cpus in the system.
7270 * - assumes symmetric Tx/Rx pairing
41c445ff 7271 * - The number of VMDq pairs
38e00438
VD		 7272#ifdef I40E_FCOE
7273 * - The number of FCOE qps.
7274#endif
41c445ff
JB		 7275 * Once we count this up, try the request.
7276 *
7277 * If we can't get what we want, we'll simplify to nearly nothing
7278 * and try again. If that still fails, we punt.
7279 */
1e200e4a
SN		 7280 vectors_left = hw->func_caps.num_msix_vectors;
7281 v_budget = 0;
7282
7283 /* reserve one vector for miscellaneous handler */
7284 if (vectors_left) {
7285 v_budget++;
7286 vectors_left--;
7287 }
7288
7289 /* reserve vectors for the main PF traffic queues */
7290 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7291 vectors_left -= pf->num_lan_msix;
7292 v_budget += pf->num_lan_msix;
7293
7294 /* reserve one vector for sideband flow director */
7295 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7296 if (vectors_left) {
7297 v_budget++;
7298 vectors_left--;
7299 } else {
7300 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7301 }
7302 }
83840e4b 7303
38e00438 7304#ifdef I40E_FCOE
1e200e4a 7305 /* can we reserve enough for FCoE? */
38e00438 7306 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7307 if (!vectors_left)
7308 pf->num_fcoe_msix = 0;
7309 else if (vectors_left >= pf->num_fcoe_qps)
7310 pf->num_fcoe_msix = pf->num_fcoe_qps;
7311 else
7312 pf->num_fcoe_msix = 1;
38e00438 7313 v_budget += pf->num_fcoe_msix;
1e200e4a 7314 vectors_left -= pf->num_fcoe_msix;
38e00438 7315 }
1e200e4a 7316
38e00438 7317#endif
1e200e4a
SN		 7318 /* any vectors left over go for VMDq support */
7319 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7320 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7321 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7322
7323 /* if we're short on vectors for what's desired, we limit
7324 * the queues per vmdq. If this is still more than are
7325 * available, the user will need to change the number of
7326 * queues/vectors used by the PF later with the ethtool
7327 * channels command
7328 */
7329 if (vmdq_vecs < vmdq_vecs_wanted)
7330 pf->num_vmdq_qps = 1;
7331 pf->num_vmdq_msix = pf->num_vmdq_qps;
7332
7333 v_budget += vmdq_vecs;
7334 vectors_left -= vmdq_vecs;
7335 }
41c445ff
JB		 7336
7337 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7338 GFP_KERNEL);
7339 if (!pf->msix_entries)
7340 return -ENOMEM;
7341
7342 for (i = 0; i < v_budget; i++)
7343 pf->msix_entries[i].entry = i;
3b444399 7344 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7345
3b444399 7346 if (v_actual != v_budget) {
a34977ba
ASJ		 7347 /* If we have limited resources, we will start with no vectors
7348 * for the special features and then allocate vectors to some
7349 * of these features based on the policy and at the end disable
7350 * the features that did not get any vectors.
7351 */
38e00438
VD		 7352#ifdef I40E_FCOE
7353 pf->num_fcoe_qps = 0;
7354 pf->num_fcoe_msix = 0;
7355#endif
a34977ba
ASJ		 7356 pf->num_vmdq_msix = 0;
7357 }
7358
3b444399 7359 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7360 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7361 kfree(pf->msix_entries);
7362 pf->msix_entries = NULL;
7363 return -ENODEV;
7364
3b444399 7365 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7366 /* Adjust for minimal MSIX use */
41c445ff
JB		 7367 pf->num_vmdq_vsis = 0;
7368 pf->num_vmdq_qps = 0;
41c445ff
JB		 7369 pf->num_lan_qps = 1;
7370 pf->num_lan_msix = 1;
7371
3b444399
SN		 7372 } else if (v_actual != v_budget) {
7373 int vec;
7374
a34977ba 7375 /* reserve the misc vector */
3b444399 7376 vec = v_actual - 1;
a34977ba 7377
41c445ff
JB		 7378 /* Scale vector usage down */
7379 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7380 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7381 pf->num_vmdq_qps = 1;
7382 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7383
7384 /* partition out the remaining vectors */
7385 switch (vec) {
7386 case 2:
41c445ff
JB		 7387 pf->num_lan_msix = 1;
7388 break;
7389 case 3:
38e00438
VD		 7390#ifdef I40E_FCOE
7391 /* give one vector to FCoE */
7392 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7393 pf->num_lan_msix = 1;
7394 pf->num_fcoe_msix = 1;
7395 }
7396#else
41c445ff 7397 pf->num_lan_msix = 2;
38e00438 7398#endif
41c445ff
JB		 7399 break;
7400 default:
38e00438
VD		 7401#ifdef I40E_FCOE
7402 /* give one vector to FCoE */
7403 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7404 pf->num_fcoe_msix = 1;
7405 vec--;
7406 }
7407#endif
1e200e4a
SN		 7408 /* give the rest to the PF */
7409 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7410 break;
7411 }
7412 }
7413
a34977ba
ASJ		 7414 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7415 (pf->num_vmdq_msix == 0)) {
7416 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7417 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7418 }
38e00438
VD		 7419#ifdef I40E_FCOE
7420
7421 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7422 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7423 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7424 }
7425#endif
3b444399 7426 return v_actual;
41c445ff
JB		 7427}
7428
493fb300 7429/**
90e04070 7430 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7431 * @vsi: the VSI being configured
7432 * @v_idx: index of the vector in the vsi struct
7433 *
7434 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7435 **/
90e04070 7436static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7437{
7438 struct i40e_q_vector *q_vector;
7439
7440 /* allocate q_vector */
7441 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7442 if (!q_vector)
7443 return -ENOMEM;
7444
7445 q_vector->vsi = vsi;
7446 q_vector->v_idx = v_idx;
7447 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7448 if (vsi->netdev)
7449 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7450 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7451
cd0b6fa6
AD		 7452 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7453 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7454
493fb300
AD		 7455 /* tie q_vector and vsi together */
7456 vsi->q_vectors[v_idx] = q_vector;
7457
7458 return 0;
7459}
7460
41c445ff 7461/**
90e04070 7462 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7463 * @vsi: the VSI being configured
7464 *
7465 * We allocate one q_vector per queue interrupt. If allocation fails we
7466 * return -ENOMEM.
7467 **/
90e04070 7468static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7469{
7470 struct i40e_pf *pf = vsi->back;
7471 int v_idx, num_q_vectors;
493fb300 7472 int err;
41c445ff
JB		 7473
7474 /* if not MSIX, give the one vector only to the LAN VSI */
7475 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7476 num_q_vectors = vsi->num_q_vectors;
7477 else if (vsi == pf->vsi[pf->lan_vsi])
7478 num_q_vectors = 1;
7479 else
7480 return -EINVAL;
7481
41c445ff 7482 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7483 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7484 if (err)
7485 goto err_out;
41c445ff
JB		 7486 }
7487
7488 return 0;
493fb300
AD		 7489
7490err_out:
7491 while (v_idx--)
7492 i40e_free_q_vector(vsi, v_idx);
7493
7494 return err;
41c445ff
JB		 7495}
7496
7497/**
7498 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7499 * @pf: board private structure to initialize
7500 **/
c1147280 7501static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7502{
3b444399
SN		 7503 int vectors = 0;
7504 ssize_t size;
41c445ff
JB		 7505
7506 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7507 vectors = i40e_init_msix(pf);
7508 if (vectors < 0) {
60ea5f83 7509 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7510#ifdef I40E_FCOE
7511 I40E_FLAG_FCOE_ENABLED |
7512#endif
60ea5f83 7513 I40E_FLAG_RSS_ENABLED |
4d9b6043 7514 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7515 I40E_FLAG_SRIOV_ENABLED |
7516 I40E_FLAG_FD_SB_ENABLED |
7517 I40E_FLAG_FD_ATR_ENABLED |
7518 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7519
7520 /* rework the queue expectations without MSIX */
7521 i40e_determine_queue_usage(pf);
7522 }
7523 }
7524
7525 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7526 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7527 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7528 vectors = pci_enable_msi(pf->pdev);
7529 if (vectors < 0) {
7530 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7531 vectors);
41c445ff
JB		 7532 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7533 }
3b444399 7534 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7535 }
7536
958a3e3b 7537 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7538 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7539
3b444399
SN		 7540 /* set up vector assignment tracking */
7541 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7542 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7543 if (!pf->irq_pile) {
7544 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7545 return -ENOMEM;
7546 }
3b444399
SN		 7547 pf->irq_pile->num_entries = vectors;
7548 pf->irq_pile->search_hint = 0;
7549
c1147280 7550 /* track first vector for misc interrupts, ignore return */
3b444399 7551 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7552
7553 return 0;
41c445ff
JB		 7554}
7555
7556/**
7557 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7558 * @pf: board private structure
7559 *
7560 * This sets up the handler for MSIX 0, which is used to manage the
7561 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7562 * when in MSI or Legacy interrupt mode.
7563 **/
7564static int i40e_setup_misc_vector(struct i40e_pf *pf)
7565{
7566 struct i40e_hw *hw = &pf->hw;
7567 int err = 0;
7568
7569 /* Only request the irq if this is the first time through, and
7570 * not when we're rebuilding after a Reset
7571 */
7572 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7573 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7574 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7575 if (err) {
7576 dev_info(&pf->pdev->dev,
77fa28be 7577 "request_irq for %s failed: %d\n",
b294ac70 7578 pf->int_name, err);
41c445ff
JB		 7579 return -EFAULT;
7580 }
7581 }
7582
ab437b5a 7583 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7584
7585 /* associate no queues to the misc vector */
7586 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7587 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7588
7589 i40e_flush(hw);
7590
7591 i40e_irq_dynamic_enable_icr0(pf);
7592
7593 return err;
7594}
7595
7596/**
e25d00b8
ASJ		 7597 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7598 * @vsi: vsi structure
7599 * @seed: RSS hash seed
7600 **/
7601static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7602{
7603 struct i40e_aqc_get_set_rss_key_data rss_key;
7604 struct i40e_pf *pf = vsi->back;
7605 struct i40e_hw *hw = &pf->hw;
7606 bool pf_lut = false;
7607 u8 *rss_lut;
7608 int ret, i;
7609
7610 memset(&rss_key, 0, sizeof(rss_key));
7611 memcpy(&rss_key, seed, sizeof(rss_key));
7612
7613 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7614 if (!rss_lut)
7615 return -ENOMEM;
7616
7617 /* Populate the LUT with max no. of queues in round robin fashion */
7618 for (i = 0; i < vsi->rss_table_size; i++)
7619 rss_lut[i] = i % vsi->rss_size;
7620
7621 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7622 if (ret) {
7623 dev_info(&pf->pdev->dev,
7624 "Cannot set RSS key, err %s aq_err %s\n",
7625 i40e_stat_str(&pf->hw, ret),
7626 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7627 return ret;
7628 }
7629
7630 if (vsi->type == I40E_VSI_MAIN)
7631 pf_lut = true;
7632
7633 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7634 vsi->rss_table_size);
7635 if (ret)
7636 dev_info(&pf->pdev->dev,
7637 "Cannot set RSS lut, err %s aq_err %s\n",
7638 i40e_stat_str(&pf->hw, ret),
7639 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7640
7641 return ret;
7642}
7643
7644/**
7645 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7646 * @vsi: VSI structure
7647 **/
7648static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7649{
7650 u8 seed[I40E_HKEY_ARRAY_SIZE];
7651 struct i40e_pf *pf = vsi->back;
7652
7653 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7654 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7655
7656 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7657 return i40e_config_rss_aq(vsi, seed);
7658
7659 return 0;
7660}
7661
7662/**
7663 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7664 * @pf: board private structure
e25d00b8 7665 * @seed: RSS hash seed
41c445ff 7666 **/
e25d00b8 7667static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7668{
66ddcffb 7669 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7670 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7671 u32 *seed_dw = (u32 *)seed;
7672 u32 current_queue = 0;
4617e8c0
ASJ		 7673 u32 lut = 0;
7674 int i, j;
41c445ff 7675
e25d00b8 7676 /* Fill out hash function seed */
41c445ff 7677 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7678 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7679
7680 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7681 lut = 0;
7682 for (j = 0; j < 4; j++) {
7683 if (current_queue == vsi->rss_size)
7684 current_queue = 0;
7685 lut |= ((current_queue) << (8 * j));
7686 current_queue++;
7687 }
7688 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7689 }
7690 i40e_flush(hw);
7691
7692 return 0;
7693}
7694
7695/**
7696 * i40e_config_rss - Prepare for RSS if used
7697 * @pf: board private structure
7698 **/
7699static int i40e_config_rss(struct i40e_pf *pf)
7700{
7701 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7702 u8 seed[I40E_HKEY_ARRAY_SIZE];
7703 struct i40e_hw *hw = &pf->hw;
7704 u32 reg_val;
7705 u64 hena;
7706
7707 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7708
7709 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7710 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7711 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7712 hena |= i40e_pf_get_default_rss_hena(pf);
7713
41c445ff
JB		 7714 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7715 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7716
66ddcffb
ASJ		 7717 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7718
e25d00b8 7719 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7720 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7721 reg_val = (pf->rss_table_size == 512) ?
7722 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7723 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7724 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7725
e25d00b8
ASJ		 7726 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7727 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7728 else
7729 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7730}
7731
f8ff1464
ASJ		 7732/**
7733 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7734 * @pf: board private structure
7735 * @queue_count: the requested queue count for rss.
7736 *
7737 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7738 * count which may be different from the requested queue count.
7739 **/
7740int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7741{
9a3bd2f1
ASJ		 7742 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7743 int new_rss_size;
7744
f8ff1464
ASJ		 7745 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7746 return 0;
7747
9a3bd2f1 7748 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7749
9a3bd2f1
ASJ		 7750 if (queue_count != vsi->num_queue_pairs) {
7751 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7752 i40e_prep_for_reset(pf);
7753
9a3bd2f1 7754 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7755
7756 i40e_reset_and_rebuild(pf, true);
7757 i40e_config_rss(pf);
7758 }
7759 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7760 return pf->rss_size;
7761}
7762
f4492db1
GR		 7763/**
7764 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7765 * @pf: board private structure
7766 **/
7767i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7768{
7769 i40e_status status;
7770 bool min_valid, max_valid;
7771 u32 max_bw, min_bw;
7772
7773 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7774 &min_valid, &max_valid);
7775
7776 if (!status) {
7777 if (min_valid)
7778 pf->npar_min_bw = min_bw;
7779 if (max_valid)
7780 pf->npar_max_bw = max_bw;
7781 }
7782
7783 return status;
7784}
7785
7786/**
7787 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7788 * @pf: board private structure
7789 **/
7790i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7791{
7792 struct i40e_aqc_configure_partition_bw_data bw_data;
7793 i40e_status status;
7794
b40c82e6 7795 /* Set the valid bit for this PF */
41a1d04b 7796 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7797 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7798 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7799
7800 /* Set the new bandwidths */
7801 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7802
7803 return status;
7804}
7805
7806/**
7807 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7808 * @pf: board private structure
7809 **/
7810i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7811{
7812 /* Commit temporary BW setting to permanent NVM image */
7813 enum i40e_admin_queue_err last_aq_status;
7814 i40e_status ret;
7815 u16 nvm_word;
7816
7817 if (pf->hw.partition_id != 1) {
7818 dev_info(&pf->pdev->dev,
7819 "Commit BW only works on partition 1! This is partition %d",
7820 pf->hw.partition_id);
7821 ret = I40E_NOT_SUPPORTED;
7822 goto bw_commit_out;
7823 }
7824
7825 /* Acquire NVM for read access */
7826 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7827 last_aq_status = pf->hw.aq.asq_last_status;
7828 if (ret) {
7829 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7830 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7831 i40e_stat_str(&pf->hw, ret),
7832 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7833 goto bw_commit_out;
7834 }
7835
7836 /* Read word 0x10 of NVM - SW compatibility word 1 */
7837 ret = i40e_aq_read_nvm(&pf->hw,
7838 I40E_SR_NVM_CONTROL_WORD,
7839 0x10, sizeof(nvm_word), &nvm_word,
7840 false, NULL);
7841 /* Save off last admin queue command status before releasing
7842 * the NVM
7843 */
7844 last_aq_status = pf->hw.aq.asq_last_status;
7845 i40e_release_nvm(&pf->hw);
7846 if (ret) {
f1c7e72e
SN		 7847 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7848 i40e_stat_str(&pf->hw, ret),
7849 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7850 goto bw_commit_out;
7851 }
7852
7853 /* Wait a bit for NVM release to complete */
7854 msleep(50);
7855
7856 /* Acquire NVM for write access */
7857 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7858 last_aq_status = pf->hw.aq.asq_last_status;
7859 if (ret) {
7860 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7861 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7862 i40e_stat_str(&pf->hw, ret),
7863 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7864 goto bw_commit_out;
7865 }
7866 /* Write it back out unchanged to initiate update NVM,
7867 * which will force a write of the shadow (alt) RAM to
7868 * the NVM - thus storing the bandwidth values permanently.
7869 */
7870 ret = i40e_aq_update_nvm(&pf->hw,
7871 I40E_SR_NVM_CONTROL_WORD,
7872 0x10, sizeof(nvm_word),
7873 &nvm_word, true, NULL);
7874 /* Save off last admin queue command status before releasing
7875 * the NVM
7876 */
7877 last_aq_status = pf->hw.aq.asq_last_status;
7878 i40e_release_nvm(&pf->hw);
7879 if (ret)
7880 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7881 "BW settings NOT SAVED, err %s aq_err %s\n",
7882 i40e_stat_str(&pf->hw, ret),
7883 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7884bw_commit_out:
7885
7886 return ret;
7887}
7888
41c445ff
JB		 7889/**
7890 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7891 * @pf: board private structure to initialize
7892 *
7893 * i40e_sw_init initializes the Adapter private data structure.
7894 * Fields are initialized based on PCI device information and
7895 * OS network device settings (MTU size).
7896 **/
7897static int i40e_sw_init(struct i40e_pf *pf)
7898{
7899 int err = 0;
7900 int size;
7901
7902 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7903 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7904 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7905 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7906 if (I40E_DEBUG_USER & debug)
7907 pf->hw.debug_mask = debug;
7908 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7909 I40E_DEFAULT_MSG_ENABLE);
7910 }
7911
7912 /* Set default capability flags */
7913 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7914 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7915 I40E_FLAG_MSIX_ENABLED;
7916
7917 if (iommu_present(&pci_bus_type))
7918 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7919 else
7920 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7921
ca99eb99
MW		 7922 /* Set default ITR */
7923 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7924 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7925
7134f9ce
JB		 7926 /* Depending on PF configurations, it is possible that the RSS
7927 * maximum might end up larger than the available queues
7928 */
41a1d04b 7929 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7930 pf->rss_size = 1;
5db4cb59 7931 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7932 pf->rss_size_max = min_t(int, pf->rss_size_max,
7933 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7934 if (pf->hw.func_caps.rss) {
7935 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7936 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7937 }
7938
2050bc65 7939 /* MFP mode enabled */
c78b953e 7940 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7941 pf->flags |= I40E_FLAG_MFP_ENABLED;
7942 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7943 if (i40e_get_npar_bw_setting(pf))
7944 dev_warn(&pf->pdev->dev,
7945 "Could not get NPAR bw settings\n");
7946 else
7947 dev_info(&pf->pdev->dev,
7948 "Min BW = %8.8x, Max BW = %8.8x\n",
7949 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7950 }
7951
cbf61325
ASJ		 7952 /* FW/NVM is not yet fixed in this regard */
7953 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7954 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7955 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7956 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 7957 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7958 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7959 } else {
7960 dev_info(&pf->pdev->dev,
0b67584f 7961 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7962 }
cbf61325
ASJ		 7963 pf->fdir_pf_filter_count =
7964 pf->hw.func_caps.fd_filters_guaranteed;
7965 pf->hw.fdir_shared_filter_count =
7966 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7967 }
7968
7969 if (pf->hw.func_caps.vmdq) {
41c445ff 7970 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 7971 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
41c445ff
JB		 7972 }
7973
38e00438
VD		 7974#ifdef I40E_FCOE
7975 err = i40e_init_pf_fcoe(pf);
7976 if (err)
7977 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7978
7979#endif /* I40E_FCOE */
41c445ff 7980#ifdef CONFIG_PCI_IOV
ba252f13 7981 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7982 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7983 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7984 pf->num_req_vfs = min_t(int,
7985 pf->hw.func_caps.num_vfs,
7986 I40E_MAX_VF_COUNT);
7987 }
7988#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7989 if (pf->hw.mac.type == I40E_MAC_X722) {
7990 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7991 I40E_FLAG_128_QP_RSS_CAPABLE |
7992 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7993 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7994 I40E_FLAG_WB_ON_ITR_CAPABLE |
7995 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
7996 }
41c445ff
JB		 7997 pf->eeprom_version = 0xDEAD;
7998 pf->lan_veb = I40E_NO_VEB;
7999 pf->lan_vsi = I40E_NO_VSI;
8000
8001 /* set up queue assignment tracking */
8002 size = sizeof(struct i40e_lump_tracking)
8003 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8004 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8005 if (!pf->qp_pile) {
8006 err = -ENOMEM;
8007 goto sw_init_done;
8008 }
8009 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8010 pf->qp_pile->search_hint = 0;
8011
327fe04b
ASJ		 8012 pf->tx_timeout_recovery_level = 1;
8013
41c445ff
JB		 8014 mutex_init(&pf->switch_mutex);
8015
c668a12c
GR		 8016 /* If NPAR is enabled nudge the Tx scheduler */
8017 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8018 i40e_set_npar_bw_setting(pf);
8019
41c445ff
JB		 8020sw_init_done:
8021 return err;
8022}
8023
7c3c288b
ASJ		 8024/**
8025 * i40e_set_ntuple - set the ntuple feature flag and take action
8026 * @pf: board private structure to initialize
8027 * @features: the feature set that the stack is suggesting
8028 *
8029 * returns a bool to indicate if reset needs to happen
8030 **/
8031bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8032{
8033 bool need_reset = false;
8034
8035 /* Check if Flow Director n-tuple support was enabled or disabled. If
8036 * the state changed, we need to reset.
8037 */
8038 if (features & NETIF_F_NTUPLE) {
8039 /* Enable filters and mark for reset */
8040 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8041 need_reset = true;
8042 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8043 } else {
8044 /* turn off filters, mark for reset and clear SW filter list */
8045 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8046 need_reset = true;
8047 i40e_fdir_filter_exit(pf);
8048 }
8049 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8050 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8051 /* reset fd counters */
8052 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8053 pf->fdir_pf_active_filters = 0;
8054 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8055 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8056 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8057 /* if ATR was auto disabled it can be re-enabled. */
8058 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8059 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8060 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8061 }
8062 return need_reset;
8063}
8064
41c445ff
JB		 8065/**
8066 * i40e_set_features - set the netdev feature flags
8067 * @netdev: ptr to the netdev being adjusted
8068 * @features: the feature set that the stack is suggesting
8069 **/
8070static int i40e_set_features(struct net_device *netdev,
8071 netdev_features_t features)
8072{
8073 struct i40e_netdev_priv *np = netdev_priv(netdev);
8074 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8075 struct i40e_pf *pf = vsi->back;
8076 bool need_reset;
41c445ff
JB		 8077
8078 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8079 i40e_vlan_stripping_enable(vsi);
8080 else
8081 i40e_vlan_stripping_disable(vsi);
8082
7c3c288b
ASJ		 8083 need_reset = i40e_set_ntuple(pf, features);
8084
8085 if (need_reset)
41a1d04b 8086 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8087
41c445ff
JB		 8088 return 0;
8089}
8090
a1c9a9d9
JK		 8091#ifdef CONFIG_I40E_VXLAN
8092/**
8093 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8094 * @pf: board private structure
8095 * @port: The UDP port to look up
8096 *
8097 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8098 **/
8099static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8100{
8101 u8 i;
8102
8103 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8104 if (pf->vxlan_ports[i] == port)
8105 return i;
8106 }
8107
8108 return i;
8109}
8110
8111/**
8112 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8113 * @netdev: This physical port's netdev
8114 * @sa_family: Socket Family that VXLAN is notifying us about
8115 * @port: New UDP port number that VXLAN started listening to
8116 **/
8117static void i40e_add_vxlan_port(struct net_device *netdev,
8118 sa_family_t sa_family, __be16 port)
8119{
8120 struct i40e_netdev_priv *np = netdev_priv(netdev);
8121 struct i40e_vsi *vsi = np->vsi;
8122 struct i40e_pf *pf = vsi->back;
8123 u8 next_idx;
8124 u8 idx;
8125
8126 if (sa_family == AF_INET6)
8127 return;
8128
8129 idx = i40e_get_vxlan_port_idx(pf, port);
8130
8131 /* Check if port already exists */
8132 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8133 netdev_info(netdev, "vxlan port %d already offloaded\n",
8134 ntohs(port));
a1c9a9d9
JK		 8135 return;
8136 }
8137
8138 /* Now check if there is space to add the new port */
8139 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8140
8141 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8142 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8143 ntohs(port));
8144 return;
8145 }
8146
8147 /* New port: add it and mark its index in the bitmap */
8148 pf->vxlan_ports[next_idx] = port;
41a1d04b 8149 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8150 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8151}
8152
8153/**
8154 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8155 * @netdev: This physical port's netdev
8156 * @sa_family: Socket Family that VXLAN is notifying us about
8157 * @port: UDP port number that VXLAN stopped listening to
8158 **/
8159static void i40e_del_vxlan_port(struct net_device *netdev,
8160 sa_family_t sa_family, __be16 port)
8161{
8162 struct i40e_netdev_priv *np = netdev_priv(netdev);
8163 struct i40e_vsi *vsi = np->vsi;
8164 struct i40e_pf *pf = vsi->back;
8165 u8 idx;
8166
8167 if (sa_family == AF_INET6)
8168 return;
8169
8170 idx = i40e_get_vxlan_port_idx(pf, port);
8171
8172 /* Check if port already exists */
8173 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8174 /* if port exists, set it to 0 (mark for deletion)
8175 * and make it pending
8176 */
8177 pf->vxlan_ports[idx] = 0;
41a1d04b 8178 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8179 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8180 } else {
c22c06c8 8181 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8182 ntohs(port));
8183 }
8184}
8185
8186#endif
1f224ad2 8187static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8188 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8189{
8190 struct i40e_netdev_priv *np = netdev_priv(netdev);
8191 struct i40e_pf *pf = np->vsi->back;
8192 struct i40e_hw *hw = &pf->hw;
8193
8194 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8195 return -EOPNOTSUPP;
8196
8197 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8198 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8199
8200 return 0;
8201}
8202
2f90ade6
JB		 8203/**
8204 * i40e_ndo_fdb_add - add an entry to the hardware database
8205 * @ndm: the input from the stack
8206 * @tb: pointer to array of nladdr (unused)
8207 * @dev: the net device pointer
8208 * @addr: the MAC address entry being added
8209 * @flags: instructions from stack about fdb operation
8210 */
4ba0dea5
GR		 8211static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8212 struct net_device *dev,
f6f6424b 8213 const unsigned char *addr, u16 vid,
4ba0dea5 8214 u16 flags)
4ba0dea5
GR		 8215{
8216 struct i40e_netdev_priv *np = netdev_priv(dev);
8217 struct i40e_pf *pf = np->vsi->back;
8218 int err = 0;
8219
8220 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8221 return -EOPNOTSUPP;
8222
65891fea
OG		 8223 if (vid) {
8224 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8225 return -EINVAL;
8226 }
8227
4ba0dea5
GR		 8228 /* Hardware does not support aging addresses so if a
8229 * ndm_state is given only allow permanent addresses
8230 */
8231 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8232 netdev_info(dev, "FDB only supports static addresses\n");
8233 return -EINVAL;
8234 }
8235
8236 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8237 err = dev_uc_add_excl(dev, addr);
8238 else if (is_multicast_ether_addr(addr))
8239 err = dev_mc_add_excl(dev, addr);
8240 else
8241 err = -EINVAL;
8242
8243 /* Only return duplicate errors if NLM_F_EXCL is set */
8244 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8245 err = 0;
8246
8247 return err;
8248}
8249
51616018
NP		 8250/**
8251 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8252 * @dev: the netdev being configured
8253 * @nlh: RTNL message
8254 *
8255 * Inserts a new hardware bridge if not already created and
8256 * enables the bridging mode requested (VEB or VEPA). If the
8257 * hardware bridge has already been inserted and the request
8258 * is to change the mode then that requires a PF reset to
8259 * allow rebuild of the components with required hardware
8260 * bridge mode enabled.
8261 **/
8262static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8263 struct nlmsghdr *nlh,
8264 u16 flags)
51616018
NP		 8265{
8266 struct i40e_netdev_priv *np = netdev_priv(dev);
8267 struct i40e_vsi *vsi = np->vsi;
8268 struct i40e_pf *pf = vsi->back;
8269 struct i40e_veb *veb = NULL;
8270 struct nlattr *attr, *br_spec;
8271 int i, rem;
8272
8273 /* Only for PF VSI for now */
8274 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8275 return -EOPNOTSUPP;
8276
8277 /* Find the HW bridge for PF VSI */
8278 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8279 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8280 veb = pf->veb[i];
8281 }
8282
8283 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8284
8285 nla_for_each_nested(attr, br_spec, rem) {
8286 __u16 mode;
8287
8288 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8289 continue;
8290
8291 mode = nla_get_u16(attr);
8292 if ((mode != BRIDGE_MODE_VEPA) &&
8293 (mode != BRIDGE_MODE_VEB))
8294 return -EINVAL;
8295
8296 /* Insert a new HW bridge */
8297 if (!veb) {
8298 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8299 vsi->tc_config.enabled_tc);
8300 if (veb) {
8301 veb->bridge_mode = mode;
8302 i40e_config_bridge_mode(veb);
8303 } else {
8304 /* No Bridge HW offload available */
8305 return -ENOENT;
8306 }
8307 break;
8308 } else if (mode != veb->bridge_mode) {
8309 /* Existing HW bridge but different mode needs reset */
8310 veb->bridge_mode = mode;
fc60861e
ASJ		 8311 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8312 if (mode == BRIDGE_MODE_VEB)
8313 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8314 else
8315 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8316 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8317 break;
8318 }
8319 }
8320
8321 return 0;
8322}
8323
8324/**
8325 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8326 * @skb: skb buff
8327 * @pid: process id
8328 * @seq: RTNL message seq #
8329 * @dev: the netdev being configured
8330 * @filter_mask: unused
8331 *
8332 * Return the mode in which the hardware bridge is operating in
8333 * i.e VEB or VEPA.
8334 **/
51616018
NP		 8335static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8336 struct net_device *dev,
7d4f8d87 8337 u32 filter_mask, int nlflags)
51616018
NP		 8338{
8339 struct i40e_netdev_priv *np = netdev_priv(dev);
8340 struct i40e_vsi *vsi = np->vsi;
8341 struct i40e_pf *pf = vsi->back;
8342 struct i40e_veb *veb = NULL;
8343 int i;
8344
8345 /* Only for PF VSI for now */
8346 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8347 return -EOPNOTSUPP;
8348
8349 /* Find the HW bridge for the PF VSI */
8350 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8351 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8352 veb = pf->veb[i];
8353 }
8354
8355 if (!veb)
8356 return 0;
8357
46c264da 8358 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8359 nlflags, 0, 0, filter_mask, NULL);
51616018 8360}
51616018 8361
f44a75e2
JS		 8362#define I40E_MAX_TUNNEL_HDR_LEN 80
8363/**
8364 * i40e_features_check - Validate encapsulated packet conforms to limits
8365 * @skb: skb buff
8366 * @netdev: This physical port's netdev
8367 * @features: Offload features that the stack believes apply
8368 **/
8369static netdev_features_t i40e_features_check(struct sk_buff *skb,
8370 struct net_device *dev,
8371 netdev_features_t features)
8372{
8373 if (skb->encapsulation &&
8374 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8375 I40E_MAX_TUNNEL_HDR_LEN))
8376 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8377
8378 return features;
8379}
8380
37a2973a 8381static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8382 .ndo_open = i40e_open,
8383 .ndo_stop = i40e_close,
8384 .ndo_start_xmit = i40e_lan_xmit_frame,
8385 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8386 .ndo_set_rx_mode = i40e_set_rx_mode,
8387 .ndo_validate_addr = eth_validate_addr,
8388 .ndo_set_mac_address = i40e_set_mac,
8389 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8390 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8391 .ndo_tx_timeout = i40e_tx_timeout,
8392 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8393 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8394#ifdef CONFIG_NET_POLL_CONTROLLER
8395 .ndo_poll_controller = i40e_netpoll,
8396#endif
8397 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8398#ifdef I40E_FCOE
8399 .ndo_fcoe_enable = i40e_fcoe_enable,
8400 .ndo_fcoe_disable = i40e_fcoe_disable,
8401#endif
41c445ff
JB		 8402 .ndo_set_features = i40e_set_features,
8403 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8404 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8405 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8406 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8407 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8408 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8409#ifdef CONFIG_I40E_VXLAN
8410 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8411 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8412#endif
1f224ad2 8413 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8414 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8415 .ndo_features_check = i40e_features_check,
51616018
NP		 8416 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8417 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8418};
8419
8420/**
8421 * i40e_config_netdev - Setup the netdev flags
8422 * @vsi: the VSI being configured
8423 *
8424 * Returns 0 on success, negative value on failure
8425 **/
8426static int i40e_config_netdev(struct i40e_vsi *vsi)
8427{
1a10370a 8428 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8429 struct i40e_pf *pf = vsi->back;
8430 struct i40e_hw *hw = &pf->hw;
8431 struct i40e_netdev_priv *np;
8432 struct net_device *netdev;
8433 u8 mac_addr[ETH_ALEN];
8434 int etherdev_size;
8435
8436 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8437 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8438 if (!netdev)
8439 return -ENOMEM;
8440
8441 vsi->netdev = netdev;
8442 np = netdev_priv(netdev);
8443 np->vsi = vsi;
8444
d70e941b 8445 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8446 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8447 NETIF_F_TSO;
41c445ff
JB		 8448
8449 netdev->features = NETIF_F_SG |
8450 NETIF_F_IP_CSUM |
8451 NETIF_F_SCTP_CSUM |
8452 NETIF_F_HIGHDMA |
8453 NETIF_F_GSO_UDP_TUNNEL |
8454 NETIF_F_HW_VLAN_CTAG_TX |
8455 NETIF_F_HW_VLAN_CTAG_RX |
8456 NETIF_F_HW_VLAN_CTAG_FILTER |
8457 NETIF_F_IPV6_CSUM |
8458 NETIF_F_TSO |
059dab69 8459 NETIF_F_TSO_ECN |
41c445ff
JB		 8460 NETIF_F_TSO6 |
8461 NETIF_F_RXCSUM |
8462 NETIF_F_RXHASH |
8463 0;
8464
2e86a0b6
ASJ		 8465 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8466 netdev->features |= NETIF_F_NTUPLE;
8467
41c445ff
JB		 8468 /* copy netdev features into list of user selectable features */
8469 netdev->hw_features |= netdev->features;
8470
8471 if (vsi->type == I40E_VSI_MAIN) {
8472 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8473 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8474 /* The following steps are necessary to prevent reception
8475 * of tagged packets - some older NVM configurations load a
8476 * default a MAC-VLAN filter that accepts any tagged packet
8477 * which must be replaced by a normal filter.
8c27d42e 8478 */
30650cc5
SN		 8479 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8480 i40e_add_filter(vsi, mac_addr,
8481 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8482 } else {
8483 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8484 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8485 pf->vsi[pf->lan_vsi]->netdev->name);
8486 random_ether_addr(mac_addr);
8487 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8488 }
1a10370a 8489 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8490
9a173901
GR		 8491 ether_addr_copy(netdev->dev_addr, mac_addr);
8492 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8493 /* vlan gets same features (except vlan offload)
8494 * after any tweaks for specific VSI types
8495 */
8496 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8497 NETIF_F_HW_VLAN_CTAG_RX |
8498 NETIF_F_HW_VLAN_CTAG_FILTER);
8499 netdev->priv_flags |= IFF_UNICAST_FLT;
8500 netdev->priv_flags |= IFF_SUPP_NOFCS;
8501 /* Setup netdev TC information */
8502 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8503
8504 netdev->netdev_ops = &i40e_netdev_ops;
8505 netdev->watchdog_timeo = 5 * HZ;
8506 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8507#ifdef I40E_FCOE
8508 i40e_fcoe_config_netdev(netdev, vsi);
8509#endif
41c445ff
JB		 8510
8511 return 0;
8512}
8513
8514/**
8515 * i40e_vsi_delete - Delete a VSI from the switch
8516 * @vsi: the VSI being removed
8517 *
8518 * Returns 0 on success, negative value on failure
8519 **/
8520static void i40e_vsi_delete(struct i40e_vsi *vsi)
8521{
8522 /* remove default VSI is not allowed */
8523 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8524 return;
8525
41c445ff 8526 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8527}
8528
51616018
NP		 8529/**
8530 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8531 * @vsi: the VSI being queried
8532 *
8533 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8534 **/
8535int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8536{
8537 struct i40e_veb *veb;
8538 struct i40e_pf *pf = vsi->back;
8539
8540 /* Uplink is not a bridge so default to VEB */
8541 if (vsi->veb_idx == I40E_NO_VEB)
8542 return 1;
8543
8544 veb = pf->veb[vsi->veb_idx];
8545 /* Uplink is a bridge in VEPA mode */
8546 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8547 return 0;
8548
8549 /* Uplink is a bridge in VEB mode */
8550 return 1;
8551}
8552
41c445ff
JB		 8553/**
8554 * i40e_add_vsi - Add a VSI to the switch
8555 * @vsi: the VSI being configured
8556 *
8557 * This initializes a VSI context depending on the VSI type to be added and
8558 * passes it down to the add_vsi aq command.
8559 **/
8560static int i40e_add_vsi(struct i40e_vsi *vsi)
8561{
8562 int ret = -ENODEV;
8563 struct i40e_mac_filter *f, *ftmp;
8564 struct i40e_pf *pf = vsi->back;
8565 struct i40e_hw *hw = &pf->hw;
8566 struct i40e_vsi_context ctxt;
8567 u8 enabled_tc = 0x1; /* TC0 enabled */
8568 int f_count = 0;
8569
8570 memset(&ctxt, 0, sizeof(ctxt));
8571 switch (vsi->type) {
8572 case I40E_VSI_MAIN:
8573 /* The PF's main VSI is already setup as part of the
8574 * device initialization, so we'll not bother with
8575 * the add_vsi call, but we will retrieve the current
8576 * VSI context.
8577 */
8578 ctxt.seid = pf->main_vsi_seid;
8579 ctxt.pf_num = pf->hw.pf_id;
8580 ctxt.vf_num = 0;
8581 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8582 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8583 if (ret) {
8584 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8585 "couldn't get PF vsi config, err %s aq_err %s\n",
8586 i40e_stat_str(&pf->hw, ret),
8587 i40e_aq_str(&pf->hw,
8588 pf->hw.aq.asq_last_status));
41c445ff
JB		 8589 return -ENOENT;
8590 }
1a2f6248 8591 vsi->info = ctxt.info;
41c445ff
JB		 8592 vsi->info.valid_sections = 0;
8593
8594 vsi->seid = ctxt.seid;
8595 vsi->id = ctxt.vsi_number;
8596
8597 enabled_tc = i40e_pf_get_tc_map(pf);
8598
8599 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8600 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8601 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8602 memset(&ctxt, 0, sizeof(ctxt));
8603 ctxt.seid = pf->main_vsi_seid;
8604 ctxt.pf_num = pf->hw.pf_id;
8605 ctxt.vf_num = 0;
8606 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8607 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8608 if (ret) {
8609 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8610 "update vsi failed, err %s aq_err %s\n",
8611 i40e_stat_str(&pf->hw, ret),
8612 i40e_aq_str(&pf->hw,
8613 pf->hw.aq.asq_last_status));
41c445ff
JB		 8614 ret = -ENOENT;
8615 goto err;
8616 }
8617 /* update the local VSI info queue map */
8618 i40e_vsi_update_queue_map(vsi, &ctxt);
8619 vsi->info.valid_sections = 0;
8620 } else {
8621 /* Default/Main VSI is only enabled for TC0
8622 * reconfigure it to enable all TCs that are
8623 * available on the port in SFP mode.
63d7e5a4
NP		 8624 * For MFP case the iSCSI PF would use this
8625 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8626 */
8627 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8628 if (ret) {
8629 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8630 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8631 enabled_tc,
8632 i40e_stat_str(&pf->hw, ret),
8633 i40e_aq_str(&pf->hw,
8634 pf->hw.aq.asq_last_status));
41c445ff
JB		 8635 ret = -ENOENT;
8636 }
8637 }
8638 break;
8639
8640 case I40E_VSI_FDIR:
cbf61325
ASJ		 8641 ctxt.pf_num = hw->pf_id;
8642 ctxt.vf_num = 0;
8643 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8644 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8645 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8646 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8647 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8648 ctxt.info.valid_sections |=
fc60861e 8649 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8650 ctxt.info.switch_id =
fc60861e 8651 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8652 }
41c445ff 8653 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8654 break;
8655
8656 case I40E_VSI_VMDQ2:
8657 ctxt.pf_num = hw->pf_id;
8658 ctxt.vf_num = 0;
8659 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8660 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8661 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8662
41c445ff
JB		 8663 /* This VSI is connected to VEB so the switch_id
8664 * should be set to zero by default.
8665 */
51616018
NP		 8666 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8667 ctxt.info.valid_sections |=
8668 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8669 ctxt.info.switch_id =
8670 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8671 }
41c445ff
JB		 8672
8673 /* Setup the VSI tx/rx queue map for TC0 only for now */
8674 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8675 break;
8676
8677 case I40E_VSI_SRIOV:
8678 ctxt.pf_num = hw->pf_id;
8679 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8680 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8681 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8682 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8683
41c445ff
JB		 8684 /* This VSI is connected to VEB so the switch_id
8685 * should be set to zero by default.
8686 */
51616018
NP		 8687 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8688 ctxt.info.valid_sections |=
8689 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8690 ctxt.info.switch_id =
8691 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8692 }
41c445ff
JB		 8693
8694 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8695 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8696 if (pf->vf[vsi->vf_id].spoofchk) {
8697 ctxt.info.valid_sections |=
8698 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8699 ctxt.info.sec_flags |=
8700 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8701 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8702 }
41c445ff
JB		 8703 /* Setup the VSI tx/rx queue map for TC0 only for now */
8704 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8705 break;
8706
38e00438
VD		 8707#ifdef I40E_FCOE
8708 case I40E_VSI_FCOE:
8709 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8710 if (ret) {
8711 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8712 return ret;
8713 }
8714 break;
8715
8716#endif /* I40E_FCOE */
41c445ff
JB		 8717 default:
8718 return -ENODEV;
8719 }
8720
8721 if (vsi->type != I40E_VSI_MAIN) {
8722 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8723 if (ret) {
8724 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8725 "add vsi failed, err %s aq_err %s\n",
8726 i40e_stat_str(&pf->hw, ret),
8727 i40e_aq_str(&pf->hw,
8728 pf->hw.aq.asq_last_status));
41c445ff
JB		 8729 ret = -ENOENT;
8730 goto err;
8731 }
1a2f6248 8732 vsi->info = ctxt.info;
41c445ff
JB		 8733 vsi->info.valid_sections = 0;
8734 vsi->seid = ctxt.seid;
8735 vsi->id = ctxt.vsi_number;
8736 }
8737
8738 /* If macvlan filters already exist, force them to get loaded */
8739 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8740 f->changed = true;
8741 f_count++;
6252c7e4
SN		 8742
8743 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8744 struct i40e_aqc_remove_macvlan_element_data element;
8745
8746 memset(&element, 0, sizeof(element));
8747 ether_addr_copy(element.mac_addr, f->macaddr);
8748 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8749 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8750 &element, 1, NULL);
8751 if (ret) {
8752 /* some older FW has a different default */
8753 element.flags |=
8754 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8755 i40e_aq_remove_macvlan(hw, vsi->seid,
8756 &element, 1, NULL);
8757 }
8758
8759 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8760 I40E_AQC_WRITE_TYPE_LAA_WOL,
8761 f->macaddr, NULL);
8762 }
41c445ff
JB		 8763 }
8764 if (f_count) {
8765 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8766 pf->flags |= I40E_FLAG_FILTER_SYNC;
8767 }
8768
8769 /* Update VSI BW information */
8770 ret = i40e_vsi_get_bw_info(vsi);
8771 if (ret) {
8772 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8773 "couldn't get vsi bw info, err %s aq_err %s\n",
8774 i40e_stat_str(&pf->hw, ret),
8775 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8776 /* VSI is already added so not tearing that up */
8777 ret = 0;
8778 }
8779
8780err:
8781 return ret;
8782}
8783
8784/**
8785 * i40e_vsi_release - Delete a VSI and free its resources
8786 * @vsi: the VSI being removed
8787 *
8788 * Returns 0 on success or < 0 on error
8789 **/
8790int i40e_vsi_release(struct i40e_vsi *vsi)
8791{
8792 struct i40e_mac_filter *f, *ftmp;
8793 struct i40e_veb *veb = NULL;
8794 struct i40e_pf *pf;
8795 u16 uplink_seid;
8796 int i, n;
8797
8798 pf = vsi->back;
8799
8800 /* release of a VEB-owner or last VSI is not allowed */
8801 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8802 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8803 vsi->seid, vsi->uplink_seid);
8804 return -ENODEV;
8805 }
8806 if (vsi == pf->vsi[pf->lan_vsi] &&
8807 !test_bit(__I40E_DOWN, &pf->state)) {
8808 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8809 return -ENODEV;
8810 }
8811
8812 uplink_seid = vsi->uplink_seid;
8813 if (vsi->type != I40E_VSI_SRIOV) {
8814 if (vsi->netdev_registered) {
8815 vsi->netdev_registered = false;
8816 if (vsi->netdev) {
8817 /* results in a call to i40e_close() */
8818 unregister_netdev(vsi->netdev);
41c445ff
JB		 8819 }
8820 } else {
90ef8d47 8821 i40e_vsi_close(vsi);
41c445ff
JB		 8822 }
8823 i40e_vsi_disable_irq(vsi);
8824 }
8825
8826 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8827 i40e_del_filter(vsi, f->macaddr, f->vlan,
8828 f->is_vf, f->is_netdev);
30e2561b 8829 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 8830
8831 i40e_vsi_delete(vsi);
8832 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8833 if (vsi->netdev) {
8834 free_netdev(vsi->netdev);
8835 vsi->netdev = NULL;
8836 }
41c445ff
JB		 8837 i40e_vsi_clear_rings(vsi);
8838 i40e_vsi_clear(vsi);
8839
8840 /* If this was the last thing on the VEB, except for the
8841 * controlling VSI, remove the VEB, which puts the controlling
8842 * VSI onto the next level down in the switch.
8843 *
8844 * Well, okay, there's one more exception here: don't remove
8845 * the orphan VEBs yet. We'll wait for an explicit remove request
8846 * from up the network stack.
8847 */
505682cd 8848 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8849 if (pf->vsi[i] &&
8850 pf->vsi[i]->uplink_seid == uplink_seid &&
8851 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8852 n++; /* count the VSIs */
8853 }
8854 }
8855 for (i = 0; i < I40E_MAX_VEB; i++) {
8856 if (!pf->veb[i])
8857 continue;
8858 if (pf->veb[i]->uplink_seid == uplink_seid)
8859 n++; /* count the VEBs */
8860 if (pf->veb[i]->seid == uplink_seid)
8861 veb = pf->veb[i];
8862 }
8863 if (n == 0 && veb && veb->uplink_seid != 0)
8864 i40e_veb_release(veb);
8865
8866 return 0;
8867}
8868
8869/**
8870 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8871 * @vsi: ptr to the VSI
8872 *
8873 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8874 * corresponding SW VSI structure and initializes num_queue_pairs for the
8875 * newly allocated VSI.
8876 *
8877 * Returns 0 on success or negative on failure
8878 **/
8879static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8880{
8881 int ret = -ENOENT;
8882 struct i40e_pf *pf = vsi->back;
8883
493fb300 8884 if (vsi->q_vectors[0]) {
41c445ff
JB		 8885 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8886 vsi->seid);
8887 return -EEXIST;
8888 }
8889
8890 if (vsi->base_vector) {
f29eaa3d 8891 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8892 vsi->seid, vsi->base_vector);
8893 return -EEXIST;
8894 }
8895
90e04070 8896 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8897 if (ret) {
8898 dev_info(&pf->pdev->dev,
8899 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8900 vsi->num_q_vectors, vsi->seid, ret);
8901 vsi->num_q_vectors = 0;
8902 goto vector_setup_out;
8903 }
8904
26cdc443
ASJ		 8905 /* In Legacy mode, we do not have to get any other vector since we
8906 * piggyback on the misc/ICR0 for queue interrupts.
8907 */
8908 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
8909 return ret;
958a3e3b
SN		 8910 if (vsi->num_q_vectors)
8911 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8912 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8913 if (vsi->base_vector < 0) {
8914 dev_info(&pf->pdev->dev,
049a2be8
SN		 8915 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8916 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8917 i40e_vsi_free_q_vectors(vsi);
8918 ret = -ENOENT;
8919 goto vector_setup_out;
8920 }
8921
8922vector_setup_out:
8923 return ret;
8924}
8925
bc7d338f
ASJ		 8926/**
8927 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8928 * @vsi: pointer to the vsi.
8929 *
8930 * This re-allocates a vsi's queue resources.
8931 *
8932 * Returns pointer to the successfully allocated and configured VSI sw struct
8933 * on success, otherwise returns NULL on failure.
8934 **/
8935static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8936{
8937 struct i40e_pf *pf = vsi->back;
8938 u8 enabled_tc;
8939 int ret;
8940
8941 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8942 i40e_vsi_clear_rings(vsi);
8943
8944 i40e_vsi_free_arrays(vsi, false);
8945 i40e_set_num_rings_in_vsi(vsi);
8946 ret = i40e_vsi_alloc_arrays(vsi, false);
8947 if (ret)
8948 goto err_vsi;
8949
8950 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8951 if (ret < 0) {
049a2be8 8952 dev_info(&pf->pdev->dev,
f1c7e72e 8953 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8954 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8955 goto err_vsi;
8956 }
8957 vsi->base_queue = ret;
8958
8959 /* Update the FW view of the VSI. Force a reset of TC and queue
8960 * layout configurations.
8961 */
8962 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8963 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8964 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8965 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8966
8967 /* assign it some queues */
8968 ret = i40e_alloc_rings(vsi);
8969 if (ret)
8970 goto err_rings;
8971
8972 /* map all of the rings to the q_vectors */
8973 i40e_vsi_map_rings_to_vectors(vsi);
8974 return vsi;
8975
8976err_rings:
8977 i40e_vsi_free_q_vectors(vsi);
8978 if (vsi->netdev_registered) {
8979 vsi->netdev_registered = false;
8980 unregister_netdev(vsi->netdev);
8981 free_netdev(vsi->netdev);
8982 vsi->netdev = NULL;
8983 }
8984 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8985err_vsi:
8986 i40e_vsi_clear(vsi);
8987 return NULL;
8988}
8989
41c445ff
JB		 8990/**
8991 * i40e_vsi_setup - Set up a VSI by a given type
8992 * @pf: board private structure
8993 * @type: VSI type
8994 * @uplink_seid: the switch element to link to
8995 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8996 *
8997 * This allocates the sw VSI structure and its queue resources, then add a VSI
8998 * to the identified VEB.
8999 *
9000 * Returns pointer to the successfully allocated and configure VSI sw struct on
9001 * success, otherwise returns NULL on failure.
9002 **/
9003struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9004 u16 uplink_seid, u32 param1)
9005{
9006 struct i40e_vsi *vsi = NULL;
9007 struct i40e_veb *veb = NULL;
9008 int ret, i;
9009 int v_idx;
9010
9011 /* The requested uplink_seid must be either
9012 * - the PF's port seid
9013 * no VEB is needed because this is the PF
9014 * or this is a Flow Director special case VSI
9015 * - seid of an existing VEB
9016 * - seid of a VSI that owns an existing VEB
9017 * - seid of a VSI that doesn't own a VEB
9018 * a new VEB is created and the VSI becomes the owner
9019 * - seid of the PF VSI, which is what creates the first VEB
9020 * this is a special case of the previous
9021 *
9022 * Find which uplink_seid we were given and create a new VEB if needed
9023 */
9024 for (i = 0; i < I40E_MAX_VEB; i++) {
9025 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9026 veb = pf->veb[i];
9027 break;
9028 }
9029 }
9030
9031 if (!veb && uplink_seid != pf->mac_seid) {
9032
505682cd 9033 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9034 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9035 vsi = pf->vsi[i];
9036 break;
9037 }
9038 }
9039 if (!vsi) {
9040 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9041 uplink_seid);
9042 return NULL;
9043 }
9044
9045 if (vsi->uplink_seid == pf->mac_seid)
9046 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9047 vsi->tc_config.enabled_tc);
9048 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9049 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9050 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9051 if (veb) {
9052 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9053 dev_info(&vsi->back->pdev->dev,
9054 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
9055 __func__);
9056 return NULL;
9057 }
fa11cb3d
ASJ		 9058 /* We come up by default in VEPA mode if SRIOV is not
9059 * already enabled, in which case we can't force VEPA
9060 * mode.
9061 */
9062 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9063 veb->bridge_mode = BRIDGE_MODE_VEPA;
9064 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9065 }
51616018 9066 i40e_config_bridge_mode(veb);
79c21a82 9067 }
41c445ff
JB		 9068 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9069 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9070 veb = pf->veb[i];
9071 }
9072 if (!veb) {
9073 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9074 return NULL;
9075 }
9076
9077 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9078 uplink_seid = veb->seid;
9079 }
9080
9081 /* get vsi sw struct */
9082 v_idx = i40e_vsi_mem_alloc(pf, type);
9083 if (v_idx < 0)
9084 goto err_alloc;
9085 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9086 if (!vsi)
9087 goto err_alloc;
41c445ff
JB		 9088 vsi->type = type;
9089 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9090
9091 if (type == I40E_VSI_MAIN)
9092 pf->lan_vsi = v_idx;
9093 else if (type == I40E_VSI_SRIOV)
9094 vsi->vf_id = param1;
9095 /* assign it some queues */
cbf61325
ASJ		 9096 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9097 vsi->idx);
41c445ff 9098 if (ret < 0) {
049a2be8
SN		 9099 dev_info(&pf->pdev->dev,
9100 "failed to get tracking for %d queues for VSI %d err=%d\n",
9101 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9102 goto err_vsi;
9103 }
9104 vsi->base_queue = ret;
9105
9106 /* get a VSI from the hardware */
9107 vsi->uplink_seid = uplink_seid;
9108 ret = i40e_add_vsi(vsi);
9109 if (ret)
9110 goto err_vsi;
9111
9112 switch (vsi->type) {
9113 /* setup the netdev if needed */
9114 case I40E_VSI_MAIN:
9115 case I40E_VSI_VMDQ2:
38e00438 9116 case I40E_VSI_FCOE:
41c445ff
JB		 9117 ret = i40e_config_netdev(vsi);
9118 if (ret)
9119 goto err_netdev;
9120 ret = register_netdev(vsi->netdev);
9121 if (ret)
9122 goto err_netdev;
9123 vsi->netdev_registered = true;
9124 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9125#ifdef CONFIG_I40E_DCB
9126 /* Setup DCB netlink interface */
9127 i40e_dcbnl_setup(vsi);
9128#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9129 /* fall through */
9130
9131 case I40E_VSI_FDIR:
9132 /* set up vectors and rings if needed */
9133 ret = i40e_vsi_setup_vectors(vsi);
9134 if (ret)
9135 goto err_msix;
9136
9137 ret = i40e_alloc_rings(vsi);
9138 if (ret)
9139 goto err_rings;
9140
9141 /* map all of the rings to the q_vectors */
9142 i40e_vsi_map_rings_to_vectors(vsi);
9143
9144 i40e_vsi_reset_stats(vsi);
9145 break;
9146
9147 default:
9148 /* no netdev or rings for the other VSI types */
9149 break;
9150 }
9151
e25d00b8
ASJ		 9152 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9153 (vsi->type == I40E_VSI_VMDQ2)) {
9154 ret = i40e_vsi_config_rss(vsi);
9155 }
41c445ff
JB		 9156 return vsi;
9157
9158err_rings:
9159 i40e_vsi_free_q_vectors(vsi);
9160err_msix:
9161 if (vsi->netdev_registered) {
9162 vsi->netdev_registered = false;
9163 unregister_netdev(vsi->netdev);
9164 free_netdev(vsi->netdev);
9165 vsi->netdev = NULL;
9166 }
9167err_netdev:
9168 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9169err_vsi:
9170 i40e_vsi_clear(vsi);
9171err_alloc:
9172 return NULL;
9173}
9174
9175/**
9176 * i40e_veb_get_bw_info - Query VEB BW information
9177 * @veb: the veb to query
9178 *
9179 * Query the Tx scheduler BW configuration data for given VEB
9180 **/
9181static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9182{
9183 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9184 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9185 struct i40e_pf *pf = veb->pf;
9186 struct i40e_hw *hw = &pf->hw;
9187 u32 tc_bw_max;
9188 int ret = 0;
9189 int i;
9190
9191 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9192 &bw_data, NULL);
9193 if (ret) {
9194 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9195 "query veb bw config failed, err %s aq_err %s\n",
9196 i40e_stat_str(&pf->hw, ret),
9197 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9198 goto out;
9199 }
9200
9201 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9202 &ets_data, NULL);
9203 if (ret) {
9204 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9205 "query veb bw ets config failed, err %s aq_err %s\n",
9206 i40e_stat_str(&pf->hw, ret),
9207 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9208 goto out;
9209 }
9210
9211 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9212 veb->bw_max_quanta = ets_data.tc_bw_max;
9213 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9214 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9215 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9216 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9217 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9218 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9219 veb->bw_tc_limit_credits[i] =
9220 le16_to_cpu(bw_data.tc_bw_limits[i]);
9221 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9222 }
9223
9224out:
9225 return ret;
9226}
9227
9228/**
9229 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9230 * @pf: board private structure
9231 *
9232 * On error: returns error code (negative)
9233 * On success: returns vsi index in PF (positive)
9234 **/
9235static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9236{
9237 int ret = -ENOENT;
9238 struct i40e_veb *veb;
9239 int i;
9240
9241 /* Need to protect the allocation of switch elements at the PF level */
9242 mutex_lock(&pf->switch_mutex);
9243
9244 /* VEB list may be fragmented if VEB creation/destruction has
9245 * been happening. We can afford to do a quick scan to look
9246 * for any free slots in the list.
9247 *
9248 * find next empty veb slot, looping back around if necessary
9249 */
9250 i = 0;
9251 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9252 i++;
9253 if (i >= I40E_MAX_VEB) {
9254 ret = -ENOMEM;
9255 goto err_alloc_veb; /* out of VEB slots! */
9256 }
9257
9258 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9259 if (!veb) {
9260 ret = -ENOMEM;
9261 goto err_alloc_veb;
9262 }
9263 veb->pf = pf;
9264 veb->idx = i;
9265 veb->enabled_tc = 1;
9266
9267 pf->veb[i] = veb;
9268 ret = i;
9269err_alloc_veb:
9270 mutex_unlock(&pf->switch_mutex);
9271 return ret;
9272}
9273
9274/**
9275 * i40e_switch_branch_release - Delete a branch of the switch tree
9276 * @branch: where to start deleting
9277 *
9278 * This uses recursion to find the tips of the branch to be
9279 * removed, deleting until we get back to and can delete this VEB.
9280 **/
9281static void i40e_switch_branch_release(struct i40e_veb *branch)
9282{
9283 struct i40e_pf *pf = branch->pf;
9284 u16 branch_seid = branch->seid;
9285 u16 veb_idx = branch->idx;
9286 int i;
9287
9288 /* release any VEBs on this VEB - RECURSION */
9289 for (i = 0; i < I40E_MAX_VEB; i++) {
9290 if (!pf->veb[i])
9291 continue;
9292 if (pf->veb[i]->uplink_seid == branch->seid)
9293 i40e_switch_branch_release(pf->veb[i]);
9294 }
9295
9296 /* Release the VSIs on this VEB, but not the owner VSI.
9297 *
9298 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9299 * the VEB itself, so don't use (*branch) after this loop.
9300 */
505682cd 9301 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9302 if (!pf->vsi[i])
9303 continue;
9304 if (pf->vsi[i]->uplink_seid == branch_seid &&
9305 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9306 i40e_vsi_release(pf->vsi[i]);
9307 }
9308 }
9309
9310 /* There's one corner case where the VEB might not have been
9311 * removed, so double check it here and remove it if needed.
9312 * This case happens if the veb was created from the debugfs
9313 * commands and no VSIs were added to it.
9314 */
9315 if (pf->veb[veb_idx])
9316 i40e_veb_release(pf->veb[veb_idx]);
9317}
9318
9319/**
9320 * i40e_veb_clear - remove veb struct
9321 * @veb: the veb to remove
9322 **/
9323static void i40e_veb_clear(struct i40e_veb *veb)
9324{
9325 if (!veb)
9326 return;
9327
9328 if (veb->pf) {
9329 struct i40e_pf *pf = veb->pf;
9330
9331 mutex_lock(&pf->switch_mutex);
9332 if (pf->veb[veb->idx] == veb)
9333 pf->veb[veb->idx] = NULL;
9334 mutex_unlock(&pf->switch_mutex);
9335 }
9336
9337 kfree(veb);
9338}
9339
9340/**
9341 * i40e_veb_release - Delete a VEB and free its resources
9342 * @veb: the VEB being removed
9343 **/
9344void i40e_veb_release(struct i40e_veb *veb)
9345{
9346 struct i40e_vsi *vsi = NULL;
9347 struct i40e_pf *pf;
9348 int i, n = 0;
9349
9350 pf = veb->pf;
9351
9352 /* find the remaining VSI and check for extras */
505682cd 9353 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9354 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9355 n++;
9356 vsi = pf->vsi[i];
9357 }
9358 }
9359 if (n != 1) {
9360 dev_info(&pf->pdev->dev,
9361 "can't remove VEB %d with %d VSIs left\n",
9362 veb->seid, n);
9363 return;
9364 }
9365
9366 /* move the remaining VSI to uplink veb */
9367 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9368 if (veb->uplink_seid) {
9369 vsi->uplink_seid = veb->uplink_seid;
9370 if (veb->uplink_seid == pf->mac_seid)
9371 vsi->veb_idx = I40E_NO_VEB;
9372 else
9373 vsi->veb_idx = veb->veb_idx;
9374 } else {
9375 /* floating VEB */
9376 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9377 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9378 }
9379
9380 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9381 i40e_veb_clear(veb);
41c445ff
JB		 9382}
9383
9384/**
9385 * i40e_add_veb - create the VEB in the switch
9386 * @veb: the VEB to be instantiated
9387 * @vsi: the controlling VSI
9388 **/
9389static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9390{
f1c7e72e 9391 struct i40e_pf *pf = veb->pf;
92faef85 9392 bool is_default = veb->pf->cur_promisc;
e1c51b95 9393 bool is_cloud = false;
41c445ff
JB		 9394 int ret;
9395
9396 /* get a VEB from the hardware */
f1c7e72e 9397 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9398 veb->enabled_tc, is_default,
9399 is_cloud, &veb->seid, NULL);
41c445ff 9400 if (ret) {
f1c7e72e
SN		 9401 dev_info(&pf->pdev->dev,
9402 "couldn't add VEB, err %s aq_err %s\n",
9403 i40e_stat_str(&pf->hw, ret),
9404 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9405 return -EPERM;
9406 }
9407
9408 /* get statistics counter */
f1c7e72e 9409 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9410 &veb->stats_idx, NULL, NULL, NULL);
9411 if (ret) {
f1c7e72e
SN		 9412 dev_info(&pf->pdev->dev,
9413 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9414 i40e_stat_str(&pf->hw, ret),
9415 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9416 return -EPERM;
9417 }
9418 ret = i40e_veb_get_bw_info(veb);
9419 if (ret) {
f1c7e72e
SN		 9420 dev_info(&pf->pdev->dev,
9421 "couldn't get VEB bw info, err %s aq_err %s\n",
9422 i40e_stat_str(&pf->hw, ret),
9423 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9424 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9425 return -ENOENT;
9426 }
9427
9428 vsi->uplink_seid = veb->seid;
9429 vsi->veb_idx = veb->idx;
9430 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9431
9432 return 0;
9433}
9434
9435/**
9436 * i40e_veb_setup - Set up a VEB
9437 * @pf: board private structure
9438 * @flags: VEB setup flags
9439 * @uplink_seid: the switch element to link to
9440 * @vsi_seid: the initial VSI seid
9441 * @enabled_tc: Enabled TC bit-map
9442 *
9443 * This allocates the sw VEB structure and links it into the switch
9444 * It is possible and legal for this to be a duplicate of an already
9445 * existing VEB. It is also possible for both uplink and vsi seids
9446 * to be zero, in order to create a floating VEB.
9447 *
9448 * Returns pointer to the successfully allocated VEB sw struct on
9449 * success, otherwise returns NULL on failure.
9450 **/
9451struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9452 u16 uplink_seid, u16 vsi_seid,
9453 u8 enabled_tc)
9454{
9455 struct i40e_veb *veb, *uplink_veb = NULL;
9456 int vsi_idx, veb_idx;
9457 int ret;
9458
9459 /* if one seid is 0, the other must be 0 to create a floating relay */
9460 if ((uplink_seid == 0 || vsi_seid == 0) &&
9461 (uplink_seid + vsi_seid != 0)) {
9462 dev_info(&pf->pdev->dev,
9463 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9464 uplink_seid, vsi_seid);
9465 return NULL;
9466 }
9467
9468 /* make sure there is such a vsi and uplink */
505682cd 9469 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9470 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9471 break;
505682cd 9472 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9473 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9474 vsi_seid);
9475 return NULL;
9476 }
9477
9478 if (uplink_seid && uplink_seid != pf->mac_seid) {
9479 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9480 if (pf->veb[veb_idx] &&
9481 pf->veb[veb_idx]->seid == uplink_seid) {
9482 uplink_veb = pf->veb[veb_idx];
9483 break;
9484 }
9485 }
9486 if (!uplink_veb) {
9487 dev_info(&pf->pdev->dev,
9488 "uplink seid %d not found\n", uplink_seid);
9489 return NULL;
9490 }
9491 }
9492
9493 /* get veb sw struct */
9494 veb_idx = i40e_veb_mem_alloc(pf);
9495 if (veb_idx < 0)
9496 goto err_alloc;
9497 veb = pf->veb[veb_idx];
9498 veb->flags = flags;
9499 veb->uplink_seid = uplink_seid;
9500 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9501 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9502
9503 /* create the VEB in the switch */
9504 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9505 if (ret)
9506 goto err_veb;
1bb8b935
SN		 9507 if (vsi_idx == pf->lan_vsi)
9508 pf->lan_veb = veb->idx;
41c445ff
JB		 9509
9510 return veb;
9511
9512err_veb:
9513 i40e_veb_clear(veb);
9514err_alloc:
9515 return NULL;
9516}
9517
9518/**
b40c82e6 9519 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9520 * @pf: board private structure
9521 * @ele: element we are building info from
9522 * @num_reported: total number of elements
9523 * @printconfig: should we print the contents
9524 *
9525 * helper function to assist in extracting a few useful SEID values.
9526 **/
9527static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9528 struct i40e_aqc_switch_config_element_resp *ele,
9529 u16 num_reported, bool printconfig)
9530{
9531 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9532 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9533 u8 element_type = ele->element_type;
9534 u16 seid = le16_to_cpu(ele->seid);
9535
9536 if (printconfig)
9537 dev_info(&pf->pdev->dev,
9538 "type=%d seid=%d uplink=%d downlink=%d\n",
9539 element_type, seid, uplink_seid, downlink_seid);
9540
9541 switch (element_type) {
9542 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9543 pf->mac_seid = seid;
9544 break;
9545 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9546 /* Main VEB? */
9547 if (uplink_seid != pf->mac_seid)
9548 break;
9549 if (pf->lan_veb == I40E_NO_VEB) {
9550 int v;
9551
9552 /* find existing or else empty VEB */
9553 for (v = 0; v < I40E_MAX_VEB; v++) {
9554 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9555 pf->lan_veb = v;
9556 break;
9557 }
9558 }
9559 if (pf->lan_veb == I40E_NO_VEB) {
9560 v = i40e_veb_mem_alloc(pf);
9561 if (v < 0)
9562 break;
9563 pf->lan_veb = v;
9564 }
9565 }
9566
9567 pf->veb[pf->lan_veb]->seid = seid;
9568 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9569 pf->veb[pf->lan_veb]->pf = pf;
9570 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9571 break;
9572 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9573 if (num_reported != 1)
9574 break;
9575 /* This is immediately after a reset so we can assume this is
9576 * the PF's VSI
9577 */
9578 pf->mac_seid = uplink_seid;
9579 pf->pf_seid = downlink_seid;
9580 pf->main_vsi_seid = seid;
9581 if (printconfig)
9582 dev_info(&pf->pdev->dev,
9583 "pf_seid=%d main_vsi_seid=%d\n",
9584 pf->pf_seid, pf->main_vsi_seid);
9585 break;
9586 case I40E_SWITCH_ELEMENT_TYPE_PF:
9587 case I40E_SWITCH_ELEMENT_TYPE_VF:
9588 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9589 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9590 case I40E_SWITCH_ELEMENT_TYPE_PE:
9591 case I40E_SWITCH_ELEMENT_TYPE_PA:
9592 /* ignore these for now */
9593 break;
9594 default:
9595 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9596 element_type, seid);
9597 break;
9598 }
9599}
9600
9601/**
9602 * i40e_fetch_switch_configuration - Get switch config from firmware
9603 * @pf: board private structure
9604 * @printconfig: should we print the contents
9605 *
9606 * Get the current switch configuration from the device and
9607 * extract a few useful SEID values.
9608 **/
9609int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9610{
9611 struct i40e_aqc_get_switch_config_resp *sw_config;
9612 u16 next_seid = 0;
9613 int ret = 0;
9614 u8 *aq_buf;
9615 int i;
9616
9617 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9618 if (!aq_buf)
9619 return -ENOMEM;
9620
9621 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9622 do {
9623 u16 num_reported, num_total;
9624
9625 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9626 I40E_AQ_LARGE_BUF,
9627 &next_seid, NULL);
9628 if (ret) {
9629 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9630 "get switch config failed err %s aq_err %s\n",
9631 i40e_stat_str(&pf->hw, ret),
9632 i40e_aq_str(&pf->hw,
9633 pf->hw.aq.asq_last_status));
41c445ff
JB		 9634 kfree(aq_buf);
9635 return -ENOENT;
9636 }
9637
9638 num_reported = le16_to_cpu(sw_config->header.num_reported);
9639 num_total = le16_to_cpu(sw_config->header.num_total);
9640
9641 if (printconfig)
9642 dev_info(&pf->pdev->dev,
9643 "header: %d reported %d total\n",
9644 num_reported, num_total);
9645
41c445ff
JB		 9646 for (i = 0; i < num_reported; i++) {
9647 struct i40e_aqc_switch_config_element_resp *ele =
9648 &sw_config->element[i];
9649
9650 i40e_setup_pf_switch_element(pf, ele, num_reported,
9651 printconfig);
9652 }
9653 } while (next_seid != 0);
9654
9655 kfree(aq_buf);
9656 return ret;
9657}
9658
9659/**
9660 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9661 * @pf: board private structure
bc7d338f 9662 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9663 *
9664 * Returns 0 on success, negative value on failure
9665 **/
bc7d338f 9666static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9667{
9668 int ret;
9669
9670 /* find out what's out there already */
9671 ret = i40e_fetch_switch_configuration(pf, false);
9672 if (ret) {
9673 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9674 "couldn't fetch switch config, err %s aq_err %s\n",
9675 i40e_stat_str(&pf->hw, ret),
9676 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9677 return ret;
9678 }
9679 i40e_pf_reset_stats(pf);
9680
41c445ff 9681 /* first time setup */
bc7d338f 9682 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9683 struct i40e_vsi *vsi = NULL;
9684 u16 uplink_seid;
9685
9686 /* Set up the PF VSI associated with the PF's main VSI
9687 * that is already in the HW switch
9688 */
9689 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9690 uplink_seid = pf->veb[pf->lan_veb]->seid;
9691 else
9692 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9693 if (pf->lan_vsi == I40E_NO_VSI)
9694 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9695 else if (reinit)
9696 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9697 if (!vsi) {
9698 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9699 i40e_fdir_teardown(pf);
9700 return -EAGAIN;
9701 }
41c445ff
JB		 9702 } else {
9703 /* force a reset of TC and queue layout configurations */
9704 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9705 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9706 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9707 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9708 }
9709 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9710
cbf61325
ASJ		 9711 i40e_fdir_sb_setup(pf);
9712
41c445ff
JB		 9713 /* Setup static PF queue filter control settings */
9714 ret = i40e_setup_pf_filter_control(pf);
9715 if (ret) {
9716 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9717 ret);
9718 /* Failure here should not stop continuing other steps */
9719 }
9720
9721 /* enable RSS in the HW, even for only one queue, as the stack can use
9722 * the hash
9723 */
9724 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9725 i40e_config_rss(pf);
9726
9727 /* fill in link information and enable LSE reporting */
21af70fb 9728 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9729 i40e_link_event(pf);
9730
d52c20b7 9731 /* Initialize user-specific link properties */
41c445ff
JB		 9732 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9733 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9734
beb0dff1
JK		 9735 i40e_ptp_init(pf);
9736
41c445ff
JB		 9737 return ret;
9738}
9739
41c445ff
JB		 9740/**
9741 * i40e_determine_queue_usage - Work out queue distribution
9742 * @pf: board private structure
9743 **/
9744static void i40e_determine_queue_usage(struct i40e_pf *pf)
9745{
41c445ff
JB		 9746 int queues_left;
9747
9748 pf->num_lan_qps = 0;
38e00438
VD		 9749#ifdef I40E_FCOE
9750 pf->num_fcoe_qps = 0;
9751#endif
41c445ff
JB		 9752
9753 /* Find the max queues to be put into basic use. We'll always be
9754 * using TC0, whether or not DCB is running, and TC0 will get the
9755 * big RSS set.
9756 */
9757 queues_left = pf->hw.func_caps.num_tx_qp;
9758
cbf61325 9759 if ((queues_left == 1) ||
9aa7e935 9760 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9761 /* one qp for PF, no queues for anything else */
9762 queues_left = 0;
9763 pf->rss_size = pf->num_lan_qps = 1;
9764
9765 /* make sure all the fancies are disabled */
60ea5f83 9766 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9767#ifdef I40E_FCOE
9768 I40E_FLAG_FCOE_ENABLED |
9769#endif
60ea5f83
JB		 9770 I40E_FLAG_FD_SB_ENABLED |
9771 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9772 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9773 I40E_FLAG_SRIOV_ENABLED |
9774 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9775 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9776 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9777 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9778 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9779 /* one qp for PF */
9780 pf->rss_size = pf->num_lan_qps = 1;
9781 queues_left -= pf->num_lan_qps;
9782
9783 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9784#ifdef I40E_FCOE
9785 I40E_FLAG_FCOE_ENABLED |
9786#endif
9aa7e935
FZ		 9787 I40E_FLAG_FD_SB_ENABLED |
9788 I40E_FLAG_FD_ATR_ENABLED |
9789 I40E_FLAG_DCB_ENABLED |
9790 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9791 } else {
cbf61325 9792 /* Not enough queues for all TCs */
4d9b6043 9793 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9794 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9795 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9796 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9797 }
9a3bd2f1
ASJ		 9798 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9799 num_online_cpus());
9800 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9801 pf->hw.func_caps.num_tx_qp);
9802
cbf61325
ASJ		 9803 queues_left -= pf->num_lan_qps;
9804 }
9805
38e00438
VD		 9806#ifdef I40E_FCOE
9807 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9808 if (I40E_DEFAULT_FCOE <= queues_left) {
9809 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9810 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9811 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9812 } else {
9813 pf->num_fcoe_qps = 0;
9814 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9815 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9816 }
9817
9818 queues_left -= pf->num_fcoe_qps;
9819 }
9820
9821#endif
cbf61325
ASJ		 9822 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9823 if (queues_left > 1) {
9824 queues_left -= 1; /* save 1 queue for FD */
9825 } else {
9826 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9827 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9828 }
41c445ff
JB		 9829 }
9830
9831 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9832 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9833 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9834 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9835 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9836 }
9837
9838 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9839 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9840 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9841 (queues_left / pf->num_vmdq_qps));
9842 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9843 }
9844
f8ff1464 9845 pf->queues_left = queues_left;
38e00438
VD		 9846#ifdef I40E_FCOE
9847 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9848#endif
41c445ff
JB		 9849}
9850
9851/**
9852 * i40e_setup_pf_filter_control - Setup PF static filter control
9853 * @pf: PF to be setup
9854 *
b40c82e6 9855 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9856 * settings. If PE/FCoE are enabled then it will also set the per PF
9857 * based filter sizes required for them. It also enables Flow director,
9858 * ethertype and macvlan type filter settings for the pf.
9859 *
9860 * Returns 0 on success, negative on failure
9861 **/
9862static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9863{
9864 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9865
9866 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9867
9868 /* Flow Director is enabled */
60ea5f83 9869 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9870 settings->enable_fdir = true;
9871
9872 /* Ethtype and MACVLAN filters enabled for PF */
9873 settings->enable_ethtype = true;
9874 settings->enable_macvlan = true;
9875
9876 if (i40e_set_filter_control(&pf->hw, settings))
9877 return -ENOENT;
9878
9879 return 0;
9880}
9881
0c22b3dd
JB		 9882#define INFO_STRING_LEN 255
9883static void i40e_print_features(struct i40e_pf *pf)
9884{
9885 struct i40e_hw *hw = &pf->hw;
9886 char *buf, *string;
9887
9888 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9889 if (!string) {
9890 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9891 return;
9892 }
9893
9894 buf = string;
9895
9896 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9897#ifdef CONFIG_PCI_IOV
9898 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9899#endif
aba237d1
MW		 9900 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9901 pf->hw.func_caps.num_vsis,
9902 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9903 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9904
9905 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9906 buf += sprintf(buf, "RSS ");
0c22b3dd 9907 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9908 buf += sprintf(buf, "FD_ATR ");
9909 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9910 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9911 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9912 }
4d9b6043 9913 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9914 buf += sprintf(buf, "DCB ");
9915 if (pf->flags & I40E_FLAG_PTP)
9916 buf += sprintf(buf, "PTP ");
38e00438
VD		 9917#ifdef I40E_FCOE
9918 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9919 buf += sprintf(buf, "FCOE ");
9920#endif
0c22b3dd
JB		 9921
9922 BUG_ON(buf > (string + INFO_STRING_LEN));
9923 dev_info(&pf->pdev->dev, "%s\n", string);
9924 kfree(string);
9925}
9926
41c445ff
JB		 9927/**
9928 * i40e_probe - Device initialization routine
9929 * @pdev: PCI device information struct
9930 * @ent: entry in i40e_pci_tbl
9931 *
b40c82e6
JK		 9932 * i40e_probe initializes a PF identified by a pci_dev structure.
9933 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9934 * and a hardware reset occur.
9935 *
9936 * Returns 0 on success, negative on failure
9937 **/
9938static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9939{
e827845c 9940 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9941 struct i40e_pf *pf;
9942 struct i40e_hw *hw;
93cd765b 9943 static u16 pfs_found;
d4dfb81a 9944 u16 link_status;
41c445ff
JB		 9945 int err = 0;
9946 u32 len;
8a9eb7d3 9947 u32 i;
41c445ff
JB		 9948
9949 err = pci_enable_device_mem(pdev);
9950 if (err)
9951 return err;
9952
9953 /* set up for high or low dma */
6494294f 9954 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9955 if (err) {
e3e3bfdd
JS		 9956 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9957 if (err) {
9958 dev_err(&pdev->dev,
9959 "DMA configuration failed: 0x%x\n", err);
9960 goto err_dma;
9961 }
41c445ff
JB		 9962 }
9963
9964 /* set up pci connections */
9965 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9966 IORESOURCE_MEM), i40e_driver_name);
9967 if (err) {
9968 dev_info(&pdev->dev,
9969 "pci_request_selected_regions failed %d\n", err);
9970 goto err_pci_reg;
9971 }
9972
9973 pci_enable_pcie_error_reporting(pdev);
9974 pci_set_master(pdev);
9975
9976 /* Now that we have a PCI connection, we need to do the
9977 * low level device setup. This is primarily setting up
9978 * the Admin Queue structures and then querying for the
9979 * device's current profile information.
9980 */
9981 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9982 if (!pf) {
9983 err = -ENOMEM;
9984 goto err_pf_alloc;
9985 }
9986 pf->next_vsi = 0;
9987 pf->pdev = pdev;
9988 set_bit(__I40E_DOWN, &pf->state);
9989
9990 hw = &pf->hw;
9991 hw->back = pf;
232f4706 9992
2ac8b675
SN		 9993 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
9994 I40E_MAX_CSR_SPACE);
232f4706 9995
2ac8b675 9996 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 9997 if (!hw->hw_addr) {
9998 err = -EIO;
9999 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10000 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10001 pf->ioremap_len, err);
41c445ff
JB		 10002 goto err_ioremap;
10003 }
10004 hw->vendor_id = pdev->vendor;
10005 hw->device_id = pdev->device;
10006 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10007 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10008 hw->subsystem_device_id = pdev->subsystem_device;
10009 hw->bus.device = PCI_SLOT(pdev->devfn);
10010 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10011 pf->instance = pfs_found;
41c445ff 10012
5b5faa43
SN		 10013 if (debug != -1) {
10014 pf->msg_enable = pf->hw.debug_mask;
10015 pf->msg_enable = debug;
10016 }
10017
7134f9ce
JB		 10018 /* do a special CORER for clearing PXE mode once at init */
10019 if (hw->revision_id == 0 &&
10020 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10021 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10022 i40e_flush(hw);
10023 msleep(200);
10024 pf->corer_count++;
10025
10026 i40e_clear_pxe_mode(hw);
10027 }
10028
41c445ff 10029 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10030 i40e_clear_hw(hw);
41c445ff
JB		 10031 err = i40e_pf_reset(hw);
10032 if (err) {
10033 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10034 goto err_pf_reset;
10035 }
10036 pf->pfr_count++;
10037
10038 hw->aq.num_arq_entries = I40E_AQ_LEN;
10039 hw->aq.num_asq_entries = I40E_AQ_LEN;
10040 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10041 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10042 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10043
b294ac70 10044 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10045 "%s-%s:misc",
10046 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10047
10048 err = i40e_init_shared_code(hw);
10049 if (err) {
b2a75c58
ASJ		 10050 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10051 err);
41c445ff
JB		 10052 goto err_pf_reset;
10053 }
10054
d52c20b7
JB		 10055 /* set up a default setting for link flow control */
10056 pf->hw.fc.requested_mode = I40E_FC_NONE;
10057
41c445ff
JB		 10058 err = i40e_init_adminq(hw);
10059 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
10060 if (err) {
10061 dev_info(&pdev->dev,
7aa67613 10062 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10063 goto err_pf_reset;
10064 }
10065
7aa67613
CS		 10066 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10067 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10068 dev_info(&pdev->dev,
7aa67613
CS		 10069 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10070 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10071 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10072 dev_info(&pdev->dev,
7aa67613 10073 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10074
4eb3f768
SN		 10075 i40e_verify_eeprom(pf);
10076
2c5fe33b
JB		 10077 /* Rev 0 hardware was never productized */
10078 if (hw->revision_id < 1)
10079 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10080
6ff4ef86 10081 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10082 err = i40e_get_capabilities(pf);
10083 if (err)
10084 goto err_adminq_setup;
10085
10086 err = i40e_sw_init(pf);
10087 if (err) {
10088 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10089 goto err_sw_init;
10090 }
10091
10092 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10093 hw->func_caps.num_rx_qp,
10094 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10095 if (err) {
10096 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10097 goto err_init_lan_hmc;
10098 }
10099
10100 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10101 if (err) {
10102 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10103 err = -ENOENT;
10104 goto err_configure_lan_hmc;
10105 }
10106
b686ece5
NP		 10107 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10108 * Ignore error return codes because if it was already disabled via
10109 * hardware settings this will fail
10110 */
10111 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10112 (pf->hw.aq.fw_maj_ver < 4)) {
10113 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10114 i40e_aq_stop_lldp(hw, true, NULL);
10115 }
10116
41c445ff 10117 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10118 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10119 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10120 err = -EIO;
10121 goto err_mac_addr;
10122 }
10123 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10124 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10125 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10126 if (is_valid_ether_addr(hw->mac.port_addr))
10127 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10128#ifdef I40E_FCOE
10129 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10130 if (err)
10131 dev_info(&pdev->dev,
10132 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10133 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10134 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10135 hw->mac.san_addr);
10136 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10137 }
10138 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10139#endif /* I40E_FCOE */
41c445ff
JB		 10140
10141 pci_set_drvdata(pdev, pf);
10142 pci_save_state(pdev);
4e3b35b0
NP		 10143#ifdef CONFIG_I40E_DCB
10144 err = i40e_init_pf_dcb(pf);
10145 if (err) {
aebfc816 10146 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10147 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10148 /* Continue without DCB enabled */
4e3b35b0
NP		 10149 }
10150#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10151
10152 /* set up periodic task facility */
10153 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10154 pf->service_timer_period = HZ;
10155
10156 INIT_WORK(&pf->service_task, i40e_service_task);
10157 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10158 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10159
8e2773ae
SN		 10160 /* WoL defaults to disabled */
10161 pf->wol_en = false;
10162 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10163
41c445ff
JB		 10164 /* set up the main switch operations */
10165 i40e_determine_queue_usage(pf);
c1147280
JB		 10166 err = i40e_init_interrupt_scheme(pf);
10167 if (err)
10168 goto err_switch_setup;
41c445ff 10169
505682cd
MW		 10170 /* The number of VSIs reported by the FW is the minimum guaranteed
10171 * to us; HW supports far more and we share the remaining pool with
10172 * the other PFs. We allocate space for more than the guarantee with
10173 * the understanding that we might not get them all later.
41c445ff 10174 */
505682cd
MW		 10175 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10176 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10177 else
10178 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10179
10180 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10181 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10182 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10183 if (!pf->vsi) {
10184 err = -ENOMEM;
41c445ff 10185 goto err_switch_setup;
ed87ac09 10186 }
41c445ff 10187
fa11cb3d
ASJ		 10188#ifdef CONFIG_PCI_IOV
10189 /* prep for VF support */
10190 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10191 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10192 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10193 if (pci_num_vf(pdev))
10194 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10195 }
10196#endif
bc7d338f 10197 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10198 if (err) {
10199 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10200 goto err_vsis;
10201 }
8a9eb7d3 10202 /* if FDIR VSI was set up, start it now */
505682cd 10203 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10204 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10205 i40e_vsi_open(pf->vsi[i]);
10206 break;
10207 }
10208 }
41c445ff 10209
7e2453fe
JB		 10210 /* driver is only interested in link up/down and module qualification
10211 * reports from firmware
10212 */
10213 err = i40e_aq_set_phy_int_mask(&pf->hw,
10214 I40E_AQ_EVENT_LINK_UPDOWN |
10215 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10216 if (err)
f1c7e72e
SN		 10217 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10218 i40e_stat_str(&pf->hw, err),
10219 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10220
025b4a54
ASJ		 10221 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10222 (pf->hw.aq.fw_maj_ver < 4)) {
10223 msleep(75);
10224 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10225 if (err)
f1c7e72e
SN		 10226 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10227 i40e_stat_str(&pf->hw, err),
10228 i40e_aq_str(&pf->hw,
10229 pf->hw.aq.asq_last_status));
cafa2ee6 10230 }
41c445ff
JB		 10231 /* The main driver is (mostly) up and happy. We need to set this state
10232 * before setting up the misc vector or we get a race and the vector
10233 * ends up disabled forever.
10234 */
10235 clear_bit(__I40E_DOWN, &pf->state);
10236
10237 /* In case of MSIX we are going to setup the misc vector right here
10238 * to handle admin queue events etc. In case of legacy and MSI
10239 * the misc functionality and queue processing is combined in
10240 * the same vector and that gets setup at open.
10241 */
10242 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10243 err = i40e_setup_misc_vector(pf);
10244 if (err) {
10245 dev_info(&pdev->dev,
10246 "setup of misc vector failed: %d\n", err);
10247 goto err_vsis;
10248 }
10249 }
10250
df805f62 10251#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10252 /* prep for VF support */
10253 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10254 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10255 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10256 u32 val;
10257
10258 /* disable link interrupts for VFs */
10259 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10260 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10261 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10262 i40e_flush(hw);
4aeec010
MW		 10263
10264 if (pci_num_vf(pdev)) {
10265 dev_info(&pdev->dev,
10266 "Active VFs found, allocating resources.\n");
10267 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10268 if (err)
10269 dev_info(&pdev->dev,
10270 "Error %d allocating resources for existing VFs\n",
10271 err);
10272 }
41c445ff 10273 }
df805f62 10274#endif /* CONFIG_PCI_IOV */
41c445ff 10275
93cd765b
ASJ		 10276 pfs_found++;
10277
41c445ff
JB		 10278 i40e_dbg_pf_init(pf);
10279
10280 /* tell the firmware that we're starting */
44033fac 10281 i40e_send_version(pf);
41c445ff
JB		 10282
10283 /* since everything's happy, start the service_task timer */
10284 mod_timer(&pf->service_timer,
10285 round_jiffies(jiffies + pf->service_timer_period));
10286
38e00438
VD		 10287#ifdef I40E_FCOE
10288 /* create FCoE interface */
10289 i40e_fcoe_vsi_setup(pf);
10290
10291#endif
d4dfb81a
CS		 10292 /* Get the negotiated link width and speed from PCI config space */
10293 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
10294
10295 i40e_set_pci_config_data(hw, link_status);
10296
69bfb110 10297 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 10298 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
10299 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
10300 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
10301 "Unknown"),
10302 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
10303 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
10304 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
10305 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
10306 "Unknown"));
10307
10308 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10309 hw->bus.speed < i40e_bus_speed_8000) {
10310 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10311 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10312 }
10313
e827845c
CS		 10314 /* get the requested speeds from the fw */
10315 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10316 if (err)
f1c7e72e
SN		 10317 dev_info(&pf->pdev->dev,
10318 "get phy capabilities failed, err %s aq_err %s, advertised speed settings may not be correct\n",
10319 i40e_stat_str(&pf->hw, err),
10320 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10321 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10322
0c22b3dd
JB		 10323 /* print a string summarizing features */
10324 i40e_print_features(pf);
10325
41c445ff
JB		 10326 return 0;
10327
10328 /* Unwind what we've done if something failed in the setup */
10329err_vsis:
10330 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10331 i40e_clear_interrupt_scheme(pf);
10332 kfree(pf->vsi);
04b03013
SN		 10333err_switch_setup:
10334 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10335 del_timer_sync(&pf->service_timer);
10336err_mac_addr:
10337err_configure_lan_hmc:
10338 (void)i40e_shutdown_lan_hmc(hw);
10339err_init_lan_hmc:
10340 kfree(pf->qp_pile);
41c445ff
JB		 10341err_sw_init:
10342err_adminq_setup:
10343 (void)i40e_shutdown_adminq(hw);
10344err_pf_reset:
10345 iounmap(hw->hw_addr);
10346err_ioremap:
10347 kfree(pf);
10348err_pf_alloc:
10349 pci_disable_pcie_error_reporting(pdev);
10350 pci_release_selected_regions(pdev,
10351 pci_select_bars(pdev, IORESOURCE_MEM));
10352err_pci_reg:
10353err_dma:
10354 pci_disable_device(pdev);
10355 return err;
10356}
10357
10358/**
10359 * i40e_remove - Device removal routine
10360 * @pdev: PCI device information struct
10361 *
10362 * i40e_remove is called by the PCI subsystem to alert the driver
10363 * that is should release a PCI device. This could be caused by a
10364 * Hot-Plug event, or because the driver is going to be removed from
10365 * memory.
10366 **/
10367static void i40e_remove(struct pci_dev *pdev)
10368{
10369 struct i40e_pf *pf = pci_get_drvdata(pdev);
10370 i40e_status ret_code;
41c445ff
JB		 10371 int i;
10372
10373 i40e_dbg_pf_exit(pf);
10374
beb0dff1
JK		 10375 i40e_ptp_stop(pf);
10376
41c445ff
JB		 10377 /* no more scheduling of any task */
10378 set_bit(__I40E_DOWN, &pf->state);
10379 del_timer_sync(&pf->service_timer);
10380 cancel_work_sync(&pf->service_task);
33c62b34 10381 i40e_fdir_teardown(pf);
41c445ff 10382
eb2d80bc
MW		 10383 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10384 i40e_free_vfs(pf);
10385 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10386 }
10387
41c445ff
JB		 10388 i40e_fdir_teardown(pf);
10389
10390 /* If there is a switch structure or any orphans, remove them.
10391 * This will leave only the PF's VSI remaining.
10392 */
10393 for (i = 0; i < I40E_MAX_VEB; i++) {
10394 if (!pf->veb[i])
10395 continue;
10396
10397 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10398 pf->veb[i]->uplink_seid == 0)
10399 i40e_switch_branch_release(pf->veb[i]);
10400 }
10401
10402 /* Now we can shutdown the PF's VSI, just before we kill
10403 * adminq and hmc.
10404 */
10405 if (pf->vsi[pf->lan_vsi])
10406 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10407
41c445ff 10408 /* shutdown and destroy the HMC */
60442dea
SN		 10409 if (pf->hw.hmc.hmc_obj) {
10410 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10411 if (ret_code)
10412 dev_warn(&pdev->dev,
10413 "Failed to destroy the HMC resources: %d\n",
10414 ret_code);
10415 }
41c445ff
JB		 10416
10417 /* shutdown the adminq */
41c445ff
JB		 10418 ret_code = i40e_shutdown_adminq(&pf->hw);
10419 if (ret_code)
10420 dev_warn(&pdev->dev,
10421 "Failed to destroy the Admin Queue resources: %d\n",
10422 ret_code);
10423
10424 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10425 i40e_clear_interrupt_scheme(pf);
505682cd 10426 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10427 if (pf->vsi[i]) {
10428 i40e_vsi_clear_rings(pf->vsi[i]);
10429 i40e_vsi_clear(pf->vsi[i]);
10430 pf->vsi[i] = NULL;
10431 }
10432 }
10433
10434 for (i = 0; i < I40E_MAX_VEB; i++) {
10435 kfree(pf->veb[i]);
10436 pf->veb[i] = NULL;
10437 }
10438
10439 kfree(pf->qp_pile);
41c445ff
JB		 10440 kfree(pf->vsi);
10441
41c445ff
JB		 10442 iounmap(pf->hw.hw_addr);
10443 kfree(pf);
10444 pci_release_selected_regions(pdev,
10445 pci_select_bars(pdev, IORESOURCE_MEM));
10446
10447 pci_disable_pcie_error_reporting(pdev);
10448 pci_disable_device(pdev);
10449}
10450
10451/**
10452 * i40e_pci_error_detected - warning that something funky happened in PCI land
10453 * @pdev: PCI device information struct
10454 *
10455 * Called to warn that something happened and the error handling steps
10456 * are in progress. Allows the driver to quiesce things, be ready for
10457 * remediation.
10458 **/
10459static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10460 enum pci_channel_state error)
10461{
10462 struct i40e_pf *pf = pci_get_drvdata(pdev);
10463
10464 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10465
10466 /* shutdown all operations */
9007bccd
SN		 10467 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10468 rtnl_lock();
10469 i40e_prep_for_reset(pf);
10470 rtnl_unlock();
10471 }
41c445ff
JB		 10472
10473 /* Request a slot reset */
10474 return PCI_ERS_RESULT_NEED_RESET;
10475}
10476
10477/**
10478 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10479 * @pdev: PCI device information struct
10480 *
10481 * Called to find if the driver can work with the device now that
10482 * the pci slot has been reset. If a basic connection seems good
10483 * (registers are readable and have sane content) then return a
10484 * happy little PCI_ERS_RESULT_xxx.
10485 **/
10486static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10487{
10488 struct i40e_pf *pf = pci_get_drvdata(pdev);
10489 pci_ers_result_t result;
10490 int err;
10491 u32 reg;
10492
10493 dev_info(&pdev->dev, "%s\n", __func__);
10494 if (pci_enable_device_mem(pdev)) {
10495 dev_info(&pdev->dev,
10496 "Cannot re-enable PCI device after reset.\n");
10497 result = PCI_ERS_RESULT_DISCONNECT;
10498 } else {
10499 pci_set_master(pdev);
10500 pci_restore_state(pdev);
10501 pci_save_state(pdev);
10502 pci_wake_from_d3(pdev, false);
10503
10504 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10505 if (reg == 0)
10506 result = PCI_ERS_RESULT_RECOVERED;
10507 else
10508 result = PCI_ERS_RESULT_DISCONNECT;
10509 }
10510
10511 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10512 if (err) {
10513 dev_info(&pdev->dev,
10514 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10515 err);
10516 /* non-fatal, continue */
10517 }
10518
10519 return result;
10520}
10521
10522/**
10523 * i40e_pci_error_resume - restart operations after PCI error recovery
10524 * @pdev: PCI device information struct
10525 *
10526 * Called to allow the driver to bring things back up after PCI error
10527 * and/or reset recovery has finished.
10528 **/
10529static void i40e_pci_error_resume(struct pci_dev *pdev)
10530{
10531 struct i40e_pf *pf = pci_get_drvdata(pdev);
10532
10533 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10534 if (test_bit(__I40E_SUSPENDED, &pf->state))
10535 return;
10536
10537 rtnl_lock();
41c445ff 10538 i40e_handle_reset_warning(pf);
4c4935a9 10539 rtnl_unlock();
9007bccd
SN		 10540}
10541
10542/**
10543 * i40e_shutdown - PCI callback for shutting down
10544 * @pdev: PCI device information struct
10545 **/
10546static void i40e_shutdown(struct pci_dev *pdev)
10547{
10548 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10549 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10550
10551 set_bit(__I40E_SUSPENDED, &pf->state);
10552 set_bit(__I40E_DOWN, &pf->state);
10553 rtnl_lock();
10554 i40e_prep_for_reset(pf);
10555 rtnl_unlock();
10556
8e2773ae
SN		 10557 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10558 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10559
02b42498
CS		 10560 del_timer_sync(&pf->service_timer);
10561 cancel_work_sync(&pf->service_task);
10562 i40e_fdir_teardown(pf);
10563
10564 rtnl_lock();
10565 i40e_prep_for_reset(pf);
10566 rtnl_unlock();
10567
10568 wr32(hw, I40E_PFPM_APM,
10569 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10570 wr32(hw, I40E_PFPM_WUFC,
10571 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10572
e147758d
SN		 10573 i40e_clear_interrupt_scheme(pf);
10574
9007bccd 10575 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10576 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10577 pci_set_power_state(pdev, PCI_D3hot);
10578 }
10579}
10580
10581#ifdef CONFIG_PM
10582/**
10583 * i40e_suspend - PCI callback for moving to D3
10584 * @pdev: PCI device information struct
10585 **/
10586static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10587{
10588 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10589 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10590
10591 set_bit(__I40E_SUSPENDED, &pf->state);
10592 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10593
9007bccd
SN		 10594 rtnl_lock();
10595 i40e_prep_for_reset(pf);
10596 rtnl_unlock();
10597
8e2773ae
SN		 10598 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10599 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10600
10601 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10602 pci_set_power_state(pdev, PCI_D3hot);
10603
10604 return 0;
41c445ff
JB		 10605}
10606
9007bccd
SN		 10607/**
10608 * i40e_resume - PCI callback for waking up from D3
10609 * @pdev: PCI device information struct
10610 **/
10611static int i40e_resume(struct pci_dev *pdev)
10612{
10613 struct i40e_pf *pf = pci_get_drvdata(pdev);
10614 u32 err;
10615
10616 pci_set_power_state(pdev, PCI_D0);
10617 pci_restore_state(pdev);
10618 /* pci_restore_state() clears dev->state_saves, so
10619 * call pci_save_state() again to restore it.
10620 */
10621 pci_save_state(pdev);
10622
10623 err = pci_enable_device_mem(pdev);
10624 if (err) {
10625 dev_err(&pdev->dev,
10626 "%s: Cannot enable PCI device from suspend\n",
10627 __func__);
10628 return err;
10629 }
10630 pci_set_master(pdev);
10631
10632 /* no wakeup events while running */
10633 pci_wake_from_d3(pdev, false);
10634
10635 /* handling the reset will rebuild the device state */
10636 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10637 clear_bit(__I40E_DOWN, &pf->state);
10638 rtnl_lock();
10639 i40e_reset_and_rebuild(pf, false);
10640 rtnl_unlock();
10641 }
10642
10643 return 0;
10644}
10645
10646#endif
41c445ff
JB		 10647static const struct pci_error_handlers i40e_err_handler = {
10648 .error_detected = i40e_pci_error_detected,
10649 .slot_reset = i40e_pci_error_slot_reset,
10650 .resume = i40e_pci_error_resume,
10651};
10652
10653static struct pci_driver i40e_driver = {
10654 .name = i40e_driver_name,
10655 .id_table = i40e_pci_tbl,
10656 .probe = i40e_probe,
10657 .remove = i40e_remove,
9007bccd
SN		 10658#ifdef CONFIG_PM
10659 .suspend = i40e_suspend,
10660 .resume = i40e_resume,
10661#endif
10662 .shutdown = i40e_shutdown,
41c445ff
JB		 10663 .err_handler = &i40e_err_handler,
10664 .sriov_configure = i40e_pci_sriov_configure,
10665};
10666
10667/**
10668 * i40e_init_module - Driver registration routine
10669 *
10670 * i40e_init_module is the first routine called when the driver is
10671 * loaded. All it does is register with the PCI subsystem.
10672 **/
10673static int __init i40e_init_module(void)
10674{
10675 pr_info("%s: %s - version %s\n", i40e_driver_name,
10676 i40e_driver_string, i40e_driver_version_str);
10677 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10678
41c445ff
JB		 10679 i40e_dbg_init();
10680 return pci_register_driver(&i40e_driver);
10681}
10682module_init(i40e_init_module);
10683
10684/**
10685 * i40e_exit_module - Driver exit cleanup routine
10686 *
10687 * i40e_exit_module is called just before the driver is removed
10688 * from memory.
10689 **/
10690static void __exit i40e_exit_module(void)
10691{
10692 pci_unregister_driver(&i40e_driver);
10693 i40e_dbg_exit();
10694}
10695module_exit(i40e_exit_module);
Linux kernel - Deliverables
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