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Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
1c2df9e5 41#define DRV_VERSION_MINOR 4
e1c22791 42#define DRV_VERSION_BUILD 4
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 58static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
59 u16 rss_table_size, u16 rss_size);
cbf61325 60static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 61static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 62
63/* i40e_pci_tbl - PCI Device ID Table
64 *
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
9baa3c34 70static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 87 /* required last entry */
88 {0, }
89};
90MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
91
92#define I40E_MAX_VF_COUNT 128
93static int debug = -1;
94module_param(debug, int, 0);
95MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
96
97MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
98MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
99MODULE_LICENSE("GPL");
100MODULE_VERSION(DRV_VERSION);
101
102/**
103 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
104 * @hw: pointer to the HW structure
105 * @mem: ptr to mem struct to fill out
106 * @size: size of memory requested
107 * @alignment: what to align the allocation to
108 **/
109int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
110 u64 size, u32 alignment)
111{
112 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
113
114 mem->size = ALIGN(size, alignment);
115 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
116 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 117 if (!mem->va)
118 return -ENOMEM;
41c445ff 119
93bc73b8 120 return 0;
41c445ff
JB		 121}
122
123/**
124 * i40e_free_dma_mem_d - OS specific memory free for shared code
125 * @hw: pointer to the HW structure
126 * @mem: ptr to mem struct to free
127 **/
128int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
129{
130 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
131
132 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
133 mem->va = NULL;
134 mem->pa = 0;
135 mem->size = 0;
136
137 return 0;
138}
139
140/**
141 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
142 * @hw: pointer to the HW structure
143 * @mem: ptr to mem struct to fill out
144 * @size: size of memory requested
145 **/
146int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
147 u32 size)
148{
149 mem->size = size;
150 mem->va = kzalloc(size, GFP_KERNEL);
151
93bc73b8
JB		 152 if (!mem->va)
153 return -ENOMEM;
41c445ff 154
93bc73b8 155 return 0;
41c445ff
JB		 156}
157
158/**
159 * i40e_free_virt_mem_d - OS specific memory free for shared code
160 * @hw: pointer to the HW structure
161 * @mem: ptr to mem struct to free
162 **/
163int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
164{
165 /* it's ok to kfree a NULL pointer */
166 kfree(mem->va);
167 mem->va = NULL;
168 mem->size = 0;
169
170 return 0;
171}
172
173/**
174 * i40e_get_lump - find a lump of free generic resource
175 * @pf: board private structure
176 * @pile: the pile of resource to search
177 * @needed: the number of items needed
178 * @id: an owner id to stick on the items assigned
179 *
180 * Returns the base item index of the lump, or negative for error
181 *
182 * The search_hint trick and lack of advanced fit-finding only work
183 * because we're highly likely to have all the same size lump requests.
184 * Linear search time and any fragmentation should be minimal.
185 **/
186static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
187 u16 needed, u16 id)
188{
189 int ret = -ENOMEM;
ddf434ac 190 int i, j;
41c445ff
JB		 191
192 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
193 dev_info(&pf->pdev->dev,
194 "param err: pile=%p needed=%d id=0x%04x\n",
195 pile, needed, id);
196 return -EINVAL;
197 }
198
199 /* start the linear search with an imperfect hint */
200 i = pile->search_hint;
ddf434ac 201 while (i < pile->num_entries) {
41c445ff
JB		 202 /* skip already allocated entries */
203 if (pile->list[i] & I40E_PILE_VALID_BIT) {
204 i++;
205 continue;
206 }
207
208 /* do we have enough in this lump? */
209 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
210 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
211 break;
212 }
213
214 if (j == needed) {
215 /* there was enough, so assign it to the requestor */
216 for (j = 0; j < needed; j++)
217 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
218 ret = i;
219 pile->search_hint = i + j;
ddf434ac 220 break;
41c445ff 221 }
6995b36c
JB		 222
223 /* not enough, so skip over it and continue looking */
224 i += j;
41c445ff
JB		 225 }
226
227 return ret;
228}
229
230/**
231 * i40e_put_lump - return a lump of generic resource
232 * @pile: the pile of resource to search
233 * @index: the base item index
234 * @id: the owner id of the items assigned
235 *
236 * Returns the count of items in the lump
237 **/
238static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
239{
240 int valid_id = (id | I40E_PILE_VALID_BIT);
241 int count = 0;
242 int i;
243
244 if (!pile || index >= pile->num_entries)
245 return -EINVAL;
246
247 for (i = index;
248 i < pile->num_entries && pile->list[i] == valid_id;
249 i++) {
250 pile->list[i] = 0;
251 count++;
252 }
253
254 if (count && index < pile->search_hint)
255 pile->search_hint = index;
256
257 return count;
258}
259
fdf0e0bf
ASJ		 260/**
261 * i40e_find_vsi_from_id - searches for the vsi with the given id
262 * @pf - the pf structure to search for the vsi
263 * @id - id of the vsi it is searching for
264 **/
265struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
266{
267 int i;
268
269 for (i = 0; i < pf->num_alloc_vsi; i++)
270 if (pf->vsi[i] && (pf->vsi[i]->id == id))
271 return pf->vsi[i];
272
273 return NULL;
274}
275
41c445ff
JB		 276/**
277 * i40e_service_event_schedule - Schedule the service task to wake up
278 * @pf: board private structure
279 *
280 * If not already scheduled, this puts the task into the work queue
281 **/
282static void i40e_service_event_schedule(struct i40e_pf *pf)
283{
284 if (!test_bit(__I40E_DOWN, &pf->state) &&
285 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
286 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
287 schedule_work(&pf->service_task);
288}
289
290/**
291 * i40e_tx_timeout - Respond to a Tx Hang
292 * @netdev: network interface device structure
293 *
294 * If any port has noticed a Tx timeout, it is likely that the whole
295 * device is munged, not just the one netdev port, so go for the full
296 * reset.
297 **/
38e00438
VD		 298#ifdef I40E_FCOE
299void i40e_tx_timeout(struct net_device *netdev)
300#else
41c445ff 301static void i40e_tx_timeout(struct net_device *netdev)
38e00438 302#endif
41c445ff
JB		 303{
304 struct i40e_netdev_priv *np = netdev_priv(netdev);
305 struct i40e_vsi *vsi = np->vsi;
306 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 307 struct i40e_ring *tx_ring = NULL;
308 unsigned int i, hung_queue = 0;
309 u32 head, val;
41c445ff
JB		 310
311 pf->tx_timeout_count++;
312
b03a8c1f
KP		 313 /* find the stopped queue the same way the stack does */
314 for (i = 0; i < netdev->num_tx_queues; i++) {
315 struct netdev_queue *q;
316 unsigned long trans_start;
317
318 q = netdev_get_tx_queue(netdev, i);
319 trans_start = q->trans_start ? : netdev->trans_start;
320 if (netif_xmit_stopped(q) &&
321 time_after(jiffies,
322 (trans_start + netdev->watchdog_timeo))) {
323 hung_queue = i;
324 break;
325 }
326 }
327
328 if (i == netdev->num_tx_queues) {
329 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
330 } else {
331 /* now that we have an index, find the tx_ring struct */
332 for (i = 0; i < vsi->num_queue_pairs; i++) {
333 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
334 if (hung_queue ==
335 vsi->tx_rings[i]->queue_index) {
336 tx_ring = vsi->tx_rings[i];
337 break;
338 }
339 }
340 }
341 }
342
41c445ff 343 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 344 pf->tx_timeout_recovery_level = 1; /* reset after some time */
345 else if (time_before(jiffies,
346 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
347 return; /* don't do any new action before the next timeout */
348
349 if (tx_ring) {
350 head = i40e_get_head(tx_ring);
351 /* Read interrupt register */
352 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
353 val = rd32(&pf->hw,
354 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
355 tx_ring->vsi->base_vector - 1));
356 else
357 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
358
359 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
360 vsi->seid, hung_queue, tx_ring->next_to_clean,
361 head, tx_ring->next_to_use,
362 readl(tx_ring->tail), val);
363 }
364
41c445ff 365 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 366 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
367 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 368
369 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 370 case 1:
371 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
372 break;
373 case 2:
374 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
375 break;
376 case 3:
377 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
378 break;
379 default:
380 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 381 break;
382 }
b03a8c1f 383
41c445ff
JB		 384 i40e_service_event_schedule(pf);
385 pf->tx_timeout_recovery_level++;
386}
387
388/**
389 * i40e_release_rx_desc - Store the new tail and head values
390 * @rx_ring: ring to bump
391 * @val: new head index
392 **/
393static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
394{
395 rx_ring->next_to_use = val;
396
397 /* Force memory writes to complete before letting h/w
398 * know there are new descriptors to fetch. (Only
399 * applicable for weak-ordered memory model archs,
400 * such as IA-64).
401 */
402 wmb();
403 writel(val, rx_ring->tail);
404}
405
406/**
407 * i40e_get_vsi_stats_struct - Get System Network Statistics
408 * @vsi: the VSI we care about
409 *
410 * Returns the address of the device statistics structure.
411 * The statistics are actually updated from the service task.
412 **/
413struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
414{
415 return &vsi->net_stats;
416}
417
418/**
419 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
420 * @netdev: network interface device structure
421 *
422 * Returns the address of the device statistics structure.
423 * The statistics are actually updated from the service task.
424 **/
38e00438
VD		 425#ifdef I40E_FCOE
426struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
427 struct net_device *netdev,
428 struct rtnl_link_stats64 *stats)
429#else
41c445ff
JB		 430static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
431 struct net_device *netdev,
980e9b11 432 struct rtnl_link_stats64 *stats)
38e00438 433#endif
41c445ff
JB		 434{
435 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 436 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 437 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 438 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
439 int i;
440
bc7d338f
ASJ		 441 if (test_bit(__I40E_DOWN, &vsi->state))
442 return stats;
443
3c325ced
JB		 444 if (!vsi->tx_rings)
445 return stats;
446
980e9b11
AD		 447 rcu_read_lock();
448 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 449 u64 bytes, packets;
450 unsigned int start;
451
452 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
453 if (!tx_ring)
454 continue;
455
456 do {
57a7744e 457 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 458 packets = tx_ring->stats.packets;
459 bytes = tx_ring->stats.bytes;
57a7744e 460 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 461
462 stats->tx_packets += packets;
463 stats->tx_bytes += bytes;
464 rx_ring = &tx_ring[1];
465
466 do {
57a7744e 467 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 468 packets = rx_ring->stats.packets;
469 bytes = rx_ring->stats.bytes;
57a7744e 470 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 471
980e9b11
AD		 472 stats->rx_packets += packets;
473 stats->rx_bytes += bytes;
474 }
475 rcu_read_unlock();
476
a5282f44 477 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 478 stats->multicast = vsi_stats->multicast;
479 stats->tx_errors = vsi_stats->tx_errors;
480 stats->tx_dropped = vsi_stats->tx_dropped;
481 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 482 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 483 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
484 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 485
980e9b11 486 return stats;
41c445ff
JB		 487}
488
489/**
490 * i40e_vsi_reset_stats - Resets all stats of the given vsi
491 * @vsi: the VSI to have its stats reset
492 **/
493void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
494{
495 struct rtnl_link_stats64 *ns;
496 int i;
497
498 if (!vsi)
499 return;
500
501 ns = i40e_get_vsi_stats_struct(vsi);
502 memset(ns, 0, sizeof(*ns));
503 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
504 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
505 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 506 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 507 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 508 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->stats));
6995b36c 510 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 511 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 512 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 513 sizeof(vsi->tx_rings[i]->stats));
514 memset(&vsi->tx_rings[i]->tx_stats, 0,
515 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 516 }
8e9dca53 517 }
41c445ff
JB		 518 vsi->stat_offsets_loaded = false;
519}
520
521/**
b40c82e6 522 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 523 * @pf: the PF to be reset
524 **/
525void i40e_pf_reset_stats(struct i40e_pf *pf)
526{
e91fdf76
SN		 527 int i;
528
41c445ff
JB		 529 memset(&pf->stats, 0, sizeof(pf->stats));
530 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
531 pf->stat_offsets_loaded = false;
e91fdf76
SN		 532
533 for (i = 0; i < I40E_MAX_VEB; i++) {
534 if (pf->veb[i]) {
535 memset(&pf->veb[i]->stats, 0,
536 sizeof(pf->veb[i]->stats));
537 memset(&pf->veb[i]->stats_offsets, 0,
538 sizeof(pf->veb[i]->stats_offsets));
539 pf->veb[i]->stat_offsets_loaded = false;
540 }
541 }
41c445ff
JB		 542}
543
544/**
545 * i40e_stat_update48 - read and update a 48 bit stat from the chip
546 * @hw: ptr to the hardware info
547 * @hireg: the high 32 bit reg to read
548 * @loreg: the low 32 bit reg to read
549 * @offset_loaded: has the initial offset been loaded yet
550 * @offset: ptr to current offset value
551 * @stat: ptr to the stat
552 *
553 * Since the device stats are not reset at PFReset, they likely will not
554 * be zeroed when the driver starts. We'll save the first values read
555 * and use them as offsets to be subtracted from the raw values in order
556 * to report stats that count from zero. In the process, we also manage
557 * the potential roll-over.
558 **/
559static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
560 bool offset_loaded, u64 *offset, u64 *stat)
561{
562 u64 new_data;
563
ab60085e 564 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 565 new_data = rd32(hw, loreg);
566 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
567 } else {
568 new_data = rd64(hw, loreg);
569 }
570 if (!offset_loaded)
571 *offset = new_data;
572 if (likely(new_data >= *offset))
573 *stat = new_data - *offset;
574 else
41a1d04b 575 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 576 *stat &= 0xFFFFFFFFFFFFULL;
577}
578
579/**
580 * i40e_stat_update32 - read and update a 32 bit stat from the chip
581 * @hw: ptr to the hardware info
582 * @reg: the hw reg to read
583 * @offset_loaded: has the initial offset been loaded yet
584 * @offset: ptr to current offset value
585 * @stat: ptr to the stat
586 **/
587static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
588 bool offset_loaded, u64 *offset, u64 *stat)
589{
590 u32 new_data;
591
592 new_data = rd32(hw, reg);
593 if (!offset_loaded)
594 *offset = new_data;
595 if (likely(new_data >= *offset))
596 *stat = (u32)(new_data - *offset);
597 else
41a1d04b 598 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 599}
600
601/**
602 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
603 * @vsi: the VSI to be updated
604 **/
605void i40e_update_eth_stats(struct i40e_vsi *vsi)
606{
607 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
608 struct i40e_pf *pf = vsi->back;
609 struct i40e_hw *hw = &pf->hw;
610 struct i40e_eth_stats *oes;
611 struct i40e_eth_stats *es; /* device's eth stats */
612
613 es = &vsi->eth_stats;
614 oes = &vsi->eth_stats_offsets;
615
616 /* Gather up the stats that the hw collects */
617 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
618 vsi->stat_offsets_loaded,
619 &oes->tx_errors, &es->tx_errors);
620 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 623 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
626 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
627 vsi->stat_offsets_loaded,
628 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 629
630 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
631 I40E_GLV_GORCL(stat_idx),
632 vsi->stat_offsets_loaded,
633 &oes->rx_bytes, &es->rx_bytes);
634 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
635 I40E_GLV_UPRCL(stat_idx),
636 vsi->stat_offsets_loaded,
637 &oes->rx_unicast, &es->rx_unicast);
638 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
639 I40E_GLV_MPRCL(stat_idx),
640 vsi->stat_offsets_loaded,
641 &oes->rx_multicast, &es->rx_multicast);
642 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
643 I40E_GLV_BPRCL(stat_idx),
644 vsi->stat_offsets_loaded,
645 &oes->rx_broadcast, &es->rx_broadcast);
646
647 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
648 I40E_GLV_GOTCL(stat_idx),
649 vsi->stat_offsets_loaded,
650 &oes->tx_bytes, &es->tx_bytes);
651 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
652 I40E_GLV_UPTCL(stat_idx),
653 vsi->stat_offsets_loaded,
654 &oes->tx_unicast, &es->tx_unicast);
655 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
656 I40E_GLV_MPTCL(stat_idx),
657 vsi->stat_offsets_loaded,
658 &oes->tx_multicast, &es->tx_multicast);
659 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
660 I40E_GLV_BPTCL(stat_idx),
661 vsi->stat_offsets_loaded,
662 &oes->tx_broadcast, &es->tx_broadcast);
663 vsi->stat_offsets_loaded = true;
664}
665
666/**
667 * i40e_update_veb_stats - Update Switch component statistics
668 * @veb: the VEB being updated
669 **/
670static void i40e_update_veb_stats(struct i40e_veb *veb)
671{
672 struct i40e_pf *pf = veb->pf;
673 struct i40e_hw *hw = &pf->hw;
674 struct i40e_eth_stats *oes;
675 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 676 struct i40e_veb_tc_stats *veb_oes;
677 struct i40e_veb_tc_stats *veb_es;
678 int i, idx = 0;
41c445ff
JB		 679
680 idx = veb->stats_idx;
681 es = &veb->stats;
682 oes = &veb->stats_offsets;
fe860afb
NP		 683 veb_es = &veb->tc_stats;
684 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 685
686 /* Gather up the stats that the hw collects */
687 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
688 veb->stat_offsets_loaded,
689 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 690 if (hw->revision_id > 0)
691 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
692 veb->stat_offsets_loaded,
693 &oes->rx_unknown_protocol,
694 &es->rx_unknown_protocol);
41c445ff
JB		 695 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
696 veb->stat_offsets_loaded,
697 &oes->rx_bytes, &es->rx_bytes);
698 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_unicast, &es->rx_unicast);
701 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_multicast, &es->rx_multicast);
704 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
705 veb->stat_offsets_loaded,
706 &oes->rx_broadcast, &es->rx_broadcast);
707
708 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->tx_bytes, &es->tx_bytes);
711 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_unicast, &es->tx_unicast);
714 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->tx_multicast, &es->tx_multicast);
717 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
718 veb->stat_offsets_loaded,
719 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
721 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
722 I40E_GLVEBTC_RPCL(i, idx),
723 veb->stat_offsets_loaded,
724 &veb_oes->tc_rx_packets[i],
725 &veb_es->tc_rx_packets[i]);
726 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
727 I40E_GLVEBTC_RBCL(i, idx),
728 veb->stat_offsets_loaded,
729 &veb_oes->tc_rx_bytes[i],
730 &veb_es->tc_rx_bytes[i]);
731 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
732 I40E_GLVEBTC_TPCL(i, idx),
733 veb->stat_offsets_loaded,
734 &veb_oes->tc_tx_packets[i],
735 &veb_es->tc_tx_packets[i]);
736 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
737 I40E_GLVEBTC_TBCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_tx_bytes[i],
740 &veb_es->tc_tx_bytes[i]);
741 }
41c445ff
JB		 742 veb->stat_offsets_loaded = true;
743}
744
38e00438
VD		 745#ifdef I40E_FCOE
746/**
747 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
748 * @vsi: the VSI that is capable of doing FCoE
749 **/
750static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
751{
752 struct i40e_pf *pf = vsi->back;
753 struct i40e_hw *hw = &pf->hw;
754 struct i40e_fcoe_stats *ofs;
755 struct i40e_fcoe_stats *fs; /* device's eth stats */
756 int idx;
757
758 if (vsi->type != I40E_VSI_FCOE)
759 return;
760
761 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
762 fs = &vsi->fcoe_stats;
763 ofs = &vsi->fcoe_stats_offsets;
764
765 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
768 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
771 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
774 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
777 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
780 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
783 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->fcoe_last_error, &fs->fcoe_last_error);
786 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
789
790 vsi->fcoe_stat_offsets_loaded = true;
791}
792
793#endif
41c445ff
JB		 794/**
795 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
796 * @pf: the corresponding PF
797 *
798 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
799 **/
800static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
801{
802 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
803 struct i40e_hw_port_stats *nsd = &pf->stats;
804 struct i40e_hw *hw = &pf->hw;
805 u64 xoff = 0;
41c445ff
JB		 806
807 if ((hw->fc.current_mode != I40E_FC_FULL) &&
808 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
809 return;
810
811 xoff = nsd->link_xoff_rx;
812 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
813 pf->stat_offsets_loaded,
814 &osd->link_xoff_rx, &nsd->link_xoff_rx);
815
816 /* No new LFC xoff rx */
817 if (!(nsd->link_xoff_rx - xoff))
818 return;
819
41c445ff
JB		 820}
821
822/**
823 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
824 * @pf: the corresponding PF
825 *
826 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
827 **/
828static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
829{
830 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
831 struct i40e_hw_port_stats *nsd = &pf->stats;
832 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
833 struct i40e_dcbx_config *dcb_cfg;
834 struct i40e_hw *hw = &pf->hw;
b03a8c1f 835 u16 i;
41c445ff
JB		 836 u8 tc;
837
838 dcb_cfg = &hw->local_dcbx_config;
839
e120814d
NP		 840 /* Collect Link XOFF stats when PFC is disabled */
841 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 842 i40e_update_link_xoff_rx(pf);
843 return;
844 }
845
846 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
847 u64 prio_xoff = nsd->priority_xoff_rx[i];
6995b36c 848
41c445ff
JB		 849 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
850 pf->stat_offsets_loaded,
851 &osd->priority_xoff_rx[i],
852 &nsd->priority_xoff_rx[i]);
853
854 /* No new PFC xoff rx */
855 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
856 continue;
857 /* Get the TC for given priority */
858 tc = dcb_cfg->etscfg.prioritytable[i];
859 xoff[tc] = true;
860 }
41c445ff
JB		 861}
862
863/**
7812fddc 864 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 865 * @vsi: the VSI to be updated
866 *
867 * There are a few instances where we store the same stat in a
868 * couple of different structs. This is partly because we have
869 * the netdev stats that need to be filled out, which is slightly
870 * different from the "eth_stats" defined by the chip and used in
7812fddc 871 * VF communications. We sort it out here.
41c445ff 872 **/
7812fddc 873static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 874{
875 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 876 struct rtnl_link_stats64 *ons;
877 struct rtnl_link_stats64 *ns; /* netdev stats */
878 struct i40e_eth_stats *oes;
879 struct i40e_eth_stats *es; /* device's eth stats */
880 u32 tx_restart, tx_busy;
bf00b376 881 struct i40e_ring *p;
41c445ff 882 u32 rx_page, rx_buf;
bf00b376
AA		 883 u64 bytes, packets;
884 unsigned int start;
2fc3d715 885 u64 tx_linearize;
164c9f54 886 u64 tx_force_wb;
41c445ff
JB		 887 u64 rx_p, rx_b;
888 u64 tx_p, tx_b;
41c445ff
JB		 889 u16 q;
890
891 if (test_bit(__I40E_DOWN, &vsi->state) ||
892 test_bit(__I40E_CONFIG_BUSY, &pf->state))
893 return;
894
895 ns = i40e_get_vsi_stats_struct(vsi);
896 ons = &vsi->net_stats_offsets;
897 es = &vsi->eth_stats;
898 oes = &vsi->eth_stats_offsets;
899
900 /* Gather up the netdev and vsi stats that the driver collects
901 * on the fly during packet processing
902 */
903 rx_b = rx_p = 0;
904 tx_b = tx_p = 0;
164c9f54 905 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 906 rx_page = 0;
907 rx_buf = 0;
980e9b11 908 rcu_read_lock();
41c445ff 909 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 910 /* locate Tx ring */
911 p = ACCESS_ONCE(vsi->tx_rings[q]);
912
913 do {
57a7744e 914 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 915 packets = p->stats.packets;
916 bytes = p->stats.bytes;
57a7744e 917 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 918 tx_b += bytes;
919 tx_p += packets;
920 tx_restart += p->tx_stats.restart_queue;
921 tx_busy += p->tx_stats.tx_busy;
2fc3d715 922 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 923 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 924
980e9b11
AD		 925 /* Rx queue is part of the same block as Tx queue */
926 p = &p[1];
927 do {
57a7744e 928 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 929 packets = p->stats.packets;
930 bytes = p->stats.bytes;
57a7744e 931 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 932 rx_b += bytes;
933 rx_p += packets;
420136cc
MW		 934 rx_buf += p->rx_stats.alloc_buff_failed;
935 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 936 }
980e9b11 937 rcu_read_unlock();
41c445ff
JB		 938 vsi->tx_restart = tx_restart;
939 vsi->tx_busy = tx_busy;
2fc3d715 940 vsi->tx_linearize = tx_linearize;
164c9f54 941 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 942 vsi->rx_page_failed = rx_page;
943 vsi->rx_buf_failed = rx_buf;
944
945 ns->rx_packets = rx_p;
946 ns->rx_bytes = rx_b;
947 ns->tx_packets = tx_p;
948 ns->tx_bytes = tx_b;
949
41c445ff 950 /* update netdev stats from eth stats */
7812fddc 951 i40e_update_eth_stats(vsi);
41c445ff
JB		 952 ons->tx_errors = oes->tx_errors;
953 ns->tx_errors = es->tx_errors;
954 ons->multicast = oes->rx_multicast;
955 ns->multicast = es->rx_multicast;
41a9e55c
SN		 956 ons->rx_dropped = oes->rx_discards;
957 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 958 ons->tx_dropped = oes->tx_discards;
959 ns->tx_dropped = es->tx_discards;
960
7812fddc 961 /* pull in a couple PF stats if this is the main vsi */
41c445ff 962 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 963 ns->rx_crc_errors = pf->stats.crc_errors;
964 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
965 ns->rx_length_errors = pf->stats.rx_length_errors;
966 }
967}
41c445ff 968
7812fddc 969/**
b40c82e6 970 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 971 * @pf: the PF to be updated
972 **/
973static void i40e_update_pf_stats(struct i40e_pf *pf)
974{
975 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
976 struct i40e_hw_port_stats *nsd = &pf->stats;
977 struct i40e_hw *hw = &pf->hw;
978 u32 val;
979 int i;
41c445ff 980
7812fddc
SN		 981 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
982 I40E_GLPRT_GORCL(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
985 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
986 I40E_GLPRT_GOTCL(hw->port),
987 pf->stat_offsets_loaded,
988 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
989 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->eth.rx_discards,
992 &nsd->eth.rx_discards);
532d283d
SN		 993 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
994 I40E_GLPRT_UPRCL(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->eth.rx_unicast,
997 &nsd->eth.rx_unicast);
7812fddc
SN		 998 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
999 I40E_GLPRT_MPRCL(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->eth.rx_multicast,
1002 &nsd->eth.rx_multicast);
532d283d
SN		 1003 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
1004 I40E_GLPRT_BPRCL(hw->port),
1005 pf->stat_offsets_loaded,
1006 &osd->eth.rx_broadcast,
1007 &nsd->eth.rx_broadcast);
1008 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1009 I40E_GLPRT_UPTCL(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->eth.tx_unicast,
1012 &nsd->eth.tx_unicast);
1013 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1014 I40E_GLPRT_MPTCL(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->eth.tx_multicast,
1017 &nsd->eth.tx_multicast);
1018 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1019 I40E_GLPRT_BPTCL(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->eth.tx_broadcast,
1022 &nsd->eth.tx_broadcast);
41c445ff 1023
7812fddc
SN		 1024 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->tx_dropped_link_down,
1027 &nsd->tx_dropped_link_down);
41c445ff 1028
7812fddc
SN		 1029 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1032
7812fddc
SN		 1033 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1036
7812fddc
SN		 1037 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->mac_local_faults,
1040 &nsd->mac_local_faults);
1041 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->mac_remote_faults,
1044 &nsd->mac_remote_faults);
41c445ff 1045
7812fddc
SN		 1046 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->rx_length_errors,
1049 &nsd->rx_length_errors);
41c445ff 1050
7812fddc
SN		 1051 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->link_xon_rx, &nsd->link_xon_rx);
1054 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->link_xon_tx, &nsd->link_xon_tx);
1057 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1058 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1061
7812fddc
SN		 1062 for (i = 0; i < 8; i++) {
1063 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1064 pf->stat_offsets_loaded,
7812fddc
SN		 1065 &osd->priority_xon_rx[i],
1066 &nsd->priority_xon_rx[i]);
1067 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1068 pf->stat_offsets_loaded,
7812fddc
SN		 1069 &osd->priority_xon_tx[i],
1070 &nsd->priority_xon_tx[i]);
1071 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1072 pf->stat_offsets_loaded,
7812fddc
SN		 1073 &osd->priority_xoff_tx[i],
1074 &nsd->priority_xoff_tx[i]);
1075 i40e_stat_update32(hw,
1076 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1077 pf->stat_offsets_loaded,
7812fddc
SN		 1078 &osd->priority_xon_2_xoff[i],
1079 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1080 }
1081
7812fddc
SN		 1082 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1083 I40E_GLPRT_PRC64L(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_size_64, &nsd->rx_size_64);
1086 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1087 I40E_GLPRT_PRC127L(hw->port),
1088 pf->stat_offsets_loaded,
1089 &osd->rx_size_127, &nsd->rx_size_127);
1090 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1091 I40E_GLPRT_PRC255L(hw->port),
1092 pf->stat_offsets_loaded,
1093 &osd->rx_size_255, &nsd->rx_size_255);
1094 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1095 I40E_GLPRT_PRC511L(hw->port),
1096 pf->stat_offsets_loaded,
1097 &osd->rx_size_511, &nsd->rx_size_511);
1098 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1099 I40E_GLPRT_PRC1023L(hw->port),
1100 pf->stat_offsets_loaded,
1101 &osd->rx_size_1023, &nsd->rx_size_1023);
1102 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1103 I40E_GLPRT_PRC1522L(hw->port),
1104 pf->stat_offsets_loaded,
1105 &osd->rx_size_1522, &nsd->rx_size_1522);
1106 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1107 I40E_GLPRT_PRC9522L(hw->port),
1108 pf->stat_offsets_loaded,
1109 &osd->rx_size_big, &nsd->rx_size_big);
1110
1111 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1112 I40E_GLPRT_PTC64L(hw->port),
1113 pf->stat_offsets_loaded,
1114 &osd->tx_size_64, &nsd->tx_size_64);
1115 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1116 I40E_GLPRT_PTC127L(hw->port),
1117 pf->stat_offsets_loaded,
1118 &osd->tx_size_127, &nsd->tx_size_127);
1119 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1120 I40E_GLPRT_PTC255L(hw->port),
1121 pf->stat_offsets_loaded,
1122 &osd->tx_size_255, &nsd->tx_size_255);
1123 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1124 I40E_GLPRT_PTC511L(hw->port),
1125 pf->stat_offsets_loaded,
1126 &osd->tx_size_511, &nsd->tx_size_511);
1127 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1128 I40E_GLPRT_PTC1023L(hw->port),
1129 pf->stat_offsets_loaded,
1130 &osd->tx_size_1023, &nsd->tx_size_1023);
1131 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1132 I40E_GLPRT_PTC1522L(hw->port),
1133 pf->stat_offsets_loaded,
1134 &osd->tx_size_1522, &nsd->tx_size_1522);
1135 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1136 I40E_GLPRT_PTC9522L(hw->port),
1137 pf->stat_offsets_loaded,
1138 &osd->tx_size_big, &nsd->tx_size_big);
1139
1140 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1141 pf->stat_offsets_loaded,
1142 &osd->rx_undersize, &nsd->rx_undersize);
1143 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1144 pf->stat_offsets_loaded,
1145 &osd->rx_fragments, &nsd->rx_fragments);
1146 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1147 pf->stat_offsets_loaded,
1148 &osd->rx_oversize, &nsd->rx_oversize);
1149 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1150 pf->stat_offsets_loaded,
1151 &osd->rx_jabber, &nsd->rx_jabber);
1152
433c47de 1153 /* FDIR stats */
0bf4b1b0
ASJ		 1154 i40e_stat_update32(hw,
1155 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1156 pf->stat_offsets_loaded,
1157 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1158 i40e_stat_update32(hw,
1159 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1160 pf->stat_offsets_loaded,
1161 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1162 i40e_stat_update32(hw,
1163 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1164 pf->stat_offsets_loaded,
1165 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1166
7812fddc
SN		 1167 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1168 nsd->tx_lpi_status =
1169 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1170 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1171 nsd->rx_lpi_status =
1172 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1173 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1174 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1175 pf->stat_offsets_loaded,
1176 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1177 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1178 pf->stat_offsets_loaded,
1179 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1180
d0389e51
ASJ		 1181 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1182 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1183 nsd->fd_sb_status = true;
1184 else
1185 nsd->fd_sb_status = false;
1186
1187 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1188 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1189 nsd->fd_atr_status = true;
1190 else
1191 nsd->fd_atr_status = false;
1192
41c445ff
JB		 1193 pf->stat_offsets_loaded = true;
1194}
1195
7812fddc
SN		 1196/**
1197 * i40e_update_stats - Update the various statistics counters.
1198 * @vsi: the VSI to be updated
1199 *
1200 * Update the various stats for this VSI and its related entities.
1201 **/
1202void i40e_update_stats(struct i40e_vsi *vsi)
1203{
1204 struct i40e_pf *pf = vsi->back;
1205
1206 if (vsi == pf->vsi[pf->lan_vsi])
1207 i40e_update_pf_stats(pf);
1208
1209 i40e_update_vsi_stats(vsi);
38e00438
VD		 1210#ifdef I40E_FCOE
1211 i40e_update_fcoe_stats(vsi);
1212#endif
7812fddc
SN		 1213}
1214
41c445ff
JB		 1215/**
1216 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1217 * @vsi: the VSI to be searched
1218 * @macaddr: the MAC address
1219 * @vlan: the vlan
b40c82e6 1220 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1221 * @is_netdev: make sure its a netdev filter, else doesn't matter
1222 *
1223 * Returns ptr to the filter object or NULL
1224 **/
1225static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1226 u8 *macaddr, s16 vlan,
1227 bool is_vf, bool is_netdev)
1228{
1229 struct i40e_mac_filter *f;
1230
1231 if (!vsi || !macaddr)
1232 return NULL;
1233
1234 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1235 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1236 (vlan == f->vlan) &&
1237 (!is_vf || f->is_vf) &&
1238 (!is_netdev || f->is_netdev))
1239 return f;
1240 }
1241 return NULL;
1242}
1243
1244/**
1245 * i40e_find_mac - Find a mac addr in the macvlan filters list
1246 * @vsi: the VSI to be searched
1247 * @macaddr: the MAC address we are searching for
b40c82e6 1248 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1249 * @is_netdev: make sure its a netdev filter, else doesn't matter
1250 *
1251 * Returns the first filter with the provided MAC address or NULL if
1252 * MAC address was not found
1253 **/
1254struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1255 bool is_vf, bool is_netdev)
1256{
1257 struct i40e_mac_filter *f;
1258
1259 if (!vsi || !macaddr)
1260 return NULL;
1261
1262 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1263 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1264 (!is_vf || f->is_vf) &&
1265 (!is_netdev || f->is_netdev))
1266 return f;
1267 }
1268 return NULL;
1269}
1270
1271/**
1272 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1273 * @vsi: the VSI to be searched
1274 *
1275 * Returns true if VSI is in vlan mode or false otherwise
1276 **/
1277bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1278{
1279 struct i40e_mac_filter *f;
1280
1281 /* Only -1 for all the filters denotes not in vlan mode
1282 * so we have to go through all the list in order to make sure
1283 */
1284 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1285 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1286 return true;
1287 }
1288
1289 return false;
1290}
1291
1292/**
1293 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1294 * @vsi: the VSI to be searched
1295 * @macaddr: the mac address to be filtered
b40c82e6 1296 * @is_vf: true if it is a VF
41c445ff
JB		 1297 * @is_netdev: true if it is a netdev
1298 *
1299 * Goes through all the macvlan filters and adds a
1300 * macvlan filter for each unique vlan that already exists
1301 *
1302 * Returns first filter found on success, else NULL
1303 **/
1304struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1305 bool is_vf, bool is_netdev)
1306{
1307 struct i40e_mac_filter *f;
1308
1309 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1310 if (vsi->info.pvid)
1311 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1312 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1313 is_vf, is_netdev)) {
1314 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1315 is_vf, is_netdev))
41c445ff
JB		 1316 return NULL;
1317 }
1318 }
1319
1320 return list_first_entry_or_null(&vsi->mac_filter_list,
1321 struct i40e_mac_filter, list);
1322}
1323
8c27d42e
GR		 1324/**
1325 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1326 * @vsi: the PF Main VSI - inappropriate for any other VSI
1327 * @macaddr: the MAC address
30650cc5
SN		 1328 *
1329 * Some older firmware configurations set up a default promiscuous VLAN
1330 * filter that needs to be removed.
8c27d42e 1331 **/
30650cc5 1332static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1333{
1334 struct i40e_aqc_remove_macvlan_element_data element;
1335 struct i40e_pf *pf = vsi->back;
f1c7e72e 1336 i40e_status ret;
8c27d42e
GR		 1337
1338 /* Only appropriate for the PF main VSI */
1339 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1340 return -EINVAL;
8c27d42e 1341
30650cc5 1342 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1343 ether_addr_copy(element.mac_addr, macaddr);
1344 element.vlan_tag = 0;
1345 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1346 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1347 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1348 if (ret)
30650cc5
SN		 1349 return -ENOENT;
1350
1351 return 0;
8c27d42e
GR		 1352}
1353
41c445ff
JB		 1354/**
1355 * i40e_add_filter - Add a mac/vlan filter to the VSI
1356 * @vsi: the VSI to be searched
1357 * @macaddr: the MAC address
1358 * @vlan: the vlan
b40c82e6 1359 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1360 * @is_netdev: make sure its a netdev filter, else doesn't matter
1361 *
1362 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1363 *
1364 * NOTE: This function is expected to be called with mac_filter_list_lock
1365 * being held.
41c445ff
JB		 1366 **/
1367struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1368 u8 *macaddr, s16 vlan,
1369 bool is_vf, bool is_netdev)
1370{
1371 struct i40e_mac_filter *f;
1372
1373 if (!vsi || !macaddr)
1374 return NULL;
1375
1376 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1377 if (!f) {
1378 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1379 if (!f)
1380 goto add_filter_out;
1381
9a173901 1382 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1383 f->vlan = vlan;
1384 f->changed = true;
1385
1386 INIT_LIST_HEAD(&f->list);
1387 list_add(&f->list, &vsi->mac_filter_list);
1388 }
1389
1390 /* increment counter and add a new flag if needed */
1391 if (is_vf) {
1392 if (!f->is_vf) {
1393 f->is_vf = true;
1394 f->counter++;
1395 }
1396 } else if (is_netdev) {
1397 if (!f->is_netdev) {
1398 f->is_netdev = true;
1399 f->counter++;
1400 }
1401 } else {
1402 f->counter++;
1403 }
1404
1405 /* changed tells sync_filters_subtask to
1406 * push the filter down to the firmware
1407 */
1408 if (f->changed) {
1409 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1410 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1411 }
1412
1413add_filter_out:
1414 return f;
1415}
1416
1417/**
1418 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1419 * @vsi: the VSI to be searched
1420 * @macaddr: the MAC address
1421 * @vlan: the vlan
b40c82e6 1422 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1423 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1424 *
1425 * NOTE: This function is expected to be called with mac_filter_list_lock
1426 * being held.
41c445ff
JB		 1427 **/
1428void i40e_del_filter(struct i40e_vsi *vsi,
1429 u8 *macaddr, s16 vlan,
1430 bool is_vf, bool is_netdev)
1431{
1432 struct i40e_mac_filter *f;
1433
1434 if (!vsi || !macaddr)
1435 return;
1436
1437 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1438 if (!f || f->counter == 0)
1439 return;
1440
1441 if (is_vf) {
1442 if (f->is_vf) {
1443 f->is_vf = false;
1444 f->counter--;
1445 }
1446 } else if (is_netdev) {
1447 if (f->is_netdev) {
1448 f->is_netdev = false;
1449 f->counter--;
1450 }
1451 } else {
b40c82e6 1452 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1453 int min_f = 0;
6995b36c 1454
41c445ff
JB		 1455 min_f += (f->is_vf ? 1 : 0);
1456 min_f += (f->is_netdev ? 1 : 0);
1457
1458 if (f->counter > min_f)
1459 f->counter--;
1460 }
1461
1462 /* counter == 0 tells sync_filters_subtask to
1463 * remove the filter from the firmware's list
1464 */
1465 if (f->counter == 0) {
1466 f->changed = true;
1467 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1468 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1469 }
1470}
1471
1472/**
1473 * i40e_set_mac - NDO callback to set mac address
1474 * @netdev: network interface device structure
1475 * @p: pointer to an address structure
1476 *
1477 * Returns 0 on success, negative on failure
1478 **/
38e00438
VD		 1479#ifdef I40E_FCOE
1480int i40e_set_mac(struct net_device *netdev, void *p)
1481#else
41c445ff 1482static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1483#endif
41c445ff
JB		 1484{
1485 struct i40e_netdev_priv *np = netdev_priv(netdev);
1486 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1487 struct i40e_pf *pf = vsi->back;
1488 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1489 struct sockaddr *addr = p;
1490 struct i40e_mac_filter *f;
1491
1492 if (!is_valid_ether_addr(addr->sa_data))
1493 return -EADDRNOTAVAIL;
1494
30650cc5
SN		 1495 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1496 netdev_info(netdev, "already using mac address %pM\n",
1497 addr->sa_data);
1498 return 0;
1499 }
41c445ff 1500
80f6428f
ASJ		 1501 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1502 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1503 return -EADDRNOTAVAIL;
1504
30650cc5
SN		 1505 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1506 netdev_info(netdev, "returning to hw mac address %pM\n",
1507 hw->mac.addr);
1508 else
1509 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1510
41c445ff
JB		 1511 if (vsi->type == I40E_VSI_MAIN) {
1512 i40e_status ret;
6995b36c 1513
41c445ff 1514 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1515 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1516 addr->sa_data, NULL);
1517 if (ret) {
1518 netdev_info(netdev,
1519 "Addr change for Main VSI failed: %d\n",
1520 ret);
1521 return -EADDRNOTAVAIL;
1522 }
41c445ff
JB		 1523 }
1524
30650cc5
SN		 1525 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1526 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1527
30650cc5
SN		 1528 memset(&element, 0, sizeof(element));
1529 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1530 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1531 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1532 } else {
21659035 1533 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1534 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1535 false, false);
21659035 1536 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1537 }
41c445ff 1538
30650cc5
SN		 1539 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1540 struct i40e_aqc_add_macvlan_element_data element;
1541
1542 memset(&element, 0, sizeof(element));
1543 ether_addr_copy(element.mac_addr, hw->mac.addr);
1544 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1545 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1546 } else {
21659035 1547 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1548 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1549 false, false);
1550 if (f)
1551 f->is_laa = true;
21659035 1552 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1553 }
1554
30650cc5 1555 ether_addr_copy(netdev->dev_addr, addr->sa_data);
0e4425ed
JB		 1556 /* schedule our worker thread which will take care of
1557 * applying the new filter changes
1558 */
1559 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1560 return 0;
1561}
1562
1563/**
1564 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1565 * @vsi: the VSI being setup
1566 * @ctxt: VSI context structure
1567 * @enabled_tc: Enabled TCs bitmap
1568 * @is_add: True if called before Add VSI
1569 *
1570 * Setup VSI queue mapping for enabled traffic classes.
1571 **/
38e00438
VD		 1572#ifdef I40E_FCOE
1573void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1574 struct i40e_vsi_context *ctxt,
1575 u8 enabled_tc,
1576 bool is_add)
1577#else
41c445ff
JB		 1578static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1579 struct i40e_vsi_context *ctxt,
1580 u8 enabled_tc,
1581 bool is_add)
38e00438 1582#endif
41c445ff
JB		 1583{
1584 struct i40e_pf *pf = vsi->back;
1585 u16 sections = 0;
1586 u8 netdev_tc = 0;
1587 u16 numtc = 0;
1588 u16 qcount;
1589 u8 offset;
1590 u16 qmap;
1591 int i;
4e3b35b0 1592 u16 num_tc_qps = 0;
41c445ff
JB		 1593
1594 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1595 offset = 0;
1596
1597 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1598 /* Find numtc from enabled TC bitmap */
1599 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1600 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1601 numtc++;
1602 }
1603 if (!numtc) {
1604 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1605 numtc = 1;
1606 }
1607 } else {
1608 /* At least TC0 is enabled in case of non-DCB case */
1609 numtc = 1;
1610 }
1611
1612 vsi->tc_config.numtc = numtc;
1613 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1614 /* Number of queues per enabled TC */
7f9ff476
AS		 1615 /* In MFP case we can have a much lower count of MSIx
1616 * vectors available and so we need to lower the used
1617 * q count.
1618 */
26cdc443
ASJ		 1619 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1620 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1621 else
1622 qcount = vsi->alloc_queue_pairs;
7f9ff476 1623 num_tc_qps = qcount / numtc;
e25d00b8 1624 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1625
1626 /* Setup queue offset/count for all TCs for given VSI */
1627 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1628 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1629 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1630 /* TC is enabled */
41c445ff
JB		 1631 int pow, num_qps;
1632
41c445ff
JB		 1633 switch (vsi->type) {
1634 case I40E_VSI_MAIN:
acd65448
HZ		 1635 qcount = min_t(int, pf->alloc_rss_size,
1636 num_tc_qps);
41c445ff 1637 break;
38e00438
VD		 1638#ifdef I40E_FCOE
1639 case I40E_VSI_FCOE:
1640 qcount = num_tc_qps;
1641 break;
1642#endif
41c445ff
JB		 1643 case I40E_VSI_FDIR:
1644 case I40E_VSI_SRIOV:
1645 case I40E_VSI_VMDQ2:
1646 default:
4e3b35b0 1647 qcount = num_tc_qps;
41c445ff
JB		 1648 WARN_ON(i != 0);
1649 break;
1650 }
4e3b35b0
NP		 1651 vsi->tc_config.tc_info[i].qoffset = offset;
1652 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1653
1e200e4a 1654 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1655 num_qps = qcount;
41c445ff 1656 pow = 0;
41a1d04b 1657 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1658 pow++;
1659 num_qps >>= 1;
1660 }
1661
1662 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1663 qmap =
1664 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1665 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1666
4e3b35b0 1667 offset += qcount;
41c445ff
JB		 1668 } else {
1669 /* TC is not enabled so set the offset to
1670 * default queue and allocate one queue
1671 * for the given TC.
1672 */
1673 vsi->tc_config.tc_info[i].qoffset = 0;
1674 vsi->tc_config.tc_info[i].qcount = 1;
1675 vsi->tc_config.tc_info[i].netdev_tc = 0;
1676
1677 qmap = 0;
1678 }
1679 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1680 }
1681
1682 /* Set actual Tx/Rx queue pairs */
1683 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1684 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1685 if (vsi->req_queue_pairs > 0)
1686 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1687 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1688 vsi->num_queue_pairs = pf->num_lan_msix;
1689 }
41c445ff
JB		 1690
1691 /* Scheduler section valid can only be set for ADD VSI */
1692 if (is_add) {
1693 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1694
1695 ctxt->info.up_enable_bits = enabled_tc;
1696 }
1697 if (vsi->type == I40E_VSI_SRIOV) {
1698 ctxt->info.mapping_flags |=
1699 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1700 for (i = 0; i < vsi->num_queue_pairs; i++)
1701 ctxt->info.queue_mapping[i] =
1702 cpu_to_le16(vsi->base_queue + i);
1703 } else {
1704 ctxt->info.mapping_flags |=
1705 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1706 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1707 }
1708 ctxt->info.valid_sections |= cpu_to_le16(sections);
1709}
1710
1711/**
1712 * i40e_set_rx_mode - NDO callback to set the netdev filters
1713 * @netdev: network interface device structure
1714 **/
38e00438
VD		 1715#ifdef I40E_FCOE
1716void i40e_set_rx_mode(struct net_device *netdev)
1717#else
41c445ff 1718static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1719#endif
41c445ff
JB		 1720{
1721 struct i40e_netdev_priv *np = netdev_priv(netdev);
1722 struct i40e_mac_filter *f, *ftmp;
1723 struct i40e_vsi *vsi = np->vsi;
1724 struct netdev_hw_addr *uca;
1725 struct netdev_hw_addr *mca;
1726 struct netdev_hw_addr *ha;
1727
21659035
KP		 1728 spin_lock_bh(&vsi->mac_filter_list_lock);
1729
41c445ff
JB		 1730 /* add addr if not already in the filter list */
1731 netdev_for_each_uc_addr(uca, netdev) {
1732 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1733 if (i40e_is_vsi_in_vlan(vsi))
1734 i40e_put_mac_in_vlan(vsi, uca->addr,
1735 false, true);
1736 else
1737 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1738 false, true);
1739 }
1740 }
1741
1742 netdev_for_each_mc_addr(mca, netdev) {
1743 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1744 if (i40e_is_vsi_in_vlan(vsi))
1745 i40e_put_mac_in_vlan(vsi, mca->addr,
1746 false, true);
1747 else
1748 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1749 false, true);
1750 }
1751 }
1752
1753 /* remove filter if not in netdev list */
1754 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1755
1756 if (!f->is_netdev)
1757 continue;
1758
2f41f335
SN		 1759 netdev_for_each_mc_addr(mca, netdev)
1760 if (ether_addr_equal(mca->addr, f->macaddr))
1761 goto bottom_of_search_loop;
41c445ff 1762
2f41f335
SN		 1763 netdev_for_each_uc_addr(uca, netdev)
1764 if (ether_addr_equal(uca->addr, f->macaddr))
1765 goto bottom_of_search_loop;
1766
1767 for_each_dev_addr(netdev, ha)
1768 if (ether_addr_equal(ha->addr, f->macaddr))
1769 goto bottom_of_search_loop;
1770
1771 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1772 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1773
1774bottom_of_search_loop:
1775 continue;
41c445ff 1776 }
21659035 1777 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1778
1779 /* check for other flag changes */
1780 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1781 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1782 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1783 }
1784}
1785
21659035
KP		 1786/**
1787 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1788 * @src: source MAC filter entry to be clones
1789 *
1790 * Returns the pointer to newly cloned MAC filter entry or NULL
1791 * in case of error
1792 **/
1793static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1794 struct i40e_mac_filter *src)
1795{
1796 struct i40e_mac_filter *f;
1797
1798 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1799 if (!f)
1800 return NULL;
1801 *f = *src;
1802
1803 INIT_LIST_HEAD(&f->list);
1804
1805 return f;
1806}
1807
1808/**
1809 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1810 * @vsi: pointer to vsi struct
1811 * @from: Pointer to list which contains MAC filter entries - changes to
1812 * those entries needs to be undone.
1813 *
1814 * MAC filter entries from list were slated to be removed from device.
1815 **/
1816static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1817 struct list_head *from)
1818{
1819 struct i40e_mac_filter *f, *ftmp;
1820
1821 list_for_each_entry_safe(f, ftmp, from, list) {
1822 f->changed = true;
1823 /* Move the element back into MAC filter list*/
1824 list_move_tail(&f->list, &vsi->mac_filter_list);
1825 }
1826}
1827
1828/**
1829 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1830 * @vsi: pointer to vsi struct
1831 *
1832 * MAC filter entries from list were slated to be added from device.
1833 **/
1834static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1835{
1836 struct i40e_mac_filter *f, *ftmp;
1837
1838 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1839 if (!f->changed && f->counter)
1840 f->changed = true;
1841 }
1842}
1843
1844/**
1845 * i40e_cleanup_add_list - Deletes the element from add list and release
1846 * memory
1847 * @add_list: Pointer to list which contains MAC filter entries
1848 **/
1849static void i40e_cleanup_add_list(struct list_head *add_list)
1850{
1851 struct i40e_mac_filter *f, *ftmp;
1852
1853 list_for_each_entry_safe(f, ftmp, add_list, list) {
1854 list_del(&f->list);
1855 kfree(f);
1856 }
1857}
1858
41c445ff
JB		 1859/**
1860 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1861 * @vsi: ptr to the VSI
1862 *
1863 * Push any outstanding VSI filter changes through the AdminQ.
1864 *
1865 * Returns 0 or error value
1866 **/
17652c63 1867int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1868{
21659035
KP		 1869 struct list_head tmp_del_list, tmp_add_list;
1870 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1871 bool promisc_forced_on = false;
1872 bool add_happened = false;
1873 int filter_list_len = 0;
1874 u32 changed_flags = 0;
21659035 1875 bool err_cond = false;
f1c7e72e 1876 i40e_status ret = 0;
41c445ff
JB		 1877 struct i40e_pf *pf;
1878 int num_add = 0;
1879 int num_del = 0;
f1c7e72e 1880 int aq_err = 0;
41c445ff
JB		 1881 u16 cmd_flags;
1882
1883 /* empty array typed pointers, kcalloc later */
1884 struct i40e_aqc_add_macvlan_element_data *add_list;
1885 struct i40e_aqc_remove_macvlan_element_data *del_list;
1886
1887 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1888 usleep_range(1000, 2000);
1889 pf = vsi->back;
1890
1891 if (vsi->netdev) {
1892 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1893 vsi->current_netdev_flags = vsi->netdev->flags;
1894 }
1895
21659035
KP		 1896 INIT_LIST_HEAD(&tmp_del_list);
1897 INIT_LIST_HEAD(&tmp_add_list);
1898
41c445ff
JB		 1899 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1900 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1901
21659035 1902 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1903 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1904 if (!f->changed)
1905 continue;
1906
1907 if (f->counter != 0)
1908 continue;
1909 f->changed = false;
21659035
KP		 1910
1911 /* Move the element into temporary del_list */
1912 list_move_tail(&f->list, &tmp_del_list);
1913 }
1914
1915 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1916 if (!f->changed)
1917 continue;
1918
1919 if (f->counter == 0)
1920 continue;
1921 f->changed = false;
1922
1923 /* Clone MAC filter entry and add into temporary list */
1924 fclone = i40e_mac_filter_entry_clone(f);
1925 if (!fclone) {
1926 err_cond = true;
1927 break;
1928 }
1929 list_add_tail(&fclone->list, &tmp_add_list);
1930 }
1931
1932 /* if failed to clone MAC filter entry - undo */
1933 if (err_cond) {
1934 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1935 i40e_undo_add_filter_entries(vsi);
1936 }
1937 spin_unlock_bh(&vsi->mac_filter_list_lock);
1938
1939 if (err_cond)
1940 i40e_cleanup_add_list(&tmp_add_list);
1941 }
1942
1943 /* Now process 'del_list' outside the lock */
1944 if (!list_empty(&tmp_del_list)) {
1945 filter_list_len = pf->hw.aq.asq_buf_size /
1946 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1947 del_list = kcalloc(filter_list_len,
1948 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1949 GFP_KERNEL);
1950 if (!del_list) {
1951 i40e_cleanup_add_list(&tmp_add_list);
1952
1953 /* Undo VSI's MAC filter entry element updates */
1954 spin_lock_bh(&vsi->mac_filter_list_lock);
1955 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1956 i40e_undo_add_filter_entries(vsi);
1957 spin_unlock_bh(&vsi->mac_filter_list_lock);
1958 return -ENOMEM;
1959 }
1960
1961 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1962 cmd_flags = 0;
1963
1964 /* add to delete list */
9a173901 1965 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1966 del_list[num_del].vlan_tag =
1967 cpu_to_le16((u16)(f->vlan ==
1968 I40E_VLAN_ANY ? 0 : f->vlan));
1969
41c445ff
JB		 1970 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1971 del_list[num_del].flags = cmd_flags;
1972 num_del++;
1973
41c445ff
JB		 1974 /* flush a full buffer */
1975 if (num_del == filter_list_len) {
f1c7e72e
SN		 1976 ret = i40e_aq_remove_macvlan(&pf->hw,
1977 vsi->seid, del_list, num_del,
1978 NULL);
1979 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1980 num_del = 0;
1981 memset(del_list, 0, sizeof(*del_list));
1982
f1c7e72e 1983 if (ret && aq_err != I40E_AQ_RC_ENOENT)
21659035
KP		 1984 dev_err(&pf->pdev->dev,
1985 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1986 i40e_stat_str(&pf->hw, ret),
1987 i40e_aq_str(&pf->hw, aq_err));
41c445ff 1988 }
21659035
KP		 1989 /* Release memory for MAC filter entries which were
1990 * synced up with HW.
1991 */
1992 list_del(&f->list);
1993 kfree(f);
41c445ff 1994 }
21659035 1995
41c445ff 1996 if (num_del) {
f1c7e72e 1997 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1998 del_list, num_del, NULL);
f1c7e72e 1999 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2000 num_del = 0;
2001
f1c7e72e 2002 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 2003 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2004 "ignoring delete macvlan error, err %s aq_err %s\n",
2005 i40e_stat_str(&pf->hw, ret),
2006 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2007 }
2008
2009 kfree(del_list);
2010 del_list = NULL;
21659035
KP		 2011 }
2012
2013 if (!list_empty(&tmp_add_list)) {
41c445ff
JB		 2014
2015 /* do all the adds now */
2016 filter_list_len = pf->hw.aq.asq_buf_size /
2017 sizeof(struct i40e_aqc_add_macvlan_element_data),
2018 add_list = kcalloc(filter_list_len,
2019 sizeof(struct i40e_aqc_add_macvlan_element_data),
2020 GFP_KERNEL);
21659035
KP		 2021 if (!add_list) {
2022 /* Purge element from temporary lists */
2023 i40e_cleanup_add_list(&tmp_add_list);
2024
2025 /* Undo add filter entries from VSI MAC filter list */
2026 spin_lock_bh(&vsi->mac_filter_list_lock);
2027 i40e_undo_add_filter_entries(vsi);
2028 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 2029 return -ENOMEM;
21659035 2030 }
41c445ff 2031
21659035 2032 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2033
41c445ff
JB		 2034 add_happened = true;
2035 cmd_flags = 0;
2036
2037 /* add to add array */
9a173901 2038 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2039 add_list[num_add].vlan_tag =
2040 cpu_to_le16(
2041 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2042 add_list[num_add].queue_number = 0;
2043
2044 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2045 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2046 num_add++;
2047
2048 /* flush a full buffer */
2049 if (num_add == filter_list_len) {
f1c7e72e
SN		 2050 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2051 add_list, num_add,
2052 NULL);
2053 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2054 num_add = 0;
2055
f1c7e72e 2056 if (ret)
41c445ff
JB		 2057 break;
2058 memset(add_list, 0, sizeof(*add_list));
2059 }
21659035
KP		 2060 /* Entries from tmp_add_list were cloned from MAC
2061 * filter list, hence clean those cloned entries
2062 */
2063 list_del(&f->list);
2064 kfree(f);
41c445ff 2065 }
21659035 2066
41c445ff 2067 if (num_add) {
f1c7e72e
SN		 2068 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2069 add_list, num_add, NULL);
2070 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2071 num_add = 0;
2072 }
2073 kfree(add_list);
2074 add_list = NULL;
2075
f1c7e72e 2076 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 2077 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2078 "add filter failed, err %s aq_err %s\n",
2079 i40e_stat_str(&pf->hw, ret),
2080 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2081 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2082 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2083 &vsi->state)) {
2084 promisc_forced_on = true;
2085 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2086 &vsi->state);
2087 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2088 }
2089 }
2090 }
2091
2092 /* check for changes in promiscuous modes */
2093 if (changed_flags & IFF_ALLMULTI) {
2094 bool cur_multipromisc;
6995b36c 2095
41c445ff 2096 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 2097 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2098 vsi->seid,
2099 cur_multipromisc,
2100 NULL);
2101 if (ret)
41c445ff 2102 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2103 "set multi promisc failed, err %s aq_err %s\n",
2104 i40e_stat_str(&pf->hw, ret),
2105 i40e_aq_str(&pf->hw,
2106 pf->hw.aq.asq_last_status));
41c445ff
JB		 2107 }
2108 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2109 bool cur_promisc;
6995b36c 2110
41c445ff
JB		 2111 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2112 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2113 &vsi->state));
92faef85
ASJ		 2114 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2115 /* set defport ON for Main VSI instead of true promisc
2116 * this way we will get all unicast/multicast and VLAN
2117 * promisc behavior but will not get VF or VMDq traffic
2118 * replicated on the Main VSI.
2119 */
2120 if (pf->cur_promisc != cur_promisc) {
2121 pf->cur_promisc = cur_promisc;
0e4425ed 2122 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2123 }
2124 } else {
2125 ret = i40e_aq_set_vsi_unicast_promiscuous(
2126 &vsi->back->hw,
f1c7e72e
SN		 2127 vsi->seid,
2128 cur_promisc, NULL);
92faef85
ASJ		 2129 if (ret)
2130 dev_info(&pf->pdev->dev,
2131 "set unicast promisc failed, err %d, aq_err %d\n",
2132 ret, pf->hw.aq.asq_last_status);
2133 ret = i40e_aq_set_vsi_multicast_promiscuous(
2134 &vsi->back->hw,
2135 vsi->seid,
2136 cur_promisc, NULL);
2137 if (ret)
2138 dev_info(&pf->pdev->dev,
2139 "set multicast promisc failed, err %d, aq_err %d\n",
2140 ret, pf->hw.aq.asq_last_status);
2141 }
f1c7e72e
SN		 2142 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2143 vsi->seid,
2144 cur_promisc, NULL);
2145 if (ret)
1a10370a 2146 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2147 "set brdcast promisc failed, err %s, aq_err %s\n",
2148 i40e_stat_str(&pf->hw, ret),
2149 i40e_aq_str(&pf->hw,
2150 pf->hw.aq.asq_last_status));
41c445ff
JB		 2151 }
2152
2153 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2154 return 0;
2155}
2156
2157/**
2158 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2159 * @pf: board private structure
2160 **/
2161static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2162{
2163 int v;
2164
2165 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2166 return;
2167 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2168
505682cd 2169 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2170 if (pf->vsi[v] &&
17652c63
JB		 2171 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2172 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2173
2174 if (ret) {
2175 /* come back and try again later */
2176 pf->flags |= I40E_FLAG_FILTER_SYNC;
2177 break;
2178 }
2179 }
41c445ff
JB		 2180 }
2181}
2182
2183/**
2184 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2185 * @netdev: network interface device structure
2186 * @new_mtu: new value for maximum frame size
2187 *
2188 * Returns 0 on success, negative on failure
2189 **/
2190static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2191{
2192 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2193 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2194 struct i40e_vsi *vsi = np->vsi;
2195
2196 /* MTU < 68 is an error and causes problems on some kernels */
2197 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2198 return -EINVAL;
2199
2200 netdev_info(netdev, "changing MTU from %d to %d\n",
2201 netdev->mtu, new_mtu);
2202 netdev->mtu = new_mtu;
2203 if (netif_running(netdev))
2204 i40e_vsi_reinit_locked(vsi);
2205
2206 return 0;
2207}
2208
beb0dff1
JK		 2209/**
2210 * i40e_ioctl - Access the hwtstamp interface
2211 * @netdev: network interface device structure
2212 * @ifr: interface request data
2213 * @cmd: ioctl command
2214 **/
2215int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2216{
2217 struct i40e_netdev_priv *np = netdev_priv(netdev);
2218 struct i40e_pf *pf = np->vsi->back;
2219
2220 switch (cmd) {
2221 case SIOCGHWTSTAMP:
2222 return i40e_ptp_get_ts_config(pf, ifr);
2223 case SIOCSHWTSTAMP:
2224 return i40e_ptp_set_ts_config(pf, ifr);
2225 default:
2226 return -EOPNOTSUPP;
2227 }
2228}
2229
41c445ff
JB		 2230/**
2231 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2232 * @vsi: the vsi being adjusted
2233 **/
2234void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2235{
2236 struct i40e_vsi_context ctxt;
2237 i40e_status ret;
2238
2239 if ((vsi->info.valid_sections &
2240 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2241 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2242 return; /* already enabled */
2243
2244 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2245 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2246 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2247
2248 ctxt.seid = vsi->seid;
1a2f6248 2249 ctxt.info = vsi->info;
41c445ff
JB		 2250 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2251 if (ret) {
2252 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2253 "update vlan stripping failed, err %s aq_err %s\n",
2254 i40e_stat_str(&vsi->back->hw, ret),
2255 i40e_aq_str(&vsi->back->hw,
2256 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2257 }
2258}
2259
2260/**
2261 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2262 * @vsi: the vsi being adjusted
2263 **/
2264void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2265{
2266 struct i40e_vsi_context ctxt;
2267 i40e_status ret;
2268
2269 if ((vsi->info.valid_sections &
2270 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2271 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2272 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2273 return; /* already disabled */
2274
2275 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2276 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2277 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2278
2279 ctxt.seid = vsi->seid;
1a2f6248 2280 ctxt.info = vsi->info;
41c445ff
JB		 2281 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2282 if (ret) {
2283 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2284 "update vlan stripping failed, err %s aq_err %s\n",
2285 i40e_stat_str(&vsi->back->hw, ret),
2286 i40e_aq_str(&vsi->back->hw,
2287 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2288 }
2289}
2290
2291/**
2292 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2293 * @netdev: network interface to be adjusted
2294 * @features: netdev features to test if VLAN offload is enabled or not
2295 **/
2296static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2297{
2298 struct i40e_netdev_priv *np = netdev_priv(netdev);
2299 struct i40e_vsi *vsi = np->vsi;
2300
2301 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2302 i40e_vlan_stripping_enable(vsi);
2303 else
2304 i40e_vlan_stripping_disable(vsi);
2305}
2306
2307/**
2308 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2309 * @vsi: the vsi being configured
2310 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2311 **/
2312int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2313{
2314 struct i40e_mac_filter *f, *add_f;
2315 bool is_netdev, is_vf;
41c445ff
JB		 2316
2317 is_vf = (vsi->type == I40E_VSI_SRIOV);
2318 is_netdev = !!(vsi->netdev);
2319
21659035
KP		 2320 /* Locked once because all functions invoked below iterates list*/
2321 spin_lock_bh(&vsi->mac_filter_list_lock);
2322
41c445ff
JB		 2323 if (is_netdev) {
2324 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2325 is_vf, is_netdev);
2326 if (!add_f) {
2327 dev_info(&vsi->back->pdev->dev,
2328 "Could not add vlan filter %d for %pM\n",
2329 vid, vsi->netdev->dev_addr);
21659035 2330 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2331 return -ENOMEM;
2332 }
2333 }
2334
2335 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2336 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2337 if (!add_f) {
2338 dev_info(&vsi->back->pdev->dev,
2339 "Could not add vlan filter %d for %pM\n",
2340 vid, f->macaddr);
21659035 2341 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2342 return -ENOMEM;
2343 }
2344 }
2345
41c445ff
JB		 2346 /* Now if we add a vlan tag, make sure to check if it is the first
2347 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2348 * with 0, so we now accept untagged and specified tagged traffic
2349 * (and not any taged and untagged)
2350 */
2351 if (vid > 0) {
2352 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2353 I40E_VLAN_ANY,
2354 is_vf, is_netdev)) {
2355 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2356 I40E_VLAN_ANY, is_vf, is_netdev);
2357 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2358 is_vf, is_netdev);
2359 if (!add_f) {
2360 dev_info(&vsi->back->pdev->dev,
2361 "Could not add filter 0 for %pM\n",
2362 vsi->netdev->dev_addr);
21659035 2363 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2364 return -ENOMEM;
2365 }
2366 }
8d82a7c5 2367 }
41c445ff 2368
8d82a7c5
GR		 2369 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2370 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2371 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2372 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2373 is_vf, is_netdev))
2374 continue;
2375 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2376 is_vf, is_netdev);
2377 add_f = i40e_add_filter(vsi, f->macaddr,
2378 0, is_vf, is_netdev);
2379 if (!add_f) {
2380 dev_info(&vsi->back->pdev->dev,
2381 "Could not add filter 0 for %pM\n",
2382 f->macaddr);
2383 spin_unlock_bh(&vsi->mac_filter_list_lock);
2384 return -ENOMEM;
41c445ff
JB		 2385 }
2386 }
41c445ff
JB		 2387 }
2388
21659035
KP		 2389 spin_unlock_bh(&vsi->mac_filter_list_lock);
2390
0e4425ed
JB		 2391 /* schedule our worker thread which will take care of
2392 * applying the new filter changes
2393 */
2394 i40e_service_event_schedule(vsi->back);
2395 return 0;
41c445ff
JB		 2396}
2397
2398/**
2399 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2400 * @vsi: the vsi being configured
2401 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2402 *
2403 * Return: 0 on success or negative otherwise
41c445ff
JB		 2404 **/
2405int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2406{
2407 struct net_device *netdev = vsi->netdev;
2408 struct i40e_mac_filter *f, *add_f;
2409 bool is_vf, is_netdev;
2410 int filter_count = 0;
41c445ff
JB		 2411
2412 is_vf = (vsi->type == I40E_VSI_SRIOV);
2413 is_netdev = !!(netdev);
2414
21659035
KP		 2415 /* Locked once because all functions invoked below iterates list */
2416 spin_lock_bh(&vsi->mac_filter_list_lock);
2417
41c445ff
JB		 2418 if (is_netdev)
2419 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2420
2421 list_for_each_entry(f, &vsi->mac_filter_list, list)
2422 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2423
41c445ff
JB		 2424 /* go through all the filters for this VSI and if there is only
2425 * vid == 0 it means there are no other filters, so vid 0 must
2426 * be replaced with -1. This signifies that we should from now
2427 * on accept any traffic (with any tag present, or untagged)
2428 */
2429 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2430 if (is_netdev) {
2431 if (f->vlan &&
2432 ether_addr_equal(netdev->dev_addr, f->macaddr))
2433 filter_count++;
2434 }
2435
2436 if (f->vlan)
2437 filter_count++;
2438 }
2439
2440 if (!filter_count && is_netdev) {
2441 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2442 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2443 is_vf, is_netdev);
2444 if (!f) {
2445 dev_info(&vsi->back->pdev->dev,
2446 "Could not add filter %d for %pM\n",
2447 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2448 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2449 return -ENOMEM;
2450 }
2451 }
2452
2453 if (!filter_count) {
2454 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2455 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2456 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2457 is_vf, is_netdev);
41c445ff
JB		 2458 if (!add_f) {
2459 dev_info(&vsi->back->pdev->dev,
2460 "Could not add filter %d for %pM\n",
2461 I40E_VLAN_ANY, f->macaddr);
21659035 2462 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2463 return -ENOMEM;
2464 }
2465 }
2466 }
2467
21659035
KP		 2468 spin_unlock_bh(&vsi->mac_filter_list_lock);
2469
0e4425ed
JB		 2470 /* schedule our worker thread which will take care of
2471 * applying the new filter changes
2472 */
2473 i40e_service_event_schedule(vsi->back);
2474 return 0;
41c445ff
JB		 2475}
2476
2477/**
2478 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2479 * @netdev: network interface to be adjusted
2480 * @vid: vlan id to be added
078b5876
JB		 2481 *
2482 * net_device_ops implementation for adding vlan ids
41c445ff 2483 **/
38e00438
VD		 2484#ifdef I40E_FCOE
2485int i40e_vlan_rx_add_vid(struct net_device *netdev,
2486 __always_unused __be16 proto, u16 vid)
2487#else
41c445ff
JB		 2488static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2489 __always_unused __be16 proto, u16 vid)
38e00438 2490#endif
41c445ff
JB		 2491{
2492 struct i40e_netdev_priv *np = netdev_priv(netdev);
2493 struct i40e_vsi *vsi = np->vsi;
078b5876 2494 int ret = 0;
41c445ff
JB		 2495
2496 if (vid > 4095)
078b5876
JB		 2497 return -EINVAL;
2498
2499 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2500
6982d429
ASJ		 2501 /* If the network stack called us with vid = 0 then
2502 * it is asking to receive priority tagged packets with
2503 * vlan id 0. Our HW receives them by default when configured
2504 * to receive untagged packets so there is no need to add an
2505 * extra filter for vlan 0 tagged packets.
41c445ff 2506 */
6982d429
ASJ		 2507 if (vid)
2508 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2509
078b5876
JB		 2510 if (!ret && (vid < VLAN_N_VID))
2511 set_bit(vid, vsi->active_vlans);
41c445ff 2512
078b5876 2513 return ret;
41c445ff
JB		 2514}
2515
2516/**
2517 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2518 * @netdev: network interface to be adjusted
2519 * @vid: vlan id to be removed
078b5876 2520 *
fdfd943e 2521 * net_device_ops implementation for removing vlan ids
41c445ff 2522 **/
38e00438
VD		 2523#ifdef I40E_FCOE
2524int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2525 __always_unused __be16 proto, u16 vid)
2526#else
41c445ff
JB		 2527static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2528 __always_unused __be16 proto, u16 vid)
38e00438 2529#endif
41c445ff
JB		 2530{
2531 struct i40e_netdev_priv *np = netdev_priv(netdev);
2532 struct i40e_vsi *vsi = np->vsi;
2533
078b5876
JB		 2534 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2535
41c445ff
JB		 2536 /* return code is ignored as there is nothing a user
2537 * can do about failure to remove and a log message was
078b5876 2538 * already printed from the other function
41c445ff
JB		 2539 */
2540 i40e_vsi_kill_vlan(vsi, vid);
2541
2542 clear_bit(vid, vsi->active_vlans);
078b5876 2543
41c445ff
JB		 2544 return 0;
2545}
2546
2547/**
2548 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2549 * @vsi: the vsi being brought back up
2550 **/
2551static void i40e_restore_vlan(struct i40e_vsi *vsi)
2552{
2553 u16 vid;
2554
2555 if (!vsi->netdev)
2556 return;
2557
2558 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2559
2560 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2561 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2562 vid);
2563}
2564
2565/**
2566 * i40e_vsi_add_pvid - Add pvid for the VSI
2567 * @vsi: the vsi being adjusted
2568 * @vid: the vlan id to set as a PVID
2569 **/
dcae29be 2570int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2571{
2572 struct i40e_vsi_context ctxt;
f1c7e72e 2573 i40e_status ret;
41c445ff
JB		 2574
2575 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2576 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2577 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2578 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2579 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2580
2581 ctxt.seid = vsi->seid;
1a2f6248 2582 ctxt.info = vsi->info;
f1c7e72e
SN		 2583 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2584 if (ret) {
41c445ff 2585 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2586 "add pvid failed, err %s aq_err %s\n",
2587 i40e_stat_str(&vsi->back->hw, ret),
2588 i40e_aq_str(&vsi->back->hw,
2589 vsi->back->hw.aq.asq_last_status));
dcae29be 2590 return -ENOENT;
41c445ff
JB		 2591 }
2592
dcae29be 2593 return 0;
41c445ff
JB		 2594}
2595
2596/**
2597 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2598 * @vsi: the vsi being adjusted
2599 *
2600 * Just use the vlan_rx_register() service to put it back to normal
2601 **/
2602void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2603{
6c12fcbf
GR		 2604 i40e_vlan_stripping_disable(vsi);
2605
41c445ff 2606 vsi->info.pvid = 0;
41c445ff
JB		 2607}
2608
2609/**
2610 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2611 * @vsi: ptr to the VSI
2612 *
2613 * If this function returns with an error, then it's possible one or
2614 * more of the rings is populated (while the rest are not). It is the
2615 * callers duty to clean those orphaned rings.
2616 *
2617 * Return 0 on success, negative on failure
2618 **/
2619static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2620{
2621 int i, err = 0;
2622
2623 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2624 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2625
2626 return err;
2627}
2628
2629/**
2630 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2631 * @vsi: ptr to the VSI
2632 *
2633 * Free VSI's transmit software resources
2634 **/
2635static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2636{
2637 int i;
2638
8e9dca53
GR		 2639 if (!vsi->tx_rings)
2640 return;
2641
41c445ff 2642 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2643 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2644 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2645}
2646
2647/**
2648 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2649 * @vsi: ptr to the VSI
2650 *
2651 * If this function returns with an error, then it's possible one or
2652 * more of the rings is populated (while the rest are not). It is the
2653 * callers duty to clean those orphaned rings.
2654 *
2655 * Return 0 on success, negative on failure
2656 **/
2657static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2658{
2659 int i, err = 0;
2660
2661 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2662 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2663#ifdef I40E_FCOE
2664 i40e_fcoe_setup_ddp_resources(vsi);
2665#endif
41c445ff
JB		 2666 return err;
2667}
2668
2669/**
2670 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2671 * @vsi: ptr to the VSI
2672 *
2673 * Free all receive software resources
2674 **/
2675static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2676{
2677 int i;
2678
8e9dca53
GR		 2679 if (!vsi->rx_rings)
2680 return;
2681
41c445ff 2682 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2683 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2684 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2685#ifdef I40E_FCOE
2686 i40e_fcoe_free_ddp_resources(vsi);
2687#endif
41c445ff
JB		 2688}
2689
3ffa037d
NP		 2690/**
2691 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2692 * @ring: The Tx ring to configure
2693 *
2694 * This enables/disables XPS for a given Tx descriptor ring
2695 * based on the TCs enabled for the VSI that ring belongs to.
2696 **/
2697static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2698{
2699 struct i40e_vsi *vsi = ring->vsi;
2700 cpumask_var_t mask;
2701
9a660eea
JB		 2702 if (!ring->q_vector || !ring->netdev)
2703 return;
2704
2705 /* Single TC mode enable XPS */
2706 if (vsi->tc_config.numtc <= 1) {
2707 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2708 netif_set_xps_queue(ring->netdev,
2709 &ring->q_vector->affinity_mask,
2710 ring->queue_index);
9a660eea
JB		 2711 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2712 /* Disable XPS to allow selection based on TC */
2713 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2714 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2715 free_cpumask_var(mask);
3ffa037d 2716 }
0e4425ed
JB		 2717
2718 /* schedule our worker thread which will take care of
2719 * applying the new filter changes
2720 */
2721 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2722}
2723
41c445ff
JB		 2724/**
2725 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2726 * @ring: The Tx ring to configure
2727 *
2728 * Configure the Tx descriptor ring in the HMC context.
2729 **/
2730static int i40e_configure_tx_ring(struct i40e_ring *ring)
2731{
2732 struct i40e_vsi *vsi = ring->vsi;
2733 u16 pf_q = vsi->base_queue + ring->queue_index;
2734 struct i40e_hw *hw = &vsi->back->hw;
2735 struct i40e_hmc_obj_txq tx_ctx;
2736 i40e_status err = 0;
2737 u32 qtx_ctl = 0;
2738
2739 /* some ATR related tx ring init */
60ea5f83 2740 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2741 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2742 ring->atr_count = 0;
2743 } else {
2744 ring->atr_sample_rate = 0;
2745 }
2746
3ffa037d
NP		 2747 /* configure XPS */
2748 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2749
2750 /* clear the context structure first */
2751 memset(&tx_ctx, 0, sizeof(tx_ctx));
2752
2753 tx_ctx.new_context = 1;
2754 tx_ctx.base = (ring->dma / 128);
2755 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2756 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2757 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2758#ifdef I40E_FCOE
2759 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2760#endif
beb0dff1 2761 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2762 /* FDIR VSI tx ring can still use RS bit and writebacks */
2763 if (vsi->type != I40E_VSI_FDIR)
2764 tx_ctx.head_wb_ena = 1;
2765 tx_ctx.head_wb_addr = ring->dma +
2766 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2767
2768 /* As part of VSI creation/update, FW allocates certain
2769 * Tx arbitration queue sets for each TC enabled for
2770 * the VSI. The FW returns the handles to these queue
2771 * sets as part of the response buffer to Add VSI,
2772 * Update VSI, etc. AQ commands. It is expected that
2773 * these queue set handles be associated with the Tx
2774 * queues by the driver as part of the TX queue context
2775 * initialization. This has to be done regardless of
2776 * DCB as by default everything is mapped to TC0.
2777 */
2778 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2779 tx_ctx.rdylist_act = 0;
2780
2781 /* clear the context in the HMC */
2782 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2783 if (err) {
2784 dev_info(&vsi->back->pdev->dev,
2785 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2786 ring->queue_index, pf_q, err);
2787 return -ENOMEM;
2788 }
2789
2790 /* set the context in the HMC */
2791 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2792 if (err) {
2793 dev_info(&vsi->back->pdev->dev,
2794 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2795 ring->queue_index, pf_q, err);
2796 return -ENOMEM;
2797 }
2798
2799 /* Now associate this queue with this PCI function */
7a28d885 2800 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2801 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2802 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2803 I40E_QTX_CTL_VFVM_INDX_MASK;
2804 } else {
9d8bf547 2805 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2806 }
2807
13fd9774
SN		 2808 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2809 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2810 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2811 i40e_flush(hw);
2812
41c445ff
JB		 2813 /* cache tail off for easier writes later */
2814 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2815
2816 return 0;
2817}
2818
2819/**
2820 * i40e_configure_rx_ring - Configure a receive ring context
2821 * @ring: The Rx ring to configure
2822 *
2823 * Configure the Rx descriptor ring in the HMC context.
2824 **/
2825static int i40e_configure_rx_ring(struct i40e_ring *ring)
2826{
2827 struct i40e_vsi *vsi = ring->vsi;
2828 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2829 u16 pf_q = vsi->base_queue + ring->queue_index;
2830 struct i40e_hw *hw = &vsi->back->hw;
2831 struct i40e_hmc_obj_rxq rx_ctx;
2832 i40e_status err = 0;
2833
2834 ring->state = 0;
2835
2836 /* clear the context structure first */
2837 memset(&rx_ctx, 0, sizeof(rx_ctx));
2838
2839 ring->rx_buf_len = vsi->rx_buf_len;
2840 ring->rx_hdr_len = vsi->rx_hdr_len;
2841
2842 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2843 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2844
2845 rx_ctx.base = (ring->dma / 128);
2846 rx_ctx.qlen = ring->count;
2847
2848 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2849 set_ring_16byte_desc_enabled(ring);
2850 rx_ctx.dsize = 0;
2851 } else {
2852 rx_ctx.dsize = 1;
2853 }
2854
2855 rx_ctx.dtype = vsi->dtype;
2856 if (vsi->dtype) {
2857 set_ring_ps_enabled(ring);
2858 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2859 I40E_RX_SPLIT_IP |
2860 I40E_RX_SPLIT_TCP_UDP |
2861 I40E_RX_SPLIT_SCTP;
2862 } else {
2863 rx_ctx.hsplit_0 = 0;
2864 }
2865
2866 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2867 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2868 if (hw->revision_id == 0)
2869 rx_ctx.lrxqthresh = 0;
2870 else
2871 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2872 rx_ctx.crcstrip = 1;
2873 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2874 /* this controls whether VLAN is stripped from inner headers */
2875 rx_ctx.showiv = 0;
38e00438
VD		 2876#ifdef I40E_FCOE
2877 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2878#endif
acb3676b
CS		 2879 /* set the prefena field to 1 because the manual says to */
2880 rx_ctx.prefena = 1;
41c445ff
JB		 2881
2882 /* clear the context in the HMC */
2883 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2884 if (err) {
2885 dev_info(&vsi->back->pdev->dev,
2886 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2887 ring->queue_index, pf_q, err);
2888 return -ENOMEM;
2889 }
2890
2891 /* set the context in the HMC */
2892 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2893 if (err) {
2894 dev_info(&vsi->back->pdev->dev,
2895 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2896 ring->queue_index, pf_q, err);
2897 return -ENOMEM;
2898 }
2899
2900 /* cache tail for quicker writes, and clear the reg before use */
2901 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2902 writel(0, ring->tail);
2903
a132af24
MW		 2904 if (ring_is_ps_enabled(ring)) {
2905 i40e_alloc_rx_headers(ring);
2906 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2907 } else {
2908 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2909 }
41c445ff
JB		 2910
2911 return 0;
2912}
2913
2914/**
2915 * i40e_vsi_configure_tx - Configure the VSI for Tx
2916 * @vsi: VSI structure describing this set of rings and resources
2917 *
2918 * Configure the Tx VSI for operation.
2919 **/
2920static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2921{
2922 int err = 0;
2923 u16 i;
2924
9f65e15b
AD		 2925 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2926 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2927
2928 return err;
2929}
2930
2931/**
2932 * i40e_vsi_configure_rx - Configure the VSI for Rx
2933 * @vsi: the VSI being configured
2934 *
2935 * Configure the Rx VSI for operation.
2936 **/
2937static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2938{
2939 int err = 0;
2940 u16 i;
2941
2942 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2943 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2944 + ETH_FCS_LEN + VLAN_HLEN;
2945 else
2946 vsi->max_frame = I40E_RXBUFFER_2048;
2947
2948 /* figure out correct receive buffer length */
2949 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2950 I40E_FLAG_RX_PS_ENABLED)) {
2951 case I40E_FLAG_RX_1BUF_ENABLED:
2952 vsi->rx_hdr_len = 0;
2953 vsi->rx_buf_len = vsi->max_frame;
2954 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2955 break;
2956 case I40E_FLAG_RX_PS_ENABLED:
2957 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2958 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2959 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2960 break;
2961 default:
2962 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2963 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2964 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2965 break;
2966 }
2967
38e00438
VD		 2968#ifdef I40E_FCOE
2969 /* setup rx buffer for FCoE */
2970 if ((vsi->type == I40E_VSI_FCOE) &&
2971 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2972 vsi->rx_hdr_len = 0;
2973 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2974 vsi->max_frame = I40E_RXBUFFER_3072;
2975 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2976 }
2977
2978#endif /* I40E_FCOE */
41c445ff
JB		 2979 /* round up for the chip's needs */
2980 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2981 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2982 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2983 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2984
2985 /* set up individual rings */
2986 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2987 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2988
2989 return err;
2990}
2991
2992/**
2993 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2994 * @vsi: ptr to the VSI
2995 **/
2996static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2997{
e7046ee1 2998 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2999 u16 qoffset, qcount;
3000 int i, n;
3001
cd238a3e
PN		 3002 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3003 /* Reset the TC information */
3004 for (i = 0; i < vsi->num_queue_pairs; i++) {
3005 rx_ring = vsi->rx_rings[i];
3006 tx_ring = vsi->tx_rings[i];
3007 rx_ring->dcb_tc = 0;
3008 tx_ring->dcb_tc = 0;
3009 }
3010 }
41c445ff
JB		 3011
3012 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3013 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3014 continue;
3015
3016 qoffset = vsi->tc_config.tc_info[n].qoffset;
3017 qcount = vsi->tc_config.tc_info[n].qcount;
3018 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3019 rx_ring = vsi->rx_rings[i];
3020 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3021 rx_ring->dcb_tc = n;
3022 tx_ring->dcb_tc = n;
3023 }
3024 }
3025}
3026
3027/**
3028 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3029 * @vsi: ptr to the VSI
3030 **/
3031static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3032{
3033 if (vsi->netdev)
3034 i40e_set_rx_mode(vsi->netdev);
3035}
3036
17a73f6b
JG		 3037/**
3038 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3039 * @vsi: Pointer to the targeted VSI
3040 *
3041 * This function replays the hlist on the hw where all the SB Flow Director
3042 * filters were saved.
3043 **/
3044static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3045{
3046 struct i40e_fdir_filter *filter;
3047 struct i40e_pf *pf = vsi->back;
3048 struct hlist_node *node;
3049
55a5e60b
ASJ		 3050 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3051 return;
3052
17a73f6b
JG		 3053 hlist_for_each_entry_safe(filter, node,
3054 &pf->fdir_filter_list, fdir_node) {
3055 i40e_add_del_fdir(vsi, filter, true);
3056 }
3057}
3058
41c445ff
JB		 3059/**
3060 * i40e_vsi_configure - Set up the VSI for action
3061 * @vsi: the VSI being configured
3062 **/
3063static int i40e_vsi_configure(struct i40e_vsi *vsi)
3064{
3065 int err;
3066
3067 i40e_set_vsi_rx_mode(vsi);
3068 i40e_restore_vlan(vsi);
3069 i40e_vsi_config_dcb_rings(vsi);
3070 err = i40e_vsi_configure_tx(vsi);
3071 if (!err)
3072 err = i40e_vsi_configure_rx(vsi);
3073
3074 return err;
3075}
3076
3077/**
3078 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3079 * @vsi: the VSI being configured
3080 **/
3081static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3082{
3083 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3084 struct i40e_hw *hw = &pf->hw;
3085 u16 vector;
3086 int i, q;
41c445ff
JB		 3087 u32 qp;
3088
3089 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3090 * and PFINT_LNKLSTn registers, e.g.:
3091 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3092 */
3093 qp = vsi->base_queue;
3094 vector = vsi->base_vector;
493fb300 3095 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3096 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3097
ee2319cf 3098 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3099 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3100 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3101 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3102 q_vector->rx.itr);
3103 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3104 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3105 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3106 q_vector->tx.itr);
ac26fc13
JB		 3107 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3108 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3109
3110 /* Linked list for the queuepairs assigned to this vector */
3111 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3112 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3113 u32 val;
3114
41c445ff
JB		 3115 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3116 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3117 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3118 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3119 (I40E_QUEUE_TYPE_TX
3120 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3121
3122 wr32(hw, I40E_QINT_RQCTL(qp), val);
3123
3124 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3125 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3126 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3127 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3128 (I40E_QUEUE_TYPE_RX
3129 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3130
3131 /* Terminate the linked list */
3132 if (q == (q_vector->num_ringpairs - 1))
3133 val |= (I40E_QUEUE_END_OF_LIST
3134 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3135
3136 wr32(hw, I40E_QINT_TQCTL(qp), val);
3137 qp++;
3138 }
3139 }
3140
3141 i40e_flush(hw);
3142}
3143
3144/**
3145 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3146 * @hw: ptr to the hardware info
3147 **/
ab437b5a 3148static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3149{
ab437b5a 3150 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3151 u32 val;
3152
3153 /* clear things first */
3154 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3155 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3156
3157 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3158 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3159 I40E_PFINT_ICR0_ENA_GRST_MASK |
3160 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3161 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3162 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3163 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3164 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3165
0d8e1439
ASJ		 3166 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3167 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3168
ab437b5a
JK		 3169 if (pf->flags & I40E_FLAG_PTP)
3170 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3171
41c445ff
JB		 3172 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3173
3174 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3175 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3176 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3177
3178 /* OTHER_ITR_IDX = 0 */
3179 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3180}
3181
3182/**
3183 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3184 * @vsi: the VSI being configured
3185 **/
3186static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3187{
493fb300 3188 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3189 struct i40e_pf *pf = vsi->back;
3190 struct i40e_hw *hw = &pf->hw;
3191 u32 val;
3192
3193 /* set the ITR configuration */
ee2319cf 3194 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3195 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3196 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3197 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3198 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3199 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3200 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3201
ab437b5a 3202 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3203
3204 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3205 wr32(hw, I40E_PFINT_LNKLST0, 0);
3206
f29eaa3d 3207 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3208 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3209 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3210 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3211
3212 wr32(hw, I40E_QINT_RQCTL(0), val);
3213
3214 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3215 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3216 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3217
3218 wr32(hw, I40E_QINT_TQCTL(0), val);
3219 i40e_flush(hw);
3220}
3221
2ef28cfb
MW		 3222/**
3223 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3224 * @pf: board private structure
3225 **/
3226void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3227{
3228 struct i40e_hw *hw = &pf->hw;
3229
3230 wr32(hw, I40E_PFINT_DYN_CTL0,
3231 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3232 i40e_flush(hw);
3233}
3234
41c445ff
JB		 3235/**
3236 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3237 * @pf: board private structure
3238 **/
116a57d4 3239void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3240{
3241 struct i40e_hw *hw = &pf->hw;
3242 u32 val;
3243
3244 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3245 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3246 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3247
3248 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3249 i40e_flush(hw);
3250}
3251
5c2cebda
CW		 3252/**
3253 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3254 * @vsi: pointer to a vsi
03147773 3255 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3256 **/
3257void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3258{
3259 struct i40e_pf *pf = vsi->back;
3260 struct i40e_hw *hw = &pf->hw;
3261 u32 val;
3262
3263 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3264 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3265 i40e_flush(hw);
3266}
3267
41c445ff
JB		 3268/**
3269 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3270 * @irq: interrupt number
3271 * @data: pointer to a q_vector
3272 **/
3273static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3274{
3275 struct i40e_q_vector *q_vector = data;
3276
cd0b6fa6 3277 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3278 return IRQ_HANDLED;
3279
5d3465a1 3280 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3281
3282 return IRQ_HANDLED;
3283}
3284
41c445ff
JB		 3285/**
3286 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3287 * @vsi: the VSI being configured
3288 * @basename: name for the vector
3289 *
3290 * Allocates MSI-X vectors and requests interrupts from the kernel.
3291 **/
3292static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3293{
3294 int q_vectors = vsi->num_q_vectors;
3295 struct i40e_pf *pf = vsi->back;
3296 int base = vsi->base_vector;
3297 int rx_int_idx = 0;
3298 int tx_int_idx = 0;
3299 int vector, err;
3300
3301 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3302 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3303
cd0b6fa6 3304 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3305 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3306 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3307 tx_int_idx++;
cd0b6fa6 3308 } else if (q_vector->rx.ring) {
41c445ff
JB		 3309 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3310 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3311 } else if (q_vector->tx.ring) {
41c445ff
JB		 3312 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3313 "%s-%s-%d", basename, "tx", tx_int_idx++);
3314 } else {
3315 /* skip this unused q_vector */
3316 continue;
3317 }
3318 err = request_irq(pf->msix_entries[base + vector].vector,
3319 vsi->irq_handler,
3320 0,
3321 q_vector->name,
3322 q_vector);
3323 if (err) {
3324 dev_info(&pf->pdev->dev,
fb43201f 3325 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3326 goto free_queue_irqs;
3327 }
3328 /* assign the mask for this irq */
3329 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3330 &q_vector->affinity_mask);
3331 }
3332
63741846 3333 vsi->irqs_ready = true;
41c445ff
JB		 3334 return 0;
3335
3336free_queue_irqs:
3337 while (vector) {
3338 vector--;
3339 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3340 NULL);
3341 free_irq(pf->msix_entries[base + vector].vector,
3342 &(vsi->q_vectors[vector]));
3343 }
3344 return err;
3345}
3346
3347/**
3348 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3349 * @vsi: the VSI being un-configured
3350 **/
3351static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3352{
3353 struct i40e_pf *pf = vsi->back;
3354 struct i40e_hw *hw = &pf->hw;
3355 int base = vsi->base_vector;
3356 int i;
3357
3358 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3359 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3360 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3361 }
3362
3363 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3364 for (i = vsi->base_vector;
3365 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3366 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3367
3368 i40e_flush(hw);
3369 for (i = 0; i < vsi->num_q_vectors; i++)
3370 synchronize_irq(pf->msix_entries[i + base].vector);
3371 } else {
3372 /* Legacy and MSI mode - this stops all interrupt handling */
3373 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3374 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3375 i40e_flush(hw);
3376 synchronize_irq(pf->pdev->irq);
3377 }
3378}
3379
3380/**
3381 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3382 * @vsi: the VSI being configured
3383 **/
3384static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3385{
3386 struct i40e_pf *pf = vsi->back;
3387 int i;
3388
3389 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3390 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3391 i40e_irq_dynamic_enable(vsi, i);
3392 } else {
3393 i40e_irq_dynamic_enable_icr0(pf);
3394 }
3395
1022cb6c 3396 i40e_flush(&pf->hw);
41c445ff
JB		 3397 return 0;
3398}
3399
3400/**
3401 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3402 * @pf: board private structure
3403 **/
3404static void i40e_stop_misc_vector(struct i40e_pf *pf)
3405{
3406 /* Disable ICR 0 */
3407 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3408 i40e_flush(&pf->hw);
3409}
3410
3411/**
3412 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3413 * @irq: interrupt number
3414 * @data: pointer to a q_vector
3415 *
3416 * This is the handler used for all MSI/Legacy interrupts, and deals
3417 * with both queue and non-queue interrupts. This is also used in
3418 * MSIX mode to handle the non-queue interrupts.
3419 **/
3420static irqreturn_t i40e_intr(int irq, void *data)
3421{
3422 struct i40e_pf *pf = (struct i40e_pf *)data;
3423 struct i40e_hw *hw = &pf->hw;
5e823066 3424 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3425 u32 icr0, icr0_remaining;
3426 u32 val, ena_mask;
3427
3428 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3429 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3430
116a57d4
SN		 3431 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3432 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3433 goto enable_intr;
41c445ff 3434
cd92e72f
SN		 3435 /* if interrupt but no bits showing, must be SWINT */
3436 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3437 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3438 pf->sw_int_count++;
3439
0d8e1439
ASJ		 3440 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3441 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3442 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3443 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3444 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3445 }
3446
41c445ff
JB		 3447 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3448 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3449 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3450 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3451
3452 /* temporarily disable queue cause for NAPI processing */
3453 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3454
41c445ff
JB		 3455 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3456 wr32(hw, I40E_QINT_RQCTL(0), qval);
3457
3458 qval = rd32(hw, I40E_QINT_TQCTL(0));
3459 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3460 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3461
3462 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3463 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3464 }
3465
3466 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3467 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3468 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3469 }
3470
3471 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3472 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3473 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3474 }
3475
3476 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3477 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3478 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3479 }
3480
3481 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3482 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3483 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3484 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3485 val = rd32(hw, I40E_GLGEN_RSTAT);
3486 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3487 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3488 if (val == I40E_RESET_CORER) {
41c445ff 3489 pf->corer_count++;
4eb3f768 3490 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3491 pf->globr_count++;
4eb3f768 3492 } else if (val == I40E_RESET_EMPR) {
41c445ff 3493 pf->empr_count++;
9df42d1a 3494 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3495 }
41c445ff
JB		 3496 }
3497
9c010ee0
ASJ		 3498 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3499 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3500 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3501 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3502 rd32(hw, I40E_PFHMC_ERRORINFO),
3503 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3504 }
3505
beb0dff1
JK		 3506 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3507 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3508
3509 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3510 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3511 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3512 }
beb0dff1
JK		 3513 }
3514
41c445ff
JB		 3515 /* If a critical error is pending we have no choice but to reset the
3516 * device.
3517 * Report and mask out any remaining unexpected interrupts.
3518 */
3519 icr0_remaining = icr0 & ena_mask;
3520 if (icr0_remaining) {
3521 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3522 icr0_remaining);
9c010ee0 3523 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3524 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3525 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3526 dev_info(&pf->pdev->dev, "device will be reset\n");
3527 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3528 i40e_service_event_schedule(pf);
41c445ff
JB		 3529 }
3530 ena_mask &= ~icr0_remaining;
3531 }
5e823066 3532 ret = IRQ_HANDLED;
41c445ff 3533
5e823066 3534enable_intr:
41c445ff
JB		 3535 /* re-enable interrupt causes */
3536 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3537 if (!test_bit(__I40E_DOWN, &pf->state)) {
3538 i40e_service_event_schedule(pf);
3539 i40e_irq_dynamic_enable_icr0(pf);
3540 }
3541
5e823066 3542 return ret;
41c445ff
JB		 3543}
3544
cbf61325
ASJ		 3545/**
3546 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3547 * @tx_ring: tx ring to clean
3548 * @budget: how many cleans we're allowed
3549 *
3550 * Returns true if there's any budget left (e.g. the clean is finished)
3551 **/
3552static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3553{
3554 struct i40e_vsi *vsi = tx_ring->vsi;
3555 u16 i = tx_ring->next_to_clean;
3556 struct i40e_tx_buffer *tx_buf;
3557 struct i40e_tx_desc *tx_desc;
3558
3559 tx_buf = &tx_ring->tx_bi[i];
3560 tx_desc = I40E_TX_DESC(tx_ring, i);
3561 i -= tx_ring->count;
3562
3563 do {
3564 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3565
3566 /* if next_to_watch is not set then there is no work pending */
3567 if (!eop_desc)
3568 break;
3569
3570 /* prevent any other reads prior to eop_desc */
3571 read_barrier_depends();
3572
3573 /* if the descriptor isn't done, no work yet to do */
3574 if (!(eop_desc->cmd_type_offset_bsz &
3575 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3576 break;
3577
3578 /* clear next_to_watch to prevent false hangs */
3579 tx_buf->next_to_watch = NULL;
3580
49d7d933
ASJ		 3581 tx_desc->buffer_addr = 0;
3582 tx_desc->cmd_type_offset_bsz = 0;
3583 /* move past filter desc */
3584 tx_buf++;
3585 tx_desc++;
3586 i++;
3587 if (unlikely(!i)) {
3588 i -= tx_ring->count;
3589 tx_buf = tx_ring->tx_bi;
3590 tx_desc = I40E_TX_DESC(tx_ring, 0);
3591 }
cbf61325
ASJ		 3592 /* unmap skb header data */
3593 dma_unmap_single(tx_ring->dev,
3594 dma_unmap_addr(tx_buf, dma),
3595 dma_unmap_len(tx_buf, len),
3596 DMA_TO_DEVICE);
49d7d933
ASJ		 3597 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3598 kfree(tx_buf->raw_buf);
cbf61325 3599
49d7d933
ASJ		 3600 tx_buf->raw_buf = NULL;
3601 tx_buf->tx_flags = 0;
3602 tx_buf->next_to_watch = NULL;
cbf61325 3603 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3604 tx_desc->buffer_addr = 0;
3605 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3606
49d7d933 3607 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3608 tx_buf++;
3609 tx_desc++;
3610 i++;
3611 if (unlikely(!i)) {
3612 i -= tx_ring->count;
3613 tx_buf = tx_ring->tx_bi;
3614 tx_desc = I40E_TX_DESC(tx_ring, 0);
3615 }
3616
3617 /* update budget accounting */
3618 budget--;
3619 } while (likely(budget));
3620
3621 i += tx_ring->count;
3622 tx_ring->next_to_clean = i;
3623
6995b36c 3624 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3625 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3626
cbf61325
ASJ		 3627 return budget > 0;
3628}
3629
3630/**
3631 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3632 * @irq: interrupt number
3633 * @data: pointer to a q_vector
3634 **/
3635static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3636{
3637 struct i40e_q_vector *q_vector = data;
3638 struct i40e_vsi *vsi;
3639
3640 if (!q_vector->tx.ring)
3641 return IRQ_HANDLED;
3642
3643 vsi = q_vector->tx.ring->vsi;
3644 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3645
3646 return IRQ_HANDLED;
3647}
3648
41c445ff 3649/**
cd0b6fa6 3650 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3651 * @vsi: the VSI being configured
3652 * @v_idx: vector index
cd0b6fa6 3653 * @qp_idx: queue pair index
41c445ff 3654 **/
26cdc443 3655static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3656{
493fb300 3657 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3658 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3659 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3660
3661 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3662 tx_ring->next = q_vector->tx.ring;
3663 q_vector->tx.ring = tx_ring;
41c445ff 3664 q_vector->tx.count++;
cd0b6fa6
AD		 3665
3666 rx_ring->q_vector = q_vector;
3667 rx_ring->next = q_vector->rx.ring;
3668 q_vector->rx.ring = rx_ring;
3669 q_vector->rx.count++;
41c445ff
JB		 3670}
3671
3672/**
3673 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3674 * @vsi: the VSI being configured
3675 *
3676 * This function maps descriptor rings to the queue-specific vectors
3677 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3678 * one vector per queue pair, but on a constrained vector budget, we
3679 * group the queue pairs as "efficiently" as possible.
3680 **/
3681static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3682{
3683 int qp_remaining = vsi->num_queue_pairs;
3684 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3685 int num_ringpairs;
41c445ff
JB		 3686 int v_start = 0;
3687 int qp_idx = 0;
3688
3689 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3690 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3691 * It is also important to go through all the vectors available to be
3692 * sure that if we don't use all the vectors, that the remaining vectors
3693 * are cleared. This is especially important when decreasing the
3694 * number of queues in use.
41c445ff 3695 */
70114ec4 3696 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3697 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3698
3699 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3700
3701 q_vector->num_ringpairs = num_ringpairs;
3702
3703 q_vector->rx.count = 0;
3704 q_vector->tx.count = 0;
3705 q_vector->rx.ring = NULL;
3706 q_vector->tx.ring = NULL;
3707
3708 while (num_ringpairs--) {
26cdc443 3709 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3710 qp_idx++;
3711 qp_remaining--;
41c445ff
JB		 3712 }
3713 }
3714}
3715
3716/**
3717 * i40e_vsi_request_irq - Request IRQ from the OS
3718 * @vsi: the VSI being configured
3719 * @basename: name for the vector
3720 **/
3721static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3722{
3723 struct i40e_pf *pf = vsi->back;
3724 int err;
3725
3726 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3727 err = i40e_vsi_request_irq_msix(vsi, basename);
3728 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3729 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3730 pf->int_name, pf);
41c445ff
JB		 3731 else
3732 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3733 pf->int_name, pf);
41c445ff
JB		 3734
3735 if (err)
3736 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3737
3738 return err;
3739}
3740
3741#ifdef CONFIG_NET_POLL_CONTROLLER
3742/**
3743 * i40e_netpoll - A Polling 'interrupt'handler
3744 * @netdev: network interface device structure
3745 *
3746 * This is used by netconsole to send skbs without having to re-enable
3747 * interrupts. It's not called while the normal interrupt routine is executing.
3748 **/
38e00438
VD		 3749#ifdef I40E_FCOE
3750void i40e_netpoll(struct net_device *netdev)
3751#else
41c445ff 3752static void i40e_netpoll(struct net_device *netdev)
38e00438 3753#endif
41c445ff
JB		 3754{
3755 struct i40e_netdev_priv *np = netdev_priv(netdev);
3756 struct i40e_vsi *vsi = np->vsi;
3757 struct i40e_pf *pf = vsi->back;
3758 int i;
3759
3760 /* if interface is down do nothing */
3761 if (test_bit(__I40E_DOWN, &vsi->state))
3762 return;
3763
41c445ff
JB		 3764 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3765 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3766 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3767 } else {
3768 i40e_intr(pf->pdev->irq, netdev);
3769 }
41c445ff
JB		 3770}
3771#endif
3772
23527308
NP		 3773/**
3774 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3775 * @pf: the PF being configured
3776 * @pf_q: the PF queue
3777 * @enable: enable or disable state of the queue
3778 *
3779 * This routine will wait for the given Tx queue of the PF to reach the
3780 * enabled or disabled state.
3781 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3782 * multiple retries; else will return 0 in case of success.
3783 **/
3784static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3785{
3786 int i;
3787 u32 tx_reg;
3788
3789 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3790 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3791 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3792 break;
3793
f98a2006 3794 usleep_range(10, 20);
23527308
NP		 3795 }
3796 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3797 return -ETIMEDOUT;
3798
3799 return 0;
3800}
3801
41c445ff
JB		 3802/**
3803 * i40e_vsi_control_tx - Start or stop a VSI's rings
3804 * @vsi: the VSI being configured
3805 * @enable: start or stop the rings
3806 **/
3807static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3808{
3809 struct i40e_pf *pf = vsi->back;
3810 struct i40e_hw *hw = &pf->hw;
23527308 3811 int i, j, pf_q, ret = 0;
41c445ff
JB		 3812 u32 tx_reg;
3813
3814 pf_q = vsi->base_queue;
3815 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3816
3817 /* warn the TX unit of coming changes */
3818 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3819 if (!enable)
f98a2006 3820 usleep_range(10, 20);
351499ab 3821
6c5ef620 3822 for (j = 0; j < 50; j++) {
41c445ff 3823 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3824 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3825 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3826 break;
3827 usleep_range(1000, 2000);
3828 }
fda972f6 3829 /* Skip if the queue is already in the requested state */
7c122007 3830 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3831 continue;
41c445ff
JB		 3832
3833 /* turn on/off the queue */
c5c9eb9e
SN		 3834 if (enable) {
3835 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3836 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3837 } else {
41c445ff 3838 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3839 }
41c445ff
JB		 3840
3841 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3842 /* No waiting for the Tx queue to disable */
3843 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3844 continue;
41c445ff
JB		 3845
3846 /* wait for the change to finish */
23527308
NP		 3847 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3848 if (ret) {
3849 dev_info(&pf->pdev->dev,
fb43201f
SN		 3850 "VSI seid %d Tx ring %d %sable timeout\n",
3851 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3852 break;
41c445ff
JB		 3853 }
3854 }
3855
7134f9ce
JB		 3856 if (hw->revision_id == 0)
3857 mdelay(50);
23527308
NP		 3858 return ret;
3859}
3860
3861/**
3862 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3863 * @pf: the PF being configured
3864 * @pf_q: the PF queue
3865 * @enable: enable or disable state of the queue
3866 *
3867 * This routine will wait for the given Rx queue of the PF to reach the
3868 * enabled or disabled state.
3869 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3870 * multiple retries; else will return 0 in case of success.
3871 **/
3872static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3873{
3874 int i;
3875 u32 rx_reg;
3876
3877 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3878 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3879 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3880 break;
3881
f98a2006 3882 usleep_range(10, 20);
23527308
NP		 3883 }
3884 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3885 return -ETIMEDOUT;
7134f9ce 3886
41c445ff
JB		 3887 return 0;
3888}
3889
3890/**
3891 * i40e_vsi_control_rx - Start or stop a VSI's rings
3892 * @vsi: the VSI being configured
3893 * @enable: start or stop the rings
3894 **/
3895static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3896{
3897 struct i40e_pf *pf = vsi->back;
3898 struct i40e_hw *hw = &pf->hw;
23527308 3899 int i, j, pf_q, ret = 0;
41c445ff
JB		 3900 u32 rx_reg;
3901
3902 pf_q = vsi->base_queue;
3903 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3904 for (j = 0; j < 50; j++) {
41c445ff 3905 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3906 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3907 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3908 break;
3909 usleep_range(1000, 2000);
3910 }
41c445ff 3911
7c122007
CS		 3912 /* Skip if the queue is already in the requested state */
3913 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3914 continue;
41c445ff
JB		 3915
3916 /* turn on/off the queue */
3917 if (enable)
6c5ef620 3918 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3919 else
6c5ef620 3920 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3921 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3922
3923 /* wait for the change to finish */
23527308
NP		 3924 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3925 if (ret) {
3926 dev_info(&pf->pdev->dev,
fb43201f
SN		 3927 "VSI seid %d Rx ring %d %sable timeout\n",
3928 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3929 break;
41c445ff
JB		 3930 }
3931 }
3932
23527308 3933 return ret;
41c445ff
JB		 3934}
3935
3936/**
3937 * i40e_vsi_control_rings - Start or stop a VSI's rings
3938 * @vsi: the VSI being configured
3939 * @enable: start or stop the rings
3940 **/
fc18eaa0 3941int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3942{
3b867b28 3943 int ret = 0;
41c445ff
JB		 3944
3945 /* do rx first for enable and last for disable */
3946 if (request) {
3947 ret = i40e_vsi_control_rx(vsi, request);
3948 if (ret)
3949 return ret;
3950 ret = i40e_vsi_control_tx(vsi, request);
3951 } else {
3b867b28
ASJ		 3952 /* Ignore return value, we need to shutdown whatever we can */
3953 i40e_vsi_control_tx(vsi, request);
3954 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3955 }
3956
3957 return ret;
3958}
3959
3960/**
3961 * i40e_vsi_free_irq - Free the irq association with the OS
3962 * @vsi: the VSI being configured
3963 **/
3964static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3965{
3966 struct i40e_pf *pf = vsi->back;
3967 struct i40e_hw *hw = &pf->hw;
3968 int base = vsi->base_vector;
3969 u32 val, qp;
3970 int i;
3971
3972 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3973 if (!vsi->q_vectors)
3974 return;
3975
63741846
SN		 3976 if (!vsi->irqs_ready)
3977 return;
3978
3979 vsi->irqs_ready = false;
41c445ff
JB		 3980 for (i = 0; i < vsi->num_q_vectors; i++) {
3981 u16 vector = i + base;
3982
3983 /* free only the irqs that were actually requested */
78681b1f
SN		 3984 if (!vsi->q_vectors[i] ||
3985 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3986 continue;
3987
3988 /* clear the affinity_mask in the IRQ descriptor */
3989 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3990 NULL);
3991 free_irq(pf->msix_entries[vector].vector,
493fb300 3992 vsi->q_vectors[i]);
41c445ff
JB		 3993
3994 /* Tear down the interrupt queue link list
3995 *
3996 * We know that they come in pairs and always
3997 * the Rx first, then the Tx. To clear the
3998 * link list, stick the EOL value into the
3999 * next_q field of the registers.
4000 */
4001 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4002 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4003 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4004 val |= I40E_QUEUE_END_OF_LIST
4005 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4006 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4007
4008 while (qp != I40E_QUEUE_END_OF_LIST) {
4009 u32 next;
4010
4011 val = rd32(hw, I40E_QINT_RQCTL(qp));
4012
4013 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4014 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4015 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4016 I40E_QINT_RQCTL_INTEVENT_MASK);
4017
4018 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4019 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4020
4021 wr32(hw, I40E_QINT_RQCTL(qp), val);
4022
4023 val = rd32(hw, I40E_QINT_TQCTL(qp));
4024
4025 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4026 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4027
4028 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4029 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4030 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4031 I40E_QINT_TQCTL_INTEVENT_MASK);
4032
4033 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4034 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4035
4036 wr32(hw, I40E_QINT_TQCTL(qp), val);
4037 qp = next;
4038 }
4039 }
4040 } else {
4041 free_irq(pf->pdev->irq, pf);
4042
4043 val = rd32(hw, I40E_PFINT_LNKLST0);
4044 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4045 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4046 val |= I40E_QUEUE_END_OF_LIST
4047 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4048 wr32(hw, I40E_PFINT_LNKLST0, val);
4049
4050 val = rd32(hw, I40E_QINT_RQCTL(qp));
4051 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4052 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4053 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4054 I40E_QINT_RQCTL_INTEVENT_MASK);
4055
4056 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4057 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4058
4059 wr32(hw, I40E_QINT_RQCTL(qp), val);
4060
4061 val = rd32(hw, I40E_QINT_TQCTL(qp));
4062
4063 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4064 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4065 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4066 I40E_QINT_TQCTL_INTEVENT_MASK);
4067
4068 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4069 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4070
4071 wr32(hw, I40E_QINT_TQCTL(qp), val);
4072 }
4073}
4074
493fb300
AD		 4075/**
4076 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4077 * @vsi: the VSI being configured
4078 * @v_idx: Index of vector to be freed
4079 *
4080 * This function frees the memory allocated to the q_vector. In addition if
4081 * NAPI is enabled it will delete any references to the NAPI struct prior
4082 * to freeing the q_vector.
4083 **/
4084static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4085{
4086 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4087 struct i40e_ring *ring;
493fb300
AD		 4088
4089 if (!q_vector)
4090 return;
4091
4092 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4093 i40e_for_each_ring(ring, q_vector->tx)
4094 ring->q_vector = NULL;
4095
4096 i40e_for_each_ring(ring, q_vector->rx)
4097 ring->q_vector = NULL;
493fb300
AD		 4098
4099 /* only VSI w/ an associated netdev is set up w/ NAPI */
4100 if (vsi->netdev)
4101 netif_napi_del(&q_vector->napi);
4102
4103 vsi->q_vectors[v_idx] = NULL;
4104
4105 kfree_rcu(q_vector, rcu);
4106}
4107
41c445ff
JB		 4108/**
4109 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4110 * @vsi: the VSI being un-configured
4111 *
4112 * This frees the memory allocated to the q_vectors and
4113 * deletes references to the NAPI struct.
4114 **/
4115static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4116{
4117 int v_idx;
4118
493fb300
AD		 4119 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4120 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4121}
4122
4123/**
4124 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4125 * @pf: board private structure
4126 **/
4127static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4128{
4129 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4130 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4131 pci_disable_msix(pf->pdev);
4132 kfree(pf->msix_entries);
4133 pf->msix_entries = NULL;
3b444399
SN		 4134 kfree(pf->irq_pile);
4135 pf->irq_pile = NULL;
41c445ff
JB		 4136 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4137 pci_disable_msi(pf->pdev);
4138 }
4139 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4140}
4141
4142/**
4143 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4144 * @pf: board private structure
4145 *
4146 * We go through and clear interrupt specific resources and reset the structure
4147 * to pre-load conditions
4148 **/
4149static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4150{
4151 int i;
4152
e147758d
SN		 4153 i40e_stop_misc_vector(pf);
4154 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4155 synchronize_irq(pf->msix_entries[0].vector);
4156 free_irq(pf->msix_entries[0].vector, pf);
4157 }
4158
41c445ff 4159 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4160 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4161 if (pf->vsi[i])
4162 i40e_vsi_free_q_vectors(pf->vsi[i]);
4163 i40e_reset_interrupt_capability(pf);
4164}
4165
4166/**
4167 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4168 * @vsi: the VSI being configured
4169 **/
4170static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4171{
4172 int q_idx;
4173
4174 if (!vsi->netdev)
4175 return;
4176
4177 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4178 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4179}
4180
4181/**
4182 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4183 * @vsi: the VSI being configured
4184 **/
4185static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4186{
4187 int q_idx;
4188
4189 if (!vsi->netdev)
4190 return;
4191
4192 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4193 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4194}
4195
90ef8d47
SN		 4196/**
4197 * i40e_vsi_close - Shut down a VSI
4198 * @vsi: the vsi to be quelled
4199 **/
4200static void i40e_vsi_close(struct i40e_vsi *vsi)
4201{
4202 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4203 i40e_down(vsi);
4204 i40e_vsi_free_irq(vsi);
4205 i40e_vsi_free_tx_resources(vsi);
4206 i40e_vsi_free_rx_resources(vsi);
92faef85 4207 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4208}
4209
41c445ff
JB		 4210/**
4211 * i40e_quiesce_vsi - Pause a given VSI
4212 * @vsi: the VSI being paused
4213 **/
4214static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4215{
4216 if (test_bit(__I40E_DOWN, &vsi->state))
4217 return;
4218
d341b7a5
NP		 4219 /* No need to disable FCoE VSI when Tx suspended */
4220 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4221 vsi->type == I40E_VSI_FCOE) {
4222 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4223 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4224 return;
4225 }
4226
41c445ff 4227 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4228 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4229 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4230 else
90ef8d47 4231 i40e_vsi_close(vsi);
41c445ff
JB		 4232}
4233
4234/**
4235 * i40e_unquiesce_vsi - Resume a given VSI
4236 * @vsi: the VSI being resumed
4237 **/
4238static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4239{
4240 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4241 return;
4242
4243 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4244 if (vsi->netdev && netif_running(vsi->netdev))
4245 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4246 else
8276f757 4247 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4248}
4249
4250/**
4251 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4252 * @pf: the PF
4253 **/
4254static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4255{
4256 int v;
4257
505682cd 4258 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4259 if (pf->vsi[v])
4260 i40e_quiesce_vsi(pf->vsi[v]);
4261 }
4262}
4263
4264/**
4265 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4266 * @pf: the PF
4267 **/
4268static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4269{
4270 int v;
4271
505682cd 4272 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4273 if (pf->vsi[v])
4274 i40e_unquiesce_vsi(pf->vsi[v]);
4275 }
4276}
4277
69129dc3
NP		 4278#ifdef CONFIG_I40E_DCB
4279/**
4280 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4281 * @vsi: the VSI being configured
4282 *
4283 * This function waits for the given VSI's Tx queues to be disabled.
4284 **/
4285static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4286{
4287 struct i40e_pf *pf = vsi->back;
4288 int i, pf_q, ret;
4289
4290 pf_q = vsi->base_queue;
4291 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4292 /* Check and wait for the disable status of the queue */
4293 ret = i40e_pf_txq_wait(pf, pf_q, false);
4294 if (ret) {
4295 dev_info(&pf->pdev->dev,
fb43201f
SN		 4296 "VSI seid %d Tx ring %d disable timeout\n",
4297 vsi->seid, pf_q);
69129dc3
NP		 4298 return ret;
4299 }
4300 }
4301
4302 return 0;
4303}
4304
4305/**
4306 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4307 * @pf: the PF
4308 *
4309 * This function waits for the Tx queues to be in disabled state for all the
4310 * VSIs that are managed by this PF.
4311 **/
4312static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4313{
4314 int v, ret = 0;
4315
4316 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4317 /* No need to wait for FCoE VSI queues */
4318 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4319 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4320 if (ret)
4321 break;
4322 }
4323 }
4324
4325 return ret;
4326}
4327
4328#endif
b03a8c1f
KP		 4329
4330/**
4331 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4332 * @q_idx: TX queue number
4333 * @vsi: Pointer to VSI struct
4334 *
4335 * This function checks specified queue for given VSI. Detects hung condition.
4336 * Sets hung bit since it is two step process. Before next run of service task
4337 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4338 * hung condition remain unchanged and during subsequent run, this function
4339 * issues SW interrupt to recover from hung condition.
4340 **/
4341static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4342{
4343 struct i40e_ring *tx_ring = NULL;
4344 struct i40e_pf *pf;
4345 u32 head, val, tx_pending;
4346 int i;
4347
4348 pf = vsi->back;
4349
4350 /* now that we have an index, find the tx_ring struct */
4351 for (i = 0; i < vsi->num_queue_pairs; i++) {
4352 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4353 if (q_idx == vsi->tx_rings[i]->queue_index) {
4354 tx_ring = vsi->tx_rings[i];
4355 break;
4356 }
4357 }
4358 }
4359
4360 if (!tx_ring)
4361 return;
4362
4363 /* Read interrupt register */
4364 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4365 val = rd32(&pf->hw,
4366 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4367 tx_ring->vsi->base_vector - 1));
4368 else
4369 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4370
4371 head = i40e_get_head(tx_ring);
4372
4373 tx_pending = i40e_get_tx_pending(tx_ring);
4374
4375 /* Interrupts are disabled and TX pending is non-zero,
4376 * trigger the SW interrupt (don't wait). Worst case
4377 * there will be one extra interrupt which may result
4378 * into not cleaning any queues because queues are cleaned.
4379 */
4380 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4381 i40e_force_wb(vsi, tx_ring->q_vector);
4382}
4383
4384/**
4385 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4386 * @pf: pointer to PF struct
4387 *
4388 * LAN VSI has netdev and netdev has TX queues. This function is to check
4389 * each of those TX queues if they are hung, trigger recovery by issuing
4390 * SW interrupt.
4391 **/
4392static void i40e_detect_recover_hung(struct i40e_pf *pf)
4393{
4394 struct net_device *netdev;
4395 struct i40e_vsi *vsi;
4396 int i;
4397
4398 /* Only for LAN VSI */
4399 vsi = pf->vsi[pf->lan_vsi];
4400
4401 if (!vsi)
4402 return;
4403
4404 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4405 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4406 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4407 return;
4408
4409 /* Make sure type is MAIN VSI */
4410 if (vsi->type != I40E_VSI_MAIN)
4411 return;
4412
4413 netdev = vsi->netdev;
4414 if (!netdev)
4415 return;
4416
4417 /* Bail out if netif_carrier is not OK */
4418 if (!netif_carrier_ok(netdev))
4419 return;
4420
4421 /* Go thru' TX queues for netdev */
4422 for (i = 0; i < netdev->num_tx_queues; i++) {
4423 struct netdev_queue *q;
4424
4425 q = netdev_get_tx_queue(netdev, i);
4426 if (q)
4427 i40e_detect_recover_hung_queue(i, vsi);
4428 }
4429}
4430
63d7e5a4
NP		 4431/**
4432 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4433 * @pf: pointer to PF
63d7e5a4
NP		 4434 *
4435 * Get TC map for ISCSI PF type that will include iSCSI TC
4436 * and LAN TC.
4437 **/
4438static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4439{
4440 struct i40e_dcb_app_priority_table app;
4441 struct i40e_hw *hw = &pf->hw;
4442 u8 enabled_tc = 1; /* TC0 is always enabled */
4443 u8 tc, i;
4444 /* Get the iSCSI APP TLV */
4445 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4446
4447 for (i = 0; i < dcbcfg->numapps; i++) {
4448 app = dcbcfg->app[i];
4449 if (app.selector == I40E_APP_SEL_TCPIP &&
4450 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4451 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4452 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4453 break;
4454 }
4455 }
4456
4457 return enabled_tc;
4458}
4459
41c445ff
JB		 4460/**
4461 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4462 * @dcbcfg: the corresponding DCBx configuration structure
4463 *
4464 * Return the number of TCs from given DCBx configuration
4465 **/
4466static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4467{
078b5876
JB		 4468 u8 num_tc = 0;
4469 int i;
41c445ff
JB		 4470
4471 /* Scan the ETS Config Priority Table to find
4472 * traffic class enabled for a given priority
4473 * and use the traffic class index to get the
4474 * number of traffic classes enabled
4475 */
4476 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4477 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4478 num_tc = dcbcfg->etscfg.prioritytable[i];
4479 }
4480
4481 /* Traffic class index starts from zero so
4482 * increment to return the actual count
4483 */
078b5876 4484 return num_tc + 1;
41c445ff
JB		 4485}
4486
4487/**
4488 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4489 * @dcbcfg: the corresponding DCBx configuration structure
4490 *
4491 * Query the current DCB configuration and return the number of
4492 * traffic classes enabled from the given DCBX config
4493 **/
4494static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4495{
4496 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4497 u8 enabled_tc = 1;
4498 u8 i;
4499
4500 for (i = 0; i < num_tc; i++)
41a1d04b 4501 enabled_tc |= BIT(i);
41c445ff
JB		 4502
4503 return enabled_tc;
4504}
4505
4506/**
4507 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4508 * @pf: PF being queried
4509 *
4510 * Return number of traffic classes enabled for the given PF
4511 **/
4512static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4513{
4514 struct i40e_hw *hw = &pf->hw;
4515 u8 i, enabled_tc;
4516 u8 num_tc = 0;
4517 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4518
4519 /* If DCB is not enabled then always in single TC */
4520 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4521 return 1;
4522
63d7e5a4
NP		 4523 /* SFP mode will be enabled for all TCs on port */
4524 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4525 return i40e_dcb_get_num_tc(dcbcfg);
4526
41c445ff 4527 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4528 if (pf->hw.func_caps.iscsi)
4529 enabled_tc = i40e_get_iscsi_tc_map(pf);
4530 else
fc51de96 4531 return 1; /* Only TC0 */
41c445ff 4532
63d7e5a4
NP		 4533 /* At least have TC0 */
4534 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4535 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4536 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4537 num_tc++;
4538 }
4539 return num_tc;
41c445ff
JB		 4540}
4541
4542/**
4543 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4544 * @pf: PF being queried
4545 *
4546 * Return a bitmap for first enabled traffic class for this PF.
4547 **/
4548static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4549{
4550 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4551 u8 i = 0;
4552
4553 if (!enabled_tc)
4554 return 0x1; /* TC0 */
4555
4556 /* Find the first enabled TC */
4557 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4558 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4559 break;
4560 }
4561
41a1d04b 4562 return BIT(i);
41c445ff
JB		 4563}
4564
4565/**
4566 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4567 * @pf: PF being queried
4568 *
4569 * Return a bitmap for enabled traffic classes for this PF.
4570 **/
4571static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4572{
4573 /* If DCB is not enabled for this PF then just return default TC */
4574 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4575 return i40e_pf_get_default_tc(pf);
4576
41c445ff 4577 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4578 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4579 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4580
fc51de96 4581 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4582 if (pf->hw.func_caps.iscsi)
4583 return i40e_get_iscsi_tc_map(pf);
4584 else
fc51de96 4585 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4586}
4587
4588/**
4589 * i40e_vsi_get_bw_info - Query VSI BW Information
4590 * @vsi: the VSI being queried
4591 *
4592 * Returns 0 on success, negative value on failure
4593 **/
4594static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4595{
4596 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4597 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4598 struct i40e_pf *pf = vsi->back;
4599 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4600 i40e_status ret;
41c445ff 4601 u32 tc_bw_max;
41c445ff
JB		 4602 int i;
4603
4604 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4605 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4606 if (ret) {
41c445ff 4607 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4608 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4609 i40e_stat_str(&pf->hw, ret),
4610 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4611 return -EINVAL;
41c445ff
JB		 4612 }
4613
4614 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4615 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4616 NULL);
4617 if (ret) {
41c445ff 4618 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4619 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4620 i40e_stat_str(&pf->hw, ret),
4621 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4622 return -EINVAL;
41c445ff
JB		 4623 }
4624
4625 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4626 dev_info(&pf->pdev->dev,
4627 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4628 bw_config.tc_valid_bits,
4629 bw_ets_config.tc_valid_bits);
4630 /* Still continuing */
4631 }
4632
4633 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4634 vsi->bw_max_quanta = bw_config.max_bw;
4635 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4636 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4637 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4638 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4639 vsi->bw_ets_limit_credits[i] =
4640 le16_to_cpu(bw_ets_config.credits[i]);
4641 /* 3 bits out of 4 for each TC */
4642 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4643 }
078b5876 4644
dcae29be 4645 return 0;
41c445ff
JB		 4646}
4647
4648/**
4649 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4650 * @vsi: the VSI being configured
4651 * @enabled_tc: TC bitmap
4652 * @bw_credits: BW shared credits per TC
4653 *
4654 * Returns 0 on success, negative value on failure
4655 **/
dcae29be 4656static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4657 u8 *bw_share)
4658{
4659 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4660 i40e_status ret;
dcae29be 4661 int i;
41c445ff
JB		 4662
4663 bw_data.tc_valid_bits = enabled_tc;
4664 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4665 bw_data.tc_bw_credits[i] = bw_share[i];
4666
f1c7e72e
SN		 4667 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4668 NULL);
4669 if (ret) {
41c445ff 4670 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4671 "AQ command Config VSI BW allocation per TC failed = %d\n",
4672 vsi->back->hw.aq.asq_last_status);
dcae29be 4673 return -EINVAL;
41c445ff
JB		 4674 }
4675
4676 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4677 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4678
dcae29be 4679 return 0;
41c445ff
JB		 4680}
4681
4682/**
4683 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4684 * @vsi: the VSI being configured
4685 * @enabled_tc: TC map to be enabled
4686 *
4687 **/
4688static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4689{
4690 struct net_device *netdev = vsi->netdev;
4691 struct i40e_pf *pf = vsi->back;
4692 struct i40e_hw *hw = &pf->hw;
4693 u8 netdev_tc = 0;
4694 int i;
4695 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4696
4697 if (!netdev)
4698 return;
4699
4700 if (!enabled_tc) {
4701 netdev_reset_tc(netdev);
4702 return;
4703 }
4704
4705 /* Set up actual enabled TCs on the VSI */
4706 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4707 return;
4708
4709 /* set per TC queues for the VSI */
4710 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4711 /* Only set TC queues for enabled tcs
4712 *
4713 * e.g. For a VSI that has TC0 and TC3 enabled the
4714 * enabled_tc bitmap would be 0x00001001; the driver
4715 * will set the numtc for netdev as 2 that will be
4716 * referenced by the netdev layer as TC 0 and 1.
4717 */
41a1d04b 4718 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4719 netdev_set_tc_queue(netdev,
4720 vsi->tc_config.tc_info[i].netdev_tc,
4721 vsi->tc_config.tc_info[i].qcount,
4722 vsi->tc_config.tc_info[i].qoffset);
4723 }
4724
4725 /* Assign UP2TC map for the VSI */
4726 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4727 /* Get the actual TC# for the UP */
4728 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4729 /* Get the mapped netdev TC# for the UP */
4730 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4731 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4732 }
4733}
4734
4735/**
4736 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4737 * @vsi: the VSI being configured
4738 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4739 **/
4740static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4741 struct i40e_vsi_context *ctxt)
4742{
4743 /* copy just the sections touched not the entire info
4744 * since not all sections are valid as returned by
4745 * update vsi params
4746 */
4747 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4748 memcpy(&vsi->info.queue_mapping,
4749 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4750 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4751 sizeof(vsi->info.tc_mapping));
4752}
4753
4754/**
4755 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4756 * @vsi: VSI to be configured
4757 * @enabled_tc: TC bitmap
4758 *
4759 * This configures a particular VSI for TCs that are mapped to the
4760 * given TC bitmap. It uses default bandwidth share for TCs across
4761 * VSIs to configure TC for a particular VSI.
4762 *
4763 * NOTE:
4764 * It is expected that the VSI queues have been quisced before calling
4765 * this function.
4766 **/
4767static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4768{
4769 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4770 struct i40e_vsi_context ctxt;
4771 int ret = 0;
4772 int i;
4773
4774 /* Check if enabled_tc is same as existing or new TCs */
4775 if (vsi->tc_config.enabled_tc == enabled_tc)
4776 return ret;
4777
4778 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4779 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4780 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4781 bw_share[i] = 1;
4782 }
4783
4784 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4785 if (ret) {
4786 dev_info(&vsi->back->pdev->dev,
4787 "Failed configuring TC map %d for VSI %d\n",
4788 enabled_tc, vsi->seid);
4789 goto out;
4790 }
4791
4792 /* Update Queue Pairs Mapping for currently enabled UPs */
4793 ctxt.seid = vsi->seid;
4794 ctxt.pf_num = vsi->back->hw.pf_id;
4795 ctxt.vf_num = 0;
4796 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4797 ctxt.info = vsi->info;
41c445ff
JB		 4798 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4799
4800 /* Update the VSI after updating the VSI queue-mapping information */
4801 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4802 if (ret) {
4803 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4804 "Update vsi tc config failed, err %s aq_err %s\n",
4805 i40e_stat_str(&vsi->back->hw, ret),
4806 i40e_aq_str(&vsi->back->hw,
4807 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4808 goto out;
4809 }
4810 /* update the local VSI info with updated queue map */
4811 i40e_vsi_update_queue_map(vsi, &ctxt);
4812 vsi->info.valid_sections = 0;
4813
4814 /* Update current VSI BW information */
4815 ret = i40e_vsi_get_bw_info(vsi);
4816 if (ret) {
4817 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4818 "Failed updating vsi bw info, err %s aq_err %s\n",
4819 i40e_stat_str(&vsi->back->hw, ret),
4820 i40e_aq_str(&vsi->back->hw,
4821 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4822 goto out;
4823 }
4824
4825 /* Update the netdev TC setup */
4826 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4827out:
4828 return ret;
4829}
4830
4e3b35b0
NP		 4831/**
4832 * i40e_veb_config_tc - Configure TCs for given VEB
4833 * @veb: given VEB
4834 * @enabled_tc: TC bitmap
4835 *
4836 * Configures given TC bitmap for VEB (switching) element
4837 **/
4838int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4839{
4840 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4841 struct i40e_pf *pf = veb->pf;
4842 int ret = 0;
4843 int i;
4844
4845 /* No TCs or already enabled TCs just return */
4846 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4847 return ret;
4848
4849 bw_data.tc_valid_bits = enabled_tc;
4850 /* bw_data.absolute_credits is not set (relative) */
4851
4852 /* Enable ETS TCs with equal BW Share for now */
4853 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4854 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4855 bw_data.tc_bw_share_credits[i] = 1;
4856 }
4857
4858 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4859 &bw_data, NULL);
4860 if (ret) {
4861 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4862 "VEB bw config failed, err %s aq_err %s\n",
4863 i40e_stat_str(&pf->hw, ret),
4864 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4865 goto out;
4866 }
4867
4868 /* Update the BW information */
4869 ret = i40e_veb_get_bw_info(veb);
4870 if (ret) {
4871 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4872 "Failed getting veb bw config, err %s aq_err %s\n",
4873 i40e_stat_str(&pf->hw, ret),
4874 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4875 }
4876
4877out:
4878 return ret;
4879}
4880
4881#ifdef CONFIG_I40E_DCB
4882/**
4883 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4884 * @pf: PF struct
4885 *
4886 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4887 * the caller would've quiesce all the VSIs before calling
4888 * this function
4889 **/
4890static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4891{
4892 u8 tc_map = 0;
4893 int ret;
4894 u8 v;
4895
4896 /* Enable the TCs available on PF to all VEBs */
4897 tc_map = i40e_pf_get_tc_map(pf);
4898 for (v = 0; v < I40E_MAX_VEB; v++) {
4899 if (!pf->veb[v])
4900 continue;
4901 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4902 if (ret) {
4903 dev_info(&pf->pdev->dev,
4904 "Failed configuring TC for VEB seid=%d\n",
4905 pf->veb[v]->seid);
4906 /* Will try to configure as many components */
4907 }
4908 }
4909
4910 /* Update each VSI */
505682cd 4911 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4912 if (!pf->vsi[v])
4913 continue;
4914
4915 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4916#ifdef I40E_FCOE
4917 * - For FCoE VSI only enable the TC configured
4918 * as per the APP TLV
4919#endif
4e3b35b0
NP		 4920 * - For all others keep them at TC0 for now
4921 */
4922 if (v == pf->lan_vsi)
4923 tc_map = i40e_pf_get_tc_map(pf);
4924 else
4925 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4926#ifdef I40E_FCOE
4927 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4928 tc_map = i40e_get_fcoe_tc_map(pf);
4929#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4930
4931 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4932 if (ret) {
4933 dev_info(&pf->pdev->dev,
4934 "Failed configuring TC for VSI seid=%d\n",
4935 pf->vsi[v]->seid);
4936 /* Will try to configure as many components */
4937 } else {
0672a091
NP		 4938 /* Re-configure VSI vectors based on updated TC map */
4939 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4940 if (pf->vsi[v]->netdev)
4941 i40e_dcbnl_set_all(pf->vsi[v]);
4942 }
4943 }
4944}
4945
2fd75f31
NP		 4946/**
4947 * i40e_resume_port_tx - Resume port Tx
4948 * @pf: PF struct
4949 *
4950 * Resume a port's Tx and issue a PF reset in case of failure to
4951 * resume.
4952 **/
4953static int i40e_resume_port_tx(struct i40e_pf *pf)
4954{
4955 struct i40e_hw *hw = &pf->hw;
4956 int ret;
4957
4958 ret = i40e_aq_resume_port_tx(hw, NULL);
4959 if (ret) {
4960 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4961 "Resume Port Tx failed, err %s aq_err %s\n",
4962 i40e_stat_str(&pf->hw, ret),
4963 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4964 /* Schedule PF reset to recover */
4965 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4966 i40e_service_event_schedule(pf);
4967 }
4968
4969 return ret;
4970}
4971
4e3b35b0
NP		 4972/**
4973 * i40e_init_pf_dcb - Initialize DCB configuration
4974 * @pf: PF being configured
4975 *
4976 * Query the current DCB configuration and cache it
4977 * in the hardware structure
4978 **/
4979static int i40e_init_pf_dcb(struct i40e_pf *pf)
4980{
4981 struct i40e_hw *hw = &pf->hw;
4982 int err = 0;
4983
025b4a54
ASJ		 4984 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4985 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4986 (pf->hw.aq.fw_maj_ver < 4))
4987 goto out;
4988
4e3b35b0
NP		 4989 /* Get the initial DCB configuration */
4990 err = i40e_init_dcb(hw);
4991 if (!err) {
4992 /* Device/Function is not DCBX capable */
4993 if ((!hw->func_caps.dcb) ||
4994 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4995 dev_info(&pf->pdev->dev,
4996 "DCBX offload is not supported or is disabled for this PF.\n");
4997
4998 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4999 goto out;
5000
5001 } else {
5002 /* When status is not DISABLED then DCBX in FW */
5003 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5004 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5005
5006 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5007 /* Enable DCB tagging only when more than one TC */
5008 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5009 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5010 dev_dbg(&pf->pdev->dev,
5011 "DCBX offload is supported for this PF.\n");
4e3b35b0 5012 }
014269ff 5013 } else {
aebfc816 5014 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5015 "Query for DCB configuration failed, err %s aq_err %s\n",
5016 i40e_stat_str(&pf->hw, err),
5017 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5018 }
5019
5020out:
5021 return err;
5022}
5023#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5024#define SPEED_SIZE 14
5025#define FC_SIZE 8
5026/**
5027 * i40e_print_link_message - print link up or down
5028 * @vsi: the VSI for which link needs a message
5029 */
c156f856 5030void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5031{
a9165490
SN		 5032 char *speed = "Unknown";
5033 char *fc = "Unknown";
cf05ed08 5034
c156f856
MJ		 5035 if (vsi->current_isup == isup)
5036 return;
5037 vsi->current_isup = isup;
cf05ed08
JB		 5038 if (!isup) {
5039 netdev_info(vsi->netdev, "NIC Link is Down\n");
5040 return;
5041 }
5042
148c2d80
GR		 5043 /* Warn user if link speed on NPAR enabled partition is not at
5044 * least 10GB
5045 */
5046 if (vsi->back->hw.func_caps.npar_enable &&
5047 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5048 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5049 netdev_warn(vsi->netdev,
5050 "The partition detected link speed that is less than 10Gbps\n");
5051
cf05ed08
JB		 5052 switch (vsi->back->hw.phy.link_info.link_speed) {
5053 case I40E_LINK_SPEED_40GB:
a9165490 5054 speed = "40 G";
cf05ed08 5055 break;
ae24b409 5056 case I40E_LINK_SPEED_20GB:
a9165490 5057 speed = "20 G";
ae24b409 5058 break;
cf05ed08 5059 case I40E_LINK_SPEED_10GB:
a9165490 5060 speed = "10 G";
cf05ed08
JB		 5061 break;
5062 case I40E_LINK_SPEED_1GB:
a9165490 5063 speed = "1000 M";
cf05ed08 5064 break;
5960d33f 5065 case I40E_LINK_SPEED_100MB:
a9165490 5066 speed = "100 M";
5960d33f 5067 break;
cf05ed08
JB		 5068 default:
5069 break;
5070 }
5071
5072 switch (vsi->back->hw.fc.current_mode) {
5073 case I40E_FC_FULL:
a9165490 5074 fc = "RX/TX";
cf05ed08
JB		 5075 break;
5076 case I40E_FC_TX_PAUSE:
a9165490 5077 fc = "TX";
cf05ed08
JB		 5078 break;
5079 case I40E_FC_RX_PAUSE:
a9165490 5080 fc = "RX";
cf05ed08
JB		 5081 break;
5082 default:
a9165490 5083 fc = "None";
cf05ed08
JB		 5084 break;
5085 }
5086
a9165490 5087 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5088 speed, fc);
5089}
4e3b35b0 5090
41c445ff
JB		 5091/**
5092 * i40e_up_complete - Finish the last steps of bringing up a connection
5093 * @vsi: the VSI being configured
5094 **/
5095static int i40e_up_complete(struct i40e_vsi *vsi)
5096{
5097 struct i40e_pf *pf = vsi->back;
5098 int err;
5099
5100 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5101 i40e_vsi_configure_msix(vsi);
5102 else
5103 i40e_configure_msi_and_legacy(vsi);
5104
5105 /* start rings */
5106 err = i40e_vsi_control_rings(vsi, true);
5107 if (err)
5108 return err;
5109
5110 clear_bit(__I40E_DOWN, &vsi->state);
5111 i40e_napi_enable_all(vsi);
5112 i40e_vsi_enable_irq(vsi);
5113
5114 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5115 (vsi->netdev)) {
cf05ed08 5116 i40e_print_link_message(vsi, true);
41c445ff
JB		 5117 netif_tx_start_all_queues(vsi->netdev);
5118 netif_carrier_on(vsi->netdev);
6d779b41 5119 } else if (vsi->netdev) {
cf05ed08 5120 i40e_print_link_message(vsi, false);
7b592f61
CW		 5121 /* need to check for qualified module here*/
5122 if ((pf->hw.phy.link_info.link_info &
5123 I40E_AQ_MEDIA_AVAILABLE) &&
5124 (!(pf->hw.phy.link_info.an_info &
5125 I40E_AQ_QUALIFIED_MODULE)))
5126 netdev_err(vsi->netdev,
5127 "the driver failed to link because an unqualified module was detected.");
41c445ff 5128 }
ca64fa4e
ASJ		 5129
5130 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5131 if (vsi->type == I40E_VSI_FDIR) {
5132 /* reset fd counters */
5133 pf->fd_add_err = pf->fd_atr_cnt = 0;
5134 if (pf->fd_tcp_rule > 0) {
5135 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5136 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5137 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5138 pf->fd_tcp_rule = 0;
5139 }
ca64fa4e 5140 i40e_fdir_filter_restore(vsi);
1e1be8f6 5141 }
41c445ff
JB		 5142 i40e_service_event_schedule(pf);
5143
5144 return 0;
5145}
5146
5147/**
5148 * i40e_vsi_reinit_locked - Reset the VSI
5149 * @vsi: the VSI being configured
5150 *
5151 * Rebuild the ring structs after some configuration
5152 * has changed, e.g. MTU size.
5153 **/
5154static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5155{
5156 struct i40e_pf *pf = vsi->back;
5157
5158 WARN_ON(in_interrupt());
5159 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5160 usleep_range(1000, 2000);
5161 i40e_down(vsi);
5162
5163 /* Give a VF some time to respond to the reset. The
5164 * two second wait is based upon the watchdog cycle in
5165 * the VF driver.
5166 */
5167 if (vsi->type == I40E_VSI_SRIOV)
5168 msleep(2000);
5169 i40e_up(vsi);
5170 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5171}
5172
5173/**
5174 * i40e_up - Bring the connection back up after being down
5175 * @vsi: the VSI being configured
5176 **/
5177int i40e_up(struct i40e_vsi *vsi)
5178{
5179 int err;
5180
5181 err = i40e_vsi_configure(vsi);
5182 if (!err)
5183 err = i40e_up_complete(vsi);
5184
5185 return err;
5186}
5187
5188/**
5189 * i40e_down - Shutdown the connection processing
5190 * @vsi: the VSI being stopped
5191 **/
5192void i40e_down(struct i40e_vsi *vsi)
5193{
5194 int i;
5195
5196 /* It is assumed that the caller of this function
5197 * sets the vsi->state __I40E_DOWN bit.
5198 */
5199 if (vsi->netdev) {
5200 netif_carrier_off(vsi->netdev);
5201 netif_tx_disable(vsi->netdev);
5202 }
5203 i40e_vsi_disable_irq(vsi);
5204 i40e_vsi_control_rings(vsi, false);
5205 i40e_napi_disable_all(vsi);
5206
5207 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5208 i40e_clean_tx_ring(vsi->tx_rings[i]);
5209 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5210 }
5211}
5212
5213/**
5214 * i40e_setup_tc - configure multiple traffic classes
5215 * @netdev: net device to configure
5216 * @tc: number of traffic classes to enable
5217 **/
38e00438
VD		 5218#ifdef I40E_FCOE
5219int i40e_setup_tc(struct net_device *netdev, u8 tc)
5220#else
41c445ff 5221static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5222#endif
41c445ff
JB		 5223{
5224 struct i40e_netdev_priv *np = netdev_priv(netdev);
5225 struct i40e_vsi *vsi = np->vsi;
5226 struct i40e_pf *pf = vsi->back;
5227 u8 enabled_tc = 0;
5228 int ret = -EINVAL;
5229 int i;
5230
5231 /* Check if DCB enabled to continue */
5232 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5233 netdev_info(netdev, "DCB is not enabled for adapter\n");
5234 goto exit;
5235 }
5236
5237 /* Check if MFP enabled */
5238 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5239 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5240 goto exit;
5241 }
5242
5243 /* Check whether tc count is within enabled limit */
5244 if (tc > i40e_pf_get_num_tc(pf)) {
5245 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5246 goto exit;
5247 }
5248
5249 /* Generate TC map for number of tc requested */
5250 for (i = 0; i < tc; i++)
41a1d04b 5251 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5252
5253 /* Requesting same TC configuration as already enabled */
5254 if (enabled_tc == vsi->tc_config.enabled_tc)
5255 return 0;
5256
5257 /* Quiesce VSI queues */
5258 i40e_quiesce_vsi(vsi);
5259
5260 /* Configure VSI for enabled TCs */
5261 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5262 if (ret) {
5263 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5264 vsi->seid);
5265 goto exit;
5266 }
5267
5268 /* Unquiesce VSI */
5269 i40e_unquiesce_vsi(vsi);
5270
5271exit:
5272 return ret;
5273}
5274
5275/**
5276 * i40e_open - Called when a network interface is made active
5277 * @netdev: network interface device structure
5278 *
5279 * The open entry point is called when a network interface is made
5280 * active by the system (IFF_UP). At this point all resources needed
5281 * for transmit and receive operations are allocated, the interrupt
5282 * handler is registered with the OS, the netdev watchdog subtask is
5283 * enabled, and the stack is notified that the interface is ready.
5284 *
5285 * Returns 0 on success, negative value on failure
5286 **/
38e00438 5287int i40e_open(struct net_device *netdev)
41c445ff
JB		 5288{
5289 struct i40e_netdev_priv *np = netdev_priv(netdev);
5290 struct i40e_vsi *vsi = np->vsi;
5291 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5292 int err;
5293
4eb3f768
SN		 5294 /* disallow open during test or if eeprom is broken */
5295 if (test_bit(__I40E_TESTING, &pf->state) ||
5296 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5297 return -EBUSY;
5298
5299 netif_carrier_off(netdev);
5300
6c167f58
EK		 5301 err = i40e_vsi_open(vsi);
5302 if (err)
5303 return err;
5304
059dab69
JB		 5305 /* configure global TSO hardware offload settings */
5306 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5307 TCP_FLAG_FIN) >> 16);
5308 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5309 TCP_FLAG_FIN |
5310 TCP_FLAG_CWR) >> 16);
5311 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5312
6c167f58
EK		 5313#ifdef CONFIG_I40E_VXLAN
5314 vxlan_get_rx_port(netdev);
5315#endif
5316
5317 return 0;
5318}
5319
5320/**
5321 * i40e_vsi_open -
5322 * @vsi: the VSI to open
5323 *
5324 * Finish initialization of the VSI.
5325 *
5326 * Returns 0 on success, negative value on failure
5327 **/
5328int i40e_vsi_open(struct i40e_vsi *vsi)
5329{
5330 struct i40e_pf *pf = vsi->back;
b294ac70 5331 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5332 int err;
5333
41c445ff
JB		 5334 /* allocate descriptors */
5335 err = i40e_vsi_setup_tx_resources(vsi);
5336 if (err)
5337 goto err_setup_tx;
5338 err = i40e_vsi_setup_rx_resources(vsi);
5339 if (err)
5340 goto err_setup_rx;
5341
5342 err = i40e_vsi_configure(vsi);
5343 if (err)
5344 goto err_setup_rx;
5345
c22e3c6c
SN		 5346 if (vsi->netdev) {
5347 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5348 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5349 err = i40e_vsi_request_irq(vsi, int_name);
5350 if (err)
5351 goto err_setup_rx;
41c445ff 5352
c22e3c6c
SN		 5353 /* Notify the stack of the actual queue counts. */
5354 err = netif_set_real_num_tx_queues(vsi->netdev,
5355 vsi->num_queue_pairs);
5356 if (err)
5357 goto err_set_queues;
25946ddb 5358
c22e3c6c
SN		 5359 err = netif_set_real_num_rx_queues(vsi->netdev,
5360 vsi->num_queue_pairs);
5361 if (err)
5362 goto err_set_queues;
8a9eb7d3
SN		 5363
5364 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5365 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5366 dev_driver_string(&pf->pdev->dev),
5367 dev_name(&pf->pdev->dev));
8a9eb7d3 5368 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5369
c22e3c6c 5370 } else {
ce9ccb17 5371 err = -EINVAL;
6c167f58
EK		 5372 goto err_setup_rx;
5373 }
25946ddb 5374
41c445ff
JB		 5375 err = i40e_up_complete(vsi);
5376 if (err)
5377 goto err_up_complete;
5378
41c445ff
JB		 5379 return 0;
5380
5381err_up_complete:
5382 i40e_down(vsi);
25946ddb 5383err_set_queues:
41c445ff
JB		 5384 i40e_vsi_free_irq(vsi);
5385err_setup_rx:
5386 i40e_vsi_free_rx_resources(vsi);
5387err_setup_tx:
5388 i40e_vsi_free_tx_resources(vsi);
5389 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5390 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5391
5392 return err;
5393}
5394
17a73f6b
JG		 5395/**
5396 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5397 * @pf: Pointer to PF
17a73f6b
JG		 5398 *
5399 * This function destroys the hlist where all the Flow Director
5400 * filters were saved.
5401 **/
5402static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5403{
5404 struct i40e_fdir_filter *filter;
5405 struct hlist_node *node2;
5406
5407 hlist_for_each_entry_safe(filter, node2,
5408 &pf->fdir_filter_list, fdir_node) {
5409 hlist_del(&filter->fdir_node);
5410 kfree(filter);
5411 }
5412 pf->fdir_pf_active_filters = 0;
5413}
5414
41c445ff
JB		 5415/**
5416 * i40e_close - Disables a network interface
5417 * @netdev: network interface device structure
5418 *
5419 * The close entry point is called when an interface is de-activated
5420 * by the OS. The hardware is still under the driver's control, but
5421 * this netdev interface is disabled.
5422 *
5423 * Returns 0, this is not allowed to fail
5424 **/
38e00438
VD		 5425#ifdef I40E_FCOE
5426int i40e_close(struct net_device *netdev)
5427#else
41c445ff 5428static int i40e_close(struct net_device *netdev)
38e00438 5429#endif
41c445ff
JB		 5430{
5431 struct i40e_netdev_priv *np = netdev_priv(netdev);
5432 struct i40e_vsi *vsi = np->vsi;
5433
90ef8d47 5434 i40e_vsi_close(vsi);
41c445ff
JB		 5435
5436 return 0;
5437}
5438
5439/**
5440 * i40e_do_reset - Start a PF or Core Reset sequence
5441 * @pf: board private structure
5442 * @reset_flags: which reset is requested
5443 *
5444 * The essential difference in resets is that the PF Reset
5445 * doesn't clear the packet buffers, doesn't reset the PE
5446 * firmware, and doesn't bother the other PFs on the chip.
5447 **/
5448void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5449{
5450 u32 val;
5451
5452 WARN_ON(in_interrupt());
5453
263fc48f
MW		 5454 if (i40e_check_asq_alive(&pf->hw))
5455 i40e_vc_notify_reset(pf);
5456
41c445ff 5457 /* do the biggest reset indicated */
41a1d04b 5458 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5459
5460 /* Request a Global Reset
5461 *
5462 * This will start the chip's countdown to the actual full
5463 * chip reset event, and a warning interrupt to be sent
5464 * to all PFs, including the requestor. Our handler
5465 * for the warning interrupt will deal with the shutdown
5466 * and recovery of the switch setup.
5467 */
69bfb110 5468 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5469 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5470 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5471 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5472
41a1d04b 5473 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5474
5475 /* Request a Core Reset
5476 *
5477 * Same as Global Reset, except does *not* include the MAC/PHY
5478 */
69bfb110 5479 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5480 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5481 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5482 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5483 i40e_flush(&pf->hw);
5484
41a1d04b 5485 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5486
5487 /* Request a PF Reset
5488 *
5489 * Resets only the PF-specific registers
5490 *
5491 * This goes directly to the tear-down and rebuild of
5492 * the switch, since we need to do all the recovery as
5493 * for the Core Reset.
5494 */
69bfb110 5495 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5496 i40e_handle_reset_warning(pf);
5497
41a1d04b 5498 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5499 int v;
5500
5501 /* Find the VSI(s) that requested a re-init */
5502 dev_info(&pf->pdev->dev,
5503 "VSI reinit requested\n");
505682cd 5504 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5505 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5506
41c445ff
JB		 5507 if (vsi != NULL &&
5508 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5509 i40e_vsi_reinit_locked(pf->vsi[v]);
5510 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5511 }
5512 }
41a1d04b 5513 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5514 int v;
5515
5516 /* Find the VSI(s) that needs to be brought down */
5517 dev_info(&pf->pdev->dev, "VSI down requested\n");
5518 for (v = 0; v < pf->num_alloc_vsi; v++) {
5519 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5520
b5d06f05
NP		 5521 if (vsi != NULL &&
5522 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5523 set_bit(__I40E_DOWN, &vsi->state);
5524 i40e_down(vsi);
5525 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5526 }
5527 }
41c445ff
JB		 5528 } else {
5529 dev_info(&pf->pdev->dev,
5530 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5531 }
5532}
5533
4e3b35b0
NP		 5534#ifdef CONFIG_I40E_DCB
5535/**
5536 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5537 * @pf: board private structure
5538 * @old_cfg: current DCB config
5539 * @new_cfg: new DCB config
5540 **/
5541bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5542 struct i40e_dcbx_config *old_cfg,
5543 struct i40e_dcbx_config *new_cfg)
5544{
5545 bool need_reconfig = false;
5546
5547 /* Check if ETS configuration has changed */
5548 if (memcmp(&new_cfg->etscfg,
5549 &old_cfg->etscfg,
5550 sizeof(new_cfg->etscfg))) {
5551 /* If Priority Table has changed reconfig is needed */
5552 if (memcmp(&new_cfg->etscfg.prioritytable,
5553 &old_cfg->etscfg.prioritytable,
5554 sizeof(new_cfg->etscfg.prioritytable))) {
5555 need_reconfig = true;
69bfb110 5556 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5557 }
5558
5559 if (memcmp(&new_cfg->etscfg.tcbwtable,
5560 &old_cfg->etscfg.tcbwtable,
5561 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5562 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5563
5564 if (memcmp(&new_cfg->etscfg.tsatable,
5565 &old_cfg->etscfg.tsatable,
5566 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5567 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5568 }
5569
5570 /* Check if PFC configuration has changed */
5571 if (memcmp(&new_cfg->pfc,
5572 &old_cfg->pfc,
5573 sizeof(new_cfg->pfc))) {
5574 need_reconfig = true;
69bfb110 5575 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5576 }
5577
5578 /* Check if APP Table has changed */
5579 if (memcmp(&new_cfg->app,
5580 &old_cfg->app,
3d9667a9 5581 sizeof(new_cfg->app))) {
4e3b35b0 5582 need_reconfig = true;
69bfb110 5583 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5584 }
4e3b35b0 5585
fb43201f 5586 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5587 return need_reconfig;
5588}
5589
5590/**
5591 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5592 * @pf: board private structure
5593 * @e: event info posted on ARQ
5594 **/
5595static int i40e_handle_lldp_event(struct i40e_pf *pf,
5596 struct i40e_arq_event_info *e)
5597{
5598 struct i40e_aqc_lldp_get_mib *mib =
5599 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5600 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5601 struct i40e_dcbx_config tmp_dcbx_cfg;
5602 bool need_reconfig = false;
5603 int ret = 0;
5604 u8 type;
5605
4d9b6043
NP		 5606 /* Not DCB capable or capability disabled */
5607 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5608 return ret;
5609
4e3b35b0
NP		 5610 /* Ignore if event is not for Nearest Bridge */
5611 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5612 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5613 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5614 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5615 return ret;
5616
5617 /* Check MIB Type and return if event for Remote MIB update */
5618 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5619 dev_dbg(&pf->pdev->dev,
fb43201f 5620 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5621 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5622 /* Update the remote cached instance and return */
5623 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5624 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5625 &hw->remote_dcbx_config);
5626 goto exit;
5627 }
5628
9fa61dd2 5629 /* Store the old configuration */
1a2f6248 5630 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5631
750fcbcf
NP		 5632 /* Reset the old DCBx configuration data */
5633 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5634 /* Get updated DCBX data from firmware */
5635 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5636 if (ret) {
f1c7e72e
SN		 5637 dev_info(&pf->pdev->dev,
5638 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5639 i40e_stat_str(&pf->hw, ret),
5640 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5641 goto exit;
5642 }
5643
5644 /* No change detected in DCBX configs */
750fcbcf
NP		 5645 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5646 sizeof(tmp_dcbx_cfg))) {
69bfb110 5647 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5648 goto exit;
5649 }
5650
750fcbcf
NP		 5651 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5652 &hw->local_dcbx_config);
4e3b35b0 5653
750fcbcf 5654 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5655
5656 if (!need_reconfig)
5657 goto exit;
5658
4d9b6043 5659 /* Enable DCB tagging only when more than one TC */
750fcbcf 5660 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5661 pf->flags |= I40E_FLAG_DCB_ENABLED;
5662 else
5663 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5664
69129dc3 5665 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5666 /* Reconfiguration needed quiesce all VSIs */
5667 i40e_pf_quiesce_all_vsi(pf);
5668
5669 /* Changes in configuration update VEB/VSI */
5670 i40e_dcb_reconfigure(pf);
5671
2fd75f31
NP		 5672 ret = i40e_resume_port_tx(pf);
5673
69129dc3 5674 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5675 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5676 if (ret)
5677 goto exit;
5678
5679 /* Wait for the PF's Tx queues to be disabled */
5680 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5681 if (ret) {
5682 /* Schedule PF reset to recover */
5683 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5684 i40e_service_event_schedule(pf);
5685 } else {
2fd75f31 5686 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5687 }
5688
4e3b35b0
NP		 5689exit:
5690 return ret;
5691}
5692#endif /* CONFIG_I40E_DCB */
5693
23326186
ASJ		 5694/**
5695 * i40e_do_reset_safe - Protected reset path for userland calls.
5696 * @pf: board private structure
5697 * @reset_flags: which reset is requested
5698 *
5699 **/
5700void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5701{
5702 rtnl_lock();
5703 i40e_do_reset(pf, reset_flags);
5704 rtnl_unlock();
5705}
5706
41c445ff
JB		 5707/**
5708 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5709 * @pf: board private structure
5710 * @e: event info posted on ARQ
5711 *
5712 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5713 * and VF queues
5714 **/
5715static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5716 struct i40e_arq_event_info *e)
5717{
5718 struct i40e_aqc_lan_overflow *data =
5719 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5720 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5721 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5722 struct i40e_hw *hw = &pf->hw;
5723 struct i40e_vf *vf;
5724 u16 vf_id;
5725
69bfb110
JB		 5726 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5727 queue, qtx_ctl);
41c445ff
JB		 5728
5729 /* Queue belongs to VF, find the VF and issue VF reset */
5730 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5731 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5732 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5733 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5734 vf_id -= hw->func_caps.vf_base_id;
5735 vf = &pf->vf[vf_id];
5736 i40e_vc_notify_vf_reset(vf);
5737 /* Allow VF to process pending reset notification */
5738 msleep(20);
5739 i40e_reset_vf(vf, false);
5740 }
5741}
5742
5743/**
5744 * i40e_service_event_complete - Finish up the service event
5745 * @pf: board private structure
5746 **/
5747static void i40e_service_event_complete(struct i40e_pf *pf)
5748{
b875f99b 5749 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5750
5751 /* flush memory to make sure state is correct before next watchog */
4e857c58 5752 smp_mb__before_atomic();
41c445ff
JB		 5753 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5754}
5755
55a5e60b 5756/**
12957388
ASJ		 5757 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5758 * @pf: board private structure
5759 **/
04294e38 5760u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5761{
04294e38 5762 u32 val, fcnt_prog;
12957388
ASJ		 5763
5764 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5765 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5766 return fcnt_prog;
5767}
5768
5769/**
04294e38 5770 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5771 * @pf: board private structure
5772 **/
04294e38 5773u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5774{
04294e38
ASJ		 5775 u32 val, fcnt_prog;
5776
55a5e60b
ASJ		 5777 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5778 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5779 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5780 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5781 return fcnt_prog;
5782}
1e1be8f6 5783
04294e38
ASJ		 5784/**
5785 * i40e_get_global_fd_count - Get total FD filters programmed on device
5786 * @pf: board private structure
5787 **/
5788u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5789{
5790 u32 val, fcnt_prog;
5791
5792 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5793 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5794 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5795 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5796 return fcnt_prog;
5797}
5798
55a5e60b
ASJ		 5799/**
5800 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5801 * @pf: board private structure
5802 **/
5803void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5804{
3487b6c3 5805 struct i40e_fdir_filter *filter;
55a5e60b 5806 u32 fcnt_prog, fcnt_avail;
3487b6c3 5807 struct hlist_node *node;
55a5e60b 5808
1e1be8f6
ASJ		 5809 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5810 return;
5811
55a5e60b
ASJ		 5812 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5813 * to re-enable
5814 */
04294e38 5815 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5816 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5817 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5818 (pf->fd_add_err == 0) ||
5819 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5820 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5821 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5822 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5823 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5824 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5825 }
5826 }
5827 /* Wait for some more space to be available to turn on ATR */
5828 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5829 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5830 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5831 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5832 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5833 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5834 }
5835 }
3487b6c3
CW		 5836
5837 /* if hw had a problem adding a filter, delete it */
5838 if (pf->fd_inv > 0) {
5839 hlist_for_each_entry_safe(filter, node,
5840 &pf->fdir_filter_list, fdir_node) {
5841 if (filter->fd_id == pf->fd_inv) {
5842 hlist_del(&filter->fdir_node);
5843 kfree(filter);
5844 pf->fdir_pf_active_filters--;
5845 }
5846 }
5847 }
55a5e60b
ASJ		 5848}
5849
1e1be8f6 5850#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5851#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5852/**
5853 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5854 * @pf: board private structure
5855 **/
5856static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5857{
04294e38 5858 unsigned long min_flush_time;
1e1be8f6 5859 int flush_wait_retry = 50;
04294e38
ASJ		 5860 bool disable_atr = false;
5861 int fd_room;
1e1be8f6
ASJ		 5862 int reg;
5863
1790ed0c
AA		 5864 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5865 return;
5866
a5fdaf34
JB		 5867 if (!time_after(jiffies, pf->fd_flush_timestamp +
5868 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5869 return;
04294e38 5870
a5fdaf34
JB		 5871 /* If the flush is happening too quick and we have mostly SB rules we
5872 * should not re-enable ATR for some time.
5873 */
5874 min_flush_time = pf->fd_flush_timestamp +
5875 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5876 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5877
5878 if (!(time_after(jiffies, min_flush_time)) &&
5879 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5880 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5881 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5882 disable_atr = true;
5883 }
5884
5885 pf->fd_flush_timestamp = jiffies;
5886 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5887 /* flush all filters */
5888 wr32(&pf->hw, I40E_PFQF_CTL_1,
5889 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5890 i40e_flush(&pf->hw);
5891 pf->fd_flush_cnt++;
5892 pf->fd_add_err = 0;
5893 do {
5894 /* Check FD flush status every 5-6msec */
5895 usleep_range(5000, 6000);
5896 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5897 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5898 break;
5899 } while (flush_wait_retry--);
5900 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5901 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5902 } else {
5903 /* replay sideband filters */
5904 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5905 if (!disable_atr)
5906 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5907 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5908 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5909 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5910 }
a5fdaf34 5911
1e1be8f6
ASJ		 5912}
5913
5914/**
5915 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5916 * @pf: board private structure
5917 **/
04294e38 5918u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5919{
5920 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5921}
5922
5923/* We can see up to 256 filter programming desc in transit if the filters are
5924 * being applied really fast; before we see the first
5925 * filter miss error on Rx queue 0. Accumulating enough error messages before
5926 * reacting will make sure we don't cause flush too often.
5927 */
5928#define I40E_MAX_FD_PROGRAM_ERROR 256
5929
41c445ff
JB		 5930/**
5931 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5932 * @pf: board private structure
5933 **/
5934static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5935{
41c445ff 5936
41c445ff
JB		 5937 /* if interface is down do nothing */
5938 if (test_bit(__I40E_DOWN, &pf->state))
5939 return;
1e1be8f6 5940
1790ed0c
AA		 5941 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5942 return;
5943
04294e38 5944 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5945 i40e_fdir_flush_and_replay(pf);
5946
55a5e60b
ASJ		 5947 i40e_fdir_check_and_reenable(pf);
5948
41c445ff
JB		 5949}
5950
5951/**
5952 * i40e_vsi_link_event - notify VSI of a link event
5953 * @vsi: vsi to be notified
5954 * @link_up: link up or down
5955 **/
5956static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5957{
32b5b811 5958 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5959 return;
5960
5961 switch (vsi->type) {
5962 case I40E_VSI_MAIN:
38e00438
VD		 5963#ifdef I40E_FCOE
5964 case I40E_VSI_FCOE:
5965#endif
41c445ff
JB		 5966 if (!vsi->netdev || !vsi->netdev_registered)
5967 break;
5968
5969 if (link_up) {
5970 netif_carrier_on(vsi->netdev);
5971 netif_tx_wake_all_queues(vsi->netdev);
5972 } else {
5973 netif_carrier_off(vsi->netdev);
5974 netif_tx_stop_all_queues(vsi->netdev);
5975 }
5976 break;
5977
5978 case I40E_VSI_SRIOV:
41c445ff
JB		 5979 case I40E_VSI_VMDQ2:
5980 case I40E_VSI_CTRL:
5981 case I40E_VSI_MIRROR:
5982 default:
5983 /* there is no notification for other VSIs */
5984 break;
5985 }
5986}
5987
5988/**
5989 * i40e_veb_link_event - notify elements on the veb of a link event
5990 * @veb: veb to be notified
5991 * @link_up: link up or down
5992 **/
5993static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5994{
5995 struct i40e_pf *pf;
5996 int i;
5997
5998 if (!veb || !veb->pf)
5999 return;
6000 pf = veb->pf;
6001
6002 /* depth first... */
6003 for (i = 0; i < I40E_MAX_VEB; i++)
6004 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6005 i40e_veb_link_event(pf->veb[i], link_up);
6006
6007 /* ... now the local VSIs */
505682cd 6008 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6009 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6010 i40e_vsi_link_event(pf->vsi[i], link_up);
6011}
6012
6013/**
6014 * i40e_link_event - Update netif_carrier status
6015 * @pf: board private structure
6016 **/
6017static void i40e_link_event(struct i40e_pf *pf)
6018{
320684cd 6019 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6020 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6021 i40e_status status;
6022 bool new_link, old_link;
41c445ff 6023
1f9610e4
CS		 6024 /* save off old link status information */
6025 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6026
1e701e09
JB		 6027 /* set this to force the get_link_status call to refresh state */
6028 pf->hw.phy.get_link_info = true;
6029
41c445ff 6030 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6031
6032 status = i40e_get_link_status(&pf->hw, &new_link);
6033 if (status) {
6034 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6035 status);
6036 return;
6037 }
6038
fef59ddf
CS		 6039 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6040 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6041
1e701e09 6042 if (new_link == old_link &&
fef59ddf 6043 new_link_speed == old_link_speed &&
320684cd
MW		 6044 (test_bit(__I40E_DOWN, &vsi->state) ||
6045 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6046 return;
320684cd
MW		 6047
6048 if (!test_bit(__I40E_DOWN, &vsi->state))
6049 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6050
6051 /* Notify the base of the switch tree connected to
6052 * the link. Floating VEBs are not notified.
6053 */
6054 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6055 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6056 else
320684cd 6057 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6058
6059 if (pf->vf)
6060 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6061
6062 if (pf->flags & I40E_FLAG_PTP)
6063 i40e_ptp_set_increment(pf);
41c445ff
JB		 6064}
6065
41c445ff 6066/**
21536717 6067 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6068 * @pf: board private structure
6069 **/
6070static void i40e_watchdog_subtask(struct i40e_pf *pf)
6071{
6072 int i;
6073
6074 /* if interface is down do nothing */
6075 if (test_bit(__I40E_DOWN, &pf->state) ||
6076 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6077 return;
6078
21536717
SN		 6079 /* make sure we don't do these things too often */
6080 if (time_before(jiffies, (pf->service_timer_previous +
6081 pf->service_timer_period)))
6082 return;
6083 pf->service_timer_previous = jiffies;
6084
9ac77266
SN		 6085 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6086 i40e_link_event(pf);
21536717 6087
41c445ff
JB		 6088 /* Update the stats for active netdevs so the network stack
6089 * can look at updated numbers whenever it cares to
6090 */
505682cd 6091 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6092 if (pf->vsi[i] && pf->vsi[i]->netdev)
6093 i40e_update_stats(pf->vsi[i]);
6094
d1a8d275
ASJ		 6095 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6096 /* Update the stats for the active switching components */
6097 for (i = 0; i < I40E_MAX_VEB; i++)
6098 if (pf->veb[i])
6099 i40e_update_veb_stats(pf->veb[i]);
6100 }
beb0dff1
JK		 6101
6102 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6103}
6104
6105/**
6106 * i40e_reset_subtask - Set up for resetting the device and driver
6107 * @pf: board private structure
6108 **/
6109static void i40e_reset_subtask(struct i40e_pf *pf)
6110{
6111 u32 reset_flags = 0;
6112
23326186 6113 rtnl_lock();
41c445ff 6114 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 6115 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6116 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6117 }
6118 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 6119 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6120 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6121 }
6122 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 6123 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6124 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6125 }
6126 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 6127 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6128 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6129 }
b5d06f05 6130 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 6131 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6132 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6133 }
41c445ff
JB		 6134
6135 /* If there's a recovery already waiting, it takes
6136 * precedence before starting a new reset sequence.
6137 */
6138 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6139 i40e_handle_reset_warning(pf);
23326186 6140 goto unlock;
41c445ff
JB		 6141 }
6142
6143 /* If we're already down or resetting, just bail */
6144 if (reset_flags &&
6145 !test_bit(__I40E_DOWN, &pf->state) &&
6146 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6147 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6148
6149unlock:
6150 rtnl_unlock();
41c445ff
JB		 6151}
6152
6153/**
6154 * i40e_handle_link_event - Handle link event
6155 * @pf: board private structure
6156 * @e: event info posted on ARQ
6157 **/
6158static void i40e_handle_link_event(struct i40e_pf *pf,
6159 struct i40e_arq_event_info *e)
6160{
41c445ff
JB		 6161 struct i40e_aqc_get_link_status *status =
6162 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6163
1e701e09
JB		 6164 /* Do a new status request to re-enable LSE reporting
6165 * and load new status information into the hw struct
6166 * This completely ignores any state information
6167 * in the ARQ event info, instead choosing to always
6168 * issue the AQ update link status command.
6169 */
6170 i40e_link_event(pf);
6171
7b592f61
CW		 6172 /* check for unqualified module, if link is down */
6173 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6174 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6175 (!(status->link_info & I40E_AQ_LINK_UP)))
6176 dev_err(&pf->pdev->dev,
6177 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6178}
6179
6180/**
6181 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6182 * @pf: board private structure
6183 **/
6184static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6185{
6186 struct i40e_arq_event_info event;
6187 struct i40e_hw *hw = &pf->hw;
6188 u16 pending, i = 0;
6189 i40e_status ret;
6190 u16 opcode;
86df242b 6191 u32 oldval;
41c445ff
JB		 6192 u32 val;
6193
a316f651
ASJ		 6194 /* Do not run clean AQ when PF reset fails */
6195 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6196 return;
6197
86df242b
SN		 6198 /* check for error indications */
6199 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6200 oldval = val;
6201 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6202 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6203 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6204 }
6205 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6206 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6207 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6208 }
6209 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6210 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6211 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6212 }
6213 if (oldval != val)
6214 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6215
6216 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6217 oldval = val;
6218 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6219 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6220 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6221 }
6222 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6223 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6224 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6225 }
6226 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6227 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6228 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6229 }
6230 if (oldval != val)
6231 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6232
1001dc37
MW		 6233 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6234 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6235 if (!event.msg_buf)
6236 return;
6237
6238 do {
6239 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6240 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6241 break;
56497978 6242 else if (ret) {
41c445ff
JB		 6243 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6244 break;
6245 }
6246
6247 opcode = le16_to_cpu(event.desc.opcode);
6248 switch (opcode) {
6249
6250 case i40e_aqc_opc_get_link_status:
6251 i40e_handle_link_event(pf, &event);
6252 break;
6253 case i40e_aqc_opc_send_msg_to_pf:
6254 ret = i40e_vc_process_vf_msg(pf,
6255 le16_to_cpu(event.desc.retval),
6256 le32_to_cpu(event.desc.cookie_high),
6257 le32_to_cpu(event.desc.cookie_low),
6258 event.msg_buf,
1001dc37 6259 event.msg_len);
41c445ff
JB		 6260 break;
6261 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6262 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6263#ifdef CONFIG_I40E_DCB
6264 rtnl_lock();
6265 ret = i40e_handle_lldp_event(pf, &event);
6266 rtnl_unlock();
6267#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6268 break;
6269 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6270 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6271 i40e_handle_lan_overflow_event(pf, &event);
6272 break;
0467bc91
SN		 6273 case i40e_aqc_opc_send_msg_to_peer:
6274 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6275 break;
91a0f930
SN		 6276 case i40e_aqc_opc_nvm_erase:
6277 case i40e_aqc_opc_nvm_update:
6278 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6279 break;
41c445ff
JB		 6280 default:
6281 dev_info(&pf->pdev->dev,
0467bc91
SN		 6282 "ARQ Error: Unknown event 0x%04x received\n",
6283 opcode);
41c445ff
JB		 6284 break;
6285 }
6286 } while (pending && (i++ < pf->adminq_work_limit));
6287
6288 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6289 /* re-enable Admin queue interrupt cause */
6290 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6291 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6292 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6293 i40e_flush(hw);
6294
6295 kfree(event.msg_buf);
6296}
6297
4eb3f768
SN		 6298/**
6299 * i40e_verify_eeprom - make sure eeprom is good to use
6300 * @pf: board private structure
6301 **/
6302static void i40e_verify_eeprom(struct i40e_pf *pf)
6303{
6304 int err;
6305
6306 err = i40e_diag_eeprom_test(&pf->hw);
6307 if (err) {
6308 /* retry in case of garbage read */
6309 err = i40e_diag_eeprom_test(&pf->hw);
6310 if (err) {
6311 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6312 err);
6313 set_bit(__I40E_BAD_EEPROM, &pf->state);
6314 }
6315 }
6316
6317 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6318 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6319 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6320 }
6321}
6322
386a0afa
AA		 6323/**
6324 * i40e_enable_pf_switch_lb
b40c82e6 6325 * @pf: pointer to the PF structure
386a0afa
AA		 6326 *
6327 * enable switch loop back or die - no point in a return value
6328 **/
6329static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6330{
6331 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6332 struct i40e_vsi_context ctxt;
f1c7e72e 6333 int ret;
386a0afa
AA		 6334
6335 ctxt.seid = pf->main_vsi_seid;
6336 ctxt.pf_num = pf->hw.pf_id;
6337 ctxt.vf_num = 0;
f1c7e72e
SN		 6338 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6339 if (ret) {
386a0afa 6340 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6341 "couldn't get PF vsi config, err %s aq_err %s\n",
6342 i40e_stat_str(&pf->hw, ret),
6343 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6344 return;
6345 }
6346 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6347 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6348 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6349
f1c7e72e
SN		 6350 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6351 if (ret) {
386a0afa 6352 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6353 "update vsi switch failed, err %s aq_err %s\n",
6354 i40e_stat_str(&pf->hw, ret),
6355 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6356 }
6357}
6358
6359/**
6360 * i40e_disable_pf_switch_lb
b40c82e6 6361 * @pf: pointer to the PF structure
386a0afa
AA		 6362 *
6363 * disable switch loop back or die - no point in a return value
6364 **/
6365static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6366{
6367 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6368 struct i40e_vsi_context ctxt;
f1c7e72e 6369 int ret;
386a0afa
AA		 6370
6371 ctxt.seid = pf->main_vsi_seid;
6372 ctxt.pf_num = pf->hw.pf_id;
6373 ctxt.vf_num = 0;
f1c7e72e
SN		 6374 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6375 if (ret) {
386a0afa 6376 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6377 "couldn't get PF vsi config, err %s aq_err %s\n",
6378 i40e_stat_str(&pf->hw, ret),
6379 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6380 return;
6381 }
6382 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6383 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6384 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6385
f1c7e72e
SN		 6386 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6387 if (ret) {
386a0afa 6388 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6389 "update vsi switch failed, err %s aq_err %s\n",
6390 i40e_stat_str(&pf->hw, ret),
6391 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6392 }
6393}
6394
51616018
NP		 6395/**
6396 * i40e_config_bridge_mode - Configure the HW bridge mode
6397 * @veb: pointer to the bridge instance
6398 *
6399 * Configure the loop back mode for the LAN VSI that is downlink to the
6400 * specified HW bridge instance. It is expected this function is called
6401 * when a new HW bridge is instantiated.
6402 **/
6403static void i40e_config_bridge_mode(struct i40e_veb *veb)
6404{
6405 struct i40e_pf *pf = veb->pf;
6406
6dec1017
SN		 6407 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6408 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6409 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6410 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6411 i40e_disable_pf_switch_lb(pf);
6412 else
6413 i40e_enable_pf_switch_lb(pf);
6414}
6415
41c445ff
JB		 6416/**
6417 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6418 * @veb: pointer to the VEB instance
6419 *
6420 * This is a recursive function that first builds the attached VSIs then
6421 * recurses in to build the next layer of VEB. We track the connections
6422 * through our own index numbers because the seid's from the HW could
6423 * change across the reset.
6424 **/
6425static int i40e_reconstitute_veb(struct i40e_veb *veb)
6426{
6427 struct i40e_vsi *ctl_vsi = NULL;
6428 struct i40e_pf *pf = veb->pf;
6429 int v, veb_idx;
6430 int ret;
6431
6432 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6433 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6434 if (pf->vsi[v] &&
6435 pf->vsi[v]->veb_idx == veb->idx &&
6436 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6437 ctl_vsi = pf->vsi[v];
6438 break;
6439 }
6440 }
6441 if (!ctl_vsi) {
6442 dev_info(&pf->pdev->dev,
6443 "missing owner VSI for veb_idx %d\n", veb->idx);
6444 ret = -ENOENT;
6445 goto end_reconstitute;
6446 }
6447 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6448 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6449 ret = i40e_add_vsi(ctl_vsi);
6450 if (ret) {
6451 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6452 "rebuild of veb_idx %d owner VSI failed: %d\n",
6453 veb->idx, ret);
41c445ff
JB		 6454 goto end_reconstitute;
6455 }
6456 i40e_vsi_reset_stats(ctl_vsi);
6457
6458 /* create the VEB in the switch and move the VSI onto the VEB */
6459 ret = i40e_add_veb(veb, ctl_vsi);
6460 if (ret)
6461 goto end_reconstitute;
6462
fc60861e
ASJ		 6463 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6464 veb->bridge_mode = BRIDGE_MODE_VEB;
6465 else
6466 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6467 i40e_config_bridge_mode(veb);
b64ba084 6468
41c445ff 6469 /* create the remaining VSIs attached to this VEB */
505682cd 6470 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6471 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6472 continue;
6473
6474 if (pf->vsi[v]->veb_idx == veb->idx) {
6475 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6476
41c445ff
JB		 6477 vsi->uplink_seid = veb->seid;
6478 ret = i40e_add_vsi(vsi);
6479 if (ret) {
6480 dev_info(&pf->pdev->dev,
6481 "rebuild of vsi_idx %d failed: %d\n",
6482 v, ret);
6483 goto end_reconstitute;
6484 }
6485 i40e_vsi_reset_stats(vsi);
6486 }
6487 }
6488
6489 /* create any VEBs attached to this VEB - RECURSION */
6490 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6491 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6492 pf->veb[veb_idx]->uplink_seid = veb->seid;
6493 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6494 if (ret)
6495 break;
6496 }
6497 }
6498
6499end_reconstitute:
6500 return ret;
6501}
6502
6503/**
6504 * i40e_get_capabilities - get info about the HW
6505 * @pf: the PF struct
6506 **/
6507static int i40e_get_capabilities(struct i40e_pf *pf)
6508{
6509 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6510 u16 data_size;
6511 int buf_len;
6512 int err;
6513
6514 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6515 do {
6516 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6517 if (!cap_buf)
6518 return -ENOMEM;
6519
6520 /* this loads the data into the hw struct for us */
6521 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6522 &data_size,
6523 i40e_aqc_opc_list_func_capabilities,
6524 NULL);
6525 /* data loaded, buffer no longer needed */
6526 kfree(cap_buf);
6527
6528 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6529 /* retry with a larger buffer */
6530 buf_len = data_size;
6531 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6532 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6533 "capability discovery failed, err %s aq_err %s\n",
6534 i40e_stat_str(&pf->hw, err),
6535 i40e_aq_str(&pf->hw,
6536 pf->hw.aq.asq_last_status));
41c445ff
JB		 6537 return -ENODEV;
6538 }
6539 } while (err);
6540
6541 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6542 dev_info(&pf->pdev->dev,
6543 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6544 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6545 pf->hw.func_caps.num_msix_vectors,
6546 pf->hw.func_caps.num_msix_vectors_vf,
6547 pf->hw.func_caps.fd_filters_guaranteed,
6548 pf->hw.func_caps.fd_filters_best_effort,
6549 pf->hw.func_caps.num_tx_qp,
6550 pf->hw.func_caps.num_vsis);
6551
7134f9ce
JB		 6552#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6553 + pf->hw.func_caps.num_vfs)
6554 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6555 dev_info(&pf->pdev->dev,
6556 "got num_vsis %d, setting num_vsis to %d\n",
6557 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6558 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6559 }
6560
41c445ff
JB		 6561 return 0;
6562}
6563
cbf61325
ASJ		 6564static int i40e_vsi_clear(struct i40e_vsi *vsi);
6565
41c445ff 6566/**
cbf61325 6567 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6568 * @pf: board private structure
6569 **/
cbf61325 6570static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6571{
6572 struct i40e_vsi *vsi;
8a9eb7d3 6573 int i;
41c445ff 6574
407e063c
JB		 6575 /* quick workaround for an NVM issue that leaves a critical register
6576 * uninitialized
6577 */
6578 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6579 static const u32 hkey[] = {
6580 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6581 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6582 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6583 0x95b3a76d};
6584
6585 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6586 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6587 }
6588
cbf61325 6589 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6590 return;
6591
cbf61325 6592 /* find existing VSI and see if it needs configuring */
41c445ff 6593 vsi = NULL;
505682cd 6594 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6595 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6596 vsi = pf->vsi[i];
cbf61325
ASJ		 6597 break;
6598 }
6599 }
6600
6601 /* create a new VSI if none exists */
41c445ff 6602 if (!vsi) {
cbf61325
ASJ		 6603 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6604 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6605 if (!vsi) {
6606 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6607 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6608 return;
41c445ff 6609 }
cbf61325 6610 }
41c445ff 6611
8a9eb7d3 6612 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6613}
6614
6615/**
6616 * i40e_fdir_teardown - release the Flow Director resources
6617 * @pf: board private structure
6618 **/
6619static void i40e_fdir_teardown(struct i40e_pf *pf)
6620{
6621 int i;
6622
17a73f6b 6623 i40e_fdir_filter_exit(pf);
505682cd 6624 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6625 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6626 i40e_vsi_release(pf->vsi[i]);
6627 break;
6628 }
6629 }
6630}
6631
6632/**
f650a38b 6633 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6634 * @pf: board private structure
6635 *
b40c82e6 6636 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6637 **/
23cfbe07 6638static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6639{
41c445ff 6640 struct i40e_hw *hw = &pf->hw;
60442dea 6641 i40e_status ret = 0;
41c445ff
JB		 6642 u32 v;
6643
6644 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6645 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6646 return;
41c445ff 6647
69bfb110 6648 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6649
41c445ff
JB		 6650 /* quiesce the VSIs and their queues that are not already DOWN */
6651 i40e_pf_quiesce_all_vsi(pf);
6652
505682cd 6653 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6654 if (pf->vsi[v])
6655 pf->vsi[v]->seid = 0;
6656 }
6657
6658 i40e_shutdown_adminq(&pf->hw);
6659
f650a38b 6660 /* call shutdown HMC */
60442dea
SN		 6661 if (hw->hmc.hmc_obj) {
6662 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6663 if (ret)
60442dea
SN		 6664 dev_warn(&pf->pdev->dev,
6665 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6666 }
f650a38b
ASJ		 6667}
6668
44033fac
JB		 6669/**
6670 * i40e_send_version - update firmware with driver version
6671 * @pf: PF struct
6672 */
6673static void i40e_send_version(struct i40e_pf *pf)
6674{
6675 struct i40e_driver_version dv;
6676
6677 dv.major_version = DRV_VERSION_MAJOR;
6678 dv.minor_version = DRV_VERSION_MINOR;
6679 dv.build_version = DRV_VERSION_BUILD;
6680 dv.subbuild_version = 0;
35a7d804 6681 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6682 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6683}
6684
f650a38b 6685/**
4dda12e6 6686 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6687 * @pf: board private structure
bc7d338f 6688 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6689 **/
bc7d338f 6690static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6691{
f650a38b 6692 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6693 u8 set_fc_aq_fail = 0;
f650a38b 6694 i40e_status ret;
4f2f017c 6695 u32 val;
f650a38b
ASJ		 6696 u32 v;
6697
41c445ff
JB		 6698 /* Now we wait for GRST to settle out.
6699 * We don't have to delete the VEBs or VSIs from the hw switch
6700 * because the reset will make them disappear.
6701 */
6702 ret = i40e_pf_reset(hw);
b5565400 6703 if (ret) {
41c445ff 6704 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6705 set_bit(__I40E_RESET_FAILED, &pf->state);
6706 goto clear_recovery;
b5565400 6707 }
41c445ff
JB		 6708 pf->pfr_count++;
6709
6710 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6711 goto clear_recovery;
69bfb110 6712 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6713
6714 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6715 ret = i40e_init_adminq(&pf->hw);
6716 if (ret) {
f1c7e72e
SN		 6717 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6718 i40e_stat_str(&pf->hw, ret),
6719 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6720 goto clear_recovery;
41c445ff
JB		 6721 }
6722
4eb3f768 6723 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6724 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6725 i40e_verify_eeprom(pf);
4eb3f768 6726
e78ac4bf 6727 i40e_clear_pxe_mode(hw);
41c445ff 6728 ret = i40e_get_capabilities(pf);
f1c7e72e 6729 if (ret)
41c445ff 6730 goto end_core_reset;
41c445ff 6731
41c445ff
JB		 6732 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6733 hw->func_caps.num_rx_qp,
6734 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6735 if (ret) {
6736 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6737 goto end_core_reset;
6738 }
6739 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6740 if (ret) {
6741 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6742 goto end_core_reset;
6743 }
6744
4e3b35b0
NP		 6745#ifdef CONFIG_I40E_DCB
6746 ret = i40e_init_pf_dcb(pf);
6747 if (ret) {
aebfc816
SN		 6748 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6749 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6750 /* Continue without DCB enabled */
4e3b35b0
NP		 6751 }
6752#endif /* CONFIG_I40E_DCB */
38e00438 6753#ifdef I40E_FCOE
21364bcf 6754 i40e_init_pf_fcoe(pf);
4e3b35b0 6755
38e00438 6756#endif
41c445ff 6757 /* do basic switch setup */
bc7d338f 6758 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6759 if (ret)
6760 goto end_core_reset;
6761
7e2453fe
JB		 6762 /* driver is only interested in link up/down and module qualification
6763 * reports from firmware
6764 */
6765 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6766 I40E_AQ_EVENT_LINK_UPDOWN |
6767 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6768 if (ret)
f1c7e72e
SN		 6769 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6770 i40e_stat_str(&pf->hw, ret),
6771 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6772
cafa2ee6
ASJ		 6773 /* make sure our flow control settings are restored */
6774 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6775 if (ret)
8279e495
NP		 6776 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6777 i40e_stat_str(&pf->hw, ret),
6778 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6779
41c445ff
JB		 6780 /* Rebuild the VSIs and VEBs that existed before reset.
6781 * They are still in our local switch element arrays, so only
6782 * need to rebuild the switch model in the HW.
6783 *
6784 * If there were VEBs but the reconstitution failed, we'll try
6785 * try to recover minimal use by getting the basic PF VSI working.
6786 */
6787 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6788 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6789 /* find the one VEB connected to the MAC, and find orphans */
6790 for (v = 0; v < I40E_MAX_VEB; v++) {
6791 if (!pf->veb[v])
6792 continue;
6793
6794 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6795 pf->veb[v]->uplink_seid == 0) {
6796 ret = i40e_reconstitute_veb(pf->veb[v]);
6797
6798 if (!ret)
6799 continue;
6800
6801 /* If Main VEB failed, we're in deep doodoo,
6802 * so give up rebuilding the switch and set up
6803 * for minimal rebuild of PF VSI.
6804 * If orphan failed, we'll report the error
6805 * but try to keep going.
6806 */
6807 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6808 dev_info(&pf->pdev->dev,
6809 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6810 ret);
6811 pf->vsi[pf->lan_vsi]->uplink_seid
6812 = pf->mac_seid;
6813 break;
6814 } else if (pf->veb[v]->uplink_seid == 0) {
6815 dev_info(&pf->pdev->dev,
6816 "rebuild of orphan VEB failed: %d\n",
6817 ret);
6818 }
6819 }
6820 }
6821 }
6822
6823 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6824 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6825 /* no VEB, so rebuild only the Main VSI */
6826 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6827 if (ret) {
6828 dev_info(&pf->pdev->dev,
6829 "rebuild of Main VSI failed: %d\n", ret);
6830 goto end_core_reset;
6831 }
6832 }
6833
4f2f017c
ASJ		 6834 /* Reconfigure hardware for allowing smaller MSS in the case
6835 * of TSO, so that we avoid the MDD being fired and causing
6836 * a reset in the case of small MSS+TSO.
6837 */
6838#define I40E_REG_MSS 0x000E64DC
6839#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6840#define I40E_64BYTE_MSS 0x400000
6841 val = rd32(hw, I40E_REG_MSS);
6842 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6843 val &= ~I40E_REG_MSS_MIN_MASK;
6844 val |= I40E_64BYTE_MSS;
6845 wr32(hw, I40E_REG_MSS, val);
6846 }
6847
025b4a54
ASJ		 6848 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6849 (pf->hw.aq.fw_maj_ver < 4)) {
6850 msleep(75);
6851 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6852 if (ret)
f1c7e72e
SN		 6853 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6854 i40e_stat_str(&pf->hw, ret),
6855 i40e_aq_str(&pf->hw,
6856 pf->hw.aq.asq_last_status));
cafa2ee6 6857 }
41c445ff
JB		 6858 /* reinit the misc interrupt */
6859 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6860 ret = i40e_setup_misc_vector(pf);
6861
e7358f54
ASJ		 6862 /* Add a filter to drop all Flow control frames from any VSI from being
6863 * transmitted. By doing so we stop a malicious VF from sending out
6864 * PAUSE or PFC frames and potentially controlling traffic for other
6865 * PF/VF VSIs.
6866 * The FW can still send Flow control frames if enabled.
6867 */
6868 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6869 pf->main_vsi_seid);
6870
41c445ff
JB		 6871 /* restart the VSIs that were rebuilt and running before the reset */
6872 i40e_pf_unquiesce_all_vsi(pf);
6873
69f64b2b
MW		 6874 if (pf->num_alloc_vfs) {
6875 for (v = 0; v < pf->num_alloc_vfs; v++)
6876 i40e_reset_vf(&pf->vf[v], true);
6877 }
6878
41c445ff 6879 /* tell the firmware that we're starting */
44033fac 6880 i40e_send_version(pf);
41c445ff
JB		 6881
6882end_core_reset:
a316f651
ASJ		 6883 clear_bit(__I40E_RESET_FAILED, &pf->state);
6884clear_recovery:
41c445ff
JB		 6885 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6886}
6887
f650a38b 6888/**
b40c82e6 6889 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6890 * @pf: board private structure
6891 *
6892 * Close up the VFs and other things in prep for a Core Reset,
6893 * then get ready to rebuild the world.
6894 **/
6895static void i40e_handle_reset_warning(struct i40e_pf *pf)
6896{
23cfbe07
SN		 6897 i40e_prep_for_reset(pf);
6898 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6899}
6900
41c445ff
JB		 6901/**
6902 * i40e_handle_mdd_event
b40c82e6 6903 * @pf: pointer to the PF structure
41c445ff
JB		 6904 *
6905 * Called from the MDD irq handler to identify possibly malicious vfs
6906 **/
6907static void i40e_handle_mdd_event(struct i40e_pf *pf)
6908{
6909 struct i40e_hw *hw = &pf->hw;
6910 bool mdd_detected = false;
df430b12 6911 bool pf_mdd_detected = false;
41c445ff
JB		 6912 struct i40e_vf *vf;
6913 u32 reg;
6914 int i;
6915
6916 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6917 return;
6918
6919 /* find what triggered the MDD event */
6920 reg = rd32(hw, I40E_GL_MDET_TX);
6921 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6922 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6923 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6924 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6925 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6926 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6927 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6928 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6929 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6930 pf->hw.func_caps.base_queue;
faf32978 6931 if (netif_msg_tx_err(pf))
b40c82e6 6932 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6933 event, queue, pf_num, vf_num);
41c445ff
JB		 6934 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6935 mdd_detected = true;
6936 }
6937 reg = rd32(hw, I40E_GL_MDET_RX);
6938 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6939 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6940 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6941 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6942 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6943 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6944 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6945 pf->hw.func_caps.base_queue;
faf32978
JB		 6946 if (netif_msg_rx_err(pf))
6947 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6948 event, queue, func);
41c445ff
JB		 6949 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6950 mdd_detected = true;
6951 }
6952
df430b12
NP		 6953 if (mdd_detected) {
6954 reg = rd32(hw, I40E_PF_MDET_TX);
6955 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6956 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6957 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6958 pf_mdd_detected = true;
6959 }
6960 reg = rd32(hw, I40E_PF_MDET_RX);
6961 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6962 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6963 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6964 pf_mdd_detected = true;
6965 }
6966 /* Queue belongs to the PF, initiate a reset */
6967 if (pf_mdd_detected) {
6968 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6969 i40e_service_event_schedule(pf);
6970 }
6971 }
6972
41c445ff
JB		 6973 /* see if one of the VFs needs its hand slapped */
6974 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6975 vf = &(pf->vf[i]);
6976 reg = rd32(hw, I40E_VP_MDET_TX(i));
6977 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6978 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6979 vf->num_mdd_events++;
faf32978
JB		 6980 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6981 i);
41c445ff
JB		 6982 }
6983
6984 reg = rd32(hw, I40E_VP_MDET_RX(i));
6985 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6986 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6987 vf->num_mdd_events++;
faf32978
JB		 6988 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6989 i);
41c445ff
JB		 6990 }
6991
6992 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6993 dev_info(&pf->pdev->dev,
6994 "Too many MDD events on VF %d, disabled\n", i);
6995 dev_info(&pf->pdev->dev,
6996 "Use PF Control I/F to re-enable the VF\n");
6997 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6998 }
6999 }
7000
7001 /* re-enable mdd interrupt cause */
7002 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7003 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7004 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7005 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7006 i40e_flush(hw);
7007}
7008
a1c9a9d9
JK		 7009#ifdef CONFIG_I40E_VXLAN
7010/**
7011 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
7012 * @pf: board private structure
7013 **/
7014static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
7015{
a1c9a9d9
JK		 7016 struct i40e_hw *hw = &pf->hw;
7017 i40e_status ret;
a1c9a9d9
JK		 7018 __be16 port;
7019 int i;
7020
7021 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
7022 return;
7023
7024 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
7025
7026 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 7027 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
7028 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 7029 port = pf->vxlan_ports[i];
c22c06c8
SN		 7030 if (port)
7031 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 7032 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 7033 NULL, NULL);
7034 else
7035 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7036
7037 if (ret) {
c22c06c8 7038 dev_info(&pf->pdev->dev,
f1c7e72e 7039 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7040 port ? "add" : "delete",
f1c7e72e
SN		 7041 ntohs(port), i,
7042 i40e_stat_str(&pf->hw, ret),
7043 i40e_aq_str(&pf->hw,
7044 pf->hw.aq.asq_last_status));
a1c9a9d9 7045 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 7046 }
7047 }
7048 }
7049}
7050
7051#endif
41c445ff
JB		 7052/**
7053 * i40e_service_task - Run the driver's async subtasks
7054 * @work: pointer to work_struct containing our data
7055 **/
7056static void i40e_service_task(struct work_struct *work)
7057{
7058 struct i40e_pf *pf = container_of(work,
7059 struct i40e_pf,
7060 service_task);
7061 unsigned long start_time = jiffies;
7062
e57a2fea
SN		 7063 /* don't bother with service tasks if a reset is in progress */
7064 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7065 i40e_service_event_complete(pf);
7066 return;
7067 }
7068
b03a8c1f 7069 i40e_detect_recover_hung(pf);
41c445ff
JB		 7070 i40e_reset_subtask(pf);
7071 i40e_handle_mdd_event(pf);
7072 i40e_vc_process_vflr_event(pf);
7073 i40e_watchdog_subtask(pf);
7074 i40e_fdir_reinit_subtask(pf);
41c445ff 7075 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 7076#ifdef CONFIG_I40E_VXLAN
7077 i40e_sync_vxlan_filters_subtask(pf);
7078#endif
41c445ff
JB		 7079 i40e_clean_adminq_subtask(pf);
7080
7081 i40e_service_event_complete(pf);
7082
7083 /* If the tasks have taken longer than one timer cycle or there
7084 * is more work to be done, reschedule the service task now
7085 * rather than wait for the timer to tick again.
7086 */
7087 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7088 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7089 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7090 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7091 i40e_service_event_schedule(pf);
7092}
7093
7094/**
7095 * i40e_service_timer - timer callback
7096 * @data: pointer to PF struct
7097 **/
7098static void i40e_service_timer(unsigned long data)
7099{
7100 struct i40e_pf *pf = (struct i40e_pf *)data;
7101
7102 mod_timer(&pf->service_timer,
7103 round_jiffies(jiffies + pf->service_timer_period));
7104 i40e_service_event_schedule(pf);
7105}
7106
7107/**
7108 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7109 * @vsi: the VSI being configured
7110 **/
7111static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7112{
7113 struct i40e_pf *pf = vsi->back;
7114
7115 switch (vsi->type) {
7116 case I40E_VSI_MAIN:
7117 vsi->alloc_queue_pairs = pf->num_lan_qps;
7118 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7119 I40E_REQ_DESCRIPTOR_MULTIPLE);
7120 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7121 vsi->num_q_vectors = pf->num_lan_msix;
7122 else
7123 vsi->num_q_vectors = 1;
7124
7125 break;
7126
7127 case I40E_VSI_FDIR:
7128 vsi->alloc_queue_pairs = 1;
7129 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7130 I40E_REQ_DESCRIPTOR_MULTIPLE);
7131 vsi->num_q_vectors = 1;
7132 break;
7133
7134 case I40E_VSI_VMDQ2:
7135 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7136 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7137 I40E_REQ_DESCRIPTOR_MULTIPLE);
7138 vsi->num_q_vectors = pf->num_vmdq_msix;
7139 break;
7140
7141 case I40E_VSI_SRIOV:
7142 vsi->alloc_queue_pairs = pf->num_vf_qps;
7143 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7144 I40E_REQ_DESCRIPTOR_MULTIPLE);
7145 break;
7146
38e00438
VD		 7147#ifdef I40E_FCOE
7148 case I40E_VSI_FCOE:
7149 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7150 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7151 I40E_REQ_DESCRIPTOR_MULTIPLE);
7152 vsi->num_q_vectors = pf->num_fcoe_msix;
7153 break;
7154
7155#endif /* I40E_FCOE */
41c445ff
JB		 7156 default:
7157 WARN_ON(1);
7158 return -ENODATA;
7159 }
7160
7161 return 0;
7162}
7163
f650a38b
ASJ		 7164/**
7165 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7166 * @type: VSI pointer
bc7d338f 7167 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7168 *
7169 * On error: returns error code (negative)
7170 * On success: returns 0
7171 **/
bc7d338f 7172static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7173{
7174 int size;
7175 int ret = 0;
7176
ac6c5e3d 7177 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7178 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7179 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7180 if (!vsi->tx_rings)
7181 return -ENOMEM;
f650a38b
ASJ		 7182 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7183
bc7d338f
ASJ		 7184 if (alloc_qvectors) {
7185 /* allocate memory for q_vector pointers */
f57e4fbd 7186 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7187 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7188 if (!vsi->q_vectors) {
7189 ret = -ENOMEM;
7190 goto err_vectors;
7191 }
f650a38b
ASJ		 7192 }
7193 return ret;
7194
7195err_vectors:
7196 kfree(vsi->tx_rings);
7197 return ret;
7198}
7199
41c445ff
JB		 7200/**
7201 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7202 * @pf: board private structure
7203 * @type: type of VSI
7204 *
7205 * On error: returns error code (negative)
7206 * On success: returns vsi index in PF (positive)
7207 **/
7208static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7209{
7210 int ret = -ENODEV;
7211 struct i40e_vsi *vsi;
7212 int vsi_idx;
7213 int i;
7214
7215 /* Need to protect the allocation of the VSIs at the PF level */
7216 mutex_lock(&pf->switch_mutex);
7217
7218 /* VSI list may be fragmented if VSI creation/destruction has
7219 * been happening. We can afford to do a quick scan to look
7220 * for any free VSIs in the list.
7221 *
7222 * find next empty vsi slot, looping back around if necessary
7223 */
7224 i = pf->next_vsi;
505682cd 7225 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7226 i++;
505682cd 7227 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7228 i = 0;
7229 while (i < pf->next_vsi && pf->vsi[i])
7230 i++;
7231 }
7232
505682cd 7233 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7234 vsi_idx = i; /* Found one! */
7235 } else {
7236 ret = -ENODEV;
493fb300 7237 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7238 }
7239 pf->next_vsi = ++i;
7240
7241 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7242 if (!vsi) {
7243 ret = -ENOMEM;
493fb300 7244 goto unlock_pf;
41c445ff
JB		 7245 }
7246 vsi->type = type;
7247 vsi->back = pf;
7248 set_bit(__I40E_DOWN, &vsi->state);
7249 vsi->flags = 0;
7250 vsi->idx = vsi_idx;
7251 vsi->rx_itr_setting = pf->rx_itr_default;
7252 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7253 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7254 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7255 pf->rss_table_size : 64;
41c445ff
JB		 7256 vsi->netdev_registered = false;
7257 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7258 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7259 vsi->irqs_ready = false;
41c445ff 7260
9f65e15b
AD		 7261 ret = i40e_set_num_rings_in_vsi(vsi);
7262 if (ret)
7263 goto err_rings;
7264
bc7d338f 7265 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7266 if (ret)
9f65e15b 7267 goto err_rings;
493fb300 7268
41c445ff
JB		 7269 /* Setup default MSIX irq handler for VSI */
7270 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7271
21659035
KP		 7272 /* Initialize VSI lock */
7273 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7274 pf->vsi[vsi_idx] = vsi;
7275 ret = vsi_idx;
493fb300
AD		 7276 goto unlock_pf;
7277
9f65e15b 7278err_rings:
493fb300
AD		 7279 pf->next_vsi = i - 1;
7280 kfree(vsi);
7281unlock_pf:
41c445ff
JB		 7282 mutex_unlock(&pf->switch_mutex);
7283 return ret;
7284}
7285
f650a38b
ASJ		 7286/**
7287 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7288 * @type: VSI pointer
bc7d338f 7289 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7290 *
7291 * On error: returns error code (negative)
7292 * On success: returns 0
7293 **/
bc7d338f 7294static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7295{
7296 /* free the ring and vector containers */
bc7d338f
ASJ		 7297 if (free_qvectors) {
7298 kfree(vsi->q_vectors);
7299 vsi->q_vectors = NULL;
7300 }
f650a38b
ASJ		 7301 kfree(vsi->tx_rings);
7302 vsi->tx_rings = NULL;
7303 vsi->rx_rings = NULL;
7304}
7305
28c5869f
HZ		 7306/**
7307 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7308 * and lookup table
7309 * @vsi: Pointer to VSI structure
7310 */
7311static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7312{
7313 if (!vsi)
7314 return;
7315
7316 kfree(vsi->rss_hkey_user);
7317 vsi->rss_hkey_user = NULL;
7318
7319 kfree(vsi->rss_lut_user);
7320 vsi->rss_lut_user = NULL;
7321}
7322
41c445ff
JB		 7323/**
7324 * i40e_vsi_clear - Deallocate the VSI provided
7325 * @vsi: the VSI being un-configured
7326 **/
7327static int i40e_vsi_clear(struct i40e_vsi *vsi)
7328{
7329 struct i40e_pf *pf;
7330
7331 if (!vsi)
7332 return 0;
7333
7334 if (!vsi->back)
7335 goto free_vsi;
7336 pf = vsi->back;
7337
7338 mutex_lock(&pf->switch_mutex);
7339 if (!pf->vsi[vsi->idx]) {
7340 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7341 vsi->idx, vsi->idx, vsi, vsi->type);
7342 goto unlock_vsi;
7343 }
7344
7345 if (pf->vsi[vsi->idx] != vsi) {
7346 dev_err(&pf->pdev->dev,
7347 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7348 pf->vsi[vsi->idx]->idx,
7349 pf->vsi[vsi->idx],
7350 pf->vsi[vsi->idx]->type,
7351 vsi->idx, vsi, vsi->type);
7352 goto unlock_vsi;
7353 }
7354
b40c82e6 7355 /* updates the PF for this cleared vsi */
41c445ff
JB		 7356 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7357 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7358
bc7d338f 7359 i40e_vsi_free_arrays(vsi, true);
28c5869f 7360 i40e_clear_rss_config_user(vsi);
493fb300 7361
41c445ff
JB		 7362 pf->vsi[vsi->idx] = NULL;
7363 if (vsi->idx < pf->next_vsi)
7364 pf->next_vsi = vsi->idx;
7365
7366unlock_vsi:
7367 mutex_unlock(&pf->switch_mutex);
7368free_vsi:
7369 kfree(vsi);
7370
7371 return 0;
7372}
7373
9f65e15b
AD		 7374/**
7375 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7376 * @vsi: the VSI being cleaned
7377 **/
be1d5eea 7378static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7379{
7380 int i;
7381
8e9dca53 7382 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7383 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7384 kfree_rcu(vsi->tx_rings[i], rcu);
7385 vsi->tx_rings[i] = NULL;
7386 vsi->rx_rings[i] = NULL;
7387 }
be1d5eea 7388 }
9f65e15b
AD		 7389}
7390
41c445ff
JB		 7391/**
7392 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7393 * @vsi: the VSI being configured
7394 **/
7395static int i40e_alloc_rings(struct i40e_vsi *vsi)
7396{
e7046ee1 7397 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7398 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7399 int i;
7400
41c445ff 7401 /* Set basic values in the rings to be used later during open() */
d7397644 7402 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7403 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7404 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7405 if (!tx_ring)
7406 goto err_out;
41c445ff
JB		 7407
7408 tx_ring->queue_index = i;
7409 tx_ring->reg_idx = vsi->base_queue + i;
7410 tx_ring->ring_active = false;
7411 tx_ring->vsi = vsi;
7412 tx_ring->netdev = vsi->netdev;
7413 tx_ring->dev = &pf->pdev->dev;
7414 tx_ring->count = vsi->num_desc;
7415 tx_ring->size = 0;
7416 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7417 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7418 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7419 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7420 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7421 vsi->tx_rings[i] = tx_ring;
41c445ff 7422
9f65e15b 7423 rx_ring = &tx_ring[1];
41c445ff
JB		 7424 rx_ring->queue_index = i;
7425 rx_ring->reg_idx = vsi->base_queue + i;
7426 rx_ring->ring_active = false;
7427 rx_ring->vsi = vsi;
7428 rx_ring->netdev = vsi->netdev;
7429 rx_ring->dev = &pf->pdev->dev;
7430 rx_ring->count = vsi->num_desc;
7431 rx_ring->size = 0;
7432 rx_ring->dcb_tc = 0;
7433 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7434 set_ring_16byte_desc_enabled(rx_ring);
7435 else
7436 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7437 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7438 }
7439
7440 return 0;
9f65e15b
AD		 7441
7442err_out:
7443 i40e_vsi_clear_rings(vsi);
7444 return -ENOMEM;
41c445ff
JB		 7445}
7446
7447/**
7448 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7449 * @pf: board private structure
7450 * @vectors: the number of MSI-X vectors to request
7451 *
7452 * Returns the number of vectors reserved, or error
7453 **/
7454static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7455{
7b37f376
AG		 7456 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7457 I40E_MIN_MSIX, vectors);
7458 if (vectors < 0) {
41c445ff 7459 dev_info(&pf->pdev->dev,
7b37f376 7460 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7461 vectors = 0;
7462 }
7463
7464 return vectors;
7465}
7466
7467/**
7468 * i40e_init_msix - Setup the MSIX capability
7469 * @pf: board private structure
7470 *
7471 * Work with the OS to set up the MSIX vectors needed.
7472 *
3b444399 7473 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7474 **/
7475static int i40e_init_msix(struct i40e_pf *pf)
7476{
41c445ff 7477 struct i40e_hw *hw = &pf->hw;
1e200e4a 7478 int vectors_left;
41c445ff 7479 int v_budget, i;
3b444399 7480 int v_actual;
41c445ff
JB		 7481
7482 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7483 return -ENODEV;
7484
7485 /* The number of vectors we'll request will be comprised of:
7486 * - Add 1 for "other" cause for Admin Queue events, etc.
7487 * - The number of LAN queue pairs
f8ff1464
ASJ		 7488 * - Queues being used for RSS.
7489 * We don't need as many as max_rss_size vectors.
7490 * use rss_size instead in the calculation since that
7491 * is governed by number of cpus in the system.
7492 * - assumes symmetric Tx/Rx pairing
41c445ff 7493 * - The number of VMDq pairs
38e00438
VD		 7494#ifdef I40E_FCOE
7495 * - The number of FCOE qps.
7496#endif
41c445ff
JB		 7497 * Once we count this up, try the request.
7498 *
7499 * If we can't get what we want, we'll simplify to nearly nothing
7500 * and try again. If that still fails, we punt.
7501 */
1e200e4a
SN		 7502 vectors_left = hw->func_caps.num_msix_vectors;
7503 v_budget = 0;
7504
7505 /* reserve one vector for miscellaneous handler */
7506 if (vectors_left) {
7507 v_budget++;
7508 vectors_left--;
7509 }
7510
7511 /* reserve vectors for the main PF traffic queues */
7512 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7513 vectors_left -= pf->num_lan_msix;
7514 v_budget += pf->num_lan_msix;
7515
7516 /* reserve one vector for sideband flow director */
7517 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7518 if (vectors_left) {
7519 v_budget++;
7520 vectors_left--;
7521 } else {
7522 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7523 }
7524 }
83840e4b 7525
38e00438 7526#ifdef I40E_FCOE
1e200e4a 7527 /* can we reserve enough for FCoE? */
38e00438 7528 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7529 if (!vectors_left)
7530 pf->num_fcoe_msix = 0;
7531 else if (vectors_left >= pf->num_fcoe_qps)
7532 pf->num_fcoe_msix = pf->num_fcoe_qps;
7533 else
7534 pf->num_fcoe_msix = 1;
38e00438 7535 v_budget += pf->num_fcoe_msix;
1e200e4a 7536 vectors_left -= pf->num_fcoe_msix;
38e00438 7537 }
1e200e4a 7538
38e00438 7539#endif
1e200e4a
SN		 7540 /* any vectors left over go for VMDq support */
7541 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7542 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7543 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7544
7545 /* if we're short on vectors for what's desired, we limit
7546 * the queues per vmdq. If this is still more than are
7547 * available, the user will need to change the number of
7548 * queues/vectors used by the PF later with the ethtool
7549 * channels command
7550 */
7551 if (vmdq_vecs < vmdq_vecs_wanted)
7552 pf->num_vmdq_qps = 1;
7553 pf->num_vmdq_msix = pf->num_vmdq_qps;
7554
7555 v_budget += vmdq_vecs;
7556 vectors_left -= vmdq_vecs;
7557 }
41c445ff
JB		 7558
7559 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7560 GFP_KERNEL);
7561 if (!pf->msix_entries)
7562 return -ENOMEM;
7563
7564 for (i = 0; i < v_budget; i++)
7565 pf->msix_entries[i].entry = i;
3b444399 7566 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7567
3b444399 7568 if (v_actual != v_budget) {
a34977ba
ASJ		 7569 /* If we have limited resources, we will start with no vectors
7570 * for the special features and then allocate vectors to some
7571 * of these features based on the policy and at the end disable
7572 * the features that did not get any vectors.
7573 */
38e00438
VD		 7574#ifdef I40E_FCOE
7575 pf->num_fcoe_qps = 0;
7576 pf->num_fcoe_msix = 0;
7577#endif
a34977ba
ASJ		 7578 pf->num_vmdq_msix = 0;
7579 }
7580
3b444399 7581 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7582 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7583 kfree(pf->msix_entries);
7584 pf->msix_entries = NULL;
7585 return -ENODEV;
7586
3b444399 7587 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7588 /* Adjust for minimal MSIX use */
41c445ff
JB		 7589 pf->num_vmdq_vsis = 0;
7590 pf->num_vmdq_qps = 0;
41c445ff
JB		 7591 pf->num_lan_qps = 1;
7592 pf->num_lan_msix = 1;
7593
3b444399
SN		 7594 } else if (v_actual != v_budget) {
7595 int vec;
7596
a34977ba 7597 /* reserve the misc vector */
3b444399 7598 vec = v_actual - 1;
a34977ba 7599
41c445ff
JB		 7600 /* Scale vector usage down */
7601 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7602 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7603 pf->num_vmdq_qps = 1;
7604 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7605
7606 /* partition out the remaining vectors */
7607 switch (vec) {
7608 case 2:
41c445ff
JB		 7609 pf->num_lan_msix = 1;
7610 break;
7611 case 3:
38e00438
VD		 7612#ifdef I40E_FCOE
7613 /* give one vector to FCoE */
7614 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7615 pf->num_lan_msix = 1;
7616 pf->num_fcoe_msix = 1;
7617 }
7618#else
41c445ff 7619 pf->num_lan_msix = 2;
38e00438 7620#endif
41c445ff
JB		 7621 break;
7622 default:
38e00438
VD		 7623#ifdef I40E_FCOE
7624 /* give one vector to FCoE */
7625 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7626 pf->num_fcoe_msix = 1;
7627 vec--;
7628 }
7629#endif
1e200e4a
SN		 7630 /* give the rest to the PF */
7631 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7632 break;
7633 }
7634 }
7635
a34977ba
ASJ		 7636 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7637 (pf->num_vmdq_msix == 0)) {
7638 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7639 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7640 }
38e00438
VD		 7641#ifdef I40E_FCOE
7642
7643 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7644 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7645 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7646 }
7647#endif
3b444399 7648 return v_actual;
41c445ff
JB		 7649}
7650
493fb300 7651/**
90e04070 7652 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7653 * @vsi: the VSI being configured
7654 * @v_idx: index of the vector in the vsi struct
7655 *
7656 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7657 **/
90e04070 7658static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7659{
7660 struct i40e_q_vector *q_vector;
7661
7662 /* allocate q_vector */
7663 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7664 if (!q_vector)
7665 return -ENOMEM;
7666
7667 q_vector->vsi = vsi;
7668 q_vector->v_idx = v_idx;
7669 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7670 if (vsi->netdev)
7671 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7672 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7673
cd0b6fa6
AD		 7674 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7675 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7676
493fb300
AD		 7677 /* tie q_vector and vsi together */
7678 vsi->q_vectors[v_idx] = q_vector;
7679
7680 return 0;
7681}
7682
41c445ff 7683/**
90e04070 7684 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7685 * @vsi: the VSI being configured
7686 *
7687 * We allocate one q_vector per queue interrupt. If allocation fails we
7688 * return -ENOMEM.
7689 **/
90e04070 7690static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7691{
7692 struct i40e_pf *pf = vsi->back;
7693 int v_idx, num_q_vectors;
493fb300 7694 int err;
41c445ff
JB		 7695
7696 /* if not MSIX, give the one vector only to the LAN VSI */
7697 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7698 num_q_vectors = vsi->num_q_vectors;
7699 else if (vsi == pf->vsi[pf->lan_vsi])
7700 num_q_vectors = 1;
7701 else
7702 return -EINVAL;
7703
41c445ff 7704 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7705 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7706 if (err)
7707 goto err_out;
41c445ff
JB		 7708 }
7709
7710 return 0;
493fb300
AD		 7711
7712err_out:
7713 while (v_idx--)
7714 i40e_free_q_vector(vsi, v_idx);
7715
7716 return err;
41c445ff
JB		 7717}
7718
7719/**
7720 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7721 * @pf: board private structure to initialize
7722 **/
c1147280 7723static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7724{
3b444399
SN		 7725 int vectors = 0;
7726 ssize_t size;
41c445ff
JB		 7727
7728 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7729 vectors = i40e_init_msix(pf);
7730 if (vectors < 0) {
60ea5f83 7731 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7732#ifdef I40E_FCOE
7733 I40E_FLAG_FCOE_ENABLED |
7734#endif
60ea5f83 7735 I40E_FLAG_RSS_ENABLED |
4d9b6043 7736 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7737 I40E_FLAG_SRIOV_ENABLED |
7738 I40E_FLAG_FD_SB_ENABLED |
7739 I40E_FLAG_FD_ATR_ENABLED |
7740 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7741
7742 /* rework the queue expectations without MSIX */
7743 i40e_determine_queue_usage(pf);
7744 }
7745 }
7746
7747 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7748 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7749 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7750 vectors = pci_enable_msi(pf->pdev);
7751 if (vectors < 0) {
7752 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7753 vectors);
41c445ff
JB		 7754 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7755 }
3b444399 7756 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7757 }
7758
958a3e3b 7759 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7760 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7761
3b444399
SN		 7762 /* set up vector assignment tracking */
7763 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7764 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7765 if (!pf->irq_pile) {
7766 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7767 return -ENOMEM;
7768 }
3b444399
SN		 7769 pf->irq_pile->num_entries = vectors;
7770 pf->irq_pile->search_hint = 0;
7771
c1147280 7772 /* track first vector for misc interrupts, ignore return */
3b444399 7773 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7774
7775 return 0;
41c445ff
JB		 7776}
7777
7778/**
7779 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7780 * @pf: board private structure
7781 *
7782 * This sets up the handler for MSIX 0, which is used to manage the
7783 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7784 * when in MSI or Legacy interrupt mode.
7785 **/
7786static int i40e_setup_misc_vector(struct i40e_pf *pf)
7787{
7788 struct i40e_hw *hw = &pf->hw;
7789 int err = 0;
7790
7791 /* Only request the irq if this is the first time through, and
7792 * not when we're rebuilding after a Reset
7793 */
7794 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7795 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7796 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7797 if (err) {
7798 dev_info(&pf->pdev->dev,
77fa28be 7799 "request_irq for %s failed: %d\n",
b294ac70 7800 pf->int_name, err);
41c445ff
JB		 7801 return -EFAULT;
7802 }
7803 }
7804
ab437b5a 7805 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7806
7807 /* associate no queues to the misc vector */
7808 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7809 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7810
7811 i40e_flush(hw);
7812
7813 i40e_irq_dynamic_enable_icr0(pf);
7814
7815 return err;
7816}
7817
7818/**
e25d00b8
ASJ		 7819 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7820 * @vsi: vsi structure
7821 * @seed: RSS hash seed
7822 **/
e69ff813
HZ		 7823static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7824 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7825{
7826 struct i40e_aqc_get_set_rss_key_data rss_key;
7827 struct i40e_pf *pf = vsi->back;
7828 struct i40e_hw *hw = &pf->hw;
7829 bool pf_lut = false;
7830 u8 *rss_lut;
7831 int ret, i;
7832
7833 memset(&rss_key, 0, sizeof(rss_key));
7834 memcpy(&rss_key, seed, sizeof(rss_key));
7835
7836 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7837 if (!rss_lut)
7838 return -ENOMEM;
7839
7840 /* Populate the LUT with max no. of queues in round robin fashion */
7841 for (i = 0; i < vsi->rss_table_size; i++)
7842 rss_lut[i] = i % vsi->rss_size;
7843
7844 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7845 if (ret) {
7846 dev_info(&pf->pdev->dev,
7847 "Cannot set RSS key, err %s aq_err %s\n",
7848 i40e_stat_str(&pf->hw, ret),
7849 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7850 goto config_rss_aq_out;
e25d00b8
ASJ		 7851 }
7852
7853 if (vsi->type == I40E_VSI_MAIN)
7854 pf_lut = true;
7855
7856 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7857 vsi->rss_table_size);
7858 if (ret)
7859 dev_info(&pf->pdev->dev,
7860 "Cannot set RSS lut, err %s aq_err %s\n",
7861 i40e_stat_str(&pf->hw, ret),
7862 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7863
126b63d9
AS		 7864config_rss_aq_out:
7865 kfree(rss_lut);
e25d00b8
ASJ		 7866 return ret;
7867}
7868
7869/**
7870 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7871 * @vsi: VSI structure
7872 **/
7873static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7874{
7875 u8 seed[I40E_HKEY_ARRAY_SIZE];
7876 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7877 u8 *lut;
7878 int ret;
7879
7880 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7881 return 0;
7882
7883 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7884 if (!lut)
7885 return -ENOMEM;
e25d00b8 7886
e69ff813 7887 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7888 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7889 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7890 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7891 kfree(lut);
e25d00b8 7892
e69ff813 7893 return ret;
e25d00b8
ASJ		 7894}
7895
7896/**
043dd650 7897 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7898 * @vsi: Pointer to vsi structure
e25d00b8 7899 * @seed: RSS hash seed
e69ff813
HZ		 7900 * @lut: Lookup table
7901 * @lut_size: Lookup table size
7902 *
7903 * Returns 0 on success, negative on failure
41c445ff 7904 **/
e69ff813
HZ		 7905static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
7906 const u8 *lut, u16 lut_size)
41c445ff 7907{
e69ff813 7908 struct i40e_pf *pf = vsi->back;
4617e8c0 7909 struct i40e_hw *hw = &pf->hw;
e69ff813 7910 u8 i;
41c445ff 7911
e25d00b8 7912 /* Fill out hash function seed */
e69ff813
HZ		 7913 if (seed) {
7914 u32 *seed_dw = (u32 *)seed;
7915
7916 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7917 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7918 }
7919
7920 if (lut) {
7921 u32 *lut_dw = (u32 *)lut;
7922
7923 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7924 return -EINVAL;
7925
7926 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7927 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 7928 }
7929 i40e_flush(hw);
7930
7931 return 0;
7932}
7933
043dd650
HZ		 7934/**
7935 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
7936 * @vsi: Pointer to VSI structure
7937 * @seed: Buffer to store the keys
7938 * @lut: Buffer to store the lookup table entries
7939 * @lut_size: Size of buffer to store the lookup table entries
7940 *
7941 * Returns 0 on success, negative on failure
7942 */
7943static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
7944 u8 *lut, u16 lut_size)
7945{
7946 struct i40e_pf *pf = vsi->back;
7947 struct i40e_hw *hw = &pf->hw;
7948 u16 i;
7949
7950 if (seed) {
7951 u32 *seed_dw = (u32 *)seed;
7952
7953 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7954 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
7955 }
7956 if (lut) {
7957 u32 *lut_dw = (u32 *)lut;
7958
7959 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7960 return -EINVAL;
7961 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7962 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
7963 }
7964
7965 return 0;
7966}
7967
7968/**
7969 * i40e_config_rss - Configure RSS keys and lut
7970 * @vsi: Pointer to VSI structure
7971 * @seed: RSS hash seed
7972 * @lut: Lookup table
7973 * @lut_size: Lookup table size
7974 *
7975 * Returns 0 on success, negative on failure
7976 */
7977int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
7978{
7979 struct i40e_pf *pf = vsi->back;
7980
7981 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7982 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
7983 else
7984 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
7985}
7986
7987/**
7988 * i40e_get_rss - Get RSS keys and lut
7989 * @vsi: Pointer to VSI structure
7990 * @seed: Buffer to store the keys
7991 * @lut: Buffer to store the lookup table entries
7992 * lut_size: Size of buffer to store the lookup table entries
7993 *
7994 * Returns 0 on success, negative on failure
7995 */
7996int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
7997{
7998 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
7999}
8000
e69ff813
HZ		 8001/**
8002 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8003 * @pf: Pointer to board private structure
8004 * @lut: Lookup table
8005 * @rss_table_size: Lookup table size
8006 * @rss_size: Range of queue number for hashing
8007 */
8008static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8009 u16 rss_table_size, u16 rss_size)
8010{
8011 u16 i;
8012
8013 for (i = 0; i < rss_table_size; i++)
8014 lut[i] = i % rss_size;
8015}
8016
e25d00b8 8017/**
043dd650 8018 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8019 * @pf: board private structure
8020 **/
043dd650 8021static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8022{
8023 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8024 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8025 u8 *lut;
e25d00b8
ASJ		 8026 struct i40e_hw *hw = &pf->hw;
8027 u32 reg_val;
8028 u64 hena;
e69ff813 8029 int ret;
e25d00b8 8030
41c445ff
JB		 8031 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8032 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8033 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8034 hena |= i40e_pf_get_default_rss_hena(pf);
8035
41c445ff
JB		 8036 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8037 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8038
e25d00b8 8039 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8040 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8041 reg_val = (pf->rss_table_size == 512) ?
8042 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8043 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8044 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8045
28c5869f
HZ		 8046 /* Determine the RSS size of the VSI */
8047 if (!vsi->rss_size)
acd65448
HZ		 8048 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8049 vsi->num_queue_pairs);
28c5869f 8050
e69ff813
HZ		 8051 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8052 if (!lut)
8053 return -ENOMEM;
8054
28c5869f
HZ		 8055 /* Use user configured lut if there is one, otherwise use default */
8056 if (vsi->rss_lut_user)
8057 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8058 else
8059 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8060
28c5869f
HZ		 8061 /* Use user configured hash key if there is one, otherwise
8062 * use default.
8063 */
8064 if (vsi->rss_hkey_user)
8065 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8066 else
8067 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8068 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8069 kfree(lut);
8070
8071 return ret;
41c445ff
JB		 8072}
8073
f8ff1464
ASJ		 8074/**
8075 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8076 * @pf: board private structure
8077 * @queue_count: the requested queue count for rss.
8078 *
8079 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8080 * count which may be different from the requested queue count.
8081 **/
8082int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8083{
9a3bd2f1
ASJ		 8084 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8085 int new_rss_size;
8086
f8ff1464
ASJ		 8087 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8088 return 0;
8089
9a3bd2f1 8090 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8091
9a3bd2f1
ASJ		 8092 if (queue_count != vsi->num_queue_pairs) {
8093 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8094 i40e_prep_for_reset(pf);
8095
acd65448 8096 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8097
8098 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8099
8100 /* Discard the user configured hash keys and lut, if less
8101 * queues are enabled.
8102 */
8103 if (queue_count < vsi->rss_size) {
8104 i40e_clear_rss_config_user(vsi);
8105 dev_dbg(&pf->pdev->dev,
8106 "discard user configured hash keys and lut\n");
8107 }
8108
8109 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8110 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8111 vsi->num_queue_pairs);
28c5869f 8112
043dd650 8113 i40e_pf_config_rss(pf);
f8ff1464 8114 }
e36b0b11
HZ		 8115 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8116 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8117 return pf->alloc_rss_size;
f8ff1464
ASJ		 8118}
8119
f4492db1
GR		 8120/**
8121 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8122 * @pf: board private structure
8123 **/
8124i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8125{
8126 i40e_status status;
8127 bool min_valid, max_valid;
8128 u32 max_bw, min_bw;
8129
8130 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8131 &min_valid, &max_valid);
8132
8133 if (!status) {
8134 if (min_valid)
8135 pf->npar_min_bw = min_bw;
8136 if (max_valid)
8137 pf->npar_max_bw = max_bw;
8138 }
8139
8140 return status;
8141}
8142
8143/**
8144 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8145 * @pf: board private structure
8146 **/
8147i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8148{
8149 struct i40e_aqc_configure_partition_bw_data bw_data;
8150 i40e_status status;
8151
b40c82e6 8152 /* Set the valid bit for this PF */
41a1d04b 8153 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8154 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8155 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8156
8157 /* Set the new bandwidths */
8158 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8159
8160 return status;
8161}
8162
8163/**
8164 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8165 * @pf: board private structure
8166 **/
8167i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8168{
8169 /* Commit temporary BW setting to permanent NVM image */
8170 enum i40e_admin_queue_err last_aq_status;
8171 i40e_status ret;
8172 u16 nvm_word;
8173
8174 if (pf->hw.partition_id != 1) {
8175 dev_info(&pf->pdev->dev,
8176 "Commit BW only works on partition 1! This is partition %d",
8177 pf->hw.partition_id);
8178 ret = I40E_NOT_SUPPORTED;
8179 goto bw_commit_out;
8180 }
8181
8182 /* Acquire NVM for read access */
8183 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8184 last_aq_status = pf->hw.aq.asq_last_status;
8185 if (ret) {
8186 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8187 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8188 i40e_stat_str(&pf->hw, ret),
8189 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8190 goto bw_commit_out;
8191 }
8192
8193 /* Read word 0x10 of NVM - SW compatibility word 1 */
8194 ret = i40e_aq_read_nvm(&pf->hw,
8195 I40E_SR_NVM_CONTROL_WORD,
8196 0x10, sizeof(nvm_word), &nvm_word,
8197 false, NULL);
8198 /* Save off last admin queue command status before releasing
8199 * the NVM
8200 */
8201 last_aq_status = pf->hw.aq.asq_last_status;
8202 i40e_release_nvm(&pf->hw);
8203 if (ret) {
f1c7e72e
SN		 8204 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8205 i40e_stat_str(&pf->hw, ret),
8206 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8207 goto bw_commit_out;
8208 }
8209
8210 /* Wait a bit for NVM release to complete */
8211 msleep(50);
8212
8213 /* Acquire NVM for write access */
8214 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8215 last_aq_status = pf->hw.aq.asq_last_status;
8216 if (ret) {
8217 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8218 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8219 i40e_stat_str(&pf->hw, ret),
8220 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8221 goto bw_commit_out;
8222 }
8223 /* Write it back out unchanged to initiate update NVM,
8224 * which will force a write of the shadow (alt) RAM to
8225 * the NVM - thus storing the bandwidth values permanently.
8226 */
8227 ret = i40e_aq_update_nvm(&pf->hw,
8228 I40E_SR_NVM_CONTROL_WORD,
8229 0x10, sizeof(nvm_word),
8230 &nvm_word, true, NULL);
8231 /* Save off last admin queue command status before releasing
8232 * the NVM
8233 */
8234 last_aq_status = pf->hw.aq.asq_last_status;
8235 i40e_release_nvm(&pf->hw);
8236 if (ret)
8237 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8238 "BW settings NOT SAVED, err %s aq_err %s\n",
8239 i40e_stat_str(&pf->hw, ret),
8240 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8241bw_commit_out:
8242
8243 return ret;
8244}
8245
41c445ff
JB		 8246/**
8247 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8248 * @pf: board private structure to initialize
8249 *
8250 * i40e_sw_init initializes the Adapter private data structure.
8251 * Fields are initialized based on PCI device information and
8252 * OS network device settings (MTU size).
8253 **/
8254static int i40e_sw_init(struct i40e_pf *pf)
8255{
8256 int err = 0;
8257 int size;
8258
8259 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8260 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8261 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8262 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8263 if (I40E_DEBUG_USER & debug)
8264 pf->hw.debug_mask = debug;
8265 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8266 I40E_DEFAULT_MSG_ENABLE);
8267 }
8268
8269 /* Set default capability flags */
8270 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8271 I40E_FLAG_MSI_ENABLED |
9ac77266 8272 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8273 I40E_FLAG_MSIX_ENABLED;
8274
8275 if (iommu_present(&pci_bus_type))
8276 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8277 else
8278 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8279
ca99eb99
MW		 8280 /* Set default ITR */
8281 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8282 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8283
7134f9ce
JB		 8284 /* Depending on PF configurations, it is possible that the RSS
8285 * maximum might end up larger than the available queues
8286 */
41a1d04b 8287 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8288 pf->alloc_rss_size = 1;
5db4cb59 8289 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8290 pf->rss_size_max = min_t(int, pf->rss_size_max,
8291 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8292 if (pf->hw.func_caps.rss) {
8293 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8294 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8295 num_online_cpus());
41c445ff
JB		 8296 }
8297
2050bc65 8298 /* MFP mode enabled */
c78b953e 8299 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8300 pf->flags |= I40E_FLAG_MFP_ENABLED;
8301 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8302 if (i40e_get_npar_bw_setting(pf))
8303 dev_warn(&pf->pdev->dev,
8304 "Could not get NPAR bw settings\n");
8305 else
8306 dev_info(&pf->pdev->dev,
8307 "Min BW = %8.8x, Max BW = %8.8x\n",
8308 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8309 }
8310
cbf61325
ASJ		 8311 /* FW/NVM is not yet fixed in this regard */
8312 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8313 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8314 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8315 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8316 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8317 pf->hw.num_partitions > 1)
cbf61325 8318 dev_info(&pf->pdev->dev,
0b67584f 8319 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8320 else
8321 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8322 pf->fdir_pf_filter_count =
8323 pf->hw.func_caps.fd_filters_guaranteed;
8324 pf->hw.fdir_shared_filter_count =
8325 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8326 }
8327
8328 if (pf->hw.func_caps.vmdq) {
41c445ff 8329 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8330 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8331 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8332 }
8333
38e00438 8334#ifdef I40E_FCOE
21364bcf 8335 i40e_init_pf_fcoe(pf);
38e00438
VD		 8336
8337#endif /* I40E_FCOE */
41c445ff 8338#ifdef CONFIG_PCI_IOV
ba252f13 8339 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8340 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8341 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8342 pf->num_req_vfs = min_t(int,
8343 pf->hw.func_caps.num_vfs,
8344 I40E_MAX_VF_COUNT);
8345 }
8346#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8347 if (pf->hw.mac.type == I40E_MAC_X722) {
8348 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8349 I40E_FLAG_128_QP_RSS_CAPABLE |
8350 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8351 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8352 I40E_FLAG_WB_ON_ITR_CAPABLE |
8353 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
8354 }
41c445ff
JB		 8355 pf->eeprom_version = 0xDEAD;
8356 pf->lan_veb = I40E_NO_VEB;
8357 pf->lan_vsi = I40E_NO_VSI;
8358
d1a8d275
ASJ		 8359 /* By default FW has this off for performance reasons */
8360 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8361
41c445ff
JB		 8362 /* set up queue assignment tracking */
8363 size = sizeof(struct i40e_lump_tracking)
8364 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8365 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8366 if (!pf->qp_pile) {
8367 err = -ENOMEM;
8368 goto sw_init_done;
8369 }
8370 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8371 pf->qp_pile->search_hint = 0;
8372
327fe04b
ASJ		 8373 pf->tx_timeout_recovery_level = 1;
8374
41c445ff
JB		 8375 mutex_init(&pf->switch_mutex);
8376
c668a12c
GR		 8377 /* If NPAR is enabled nudge the Tx scheduler */
8378 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8379 i40e_set_npar_bw_setting(pf);
8380
41c445ff
JB		 8381sw_init_done:
8382 return err;
8383}
8384
7c3c288b
ASJ		 8385/**
8386 * i40e_set_ntuple - set the ntuple feature flag and take action
8387 * @pf: board private structure to initialize
8388 * @features: the feature set that the stack is suggesting
8389 *
8390 * returns a bool to indicate if reset needs to happen
8391 **/
8392bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8393{
8394 bool need_reset = false;
8395
8396 /* Check if Flow Director n-tuple support was enabled or disabled. If
8397 * the state changed, we need to reset.
8398 */
8399 if (features & NETIF_F_NTUPLE) {
8400 /* Enable filters and mark for reset */
8401 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8402 need_reset = true;
8403 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8404 } else {
8405 /* turn off filters, mark for reset and clear SW filter list */
8406 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8407 need_reset = true;
8408 i40e_fdir_filter_exit(pf);
8409 }
8410 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8411 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8412 /* reset fd counters */
8413 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8414 pf->fdir_pf_active_filters = 0;
8415 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8416 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8417 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8418 /* if ATR was auto disabled it can be re-enabled. */
8419 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8420 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8421 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8422 }
8423 return need_reset;
8424}
8425
41c445ff
JB		 8426/**
8427 * i40e_set_features - set the netdev feature flags
8428 * @netdev: ptr to the netdev being adjusted
8429 * @features: the feature set that the stack is suggesting
8430 **/
8431static int i40e_set_features(struct net_device *netdev,
8432 netdev_features_t features)
8433{
8434 struct i40e_netdev_priv *np = netdev_priv(netdev);
8435 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8436 struct i40e_pf *pf = vsi->back;
8437 bool need_reset;
41c445ff
JB		 8438
8439 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8440 i40e_vlan_stripping_enable(vsi);
8441 else
8442 i40e_vlan_stripping_disable(vsi);
8443
7c3c288b
ASJ		 8444 need_reset = i40e_set_ntuple(pf, features);
8445
8446 if (need_reset)
41a1d04b 8447 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8448
41c445ff
JB		 8449 return 0;
8450}
8451
a1c9a9d9
JK		 8452#ifdef CONFIG_I40E_VXLAN
8453/**
8454 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8455 * @pf: board private structure
8456 * @port: The UDP port to look up
8457 *
8458 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8459 **/
8460static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8461{
8462 u8 i;
8463
8464 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8465 if (pf->vxlan_ports[i] == port)
8466 return i;
8467 }
8468
8469 return i;
8470}
8471
8472/**
8473 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8474 * @netdev: This physical port's netdev
8475 * @sa_family: Socket Family that VXLAN is notifying us about
8476 * @port: New UDP port number that VXLAN started listening to
8477 **/
8478static void i40e_add_vxlan_port(struct net_device *netdev,
8479 sa_family_t sa_family, __be16 port)
8480{
8481 struct i40e_netdev_priv *np = netdev_priv(netdev);
8482 struct i40e_vsi *vsi = np->vsi;
8483 struct i40e_pf *pf = vsi->back;
8484 u8 next_idx;
8485 u8 idx;
8486
8487 if (sa_family == AF_INET6)
8488 return;
8489
8490 idx = i40e_get_vxlan_port_idx(pf, port);
8491
8492 /* Check if port already exists */
8493 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8494 netdev_info(netdev, "vxlan port %d already offloaded\n",
8495 ntohs(port));
a1c9a9d9
JK		 8496 return;
8497 }
8498
8499 /* Now check if there is space to add the new port */
8500 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8501
8502 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8503 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8504 ntohs(port));
8505 return;
8506 }
8507
8508 /* New port: add it and mark its index in the bitmap */
8509 pf->vxlan_ports[next_idx] = port;
41a1d04b 8510 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8511 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8512}
8513
8514/**
8515 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8516 * @netdev: This physical port's netdev
8517 * @sa_family: Socket Family that VXLAN is notifying us about
8518 * @port: UDP port number that VXLAN stopped listening to
8519 **/
8520static void i40e_del_vxlan_port(struct net_device *netdev,
8521 sa_family_t sa_family, __be16 port)
8522{
8523 struct i40e_netdev_priv *np = netdev_priv(netdev);
8524 struct i40e_vsi *vsi = np->vsi;
8525 struct i40e_pf *pf = vsi->back;
8526 u8 idx;
8527
8528 if (sa_family == AF_INET6)
8529 return;
8530
8531 idx = i40e_get_vxlan_port_idx(pf, port);
8532
8533 /* Check if port already exists */
8534 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8535 /* if port exists, set it to 0 (mark for deletion)
8536 * and make it pending
8537 */
8538 pf->vxlan_ports[idx] = 0;
41a1d04b 8539 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8540 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8541 } else {
c22c06c8 8542 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8543 ntohs(port));
8544 }
8545}
8546
8547#endif
1f224ad2 8548static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8549 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8550{
8551 struct i40e_netdev_priv *np = netdev_priv(netdev);
8552 struct i40e_pf *pf = np->vsi->back;
8553 struct i40e_hw *hw = &pf->hw;
8554
8555 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8556 return -EOPNOTSUPP;
8557
8558 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8559 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8560
8561 return 0;
8562}
8563
2f90ade6
JB		 8564/**
8565 * i40e_ndo_fdb_add - add an entry to the hardware database
8566 * @ndm: the input from the stack
8567 * @tb: pointer to array of nladdr (unused)
8568 * @dev: the net device pointer
8569 * @addr: the MAC address entry being added
8570 * @flags: instructions from stack about fdb operation
8571 */
4ba0dea5
GR		 8572static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8573 struct net_device *dev,
f6f6424b 8574 const unsigned char *addr, u16 vid,
4ba0dea5 8575 u16 flags)
4ba0dea5
GR		 8576{
8577 struct i40e_netdev_priv *np = netdev_priv(dev);
8578 struct i40e_pf *pf = np->vsi->back;
8579 int err = 0;
8580
8581 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8582 return -EOPNOTSUPP;
8583
65891fea
OG		 8584 if (vid) {
8585 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8586 return -EINVAL;
8587 }
8588
4ba0dea5
GR		 8589 /* Hardware does not support aging addresses so if a
8590 * ndm_state is given only allow permanent addresses
8591 */
8592 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8593 netdev_info(dev, "FDB only supports static addresses\n");
8594 return -EINVAL;
8595 }
8596
8597 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8598 err = dev_uc_add_excl(dev, addr);
8599 else if (is_multicast_ether_addr(addr))
8600 err = dev_mc_add_excl(dev, addr);
8601 else
8602 err = -EINVAL;
8603
8604 /* Only return duplicate errors if NLM_F_EXCL is set */
8605 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8606 err = 0;
8607
8608 return err;
8609}
8610
51616018
NP		 8611/**
8612 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8613 * @dev: the netdev being configured
8614 * @nlh: RTNL message
8615 *
8616 * Inserts a new hardware bridge if not already created and
8617 * enables the bridging mode requested (VEB or VEPA). If the
8618 * hardware bridge has already been inserted and the request
8619 * is to change the mode then that requires a PF reset to
8620 * allow rebuild of the components with required hardware
8621 * bridge mode enabled.
8622 **/
8623static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8624 struct nlmsghdr *nlh,
8625 u16 flags)
51616018
NP		 8626{
8627 struct i40e_netdev_priv *np = netdev_priv(dev);
8628 struct i40e_vsi *vsi = np->vsi;
8629 struct i40e_pf *pf = vsi->back;
8630 struct i40e_veb *veb = NULL;
8631 struct nlattr *attr, *br_spec;
8632 int i, rem;
8633
8634 /* Only for PF VSI for now */
8635 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8636 return -EOPNOTSUPP;
8637
8638 /* Find the HW bridge for PF VSI */
8639 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8640 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8641 veb = pf->veb[i];
8642 }
8643
8644 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8645
8646 nla_for_each_nested(attr, br_spec, rem) {
8647 __u16 mode;
8648
8649 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8650 continue;
8651
8652 mode = nla_get_u16(attr);
8653 if ((mode != BRIDGE_MODE_VEPA) &&
8654 (mode != BRIDGE_MODE_VEB))
8655 return -EINVAL;
8656
8657 /* Insert a new HW bridge */
8658 if (!veb) {
8659 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8660 vsi->tc_config.enabled_tc);
8661 if (veb) {
8662 veb->bridge_mode = mode;
8663 i40e_config_bridge_mode(veb);
8664 } else {
8665 /* No Bridge HW offload available */
8666 return -ENOENT;
8667 }
8668 break;
8669 } else if (mode != veb->bridge_mode) {
8670 /* Existing HW bridge but different mode needs reset */
8671 veb->bridge_mode = mode;
fc60861e
ASJ		 8672 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8673 if (mode == BRIDGE_MODE_VEB)
8674 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8675 else
8676 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8677 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8678 break;
8679 }
8680 }
8681
8682 return 0;
8683}
8684
8685/**
8686 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8687 * @skb: skb buff
8688 * @pid: process id
8689 * @seq: RTNL message seq #
8690 * @dev: the netdev being configured
8691 * @filter_mask: unused
d4b2f9fe 8692 * @nlflags: netlink flags passed in
51616018
NP		 8693 *
8694 * Return the mode in which the hardware bridge is operating in
8695 * i.e VEB or VEPA.
8696 **/
51616018
NP		 8697static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8698 struct net_device *dev,
9f4ffc44
CW		 8699 u32 __always_unused filter_mask,
8700 int nlflags)
51616018
NP		 8701{
8702 struct i40e_netdev_priv *np = netdev_priv(dev);
8703 struct i40e_vsi *vsi = np->vsi;
8704 struct i40e_pf *pf = vsi->back;
8705 struct i40e_veb *veb = NULL;
8706 int i;
8707
8708 /* Only for PF VSI for now */
8709 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8710 return -EOPNOTSUPP;
8711
8712 /* Find the HW bridge for the PF VSI */
8713 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8714 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8715 veb = pf->veb[i];
8716 }
8717
8718 if (!veb)
8719 return 0;
8720
46c264da 8721 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8722 nlflags, 0, 0, filter_mask, NULL);
51616018 8723}
51616018 8724
f44a75e2
JS		 8725#define I40E_MAX_TUNNEL_HDR_LEN 80
8726/**
8727 * i40e_features_check - Validate encapsulated packet conforms to limits
8728 * @skb: skb buff
2bc11c63 8729 * @dev: This physical port's netdev
f44a75e2
JS		 8730 * @features: Offload features that the stack believes apply
8731 **/
8732static netdev_features_t i40e_features_check(struct sk_buff *skb,
8733 struct net_device *dev,
8734 netdev_features_t features)
8735{
8736 if (skb->encapsulation &&
8737 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8738 I40E_MAX_TUNNEL_HDR_LEN))
8739 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8740
8741 return features;
8742}
8743
37a2973a 8744static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8745 .ndo_open = i40e_open,
8746 .ndo_stop = i40e_close,
8747 .ndo_start_xmit = i40e_lan_xmit_frame,
8748 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8749 .ndo_set_rx_mode = i40e_set_rx_mode,
8750 .ndo_validate_addr = eth_validate_addr,
8751 .ndo_set_mac_address = i40e_set_mac,
8752 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8753 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8754 .ndo_tx_timeout = i40e_tx_timeout,
8755 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8756 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8757#ifdef CONFIG_NET_POLL_CONTROLLER
8758 .ndo_poll_controller = i40e_netpoll,
8759#endif
8760 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8761#ifdef I40E_FCOE
8762 .ndo_fcoe_enable = i40e_fcoe_enable,
8763 .ndo_fcoe_disable = i40e_fcoe_disable,
8764#endif
41c445ff
JB		 8765 .ndo_set_features = i40e_set_features,
8766 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8767 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8768 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8769 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8770 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8771 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8772#ifdef CONFIG_I40E_VXLAN
8773 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8774 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8775#endif
1f224ad2 8776 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8777 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8778 .ndo_features_check = i40e_features_check,
51616018
NP		 8779 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8780 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8781};
8782
8783/**
8784 * i40e_config_netdev - Setup the netdev flags
8785 * @vsi: the VSI being configured
8786 *
8787 * Returns 0 on success, negative value on failure
8788 **/
8789static int i40e_config_netdev(struct i40e_vsi *vsi)
8790{
1a10370a 8791 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8792 struct i40e_pf *pf = vsi->back;
8793 struct i40e_hw *hw = &pf->hw;
8794 struct i40e_netdev_priv *np;
8795 struct net_device *netdev;
8796 u8 mac_addr[ETH_ALEN];
8797 int etherdev_size;
8798
8799 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8800 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8801 if (!netdev)
8802 return -ENOMEM;
8803
8804 vsi->netdev = netdev;
8805 np = netdev_priv(netdev);
8806 np->vsi = vsi;
8807
d70e941b 8808 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8809 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8810 NETIF_F_GSO_GRE |
d70e941b 8811 NETIF_F_TSO;
41c445ff
JB		 8812
8813 netdev->features = NETIF_F_SG |
8814 NETIF_F_IP_CSUM |
8815 NETIF_F_SCTP_CSUM |
8816 NETIF_F_HIGHDMA |
8817 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8818 NETIF_F_GSO_GRE |
41c445ff
JB		 8819 NETIF_F_HW_VLAN_CTAG_TX |
8820 NETIF_F_HW_VLAN_CTAG_RX |
8821 NETIF_F_HW_VLAN_CTAG_FILTER |
8822 NETIF_F_IPV6_CSUM |
8823 NETIF_F_TSO |
059dab69 8824 NETIF_F_TSO_ECN |
41c445ff
JB		 8825 NETIF_F_TSO6 |
8826 NETIF_F_RXCSUM |
8827 NETIF_F_RXHASH |
8828 0;
8829
2e86a0b6
ASJ		 8830 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8831 netdev->features |= NETIF_F_NTUPLE;
8832
41c445ff
JB		 8833 /* copy netdev features into list of user selectable features */
8834 netdev->hw_features |= netdev->features;
8835
8836 if (vsi->type == I40E_VSI_MAIN) {
8837 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8838 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8839 /* The following steps are necessary to prevent reception
8840 * of tagged packets - some older NVM configurations load a
8841 * default a MAC-VLAN filter that accepts any tagged packet
8842 * which must be replaced by a normal filter.
8c27d42e 8843 */
21659035
KP		 8844 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
8845 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 8846 i40e_add_filter(vsi, mac_addr,
8847 I40E_VLAN_ANY, false, true);
21659035
KP		 8848 spin_unlock_bh(&vsi->mac_filter_list_lock);
8849 }
41c445ff
JB		 8850 } else {
8851 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8852 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8853 pf->vsi[pf->lan_vsi]->netdev->name);
8854 random_ether_addr(mac_addr);
21659035
KP		 8855
8856 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 8857 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 8858 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8859 }
21659035
KP		 8860
8861 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 8862 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 8863 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8864
9a173901
GR		 8865 ether_addr_copy(netdev->dev_addr, mac_addr);
8866 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8867 /* vlan gets same features (except vlan offload)
8868 * after any tweaks for specific VSI types
8869 */
8870 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8871 NETIF_F_HW_VLAN_CTAG_RX |
8872 NETIF_F_HW_VLAN_CTAG_FILTER);
8873 netdev->priv_flags |= IFF_UNICAST_FLT;
8874 netdev->priv_flags |= IFF_SUPP_NOFCS;
8875 /* Setup netdev TC information */
8876 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8877
8878 netdev->netdev_ops = &i40e_netdev_ops;
8879 netdev->watchdog_timeo = 5 * HZ;
8880 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8881#ifdef I40E_FCOE
8882 i40e_fcoe_config_netdev(netdev, vsi);
8883#endif
41c445ff
JB		 8884
8885 return 0;
8886}
8887
8888/**
8889 * i40e_vsi_delete - Delete a VSI from the switch
8890 * @vsi: the VSI being removed
8891 *
8892 * Returns 0 on success, negative value on failure
8893 **/
8894static void i40e_vsi_delete(struct i40e_vsi *vsi)
8895{
8896 /* remove default VSI is not allowed */
8897 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8898 return;
8899
41c445ff 8900 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8901}
8902
51616018
NP		 8903/**
8904 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8905 * @vsi: the VSI being queried
8906 *
8907 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8908 **/
8909int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8910{
8911 struct i40e_veb *veb;
8912 struct i40e_pf *pf = vsi->back;
8913
8914 /* Uplink is not a bridge so default to VEB */
8915 if (vsi->veb_idx == I40E_NO_VEB)
8916 return 1;
8917
8918 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 8919 if (!veb) {
8920 dev_info(&pf->pdev->dev,
8921 "There is no veb associated with the bridge\n");
8922 return -ENOENT;
8923 }
8924
51616018 8925 /* Uplink is a bridge in VEPA mode */
09603eaa 8926 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 8927 return 0;
09603eaa
AA		 8928 } else {
8929 /* Uplink is a bridge in VEB mode */
8930 return 1;
8931 }
51616018 8932
09603eaa
AA		 8933 /* VEPA is now default bridge, so return 0 */
8934 return 0;
51616018
NP		 8935}
8936
41c445ff
JB		 8937/**
8938 * i40e_add_vsi - Add a VSI to the switch
8939 * @vsi: the VSI being configured
8940 *
8941 * This initializes a VSI context depending on the VSI type to be added and
8942 * passes it down to the add_vsi aq command.
8943 **/
8944static int i40e_add_vsi(struct i40e_vsi *vsi)
8945{
8946 int ret = -ENODEV;
21659035
KP		 8947 u8 laa_macaddr[ETH_ALEN];
8948 bool found_laa_mac_filter = false;
41c445ff
JB		 8949 struct i40e_pf *pf = vsi->back;
8950 struct i40e_hw *hw = &pf->hw;
8951 struct i40e_vsi_context ctxt;
21659035
KP		 8952 struct i40e_mac_filter *f, *ftmp;
8953
41c445ff
JB		 8954 u8 enabled_tc = 0x1; /* TC0 enabled */
8955 int f_count = 0;
8956
8957 memset(&ctxt, 0, sizeof(ctxt));
8958 switch (vsi->type) {
8959 case I40E_VSI_MAIN:
8960 /* The PF's main VSI is already setup as part of the
8961 * device initialization, so we'll not bother with
8962 * the add_vsi call, but we will retrieve the current
8963 * VSI context.
8964 */
8965 ctxt.seid = pf->main_vsi_seid;
8966 ctxt.pf_num = pf->hw.pf_id;
8967 ctxt.vf_num = 0;
8968 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8969 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8970 if (ret) {
8971 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8972 "couldn't get PF vsi config, err %s aq_err %s\n",
8973 i40e_stat_str(&pf->hw, ret),
8974 i40e_aq_str(&pf->hw,
8975 pf->hw.aq.asq_last_status));
41c445ff
JB		 8976 return -ENOENT;
8977 }
1a2f6248 8978 vsi->info = ctxt.info;
41c445ff
JB		 8979 vsi->info.valid_sections = 0;
8980
8981 vsi->seid = ctxt.seid;
8982 vsi->id = ctxt.vsi_number;
8983
8984 enabled_tc = i40e_pf_get_tc_map(pf);
8985
8986 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8987 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8988 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8989 memset(&ctxt, 0, sizeof(ctxt));
8990 ctxt.seid = pf->main_vsi_seid;
8991 ctxt.pf_num = pf->hw.pf_id;
8992 ctxt.vf_num = 0;
8993 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8994 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8995 if (ret) {
8996 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8997 "update vsi failed, err %s aq_err %s\n",
8998 i40e_stat_str(&pf->hw, ret),
8999 i40e_aq_str(&pf->hw,
9000 pf->hw.aq.asq_last_status));
41c445ff
JB		 9001 ret = -ENOENT;
9002 goto err;
9003 }
9004 /* update the local VSI info queue map */
9005 i40e_vsi_update_queue_map(vsi, &ctxt);
9006 vsi->info.valid_sections = 0;
9007 } else {
9008 /* Default/Main VSI is only enabled for TC0
9009 * reconfigure it to enable all TCs that are
9010 * available on the port in SFP mode.
63d7e5a4
NP		 9011 * For MFP case the iSCSI PF would use this
9012 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9013 */
9014 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9015 if (ret) {
9016 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9017 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9018 enabled_tc,
9019 i40e_stat_str(&pf->hw, ret),
9020 i40e_aq_str(&pf->hw,
9021 pf->hw.aq.asq_last_status));
41c445ff
JB		 9022 ret = -ENOENT;
9023 }
9024 }
9025 break;
9026
9027 case I40E_VSI_FDIR:
cbf61325
ASJ		 9028 ctxt.pf_num = hw->pf_id;
9029 ctxt.vf_num = 0;
9030 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9031 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9032 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9033 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9034 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9035 ctxt.info.valid_sections |=
fc60861e 9036 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9037 ctxt.info.switch_id =
fc60861e 9038 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9039 }
41c445ff 9040 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9041 break;
9042
9043 case I40E_VSI_VMDQ2:
9044 ctxt.pf_num = hw->pf_id;
9045 ctxt.vf_num = 0;
9046 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9047 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9048 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9049
41c445ff
JB		 9050 /* This VSI is connected to VEB so the switch_id
9051 * should be set to zero by default.
9052 */
51616018
NP		 9053 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9054 ctxt.info.valid_sections |=
9055 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9056 ctxt.info.switch_id =
9057 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9058 }
41c445ff
JB		 9059
9060 /* Setup the VSI tx/rx queue map for TC0 only for now */
9061 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9062 break;
9063
9064 case I40E_VSI_SRIOV:
9065 ctxt.pf_num = hw->pf_id;
9066 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9067 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9068 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9069 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9070
41c445ff
JB		 9071 /* This VSI is connected to VEB so the switch_id
9072 * should be set to zero by default.
9073 */
51616018
NP		 9074 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9075 ctxt.info.valid_sections |=
9076 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9077 ctxt.info.switch_id =
9078 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9079 }
41c445ff
JB		 9080
9081 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9082 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9083 if (pf->vf[vsi->vf_id].spoofchk) {
9084 ctxt.info.valid_sections |=
9085 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9086 ctxt.info.sec_flags |=
9087 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9088 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9089 }
41c445ff
JB		 9090 /* Setup the VSI tx/rx queue map for TC0 only for now */
9091 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9092 break;
9093
38e00438
VD		 9094#ifdef I40E_FCOE
9095 case I40E_VSI_FCOE:
9096 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9097 if (ret) {
9098 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9099 return ret;
9100 }
9101 break;
9102
9103#endif /* I40E_FCOE */
41c445ff
JB		 9104 default:
9105 return -ENODEV;
9106 }
9107
9108 if (vsi->type != I40E_VSI_MAIN) {
9109 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9110 if (ret) {
9111 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9112 "add vsi failed, err %s aq_err %s\n",
9113 i40e_stat_str(&pf->hw, ret),
9114 i40e_aq_str(&pf->hw,
9115 pf->hw.aq.asq_last_status));
41c445ff
JB		 9116 ret = -ENOENT;
9117 goto err;
9118 }
1a2f6248 9119 vsi->info = ctxt.info;
41c445ff
JB		 9120 vsi->info.valid_sections = 0;
9121 vsi->seid = ctxt.seid;
9122 vsi->id = ctxt.vsi_number;
9123 }
9124
21659035 9125 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9126 /* If macvlan filters already exist, force them to get loaded */
9127 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9128 f->changed = true;
9129 f_count++;
6252c7e4 9130
21659035 9131 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9132 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9133 ether_addr_copy(laa_macaddr, f->macaddr);
9134 found_laa_mac_filter = true;
9135 }
9136 }
9137 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9138
21659035
KP		 9139 if (found_laa_mac_filter) {
9140 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9141
21659035
KP		 9142 memset(&element, 0, sizeof(element));
9143 ether_addr_copy(element.mac_addr, laa_macaddr);
9144 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9145 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9146 &element, 1, NULL);
9147 if (ret) {
9148 /* some older FW has a different default */
9149 element.flags |=
9150 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9151 i40e_aq_remove_macvlan(hw, vsi->seid,
9152 &element, 1, NULL);
6252c7e4 9153 }
21659035
KP		 9154
9155 i40e_aq_mac_address_write(hw,
9156 I40E_AQC_WRITE_TYPE_LAA_WOL,
9157 laa_macaddr, NULL);
41c445ff 9158 }
21659035 9159
41c445ff
JB		 9160 if (f_count) {
9161 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9162 pf->flags |= I40E_FLAG_FILTER_SYNC;
9163 }
9164
9165 /* Update VSI BW information */
9166 ret = i40e_vsi_get_bw_info(vsi);
9167 if (ret) {
9168 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9169 "couldn't get vsi bw info, err %s aq_err %s\n",
9170 i40e_stat_str(&pf->hw, ret),
9171 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9172 /* VSI is already added so not tearing that up */
9173 ret = 0;
9174 }
9175
9176err:
9177 return ret;
9178}
9179
9180/**
9181 * i40e_vsi_release - Delete a VSI and free its resources
9182 * @vsi: the VSI being removed
9183 *
9184 * Returns 0 on success or < 0 on error
9185 **/
9186int i40e_vsi_release(struct i40e_vsi *vsi)
9187{
9188 struct i40e_mac_filter *f, *ftmp;
9189 struct i40e_veb *veb = NULL;
9190 struct i40e_pf *pf;
9191 u16 uplink_seid;
9192 int i, n;
9193
9194 pf = vsi->back;
9195
9196 /* release of a VEB-owner or last VSI is not allowed */
9197 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9198 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9199 vsi->seid, vsi->uplink_seid);
9200 return -ENODEV;
9201 }
9202 if (vsi == pf->vsi[pf->lan_vsi] &&
9203 !test_bit(__I40E_DOWN, &pf->state)) {
9204 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9205 return -ENODEV;
9206 }
9207
9208 uplink_seid = vsi->uplink_seid;
9209 if (vsi->type != I40E_VSI_SRIOV) {
9210 if (vsi->netdev_registered) {
9211 vsi->netdev_registered = false;
9212 if (vsi->netdev) {
9213 /* results in a call to i40e_close() */
9214 unregister_netdev(vsi->netdev);
41c445ff
JB		 9215 }
9216 } else {
90ef8d47 9217 i40e_vsi_close(vsi);
41c445ff
JB		 9218 }
9219 i40e_vsi_disable_irq(vsi);
9220 }
9221
21659035 9222 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9223 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9224 i40e_del_filter(vsi, f->macaddr, f->vlan,
9225 f->is_vf, f->is_netdev);
21659035
KP		 9226 spin_unlock_bh(&vsi->mac_filter_list_lock);
9227
17652c63 9228 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9229
9230 i40e_vsi_delete(vsi);
9231 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9232 if (vsi->netdev) {
9233 free_netdev(vsi->netdev);
9234 vsi->netdev = NULL;
9235 }
41c445ff
JB		 9236 i40e_vsi_clear_rings(vsi);
9237 i40e_vsi_clear(vsi);
9238
9239 /* If this was the last thing on the VEB, except for the
9240 * controlling VSI, remove the VEB, which puts the controlling
9241 * VSI onto the next level down in the switch.
9242 *
9243 * Well, okay, there's one more exception here: don't remove
9244 * the orphan VEBs yet. We'll wait for an explicit remove request
9245 * from up the network stack.
9246 */
505682cd 9247 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9248 if (pf->vsi[i] &&
9249 pf->vsi[i]->uplink_seid == uplink_seid &&
9250 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9251 n++; /* count the VSIs */
9252 }
9253 }
9254 for (i = 0; i < I40E_MAX_VEB; i++) {
9255 if (!pf->veb[i])
9256 continue;
9257 if (pf->veb[i]->uplink_seid == uplink_seid)
9258 n++; /* count the VEBs */
9259 if (pf->veb[i]->seid == uplink_seid)
9260 veb = pf->veb[i];
9261 }
9262 if (n == 0 && veb && veb->uplink_seid != 0)
9263 i40e_veb_release(veb);
9264
9265 return 0;
9266}
9267
9268/**
9269 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9270 * @vsi: ptr to the VSI
9271 *
9272 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9273 * corresponding SW VSI structure and initializes num_queue_pairs for the
9274 * newly allocated VSI.
9275 *
9276 * Returns 0 on success or negative on failure
9277 **/
9278static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9279{
9280 int ret = -ENOENT;
9281 struct i40e_pf *pf = vsi->back;
9282
493fb300 9283 if (vsi->q_vectors[0]) {
41c445ff
JB		 9284 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9285 vsi->seid);
9286 return -EEXIST;
9287 }
9288
9289 if (vsi->base_vector) {
f29eaa3d 9290 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9291 vsi->seid, vsi->base_vector);
9292 return -EEXIST;
9293 }
9294
90e04070 9295 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9296 if (ret) {
9297 dev_info(&pf->pdev->dev,
9298 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9299 vsi->num_q_vectors, vsi->seid, ret);
9300 vsi->num_q_vectors = 0;
9301 goto vector_setup_out;
9302 }
9303
26cdc443
ASJ		 9304 /* In Legacy mode, we do not have to get any other vector since we
9305 * piggyback on the misc/ICR0 for queue interrupts.
9306 */
9307 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9308 return ret;
958a3e3b
SN		 9309 if (vsi->num_q_vectors)
9310 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9311 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9312 if (vsi->base_vector < 0) {
9313 dev_info(&pf->pdev->dev,
049a2be8
SN		 9314 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9315 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9316 i40e_vsi_free_q_vectors(vsi);
9317 ret = -ENOENT;
9318 goto vector_setup_out;
9319 }
9320
9321vector_setup_out:
9322 return ret;
9323}
9324
bc7d338f
ASJ		 9325/**
9326 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9327 * @vsi: pointer to the vsi.
9328 *
9329 * This re-allocates a vsi's queue resources.
9330 *
9331 * Returns pointer to the successfully allocated and configured VSI sw struct
9332 * on success, otherwise returns NULL on failure.
9333 **/
9334static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9335{
9336 struct i40e_pf *pf = vsi->back;
9337 u8 enabled_tc;
9338 int ret;
9339
9340 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9341 i40e_vsi_clear_rings(vsi);
9342
9343 i40e_vsi_free_arrays(vsi, false);
9344 i40e_set_num_rings_in_vsi(vsi);
9345 ret = i40e_vsi_alloc_arrays(vsi, false);
9346 if (ret)
9347 goto err_vsi;
9348
9349 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9350 if (ret < 0) {
049a2be8 9351 dev_info(&pf->pdev->dev,
f1c7e72e 9352 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9353 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9354 goto err_vsi;
9355 }
9356 vsi->base_queue = ret;
9357
9358 /* Update the FW view of the VSI. Force a reset of TC and queue
9359 * layout configurations.
9360 */
9361 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9362 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9363 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9364 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9365
9366 /* assign it some queues */
9367 ret = i40e_alloc_rings(vsi);
9368 if (ret)
9369 goto err_rings;
9370
9371 /* map all of the rings to the q_vectors */
9372 i40e_vsi_map_rings_to_vectors(vsi);
9373 return vsi;
9374
9375err_rings:
9376 i40e_vsi_free_q_vectors(vsi);
9377 if (vsi->netdev_registered) {
9378 vsi->netdev_registered = false;
9379 unregister_netdev(vsi->netdev);
9380 free_netdev(vsi->netdev);
9381 vsi->netdev = NULL;
9382 }
9383 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9384err_vsi:
9385 i40e_vsi_clear(vsi);
9386 return NULL;
9387}
9388
41c445ff
JB		 9389/**
9390 * i40e_vsi_setup - Set up a VSI by a given type
9391 * @pf: board private structure
9392 * @type: VSI type
9393 * @uplink_seid: the switch element to link to
9394 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9395 *
9396 * This allocates the sw VSI structure and its queue resources, then add a VSI
9397 * to the identified VEB.
9398 *
9399 * Returns pointer to the successfully allocated and configure VSI sw struct on
9400 * success, otherwise returns NULL on failure.
9401 **/
9402struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9403 u16 uplink_seid, u32 param1)
9404{
9405 struct i40e_vsi *vsi = NULL;
9406 struct i40e_veb *veb = NULL;
9407 int ret, i;
9408 int v_idx;
9409
9410 /* The requested uplink_seid must be either
9411 * - the PF's port seid
9412 * no VEB is needed because this is the PF
9413 * or this is a Flow Director special case VSI
9414 * - seid of an existing VEB
9415 * - seid of a VSI that owns an existing VEB
9416 * - seid of a VSI that doesn't own a VEB
9417 * a new VEB is created and the VSI becomes the owner
9418 * - seid of the PF VSI, which is what creates the first VEB
9419 * this is a special case of the previous
9420 *
9421 * Find which uplink_seid we were given and create a new VEB if needed
9422 */
9423 for (i = 0; i < I40E_MAX_VEB; i++) {
9424 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9425 veb = pf->veb[i];
9426 break;
9427 }
9428 }
9429
9430 if (!veb && uplink_seid != pf->mac_seid) {
9431
505682cd 9432 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9433 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9434 vsi = pf->vsi[i];
9435 break;
9436 }
9437 }
9438 if (!vsi) {
9439 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9440 uplink_seid);
9441 return NULL;
9442 }
9443
9444 if (vsi->uplink_seid == pf->mac_seid)
9445 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9446 vsi->tc_config.enabled_tc);
9447 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9448 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9449 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9450 if (veb) {
9451 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9452 dev_info(&vsi->back->pdev->dev,
fb43201f 9453 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9454 return NULL;
9455 }
fa11cb3d
ASJ		 9456 /* We come up by default in VEPA mode if SRIOV is not
9457 * already enabled, in which case we can't force VEPA
9458 * mode.
9459 */
9460 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9461 veb->bridge_mode = BRIDGE_MODE_VEPA;
9462 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9463 }
51616018 9464 i40e_config_bridge_mode(veb);
79c21a82 9465 }
41c445ff
JB		 9466 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9467 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9468 veb = pf->veb[i];
9469 }
9470 if (!veb) {
9471 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9472 return NULL;
9473 }
9474
9475 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9476 uplink_seid = veb->seid;
9477 }
9478
9479 /* get vsi sw struct */
9480 v_idx = i40e_vsi_mem_alloc(pf, type);
9481 if (v_idx < 0)
9482 goto err_alloc;
9483 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9484 if (!vsi)
9485 goto err_alloc;
41c445ff
JB		 9486 vsi->type = type;
9487 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9488
9489 if (type == I40E_VSI_MAIN)
9490 pf->lan_vsi = v_idx;
9491 else if (type == I40E_VSI_SRIOV)
9492 vsi->vf_id = param1;
9493 /* assign it some queues */
cbf61325
ASJ		 9494 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9495 vsi->idx);
41c445ff 9496 if (ret < 0) {
049a2be8
SN		 9497 dev_info(&pf->pdev->dev,
9498 "failed to get tracking for %d queues for VSI %d err=%d\n",
9499 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9500 goto err_vsi;
9501 }
9502 vsi->base_queue = ret;
9503
9504 /* get a VSI from the hardware */
9505 vsi->uplink_seid = uplink_seid;
9506 ret = i40e_add_vsi(vsi);
9507 if (ret)
9508 goto err_vsi;
9509
9510 switch (vsi->type) {
9511 /* setup the netdev if needed */
9512 case I40E_VSI_MAIN:
9513 case I40E_VSI_VMDQ2:
38e00438 9514 case I40E_VSI_FCOE:
41c445ff
JB		 9515 ret = i40e_config_netdev(vsi);
9516 if (ret)
9517 goto err_netdev;
9518 ret = register_netdev(vsi->netdev);
9519 if (ret)
9520 goto err_netdev;
9521 vsi->netdev_registered = true;
9522 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9523#ifdef CONFIG_I40E_DCB
9524 /* Setup DCB netlink interface */
9525 i40e_dcbnl_setup(vsi);
9526#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9527 /* fall through */
9528
9529 case I40E_VSI_FDIR:
9530 /* set up vectors and rings if needed */
9531 ret = i40e_vsi_setup_vectors(vsi);
9532 if (ret)
9533 goto err_msix;
9534
9535 ret = i40e_alloc_rings(vsi);
9536 if (ret)
9537 goto err_rings;
9538
9539 /* map all of the rings to the q_vectors */
9540 i40e_vsi_map_rings_to_vectors(vsi);
9541
9542 i40e_vsi_reset_stats(vsi);
9543 break;
9544
9545 default:
9546 /* no netdev or rings for the other VSI types */
9547 break;
9548 }
9549
e25d00b8
ASJ		 9550 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9551 (vsi->type == I40E_VSI_VMDQ2)) {
9552 ret = i40e_vsi_config_rss(vsi);
9553 }
41c445ff
JB		 9554 return vsi;
9555
9556err_rings:
9557 i40e_vsi_free_q_vectors(vsi);
9558err_msix:
9559 if (vsi->netdev_registered) {
9560 vsi->netdev_registered = false;
9561 unregister_netdev(vsi->netdev);
9562 free_netdev(vsi->netdev);
9563 vsi->netdev = NULL;
9564 }
9565err_netdev:
9566 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9567err_vsi:
9568 i40e_vsi_clear(vsi);
9569err_alloc:
9570 return NULL;
9571}
9572
9573/**
9574 * i40e_veb_get_bw_info - Query VEB BW information
9575 * @veb: the veb to query
9576 *
9577 * Query the Tx scheduler BW configuration data for given VEB
9578 **/
9579static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9580{
9581 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9582 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9583 struct i40e_pf *pf = veb->pf;
9584 struct i40e_hw *hw = &pf->hw;
9585 u32 tc_bw_max;
9586 int ret = 0;
9587 int i;
9588
9589 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9590 &bw_data, NULL);
9591 if (ret) {
9592 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9593 "query veb bw config failed, err %s aq_err %s\n",
9594 i40e_stat_str(&pf->hw, ret),
9595 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9596 goto out;
9597 }
9598
9599 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9600 &ets_data, NULL);
9601 if (ret) {
9602 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9603 "query veb bw ets config failed, err %s aq_err %s\n",
9604 i40e_stat_str(&pf->hw, ret),
9605 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9606 goto out;
9607 }
9608
9609 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9610 veb->bw_max_quanta = ets_data.tc_bw_max;
9611 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9612 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9613 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9614 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9615 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9616 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9617 veb->bw_tc_limit_credits[i] =
9618 le16_to_cpu(bw_data.tc_bw_limits[i]);
9619 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9620 }
9621
9622out:
9623 return ret;
9624}
9625
9626/**
9627 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9628 * @pf: board private structure
9629 *
9630 * On error: returns error code (negative)
9631 * On success: returns vsi index in PF (positive)
9632 **/
9633static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9634{
9635 int ret = -ENOENT;
9636 struct i40e_veb *veb;
9637 int i;
9638
9639 /* Need to protect the allocation of switch elements at the PF level */
9640 mutex_lock(&pf->switch_mutex);
9641
9642 /* VEB list may be fragmented if VEB creation/destruction has
9643 * been happening. We can afford to do a quick scan to look
9644 * for any free slots in the list.
9645 *
9646 * find next empty veb slot, looping back around if necessary
9647 */
9648 i = 0;
9649 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9650 i++;
9651 if (i >= I40E_MAX_VEB) {
9652 ret = -ENOMEM;
9653 goto err_alloc_veb; /* out of VEB slots! */
9654 }
9655
9656 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9657 if (!veb) {
9658 ret = -ENOMEM;
9659 goto err_alloc_veb;
9660 }
9661 veb->pf = pf;
9662 veb->idx = i;
9663 veb->enabled_tc = 1;
9664
9665 pf->veb[i] = veb;
9666 ret = i;
9667err_alloc_veb:
9668 mutex_unlock(&pf->switch_mutex);
9669 return ret;
9670}
9671
9672/**
9673 * i40e_switch_branch_release - Delete a branch of the switch tree
9674 * @branch: where to start deleting
9675 *
9676 * This uses recursion to find the tips of the branch to be
9677 * removed, deleting until we get back to and can delete this VEB.
9678 **/
9679static void i40e_switch_branch_release(struct i40e_veb *branch)
9680{
9681 struct i40e_pf *pf = branch->pf;
9682 u16 branch_seid = branch->seid;
9683 u16 veb_idx = branch->idx;
9684 int i;
9685
9686 /* release any VEBs on this VEB - RECURSION */
9687 for (i = 0; i < I40E_MAX_VEB; i++) {
9688 if (!pf->veb[i])
9689 continue;
9690 if (pf->veb[i]->uplink_seid == branch->seid)
9691 i40e_switch_branch_release(pf->veb[i]);
9692 }
9693
9694 /* Release the VSIs on this VEB, but not the owner VSI.
9695 *
9696 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9697 * the VEB itself, so don't use (*branch) after this loop.
9698 */
505682cd 9699 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9700 if (!pf->vsi[i])
9701 continue;
9702 if (pf->vsi[i]->uplink_seid == branch_seid &&
9703 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9704 i40e_vsi_release(pf->vsi[i]);
9705 }
9706 }
9707
9708 /* There's one corner case where the VEB might not have been
9709 * removed, so double check it here and remove it if needed.
9710 * This case happens if the veb was created from the debugfs
9711 * commands and no VSIs were added to it.
9712 */
9713 if (pf->veb[veb_idx])
9714 i40e_veb_release(pf->veb[veb_idx]);
9715}
9716
9717/**
9718 * i40e_veb_clear - remove veb struct
9719 * @veb: the veb to remove
9720 **/
9721static void i40e_veb_clear(struct i40e_veb *veb)
9722{
9723 if (!veb)
9724 return;
9725
9726 if (veb->pf) {
9727 struct i40e_pf *pf = veb->pf;
9728
9729 mutex_lock(&pf->switch_mutex);
9730 if (pf->veb[veb->idx] == veb)
9731 pf->veb[veb->idx] = NULL;
9732 mutex_unlock(&pf->switch_mutex);
9733 }
9734
9735 kfree(veb);
9736}
9737
9738/**
9739 * i40e_veb_release - Delete a VEB and free its resources
9740 * @veb: the VEB being removed
9741 **/
9742void i40e_veb_release(struct i40e_veb *veb)
9743{
9744 struct i40e_vsi *vsi = NULL;
9745 struct i40e_pf *pf;
9746 int i, n = 0;
9747
9748 pf = veb->pf;
9749
9750 /* find the remaining VSI and check for extras */
505682cd 9751 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9752 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9753 n++;
9754 vsi = pf->vsi[i];
9755 }
9756 }
9757 if (n != 1) {
9758 dev_info(&pf->pdev->dev,
9759 "can't remove VEB %d with %d VSIs left\n",
9760 veb->seid, n);
9761 return;
9762 }
9763
9764 /* move the remaining VSI to uplink veb */
9765 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9766 if (veb->uplink_seid) {
9767 vsi->uplink_seid = veb->uplink_seid;
9768 if (veb->uplink_seid == pf->mac_seid)
9769 vsi->veb_idx = I40E_NO_VEB;
9770 else
9771 vsi->veb_idx = veb->veb_idx;
9772 } else {
9773 /* floating VEB */
9774 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9775 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9776 }
9777
9778 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9779 i40e_veb_clear(veb);
41c445ff
JB		 9780}
9781
9782/**
9783 * i40e_add_veb - create the VEB in the switch
9784 * @veb: the VEB to be instantiated
9785 * @vsi: the controlling VSI
9786 **/
9787static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9788{
f1c7e72e 9789 struct i40e_pf *pf = veb->pf;
92faef85 9790 bool is_default = veb->pf->cur_promisc;
e1c51b95 9791 bool is_cloud = false;
41c445ff
JB		 9792 int ret;
9793
9794 /* get a VEB from the hardware */
f1c7e72e 9795 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9796 veb->enabled_tc, is_default,
9797 is_cloud, &veb->seid, NULL);
41c445ff 9798 if (ret) {
f1c7e72e
SN		 9799 dev_info(&pf->pdev->dev,
9800 "couldn't add VEB, err %s aq_err %s\n",
9801 i40e_stat_str(&pf->hw, ret),
9802 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9803 return -EPERM;
9804 }
9805
9806 /* get statistics counter */
f1c7e72e 9807 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9808 &veb->stats_idx, NULL, NULL, NULL);
9809 if (ret) {
f1c7e72e
SN		 9810 dev_info(&pf->pdev->dev,
9811 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9812 i40e_stat_str(&pf->hw, ret),
9813 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9814 return -EPERM;
9815 }
9816 ret = i40e_veb_get_bw_info(veb);
9817 if (ret) {
f1c7e72e
SN		 9818 dev_info(&pf->pdev->dev,
9819 "couldn't get VEB bw info, err %s aq_err %s\n",
9820 i40e_stat_str(&pf->hw, ret),
9821 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9822 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9823 return -ENOENT;
9824 }
9825
9826 vsi->uplink_seid = veb->seid;
9827 vsi->veb_idx = veb->idx;
9828 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9829
9830 return 0;
9831}
9832
9833/**
9834 * i40e_veb_setup - Set up a VEB
9835 * @pf: board private structure
9836 * @flags: VEB setup flags
9837 * @uplink_seid: the switch element to link to
9838 * @vsi_seid: the initial VSI seid
9839 * @enabled_tc: Enabled TC bit-map
9840 *
9841 * This allocates the sw VEB structure and links it into the switch
9842 * It is possible and legal for this to be a duplicate of an already
9843 * existing VEB. It is also possible for both uplink and vsi seids
9844 * to be zero, in order to create a floating VEB.
9845 *
9846 * Returns pointer to the successfully allocated VEB sw struct on
9847 * success, otherwise returns NULL on failure.
9848 **/
9849struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9850 u16 uplink_seid, u16 vsi_seid,
9851 u8 enabled_tc)
9852{
9853 struct i40e_veb *veb, *uplink_veb = NULL;
9854 int vsi_idx, veb_idx;
9855 int ret;
9856
9857 /* if one seid is 0, the other must be 0 to create a floating relay */
9858 if ((uplink_seid == 0 || vsi_seid == 0) &&
9859 (uplink_seid + vsi_seid != 0)) {
9860 dev_info(&pf->pdev->dev,
9861 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9862 uplink_seid, vsi_seid);
9863 return NULL;
9864 }
9865
9866 /* make sure there is such a vsi and uplink */
505682cd 9867 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9868 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9869 break;
505682cd 9870 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9871 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9872 vsi_seid);
9873 return NULL;
9874 }
9875
9876 if (uplink_seid && uplink_seid != pf->mac_seid) {
9877 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9878 if (pf->veb[veb_idx] &&
9879 pf->veb[veb_idx]->seid == uplink_seid) {
9880 uplink_veb = pf->veb[veb_idx];
9881 break;
9882 }
9883 }
9884 if (!uplink_veb) {
9885 dev_info(&pf->pdev->dev,
9886 "uplink seid %d not found\n", uplink_seid);
9887 return NULL;
9888 }
9889 }
9890
9891 /* get veb sw struct */
9892 veb_idx = i40e_veb_mem_alloc(pf);
9893 if (veb_idx < 0)
9894 goto err_alloc;
9895 veb = pf->veb[veb_idx];
9896 veb->flags = flags;
9897 veb->uplink_seid = uplink_seid;
9898 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9899 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9900
9901 /* create the VEB in the switch */
9902 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9903 if (ret)
9904 goto err_veb;
1bb8b935
SN		 9905 if (vsi_idx == pf->lan_vsi)
9906 pf->lan_veb = veb->idx;
41c445ff
JB		 9907
9908 return veb;
9909
9910err_veb:
9911 i40e_veb_clear(veb);
9912err_alloc:
9913 return NULL;
9914}
9915
9916/**
b40c82e6 9917 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9918 * @pf: board private structure
9919 * @ele: element we are building info from
9920 * @num_reported: total number of elements
9921 * @printconfig: should we print the contents
9922 *
9923 * helper function to assist in extracting a few useful SEID values.
9924 **/
9925static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9926 struct i40e_aqc_switch_config_element_resp *ele,
9927 u16 num_reported, bool printconfig)
9928{
9929 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9930 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9931 u8 element_type = ele->element_type;
9932 u16 seid = le16_to_cpu(ele->seid);
9933
9934 if (printconfig)
9935 dev_info(&pf->pdev->dev,
9936 "type=%d seid=%d uplink=%d downlink=%d\n",
9937 element_type, seid, uplink_seid, downlink_seid);
9938
9939 switch (element_type) {
9940 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9941 pf->mac_seid = seid;
9942 break;
9943 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9944 /* Main VEB? */
9945 if (uplink_seid != pf->mac_seid)
9946 break;
9947 if (pf->lan_veb == I40E_NO_VEB) {
9948 int v;
9949
9950 /* find existing or else empty VEB */
9951 for (v = 0; v < I40E_MAX_VEB; v++) {
9952 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9953 pf->lan_veb = v;
9954 break;
9955 }
9956 }
9957 if (pf->lan_veb == I40E_NO_VEB) {
9958 v = i40e_veb_mem_alloc(pf);
9959 if (v < 0)
9960 break;
9961 pf->lan_veb = v;
9962 }
9963 }
9964
9965 pf->veb[pf->lan_veb]->seid = seid;
9966 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9967 pf->veb[pf->lan_veb]->pf = pf;
9968 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9969 break;
9970 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9971 if (num_reported != 1)
9972 break;
9973 /* This is immediately after a reset so we can assume this is
9974 * the PF's VSI
9975 */
9976 pf->mac_seid = uplink_seid;
9977 pf->pf_seid = downlink_seid;
9978 pf->main_vsi_seid = seid;
9979 if (printconfig)
9980 dev_info(&pf->pdev->dev,
9981 "pf_seid=%d main_vsi_seid=%d\n",
9982 pf->pf_seid, pf->main_vsi_seid);
9983 break;
9984 case I40E_SWITCH_ELEMENT_TYPE_PF:
9985 case I40E_SWITCH_ELEMENT_TYPE_VF:
9986 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9987 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9988 case I40E_SWITCH_ELEMENT_TYPE_PE:
9989 case I40E_SWITCH_ELEMENT_TYPE_PA:
9990 /* ignore these for now */
9991 break;
9992 default:
9993 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9994 element_type, seid);
9995 break;
9996 }
9997}
9998
9999/**
10000 * i40e_fetch_switch_configuration - Get switch config from firmware
10001 * @pf: board private structure
10002 * @printconfig: should we print the contents
10003 *
10004 * Get the current switch configuration from the device and
10005 * extract a few useful SEID values.
10006 **/
10007int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10008{
10009 struct i40e_aqc_get_switch_config_resp *sw_config;
10010 u16 next_seid = 0;
10011 int ret = 0;
10012 u8 *aq_buf;
10013 int i;
10014
10015 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10016 if (!aq_buf)
10017 return -ENOMEM;
10018
10019 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10020 do {
10021 u16 num_reported, num_total;
10022
10023 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10024 I40E_AQ_LARGE_BUF,
10025 &next_seid, NULL);
10026 if (ret) {
10027 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10028 "get switch config failed err %s aq_err %s\n",
10029 i40e_stat_str(&pf->hw, ret),
10030 i40e_aq_str(&pf->hw,
10031 pf->hw.aq.asq_last_status));
41c445ff
JB		 10032 kfree(aq_buf);
10033 return -ENOENT;
10034 }
10035
10036 num_reported = le16_to_cpu(sw_config->header.num_reported);
10037 num_total = le16_to_cpu(sw_config->header.num_total);
10038
10039 if (printconfig)
10040 dev_info(&pf->pdev->dev,
10041 "header: %d reported %d total\n",
10042 num_reported, num_total);
10043
41c445ff
JB		 10044 for (i = 0; i < num_reported; i++) {
10045 struct i40e_aqc_switch_config_element_resp *ele =
10046 &sw_config->element[i];
10047
10048 i40e_setup_pf_switch_element(pf, ele, num_reported,
10049 printconfig);
10050 }
10051 } while (next_seid != 0);
10052
10053 kfree(aq_buf);
10054 return ret;
10055}
10056
10057/**
10058 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10059 * @pf: board private structure
bc7d338f 10060 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10061 *
10062 * Returns 0 on success, negative value on failure
10063 **/
bc7d338f 10064static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10065{
10066 int ret;
10067
10068 /* find out what's out there already */
10069 ret = i40e_fetch_switch_configuration(pf, false);
10070 if (ret) {
10071 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10072 "couldn't fetch switch config, err %s aq_err %s\n",
10073 i40e_stat_str(&pf->hw, ret),
10074 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10075 return ret;
10076 }
10077 i40e_pf_reset_stats(pf);
10078
41c445ff 10079 /* first time setup */
bc7d338f 10080 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10081 struct i40e_vsi *vsi = NULL;
10082 u16 uplink_seid;
10083
10084 /* Set up the PF VSI associated with the PF's main VSI
10085 * that is already in the HW switch
10086 */
10087 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10088 uplink_seid = pf->veb[pf->lan_veb]->seid;
10089 else
10090 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10091 if (pf->lan_vsi == I40E_NO_VSI)
10092 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10093 else if (reinit)
10094 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10095 if (!vsi) {
10096 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10097 i40e_fdir_teardown(pf);
10098 return -EAGAIN;
10099 }
41c445ff
JB		 10100 } else {
10101 /* force a reset of TC and queue layout configurations */
10102 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10103
41c445ff
JB		 10104 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10105 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10106 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10107 }
10108 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10109
cbf61325
ASJ		 10110 i40e_fdir_sb_setup(pf);
10111
41c445ff
JB		 10112 /* Setup static PF queue filter control settings */
10113 ret = i40e_setup_pf_filter_control(pf);
10114 if (ret) {
10115 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10116 ret);
10117 /* Failure here should not stop continuing other steps */
10118 }
10119
10120 /* enable RSS in the HW, even for only one queue, as the stack can use
10121 * the hash
10122 */
10123 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10124 i40e_pf_config_rss(pf);
41c445ff
JB		 10125
10126 /* fill in link information and enable LSE reporting */
0a862b43 10127 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10128 i40e_link_event(pf);
10129
d52c20b7 10130 /* Initialize user-specific link properties */
41c445ff
JB		 10131 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10132 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10133
beb0dff1
JK		 10134 i40e_ptp_init(pf);
10135
41c445ff
JB		 10136 return ret;
10137}
10138
41c445ff
JB		 10139/**
10140 * i40e_determine_queue_usage - Work out queue distribution
10141 * @pf: board private structure
10142 **/
10143static void i40e_determine_queue_usage(struct i40e_pf *pf)
10144{
41c445ff
JB		 10145 int queues_left;
10146
10147 pf->num_lan_qps = 0;
38e00438
VD		 10148#ifdef I40E_FCOE
10149 pf->num_fcoe_qps = 0;
10150#endif
41c445ff
JB		 10151
10152 /* Find the max queues to be put into basic use. We'll always be
10153 * using TC0, whether or not DCB is running, and TC0 will get the
10154 * big RSS set.
10155 */
10156 queues_left = pf->hw.func_caps.num_tx_qp;
10157
cbf61325 10158 if ((queues_left == 1) ||
9aa7e935 10159 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10160 /* one qp for PF, no queues for anything else */
10161 queues_left = 0;
acd65448 10162 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10163
10164 /* make sure all the fancies are disabled */
60ea5f83 10165 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10166#ifdef I40E_FCOE
10167 I40E_FLAG_FCOE_ENABLED |
10168#endif
60ea5f83
JB		 10169 I40E_FLAG_FD_SB_ENABLED |
10170 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10171 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10172 I40E_FLAG_SRIOV_ENABLED |
10173 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10174 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10175 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10176 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10177 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10178 /* one qp for PF */
acd65448 10179 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10180 queues_left -= pf->num_lan_qps;
10181
10182 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10183#ifdef I40E_FCOE
10184 I40E_FLAG_FCOE_ENABLED |
10185#endif
9aa7e935
FZ		 10186 I40E_FLAG_FD_SB_ENABLED |
10187 I40E_FLAG_FD_ATR_ENABLED |
10188 I40E_FLAG_DCB_ENABLED |
10189 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10190 } else {
cbf61325 10191 /* Not enough queues for all TCs */
4d9b6043 10192 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10193 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10194 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10195 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10196 }
9a3bd2f1
ASJ		 10197 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10198 num_online_cpus());
10199 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10200 pf->hw.func_caps.num_tx_qp);
10201
cbf61325
ASJ		 10202 queues_left -= pf->num_lan_qps;
10203 }
10204
38e00438
VD		 10205#ifdef I40E_FCOE
10206 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10207 if (I40E_DEFAULT_FCOE <= queues_left) {
10208 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10209 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10210 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10211 } else {
10212 pf->num_fcoe_qps = 0;
10213 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10214 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10215 }
10216
10217 queues_left -= pf->num_fcoe_qps;
10218 }
10219
10220#endif
cbf61325
ASJ		 10221 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10222 if (queues_left > 1) {
10223 queues_left -= 1; /* save 1 queue for FD */
10224 } else {
10225 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10226 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10227 }
41c445ff
JB		 10228 }
10229
10230 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10231 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10232 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10233 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10234 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10235 }
10236
10237 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10238 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10239 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10240 (queues_left / pf->num_vmdq_qps));
10241 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10242 }
10243
f8ff1464 10244 pf->queues_left = queues_left;
8279e495
NP		 10245 dev_dbg(&pf->pdev->dev,
10246 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10247 pf->hw.func_caps.num_tx_qp,
10248 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10249 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10250 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10251 queues_left);
38e00438 10252#ifdef I40E_FCOE
8279e495 10253 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10254#endif
41c445ff
JB		 10255}
10256
10257/**
10258 * i40e_setup_pf_filter_control - Setup PF static filter control
10259 * @pf: PF to be setup
10260 *
b40c82e6 10261 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10262 * settings. If PE/FCoE are enabled then it will also set the per PF
10263 * based filter sizes required for them. It also enables Flow director,
10264 * ethertype and macvlan type filter settings for the pf.
10265 *
10266 * Returns 0 on success, negative on failure
10267 **/
10268static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10269{
10270 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10271
10272 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10273
10274 /* Flow Director is enabled */
60ea5f83 10275 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10276 settings->enable_fdir = true;
10277
10278 /* Ethtype and MACVLAN filters enabled for PF */
10279 settings->enable_ethtype = true;
10280 settings->enable_macvlan = true;
10281
10282 if (i40e_set_filter_control(&pf->hw, settings))
10283 return -ENOENT;
10284
10285 return 0;
10286}
10287
0c22b3dd 10288#define INFO_STRING_LEN 255
7fd89545 10289#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10290static void i40e_print_features(struct i40e_pf *pf)
10291{
10292 struct i40e_hw *hw = &pf->hw;
10293 char *buf, *string;
7fd89545 10294 int i = 0;
0c22b3dd
JB		 10295
10296 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
10297 if (!string) {
10298 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
10299 return;
10300 }
10301
10302 buf = string;
10303
7fd89545 10304 i += snprintf(&buf[i], REMAIN(i), "Features: PF-id[%d] ", hw->pf_id);
0c22b3dd 10305#ifdef CONFIG_PCI_IOV
7fd89545 10306 i += snprintf(&buf[i], REMAIN(i), "VFs: %d ", pf->num_req_vfs);
0c22b3dd 10307#endif
7fd89545
SN		 10308 i += snprintf(&buf[i], REMAIN(i), "VSIs: %d QP: %d RX: %s ",
10309 pf->hw.func_caps.num_vsis,
10310 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10311 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10312
10313 if (pf->flags & I40E_FLAG_RSS_ENABLED)
7fd89545 10314 i += snprintf(&buf[i], REMAIN(i), "RSS ");
0c22b3dd 10315 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
7fd89545 10316 i += snprintf(&buf[i], REMAIN(i), "FD_ATR ");
c6423ff1 10317 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7fd89545
SN		 10318 i += snprintf(&buf[i], REMAIN(i), "FD_SB ");
10319 i += snprintf(&buf[i], REMAIN(i), "NTUPLE ");
c6423ff1 10320 }
4d9b6043 10321 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
7fd89545 10322 i += snprintf(&buf[i], REMAIN(i), "DCB ");
ce6fcb3f 10323#if IS_ENABLED(CONFIG_VXLAN)
7fd89545 10324 i += snprintf(&buf[i], REMAIN(i), "VxLAN ");
ce6fcb3f 10325#endif
0c22b3dd 10326 if (pf->flags & I40E_FLAG_PTP)
7fd89545 10327 i += snprintf(&buf[i], REMAIN(i), "PTP ");
38e00438
VD		 10328#ifdef I40E_FCOE
10329 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
7fd89545 10330 i += snprintf(&buf[i], REMAIN(i), "FCOE ");
38e00438 10331#endif
6dec1017 10332 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
7fd89545 10333 i += snprintf(&buf[i], REMAIN(i), "VEPA ");
6dec1017
SN		 10334 else
10335 buf += sprintf(buf, "VEPA ");
0c22b3dd 10336
0c22b3dd
JB		 10337 dev_info(&pf->pdev->dev, "%s\n", string);
10338 kfree(string);
7fd89545 10339 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10340}
10341
41c445ff
JB		 10342/**
10343 * i40e_probe - Device initialization routine
10344 * @pdev: PCI device information struct
10345 * @ent: entry in i40e_pci_tbl
10346 *
b40c82e6
JK		 10347 * i40e_probe initializes a PF identified by a pci_dev structure.
10348 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10349 * and a hardware reset occur.
10350 *
10351 * Returns 0 on success, negative on failure
10352 **/
10353static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10354{
e827845c 10355 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10356 struct i40e_pf *pf;
10357 struct i40e_hw *hw;
93cd765b 10358 static u16 pfs_found;
1d5109d1 10359 u16 wol_nvm_bits;
d4dfb81a 10360 u16 link_status;
6f66a484 10361 int err;
41c445ff 10362 u32 len;
4f2f017c 10363 u32 val;
8a9eb7d3 10364 u32 i;
58fc3267 10365 u8 set_fc_aq_fail;
41c445ff
JB		 10366
10367 err = pci_enable_device_mem(pdev);
10368 if (err)
10369 return err;
10370
10371 /* set up for high or low dma */
6494294f 10372 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10373 if (err) {
e3e3bfdd
JS		 10374 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10375 if (err) {
10376 dev_err(&pdev->dev,
10377 "DMA configuration failed: 0x%x\n", err);
10378 goto err_dma;
10379 }
41c445ff
JB		 10380 }
10381
10382 /* set up pci connections */
10383 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10384 IORESOURCE_MEM), i40e_driver_name);
10385 if (err) {
10386 dev_info(&pdev->dev,
10387 "pci_request_selected_regions failed %d\n", err);
10388 goto err_pci_reg;
10389 }
10390
10391 pci_enable_pcie_error_reporting(pdev);
10392 pci_set_master(pdev);
10393
10394 /* Now that we have a PCI connection, we need to do the
10395 * low level device setup. This is primarily setting up
10396 * the Admin Queue structures and then querying for the
10397 * device's current profile information.
10398 */
10399 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10400 if (!pf) {
10401 err = -ENOMEM;
10402 goto err_pf_alloc;
10403 }
10404 pf->next_vsi = 0;
10405 pf->pdev = pdev;
10406 set_bit(__I40E_DOWN, &pf->state);
10407
10408 hw = &pf->hw;
10409 hw->back = pf;
232f4706 10410
2ac8b675
SN		 10411 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10412 I40E_MAX_CSR_SPACE);
232f4706 10413
2ac8b675 10414 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10415 if (!hw->hw_addr) {
10416 err = -EIO;
10417 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10418 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10419 pf->ioremap_len, err);
41c445ff
JB		 10420 goto err_ioremap;
10421 }
10422 hw->vendor_id = pdev->vendor;
10423 hw->device_id = pdev->device;
10424 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10425 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10426 hw->subsystem_device_id = pdev->subsystem_device;
10427 hw->bus.device = PCI_SLOT(pdev->devfn);
10428 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10429 pf->instance = pfs_found;
41c445ff 10430
5b5faa43
SN		 10431 if (debug != -1) {
10432 pf->msg_enable = pf->hw.debug_mask;
10433 pf->msg_enable = debug;
10434 }
10435
7134f9ce
JB		 10436 /* do a special CORER for clearing PXE mode once at init */
10437 if (hw->revision_id == 0 &&
10438 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10439 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10440 i40e_flush(hw);
10441 msleep(200);
10442 pf->corer_count++;
10443
10444 i40e_clear_pxe_mode(hw);
10445 }
10446
41c445ff 10447 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10448 i40e_clear_hw(hw);
41c445ff
JB		 10449 err = i40e_pf_reset(hw);
10450 if (err) {
10451 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10452 goto err_pf_reset;
10453 }
10454 pf->pfr_count++;
10455
10456 hw->aq.num_arq_entries = I40E_AQ_LEN;
10457 hw->aq.num_asq_entries = I40E_AQ_LEN;
10458 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10459 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10460 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10461
b294ac70 10462 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10463 "%s-%s:misc",
10464 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10465
10466 err = i40e_init_shared_code(hw);
10467 if (err) {
b2a75c58
ASJ		 10468 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10469 err);
41c445ff
JB		 10470 goto err_pf_reset;
10471 }
10472
d52c20b7
JB		 10473 /* set up a default setting for link flow control */
10474 pf->hw.fc.requested_mode = I40E_FC_NONE;
10475
41c445ff 10476 err = i40e_init_adminq(hw);
2b2426a7
CW		 10477 if (err) {
10478 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10479 dev_info(&pdev->dev,
10480 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10481 else
10482 dev_info(&pdev->dev,
10483 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10484
10485 goto err_pf_reset;
10486 }
f0b44440 10487
6dec1017
SN		 10488 /* provide nvm, fw, api versions */
10489 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10490 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10491 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10492 i40e_nvm_version_str(hw));
f0b44440 10493
7aa67613
CS		 10494 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10495 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10496 dev_info(&pdev->dev,
7aa67613
CS		 10497 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10498 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10499 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10500 dev_info(&pdev->dev,
7aa67613 10501 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10502
4eb3f768
SN		 10503 i40e_verify_eeprom(pf);
10504
2c5fe33b
JB		 10505 /* Rev 0 hardware was never productized */
10506 if (hw->revision_id < 1)
10507 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10508
6ff4ef86 10509 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10510 err = i40e_get_capabilities(pf);
10511 if (err)
10512 goto err_adminq_setup;
10513
10514 err = i40e_sw_init(pf);
10515 if (err) {
10516 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10517 goto err_sw_init;
10518 }
10519
10520 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10521 hw->func_caps.num_rx_qp,
10522 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10523 if (err) {
10524 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10525 goto err_init_lan_hmc;
10526 }
10527
10528 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10529 if (err) {
10530 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10531 err = -ENOENT;
10532 goto err_configure_lan_hmc;
10533 }
10534
b686ece5
NP		 10535 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10536 * Ignore error return codes because if it was already disabled via
10537 * hardware settings this will fail
10538 */
10539 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10540 (pf->hw.aq.fw_maj_ver < 4)) {
10541 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10542 i40e_aq_stop_lldp(hw, true, NULL);
10543 }
10544
41c445ff 10545 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10546 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10547 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10548 err = -EIO;
10549 goto err_mac_addr;
10550 }
10551 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10552 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10553 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10554 if (is_valid_ether_addr(hw->mac.port_addr))
10555 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10556#ifdef I40E_FCOE
10557 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10558 if (err)
10559 dev_info(&pdev->dev,
10560 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10561 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10562 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10563 hw->mac.san_addr);
10564 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10565 }
10566 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10567#endif /* I40E_FCOE */
41c445ff
JB		 10568
10569 pci_set_drvdata(pdev, pf);
10570 pci_save_state(pdev);
4e3b35b0
NP		 10571#ifdef CONFIG_I40E_DCB
10572 err = i40e_init_pf_dcb(pf);
10573 if (err) {
aebfc816 10574 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10575 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10576 /* Continue without DCB enabled */
4e3b35b0
NP		 10577 }
10578#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10579
10580 /* set up periodic task facility */
10581 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10582 pf->service_timer_period = HZ;
10583
10584 INIT_WORK(&pf->service_task, i40e_service_task);
10585 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10586 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10587
1d5109d1
SN		 10588 /* NVM bit on means WoL disabled for the port */
10589 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10590 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10591 pf->wol_en = false;
10592 else
10593 pf->wol_en = true;
8e2773ae
SN		 10594 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10595
41c445ff
JB		 10596 /* set up the main switch operations */
10597 i40e_determine_queue_usage(pf);
c1147280
JB		 10598 err = i40e_init_interrupt_scheme(pf);
10599 if (err)
10600 goto err_switch_setup;
41c445ff 10601
505682cd
MW		 10602 /* The number of VSIs reported by the FW is the minimum guaranteed
10603 * to us; HW supports far more and we share the remaining pool with
10604 * the other PFs. We allocate space for more than the guarantee with
10605 * the understanding that we might not get them all later.
41c445ff 10606 */
505682cd
MW		 10607 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10608 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10609 else
10610 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10611
10612 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10613 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10614 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10615 if (!pf->vsi) {
10616 err = -ENOMEM;
41c445ff 10617 goto err_switch_setup;
ed87ac09 10618 }
41c445ff 10619
fa11cb3d
ASJ		 10620#ifdef CONFIG_PCI_IOV
10621 /* prep for VF support */
10622 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10623 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10624 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10625 if (pci_num_vf(pdev))
10626 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10627 }
10628#endif
bc7d338f 10629 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10630 if (err) {
10631 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10632 goto err_vsis;
10633 }
58fc3267
HZ		 10634
10635 /* Make sure flow control is set according to current settings */
10636 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10637 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10638 dev_dbg(&pf->pdev->dev,
10639 "Set fc with err %s aq_err %s on get_phy_cap\n",
10640 i40e_stat_str(hw, err),
10641 i40e_aq_str(hw, hw->aq.asq_last_status));
10642 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10643 dev_dbg(&pf->pdev->dev,
10644 "Set fc with err %s aq_err %s on set_phy_config\n",
10645 i40e_stat_str(hw, err),
10646 i40e_aq_str(hw, hw->aq.asq_last_status));
10647 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10648 dev_dbg(&pf->pdev->dev,
10649 "Set fc with err %s aq_err %s on get_link_info\n",
10650 i40e_stat_str(hw, err),
10651 i40e_aq_str(hw, hw->aq.asq_last_status));
10652
8a9eb7d3 10653 /* if FDIR VSI was set up, start it now */
505682cd 10654 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10655 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10656 i40e_vsi_open(pf->vsi[i]);
10657 break;
10658 }
10659 }
41c445ff 10660
7e2453fe
JB		 10661 /* driver is only interested in link up/down and module qualification
10662 * reports from firmware
10663 */
10664 err = i40e_aq_set_phy_int_mask(&pf->hw,
10665 I40E_AQ_EVENT_LINK_UPDOWN |
10666 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10667 if (err)
f1c7e72e
SN		 10668 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10669 i40e_stat_str(&pf->hw, err),
10670 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10671
4f2f017c
ASJ		 10672 /* Reconfigure hardware for allowing smaller MSS in the case
10673 * of TSO, so that we avoid the MDD being fired and causing
10674 * a reset in the case of small MSS+TSO.
10675 */
10676 val = rd32(hw, I40E_REG_MSS);
10677 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10678 val &= ~I40E_REG_MSS_MIN_MASK;
10679 val |= I40E_64BYTE_MSS;
10680 wr32(hw, I40E_REG_MSS, val);
10681 }
10682
025b4a54
ASJ		 10683 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10684 (pf->hw.aq.fw_maj_ver < 4)) {
10685 msleep(75);
10686 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10687 if (err)
f1c7e72e
SN		 10688 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10689 i40e_stat_str(&pf->hw, err),
10690 i40e_aq_str(&pf->hw,
10691 pf->hw.aq.asq_last_status));
cafa2ee6 10692 }
41c445ff
JB		 10693 /* The main driver is (mostly) up and happy. We need to set this state
10694 * before setting up the misc vector or we get a race and the vector
10695 * ends up disabled forever.
10696 */
10697 clear_bit(__I40E_DOWN, &pf->state);
10698
10699 /* In case of MSIX we are going to setup the misc vector right here
10700 * to handle admin queue events etc. In case of legacy and MSI
10701 * the misc functionality and queue processing is combined in
10702 * the same vector and that gets setup at open.
10703 */
10704 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10705 err = i40e_setup_misc_vector(pf);
10706 if (err) {
10707 dev_info(&pdev->dev,
10708 "setup of misc vector failed: %d\n", err);
10709 goto err_vsis;
10710 }
10711 }
10712
df805f62 10713#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10714 /* prep for VF support */
10715 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10716 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10717 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10718 u32 val;
10719
10720 /* disable link interrupts for VFs */
10721 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10722 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10723 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10724 i40e_flush(hw);
4aeec010
MW		 10725
10726 if (pci_num_vf(pdev)) {
10727 dev_info(&pdev->dev,
10728 "Active VFs found, allocating resources.\n");
10729 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10730 if (err)
10731 dev_info(&pdev->dev,
10732 "Error %d allocating resources for existing VFs\n",
10733 err);
10734 }
41c445ff 10735 }
df805f62 10736#endif /* CONFIG_PCI_IOV */
41c445ff 10737
93cd765b
ASJ		 10738 pfs_found++;
10739
41c445ff
JB		 10740 i40e_dbg_pf_init(pf);
10741
10742 /* tell the firmware that we're starting */
44033fac 10743 i40e_send_version(pf);
41c445ff
JB		 10744
10745 /* since everything's happy, start the service_task timer */
10746 mod_timer(&pf->service_timer,
10747 round_jiffies(jiffies + pf->service_timer_period));
10748
38e00438
VD		 10749#ifdef I40E_FCOE
10750 /* create FCoE interface */
10751 i40e_fcoe_vsi_setup(pf);
10752
10753#endif
3fced535
ASJ		 10754#define PCI_SPEED_SIZE 8
10755#define PCI_WIDTH_SIZE 8
10756 /* Devices on the IOSF bus do not have this information
10757 * and will report PCI Gen 1 x 1 by default so don't bother
10758 * checking them.
10759 */
10760 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10761 char speed[PCI_SPEED_SIZE] = "Unknown";
10762 char width[PCI_WIDTH_SIZE] = "Unknown";
10763
10764 /* Get the negotiated link width and speed from PCI config
10765 * space
10766 */
10767 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10768 &link_status);
10769
10770 i40e_set_pci_config_data(hw, link_status);
10771
10772 switch (hw->bus.speed) {
10773 case i40e_bus_speed_8000:
10774 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10775 case i40e_bus_speed_5000:
10776 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10777 case i40e_bus_speed_2500:
10778 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10779 default:
10780 break;
10781 }
10782 switch (hw->bus.width) {
10783 case i40e_bus_width_pcie_x8:
10784 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10785 case i40e_bus_width_pcie_x4:
10786 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10787 case i40e_bus_width_pcie_x2:
10788 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10789 case i40e_bus_width_pcie_x1:
10790 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10791 default:
10792 break;
10793 }
10794
10795 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10796 speed, width);
10797
10798 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10799 hw->bus.speed < i40e_bus_speed_8000) {
10800 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10801 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10802 }
d4dfb81a
CS		 10803 }
10804
e827845c
CS		 10805 /* get the requested speeds from the fw */
10806 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10807 if (err)
8279e495
NP		 10808 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10809 i40e_stat_str(&pf->hw, err),
10810 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10811 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10812
fc72dbce
CS		 10813 /* get the supported phy types from the fw */
10814 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10815 if (err)
10816 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10817 i40e_stat_str(&pf->hw, err),
10818 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10819 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10820
e7358f54
ASJ		 10821 /* Add a filter to drop all Flow control frames from any VSI from being
10822 * transmitted. By doing so we stop a malicious VF from sending out
10823 * PAUSE or PFC frames and potentially controlling traffic for other
10824 * PF/VF VSIs.
10825 * The FW can still send Flow control frames if enabled.
10826 */
10827 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
10828 pf->main_vsi_seid);
10829
0c22b3dd
JB		 10830 /* print a string summarizing features */
10831 i40e_print_features(pf);
10832
41c445ff
JB		 10833 return 0;
10834
10835 /* Unwind what we've done if something failed in the setup */
10836err_vsis:
10837 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10838 i40e_clear_interrupt_scheme(pf);
10839 kfree(pf->vsi);
04b03013
SN		 10840err_switch_setup:
10841 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10842 del_timer_sync(&pf->service_timer);
10843err_mac_addr:
10844err_configure_lan_hmc:
10845 (void)i40e_shutdown_lan_hmc(hw);
10846err_init_lan_hmc:
10847 kfree(pf->qp_pile);
41c445ff
JB		 10848err_sw_init:
10849err_adminq_setup:
10850 (void)i40e_shutdown_adminq(hw);
10851err_pf_reset:
10852 iounmap(hw->hw_addr);
10853err_ioremap:
10854 kfree(pf);
10855err_pf_alloc:
10856 pci_disable_pcie_error_reporting(pdev);
10857 pci_release_selected_regions(pdev,
10858 pci_select_bars(pdev, IORESOURCE_MEM));
10859err_pci_reg:
10860err_dma:
10861 pci_disable_device(pdev);
10862 return err;
10863}
10864
10865/**
10866 * i40e_remove - Device removal routine
10867 * @pdev: PCI device information struct
10868 *
10869 * i40e_remove is called by the PCI subsystem to alert the driver
10870 * that is should release a PCI device. This could be caused by a
10871 * Hot-Plug event, or because the driver is going to be removed from
10872 * memory.
10873 **/
10874static void i40e_remove(struct pci_dev *pdev)
10875{
10876 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 10877 struct i40e_hw *hw = &pf->hw;
41c445ff 10878 i40e_status ret_code;
41c445ff
JB		 10879 int i;
10880
10881 i40e_dbg_pf_exit(pf);
10882
beb0dff1
JK		 10883 i40e_ptp_stop(pf);
10884
bcab2db9
CW		 10885 /* Disable RSS in hw */
10886 wr32(hw, I40E_PFQF_HENA(0), 0);
10887 wr32(hw, I40E_PFQF_HENA(1), 0);
10888
41c445ff
JB		 10889 /* no more scheduling of any task */
10890 set_bit(__I40E_DOWN, &pf->state);
10891 del_timer_sync(&pf->service_timer);
10892 cancel_work_sync(&pf->service_task);
33c62b34 10893 i40e_fdir_teardown(pf);
41c445ff 10894
eb2d80bc
MW		 10895 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10896 i40e_free_vfs(pf);
10897 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10898 }
10899
41c445ff
JB		 10900 i40e_fdir_teardown(pf);
10901
10902 /* If there is a switch structure or any orphans, remove them.
10903 * This will leave only the PF's VSI remaining.
10904 */
10905 for (i = 0; i < I40E_MAX_VEB; i++) {
10906 if (!pf->veb[i])
10907 continue;
10908
10909 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10910 pf->veb[i]->uplink_seid == 0)
10911 i40e_switch_branch_release(pf->veb[i]);
10912 }
10913
10914 /* Now we can shutdown the PF's VSI, just before we kill
10915 * adminq and hmc.
10916 */
10917 if (pf->vsi[pf->lan_vsi])
10918 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10919
41c445ff 10920 /* shutdown and destroy the HMC */
60442dea
SN		 10921 if (pf->hw.hmc.hmc_obj) {
10922 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10923 if (ret_code)
10924 dev_warn(&pdev->dev,
10925 "Failed to destroy the HMC resources: %d\n",
10926 ret_code);
10927 }
41c445ff
JB		 10928
10929 /* shutdown the adminq */
41c445ff
JB		 10930 ret_code = i40e_shutdown_adminq(&pf->hw);
10931 if (ret_code)
10932 dev_warn(&pdev->dev,
10933 "Failed to destroy the Admin Queue resources: %d\n",
10934 ret_code);
10935
10936 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10937 i40e_clear_interrupt_scheme(pf);
505682cd 10938 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10939 if (pf->vsi[i]) {
10940 i40e_vsi_clear_rings(pf->vsi[i]);
10941 i40e_vsi_clear(pf->vsi[i]);
10942 pf->vsi[i] = NULL;
10943 }
10944 }
10945
10946 for (i = 0; i < I40E_MAX_VEB; i++) {
10947 kfree(pf->veb[i]);
10948 pf->veb[i] = NULL;
10949 }
10950
10951 kfree(pf->qp_pile);
41c445ff
JB		 10952 kfree(pf->vsi);
10953
41c445ff
JB		 10954 iounmap(pf->hw.hw_addr);
10955 kfree(pf);
10956 pci_release_selected_regions(pdev,
10957 pci_select_bars(pdev, IORESOURCE_MEM));
10958
10959 pci_disable_pcie_error_reporting(pdev);
10960 pci_disable_device(pdev);
10961}
10962
10963/**
10964 * i40e_pci_error_detected - warning that something funky happened in PCI land
10965 * @pdev: PCI device information struct
10966 *
10967 * Called to warn that something happened and the error handling steps
10968 * are in progress. Allows the driver to quiesce things, be ready for
10969 * remediation.
10970 **/
10971static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10972 enum pci_channel_state error)
10973{
10974 struct i40e_pf *pf = pci_get_drvdata(pdev);
10975
10976 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10977
10978 /* shutdown all operations */
9007bccd
SN		 10979 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10980 rtnl_lock();
10981 i40e_prep_for_reset(pf);
10982 rtnl_unlock();
10983 }
41c445ff
JB		 10984
10985 /* Request a slot reset */
10986 return PCI_ERS_RESULT_NEED_RESET;
10987}
10988
10989/**
10990 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10991 * @pdev: PCI device information struct
10992 *
10993 * Called to find if the driver can work with the device now that
10994 * the pci slot has been reset. If a basic connection seems good
10995 * (registers are readable and have sane content) then return a
10996 * happy little PCI_ERS_RESULT_xxx.
10997 **/
10998static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10999{
11000 struct i40e_pf *pf = pci_get_drvdata(pdev);
11001 pci_ers_result_t result;
11002 int err;
11003 u32 reg;
11004
fb43201f 11005 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11006 if (pci_enable_device_mem(pdev)) {
11007 dev_info(&pdev->dev,
11008 "Cannot re-enable PCI device after reset.\n");
11009 result = PCI_ERS_RESULT_DISCONNECT;
11010 } else {
11011 pci_set_master(pdev);
11012 pci_restore_state(pdev);
11013 pci_save_state(pdev);
11014 pci_wake_from_d3(pdev, false);
11015
11016 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11017 if (reg == 0)
11018 result = PCI_ERS_RESULT_RECOVERED;
11019 else
11020 result = PCI_ERS_RESULT_DISCONNECT;
11021 }
11022
11023 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11024 if (err) {
11025 dev_info(&pdev->dev,
11026 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11027 err);
11028 /* non-fatal, continue */
11029 }
11030
11031 return result;
11032}
11033
11034/**
11035 * i40e_pci_error_resume - restart operations after PCI error recovery
11036 * @pdev: PCI device information struct
11037 *
11038 * Called to allow the driver to bring things back up after PCI error
11039 * and/or reset recovery has finished.
11040 **/
11041static void i40e_pci_error_resume(struct pci_dev *pdev)
11042{
11043 struct i40e_pf *pf = pci_get_drvdata(pdev);
11044
fb43201f 11045 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11046 if (test_bit(__I40E_SUSPENDED, &pf->state))
11047 return;
11048
11049 rtnl_lock();
41c445ff 11050 i40e_handle_reset_warning(pf);
4c4935a9 11051 rtnl_unlock();
9007bccd
SN		 11052}
11053
11054/**
11055 * i40e_shutdown - PCI callback for shutting down
11056 * @pdev: PCI device information struct
11057 **/
11058static void i40e_shutdown(struct pci_dev *pdev)
11059{
11060 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11061 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11062
11063 set_bit(__I40E_SUSPENDED, &pf->state);
11064 set_bit(__I40E_DOWN, &pf->state);
11065 rtnl_lock();
11066 i40e_prep_for_reset(pf);
11067 rtnl_unlock();
11068
8e2773ae
SN		 11069 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11070 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11071
02b42498
CS		 11072 del_timer_sync(&pf->service_timer);
11073 cancel_work_sync(&pf->service_task);
11074 i40e_fdir_teardown(pf);
11075
11076 rtnl_lock();
11077 i40e_prep_for_reset(pf);
11078 rtnl_unlock();
11079
11080 wr32(hw, I40E_PFPM_APM,
11081 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11082 wr32(hw, I40E_PFPM_WUFC,
11083 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11084
e147758d
SN		 11085 i40e_clear_interrupt_scheme(pf);
11086
9007bccd 11087 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11088 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11089 pci_set_power_state(pdev, PCI_D3hot);
11090 }
11091}
11092
11093#ifdef CONFIG_PM
11094/**
11095 * i40e_suspend - PCI callback for moving to D3
11096 * @pdev: PCI device information struct
11097 **/
11098static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11099{
11100 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11101 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11102
11103 set_bit(__I40E_SUSPENDED, &pf->state);
11104 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11105
9007bccd
SN		 11106 rtnl_lock();
11107 i40e_prep_for_reset(pf);
11108 rtnl_unlock();
11109
8e2773ae
SN		 11110 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11111 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11112
11113 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11114 pci_set_power_state(pdev, PCI_D3hot);
11115
11116 return 0;
41c445ff
JB		 11117}
11118
9007bccd
SN		 11119/**
11120 * i40e_resume - PCI callback for waking up from D3
11121 * @pdev: PCI device information struct
11122 **/
11123static int i40e_resume(struct pci_dev *pdev)
11124{
11125 struct i40e_pf *pf = pci_get_drvdata(pdev);
11126 u32 err;
11127
11128 pci_set_power_state(pdev, PCI_D0);
11129 pci_restore_state(pdev);
11130 /* pci_restore_state() clears dev->state_saves, so
11131 * call pci_save_state() again to restore it.
11132 */
11133 pci_save_state(pdev);
11134
11135 err = pci_enable_device_mem(pdev);
11136 if (err) {
fb43201f 11137 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11138 return err;
11139 }
11140 pci_set_master(pdev);
11141
11142 /* no wakeup events while running */
11143 pci_wake_from_d3(pdev, false);
11144
11145 /* handling the reset will rebuild the device state */
11146 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11147 clear_bit(__I40E_DOWN, &pf->state);
11148 rtnl_lock();
11149 i40e_reset_and_rebuild(pf, false);
11150 rtnl_unlock();
11151 }
11152
11153 return 0;
11154}
11155
11156#endif
41c445ff
JB		 11157static const struct pci_error_handlers i40e_err_handler = {
11158 .error_detected = i40e_pci_error_detected,
11159 .slot_reset = i40e_pci_error_slot_reset,
11160 .resume = i40e_pci_error_resume,
11161};
11162
11163static struct pci_driver i40e_driver = {
11164 .name = i40e_driver_name,
11165 .id_table = i40e_pci_tbl,
11166 .probe = i40e_probe,
11167 .remove = i40e_remove,
9007bccd
SN		 11168#ifdef CONFIG_PM
11169 .suspend = i40e_suspend,
11170 .resume = i40e_resume,
11171#endif
11172 .shutdown = i40e_shutdown,
41c445ff
JB		 11173 .err_handler = &i40e_err_handler,
11174 .sriov_configure = i40e_pci_sriov_configure,
11175};
11176
11177/**
11178 * i40e_init_module - Driver registration routine
11179 *
11180 * i40e_init_module is the first routine called when the driver is
11181 * loaded. All it does is register with the PCI subsystem.
11182 **/
11183static int __init i40e_init_module(void)
11184{
11185 pr_info("%s: %s - version %s\n", i40e_driver_name,
11186 i40e_driver_string, i40e_driver_version_str);
11187 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11188
41c445ff
JB		 11189 i40e_dbg_init();
11190 return pci_register_driver(&i40e_driver);
11191}
11192module_init(i40e_init_module);
11193
11194/**
11195 * i40e_exit_module - Driver exit cleanup routine
11196 *
11197 * i40e_exit_module is called just before the driver is removed
11198 * from memory.
11199 **/
11200static void __exit i40e_exit_module(void)
11201{
11202 pci_unregister_driver(&i40e_driver);
11203 i40e_dbg_exit();
11204}
11205module_exit(i40e_exit_module);
Linux kernel - Deliverables
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