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i40e/i40evf: clean up some code
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
f91638af 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 85 /* required last entry */
86 {0, }
87};
88MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
89
90#define I40E_MAX_VF_COUNT 128
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
96MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100/**
101 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
102 * @hw: pointer to the HW structure
103 * @mem: ptr to mem struct to fill out
104 * @size: size of memory requested
105 * @alignment: what to align the allocation to
106 **/
107int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
108 u64 size, u32 alignment)
109{
110 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
111
112 mem->size = ALIGN(size, alignment);
113 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
114 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 115 if (!mem->va)
116 return -ENOMEM;
41c445ff 117
93bc73b8 118 return 0;
41c445ff
JB		 119}
120
121/**
122 * i40e_free_dma_mem_d - OS specific memory free for shared code
123 * @hw: pointer to the HW structure
124 * @mem: ptr to mem struct to free
125 **/
126int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
127{
128 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
129
130 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
131 mem->va = NULL;
132 mem->pa = 0;
133 mem->size = 0;
134
135 return 0;
136}
137
138/**
139 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to fill out
142 * @size: size of memory requested
143 **/
144int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
145 u32 size)
146{
147 mem->size = size;
148 mem->va = kzalloc(size, GFP_KERNEL);
149
93bc73b8
JB		 150 if (!mem->va)
151 return -ENOMEM;
41c445ff 152
93bc73b8 153 return 0;
41c445ff
JB		 154}
155
156/**
157 * i40e_free_virt_mem_d - OS specific memory free for shared code
158 * @hw: pointer to the HW structure
159 * @mem: ptr to mem struct to free
160 **/
161int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
162{
163 /* it's ok to kfree a NULL pointer */
164 kfree(mem->va);
165 mem->va = NULL;
166 mem->size = 0;
167
168 return 0;
169}
170
171/**
172 * i40e_get_lump - find a lump of free generic resource
173 * @pf: board private structure
174 * @pile: the pile of resource to search
175 * @needed: the number of items needed
176 * @id: an owner id to stick on the items assigned
177 *
178 * Returns the base item index of the lump, or negative for error
179 *
180 * The search_hint trick and lack of advanced fit-finding only work
181 * because we're highly likely to have all the same size lump requests.
182 * Linear search time and any fragmentation should be minimal.
183 **/
184static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
185 u16 needed, u16 id)
186{
187 int ret = -ENOMEM;
ddf434ac 188 int i, j;
41c445ff
JB		 189
190 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
191 dev_info(&pf->pdev->dev,
192 "param err: pile=%p needed=%d id=0x%04x\n",
193 pile, needed, id);
194 return -EINVAL;
195 }
196
197 /* start the linear search with an imperfect hint */
198 i = pile->search_hint;
ddf434ac 199 while (i < pile->num_entries) {
41c445ff
JB		 200 /* skip already allocated entries */
201 if (pile->list[i] & I40E_PILE_VALID_BIT) {
202 i++;
203 continue;
204 }
205
206 /* do we have enough in this lump? */
207 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
208 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
209 break;
210 }
211
212 if (j == needed) {
213 /* there was enough, so assign it to the requestor */
214 for (j = 0; j < needed; j++)
215 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
216 ret = i;
217 pile->search_hint = i + j;
ddf434ac 218 break;
41c445ff 219 }
6995b36c
JB		 220
221 /* not enough, so skip over it and continue looking */
222 i += j;
41c445ff
JB		 223 }
224
225 return ret;
226}
227
228/**
229 * i40e_put_lump - return a lump of generic resource
230 * @pile: the pile of resource to search
231 * @index: the base item index
232 * @id: the owner id of the items assigned
233 *
234 * Returns the count of items in the lump
235 **/
236static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
237{
238 int valid_id = (id | I40E_PILE_VALID_BIT);
239 int count = 0;
240 int i;
241
242 if (!pile || index >= pile->num_entries)
243 return -EINVAL;
244
245 for (i = index;
246 i < pile->num_entries && pile->list[i] == valid_id;
247 i++) {
248 pile->list[i] = 0;
249 count++;
250 }
251
252 if (count && index < pile->search_hint)
253 pile->search_hint = index;
254
255 return count;
256}
257
fdf0e0bf
ASJ		 258/**
259 * i40e_find_vsi_from_id - searches for the vsi with the given id
260 * @pf - the pf structure to search for the vsi
261 * @id - id of the vsi it is searching for
262 **/
263struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
264{
265 int i;
266
267 for (i = 0; i < pf->num_alloc_vsi; i++)
268 if (pf->vsi[i] && (pf->vsi[i]->id == id))
269 return pf->vsi[i];
270
271 return NULL;
272}
273
41c445ff
JB		 274/**
275 * i40e_service_event_schedule - Schedule the service task to wake up
276 * @pf: board private structure
277 *
278 * If not already scheduled, this puts the task into the work queue
279 **/
280static void i40e_service_event_schedule(struct i40e_pf *pf)
281{
282 if (!test_bit(__I40E_DOWN, &pf->state) &&
283 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
284 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
285 schedule_work(&pf->service_task);
286}
287
288/**
289 * i40e_tx_timeout - Respond to a Tx Hang
290 * @netdev: network interface device structure
291 *
292 * If any port has noticed a Tx timeout, it is likely that the whole
293 * device is munged, not just the one netdev port, so go for the full
294 * reset.
295 **/
38e00438
VD		 296#ifdef I40E_FCOE
297void i40e_tx_timeout(struct net_device *netdev)
298#else
41c445ff 299static void i40e_tx_timeout(struct net_device *netdev)
38e00438 300#endif
41c445ff
JB		 301{
302 struct i40e_netdev_priv *np = netdev_priv(netdev);
303 struct i40e_vsi *vsi = np->vsi;
304 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 305 struct i40e_ring *tx_ring = NULL;
306 unsigned int i, hung_queue = 0;
307 u32 head, val;
41c445ff
JB		 308
309 pf->tx_timeout_count++;
310
b03a8c1f
KP		 311 /* find the stopped queue the same way the stack does */
312 for (i = 0; i < netdev->num_tx_queues; i++) {
313 struct netdev_queue *q;
314 unsigned long trans_start;
315
316 q = netdev_get_tx_queue(netdev, i);
317 trans_start = q->trans_start ? : netdev->trans_start;
318 if (netif_xmit_stopped(q) &&
319 time_after(jiffies,
320 (trans_start + netdev->watchdog_timeo))) {
321 hung_queue = i;
322 break;
323 }
324 }
325
326 if (i == netdev->num_tx_queues) {
327 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
328 } else {
329 /* now that we have an index, find the tx_ring struct */
330 for (i = 0; i < vsi->num_queue_pairs; i++) {
331 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
332 if (hung_queue ==
333 vsi->tx_rings[i]->queue_index) {
334 tx_ring = vsi->tx_rings[i];
335 break;
336 }
337 }
338 }
339 }
340
41c445ff 341 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 342 pf->tx_timeout_recovery_level = 1; /* reset after some time */
343 else if (time_before(jiffies,
344 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
345 return; /* don't do any new action before the next timeout */
346
347 if (tx_ring) {
348 head = i40e_get_head(tx_ring);
349 /* Read interrupt register */
350 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
351 val = rd32(&pf->hw,
352 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
353 tx_ring->vsi->base_vector - 1));
354 else
355 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
356
357 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
358 vsi->seid, hung_queue, tx_ring->next_to_clean,
359 head, tx_ring->next_to_use,
360 readl(tx_ring->tail), val);
361 }
362
41c445ff 363 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 364 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
365 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 366
367 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 368 case 1:
369 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
370 break;
371 case 2:
372 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
373 break;
374 case 3:
375 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
376 break;
377 default:
378 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 379 break;
380 }
b03a8c1f 381
41c445ff
JB		 382 i40e_service_event_schedule(pf);
383 pf->tx_timeout_recovery_level++;
384}
385
386/**
387 * i40e_release_rx_desc - Store the new tail and head values
388 * @rx_ring: ring to bump
389 * @val: new head index
390 **/
391static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
392{
393 rx_ring->next_to_use = val;
394
395 /* Force memory writes to complete before letting h/w
396 * know there are new descriptors to fetch. (Only
397 * applicable for weak-ordered memory model archs,
398 * such as IA-64).
399 */
400 wmb();
401 writel(val, rx_ring->tail);
402}
403
404/**
405 * i40e_get_vsi_stats_struct - Get System Network Statistics
406 * @vsi: the VSI we care about
407 *
408 * Returns the address of the device statistics structure.
409 * The statistics are actually updated from the service task.
410 **/
411struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
412{
413 return &vsi->net_stats;
414}
415
416/**
417 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
418 * @netdev: network interface device structure
419 *
420 * Returns the address of the device statistics structure.
421 * The statistics are actually updated from the service task.
422 **/
38e00438
VD		 423#ifdef I40E_FCOE
424struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
425 struct net_device *netdev,
426 struct rtnl_link_stats64 *stats)
427#else
41c445ff
JB		 428static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
429 struct net_device *netdev,
980e9b11 430 struct rtnl_link_stats64 *stats)
38e00438 431#endif
41c445ff
JB		 432{
433 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 434 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 435 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 436 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
437 int i;
438
bc7d338f
ASJ		 439 if (test_bit(__I40E_DOWN, &vsi->state))
440 return stats;
441
3c325ced
JB		 442 if (!vsi->tx_rings)
443 return stats;
444
980e9b11
AD		 445 rcu_read_lock();
446 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 447 u64 bytes, packets;
448 unsigned int start;
449
450 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
451 if (!tx_ring)
452 continue;
453
454 do {
57a7744e 455 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 456 packets = tx_ring->stats.packets;
457 bytes = tx_ring->stats.bytes;
57a7744e 458 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 459
460 stats->tx_packets += packets;
461 stats->tx_bytes += bytes;
462 rx_ring = &tx_ring[1];
463
464 do {
57a7744e 465 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 466 packets = rx_ring->stats.packets;
467 bytes = rx_ring->stats.bytes;
57a7744e 468 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 469
980e9b11
AD		 470 stats->rx_packets += packets;
471 stats->rx_bytes += bytes;
472 }
473 rcu_read_unlock();
474
a5282f44 475 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 476 stats->multicast = vsi_stats->multicast;
477 stats->tx_errors = vsi_stats->tx_errors;
478 stats->tx_dropped = vsi_stats->tx_dropped;
479 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 480 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 481 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
482 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 483
980e9b11 484 return stats;
41c445ff
JB		 485}
486
487/**
488 * i40e_vsi_reset_stats - Resets all stats of the given vsi
489 * @vsi: the VSI to have its stats reset
490 **/
491void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
492{
493 struct rtnl_link_stats64 *ns;
494 int i;
495
496 if (!vsi)
497 return;
498
499 ns = i40e_get_vsi_stats_struct(vsi);
500 memset(ns, 0, sizeof(*ns));
501 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
502 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
503 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 504 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 505 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 506 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 507 sizeof(vsi->rx_rings[i]->stats));
6995b36c 508 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 510 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 511 sizeof(vsi->tx_rings[i]->stats));
512 memset(&vsi->tx_rings[i]->tx_stats, 0,
513 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 514 }
8e9dca53 515 }
41c445ff
JB		 516 vsi->stat_offsets_loaded = false;
517}
518
519/**
b40c82e6 520 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 521 * @pf: the PF to be reset
522 **/
523void i40e_pf_reset_stats(struct i40e_pf *pf)
524{
e91fdf76
SN		 525 int i;
526
41c445ff
JB		 527 memset(&pf->stats, 0, sizeof(pf->stats));
528 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
529 pf->stat_offsets_loaded = false;
e91fdf76
SN		 530
531 for (i = 0; i < I40E_MAX_VEB; i++) {
532 if (pf->veb[i]) {
533 memset(&pf->veb[i]->stats, 0,
534 sizeof(pf->veb[i]->stats));
535 memset(&pf->veb[i]->stats_offsets, 0,
536 sizeof(pf->veb[i]->stats_offsets));
537 pf->veb[i]->stat_offsets_loaded = false;
538 }
539 }
41c445ff
JB		 540}
541
542/**
543 * i40e_stat_update48 - read and update a 48 bit stat from the chip
544 * @hw: ptr to the hardware info
545 * @hireg: the high 32 bit reg to read
546 * @loreg: the low 32 bit reg to read
547 * @offset_loaded: has the initial offset been loaded yet
548 * @offset: ptr to current offset value
549 * @stat: ptr to the stat
550 *
551 * Since the device stats are not reset at PFReset, they likely will not
552 * be zeroed when the driver starts. We'll save the first values read
553 * and use them as offsets to be subtracted from the raw values in order
554 * to report stats that count from zero. In the process, we also manage
555 * the potential roll-over.
556 **/
557static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
558 bool offset_loaded, u64 *offset, u64 *stat)
559{
560 u64 new_data;
561
ab60085e 562 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 563 new_data = rd32(hw, loreg);
564 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
565 } else {
566 new_data = rd64(hw, loreg);
567 }
568 if (!offset_loaded)
569 *offset = new_data;
570 if (likely(new_data >= *offset))
571 *stat = new_data - *offset;
572 else
41a1d04b 573 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 574 *stat &= 0xFFFFFFFFFFFFULL;
575}
576
577/**
578 * i40e_stat_update32 - read and update a 32 bit stat from the chip
579 * @hw: ptr to the hardware info
580 * @reg: the hw reg to read
581 * @offset_loaded: has the initial offset been loaded yet
582 * @offset: ptr to current offset value
583 * @stat: ptr to the stat
584 **/
585static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
586 bool offset_loaded, u64 *offset, u64 *stat)
587{
588 u32 new_data;
589
590 new_data = rd32(hw, reg);
591 if (!offset_loaded)
592 *offset = new_data;
593 if (likely(new_data >= *offset))
594 *stat = (u32)(new_data - *offset);
595 else
41a1d04b 596 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 597}
598
599/**
600 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
601 * @vsi: the VSI to be updated
602 **/
603void i40e_update_eth_stats(struct i40e_vsi *vsi)
604{
605 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
606 struct i40e_pf *pf = vsi->back;
607 struct i40e_hw *hw = &pf->hw;
608 struct i40e_eth_stats *oes;
609 struct i40e_eth_stats *es; /* device's eth stats */
610
611 es = &vsi->eth_stats;
612 oes = &vsi->eth_stats_offsets;
613
614 /* Gather up the stats that the hw collects */
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
618 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
619 vsi->stat_offsets_loaded,
620 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 621 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
622 vsi->stat_offsets_loaded,
623 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
624 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 627
628 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
629 I40E_GLV_GORCL(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->rx_bytes, &es->rx_bytes);
632 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
633 I40E_GLV_UPRCL(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_unicast, &es->rx_unicast);
636 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
637 I40E_GLV_MPRCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->rx_multicast, &es->rx_multicast);
640 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
641 I40E_GLV_BPRCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->rx_broadcast, &es->rx_broadcast);
644
645 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
646 I40E_GLV_GOTCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->tx_bytes, &es->tx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
650 I40E_GLV_UPTCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->tx_unicast, &es->tx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
654 I40E_GLV_MPTCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->tx_multicast, &es->tx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
658 I40E_GLV_BPTCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->tx_broadcast, &es->tx_broadcast);
661 vsi->stat_offsets_loaded = true;
662}
663
664/**
665 * i40e_update_veb_stats - Update Switch component statistics
666 * @veb: the VEB being updated
667 **/
668static void i40e_update_veb_stats(struct i40e_veb *veb)
669{
670 struct i40e_pf *pf = veb->pf;
671 struct i40e_hw *hw = &pf->hw;
672 struct i40e_eth_stats *oes;
673 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 674 struct i40e_veb_tc_stats *veb_oes;
675 struct i40e_veb_tc_stats *veb_es;
676 int i, idx = 0;
41c445ff
JB		 677
678 idx = veb->stats_idx;
679 es = &veb->stats;
680 oes = &veb->stats_offsets;
fe860afb
NP		 681 veb_es = &veb->tc_stats;
682 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 683
684 /* Gather up the stats that the hw collects */
685 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
686 veb->stat_offsets_loaded,
687 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 688 if (hw->revision_id > 0)
689 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_unknown_protocol,
692 &es->rx_unknown_protocol);
41c445ff
JB		 693 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_bytes, &es->rx_bytes);
696 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->rx_unicast, &es->rx_unicast);
699 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->rx_multicast, &es->rx_multicast);
702 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->rx_broadcast, &es->rx_broadcast);
705
706 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_bytes, &es->tx_bytes);
709 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->tx_unicast, &es->tx_unicast);
712 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->tx_multicast, &es->tx_multicast);
715 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
716 veb->stat_offsets_loaded,
717 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 718 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
719 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
720 I40E_GLVEBTC_RPCL(i, idx),
721 veb->stat_offsets_loaded,
722 &veb_oes->tc_rx_packets[i],
723 &veb_es->tc_rx_packets[i]);
724 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
725 I40E_GLVEBTC_RBCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_rx_bytes[i],
728 &veb_es->tc_rx_bytes[i]);
729 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
730 I40E_GLVEBTC_TPCL(i, idx),
731 veb->stat_offsets_loaded,
732 &veb_oes->tc_tx_packets[i],
733 &veb_es->tc_tx_packets[i]);
734 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
735 I40E_GLVEBTC_TBCL(i, idx),
736 veb->stat_offsets_loaded,
737 &veb_oes->tc_tx_bytes[i],
738 &veb_es->tc_tx_bytes[i]);
739 }
41c445ff
JB		 740 veb->stat_offsets_loaded = true;
741}
742
38e00438
VD		 743#ifdef I40E_FCOE
744/**
745 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
746 * @vsi: the VSI that is capable of doing FCoE
747 **/
748static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
749{
750 struct i40e_pf *pf = vsi->back;
751 struct i40e_hw *hw = &pf->hw;
752 struct i40e_fcoe_stats *ofs;
753 struct i40e_fcoe_stats *fs; /* device's eth stats */
754 int idx;
755
756 if (vsi->type != I40E_VSI_FCOE)
757 return;
758
759 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
760 fs = &vsi->fcoe_stats;
761 ofs = &vsi->fcoe_stats_offsets;
762
763 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
772 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
775 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
778 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
781 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->fcoe_last_error, &fs->fcoe_last_error);
784 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
785 vsi->fcoe_stat_offsets_loaded,
786 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
787
788 vsi->fcoe_stat_offsets_loaded = true;
789}
790
791#endif
41c445ff
JB		 792/**
793 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
794 * @pf: the corresponding PF
795 *
796 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
797 **/
798static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
799{
800 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
801 struct i40e_hw_port_stats *nsd = &pf->stats;
802 struct i40e_hw *hw = &pf->hw;
803 u64 xoff = 0;
41c445ff
JB		 804
805 if ((hw->fc.current_mode != I40E_FC_FULL) &&
806 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
807 return;
808
809 xoff = nsd->link_xoff_rx;
810 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
811 pf->stat_offsets_loaded,
812 &osd->link_xoff_rx, &nsd->link_xoff_rx);
813
814 /* No new LFC xoff rx */
815 if (!(nsd->link_xoff_rx - xoff))
816 return;
817
41c445ff
JB		 818}
819
820/**
821 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
822 * @pf: the corresponding PF
823 *
824 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
825 **/
826static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
827{
828 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
829 struct i40e_hw_port_stats *nsd = &pf->stats;
830 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
831 struct i40e_dcbx_config *dcb_cfg;
832 struct i40e_hw *hw = &pf->hw;
b03a8c1f 833 u16 i;
41c445ff
JB		 834 u8 tc;
835
836 dcb_cfg = &hw->local_dcbx_config;
837
e120814d
NP		 838 /* Collect Link XOFF stats when PFC is disabled */
839 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 840 i40e_update_link_xoff_rx(pf);
841 return;
842 }
843
844 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
845 u64 prio_xoff = nsd->priority_xoff_rx[i];
6995b36c 846
41c445ff
JB		 847 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
848 pf->stat_offsets_loaded,
849 &osd->priority_xoff_rx[i],
850 &nsd->priority_xoff_rx[i]);
851
852 /* No new PFC xoff rx */
853 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
854 continue;
855 /* Get the TC for given priority */
856 tc = dcb_cfg->etscfg.prioritytable[i];
857 xoff[tc] = true;
858 }
41c445ff
JB		 859}
860
861/**
7812fddc 862 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 863 * @vsi: the VSI to be updated
864 *
865 * There are a few instances where we store the same stat in a
866 * couple of different structs. This is partly because we have
867 * the netdev stats that need to be filled out, which is slightly
868 * different from the "eth_stats" defined by the chip and used in
7812fddc 869 * VF communications. We sort it out here.
41c445ff 870 **/
7812fddc 871static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 872{
873 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 874 struct rtnl_link_stats64 *ons;
875 struct rtnl_link_stats64 *ns; /* netdev stats */
876 struct i40e_eth_stats *oes;
877 struct i40e_eth_stats *es; /* device's eth stats */
878 u32 tx_restart, tx_busy;
bf00b376 879 struct i40e_ring *p;
41c445ff 880 u32 rx_page, rx_buf;
bf00b376
AA		 881 u64 bytes, packets;
882 unsigned int start;
2fc3d715 883 u64 tx_linearize;
41c445ff
JB		 884 u64 rx_p, rx_b;
885 u64 tx_p, tx_b;
41c445ff
JB		 886 u16 q;
887
888 if (test_bit(__I40E_DOWN, &vsi->state) ||
889 test_bit(__I40E_CONFIG_BUSY, &pf->state))
890 return;
891
892 ns = i40e_get_vsi_stats_struct(vsi);
893 ons = &vsi->net_stats_offsets;
894 es = &vsi->eth_stats;
895 oes = &vsi->eth_stats_offsets;
896
897 /* Gather up the netdev and vsi stats that the driver collects
898 * on the fly during packet processing
899 */
900 rx_b = rx_p = 0;
901 tx_b = tx_p = 0;
2fc3d715 902 tx_restart = tx_busy = tx_linearize = 0;
41c445ff
JB		 903 rx_page = 0;
904 rx_buf = 0;
980e9b11 905 rcu_read_lock();
41c445ff 906 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 907 /* locate Tx ring */
908 p = ACCESS_ONCE(vsi->tx_rings[q]);
909
910 do {
57a7744e 911 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 912 packets = p->stats.packets;
913 bytes = p->stats.bytes;
57a7744e 914 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 915 tx_b += bytes;
916 tx_p += packets;
917 tx_restart += p->tx_stats.restart_queue;
918 tx_busy += p->tx_stats.tx_busy;
2fc3d715 919 tx_linearize += p->tx_stats.tx_linearize;
41c445ff 920
980e9b11
AD		 921 /* Rx queue is part of the same block as Tx queue */
922 p = &p[1];
923 do {
57a7744e 924 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 925 packets = p->stats.packets;
926 bytes = p->stats.bytes;
57a7744e 927 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 928 rx_b += bytes;
929 rx_p += packets;
420136cc
MW		 930 rx_buf += p->rx_stats.alloc_buff_failed;
931 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 932 }
980e9b11 933 rcu_read_unlock();
41c445ff
JB		 934 vsi->tx_restart = tx_restart;
935 vsi->tx_busy = tx_busy;
2fc3d715 936 vsi->tx_linearize = tx_linearize;
41c445ff
JB		 937 vsi->rx_page_failed = rx_page;
938 vsi->rx_buf_failed = rx_buf;
939
940 ns->rx_packets = rx_p;
941 ns->rx_bytes = rx_b;
942 ns->tx_packets = tx_p;
943 ns->tx_bytes = tx_b;
944
41c445ff 945 /* update netdev stats from eth stats */
7812fddc 946 i40e_update_eth_stats(vsi);
41c445ff
JB		 947 ons->tx_errors = oes->tx_errors;
948 ns->tx_errors = es->tx_errors;
949 ons->multicast = oes->rx_multicast;
950 ns->multicast = es->rx_multicast;
41a9e55c
SN		 951 ons->rx_dropped = oes->rx_discards;
952 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 953 ons->tx_dropped = oes->tx_discards;
954 ns->tx_dropped = es->tx_discards;
955
7812fddc 956 /* pull in a couple PF stats if this is the main vsi */
41c445ff 957 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 958 ns->rx_crc_errors = pf->stats.crc_errors;
959 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
960 ns->rx_length_errors = pf->stats.rx_length_errors;
961 }
962}
41c445ff 963
7812fddc 964/**
b40c82e6 965 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 966 * @pf: the PF to be updated
967 **/
968static void i40e_update_pf_stats(struct i40e_pf *pf)
969{
970 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
971 struct i40e_hw_port_stats *nsd = &pf->stats;
972 struct i40e_hw *hw = &pf->hw;
973 u32 val;
974 int i;
41c445ff 975
7812fddc
SN		 976 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
977 I40E_GLPRT_GORCL(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
980 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
981 I40E_GLPRT_GOTCL(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
984 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->eth.rx_discards,
987 &nsd->eth.rx_discards);
532d283d
SN		 988 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
989 I40E_GLPRT_UPRCL(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->eth.rx_unicast,
992 &nsd->eth.rx_unicast);
7812fddc
SN		 993 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
994 I40E_GLPRT_MPRCL(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->eth.rx_multicast,
997 &nsd->eth.rx_multicast);
532d283d
SN		 998 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
999 I40E_GLPRT_BPRCL(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->eth.rx_broadcast,
1002 &nsd->eth.rx_broadcast);
1003 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1004 I40E_GLPRT_UPTCL(hw->port),
1005 pf->stat_offsets_loaded,
1006 &osd->eth.tx_unicast,
1007 &nsd->eth.tx_unicast);
1008 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1009 I40E_GLPRT_MPTCL(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->eth.tx_multicast,
1012 &nsd->eth.tx_multicast);
1013 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1014 I40E_GLPRT_BPTCL(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->eth.tx_broadcast,
1017 &nsd->eth.tx_broadcast);
41c445ff 1018
7812fddc
SN		 1019 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->tx_dropped_link_down,
1022 &nsd->tx_dropped_link_down);
41c445ff 1023
7812fddc
SN		 1024 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1027
7812fddc
SN		 1028 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1031
7812fddc
SN		 1032 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->mac_local_faults,
1035 &nsd->mac_local_faults);
1036 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->mac_remote_faults,
1039 &nsd->mac_remote_faults);
41c445ff 1040
7812fddc
SN		 1041 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_length_errors,
1044 &nsd->rx_length_errors);
41c445ff 1045
7812fddc
SN		 1046 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->link_xon_rx, &nsd->link_xon_rx);
1049 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->link_xon_tx, &nsd->link_xon_tx);
1052 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1053 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1056
7812fddc
SN		 1057 for (i = 0; i < 8; i++) {
1058 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1059 pf->stat_offsets_loaded,
7812fddc
SN		 1060 &osd->priority_xon_rx[i],
1061 &nsd->priority_xon_rx[i]);
1062 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1063 pf->stat_offsets_loaded,
7812fddc
SN		 1064 &osd->priority_xon_tx[i],
1065 &nsd->priority_xon_tx[i]);
1066 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1067 pf->stat_offsets_loaded,
7812fddc
SN		 1068 &osd->priority_xoff_tx[i],
1069 &nsd->priority_xoff_tx[i]);
1070 i40e_stat_update32(hw,
1071 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1072 pf->stat_offsets_loaded,
7812fddc
SN		 1073 &osd->priority_xon_2_xoff[i],
1074 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1075 }
1076
7812fddc
SN		 1077 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1078 I40E_GLPRT_PRC64L(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_size_64, &nsd->rx_size_64);
1081 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1082 I40E_GLPRT_PRC127L(hw->port),
1083 pf->stat_offsets_loaded,
1084 &osd->rx_size_127, &nsd->rx_size_127);
1085 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1086 I40E_GLPRT_PRC255L(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_size_255, &nsd->rx_size_255);
1089 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1090 I40E_GLPRT_PRC511L(hw->port),
1091 pf->stat_offsets_loaded,
1092 &osd->rx_size_511, &nsd->rx_size_511);
1093 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1094 I40E_GLPRT_PRC1023L(hw->port),
1095 pf->stat_offsets_loaded,
1096 &osd->rx_size_1023, &nsd->rx_size_1023);
1097 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1098 I40E_GLPRT_PRC1522L(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_size_1522, &nsd->rx_size_1522);
1101 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1102 I40E_GLPRT_PRC9522L(hw->port),
1103 pf->stat_offsets_loaded,
1104 &osd->rx_size_big, &nsd->rx_size_big);
1105
1106 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1107 I40E_GLPRT_PTC64L(hw->port),
1108 pf->stat_offsets_loaded,
1109 &osd->tx_size_64, &nsd->tx_size_64);
1110 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1111 I40E_GLPRT_PTC127L(hw->port),
1112 pf->stat_offsets_loaded,
1113 &osd->tx_size_127, &nsd->tx_size_127);
1114 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1115 I40E_GLPRT_PTC255L(hw->port),
1116 pf->stat_offsets_loaded,
1117 &osd->tx_size_255, &nsd->tx_size_255);
1118 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1119 I40E_GLPRT_PTC511L(hw->port),
1120 pf->stat_offsets_loaded,
1121 &osd->tx_size_511, &nsd->tx_size_511);
1122 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1123 I40E_GLPRT_PTC1023L(hw->port),
1124 pf->stat_offsets_loaded,
1125 &osd->tx_size_1023, &nsd->tx_size_1023);
1126 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1127 I40E_GLPRT_PTC1522L(hw->port),
1128 pf->stat_offsets_loaded,
1129 &osd->tx_size_1522, &nsd->tx_size_1522);
1130 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1131 I40E_GLPRT_PTC9522L(hw->port),
1132 pf->stat_offsets_loaded,
1133 &osd->tx_size_big, &nsd->tx_size_big);
1134
1135 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1136 pf->stat_offsets_loaded,
1137 &osd->rx_undersize, &nsd->rx_undersize);
1138 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1139 pf->stat_offsets_loaded,
1140 &osd->rx_fragments, &nsd->rx_fragments);
1141 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1142 pf->stat_offsets_loaded,
1143 &osd->rx_oversize, &nsd->rx_oversize);
1144 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1145 pf->stat_offsets_loaded,
1146 &osd->rx_jabber, &nsd->rx_jabber);
1147
433c47de 1148 /* FDIR stats */
0bf4b1b0
ASJ		 1149 i40e_stat_update32(hw,
1150 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1151 pf->stat_offsets_loaded,
1152 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1153 i40e_stat_update32(hw,
1154 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1155 pf->stat_offsets_loaded,
1156 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1157 i40e_stat_update32(hw,
1158 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1159 pf->stat_offsets_loaded,
1160 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1161
7812fddc
SN		 1162 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1163 nsd->tx_lpi_status =
1164 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1165 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1166 nsd->rx_lpi_status =
1167 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1168 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1169 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1170 pf->stat_offsets_loaded,
1171 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1172 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1173 pf->stat_offsets_loaded,
1174 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1175
d0389e51
ASJ		 1176 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1177 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1178 nsd->fd_sb_status = true;
1179 else
1180 nsd->fd_sb_status = false;
1181
1182 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1183 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1184 nsd->fd_atr_status = true;
1185 else
1186 nsd->fd_atr_status = false;
1187
41c445ff
JB		 1188 pf->stat_offsets_loaded = true;
1189}
1190
7812fddc
SN		 1191/**
1192 * i40e_update_stats - Update the various statistics counters.
1193 * @vsi: the VSI to be updated
1194 *
1195 * Update the various stats for this VSI and its related entities.
1196 **/
1197void i40e_update_stats(struct i40e_vsi *vsi)
1198{
1199 struct i40e_pf *pf = vsi->back;
1200
1201 if (vsi == pf->vsi[pf->lan_vsi])
1202 i40e_update_pf_stats(pf);
1203
1204 i40e_update_vsi_stats(vsi);
38e00438
VD		 1205#ifdef I40E_FCOE
1206 i40e_update_fcoe_stats(vsi);
1207#endif
7812fddc
SN		 1208}
1209
41c445ff
JB		 1210/**
1211 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1212 * @vsi: the VSI to be searched
1213 * @macaddr: the MAC address
1214 * @vlan: the vlan
b40c82e6 1215 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1216 * @is_netdev: make sure its a netdev filter, else doesn't matter
1217 *
1218 * Returns ptr to the filter object or NULL
1219 **/
1220static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1221 u8 *macaddr, s16 vlan,
1222 bool is_vf, bool is_netdev)
1223{
1224 struct i40e_mac_filter *f;
1225
1226 if (!vsi || !macaddr)
1227 return NULL;
1228
1229 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1230 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1231 (vlan == f->vlan) &&
1232 (!is_vf || f->is_vf) &&
1233 (!is_netdev || f->is_netdev))
1234 return f;
1235 }
1236 return NULL;
1237}
1238
1239/**
1240 * i40e_find_mac - Find a mac addr in the macvlan filters list
1241 * @vsi: the VSI to be searched
1242 * @macaddr: the MAC address we are searching for
b40c82e6 1243 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1244 * @is_netdev: make sure its a netdev filter, else doesn't matter
1245 *
1246 * Returns the first filter with the provided MAC address or NULL if
1247 * MAC address was not found
1248 **/
1249struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1250 bool is_vf, bool is_netdev)
1251{
1252 struct i40e_mac_filter *f;
1253
1254 if (!vsi || !macaddr)
1255 return NULL;
1256
1257 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1258 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1259 (!is_vf || f->is_vf) &&
1260 (!is_netdev || f->is_netdev))
1261 return f;
1262 }
1263 return NULL;
1264}
1265
1266/**
1267 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1268 * @vsi: the VSI to be searched
1269 *
1270 * Returns true if VSI is in vlan mode or false otherwise
1271 **/
1272bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1273{
1274 struct i40e_mac_filter *f;
1275
1276 /* Only -1 for all the filters denotes not in vlan mode
1277 * so we have to go through all the list in order to make sure
1278 */
1279 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1280 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1281 return true;
1282 }
1283
1284 return false;
1285}
1286
1287/**
1288 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1289 * @vsi: the VSI to be searched
1290 * @macaddr: the mac address to be filtered
b40c82e6 1291 * @is_vf: true if it is a VF
41c445ff
JB		 1292 * @is_netdev: true if it is a netdev
1293 *
1294 * Goes through all the macvlan filters and adds a
1295 * macvlan filter for each unique vlan that already exists
1296 *
1297 * Returns first filter found on success, else NULL
1298 **/
1299struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1300 bool is_vf, bool is_netdev)
1301{
1302 struct i40e_mac_filter *f;
1303
1304 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1305 if (vsi->info.pvid)
1306 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1307 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1308 is_vf, is_netdev)) {
1309 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1310 is_vf, is_netdev))
41c445ff
JB		 1311 return NULL;
1312 }
1313 }
1314
1315 return list_first_entry_or_null(&vsi->mac_filter_list,
1316 struct i40e_mac_filter, list);
1317}
1318
8c27d42e
GR		 1319/**
1320 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1321 * @vsi: the PF Main VSI - inappropriate for any other VSI
1322 * @macaddr: the MAC address
30650cc5
SN		 1323 *
1324 * Some older firmware configurations set up a default promiscuous VLAN
1325 * filter that needs to be removed.
8c27d42e 1326 **/
30650cc5 1327static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1328{
1329 struct i40e_aqc_remove_macvlan_element_data element;
1330 struct i40e_pf *pf = vsi->back;
f1c7e72e 1331 i40e_status ret;
8c27d42e
GR		 1332
1333 /* Only appropriate for the PF main VSI */
1334 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1335 return -EINVAL;
8c27d42e 1336
30650cc5 1337 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1338 ether_addr_copy(element.mac_addr, macaddr);
1339 element.vlan_tag = 0;
1340 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1341 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1342 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1343 if (ret)
30650cc5
SN		 1344 return -ENOENT;
1345
1346 return 0;
8c27d42e
GR		 1347}
1348
41c445ff
JB		 1349/**
1350 * i40e_add_filter - Add a mac/vlan filter to the VSI
1351 * @vsi: the VSI to be searched
1352 * @macaddr: the MAC address
1353 * @vlan: the vlan
b40c82e6 1354 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1355 * @is_netdev: make sure its a netdev filter, else doesn't matter
1356 *
1357 * Returns ptr to the filter object or NULL when no memory available.
1358 **/
1359struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1360 u8 *macaddr, s16 vlan,
1361 bool is_vf, bool is_netdev)
1362{
1363 struct i40e_mac_filter *f;
1364
1365 if (!vsi || !macaddr)
1366 return NULL;
1367
1368 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1369 if (!f) {
1370 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1371 if (!f)
1372 goto add_filter_out;
1373
9a173901 1374 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1375 f->vlan = vlan;
1376 f->changed = true;
1377
1378 INIT_LIST_HEAD(&f->list);
1379 list_add(&f->list, &vsi->mac_filter_list);
1380 }
1381
1382 /* increment counter and add a new flag if needed */
1383 if (is_vf) {
1384 if (!f->is_vf) {
1385 f->is_vf = true;
1386 f->counter++;
1387 }
1388 } else if (is_netdev) {
1389 if (!f->is_netdev) {
1390 f->is_netdev = true;
1391 f->counter++;
1392 }
1393 } else {
1394 f->counter++;
1395 }
1396
1397 /* changed tells sync_filters_subtask to
1398 * push the filter down to the firmware
1399 */
1400 if (f->changed) {
1401 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1402 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1403 }
1404
1405add_filter_out:
1406 return f;
1407}
1408
1409/**
1410 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1411 * @vsi: the VSI to be searched
1412 * @macaddr: the MAC address
1413 * @vlan: the vlan
b40c82e6 1414 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1415 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1416 **/
1417void i40e_del_filter(struct i40e_vsi *vsi,
1418 u8 *macaddr, s16 vlan,
1419 bool is_vf, bool is_netdev)
1420{
1421 struct i40e_mac_filter *f;
1422
1423 if (!vsi || !macaddr)
1424 return;
1425
1426 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1427 if (!f || f->counter == 0)
1428 return;
1429
1430 if (is_vf) {
1431 if (f->is_vf) {
1432 f->is_vf = false;
1433 f->counter--;
1434 }
1435 } else if (is_netdev) {
1436 if (f->is_netdev) {
1437 f->is_netdev = false;
1438 f->counter--;
1439 }
1440 } else {
b40c82e6 1441 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1442 int min_f = 0;
6995b36c 1443
41c445ff
JB		 1444 min_f += (f->is_vf ? 1 : 0);
1445 min_f += (f->is_netdev ? 1 : 0);
1446
1447 if (f->counter > min_f)
1448 f->counter--;
1449 }
1450
1451 /* counter == 0 tells sync_filters_subtask to
1452 * remove the filter from the firmware's list
1453 */
1454 if (f->counter == 0) {
1455 f->changed = true;
1456 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1457 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1458 }
1459}
1460
1461/**
1462 * i40e_set_mac - NDO callback to set mac address
1463 * @netdev: network interface device structure
1464 * @p: pointer to an address structure
1465 *
1466 * Returns 0 on success, negative on failure
1467 **/
38e00438
VD		 1468#ifdef I40E_FCOE
1469int i40e_set_mac(struct net_device *netdev, void *p)
1470#else
41c445ff 1471static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1472#endif
41c445ff
JB		 1473{
1474 struct i40e_netdev_priv *np = netdev_priv(netdev);
1475 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1476 struct i40e_pf *pf = vsi->back;
1477 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1478 struct sockaddr *addr = p;
1479 struct i40e_mac_filter *f;
1480
1481 if (!is_valid_ether_addr(addr->sa_data))
1482 return -EADDRNOTAVAIL;
1483
30650cc5
SN		 1484 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1485 netdev_info(netdev, "already using mac address %pM\n",
1486 addr->sa_data);
1487 return 0;
1488 }
41c445ff 1489
80f6428f
ASJ		 1490 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1491 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1492 return -EADDRNOTAVAIL;
1493
30650cc5
SN		 1494 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1495 netdev_info(netdev, "returning to hw mac address %pM\n",
1496 hw->mac.addr);
1497 else
1498 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1499
41c445ff
JB		 1500 if (vsi->type == I40E_VSI_MAIN) {
1501 i40e_status ret;
6995b36c 1502
41c445ff 1503 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1504 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1505 addr->sa_data, NULL);
1506 if (ret) {
1507 netdev_info(netdev,
1508 "Addr change for Main VSI failed: %d\n",
1509 ret);
1510 return -EADDRNOTAVAIL;
1511 }
41c445ff
JB		 1512 }
1513
30650cc5
SN		 1514 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1515 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1516
30650cc5
SN		 1517 memset(&element, 0, sizeof(element));
1518 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1519 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1520 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1521 } else {
6c8ad1ba
SN		 1522 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1523 false, false);
6c8ad1ba 1524 }
41c445ff 1525
30650cc5
SN		 1526 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1527 struct i40e_aqc_add_macvlan_element_data element;
1528
1529 memset(&element, 0, sizeof(element));
1530 ether_addr_copy(element.mac_addr, hw->mac.addr);
1531 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1532 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1533 } else {
1534 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1535 false, false);
1536 if (f)
1537 f->is_laa = true;
1538 }
1539
30e2561b 1540 i40e_sync_vsi_filters(vsi, false);
30650cc5 1541 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1542
1543 return 0;
1544}
1545
1546/**
1547 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1548 * @vsi: the VSI being setup
1549 * @ctxt: VSI context structure
1550 * @enabled_tc: Enabled TCs bitmap
1551 * @is_add: True if called before Add VSI
1552 *
1553 * Setup VSI queue mapping for enabled traffic classes.
1554 **/
38e00438
VD		 1555#ifdef I40E_FCOE
1556void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1557 struct i40e_vsi_context *ctxt,
1558 u8 enabled_tc,
1559 bool is_add)
1560#else
41c445ff
JB		 1561static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1562 struct i40e_vsi_context *ctxt,
1563 u8 enabled_tc,
1564 bool is_add)
38e00438 1565#endif
41c445ff
JB		 1566{
1567 struct i40e_pf *pf = vsi->back;
1568 u16 sections = 0;
1569 u8 netdev_tc = 0;
1570 u16 numtc = 0;
1571 u16 qcount;
1572 u8 offset;
1573 u16 qmap;
1574 int i;
4e3b35b0 1575 u16 num_tc_qps = 0;
41c445ff
JB		 1576
1577 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1578 offset = 0;
1579
1580 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1581 /* Find numtc from enabled TC bitmap */
1582 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1583 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1584 numtc++;
1585 }
1586 if (!numtc) {
1587 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1588 numtc = 1;
1589 }
1590 } else {
1591 /* At least TC0 is enabled in case of non-DCB case */
1592 numtc = 1;
1593 }
1594
1595 vsi->tc_config.numtc = numtc;
1596 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1597 /* Number of queues per enabled TC */
7f9ff476
AS		 1598 /* In MFP case we can have a much lower count of MSIx
1599 * vectors available and so we need to lower the used
1600 * q count.
1601 */
26cdc443
ASJ		 1602 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1603 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1604 else
1605 qcount = vsi->alloc_queue_pairs;
7f9ff476 1606 num_tc_qps = qcount / numtc;
e25d00b8 1607 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1608
1609 /* Setup queue offset/count for all TCs for given VSI */
1610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1611 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1612 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1613 /* TC is enabled */
41c445ff
JB		 1614 int pow, num_qps;
1615
41c445ff
JB		 1616 switch (vsi->type) {
1617 case I40E_VSI_MAIN:
4e3b35b0 1618 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1619 break;
38e00438
VD		 1620#ifdef I40E_FCOE
1621 case I40E_VSI_FCOE:
1622 qcount = num_tc_qps;
1623 break;
1624#endif
41c445ff
JB		 1625 case I40E_VSI_FDIR:
1626 case I40E_VSI_SRIOV:
1627 case I40E_VSI_VMDQ2:
1628 default:
4e3b35b0 1629 qcount = num_tc_qps;
41c445ff
JB		 1630 WARN_ON(i != 0);
1631 break;
1632 }
4e3b35b0
NP		 1633 vsi->tc_config.tc_info[i].qoffset = offset;
1634 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1635
1e200e4a 1636 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1637 num_qps = qcount;
41c445ff 1638 pow = 0;
41a1d04b 1639 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1640 pow++;
1641 num_qps >>= 1;
1642 }
1643
1644 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1645 qmap =
1646 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1647 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1648
4e3b35b0 1649 offset += qcount;
41c445ff
JB		 1650 } else {
1651 /* TC is not enabled so set the offset to
1652 * default queue and allocate one queue
1653 * for the given TC.
1654 */
1655 vsi->tc_config.tc_info[i].qoffset = 0;
1656 vsi->tc_config.tc_info[i].qcount = 1;
1657 vsi->tc_config.tc_info[i].netdev_tc = 0;
1658
1659 qmap = 0;
1660 }
1661 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1662 }
1663
1664 /* Set actual Tx/Rx queue pairs */
1665 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1666 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1667 if (vsi->req_queue_pairs > 0)
1668 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1669 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1670 vsi->num_queue_pairs = pf->num_lan_msix;
1671 }
41c445ff
JB		 1672
1673 /* Scheduler section valid can only be set for ADD VSI */
1674 if (is_add) {
1675 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1676
1677 ctxt->info.up_enable_bits = enabled_tc;
1678 }
1679 if (vsi->type == I40E_VSI_SRIOV) {
1680 ctxt->info.mapping_flags |=
1681 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1682 for (i = 0; i < vsi->num_queue_pairs; i++)
1683 ctxt->info.queue_mapping[i] =
1684 cpu_to_le16(vsi->base_queue + i);
1685 } else {
1686 ctxt->info.mapping_flags |=
1687 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1688 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1689 }
1690 ctxt->info.valid_sections |= cpu_to_le16(sections);
1691}
1692
1693/**
1694 * i40e_set_rx_mode - NDO callback to set the netdev filters
1695 * @netdev: network interface device structure
1696 **/
38e00438
VD		 1697#ifdef I40E_FCOE
1698void i40e_set_rx_mode(struct net_device *netdev)
1699#else
41c445ff 1700static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1701#endif
41c445ff
JB		 1702{
1703 struct i40e_netdev_priv *np = netdev_priv(netdev);
1704 struct i40e_mac_filter *f, *ftmp;
1705 struct i40e_vsi *vsi = np->vsi;
1706 struct netdev_hw_addr *uca;
1707 struct netdev_hw_addr *mca;
1708 struct netdev_hw_addr *ha;
1709
1710 /* add addr if not already in the filter list */
1711 netdev_for_each_uc_addr(uca, netdev) {
1712 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1713 if (i40e_is_vsi_in_vlan(vsi))
1714 i40e_put_mac_in_vlan(vsi, uca->addr,
1715 false, true);
1716 else
1717 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1718 false, true);
1719 }
1720 }
1721
1722 netdev_for_each_mc_addr(mca, netdev) {
1723 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1724 if (i40e_is_vsi_in_vlan(vsi))
1725 i40e_put_mac_in_vlan(vsi, mca->addr,
1726 false, true);
1727 else
1728 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1729 false, true);
1730 }
1731 }
1732
1733 /* remove filter if not in netdev list */
1734 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1735
1736 if (!f->is_netdev)
1737 continue;
1738
2f41f335
SN		 1739 netdev_for_each_mc_addr(mca, netdev)
1740 if (ether_addr_equal(mca->addr, f->macaddr))
1741 goto bottom_of_search_loop;
41c445ff 1742
2f41f335
SN		 1743 netdev_for_each_uc_addr(uca, netdev)
1744 if (ether_addr_equal(uca->addr, f->macaddr))
1745 goto bottom_of_search_loop;
1746
1747 for_each_dev_addr(netdev, ha)
1748 if (ether_addr_equal(ha->addr, f->macaddr))
1749 goto bottom_of_search_loop;
1750
1751 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1752 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1753
1754bottom_of_search_loop:
1755 continue;
41c445ff
JB		 1756 }
1757
1758 /* check for other flag changes */
1759 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1760 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1761 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1762 }
1763}
1764
1765/**
1766 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1767 * @vsi: ptr to the VSI
30e2561b 1768 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1769 *
1770 * Push any outstanding VSI filter changes through the AdminQ.
1771 *
1772 * Returns 0 or error value
1773 **/
30e2561b 1774int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff
JB		 1775{
1776 struct i40e_mac_filter *f, *ftmp;
1777 bool promisc_forced_on = false;
1778 bool add_happened = false;
1779 int filter_list_len = 0;
1780 u32 changed_flags = 0;
f1c7e72e 1781 i40e_status ret = 0;
41c445ff
JB		 1782 struct i40e_pf *pf;
1783 int num_add = 0;
1784 int num_del = 0;
f1c7e72e 1785 int aq_err = 0;
41c445ff
JB		 1786 u16 cmd_flags;
1787
1788 /* empty array typed pointers, kcalloc later */
1789 struct i40e_aqc_add_macvlan_element_data *add_list;
1790 struct i40e_aqc_remove_macvlan_element_data *del_list;
1791
1792 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1793 usleep_range(1000, 2000);
1794 pf = vsi->back;
1795
1796 if (vsi->netdev) {
1797 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1798 vsi->current_netdev_flags = vsi->netdev->flags;
1799 }
1800
1801 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1802 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1803
1804 filter_list_len = pf->hw.aq.asq_buf_size /
1805 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1806 del_list = kcalloc(filter_list_len,
1807 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1808 GFP_KERNEL);
1809 if (!del_list)
1810 return -ENOMEM;
1811
1812 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1813 if (!f->changed)
1814 continue;
1815
1816 if (f->counter != 0)
1817 continue;
1818 f->changed = false;
1819 cmd_flags = 0;
1820
1821 /* add to delete list */
9a173901 1822 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1823 del_list[num_del].vlan_tag =
1824 cpu_to_le16((u16)(f->vlan ==
1825 I40E_VLAN_ANY ? 0 : f->vlan));
1826
41c445ff
JB		 1827 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1828 del_list[num_del].flags = cmd_flags;
1829 num_del++;
1830
1831 /* unlink from filter list */
1832 list_del(&f->list);
1833 kfree(f);
1834
1835 /* flush a full buffer */
1836 if (num_del == filter_list_len) {
f1c7e72e
SN		 1837 ret = i40e_aq_remove_macvlan(&pf->hw,
1838 vsi->seid, del_list, num_del,
1839 NULL);
1840 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1841 num_del = 0;
1842 memset(del_list, 0, sizeof(*del_list));
1843
f1c7e72e 1844 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1845 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1846 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1847 i40e_stat_str(&pf->hw, ret),
1848 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1849 }
1850 }
1851 if (num_del) {
f1c7e72e 1852 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1853 del_list, num_del, NULL);
f1c7e72e 1854 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1855 num_del = 0;
1856
f1c7e72e 1857 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1859 "ignoring delete macvlan error, err %s aq_err %s\n",
1860 i40e_stat_str(&pf->hw, ret),
1861 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1862 }
1863
1864 kfree(del_list);
1865 del_list = NULL;
1866
1867 /* do all the adds now */
1868 filter_list_len = pf->hw.aq.asq_buf_size /
1869 sizeof(struct i40e_aqc_add_macvlan_element_data),
1870 add_list = kcalloc(filter_list_len,
1871 sizeof(struct i40e_aqc_add_macvlan_element_data),
1872 GFP_KERNEL);
1873 if (!add_list)
1874 return -ENOMEM;
1875
1876 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1877 if (!f->changed)
1878 continue;
1879
1880 if (f->counter == 0)
1881 continue;
1882 f->changed = false;
1883 add_happened = true;
1884 cmd_flags = 0;
1885
1886 /* add to add array */
9a173901 1887 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1888 add_list[num_add].vlan_tag =
1889 cpu_to_le16(
1890 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1891 add_list[num_add].queue_number = 0;
1892
1893 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1894 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1895 num_add++;
1896
1897 /* flush a full buffer */
1898 if (num_add == filter_list_len) {
f1c7e72e
SN		 1899 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1900 add_list, num_add,
1901 NULL);
1902 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1903 num_add = 0;
1904
f1c7e72e 1905 if (ret)
41c445ff
JB		 1906 break;
1907 memset(add_list, 0, sizeof(*add_list));
1908 }
1909 }
1910 if (num_add) {
f1c7e72e
SN		 1911 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1912 add_list, num_add, NULL);
1913 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1914 num_add = 0;
1915 }
1916 kfree(add_list);
1917 add_list = NULL;
1918
f1c7e72e 1919 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1920 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1921 "add filter failed, err %s aq_err %s\n",
1922 i40e_stat_str(&pf->hw, ret),
1923 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1924 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1925 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1926 &vsi->state)) {
1927 promisc_forced_on = true;
1928 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1929 &vsi->state);
1930 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1931 }
1932 }
1933 }
1934
1935 /* check for changes in promiscuous modes */
1936 if (changed_flags & IFF_ALLMULTI) {
1937 bool cur_multipromisc;
6995b36c 1938
41c445ff 1939 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1940 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1941 vsi->seid,
1942 cur_multipromisc,
1943 NULL);
1944 if (ret)
41c445ff 1945 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1946 "set multi promisc failed, err %s aq_err %s\n",
1947 i40e_stat_str(&pf->hw, ret),
1948 i40e_aq_str(&pf->hw,
1949 pf->hw.aq.asq_last_status));
41c445ff
JB		 1950 }
1951 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1952 bool cur_promisc;
6995b36c 1953
41c445ff
JB		 1954 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1955 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1956 &vsi->state));
92faef85
ASJ		 1957 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
1958 /* set defport ON for Main VSI instead of true promisc
1959 * this way we will get all unicast/multicast and VLAN
1960 * promisc behavior but will not get VF or VMDq traffic
1961 * replicated on the Main VSI.
1962 */
1963 if (pf->cur_promisc != cur_promisc) {
1964 pf->cur_promisc = cur_promisc;
30e2561b
AS		 1965 if (grab_rtnl)
1966 i40e_do_reset_safe(pf,
1967 BIT(__I40E_PF_RESET_REQUESTED));
1968 else
1969 i40e_do_reset(pf,
92faef85
ASJ		 1970 BIT(__I40E_PF_RESET_REQUESTED));
1971 }
1972 } else {
1973 ret = i40e_aq_set_vsi_unicast_promiscuous(
1974 &vsi->back->hw,
f1c7e72e
SN		 1975 vsi->seid,
1976 cur_promisc, NULL);
92faef85
ASJ		 1977 if (ret)
1978 dev_info(&pf->pdev->dev,
1979 "set unicast promisc failed, err %d, aq_err %d\n",
1980 ret, pf->hw.aq.asq_last_status);
1981 ret = i40e_aq_set_vsi_multicast_promiscuous(
1982 &vsi->back->hw,
1983 vsi->seid,
1984 cur_promisc, NULL);
1985 if (ret)
1986 dev_info(&pf->pdev->dev,
1987 "set multicast promisc failed, err %d, aq_err %d\n",
1988 ret, pf->hw.aq.asq_last_status);
1989 }
f1c7e72e
SN		 1990 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1991 vsi->seid,
1992 cur_promisc, NULL);
1993 if (ret)
1a10370a 1994 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1995 "set brdcast promisc failed, err %s, aq_err %s\n",
1996 i40e_stat_str(&pf->hw, ret),
1997 i40e_aq_str(&pf->hw,
1998 pf->hw.aq.asq_last_status));
41c445ff
JB		 1999 }
2000
2001 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2002 return 0;
2003}
2004
2005/**
2006 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2007 * @pf: board private structure
2008 **/
2009static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2010{
2011 int v;
2012
2013 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2014 return;
2015 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2016
505682cd 2017 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2018 if (pf->vsi[v] &&
2019 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2020 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2021 }
2022}
2023
2024/**
2025 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2026 * @netdev: network interface device structure
2027 * @new_mtu: new value for maximum frame size
2028 *
2029 * Returns 0 on success, negative on failure
2030 **/
2031static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2032{
2033 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2034 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2035 struct i40e_vsi *vsi = np->vsi;
2036
2037 /* MTU < 68 is an error and causes problems on some kernels */
2038 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2039 return -EINVAL;
2040
2041 netdev_info(netdev, "changing MTU from %d to %d\n",
2042 netdev->mtu, new_mtu);
2043 netdev->mtu = new_mtu;
2044 if (netif_running(netdev))
2045 i40e_vsi_reinit_locked(vsi);
2046
2047 return 0;
2048}
2049
beb0dff1
JK		 2050/**
2051 * i40e_ioctl - Access the hwtstamp interface
2052 * @netdev: network interface device structure
2053 * @ifr: interface request data
2054 * @cmd: ioctl command
2055 **/
2056int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2057{
2058 struct i40e_netdev_priv *np = netdev_priv(netdev);
2059 struct i40e_pf *pf = np->vsi->back;
2060
2061 switch (cmd) {
2062 case SIOCGHWTSTAMP:
2063 return i40e_ptp_get_ts_config(pf, ifr);
2064 case SIOCSHWTSTAMP:
2065 return i40e_ptp_set_ts_config(pf, ifr);
2066 default:
2067 return -EOPNOTSUPP;
2068 }
2069}
2070
41c445ff
JB		 2071/**
2072 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2073 * @vsi: the vsi being adjusted
2074 **/
2075void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2076{
2077 struct i40e_vsi_context ctxt;
2078 i40e_status ret;
2079
2080 if ((vsi->info.valid_sections &
2081 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2082 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2083 return; /* already enabled */
2084
2085 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2086 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2087 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2088
2089 ctxt.seid = vsi->seid;
1a2f6248 2090 ctxt.info = vsi->info;
41c445ff
JB		 2091 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2092 if (ret) {
2093 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2094 "update vlan stripping failed, err %s aq_err %s\n",
2095 i40e_stat_str(&vsi->back->hw, ret),
2096 i40e_aq_str(&vsi->back->hw,
2097 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2098 }
2099}
2100
2101/**
2102 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2103 * @vsi: the vsi being adjusted
2104 **/
2105void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2106{
2107 struct i40e_vsi_context ctxt;
2108 i40e_status ret;
2109
2110 if ((vsi->info.valid_sections &
2111 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2112 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2113 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2114 return; /* already disabled */
2115
2116 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2117 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2118 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2119
2120 ctxt.seid = vsi->seid;
1a2f6248 2121 ctxt.info = vsi->info;
41c445ff
JB		 2122 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2123 if (ret) {
2124 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2125 "update vlan stripping failed, err %s aq_err %s\n",
2126 i40e_stat_str(&vsi->back->hw, ret),
2127 i40e_aq_str(&vsi->back->hw,
2128 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2129 }
2130}
2131
2132/**
2133 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2134 * @netdev: network interface to be adjusted
2135 * @features: netdev features to test if VLAN offload is enabled or not
2136 **/
2137static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2138{
2139 struct i40e_netdev_priv *np = netdev_priv(netdev);
2140 struct i40e_vsi *vsi = np->vsi;
2141
2142 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2143 i40e_vlan_stripping_enable(vsi);
2144 else
2145 i40e_vlan_stripping_disable(vsi);
2146}
2147
2148/**
2149 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2150 * @vsi: the vsi being configured
2151 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2152 **/
2153int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2154{
2155 struct i40e_mac_filter *f, *add_f;
2156 bool is_netdev, is_vf;
41c445ff
JB		 2157
2158 is_vf = (vsi->type == I40E_VSI_SRIOV);
2159 is_netdev = !!(vsi->netdev);
2160
2161 if (is_netdev) {
2162 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2163 is_vf, is_netdev);
2164 if (!add_f) {
2165 dev_info(&vsi->back->pdev->dev,
2166 "Could not add vlan filter %d for %pM\n",
2167 vid, vsi->netdev->dev_addr);
2168 return -ENOMEM;
2169 }
2170 }
2171
2172 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2173 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2174 if (!add_f) {
2175 dev_info(&vsi->back->pdev->dev,
2176 "Could not add vlan filter %d for %pM\n",
2177 vid, f->macaddr);
2178 return -ENOMEM;
2179 }
2180 }
2181
41c445ff
JB		 2182 /* Now if we add a vlan tag, make sure to check if it is the first
2183 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2184 * with 0, so we now accept untagged and specified tagged traffic
2185 * (and not any taged and untagged)
2186 */
2187 if (vid > 0) {
2188 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2189 I40E_VLAN_ANY,
2190 is_vf, is_netdev)) {
2191 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2192 I40E_VLAN_ANY, is_vf, is_netdev);
2193 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2194 is_vf, is_netdev);
2195 if (!add_f) {
2196 dev_info(&vsi->back->pdev->dev,
2197 "Could not add filter 0 for %pM\n",
2198 vsi->netdev->dev_addr);
2199 return -ENOMEM;
2200 }
2201 }
8d82a7c5 2202 }
41c445ff 2203
8d82a7c5
GR		 2204 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2205 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2206 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2207 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2208 is_vf, is_netdev)) {
2209 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2210 is_vf, is_netdev);
2211 add_f = i40e_add_filter(vsi, f->macaddr,
2212 0, is_vf, is_netdev);
2213 if (!add_f) {
2214 dev_info(&vsi->back->pdev->dev,
2215 "Could not add filter 0 for %pM\n",
2216 f->macaddr);
2217 return -ENOMEM;
2218 }
2219 }
2220 }
41c445ff
JB		 2221 }
2222
80f6428f
ASJ		 2223 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2224 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2225 return 0;
2226
30e2561b 2227 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2228}
2229
2230/**
2231 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2232 * @vsi: the vsi being configured
2233 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2234 *
2235 * Return: 0 on success or negative otherwise
41c445ff
JB		 2236 **/
2237int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2238{
2239 struct net_device *netdev = vsi->netdev;
2240 struct i40e_mac_filter *f, *add_f;
2241 bool is_vf, is_netdev;
2242 int filter_count = 0;
41c445ff
JB		 2243
2244 is_vf = (vsi->type == I40E_VSI_SRIOV);
2245 is_netdev = !!(netdev);
2246
2247 if (is_netdev)
2248 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2249
2250 list_for_each_entry(f, &vsi->mac_filter_list, list)
2251 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2252
41c445ff
JB		 2253 /* go through all the filters for this VSI and if there is only
2254 * vid == 0 it means there are no other filters, so vid 0 must
2255 * be replaced with -1. This signifies that we should from now
2256 * on accept any traffic (with any tag present, or untagged)
2257 */
2258 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2259 if (is_netdev) {
2260 if (f->vlan &&
2261 ether_addr_equal(netdev->dev_addr, f->macaddr))
2262 filter_count++;
2263 }
2264
2265 if (f->vlan)
2266 filter_count++;
2267 }
2268
2269 if (!filter_count && is_netdev) {
2270 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2271 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2272 is_vf, is_netdev);
2273 if (!f) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Could not add filter %d for %pM\n",
2276 I40E_VLAN_ANY, netdev->dev_addr);
2277 return -ENOMEM;
2278 }
2279 }
2280
2281 if (!filter_count) {
2282 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2283 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2284 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2285 is_vf, is_netdev);
2286 if (!add_f) {
2287 dev_info(&vsi->back->pdev->dev,
2288 "Could not add filter %d for %pM\n",
2289 I40E_VLAN_ANY, f->macaddr);
2290 return -ENOMEM;
2291 }
2292 }
2293 }
2294
80f6428f
ASJ		 2295 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2296 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2297 return 0;
2298
30e2561b 2299 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2300}
2301
2302/**
2303 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2304 * @netdev: network interface to be adjusted
2305 * @vid: vlan id to be added
078b5876
JB		 2306 *
2307 * net_device_ops implementation for adding vlan ids
41c445ff 2308 **/
38e00438
VD		 2309#ifdef I40E_FCOE
2310int i40e_vlan_rx_add_vid(struct net_device *netdev,
2311 __always_unused __be16 proto, u16 vid)
2312#else
41c445ff
JB		 2313static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2314 __always_unused __be16 proto, u16 vid)
38e00438 2315#endif
41c445ff
JB		 2316{
2317 struct i40e_netdev_priv *np = netdev_priv(netdev);
2318 struct i40e_vsi *vsi = np->vsi;
078b5876 2319 int ret = 0;
41c445ff
JB		 2320
2321 if (vid > 4095)
078b5876
JB		 2322 return -EINVAL;
2323
2324 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2325
6982d429
ASJ		 2326 /* If the network stack called us with vid = 0 then
2327 * it is asking to receive priority tagged packets with
2328 * vlan id 0. Our HW receives them by default when configured
2329 * to receive untagged packets so there is no need to add an
2330 * extra filter for vlan 0 tagged packets.
41c445ff 2331 */
6982d429
ASJ		 2332 if (vid)
2333 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2334
078b5876
JB		 2335 if (!ret && (vid < VLAN_N_VID))
2336 set_bit(vid, vsi->active_vlans);
41c445ff 2337
078b5876 2338 return ret;
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2343 * @netdev: network interface to be adjusted
2344 * @vid: vlan id to be removed
078b5876 2345 *
fdfd943e 2346 * net_device_ops implementation for removing vlan ids
41c445ff 2347 **/
38e00438
VD		 2348#ifdef I40E_FCOE
2349int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2350 __always_unused __be16 proto, u16 vid)
2351#else
41c445ff
JB		 2352static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2353 __always_unused __be16 proto, u16 vid)
38e00438 2354#endif
41c445ff
JB		 2355{
2356 struct i40e_netdev_priv *np = netdev_priv(netdev);
2357 struct i40e_vsi *vsi = np->vsi;
2358
078b5876
JB		 2359 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2360
41c445ff
JB		 2361 /* return code is ignored as there is nothing a user
2362 * can do about failure to remove and a log message was
078b5876 2363 * already printed from the other function
41c445ff
JB		 2364 */
2365 i40e_vsi_kill_vlan(vsi, vid);
2366
2367 clear_bit(vid, vsi->active_vlans);
078b5876 2368
41c445ff
JB		 2369 return 0;
2370}
2371
2372/**
2373 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2374 * @vsi: the vsi being brought back up
2375 **/
2376static void i40e_restore_vlan(struct i40e_vsi *vsi)
2377{
2378 u16 vid;
2379
2380 if (!vsi->netdev)
2381 return;
2382
2383 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2384
2385 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2386 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2387 vid);
2388}
2389
2390/**
2391 * i40e_vsi_add_pvid - Add pvid for the VSI
2392 * @vsi: the vsi being adjusted
2393 * @vid: the vlan id to set as a PVID
2394 **/
dcae29be 2395int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2396{
2397 struct i40e_vsi_context ctxt;
f1c7e72e 2398 i40e_status ret;
41c445ff
JB		 2399
2400 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2401 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2402 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2403 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2404 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2405
2406 ctxt.seid = vsi->seid;
1a2f6248 2407 ctxt.info = vsi->info;
f1c7e72e
SN		 2408 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2409 if (ret) {
41c445ff 2410 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2411 "add pvid failed, err %s aq_err %s\n",
2412 i40e_stat_str(&vsi->back->hw, ret),
2413 i40e_aq_str(&vsi->back->hw,
2414 vsi->back->hw.aq.asq_last_status));
dcae29be 2415 return -ENOENT;
41c445ff
JB		 2416 }
2417
dcae29be 2418 return 0;
41c445ff
JB		 2419}
2420
2421/**
2422 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2423 * @vsi: the vsi being adjusted
2424 *
2425 * Just use the vlan_rx_register() service to put it back to normal
2426 **/
2427void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2428{
6c12fcbf
GR		 2429 i40e_vlan_stripping_disable(vsi);
2430
41c445ff 2431 vsi->info.pvid = 0;
41c445ff
JB		 2432}
2433
2434/**
2435 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2436 * @vsi: ptr to the VSI
2437 *
2438 * If this function returns with an error, then it's possible one or
2439 * more of the rings is populated (while the rest are not). It is the
2440 * callers duty to clean those orphaned rings.
2441 *
2442 * Return 0 on success, negative on failure
2443 **/
2444static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2445{
2446 int i, err = 0;
2447
2448 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2449 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2450
2451 return err;
2452}
2453
2454/**
2455 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2456 * @vsi: ptr to the VSI
2457 *
2458 * Free VSI's transmit software resources
2459 **/
2460static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2461{
2462 int i;
2463
8e9dca53
GR		 2464 if (!vsi->tx_rings)
2465 return;
2466
41c445ff 2467 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2468 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2469 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2470}
2471
2472/**
2473 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2474 * @vsi: ptr to the VSI
2475 *
2476 * If this function returns with an error, then it's possible one or
2477 * more of the rings is populated (while the rest are not). It is the
2478 * callers duty to clean those orphaned rings.
2479 *
2480 * Return 0 on success, negative on failure
2481 **/
2482static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2483{
2484 int i, err = 0;
2485
2486 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2487 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2488#ifdef I40E_FCOE
2489 i40e_fcoe_setup_ddp_resources(vsi);
2490#endif
41c445ff
JB		 2491 return err;
2492}
2493
2494/**
2495 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2496 * @vsi: ptr to the VSI
2497 *
2498 * Free all receive software resources
2499 **/
2500static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2501{
2502 int i;
2503
8e9dca53
GR		 2504 if (!vsi->rx_rings)
2505 return;
2506
41c445ff 2507 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2508 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2509 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2510#ifdef I40E_FCOE
2511 i40e_fcoe_free_ddp_resources(vsi);
2512#endif
41c445ff
JB		 2513}
2514
3ffa037d
NP		 2515/**
2516 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2517 * @ring: The Tx ring to configure
2518 *
2519 * This enables/disables XPS for a given Tx descriptor ring
2520 * based on the TCs enabled for the VSI that ring belongs to.
2521 **/
2522static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2523{
2524 struct i40e_vsi *vsi = ring->vsi;
2525 cpumask_var_t mask;
2526
9a660eea
JB		 2527 if (!ring->q_vector || !ring->netdev)
2528 return;
2529
2530 /* Single TC mode enable XPS */
2531 if (vsi->tc_config.numtc <= 1) {
2532 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2533 netif_set_xps_queue(ring->netdev,
2534 &ring->q_vector->affinity_mask,
2535 ring->queue_index);
9a660eea
JB		 2536 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2537 /* Disable XPS to allow selection based on TC */
2538 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2539 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2540 free_cpumask_var(mask);
3ffa037d
NP		 2541 }
2542}
2543
41c445ff
JB		 2544/**
2545 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2546 * @ring: The Tx ring to configure
2547 *
2548 * Configure the Tx descriptor ring in the HMC context.
2549 **/
2550static int i40e_configure_tx_ring(struct i40e_ring *ring)
2551{
2552 struct i40e_vsi *vsi = ring->vsi;
2553 u16 pf_q = vsi->base_queue + ring->queue_index;
2554 struct i40e_hw *hw = &vsi->back->hw;
2555 struct i40e_hmc_obj_txq tx_ctx;
2556 i40e_status err = 0;
2557 u32 qtx_ctl = 0;
2558
2559 /* some ATR related tx ring init */
60ea5f83 2560 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2561 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2562 ring->atr_count = 0;
2563 } else {
2564 ring->atr_sample_rate = 0;
2565 }
2566
3ffa037d
NP		 2567 /* configure XPS */
2568 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2569
2570 /* clear the context structure first */
2571 memset(&tx_ctx, 0, sizeof(tx_ctx));
2572
2573 tx_ctx.new_context = 1;
2574 tx_ctx.base = (ring->dma / 128);
2575 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2576 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2577 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2578#ifdef I40E_FCOE
2579 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2580#endif
beb0dff1 2581 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2582 /* FDIR VSI tx ring can still use RS bit and writebacks */
2583 if (vsi->type != I40E_VSI_FDIR)
2584 tx_ctx.head_wb_ena = 1;
2585 tx_ctx.head_wb_addr = ring->dma +
2586 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2587
2588 /* As part of VSI creation/update, FW allocates certain
2589 * Tx arbitration queue sets for each TC enabled for
2590 * the VSI. The FW returns the handles to these queue
2591 * sets as part of the response buffer to Add VSI,
2592 * Update VSI, etc. AQ commands. It is expected that
2593 * these queue set handles be associated with the Tx
2594 * queues by the driver as part of the TX queue context
2595 * initialization. This has to be done regardless of
2596 * DCB as by default everything is mapped to TC0.
2597 */
2598 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2599 tx_ctx.rdylist_act = 0;
2600
2601 /* clear the context in the HMC */
2602 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2603 if (err) {
2604 dev_info(&vsi->back->pdev->dev,
2605 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2606 ring->queue_index, pf_q, err);
2607 return -ENOMEM;
2608 }
2609
2610 /* set the context in the HMC */
2611 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2612 if (err) {
2613 dev_info(&vsi->back->pdev->dev,
2614 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2615 ring->queue_index, pf_q, err);
2616 return -ENOMEM;
2617 }
2618
2619 /* Now associate this queue with this PCI function */
7a28d885 2620 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2621 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2622 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2623 I40E_QTX_CTL_VFVM_INDX_MASK;
2624 } else {
9d8bf547 2625 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2626 }
2627
13fd9774
SN		 2628 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2629 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2630 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2631 i40e_flush(hw);
2632
41c445ff
JB		 2633 /* cache tail off for easier writes later */
2634 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2635
2636 return 0;
2637}
2638
2639/**
2640 * i40e_configure_rx_ring - Configure a receive ring context
2641 * @ring: The Rx ring to configure
2642 *
2643 * Configure the Rx descriptor ring in the HMC context.
2644 **/
2645static int i40e_configure_rx_ring(struct i40e_ring *ring)
2646{
2647 struct i40e_vsi *vsi = ring->vsi;
2648 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2649 u16 pf_q = vsi->base_queue + ring->queue_index;
2650 struct i40e_hw *hw = &vsi->back->hw;
2651 struct i40e_hmc_obj_rxq rx_ctx;
2652 i40e_status err = 0;
2653
2654 ring->state = 0;
2655
2656 /* clear the context structure first */
2657 memset(&rx_ctx, 0, sizeof(rx_ctx));
2658
2659 ring->rx_buf_len = vsi->rx_buf_len;
2660 ring->rx_hdr_len = vsi->rx_hdr_len;
2661
2662 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2663 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2664
2665 rx_ctx.base = (ring->dma / 128);
2666 rx_ctx.qlen = ring->count;
2667
2668 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2669 set_ring_16byte_desc_enabled(ring);
2670 rx_ctx.dsize = 0;
2671 } else {
2672 rx_ctx.dsize = 1;
2673 }
2674
2675 rx_ctx.dtype = vsi->dtype;
2676 if (vsi->dtype) {
2677 set_ring_ps_enabled(ring);
2678 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2679 I40E_RX_SPLIT_IP |
2680 I40E_RX_SPLIT_TCP_UDP |
2681 I40E_RX_SPLIT_SCTP;
2682 } else {
2683 rx_ctx.hsplit_0 = 0;
2684 }
2685
2686 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2687 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2688 if (hw->revision_id == 0)
2689 rx_ctx.lrxqthresh = 0;
2690 else
2691 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2692 rx_ctx.crcstrip = 1;
2693 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2694 /* this controls whether VLAN is stripped from inner headers */
2695 rx_ctx.showiv = 0;
38e00438
VD		 2696#ifdef I40E_FCOE
2697 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2698#endif
acb3676b
CS		 2699 /* set the prefena field to 1 because the manual says to */
2700 rx_ctx.prefena = 1;
41c445ff
JB		 2701
2702 /* clear the context in the HMC */
2703 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2704 if (err) {
2705 dev_info(&vsi->back->pdev->dev,
2706 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2707 ring->queue_index, pf_q, err);
2708 return -ENOMEM;
2709 }
2710
2711 /* set the context in the HMC */
2712 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2713 if (err) {
2714 dev_info(&vsi->back->pdev->dev,
2715 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2716 ring->queue_index, pf_q, err);
2717 return -ENOMEM;
2718 }
2719
2720 /* cache tail for quicker writes, and clear the reg before use */
2721 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2722 writel(0, ring->tail);
2723
a132af24
MW		 2724 if (ring_is_ps_enabled(ring)) {
2725 i40e_alloc_rx_headers(ring);
2726 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2727 } else {
2728 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2729 }
41c445ff
JB		 2730
2731 return 0;
2732}
2733
2734/**
2735 * i40e_vsi_configure_tx - Configure the VSI for Tx
2736 * @vsi: VSI structure describing this set of rings and resources
2737 *
2738 * Configure the Tx VSI for operation.
2739 **/
2740static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2741{
2742 int err = 0;
2743 u16 i;
2744
9f65e15b
AD		 2745 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2746 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2747
2748 return err;
2749}
2750
2751/**
2752 * i40e_vsi_configure_rx - Configure the VSI for Rx
2753 * @vsi: the VSI being configured
2754 *
2755 * Configure the Rx VSI for operation.
2756 **/
2757static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2758{
2759 int err = 0;
2760 u16 i;
2761
2762 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2763 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2764 + ETH_FCS_LEN + VLAN_HLEN;
2765 else
2766 vsi->max_frame = I40E_RXBUFFER_2048;
2767
2768 /* figure out correct receive buffer length */
2769 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2770 I40E_FLAG_RX_PS_ENABLED)) {
2771 case I40E_FLAG_RX_1BUF_ENABLED:
2772 vsi->rx_hdr_len = 0;
2773 vsi->rx_buf_len = vsi->max_frame;
2774 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2775 break;
2776 case I40E_FLAG_RX_PS_ENABLED:
2777 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2778 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2779 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2780 break;
2781 default:
2782 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2783 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2784 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2785 break;
2786 }
2787
38e00438
VD		 2788#ifdef I40E_FCOE
2789 /* setup rx buffer for FCoE */
2790 if ((vsi->type == I40E_VSI_FCOE) &&
2791 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2792 vsi->rx_hdr_len = 0;
2793 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2794 vsi->max_frame = I40E_RXBUFFER_3072;
2795 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2796 }
2797
2798#endif /* I40E_FCOE */
41c445ff
JB		 2799 /* round up for the chip's needs */
2800 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2801 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2802 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2803 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2804
2805 /* set up individual rings */
2806 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2807 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2808
2809 return err;
2810}
2811
2812/**
2813 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2814 * @vsi: ptr to the VSI
2815 **/
2816static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2817{
e7046ee1 2818 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2819 u16 qoffset, qcount;
2820 int i, n;
2821
cd238a3e
PN		 2822 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2823 /* Reset the TC information */
2824 for (i = 0; i < vsi->num_queue_pairs; i++) {
2825 rx_ring = vsi->rx_rings[i];
2826 tx_ring = vsi->tx_rings[i];
2827 rx_ring->dcb_tc = 0;
2828 tx_ring->dcb_tc = 0;
2829 }
2830 }
41c445ff
JB		 2831
2832 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2833 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2834 continue;
2835
2836 qoffset = vsi->tc_config.tc_info[n].qoffset;
2837 qcount = vsi->tc_config.tc_info[n].qcount;
2838 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2839 rx_ring = vsi->rx_rings[i];
2840 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2841 rx_ring->dcb_tc = n;
2842 tx_ring->dcb_tc = n;
2843 }
2844 }
2845}
2846
2847/**
2848 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2849 * @vsi: ptr to the VSI
2850 **/
2851static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2852{
2853 if (vsi->netdev)
2854 i40e_set_rx_mode(vsi->netdev);
2855}
2856
17a73f6b
JG		 2857/**
2858 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2859 * @vsi: Pointer to the targeted VSI
2860 *
2861 * This function replays the hlist on the hw where all the SB Flow Director
2862 * filters were saved.
2863 **/
2864static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2865{
2866 struct i40e_fdir_filter *filter;
2867 struct i40e_pf *pf = vsi->back;
2868 struct hlist_node *node;
2869
55a5e60b
ASJ		 2870 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2871 return;
2872
17a73f6b
JG		 2873 hlist_for_each_entry_safe(filter, node,
2874 &pf->fdir_filter_list, fdir_node) {
2875 i40e_add_del_fdir(vsi, filter, true);
2876 }
2877}
2878
41c445ff
JB		 2879/**
2880 * i40e_vsi_configure - Set up the VSI for action
2881 * @vsi: the VSI being configured
2882 **/
2883static int i40e_vsi_configure(struct i40e_vsi *vsi)
2884{
2885 int err;
2886
2887 i40e_set_vsi_rx_mode(vsi);
2888 i40e_restore_vlan(vsi);
2889 i40e_vsi_config_dcb_rings(vsi);
2890 err = i40e_vsi_configure_tx(vsi);
2891 if (!err)
2892 err = i40e_vsi_configure_rx(vsi);
2893
2894 return err;
2895}
2896
2897/**
2898 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2899 * @vsi: the VSI being configured
2900 **/
2901static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2902{
2903 struct i40e_pf *pf = vsi->back;
2904 struct i40e_q_vector *q_vector;
2905 struct i40e_hw *hw = &pf->hw;
2906 u16 vector;
2907 int i, q;
2908 u32 val;
2909 u32 qp;
2910
2911 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2912 * and PFINT_LNKLSTn registers, e.g.:
2913 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2914 */
2915 qp = vsi->base_queue;
2916 vector = vsi->base_vector;
493fb300
AD		 2917 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2918 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2919 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2920 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2921 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2922 q_vector->rx.itr);
2923 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2924 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2925 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2926 q_vector->tx.itr);
2927
2928 /* Linked list for the queuepairs assigned to this vector */
2929 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2930 for (q = 0; q < q_vector->num_ringpairs; q++) {
2931 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2932 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2933 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2934 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2935 (I40E_QUEUE_TYPE_TX
2936 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2937
2938 wr32(hw, I40E_QINT_RQCTL(qp), val);
2939
2940 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2941 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2942 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2943 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2944 (I40E_QUEUE_TYPE_RX
2945 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2946
2947 /* Terminate the linked list */
2948 if (q == (q_vector->num_ringpairs - 1))
2949 val |= (I40E_QUEUE_END_OF_LIST
2950 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2951
2952 wr32(hw, I40E_QINT_TQCTL(qp), val);
2953 qp++;
2954 }
2955 }
2956
2957 i40e_flush(hw);
2958}
2959
2960/**
2961 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2962 * @hw: ptr to the hardware info
2963 **/
ab437b5a 2964static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2965{
ab437b5a 2966 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2967 u32 val;
2968
2969 /* clear things first */
2970 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2971 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2972
2973 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2974 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2975 I40E_PFINT_ICR0_ENA_GRST_MASK |
2976 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2977 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2978 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2979 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2980 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2981
0d8e1439
ASJ		 2982 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
2983 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
2984
ab437b5a
JK		 2985 if (pf->flags & I40E_FLAG_PTP)
2986 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2987
41c445ff
JB		 2988 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2989
2990 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2991 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2992 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2993
2994 /* OTHER_ITR_IDX = 0 */
2995 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2996}
2997
2998/**
2999 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3000 * @vsi: the VSI being configured
3001 **/
3002static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3003{
493fb300 3004 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3005 struct i40e_pf *pf = vsi->back;
3006 struct i40e_hw *hw = &pf->hw;
3007 u32 val;
3008
3009 /* set the ITR configuration */
3010 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3011 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3012 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3013 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3014 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3015 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3016
ab437b5a 3017 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3018
3019 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3020 wr32(hw, I40E_PFINT_LNKLST0, 0);
3021
f29eaa3d 3022 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3023 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3024 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3025 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3026
3027 wr32(hw, I40E_QINT_RQCTL(0), val);
3028
3029 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3030 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3031 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3032
3033 wr32(hw, I40E_QINT_TQCTL(0), val);
3034 i40e_flush(hw);
3035}
3036
2ef28cfb
MW		 3037/**
3038 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3039 * @pf: board private structure
3040 **/
3041void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3042{
3043 struct i40e_hw *hw = &pf->hw;
3044
3045 wr32(hw, I40E_PFINT_DYN_CTL0,
3046 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3047 i40e_flush(hw);
3048}
3049
41c445ff
JB		 3050/**
3051 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3052 * @pf: board private structure
3053 **/
116a57d4 3054void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3055{
3056 struct i40e_hw *hw = &pf->hw;
3057 u32 val;
3058
3059 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3060 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3061 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3062
3063 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3064 i40e_flush(hw);
3065}
3066
5c2cebda
CW		 3067/**
3068 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3069 * @vsi: pointer to a vsi
03147773 3070 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3071 **/
3072void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3073{
3074 struct i40e_pf *pf = vsi->back;
3075 struct i40e_hw *hw = &pf->hw;
3076 u32 val;
3077
3078 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3079 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3080 i40e_flush(hw);
3081}
3082
41c445ff
JB		 3083/**
3084 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3085 * @irq: interrupt number
3086 * @data: pointer to a q_vector
3087 **/
3088static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3089{
3090 struct i40e_q_vector *q_vector = data;
3091
cd0b6fa6 3092 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3093 return IRQ_HANDLED;
3094
3095 napi_schedule(&q_vector->napi);
3096
3097 return IRQ_HANDLED;
3098}
3099
41c445ff
JB		 3100/**
3101 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3102 * @vsi: the VSI being configured
3103 * @basename: name for the vector
3104 *
3105 * Allocates MSI-X vectors and requests interrupts from the kernel.
3106 **/
3107static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3108{
3109 int q_vectors = vsi->num_q_vectors;
3110 struct i40e_pf *pf = vsi->back;
3111 int base = vsi->base_vector;
3112 int rx_int_idx = 0;
3113 int tx_int_idx = 0;
3114 int vector, err;
3115
3116 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3117 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3118
cd0b6fa6 3119 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3120 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3121 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3122 tx_int_idx++;
cd0b6fa6 3123 } else if (q_vector->rx.ring) {
41c445ff
JB		 3124 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3125 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3126 } else if (q_vector->tx.ring) {
41c445ff
JB		 3127 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3128 "%s-%s-%d", basename, "tx", tx_int_idx++);
3129 } else {
3130 /* skip this unused q_vector */
3131 continue;
3132 }
3133 err = request_irq(pf->msix_entries[base + vector].vector,
3134 vsi->irq_handler,
3135 0,
3136 q_vector->name,
3137 q_vector);
3138 if (err) {
3139 dev_info(&pf->pdev->dev,
fb43201f 3140 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3141 goto free_queue_irqs;
3142 }
3143 /* assign the mask for this irq */
3144 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3145 &q_vector->affinity_mask);
3146 }
3147
63741846 3148 vsi->irqs_ready = true;
41c445ff
JB		 3149 return 0;
3150
3151free_queue_irqs:
3152 while (vector) {
3153 vector--;
3154 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3155 NULL);
3156 free_irq(pf->msix_entries[base + vector].vector,
3157 &(vsi->q_vectors[vector]));
3158 }
3159 return err;
3160}
3161
3162/**
3163 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3164 * @vsi: the VSI being un-configured
3165 **/
3166static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3167{
3168 struct i40e_pf *pf = vsi->back;
3169 struct i40e_hw *hw = &pf->hw;
3170 int base = vsi->base_vector;
3171 int i;
3172
3173 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3174 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3175 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3176 }
3177
3178 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3179 for (i = vsi->base_vector;
3180 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3181 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3182
3183 i40e_flush(hw);
3184 for (i = 0; i < vsi->num_q_vectors; i++)
3185 synchronize_irq(pf->msix_entries[i + base].vector);
3186 } else {
3187 /* Legacy and MSI mode - this stops all interrupt handling */
3188 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3189 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3190 i40e_flush(hw);
3191 synchronize_irq(pf->pdev->irq);
3192 }
3193}
3194
3195/**
3196 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3197 * @vsi: the VSI being configured
3198 **/
3199static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3200{
3201 struct i40e_pf *pf = vsi->back;
3202 int i;
3203
3204 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3205 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3206 i40e_irq_dynamic_enable(vsi, i);
3207 } else {
3208 i40e_irq_dynamic_enable_icr0(pf);
3209 }
3210
1022cb6c 3211 i40e_flush(&pf->hw);
41c445ff
JB		 3212 return 0;
3213}
3214
3215/**
3216 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3217 * @pf: board private structure
3218 **/
3219static void i40e_stop_misc_vector(struct i40e_pf *pf)
3220{
3221 /* Disable ICR 0 */
3222 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3223 i40e_flush(&pf->hw);
3224}
3225
3226/**
3227 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3228 * @irq: interrupt number
3229 * @data: pointer to a q_vector
3230 *
3231 * This is the handler used for all MSI/Legacy interrupts, and deals
3232 * with both queue and non-queue interrupts. This is also used in
3233 * MSIX mode to handle the non-queue interrupts.
3234 **/
3235static irqreturn_t i40e_intr(int irq, void *data)
3236{
3237 struct i40e_pf *pf = (struct i40e_pf *)data;
3238 struct i40e_hw *hw = &pf->hw;
5e823066 3239 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3240 u32 icr0, icr0_remaining;
3241 u32 val, ena_mask;
3242
3243 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3244 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3245
116a57d4
SN		 3246 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3247 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3248 goto enable_intr;
41c445ff 3249
cd92e72f
SN		 3250 /* if interrupt but no bits showing, must be SWINT */
3251 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3252 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3253 pf->sw_int_count++;
3254
0d8e1439
ASJ		 3255 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3256 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3257 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3258 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3259 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3260 }
3261
41c445ff
JB		 3262 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3263 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3264
3265 /* temporarily disable queue cause for NAPI processing */
3266 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3267
41c445ff
JB		 3268 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3269 wr32(hw, I40E_QINT_RQCTL(0), qval);
3270
3271 qval = rd32(hw, I40E_QINT_TQCTL(0));
3272 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3273 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3274
3275 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3276 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3277 }
3278
3279 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3280 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3281 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3282 }
3283
3284 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3285 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3286 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3287 }
3288
3289 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3290 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3291 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3292 }
3293
3294 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3295 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3296 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3297 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3298 val = rd32(hw, I40E_GLGEN_RSTAT);
3299 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3300 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3301 if (val == I40E_RESET_CORER) {
41c445ff 3302 pf->corer_count++;
4eb3f768 3303 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3304 pf->globr_count++;
4eb3f768 3305 } else if (val == I40E_RESET_EMPR) {
41c445ff 3306 pf->empr_count++;
9df42d1a 3307 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3308 }
41c445ff
JB		 3309 }
3310
9c010ee0
ASJ		 3311 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3312 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3313 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3314 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3315 rd32(hw, I40E_PFHMC_ERRORINFO),
3316 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3317 }
3318
beb0dff1
JK		 3319 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3320 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3321
3322 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3323 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3324 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3325 }
beb0dff1
JK		 3326 }
3327
41c445ff
JB		 3328 /* If a critical error is pending we have no choice but to reset the
3329 * device.
3330 * Report and mask out any remaining unexpected interrupts.
3331 */
3332 icr0_remaining = icr0 & ena_mask;
3333 if (icr0_remaining) {
3334 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3335 icr0_remaining);
9c010ee0 3336 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3337 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3338 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3339 dev_info(&pf->pdev->dev, "device will be reset\n");
3340 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3341 i40e_service_event_schedule(pf);
41c445ff
JB		 3342 }
3343 ena_mask &= ~icr0_remaining;
3344 }
5e823066 3345 ret = IRQ_HANDLED;
41c445ff 3346
5e823066 3347enable_intr:
41c445ff
JB		 3348 /* re-enable interrupt causes */
3349 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3350 if (!test_bit(__I40E_DOWN, &pf->state)) {
3351 i40e_service_event_schedule(pf);
3352 i40e_irq_dynamic_enable_icr0(pf);
3353 }
3354
5e823066 3355 return ret;
41c445ff
JB		 3356}
3357
cbf61325
ASJ		 3358/**
3359 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3360 * @tx_ring: tx ring to clean
3361 * @budget: how many cleans we're allowed
3362 *
3363 * Returns true if there's any budget left (e.g. the clean is finished)
3364 **/
3365static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3366{
3367 struct i40e_vsi *vsi = tx_ring->vsi;
3368 u16 i = tx_ring->next_to_clean;
3369 struct i40e_tx_buffer *tx_buf;
3370 struct i40e_tx_desc *tx_desc;
3371
3372 tx_buf = &tx_ring->tx_bi[i];
3373 tx_desc = I40E_TX_DESC(tx_ring, i);
3374 i -= tx_ring->count;
3375
3376 do {
3377 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3378
3379 /* if next_to_watch is not set then there is no work pending */
3380 if (!eop_desc)
3381 break;
3382
3383 /* prevent any other reads prior to eop_desc */
3384 read_barrier_depends();
3385
3386 /* if the descriptor isn't done, no work yet to do */
3387 if (!(eop_desc->cmd_type_offset_bsz &
3388 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3389 break;
3390
3391 /* clear next_to_watch to prevent false hangs */
3392 tx_buf->next_to_watch = NULL;
3393
49d7d933
ASJ		 3394 tx_desc->buffer_addr = 0;
3395 tx_desc->cmd_type_offset_bsz = 0;
3396 /* move past filter desc */
3397 tx_buf++;
3398 tx_desc++;
3399 i++;
3400 if (unlikely(!i)) {
3401 i -= tx_ring->count;
3402 tx_buf = tx_ring->tx_bi;
3403 tx_desc = I40E_TX_DESC(tx_ring, 0);
3404 }
cbf61325
ASJ		 3405 /* unmap skb header data */
3406 dma_unmap_single(tx_ring->dev,
3407 dma_unmap_addr(tx_buf, dma),
3408 dma_unmap_len(tx_buf, len),
3409 DMA_TO_DEVICE);
49d7d933
ASJ		 3410 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3411 kfree(tx_buf->raw_buf);
cbf61325 3412
49d7d933
ASJ		 3413 tx_buf->raw_buf = NULL;
3414 tx_buf->tx_flags = 0;
3415 tx_buf->next_to_watch = NULL;
cbf61325 3416 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3417 tx_desc->buffer_addr = 0;
3418 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3419
49d7d933 3420 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3421 tx_buf++;
3422 tx_desc++;
3423 i++;
3424 if (unlikely(!i)) {
3425 i -= tx_ring->count;
3426 tx_buf = tx_ring->tx_bi;
3427 tx_desc = I40E_TX_DESC(tx_ring, 0);
3428 }
3429
3430 /* update budget accounting */
3431 budget--;
3432 } while (likely(budget));
3433
3434 i += tx_ring->count;
3435 tx_ring->next_to_clean = i;
3436
6995b36c 3437 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3438 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3439
cbf61325
ASJ		 3440 return budget > 0;
3441}
3442
3443/**
3444 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3445 * @irq: interrupt number
3446 * @data: pointer to a q_vector
3447 **/
3448static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3449{
3450 struct i40e_q_vector *q_vector = data;
3451 struct i40e_vsi *vsi;
3452
3453 if (!q_vector->tx.ring)
3454 return IRQ_HANDLED;
3455
3456 vsi = q_vector->tx.ring->vsi;
3457 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3458
3459 return IRQ_HANDLED;
3460}
3461
41c445ff 3462/**
cd0b6fa6 3463 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3464 * @vsi: the VSI being configured
3465 * @v_idx: vector index
cd0b6fa6 3466 * @qp_idx: queue pair index
41c445ff 3467 **/
26cdc443 3468static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3469{
493fb300 3470 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3471 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3472 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3473
3474 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3475 tx_ring->next = q_vector->tx.ring;
3476 q_vector->tx.ring = tx_ring;
41c445ff 3477 q_vector->tx.count++;
cd0b6fa6
AD		 3478
3479 rx_ring->q_vector = q_vector;
3480 rx_ring->next = q_vector->rx.ring;
3481 q_vector->rx.ring = rx_ring;
3482 q_vector->rx.count++;
41c445ff
JB		 3483}
3484
3485/**
3486 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3487 * @vsi: the VSI being configured
3488 *
3489 * This function maps descriptor rings to the queue-specific vectors
3490 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3491 * one vector per queue pair, but on a constrained vector budget, we
3492 * group the queue pairs as "efficiently" as possible.
3493 **/
3494static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3495{
3496 int qp_remaining = vsi->num_queue_pairs;
3497 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3498 int num_ringpairs;
41c445ff
JB		 3499 int v_start = 0;
3500 int qp_idx = 0;
3501
3502 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3503 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3504 * It is also important to go through all the vectors available to be
3505 * sure that if we don't use all the vectors, that the remaining vectors
3506 * are cleared. This is especially important when decreasing the
3507 * number of queues in use.
41c445ff 3508 */
70114ec4 3509 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3510 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3511
3512 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3513
3514 q_vector->num_ringpairs = num_ringpairs;
3515
3516 q_vector->rx.count = 0;
3517 q_vector->tx.count = 0;
3518 q_vector->rx.ring = NULL;
3519 q_vector->tx.ring = NULL;
3520
3521 while (num_ringpairs--) {
26cdc443 3522 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3523 qp_idx++;
3524 qp_remaining--;
41c445ff
JB		 3525 }
3526 }
3527}
3528
3529/**
3530 * i40e_vsi_request_irq - Request IRQ from the OS
3531 * @vsi: the VSI being configured
3532 * @basename: name for the vector
3533 **/
3534static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3535{
3536 struct i40e_pf *pf = vsi->back;
3537 int err;
3538
3539 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3540 err = i40e_vsi_request_irq_msix(vsi, basename);
3541 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3542 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3543 pf->int_name, pf);
41c445ff
JB		 3544 else
3545 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3546 pf->int_name, pf);
41c445ff
JB		 3547
3548 if (err)
3549 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3550
3551 return err;
3552}
3553
3554#ifdef CONFIG_NET_POLL_CONTROLLER
3555/**
3556 * i40e_netpoll - A Polling 'interrupt'handler
3557 * @netdev: network interface device structure
3558 *
3559 * This is used by netconsole to send skbs without having to re-enable
3560 * interrupts. It's not called while the normal interrupt routine is executing.
3561 **/
38e00438
VD		 3562#ifdef I40E_FCOE
3563void i40e_netpoll(struct net_device *netdev)
3564#else
41c445ff 3565static void i40e_netpoll(struct net_device *netdev)
38e00438 3566#endif
41c445ff
JB		 3567{
3568 struct i40e_netdev_priv *np = netdev_priv(netdev);
3569 struct i40e_vsi *vsi = np->vsi;
3570 struct i40e_pf *pf = vsi->back;
3571 int i;
3572
3573 /* if interface is down do nothing */
3574 if (test_bit(__I40E_DOWN, &vsi->state))
3575 return;
3576
3577 pf->flags |= I40E_FLAG_IN_NETPOLL;
3578 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3579 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3580 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3581 } else {
3582 i40e_intr(pf->pdev->irq, netdev);
3583 }
3584 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3585}
3586#endif
3587
23527308
NP		 3588/**
3589 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3590 * @pf: the PF being configured
3591 * @pf_q: the PF queue
3592 * @enable: enable or disable state of the queue
3593 *
3594 * This routine will wait for the given Tx queue of the PF to reach the
3595 * enabled or disabled state.
3596 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3597 * multiple retries; else will return 0 in case of success.
3598 **/
3599static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3600{
3601 int i;
3602 u32 tx_reg;
3603
3604 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3605 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3606 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3607 break;
3608
f98a2006 3609 usleep_range(10, 20);
23527308
NP		 3610 }
3611 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3612 return -ETIMEDOUT;
3613
3614 return 0;
3615}
3616
41c445ff
JB		 3617/**
3618 * i40e_vsi_control_tx - Start or stop a VSI's rings
3619 * @vsi: the VSI being configured
3620 * @enable: start or stop the rings
3621 **/
3622static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3623{
3624 struct i40e_pf *pf = vsi->back;
3625 struct i40e_hw *hw = &pf->hw;
23527308 3626 int i, j, pf_q, ret = 0;
41c445ff
JB		 3627 u32 tx_reg;
3628
3629 pf_q = vsi->base_queue;
3630 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3631
3632 /* warn the TX unit of coming changes */
3633 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3634 if (!enable)
f98a2006 3635 usleep_range(10, 20);
351499ab 3636
6c5ef620 3637 for (j = 0; j < 50; j++) {
41c445ff 3638 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3639 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3640 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3641 break;
3642 usleep_range(1000, 2000);
3643 }
fda972f6 3644 /* Skip if the queue is already in the requested state */
7c122007 3645 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3646 continue;
41c445ff
JB		 3647
3648 /* turn on/off the queue */
c5c9eb9e
SN		 3649 if (enable) {
3650 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3651 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3652 } else {
41c445ff 3653 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3654 }
41c445ff
JB		 3655
3656 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3657 /* No waiting for the Tx queue to disable */
3658 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3659 continue;
41c445ff
JB		 3660
3661 /* wait for the change to finish */
23527308
NP		 3662 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3663 if (ret) {
3664 dev_info(&pf->pdev->dev,
fb43201f
SN		 3665 "VSI seid %d Tx ring %d %sable timeout\n",
3666 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3667 break;
41c445ff
JB		 3668 }
3669 }
3670
7134f9ce
JB		 3671 if (hw->revision_id == 0)
3672 mdelay(50);
23527308
NP		 3673 return ret;
3674}
3675
3676/**
3677 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3678 * @pf: the PF being configured
3679 * @pf_q: the PF queue
3680 * @enable: enable or disable state of the queue
3681 *
3682 * This routine will wait for the given Rx queue of the PF to reach the
3683 * enabled or disabled state.
3684 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3685 * multiple retries; else will return 0 in case of success.
3686 **/
3687static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3688{
3689 int i;
3690 u32 rx_reg;
3691
3692 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3693 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3694 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3695 break;
3696
f98a2006 3697 usleep_range(10, 20);
23527308
NP		 3698 }
3699 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3700 return -ETIMEDOUT;
7134f9ce 3701
41c445ff
JB		 3702 return 0;
3703}
3704
3705/**
3706 * i40e_vsi_control_rx - Start or stop a VSI's rings
3707 * @vsi: the VSI being configured
3708 * @enable: start or stop the rings
3709 **/
3710static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3711{
3712 struct i40e_pf *pf = vsi->back;
3713 struct i40e_hw *hw = &pf->hw;
23527308 3714 int i, j, pf_q, ret = 0;
41c445ff
JB		 3715 u32 rx_reg;
3716
3717 pf_q = vsi->base_queue;
3718 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3719 for (j = 0; j < 50; j++) {
41c445ff 3720 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3721 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3722 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3723 break;
3724 usleep_range(1000, 2000);
3725 }
41c445ff 3726
7c122007
CS		 3727 /* Skip if the queue is already in the requested state */
3728 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3729 continue;
41c445ff
JB		 3730
3731 /* turn on/off the queue */
3732 if (enable)
6c5ef620 3733 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3734 else
6c5ef620 3735 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3736 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3737
3738 /* wait for the change to finish */
23527308
NP		 3739 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3740 if (ret) {
3741 dev_info(&pf->pdev->dev,
fb43201f
SN		 3742 "VSI seid %d Rx ring %d %sable timeout\n",
3743 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3744 break;
41c445ff
JB		 3745 }
3746 }
3747
23527308 3748 return ret;
41c445ff
JB		 3749}
3750
3751/**
3752 * i40e_vsi_control_rings - Start or stop a VSI's rings
3753 * @vsi: the VSI being configured
3754 * @enable: start or stop the rings
3755 **/
fc18eaa0 3756int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3757{
3b867b28 3758 int ret = 0;
41c445ff
JB		 3759
3760 /* do rx first for enable and last for disable */
3761 if (request) {
3762 ret = i40e_vsi_control_rx(vsi, request);
3763 if (ret)
3764 return ret;
3765 ret = i40e_vsi_control_tx(vsi, request);
3766 } else {
3b867b28
ASJ		 3767 /* Ignore return value, we need to shutdown whatever we can */
3768 i40e_vsi_control_tx(vsi, request);
3769 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3770 }
3771
3772 return ret;
3773}
3774
3775/**
3776 * i40e_vsi_free_irq - Free the irq association with the OS
3777 * @vsi: the VSI being configured
3778 **/
3779static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3780{
3781 struct i40e_pf *pf = vsi->back;
3782 struct i40e_hw *hw = &pf->hw;
3783 int base = vsi->base_vector;
3784 u32 val, qp;
3785 int i;
3786
3787 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3788 if (!vsi->q_vectors)
3789 return;
3790
63741846
SN		 3791 if (!vsi->irqs_ready)
3792 return;
3793
3794 vsi->irqs_ready = false;
41c445ff
JB		 3795 for (i = 0; i < vsi->num_q_vectors; i++) {
3796 u16 vector = i + base;
3797
3798 /* free only the irqs that were actually requested */
78681b1f
SN		 3799 if (!vsi->q_vectors[i] ||
3800 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3801 continue;
3802
3803 /* clear the affinity_mask in the IRQ descriptor */
3804 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3805 NULL);
3806 free_irq(pf->msix_entries[vector].vector,
493fb300 3807 vsi->q_vectors[i]);
41c445ff
JB		 3808
3809 /* Tear down the interrupt queue link list
3810 *
3811 * We know that they come in pairs and always
3812 * the Rx first, then the Tx. To clear the
3813 * link list, stick the EOL value into the
3814 * next_q field of the registers.
3815 */
3816 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3817 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3818 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3819 val |= I40E_QUEUE_END_OF_LIST
3820 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3821 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3822
3823 while (qp != I40E_QUEUE_END_OF_LIST) {
3824 u32 next;
3825
3826 val = rd32(hw, I40E_QINT_RQCTL(qp));
3827
3828 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3829 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3830 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3831 I40E_QINT_RQCTL_INTEVENT_MASK);
3832
3833 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3834 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3835
3836 wr32(hw, I40E_QINT_RQCTL(qp), val);
3837
3838 val = rd32(hw, I40E_QINT_TQCTL(qp));
3839
3840 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3841 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3842
3843 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3844 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3845 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3846 I40E_QINT_TQCTL_INTEVENT_MASK);
3847
3848 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3849 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3850
3851 wr32(hw, I40E_QINT_TQCTL(qp), val);
3852 qp = next;
3853 }
3854 }
3855 } else {
3856 free_irq(pf->pdev->irq, pf);
3857
3858 val = rd32(hw, I40E_PFINT_LNKLST0);
3859 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3860 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3861 val |= I40E_QUEUE_END_OF_LIST
3862 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3863 wr32(hw, I40E_PFINT_LNKLST0, val);
3864
3865 val = rd32(hw, I40E_QINT_RQCTL(qp));
3866 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3867 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3868 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3869 I40E_QINT_RQCTL_INTEVENT_MASK);
3870
3871 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3872 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3873
3874 wr32(hw, I40E_QINT_RQCTL(qp), val);
3875
3876 val = rd32(hw, I40E_QINT_TQCTL(qp));
3877
3878 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3879 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3880 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3881 I40E_QINT_TQCTL_INTEVENT_MASK);
3882
3883 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3884 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3885
3886 wr32(hw, I40E_QINT_TQCTL(qp), val);
3887 }
3888}
3889
493fb300
AD		 3890/**
3891 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3892 * @vsi: the VSI being configured
3893 * @v_idx: Index of vector to be freed
3894 *
3895 * This function frees the memory allocated to the q_vector. In addition if
3896 * NAPI is enabled it will delete any references to the NAPI struct prior
3897 * to freeing the q_vector.
3898 **/
3899static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3900{
3901 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3902 struct i40e_ring *ring;
493fb300
AD		 3903
3904 if (!q_vector)
3905 return;
3906
3907 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3908 i40e_for_each_ring(ring, q_vector->tx)
3909 ring->q_vector = NULL;
3910
3911 i40e_for_each_ring(ring, q_vector->rx)
3912 ring->q_vector = NULL;
493fb300
AD		 3913
3914 /* only VSI w/ an associated netdev is set up w/ NAPI */
3915 if (vsi->netdev)
3916 netif_napi_del(&q_vector->napi);
3917
3918 vsi->q_vectors[v_idx] = NULL;
3919
3920 kfree_rcu(q_vector, rcu);
3921}
3922
41c445ff
JB		 3923/**
3924 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3925 * @vsi: the VSI being un-configured
3926 *
3927 * This frees the memory allocated to the q_vectors and
3928 * deletes references to the NAPI struct.
3929 **/
3930static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3931{
3932 int v_idx;
3933
493fb300
AD		 3934 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3935 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3936}
3937
3938/**
3939 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3940 * @pf: board private structure
3941 **/
3942static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3943{
3944 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3945 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3946 pci_disable_msix(pf->pdev);
3947 kfree(pf->msix_entries);
3948 pf->msix_entries = NULL;
3b444399
SN		 3949 kfree(pf->irq_pile);
3950 pf->irq_pile = NULL;
41c445ff
JB		 3951 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3952 pci_disable_msi(pf->pdev);
3953 }
3954 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3955}
3956
3957/**
3958 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3959 * @pf: board private structure
3960 *
3961 * We go through and clear interrupt specific resources and reset the structure
3962 * to pre-load conditions
3963 **/
3964static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3965{
3966 int i;
3967
e147758d
SN		 3968 i40e_stop_misc_vector(pf);
3969 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3970 synchronize_irq(pf->msix_entries[0].vector);
3971 free_irq(pf->msix_entries[0].vector, pf);
3972 }
3973
41c445ff 3974 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3975 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3976 if (pf->vsi[i])
3977 i40e_vsi_free_q_vectors(pf->vsi[i]);
3978 i40e_reset_interrupt_capability(pf);
3979}
3980
3981/**
3982 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3983 * @vsi: the VSI being configured
3984 **/
3985static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3986{
3987 int q_idx;
3988
3989 if (!vsi->netdev)
3990 return;
3991
3992 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3993 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3994}
3995
3996/**
3997 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3998 * @vsi: the VSI being configured
3999 **/
4000static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4001{
4002 int q_idx;
4003
4004 if (!vsi->netdev)
4005 return;
4006
4007 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4008 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4009}
4010
90ef8d47
SN		 4011/**
4012 * i40e_vsi_close - Shut down a VSI
4013 * @vsi: the vsi to be quelled
4014 **/
4015static void i40e_vsi_close(struct i40e_vsi *vsi)
4016{
4017 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4018 i40e_down(vsi);
4019 i40e_vsi_free_irq(vsi);
4020 i40e_vsi_free_tx_resources(vsi);
4021 i40e_vsi_free_rx_resources(vsi);
92faef85 4022 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4023}
4024
41c445ff
JB		 4025/**
4026 * i40e_quiesce_vsi - Pause a given VSI
4027 * @vsi: the VSI being paused
4028 **/
4029static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4030{
4031 if (test_bit(__I40E_DOWN, &vsi->state))
4032 return;
4033
d341b7a5
NP		 4034 /* No need to disable FCoE VSI when Tx suspended */
4035 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4036 vsi->type == I40E_VSI_FCOE) {
4037 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4038 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4039 return;
4040 }
4041
41c445ff 4042 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4043 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4044 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4045 else
90ef8d47 4046 i40e_vsi_close(vsi);
41c445ff
JB		 4047}
4048
4049/**
4050 * i40e_unquiesce_vsi - Resume a given VSI
4051 * @vsi: the VSI being resumed
4052 **/
4053static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4054{
4055 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4056 return;
4057
4058 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4059 if (vsi->netdev && netif_running(vsi->netdev))
4060 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4061 else
8276f757 4062 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4063}
4064
4065/**
4066 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4067 * @pf: the PF
4068 **/
4069static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4070{
4071 int v;
4072
505682cd 4073 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4074 if (pf->vsi[v])
4075 i40e_quiesce_vsi(pf->vsi[v]);
4076 }
4077}
4078
4079/**
4080 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4081 * @pf: the PF
4082 **/
4083static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4084{
4085 int v;
4086
505682cd 4087 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4088 if (pf->vsi[v])
4089 i40e_unquiesce_vsi(pf->vsi[v]);
4090 }
4091}
4092
69129dc3
NP		 4093#ifdef CONFIG_I40E_DCB
4094/**
4095 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4096 * @vsi: the VSI being configured
4097 *
4098 * This function waits for the given VSI's Tx queues to be disabled.
4099 **/
4100static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4101{
4102 struct i40e_pf *pf = vsi->back;
4103 int i, pf_q, ret;
4104
4105 pf_q = vsi->base_queue;
4106 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4107 /* Check and wait for the disable status of the queue */
4108 ret = i40e_pf_txq_wait(pf, pf_q, false);
4109 if (ret) {
4110 dev_info(&pf->pdev->dev,
fb43201f
SN		 4111 "VSI seid %d Tx ring %d disable timeout\n",
4112 vsi->seid, pf_q);
69129dc3
NP		 4113 return ret;
4114 }
4115 }
4116
4117 return 0;
4118}
4119
4120/**
4121 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4122 * @pf: the PF
4123 *
4124 * This function waits for the Tx queues to be in disabled state for all the
4125 * VSIs that are managed by this PF.
4126 **/
4127static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4128{
4129 int v, ret = 0;
4130
4131 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4132 /* No need to wait for FCoE VSI queues */
4133 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4134 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4135 if (ret)
4136 break;
4137 }
4138 }
4139
4140 return ret;
4141}
4142
4143#endif
b03a8c1f
KP		 4144
4145/**
4146 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4147 * @q_idx: TX queue number
4148 * @vsi: Pointer to VSI struct
4149 *
4150 * This function checks specified queue for given VSI. Detects hung condition.
4151 * Sets hung bit since it is two step process. Before next run of service task
4152 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4153 * hung condition remain unchanged and during subsequent run, this function
4154 * issues SW interrupt to recover from hung condition.
4155 **/
4156static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4157{
4158 struct i40e_ring *tx_ring = NULL;
4159 struct i40e_pf *pf;
4160 u32 head, val, tx_pending;
4161 int i;
4162
4163 pf = vsi->back;
4164
4165 /* now that we have an index, find the tx_ring struct */
4166 for (i = 0; i < vsi->num_queue_pairs; i++) {
4167 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4168 if (q_idx == vsi->tx_rings[i]->queue_index) {
4169 tx_ring = vsi->tx_rings[i];
4170 break;
4171 }
4172 }
4173 }
4174
4175 if (!tx_ring)
4176 return;
4177
4178 /* Read interrupt register */
4179 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4180 val = rd32(&pf->hw,
4181 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4182 tx_ring->vsi->base_vector - 1));
4183 else
4184 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4185
4186 head = i40e_get_head(tx_ring);
4187
4188 tx_pending = i40e_get_tx_pending(tx_ring);
4189
4190 /* Interrupts are disabled and TX pending is non-zero,
4191 * trigger the SW interrupt (don't wait). Worst case
4192 * there will be one extra interrupt which may result
4193 * into not cleaning any queues because queues are cleaned.
4194 */
4195 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4196 i40e_force_wb(vsi, tx_ring->q_vector);
4197}
4198
4199/**
4200 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4201 * @pf: pointer to PF struct
4202 *
4203 * LAN VSI has netdev and netdev has TX queues. This function is to check
4204 * each of those TX queues if they are hung, trigger recovery by issuing
4205 * SW interrupt.
4206 **/
4207static void i40e_detect_recover_hung(struct i40e_pf *pf)
4208{
4209 struct net_device *netdev;
4210 struct i40e_vsi *vsi;
4211 int i;
4212
4213 /* Only for LAN VSI */
4214 vsi = pf->vsi[pf->lan_vsi];
4215
4216 if (!vsi)
4217 return;
4218
4219 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4220 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4221 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4222 return;
4223
4224 /* Make sure type is MAIN VSI */
4225 if (vsi->type != I40E_VSI_MAIN)
4226 return;
4227
4228 netdev = vsi->netdev;
4229 if (!netdev)
4230 return;
4231
4232 /* Bail out if netif_carrier is not OK */
4233 if (!netif_carrier_ok(netdev))
4234 return;
4235
4236 /* Go thru' TX queues for netdev */
4237 for (i = 0; i < netdev->num_tx_queues; i++) {
4238 struct netdev_queue *q;
4239
4240 q = netdev_get_tx_queue(netdev, i);
4241 if (q)
4242 i40e_detect_recover_hung_queue(i, vsi);
4243 }
4244}
4245
63d7e5a4
NP		 4246/**
4247 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4248 * @pf: pointer to PF
63d7e5a4
NP		 4249 *
4250 * Get TC map for ISCSI PF type that will include iSCSI TC
4251 * and LAN TC.
4252 **/
4253static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4254{
4255 struct i40e_dcb_app_priority_table app;
4256 struct i40e_hw *hw = &pf->hw;
4257 u8 enabled_tc = 1; /* TC0 is always enabled */
4258 u8 tc, i;
4259 /* Get the iSCSI APP TLV */
4260 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4261
4262 for (i = 0; i < dcbcfg->numapps; i++) {
4263 app = dcbcfg->app[i];
4264 if (app.selector == I40E_APP_SEL_TCPIP &&
4265 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4266 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4267 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4268 break;
4269 }
4270 }
4271
4272 return enabled_tc;
4273}
4274
41c445ff
JB		 4275/**
4276 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4277 * @dcbcfg: the corresponding DCBx configuration structure
4278 *
4279 * Return the number of TCs from given DCBx configuration
4280 **/
4281static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4282{
078b5876
JB		 4283 u8 num_tc = 0;
4284 int i;
41c445ff
JB		 4285
4286 /* Scan the ETS Config Priority Table to find
4287 * traffic class enabled for a given priority
4288 * and use the traffic class index to get the
4289 * number of traffic classes enabled
4290 */
4291 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4292 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4293 num_tc = dcbcfg->etscfg.prioritytable[i];
4294 }
4295
4296 /* Traffic class index starts from zero so
4297 * increment to return the actual count
4298 */
078b5876 4299 return num_tc + 1;
41c445ff
JB		 4300}
4301
4302/**
4303 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4304 * @dcbcfg: the corresponding DCBx configuration structure
4305 *
4306 * Query the current DCB configuration and return the number of
4307 * traffic classes enabled from the given DCBX config
4308 **/
4309static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4310{
4311 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4312 u8 enabled_tc = 1;
4313 u8 i;
4314
4315 for (i = 0; i < num_tc; i++)
41a1d04b 4316 enabled_tc |= BIT(i);
41c445ff
JB		 4317
4318 return enabled_tc;
4319}
4320
4321/**
4322 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4323 * @pf: PF being queried
4324 *
4325 * Return number of traffic classes enabled for the given PF
4326 **/
4327static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4328{
4329 struct i40e_hw *hw = &pf->hw;
4330 u8 i, enabled_tc;
4331 u8 num_tc = 0;
4332 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4333
4334 /* If DCB is not enabled then always in single TC */
4335 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4336 return 1;
4337
63d7e5a4
NP		 4338 /* SFP mode will be enabled for all TCs on port */
4339 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4340 return i40e_dcb_get_num_tc(dcbcfg);
4341
41c445ff 4342 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4343 if (pf->hw.func_caps.iscsi)
4344 enabled_tc = i40e_get_iscsi_tc_map(pf);
4345 else
fc51de96 4346 return 1; /* Only TC0 */
41c445ff 4347
63d7e5a4
NP		 4348 /* At least have TC0 */
4349 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4350 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4351 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4352 num_tc++;
4353 }
4354 return num_tc;
41c445ff
JB		 4355}
4356
4357/**
4358 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4359 * @pf: PF being queried
4360 *
4361 * Return a bitmap for first enabled traffic class for this PF.
4362 **/
4363static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4364{
4365 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4366 u8 i = 0;
4367
4368 if (!enabled_tc)
4369 return 0x1; /* TC0 */
4370
4371 /* Find the first enabled TC */
4372 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4373 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4374 break;
4375 }
4376
41a1d04b 4377 return BIT(i);
41c445ff
JB		 4378}
4379
4380/**
4381 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4382 * @pf: PF being queried
4383 *
4384 * Return a bitmap for enabled traffic classes for this PF.
4385 **/
4386static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4387{
4388 /* If DCB is not enabled for this PF then just return default TC */
4389 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4390 return i40e_pf_get_default_tc(pf);
4391
41c445ff 4392 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4393 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4394 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4395
fc51de96 4396 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4397 if (pf->hw.func_caps.iscsi)
4398 return i40e_get_iscsi_tc_map(pf);
4399 else
fc51de96 4400 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4401}
4402
4403/**
4404 * i40e_vsi_get_bw_info - Query VSI BW Information
4405 * @vsi: the VSI being queried
4406 *
4407 * Returns 0 on success, negative value on failure
4408 **/
4409static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4410{
4411 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4412 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4413 struct i40e_pf *pf = vsi->back;
4414 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4415 i40e_status ret;
41c445ff 4416 u32 tc_bw_max;
41c445ff
JB		 4417 int i;
4418
4419 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4420 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4421 if (ret) {
41c445ff 4422 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4423 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4424 i40e_stat_str(&pf->hw, ret),
4425 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4426 return -EINVAL;
41c445ff
JB		 4427 }
4428
4429 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4430 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4431 NULL);
4432 if (ret) {
41c445ff 4433 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4434 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4435 i40e_stat_str(&pf->hw, ret),
4436 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4437 return -EINVAL;
41c445ff
JB		 4438 }
4439
4440 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4441 dev_info(&pf->pdev->dev,
4442 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4443 bw_config.tc_valid_bits,
4444 bw_ets_config.tc_valid_bits);
4445 /* Still continuing */
4446 }
4447
4448 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4449 vsi->bw_max_quanta = bw_config.max_bw;
4450 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4451 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4452 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4453 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4454 vsi->bw_ets_limit_credits[i] =
4455 le16_to_cpu(bw_ets_config.credits[i]);
4456 /* 3 bits out of 4 for each TC */
4457 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4458 }
078b5876 4459
dcae29be 4460 return 0;
41c445ff
JB		 4461}
4462
4463/**
4464 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4465 * @vsi: the VSI being configured
4466 * @enabled_tc: TC bitmap
4467 * @bw_credits: BW shared credits per TC
4468 *
4469 * Returns 0 on success, negative value on failure
4470 **/
dcae29be 4471static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4472 u8 *bw_share)
4473{
4474 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4475 i40e_status ret;
dcae29be 4476 int i;
41c445ff
JB		 4477
4478 bw_data.tc_valid_bits = enabled_tc;
4479 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4480 bw_data.tc_bw_credits[i] = bw_share[i];
4481
f1c7e72e
SN		 4482 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4483 NULL);
4484 if (ret) {
41c445ff 4485 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4486 "AQ command Config VSI BW allocation per TC failed = %d\n",
4487 vsi->back->hw.aq.asq_last_status);
dcae29be 4488 return -EINVAL;
41c445ff
JB		 4489 }
4490
4491 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4492 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4493
dcae29be 4494 return 0;
41c445ff
JB		 4495}
4496
4497/**
4498 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4499 * @vsi: the VSI being configured
4500 * @enabled_tc: TC map to be enabled
4501 *
4502 **/
4503static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4504{
4505 struct net_device *netdev = vsi->netdev;
4506 struct i40e_pf *pf = vsi->back;
4507 struct i40e_hw *hw = &pf->hw;
4508 u8 netdev_tc = 0;
4509 int i;
4510 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4511
4512 if (!netdev)
4513 return;
4514
4515 if (!enabled_tc) {
4516 netdev_reset_tc(netdev);
4517 return;
4518 }
4519
4520 /* Set up actual enabled TCs on the VSI */
4521 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4522 return;
4523
4524 /* set per TC queues for the VSI */
4525 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4526 /* Only set TC queues for enabled tcs
4527 *
4528 * e.g. For a VSI that has TC0 and TC3 enabled the
4529 * enabled_tc bitmap would be 0x00001001; the driver
4530 * will set the numtc for netdev as 2 that will be
4531 * referenced by the netdev layer as TC 0 and 1.
4532 */
41a1d04b 4533 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4534 netdev_set_tc_queue(netdev,
4535 vsi->tc_config.tc_info[i].netdev_tc,
4536 vsi->tc_config.tc_info[i].qcount,
4537 vsi->tc_config.tc_info[i].qoffset);
4538 }
4539
4540 /* Assign UP2TC map for the VSI */
4541 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4542 /* Get the actual TC# for the UP */
4543 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4544 /* Get the mapped netdev TC# for the UP */
4545 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4546 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4547 }
4548}
4549
4550/**
4551 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4552 * @vsi: the VSI being configured
4553 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4554 **/
4555static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4556 struct i40e_vsi_context *ctxt)
4557{
4558 /* copy just the sections touched not the entire info
4559 * since not all sections are valid as returned by
4560 * update vsi params
4561 */
4562 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4563 memcpy(&vsi->info.queue_mapping,
4564 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4565 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4566 sizeof(vsi->info.tc_mapping));
4567}
4568
4569/**
4570 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4571 * @vsi: VSI to be configured
4572 * @enabled_tc: TC bitmap
4573 *
4574 * This configures a particular VSI for TCs that are mapped to the
4575 * given TC bitmap. It uses default bandwidth share for TCs across
4576 * VSIs to configure TC for a particular VSI.
4577 *
4578 * NOTE:
4579 * It is expected that the VSI queues have been quisced before calling
4580 * this function.
4581 **/
4582static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4583{
4584 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4585 struct i40e_vsi_context ctxt;
4586 int ret = 0;
4587 int i;
4588
4589 /* Check if enabled_tc is same as existing or new TCs */
4590 if (vsi->tc_config.enabled_tc == enabled_tc)
4591 return ret;
4592
4593 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4594 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4595 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4596 bw_share[i] = 1;
4597 }
4598
4599 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4600 if (ret) {
4601 dev_info(&vsi->back->pdev->dev,
4602 "Failed configuring TC map %d for VSI %d\n",
4603 enabled_tc, vsi->seid);
4604 goto out;
4605 }
4606
4607 /* Update Queue Pairs Mapping for currently enabled UPs */
4608 ctxt.seid = vsi->seid;
4609 ctxt.pf_num = vsi->back->hw.pf_id;
4610 ctxt.vf_num = 0;
4611 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4612 ctxt.info = vsi->info;
41c445ff
JB		 4613 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4614
4615 /* Update the VSI after updating the VSI queue-mapping information */
4616 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4617 if (ret) {
4618 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4619 "Update vsi tc config failed, err %s aq_err %s\n",
4620 i40e_stat_str(&vsi->back->hw, ret),
4621 i40e_aq_str(&vsi->back->hw,
4622 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4623 goto out;
4624 }
4625 /* update the local VSI info with updated queue map */
4626 i40e_vsi_update_queue_map(vsi, &ctxt);
4627 vsi->info.valid_sections = 0;
4628
4629 /* Update current VSI BW information */
4630 ret = i40e_vsi_get_bw_info(vsi);
4631 if (ret) {
4632 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4633 "Failed updating vsi bw info, err %s aq_err %s\n",
4634 i40e_stat_str(&vsi->back->hw, ret),
4635 i40e_aq_str(&vsi->back->hw,
4636 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4637 goto out;
4638 }
4639
4640 /* Update the netdev TC setup */
4641 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4642out:
4643 return ret;
4644}
4645
4e3b35b0
NP		 4646/**
4647 * i40e_veb_config_tc - Configure TCs for given VEB
4648 * @veb: given VEB
4649 * @enabled_tc: TC bitmap
4650 *
4651 * Configures given TC bitmap for VEB (switching) element
4652 **/
4653int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4654{
4655 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4656 struct i40e_pf *pf = veb->pf;
4657 int ret = 0;
4658 int i;
4659
4660 /* No TCs or already enabled TCs just return */
4661 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4662 return ret;
4663
4664 bw_data.tc_valid_bits = enabled_tc;
4665 /* bw_data.absolute_credits is not set (relative) */
4666
4667 /* Enable ETS TCs with equal BW Share for now */
4668 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4669 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4670 bw_data.tc_bw_share_credits[i] = 1;
4671 }
4672
4673 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4674 &bw_data, NULL);
4675 if (ret) {
4676 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4677 "VEB bw config failed, err %s aq_err %s\n",
4678 i40e_stat_str(&pf->hw, ret),
4679 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4680 goto out;
4681 }
4682
4683 /* Update the BW information */
4684 ret = i40e_veb_get_bw_info(veb);
4685 if (ret) {
4686 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4687 "Failed getting veb bw config, err %s aq_err %s\n",
4688 i40e_stat_str(&pf->hw, ret),
4689 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4690 }
4691
4692out:
4693 return ret;
4694}
4695
4696#ifdef CONFIG_I40E_DCB
4697/**
4698 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4699 * @pf: PF struct
4700 *
4701 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4702 * the caller would've quiesce all the VSIs before calling
4703 * this function
4704 **/
4705static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4706{
4707 u8 tc_map = 0;
4708 int ret;
4709 u8 v;
4710
4711 /* Enable the TCs available on PF to all VEBs */
4712 tc_map = i40e_pf_get_tc_map(pf);
4713 for (v = 0; v < I40E_MAX_VEB; v++) {
4714 if (!pf->veb[v])
4715 continue;
4716 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4717 if (ret) {
4718 dev_info(&pf->pdev->dev,
4719 "Failed configuring TC for VEB seid=%d\n",
4720 pf->veb[v]->seid);
4721 /* Will try to configure as many components */
4722 }
4723 }
4724
4725 /* Update each VSI */
505682cd 4726 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4727 if (!pf->vsi[v])
4728 continue;
4729
4730 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4731#ifdef I40E_FCOE
4732 * - For FCoE VSI only enable the TC configured
4733 * as per the APP TLV
4734#endif
4e3b35b0
NP		 4735 * - For all others keep them at TC0 for now
4736 */
4737 if (v == pf->lan_vsi)
4738 tc_map = i40e_pf_get_tc_map(pf);
4739 else
4740 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4741#ifdef I40E_FCOE
4742 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4743 tc_map = i40e_get_fcoe_tc_map(pf);
4744#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4745
4746 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4747 if (ret) {
4748 dev_info(&pf->pdev->dev,
4749 "Failed configuring TC for VSI seid=%d\n",
4750 pf->vsi[v]->seid);
4751 /* Will try to configure as many components */
4752 } else {
0672a091
NP		 4753 /* Re-configure VSI vectors based on updated TC map */
4754 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4755 if (pf->vsi[v]->netdev)
4756 i40e_dcbnl_set_all(pf->vsi[v]);
4757 }
4758 }
4759}
4760
2fd75f31
NP		 4761/**
4762 * i40e_resume_port_tx - Resume port Tx
4763 * @pf: PF struct
4764 *
4765 * Resume a port's Tx and issue a PF reset in case of failure to
4766 * resume.
4767 **/
4768static int i40e_resume_port_tx(struct i40e_pf *pf)
4769{
4770 struct i40e_hw *hw = &pf->hw;
4771 int ret;
4772
4773 ret = i40e_aq_resume_port_tx(hw, NULL);
4774 if (ret) {
4775 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4776 "Resume Port Tx failed, err %s aq_err %s\n",
4777 i40e_stat_str(&pf->hw, ret),
4778 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4779 /* Schedule PF reset to recover */
4780 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4781 i40e_service_event_schedule(pf);
4782 }
4783
4784 return ret;
4785}
4786
4e3b35b0
NP		 4787/**
4788 * i40e_init_pf_dcb - Initialize DCB configuration
4789 * @pf: PF being configured
4790 *
4791 * Query the current DCB configuration and cache it
4792 * in the hardware structure
4793 **/
4794static int i40e_init_pf_dcb(struct i40e_pf *pf)
4795{
4796 struct i40e_hw *hw = &pf->hw;
4797 int err = 0;
4798
025b4a54
ASJ		 4799 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4800 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4801 (pf->hw.aq.fw_maj_ver < 4))
4802 goto out;
4803
4e3b35b0
NP		 4804 /* Get the initial DCB configuration */
4805 err = i40e_init_dcb(hw);
4806 if (!err) {
4807 /* Device/Function is not DCBX capable */
4808 if ((!hw->func_caps.dcb) ||
4809 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4810 dev_info(&pf->pdev->dev,
4811 "DCBX offload is not supported or is disabled for this PF.\n");
4812
4813 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4814 goto out;
4815
4816 } else {
4817 /* When status is not DISABLED then DCBX in FW */
4818 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4819 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4820
4821 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4822 /* Enable DCB tagging only when more than one TC */
4823 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4824 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4825 dev_dbg(&pf->pdev->dev,
4826 "DCBX offload is supported for this PF.\n");
4e3b35b0 4827 }
014269ff 4828 } else {
aebfc816 4829 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4830 "Query for DCB configuration failed, err %s aq_err %s\n",
4831 i40e_stat_str(&pf->hw, err),
4832 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4833 }
4834
4835out:
4836 return err;
4837}
4838#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4839#define SPEED_SIZE 14
4840#define FC_SIZE 8
4841/**
4842 * i40e_print_link_message - print link up or down
4843 * @vsi: the VSI for which link needs a message
4844 */
c156f856 4845void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08
JB		 4846{
4847 char speed[SPEED_SIZE] = "Unknown";
4848 char fc[FC_SIZE] = "RX/TX";
4849
c156f856
MJ		 4850 if (vsi->current_isup == isup)
4851 return;
4852 vsi->current_isup = isup;
cf05ed08
JB		 4853 if (!isup) {
4854 netdev_info(vsi->netdev, "NIC Link is Down\n");
4855 return;
4856 }
4857
148c2d80
GR		 4858 /* Warn user if link speed on NPAR enabled partition is not at
4859 * least 10GB
4860 */
4861 if (vsi->back->hw.func_caps.npar_enable &&
4862 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4863 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4864 netdev_warn(vsi->netdev,
4865 "The partition detected link speed that is less than 10Gbps\n");
4866
cf05ed08
JB		 4867 switch (vsi->back->hw.phy.link_info.link_speed) {
4868 case I40E_LINK_SPEED_40GB:
35a7d804 4869 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08 4870 break;
ae24b409
JB		 4871 case I40E_LINK_SPEED_20GB:
4872 strncpy(speed, "20 Gbps", SPEED_SIZE);
4873 break;
cf05ed08 4874 case I40E_LINK_SPEED_10GB:
35a7d804 4875 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4876 break;
4877 case I40E_LINK_SPEED_1GB:
35a7d804 4878 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4879 break;
5960d33f
MW		 4880 case I40E_LINK_SPEED_100MB:
4881 strncpy(speed, "100 Mbps", SPEED_SIZE);
4882 break;
cf05ed08
JB		 4883 default:
4884 break;
4885 }
4886
4887 switch (vsi->back->hw.fc.current_mode) {
4888 case I40E_FC_FULL:
35a7d804 4889 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4890 break;
4891 case I40E_FC_TX_PAUSE:
35a7d804 4892 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4893 break;
4894 case I40E_FC_RX_PAUSE:
35a7d804 4895 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4896 break;
4897 default:
35a7d804 4898 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4899 break;
4900 }
4901
4902 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4903 speed, fc);
4904}
4e3b35b0 4905
41c445ff
JB		 4906/**
4907 * i40e_up_complete - Finish the last steps of bringing up a connection
4908 * @vsi: the VSI being configured
4909 **/
4910static int i40e_up_complete(struct i40e_vsi *vsi)
4911{
4912 struct i40e_pf *pf = vsi->back;
4913 int err;
4914
4915 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4916 i40e_vsi_configure_msix(vsi);
4917 else
4918 i40e_configure_msi_and_legacy(vsi);
4919
4920 /* start rings */
4921 err = i40e_vsi_control_rings(vsi, true);
4922 if (err)
4923 return err;
4924
4925 clear_bit(__I40E_DOWN, &vsi->state);
4926 i40e_napi_enable_all(vsi);
4927 i40e_vsi_enable_irq(vsi);
4928
4929 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4930 (vsi->netdev)) {
cf05ed08 4931 i40e_print_link_message(vsi, true);
41c445ff
JB		 4932 netif_tx_start_all_queues(vsi->netdev);
4933 netif_carrier_on(vsi->netdev);
6d779b41 4934 } else if (vsi->netdev) {
cf05ed08 4935 i40e_print_link_message(vsi, false);
7b592f61
CW		 4936 /* need to check for qualified module here*/
4937 if ((pf->hw.phy.link_info.link_info &
4938 I40E_AQ_MEDIA_AVAILABLE) &&
4939 (!(pf->hw.phy.link_info.an_info &
4940 I40E_AQ_QUALIFIED_MODULE)))
4941 netdev_err(vsi->netdev,
4942 "the driver failed to link because an unqualified module was detected.");
41c445ff 4943 }
ca64fa4e
ASJ		 4944
4945 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4946 if (vsi->type == I40E_VSI_FDIR) {
4947 /* reset fd counters */
4948 pf->fd_add_err = pf->fd_atr_cnt = 0;
4949 if (pf->fd_tcp_rule > 0) {
4950 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4951 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4952 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4953 pf->fd_tcp_rule = 0;
4954 }
ca64fa4e 4955 i40e_fdir_filter_restore(vsi);
1e1be8f6 4956 }
41c445ff
JB		 4957 i40e_service_event_schedule(pf);
4958
4959 return 0;
4960}
4961
4962/**
4963 * i40e_vsi_reinit_locked - Reset the VSI
4964 * @vsi: the VSI being configured
4965 *
4966 * Rebuild the ring structs after some configuration
4967 * has changed, e.g. MTU size.
4968 **/
4969static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4970{
4971 struct i40e_pf *pf = vsi->back;
4972
4973 WARN_ON(in_interrupt());
4974 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4975 usleep_range(1000, 2000);
4976 i40e_down(vsi);
4977
4978 /* Give a VF some time to respond to the reset. The
4979 * two second wait is based upon the watchdog cycle in
4980 * the VF driver.
4981 */
4982 if (vsi->type == I40E_VSI_SRIOV)
4983 msleep(2000);
4984 i40e_up(vsi);
4985 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4986}
4987
4988/**
4989 * i40e_up - Bring the connection back up after being down
4990 * @vsi: the VSI being configured
4991 **/
4992int i40e_up(struct i40e_vsi *vsi)
4993{
4994 int err;
4995
4996 err = i40e_vsi_configure(vsi);
4997 if (!err)
4998 err = i40e_up_complete(vsi);
4999
5000 return err;
5001}
5002
5003/**
5004 * i40e_down - Shutdown the connection processing
5005 * @vsi: the VSI being stopped
5006 **/
5007void i40e_down(struct i40e_vsi *vsi)
5008{
5009 int i;
5010
5011 /* It is assumed that the caller of this function
5012 * sets the vsi->state __I40E_DOWN bit.
5013 */
5014 if (vsi->netdev) {
5015 netif_carrier_off(vsi->netdev);
5016 netif_tx_disable(vsi->netdev);
5017 }
5018 i40e_vsi_disable_irq(vsi);
5019 i40e_vsi_control_rings(vsi, false);
5020 i40e_napi_disable_all(vsi);
5021
5022 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5023 i40e_clean_tx_ring(vsi->tx_rings[i]);
5024 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5025 }
5026}
5027
5028/**
5029 * i40e_setup_tc - configure multiple traffic classes
5030 * @netdev: net device to configure
5031 * @tc: number of traffic classes to enable
5032 **/
38e00438
VD		 5033#ifdef I40E_FCOE
5034int i40e_setup_tc(struct net_device *netdev, u8 tc)
5035#else
41c445ff 5036static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5037#endif
41c445ff
JB		 5038{
5039 struct i40e_netdev_priv *np = netdev_priv(netdev);
5040 struct i40e_vsi *vsi = np->vsi;
5041 struct i40e_pf *pf = vsi->back;
5042 u8 enabled_tc = 0;
5043 int ret = -EINVAL;
5044 int i;
5045
5046 /* Check if DCB enabled to continue */
5047 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5048 netdev_info(netdev, "DCB is not enabled for adapter\n");
5049 goto exit;
5050 }
5051
5052 /* Check if MFP enabled */
5053 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5054 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5055 goto exit;
5056 }
5057
5058 /* Check whether tc count is within enabled limit */
5059 if (tc > i40e_pf_get_num_tc(pf)) {
5060 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5061 goto exit;
5062 }
5063
5064 /* Generate TC map for number of tc requested */
5065 for (i = 0; i < tc; i++)
41a1d04b 5066 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5067
5068 /* Requesting same TC configuration as already enabled */
5069 if (enabled_tc == vsi->tc_config.enabled_tc)
5070 return 0;
5071
5072 /* Quiesce VSI queues */
5073 i40e_quiesce_vsi(vsi);
5074
5075 /* Configure VSI for enabled TCs */
5076 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5077 if (ret) {
5078 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5079 vsi->seid);
5080 goto exit;
5081 }
5082
5083 /* Unquiesce VSI */
5084 i40e_unquiesce_vsi(vsi);
5085
5086exit:
5087 return ret;
5088}
5089
5090/**
5091 * i40e_open - Called when a network interface is made active
5092 * @netdev: network interface device structure
5093 *
5094 * The open entry point is called when a network interface is made
5095 * active by the system (IFF_UP). At this point all resources needed
5096 * for transmit and receive operations are allocated, the interrupt
5097 * handler is registered with the OS, the netdev watchdog subtask is
5098 * enabled, and the stack is notified that the interface is ready.
5099 *
5100 * Returns 0 on success, negative value on failure
5101 **/
38e00438 5102int i40e_open(struct net_device *netdev)
41c445ff
JB		 5103{
5104 struct i40e_netdev_priv *np = netdev_priv(netdev);
5105 struct i40e_vsi *vsi = np->vsi;
5106 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5107 int err;
5108
4eb3f768
SN		 5109 /* disallow open during test or if eeprom is broken */
5110 if (test_bit(__I40E_TESTING, &pf->state) ||
5111 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5112 return -EBUSY;
5113
5114 netif_carrier_off(netdev);
5115
6c167f58
EK		 5116 err = i40e_vsi_open(vsi);
5117 if (err)
5118 return err;
5119
059dab69
JB		 5120 /* configure global TSO hardware offload settings */
5121 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5122 TCP_FLAG_FIN) >> 16);
5123 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5124 TCP_FLAG_FIN |
5125 TCP_FLAG_CWR) >> 16);
5126 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5127
6c167f58
EK		 5128#ifdef CONFIG_I40E_VXLAN
5129 vxlan_get_rx_port(netdev);
5130#endif
5131
5132 return 0;
5133}
5134
5135/**
5136 * i40e_vsi_open -
5137 * @vsi: the VSI to open
5138 *
5139 * Finish initialization of the VSI.
5140 *
5141 * Returns 0 on success, negative value on failure
5142 **/
5143int i40e_vsi_open(struct i40e_vsi *vsi)
5144{
5145 struct i40e_pf *pf = vsi->back;
b294ac70 5146 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5147 int err;
5148
41c445ff
JB		 5149 /* allocate descriptors */
5150 err = i40e_vsi_setup_tx_resources(vsi);
5151 if (err)
5152 goto err_setup_tx;
5153 err = i40e_vsi_setup_rx_resources(vsi);
5154 if (err)
5155 goto err_setup_rx;
5156
5157 err = i40e_vsi_configure(vsi);
5158 if (err)
5159 goto err_setup_rx;
5160
c22e3c6c
SN		 5161 if (vsi->netdev) {
5162 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5163 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5164 err = i40e_vsi_request_irq(vsi, int_name);
5165 if (err)
5166 goto err_setup_rx;
41c445ff 5167
c22e3c6c
SN		 5168 /* Notify the stack of the actual queue counts. */
5169 err = netif_set_real_num_tx_queues(vsi->netdev,
5170 vsi->num_queue_pairs);
5171 if (err)
5172 goto err_set_queues;
25946ddb 5173
c22e3c6c
SN		 5174 err = netif_set_real_num_rx_queues(vsi->netdev,
5175 vsi->num_queue_pairs);
5176 if (err)
5177 goto err_set_queues;
8a9eb7d3
SN		 5178
5179 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5180 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5181 dev_driver_string(&pf->pdev->dev),
5182 dev_name(&pf->pdev->dev));
8a9eb7d3 5183 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5184
c22e3c6c 5185 } else {
ce9ccb17 5186 err = -EINVAL;
6c167f58
EK		 5187 goto err_setup_rx;
5188 }
25946ddb 5189
41c445ff
JB		 5190 err = i40e_up_complete(vsi);
5191 if (err)
5192 goto err_up_complete;
5193
41c445ff
JB		 5194 return 0;
5195
5196err_up_complete:
5197 i40e_down(vsi);
25946ddb 5198err_set_queues:
41c445ff
JB		 5199 i40e_vsi_free_irq(vsi);
5200err_setup_rx:
5201 i40e_vsi_free_rx_resources(vsi);
5202err_setup_tx:
5203 i40e_vsi_free_tx_resources(vsi);
5204 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5205 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5206
5207 return err;
5208}
5209
17a73f6b
JG		 5210/**
5211 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5212 * @pf: Pointer to PF
17a73f6b
JG		 5213 *
5214 * This function destroys the hlist where all the Flow Director
5215 * filters were saved.
5216 **/
5217static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5218{
5219 struct i40e_fdir_filter *filter;
5220 struct hlist_node *node2;
5221
5222 hlist_for_each_entry_safe(filter, node2,
5223 &pf->fdir_filter_list, fdir_node) {
5224 hlist_del(&filter->fdir_node);
5225 kfree(filter);
5226 }
5227 pf->fdir_pf_active_filters = 0;
5228}
5229
41c445ff
JB		 5230/**
5231 * i40e_close - Disables a network interface
5232 * @netdev: network interface device structure
5233 *
5234 * The close entry point is called when an interface is de-activated
5235 * by the OS. The hardware is still under the driver's control, but
5236 * this netdev interface is disabled.
5237 *
5238 * Returns 0, this is not allowed to fail
5239 **/
38e00438
VD		 5240#ifdef I40E_FCOE
5241int i40e_close(struct net_device *netdev)
5242#else
41c445ff 5243static int i40e_close(struct net_device *netdev)
38e00438 5244#endif
41c445ff
JB		 5245{
5246 struct i40e_netdev_priv *np = netdev_priv(netdev);
5247 struct i40e_vsi *vsi = np->vsi;
5248
90ef8d47 5249 i40e_vsi_close(vsi);
41c445ff
JB		 5250
5251 return 0;
5252}
5253
5254/**
5255 * i40e_do_reset - Start a PF or Core Reset sequence
5256 * @pf: board private structure
5257 * @reset_flags: which reset is requested
5258 *
5259 * The essential difference in resets is that the PF Reset
5260 * doesn't clear the packet buffers, doesn't reset the PE
5261 * firmware, and doesn't bother the other PFs on the chip.
5262 **/
5263void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5264{
5265 u32 val;
5266
5267 WARN_ON(in_interrupt());
5268
263fc48f
MW		 5269 if (i40e_check_asq_alive(&pf->hw))
5270 i40e_vc_notify_reset(pf);
5271
41c445ff 5272 /* do the biggest reset indicated */
41a1d04b 5273 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5274
5275 /* Request a Global Reset
5276 *
5277 * This will start the chip's countdown to the actual full
5278 * chip reset event, and a warning interrupt to be sent
5279 * to all PFs, including the requestor. Our handler
5280 * for the warning interrupt will deal with the shutdown
5281 * and recovery of the switch setup.
5282 */
69bfb110 5283 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5284 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5285 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5286 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5287
41a1d04b 5288 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5289
5290 /* Request a Core Reset
5291 *
5292 * Same as Global Reset, except does *not* include the MAC/PHY
5293 */
69bfb110 5294 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5295 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5296 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5297 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5298 i40e_flush(&pf->hw);
5299
41a1d04b 5300 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5301
5302 /* Request a PF Reset
5303 *
5304 * Resets only the PF-specific registers
5305 *
5306 * This goes directly to the tear-down and rebuild of
5307 * the switch, since we need to do all the recovery as
5308 * for the Core Reset.
5309 */
69bfb110 5310 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5311 i40e_handle_reset_warning(pf);
5312
41a1d04b 5313 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5314 int v;
5315
5316 /* Find the VSI(s) that requested a re-init */
5317 dev_info(&pf->pdev->dev,
5318 "VSI reinit requested\n");
505682cd 5319 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5320 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5321
41c445ff
JB		 5322 if (vsi != NULL &&
5323 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5324 i40e_vsi_reinit_locked(pf->vsi[v]);
5325 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5326 }
5327 }
41a1d04b 5328 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5329 int v;
5330
5331 /* Find the VSI(s) that needs to be brought down */
5332 dev_info(&pf->pdev->dev, "VSI down requested\n");
5333 for (v = 0; v < pf->num_alloc_vsi; v++) {
5334 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5335
b5d06f05
NP		 5336 if (vsi != NULL &&
5337 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5338 set_bit(__I40E_DOWN, &vsi->state);
5339 i40e_down(vsi);
5340 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5341 }
5342 }
41c445ff
JB		 5343 } else {
5344 dev_info(&pf->pdev->dev,
5345 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5346 }
5347}
5348
4e3b35b0
NP		 5349#ifdef CONFIG_I40E_DCB
5350/**
5351 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5352 * @pf: board private structure
5353 * @old_cfg: current DCB config
5354 * @new_cfg: new DCB config
5355 **/
5356bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5357 struct i40e_dcbx_config *old_cfg,
5358 struct i40e_dcbx_config *new_cfg)
5359{
5360 bool need_reconfig = false;
5361
5362 /* Check if ETS configuration has changed */
5363 if (memcmp(&new_cfg->etscfg,
5364 &old_cfg->etscfg,
5365 sizeof(new_cfg->etscfg))) {
5366 /* If Priority Table has changed reconfig is needed */
5367 if (memcmp(&new_cfg->etscfg.prioritytable,
5368 &old_cfg->etscfg.prioritytable,
5369 sizeof(new_cfg->etscfg.prioritytable))) {
5370 need_reconfig = true;
69bfb110 5371 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5372 }
5373
5374 if (memcmp(&new_cfg->etscfg.tcbwtable,
5375 &old_cfg->etscfg.tcbwtable,
5376 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5377 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5378
5379 if (memcmp(&new_cfg->etscfg.tsatable,
5380 &old_cfg->etscfg.tsatable,
5381 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5382 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5383 }
5384
5385 /* Check if PFC configuration has changed */
5386 if (memcmp(&new_cfg->pfc,
5387 &old_cfg->pfc,
5388 sizeof(new_cfg->pfc))) {
5389 need_reconfig = true;
69bfb110 5390 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5391 }
5392
5393 /* Check if APP Table has changed */
5394 if (memcmp(&new_cfg->app,
5395 &old_cfg->app,
3d9667a9 5396 sizeof(new_cfg->app))) {
4e3b35b0 5397 need_reconfig = true;
69bfb110 5398 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5399 }
4e3b35b0 5400
fb43201f 5401 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5402 return need_reconfig;
5403}
5404
5405/**
5406 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5407 * @pf: board private structure
5408 * @e: event info posted on ARQ
5409 **/
5410static int i40e_handle_lldp_event(struct i40e_pf *pf,
5411 struct i40e_arq_event_info *e)
5412{
5413 struct i40e_aqc_lldp_get_mib *mib =
5414 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5415 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5416 struct i40e_dcbx_config tmp_dcbx_cfg;
5417 bool need_reconfig = false;
5418 int ret = 0;
5419 u8 type;
5420
4d9b6043
NP		 5421 /* Not DCB capable or capability disabled */
5422 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5423 return ret;
5424
4e3b35b0
NP		 5425 /* Ignore if event is not for Nearest Bridge */
5426 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5427 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5428 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5429 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5430 return ret;
5431
5432 /* Check MIB Type and return if event for Remote MIB update */
5433 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5434 dev_dbg(&pf->pdev->dev,
fb43201f 5435 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5436 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5437 /* Update the remote cached instance and return */
5438 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5439 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5440 &hw->remote_dcbx_config);
5441 goto exit;
5442 }
5443
9fa61dd2 5444 /* Store the old configuration */
1a2f6248 5445 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5446
750fcbcf
NP		 5447 /* Reset the old DCBx configuration data */
5448 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5449 /* Get updated DCBX data from firmware */
5450 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5451 if (ret) {
f1c7e72e
SN		 5452 dev_info(&pf->pdev->dev,
5453 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5454 i40e_stat_str(&pf->hw, ret),
5455 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5456 goto exit;
5457 }
5458
5459 /* No change detected in DCBX configs */
750fcbcf
NP		 5460 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5461 sizeof(tmp_dcbx_cfg))) {
69bfb110 5462 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5463 goto exit;
5464 }
5465
750fcbcf
NP		 5466 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5467 &hw->local_dcbx_config);
4e3b35b0 5468
750fcbcf 5469 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5470
5471 if (!need_reconfig)
5472 goto exit;
5473
4d9b6043 5474 /* Enable DCB tagging only when more than one TC */
750fcbcf 5475 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5476 pf->flags |= I40E_FLAG_DCB_ENABLED;
5477 else
5478 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5479
69129dc3 5480 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5481 /* Reconfiguration needed quiesce all VSIs */
5482 i40e_pf_quiesce_all_vsi(pf);
5483
5484 /* Changes in configuration update VEB/VSI */
5485 i40e_dcb_reconfigure(pf);
5486
2fd75f31
NP		 5487 ret = i40e_resume_port_tx(pf);
5488
69129dc3 5489 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5490 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5491 if (ret)
5492 goto exit;
5493
5494 /* Wait for the PF's Tx queues to be disabled */
5495 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5496 if (ret) {
5497 /* Schedule PF reset to recover */
5498 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5499 i40e_service_event_schedule(pf);
5500 } else {
2fd75f31 5501 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5502 }
5503
4e3b35b0
NP		 5504exit:
5505 return ret;
5506}
5507#endif /* CONFIG_I40E_DCB */
5508
23326186
ASJ		 5509/**
5510 * i40e_do_reset_safe - Protected reset path for userland calls.
5511 * @pf: board private structure
5512 * @reset_flags: which reset is requested
5513 *
5514 **/
5515void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5516{
5517 rtnl_lock();
5518 i40e_do_reset(pf, reset_flags);
5519 rtnl_unlock();
5520}
5521
41c445ff
JB		 5522/**
5523 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5524 * @pf: board private structure
5525 * @e: event info posted on ARQ
5526 *
5527 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5528 * and VF queues
5529 **/
5530static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5531 struct i40e_arq_event_info *e)
5532{
5533 struct i40e_aqc_lan_overflow *data =
5534 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5535 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5536 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5537 struct i40e_hw *hw = &pf->hw;
5538 struct i40e_vf *vf;
5539 u16 vf_id;
5540
69bfb110
JB		 5541 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5542 queue, qtx_ctl);
41c445ff
JB		 5543
5544 /* Queue belongs to VF, find the VF and issue VF reset */
5545 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5546 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5547 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5548 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5549 vf_id -= hw->func_caps.vf_base_id;
5550 vf = &pf->vf[vf_id];
5551 i40e_vc_notify_vf_reset(vf);
5552 /* Allow VF to process pending reset notification */
5553 msleep(20);
5554 i40e_reset_vf(vf, false);
5555 }
5556}
5557
5558/**
5559 * i40e_service_event_complete - Finish up the service event
5560 * @pf: board private structure
5561 **/
5562static void i40e_service_event_complete(struct i40e_pf *pf)
5563{
5564 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5565
5566 /* flush memory to make sure state is correct before next watchog */
4e857c58 5567 smp_mb__before_atomic();
41c445ff
JB		 5568 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5569}
5570
55a5e60b 5571/**
12957388
ASJ		 5572 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5573 * @pf: board private structure
5574 **/
04294e38 5575u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5576{
04294e38 5577 u32 val, fcnt_prog;
12957388
ASJ		 5578
5579 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5580 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5581 return fcnt_prog;
5582}
5583
5584/**
04294e38 5585 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5586 * @pf: board private structure
5587 **/
04294e38 5588u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5589{
04294e38
ASJ		 5590 u32 val, fcnt_prog;
5591
55a5e60b
ASJ		 5592 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5593 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5594 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5595 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5596 return fcnt_prog;
5597}
1e1be8f6 5598
04294e38
ASJ		 5599/**
5600 * i40e_get_global_fd_count - Get total FD filters programmed on device
5601 * @pf: board private structure
5602 **/
5603u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5604{
5605 u32 val, fcnt_prog;
5606
5607 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5608 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5609 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5610 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5611 return fcnt_prog;
5612}
5613
55a5e60b
ASJ		 5614/**
5615 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5616 * @pf: board private structure
5617 **/
5618void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5619{
3487b6c3 5620 struct i40e_fdir_filter *filter;
55a5e60b 5621 u32 fcnt_prog, fcnt_avail;
3487b6c3 5622 struct hlist_node *node;
55a5e60b 5623
1e1be8f6
ASJ		 5624 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5625 return;
5626
55a5e60b
ASJ		 5627 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5628 * to re-enable
5629 */
04294e38 5630 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5631 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5632 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5633 (pf->fd_add_err == 0) ||
5634 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5635 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5636 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5637 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5638 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5639 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5640 }
5641 }
5642 /* Wait for some more space to be available to turn on ATR */
5643 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5644 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5645 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5646 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5647 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5648 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5649 }
5650 }
3487b6c3
CW		 5651
5652 /* if hw had a problem adding a filter, delete it */
5653 if (pf->fd_inv > 0) {
5654 hlist_for_each_entry_safe(filter, node,
5655 &pf->fdir_filter_list, fdir_node) {
5656 if (filter->fd_id == pf->fd_inv) {
5657 hlist_del(&filter->fdir_node);
5658 kfree(filter);
5659 pf->fdir_pf_active_filters--;
5660 }
5661 }
5662 }
55a5e60b
ASJ		 5663}
5664
1e1be8f6 5665#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5666#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5667/**
5668 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5669 * @pf: board private structure
5670 **/
5671static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5672{
04294e38 5673 unsigned long min_flush_time;
1e1be8f6 5674 int flush_wait_retry = 50;
04294e38
ASJ		 5675 bool disable_atr = false;
5676 int fd_room;
1e1be8f6
ASJ		 5677 int reg;
5678
1790ed0c
AA		 5679 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5680 return;
5681
1e1be8f6
ASJ		 5682 if (time_after(jiffies, pf->fd_flush_timestamp +
5683 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5684 /* If the flush is happening too quick and we have mostly
5685 * SB rules we should not re-enable ATR for some time.
5686 */
5687 min_flush_time = pf->fd_flush_timestamp
5688 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5689 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5690
5691 if (!(time_after(jiffies, min_flush_time)) &&
5692 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
2e4875e3
ASJ		 5693 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5694 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
04294e38
ASJ		 5695 disable_atr = true;
5696 }
5697
1e1be8f6 5698 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5699 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5700 /* flush all filters */
5701 wr32(&pf->hw, I40E_PFQF_CTL_1,
5702 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5703 i40e_flush(&pf->hw);
60793f4a 5704 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5705 pf->fd_add_err = 0;
5706 do {
5707 /* Check FD flush status every 5-6msec */
5708 usleep_range(5000, 6000);
5709 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5710 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5711 break;
5712 } while (flush_wait_retry--);
5713 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5714 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5715 } else {
5716 /* replay sideband filters */
5717 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5718 if (!disable_atr)
5719 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6 5720 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
2e4875e3
ASJ		 5721 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5722 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5723 }
5724 }
5725}
5726
5727/**
5728 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5729 * @pf: board private structure
5730 **/
04294e38 5731u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5732{
5733 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5734}
5735
5736/* We can see up to 256 filter programming desc in transit if the filters are
5737 * being applied really fast; before we see the first
5738 * filter miss error on Rx queue 0. Accumulating enough error messages before
5739 * reacting will make sure we don't cause flush too often.
5740 */
5741#define I40E_MAX_FD_PROGRAM_ERROR 256
5742
41c445ff
JB		 5743/**
5744 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5745 * @pf: board private structure
5746 **/
5747static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5748{
41c445ff 5749
41c445ff
JB		 5750 /* if interface is down do nothing */
5751 if (test_bit(__I40E_DOWN, &pf->state))
5752 return;
1e1be8f6 5753
1790ed0c
AA		 5754 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5755 return;
5756
04294e38 5757 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5758 i40e_fdir_flush_and_replay(pf);
5759
55a5e60b
ASJ		 5760 i40e_fdir_check_and_reenable(pf);
5761
41c445ff
JB		 5762}
5763
5764/**
5765 * i40e_vsi_link_event - notify VSI of a link event
5766 * @vsi: vsi to be notified
5767 * @link_up: link up or down
5768 **/
5769static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5770{
32b5b811 5771 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5772 return;
5773
5774 switch (vsi->type) {
5775 case I40E_VSI_MAIN:
38e00438
VD		 5776#ifdef I40E_FCOE
5777 case I40E_VSI_FCOE:
5778#endif
41c445ff
JB		 5779 if (!vsi->netdev || !vsi->netdev_registered)
5780 break;
5781
5782 if (link_up) {
5783 netif_carrier_on(vsi->netdev);
5784 netif_tx_wake_all_queues(vsi->netdev);
5785 } else {
5786 netif_carrier_off(vsi->netdev);
5787 netif_tx_stop_all_queues(vsi->netdev);
5788 }
5789 break;
5790
5791 case I40E_VSI_SRIOV:
41c445ff
JB		 5792 case I40E_VSI_VMDQ2:
5793 case I40E_VSI_CTRL:
5794 case I40E_VSI_MIRROR:
5795 default:
5796 /* there is no notification for other VSIs */
5797 break;
5798 }
5799}
5800
5801/**
5802 * i40e_veb_link_event - notify elements on the veb of a link event
5803 * @veb: veb to be notified
5804 * @link_up: link up or down
5805 **/
5806static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5807{
5808 struct i40e_pf *pf;
5809 int i;
5810
5811 if (!veb || !veb->pf)
5812 return;
5813 pf = veb->pf;
5814
5815 /* depth first... */
5816 for (i = 0; i < I40E_MAX_VEB; i++)
5817 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5818 i40e_veb_link_event(pf->veb[i], link_up);
5819
5820 /* ... now the local VSIs */
505682cd 5821 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5822 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5823 i40e_vsi_link_event(pf->vsi[i], link_up);
5824}
5825
5826/**
5827 * i40e_link_event - Update netif_carrier status
5828 * @pf: board private structure
5829 **/
5830static void i40e_link_event(struct i40e_pf *pf)
5831{
320684cd 5832 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5833 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 5834 i40e_status status;
5835 bool new_link, old_link;
41c445ff 5836
1e701e09
JB		 5837 /* set this to force the get_link_status call to refresh state */
5838 pf->hw.phy.get_link_info = true;
5839
41c445ff 5840 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 5841
5842 status = i40e_get_link_status(&pf->hw, &new_link);
5843 if (status) {
5844 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
5845 status);
5846 return;
5847 }
5848
fef59ddf
CS		 5849 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5850 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5851
1e701e09 5852 if (new_link == old_link &&
fef59ddf 5853 new_link_speed == old_link_speed &&
320684cd
MW		 5854 (test_bit(__I40E_DOWN, &vsi->state) ||
5855 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5856 return;
320684cd
MW		 5857
5858 if (!test_bit(__I40E_DOWN, &vsi->state))
5859 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5860
5861 /* Notify the base of the switch tree connected to
5862 * the link. Floating VEBs are not notified.
5863 */
5864 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5865 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5866 else
320684cd 5867 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5868
5869 if (pf->vf)
5870 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5871
5872 if (pf->flags & I40E_FLAG_PTP)
5873 i40e_ptp_set_increment(pf);
41c445ff
JB		 5874}
5875
41c445ff 5876/**
21536717 5877 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5878 * @pf: board private structure
5879 **/
5880static void i40e_watchdog_subtask(struct i40e_pf *pf)
5881{
5882 int i;
5883
5884 /* if interface is down do nothing */
5885 if (test_bit(__I40E_DOWN, &pf->state) ||
5886 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5887 return;
5888
21536717
SN		 5889 /* make sure we don't do these things too often */
5890 if (time_before(jiffies, (pf->service_timer_previous +
5891 pf->service_timer_period)))
5892 return;
5893 pf->service_timer_previous = jiffies;
5894
9ac77266
SN		 5895 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
5896 i40e_link_event(pf);
21536717 5897
41c445ff
JB		 5898 /* Update the stats for active netdevs so the network stack
5899 * can look at updated numbers whenever it cares to
5900 */
505682cd 5901 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5902 if (pf->vsi[i] && pf->vsi[i]->netdev)
5903 i40e_update_stats(pf->vsi[i]);
5904
d1a8d275
ASJ		 5905 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
5906 /* Update the stats for the active switching components */
5907 for (i = 0; i < I40E_MAX_VEB; i++)
5908 if (pf->veb[i])
5909 i40e_update_veb_stats(pf->veb[i]);
5910 }
beb0dff1
JK		 5911
5912 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5913}
5914
5915/**
5916 * i40e_reset_subtask - Set up for resetting the device and driver
5917 * @pf: board private structure
5918 **/
5919static void i40e_reset_subtask(struct i40e_pf *pf)
5920{
5921 u32 reset_flags = 0;
5922
23326186 5923 rtnl_lock();
41c445ff 5924 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5925 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5926 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5927 }
5928 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5929 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5930 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5931 }
5932 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5933 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5934 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5935 }
5936 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5937 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5938 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5939 }
b5d06f05 5940 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5941 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5942 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5943 }
41c445ff
JB		 5944
5945 /* If there's a recovery already waiting, it takes
5946 * precedence before starting a new reset sequence.
5947 */
5948 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5949 i40e_handle_reset_warning(pf);
23326186 5950 goto unlock;
41c445ff
JB		 5951 }
5952
5953 /* If we're already down or resetting, just bail */
5954 if (reset_flags &&
5955 !test_bit(__I40E_DOWN, &pf->state) &&
5956 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5957 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5958
5959unlock:
5960 rtnl_unlock();
41c445ff
JB		 5961}
5962
5963/**
5964 * i40e_handle_link_event - Handle link event
5965 * @pf: board private structure
5966 * @e: event info posted on ARQ
5967 **/
5968static void i40e_handle_link_event(struct i40e_pf *pf,
5969 struct i40e_arq_event_info *e)
5970{
5971 struct i40e_hw *hw = &pf->hw;
5972 struct i40e_aqc_get_link_status *status =
5973 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5974
5975 /* save off old link status information */
1a2f6248 5976 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5977
1e701e09
JB		 5978 /* Do a new status request to re-enable LSE reporting
5979 * and load new status information into the hw struct
5980 * This completely ignores any state information
5981 * in the ARQ event info, instead choosing to always
5982 * issue the AQ update link status command.
5983 */
5984 i40e_link_event(pf);
5985
7b592f61
CW		 5986 /* check for unqualified module, if link is down */
5987 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5988 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5989 (!(status->link_info & I40E_AQ_LINK_UP)))
5990 dev_err(&pf->pdev->dev,
5991 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5992}
5993
5994/**
5995 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5996 * @pf: board private structure
5997 **/
5998static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5999{
6000 struct i40e_arq_event_info event;
6001 struct i40e_hw *hw = &pf->hw;
6002 u16 pending, i = 0;
6003 i40e_status ret;
6004 u16 opcode;
86df242b 6005 u32 oldval;
41c445ff
JB		 6006 u32 val;
6007
a316f651
ASJ		 6008 /* Do not run clean AQ when PF reset fails */
6009 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6010 return;
6011
86df242b
SN		 6012 /* check for error indications */
6013 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6014 oldval = val;
6015 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6016 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6017 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6018 }
6019 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6020 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6021 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6022 }
6023 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6024 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6025 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6026 }
6027 if (oldval != val)
6028 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6029
6030 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6031 oldval = val;
6032 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6033 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6034 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6035 }
6036 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6037 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6038 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6039 }
6040 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6041 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6042 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6043 }
6044 if (oldval != val)
6045 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6046
1001dc37
MW		 6047 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6048 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6049 if (!event.msg_buf)
6050 return;
6051
6052 do {
6053 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6054 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6055 break;
56497978 6056 else if (ret) {
41c445ff
JB		 6057 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6058 break;
6059 }
6060
6061 opcode = le16_to_cpu(event.desc.opcode);
6062 switch (opcode) {
6063
6064 case i40e_aqc_opc_get_link_status:
6065 i40e_handle_link_event(pf, &event);
6066 break;
6067 case i40e_aqc_opc_send_msg_to_pf:
6068 ret = i40e_vc_process_vf_msg(pf,
6069 le16_to_cpu(event.desc.retval),
6070 le32_to_cpu(event.desc.cookie_high),
6071 le32_to_cpu(event.desc.cookie_low),
6072 event.msg_buf,
1001dc37 6073 event.msg_len);
41c445ff
JB		 6074 break;
6075 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6076 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6077#ifdef CONFIG_I40E_DCB
6078 rtnl_lock();
6079 ret = i40e_handle_lldp_event(pf, &event);
6080 rtnl_unlock();
6081#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6082 break;
6083 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6084 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6085 i40e_handle_lan_overflow_event(pf, &event);
6086 break;
0467bc91
SN		 6087 case i40e_aqc_opc_send_msg_to_peer:
6088 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6089 break;
91a0f930
SN		 6090 case i40e_aqc_opc_nvm_erase:
6091 case i40e_aqc_opc_nvm_update:
6092 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6093 break;
41c445ff
JB		 6094 default:
6095 dev_info(&pf->pdev->dev,
0467bc91
SN		 6096 "ARQ Error: Unknown event 0x%04x received\n",
6097 opcode);
41c445ff
JB		 6098 break;
6099 }
6100 } while (pending && (i++ < pf->adminq_work_limit));
6101
6102 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6103 /* re-enable Admin queue interrupt cause */
6104 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6105 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6106 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6107 i40e_flush(hw);
6108
6109 kfree(event.msg_buf);
6110}
6111
4eb3f768
SN		 6112/**
6113 * i40e_verify_eeprom - make sure eeprom is good to use
6114 * @pf: board private structure
6115 **/
6116static void i40e_verify_eeprom(struct i40e_pf *pf)
6117{
6118 int err;
6119
6120 err = i40e_diag_eeprom_test(&pf->hw);
6121 if (err) {
6122 /* retry in case of garbage read */
6123 err = i40e_diag_eeprom_test(&pf->hw);
6124 if (err) {
6125 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6126 err);
6127 set_bit(__I40E_BAD_EEPROM, &pf->state);
6128 }
6129 }
6130
6131 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6132 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6133 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6134 }
6135}
6136
386a0afa
AA		 6137/**
6138 * i40e_enable_pf_switch_lb
b40c82e6 6139 * @pf: pointer to the PF structure
386a0afa
AA		 6140 *
6141 * enable switch loop back or die - no point in a return value
6142 **/
6143static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6144{
6145 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6146 struct i40e_vsi_context ctxt;
f1c7e72e 6147 int ret;
386a0afa
AA		 6148
6149 ctxt.seid = pf->main_vsi_seid;
6150 ctxt.pf_num = pf->hw.pf_id;
6151 ctxt.vf_num = 0;
f1c7e72e
SN		 6152 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6153 if (ret) {
386a0afa 6154 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6155 "couldn't get PF vsi config, err %s aq_err %s\n",
6156 i40e_stat_str(&pf->hw, ret),
6157 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6158 return;
6159 }
6160 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6161 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6162 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6163
f1c7e72e
SN		 6164 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6165 if (ret) {
386a0afa 6166 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6167 "update vsi switch failed, err %s aq_err %s\n",
6168 i40e_stat_str(&pf->hw, ret),
6169 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6170 }
6171}
6172
6173/**
6174 * i40e_disable_pf_switch_lb
b40c82e6 6175 * @pf: pointer to the PF structure
386a0afa
AA		 6176 *
6177 * disable switch loop back or die - no point in a return value
6178 **/
6179static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6180{
6181 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6182 struct i40e_vsi_context ctxt;
f1c7e72e 6183 int ret;
386a0afa
AA		 6184
6185 ctxt.seid = pf->main_vsi_seid;
6186 ctxt.pf_num = pf->hw.pf_id;
6187 ctxt.vf_num = 0;
f1c7e72e
SN		 6188 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6189 if (ret) {
386a0afa 6190 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6191 "couldn't get PF vsi config, err %s aq_err %s\n",
6192 i40e_stat_str(&pf->hw, ret),
6193 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6194 return;
6195 }
6196 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6197 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6198 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6199
f1c7e72e
SN		 6200 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6201 if (ret) {
386a0afa 6202 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6203 "update vsi switch failed, err %s aq_err %s\n",
6204 i40e_stat_str(&pf->hw, ret),
6205 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6206 }
6207}
6208
51616018
NP		 6209/**
6210 * i40e_config_bridge_mode - Configure the HW bridge mode
6211 * @veb: pointer to the bridge instance
6212 *
6213 * Configure the loop back mode for the LAN VSI that is downlink to the
6214 * specified HW bridge instance. It is expected this function is called
6215 * when a new HW bridge is instantiated.
6216 **/
6217static void i40e_config_bridge_mode(struct i40e_veb *veb)
6218{
6219 struct i40e_pf *pf = veb->pf;
6220
6221 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6222 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6223 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6224 i40e_disable_pf_switch_lb(pf);
6225 else
6226 i40e_enable_pf_switch_lb(pf);
6227}
6228
41c445ff
JB		 6229/**
6230 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6231 * @veb: pointer to the VEB instance
6232 *
6233 * This is a recursive function that first builds the attached VSIs then
6234 * recurses in to build the next layer of VEB. We track the connections
6235 * through our own index numbers because the seid's from the HW could
6236 * change across the reset.
6237 **/
6238static int i40e_reconstitute_veb(struct i40e_veb *veb)
6239{
6240 struct i40e_vsi *ctl_vsi = NULL;
6241 struct i40e_pf *pf = veb->pf;
6242 int v, veb_idx;
6243 int ret;
6244
6245 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6246 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6247 if (pf->vsi[v] &&
6248 pf->vsi[v]->veb_idx == veb->idx &&
6249 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6250 ctl_vsi = pf->vsi[v];
6251 break;
6252 }
6253 }
6254 if (!ctl_vsi) {
6255 dev_info(&pf->pdev->dev,
6256 "missing owner VSI for veb_idx %d\n", veb->idx);
6257 ret = -ENOENT;
6258 goto end_reconstitute;
6259 }
6260 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6261 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6262 ret = i40e_add_vsi(ctl_vsi);
6263 if (ret) {
6264 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6265 "rebuild of veb_idx %d owner VSI failed: %d\n",
6266 veb->idx, ret);
41c445ff
JB		 6267 goto end_reconstitute;
6268 }
6269 i40e_vsi_reset_stats(ctl_vsi);
6270
6271 /* create the VEB in the switch and move the VSI onto the VEB */
6272 ret = i40e_add_veb(veb, ctl_vsi);
6273 if (ret)
6274 goto end_reconstitute;
6275
fc60861e
ASJ		 6276 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6277 veb->bridge_mode = BRIDGE_MODE_VEB;
6278 else
6279 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6280 i40e_config_bridge_mode(veb);
b64ba084 6281
41c445ff 6282 /* create the remaining VSIs attached to this VEB */
505682cd 6283 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6284 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6285 continue;
6286
6287 if (pf->vsi[v]->veb_idx == veb->idx) {
6288 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6289
41c445ff
JB		 6290 vsi->uplink_seid = veb->seid;
6291 ret = i40e_add_vsi(vsi);
6292 if (ret) {
6293 dev_info(&pf->pdev->dev,
6294 "rebuild of vsi_idx %d failed: %d\n",
6295 v, ret);
6296 goto end_reconstitute;
6297 }
6298 i40e_vsi_reset_stats(vsi);
6299 }
6300 }
6301
6302 /* create any VEBs attached to this VEB - RECURSION */
6303 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6304 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6305 pf->veb[veb_idx]->uplink_seid = veb->seid;
6306 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6307 if (ret)
6308 break;
6309 }
6310 }
6311
6312end_reconstitute:
6313 return ret;
6314}
6315
6316/**
6317 * i40e_get_capabilities - get info about the HW
6318 * @pf: the PF struct
6319 **/
6320static int i40e_get_capabilities(struct i40e_pf *pf)
6321{
6322 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6323 u16 data_size;
6324 int buf_len;
6325 int err;
6326
6327 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6328 do {
6329 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6330 if (!cap_buf)
6331 return -ENOMEM;
6332
6333 /* this loads the data into the hw struct for us */
6334 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6335 &data_size,
6336 i40e_aqc_opc_list_func_capabilities,
6337 NULL);
6338 /* data loaded, buffer no longer needed */
6339 kfree(cap_buf);
6340
6341 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6342 /* retry with a larger buffer */
6343 buf_len = data_size;
6344 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6345 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6346 "capability discovery failed, err %s aq_err %s\n",
6347 i40e_stat_str(&pf->hw, err),
6348 i40e_aq_str(&pf->hw,
6349 pf->hw.aq.asq_last_status));
41c445ff
JB		 6350 return -ENODEV;
6351 }
6352 } while (err);
6353
ac71b7ba
ASJ		 6354 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6355 (pf->hw.aq.fw_maj_ver < 2)) {
6356 pf->hw.func_caps.num_msix_vectors++;
6357 pf->hw.func_caps.num_msix_vectors_vf++;
6358 }
6359
41c445ff
JB		 6360 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6361 dev_info(&pf->pdev->dev,
6362 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6363 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6364 pf->hw.func_caps.num_msix_vectors,
6365 pf->hw.func_caps.num_msix_vectors_vf,
6366 pf->hw.func_caps.fd_filters_guaranteed,
6367 pf->hw.func_caps.fd_filters_best_effort,
6368 pf->hw.func_caps.num_tx_qp,
6369 pf->hw.func_caps.num_vsis);
6370
7134f9ce
JB		 6371#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6372 + pf->hw.func_caps.num_vfs)
6373 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6374 dev_info(&pf->pdev->dev,
6375 "got num_vsis %d, setting num_vsis to %d\n",
6376 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6377 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6378 }
6379
41c445ff
JB		 6380 return 0;
6381}
6382
cbf61325
ASJ		 6383static int i40e_vsi_clear(struct i40e_vsi *vsi);
6384
41c445ff 6385/**
cbf61325 6386 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6387 * @pf: board private structure
6388 **/
cbf61325 6389static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6390{
6391 struct i40e_vsi *vsi;
8a9eb7d3 6392 int i;
41c445ff 6393
407e063c
JB		 6394 /* quick workaround for an NVM issue that leaves a critical register
6395 * uninitialized
6396 */
6397 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6398 static const u32 hkey[] = {
6399 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6400 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6401 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6402 0x95b3a76d};
6403
6404 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6405 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6406 }
6407
cbf61325 6408 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6409 return;
6410
cbf61325 6411 /* find existing VSI and see if it needs configuring */
41c445ff 6412 vsi = NULL;
505682cd 6413 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6414 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6415 vsi = pf->vsi[i];
cbf61325
ASJ		 6416 break;
6417 }
6418 }
6419
6420 /* create a new VSI if none exists */
41c445ff 6421 if (!vsi) {
cbf61325
ASJ		 6422 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6423 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6424 if (!vsi) {
6425 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6426 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6427 return;
41c445ff 6428 }
cbf61325 6429 }
41c445ff 6430
8a9eb7d3 6431 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6432}
6433
6434/**
6435 * i40e_fdir_teardown - release the Flow Director resources
6436 * @pf: board private structure
6437 **/
6438static void i40e_fdir_teardown(struct i40e_pf *pf)
6439{
6440 int i;
6441
17a73f6b 6442 i40e_fdir_filter_exit(pf);
505682cd 6443 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6444 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6445 i40e_vsi_release(pf->vsi[i]);
6446 break;
6447 }
6448 }
6449}
6450
6451/**
f650a38b 6452 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6453 * @pf: board private structure
6454 *
b40c82e6 6455 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6456 **/
23cfbe07 6457static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6458{
41c445ff 6459 struct i40e_hw *hw = &pf->hw;
60442dea 6460 i40e_status ret = 0;
41c445ff
JB		 6461 u32 v;
6462
6463 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6464 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6465 return;
41c445ff 6466
69bfb110 6467 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6468
41c445ff
JB		 6469 /* quiesce the VSIs and their queues that are not already DOWN */
6470 i40e_pf_quiesce_all_vsi(pf);
6471
505682cd 6472 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6473 if (pf->vsi[v])
6474 pf->vsi[v]->seid = 0;
6475 }
6476
6477 i40e_shutdown_adminq(&pf->hw);
6478
f650a38b 6479 /* call shutdown HMC */
60442dea
SN		 6480 if (hw->hmc.hmc_obj) {
6481 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6482 if (ret)
60442dea
SN		 6483 dev_warn(&pf->pdev->dev,
6484 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6485 }
f650a38b
ASJ		 6486}
6487
44033fac
JB		 6488/**
6489 * i40e_send_version - update firmware with driver version
6490 * @pf: PF struct
6491 */
6492static void i40e_send_version(struct i40e_pf *pf)
6493{
6494 struct i40e_driver_version dv;
6495
6496 dv.major_version = DRV_VERSION_MAJOR;
6497 dv.minor_version = DRV_VERSION_MINOR;
6498 dv.build_version = DRV_VERSION_BUILD;
6499 dv.subbuild_version = 0;
35a7d804 6500 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6501 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6502}
6503
f650a38b 6504/**
4dda12e6 6505 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6506 * @pf: board private structure
bc7d338f 6507 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6508 **/
bc7d338f 6509static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6510{
f650a38b 6511 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6512 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6513 i40e_status ret;
6514 u32 v;
6515
41c445ff
JB		 6516 /* Now we wait for GRST to settle out.
6517 * We don't have to delete the VEBs or VSIs from the hw switch
6518 * because the reset will make them disappear.
6519 */
6520 ret = i40e_pf_reset(hw);
b5565400 6521 if (ret) {
41c445ff 6522 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6523 set_bit(__I40E_RESET_FAILED, &pf->state);
6524 goto clear_recovery;
b5565400 6525 }
41c445ff
JB		 6526 pf->pfr_count++;
6527
6528 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6529 goto clear_recovery;
69bfb110 6530 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6531
6532 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6533 ret = i40e_init_adminq(&pf->hw);
6534 if (ret) {
f1c7e72e
SN		 6535 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6536 i40e_stat_str(&pf->hw, ret),
6537 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6538 goto clear_recovery;
41c445ff
JB		 6539 }
6540
4eb3f768 6541 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6542 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6543 i40e_verify_eeprom(pf);
4eb3f768 6544
e78ac4bf 6545 i40e_clear_pxe_mode(hw);
41c445ff 6546 ret = i40e_get_capabilities(pf);
f1c7e72e 6547 if (ret)
41c445ff 6548 goto end_core_reset;
41c445ff 6549
41c445ff
JB		 6550 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6551 hw->func_caps.num_rx_qp,
6552 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6553 if (ret) {
6554 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6555 goto end_core_reset;
6556 }
6557 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6558 if (ret) {
6559 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6560 goto end_core_reset;
6561 }
6562
4e3b35b0
NP		 6563#ifdef CONFIG_I40E_DCB
6564 ret = i40e_init_pf_dcb(pf);
6565 if (ret) {
aebfc816
SN		 6566 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6567 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6568 /* Continue without DCB enabled */
4e3b35b0
NP		 6569 }
6570#endif /* CONFIG_I40E_DCB */
38e00438 6571#ifdef I40E_FCOE
21364bcf 6572 i40e_init_pf_fcoe(pf);
4e3b35b0 6573
38e00438 6574#endif
41c445ff 6575 /* do basic switch setup */
bc7d338f 6576 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6577 if (ret)
6578 goto end_core_reset;
6579
7e2453fe
JB		 6580 /* driver is only interested in link up/down and module qualification
6581 * reports from firmware
6582 */
6583 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6584 I40E_AQ_EVENT_LINK_UPDOWN |
6585 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6586 if (ret)
f1c7e72e
SN		 6587 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6588 i40e_stat_str(&pf->hw, ret),
6589 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6590
cafa2ee6
ASJ		 6591 /* make sure our flow control settings are restored */
6592 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6593 if (ret)
f1c7e72e
SN		 6594 dev_info(&pf->pdev->dev, "set fc fail, err %s aq_err %s\n",
6595 i40e_stat_str(&pf->hw, ret),
6596 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6597
41c445ff
JB		 6598 /* Rebuild the VSIs and VEBs that existed before reset.
6599 * They are still in our local switch element arrays, so only
6600 * need to rebuild the switch model in the HW.
6601 *
6602 * If there were VEBs but the reconstitution failed, we'll try
6603 * try to recover minimal use by getting the basic PF VSI working.
6604 */
6605 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6606 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6607 /* find the one VEB connected to the MAC, and find orphans */
6608 for (v = 0; v < I40E_MAX_VEB; v++) {
6609 if (!pf->veb[v])
6610 continue;
6611
6612 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6613 pf->veb[v]->uplink_seid == 0) {
6614 ret = i40e_reconstitute_veb(pf->veb[v]);
6615
6616 if (!ret)
6617 continue;
6618
6619 /* If Main VEB failed, we're in deep doodoo,
6620 * so give up rebuilding the switch and set up
6621 * for minimal rebuild of PF VSI.
6622 * If orphan failed, we'll report the error
6623 * but try to keep going.
6624 */
6625 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6626 dev_info(&pf->pdev->dev,
6627 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6628 ret);
6629 pf->vsi[pf->lan_vsi]->uplink_seid
6630 = pf->mac_seid;
6631 break;
6632 } else if (pf->veb[v]->uplink_seid == 0) {
6633 dev_info(&pf->pdev->dev,
6634 "rebuild of orphan VEB failed: %d\n",
6635 ret);
6636 }
6637 }
6638 }
6639 }
6640
6641 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6642 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6643 /* no VEB, so rebuild only the Main VSI */
6644 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6645 if (ret) {
6646 dev_info(&pf->pdev->dev,
6647 "rebuild of Main VSI failed: %d\n", ret);
6648 goto end_core_reset;
6649 }
6650 }
6651
025b4a54
ASJ		 6652 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6653 (pf->hw.aq.fw_maj_ver < 4)) {
6654 msleep(75);
6655 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6656 if (ret)
f1c7e72e
SN		 6657 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6658 i40e_stat_str(&pf->hw, ret),
6659 i40e_aq_str(&pf->hw,
6660 pf->hw.aq.asq_last_status));
cafa2ee6 6661 }
41c445ff
JB		 6662 /* reinit the misc interrupt */
6663 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6664 ret = i40e_setup_misc_vector(pf);
6665
6666 /* restart the VSIs that were rebuilt and running before the reset */
6667 i40e_pf_unquiesce_all_vsi(pf);
6668
69f64b2b
MW		 6669 if (pf->num_alloc_vfs) {
6670 for (v = 0; v < pf->num_alloc_vfs; v++)
6671 i40e_reset_vf(&pf->vf[v], true);
6672 }
6673
41c445ff 6674 /* tell the firmware that we're starting */
44033fac 6675 i40e_send_version(pf);
41c445ff
JB		 6676
6677end_core_reset:
a316f651
ASJ		 6678 clear_bit(__I40E_RESET_FAILED, &pf->state);
6679clear_recovery:
41c445ff
JB		 6680 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6681}
6682
f650a38b 6683/**
b40c82e6 6684 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6685 * @pf: board private structure
6686 *
6687 * Close up the VFs and other things in prep for a Core Reset,
6688 * then get ready to rebuild the world.
6689 **/
6690static void i40e_handle_reset_warning(struct i40e_pf *pf)
6691{
23cfbe07
SN		 6692 i40e_prep_for_reset(pf);
6693 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6694}
6695
41c445ff
JB		 6696/**
6697 * i40e_handle_mdd_event
b40c82e6 6698 * @pf: pointer to the PF structure
41c445ff
JB		 6699 *
6700 * Called from the MDD irq handler to identify possibly malicious vfs
6701 **/
6702static void i40e_handle_mdd_event(struct i40e_pf *pf)
6703{
6704 struct i40e_hw *hw = &pf->hw;
6705 bool mdd_detected = false;
df430b12 6706 bool pf_mdd_detected = false;
41c445ff
JB		 6707 struct i40e_vf *vf;
6708 u32 reg;
6709 int i;
6710
6711 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6712 return;
6713
6714 /* find what triggered the MDD event */
6715 reg = rd32(hw, I40E_GL_MDET_TX);
6716 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6717 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6718 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6719 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6720 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6721 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6722 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6723 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6724 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6725 pf->hw.func_caps.base_queue;
faf32978 6726 if (netif_msg_tx_err(pf))
b40c82e6 6727 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6728 event, queue, pf_num, vf_num);
41c445ff
JB		 6729 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6730 mdd_detected = true;
6731 }
6732 reg = rd32(hw, I40E_GL_MDET_RX);
6733 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6734 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6735 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6736 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6737 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6738 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6739 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6740 pf->hw.func_caps.base_queue;
faf32978
JB		 6741 if (netif_msg_rx_err(pf))
6742 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6743 event, queue, func);
41c445ff
JB		 6744 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6745 mdd_detected = true;
6746 }
6747
df430b12
NP		 6748 if (mdd_detected) {
6749 reg = rd32(hw, I40E_PF_MDET_TX);
6750 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6751 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6752 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6753 pf_mdd_detected = true;
6754 }
6755 reg = rd32(hw, I40E_PF_MDET_RX);
6756 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6757 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6758 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6759 pf_mdd_detected = true;
6760 }
6761 /* Queue belongs to the PF, initiate a reset */
6762 if (pf_mdd_detected) {
6763 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6764 i40e_service_event_schedule(pf);
6765 }
6766 }
6767
41c445ff
JB		 6768 /* see if one of the VFs needs its hand slapped */
6769 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6770 vf = &(pf->vf[i]);
6771 reg = rd32(hw, I40E_VP_MDET_TX(i));
6772 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6773 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6774 vf->num_mdd_events++;
faf32978
JB		 6775 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6776 i);
41c445ff
JB		 6777 }
6778
6779 reg = rd32(hw, I40E_VP_MDET_RX(i));
6780 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6781 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6782 vf->num_mdd_events++;
faf32978
JB		 6783 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6784 i);
41c445ff
JB		 6785 }
6786
6787 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6788 dev_info(&pf->pdev->dev,
6789 "Too many MDD events on VF %d, disabled\n", i);
6790 dev_info(&pf->pdev->dev,
6791 "Use PF Control I/F to re-enable the VF\n");
6792 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6793 }
6794 }
6795
6796 /* re-enable mdd interrupt cause */
6797 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6798 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6799 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6800 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6801 i40e_flush(hw);
6802}
6803
a1c9a9d9
JK		 6804#ifdef CONFIG_I40E_VXLAN
6805/**
6806 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6807 * @pf: board private structure
6808 **/
6809static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6810{
a1c9a9d9
JK		 6811 struct i40e_hw *hw = &pf->hw;
6812 i40e_status ret;
a1c9a9d9
JK		 6813 __be16 port;
6814 int i;
6815
6816 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6817 return;
6818
6819 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6820
6821 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6822 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6823 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6824 port = pf->vxlan_ports[i];
c22c06c8
SN		 6825 if (port)
6826 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6827 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6828 NULL, NULL);
6829 else
6830 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6831
6832 if (ret) {
c22c06c8 6833 dev_info(&pf->pdev->dev,
f1c7e72e 6834 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6835 port ? "add" : "delete",
f1c7e72e
SN		 6836 ntohs(port), i,
6837 i40e_stat_str(&pf->hw, ret),
6838 i40e_aq_str(&pf->hw,
6839 pf->hw.aq.asq_last_status));
a1c9a9d9 6840 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6841 }
6842 }
6843 }
6844}
6845
6846#endif
41c445ff
JB		 6847/**
6848 * i40e_service_task - Run the driver's async subtasks
6849 * @work: pointer to work_struct containing our data
6850 **/
6851static void i40e_service_task(struct work_struct *work)
6852{
6853 struct i40e_pf *pf = container_of(work,
6854 struct i40e_pf,
6855 service_task);
6856 unsigned long start_time = jiffies;
6857
e57a2fea
SN		 6858 /* don't bother with service tasks if a reset is in progress */
6859 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6860 i40e_service_event_complete(pf);
6861 return;
6862 }
6863
b03a8c1f 6864 i40e_detect_recover_hung(pf);
41c445ff
JB		 6865 i40e_reset_subtask(pf);
6866 i40e_handle_mdd_event(pf);
6867 i40e_vc_process_vflr_event(pf);
6868 i40e_watchdog_subtask(pf);
6869 i40e_fdir_reinit_subtask(pf);
41c445ff 6870 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6871#ifdef CONFIG_I40E_VXLAN
6872 i40e_sync_vxlan_filters_subtask(pf);
6873#endif
41c445ff
JB		 6874 i40e_clean_adminq_subtask(pf);
6875
6876 i40e_service_event_complete(pf);
6877
6878 /* If the tasks have taken longer than one timer cycle or there
6879 * is more work to be done, reschedule the service task now
6880 * rather than wait for the timer to tick again.
6881 */
6882 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6883 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6884 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6885 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6886 i40e_service_event_schedule(pf);
6887}
6888
6889/**
6890 * i40e_service_timer - timer callback
6891 * @data: pointer to PF struct
6892 **/
6893static void i40e_service_timer(unsigned long data)
6894{
6895 struct i40e_pf *pf = (struct i40e_pf *)data;
6896
6897 mod_timer(&pf->service_timer,
6898 round_jiffies(jiffies + pf->service_timer_period));
6899 i40e_service_event_schedule(pf);
6900}
6901
6902/**
6903 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6904 * @vsi: the VSI being configured
6905 **/
6906static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6907{
6908 struct i40e_pf *pf = vsi->back;
6909
6910 switch (vsi->type) {
6911 case I40E_VSI_MAIN:
6912 vsi->alloc_queue_pairs = pf->num_lan_qps;
6913 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6914 I40E_REQ_DESCRIPTOR_MULTIPLE);
6915 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6916 vsi->num_q_vectors = pf->num_lan_msix;
6917 else
6918 vsi->num_q_vectors = 1;
6919
6920 break;
6921
6922 case I40E_VSI_FDIR:
6923 vsi->alloc_queue_pairs = 1;
6924 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6925 I40E_REQ_DESCRIPTOR_MULTIPLE);
6926 vsi->num_q_vectors = 1;
6927 break;
6928
6929 case I40E_VSI_VMDQ2:
6930 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6931 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6932 I40E_REQ_DESCRIPTOR_MULTIPLE);
6933 vsi->num_q_vectors = pf->num_vmdq_msix;
6934 break;
6935
6936 case I40E_VSI_SRIOV:
6937 vsi->alloc_queue_pairs = pf->num_vf_qps;
6938 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6939 I40E_REQ_DESCRIPTOR_MULTIPLE);
6940 break;
6941
38e00438
VD		 6942#ifdef I40E_FCOE
6943 case I40E_VSI_FCOE:
6944 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6945 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6946 I40E_REQ_DESCRIPTOR_MULTIPLE);
6947 vsi->num_q_vectors = pf->num_fcoe_msix;
6948 break;
6949
6950#endif /* I40E_FCOE */
41c445ff
JB		 6951 default:
6952 WARN_ON(1);
6953 return -ENODATA;
6954 }
6955
6956 return 0;
6957}
6958
f650a38b
ASJ		 6959/**
6960 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6961 * @type: VSI pointer
bc7d338f 6962 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6963 *
6964 * On error: returns error code (negative)
6965 * On success: returns 0
6966 **/
bc7d338f 6967static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6968{
6969 int size;
6970 int ret = 0;
6971
ac6c5e3d 6972 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6973 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6974 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6975 if (!vsi->tx_rings)
6976 return -ENOMEM;
f650a38b
ASJ		 6977 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6978
bc7d338f
ASJ		 6979 if (alloc_qvectors) {
6980 /* allocate memory for q_vector pointers */
f57e4fbd 6981 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6982 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6983 if (!vsi->q_vectors) {
6984 ret = -ENOMEM;
6985 goto err_vectors;
6986 }
f650a38b
ASJ		 6987 }
6988 return ret;
6989
6990err_vectors:
6991 kfree(vsi->tx_rings);
6992 return ret;
6993}
6994
41c445ff
JB		 6995/**
6996 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6997 * @pf: board private structure
6998 * @type: type of VSI
6999 *
7000 * On error: returns error code (negative)
7001 * On success: returns vsi index in PF (positive)
7002 **/
7003static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7004{
7005 int ret = -ENODEV;
7006 struct i40e_vsi *vsi;
7007 int vsi_idx;
7008 int i;
7009
7010 /* Need to protect the allocation of the VSIs at the PF level */
7011 mutex_lock(&pf->switch_mutex);
7012
7013 /* VSI list may be fragmented if VSI creation/destruction has
7014 * been happening. We can afford to do a quick scan to look
7015 * for any free VSIs in the list.
7016 *
7017 * find next empty vsi slot, looping back around if necessary
7018 */
7019 i = pf->next_vsi;
505682cd 7020 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7021 i++;
505682cd 7022 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7023 i = 0;
7024 while (i < pf->next_vsi && pf->vsi[i])
7025 i++;
7026 }
7027
505682cd 7028 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7029 vsi_idx = i; /* Found one! */
7030 } else {
7031 ret = -ENODEV;
493fb300 7032 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7033 }
7034 pf->next_vsi = ++i;
7035
7036 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7037 if (!vsi) {
7038 ret = -ENOMEM;
493fb300 7039 goto unlock_pf;
41c445ff
JB		 7040 }
7041 vsi->type = type;
7042 vsi->back = pf;
7043 set_bit(__I40E_DOWN, &vsi->state);
7044 vsi->flags = 0;
7045 vsi->idx = vsi_idx;
7046 vsi->rx_itr_setting = pf->rx_itr_default;
7047 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 7048 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7049 pf->rss_table_size : 64;
41c445ff
JB		 7050 vsi->netdev_registered = false;
7051 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7052 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7053 vsi->irqs_ready = false;
41c445ff 7054
9f65e15b
AD		 7055 ret = i40e_set_num_rings_in_vsi(vsi);
7056 if (ret)
7057 goto err_rings;
7058
bc7d338f 7059 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7060 if (ret)
9f65e15b 7061 goto err_rings;
493fb300 7062
41c445ff
JB		 7063 /* Setup default MSIX irq handler for VSI */
7064 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7065
7066 pf->vsi[vsi_idx] = vsi;
7067 ret = vsi_idx;
493fb300
AD		 7068 goto unlock_pf;
7069
9f65e15b 7070err_rings:
493fb300
AD		 7071 pf->next_vsi = i - 1;
7072 kfree(vsi);
7073unlock_pf:
41c445ff
JB		 7074 mutex_unlock(&pf->switch_mutex);
7075 return ret;
7076}
7077
f650a38b
ASJ		 7078/**
7079 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7080 * @type: VSI pointer
bc7d338f 7081 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7082 *
7083 * On error: returns error code (negative)
7084 * On success: returns 0
7085 **/
bc7d338f 7086static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7087{
7088 /* free the ring and vector containers */
bc7d338f
ASJ		 7089 if (free_qvectors) {
7090 kfree(vsi->q_vectors);
7091 vsi->q_vectors = NULL;
7092 }
f650a38b
ASJ		 7093 kfree(vsi->tx_rings);
7094 vsi->tx_rings = NULL;
7095 vsi->rx_rings = NULL;
7096}
7097
41c445ff
JB		 7098/**
7099 * i40e_vsi_clear - Deallocate the VSI provided
7100 * @vsi: the VSI being un-configured
7101 **/
7102static int i40e_vsi_clear(struct i40e_vsi *vsi)
7103{
7104 struct i40e_pf *pf;
7105
7106 if (!vsi)
7107 return 0;
7108
7109 if (!vsi->back)
7110 goto free_vsi;
7111 pf = vsi->back;
7112
7113 mutex_lock(&pf->switch_mutex);
7114 if (!pf->vsi[vsi->idx]) {
7115 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7116 vsi->idx, vsi->idx, vsi, vsi->type);
7117 goto unlock_vsi;
7118 }
7119
7120 if (pf->vsi[vsi->idx] != vsi) {
7121 dev_err(&pf->pdev->dev,
7122 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7123 pf->vsi[vsi->idx]->idx,
7124 pf->vsi[vsi->idx],
7125 pf->vsi[vsi->idx]->type,
7126 vsi->idx, vsi, vsi->type);
7127 goto unlock_vsi;
7128 }
7129
b40c82e6 7130 /* updates the PF for this cleared vsi */
41c445ff
JB		 7131 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7132 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7133
bc7d338f 7134 i40e_vsi_free_arrays(vsi, true);
493fb300 7135
41c445ff
JB		 7136 pf->vsi[vsi->idx] = NULL;
7137 if (vsi->idx < pf->next_vsi)
7138 pf->next_vsi = vsi->idx;
7139
7140unlock_vsi:
7141 mutex_unlock(&pf->switch_mutex);
7142free_vsi:
7143 kfree(vsi);
7144
7145 return 0;
7146}
7147
9f65e15b
AD		 7148/**
7149 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7150 * @vsi: the VSI being cleaned
7151 **/
be1d5eea 7152static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7153{
7154 int i;
7155
8e9dca53 7156 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7157 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7158 kfree_rcu(vsi->tx_rings[i], rcu);
7159 vsi->tx_rings[i] = NULL;
7160 vsi->rx_rings[i] = NULL;
7161 }
be1d5eea 7162 }
9f65e15b
AD		 7163}
7164
41c445ff
JB		 7165/**
7166 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7167 * @vsi: the VSI being configured
7168 **/
7169static int i40e_alloc_rings(struct i40e_vsi *vsi)
7170{
e7046ee1 7171 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7172 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7173 int i;
7174
41c445ff 7175 /* Set basic values in the rings to be used later during open() */
d7397644 7176 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7177 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7178 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7179 if (!tx_ring)
7180 goto err_out;
41c445ff
JB		 7181
7182 tx_ring->queue_index = i;
7183 tx_ring->reg_idx = vsi->base_queue + i;
7184 tx_ring->ring_active = false;
7185 tx_ring->vsi = vsi;
7186 tx_ring->netdev = vsi->netdev;
7187 tx_ring->dev = &pf->pdev->dev;
7188 tx_ring->count = vsi->num_desc;
7189 tx_ring->size = 0;
7190 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7191 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7192 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7193 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7194 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7195 vsi->tx_rings[i] = tx_ring;
41c445ff 7196
9f65e15b 7197 rx_ring = &tx_ring[1];
41c445ff
JB		 7198 rx_ring->queue_index = i;
7199 rx_ring->reg_idx = vsi->base_queue + i;
7200 rx_ring->ring_active = false;
7201 rx_ring->vsi = vsi;
7202 rx_ring->netdev = vsi->netdev;
7203 rx_ring->dev = &pf->pdev->dev;
7204 rx_ring->count = vsi->num_desc;
7205 rx_ring->size = 0;
7206 rx_ring->dcb_tc = 0;
7207 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7208 set_ring_16byte_desc_enabled(rx_ring);
7209 else
7210 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7211 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7212 }
7213
7214 return 0;
9f65e15b
AD		 7215
7216err_out:
7217 i40e_vsi_clear_rings(vsi);
7218 return -ENOMEM;
41c445ff
JB		 7219}
7220
7221/**
7222 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7223 * @pf: board private structure
7224 * @vectors: the number of MSI-X vectors to request
7225 *
7226 * Returns the number of vectors reserved, or error
7227 **/
7228static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7229{
7b37f376
AG		 7230 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7231 I40E_MIN_MSIX, vectors);
7232 if (vectors < 0) {
41c445ff 7233 dev_info(&pf->pdev->dev,
7b37f376 7234 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7235 vectors = 0;
7236 }
7237
7238 return vectors;
7239}
7240
7241/**
7242 * i40e_init_msix - Setup the MSIX capability
7243 * @pf: board private structure
7244 *
7245 * Work with the OS to set up the MSIX vectors needed.
7246 *
3b444399 7247 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7248 **/
7249static int i40e_init_msix(struct i40e_pf *pf)
7250{
41c445ff 7251 struct i40e_hw *hw = &pf->hw;
1e200e4a 7252 int vectors_left;
41c445ff 7253 int v_budget, i;
3b444399 7254 int v_actual;
41c445ff
JB		 7255
7256 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7257 return -ENODEV;
7258
7259 /* The number of vectors we'll request will be comprised of:
7260 * - Add 1 for "other" cause for Admin Queue events, etc.
7261 * - The number of LAN queue pairs
f8ff1464
ASJ		 7262 * - Queues being used for RSS.
7263 * We don't need as many as max_rss_size vectors.
7264 * use rss_size instead in the calculation since that
7265 * is governed by number of cpus in the system.
7266 * - assumes symmetric Tx/Rx pairing
41c445ff 7267 * - The number of VMDq pairs
38e00438
VD		 7268#ifdef I40E_FCOE
7269 * - The number of FCOE qps.
7270#endif
41c445ff
JB		 7271 * Once we count this up, try the request.
7272 *
7273 * If we can't get what we want, we'll simplify to nearly nothing
7274 * and try again. If that still fails, we punt.
7275 */
1e200e4a
SN		 7276 vectors_left = hw->func_caps.num_msix_vectors;
7277 v_budget = 0;
7278
7279 /* reserve one vector for miscellaneous handler */
7280 if (vectors_left) {
7281 v_budget++;
7282 vectors_left--;
7283 }
7284
7285 /* reserve vectors for the main PF traffic queues */
7286 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7287 vectors_left -= pf->num_lan_msix;
7288 v_budget += pf->num_lan_msix;
7289
7290 /* reserve one vector for sideband flow director */
7291 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7292 if (vectors_left) {
7293 v_budget++;
7294 vectors_left--;
7295 } else {
7296 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7297 }
7298 }
83840e4b 7299
38e00438 7300#ifdef I40E_FCOE
1e200e4a 7301 /* can we reserve enough for FCoE? */
38e00438 7302 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7303 if (!vectors_left)
7304 pf->num_fcoe_msix = 0;
7305 else if (vectors_left >= pf->num_fcoe_qps)
7306 pf->num_fcoe_msix = pf->num_fcoe_qps;
7307 else
7308 pf->num_fcoe_msix = 1;
38e00438 7309 v_budget += pf->num_fcoe_msix;
1e200e4a 7310 vectors_left -= pf->num_fcoe_msix;
38e00438 7311 }
1e200e4a 7312
38e00438 7313#endif
1e200e4a
SN		 7314 /* any vectors left over go for VMDq support */
7315 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7316 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7317 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7318
7319 /* if we're short on vectors for what's desired, we limit
7320 * the queues per vmdq. If this is still more than are
7321 * available, the user will need to change the number of
7322 * queues/vectors used by the PF later with the ethtool
7323 * channels command
7324 */
7325 if (vmdq_vecs < vmdq_vecs_wanted)
7326 pf->num_vmdq_qps = 1;
7327 pf->num_vmdq_msix = pf->num_vmdq_qps;
7328
7329 v_budget += vmdq_vecs;
7330 vectors_left -= vmdq_vecs;
7331 }
41c445ff
JB		 7332
7333 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7334 GFP_KERNEL);
7335 if (!pf->msix_entries)
7336 return -ENOMEM;
7337
7338 for (i = 0; i < v_budget; i++)
7339 pf->msix_entries[i].entry = i;
3b444399 7340 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7341
3b444399 7342 if (v_actual != v_budget) {
a34977ba
ASJ		 7343 /* If we have limited resources, we will start with no vectors
7344 * for the special features and then allocate vectors to some
7345 * of these features based on the policy and at the end disable
7346 * the features that did not get any vectors.
7347 */
38e00438
VD		 7348#ifdef I40E_FCOE
7349 pf->num_fcoe_qps = 0;
7350 pf->num_fcoe_msix = 0;
7351#endif
a34977ba
ASJ		 7352 pf->num_vmdq_msix = 0;
7353 }
7354
3b444399 7355 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7356 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7357 kfree(pf->msix_entries);
7358 pf->msix_entries = NULL;
7359 return -ENODEV;
7360
3b444399 7361 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7362 /* Adjust for minimal MSIX use */
41c445ff
JB		 7363 pf->num_vmdq_vsis = 0;
7364 pf->num_vmdq_qps = 0;
41c445ff
JB		 7365 pf->num_lan_qps = 1;
7366 pf->num_lan_msix = 1;
7367
3b444399
SN		 7368 } else if (v_actual != v_budget) {
7369 int vec;
7370
a34977ba 7371 /* reserve the misc vector */
3b444399 7372 vec = v_actual - 1;
a34977ba 7373
41c445ff
JB		 7374 /* Scale vector usage down */
7375 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7376 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7377 pf->num_vmdq_qps = 1;
7378 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7379
7380 /* partition out the remaining vectors */
7381 switch (vec) {
7382 case 2:
41c445ff
JB		 7383 pf->num_lan_msix = 1;
7384 break;
7385 case 3:
38e00438
VD		 7386#ifdef I40E_FCOE
7387 /* give one vector to FCoE */
7388 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7389 pf->num_lan_msix = 1;
7390 pf->num_fcoe_msix = 1;
7391 }
7392#else
41c445ff 7393 pf->num_lan_msix = 2;
38e00438 7394#endif
41c445ff
JB		 7395 break;
7396 default:
38e00438
VD		 7397#ifdef I40E_FCOE
7398 /* give one vector to FCoE */
7399 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7400 pf->num_fcoe_msix = 1;
7401 vec--;
7402 }
7403#endif
1e200e4a
SN		 7404 /* give the rest to the PF */
7405 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7406 break;
7407 }
7408 }
7409
a34977ba
ASJ		 7410 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7411 (pf->num_vmdq_msix == 0)) {
7412 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7413 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7414 }
38e00438
VD		 7415#ifdef I40E_FCOE
7416
7417 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7418 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7419 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7420 }
7421#endif
3b444399 7422 return v_actual;
41c445ff
JB		 7423}
7424
493fb300 7425/**
90e04070 7426 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7427 * @vsi: the VSI being configured
7428 * @v_idx: index of the vector in the vsi struct
7429 *
7430 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7431 **/
90e04070 7432static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7433{
7434 struct i40e_q_vector *q_vector;
7435
7436 /* allocate q_vector */
7437 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7438 if (!q_vector)
7439 return -ENOMEM;
7440
7441 q_vector->vsi = vsi;
7442 q_vector->v_idx = v_idx;
7443 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7444 if (vsi->netdev)
7445 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7446 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7447
cd0b6fa6
AD		 7448 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7449 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7450
493fb300
AD		 7451 /* tie q_vector and vsi together */
7452 vsi->q_vectors[v_idx] = q_vector;
7453
7454 return 0;
7455}
7456
41c445ff 7457/**
90e04070 7458 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7459 * @vsi: the VSI being configured
7460 *
7461 * We allocate one q_vector per queue interrupt. If allocation fails we
7462 * return -ENOMEM.
7463 **/
90e04070 7464static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7465{
7466 struct i40e_pf *pf = vsi->back;
7467 int v_idx, num_q_vectors;
493fb300 7468 int err;
41c445ff
JB		 7469
7470 /* if not MSIX, give the one vector only to the LAN VSI */
7471 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7472 num_q_vectors = vsi->num_q_vectors;
7473 else if (vsi == pf->vsi[pf->lan_vsi])
7474 num_q_vectors = 1;
7475 else
7476 return -EINVAL;
7477
41c445ff 7478 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7479 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7480 if (err)
7481 goto err_out;
41c445ff
JB		 7482 }
7483
7484 return 0;
493fb300
AD		 7485
7486err_out:
7487 while (v_idx--)
7488 i40e_free_q_vector(vsi, v_idx);
7489
7490 return err;
41c445ff
JB		 7491}
7492
7493/**
7494 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7495 * @pf: board private structure to initialize
7496 **/
c1147280 7497static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7498{
3b444399
SN		 7499 int vectors = 0;
7500 ssize_t size;
41c445ff
JB		 7501
7502 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7503 vectors = i40e_init_msix(pf);
7504 if (vectors < 0) {
60ea5f83 7505 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7506#ifdef I40E_FCOE
7507 I40E_FLAG_FCOE_ENABLED |
7508#endif
60ea5f83 7509 I40E_FLAG_RSS_ENABLED |
4d9b6043 7510 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7511 I40E_FLAG_SRIOV_ENABLED |
7512 I40E_FLAG_FD_SB_ENABLED |
7513 I40E_FLAG_FD_ATR_ENABLED |
7514 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7515
7516 /* rework the queue expectations without MSIX */
7517 i40e_determine_queue_usage(pf);
7518 }
7519 }
7520
7521 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7522 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7523 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7524 vectors = pci_enable_msi(pf->pdev);
7525 if (vectors < 0) {
7526 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7527 vectors);
41c445ff
JB		 7528 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7529 }
3b444399 7530 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7531 }
7532
958a3e3b 7533 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7534 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7535
3b444399
SN		 7536 /* set up vector assignment tracking */
7537 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7538 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7539 if (!pf->irq_pile) {
7540 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7541 return -ENOMEM;
7542 }
3b444399
SN		 7543 pf->irq_pile->num_entries = vectors;
7544 pf->irq_pile->search_hint = 0;
7545
c1147280 7546 /* track first vector for misc interrupts, ignore return */
3b444399 7547 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7548
7549 return 0;
41c445ff
JB		 7550}
7551
7552/**
7553 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7554 * @pf: board private structure
7555 *
7556 * This sets up the handler for MSIX 0, which is used to manage the
7557 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7558 * when in MSI or Legacy interrupt mode.
7559 **/
7560static int i40e_setup_misc_vector(struct i40e_pf *pf)
7561{
7562 struct i40e_hw *hw = &pf->hw;
7563 int err = 0;
7564
7565 /* Only request the irq if this is the first time through, and
7566 * not when we're rebuilding after a Reset
7567 */
7568 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7569 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7570 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7571 if (err) {
7572 dev_info(&pf->pdev->dev,
77fa28be 7573 "request_irq for %s failed: %d\n",
b294ac70 7574 pf->int_name, err);
41c445ff
JB		 7575 return -EFAULT;
7576 }
7577 }
7578
ab437b5a 7579 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7580
7581 /* associate no queues to the misc vector */
7582 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7583 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7584
7585 i40e_flush(hw);
7586
7587 i40e_irq_dynamic_enable_icr0(pf);
7588
7589 return err;
7590}
7591
7592/**
e25d00b8
ASJ		 7593 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7594 * @vsi: vsi structure
7595 * @seed: RSS hash seed
7596 **/
7597static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7598{
7599 struct i40e_aqc_get_set_rss_key_data rss_key;
7600 struct i40e_pf *pf = vsi->back;
7601 struct i40e_hw *hw = &pf->hw;
7602 bool pf_lut = false;
7603 u8 *rss_lut;
7604 int ret, i;
7605
7606 memset(&rss_key, 0, sizeof(rss_key));
7607 memcpy(&rss_key, seed, sizeof(rss_key));
7608
7609 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7610 if (!rss_lut)
7611 return -ENOMEM;
7612
7613 /* Populate the LUT with max no. of queues in round robin fashion */
7614 for (i = 0; i < vsi->rss_table_size; i++)
7615 rss_lut[i] = i % vsi->rss_size;
7616
7617 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7618 if (ret) {
7619 dev_info(&pf->pdev->dev,
7620 "Cannot set RSS key, err %s aq_err %s\n",
7621 i40e_stat_str(&pf->hw, ret),
7622 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7623 goto config_rss_aq_out;
e25d00b8
ASJ		 7624 }
7625
7626 if (vsi->type == I40E_VSI_MAIN)
7627 pf_lut = true;
7628
7629 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7630 vsi->rss_table_size);
7631 if (ret)
7632 dev_info(&pf->pdev->dev,
7633 "Cannot set RSS lut, err %s aq_err %s\n",
7634 i40e_stat_str(&pf->hw, ret),
7635 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7636
126b63d9
AS		 7637config_rss_aq_out:
7638 kfree(rss_lut);
e25d00b8
ASJ		 7639 return ret;
7640}
7641
7642/**
7643 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7644 * @vsi: VSI structure
7645 **/
7646static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7647{
7648 u8 seed[I40E_HKEY_ARRAY_SIZE];
7649 struct i40e_pf *pf = vsi->back;
7650
7651 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7652 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7653
7654 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7655 return i40e_config_rss_aq(vsi, seed);
7656
7657 return 0;
7658}
7659
7660/**
7661 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7662 * @pf: board private structure
e25d00b8 7663 * @seed: RSS hash seed
41c445ff 7664 **/
e25d00b8 7665static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7666{
66ddcffb 7667 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7668 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7669 u32 *seed_dw = (u32 *)seed;
7670 u32 current_queue = 0;
4617e8c0
ASJ		 7671 u32 lut = 0;
7672 int i, j;
41c445ff 7673
e25d00b8 7674 /* Fill out hash function seed */
41c445ff 7675 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7676 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7677
7678 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7679 lut = 0;
7680 for (j = 0; j < 4; j++) {
7681 if (current_queue == vsi->rss_size)
7682 current_queue = 0;
7683 lut |= ((current_queue) << (8 * j));
7684 current_queue++;
7685 }
7686 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7687 }
7688 i40e_flush(hw);
7689
7690 return 0;
7691}
7692
7693/**
7694 * i40e_config_rss - Prepare for RSS if used
7695 * @pf: board private structure
7696 **/
7697static int i40e_config_rss(struct i40e_pf *pf)
7698{
7699 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7700 u8 seed[I40E_HKEY_ARRAY_SIZE];
7701 struct i40e_hw *hw = &pf->hw;
7702 u32 reg_val;
7703 u64 hena;
7704
7705 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7706
7707 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7708 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7709 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7710 hena |= i40e_pf_get_default_rss_hena(pf);
7711
41c445ff
JB		 7712 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7713 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7714
66ddcffb
ASJ		 7715 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7716
e25d00b8 7717 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7718 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7719 reg_val = (pf->rss_table_size == 512) ?
7720 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7721 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7722 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7723
e25d00b8
ASJ		 7724 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7725 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7726 else
7727 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7728}
7729
f8ff1464
ASJ		 7730/**
7731 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7732 * @pf: board private structure
7733 * @queue_count: the requested queue count for rss.
7734 *
7735 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7736 * count which may be different from the requested queue count.
7737 **/
7738int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7739{
9a3bd2f1
ASJ		 7740 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7741 int new_rss_size;
7742
f8ff1464
ASJ		 7743 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7744 return 0;
7745
9a3bd2f1 7746 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7747
9a3bd2f1
ASJ		 7748 if (queue_count != vsi->num_queue_pairs) {
7749 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7750 i40e_prep_for_reset(pf);
7751
9a3bd2f1 7752 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7753
7754 i40e_reset_and_rebuild(pf, true);
7755 i40e_config_rss(pf);
7756 }
7757 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7758 return pf->rss_size;
7759}
7760
f4492db1
GR		 7761/**
7762 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7763 * @pf: board private structure
7764 **/
7765i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7766{
7767 i40e_status status;
7768 bool min_valid, max_valid;
7769 u32 max_bw, min_bw;
7770
7771 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7772 &min_valid, &max_valid);
7773
7774 if (!status) {
7775 if (min_valid)
7776 pf->npar_min_bw = min_bw;
7777 if (max_valid)
7778 pf->npar_max_bw = max_bw;
7779 }
7780
7781 return status;
7782}
7783
7784/**
7785 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7786 * @pf: board private structure
7787 **/
7788i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7789{
7790 struct i40e_aqc_configure_partition_bw_data bw_data;
7791 i40e_status status;
7792
b40c82e6 7793 /* Set the valid bit for this PF */
41a1d04b 7794 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7795 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7796 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7797
7798 /* Set the new bandwidths */
7799 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7800
7801 return status;
7802}
7803
7804/**
7805 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7806 * @pf: board private structure
7807 **/
7808i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7809{
7810 /* Commit temporary BW setting to permanent NVM image */
7811 enum i40e_admin_queue_err last_aq_status;
7812 i40e_status ret;
7813 u16 nvm_word;
7814
7815 if (pf->hw.partition_id != 1) {
7816 dev_info(&pf->pdev->dev,
7817 "Commit BW only works on partition 1! This is partition %d",
7818 pf->hw.partition_id);
7819 ret = I40E_NOT_SUPPORTED;
7820 goto bw_commit_out;
7821 }
7822
7823 /* Acquire NVM for read access */
7824 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7825 last_aq_status = pf->hw.aq.asq_last_status;
7826 if (ret) {
7827 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7828 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7829 i40e_stat_str(&pf->hw, ret),
7830 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7831 goto bw_commit_out;
7832 }
7833
7834 /* Read word 0x10 of NVM - SW compatibility word 1 */
7835 ret = i40e_aq_read_nvm(&pf->hw,
7836 I40E_SR_NVM_CONTROL_WORD,
7837 0x10, sizeof(nvm_word), &nvm_word,
7838 false, NULL);
7839 /* Save off last admin queue command status before releasing
7840 * the NVM
7841 */
7842 last_aq_status = pf->hw.aq.asq_last_status;
7843 i40e_release_nvm(&pf->hw);
7844 if (ret) {
f1c7e72e
SN		 7845 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7846 i40e_stat_str(&pf->hw, ret),
7847 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7848 goto bw_commit_out;
7849 }
7850
7851 /* Wait a bit for NVM release to complete */
7852 msleep(50);
7853
7854 /* Acquire NVM for write access */
7855 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7856 last_aq_status = pf->hw.aq.asq_last_status;
7857 if (ret) {
7858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7859 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7860 i40e_stat_str(&pf->hw, ret),
7861 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7862 goto bw_commit_out;
7863 }
7864 /* Write it back out unchanged to initiate update NVM,
7865 * which will force a write of the shadow (alt) RAM to
7866 * the NVM - thus storing the bandwidth values permanently.
7867 */
7868 ret = i40e_aq_update_nvm(&pf->hw,
7869 I40E_SR_NVM_CONTROL_WORD,
7870 0x10, sizeof(nvm_word),
7871 &nvm_word, true, NULL);
7872 /* Save off last admin queue command status before releasing
7873 * the NVM
7874 */
7875 last_aq_status = pf->hw.aq.asq_last_status;
7876 i40e_release_nvm(&pf->hw);
7877 if (ret)
7878 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7879 "BW settings NOT SAVED, err %s aq_err %s\n",
7880 i40e_stat_str(&pf->hw, ret),
7881 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7882bw_commit_out:
7883
7884 return ret;
7885}
7886
41c445ff
JB		 7887/**
7888 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7889 * @pf: board private structure to initialize
7890 *
7891 * i40e_sw_init initializes the Adapter private data structure.
7892 * Fields are initialized based on PCI device information and
7893 * OS network device settings (MTU size).
7894 **/
7895static int i40e_sw_init(struct i40e_pf *pf)
7896{
7897 int err = 0;
7898 int size;
7899
7900 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7901 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7902 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7903 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7904 if (I40E_DEBUG_USER & debug)
7905 pf->hw.debug_mask = debug;
7906 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7907 I40E_DEFAULT_MSG_ENABLE);
7908 }
7909
7910 /* Set default capability flags */
7911 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7912 I40E_FLAG_MSI_ENABLED |
9ac77266 7913 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 7914 I40E_FLAG_MSIX_ENABLED;
7915
7916 if (iommu_present(&pci_bus_type))
7917 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7918 else
7919 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7920
ca99eb99
MW		 7921 /* Set default ITR */
7922 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7923 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7924
7134f9ce
JB		 7925 /* Depending on PF configurations, it is possible that the RSS
7926 * maximum might end up larger than the available queues
7927 */
41a1d04b 7928 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7929 pf->rss_size = 1;
5db4cb59 7930 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7931 pf->rss_size_max = min_t(int, pf->rss_size_max,
7932 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7933 if (pf->hw.func_caps.rss) {
7934 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7935 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7936 }
7937
2050bc65 7938 /* MFP mode enabled */
c78b953e 7939 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7940 pf->flags |= I40E_FLAG_MFP_ENABLED;
7941 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7942 if (i40e_get_npar_bw_setting(pf))
7943 dev_warn(&pf->pdev->dev,
7944 "Could not get NPAR bw settings\n");
7945 else
7946 dev_info(&pf->pdev->dev,
7947 "Min BW = %8.8x, Max BW = %8.8x\n",
7948 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7949 }
7950
cbf61325
ASJ		 7951 /* FW/NVM is not yet fixed in this regard */
7952 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7953 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7954 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7955 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 7956 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7957 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7958 } else {
7959 dev_info(&pf->pdev->dev,
0b67584f 7960 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7961 }
cbf61325
ASJ		 7962 pf->fdir_pf_filter_count =
7963 pf->hw.func_caps.fd_filters_guaranteed;
7964 pf->hw.fdir_shared_filter_count =
7965 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7966 }
7967
7968 if (pf->hw.func_caps.vmdq) {
41c445ff 7969 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 7970 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
41c445ff
JB		 7971 }
7972
38e00438 7973#ifdef I40E_FCOE
21364bcf 7974 i40e_init_pf_fcoe(pf);
38e00438
VD		 7975
7976#endif /* I40E_FCOE */
41c445ff 7977#ifdef CONFIG_PCI_IOV
ba252f13 7978 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7979 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7980 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7981 pf->num_req_vfs = min_t(int,
7982 pf->hw.func_caps.num_vfs,
7983 I40E_MAX_VF_COUNT);
7984 }
7985#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7986 if (pf->hw.mac.type == I40E_MAC_X722) {
7987 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7988 I40E_FLAG_128_QP_RSS_CAPABLE |
7989 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7990 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7991 I40E_FLAG_WB_ON_ITR_CAPABLE |
7992 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
7993 }
41c445ff
JB		 7994 pf->eeprom_version = 0xDEAD;
7995 pf->lan_veb = I40E_NO_VEB;
7996 pf->lan_vsi = I40E_NO_VSI;
7997
d1a8d275
ASJ		 7998 /* By default FW has this off for performance reasons */
7999 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8000
41c445ff
JB		 8001 /* set up queue assignment tracking */
8002 size = sizeof(struct i40e_lump_tracking)
8003 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8004 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8005 if (!pf->qp_pile) {
8006 err = -ENOMEM;
8007 goto sw_init_done;
8008 }
8009 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8010 pf->qp_pile->search_hint = 0;
8011
327fe04b
ASJ		 8012 pf->tx_timeout_recovery_level = 1;
8013
41c445ff
JB		 8014 mutex_init(&pf->switch_mutex);
8015
c668a12c
GR		 8016 /* If NPAR is enabled nudge the Tx scheduler */
8017 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8018 i40e_set_npar_bw_setting(pf);
8019
41c445ff
JB		 8020sw_init_done:
8021 return err;
8022}
8023
7c3c288b
ASJ		 8024/**
8025 * i40e_set_ntuple - set the ntuple feature flag and take action
8026 * @pf: board private structure to initialize
8027 * @features: the feature set that the stack is suggesting
8028 *
8029 * returns a bool to indicate if reset needs to happen
8030 **/
8031bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8032{
8033 bool need_reset = false;
8034
8035 /* Check if Flow Director n-tuple support was enabled or disabled. If
8036 * the state changed, we need to reset.
8037 */
8038 if (features & NETIF_F_NTUPLE) {
8039 /* Enable filters and mark for reset */
8040 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8041 need_reset = true;
8042 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8043 } else {
8044 /* turn off filters, mark for reset and clear SW filter list */
8045 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8046 need_reset = true;
8047 i40e_fdir_filter_exit(pf);
8048 }
8049 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8050 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8051 /* reset fd counters */
8052 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8053 pf->fdir_pf_active_filters = 0;
8054 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8055 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8056 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8057 /* if ATR was auto disabled it can be re-enabled. */
8058 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8059 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8060 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8061 }
8062 return need_reset;
8063}
8064
41c445ff
JB		 8065/**
8066 * i40e_set_features - set the netdev feature flags
8067 * @netdev: ptr to the netdev being adjusted
8068 * @features: the feature set that the stack is suggesting
8069 **/
8070static int i40e_set_features(struct net_device *netdev,
8071 netdev_features_t features)
8072{
8073 struct i40e_netdev_priv *np = netdev_priv(netdev);
8074 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8075 struct i40e_pf *pf = vsi->back;
8076 bool need_reset;
41c445ff
JB		 8077
8078 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8079 i40e_vlan_stripping_enable(vsi);
8080 else
8081 i40e_vlan_stripping_disable(vsi);
8082
7c3c288b
ASJ		 8083 need_reset = i40e_set_ntuple(pf, features);
8084
8085 if (need_reset)
41a1d04b 8086 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8087
41c445ff
JB		 8088 return 0;
8089}
8090
a1c9a9d9
JK		 8091#ifdef CONFIG_I40E_VXLAN
8092/**
8093 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8094 * @pf: board private structure
8095 * @port: The UDP port to look up
8096 *
8097 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8098 **/
8099static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8100{
8101 u8 i;
8102
8103 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8104 if (pf->vxlan_ports[i] == port)
8105 return i;
8106 }
8107
8108 return i;
8109}
8110
8111/**
8112 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8113 * @netdev: This physical port's netdev
8114 * @sa_family: Socket Family that VXLAN is notifying us about
8115 * @port: New UDP port number that VXLAN started listening to
8116 **/
8117static void i40e_add_vxlan_port(struct net_device *netdev,
8118 sa_family_t sa_family, __be16 port)
8119{
8120 struct i40e_netdev_priv *np = netdev_priv(netdev);
8121 struct i40e_vsi *vsi = np->vsi;
8122 struct i40e_pf *pf = vsi->back;
8123 u8 next_idx;
8124 u8 idx;
8125
8126 if (sa_family == AF_INET6)
8127 return;
8128
8129 idx = i40e_get_vxlan_port_idx(pf, port);
8130
8131 /* Check if port already exists */
8132 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8133 netdev_info(netdev, "vxlan port %d already offloaded\n",
8134 ntohs(port));
a1c9a9d9
JK		 8135 return;
8136 }
8137
8138 /* Now check if there is space to add the new port */
8139 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8140
8141 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8142 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8143 ntohs(port));
8144 return;
8145 }
8146
8147 /* New port: add it and mark its index in the bitmap */
8148 pf->vxlan_ports[next_idx] = port;
41a1d04b 8149 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8150 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8151}
8152
8153/**
8154 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8155 * @netdev: This physical port's netdev
8156 * @sa_family: Socket Family that VXLAN is notifying us about
8157 * @port: UDP port number that VXLAN stopped listening to
8158 **/
8159static void i40e_del_vxlan_port(struct net_device *netdev,
8160 sa_family_t sa_family, __be16 port)
8161{
8162 struct i40e_netdev_priv *np = netdev_priv(netdev);
8163 struct i40e_vsi *vsi = np->vsi;
8164 struct i40e_pf *pf = vsi->back;
8165 u8 idx;
8166
8167 if (sa_family == AF_INET6)
8168 return;
8169
8170 idx = i40e_get_vxlan_port_idx(pf, port);
8171
8172 /* Check if port already exists */
8173 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8174 /* if port exists, set it to 0 (mark for deletion)
8175 * and make it pending
8176 */
8177 pf->vxlan_ports[idx] = 0;
41a1d04b 8178 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8179 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8180 } else {
c22c06c8 8181 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8182 ntohs(port));
8183 }
8184}
8185
8186#endif
1f224ad2 8187static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8188 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8189{
8190 struct i40e_netdev_priv *np = netdev_priv(netdev);
8191 struct i40e_pf *pf = np->vsi->back;
8192 struct i40e_hw *hw = &pf->hw;
8193
8194 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8195 return -EOPNOTSUPP;
8196
8197 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8198 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8199
8200 return 0;
8201}
8202
2f90ade6
JB		 8203/**
8204 * i40e_ndo_fdb_add - add an entry to the hardware database
8205 * @ndm: the input from the stack
8206 * @tb: pointer to array of nladdr (unused)
8207 * @dev: the net device pointer
8208 * @addr: the MAC address entry being added
8209 * @flags: instructions from stack about fdb operation
8210 */
4ba0dea5
GR		 8211static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8212 struct net_device *dev,
f6f6424b 8213 const unsigned char *addr, u16 vid,
4ba0dea5 8214 u16 flags)
4ba0dea5
GR		 8215{
8216 struct i40e_netdev_priv *np = netdev_priv(dev);
8217 struct i40e_pf *pf = np->vsi->back;
8218 int err = 0;
8219
8220 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8221 return -EOPNOTSUPP;
8222
65891fea
OG		 8223 if (vid) {
8224 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8225 return -EINVAL;
8226 }
8227
4ba0dea5
GR		 8228 /* Hardware does not support aging addresses so if a
8229 * ndm_state is given only allow permanent addresses
8230 */
8231 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8232 netdev_info(dev, "FDB only supports static addresses\n");
8233 return -EINVAL;
8234 }
8235
8236 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8237 err = dev_uc_add_excl(dev, addr);
8238 else if (is_multicast_ether_addr(addr))
8239 err = dev_mc_add_excl(dev, addr);
8240 else
8241 err = -EINVAL;
8242
8243 /* Only return duplicate errors if NLM_F_EXCL is set */
8244 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8245 err = 0;
8246
8247 return err;
8248}
8249
51616018
NP		 8250/**
8251 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8252 * @dev: the netdev being configured
8253 * @nlh: RTNL message
8254 *
8255 * Inserts a new hardware bridge if not already created and
8256 * enables the bridging mode requested (VEB or VEPA). If the
8257 * hardware bridge has already been inserted and the request
8258 * is to change the mode then that requires a PF reset to
8259 * allow rebuild of the components with required hardware
8260 * bridge mode enabled.
8261 **/
8262static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8263 struct nlmsghdr *nlh,
8264 u16 flags)
51616018
NP		 8265{
8266 struct i40e_netdev_priv *np = netdev_priv(dev);
8267 struct i40e_vsi *vsi = np->vsi;
8268 struct i40e_pf *pf = vsi->back;
8269 struct i40e_veb *veb = NULL;
8270 struct nlattr *attr, *br_spec;
8271 int i, rem;
8272
8273 /* Only for PF VSI for now */
8274 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8275 return -EOPNOTSUPP;
8276
8277 /* Find the HW bridge for PF VSI */
8278 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8279 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8280 veb = pf->veb[i];
8281 }
8282
8283 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8284
8285 nla_for_each_nested(attr, br_spec, rem) {
8286 __u16 mode;
8287
8288 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8289 continue;
8290
8291 mode = nla_get_u16(attr);
8292 if ((mode != BRIDGE_MODE_VEPA) &&
8293 (mode != BRIDGE_MODE_VEB))
8294 return -EINVAL;
8295
8296 /* Insert a new HW bridge */
8297 if (!veb) {
8298 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8299 vsi->tc_config.enabled_tc);
8300 if (veb) {
8301 veb->bridge_mode = mode;
8302 i40e_config_bridge_mode(veb);
8303 } else {
8304 /* No Bridge HW offload available */
8305 return -ENOENT;
8306 }
8307 break;
8308 } else if (mode != veb->bridge_mode) {
8309 /* Existing HW bridge but different mode needs reset */
8310 veb->bridge_mode = mode;
fc60861e
ASJ		 8311 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8312 if (mode == BRIDGE_MODE_VEB)
8313 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8314 else
8315 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8316 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8317 break;
8318 }
8319 }
8320
8321 return 0;
8322}
8323
8324/**
8325 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8326 * @skb: skb buff
8327 * @pid: process id
8328 * @seq: RTNL message seq #
8329 * @dev: the netdev being configured
8330 * @filter_mask: unused
8331 *
8332 * Return the mode in which the hardware bridge is operating in
8333 * i.e VEB or VEPA.
8334 **/
51616018
NP		 8335static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8336 struct net_device *dev,
7d4f8d87 8337 u32 filter_mask, int nlflags)
51616018
NP		 8338{
8339 struct i40e_netdev_priv *np = netdev_priv(dev);
8340 struct i40e_vsi *vsi = np->vsi;
8341 struct i40e_pf *pf = vsi->back;
8342 struct i40e_veb *veb = NULL;
8343 int i;
8344
8345 /* Only for PF VSI for now */
8346 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8347 return -EOPNOTSUPP;
8348
8349 /* Find the HW bridge for the PF VSI */
8350 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8351 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8352 veb = pf->veb[i];
8353 }
8354
8355 if (!veb)
8356 return 0;
8357
46c264da 8358 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8359 nlflags, 0, 0, filter_mask, NULL);
51616018 8360}
51616018 8361
f44a75e2
JS		 8362#define I40E_MAX_TUNNEL_HDR_LEN 80
8363/**
8364 * i40e_features_check - Validate encapsulated packet conforms to limits
8365 * @skb: skb buff
8366 * @netdev: This physical port's netdev
8367 * @features: Offload features that the stack believes apply
8368 **/
8369static netdev_features_t i40e_features_check(struct sk_buff *skb,
8370 struct net_device *dev,
8371 netdev_features_t features)
8372{
8373 if (skb->encapsulation &&
8374 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8375 I40E_MAX_TUNNEL_HDR_LEN))
8376 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8377
8378 return features;
8379}
8380
37a2973a 8381static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8382 .ndo_open = i40e_open,
8383 .ndo_stop = i40e_close,
8384 .ndo_start_xmit = i40e_lan_xmit_frame,
8385 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8386 .ndo_set_rx_mode = i40e_set_rx_mode,
8387 .ndo_validate_addr = eth_validate_addr,
8388 .ndo_set_mac_address = i40e_set_mac,
8389 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8390 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8391 .ndo_tx_timeout = i40e_tx_timeout,
8392 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8393 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8394#ifdef CONFIG_NET_POLL_CONTROLLER
8395 .ndo_poll_controller = i40e_netpoll,
8396#endif
8397 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8398#ifdef I40E_FCOE
8399 .ndo_fcoe_enable = i40e_fcoe_enable,
8400 .ndo_fcoe_disable = i40e_fcoe_disable,
8401#endif
41c445ff
JB		 8402 .ndo_set_features = i40e_set_features,
8403 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8404 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8405 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8406 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8407 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8408 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8409#ifdef CONFIG_I40E_VXLAN
8410 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8411 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8412#endif
1f224ad2 8413 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8414 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8415 .ndo_features_check = i40e_features_check,
51616018
NP		 8416 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8417 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8418};
8419
8420/**
8421 * i40e_config_netdev - Setup the netdev flags
8422 * @vsi: the VSI being configured
8423 *
8424 * Returns 0 on success, negative value on failure
8425 **/
8426static int i40e_config_netdev(struct i40e_vsi *vsi)
8427{
1a10370a 8428 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8429 struct i40e_pf *pf = vsi->back;
8430 struct i40e_hw *hw = &pf->hw;
8431 struct i40e_netdev_priv *np;
8432 struct net_device *netdev;
8433 u8 mac_addr[ETH_ALEN];
8434 int etherdev_size;
8435
8436 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8437 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8438 if (!netdev)
8439 return -ENOMEM;
8440
8441 vsi->netdev = netdev;
8442 np = netdev_priv(netdev);
8443 np->vsi = vsi;
8444
d70e941b 8445 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8446 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8447 NETIF_F_TSO;
41c445ff
JB		 8448
8449 netdev->features = NETIF_F_SG |
8450 NETIF_F_IP_CSUM |
8451 NETIF_F_SCTP_CSUM |
8452 NETIF_F_HIGHDMA |
8453 NETIF_F_GSO_UDP_TUNNEL |
8454 NETIF_F_HW_VLAN_CTAG_TX |
8455 NETIF_F_HW_VLAN_CTAG_RX |
8456 NETIF_F_HW_VLAN_CTAG_FILTER |
8457 NETIF_F_IPV6_CSUM |
8458 NETIF_F_TSO |
059dab69 8459 NETIF_F_TSO_ECN |
41c445ff
JB		 8460 NETIF_F_TSO6 |
8461 NETIF_F_RXCSUM |
8462 NETIF_F_RXHASH |
8463 0;
8464
2e86a0b6
ASJ		 8465 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8466 netdev->features |= NETIF_F_NTUPLE;
8467
41c445ff
JB		 8468 /* copy netdev features into list of user selectable features */
8469 netdev->hw_features |= netdev->features;
8470
8471 if (vsi->type == I40E_VSI_MAIN) {
8472 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8473 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8474 /* The following steps are necessary to prevent reception
8475 * of tagged packets - some older NVM configurations load a
8476 * default a MAC-VLAN filter that accepts any tagged packet
8477 * which must be replaced by a normal filter.
8c27d42e 8478 */
30650cc5
SN		 8479 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8480 i40e_add_filter(vsi, mac_addr,
8481 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8482 } else {
8483 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8484 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8485 pf->vsi[pf->lan_vsi]->netdev->name);
8486 random_ether_addr(mac_addr);
8487 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8488 }
1a10370a 8489 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8490
9a173901
GR		 8491 ether_addr_copy(netdev->dev_addr, mac_addr);
8492 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8493 /* vlan gets same features (except vlan offload)
8494 * after any tweaks for specific VSI types
8495 */
8496 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8497 NETIF_F_HW_VLAN_CTAG_RX |
8498 NETIF_F_HW_VLAN_CTAG_FILTER);
8499 netdev->priv_flags |= IFF_UNICAST_FLT;
8500 netdev->priv_flags |= IFF_SUPP_NOFCS;
8501 /* Setup netdev TC information */
8502 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8503
8504 netdev->netdev_ops = &i40e_netdev_ops;
8505 netdev->watchdog_timeo = 5 * HZ;
8506 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8507#ifdef I40E_FCOE
8508 i40e_fcoe_config_netdev(netdev, vsi);
8509#endif
41c445ff
JB		 8510
8511 return 0;
8512}
8513
8514/**
8515 * i40e_vsi_delete - Delete a VSI from the switch
8516 * @vsi: the VSI being removed
8517 *
8518 * Returns 0 on success, negative value on failure
8519 **/
8520static void i40e_vsi_delete(struct i40e_vsi *vsi)
8521{
8522 /* remove default VSI is not allowed */
8523 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8524 return;
8525
41c445ff 8526 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8527}
8528
51616018
NP		 8529/**
8530 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8531 * @vsi: the VSI being queried
8532 *
8533 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8534 **/
8535int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8536{
8537 struct i40e_veb *veb;
8538 struct i40e_pf *pf = vsi->back;
8539
8540 /* Uplink is not a bridge so default to VEB */
8541 if (vsi->veb_idx == I40E_NO_VEB)
8542 return 1;
8543
8544 veb = pf->veb[vsi->veb_idx];
8545 /* Uplink is a bridge in VEPA mode */
8546 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8547 return 0;
8548
8549 /* Uplink is a bridge in VEB mode */
8550 return 1;
8551}
8552
41c445ff
JB		 8553/**
8554 * i40e_add_vsi - Add a VSI to the switch
8555 * @vsi: the VSI being configured
8556 *
8557 * This initializes a VSI context depending on the VSI type to be added and
8558 * passes it down to the add_vsi aq command.
8559 **/
8560static int i40e_add_vsi(struct i40e_vsi *vsi)
8561{
8562 int ret = -ENODEV;
8563 struct i40e_mac_filter *f, *ftmp;
8564 struct i40e_pf *pf = vsi->back;
8565 struct i40e_hw *hw = &pf->hw;
8566 struct i40e_vsi_context ctxt;
8567 u8 enabled_tc = 0x1; /* TC0 enabled */
8568 int f_count = 0;
8569
8570 memset(&ctxt, 0, sizeof(ctxt));
8571 switch (vsi->type) {
8572 case I40E_VSI_MAIN:
8573 /* The PF's main VSI is already setup as part of the
8574 * device initialization, so we'll not bother with
8575 * the add_vsi call, but we will retrieve the current
8576 * VSI context.
8577 */
8578 ctxt.seid = pf->main_vsi_seid;
8579 ctxt.pf_num = pf->hw.pf_id;
8580 ctxt.vf_num = 0;
8581 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8582 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8583 if (ret) {
8584 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8585 "couldn't get PF vsi config, err %s aq_err %s\n",
8586 i40e_stat_str(&pf->hw, ret),
8587 i40e_aq_str(&pf->hw,
8588 pf->hw.aq.asq_last_status));
41c445ff
JB		 8589 return -ENOENT;
8590 }
1a2f6248 8591 vsi->info = ctxt.info;
41c445ff
JB		 8592 vsi->info.valid_sections = 0;
8593
8594 vsi->seid = ctxt.seid;
8595 vsi->id = ctxt.vsi_number;
8596
8597 enabled_tc = i40e_pf_get_tc_map(pf);
8598
8599 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8600 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8601 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8602 memset(&ctxt, 0, sizeof(ctxt));
8603 ctxt.seid = pf->main_vsi_seid;
8604 ctxt.pf_num = pf->hw.pf_id;
8605 ctxt.vf_num = 0;
8606 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8607 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8608 if (ret) {
8609 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8610 "update vsi failed, err %s aq_err %s\n",
8611 i40e_stat_str(&pf->hw, ret),
8612 i40e_aq_str(&pf->hw,
8613 pf->hw.aq.asq_last_status));
41c445ff
JB		 8614 ret = -ENOENT;
8615 goto err;
8616 }
8617 /* update the local VSI info queue map */
8618 i40e_vsi_update_queue_map(vsi, &ctxt);
8619 vsi->info.valid_sections = 0;
8620 } else {
8621 /* Default/Main VSI is only enabled for TC0
8622 * reconfigure it to enable all TCs that are
8623 * available on the port in SFP mode.
63d7e5a4
NP		 8624 * For MFP case the iSCSI PF would use this
8625 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8626 */
8627 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8628 if (ret) {
8629 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8630 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8631 enabled_tc,
8632 i40e_stat_str(&pf->hw, ret),
8633 i40e_aq_str(&pf->hw,
8634 pf->hw.aq.asq_last_status));
41c445ff
JB		 8635 ret = -ENOENT;
8636 }
8637 }
8638 break;
8639
8640 case I40E_VSI_FDIR:
cbf61325
ASJ		 8641 ctxt.pf_num = hw->pf_id;
8642 ctxt.vf_num = 0;
8643 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8644 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8645 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8646 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8647 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8648 ctxt.info.valid_sections |=
fc60861e 8649 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8650 ctxt.info.switch_id =
fc60861e 8651 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8652 }
41c445ff 8653 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8654 break;
8655
8656 case I40E_VSI_VMDQ2:
8657 ctxt.pf_num = hw->pf_id;
8658 ctxt.vf_num = 0;
8659 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8660 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8661 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8662
41c445ff
JB		 8663 /* This VSI is connected to VEB so the switch_id
8664 * should be set to zero by default.
8665 */
51616018
NP		 8666 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8667 ctxt.info.valid_sections |=
8668 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8669 ctxt.info.switch_id =
8670 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8671 }
41c445ff
JB		 8672
8673 /* Setup the VSI tx/rx queue map for TC0 only for now */
8674 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8675 break;
8676
8677 case I40E_VSI_SRIOV:
8678 ctxt.pf_num = hw->pf_id;
8679 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8680 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8681 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8682 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8683
41c445ff
JB		 8684 /* This VSI is connected to VEB so the switch_id
8685 * should be set to zero by default.
8686 */
51616018
NP		 8687 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8688 ctxt.info.valid_sections |=
8689 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8690 ctxt.info.switch_id =
8691 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8692 }
41c445ff
JB		 8693
8694 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8695 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8696 if (pf->vf[vsi->vf_id].spoofchk) {
8697 ctxt.info.valid_sections |=
8698 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8699 ctxt.info.sec_flags |=
8700 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8701 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8702 }
41c445ff
JB		 8703 /* Setup the VSI tx/rx queue map for TC0 only for now */
8704 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8705 break;
8706
38e00438
VD		 8707#ifdef I40E_FCOE
8708 case I40E_VSI_FCOE:
8709 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8710 if (ret) {
8711 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8712 return ret;
8713 }
8714 break;
8715
8716#endif /* I40E_FCOE */
41c445ff
JB		 8717 default:
8718 return -ENODEV;
8719 }
8720
8721 if (vsi->type != I40E_VSI_MAIN) {
8722 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8723 if (ret) {
8724 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8725 "add vsi failed, err %s aq_err %s\n",
8726 i40e_stat_str(&pf->hw, ret),
8727 i40e_aq_str(&pf->hw,
8728 pf->hw.aq.asq_last_status));
41c445ff
JB		 8729 ret = -ENOENT;
8730 goto err;
8731 }
1a2f6248 8732 vsi->info = ctxt.info;
41c445ff
JB		 8733 vsi->info.valid_sections = 0;
8734 vsi->seid = ctxt.seid;
8735 vsi->id = ctxt.vsi_number;
8736 }
8737
8738 /* If macvlan filters already exist, force them to get loaded */
8739 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8740 f->changed = true;
8741 f_count++;
6252c7e4
SN		 8742
8743 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8744 struct i40e_aqc_remove_macvlan_element_data element;
8745
8746 memset(&element, 0, sizeof(element));
8747 ether_addr_copy(element.mac_addr, f->macaddr);
8748 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8749 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8750 &element, 1, NULL);
8751 if (ret) {
8752 /* some older FW has a different default */
8753 element.flags |=
8754 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8755 i40e_aq_remove_macvlan(hw, vsi->seid,
8756 &element, 1, NULL);
8757 }
8758
8759 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8760 I40E_AQC_WRITE_TYPE_LAA_WOL,
8761 f->macaddr, NULL);
8762 }
41c445ff
JB		 8763 }
8764 if (f_count) {
8765 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8766 pf->flags |= I40E_FLAG_FILTER_SYNC;
8767 }
8768
8769 /* Update VSI BW information */
8770 ret = i40e_vsi_get_bw_info(vsi);
8771 if (ret) {
8772 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8773 "couldn't get vsi bw info, err %s aq_err %s\n",
8774 i40e_stat_str(&pf->hw, ret),
8775 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8776 /* VSI is already added so not tearing that up */
8777 ret = 0;
8778 }
8779
8780err:
8781 return ret;
8782}
8783
8784/**
8785 * i40e_vsi_release - Delete a VSI and free its resources
8786 * @vsi: the VSI being removed
8787 *
8788 * Returns 0 on success or < 0 on error
8789 **/
8790int i40e_vsi_release(struct i40e_vsi *vsi)
8791{
8792 struct i40e_mac_filter *f, *ftmp;
8793 struct i40e_veb *veb = NULL;
8794 struct i40e_pf *pf;
8795 u16 uplink_seid;
8796 int i, n;
8797
8798 pf = vsi->back;
8799
8800 /* release of a VEB-owner or last VSI is not allowed */
8801 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8802 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8803 vsi->seid, vsi->uplink_seid);
8804 return -ENODEV;
8805 }
8806 if (vsi == pf->vsi[pf->lan_vsi] &&
8807 !test_bit(__I40E_DOWN, &pf->state)) {
8808 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8809 return -ENODEV;
8810 }
8811
8812 uplink_seid = vsi->uplink_seid;
8813 if (vsi->type != I40E_VSI_SRIOV) {
8814 if (vsi->netdev_registered) {
8815 vsi->netdev_registered = false;
8816 if (vsi->netdev) {
8817 /* results in a call to i40e_close() */
8818 unregister_netdev(vsi->netdev);
41c445ff
JB		 8819 }
8820 } else {
90ef8d47 8821 i40e_vsi_close(vsi);
41c445ff
JB		 8822 }
8823 i40e_vsi_disable_irq(vsi);
8824 }
8825
8826 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8827 i40e_del_filter(vsi, f->macaddr, f->vlan,
8828 f->is_vf, f->is_netdev);
30e2561b 8829 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 8830
8831 i40e_vsi_delete(vsi);
8832 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8833 if (vsi->netdev) {
8834 free_netdev(vsi->netdev);
8835 vsi->netdev = NULL;
8836 }
41c445ff
JB		 8837 i40e_vsi_clear_rings(vsi);
8838 i40e_vsi_clear(vsi);
8839
8840 /* If this was the last thing on the VEB, except for the
8841 * controlling VSI, remove the VEB, which puts the controlling
8842 * VSI onto the next level down in the switch.
8843 *
8844 * Well, okay, there's one more exception here: don't remove
8845 * the orphan VEBs yet. We'll wait for an explicit remove request
8846 * from up the network stack.
8847 */
505682cd 8848 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8849 if (pf->vsi[i] &&
8850 pf->vsi[i]->uplink_seid == uplink_seid &&
8851 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8852 n++; /* count the VSIs */
8853 }
8854 }
8855 for (i = 0; i < I40E_MAX_VEB; i++) {
8856 if (!pf->veb[i])
8857 continue;
8858 if (pf->veb[i]->uplink_seid == uplink_seid)
8859 n++; /* count the VEBs */
8860 if (pf->veb[i]->seid == uplink_seid)
8861 veb = pf->veb[i];
8862 }
8863 if (n == 0 && veb && veb->uplink_seid != 0)
8864 i40e_veb_release(veb);
8865
8866 return 0;
8867}
8868
8869/**
8870 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8871 * @vsi: ptr to the VSI
8872 *
8873 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8874 * corresponding SW VSI structure and initializes num_queue_pairs for the
8875 * newly allocated VSI.
8876 *
8877 * Returns 0 on success or negative on failure
8878 **/
8879static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8880{
8881 int ret = -ENOENT;
8882 struct i40e_pf *pf = vsi->back;
8883
493fb300 8884 if (vsi->q_vectors[0]) {
41c445ff
JB		 8885 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8886 vsi->seid);
8887 return -EEXIST;
8888 }
8889
8890 if (vsi->base_vector) {
f29eaa3d 8891 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8892 vsi->seid, vsi->base_vector);
8893 return -EEXIST;
8894 }
8895
90e04070 8896 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8897 if (ret) {
8898 dev_info(&pf->pdev->dev,
8899 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8900 vsi->num_q_vectors, vsi->seid, ret);
8901 vsi->num_q_vectors = 0;
8902 goto vector_setup_out;
8903 }
8904
26cdc443
ASJ		 8905 /* In Legacy mode, we do not have to get any other vector since we
8906 * piggyback on the misc/ICR0 for queue interrupts.
8907 */
8908 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
8909 return ret;
958a3e3b
SN		 8910 if (vsi->num_q_vectors)
8911 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8912 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8913 if (vsi->base_vector < 0) {
8914 dev_info(&pf->pdev->dev,
049a2be8
SN		 8915 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8916 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8917 i40e_vsi_free_q_vectors(vsi);
8918 ret = -ENOENT;
8919 goto vector_setup_out;
8920 }
8921
8922vector_setup_out:
8923 return ret;
8924}
8925
bc7d338f
ASJ		 8926/**
8927 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8928 * @vsi: pointer to the vsi.
8929 *
8930 * This re-allocates a vsi's queue resources.
8931 *
8932 * Returns pointer to the successfully allocated and configured VSI sw struct
8933 * on success, otherwise returns NULL on failure.
8934 **/
8935static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8936{
8937 struct i40e_pf *pf = vsi->back;
8938 u8 enabled_tc;
8939 int ret;
8940
8941 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8942 i40e_vsi_clear_rings(vsi);
8943
8944 i40e_vsi_free_arrays(vsi, false);
8945 i40e_set_num_rings_in_vsi(vsi);
8946 ret = i40e_vsi_alloc_arrays(vsi, false);
8947 if (ret)
8948 goto err_vsi;
8949
8950 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8951 if (ret < 0) {
049a2be8 8952 dev_info(&pf->pdev->dev,
f1c7e72e 8953 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8954 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8955 goto err_vsi;
8956 }
8957 vsi->base_queue = ret;
8958
8959 /* Update the FW view of the VSI. Force a reset of TC and queue
8960 * layout configurations.
8961 */
8962 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8963 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8964 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8965 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8966
8967 /* assign it some queues */
8968 ret = i40e_alloc_rings(vsi);
8969 if (ret)
8970 goto err_rings;
8971
8972 /* map all of the rings to the q_vectors */
8973 i40e_vsi_map_rings_to_vectors(vsi);
8974 return vsi;
8975
8976err_rings:
8977 i40e_vsi_free_q_vectors(vsi);
8978 if (vsi->netdev_registered) {
8979 vsi->netdev_registered = false;
8980 unregister_netdev(vsi->netdev);
8981 free_netdev(vsi->netdev);
8982 vsi->netdev = NULL;
8983 }
8984 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8985err_vsi:
8986 i40e_vsi_clear(vsi);
8987 return NULL;
8988}
8989
41c445ff
JB		 8990/**
8991 * i40e_vsi_setup - Set up a VSI by a given type
8992 * @pf: board private structure
8993 * @type: VSI type
8994 * @uplink_seid: the switch element to link to
8995 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8996 *
8997 * This allocates the sw VSI structure and its queue resources, then add a VSI
8998 * to the identified VEB.
8999 *
9000 * Returns pointer to the successfully allocated and configure VSI sw struct on
9001 * success, otherwise returns NULL on failure.
9002 **/
9003struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9004 u16 uplink_seid, u32 param1)
9005{
9006 struct i40e_vsi *vsi = NULL;
9007 struct i40e_veb *veb = NULL;
9008 int ret, i;
9009 int v_idx;
9010
9011 /* The requested uplink_seid must be either
9012 * - the PF's port seid
9013 * no VEB is needed because this is the PF
9014 * or this is a Flow Director special case VSI
9015 * - seid of an existing VEB
9016 * - seid of a VSI that owns an existing VEB
9017 * - seid of a VSI that doesn't own a VEB
9018 * a new VEB is created and the VSI becomes the owner
9019 * - seid of the PF VSI, which is what creates the first VEB
9020 * this is a special case of the previous
9021 *
9022 * Find which uplink_seid we were given and create a new VEB if needed
9023 */
9024 for (i = 0; i < I40E_MAX_VEB; i++) {
9025 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9026 veb = pf->veb[i];
9027 break;
9028 }
9029 }
9030
9031 if (!veb && uplink_seid != pf->mac_seid) {
9032
505682cd 9033 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9034 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9035 vsi = pf->vsi[i];
9036 break;
9037 }
9038 }
9039 if (!vsi) {
9040 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9041 uplink_seid);
9042 return NULL;
9043 }
9044
9045 if (vsi->uplink_seid == pf->mac_seid)
9046 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9047 vsi->tc_config.enabled_tc);
9048 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9049 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9050 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9051 if (veb) {
9052 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9053 dev_info(&vsi->back->pdev->dev,
fb43201f 9054 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9055 return NULL;
9056 }
fa11cb3d
ASJ		 9057 /* We come up by default in VEPA mode if SRIOV is not
9058 * already enabled, in which case we can't force VEPA
9059 * mode.
9060 */
9061 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9062 veb->bridge_mode = BRIDGE_MODE_VEPA;
9063 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9064 }
51616018 9065 i40e_config_bridge_mode(veb);
79c21a82 9066 }
41c445ff
JB		 9067 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9068 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9069 veb = pf->veb[i];
9070 }
9071 if (!veb) {
9072 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9073 return NULL;
9074 }
9075
9076 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9077 uplink_seid = veb->seid;
9078 }
9079
9080 /* get vsi sw struct */
9081 v_idx = i40e_vsi_mem_alloc(pf, type);
9082 if (v_idx < 0)
9083 goto err_alloc;
9084 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9085 if (!vsi)
9086 goto err_alloc;
41c445ff
JB		 9087 vsi->type = type;
9088 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9089
9090 if (type == I40E_VSI_MAIN)
9091 pf->lan_vsi = v_idx;
9092 else if (type == I40E_VSI_SRIOV)
9093 vsi->vf_id = param1;
9094 /* assign it some queues */
cbf61325
ASJ		 9095 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9096 vsi->idx);
41c445ff 9097 if (ret < 0) {
049a2be8
SN		 9098 dev_info(&pf->pdev->dev,
9099 "failed to get tracking for %d queues for VSI %d err=%d\n",
9100 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9101 goto err_vsi;
9102 }
9103 vsi->base_queue = ret;
9104
9105 /* get a VSI from the hardware */
9106 vsi->uplink_seid = uplink_seid;
9107 ret = i40e_add_vsi(vsi);
9108 if (ret)
9109 goto err_vsi;
9110
9111 switch (vsi->type) {
9112 /* setup the netdev if needed */
9113 case I40E_VSI_MAIN:
9114 case I40E_VSI_VMDQ2:
38e00438 9115 case I40E_VSI_FCOE:
41c445ff
JB		 9116 ret = i40e_config_netdev(vsi);
9117 if (ret)
9118 goto err_netdev;
9119 ret = register_netdev(vsi->netdev);
9120 if (ret)
9121 goto err_netdev;
9122 vsi->netdev_registered = true;
9123 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9124#ifdef CONFIG_I40E_DCB
9125 /* Setup DCB netlink interface */
9126 i40e_dcbnl_setup(vsi);
9127#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9128 /* fall through */
9129
9130 case I40E_VSI_FDIR:
9131 /* set up vectors and rings if needed */
9132 ret = i40e_vsi_setup_vectors(vsi);
9133 if (ret)
9134 goto err_msix;
9135
9136 ret = i40e_alloc_rings(vsi);
9137 if (ret)
9138 goto err_rings;
9139
9140 /* map all of the rings to the q_vectors */
9141 i40e_vsi_map_rings_to_vectors(vsi);
9142
9143 i40e_vsi_reset_stats(vsi);
9144 break;
9145
9146 default:
9147 /* no netdev or rings for the other VSI types */
9148 break;
9149 }
9150
e25d00b8
ASJ		 9151 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9152 (vsi->type == I40E_VSI_VMDQ2)) {
9153 ret = i40e_vsi_config_rss(vsi);
9154 }
41c445ff
JB		 9155 return vsi;
9156
9157err_rings:
9158 i40e_vsi_free_q_vectors(vsi);
9159err_msix:
9160 if (vsi->netdev_registered) {
9161 vsi->netdev_registered = false;
9162 unregister_netdev(vsi->netdev);
9163 free_netdev(vsi->netdev);
9164 vsi->netdev = NULL;
9165 }
9166err_netdev:
9167 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9168err_vsi:
9169 i40e_vsi_clear(vsi);
9170err_alloc:
9171 return NULL;
9172}
9173
9174/**
9175 * i40e_veb_get_bw_info - Query VEB BW information
9176 * @veb: the veb to query
9177 *
9178 * Query the Tx scheduler BW configuration data for given VEB
9179 **/
9180static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9181{
9182 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9183 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9184 struct i40e_pf *pf = veb->pf;
9185 struct i40e_hw *hw = &pf->hw;
9186 u32 tc_bw_max;
9187 int ret = 0;
9188 int i;
9189
9190 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9191 &bw_data, NULL);
9192 if (ret) {
9193 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9194 "query veb bw config failed, err %s aq_err %s\n",
9195 i40e_stat_str(&pf->hw, ret),
9196 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9197 goto out;
9198 }
9199
9200 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9201 &ets_data, NULL);
9202 if (ret) {
9203 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9204 "query veb bw ets config failed, err %s aq_err %s\n",
9205 i40e_stat_str(&pf->hw, ret),
9206 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9207 goto out;
9208 }
9209
9210 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9211 veb->bw_max_quanta = ets_data.tc_bw_max;
9212 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9213 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9214 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9215 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9216 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9217 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9218 veb->bw_tc_limit_credits[i] =
9219 le16_to_cpu(bw_data.tc_bw_limits[i]);
9220 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9221 }
9222
9223out:
9224 return ret;
9225}
9226
9227/**
9228 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9229 * @pf: board private structure
9230 *
9231 * On error: returns error code (negative)
9232 * On success: returns vsi index in PF (positive)
9233 **/
9234static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9235{
9236 int ret = -ENOENT;
9237 struct i40e_veb *veb;
9238 int i;
9239
9240 /* Need to protect the allocation of switch elements at the PF level */
9241 mutex_lock(&pf->switch_mutex);
9242
9243 /* VEB list may be fragmented if VEB creation/destruction has
9244 * been happening. We can afford to do a quick scan to look
9245 * for any free slots in the list.
9246 *
9247 * find next empty veb slot, looping back around if necessary
9248 */
9249 i = 0;
9250 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9251 i++;
9252 if (i >= I40E_MAX_VEB) {
9253 ret = -ENOMEM;
9254 goto err_alloc_veb; /* out of VEB slots! */
9255 }
9256
9257 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9258 if (!veb) {
9259 ret = -ENOMEM;
9260 goto err_alloc_veb;
9261 }
9262 veb->pf = pf;
9263 veb->idx = i;
9264 veb->enabled_tc = 1;
9265
9266 pf->veb[i] = veb;
9267 ret = i;
9268err_alloc_veb:
9269 mutex_unlock(&pf->switch_mutex);
9270 return ret;
9271}
9272
9273/**
9274 * i40e_switch_branch_release - Delete a branch of the switch tree
9275 * @branch: where to start deleting
9276 *
9277 * This uses recursion to find the tips of the branch to be
9278 * removed, deleting until we get back to and can delete this VEB.
9279 **/
9280static void i40e_switch_branch_release(struct i40e_veb *branch)
9281{
9282 struct i40e_pf *pf = branch->pf;
9283 u16 branch_seid = branch->seid;
9284 u16 veb_idx = branch->idx;
9285 int i;
9286
9287 /* release any VEBs on this VEB - RECURSION */
9288 for (i = 0; i < I40E_MAX_VEB; i++) {
9289 if (!pf->veb[i])
9290 continue;
9291 if (pf->veb[i]->uplink_seid == branch->seid)
9292 i40e_switch_branch_release(pf->veb[i]);
9293 }
9294
9295 /* Release the VSIs on this VEB, but not the owner VSI.
9296 *
9297 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9298 * the VEB itself, so don't use (*branch) after this loop.
9299 */
505682cd 9300 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9301 if (!pf->vsi[i])
9302 continue;
9303 if (pf->vsi[i]->uplink_seid == branch_seid &&
9304 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9305 i40e_vsi_release(pf->vsi[i]);
9306 }
9307 }
9308
9309 /* There's one corner case where the VEB might not have been
9310 * removed, so double check it here and remove it if needed.
9311 * This case happens if the veb was created from the debugfs
9312 * commands and no VSIs were added to it.
9313 */
9314 if (pf->veb[veb_idx])
9315 i40e_veb_release(pf->veb[veb_idx]);
9316}
9317
9318/**
9319 * i40e_veb_clear - remove veb struct
9320 * @veb: the veb to remove
9321 **/
9322static void i40e_veb_clear(struct i40e_veb *veb)
9323{
9324 if (!veb)
9325 return;
9326
9327 if (veb->pf) {
9328 struct i40e_pf *pf = veb->pf;
9329
9330 mutex_lock(&pf->switch_mutex);
9331 if (pf->veb[veb->idx] == veb)
9332 pf->veb[veb->idx] = NULL;
9333 mutex_unlock(&pf->switch_mutex);
9334 }
9335
9336 kfree(veb);
9337}
9338
9339/**
9340 * i40e_veb_release - Delete a VEB and free its resources
9341 * @veb: the VEB being removed
9342 **/
9343void i40e_veb_release(struct i40e_veb *veb)
9344{
9345 struct i40e_vsi *vsi = NULL;
9346 struct i40e_pf *pf;
9347 int i, n = 0;
9348
9349 pf = veb->pf;
9350
9351 /* find the remaining VSI and check for extras */
505682cd 9352 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9353 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9354 n++;
9355 vsi = pf->vsi[i];
9356 }
9357 }
9358 if (n != 1) {
9359 dev_info(&pf->pdev->dev,
9360 "can't remove VEB %d with %d VSIs left\n",
9361 veb->seid, n);
9362 return;
9363 }
9364
9365 /* move the remaining VSI to uplink veb */
9366 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9367 if (veb->uplink_seid) {
9368 vsi->uplink_seid = veb->uplink_seid;
9369 if (veb->uplink_seid == pf->mac_seid)
9370 vsi->veb_idx = I40E_NO_VEB;
9371 else
9372 vsi->veb_idx = veb->veb_idx;
9373 } else {
9374 /* floating VEB */
9375 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9376 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9377 }
9378
9379 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9380 i40e_veb_clear(veb);
41c445ff
JB		 9381}
9382
9383/**
9384 * i40e_add_veb - create the VEB in the switch
9385 * @veb: the VEB to be instantiated
9386 * @vsi: the controlling VSI
9387 **/
9388static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9389{
f1c7e72e 9390 struct i40e_pf *pf = veb->pf;
92faef85 9391 bool is_default = veb->pf->cur_promisc;
e1c51b95 9392 bool is_cloud = false;
41c445ff
JB		 9393 int ret;
9394
9395 /* get a VEB from the hardware */
f1c7e72e 9396 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9397 veb->enabled_tc, is_default,
9398 is_cloud, &veb->seid, NULL);
41c445ff 9399 if (ret) {
f1c7e72e
SN		 9400 dev_info(&pf->pdev->dev,
9401 "couldn't add VEB, err %s aq_err %s\n",
9402 i40e_stat_str(&pf->hw, ret),
9403 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9404 return -EPERM;
9405 }
9406
9407 /* get statistics counter */
f1c7e72e 9408 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9409 &veb->stats_idx, NULL, NULL, NULL);
9410 if (ret) {
f1c7e72e
SN		 9411 dev_info(&pf->pdev->dev,
9412 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9413 i40e_stat_str(&pf->hw, ret),
9414 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9415 return -EPERM;
9416 }
9417 ret = i40e_veb_get_bw_info(veb);
9418 if (ret) {
f1c7e72e
SN		 9419 dev_info(&pf->pdev->dev,
9420 "couldn't get VEB bw info, err %s aq_err %s\n",
9421 i40e_stat_str(&pf->hw, ret),
9422 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9423 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9424 return -ENOENT;
9425 }
9426
9427 vsi->uplink_seid = veb->seid;
9428 vsi->veb_idx = veb->idx;
9429 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9430
9431 return 0;
9432}
9433
9434/**
9435 * i40e_veb_setup - Set up a VEB
9436 * @pf: board private structure
9437 * @flags: VEB setup flags
9438 * @uplink_seid: the switch element to link to
9439 * @vsi_seid: the initial VSI seid
9440 * @enabled_tc: Enabled TC bit-map
9441 *
9442 * This allocates the sw VEB structure and links it into the switch
9443 * It is possible and legal for this to be a duplicate of an already
9444 * existing VEB. It is also possible for both uplink and vsi seids
9445 * to be zero, in order to create a floating VEB.
9446 *
9447 * Returns pointer to the successfully allocated VEB sw struct on
9448 * success, otherwise returns NULL on failure.
9449 **/
9450struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9451 u16 uplink_seid, u16 vsi_seid,
9452 u8 enabled_tc)
9453{
9454 struct i40e_veb *veb, *uplink_veb = NULL;
9455 int vsi_idx, veb_idx;
9456 int ret;
9457
9458 /* if one seid is 0, the other must be 0 to create a floating relay */
9459 if ((uplink_seid == 0 || vsi_seid == 0) &&
9460 (uplink_seid + vsi_seid != 0)) {
9461 dev_info(&pf->pdev->dev,
9462 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9463 uplink_seid, vsi_seid);
9464 return NULL;
9465 }
9466
9467 /* make sure there is such a vsi and uplink */
505682cd 9468 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9469 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9470 break;
505682cd 9471 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9472 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9473 vsi_seid);
9474 return NULL;
9475 }
9476
9477 if (uplink_seid && uplink_seid != pf->mac_seid) {
9478 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9479 if (pf->veb[veb_idx] &&
9480 pf->veb[veb_idx]->seid == uplink_seid) {
9481 uplink_veb = pf->veb[veb_idx];
9482 break;
9483 }
9484 }
9485 if (!uplink_veb) {
9486 dev_info(&pf->pdev->dev,
9487 "uplink seid %d not found\n", uplink_seid);
9488 return NULL;
9489 }
9490 }
9491
9492 /* get veb sw struct */
9493 veb_idx = i40e_veb_mem_alloc(pf);
9494 if (veb_idx < 0)
9495 goto err_alloc;
9496 veb = pf->veb[veb_idx];
9497 veb->flags = flags;
9498 veb->uplink_seid = uplink_seid;
9499 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9500 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9501
9502 /* create the VEB in the switch */
9503 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9504 if (ret)
9505 goto err_veb;
1bb8b935
SN		 9506 if (vsi_idx == pf->lan_vsi)
9507 pf->lan_veb = veb->idx;
41c445ff
JB		 9508
9509 return veb;
9510
9511err_veb:
9512 i40e_veb_clear(veb);
9513err_alloc:
9514 return NULL;
9515}
9516
9517/**
b40c82e6 9518 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9519 * @pf: board private structure
9520 * @ele: element we are building info from
9521 * @num_reported: total number of elements
9522 * @printconfig: should we print the contents
9523 *
9524 * helper function to assist in extracting a few useful SEID values.
9525 **/
9526static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9527 struct i40e_aqc_switch_config_element_resp *ele,
9528 u16 num_reported, bool printconfig)
9529{
9530 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9531 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9532 u8 element_type = ele->element_type;
9533 u16 seid = le16_to_cpu(ele->seid);
9534
9535 if (printconfig)
9536 dev_info(&pf->pdev->dev,
9537 "type=%d seid=%d uplink=%d downlink=%d\n",
9538 element_type, seid, uplink_seid, downlink_seid);
9539
9540 switch (element_type) {
9541 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9542 pf->mac_seid = seid;
9543 break;
9544 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9545 /* Main VEB? */
9546 if (uplink_seid != pf->mac_seid)
9547 break;
9548 if (pf->lan_veb == I40E_NO_VEB) {
9549 int v;
9550
9551 /* find existing or else empty VEB */
9552 for (v = 0; v < I40E_MAX_VEB; v++) {
9553 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9554 pf->lan_veb = v;
9555 break;
9556 }
9557 }
9558 if (pf->lan_veb == I40E_NO_VEB) {
9559 v = i40e_veb_mem_alloc(pf);
9560 if (v < 0)
9561 break;
9562 pf->lan_veb = v;
9563 }
9564 }
9565
9566 pf->veb[pf->lan_veb]->seid = seid;
9567 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9568 pf->veb[pf->lan_veb]->pf = pf;
9569 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9570 break;
9571 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9572 if (num_reported != 1)
9573 break;
9574 /* This is immediately after a reset so we can assume this is
9575 * the PF's VSI
9576 */
9577 pf->mac_seid = uplink_seid;
9578 pf->pf_seid = downlink_seid;
9579 pf->main_vsi_seid = seid;
9580 if (printconfig)
9581 dev_info(&pf->pdev->dev,
9582 "pf_seid=%d main_vsi_seid=%d\n",
9583 pf->pf_seid, pf->main_vsi_seid);
9584 break;
9585 case I40E_SWITCH_ELEMENT_TYPE_PF:
9586 case I40E_SWITCH_ELEMENT_TYPE_VF:
9587 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9588 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9589 case I40E_SWITCH_ELEMENT_TYPE_PE:
9590 case I40E_SWITCH_ELEMENT_TYPE_PA:
9591 /* ignore these for now */
9592 break;
9593 default:
9594 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9595 element_type, seid);
9596 break;
9597 }
9598}
9599
9600/**
9601 * i40e_fetch_switch_configuration - Get switch config from firmware
9602 * @pf: board private structure
9603 * @printconfig: should we print the contents
9604 *
9605 * Get the current switch configuration from the device and
9606 * extract a few useful SEID values.
9607 **/
9608int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9609{
9610 struct i40e_aqc_get_switch_config_resp *sw_config;
9611 u16 next_seid = 0;
9612 int ret = 0;
9613 u8 *aq_buf;
9614 int i;
9615
9616 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9617 if (!aq_buf)
9618 return -ENOMEM;
9619
9620 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9621 do {
9622 u16 num_reported, num_total;
9623
9624 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9625 I40E_AQ_LARGE_BUF,
9626 &next_seid, NULL);
9627 if (ret) {
9628 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9629 "get switch config failed err %s aq_err %s\n",
9630 i40e_stat_str(&pf->hw, ret),
9631 i40e_aq_str(&pf->hw,
9632 pf->hw.aq.asq_last_status));
41c445ff
JB		 9633 kfree(aq_buf);
9634 return -ENOENT;
9635 }
9636
9637 num_reported = le16_to_cpu(sw_config->header.num_reported);
9638 num_total = le16_to_cpu(sw_config->header.num_total);
9639
9640 if (printconfig)
9641 dev_info(&pf->pdev->dev,
9642 "header: %d reported %d total\n",
9643 num_reported, num_total);
9644
41c445ff
JB		 9645 for (i = 0; i < num_reported; i++) {
9646 struct i40e_aqc_switch_config_element_resp *ele =
9647 &sw_config->element[i];
9648
9649 i40e_setup_pf_switch_element(pf, ele, num_reported,
9650 printconfig);
9651 }
9652 } while (next_seid != 0);
9653
9654 kfree(aq_buf);
9655 return ret;
9656}
9657
9658/**
9659 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9660 * @pf: board private structure
bc7d338f 9661 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9662 *
9663 * Returns 0 on success, negative value on failure
9664 **/
bc7d338f 9665static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9666{
9667 int ret;
9668
9669 /* find out what's out there already */
9670 ret = i40e_fetch_switch_configuration(pf, false);
9671 if (ret) {
9672 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9673 "couldn't fetch switch config, err %s aq_err %s\n",
9674 i40e_stat_str(&pf->hw, ret),
9675 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9676 return ret;
9677 }
9678 i40e_pf_reset_stats(pf);
9679
41c445ff 9680 /* first time setup */
bc7d338f 9681 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9682 struct i40e_vsi *vsi = NULL;
9683 u16 uplink_seid;
9684
9685 /* Set up the PF VSI associated with the PF's main VSI
9686 * that is already in the HW switch
9687 */
9688 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9689 uplink_seid = pf->veb[pf->lan_veb]->seid;
9690 else
9691 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9692 if (pf->lan_vsi == I40E_NO_VSI)
9693 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9694 else if (reinit)
9695 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9696 if (!vsi) {
9697 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9698 i40e_fdir_teardown(pf);
9699 return -EAGAIN;
9700 }
41c445ff
JB		 9701 } else {
9702 /* force a reset of TC and queue layout configurations */
9703 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 9704
41c445ff
JB		 9705 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9706 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9707 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9708 }
9709 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9710
cbf61325
ASJ		 9711 i40e_fdir_sb_setup(pf);
9712
41c445ff
JB		 9713 /* Setup static PF queue filter control settings */
9714 ret = i40e_setup_pf_filter_control(pf);
9715 if (ret) {
9716 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9717 ret);
9718 /* Failure here should not stop continuing other steps */
9719 }
9720
9721 /* enable RSS in the HW, even for only one queue, as the stack can use
9722 * the hash
9723 */
9724 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9725 i40e_config_rss(pf);
9726
9727 /* fill in link information and enable LSE reporting */
21af70fb 9728 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9729 i40e_link_event(pf);
9730
d52c20b7 9731 /* Initialize user-specific link properties */
41c445ff
JB		 9732 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9733 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9734
beb0dff1
JK		 9735 i40e_ptp_init(pf);
9736
41c445ff
JB		 9737 return ret;
9738}
9739
41c445ff
JB		 9740/**
9741 * i40e_determine_queue_usage - Work out queue distribution
9742 * @pf: board private structure
9743 **/
9744static void i40e_determine_queue_usage(struct i40e_pf *pf)
9745{
41c445ff
JB		 9746 int queues_left;
9747
9748 pf->num_lan_qps = 0;
38e00438
VD		 9749#ifdef I40E_FCOE
9750 pf->num_fcoe_qps = 0;
9751#endif
41c445ff
JB		 9752
9753 /* Find the max queues to be put into basic use. We'll always be
9754 * using TC0, whether or not DCB is running, and TC0 will get the
9755 * big RSS set.
9756 */
9757 queues_left = pf->hw.func_caps.num_tx_qp;
9758
cbf61325 9759 if ((queues_left == 1) ||
9aa7e935 9760 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9761 /* one qp for PF, no queues for anything else */
9762 queues_left = 0;
9763 pf->rss_size = pf->num_lan_qps = 1;
9764
9765 /* make sure all the fancies are disabled */
60ea5f83 9766 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9767#ifdef I40E_FCOE
9768 I40E_FLAG_FCOE_ENABLED |
9769#endif
60ea5f83
JB		 9770 I40E_FLAG_FD_SB_ENABLED |
9771 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9772 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9773 I40E_FLAG_SRIOV_ENABLED |
9774 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9775 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9776 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9777 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9778 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9779 /* one qp for PF */
9780 pf->rss_size = pf->num_lan_qps = 1;
9781 queues_left -= pf->num_lan_qps;
9782
9783 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9784#ifdef I40E_FCOE
9785 I40E_FLAG_FCOE_ENABLED |
9786#endif
9aa7e935
FZ		 9787 I40E_FLAG_FD_SB_ENABLED |
9788 I40E_FLAG_FD_ATR_ENABLED |
9789 I40E_FLAG_DCB_ENABLED |
9790 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9791 } else {
cbf61325 9792 /* Not enough queues for all TCs */
4d9b6043 9793 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9794 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9795 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9796 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9797 }
9a3bd2f1
ASJ		 9798 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9799 num_online_cpus());
9800 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9801 pf->hw.func_caps.num_tx_qp);
9802
cbf61325
ASJ		 9803 queues_left -= pf->num_lan_qps;
9804 }
9805
38e00438
VD		 9806#ifdef I40E_FCOE
9807 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9808 if (I40E_DEFAULT_FCOE <= queues_left) {
9809 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9810 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9811 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9812 } else {
9813 pf->num_fcoe_qps = 0;
9814 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9815 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9816 }
9817
9818 queues_left -= pf->num_fcoe_qps;
9819 }
9820
9821#endif
cbf61325
ASJ		 9822 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9823 if (queues_left > 1) {
9824 queues_left -= 1; /* save 1 queue for FD */
9825 } else {
9826 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9827 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9828 }
41c445ff
JB		 9829 }
9830
9831 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9832 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9833 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9834 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9835 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9836 }
9837
9838 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9839 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9840 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9841 (queues_left / pf->num_vmdq_qps));
9842 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9843 }
9844
f8ff1464 9845 pf->queues_left = queues_left;
38e00438
VD		 9846#ifdef I40E_FCOE
9847 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9848#endif
41c445ff
JB		 9849}
9850
9851/**
9852 * i40e_setup_pf_filter_control - Setup PF static filter control
9853 * @pf: PF to be setup
9854 *
b40c82e6 9855 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9856 * settings. If PE/FCoE are enabled then it will also set the per PF
9857 * based filter sizes required for them. It also enables Flow director,
9858 * ethertype and macvlan type filter settings for the pf.
9859 *
9860 * Returns 0 on success, negative on failure
9861 **/
9862static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9863{
9864 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9865
9866 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9867
9868 /* Flow Director is enabled */
60ea5f83 9869 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9870 settings->enable_fdir = true;
9871
9872 /* Ethtype and MACVLAN filters enabled for PF */
9873 settings->enable_ethtype = true;
9874 settings->enable_macvlan = true;
9875
9876 if (i40e_set_filter_control(&pf->hw, settings))
9877 return -ENOENT;
9878
9879 return 0;
9880}
9881
0c22b3dd
JB		 9882#define INFO_STRING_LEN 255
9883static void i40e_print_features(struct i40e_pf *pf)
9884{
9885 struct i40e_hw *hw = &pf->hw;
9886 char *buf, *string;
9887
9888 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9889 if (!string) {
9890 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9891 return;
9892 }
9893
9894 buf = string;
9895
9896 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9897#ifdef CONFIG_PCI_IOV
9898 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9899#endif
aba237d1
MW		 9900 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9901 pf->hw.func_caps.num_vsis,
9902 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9903 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9904
9905 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9906 buf += sprintf(buf, "RSS ");
0c22b3dd 9907 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9908 buf += sprintf(buf, "FD_ATR ");
9909 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9910 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9911 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9912 }
4d9b6043 9913 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9914 buf += sprintf(buf, "DCB ");
9915 if (pf->flags & I40E_FLAG_PTP)
9916 buf += sprintf(buf, "PTP ");
38e00438
VD		 9917#ifdef I40E_FCOE
9918 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9919 buf += sprintf(buf, "FCOE ");
9920#endif
0c22b3dd
JB		 9921
9922 BUG_ON(buf > (string + INFO_STRING_LEN));
9923 dev_info(&pf->pdev->dev, "%s\n", string);
9924 kfree(string);
9925}
9926
41c445ff
JB		 9927/**
9928 * i40e_probe - Device initialization routine
9929 * @pdev: PCI device information struct
9930 * @ent: entry in i40e_pci_tbl
9931 *
b40c82e6
JK		 9932 * i40e_probe initializes a PF identified by a pci_dev structure.
9933 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9934 * and a hardware reset occur.
9935 *
9936 * Returns 0 on success, negative on failure
9937 **/
9938static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9939{
e827845c 9940 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9941 struct i40e_pf *pf;
9942 struct i40e_hw *hw;
93cd765b 9943 static u16 pfs_found;
1d5109d1 9944 u16 wol_nvm_bits;
d4dfb81a 9945 u16 link_status;
41c445ff
JB		 9946 int err = 0;
9947 u32 len;
8a9eb7d3 9948 u32 i;
41c445ff
JB		 9949
9950 err = pci_enable_device_mem(pdev);
9951 if (err)
9952 return err;
9953
9954 /* set up for high or low dma */
6494294f 9955 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9956 if (err) {
e3e3bfdd
JS		 9957 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9958 if (err) {
9959 dev_err(&pdev->dev,
9960 "DMA configuration failed: 0x%x\n", err);
9961 goto err_dma;
9962 }
41c445ff
JB		 9963 }
9964
9965 /* set up pci connections */
9966 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9967 IORESOURCE_MEM), i40e_driver_name);
9968 if (err) {
9969 dev_info(&pdev->dev,
9970 "pci_request_selected_regions failed %d\n", err);
9971 goto err_pci_reg;
9972 }
9973
9974 pci_enable_pcie_error_reporting(pdev);
9975 pci_set_master(pdev);
9976
9977 /* Now that we have a PCI connection, we need to do the
9978 * low level device setup. This is primarily setting up
9979 * the Admin Queue structures and then querying for the
9980 * device's current profile information.
9981 */
9982 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9983 if (!pf) {
9984 err = -ENOMEM;
9985 goto err_pf_alloc;
9986 }
9987 pf->next_vsi = 0;
9988 pf->pdev = pdev;
9989 set_bit(__I40E_DOWN, &pf->state);
9990
9991 hw = &pf->hw;
9992 hw->back = pf;
232f4706 9993
2ac8b675
SN		 9994 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
9995 I40E_MAX_CSR_SPACE);
232f4706 9996
2ac8b675 9997 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 9998 if (!hw->hw_addr) {
9999 err = -EIO;
10000 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10001 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10002 pf->ioremap_len, err);
41c445ff
JB		 10003 goto err_ioremap;
10004 }
10005 hw->vendor_id = pdev->vendor;
10006 hw->device_id = pdev->device;
10007 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10008 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10009 hw->subsystem_device_id = pdev->subsystem_device;
10010 hw->bus.device = PCI_SLOT(pdev->devfn);
10011 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10012 pf->instance = pfs_found;
41c445ff 10013
5b5faa43
SN		 10014 if (debug != -1) {
10015 pf->msg_enable = pf->hw.debug_mask;
10016 pf->msg_enable = debug;
10017 }
10018
7134f9ce
JB		 10019 /* do a special CORER for clearing PXE mode once at init */
10020 if (hw->revision_id == 0 &&
10021 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10022 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10023 i40e_flush(hw);
10024 msleep(200);
10025 pf->corer_count++;
10026
10027 i40e_clear_pxe_mode(hw);
10028 }
10029
41c445ff 10030 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10031 i40e_clear_hw(hw);
41c445ff
JB		 10032 err = i40e_pf_reset(hw);
10033 if (err) {
10034 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10035 goto err_pf_reset;
10036 }
10037 pf->pfr_count++;
10038
10039 hw->aq.num_arq_entries = I40E_AQ_LEN;
10040 hw->aq.num_asq_entries = I40E_AQ_LEN;
10041 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10042 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10043 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10044
b294ac70 10045 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10046 "%s-%s:misc",
10047 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10048
10049 err = i40e_init_shared_code(hw);
10050 if (err) {
b2a75c58
ASJ		 10051 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10052 err);
41c445ff
JB		 10053 goto err_pf_reset;
10054 }
10055
d52c20b7
JB		 10056 /* set up a default setting for link flow control */
10057 pf->hw.fc.requested_mode = I40E_FC_NONE;
10058
41c445ff
JB		 10059 err = i40e_init_adminq(hw);
10060 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
10061 if (err) {
10062 dev_info(&pdev->dev,
7aa67613 10063 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10064 goto err_pf_reset;
10065 }
10066
7aa67613
CS		 10067 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10068 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10069 dev_info(&pdev->dev,
7aa67613
CS		 10070 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10071 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10072 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10073 dev_info(&pdev->dev,
7aa67613 10074 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10075
4eb3f768
SN		 10076 i40e_verify_eeprom(pf);
10077
2c5fe33b
JB		 10078 /* Rev 0 hardware was never productized */
10079 if (hw->revision_id < 1)
10080 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10081
6ff4ef86 10082 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10083 err = i40e_get_capabilities(pf);
10084 if (err)
10085 goto err_adminq_setup;
10086
10087 err = i40e_sw_init(pf);
10088 if (err) {
10089 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10090 goto err_sw_init;
10091 }
10092
10093 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10094 hw->func_caps.num_rx_qp,
10095 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10096 if (err) {
10097 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10098 goto err_init_lan_hmc;
10099 }
10100
10101 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10102 if (err) {
10103 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10104 err = -ENOENT;
10105 goto err_configure_lan_hmc;
10106 }
10107
b686ece5
NP		 10108 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10109 * Ignore error return codes because if it was already disabled via
10110 * hardware settings this will fail
10111 */
10112 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10113 (pf->hw.aq.fw_maj_ver < 4)) {
10114 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10115 i40e_aq_stop_lldp(hw, true, NULL);
10116 }
10117
41c445ff 10118 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10119 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10120 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10121 err = -EIO;
10122 goto err_mac_addr;
10123 }
10124 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10125 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10126 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10127 if (is_valid_ether_addr(hw->mac.port_addr))
10128 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10129#ifdef I40E_FCOE
10130 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10131 if (err)
10132 dev_info(&pdev->dev,
10133 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10134 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10135 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10136 hw->mac.san_addr);
10137 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10138 }
10139 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10140#endif /* I40E_FCOE */
41c445ff
JB		 10141
10142 pci_set_drvdata(pdev, pf);
10143 pci_save_state(pdev);
4e3b35b0
NP		 10144#ifdef CONFIG_I40E_DCB
10145 err = i40e_init_pf_dcb(pf);
10146 if (err) {
aebfc816 10147 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10148 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10149 /* Continue without DCB enabled */
4e3b35b0
NP		 10150 }
10151#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10152
10153 /* set up periodic task facility */
10154 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10155 pf->service_timer_period = HZ;
10156
10157 INIT_WORK(&pf->service_task, i40e_service_task);
10158 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10159 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10160
1d5109d1
SN		 10161 /* NVM bit on means WoL disabled for the port */
10162 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10163 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10164 pf->wol_en = false;
10165 else
10166 pf->wol_en = true;
8e2773ae
SN		 10167 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10168
41c445ff
JB		 10169 /* set up the main switch operations */
10170 i40e_determine_queue_usage(pf);
c1147280
JB		 10171 err = i40e_init_interrupt_scheme(pf);
10172 if (err)
10173 goto err_switch_setup;
41c445ff 10174
505682cd
MW		 10175 /* The number of VSIs reported by the FW is the minimum guaranteed
10176 * to us; HW supports far more and we share the remaining pool with
10177 * the other PFs. We allocate space for more than the guarantee with
10178 * the understanding that we might not get them all later.
41c445ff 10179 */
505682cd
MW		 10180 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10181 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10182 else
10183 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10184
10185 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10186 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10187 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10188 if (!pf->vsi) {
10189 err = -ENOMEM;
41c445ff 10190 goto err_switch_setup;
ed87ac09 10191 }
41c445ff 10192
fa11cb3d
ASJ		 10193#ifdef CONFIG_PCI_IOV
10194 /* prep for VF support */
10195 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10196 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10197 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10198 if (pci_num_vf(pdev))
10199 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10200 }
10201#endif
bc7d338f 10202 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10203 if (err) {
10204 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10205 goto err_vsis;
10206 }
8a9eb7d3 10207 /* if FDIR VSI was set up, start it now */
505682cd 10208 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10209 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10210 i40e_vsi_open(pf->vsi[i]);
10211 break;
10212 }
10213 }
41c445ff 10214
7e2453fe
JB		 10215 /* driver is only interested in link up/down and module qualification
10216 * reports from firmware
10217 */
10218 err = i40e_aq_set_phy_int_mask(&pf->hw,
10219 I40E_AQ_EVENT_LINK_UPDOWN |
10220 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10221 if (err)
f1c7e72e
SN		 10222 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10223 i40e_stat_str(&pf->hw, err),
10224 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10225
025b4a54
ASJ		 10226 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10227 (pf->hw.aq.fw_maj_ver < 4)) {
10228 msleep(75);
10229 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10230 if (err)
f1c7e72e
SN		 10231 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10232 i40e_stat_str(&pf->hw, err),
10233 i40e_aq_str(&pf->hw,
10234 pf->hw.aq.asq_last_status));
cafa2ee6 10235 }
41c445ff
JB		 10236 /* The main driver is (mostly) up and happy. We need to set this state
10237 * before setting up the misc vector or we get a race and the vector
10238 * ends up disabled forever.
10239 */
10240 clear_bit(__I40E_DOWN, &pf->state);
10241
10242 /* In case of MSIX we are going to setup the misc vector right here
10243 * to handle admin queue events etc. In case of legacy and MSI
10244 * the misc functionality and queue processing is combined in
10245 * the same vector and that gets setup at open.
10246 */
10247 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10248 err = i40e_setup_misc_vector(pf);
10249 if (err) {
10250 dev_info(&pdev->dev,
10251 "setup of misc vector failed: %d\n", err);
10252 goto err_vsis;
10253 }
10254 }
10255
df805f62 10256#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10257 /* prep for VF support */
10258 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10259 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10260 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10261 u32 val;
10262
10263 /* disable link interrupts for VFs */
10264 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10265 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10266 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10267 i40e_flush(hw);
4aeec010
MW		 10268
10269 if (pci_num_vf(pdev)) {
10270 dev_info(&pdev->dev,
10271 "Active VFs found, allocating resources.\n");
10272 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10273 if (err)
10274 dev_info(&pdev->dev,
10275 "Error %d allocating resources for existing VFs\n",
10276 err);
10277 }
41c445ff 10278 }
df805f62 10279#endif /* CONFIG_PCI_IOV */
41c445ff 10280
93cd765b
ASJ		 10281 pfs_found++;
10282
41c445ff
JB		 10283 i40e_dbg_pf_init(pf);
10284
10285 /* tell the firmware that we're starting */
44033fac 10286 i40e_send_version(pf);
41c445ff
JB		 10287
10288 /* since everything's happy, start the service_task timer */
10289 mod_timer(&pf->service_timer,
10290 round_jiffies(jiffies + pf->service_timer_period));
10291
38e00438
VD		 10292#ifdef I40E_FCOE
10293 /* create FCoE interface */
10294 i40e_fcoe_vsi_setup(pf);
10295
10296#endif
d4dfb81a
CS		 10297 /* Get the negotiated link width and speed from PCI config space */
10298 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
10299
10300 i40e_set_pci_config_data(hw, link_status);
10301
69bfb110 10302 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 10303 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
10304 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
10305 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
10306 "Unknown"),
10307 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
10308 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
10309 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
10310 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
10311 "Unknown"));
10312
10313 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10314 hw->bus.speed < i40e_bus_speed_8000) {
10315 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10316 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10317 }
10318
e827845c
CS		 10319 /* get the requested speeds from the fw */
10320 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10321 if (err)
f1c7e72e
SN		 10322 dev_info(&pf->pdev->dev,
10323 "get phy capabilities failed, err %s aq_err %s, advertised speed settings may not be correct\n",
10324 i40e_stat_str(&pf->hw, err),
10325 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10326 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10327
0c22b3dd
JB		 10328 /* print a string summarizing features */
10329 i40e_print_features(pf);
10330
41c445ff
JB		 10331 return 0;
10332
10333 /* Unwind what we've done if something failed in the setup */
10334err_vsis:
10335 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10336 i40e_clear_interrupt_scheme(pf);
10337 kfree(pf->vsi);
04b03013
SN		 10338err_switch_setup:
10339 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10340 del_timer_sync(&pf->service_timer);
10341err_mac_addr:
10342err_configure_lan_hmc:
10343 (void)i40e_shutdown_lan_hmc(hw);
10344err_init_lan_hmc:
10345 kfree(pf->qp_pile);
41c445ff
JB		 10346err_sw_init:
10347err_adminq_setup:
10348 (void)i40e_shutdown_adminq(hw);
10349err_pf_reset:
10350 iounmap(hw->hw_addr);
10351err_ioremap:
10352 kfree(pf);
10353err_pf_alloc:
10354 pci_disable_pcie_error_reporting(pdev);
10355 pci_release_selected_regions(pdev,
10356 pci_select_bars(pdev, IORESOURCE_MEM));
10357err_pci_reg:
10358err_dma:
10359 pci_disable_device(pdev);
10360 return err;
10361}
10362
10363/**
10364 * i40e_remove - Device removal routine
10365 * @pdev: PCI device information struct
10366 *
10367 * i40e_remove is called by the PCI subsystem to alert the driver
10368 * that is should release a PCI device. This could be caused by a
10369 * Hot-Plug event, or because the driver is going to be removed from
10370 * memory.
10371 **/
10372static void i40e_remove(struct pci_dev *pdev)
10373{
10374 struct i40e_pf *pf = pci_get_drvdata(pdev);
10375 i40e_status ret_code;
41c445ff
JB		 10376 int i;
10377
10378 i40e_dbg_pf_exit(pf);
10379
beb0dff1
JK		 10380 i40e_ptp_stop(pf);
10381
41c445ff
JB		 10382 /* no more scheduling of any task */
10383 set_bit(__I40E_DOWN, &pf->state);
10384 del_timer_sync(&pf->service_timer);
10385 cancel_work_sync(&pf->service_task);
33c62b34 10386 i40e_fdir_teardown(pf);
41c445ff 10387
eb2d80bc
MW		 10388 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10389 i40e_free_vfs(pf);
10390 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10391 }
10392
41c445ff
JB		 10393 i40e_fdir_teardown(pf);
10394
10395 /* If there is a switch structure or any orphans, remove them.
10396 * This will leave only the PF's VSI remaining.
10397 */
10398 for (i = 0; i < I40E_MAX_VEB; i++) {
10399 if (!pf->veb[i])
10400 continue;
10401
10402 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10403 pf->veb[i]->uplink_seid == 0)
10404 i40e_switch_branch_release(pf->veb[i]);
10405 }
10406
10407 /* Now we can shutdown the PF's VSI, just before we kill
10408 * adminq and hmc.
10409 */
10410 if (pf->vsi[pf->lan_vsi])
10411 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10412
41c445ff 10413 /* shutdown and destroy the HMC */
60442dea
SN		 10414 if (pf->hw.hmc.hmc_obj) {
10415 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10416 if (ret_code)
10417 dev_warn(&pdev->dev,
10418 "Failed to destroy the HMC resources: %d\n",
10419 ret_code);
10420 }
41c445ff
JB		 10421
10422 /* shutdown the adminq */
41c445ff
JB		 10423 ret_code = i40e_shutdown_adminq(&pf->hw);
10424 if (ret_code)
10425 dev_warn(&pdev->dev,
10426 "Failed to destroy the Admin Queue resources: %d\n",
10427 ret_code);
10428
10429 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10430 i40e_clear_interrupt_scheme(pf);
505682cd 10431 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10432 if (pf->vsi[i]) {
10433 i40e_vsi_clear_rings(pf->vsi[i]);
10434 i40e_vsi_clear(pf->vsi[i]);
10435 pf->vsi[i] = NULL;
10436 }
10437 }
10438
10439 for (i = 0; i < I40E_MAX_VEB; i++) {
10440 kfree(pf->veb[i]);
10441 pf->veb[i] = NULL;
10442 }
10443
10444 kfree(pf->qp_pile);
41c445ff
JB		 10445 kfree(pf->vsi);
10446
41c445ff
JB		 10447 iounmap(pf->hw.hw_addr);
10448 kfree(pf);
10449 pci_release_selected_regions(pdev,
10450 pci_select_bars(pdev, IORESOURCE_MEM));
10451
10452 pci_disable_pcie_error_reporting(pdev);
10453 pci_disable_device(pdev);
10454}
10455
10456/**
10457 * i40e_pci_error_detected - warning that something funky happened in PCI land
10458 * @pdev: PCI device information struct
10459 *
10460 * Called to warn that something happened and the error handling steps
10461 * are in progress. Allows the driver to quiesce things, be ready for
10462 * remediation.
10463 **/
10464static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10465 enum pci_channel_state error)
10466{
10467 struct i40e_pf *pf = pci_get_drvdata(pdev);
10468
10469 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10470
10471 /* shutdown all operations */
9007bccd
SN		 10472 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10473 rtnl_lock();
10474 i40e_prep_for_reset(pf);
10475 rtnl_unlock();
10476 }
41c445ff
JB		 10477
10478 /* Request a slot reset */
10479 return PCI_ERS_RESULT_NEED_RESET;
10480}
10481
10482/**
10483 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10484 * @pdev: PCI device information struct
10485 *
10486 * Called to find if the driver can work with the device now that
10487 * the pci slot has been reset. If a basic connection seems good
10488 * (registers are readable and have sane content) then return a
10489 * happy little PCI_ERS_RESULT_xxx.
10490 **/
10491static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10492{
10493 struct i40e_pf *pf = pci_get_drvdata(pdev);
10494 pci_ers_result_t result;
10495 int err;
10496 u32 reg;
10497
fb43201f 10498 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 10499 if (pci_enable_device_mem(pdev)) {
10500 dev_info(&pdev->dev,
10501 "Cannot re-enable PCI device after reset.\n");
10502 result = PCI_ERS_RESULT_DISCONNECT;
10503 } else {
10504 pci_set_master(pdev);
10505 pci_restore_state(pdev);
10506 pci_save_state(pdev);
10507 pci_wake_from_d3(pdev, false);
10508
10509 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10510 if (reg == 0)
10511 result = PCI_ERS_RESULT_RECOVERED;
10512 else
10513 result = PCI_ERS_RESULT_DISCONNECT;
10514 }
10515
10516 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10517 if (err) {
10518 dev_info(&pdev->dev,
10519 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10520 err);
10521 /* non-fatal, continue */
10522 }
10523
10524 return result;
10525}
10526
10527/**
10528 * i40e_pci_error_resume - restart operations after PCI error recovery
10529 * @pdev: PCI device information struct
10530 *
10531 * Called to allow the driver to bring things back up after PCI error
10532 * and/or reset recovery has finished.
10533 **/
10534static void i40e_pci_error_resume(struct pci_dev *pdev)
10535{
10536 struct i40e_pf *pf = pci_get_drvdata(pdev);
10537
fb43201f 10538 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10539 if (test_bit(__I40E_SUSPENDED, &pf->state))
10540 return;
10541
10542 rtnl_lock();
41c445ff 10543 i40e_handle_reset_warning(pf);
4c4935a9 10544 rtnl_unlock();
9007bccd
SN		 10545}
10546
10547/**
10548 * i40e_shutdown - PCI callback for shutting down
10549 * @pdev: PCI device information struct
10550 **/
10551static void i40e_shutdown(struct pci_dev *pdev)
10552{
10553 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10554 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10555
10556 set_bit(__I40E_SUSPENDED, &pf->state);
10557 set_bit(__I40E_DOWN, &pf->state);
10558 rtnl_lock();
10559 i40e_prep_for_reset(pf);
10560 rtnl_unlock();
10561
8e2773ae
SN		 10562 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10563 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10564
02b42498
CS		 10565 del_timer_sync(&pf->service_timer);
10566 cancel_work_sync(&pf->service_task);
10567 i40e_fdir_teardown(pf);
10568
10569 rtnl_lock();
10570 i40e_prep_for_reset(pf);
10571 rtnl_unlock();
10572
10573 wr32(hw, I40E_PFPM_APM,
10574 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10575 wr32(hw, I40E_PFPM_WUFC,
10576 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10577
e147758d
SN		 10578 i40e_clear_interrupt_scheme(pf);
10579
9007bccd 10580 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10581 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10582 pci_set_power_state(pdev, PCI_D3hot);
10583 }
10584}
10585
10586#ifdef CONFIG_PM
10587/**
10588 * i40e_suspend - PCI callback for moving to D3
10589 * @pdev: PCI device information struct
10590 **/
10591static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10592{
10593 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10594 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10595
10596 set_bit(__I40E_SUSPENDED, &pf->state);
10597 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10598
9007bccd
SN		 10599 rtnl_lock();
10600 i40e_prep_for_reset(pf);
10601 rtnl_unlock();
10602
8e2773ae
SN		 10603 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10604 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10605
10606 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10607 pci_set_power_state(pdev, PCI_D3hot);
10608
10609 return 0;
41c445ff
JB		 10610}
10611
9007bccd
SN		 10612/**
10613 * i40e_resume - PCI callback for waking up from D3
10614 * @pdev: PCI device information struct
10615 **/
10616static int i40e_resume(struct pci_dev *pdev)
10617{
10618 struct i40e_pf *pf = pci_get_drvdata(pdev);
10619 u32 err;
10620
10621 pci_set_power_state(pdev, PCI_D0);
10622 pci_restore_state(pdev);
10623 /* pci_restore_state() clears dev->state_saves, so
10624 * call pci_save_state() again to restore it.
10625 */
10626 pci_save_state(pdev);
10627
10628 err = pci_enable_device_mem(pdev);
10629 if (err) {
fb43201f 10630 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 10631 return err;
10632 }
10633 pci_set_master(pdev);
10634
10635 /* no wakeup events while running */
10636 pci_wake_from_d3(pdev, false);
10637
10638 /* handling the reset will rebuild the device state */
10639 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10640 clear_bit(__I40E_DOWN, &pf->state);
10641 rtnl_lock();
10642 i40e_reset_and_rebuild(pf, false);
10643 rtnl_unlock();
10644 }
10645
10646 return 0;
10647}
10648
10649#endif
41c445ff
JB		 10650static const struct pci_error_handlers i40e_err_handler = {
10651 .error_detected = i40e_pci_error_detected,
10652 .slot_reset = i40e_pci_error_slot_reset,
10653 .resume = i40e_pci_error_resume,
10654};
10655
10656static struct pci_driver i40e_driver = {
10657 .name = i40e_driver_name,
10658 .id_table = i40e_pci_tbl,
10659 .probe = i40e_probe,
10660 .remove = i40e_remove,
9007bccd
SN		 10661#ifdef CONFIG_PM
10662 .suspend = i40e_suspend,
10663 .resume = i40e_resume,
10664#endif
10665 .shutdown = i40e_shutdown,
41c445ff
JB		 10666 .err_handler = &i40e_err_handler,
10667 .sriov_configure = i40e_pci_sriov_configure,
10668};
10669
10670/**
10671 * i40e_init_module - Driver registration routine
10672 *
10673 * i40e_init_module is the first routine called when the driver is
10674 * loaded. All it does is register with the PCI subsystem.
10675 **/
10676static int __init i40e_init_module(void)
10677{
10678 pr_info("%s: %s - version %s\n", i40e_driver_name,
10679 i40e_driver_string, i40e_driver_version_str);
10680 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10681
41c445ff
JB		 10682 i40e_dbg_init();
10683 return pci_register_driver(&i40e_driver);
10684}
10685module_init(i40e_init_module);
10686
10687/**
10688 * i40e_exit_module - Driver exit cleanup routine
10689 *
10690 * i40e_exit_module is called just before the driver is removed
10691 * from memory.
10692 **/
10693static void __exit i40e_exit_module(void)
10694{
10695 pci_unregister_driver(&i40e_driver);
10696 i40e_dbg_exit();
10697}
10698module_exit(i40e_exit_module);
Linux kernel - Deliverables
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