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i40e: add VEB stat control and remove L2 cloud filter
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
6a899024 34#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 35#include <net/vxlan.h>
36#endif
6a899024
SA		 37#if IS_ENABLED(CONFIG_GENEVE)
38#include <net/geneve.h>
39#endif
41c445ff
JB		 40
41const char i40e_driver_name[] = "i40e";
42static const char i40e_driver_string[] =
43 "Intel(R) Ethernet Connection XL710 Network Driver";
44
45#define DRV_KERN "-k"
46
e8e724db 47#define DRV_VERSION_MAJOR 1
1c2df9e5 48#define DRV_VERSION_MINOR 4
4580de0d 49#define DRV_VERSION_BUILD 12
41c445ff
JB		 50#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
51 __stringify(DRV_VERSION_MINOR) "." \
52 __stringify(DRV_VERSION_BUILD) DRV_KERN
53const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 54static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 55
56/* a bit of forward declarations */
57static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
58static void i40e_handle_reset_warning(struct i40e_pf *pf);
59static int i40e_add_vsi(struct i40e_vsi *vsi);
60static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 61static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 62static int i40e_setup_misc_vector(struct i40e_pf *pf);
63static void i40e_determine_queue_usage(struct i40e_pf *pf);
64static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 65static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
66 u16 rss_table_size, u16 rss_size);
cbf61325 67static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 68static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 69
70/* i40e_pci_tbl - PCI Device ID Table
71 *
72 * Last entry must be all 0s
73 *
74 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
75 * Class, Class Mask, private data (not used) }
76 */
9baa3c34 77static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
92 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 93 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
94 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
99
100#define I40E_MAX_VF_COUNT 128
101static int debug = -1;
102module_param(debug, int, 0);
103MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
104
105MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
106MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
107MODULE_LICENSE("GPL");
108MODULE_VERSION(DRV_VERSION);
109
2803b16c
JB		 110static struct workqueue_struct *i40e_wq;
111
41c445ff
JB		 112/**
113 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
114 * @hw: pointer to the HW structure
115 * @mem: ptr to mem struct to fill out
116 * @size: size of memory requested
117 * @alignment: what to align the allocation to
118 **/
119int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
120 u64 size, u32 alignment)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 mem->size = ALIGN(size, alignment);
125 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
126 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 127 if (!mem->va)
128 return -ENOMEM;
41c445ff 129
93bc73b8 130 return 0;
41c445ff
JB		 131}
132
133/**
134 * i40e_free_dma_mem_d - OS specific memory free for shared code
135 * @hw: pointer to the HW structure
136 * @mem: ptr to mem struct to free
137 **/
138int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
139{
140 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
141
142 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
143 mem->va = NULL;
144 mem->pa = 0;
145 mem->size = 0;
146
147 return 0;
148}
149
150/**
151 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to fill out
154 * @size: size of memory requested
155 **/
156int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
157 u32 size)
158{
159 mem->size = size;
160 mem->va = kzalloc(size, GFP_KERNEL);
161
93bc73b8
JB		 162 if (!mem->va)
163 return -ENOMEM;
41c445ff 164
93bc73b8 165 return 0;
41c445ff
JB		 166}
167
168/**
169 * i40e_free_virt_mem_d - OS specific memory free for shared code
170 * @hw: pointer to the HW structure
171 * @mem: ptr to mem struct to free
172 **/
173int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
174{
175 /* it's ok to kfree a NULL pointer */
176 kfree(mem->va);
177 mem->va = NULL;
178 mem->size = 0;
179
180 return 0;
181}
182
183/**
184 * i40e_get_lump - find a lump of free generic resource
185 * @pf: board private structure
186 * @pile: the pile of resource to search
187 * @needed: the number of items needed
188 * @id: an owner id to stick on the items assigned
189 *
190 * Returns the base item index of the lump, or negative for error
191 *
192 * The search_hint trick and lack of advanced fit-finding only work
193 * because we're highly likely to have all the same size lump requests.
194 * Linear search time and any fragmentation should be minimal.
195 **/
196static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
197 u16 needed, u16 id)
198{
199 int ret = -ENOMEM;
ddf434ac 200 int i, j;
41c445ff
JB		 201
202 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
203 dev_info(&pf->pdev->dev,
204 "param err: pile=%p needed=%d id=0x%04x\n",
205 pile, needed, id);
206 return -EINVAL;
207 }
208
209 /* start the linear search with an imperfect hint */
210 i = pile->search_hint;
ddf434ac 211 while (i < pile->num_entries) {
41c445ff
JB		 212 /* skip already allocated entries */
213 if (pile->list[i] & I40E_PILE_VALID_BIT) {
214 i++;
215 continue;
216 }
217
218 /* do we have enough in this lump? */
219 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
220 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
221 break;
222 }
223
224 if (j == needed) {
225 /* there was enough, so assign it to the requestor */
226 for (j = 0; j < needed; j++)
227 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
228 ret = i;
229 pile->search_hint = i + j;
ddf434ac 230 break;
41c445ff 231 }
6995b36c
JB		 232
233 /* not enough, so skip over it and continue looking */
234 i += j;
41c445ff
JB		 235 }
236
237 return ret;
238}
239
240/**
241 * i40e_put_lump - return a lump of generic resource
242 * @pile: the pile of resource to search
243 * @index: the base item index
244 * @id: the owner id of the items assigned
245 *
246 * Returns the count of items in the lump
247 **/
248static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
249{
250 int valid_id = (id | I40E_PILE_VALID_BIT);
251 int count = 0;
252 int i;
253
254 if (!pile || index >= pile->num_entries)
255 return -EINVAL;
256
257 for (i = index;
258 i < pile->num_entries && pile->list[i] == valid_id;
259 i++) {
260 pile->list[i] = 0;
261 count++;
262 }
263
264 if (count && index < pile->search_hint)
265 pile->search_hint = index;
266
267 return count;
268}
269
fdf0e0bf
ASJ		 270/**
271 * i40e_find_vsi_from_id - searches for the vsi with the given id
272 * @pf - the pf structure to search for the vsi
273 * @id - id of the vsi it is searching for
274 **/
275struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
276{
277 int i;
278
279 for (i = 0; i < pf->num_alloc_vsi; i++)
280 if (pf->vsi[i] && (pf->vsi[i]->id == id))
281 return pf->vsi[i];
282
283 return NULL;
284}
285
41c445ff
JB		 286/**
287 * i40e_service_event_schedule - Schedule the service task to wake up
288 * @pf: board private structure
289 *
290 * If not already scheduled, this puts the task into the work queue
291 **/
292static void i40e_service_event_schedule(struct i40e_pf *pf)
293{
294 if (!test_bit(__I40E_DOWN, &pf->state) &&
295 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
296 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 297 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 298}
299
300/**
301 * i40e_tx_timeout - Respond to a Tx Hang
302 * @netdev: network interface device structure
303 *
304 * If any port has noticed a Tx timeout, it is likely that the whole
305 * device is munged, not just the one netdev port, so go for the full
306 * reset.
307 **/
38e00438
VD		 308#ifdef I40E_FCOE
309void i40e_tx_timeout(struct net_device *netdev)
310#else
41c445ff 311static void i40e_tx_timeout(struct net_device *netdev)
38e00438 312#endif
41c445ff
JB		 313{
314 struct i40e_netdev_priv *np = netdev_priv(netdev);
315 struct i40e_vsi *vsi = np->vsi;
316 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 317 struct i40e_ring *tx_ring = NULL;
318 unsigned int i, hung_queue = 0;
319 u32 head, val;
41c445ff
JB		 320
321 pf->tx_timeout_count++;
322
b03a8c1f
KP		 323 /* find the stopped queue the same way the stack does */
324 for (i = 0; i < netdev->num_tx_queues; i++) {
325 struct netdev_queue *q;
326 unsigned long trans_start;
327
328 q = netdev_get_tx_queue(netdev, i);
329 trans_start = q->trans_start ? : netdev->trans_start;
330 if (netif_xmit_stopped(q) &&
331 time_after(jiffies,
332 (trans_start + netdev->watchdog_timeo))) {
333 hung_queue = i;
334 break;
335 }
336 }
337
338 if (i == netdev->num_tx_queues) {
339 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
340 } else {
341 /* now that we have an index, find the tx_ring struct */
342 for (i = 0; i < vsi->num_queue_pairs; i++) {
343 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
344 if (hung_queue ==
345 vsi->tx_rings[i]->queue_index) {
346 tx_ring = vsi->tx_rings[i];
347 break;
348 }
349 }
350 }
351 }
352
41c445ff 353 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 354 pf->tx_timeout_recovery_level = 1; /* reset after some time */
355 else if (time_before(jiffies,
356 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
357 return; /* don't do any new action before the next timeout */
358
359 if (tx_ring) {
360 head = i40e_get_head(tx_ring);
361 /* Read interrupt register */
362 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
363 val = rd32(&pf->hw,
364 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
365 tx_ring->vsi->base_vector - 1));
366 else
367 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
368
369 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
370 vsi->seid, hung_queue, tx_ring->next_to_clean,
371 head, tx_ring->next_to_use,
372 readl(tx_ring->tail), val);
373 }
374
41c445ff 375 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 376 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
377 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 378
379 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 380 case 1:
381 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
382 break;
383 case 2:
384 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
385 break;
386 case 3:
387 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
388 break;
389 default:
390 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 391 break;
392 }
b03a8c1f 393
41c445ff
JB		 394 i40e_service_event_schedule(pf);
395 pf->tx_timeout_recovery_level++;
396}
397
398/**
399 * i40e_release_rx_desc - Store the new tail and head values
400 * @rx_ring: ring to bump
401 * @val: new head index
402 **/
403static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
404{
405 rx_ring->next_to_use = val;
406
407 /* Force memory writes to complete before letting h/w
408 * know there are new descriptors to fetch. (Only
409 * applicable for weak-ordered memory model archs,
410 * such as IA-64).
411 */
412 wmb();
413 writel(val, rx_ring->tail);
414}
415
416/**
417 * i40e_get_vsi_stats_struct - Get System Network Statistics
418 * @vsi: the VSI we care about
419 *
420 * Returns the address of the device statistics structure.
421 * The statistics are actually updated from the service task.
422 **/
423struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
424{
425 return &vsi->net_stats;
426}
427
428/**
429 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
430 * @netdev: network interface device structure
431 *
432 * Returns the address of the device statistics structure.
433 * The statistics are actually updated from the service task.
434 **/
38e00438
VD		 435#ifdef I40E_FCOE
436struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
437 struct net_device *netdev,
438 struct rtnl_link_stats64 *stats)
439#else
41c445ff
JB		 440static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
441 struct net_device *netdev,
980e9b11 442 struct rtnl_link_stats64 *stats)
38e00438 443#endif
41c445ff
JB		 444{
445 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 446 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 447 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 448 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
449 int i;
450
bc7d338f
ASJ		 451 if (test_bit(__I40E_DOWN, &vsi->state))
452 return stats;
453
3c325ced
JB		 454 if (!vsi->tx_rings)
455 return stats;
456
980e9b11
AD		 457 rcu_read_lock();
458 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 459 u64 bytes, packets;
460 unsigned int start;
461
462 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
463 if (!tx_ring)
464 continue;
465
466 do {
57a7744e 467 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 468 packets = tx_ring->stats.packets;
469 bytes = tx_ring->stats.bytes;
57a7744e 470 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 471
472 stats->tx_packets += packets;
473 stats->tx_bytes += bytes;
474 rx_ring = &tx_ring[1];
475
476 do {
57a7744e 477 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 478 packets = rx_ring->stats.packets;
479 bytes = rx_ring->stats.bytes;
57a7744e 480 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 481
980e9b11
AD		 482 stats->rx_packets += packets;
483 stats->rx_bytes += bytes;
484 }
485 rcu_read_unlock();
486
a5282f44 487 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 488 stats->multicast = vsi_stats->multicast;
489 stats->tx_errors = vsi_stats->tx_errors;
490 stats->tx_dropped = vsi_stats->tx_dropped;
491 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 492 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 493 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
494 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 495
980e9b11 496 return stats;
41c445ff
JB		 497}
498
499/**
500 * i40e_vsi_reset_stats - Resets all stats of the given vsi
501 * @vsi: the VSI to have its stats reset
502 **/
503void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
504{
505 struct rtnl_link_stats64 *ns;
506 int i;
507
508 if (!vsi)
509 return;
510
511 ns = i40e_get_vsi_stats_struct(vsi);
512 memset(ns, 0, sizeof(*ns));
513 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
514 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
515 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 516 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 517 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 518 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 519 sizeof(vsi->rx_rings[i]->stats));
6995b36c 520 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 521 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 522 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 523 sizeof(vsi->tx_rings[i]->stats));
524 memset(&vsi->tx_rings[i]->tx_stats, 0,
525 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 526 }
8e9dca53 527 }
41c445ff
JB		 528 vsi->stat_offsets_loaded = false;
529}
530
531/**
b40c82e6 532 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 533 * @pf: the PF to be reset
534 **/
535void i40e_pf_reset_stats(struct i40e_pf *pf)
536{
e91fdf76
SN		 537 int i;
538
41c445ff
JB		 539 memset(&pf->stats, 0, sizeof(pf->stats));
540 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
541 pf->stat_offsets_loaded = false;
e91fdf76
SN		 542
543 for (i = 0; i < I40E_MAX_VEB; i++) {
544 if (pf->veb[i]) {
545 memset(&pf->veb[i]->stats, 0,
546 sizeof(pf->veb[i]->stats));
547 memset(&pf->veb[i]->stats_offsets, 0,
548 sizeof(pf->veb[i]->stats_offsets));
549 pf->veb[i]->stat_offsets_loaded = false;
550 }
551 }
41c445ff
JB		 552}
553
554/**
555 * i40e_stat_update48 - read and update a 48 bit stat from the chip
556 * @hw: ptr to the hardware info
557 * @hireg: the high 32 bit reg to read
558 * @loreg: the low 32 bit reg to read
559 * @offset_loaded: has the initial offset been loaded yet
560 * @offset: ptr to current offset value
561 * @stat: ptr to the stat
562 *
563 * Since the device stats are not reset at PFReset, they likely will not
564 * be zeroed when the driver starts. We'll save the first values read
565 * and use them as offsets to be subtracted from the raw values in order
566 * to report stats that count from zero. In the process, we also manage
567 * the potential roll-over.
568 **/
569static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
570 bool offset_loaded, u64 *offset, u64 *stat)
571{
572 u64 new_data;
573
ab60085e 574 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 575 new_data = rd32(hw, loreg);
576 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
577 } else {
578 new_data = rd64(hw, loreg);
579 }
580 if (!offset_loaded)
581 *offset = new_data;
582 if (likely(new_data >= *offset))
583 *stat = new_data - *offset;
584 else
41a1d04b 585 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 586 *stat &= 0xFFFFFFFFFFFFULL;
587}
588
589/**
590 * i40e_stat_update32 - read and update a 32 bit stat from the chip
591 * @hw: ptr to the hardware info
592 * @reg: the hw reg to read
593 * @offset_loaded: has the initial offset been loaded yet
594 * @offset: ptr to current offset value
595 * @stat: ptr to the stat
596 **/
597static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
598 bool offset_loaded, u64 *offset, u64 *stat)
599{
600 u32 new_data;
601
602 new_data = rd32(hw, reg);
603 if (!offset_loaded)
604 *offset = new_data;
605 if (likely(new_data >= *offset))
606 *stat = (u32)(new_data - *offset);
607 else
41a1d04b 608 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 609}
610
611/**
612 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
613 * @vsi: the VSI to be updated
614 **/
615void i40e_update_eth_stats(struct i40e_vsi *vsi)
616{
617 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
618 struct i40e_pf *pf = vsi->back;
619 struct i40e_hw *hw = &pf->hw;
620 struct i40e_eth_stats *oes;
621 struct i40e_eth_stats *es; /* device's eth stats */
622
623 es = &vsi->eth_stats;
624 oes = &vsi->eth_stats_offsets;
625
626 /* Gather up the stats that the hw collects */
627 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
628 vsi->stat_offsets_loaded,
629 &oes->tx_errors, &es->tx_errors);
630 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
631 vsi->stat_offsets_loaded,
632 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 633 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
636 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
637 vsi->stat_offsets_loaded,
638 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 639
640 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
641 I40E_GLV_GORCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->rx_bytes, &es->rx_bytes);
644 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
645 I40E_GLV_UPRCL(stat_idx),
646 vsi->stat_offsets_loaded,
647 &oes->rx_unicast, &es->rx_unicast);
648 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
649 I40E_GLV_MPRCL(stat_idx),
650 vsi->stat_offsets_loaded,
651 &oes->rx_multicast, &es->rx_multicast);
652 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
653 I40E_GLV_BPRCL(stat_idx),
654 vsi->stat_offsets_loaded,
655 &oes->rx_broadcast, &es->rx_broadcast);
656
657 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
658 I40E_GLV_GOTCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->tx_bytes, &es->tx_bytes);
661 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
662 I40E_GLV_UPTCL(stat_idx),
663 vsi->stat_offsets_loaded,
664 &oes->tx_unicast, &es->tx_unicast);
665 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
666 I40E_GLV_MPTCL(stat_idx),
667 vsi->stat_offsets_loaded,
668 &oes->tx_multicast, &es->tx_multicast);
669 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
670 I40E_GLV_BPTCL(stat_idx),
671 vsi->stat_offsets_loaded,
672 &oes->tx_broadcast, &es->tx_broadcast);
673 vsi->stat_offsets_loaded = true;
674}
675
676/**
677 * i40e_update_veb_stats - Update Switch component statistics
678 * @veb: the VEB being updated
679 **/
680static void i40e_update_veb_stats(struct i40e_veb *veb)
681{
682 struct i40e_pf *pf = veb->pf;
683 struct i40e_hw *hw = &pf->hw;
684 struct i40e_eth_stats *oes;
685 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 686 struct i40e_veb_tc_stats *veb_oes;
687 struct i40e_veb_tc_stats *veb_es;
688 int i, idx = 0;
41c445ff
JB		 689
690 idx = veb->stats_idx;
691 es = &veb->stats;
692 oes = &veb->stats_offsets;
fe860afb
NP		 693 veb_es = &veb->tc_stats;
694 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 695
696 /* Gather up the stats that the hw collects */
697 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
698 veb->stat_offsets_loaded,
699 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 700 if (hw->revision_id > 0)
701 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_unknown_protocol,
704 &es->rx_unknown_protocol);
41c445ff
JB		 705 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
706 veb->stat_offsets_loaded,
707 &oes->rx_bytes, &es->rx_bytes);
708 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->rx_unicast, &es->rx_unicast);
711 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->rx_multicast, &es->rx_multicast);
714 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->rx_broadcast, &es->rx_broadcast);
717
718 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
719 veb->stat_offsets_loaded,
720 &oes->tx_bytes, &es->tx_bytes);
721 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
722 veb->stat_offsets_loaded,
723 &oes->tx_unicast, &es->tx_unicast);
724 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
725 veb->stat_offsets_loaded,
726 &oes->tx_multicast, &es->tx_multicast);
727 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
728 veb->stat_offsets_loaded,
729 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 730 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
731 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
732 I40E_GLVEBTC_RPCL(i, idx),
733 veb->stat_offsets_loaded,
734 &veb_oes->tc_rx_packets[i],
735 &veb_es->tc_rx_packets[i]);
736 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
737 I40E_GLVEBTC_RBCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_rx_bytes[i],
740 &veb_es->tc_rx_bytes[i]);
741 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
742 I40E_GLVEBTC_TPCL(i, idx),
743 veb->stat_offsets_loaded,
744 &veb_oes->tc_tx_packets[i],
745 &veb_es->tc_tx_packets[i]);
746 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
747 I40E_GLVEBTC_TBCL(i, idx),
748 veb->stat_offsets_loaded,
749 &veb_oes->tc_tx_bytes[i],
750 &veb_es->tc_tx_bytes[i]);
751 }
41c445ff
JB		 752 veb->stat_offsets_loaded = true;
753}
754
38e00438
VD		 755#ifdef I40E_FCOE
756/**
757 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
758 * @vsi: the VSI that is capable of doing FCoE
759 **/
760static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
761{
762 struct i40e_pf *pf = vsi->back;
763 struct i40e_hw *hw = &pf->hw;
764 struct i40e_fcoe_stats *ofs;
765 struct i40e_fcoe_stats *fs; /* device's eth stats */
766 int idx;
767
768 if (vsi->type != I40E_VSI_FCOE)
769 return;
770
771 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
772 fs = &vsi->fcoe_stats;
773 ofs = &vsi->fcoe_stats_offsets;
774
775 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
778 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
781 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
784 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
785 vsi->fcoe_stat_offsets_loaded,
786 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
787 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
788 vsi->fcoe_stat_offsets_loaded,
789 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
790 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
791 vsi->fcoe_stat_offsets_loaded,
792 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
793 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
794 vsi->fcoe_stat_offsets_loaded,
795 &ofs->fcoe_last_error, &fs->fcoe_last_error);
796 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
797 vsi->fcoe_stat_offsets_loaded,
798 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
799
800 vsi->fcoe_stat_offsets_loaded = true;
801}
802
803#endif
41c445ff 804/**
7812fddc 805 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 806 * @vsi: the VSI to be updated
807 *
808 * There are a few instances where we store the same stat in a
809 * couple of different structs. This is partly because we have
810 * the netdev stats that need to be filled out, which is slightly
811 * different from the "eth_stats" defined by the chip and used in
7812fddc 812 * VF communications. We sort it out here.
41c445ff 813 **/
7812fddc 814static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 815{
816 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 817 struct rtnl_link_stats64 *ons;
818 struct rtnl_link_stats64 *ns; /* netdev stats */
819 struct i40e_eth_stats *oes;
820 struct i40e_eth_stats *es; /* device's eth stats */
821 u32 tx_restart, tx_busy;
bf00b376 822 struct i40e_ring *p;
41c445ff 823 u32 rx_page, rx_buf;
bf00b376
AA		 824 u64 bytes, packets;
825 unsigned int start;
2fc3d715 826 u64 tx_linearize;
164c9f54 827 u64 tx_force_wb;
41c445ff
JB		 828 u64 rx_p, rx_b;
829 u64 tx_p, tx_b;
41c445ff
JB		 830 u16 q;
831
832 if (test_bit(__I40E_DOWN, &vsi->state) ||
833 test_bit(__I40E_CONFIG_BUSY, &pf->state))
834 return;
835
836 ns = i40e_get_vsi_stats_struct(vsi);
837 ons = &vsi->net_stats_offsets;
838 es = &vsi->eth_stats;
839 oes = &vsi->eth_stats_offsets;
840
841 /* Gather up the netdev and vsi stats that the driver collects
842 * on the fly during packet processing
843 */
844 rx_b = rx_p = 0;
845 tx_b = tx_p = 0;
164c9f54 846 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 847 rx_page = 0;
848 rx_buf = 0;
980e9b11 849 rcu_read_lock();
41c445ff 850 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 851 /* locate Tx ring */
852 p = ACCESS_ONCE(vsi->tx_rings[q]);
853
854 do {
57a7744e 855 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 856 packets = p->stats.packets;
857 bytes = p->stats.bytes;
57a7744e 858 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 859 tx_b += bytes;
860 tx_p += packets;
861 tx_restart += p->tx_stats.restart_queue;
862 tx_busy += p->tx_stats.tx_busy;
2fc3d715 863 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 864 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 865
980e9b11
AD		 866 /* Rx queue is part of the same block as Tx queue */
867 p = &p[1];
868 do {
57a7744e 869 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 870 packets = p->stats.packets;
871 bytes = p->stats.bytes;
57a7744e 872 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 873 rx_b += bytes;
874 rx_p += packets;
420136cc
MW		 875 rx_buf += p->rx_stats.alloc_buff_failed;
876 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 877 }
980e9b11 878 rcu_read_unlock();
41c445ff
JB		 879 vsi->tx_restart = tx_restart;
880 vsi->tx_busy = tx_busy;
2fc3d715 881 vsi->tx_linearize = tx_linearize;
164c9f54 882 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 883 vsi->rx_page_failed = rx_page;
884 vsi->rx_buf_failed = rx_buf;
885
886 ns->rx_packets = rx_p;
887 ns->rx_bytes = rx_b;
888 ns->tx_packets = tx_p;
889 ns->tx_bytes = tx_b;
890
41c445ff 891 /* update netdev stats from eth stats */
7812fddc 892 i40e_update_eth_stats(vsi);
41c445ff
JB		 893 ons->tx_errors = oes->tx_errors;
894 ns->tx_errors = es->tx_errors;
895 ons->multicast = oes->rx_multicast;
896 ns->multicast = es->rx_multicast;
41a9e55c
SN		 897 ons->rx_dropped = oes->rx_discards;
898 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 899 ons->tx_dropped = oes->tx_discards;
900 ns->tx_dropped = es->tx_discards;
901
7812fddc 902 /* pull in a couple PF stats if this is the main vsi */
41c445ff 903 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 904 ns->rx_crc_errors = pf->stats.crc_errors;
905 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
906 ns->rx_length_errors = pf->stats.rx_length_errors;
907 }
908}
41c445ff 909
7812fddc 910/**
b40c82e6 911 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 912 * @pf: the PF to be updated
913 **/
914static void i40e_update_pf_stats(struct i40e_pf *pf)
915{
916 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
917 struct i40e_hw_port_stats *nsd = &pf->stats;
918 struct i40e_hw *hw = &pf->hw;
919 u32 val;
920 int i;
41c445ff 921
7812fddc
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
923 I40E_GLPRT_GORCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
926 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
927 I40E_GLPRT_GOTCL(hw->port),
928 pf->stat_offsets_loaded,
929 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
930 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->eth.rx_discards,
933 &nsd->eth.rx_discards);
532d283d
SN		 934 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
935 I40E_GLPRT_UPRCL(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->eth.rx_unicast,
938 &nsd->eth.rx_unicast);
7812fddc
SN		 939 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
940 I40E_GLPRT_MPRCL(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->eth.rx_multicast,
943 &nsd->eth.rx_multicast);
532d283d
SN		 944 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
945 I40E_GLPRT_BPRCL(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->eth.rx_broadcast,
948 &nsd->eth.rx_broadcast);
949 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
950 I40E_GLPRT_UPTCL(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->eth.tx_unicast,
953 &nsd->eth.tx_unicast);
954 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
955 I40E_GLPRT_MPTCL(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->eth.tx_multicast,
958 &nsd->eth.tx_multicast);
959 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
960 I40E_GLPRT_BPTCL(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->eth.tx_broadcast,
963 &nsd->eth.tx_broadcast);
41c445ff 964
7812fddc
SN		 965 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->tx_dropped_link_down,
968 &nsd->tx_dropped_link_down);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->crc_errors, &nsd->crc_errors);
41c445ff 973
7812fddc
SN		 974 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 977
7812fddc
SN		 978 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
979 pf->stat_offsets_loaded,
980 &osd->mac_local_faults,
981 &nsd->mac_local_faults);
982 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->mac_remote_faults,
985 &nsd->mac_remote_faults);
41c445ff 986
7812fddc
SN		 987 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->rx_length_errors,
990 &nsd->rx_length_errors);
41c445ff 991
7812fddc
SN		 992 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xon_rx, &nsd->link_xon_rx);
995 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 998 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
999 pf->stat_offsets_loaded,
1000 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 1001 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1002 pf->stat_offsets_loaded,
1003 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1004
7812fddc 1005 for (i = 0; i < 8; i++) {
95db239f
NP		 1006 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1007 pf->stat_offsets_loaded,
1008 &osd->priority_xoff_rx[i],
1009 &nsd->priority_xoff_rx[i]);
7812fddc 1010 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_rx[i],
1013 &nsd->priority_xon_rx[i]);
1014 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1015 pf->stat_offsets_loaded,
7812fddc
SN		 1016 &osd->priority_xon_tx[i],
1017 &nsd->priority_xon_tx[i]);
1018 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1019 pf->stat_offsets_loaded,
7812fddc
SN		 1020 &osd->priority_xoff_tx[i],
1021 &nsd->priority_xoff_tx[i]);
1022 i40e_stat_update32(hw,
1023 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1024 pf->stat_offsets_loaded,
7812fddc
SN		 1025 &osd->priority_xon_2_xoff[i],
1026 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1027 }
1028
7812fddc
SN		 1029 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1030 I40E_GLPRT_PRC64L(hw->port),
1031 pf->stat_offsets_loaded,
1032 &osd->rx_size_64, &nsd->rx_size_64);
1033 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1034 I40E_GLPRT_PRC127L(hw->port),
1035 pf->stat_offsets_loaded,
1036 &osd->rx_size_127, &nsd->rx_size_127);
1037 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1038 I40E_GLPRT_PRC255L(hw->port),
1039 pf->stat_offsets_loaded,
1040 &osd->rx_size_255, &nsd->rx_size_255);
1041 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1042 I40E_GLPRT_PRC511L(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->rx_size_511, &nsd->rx_size_511);
1045 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1046 I40E_GLPRT_PRC1023L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->rx_size_1023, &nsd->rx_size_1023);
1049 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1050 I40E_GLPRT_PRC1522L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->rx_size_1522, &nsd->rx_size_1522);
1053 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1054 I40E_GLPRT_PRC9522L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->rx_size_big, &nsd->rx_size_big);
1057
1058 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1059 I40E_GLPRT_PTC64L(hw->port),
1060 pf->stat_offsets_loaded,
1061 &osd->tx_size_64, &nsd->tx_size_64);
1062 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1063 I40E_GLPRT_PTC127L(hw->port),
1064 pf->stat_offsets_loaded,
1065 &osd->tx_size_127, &nsd->tx_size_127);
1066 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1067 I40E_GLPRT_PTC255L(hw->port),
1068 pf->stat_offsets_loaded,
1069 &osd->tx_size_255, &nsd->tx_size_255);
1070 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1071 I40E_GLPRT_PTC511L(hw->port),
1072 pf->stat_offsets_loaded,
1073 &osd->tx_size_511, &nsd->tx_size_511);
1074 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1075 I40E_GLPRT_PTC1023L(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->tx_size_1023, &nsd->tx_size_1023);
1078 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1079 I40E_GLPRT_PTC1522L(hw->port),
1080 pf->stat_offsets_loaded,
1081 &osd->tx_size_1522, &nsd->tx_size_1522);
1082 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1083 I40E_GLPRT_PTC9522L(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->tx_size_big, &nsd->tx_size_big);
1086
1087 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1088 pf->stat_offsets_loaded,
1089 &osd->rx_undersize, &nsd->rx_undersize);
1090 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1091 pf->stat_offsets_loaded,
1092 &osd->rx_fragments, &nsd->rx_fragments);
1093 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1094 pf->stat_offsets_loaded,
1095 &osd->rx_oversize, &nsd->rx_oversize);
1096 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1097 pf->stat_offsets_loaded,
1098 &osd->rx_jabber, &nsd->rx_jabber);
1099
433c47de 1100 /* FDIR stats */
0bf4b1b0
ASJ		 1101 i40e_stat_update32(hw,
1102 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1103 pf->stat_offsets_loaded,
1104 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1105 i40e_stat_update32(hw,
1106 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1107 pf->stat_offsets_loaded,
1108 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1109 i40e_stat_update32(hw,
1110 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1111 pf->stat_offsets_loaded,
1112 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1113
7812fddc
SN		 1114 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1115 nsd->tx_lpi_status =
1116 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1117 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1118 nsd->rx_lpi_status =
1119 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1120 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1121 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1122 pf->stat_offsets_loaded,
1123 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1124 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1125 pf->stat_offsets_loaded,
1126 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1127
d0389e51
ASJ		 1128 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1129 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1130 nsd->fd_sb_status = true;
1131 else
1132 nsd->fd_sb_status = false;
1133
1134 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1135 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1136 nsd->fd_atr_status = true;
1137 else
1138 nsd->fd_atr_status = false;
1139
41c445ff
JB		 1140 pf->stat_offsets_loaded = true;
1141}
1142
7812fddc
SN		 1143/**
1144 * i40e_update_stats - Update the various statistics counters.
1145 * @vsi: the VSI to be updated
1146 *
1147 * Update the various stats for this VSI and its related entities.
1148 **/
1149void i40e_update_stats(struct i40e_vsi *vsi)
1150{
1151 struct i40e_pf *pf = vsi->back;
1152
1153 if (vsi == pf->vsi[pf->lan_vsi])
1154 i40e_update_pf_stats(pf);
1155
1156 i40e_update_vsi_stats(vsi);
38e00438
VD		 1157#ifdef I40E_FCOE
1158 i40e_update_fcoe_stats(vsi);
1159#endif
7812fddc
SN		 1160}
1161
41c445ff
JB		 1162/**
1163 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1164 * @vsi: the VSI to be searched
1165 * @macaddr: the MAC address
1166 * @vlan: the vlan
b40c82e6 1167 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1168 * @is_netdev: make sure its a netdev filter, else doesn't matter
1169 *
1170 * Returns ptr to the filter object or NULL
1171 **/
1172static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1173 u8 *macaddr, s16 vlan,
1174 bool is_vf, bool is_netdev)
1175{
1176 struct i40e_mac_filter *f;
1177
1178 if (!vsi || !macaddr)
1179 return NULL;
1180
1181 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1182 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1183 (vlan == f->vlan) &&
1184 (!is_vf || f->is_vf) &&
1185 (!is_netdev || f->is_netdev))
1186 return f;
1187 }
1188 return NULL;
1189}
1190
1191/**
1192 * i40e_find_mac - Find a mac addr in the macvlan filters list
1193 * @vsi: the VSI to be searched
1194 * @macaddr: the MAC address we are searching for
b40c82e6 1195 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1196 * @is_netdev: make sure its a netdev filter, else doesn't matter
1197 *
1198 * Returns the first filter with the provided MAC address or NULL if
1199 * MAC address was not found
1200 **/
1201struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1202 bool is_vf, bool is_netdev)
1203{
1204 struct i40e_mac_filter *f;
1205
1206 if (!vsi || !macaddr)
1207 return NULL;
1208
1209 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1210 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1211 (!is_vf || f->is_vf) &&
1212 (!is_netdev || f->is_netdev))
1213 return f;
1214 }
1215 return NULL;
1216}
1217
1218/**
1219 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1220 * @vsi: the VSI to be searched
1221 *
1222 * Returns true if VSI is in vlan mode or false otherwise
1223 **/
1224bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1225{
1226 struct i40e_mac_filter *f;
1227
1228 /* Only -1 for all the filters denotes not in vlan mode
1229 * so we have to go through all the list in order to make sure
1230 */
1231 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1232 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1233 return true;
1234 }
1235
1236 return false;
1237}
1238
1239/**
1240 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1241 * @vsi: the VSI to be searched
1242 * @macaddr: the mac address to be filtered
b40c82e6 1243 * @is_vf: true if it is a VF
41c445ff
JB		 1244 * @is_netdev: true if it is a netdev
1245 *
1246 * Goes through all the macvlan filters and adds a
1247 * macvlan filter for each unique vlan that already exists
1248 *
1249 * Returns first filter found on success, else NULL
1250 **/
1251struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1252 bool is_vf, bool is_netdev)
1253{
1254 struct i40e_mac_filter *f;
1255
1256 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1257 if (vsi->info.pvid)
1258 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1259 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1260 is_vf, is_netdev)) {
1261 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1262 is_vf, is_netdev))
41c445ff
JB		 1263 return NULL;
1264 }
1265 }
1266
1267 return list_first_entry_or_null(&vsi->mac_filter_list,
1268 struct i40e_mac_filter, list);
1269}
1270
b36e9ab5
MW		 1271/**
1272 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1273 * @vsi: the VSI to be searched
1274 * @macaddr: the mac address to be removed
1275 * @is_vf: true if it is a VF
1276 * @is_netdev: true if it is a netdev
1277 *
1278 * Removes a given MAC address from a VSI, regardless of VLAN
1279 *
1280 * Returns 0 for success, or error
1281 **/
1282int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1283 bool is_vf, bool is_netdev)
1284{
1285 struct i40e_mac_filter *f = NULL;
1286 int changed = 0;
1287
1288 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1289 "Missing mac_filter_list_lock\n");
1290 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1291 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1292 (is_vf == f->is_vf) &&
1293 (is_netdev == f->is_netdev)) {
1294 f->counter--;
1295 f->changed = true;
1296 changed = 1;
1297 }
1298 }
1299 if (changed) {
1300 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1301 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1302 return 0;
1303 }
1304 return -ENOENT;
1305}
1306
8c27d42e
GR		 1307/**
1308 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1309 * @vsi: the PF Main VSI - inappropriate for any other VSI
1310 * @macaddr: the MAC address
30650cc5
SN		 1311 *
1312 * Some older firmware configurations set up a default promiscuous VLAN
1313 * filter that needs to be removed.
8c27d42e 1314 **/
30650cc5 1315static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1316{
1317 struct i40e_aqc_remove_macvlan_element_data element;
1318 struct i40e_pf *pf = vsi->back;
f1c7e72e 1319 i40e_status ret;
8c27d42e
GR		 1320
1321 /* Only appropriate for the PF main VSI */
1322 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1323 return -EINVAL;
8c27d42e 1324
30650cc5 1325 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1326 ether_addr_copy(element.mac_addr, macaddr);
1327 element.vlan_tag = 0;
1328 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1329 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1330 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1331 if (ret)
30650cc5
SN		 1332 return -ENOENT;
1333
1334 return 0;
8c27d42e
GR		 1335}
1336
41c445ff
JB		 1337/**
1338 * i40e_add_filter - Add a mac/vlan filter to the VSI
1339 * @vsi: the VSI to be searched
1340 * @macaddr: the MAC address
1341 * @vlan: the vlan
b40c82e6 1342 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1343 * @is_netdev: make sure its a netdev filter, else doesn't matter
1344 *
1345 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1346 *
1347 * NOTE: This function is expected to be called with mac_filter_list_lock
1348 * being held.
41c445ff
JB		 1349 **/
1350struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1351 u8 *macaddr, s16 vlan,
1352 bool is_vf, bool is_netdev)
1353{
1354 struct i40e_mac_filter *f;
1355
1356 if (!vsi || !macaddr)
1357 return NULL;
1358
1359 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1360 if (!f) {
1361 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1362 if (!f)
1363 goto add_filter_out;
1364
9a173901 1365 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1366 f->vlan = vlan;
1367 f->changed = true;
1368
1369 INIT_LIST_HEAD(&f->list);
04d5a21d 1370 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1371 }
1372
1373 /* increment counter and add a new flag if needed */
1374 if (is_vf) {
1375 if (!f->is_vf) {
1376 f->is_vf = true;
1377 f->counter++;
1378 }
1379 } else if (is_netdev) {
1380 if (!f->is_netdev) {
1381 f->is_netdev = true;
1382 f->counter++;
1383 }
1384 } else {
1385 f->counter++;
1386 }
1387
1388 /* changed tells sync_filters_subtask to
1389 * push the filter down to the firmware
1390 */
1391 if (f->changed) {
1392 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1393 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1394 }
1395
1396add_filter_out:
1397 return f;
1398}
1399
1400/**
1401 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1402 * @vsi: the VSI to be searched
1403 * @macaddr: the MAC address
1404 * @vlan: the vlan
b40c82e6 1405 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1406 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1407 *
1408 * NOTE: This function is expected to be called with mac_filter_list_lock
1409 * being held.
41c445ff
JB		 1410 **/
1411void i40e_del_filter(struct i40e_vsi *vsi,
1412 u8 *macaddr, s16 vlan,
1413 bool is_vf, bool is_netdev)
1414{
1415 struct i40e_mac_filter *f;
1416
1417 if (!vsi || !macaddr)
1418 return;
1419
1420 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1421 if (!f || f->counter == 0)
1422 return;
1423
1424 if (is_vf) {
1425 if (f->is_vf) {
1426 f->is_vf = false;
1427 f->counter--;
1428 }
1429 } else if (is_netdev) {
1430 if (f->is_netdev) {
1431 f->is_netdev = false;
1432 f->counter--;
1433 }
1434 } else {
b40c82e6 1435 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1436 int min_f = 0;
6995b36c 1437
41c445ff
JB		 1438 min_f += (f->is_vf ? 1 : 0);
1439 min_f += (f->is_netdev ? 1 : 0);
1440
1441 if (f->counter > min_f)
1442 f->counter--;
1443 }
1444
1445 /* counter == 0 tells sync_filters_subtask to
1446 * remove the filter from the firmware's list
1447 */
1448 if (f->counter == 0) {
1449 f->changed = true;
1450 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1451 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1452 }
1453}
1454
1455/**
1456 * i40e_set_mac - NDO callback to set mac address
1457 * @netdev: network interface device structure
1458 * @p: pointer to an address structure
1459 *
1460 * Returns 0 on success, negative on failure
1461 **/
38e00438
VD		 1462#ifdef I40E_FCOE
1463int i40e_set_mac(struct net_device *netdev, void *p)
1464#else
41c445ff 1465static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1466#endif
41c445ff
JB		 1467{
1468 struct i40e_netdev_priv *np = netdev_priv(netdev);
1469 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1470 struct i40e_pf *pf = vsi->back;
1471 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1472 struct sockaddr *addr = p;
1473 struct i40e_mac_filter *f;
1474
1475 if (!is_valid_ether_addr(addr->sa_data))
1476 return -EADDRNOTAVAIL;
1477
30650cc5
SN		 1478 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1479 netdev_info(netdev, "already using mac address %pM\n",
1480 addr->sa_data);
1481 return 0;
1482 }
41c445ff 1483
80f6428f
ASJ		 1484 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1485 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1486 return -EADDRNOTAVAIL;
1487
30650cc5
SN		 1488 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1489 netdev_info(netdev, "returning to hw mac address %pM\n",
1490 hw->mac.addr);
1491 else
1492 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1493
41c445ff
JB		 1494 if (vsi->type == I40E_VSI_MAIN) {
1495 i40e_status ret;
6995b36c 1496
41c445ff 1497 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1498 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1499 addr->sa_data, NULL);
1500 if (ret) {
1501 netdev_info(netdev,
1502 "Addr change for Main VSI failed: %d\n",
1503 ret);
1504 return -EADDRNOTAVAIL;
1505 }
41c445ff
JB		 1506 }
1507
30650cc5
SN		 1508 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1509 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1510
30650cc5
SN		 1511 memset(&element, 0, sizeof(element));
1512 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1513 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1514 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1515 } else {
21659035 1516 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1517 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1518 false, false);
21659035 1519 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1520 }
41c445ff 1521
30650cc5
SN		 1522 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1523 struct i40e_aqc_add_macvlan_element_data element;
1524
1525 memset(&element, 0, sizeof(element));
1526 ether_addr_copy(element.mac_addr, hw->mac.addr);
1527 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1528 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1529 } else {
21659035 1530 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1531 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1532 false, false);
1533 if (f)
1534 f->is_laa = true;
21659035 1535 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1536 }
1537
30650cc5 1538 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1539
c53934c6
JB		 1540 /* schedule our worker thread which will take care of
1541 * applying the new filter changes
1542 */
1543 i40e_service_event_schedule(vsi->back);
1544 return 0;
41c445ff
JB		 1545}
1546
1547/**
1548 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1549 * @vsi: the VSI being setup
1550 * @ctxt: VSI context structure
1551 * @enabled_tc: Enabled TCs bitmap
1552 * @is_add: True if called before Add VSI
1553 *
1554 * Setup VSI queue mapping for enabled traffic classes.
1555 **/
38e00438
VD		 1556#ifdef I40E_FCOE
1557void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1558 struct i40e_vsi_context *ctxt,
1559 u8 enabled_tc,
1560 bool is_add)
1561#else
41c445ff
JB		 1562static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1563 struct i40e_vsi_context *ctxt,
1564 u8 enabled_tc,
1565 bool is_add)
38e00438 1566#endif
41c445ff
JB		 1567{
1568 struct i40e_pf *pf = vsi->back;
1569 u16 sections = 0;
1570 u8 netdev_tc = 0;
1571 u16 numtc = 0;
1572 u16 qcount;
1573 u8 offset;
1574 u16 qmap;
1575 int i;
4e3b35b0 1576 u16 num_tc_qps = 0;
41c445ff
JB		 1577
1578 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1579 offset = 0;
1580
1581 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1582 /* Find numtc from enabled TC bitmap */
1583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1584 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1585 numtc++;
1586 }
1587 if (!numtc) {
1588 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1589 numtc = 1;
1590 }
1591 } else {
1592 /* At least TC0 is enabled in case of non-DCB case */
1593 numtc = 1;
1594 }
1595
1596 vsi->tc_config.numtc = numtc;
1597 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1598 /* Number of queues per enabled TC */
7f9ff476
AS		 1599 /* In MFP case we can have a much lower count of MSIx
1600 * vectors available and so we need to lower the used
1601 * q count.
1602 */
26cdc443
ASJ		 1603 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1604 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1605 else
1606 qcount = vsi->alloc_queue_pairs;
7f9ff476 1607 num_tc_qps = qcount / numtc;
e25d00b8 1608 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1609
1610 /* Setup queue offset/count for all TCs for given VSI */
1611 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1612 /* See if the given TC is enabled for the given VSI */
75f5cea9 1613 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1614 /* TC is enabled */
41c445ff
JB		 1615 int pow, num_qps;
1616
41c445ff
JB		 1617 switch (vsi->type) {
1618 case I40E_VSI_MAIN:
acd65448
HZ		 1619 qcount = min_t(int, pf->alloc_rss_size,
1620 num_tc_qps);
41c445ff 1621 break;
38e00438
VD		 1622#ifdef I40E_FCOE
1623 case I40E_VSI_FCOE:
1624 qcount = num_tc_qps;
1625 break;
1626#endif
41c445ff
JB		 1627 case I40E_VSI_FDIR:
1628 case I40E_VSI_SRIOV:
1629 case I40E_VSI_VMDQ2:
1630 default:
4e3b35b0 1631 qcount = num_tc_qps;
41c445ff
JB		 1632 WARN_ON(i != 0);
1633 break;
1634 }
4e3b35b0
NP		 1635 vsi->tc_config.tc_info[i].qoffset = offset;
1636 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1637
1e200e4a 1638 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1639 num_qps = qcount;
41c445ff 1640 pow = 0;
41a1d04b 1641 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1642 pow++;
1643 num_qps >>= 1;
1644 }
1645
1646 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1647 qmap =
1648 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1649 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1650
4e3b35b0 1651 offset += qcount;
41c445ff
JB		 1652 } else {
1653 /* TC is not enabled so set the offset to
1654 * default queue and allocate one queue
1655 * for the given TC.
1656 */
1657 vsi->tc_config.tc_info[i].qoffset = 0;
1658 vsi->tc_config.tc_info[i].qcount = 1;
1659 vsi->tc_config.tc_info[i].netdev_tc = 0;
1660
1661 qmap = 0;
1662 }
1663 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1664 }
1665
1666 /* Set actual Tx/Rx queue pairs */
1667 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1668 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1669 if (vsi->req_queue_pairs > 0)
1670 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1671 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1672 vsi->num_queue_pairs = pf->num_lan_msix;
1673 }
41c445ff
JB		 1674
1675 /* Scheduler section valid can only be set for ADD VSI */
1676 if (is_add) {
1677 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1678
1679 ctxt->info.up_enable_bits = enabled_tc;
1680 }
1681 if (vsi->type == I40E_VSI_SRIOV) {
1682 ctxt->info.mapping_flags |=
1683 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1684 for (i = 0; i < vsi->num_queue_pairs; i++)
1685 ctxt->info.queue_mapping[i] =
1686 cpu_to_le16(vsi->base_queue + i);
1687 } else {
1688 ctxt->info.mapping_flags |=
1689 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1690 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1691 }
1692 ctxt->info.valid_sections |= cpu_to_le16(sections);
1693}
1694
1695/**
1696 * i40e_set_rx_mode - NDO callback to set the netdev filters
1697 * @netdev: network interface device structure
1698 **/
38e00438
VD		 1699#ifdef I40E_FCOE
1700void i40e_set_rx_mode(struct net_device *netdev)
1701#else
41c445ff 1702static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1703#endif
41c445ff
JB		 1704{
1705 struct i40e_netdev_priv *np = netdev_priv(netdev);
1706 struct i40e_mac_filter *f, *ftmp;
1707 struct i40e_vsi *vsi = np->vsi;
1708 struct netdev_hw_addr *uca;
1709 struct netdev_hw_addr *mca;
1710 struct netdev_hw_addr *ha;
1711
21659035
KP		 1712 spin_lock_bh(&vsi->mac_filter_list_lock);
1713
41c445ff
JB		 1714 /* add addr if not already in the filter list */
1715 netdev_for_each_uc_addr(uca, netdev) {
1716 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1717 if (i40e_is_vsi_in_vlan(vsi))
1718 i40e_put_mac_in_vlan(vsi, uca->addr,
1719 false, true);
1720 else
1721 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1722 false, true);
1723 }
1724 }
1725
1726 netdev_for_each_mc_addr(mca, netdev) {
1727 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1728 if (i40e_is_vsi_in_vlan(vsi))
1729 i40e_put_mac_in_vlan(vsi, mca->addr,
1730 false, true);
1731 else
1732 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1733 false, true);
1734 }
1735 }
1736
1737 /* remove filter if not in netdev list */
1738 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1739
1740 if (!f->is_netdev)
1741 continue;
1742
2f41f335
SN		 1743 netdev_for_each_mc_addr(mca, netdev)
1744 if (ether_addr_equal(mca->addr, f->macaddr))
1745 goto bottom_of_search_loop;
41c445ff 1746
2f41f335
SN		 1747 netdev_for_each_uc_addr(uca, netdev)
1748 if (ether_addr_equal(uca->addr, f->macaddr))
1749 goto bottom_of_search_loop;
1750
1751 for_each_dev_addr(netdev, ha)
1752 if (ether_addr_equal(ha->addr, f->macaddr))
1753 goto bottom_of_search_loop;
1754
1755 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1756 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1757
1758bottom_of_search_loop:
1759 continue;
41c445ff 1760 }
21659035 1761 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1762
1763 /* check for other flag changes */
1764 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1765 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1766 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1767 }
c53934c6
JB		 1768
1769 /* schedule our worker thread which will take care of
1770 * applying the new filter changes
1771 */
1772 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1773}
1774
21659035
KP		 1775/**
1776 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1777 * @src: source MAC filter entry to be clones
1778 *
1779 * Returns the pointer to newly cloned MAC filter entry or NULL
1780 * in case of error
1781 **/
1782static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1783 struct i40e_mac_filter *src)
1784{
1785 struct i40e_mac_filter *f;
1786
1787 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1788 if (!f)
1789 return NULL;
1790 *f = *src;
1791
1792 INIT_LIST_HEAD(&f->list);
1793
1794 return f;
1795}
1796
1797/**
1798 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1799 * @vsi: pointer to vsi struct
1800 * @from: Pointer to list which contains MAC filter entries - changes to
1801 * those entries needs to be undone.
1802 *
1803 * MAC filter entries from list were slated to be removed from device.
1804 **/
1805static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1806 struct list_head *from)
1807{
1808 struct i40e_mac_filter *f, *ftmp;
1809
1810 list_for_each_entry_safe(f, ftmp, from, list) {
1811 f->changed = true;
1812 /* Move the element back into MAC filter list*/
1813 list_move_tail(&f->list, &vsi->mac_filter_list);
1814 }
1815}
1816
1817/**
1818 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1819 * @vsi: pointer to vsi struct
1820 *
1821 * MAC filter entries from list were slated to be added from device.
1822 **/
1823static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1824{
1825 struct i40e_mac_filter *f, *ftmp;
1826
1827 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1828 if (!f->changed && f->counter)
1829 f->changed = true;
1830 }
1831}
1832
1833/**
1834 * i40e_cleanup_add_list - Deletes the element from add list and release
1835 * memory
1836 * @add_list: Pointer to list which contains MAC filter entries
1837 **/
1838static void i40e_cleanup_add_list(struct list_head *add_list)
1839{
1840 struct i40e_mac_filter *f, *ftmp;
1841
1842 list_for_each_entry_safe(f, ftmp, add_list, list) {
1843 list_del(&f->list);
1844 kfree(f);
1845 }
1846}
1847
41c445ff
JB		 1848/**
1849 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1850 * @vsi: ptr to the VSI
1851 *
1852 * Push any outstanding VSI filter changes through the AdminQ.
1853 *
1854 * Returns 0 or error value
1855 **/
17652c63 1856int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1857{
21659035
KP		 1858 struct list_head tmp_del_list, tmp_add_list;
1859 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1860 bool promisc_forced_on = false;
1861 bool add_happened = false;
1862 int filter_list_len = 0;
1863 u32 changed_flags = 0;
ea02e90b 1864 i40e_status aq_ret = 0;
21659035 1865 bool err_cond = false;
ea02e90b 1866 int retval = 0;
41c445ff
JB		 1867 struct i40e_pf *pf;
1868 int num_add = 0;
1869 int num_del = 0;
f1c7e72e 1870 int aq_err = 0;
41c445ff
JB		 1871 u16 cmd_flags;
1872
1873 /* empty array typed pointers, kcalloc later */
1874 struct i40e_aqc_add_macvlan_element_data *add_list;
1875 struct i40e_aqc_remove_macvlan_element_data *del_list;
1876
1877 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1878 usleep_range(1000, 2000);
1879 pf = vsi->back;
1880
1881 if (vsi->netdev) {
1882 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1883 vsi->current_netdev_flags = vsi->netdev->flags;
1884 }
1885
21659035
KP		 1886 INIT_LIST_HEAD(&tmp_del_list);
1887 INIT_LIST_HEAD(&tmp_add_list);
1888
41c445ff
JB		 1889 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1890 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1891
21659035 1892 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1893 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1894 if (!f->changed)
1895 continue;
1896
1897 if (f->counter != 0)
1898 continue;
1899 f->changed = false;
21659035
KP		 1900
1901 /* Move the element into temporary del_list */
1902 list_move_tail(&f->list, &tmp_del_list);
1903 }
1904
1905 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1906 if (!f->changed)
1907 continue;
1908
1909 if (f->counter == 0)
1910 continue;
1911 f->changed = false;
1912
1913 /* Clone MAC filter entry and add into temporary list */
1914 fclone = i40e_mac_filter_entry_clone(f);
1915 if (!fclone) {
1916 err_cond = true;
1917 break;
1918 }
1919 list_add_tail(&fclone->list, &tmp_add_list);
1920 }
1921
1922 /* if failed to clone MAC filter entry - undo */
1923 if (err_cond) {
1924 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1925 i40e_undo_add_filter_entries(vsi);
1926 }
1927 spin_unlock_bh(&vsi->mac_filter_list_lock);
1928
ea02e90b 1929 if (err_cond) {
21659035 1930 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1931 retval = -ENOMEM;
1932 goto out;
1933 }
21659035
KP		 1934 }
1935
1936 /* Now process 'del_list' outside the lock */
1937 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1938 int del_list_size;
1939
21659035
KP		 1940 filter_list_len = pf->hw.aq.asq_buf_size /
1941 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1942 del_list_size = filter_list_len *
1943 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1944 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1945 if (!del_list) {
1946 i40e_cleanup_add_list(&tmp_add_list);
1947
1948 /* Undo VSI's MAC filter entry element updates */
1949 spin_lock_bh(&vsi->mac_filter_list_lock);
1950 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1951 i40e_undo_add_filter_entries(vsi);
1952 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1953 retval = -ENOMEM;
1954 goto out;
21659035
KP		 1955 }
1956
1957 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1958 cmd_flags = 0;
1959
1960 /* add to delete list */
9a173901 1961 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1962 del_list[num_del].vlan_tag =
1963 cpu_to_le16((u16)(f->vlan ==
1964 I40E_VLAN_ANY ? 0 : f->vlan));
1965
41c445ff
JB		 1966 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1967 del_list[num_del].flags = cmd_flags;
1968 num_del++;
1969
41c445ff
JB		 1970 /* flush a full buffer */
1971 if (num_del == filter_list_len) {
ea02e90b
MW		 1972 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1973 vsi->seid,
1974 del_list,
1975 num_del,
1976 NULL);
f1c7e72e 1977 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1978 num_del = 0;
f1199998 1979 memset(del_list, 0, del_list_size);
41c445ff 1980
ea02e90b
MW		 1981 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1982 retval = -EIO;
21659035
KP		 1983 dev_err(&pf->pdev->dev,
1984 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1985 i40e_stat_str(&pf->hw, aq_ret),
21659035 1986 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1987 }
41c445ff 1988 }
21659035
KP		 1989 /* Release memory for MAC filter entries which were
1990 * synced up with HW.
1991 */
1992 list_del(&f->list);
1993 kfree(f);
41c445ff 1994 }
21659035 1995
41c445ff 1996 if (num_del) {
ea02e90b
MW		 1997 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1998 del_list, num_del,
1999 NULL);
f1c7e72e 2000 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2001 num_del = 0;
2002
ea02e90b 2003 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 2004 dev_info(&pf->pdev->dev,
f1c7e72e 2005 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 2006 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2007 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2008 }
2009
2010 kfree(del_list);
2011 del_list = NULL;
21659035
KP		 2012 }
2013
2014 if (!list_empty(&tmp_add_list)) {
f1199998 2015 int add_list_size;
41c445ff
JB		 2016
2017 /* do all the adds now */
2018 filter_list_len = pf->hw.aq.asq_buf_size /
2019 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2020 add_list_size = filter_list_len *
2021 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2022 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2023 if (!add_list) {
2024 /* Purge element from temporary lists */
2025 i40e_cleanup_add_list(&tmp_add_list);
2026
2027 /* Undo add filter entries from VSI MAC filter list */
2028 spin_lock_bh(&vsi->mac_filter_list_lock);
2029 i40e_undo_add_filter_entries(vsi);
2030 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2031 retval = -ENOMEM;
2032 goto out;
21659035 2033 }
41c445ff 2034
21659035 2035 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2036
41c445ff
JB		 2037 add_happened = true;
2038 cmd_flags = 0;
2039
2040 /* add to add array */
9a173901 2041 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2042 add_list[num_add].vlan_tag =
2043 cpu_to_le16(
2044 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2045 add_list[num_add].queue_number = 0;
2046
2047 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2048 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2049 num_add++;
2050
2051 /* flush a full buffer */
2052 if (num_add == filter_list_len) {
ea02e90b
MW		 2053 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2054 add_list, num_add,
2055 NULL);
f1c7e72e 2056 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2057 num_add = 0;
2058
ea02e90b 2059 if (aq_ret)
41c445ff 2060 break;
f1199998 2061 memset(add_list, 0, add_list_size);
41c445ff 2062 }
21659035
KP		 2063 /* Entries from tmp_add_list were cloned from MAC
2064 * filter list, hence clean those cloned entries
2065 */
2066 list_del(&f->list);
2067 kfree(f);
41c445ff 2068 }
21659035 2069
41c445ff 2070 if (num_add) {
ea02e90b
MW		 2071 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2072 add_list, num_add, NULL);
f1c7e72e 2073 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2074 num_add = 0;
2075 }
2076 kfree(add_list);
2077 add_list = NULL;
2078
ea02e90b
MW		 2079 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2080 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2081 dev_info(&pf->pdev->dev,
f1c7e72e 2082 "add filter failed, err %s aq_err %s\n",
ea02e90b 2083 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2084 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2085 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2086 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2087 &vsi->state)) {
2088 promisc_forced_on = true;
2089 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2090 &vsi->state);
2091 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2092 }
2093 }
2094 }
2095
2096 /* check for changes in promiscuous modes */
2097 if (changed_flags & IFF_ALLMULTI) {
2098 bool cur_multipromisc;
6995b36c 2099
41c445ff 2100 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2101 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2102 vsi->seid,
2103 cur_multipromisc,
2104 NULL);
2105 if (aq_ret) {
2106 retval = i40e_aq_rc_to_posix(aq_ret,
2107 pf->hw.aq.asq_last_status);
41c445ff 2108 dev_info(&pf->pdev->dev,
f1c7e72e 2109 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2110 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2111 i40e_aq_str(&pf->hw,
2112 pf->hw.aq.asq_last_status));
ea02e90b 2113 }
41c445ff
JB		 2114 }
2115 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2116 bool cur_promisc;
6995b36c 2117
41c445ff
JB		 2118 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2119 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2120 &vsi->state));
92faef85
ASJ		 2121 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2122 /* set defport ON for Main VSI instead of true promisc
2123 * this way we will get all unicast/multicast and VLAN
2124 * promisc behavior but will not get VF or VMDq traffic
2125 * replicated on the Main VSI.
2126 */
2127 if (pf->cur_promisc != cur_promisc) {
2128 pf->cur_promisc = cur_promisc;
0e4425ed 2129 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2130 }
2131 } else {
ea02e90b 2132 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2133 &vsi->back->hw,
f1c7e72e
SN		 2134 vsi->seid,
2135 cur_promisc, NULL);
ea02e90b
MW		 2136 if (aq_ret) {
2137 retval =
2138 i40e_aq_rc_to_posix(aq_ret,
2139 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2140 dev_info(&pf->pdev->dev,
2141 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2142 aq_ret, pf->hw.aq.asq_last_status);
2143 }
2144 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2145 &vsi->back->hw,
2146 vsi->seid,
2147 cur_promisc, NULL);
ea02e90b
MW		 2148 if (aq_ret) {
2149 retval =
2150 i40e_aq_rc_to_posix(aq_ret,
2151 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2152 dev_info(&pf->pdev->dev,
2153 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2154 aq_ret, pf->hw.aq.asq_last_status);
2155 }
92faef85 2156 }
ea02e90b
MW		 2157 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2158 vsi->seid,
2159 cur_promisc, NULL);
2160 if (aq_ret) {
2161 retval = i40e_aq_rc_to_posix(aq_ret,
2162 pf->hw.aq.asq_last_status);
1a10370a 2163 dev_info(&pf->pdev->dev,
f1c7e72e 2164 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2165 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2166 i40e_aq_str(&pf->hw,
2167 pf->hw.aq.asq_last_status));
ea02e90b 2168 }
41c445ff 2169 }
ea02e90b 2170out:
2818ccd9
JB		 2171 /* if something went wrong then set the changed flag so we try again */
2172 if (retval)
2173 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2174
41c445ff 2175 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2176 return retval;
41c445ff
JB		 2177}
2178
2179/**
2180 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2181 * @pf: board private structure
2182 **/
2183static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2184{
2185 int v;
2186
2187 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2188 return;
2189 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2190
505682cd 2191 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2192 if (pf->vsi[v] &&
17652c63
JB		 2193 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2194 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2195
2196 if (ret) {
2197 /* come back and try again later */
2198 pf->flags |= I40E_FLAG_FILTER_SYNC;
2199 break;
2200 }
2201 }
41c445ff
JB		 2202 }
2203}
2204
2205/**
2206 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2207 * @netdev: network interface device structure
2208 * @new_mtu: new value for maximum frame size
2209 *
2210 * Returns 0 on success, negative on failure
2211 **/
2212static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2213{
2214 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2215 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2216 struct i40e_vsi *vsi = np->vsi;
2217
2218 /* MTU < 68 is an error and causes problems on some kernels */
2219 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2220 return -EINVAL;
2221
2222 netdev_info(netdev, "changing MTU from %d to %d\n",
2223 netdev->mtu, new_mtu);
2224 netdev->mtu = new_mtu;
2225 if (netif_running(netdev))
2226 i40e_vsi_reinit_locked(vsi);
2227
2228 return 0;
2229}
2230
beb0dff1
JK		 2231/**
2232 * i40e_ioctl - Access the hwtstamp interface
2233 * @netdev: network interface device structure
2234 * @ifr: interface request data
2235 * @cmd: ioctl command
2236 **/
2237int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2238{
2239 struct i40e_netdev_priv *np = netdev_priv(netdev);
2240 struct i40e_pf *pf = np->vsi->back;
2241
2242 switch (cmd) {
2243 case SIOCGHWTSTAMP:
2244 return i40e_ptp_get_ts_config(pf, ifr);
2245 case SIOCSHWTSTAMP:
2246 return i40e_ptp_set_ts_config(pf, ifr);
2247 default:
2248 return -EOPNOTSUPP;
2249 }
2250}
2251
41c445ff
JB		 2252/**
2253 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2254 * @vsi: the vsi being adjusted
2255 **/
2256void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2257{
2258 struct i40e_vsi_context ctxt;
2259 i40e_status ret;
2260
2261 if ((vsi->info.valid_sections &
2262 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2263 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2264 return; /* already enabled */
2265
2266 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2267 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2268 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2269
2270 ctxt.seid = vsi->seid;
1a2f6248 2271 ctxt.info = vsi->info;
41c445ff
JB		 2272 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2273 if (ret) {
2274 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2275 "update vlan stripping failed, err %s aq_err %s\n",
2276 i40e_stat_str(&vsi->back->hw, ret),
2277 i40e_aq_str(&vsi->back->hw,
2278 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2279 }
2280}
2281
2282/**
2283 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2284 * @vsi: the vsi being adjusted
2285 **/
2286void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2287{
2288 struct i40e_vsi_context ctxt;
2289 i40e_status ret;
2290
2291 if ((vsi->info.valid_sections &
2292 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2293 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2294 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2295 return; /* already disabled */
2296
2297 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2298 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2299 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2300
2301 ctxt.seid = vsi->seid;
1a2f6248 2302 ctxt.info = vsi->info;
41c445ff
JB		 2303 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2304 if (ret) {
2305 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2306 "update vlan stripping failed, err %s aq_err %s\n",
2307 i40e_stat_str(&vsi->back->hw, ret),
2308 i40e_aq_str(&vsi->back->hw,
2309 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2310 }
2311}
2312
2313/**
2314 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2315 * @netdev: network interface to be adjusted
2316 * @features: netdev features to test if VLAN offload is enabled or not
2317 **/
2318static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2319{
2320 struct i40e_netdev_priv *np = netdev_priv(netdev);
2321 struct i40e_vsi *vsi = np->vsi;
2322
2323 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2324 i40e_vlan_stripping_enable(vsi);
2325 else
2326 i40e_vlan_stripping_disable(vsi);
2327}
2328
2329/**
2330 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2331 * @vsi: the vsi being configured
2332 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2333 **/
2334int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2335{
2336 struct i40e_mac_filter *f, *add_f;
2337 bool is_netdev, is_vf;
41c445ff
JB		 2338
2339 is_vf = (vsi->type == I40E_VSI_SRIOV);
2340 is_netdev = !!(vsi->netdev);
2341
21659035
KP		 2342 /* Locked once because all functions invoked below iterates list*/
2343 spin_lock_bh(&vsi->mac_filter_list_lock);
2344
41c445ff
JB		 2345 if (is_netdev) {
2346 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2347 is_vf, is_netdev);
2348 if (!add_f) {
2349 dev_info(&vsi->back->pdev->dev,
2350 "Could not add vlan filter %d for %pM\n",
2351 vid, vsi->netdev->dev_addr);
21659035 2352 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2353 return -ENOMEM;
2354 }
2355 }
2356
2357 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2358 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2359 if (!add_f) {
2360 dev_info(&vsi->back->pdev->dev,
2361 "Could not add vlan filter %d for %pM\n",
2362 vid, f->macaddr);
21659035 2363 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2364 return -ENOMEM;
2365 }
2366 }
2367
41c445ff
JB		 2368 /* Now if we add a vlan tag, make sure to check if it is the first
2369 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2370 * with 0, so we now accept untagged and specified tagged traffic
2371 * (and not any taged and untagged)
2372 */
2373 if (vid > 0) {
2374 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2375 I40E_VLAN_ANY,
2376 is_vf, is_netdev)) {
2377 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2378 I40E_VLAN_ANY, is_vf, is_netdev);
2379 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2380 is_vf, is_netdev);
2381 if (!add_f) {
2382 dev_info(&vsi->back->pdev->dev,
2383 "Could not add filter 0 for %pM\n",
2384 vsi->netdev->dev_addr);
21659035 2385 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2386 return -ENOMEM;
2387 }
2388 }
8d82a7c5 2389 }
41c445ff 2390
8d82a7c5
GR		 2391 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2392 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2393 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2394 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2395 is_vf, is_netdev))
2396 continue;
2397 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2398 is_vf, is_netdev);
2399 add_f = i40e_add_filter(vsi, f->macaddr,
2400 0, is_vf, is_netdev);
2401 if (!add_f) {
2402 dev_info(&vsi->back->pdev->dev,
2403 "Could not add filter 0 for %pM\n",
2404 f->macaddr);
2405 spin_unlock_bh(&vsi->mac_filter_list_lock);
2406 return -ENOMEM;
41c445ff
JB		 2407 }
2408 }
41c445ff
JB		 2409 }
2410
21659035
KP		 2411 spin_unlock_bh(&vsi->mac_filter_list_lock);
2412
0e4425ed
JB		 2413 /* schedule our worker thread which will take care of
2414 * applying the new filter changes
2415 */
2416 i40e_service_event_schedule(vsi->back);
2417 return 0;
41c445ff
JB		 2418}
2419
2420/**
2421 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2422 * @vsi: the vsi being configured
2423 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2424 *
2425 * Return: 0 on success or negative otherwise
41c445ff
JB		 2426 **/
2427int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2428{
2429 struct net_device *netdev = vsi->netdev;
2430 struct i40e_mac_filter *f, *add_f;
2431 bool is_vf, is_netdev;
2432 int filter_count = 0;
41c445ff
JB		 2433
2434 is_vf = (vsi->type == I40E_VSI_SRIOV);
2435 is_netdev = !!(netdev);
2436
21659035
KP		 2437 /* Locked once because all functions invoked below iterates list */
2438 spin_lock_bh(&vsi->mac_filter_list_lock);
2439
41c445ff
JB		 2440 if (is_netdev)
2441 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2442
2443 list_for_each_entry(f, &vsi->mac_filter_list, list)
2444 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2445
41c445ff
JB		 2446 /* go through all the filters for this VSI and if there is only
2447 * vid == 0 it means there are no other filters, so vid 0 must
2448 * be replaced with -1. This signifies that we should from now
2449 * on accept any traffic (with any tag present, or untagged)
2450 */
2451 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2452 if (is_netdev) {
2453 if (f->vlan &&
2454 ether_addr_equal(netdev->dev_addr, f->macaddr))
2455 filter_count++;
2456 }
2457
2458 if (f->vlan)
2459 filter_count++;
2460 }
2461
2462 if (!filter_count && is_netdev) {
2463 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2464 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2465 is_vf, is_netdev);
2466 if (!f) {
2467 dev_info(&vsi->back->pdev->dev,
2468 "Could not add filter %d for %pM\n",
2469 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2470 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2471 return -ENOMEM;
2472 }
2473 }
2474
2475 if (!filter_count) {
2476 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2477 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2478 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2479 is_vf, is_netdev);
41c445ff
JB		 2480 if (!add_f) {
2481 dev_info(&vsi->back->pdev->dev,
2482 "Could not add filter %d for %pM\n",
2483 I40E_VLAN_ANY, f->macaddr);
21659035 2484 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2485 return -ENOMEM;
2486 }
2487 }
2488 }
2489
21659035
KP		 2490 spin_unlock_bh(&vsi->mac_filter_list_lock);
2491
0e4425ed
JB		 2492 /* schedule our worker thread which will take care of
2493 * applying the new filter changes
2494 */
2495 i40e_service_event_schedule(vsi->back);
2496 return 0;
41c445ff
JB		 2497}
2498
2499/**
2500 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2501 * @netdev: network interface to be adjusted
2502 * @vid: vlan id to be added
078b5876
JB		 2503 *
2504 * net_device_ops implementation for adding vlan ids
41c445ff 2505 **/
38e00438
VD		 2506#ifdef I40E_FCOE
2507int i40e_vlan_rx_add_vid(struct net_device *netdev,
2508 __always_unused __be16 proto, u16 vid)
2509#else
41c445ff
JB		 2510static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2511 __always_unused __be16 proto, u16 vid)
38e00438 2512#endif
41c445ff
JB		 2513{
2514 struct i40e_netdev_priv *np = netdev_priv(netdev);
2515 struct i40e_vsi *vsi = np->vsi;
078b5876 2516 int ret = 0;
41c445ff
JB		 2517
2518 if (vid > 4095)
078b5876
JB		 2519 return -EINVAL;
2520
2521 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2522
6982d429
ASJ		 2523 /* If the network stack called us with vid = 0 then
2524 * it is asking to receive priority tagged packets with
2525 * vlan id 0. Our HW receives them by default when configured
2526 * to receive untagged packets so there is no need to add an
2527 * extra filter for vlan 0 tagged packets.
41c445ff 2528 */
6982d429
ASJ		 2529 if (vid)
2530 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2531
078b5876
JB		 2532 if (!ret && (vid < VLAN_N_VID))
2533 set_bit(vid, vsi->active_vlans);
41c445ff 2534
078b5876 2535 return ret;
41c445ff
JB		 2536}
2537
2538/**
2539 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2540 * @netdev: network interface to be adjusted
2541 * @vid: vlan id to be removed
078b5876 2542 *
fdfd943e 2543 * net_device_ops implementation for removing vlan ids
41c445ff 2544 **/
38e00438
VD		 2545#ifdef I40E_FCOE
2546int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2547 __always_unused __be16 proto, u16 vid)
2548#else
41c445ff
JB		 2549static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2550 __always_unused __be16 proto, u16 vid)
38e00438 2551#endif
41c445ff
JB		 2552{
2553 struct i40e_netdev_priv *np = netdev_priv(netdev);
2554 struct i40e_vsi *vsi = np->vsi;
2555
078b5876
JB		 2556 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2557
41c445ff
JB		 2558 /* return code is ignored as there is nothing a user
2559 * can do about failure to remove and a log message was
078b5876 2560 * already printed from the other function
41c445ff
JB		 2561 */
2562 i40e_vsi_kill_vlan(vsi, vid);
2563
2564 clear_bit(vid, vsi->active_vlans);
078b5876 2565
41c445ff
JB		 2566 return 0;
2567}
2568
2569/**
2570 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2571 * @vsi: the vsi being brought back up
2572 **/
2573static void i40e_restore_vlan(struct i40e_vsi *vsi)
2574{
2575 u16 vid;
2576
2577 if (!vsi->netdev)
2578 return;
2579
2580 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2581
2582 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2583 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2584 vid);
2585}
2586
2587/**
2588 * i40e_vsi_add_pvid - Add pvid for the VSI
2589 * @vsi: the vsi being adjusted
2590 * @vid: the vlan id to set as a PVID
2591 **/
dcae29be 2592int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2593{
2594 struct i40e_vsi_context ctxt;
f1c7e72e 2595 i40e_status ret;
41c445ff
JB		 2596
2597 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2598 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2599 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2600 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2601 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2602
2603 ctxt.seid = vsi->seid;
1a2f6248 2604 ctxt.info = vsi->info;
f1c7e72e
SN		 2605 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2606 if (ret) {
41c445ff 2607 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2608 "add pvid failed, err %s aq_err %s\n",
2609 i40e_stat_str(&vsi->back->hw, ret),
2610 i40e_aq_str(&vsi->back->hw,
2611 vsi->back->hw.aq.asq_last_status));
dcae29be 2612 return -ENOENT;
41c445ff
JB		 2613 }
2614
dcae29be 2615 return 0;
41c445ff
JB		 2616}
2617
2618/**
2619 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2620 * @vsi: the vsi being adjusted
2621 *
2622 * Just use the vlan_rx_register() service to put it back to normal
2623 **/
2624void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2625{
6c12fcbf
GR		 2626 i40e_vlan_stripping_disable(vsi);
2627
41c445ff 2628 vsi->info.pvid = 0;
41c445ff
JB		 2629}
2630
2631/**
2632 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2633 * @vsi: ptr to the VSI
2634 *
2635 * If this function returns with an error, then it's possible one or
2636 * more of the rings is populated (while the rest are not). It is the
2637 * callers duty to clean those orphaned rings.
2638 *
2639 * Return 0 on success, negative on failure
2640 **/
2641static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2642{
2643 int i, err = 0;
2644
2645 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2646 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2647
2648 return err;
2649}
2650
2651/**
2652 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2653 * @vsi: ptr to the VSI
2654 *
2655 * Free VSI's transmit software resources
2656 **/
2657static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2658{
2659 int i;
2660
8e9dca53
GR		 2661 if (!vsi->tx_rings)
2662 return;
2663
41c445ff 2664 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2665 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2666 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2667}
2668
2669/**
2670 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2671 * @vsi: ptr to the VSI
2672 *
2673 * If this function returns with an error, then it's possible one or
2674 * more of the rings is populated (while the rest are not). It is the
2675 * callers duty to clean those orphaned rings.
2676 *
2677 * Return 0 on success, negative on failure
2678 **/
2679static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2680{
2681 int i, err = 0;
2682
2683 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2684 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2685#ifdef I40E_FCOE
2686 i40e_fcoe_setup_ddp_resources(vsi);
2687#endif
41c445ff
JB		 2688 return err;
2689}
2690
2691/**
2692 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2693 * @vsi: ptr to the VSI
2694 *
2695 * Free all receive software resources
2696 **/
2697static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2698{
2699 int i;
2700
8e9dca53
GR		 2701 if (!vsi->rx_rings)
2702 return;
2703
41c445ff 2704 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2705 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2706 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2707#ifdef I40E_FCOE
2708 i40e_fcoe_free_ddp_resources(vsi);
2709#endif
41c445ff
JB		 2710}
2711
3ffa037d
NP		 2712/**
2713 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2714 * @ring: The Tx ring to configure
2715 *
2716 * This enables/disables XPS for a given Tx descriptor ring
2717 * based on the TCs enabled for the VSI that ring belongs to.
2718 **/
2719static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2720{
2721 struct i40e_vsi *vsi = ring->vsi;
2722 cpumask_var_t mask;
2723
9a660eea
JB		 2724 if (!ring->q_vector || !ring->netdev)
2725 return;
2726
2727 /* Single TC mode enable XPS */
2728 if (vsi->tc_config.numtc <= 1) {
2729 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2730 netif_set_xps_queue(ring->netdev,
2731 &ring->q_vector->affinity_mask,
2732 ring->queue_index);
9a660eea
JB		 2733 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2734 /* Disable XPS to allow selection based on TC */
2735 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2736 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2737 free_cpumask_var(mask);
3ffa037d 2738 }
0e4425ed
JB		 2739
2740 /* schedule our worker thread which will take care of
2741 * applying the new filter changes
2742 */
2743 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2744}
2745
41c445ff
JB		 2746/**
2747 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2748 * @ring: The Tx ring to configure
2749 *
2750 * Configure the Tx descriptor ring in the HMC context.
2751 **/
2752static int i40e_configure_tx_ring(struct i40e_ring *ring)
2753{
2754 struct i40e_vsi *vsi = ring->vsi;
2755 u16 pf_q = vsi->base_queue + ring->queue_index;
2756 struct i40e_hw *hw = &vsi->back->hw;
2757 struct i40e_hmc_obj_txq tx_ctx;
2758 i40e_status err = 0;
2759 u32 qtx_ctl = 0;
2760
2761 /* some ATR related tx ring init */
60ea5f83 2762 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2763 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2764 ring->atr_count = 0;
2765 } else {
2766 ring->atr_sample_rate = 0;
2767 }
2768
3ffa037d
NP		 2769 /* configure XPS */
2770 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2771
2772 /* clear the context structure first */
2773 memset(&tx_ctx, 0, sizeof(tx_ctx));
2774
2775 tx_ctx.new_context = 1;
2776 tx_ctx.base = (ring->dma / 128);
2777 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2778 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2779 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2780#ifdef I40E_FCOE
2781 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2782#endif
beb0dff1 2783 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2784 /* FDIR VSI tx ring can still use RS bit and writebacks */
2785 if (vsi->type != I40E_VSI_FDIR)
2786 tx_ctx.head_wb_ena = 1;
2787 tx_ctx.head_wb_addr = ring->dma +
2788 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2789
2790 /* As part of VSI creation/update, FW allocates certain
2791 * Tx arbitration queue sets for each TC enabled for
2792 * the VSI. The FW returns the handles to these queue
2793 * sets as part of the response buffer to Add VSI,
2794 * Update VSI, etc. AQ commands. It is expected that
2795 * these queue set handles be associated with the Tx
2796 * queues by the driver as part of the TX queue context
2797 * initialization. This has to be done regardless of
2798 * DCB as by default everything is mapped to TC0.
2799 */
2800 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2801 tx_ctx.rdylist_act = 0;
2802
2803 /* clear the context in the HMC */
2804 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2805 if (err) {
2806 dev_info(&vsi->back->pdev->dev,
2807 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2808 ring->queue_index, pf_q, err);
2809 return -ENOMEM;
2810 }
2811
2812 /* set the context in the HMC */
2813 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2814 if (err) {
2815 dev_info(&vsi->back->pdev->dev,
2816 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2817 ring->queue_index, pf_q, err);
2818 return -ENOMEM;
2819 }
2820
2821 /* Now associate this queue with this PCI function */
7a28d885 2822 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2823 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2824 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2825 I40E_QTX_CTL_VFVM_INDX_MASK;
2826 } else {
9d8bf547 2827 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2828 }
2829
13fd9774
SN		 2830 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2831 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2832 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2833 i40e_flush(hw);
2834
41c445ff
JB		 2835 /* cache tail off for easier writes later */
2836 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2837
2838 return 0;
2839}
2840
2841/**
2842 * i40e_configure_rx_ring - Configure a receive ring context
2843 * @ring: The Rx ring to configure
2844 *
2845 * Configure the Rx descriptor ring in the HMC context.
2846 **/
2847static int i40e_configure_rx_ring(struct i40e_ring *ring)
2848{
2849 struct i40e_vsi *vsi = ring->vsi;
2850 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2851 u16 pf_q = vsi->base_queue + ring->queue_index;
2852 struct i40e_hw *hw = &vsi->back->hw;
2853 struct i40e_hmc_obj_rxq rx_ctx;
2854 i40e_status err = 0;
2855
2856 ring->state = 0;
2857
2858 /* clear the context structure first */
2859 memset(&rx_ctx, 0, sizeof(rx_ctx));
2860
2861 ring->rx_buf_len = vsi->rx_buf_len;
2862 ring->rx_hdr_len = vsi->rx_hdr_len;
2863
2864 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2865 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2866
2867 rx_ctx.base = (ring->dma / 128);
2868 rx_ctx.qlen = ring->count;
2869
2870 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2871 set_ring_16byte_desc_enabled(ring);
2872 rx_ctx.dsize = 0;
2873 } else {
2874 rx_ctx.dsize = 1;
2875 }
2876
2877 rx_ctx.dtype = vsi->dtype;
2878 if (vsi->dtype) {
2879 set_ring_ps_enabled(ring);
2880 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2881 I40E_RX_SPLIT_IP |
2882 I40E_RX_SPLIT_TCP_UDP |
2883 I40E_RX_SPLIT_SCTP;
2884 } else {
2885 rx_ctx.hsplit_0 = 0;
2886 }
2887
2888 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2889 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2890 if (hw->revision_id == 0)
2891 rx_ctx.lrxqthresh = 0;
2892 else
2893 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2894 rx_ctx.crcstrip = 1;
2895 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2896 /* this controls whether VLAN is stripped from inner headers */
2897 rx_ctx.showiv = 0;
38e00438
VD		 2898#ifdef I40E_FCOE
2899 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2900#endif
acb3676b
CS		 2901 /* set the prefena field to 1 because the manual says to */
2902 rx_ctx.prefena = 1;
41c445ff
JB		 2903
2904 /* clear the context in the HMC */
2905 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2906 if (err) {
2907 dev_info(&vsi->back->pdev->dev,
2908 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2909 ring->queue_index, pf_q, err);
2910 return -ENOMEM;
2911 }
2912
2913 /* set the context in the HMC */
2914 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2915 if (err) {
2916 dev_info(&vsi->back->pdev->dev,
2917 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2918 ring->queue_index, pf_q, err);
2919 return -ENOMEM;
2920 }
2921
2922 /* cache tail for quicker writes, and clear the reg before use */
2923 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2924 writel(0, ring->tail);
2925
a132af24
MW		 2926 if (ring_is_ps_enabled(ring)) {
2927 i40e_alloc_rx_headers(ring);
2928 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2929 } else {
2930 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2931 }
41c445ff
JB		 2932
2933 return 0;
2934}
2935
2936/**
2937 * i40e_vsi_configure_tx - Configure the VSI for Tx
2938 * @vsi: VSI structure describing this set of rings and resources
2939 *
2940 * Configure the Tx VSI for operation.
2941 **/
2942static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2943{
2944 int err = 0;
2945 u16 i;
2946
9f65e15b
AD		 2947 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2948 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2949
2950 return err;
2951}
2952
2953/**
2954 * i40e_vsi_configure_rx - Configure the VSI for Rx
2955 * @vsi: the VSI being configured
2956 *
2957 * Configure the Rx VSI for operation.
2958 **/
2959static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2960{
2961 int err = 0;
2962 u16 i;
2963
2964 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2965 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2966 + ETH_FCS_LEN + VLAN_HLEN;
2967 else
2968 vsi->max_frame = I40E_RXBUFFER_2048;
2969
2970 /* figure out correct receive buffer length */
2971 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2972 I40E_FLAG_RX_PS_ENABLED)) {
2973 case I40E_FLAG_RX_1BUF_ENABLED:
2974 vsi->rx_hdr_len = 0;
2975 vsi->rx_buf_len = vsi->max_frame;
2976 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2977 break;
2978 case I40E_FLAG_RX_PS_ENABLED:
2979 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2980 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2981 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2982 break;
2983 default:
2984 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2985 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2986 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2987 break;
2988 }
2989
38e00438
VD		 2990#ifdef I40E_FCOE
2991 /* setup rx buffer for FCoE */
2992 if ((vsi->type == I40E_VSI_FCOE) &&
2993 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2994 vsi->rx_hdr_len = 0;
2995 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2996 vsi->max_frame = I40E_RXBUFFER_3072;
2997 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2998 }
2999
3000#endif /* I40E_FCOE */
41c445ff
JB		 3001 /* round up for the chip's needs */
3002 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 3003 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 3004 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 3005 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 3006
3007 /* set up individual rings */
3008 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 3009 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3010
3011 return err;
3012}
3013
3014/**
3015 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
3016 * @vsi: ptr to the VSI
3017 **/
3018static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3019{
e7046ee1 3020 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3021 u16 qoffset, qcount;
3022 int i, n;
3023
cd238a3e
PN		 3024 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3025 /* Reset the TC information */
3026 for (i = 0; i < vsi->num_queue_pairs; i++) {
3027 rx_ring = vsi->rx_rings[i];
3028 tx_ring = vsi->tx_rings[i];
3029 rx_ring->dcb_tc = 0;
3030 tx_ring->dcb_tc = 0;
3031 }
3032 }
41c445ff
JB		 3033
3034 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3035 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3036 continue;
3037
3038 qoffset = vsi->tc_config.tc_info[n].qoffset;
3039 qcount = vsi->tc_config.tc_info[n].qcount;
3040 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3041 rx_ring = vsi->rx_rings[i];
3042 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3043 rx_ring->dcb_tc = n;
3044 tx_ring->dcb_tc = n;
3045 }
3046 }
3047}
3048
3049/**
3050 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3051 * @vsi: ptr to the VSI
3052 **/
3053static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3054{
3055 if (vsi->netdev)
3056 i40e_set_rx_mode(vsi->netdev);
3057}
3058
17a73f6b
JG		 3059/**
3060 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3061 * @vsi: Pointer to the targeted VSI
3062 *
3063 * This function replays the hlist on the hw where all the SB Flow Director
3064 * filters were saved.
3065 **/
3066static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3067{
3068 struct i40e_fdir_filter *filter;
3069 struct i40e_pf *pf = vsi->back;
3070 struct hlist_node *node;
3071
55a5e60b
ASJ		 3072 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3073 return;
3074
17a73f6b
JG		 3075 hlist_for_each_entry_safe(filter, node,
3076 &pf->fdir_filter_list, fdir_node) {
3077 i40e_add_del_fdir(vsi, filter, true);
3078 }
3079}
3080
41c445ff
JB		 3081/**
3082 * i40e_vsi_configure - Set up the VSI for action
3083 * @vsi: the VSI being configured
3084 **/
3085static int i40e_vsi_configure(struct i40e_vsi *vsi)
3086{
3087 int err;
3088
3089 i40e_set_vsi_rx_mode(vsi);
3090 i40e_restore_vlan(vsi);
3091 i40e_vsi_config_dcb_rings(vsi);
3092 err = i40e_vsi_configure_tx(vsi);
3093 if (!err)
3094 err = i40e_vsi_configure_rx(vsi);
3095
3096 return err;
3097}
3098
3099/**
3100 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3101 * @vsi: the VSI being configured
3102 **/
3103static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3104{
3105 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3106 struct i40e_hw *hw = &pf->hw;
3107 u16 vector;
3108 int i, q;
41c445ff
JB		 3109 u32 qp;
3110
3111 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3112 * and PFINT_LNKLSTn registers, e.g.:
3113 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3114 */
3115 qp = vsi->base_queue;
3116 vector = vsi->base_vector;
493fb300 3117 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3118 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3119
ee2319cf 3120 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3121 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3122 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3123 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3124 q_vector->rx.itr);
3125 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3126 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3127 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3128 q_vector->tx.itr);
ac26fc13
JB		 3129 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3130 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3131
3132 /* Linked list for the queuepairs assigned to this vector */
3133 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3134 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3135 u32 val;
3136
41c445ff
JB		 3137 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3138 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3139 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3140 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3141 (I40E_QUEUE_TYPE_TX
3142 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3143
3144 wr32(hw, I40E_QINT_RQCTL(qp), val);
3145
3146 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3147 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3148 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3149 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3150 (I40E_QUEUE_TYPE_RX
3151 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3152
3153 /* Terminate the linked list */
3154 if (q == (q_vector->num_ringpairs - 1))
3155 val |= (I40E_QUEUE_END_OF_LIST
3156 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3157
3158 wr32(hw, I40E_QINT_TQCTL(qp), val);
3159 qp++;
3160 }
3161 }
3162
3163 i40e_flush(hw);
3164}
3165
3166/**
3167 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3168 * @hw: ptr to the hardware info
3169 **/
ab437b5a 3170static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3171{
ab437b5a 3172 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3173 u32 val;
3174
3175 /* clear things first */
3176 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3177 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3178
3179 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3180 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3181 I40E_PFINT_ICR0_ENA_GRST_MASK |
3182 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3183 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3184 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3185 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3186 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3187
0d8e1439
ASJ		 3188 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3189 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3190
ab437b5a
JK		 3191 if (pf->flags & I40E_FLAG_PTP)
3192 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3193
41c445ff
JB		 3194 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3195
3196 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3197 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3198 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3199
3200 /* OTHER_ITR_IDX = 0 */
3201 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3202}
3203
3204/**
3205 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3206 * @vsi: the VSI being configured
3207 **/
3208static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3209{
493fb300 3210 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3211 struct i40e_pf *pf = vsi->back;
3212 struct i40e_hw *hw = &pf->hw;
3213 u32 val;
3214
3215 /* set the ITR configuration */
ee2319cf 3216 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3217 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3218 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3219 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3220 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3221 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3222 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3223
ab437b5a 3224 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3225
3226 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3227 wr32(hw, I40E_PFINT_LNKLST0, 0);
3228
f29eaa3d 3229 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3230 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3231 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3232 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3233
3234 wr32(hw, I40E_QINT_RQCTL(0), val);
3235
3236 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3237 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3238 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3239
3240 wr32(hw, I40E_QINT_TQCTL(0), val);
3241 i40e_flush(hw);
3242}
3243
2ef28cfb
MW		 3244/**
3245 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3246 * @pf: board private structure
3247 **/
3248void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3249{
3250 struct i40e_hw *hw = &pf->hw;
3251
3252 wr32(hw, I40E_PFINT_DYN_CTL0,
3253 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3254 i40e_flush(hw);
3255}
3256
41c445ff
JB		 3257/**
3258 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3259 * @pf: board private structure
3260 **/
116a57d4 3261void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3262{
3263 struct i40e_hw *hw = &pf->hw;
3264 u32 val;
3265
3266 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3267 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3268 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3269
3270 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3271 i40e_flush(hw);
3272}
3273
41c445ff
JB		 3274/**
3275 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3276 * @irq: interrupt number
3277 * @data: pointer to a q_vector
3278 **/
3279static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3280{
3281 struct i40e_q_vector *q_vector = data;
3282
cd0b6fa6 3283 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3284 return IRQ_HANDLED;
3285
5d3465a1 3286 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3287
3288 return IRQ_HANDLED;
3289}
3290
41c445ff
JB		 3291/**
3292 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3293 * @vsi: the VSI being configured
3294 * @basename: name for the vector
3295 *
3296 * Allocates MSI-X vectors and requests interrupts from the kernel.
3297 **/
3298static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3299{
3300 int q_vectors = vsi->num_q_vectors;
3301 struct i40e_pf *pf = vsi->back;
3302 int base = vsi->base_vector;
3303 int rx_int_idx = 0;
3304 int tx_int_idx = 0;
3305 int vector, err;
3306
3307 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3308 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3309
cd0b6fa6 3310 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3311 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3312 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3313 tx_int_idx++;
cd0b6fa6 3314 } else if (q_vector->rx.ring) {
41c445ff
JB		 3315 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3316 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3317 } else if (q_vector->tx.ring) {
41c445ff
JB		 3318 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3319 "%s-%s-%d", basename, "tx", tx_int_idx++);
3320 } else {
3321 /* skip this unused q_vector */
3322 continue;
3323 }
3324 err = request_irq(pf->msix_entries[base + vector].vector,
3325 vsi->irq_handler,
3326 0,
3327 q_vector->name,
3328 q_vector);
3329 if (err) {
3330 dev_info(&pf->pdev->dev,
fb43201f 3331 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3332 goto free_queue_irqs;
3333 }
3334 /* assign the mask for this irq */
3335 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3336 &q_vector->affinity_mask);
3337 }
3338
63741846 3339 vsi->irqs_ready = true;
41c445ff
JB		 3340 return 0;
3341
3342free_queue_irqs:
3343 while (vector) {
3344 vector--;
3345 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3346 NULL);
3347 free_irq(pf->msix_entries[base + vector].vector,
3348 &(vsi->q_vectors[vector]));
3349 }
3350 return err;
3351}
3352
3353/**
3354 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3355 * @vsi: the VSI being un-configured
3356 **/
3357static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3358{
3359 struct i40e_pf *pf = vsi->back;
3360 struct i40e_hw *hw = &pf->hw;
3361 int base = vsi->base_vector;
3362 int i;
3363
3364 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3365 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3366 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3367 }
3368
3369 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3370 for (i = vsi->base_vector;
3371 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3372 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3373
3374 i40e_flush(hw);
3375 for (i = 0; i < vsi->num_q_vectors; i++)
3376 synchronize_irq(pf->msix_entries[i + base].vector);
3377 } else {
3378 /* Legacy and MSI mode - this stops all interrupt handling */
3379 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3380 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3381 i40e_flush(hw);
3382 synchronize_irq(pf->pdev->irq);
3383 }
3384}
3385
3386/**
3387 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3388 * @vsi: the VSI being configured
3389 **/
3390static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3391{
3392 struct i40e_pf *pf = vsi->back;
3393 int i;
3394
3395 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3396 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3397 i40e_irq_dynamic_enable(vsi, i);
3398 } else {
3399 i40e_irq_dynamic_enable_icr0(pf);
3400 }
3401
1022cb6c 3402 i40e_flush(&pf->hw);
41c445ff
JB		 3403 return 0;
3404}
3405
3406/**
3407 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3408 * @pf: board private structure
3409 **/
3410static void i40e_stop_misc_vector(struct i40e_pf *pf)
3411{
3412 /* Disable ICR 0 */
3413 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3414 i40e_flush(&pf->hw);
3415}
3416
3417/**
3418 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3419 * @irq: interrupt number
3420 * @data: pointer to a q_vector
3421 *
3422 * This is the handler used for all MSI/Legacy interrupts, and deals
3423 * with both queue and non-queue interrupts. This is also used in
3424 * MSIX mode to handle the non-queue interrupts.
3425 **/
3426static irqreturn_t i40e_intr(int irq, void *data)
3427{
3428 struct i40e_pf *pf = (struct i40e_pf *)data;
3429 struct i40e_hw *hw = &pf->hw;
5e823066 3430 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3431 u32 icr0, icr0_remaining;
3432 u32 val, ena_mask;
3433
3434 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3435 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3436
116a57d4
SN		 3437 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3438 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3439 goto enable_intr;
41c445ff 3440
cd92e72f
SN		 3441 /* if interrupt but no bits showing, must be SWINT */
3442 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3443 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3444 pf->sw_int_count++;
3445
0d8e1439
ASJ		 3446 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3447 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3448 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3449 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3450 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3451 }
3452
41c445ff
JB		 3453 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3454 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3455 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3456 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3457
3458 /* temporarily disable queue cause for NAPI processing */
3459 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3460
41c445ff
JB		 3461 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3462 wr32(hw, I40E_QINT_RQCTL(0), qval);
3463
3464 qval = rd32(hw, I40E_QINT_TQCTL(0));
3465 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3466 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3467
3468 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3469 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3470 }
3471
3472 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3473 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3474 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3475 }
3476
3477 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3478 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3479 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3480 }
3481
3482 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3483 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3484 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3485 }
3486
3487 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3488 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3489 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3490 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3491 val = rd32(hw, I40E_GLGEN_RSTAT);
3492 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3493 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3494 if (val == I40E_RESET_CORER) {
41c445ff 3495 pf->corer_count++;
4eb3f768 3496 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3497 pf->globr_count++;
4eb3f768 3498 } else if (val == I40E_RESET_EMPR) {
41c445ff 3499 pf->empr_count++;
9df42d1a 3500 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3501 }
41c445ff
JB		 3502 }
3503
9c010ee0
ASJ		 3504 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3505 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3506 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3507 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3508 rd32(hw, I40E_PFHMC_ERRORINFO),
3509 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3510 }
3511
beb0dff1
JK		 3512 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3513 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3514
3515 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3516 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3517 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3518 }
beb0dff1
JK		 3519 }
3520
41c445ff
JB		 3521 /* If a critical error is pending we have no choice but to reset the
3522 * device.
3523 * Report and mask out any remaining unexpected interrupts.
3524 */
3525 icr0_remaining = icr0 & ena_mask;
3526 if (icr0_remaining) {
3527 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3528 icr0_remaining);
9c010ee0 3529 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3530 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3531 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3532 dev_info(&pf->pdev->dev, "device will be reset\n");
3533 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3534 i40e_service_event_schedule(pf);
41c445ff
JB		 3535 }
3536 ena_mask &= ~icr0_remaining;
3537 }
5e823066 3538 ret = IRQ_HANDLED;
41c445ff 3539
5e823066 3540enable_intr:
41c445ff
JB		 3541 /* re-enable interrupt causes */
3542 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3543 if (!test_bit(__I40E_DOWN, &pf->state)) {
3544 i40e_service_event_schedule(pf);
3545 i40e_irq_dynamic_enable_icr0(pf);
3546 }
3547
5e823066 3548 return ret;
41c445ff
JB		 3549}
3550
cbf61325
ASJ		 3551/**
3552 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3553 * @tx_ring: tx ring to clean
3554 * @budget: how many cleans we're allowed
3555 *
3556 * Returns true if there's any budget left (e.g. the clean is finished)
3557 **/
3558static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3559{
3560 struct i40e_vsi *vsi = tx_ring->vsi;
3561 u16 i = tx_ring->next_to_clean;
3562 struct i40e_tx_buffer *tx_buf;
3563 struct i40e_tx_desc *tx_desc;
3564
3565 tx_buf = &tx_ring->tx_bi[i];
3566 tx_desc = I40E_TX_DESC(tx_ring, i);
3567 i -= tx_ring->count;
3568
3569 do {
3570 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3571
3572 /* if next_to_watch is not set then there is no work pending */
3573 if (!eop_desc)
3574 break;
3575
3576 /* prevent any other reads prior to eop_desc */
3577 read_barrier_depends();
3578
3579 /* if the descriptor isn't done, no work yet to do */
3580 if (!(eop_desc->cmd_type_offset_bsz &
3581 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3582 break;
3583
3584 /* clear next_to_watch to prevent false hangs */
3585 tx_buf->next_to_watch = NULL;
3586
49d7d933
ASJ		 3587 tx_desc->buffer_addr = 0;
3588 tx_desc->cmd_type_offset_bsz = 0;
3589 /* move past filter desc */
3590 tx_buf++;
3591 tx_desc++;
3592 i++;
3593 if (unlikely(!i)) {
3594 i -= tx_ring->count;
3595 tx_buf = tx_ring->tx_bi;
3596 tx_desc = I40E_TX_DESC(tx_ring, 0);
3597 }
cbf61325
ASJ		 3598 /* unmap skb header data */
3599 dma_unmap_single(tx_ring->dev,
3600 dma_unmap_addr(tx_buf, dma),
3601 dma_unmap_len(tx_buf, len),
3602 DMA_TO_DEVICE);
49d7d933
ASJ		 3603 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3604 kfree(tx_buf->raw_buf);
cbf61325 3605
49d7d933
ASJ		 3606 tx_buf->raw_buf = NULL;
3607 tx_buf->tx_flags = 0;
3608 tx_buf->next_to_watch = NULL;
cbf61325 3609 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3610 tx_desc->buffer_addr = 0;
3611 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3612
49d7d933 3613 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3614 tx_buf++;
3615 tx_desc++;
3616 i++;
3617 if (unlikely(!i)) {
3618 i -= tx_ring->count;
3619 tx_buf = tx_ring->tx_bi;
3620 tx_desc = I40E_TX_DESC(tx_ring, 0);
3621 }
3622
3623 /* update budget accounting */
3624 budget--;
3625 } while (likely(budget));
3626
3627 i += tx_ring->count;
3628 tx_ring->next_to_clean = i;
3629
6995b36c 3630 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3631 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3632
cbf61325
ASJ		 3633 return budget > 0;
3634}
3635
3636/**
3637 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3638 * @irq: interrupt number
3639 * @data: pointer to a q_vector
3640 **/
3641static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3642{
3643 struct i40e_q_vector *q_vector = data;
3644 struct i40e_vsi *vsi;
3645
3646 if (!q_vector->tx.ring)
3647 return IRQ_HANDLED;
3648
3649 vsi = q_vector->tx.ring->vsi;
3650 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3651
3652 return IRQ_HANDLED;
3653}
3654
41c445ff 3655/**
cd0b6fa6 3656 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3657 * @vsi: the VSI being configured
3658 * @v_idx: vector index
cd0b6fa6 3659 * @qp_idx: queue pair index
41c445ff 3660 **/
26cdc443 3661static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3662{
493fb300 3663 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3664 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3665 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3666
3667 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3668 tx_ring->next = q_vector->tx.ring;
3669 q_vector->tx.ring = tx_ring;
41c445ff 3670 q_vector->tx.count++;
cd0b6fa6
AD		 3671
3672 rx_ring->q_vector = q_vector;
3673 rx_ring->next = q_vector->rx.ring;
3674 q_vector->rx.ring = rx_ring;
3675 q_vector->rx.count++;
41c445ff
JB		 3676}
3677
3678/**
3679 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3680 * @vsi: the VSI being configured
3681 *
3682 * This function maps descriptor rings to the queue-specific vectors
3683 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3684 * one vector per queue pair, but on a constrained vector budget, we
3685 * group the queue pairs as "efficiently" as possible.
3686 **/
3687static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3688{
3689 int qp_remaining = vsi->num_queue_pairs;
3690 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3691 int num_ringpairs;
41c445ff
JB		 3692 int v_start = 0;
3693 int qp_idx = 0;
3694
3695 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3696 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3697 * It is also important to go through all the vectors available to be
3698 * sure that if we don't use all the vectors, that the remaining vectors
3699 * are cleared. This is especially important when decreasing the
3700 * number of queues in use.
41c445ff 3701 */
70114ec4 3702 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3703 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3704
3705 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3706
3707 q_vector->num_ringpairs = num_ringpairs;
3708
3709 q_vector->rx.count = 0;
3710 q_vector->tx.count = 0;
3711 q_vector->rx.ring = NULL;
3712 q_vector->tx.ring = NULL;
3713
3714 while (num_ringpairs--) {
26cdc443 3715 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3716 qp_idx++;
3717 qp_remaining--;
41c445ff
JB		 3718 }
3719 }
3720}
3721
3722/**
3723 * i40e_vsi_request_irq - Request IRQ from the OS
3724 * @vsi: the VSI being configured
3725 * @basename: name for the vector
3726 **/
3727static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3728{
3729 struct i40e_pf *pf = vsi->back;
3730 int err;
3731
3732 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3733 err = i40e_vsi_request_irq_msix(vsi, basename);
3734 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3735 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3736 pf->int_name, pf);
41c445ff
JB		 3737 else
3738 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3739 pf->int_name, pf);
41c445ff
JB		 3740
3741 if (err)
3742 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3743
3744 return err;
3745}
3746
3747#ifdef CONFIG_NET_POLL_CONTROLLER
3748/**
d89d967f 3749 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3750 * @netdev: network interface device structure
3751 *
3752 * This is used by netconsole to send skbs without having to re-enable
3753 * interrupts. It's not called while the normal interrupt routine is executing.
3754 **/
38e00438
VD		 3755#ifdef I40E_FCOE
3756void i40e_netpoll(struct net_device *netdev)
3757#else
41c445ff 3758static void i40e_netpoll(struct net_device *netdev)
38e00438 3759#endif
41c445ff
JB		 3760{
3761 struct i40e_netdev_priv *np = netdev_priv(netdev);
3762 struct i40e_vsi *vsi = np->vsi;
3763 struct i40e_pf *pf = vsi->back;
3764 int i;
3765
3766 /* if interface is down do nothing */
3767 if (test_bit(__I40E_DOWN, &vsi->state))
3768 return;
3769
41c445ff
JB		 3770 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3771 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3772 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3773 } else {
3774 i40e_intr(pf->pdev->irq, netdev);
3775 }
41c445ff
JB		 3776}
3777#endif
3778
23527308
NP		 3779/**
3780 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3781 * @pf: the PF being configured
3782 * @pf_q: the PF queue
3783 * @enable: enable or disable state of the queue
3784 *
3785 * This routine will wait for the given Tx queue of the PF to reach the
3786 * enabled or disabled state.
3787 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3788 * multiple retries; else will return 0 in case of success.
3789 **/
3790static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3791{
3792 int i;
3793 u32 tx_reg;
3794
3795 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3796 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3797 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3798 break;
3799
f98a2006 3800 usleep_range(10, 20);
23527308
NP		 3801 }
3802 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3803 return -ETIMEDOUT;
3804
3805 return 0;
3806}
3807
41c445ff
JB		 3808/**
3809 * i40e_vsi_control_tx - Start or stop a VSI's rings
3810 * @vsi: the VSI being configured
3811 * @enable: start or stop the rings
3812 **/
3813static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3814{
3815 struct i40e_pf *pf = vsi->back;
3816 struct i40e_hw *hw = &pf->hw;
23527308 3817 int i, j, pf_q, ret = 0;
41c445ff
JB		 3818 u32 tx_reg;
3819
3820 pf_q = vsi->base_queue;
3821 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3822
3823 /* warn the TX unit of coming changes */
3824 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3825 if (!enable)
f98a2006 3826 usleep_range(10, 20);
351499ab 3827
6c5ef620 3828 for (j = 0; j < 50; j++) {
41c445ff 3829 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3830 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3831 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3832 break;
3833 usleep_range(1000, 2000);
3834 }
fda972f6 3835 /* Skip if the queue is already in the requested state */
7c122007 3836 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3837 continue;
41c445ff
JB		 3838
3839 /* turn on/off the queue */
c5c9eb9e
SN		 3840 if (enable) {
3841 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3842 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3843 } else {
41c445ff 3844 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3845 }
41c445ff
JB		 3846
3847 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3848 /* No waiting for the Tx queue to disable */
3849 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3850 continue;
41c445ff
JB		 3851
3852 /* wait for the change to finish */
23527308
NP		 3853 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3854 if (ret) {
3855 dev_info(&pf->pdev->dev,
fb43201f
SN		 3856 "VSI seid %d Tx ring %d %sable timeout\n",
3857 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3858 break;
41c445ff
JB		 3859 }
3860 }
3861
7134f9ce
JB		 3862 if (hw->revision_id == 0)
3863 mdelay(50);
23527308
NP		 3864 return ret;
3865}
3866
3867/**
3868 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3869 * @pf: the PF being configured
3870 * @pf_q: the PF queue
3871 * @enable: enable or disable state of the queue
3872 *
3873 * This routine will wait for the given Rx queue of the PF to reach the
3874 * enabled or disabled state.
3875 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3876 * multiple retries; else will return 0 in case of success.
3877 **/
3878static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3879{
3880 int i;
3881 u32 rx_reg;
3882
3883 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3884 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3885 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3886 break;
3887
f98a2006 3888 usleep_range(10, 20);
23527308
NP		 3889 }
3890 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3891 return -ETIMEDOUT;
7134f9ce 3892
41c445ff
JB		 3893 return 0;
3894}
3895
3896/**
3897 * i40e_vsi_control_rx - Start or stop a VSI's rings
3898 * @vsi: the VSI being configured
3899 * @enable: start or stop the rings
3900 **/
3901static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3902{
3903 struct i40e_pf *pf = vsi->back;
3904 struct i40e_hw *hw = &pf->hw;
23527308 3905 int i, j, pf_q, ret = 0;
41c445ff
JB		 3906 u32 rx_reg;
3907
3908 pf_q = vsi->base_queue;
3909 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3910 for (j = 0; j < 50; j++) {
41c445ff 3911 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3912 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3913 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3914 break;
3915 usleep_range(1000, 2000);
3916 }
41c445ff 3917
7c122007
CS		 3918 /* Skip if the queue is already in the requested state */
3919 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3920 continue;
41c445ff
JB		 3921
3922 /* turn on/off the queue */
3923 if (enable)
6c5ef620 3924 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3925 else
6c5ef620 3926 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3927 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3928
3929 /* wait for the change to finish */
23527308
NP		 3930 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3931 if (ret) {
3932 dev_info(&pf->pdev->dev,
fb43201f
SN		 3933 "VSI seid %d Rx ring %d %sable timeout\n",
3934 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3935 break;
41c445ff
JB		 3936 }
3937 }
3938
23527308 3939 return ret;
41c445ff
JB		 3940}
3941
3942/**
3943 * i40e_vsi_control_rings - Start or stop a VSI's rings
3944 * @vsi: the VSI being configured
3945 * @enable: start or stop the rings
3946 **/
fc18eaa0 3947int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3948{
3b867b28 3949 int ret = 0;
41c445ff
JB		 3950
3951 /* do rx first for enable and last for disable */
3952 if (request) {
3953 ret = i40e_vsi_control_rx(vsi, request);
3954 if (ret)
3955 return ret;
3956 ret = i40e_vsi_control_tx(vsi, request);
3957 } else {
3b867b28
ASJ		 3958 /* Ignore return value, we need to shutdown whatever we can */
3959 i40e_vsi_control_tx(vsi, request);
3960 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3961 }
3962
3963 return ret;
3964}
3965
3966/**
3967 * i40e_vsi_free_irq - Free the irq association with the OS
3968 * @vsi: the VSI being configured
3969 **/
3970static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3971{
3972 struct i40e_pf *pf = vsi->back;
3973 struct i40e_hw *hw = &pf->hw;
3974 int base = vsi->base_vector;
3975 u32 val, qp;
3976 int i;
3977
3978 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3979 if (!vsi->q_vectors)
3980 return;
3981
63741846
SN		 3982 if (!vsi->irqs_ready)
3983 return;
3984
3985 vsi->irqs_ready = false;
41c445ff
JB		 3986 for (i = 0; i < vsi->num_q_vectors; i++) {
3987 u16 vector = i + base;
3988
3989 /* free only the irqs that were actually requested */
78681b1f
SN		 3990 if (!vsi->q_vectors[i] ||
3991 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3992 continue;
3993
3994 /* clear the affinity_mask in the IRQ descriptor */
3995 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3996 NULL);
3997 free_irq(pf->msix_entries[vector].vector,
493fb300 3998 vsi->q_vectors[i]);
41c445ff
JB		 3999
4000 /* Tear down the interrupt queue link list
4001 *
4002 * We know that they come in pairs and always
4003 * the Rx first, then the Tx. To clear the
4004 * link list, stick the EOL value into the
4005 * next_q field of the registers.
4006 */
4007 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4008 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4009 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4010 val |= I40E_QUEUE_END_OF_LIST
4011 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4012 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4013
4014 while (qp != I40E_QUEUE_END_OF_LIST) {
4015 u32 next;
4016
4017 val = rd32(hw, I40E_QINT_RQCTL(qp));
4018
4019 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4020 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4021 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4022 I40E_QINT_RQCTL_INTEVENT_MASK);
4023
4024 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4025 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4026
4027 wr32(hw, I40E_QINT_RQCTL(qp), val);
4028
4029 val = rd32(hw, I40E_QINT_TQCTL(qp));
4030
4031 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4032 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4033
4034 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4035 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4036 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4037 I40E_QINT_TQCTL_INTEVENT_MASK);
4038
4039 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4040 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4041
4042 wr32(hw, I40E_QINT_TQCTL(qp), val);
4043 qp = next;
4044 }
4045 }
4046 } else {
4047 free_irq(pf->pdev->irq, pf);
4048
4049 val = rd32(hw, I40E_PFINT_LNKLST0);
4050 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4051 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4052 val |= I40E_QUEUE_END_OF_LIST
4053 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4054 wr32(hw, I40E_PFINT_LNKLST0, val);
4055
4056 val = rd32(hw, I40E_QINT_RQCTL(qp));
4057 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4058 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4059 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4060 I40E_QINT_RQCTL_INTEVENT_MASK);
4061
4062 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4063 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4064
4065 wr32(hw, I40E_QINT_RQCTL(qp), val);
4066
4067 val = rd32(hw, I40E_QINT_TQCTL(qp));
4068
4069 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4070 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4071 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4072 I40E_QINT_TQCTL_INTEVENT_MASK);
4073
4074 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4075 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4076
4077 wr32(hw, I40E_QINT_TQCTL(qp), val);
4078 }
4079}
4080
493fb300
AD		 4081/**
4082 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4083 * @vsi: the VSI being configured
4084 * @v_idx: Index of vector to be freed
4085 *
4086 * This function frees the memory allocated to the q_vector. In addition if
4087 * NAPI is enabled it will delete any references to the NAPI struct prior
4088 * to freeing the q_vector.
4089 **/
4090static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4091{
4092 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4093 struct i40e_ring *ring;
493fb300
AD		 4094
4095 if (!q_vector)
4096 return;
4097
4098 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4099 i40e_for_each_ring(ring, q_vector->tx)
4100 ring->q_vector = NULL;
4101
4102 i40e_for_each_ring(ring, q_vector->rx)
4103 ring->q_vector = NULL;
493fb300
AD		 4104
4105 /* only VSI w/ an associated netdev is set up w/ NAPI */
4106 if (vsi->netdev)
4107 netif_napi_del(&q_vector->napi);
4108
4109 vsi->q_vectors[v_idx] = NULL;
4110
4111 kfree_rcu(q_vector, rcu);
4112}
4113
41c445ff
JB		 4114/**
4115 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4116 * @vsi: the VSI being un-configured
4117 *
4118 * This frees the memory allocated to the q_vectors and
4119 * deletes references to the NAPI struct.
4120 **/
4121static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4122{
4123 int v_idx;
4124
493fb300
AD		 4125 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4126 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4127}
4128
4129/**
4130 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4131 * @pf: board private structure
4132 **/
4133static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4134{
4135 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4136 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4137 pci_disable_msix(pf->pdev);
4138 kfree(pf->msix_entries);
4139 pf->msix_entries = NULL;
3b444399
SN		 4140 kfree(pf->irq_pile);
4141 pf->irq_pile = NULL;
41c445ff
JB		 4142 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4143 pci_disable_msi(pf->pdev);
4144 }
4145 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4146}
4147
4148/**
4149 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4150 * @pf: board private structure
4151 *
4152 * We go through and clear interrupt specific resources and reset the structure
4153 * to pre-load conditions
4154 **/
4155static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4156{
4157 int i;
4158
e147758d
SN		 4159 i40e_stop_misc_vector(pf);
4160 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4161 synchronize_irq(pf->msix_entries[0].vector);
4162 free_irq(pf->msix_entries[0].vector, pf);
4163 }
4164
41c445ff 4165 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4166 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4167 if (pf->vsi[i])
4168 i40e_vsi_free_q_vectors(pf->vsi[i]);
4169 i40e_reset_interrupt_capability(pf);
4170}
4171
4172/**
4173 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4174 * @vsi: the VSI being configured
4175 **/
4176static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4177{
4178 int q_idx;
4179
4180 if (!vsi->netdev)
4181 return;
4182
4183 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4184 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4185}
4186
4187/**
4188 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4189 * @vsi: the VSI being configured
4190 **/
4191static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4192{
4193 int q_idx;
4194
4195 if (!vsi->netdev)
4196 return;
4197
4198 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4199 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4200}
4201
90ef8d47
SN		 4202/**
4203 * i40e_vsi_close - Shut down a VSI
4204 * @vsi: the vsi to be quelled
4205 **/
4206static void i40e_vsi_close(struct i40e_vsi *vsi)
4207{
4208 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4209 i40e_down(vsi);
4210 i40e_vsi_free_irq(vsi);
4211 i40e_vsi_free_tx_resources(vsi);
4212 i40e_vsi_free_rx_resources(vsi);
92faef85 4213 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4214}
4215
41c445ff
JB		 4216/**
4217 * i40e_quiesce_vsi - Pause a given VSI
4218 * @vsi: the VSI being paused
4219 **/
4220static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4221{
4222 if (test_bit(__I40E_DOWN, &vsi->state))
4223 return;
4224
d341b7a5
NP		 4225 /* No need to disable FCoE VSI when Tx suspended */
4226 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4227 vsi->type == I40E_VSI_FCOE) {
4228 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4229 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4230 return;
4231 }
4232
41c445ff 4233 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4234 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4235 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4236 else
90ef8d47 4237 i40e_vsi_close(vsi);
41c445ff
JB		 4238}
4239
4240/**
4241 * i40e_unquiesce_vsi - Resume a given VSI
4242 * @vsi: the VSI being resumed
4243 **/
4244static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4245{
4246 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4247 return;
4248
4249 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4250 if (vsi->netdev && netif_running(vsi->netdev))
4251 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4252 else
8276f757 4253 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4254}
4255
4256/**
4257 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4258 * @pf: the PF
4259 **/
4260static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4261{
4262 int v;
4263
505682cd 4264 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4265 if (pf->vsi[v])
4266 i40e_quiesce_vsi(pf->vsi[v]);
4267 }
4268}
4269
4270/**
4271 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4272 * @pf: the PF
4273 **/
4274static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4275{
4276 int v;
4277
505682cd 4278 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4279 if (pf->vsi[v])
4280 i40e_unquiesce_vsi(pf->vsi[v]);
4281 }
4282}
4283
69129dc3
NP		 4284#ifdef CONFIG_I40E_DCB
4285/**
4286 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4287 * @vsi: the VSI being configured
4288 *
4289 * This function waits for the given VSI's Tx queues to be disabled.
4290 **/
4291static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4292{
4293 struct i40e_pf *pf = vsi->back;
4294 int i, pf_q, ret;
4295
4296 pf_q = vsi->base_queue;
4297 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4298 /* Check and wait for the disable status of the queue */
4299 ret = i40e_pf_txq_wait(pf, pf_q, false);
4300 if (ret) {
4301 dev_info(&pf->pdev->dev,
fb43201f
SN		 4302 "VSI seid %d Tx ring %d disable timeout\n",
4303 vsi->seid, pf_q);
69129dc3
NP		 4304 return ret;
4305 }
4306 }
4307
4308 return 0;
4309}
4310
4311/**
4312 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4313 * @pf: the PF
4314 *
4315 * This function waits for the Tx queues to be in disabled state for all the
4316 * VSIs that are managed by this PF.
4317 **/
4318static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4319{
4320 int v, ret = 0;
4321
4322 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4323 /* No need to wait for FCoE VSI queues */
4324 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4325 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4326 if (ret)
4327 break;
4328 }
4329 }
4330
4331 return ret;
4332}
4333
4334#endif
b03a8c1f
KP		 4335
4336/**
4337 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4338 * @q_idx: TX queue number
4339 * @vsi: Pointer to VSI struct
4340 *
4341 * This function checks specified queue for given VSI. Detects hung condition.
4342 * Sets hung bit since it is two step process. Before next run of service task
4343 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4344 * hung condition remain unchanged and during subsequent run, this function
4345 * issues SW interrupt to recover from hung condition.
4346 **/
4347static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4348{
4349 struct i40e_ring *tx_ring = NULL;
4350 struct i40e_pf *pf;
4351 u32 head, val, tx_pending;
4352 int i;
4353
4354 pf = vsi->back;
4355
4356 /* now that we have an index, find the tx_ring struct */
4357 for (i = 0; i < vsi->num_queue_pairs; i++) {
4358 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4359 if (q_idx == vsi->tx_rings[i]->queue_index) {
4360 tx_ring = vsi->tx_rings[i];
4361 break;
4362 }
4363 }
4364 }
4365
4366 if (!tx_ring)
4367 return;
4368
4369 /* Read interrupt register */
4370 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4371 val = rd32(&pf->hw,
4372 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4373 tx_ring->vsi->base_vector - 1));
4374 else
4375 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4376
9c6c1259
KP		 4377 /* Bail out if interrupts are disabled because napi_poll
4378 * execution in-progress or will get scheduled soon.
4379 * napi_poll cleans TX and RX queues and updates 'next_to_clean'.
4380 */
4381 if (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))
4382 return;
4383
b03a8c1f
KP		 4384 head = i40e_get_head(tx_ring);
4385
4386 tx_pending = i40e_get_tx_pending(tx_ring);
4387
9c6c1259
KP		 4388 /* HW is done executing descriptors, updated HEAD write back,
4389 * but SW hasn't processed those descriptors. If interrupt is
4390 * not generated from this point ON, it could result into
4391 * dev_watchdog detecting timeout on those netdev_queue,
4392 * hence proactively trigger SW interrupt.
b03a8c1f 4393 */
9c6c1259
KP		 4394 if (tx_pending) {
4395 /* NAPI Poll didn't run and clear since it was set */
4396 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4397 &tx_ring->q_vector->hung_detected)) {
4398 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4399 vsi->seid, q_idx, tx_pending,
4400 tx_ring->next_to_clean, head,
4401 tx_ring->next_to_use,
4402 readl(tx_ring->tail));
4403 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4404 vsi->seid, q_idx, val);
4405 i40e_force_wb(vsi, tx_ring->q_vector);
4406 } else {
4407 /* First Chance - detected possible hung */
4408 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4409 &tx_ring->q_vector->hung_detected);
4410 }
4411 }
b03a8c1f
KP		 4412}
4413
4414/**
4415 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4416 * @pf: pointer to PF struct
4417 *
4418 * LAN VSI has netdev and netdev has TX queues. This function is to check
4419 * each of those TX queues if they are hung, trigger recovery by issuing
4420 * SW interrupt.
4421 **/
4422static void i40e_detect_recover_hung(struct i40e_pf *pf)
4423{
4424 struct net_device *netdev;
4425 struct i40e_vsi *vsi;
4426 int i;
4427
4428 /* Only for LAN VSI */
4429 vsi = pf->vsi[pf->lan_vsi];
4430
4431 if (!vsi)
4432 return;
4433
4434 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4435 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4436 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4437 return;
4438
4439 /* Make sure type is MAIN VSI */
4440 if (vsi->type != I40E_VSI_MAIN)
4441 return;
4442
4443 netdev = vsi->netdev;
4444 if (!netdev)
4445 return;
4446
4447 /* Bail out if netif_carrier is not OK */
4448 if (!netif_carrier_ok(netdev))
4449 return;
4450
4451 /* Go thru' TX queues for netdev */
4452 for (i = 0; i < netdev->num_tx_queues; i++) {
4453 struct netdev_queue *q;
4454
4455 q = netdev_get_tx_queue(netdev, i);
4456 if (q)
4457 i40e_detect_recover_hung_queue(i, vsi);
4458 }
4459}
4460
63d7e5a4
NP		 4461/**
4462 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4463 * @pf: pointer to PF
63d7e5a4
NP		 4464 *
4465 * Get TC map for ISCSI PF type that will include iSCSI TC
4466 * and LAN TC.
4467 **/
4468static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4469{
4470 struct i40e_dcb_app_priority_table app;
4471 struct i40e_hw *hw = &pf->hw;
4472 u8 enabled_tc = 1; /* TC0 is always enabled */
4473 u8 tc, i;
4474 /* Get the iSCSI APP TLV */
4475 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4476
4477 for (i = 0; i < dcbcfg->numapps; i++) {
4478 app = dcbcfg->app[i];
4479 if (app.selector == I40E_APP_SEL_TCPIP &&
4480 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4481 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4482 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4483 break;
4484 }
4485 }
4486
4487 return enabled_tc;
4488}
4489
41c445ff
JB		 4490/**
4491 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4492 * @dcbcfg: the corresponding DCBx configuration structure
4493 *
4494 * Return the number of TCs from given DCBx configuration
4495 **/
4496static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4497{
078b5876
JB		 4498 u8 num_tc = 0;
4499 int i;
41c445ff
JB		 4500
4501 /* Scan the ETS Config Priority Table to find
4502 * traffic class enabled for a given priority
4503 * and use the traffic class index to get the
4504 * number of traffic classes enabled
4505 */
4506 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4507 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4508 num_tc = dcbcfg->etscfg.prioritytable[i];
4509 }
4510
4511 /* Traffic class index starts from zero so
4512 * increment to return the actual count
4513 */
078b5876 4514 return num_tc + 1;
41c445ff
JB		 4515}
4516
4517/**
4518 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4519 * @dcbcfg: the corresponding DCBx configuration structure
4520 *
4521 * Query the current DCB configuration and return the number of
4522 * traffic classes enabled from the given DCBX config
4523 **/
4524static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4525{
4526 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4527 u8 enabled_tc = 1;
4528 u8 i;
4529
4530 for (i = 0; i < num_tc; i++)
41a1d04b 4531 enabled_tc |= BIT(i);
41c445ff
JB		 4532
4533 return enabled_tc;
4534}
4535
4536/**
4537 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4538 * @pf: PF being queried
4539 *
4540 * Return number of traffic classes enabled for the given PF
4541 **/
4542static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4543{
4544 struct i40e_hw *hw = &pf->hw;
4545 u8 i, enabled_tc;
4546 u8 num_tc = 0;
4547 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4548
4549 /* If DCB is not enabled then always in single TC */
4550 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4551 return 1;
4552
63d7e5a4
NP		 4553 /* SFP mode will be enabled for all TCs on port */
4554 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4555 return i40e_dcb_get_num_tc(dcbcfg);
4556
41c445ff 4557 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4558 if (pf->hw.func_caps.iscsi)
4559 enabled_tc = i40e_get_iscsi_tc_map(pf);
4560 else
fc51de96 4561 return 1; /* Only TC0 */
41c445ff 4562
63d7e5a4
NP		 4563 /* At least have TC0 */
4564 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4565 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4566 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4567 num_tc++;
4568 }
4569 return num_tc;
41c445ff
JB		 4570}
4571
4572/**
4573 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4574 * @pf: PF being queried
4575 *
4576 * Return a bitmap for first enabled traffic class for this PF.
4577 **/
4578static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4579{
4580 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4581 u8 i = 0;
4582
4583 if (!enabled_tc)
4584 return 0x1; /* TC0 */
4585
4586 /* Find the first enabled TC */
4587 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4588 if (enabled_tc & BIT(i))
41c445ff
JB		 4589 break;
4590 }
4591
41a1d04b 4592 return BIT(i);
41c445ff
JB		 4593}
4594
4595/**
4596 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4597 * @pf: PF being queried
4598 *
4599 * Return a bitmap for enabled traffic classes for this PF.
4600 **/
4601static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4602{
4603 /* If DCB is not enabled for this PF then just return default TC */
4604 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4605 return i40e_pf_get_default_tc(pf);
4606
41c445ff 4607 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4608 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4609 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4610
fc51de96 4611 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4612 if (pf->hw.func_caps.iscsi)
4613 return i40e_get_iscsi_tc_map(pf);
4614 else
fc51de96 4615 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4616}
4617
4618/**
4619 * i40e_vsi_get_bw_info - Query VSI BW Information
4620 * @vsi: the VSI being queried
4621 *
4622 * Returns 0 on success, negative value on failure
4623 **/
4624static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4625{
4626 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4627 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4628 struct i40e_pf *pf = vsi->back;
4629 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4630 i40e_status ret;
41c445ff 4631 u32 tc_bw_max;
41c445ff
JB		 4632 int i;
4633
4634 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4635 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4636 if (ret) {
41c445ff 4637 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4638 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4639 i40e_stat_str(&pf->hw, ret),
4640 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4641 return -EINVAL;
41c445ff
JB		 4642 }
4643
4644 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4645 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4646 NULL);
4647 if (ret) {
41c445ff 4648 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4649 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4650 i40e_stat_str(&pf->hw, ret),
4651 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4652 return -EINVAL;
41c445ff
JB		 4653 }
4654
4655 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4656 dev_info(&pf->pdev->dev,
4657 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4658 bw_config.tc_valid_bits,
4659 bw_ets_config.tc_valid_bits);
4660 /* Still continuing */
4661 }
4662
4663 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4664 vsi->bw_max_quanta = bw_config.max_bw;
4665 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4666 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4667 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4668 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4669 vsi->bw_ets_limit_credits[i] =
4670 le16_to_cpu(bw_ets_config.credits[i]);
4671 /* 3 bits out of 4 for each TC */
4672 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4673 }
078b5876 4674
dcae29be 4675 return 0;
41c445ff
JB		 4676}
4677
4678/**
4679 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4680 * @vsi: the VSI being configured
4681 * @enabled_tc: TC bitmap
4682 * @bw_credits: BW shared credits per TC
4683 *
4684 * Returns 0 on success, negative value on failure
4685 **/
dcae29be 4686static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4687 u8 *bw_share)
4688{
4689 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4690 i40e_status ret;
dcae29be 4691 int i;
41c445ff
JB		 4692
4693 bw_data.tc_valid_bits = enabled_tc;
4694 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4695 bw_data.tc_bw_credits[i] = bw_share[i];
4696
f1c7e72e
SN		 4697 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4698 NULL);
4699 if (ret) {
41c445ff 4700 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4701 "AQ command Config VSI BW allocation per TC failed = %d\n",
4702 vsi->back->hw.aq.asq_last_status);
dcae29be 4703 return -EINVAL;
41c445ff
JB		 4704 }
4705
4706 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4707 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4708
dcae29be 4709 return 0;
41c445ff
JB		 4710}
4711
4712/**
4713 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4714 * @vsi: the VSI being configured
4715 * @enabled_tc: TC map to be enabled
4716 *
4717 **/
4718static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4719{
4720 struct net_device *netdev = vsi->netdev;
4721 struct i40e_pf *pf = vsi->back;
4722 struct i40e_hw *hw = &pf->hw;
4723 u8 netdev_tc = 0;
4724 int i;
4725 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4726
4727 if (!netdev)
4728 return;
4729
4730 if (!enabled_tc) {
4731 netdev_reset_tc(netdev);
4732 return;
4733 }
4734
4735 /* Set up actual enabled TCs on the VSI */
4736 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4737 return;
4738
4739 /* set per TC queues for the VSI */
4740 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4741 /* Only set TC queues for enabled tcs
4742 *
4743 * e.g. For a VSI that has TC0 and TC3 enabled the
4744 * enabled_tc bitmap would be 0x00001001; the driver
4745 * will set the numtc for netdev as 2 that will be
4746 * referenced by the netdev layer as TC 0 and 1.
4747 */
75f5cea9 4748 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4749 netdev_set_tc_queue(netdev,
4750 vsi->tc_config.tc_info[i].netdev_tc,
4751 vsi->tc_config.tc_info[i].qcount,
4752 vsi->tc_config.tc_info[i].qoffset);
4753 }
4754
4755 /* Assign UP2TC map for the VSI */
4756 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4757 /* Get the actual TC# for the UP */
4758 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4759 /* Get the mapped netdev TC# for the UP */
4760 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4761 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4762 }
4763}
4764
4765/**
4766 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4767 * @vsi: the VSI being configured
4768 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4769 **/
4770static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4771 struct i40e_vsi_context *ctxt)
4772{
4773 /* copy just the sections touched not the entire info
4774 * since not all sections are valid as returned by
4775 * update vsi params
4776 */
4777 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4778 memcpy(&vsi->info.queue_mapping,
4779 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4780 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4781 sizeof(vsi->info.tc_mapping));
4782}
4783
4784/**
4785 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4786 * @vsi: VSI to be configured
4787 * @enabled_tc: TC bitmap
4788 *
4789 * This configures a particular VSI for TCs that are mapped to the
4790 * given TC bitmap. It uses default bandwidth share for TCs across
4791 * VSIs to configure TC for a particular VSI.
4792 *
4793 * NOTE:
4794 * It is expected that the VSI queues have been quisced before calling
4795 * this function.
4796 **/
4797static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4798{
4799 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4800 struct i40e_vsi_context ctxt;
4801 int ret = 0;
4802 int i;
4803
4804 /* Check if enabled_tc is same as existing or new TCs */
4805 if (vsi->tc_config.enabled_tc == enabled_tc)
4806 return ret;
4807
4808 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4809 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4810 if (enabled_tc & BIT(i))
41c445ff
JB		 4811 bw_share[i] = 1;
4812 }
4813
4814 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4815 if (ret) {
4816 dev_info(&vsi->back->pdev->dev,
4817 "Failed configuring TC map %d for VSI %d\n",
4818 enabled_tc, vsi->seid);
4819 goto out;
4820 }
4821
4822 /* Update Queue Pairs Mapping for currently enabled UPs */
4823 ctxt.seid = vsi->seid;
4824 ctxt.pf_num = vsi->back->hw.pf_id;
4825 ctxt.vf_num = 0;
4826 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4827 ctxt.info = vsi->info;
41c445ff
JB		 4828 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4829
4830 /* Update the VSI after updating the VSI queue-mapping information */
4831 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4832 if (ret) {
4833 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4834 "Update vsi tc config failed, err %s aq_err %s\n",
4835 i40e_stat_str(&vsi->back->hw, ret),
4836 i40e_aq_str(&vsi->back->hw,
4837 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4838 goto out;
4839 }
4840 /* update the local VSI info with updated queue map */
4841 i40e_vsi_update_queue_map(vsi, &ctxt);
4842 vsi->info.valid_sections = 0;
4843
4844 /* Update current VSI BW information */
4845 ret = i40e_vsi_get_bw_info(vsi);
4846 if (ret) {
4847 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4848 "Failed updating vsi bw info, err %s aq_err %s\n",
4849 i40e_stat_str(&vsi->back->hw, ret),
4850 i40e_aq_str(&vsi->back->hw,
4851 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4852 goto out;
4853 }
4854
4855 /* Update the netdev TC setup */
4856 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4857out:
4858 return ret;
4859}
4860
4e3b35b0
NP		 4861/**
4862 * i40e_veb_config_tc - Configure TCs for given VEB
4863 * @veb: given VEB
4864 * @enabled_tc: TC bitmap
4865 *
4866 * Configures given TC bitmap for VEB (switching) element
4867 **/
4868int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4869{
4870 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4871 struct i40e_pf *pf = veb->pf;
4872 int ret = 0;
4873 int i;
4874
4875 /* No TCs or already enabled TCs just return */
4876 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4877 return ret;
4878
4879 bw_data.tc_valid_bits = enabled_tc;
4880 /* bw_data.absolute_credits is not set (relative) */
4881
4882 /* Enable ETS TCs with equal BW Share for now */
4883 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4884 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4885 bw_data.tc_bw_share_credits[i] = 1;
4886 }
4887
4888 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4889 &bw_data, NULL);
4890 if (ret) {
4891 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4892 "VEB bw config failed, err %s aq_err %s\n",
4893 i40e_stat_str(&pf->hw, ret),
4894 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4895 goto out;
4896 }
4897
4898 /* Update the BW information */
4899 ret = i40e_veb_get_bw_info(veb);
4900 if (ret) {
4901 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4902 "Failed getting veb bw config, err %s aq_err %s\n",
4903 i40e_stat_str(&pf->hw, ret),
4904 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4905 }
4906
4907out:
4908 return ret;
4909}
4910
4911#ifdef CONFIG_I40E_DCB
4912/**
4913 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4914 * @pf: PF struct
4915 *
4916 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4917 * the caller would've quiesce all the VSIs before calling
4918 * this function
4919 **/
4920static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4921{
4922 u8 tc_map = 0;
4923 int ret;
4924 u8 v;
4925
4926 /* Enable the TCs available on PF to all VEBs */
4927 tc_map = i40e_pf_get_tc_map(pf);
4928 for (v = 0; v < I40E_MAX_VEB; v++) {
4929 if (!pf->veb[v])
4930 continue;
4931 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4932 if (ret) {
4933 dev_info(&pf->pdev->dev,
4934 "Failed configuring TC for VEB seid=%d\n",
4935 pf->veb[v]->seid);
4936 /* Will try to configure as many components */
4937 }
4938 }
4939
4940 /* Update each VSI */
505682cd 4941 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4942 if (!pf->vsi[v])
4943 continue;
4944
4945 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4946#ifdef I40E_FCOE
4947 * - For FCoE VSI only enable the TC configured
4948 * as per the APP TLV
4949#endif
4e3b35b0
NP		 4950 * - For all others keep them at TC0 for now
4951 */
4952 if (v == pf->lan_vsi)
4953 tc_map = i40e_pf_get_tc_map(pf);
4954 else
4955 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4956#ifdef I40E_FCOE
4957 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4958 tc_map = i40e_get_fcoe_tc_map(pf);
4959#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4960
4961 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4962 if (ret) {
4963 dev_info(&pf->pdev->dev,
4964 "Failed configuring TC for VSI seid=%d\n",
4965 pf->vsi[v]->seid);
4966 /* Will try to configure as many components */
4967 } else {
0672a091
NP		 4968 /* Re-configure VSI vectors based on updated TC map */
4969 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4970 if (pf->vsi[v]->netdev)
4971 i40e_dcbnl_set_all(pf->vsi[v]);
4972 }
4973 }
4974}
4975
2fd75f31
NP		 4976/**
4977 * i40e_resume_port_tx - Resume port Tx
4978 * @pf: PF struct
4979 *
4980 * Resume a port's Tx and issue a PF reset in case of failure to
4981 * resume.
4982 **/
4983static int i40e_resume_port_tx(struct i40e_pf *pf)
4984{
4985 struct i40e_hw *hw = &pf->hw;
4986 int ret;
4987
4988 ret = i40e_aq_resume_port_tx(hw, NULL);
4989 if (ret) {
4990 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4991 "Resume Port Tx failed, err %s aq_err %s\n",
4992 i40e_stat_str(&pf->hw, ret),
4993 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4994 /* Schedule PF reset to recover */
4995 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4996 i40e_service_event_schedule(pf);
4997 }
4998
4999 return ret;
5000}
5001
4e3b35b0
NP		 5002/**
5003 * i40e_init_pf_dcb - Initialize DCB configuration
5004 * @pf: PF being configured
5005 *
5006 * Query the current DCB configuration and cache it
5007 * in the hardware structure
5008 **/
5009static int i40e_init_pf_dcb(struct i40e_pf *pf)
5010{
5011 struct i40e_hw *hw = &pf->hw;
5012 int err = 0;
5013
025b4a54 5014 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 5015 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5016 goto out;
5017
4e3b35b0
NP		 5018 /* Get the initial DCB configuration */
5019 err = i40e_init_dcb(hw);
5020 if (!err) {
5021 /* Device/Function is not DCBX capable */
5022 if ((!hw->func_caps.dcb) ||
5023 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5024 dev_info(&pf->pdev->dev,
5025 "DCBX offload is not supported or is disabled for this PF.\n");
5026
5027 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5028 goto out;
5029
5030 } else {
5031 /* When status is not DISABLED then DCBX in FW */
5032 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5033 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5034
5035 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5036 /* Enable DCB tagging only when more than one TC */
5037 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5038 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5039 dev_dbg(&pf->pdev->dev,
5040 "DCBX offload is supported for this PF.\n");
4e3b35b0 5041 }
014269ff 5042 } else {
aebfc816 5043 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5044 "Query for DCB configuration failed, err %s aq_err %s\n",
5045 i40e_stat_str(&pf->hw, err),
5046 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5047 }
5048
5049out:
5050 return err;
5051}
5052#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5053#define SPEED_SIZE 14
5054#define FC_SIZE 8
5055/**
5056 * i40e_print_link_message - print link up or down
5057 * @vsi: the VSI for which link needs a message
5058 */
c156f856 5059void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5060{
a9165490
SN		 5061 char *speed = "Unknown";
5062 char *fc = "Unknown";
cf05ed08 5063
c156f856
MJ		 5064 if (vsi->current_isup == isup)
5065 return;
5066 vsi->current_isup = isup;
cf05ed08
JB		 5067 if (!isup) {
5068 netdev_info(vsi->netdev, "NIC Link is Down\n");
5069 return;
5070 }
5071
148c2d80
GR		 5072 /* Warn user if link speed on NPAR enabled partition is not at
5073 * least 10GB
5074 */
5075 if (vsi->back->hw.func_caps.npar_enable &&
5076 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5077 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5078 netdev_warn(vsi->netdev,
5079 "The partition detected link speed that is less than 10Gbps\n");
5080
cf05ed08
JB		 5081 switch (vsi->back->hw.phy.link_info.link_speed) {
5082 case I40E_LINK_SPEED_40GB:
a9165490 5083 speed = "40 G";
cf05ed08 5084 break;
ae24b409 5085 case I40E_LINK_SPEED_20GB:
a9165490 5086 speed = "20 G";
ae24b409 5087 break;
cf05ed08 5088 case I40E_LINK_SPEED_10GB:
a9165490 5089 speed = "10 G";
cf05ed08
JB		 5090 break;
5091 case I40E_LINK_SPEED_1GB:
a9165490 5092 speed = "1000 M";
cf05ed08 5093 break;
5960d33f 5094 case I40E_LINK_SPEED_100MB:
a9165490 5095 speed = "100 M";
5960d33f 5096 break;
cf05ed08
JB		 5097 default:
5098 break;
5099 }
5100
5101 switch (vsi->back->hw.fc.current_mode) {
5102 case I40E_FC_FULL:
a9165490 5103 fc = "RX/TX";
cf05ed08
JB		 5104 break;
5105 case I40E_FC_TX_PAUSE:
a9165490 5106 fc = "TX";
cf05ed08
JB		 5107 break;
5108 case I40E_FC_RX_PAUSE:
a9165490 5109 fc = "RX";
cf05ed08
JB		 5110 break;
5111 default:
a9165490 5112 fc = "None";
cf05ed08
JB		 5113 break;
5114 }
5115
a9165490 5116 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5117 speed, fc);
5118}
4e3b35b0 5119
41c445ff
JB		 5120/**
5121 * i40e_up_complete - Finish the last steps of bringing up a connection
5122 * @vsi: the VSI being configured
5123 **/
5124static int i40e_up_complete(struct i40e_vsi *vsi)
5125{
5126 struct i40e_pf *pf = vsi->back;
5127 int err;
5128
5129 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5130 i40e_vsi_configure_msix(vsi);
5131 else
5132 i40e_configure_msi_and_legacy(vsi);
5133
5134 /* start rings */
5135 err = i40e_vsi_control_rings(vsi, true);
5136 if (err)
5137 return err;
5138
5139 clear_bit(__I40E_DOWN, &vsi->state);
5140 i40e_napi_enable_all(vsi);
5141 i40e_vsi_enable_irq(vsi);
5142
5143 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5144 (vsi->netdev)) {
cf05ed08 5145 i40e_print_link_message(vsi, true);
41c445ff
JB		 5146 netif_tx_start_all_queues(vsi->netdev);
5147 netif_carrier_on(vsi->netdev);
6d779b41 5148 } else if (vsi->netdev) {
cf05ed08 5149 i40e_print_link_message(vsi, false);
7b592f61
CW		 5150 /* need to check for qualified module here*/
5151 if ((pf->hw.phy.link_info.link_info &
5152 I40E_AQ_MEDIA_AVAILABLE) &&
5153 (!(pf->hw.phy.link_info.an_info &
5154 I40E_AQ_QUALIFIED_MODULE)))
5155 netdev_err(vsi->netdev,
5156 "the driver failed to link because an unqualified module was detected.");
41c445ff 5157 }
ca64fa4e
ASJ		 5158
5159 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5160 if (vsi->type == I40E_VSI_FDIR) {
5161 /* reset fd counters */
5162 pf->fd_add_err = pf->fd_atr_cnt = 0;
5163 if (pf->fd_tcp_rule > 0) {
5164 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5165 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5166 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5167 pf->fd_tcp_rule = 0;
5168 }
ca64fa4e 5169 i40e_fdir_filter_restore(vsi);
1e1be8f6 5170 }
41c445ff
JB		 5171 i40e_service_event_schedule(pf);
5172
5173 return 0;
5174}
5175
5176/**
5177 * i40e_vsi_reinit_locked - Reset the VSI
5178 * @vsi: the VSI being configured
5179 *
5180 * Rebuild the ring structs after some configuration
5181 * has changed, e.g. MTU size.
5182 **/
5183static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5184{
5185 struct i40e_pf *pf = vsi->back;
5186
5187 WARN_ON(in_interrupt());
5188 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5189 usleep_range(1000, 2000);
5190 i40e_down(vsi);
5191
5192 /* Give a VF some time to respond to the reset. The
5193 * two second wait is based upon the watchdog cycle in
5194 * the VF driver.
5195 */
5196 if (vsi->type == I40E_VSI_SRIOV)
5197 msleep(2000);
5198 i40e_up(vsi);
5199 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5200}
5201
5202/**
5203 * i40e_up - Bring the connection back up after being down
5204 * @vsi: the VSI being configured
5205 **/
5206int i40e_up(struct i40e_vsi *vsi)
5207{
5208 int err;
5209
5210 err = i40e_vsi_configure(vsi);
5211 if (!err)
5212 err = i40e_up_complete(vsi);
5213
5214 return err;
5215}
5216
5217/**
5218 * i40e_down - Shutdown the connection processing
5219 * @vsi: the VSI being stopped
5220 **/
5221void i40e_down(struct i40e_vsi *vsi)
5222{
5223 int i;
5224
5225 /* It is assumed that the caller of this function
5226 * sets the vsi->state __I40E_DOWN bit.
5227 */
5228 if (vsi->netdev) {
5229 netif_carrier_off(vsi->netdev);
5230 netif_tx_disable(vsi->netdev);
5231 }
5232 i40e_vsi_disable_irq(vsi);
5233 i40e_vsi_control_rings(vsi, false);
5234 i40e_napi_disable_all(vsi);
5235
5236 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5237 i40e_clean_tx_ring(vsi->tx_rings[i]);
5238 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5239 }
5240}
5241
5242/**
5243 * i40e_setup_tc - configure multiple traffic classes
5244 * @netdev: net device to configure
5245 * @tc: number of traffic classes to enable
5246 **/
5247static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5248{
5249 struct i40e_netdev_priv *np = netdev_priv(netdev);
5250 struct i40e_vsi *vsi = np->vsi;
5251 struct i40e_pf *pf = vsi->back;
5252 u8 enabled_tc = 0;
5253 int ret = -EINVAL;
5254 int i;
5255
5256 /* Check if DCB enabled to continue */
5257 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5258 netdev_info(netdev, "DCB is not enabled for adapter\n");
5259 goto exit;
5260 }
5261
5262 /* Check if MFP enabled */
5263 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5264 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5265 goto exit;
5266 }
5267
5268 /* Check whether tc count is within enabled limit */
5269 if (tc > i40e_pf_get_num_tc(pf)) {
5270 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5271 goto exit;
5272 }
5273
5274 /* Generate TC map for number of tc requested */
5275 for (i = 0; i < tc; i++)
75f5cea9 5276 enabled_tc |= BIT(i);
41c445ff
JB		 5277
5278 /* Requesting same TC configuration as already enabled */
5279 if (enabled_tc == vsi->tc_config.enabled_tc)
5280 return 0;
5281
5282 /* Quiesce VSI queues */
5283 i40e_quiesce_vsi(vsi);
5284
5285 /* Configure VSI for enabled TCs */
5286 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5287 if (ret) {
5288 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5289 vsi->seid);
5290 goto exit;
5291 }
5292
5293 /* Unquiesce VSI */
5294 i40e_unquiesce_vsi(vsi);
5295
5296exit:
5297 return ret;
5298}
5299
e4c6734e 5300#ifdef I40E_FCOE
16e5cc64
JF		 5301int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5302 struct tc_to_netdev *tc)
e4c6734e 5303#else
16e5cc64
JF		 5304static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5305 struct tc_to_netdev *tc)
e4c6734e
JF		 5306#endif
5307{
16e5cc64 5308 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5309 return -EINVAL;
16e5cc64 5310 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5311}
5312
41c445ff
JB		 5313/**
5314 * i40e_open - Called when a network interface is made active
5315 * @netdev: network interface device structure
5316 *
5317 * The open entry point is called when a network interface is made
5318 * active by the system (IFF_UP). At this point all resources needed
5319 * for transmit and receive operations are allocated, the interrupt
5320 * handler is registered with the OS, the netdev watchdog subtask is
5321 * enabled, and the stack is notified that the interface is ready.
5322 *
5323 * Returns 0 on success, negative value on failure
5324 **/
38e00438 5325int i40e_open(struct net_device *netdev)
41c445ff
JB		 5326{
5327 struct i40e_netdev_priv *np = netdev_priv(netdev);
5328 struct i40e_vsi *vsi = np->vsi;
5329 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5330 int err;
5331
4eb3f768
SN		 5332 /* disallow open during test or if eeprom is broken */
5333 if (test_bit(__I40E_TESTING, &pf->state) ||
5334 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5335 return -EBUSY;
5336
5337 netif_carrier_off(netdev);
5338
6c167f58
EK		 5339 err = i40e_vsi_open(vsi);
5340 if (err)
5341 return err;
5342
059dab69
JB		 5343 /* configure global TSO hardware offload settings */
5344 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5345 TCP_FLAG_FIN) >> 16);
5346 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5347 TCP_FLAG_FIN |
5348 TCP_FLAG_CWR) >> 16);
5349 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5350
6633d381 5351#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5352 vxlan_get_rx_port(netdev);
5353#endif
cd866606 5354#ifdef CONFIG_I40E_GENEVE
a340c789
AS		 5355 if (pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE)
5356 geneve_get_rx_port(netdev);
cd866606 5357#endif
6c167f58
EK		 5358
5359 return 0;
5360}
5361
5362/**
5363 * i40e_vsi_open -
5364 * @vsi: the VSI to open
5365 *
5366 * Finish initialization of the VSI.
5367 *
5368 * Returns 0 on success, negative value on failure
5369 **/
5370int i40e_vsi_open(struct i40e_vsi *vsi)
5371{
5372 struct i40e_pf *pf = vsi->back;
b294ac70 5373 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5374 int err;
5375
41c445ff
JB		 5376 /* allocate descriptors */
5377 err = i40e_vsi_setup_tx_resources(vsi);
5378 if (err)
5379 goto err_setup_tx;
5380 err = i40e_vsi_setup_rx_resources(vsi);
5381 if (err)
5382 goto err_setup_rx;
5383
5384 err = i40e_vsi_configure(vsi);
5385 if (err)
5386 goto err_setup_rx;
5387
c22e3c6c
SN		 5388 if (vsi->netdev) {
5389 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5390 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5391 err = i40e_vsi_request_irq(vsi, int_name);
5392 if (err)
5393 goto err_setup_rx;
41c445ff 5394
c22e3c6c
SN		 5395 /* Notify the stack of the actual queue counts. */
5396 err = netif_set_real_num_tx_queues(vsi->netdev,
5397 vsi->num_queue_pairs);
5398 if (err)
5399 goto err_set_queues;
25946ddb 5400
c22e3c6c
SN		 5401 err = netif_set_real_num_rx_queues(vsi->netdev,
5402 vsi->num_queue_pairs);
5403 if (err)
5404 goto err_set_queues;
8a9eb7d3
SN		 5405
5406 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5407 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5408 dev_driver_string(&pf->pdev->dev),
5409 dev_name(&pf->pdev->dev));
8a9eb7d3 5410 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5411
c22e3c6c 5412 } else {
ce9ccb17 5413 err = -EINVAL;
6c167f58
EK		 5414 goto err_setup_rx;
5415 }
25946ddb 5416
41c445ff
JB		 5417 err = i40e_up_complete(vsi);
5418 if (err)
5419 goto err_up_complete;
5420
41c445ff
JB		 5421 return 0;
5422
5423err_up_complete:
5424 i40e_down(vsi);
25946ddb 5425err_set_queues:
41c445ff
JB		 5426 i40e_vsi_free_irq(vsi);
5427err_setup_rx:
5428 i40e_vsi_free_rx_resources(vsi);
5429err_setup_tx:
5430 i40e_vsi_free_tx_resources(vsi);
5431 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5432 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5433
5434 return err;
5435}
5436
17a73f6b
JG		 5437/**
5438 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5439 * @pf: Pointer to PF
17a73f6b
JG		 5440 *
5441 * This function destroys the hlist where all the Flow Director
5442 * filters were saved.
5443 **/
5444static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5445{
5446 struct i40e_fdir_filter *filter;
5447 struct hlist_node *node2;
5448
5449 hlist_for_each_entry_safe(filter, node2,
5450 &pf->fdir_filter_list, fdir_node) {
5451 hlist_del(&filter->fdir_node);
5452 kfree(filter);
5453 }
5454 pf->fdir_pf_active_filters = 0;
5455}
5456
41c445ff
JB		 5457/**
5458 * i40e_close - Disables a network interface
5459 * @netdev: network interface device structure
5460 *
5461 * The close entry point is called when an interface is de-activated
5462 * by the OS. The hardware is still under the driver's control, but
5463 * this netdev interface is disabled.
5464 *
5465 * Returns 0, this is not allowed to fail
5466 **/
38e00438
VD		 5467#ifdef I40E_FCOE
5468int i40e_close(struct net_device *netdev)
5469#else
41c445ff 5470static int i40e_close(struct net_device *netdev)
38e00438 5471#endif
41c445ff
JB		 5472{
5473 struct i40e_netdev_priv *np = netdev_priv(netdev);
5474 struct i40e_vsi *vsi = np->vsi;
5475
90ef8d47 5476 i40e_vsi_close(vsi);
41c445ff
JB		 5477
5478 return 0;
5479}
5480
5481/**
5482 * i40e_do_reset - Start a PF or Core Reset sequence
5483 * @pf: board private structure
5484 * @reset_flags: which reset is requested
5485 *
5486 * The essential difference in resets is that the PF Reset
5487 * doesn't clear the packet buffers, doesn't reset the PE
5488 * firmware, and doesn't bother the other PFs on the chip.
5489 **/
5490void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5491{
5492 u32 val;
5493
5494 WARN_ON(in_interrupt());
5495
263fc48f
MW		 5496 if (i40e_check_asq_alive(&pf->hw))
5497 i40e_vc_notify_reset(pf);
5498
41c445ff 5499 /* do the biggest reset indicated */
41a1d04b 5500 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5501
5502 /* Request a Global Reset
5503 *
5504 * This will start the chip's countdown to the actual full
5505 * chip reset event, and a warning interrupt to be sent
5506 * to all PFs, including the requestor. Our handler
5507 * for the warning interrupt will deal with the shutdown
5508 * and recovery of the switch setup.
5509 */
69bfb110 5510 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5511 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5512 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5513 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5514
41a1d04b 5515 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5516
5517 /* Request a Core Reset
5518 *
5519 * Same as Global Reset, except does *not* include the MAC/PHY
5520 */
69bfb110 5521 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5522 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5523 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5524 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5525 i40e_flush(&pf->hw);
5526
41a1d04b 5527 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5528
5529 /* Request a PF Reset
5530 *
5531 * Resets only the PF-specific registers
5532 *
5533 * This goes directly to the tear-down and rebuild of
5534 * the switch, since we need to do all the recovery as
5535 * for the Core Reset.
5536 */
69bfb110 5537 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5538 i40e_handle_reset_warning(pf);
5539
41a1d04b 5540 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5541 int v;
5542
5543 /* Find the VSI(s) that requested a re-init */
5544 dev_info(&pf->pdev->dev,
5545 "VSI reinit requested\n");
505682cd 5546 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5547 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5548
41c445ff
JB		 5549 if (vsi != NULL &&
5550 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5551 i40e_vsi_reinit_locked(pf->vsi[v]);
5552 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5553 }
5554 }
41a1d04b 5555 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5556 int v;
5557
5558 /* Find the VSI(s) that needs to be brought down */
5559 dev_info(&pf->pdev->dev, "VSI down requested\n");
5560 for (v = 0; v < pf->num_alloc_vsi; v++) {
5561 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5562
b5d06f05
NP		 5563 if (vsi != NULL &&
5564 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5565 set_bit(__I40E_DOWN, &vsi->state);
5566 i40e_down(vsi);
5567 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5568 }
5569 }
41c445ff
JB		 5570 } else {
5571 dev_info(&pf->pdev->dev,
5572 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5573 }
5574}
5575
4e3b35b0
NP		 5576#ifdef CONFIG_I40E_DCB
5577/**
5578 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5579 * @pf: board private structure
5580 * @old_cfg: current DCB config
5581 * @new_cfg: new DCB config
5582 **/
5583bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5584 struct i40e_dcbx_config *old_cfg,
5585 struct i40e_dcbx_config *new_cfg)
5586{
5587 bool need_reconfig = false;
5588
5589 /* Check if ETS configuration has changed */
5590 if (memcmp(&new_cfg->etscfg,
5591 &old_cfg->etscfg,
5592 sizeof(new_cfg->etscfg))) {
5593 /* If Priority Table has changed reconfig is needed */
5594 if (memcmp(&new_cfg->etscfg.prioritytable,
5595 &old_cfg->etscfg.prioritytable,
5596 sizeof(new_cfg->etscfg.prioritytable))) {
5597 need_reconfig = true;
69bfb110 5598 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5599 }
5600
5601 if (memcmp(&new_cfg->etscfg.tcbwtable,
5602 &old_cfg->etscfg.tcbwtable,
5603 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5604 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5605
5606 if (memcmp(&new_cfg->etscfg.tsatable,
5607 &old_cfg->etscfg.tsatable,
5608 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5609 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5610 }
5611
5612 /* Check if PFC configuration has changed */
5613 if (memcmp(&new_cfg->pfc,
5614 &old_cfg->pfc,
5615 sizeof(new_cfg->pfc))) {
5616 need_reconfig = true;
69bfb110 5617 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5618 }
5619
5620 /* Check if APP Table has changed */
5621 if (memcmp(&new_cfg->app,
5622 &old_cfg->app,
3d9667a9 5623 sizeof(new_cfg->app))) {
4e3b35b0 5624 need_reconfig = true;
69bfb110 5625 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5626 }
4e3b35b0 5627
fb43201f 5628 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5629 return need_reconfig;
5630}
5631
5632/**
5633 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5634 * @pf: board private structure
5635 * @e: event info posted on ARQ
5636 **/
5637static int i40e_handle_lldp_event(struct i40e_pf *pf,
5638 struct i40e_arq_event_info *e)
5639{
5640 struct i40e_aqc_lldp_get_mib *mib =
5641 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5642 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5643 struct i40e_dcbx_config tmp_dcbx_cfg;
5644 bool need_reconfig = false;
5645 int ret = 0;
5646 u8 type;
5647
4d9b6043
NP		 5648 /* Not DCB capable or capability disabled */
5649 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5650 return ret;
5651
4e3b35b0
NP		 5652 /* Ignore if event is not for Nearest Bridge */
5653 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5654 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5655 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5656 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5657 return ret;
5658
5659 /* Check MIB Type and return if event for Remote MIB update */
5660 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5661 dev_dbg(&pf->pdev->dev,
fb43201f 5662 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5663 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5664 /* Update the remote cached instance and return */
5665 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5666 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5667 &hw->remote_dcbx_config);
5668 goto exit;
5669 }
5670
9fa61dd2 5671 /* Store the old configuration */
1a2f6248 5672 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5673
750fcbcf
NP		 5674 /* Reset the old DCBx configuration data */
5675 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5676 /* Get updated DCBX data from firmware */
5677 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5678 if (ret) {
f1c7e72e
SN		 5679 dev_info(&pf->pdev->dev,
5680 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5681 i40e_stat_str(&pf->hw, ret),
5682 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5683 goto exit;
5684 }
5685
5686 /* No change detected in DCBX configs */
750fcbcf
NP		 5687 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5688 sizeof(tmp_dcbx_cfg))) {
69bfb110 5689 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5690 goto exit;
5691 }
5692
750fcbcf
NP		 5693 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5694 &hw->local_dcbx_config);
4e3b35b0 5695
750fcbcf 5696 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5697
5698 if (!need_reconfig)
5699 goto exit;
5700
4d9b6043 5701 /* Enable DCB tagging only when more than one TC */
750fcbcf 5702 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5703 pf->flags |= I40E_FLAG_DCB_ENABLED;
5704 else
5705 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5706
69129dc3 5707 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5708 /* Reconfiguration needed quiesce all VSIs */
5709 i40e_pf_quiesce_all_vsi(pf);
5710
5711 /* Changes in configuration update VEB/VSI */
5712 i40e_dcb_reconfigure(pf);
5713
2fd75f31
NP		 5714 ret = i40e_resume_port_tx(pf);
5715
69129dc3 5716 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5717 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5718 if (ret)
5719 goto exit;
5720
5721 /* Wait for the PF's Tx queues to be disabled */
5722 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5723 if (ret) {
5724 /* Schedule PF reset to recover */
5725 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5726 i40e_service_event_schedule(pf);
5727 } else {
2fd75f31 5728 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5729 }
5730
4e3b35b0
NP		 5731exit:
5732 return ret;
5733}
5734#endif /* CONFIG_I40E_DCB */
5735
23326186
ASJ		 5736/**
5737 * i40e_do_reset_safe - Protected reset path for userland calls.
5738 * @pf: board private structure
5739 * @reset_flags: which reset is requested
5740 *
5741 **/
5742void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5743{
5744 rtnl_lock();
5745 i40e_do_reset(pf, reset_flags);
5746 rtnl_unlock();
5747}
5748
41c445ff
JB		 5749/**
5750 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5751 * @pf: board private structure
5752 * @e: event info posted on ARQ
5753 *
5754 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5755 * and VF queues
5756 **/
5757static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5758 struct i40e_arq_event_info *e)
5759{
5760 struct i40e_aqc_lan_overflow *data =
5761 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5762 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5763 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5764 struct i40e_hw *hw = &pf->hw;
5765 struct i40e_vf *vf;
5766 u16 vf_id;
5767
69bfb110
JB		 5768 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5769 queue, qtx_ctl);
41c445ff
JB		 5770
5771 /* Queue belongs to VF, find the VF and issue VF reset */
5772 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5773 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5774 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5775 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5776 vf_id -= hw->func_caps.vf_base_id;
5777 vf = &pf->vf[vf_id];
5778 i40e_vc_notify_vf_reset(vf);
5779 /* Allow VF to process pending reset notification */
5780 msleep(20);
5781 i40e_reset_vf(vf, false);
5782 }
5783}
5784
5785/**
5786 * i40e_service_event_complete - Finish up the service event
5787 * @pf: board private structure
5788 **/
5789static void i40e_service_event_complete(struct i40e_pf *pf)
5790{
b875f99b 5791 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5792
5793 /* flush memory to make sure state is correct before next watchog */
4e857c58 5794 smp_mb__before_atomic();
41c445ff
JB		 5795 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5796}
5797
55a5e60b 5798/**
12957388
ASJ		 5799 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5800 * @pf: board private structure
5801 **/
04294e38 5802u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5803{
04294e38 5804 u32 val, fcnt_prog;
12957388
ASJ		 5805
5806 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5807 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5808 return fcnt_prog;
5809}
5810
5811/**
04294e38 5812 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5813 * @pf: board private structure
5814 **/
04294e38 5815u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5816{
04294e38
ASJ		 5817 u32 val, fcnt_prog;
5818
55a5e60b
ASJ		 5819 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5820 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5821 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5822 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5823 return fcnt_prog;
5824}
1e1be8f6 5825
04294e38
ASJ		 5826/**
5827 * i40e_get_global_fd_count - Get total FD filters programmed on device
5828 * @pf: board private structure
5829 **/
5830u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5831{
5832 u32 val, fcnt_prog;
5833
5834 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5835 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5836 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5837 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5838 return fcnt_prog;
5839}
5840
55a5e60b
ASJ		 5841/**
5842 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5843 * @pf: board private structure
5844 **/
5845void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5846{
3487b6c3 5847 struct i40e_fdir_filter *filter;
55a5e60b 5848 u32 fcnt_prog, fcnt_avail;
3487b6c3 5849 struct hlist_node *node;
55a5e60b 5850
1e1be8f6
ASJ		 5851 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5852 return;
5853
55a5e60b
ASJ		 5854 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5855 * to re-enable
5856 */
04294e38 5857 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5858 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5859 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5860 (pf->fd_add_err == 0) ||
5861 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5862 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5863 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5864 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5865 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5866 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5867 }
5868 }
5869 /* Wait for some more space to be available to turn on ATR */
5870 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5871 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5872 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5873 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5874 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5875 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5876 }
5877 }
3487b6c3
CW		 5878
5879 /* if hw had a problem adding a filter, delete it */
5880 if (pf->fd_inv > 0) {
5881 hlist_for_each_entry_safe(filter, node,
5882 &pf->fdir_filter_list, fdir_node) {
5883 if (filter->fd_id == pf->fd_inv) {
5884 hlist_del(&filter->fdir_node);
5885 kfree(filter);
5886 pf->fdir_pf_active_filters--;
5887 }
5888 }
5889 }
55a5e60b
ASJ		 5890}
5891
1e1be8f6 5892#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5893#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5894/**
5895 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5896 * @pf: board private structure
5897 **/
5898static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5899{
04294e38 5900 unsigned long min_flush_time;
1e1be8f6 5901 int flush_wait_retry = 50;
04294e38
ASJ		 5902 bool disable_atr = false;
5903 int fd_room;
1e1be8f6
ASJ		 5904 int reg;
5905
1790ed0c
AA		 5906 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5907 return;
5908
a5fdaf34
JB		 5909 if (!time_after(jiffies, pf->fd_flush_timestamp +
5910 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5911 return;
04294e38 5912
a5fdaf34
JB		 5913 /* If the flush is happening too quick and we have mostly SB rules we
5914 * should not re-enable ATR for some time.
5915 */
5916 min_flush_time = pf->fd_flush_timestamp +
5917 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5918 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5919
5920 if (!(time_after(jiffies, min_flush_time)) &&
5921 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5922 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5923 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5924 disable_atr = true;
5925 }
5926
5927 pf->fd_flush_timestamp = jiffies;
5928 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5929 /* flush all filters */
5930 wr32(&pf->hw, I40E_PFQF_CTL_1,
5931 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5932 i40e_flush(&pf->hw);
5933 pf->fd_flush_cnt++;
5934 pf->fd_add_err = 0;
5935 do {
5936 /* Check FD flush status every 5-6msec */
5937 usleep_range(5000, 6000);
5938 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5939 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5940 break;
5941 } while (flush_wait_retry--);
5942 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5943 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5944 } else {
5945 /* replay sideband filters */
5946 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5947 if (!disable_atr)
5948 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5949 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5950 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5951 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5952 }
a5fdaf34 5953
1e1be8f6
ASJ		 5954}
5955
5956/**
5957 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5958 * @pf: board private structure
5959 **/
04294e38 5960u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5961{
5962 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5963}
5964
5965/* We can see up to 256 filter programming desc in transit if the filters are
5966 * being applied really fast; before we see the first
5967 * filter miss error on Rx queue 0. Accumulating enough error messages before
5968 * reacting will make sure we don't cause flush too often.
5969 */
5970#define I40E_MAX_FD_PROGRAM_ERROR 256
5971
41c445ff
JB		 5972/**
5973 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5974 * @pf: board private structure
5975 **/
5976static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5977{
41c445ff 5978
41c445ff
JB		 5979 /* if interface is down do nothing */
5980 if (test_bit(__I40E_DOWN, &pf->state))
5981 return;
1e1be8f6 5982
1790ed0c
AA		 5983 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5984 return;
5985
04294e38 5986 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5987 i40e_fdir_flush_and_replay(pf);
5988
55a5e60b
ASJ		 5989 i40e_fdir_check_and_reenable(pf);
5990
41c445ff
JB		 5991}
5992
5993/**
5994 * i40e_vsi_link_event - notify VSI of a link event
5995 * @vsi: vsi to be notified
5996 * @link_up: link up or down
5997 **/
5998static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5999{
32b5b811 6000 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6001 return;
6002
6003 switch (vsi->type) {
6004 case I40E_VSI_MAIN:
38e00438
VD		 6005#ifdef I40E_FCOE
6006 case I40E_VSI_FCOE:
6007#endif
41c445ff
JB		 6008 if (!vsi->netdev || !vsi->netdev_registered)
6009 break;
6010
6011 if (link_up) {
6012 netif_carrier_on(vsi->netdev);
6013 netif_tx_wake_all_queues(vsi->netdev);
6014 } else {
6015 netif_carrier_off(vsi->netdev);
6016 netif_tx_stop_all_queues(vsi->netdev);
6017 }
6018 break;
6019
6020 case I40E_VSI_SRIOV:
41c445ff
JB		 6021 case I40E_VSI_VMDQ2:
6022 case I40E_VSI_CTRL:
6023 case I40E_VSI_MIRROR:
6024 default:
6025 /* there is no notification for other VSIs */
6026 break;
6027 }
6028}
6029
6030/**
6031 * i40e_veb_link_event - notify elements on the veb of a link event
6032 * @veb: veb to be notified
6033 * @link_up: link up or down
6034 **/
6035static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6036{
6037 struct i40e_pf *pf;
6038 int i;
6039
6040 if (!veb || !veb->pf)
6041 return;
6042 pf = veb->pf;
6043
6044 /* depth first... */
6045 for (i = 0; i < I40E_MAX_VEB; i++)
6046 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6047 i40e_veb_link_event(pf->veb[i], link_up);
6048
6049 /* ... now the local VSIs */
505682cd 6050 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6051 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6052 i40e_vsi_link_event(pf->vsi[i], link_up);
6053}
6054
6055/**
6056 * i40e_link_event - Update netif_carrier status
6057 * @pf: board private structure
6058 **/
6059static void i40e_link_event(struct i40e_pf *pf)
6060{
320684cd 6061 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6062 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6063 i40e_status status;
6064 bool new_link, old_link;
41c445ff 6065
1f9610e4
CS		 6066 /* save off old link status information */
6067 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6068
1e701e09
JB		 6069 /* set this to force the get_link_status call to refresh state */
6070 pf->hw.phy.get_link_info = true;
6071
41c445ff 6072 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6073
6074 status = i40e_get_link_status(&pf->hw, &new_link);
6075 if (status) {
6076 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6077 status);
6078 return;
6079 }
6080
fef59ddf
CS		 6081 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6082 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6083
1e701e09 6084 if (new_link == old_link &&
fef59ddf 6085 new_link_speed == old_link_speed &&
320684cd
MW		 6086 (test_bit(__I40E_DOWN, &vsi->state) ||
6087 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6088 return;
320684cd
MW		 6089
6090 if (!test_bit(__I40E_DOWN, &vsi->state))
6091 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6092
6093 /* Notify the base of the switch tree connected to
6094 * the link. Floating VEBs are not notified.
6095 */
6096 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6097 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6098 else
320684cd 6099 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6100
6101 if (pf->vf)
6102 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6103
6104 if (pf->flags & I40E_FLAG_PTP)
6105 i40e_ptp_set_increment(pf);
41c445ff
JB		 6106}
6107
41c445ff 6108/**
21536717 6109 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6110 * @pf: board private structure
6111 **/
6112static void i40e_watchdog_subtask(struct i40e_pf *pf)
6113{
6114 int i;
6115
6116 /* if interface is down do nothing */
6117 if (test_bit(__I40E_DOWN, &pf->state) ||
6118 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6119 return;
6120
21536717
SN		 6121 /* make sure we don't do these things too often */
6122 if (time_before(jiffies, (pf->service_timer_previous +
6123 pf->service_timer_period)))
6124 return;
6125 pf->service_timer_previous = jiffies;
6126
9ac77266
SN		 6127 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6128 i40e_link_event(pf);
21536717 6129
41c445ff
JB		 6130 /* Update the stats for active netdevs so the network stack
6131 * can look at updated numbers whenever it cares to
6132 */
505682cd 6133 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6134 if (pf->vsi[i] && pf->vsi[i]->netdev)
6135 i40e_update_stats(pf->vsi[i]);
6136
d1a8d275
ASJ		 6137 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6138 /* Update the stats for the active switching components */
6139 for (i = 0; i < I40E_MAX_VEB; i++)
6140 if (pf->veb[i])
6141 i40e_update_veb_stats(pf->veb[i]);
6142 }
beb0dff1
JK		 6143
6144 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6145}
6146
6147/**
6148 * i40e_reset_subtask - Set up for resetting the device and driver
6149 * @pf: board private structure
6150 **/
6151static void i40e_reset_subtask(struct i40e_pf *pf)
6152{
6153 u32 reset_flags = 0;
6154
23326186 6155 rtnl_lock();
41c445ff 6156 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6157 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6158 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6159 }
6160 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6161 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6162 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6163 }
6164 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6165 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6166 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6167 }
6168 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6169 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6170 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6171 }
b5d06f05 6172 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6173 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6174 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6175 }
41c445ff
JB		 6176
6177 /* If there's a recovery already waiting, it takes
6178 * precedence before starting a new reset sequence.
6179 */
6180 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6181 i40e_handle_reset_warning(pf);
23326186 6182 goto unlock;
41c445ff
JB		 6183 }
6184
6185 /* If we're already down or resetting, just bail */
6186 if (reset_flags &&
6187 !test_bit(__I40E_DOWN, &pf->state) &&
6188 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6189 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6190
6191unlock:
6192 rtnl_unlock();
41c445ff
JB		 6193}
6194
6195/**
6196 * i40e_handle_link_event - Handle link event
6197 * @pf: board private structure
6198 * @e: event info posted on ARQ
6199 **/
6200static void i40e_handle_link_event(struct i40e_pf *pf,
6201 struct i40e_arq_event_info *e)
6202{
41c445ff
JB		 6203 struct i40e_aqc_get_link_status *status =
6204 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6205
1e701e09
JB		 6206 /* Do a new status request to re-enable LSE reporting
6207 * and load new status information into the hw struct
6208 * This completely ignores any state information
6209 * in the ARQ event info, instead choosing to always
6210 * issue the AQ update link status command.
6211 */
6212 i40e_link_event(pf);
6213
7b592f61
CW		 6214 /* check for unqualified module, if link is down */
6215 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6216 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6217 (!(status->link_info & I40E_AQ_LINK_UP)))
6218 dev_err(&pf->pdev->dev,
6219 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6220}
6221
6222/**
6223 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6224 * @pf: board private structure
6225 **/
6226static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6227{
6228 struct i40e_arq_event_info event;
6229 struct i40e_hw *hw = &pf->hw;
6230 u16 pending, i = 0;
6231 i40e_status ret;
6232 u16 opcode;
86df242b 6233 u32 oldval;
41c445ff
JB		 6234 u32 val;
6235
a316f651
ASJ		 6236 /* Do not run clean AQ when PF reset fails */
6237 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6238 return;
6239
86df242b
SN		 6240 /* check for error indications */
6241 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6242 oldval = val;
6243 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6244 if (hw->debug_mask & I40E_DEBUG_AQ)
6245 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6246 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6247 }
6248 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6249 if (hw->debug_mask & I40E_DEBUG_AQ)
6250 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6251 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6252 pf->arq_overflows++;
86df242b
SN		 6253 }
6254 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6255 if (hw->debug_mask & I40E_DEBUG_AQ)
6256 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6257 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6258 }
6259 if (oldval != val)
6260 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6261
6262 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6263 oldval = val;
6264 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6265 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6266 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6267 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6268 }
6269 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6270 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6271 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6272 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6273 }
6274 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6275 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6276 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6277 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6278 }
6279 if (oldval != val)
6280 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6281
1001dc37
MW		 6282 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6283 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6284 if (!event.msg_buf)
6285 return;
6286
6287 do {
6288 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6289 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6290 break;
56497978 6291 else if (ret) {
41c445ff
JB		 6292 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6293 break;
6294 }
6295
6296 opcode = le16_to_cpu(event.desc.opcode);
6297 switch (opcode) {
6298
6299 case i40e_aqc_opc_get_link_status:
6300 i40e_handle_link_event(pf, &event);
6301 break;
6302 case i40e_aqc_opc_send_msg_to_pf:
6303 ret = i40e_vc_process_vf_msg(pf,
6304 le16_to_cpu(event.desc.retval),
6305 le32_to_cpu(event.desc.cookie_high),
6306 le32_to_cpu(event.desc.cookie_low),
6307 event.msg_buf,
1001dc37 6308 event.msg_len);
41c445ff
JB		 6309 break;
6310 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6311 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6312#ifdef CONFIG_I40E_DCB
6313 rtnl_lock();
6314 ret = i40e_handle_lldp_event(pf, &event);
6315 rtnl_unlock();
6316#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6317 break;
6318 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6319 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6320 i40e_handle_lan_overflow_event(pf, &event);
6321 break;
0467bc91
SN		 6322 case i40e_aqc_opc_send_msg_to_peer:
6323 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6324 break;
91a0f930
SN		 6325 case i40e_aqc_opc_nvm_erase:
6326 case i40e_aqc_opc_nvm_update:
00ada50d 6327 case i40e_aqc_opc_oem_post_update:
91a0f930
SN		 6328 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6329 break;
41c445ff
JB		 6330 default:
6331 dev_info(&pf->pdev->dev,
0467bc91
SN		 6332 "ARQ Error: Unknown event 0x%04x received\n",
6333 opcode);
41c445ff
JB		 6334 break;
6335 }
6336 } while (pending && (i++ < pf->adminq_work_limit));
6337
6338 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6339 /* re-enable Admin queue interrupt cause */
6340 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6341 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6342 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6343 i40e_flush(hw);
6344
6345 kfree(event.msg_buf);
6346}
6347
4eb3f768
SN		 6348/**
6349 * i40e_verify_eeprom - make sure eeprom is good to use
6350 * @pf: board private structure
6351 **/
6352static void i40e_verify_eeprom(struct i40e_pf *pf)
6353{
6354 int err;
6355
6356 err = i40e_diag_eeprom_test(&pf->hw);
6357 if (err) {
6358 /* retry in case of garbage read */
6359 err = i40e_diag_eeprom_test(&pf->hw);
6360 if (err) {
6361 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6362 err);
6363 set_bit(__I40E_BAD_EEPROM, &pf->state);
6364 }
6365 }
6366
6367 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6368 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6369 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6370 }
6371}
6372
386a0afa
AA		 6373/**
6374 * i40e_enable_pf_switch_lb
b40c82e6 6375 * @pf: pointer to the PF structure
386a0afa
AA		 6376 *
6377 * enable switch loop back or die - no point in a return value
6378 **/
6379static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6380{
6381 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6382 struct i40e_vsi_context ctxt;
f1c7e72e 6383 int ret;
386a0afa
AA		 6384
6385 ctxt.seid = pf->main_vsi_seid;
6386 ctxt.pf_num = pf->hw.pf_id;
6387 ctxt.vf_num = 0;
f1c7e72e
SN		 6388 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6389 if (ret) {
386a0afa 6390 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6391 "couldn't get PF vsi config, err %s aq_err %s\n",
6392 i40e_stat_str(&pf->hw, ret),
6393 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6394 return;
6395 }
6396 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6397 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6398 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6399
f1c7e72e
SN		 6400 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6401 if (ret) {
386a0afa 6402 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6403 "update vsi switch failed, err %s aq_err %s\n",
6404 i40e_stat_str(&pf->hw, ret),
6405 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6406 }
6407}
6408
6409/**
6410 * i40e_disable_pf_switch_lb
b40c82e6 6411 * @pf: pointer to the PF structure
386a0afa
AA		 6412 *
6413 * disable switch loop back or die - no point in a return value
6414 **/
6415static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6416{
6417 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6418 struct i40e_vsi_context ctxt;
f1c7e72e 6419 int ret;
386a0afa
AA		 6420
6421 ctxt.seid = pf->main_vsi_seid;
6422 ctxt.pf_num = pf->hw.pf_id;
6423 ctxt.vf_num = 0;
f1c7e72e
SN		 6424 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6425 if (ret) {
386a0afa 6426 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6427 "couldn't get PF vsi config, err %s aq_err %s\n",
6428 i40e_stat_str(&pf->hw, ret),
6429 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6430 return;
6431 }
6432 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6433 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6434 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6435
f1c7e72e
SN		 6436 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6437 if (ret) {
386a0afa 6438 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6439 "update vsi switch failed, err %s aq_err %s\n",
6440 i40e_stat_str(&pf->hw, ret),
6441 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6442 }
6443}
6444
51616018
NP		 6445/**
6446 * i40e_config_bridge_mode - Configure the HW bridge mode
6447 * @veb: pointer to the bridge instance
6448 *
6449 * Configure the loop back mode for the LAN VSI that is downlink to the
6450 * specified HW bridge instance. It is expected this function is called
6451 * when a new HW bridge is instantiated.
6452 **/
6453static void i40e_config_bridge_mode(struct i40e_veb *veb)
6454{
6455 struct i40e_pf *pf = veb->pf;
6456
6dec1017
SN		 6457 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6458 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6459 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6460 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6461 i40e_disable_pf_switch_lb(pf);
6462 else
6463 i40e_enable_pf_switch_lb(pf);
6464}
6465
41c445ff
JB		 6466/**
6467 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6468 * @veb: pointer to the VEB instance
6469 *
6470 * This is a recursive function that first builds the attached VSIs then
6471 * recurses in to build the next layer of VEB. We track the connections
6472 * through our own index numbers because the seid's from the HW could
6473 * change across the reset.
6474 **/
6475static int i40e_reconstitute_veb(struct i40e_veb *veb)
6476{
6477 struct i40e_vsi *ctl_vsi = NULL;
6478 struct i40e_pf *pf = veb->pf;
6479 int v, veb_idx;
6480 int ret;
6481
6482 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6483 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6484 if (pf->vsi[v] &&
6485 pf->vsi[v]->veb_idx == veb->idx &&
6486 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6487 ctl_vsi = pf->vsi[v];
6488 break;
6489 }
6490 }
6491 if (!ctl_vsi) {
6492 dev_info(&pf->pdev->dev,
6493 "missing owner VSI for veb_idx %d\n", veb->idx);
6494 ret = -ENOENT;
6495 goto end_reconstitute;
6496 }
6497 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6498 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6499 ret = i40e_add_vsi(ctl_vsi);
6500 if (ret) {
6501 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6502 "rebuild of veb_idx %d owner VSI failed: %d\n",
6503 veb->idx, ret);
41c445ff
JB		 6504 goto end_reconstitute;
6505 }
6506 i40e_vsi_reset_stats(ctl_vsi);
6507
6508 /* create the VEB in the switch and move the VSI onto the VEB */
6509 ret = i40e_add_veb(veb, ctl_vsi);
6510 if (ret)
6511 goto end_reconstitute;
6512
fc60861e
ASJ		 6513 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6514 veb->bridge_mode = BRIDGE_MODE_VEB;
6515 else
6516 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6517 i40e_config_bridge_mode(veb);
b64ba084 6518
41c445ff 6519 /* create the remaining VSIs attached to this VEB */
505682cd 6520 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6521 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6522 continue;
6523
6524 if (pf->vsi[v]->veb_idx == veb->idx) {
6525 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6526
41c445ff
JB		 6527 vsi->uplink_seid = veb->seid;
6528 ret = i40e_add_vsi(vsi);
6529 if (ret) {
6530 dev_info(&pf->pdev->dev,
6531 "rebuild of vsi_idx %d failed: %d\n",
6532 v, ret);
6533 goto end_reconstitute;
6534 }
6535 i40e_vsi_reset_stats(vsi);
6536 }
6537 }
6538
6539 /* create any VEBs attached to this VEB - RECURSION */
6540 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6541 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6542 pf->veb[veb_idx]->uplink_seid = veb->seid;
6543 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6544 if (ret)
6545 break;
6546 }
6547 }
6548
6549end_reconstitute:
6550 return ret;
6551}
6552
6553/**
6554 * i40e_get_capabilities - get info about the HW
6555 * @pf: the PF struct
6556 **/
6557static int i40e_get_capabilities(struct i40e_pf *pf)
6558{
6559 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6560 u16 data_size;
6561 int buf_len;
6562 int err;
6563
6564 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6565 do {
6566 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6567 if (!cap_buf)
6568 return -ENOMEM;
6569
6570 /* this loads the data into the hw struct for us */
6571 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6572 &data_size,
6573 i40e_aqc_opc_list_func_capabilities,
6574 NULL);
6575 /* data loaded, buffer no longer needed */
6576 kfree(cap_buf);
6577
6578 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6579 /* retry with a larger buffer */
6580 buf_len = data_size;
6581 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6582 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6583 "capability discovery failed, err %s aq_err %s\n",
6584 i40e_stat_str(&pf->hw, err),
6585 i40e_aq_str(&pf->hw,
6586 pf->hw.aq.asq_last_status));
41c445ff
JB		 6587 return -ENODEV;
6588 }
6589 } while (err);
6590
6591 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6592 dev_info(&pf->pdev->dev,
6593 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6594 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6595 pf->hw.func_caps.num_msix_vectors,
6596 pf->hw.func_caps.num_msix_vectors_vf,
6597 pf->hw.func_caps.fd_filters_guaranteed,
6598 pf->hw.func_caps.fd_filters_best_effort,
6599 pf->hw.func_caps.num_tx_qp,
6600 pf->hw.func_caps.num_vsis);
6601
7134f9ce
JB		 6602#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6603 + pf->hw.func_caps.num_vfs)
6604 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6605 dev_info(&pf->pdev->dev,
6606 "got num_vsis %d, setting num_vsis to %d\n",
6607 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6608 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6609 }
6610
41c445ff
JB		 6611 return 0;
6612}
6613
cbf61325
ASJ		 6614static int i40e_vsi_clear(struct i40e_vsi *vsi);
6615
41c445ff 6616/**
cbf61325 6617 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6618 * @pf: board private structure
6619 **/
cbf61325 6620static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6621{
6622 struct i40e_vsi *vsi;
8a9eb7d3 6623 int i;
41c445ff 6624
407e063c
JB		 6625 /* quick workaround for an NVM issue that leaves a critical register
6626 * uninitialized
6627 */
6628 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6629 static const u32 hkey[] = {
6630 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6631 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6632 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6633 0x95b3a76d};
6634
6635 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6636 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6637 }
6638
cbf61325 6639 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6640 return;
6641
cbf61325 6642 /* find existing VSI and see if it needs configuring */
41c445ff 6643 vsi = NULL;
505682cd 6644 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6645 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6646 vsi = pf->vsi[i];
cbf61325
ASJ		 6647 break;
6648 }
6649 }
6650
6651 /* create a new VSI if none exists */
41c445ff 6652 if (!vsi) {
cbf61325
ASJ		 6653 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6654 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6655 if (!vsi) {
6656 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6657 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6658 return;
41c445ff 6659 }
cbf61325 6660 }
41c445ff 6661
8a9eb7d3 6662 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6663}
6664
6665/**
6666 * i40e_fdir_teardown - release the Flow Director resources
6667 * @pf: board private structure
6668 **/
6669static void i40e_fdir_teardown(struct i40e_pf *pf)
6670{
6671 int i;
6672
17a73f6b 6673 i40e_fdir_filter_exit(pf);
505682cd 6674 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6675 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6676 i40e_vsi_release(pf->vsi[i]);
6677 break;
6678 }
6679 }
6680}
6681
6682/**
f650a38b 6683 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6684 * @pf: board private structure
6685 *
b40c82e6 6686 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6687 **/
23cfbe07 6688static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6689{
41c445ff 6690 struct i40e_hw *hw = &pf->hw;
60442dea 6691 i40e_status ret = 0;
41c445ff
JB		 6692 u32 v;
6693
6694 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6695 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6696 return;
41c445ff 6697
69bfb110 6698 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6699
41c445ff
JB		 6700 /* quiesce the VSIs and their queues that are not already DOWN */
6701 i40e_pf_quiesce_all_vsi(pf);
6702
505682cd 6703 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6704 if (pf->vsi[v])
6705 pf->vsi[v]->seid = 0;
6706 }
6707
6708 i40e_shutdown_adminq(&pf->hw);
6709
f650a38b 6710 /* call shutdown HMC */
60442dea
SN		 6711 if (hw->hmc.hmc_obj) {
6712 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6713 if (ret)
60442dea
SN		 6714 dev_warn(&pf->pdev->dev,
6715 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6716 }
f650a38b
ASJ		 6717}
6718
44033fac
JB		 6719/**
6720 * i40e_send_version - update firmware with driver version
6721 * @pf: PF struct
6722 */
6723static void i40e_send_version(struct i40e_pf *pf)
6724{
6725 struct i40e_driver_version dv;
6726
6727 dv.major_version = DRV_VERSION_MAJOR;
6728 dv.minor_version = DRV_VERSION_MINOR;
6729 dv.build_version = DRV_VERSION_BUILD;
6730 dv.subbuild_version = 0;
35a7d804 6731 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6732 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6733}
6734
f650a38b 6735/**
4dda12e6 6736 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6737 * @pf: board private structure
bc7d338f 6738 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6739 **/
bc7d338f 6740static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6741{
f650a38b 6742 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6743 u8 set_fc_aq_fail = 0;
f650a38b 6744 i40e_status ret;
4f2f017c 6745 u32 val;
f650a38b
ASJ		 6746 u32 v;
6747
41c445ff
JB		 6748 /* Now we wait for GRST to settle out.
6749 * We don't have to delete the VEBs or VSIs from the hw switch
6750 * because the reset will make them disappear.
6751 */
6752 ret = i40e_pf_reset(hw);
b5565400 6753 if (ret) {
41c445ff 6754 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6755 set_bit(__I40E_RESET_FAILED, &pf->state);
6756 goto clear_recovery;
b5565400 6757 }
41c445ff
JB		 6758 pf->pfr_count++;
6759
6760 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6761 goto clear_recovery;
69bfb110 6762 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6763
6764 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6765 ret = i40e_init_adminq(&pf->hw);
6766 if (ret) {
f1c7e72e
SN		 6767 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6768 i40e_stat_str(&pf->hw, ret),
6769 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6770 goto clear_recovery;
41c445ff
JB		 6771 }
6772
4eb3f768 6773 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6774 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6775 i40e_verify_eeprom(pf);
4eb3f768 6776
e78ac4bf 6777 i40e_clear_pxe_mode(hw);
41c445ff 6778 ret = i40e_get_capabilities(pf);
f1c7e72e 6779 if (ret)
41c445ff 6780 goto end_core_reset;
41c445ff 6781
41c445ff
JB		 6782 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6783 hw->func_caps.num_rx_qp,
6784 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6785 if (ret) {
6786 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6787 goto end_core_reset;
6788 }
6789 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6790 if (ret) {
6791 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6792 goto end_core_reset;
6793 }
6794
4e3b35b0
NP		 6795#ifdef CONFIG_I40E_DCB
6796 ret = i40e_init_pf_dcb(pf);
6797 if (ret) {
aebfc816
SN		 6798 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6799 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6800 /* Continue without DCB enabled */
4e3b35b0
NP		 6801 }
6802#endif /* CONFIG_I40E_DCB */
38e00438 6803#ifdef I40E_FCOE
21364bcf 6804 i40e_init_pf_fcoe(pf);
4e3b35b0 6805
38e00438 6806#endif
41c445ff 6807 /* do basic switch setup */
bc7d338f 6808 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6809 if (ret)
6810 goto end_core_reset;
6811
2f0aff41
SN		 6812 /* The driver only wants link up/down and module qualification
6813 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6814 */
6815 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41
SN		 6816 ~(I40E_AQ_EVENT_LINK_UPDOWN |
6817 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6818 if (ret)
f1c7e72e
SN		 6819 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6820 i40e_stat_str(&pf->hw, ret),
6821 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6822
cafa2ee6
ASJ		 6823 /* make sure our flow control settings are restored */
6824 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6825 if (ret)
8279e495
NP		 6826 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6827 i40e_stat_str(&pf->hw, ret),
6828 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6829
41c445ff
JB		 6830 /* Rebuild the VSIs and VEBs that existed before reset.
6831 * They are still in our local switch element arrays, so only
6832 * need to rebuild the switch model in the HW.
6833 *
6834 * If there were VEBs but the reconstitution failed, we'll try
6835 * try to recover minimal use by getting the basic PF VSI working.
6836 */
6837 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6838 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6839 /* find the one VEB connected to the MAC, and find orphans */
6840 for (v = 0; v < I40E_MAX_VEB; v++) {
6841 if (!pf->veb[v])
6842 continue;
6843
6844 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6845 pf->veb[v]->uplink_seid == 0) {
6846 ret = i40e_reconstitute_veb(pf->veb[v]);
6847
6848 if (!ret)
6849 continue;
6850
6851 /* If Main VEB failed, we're in deep doodoo,
6852 * so give up rebuilding the switch and set up
6853 * for minimal rebuild of PF VSI.
6854 * If orphan failed, we'll report the error
6855 * but try to keep going.
6856 */
6857 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6858 dev_info(&pf->pdev->dev,
6859 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6860 ret);
6861 pf->vsi[pf->lan_vsi]->uplink_seid
6862 = pf->mac_seid;
6863 break;
6864 } else if (pf->veb[v]->uplink_seid == 0) {
6865 dev_info(&pf->pdev->dev,
6866 "rebuild of orphan VEB failed: %d\n",
6867 ret);
6868 }
6869 }
6870 }
6871 }
6872
6873 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6874 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6875 /* no VEB, so rebuild only the Main VSI */
6876 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6877 if (ret) {
6878 dev_info(&pf->pdev->dev,
6879 "rebuild of Main VSI failed: %d\n", ret);
6880 goto end_core_reset;
6881 }
6882 }
6883
4f2f017c
ASJ		 6884 /* Reconfigure hardware for allowing smaller MSS in the case
6885 * of TSO, so that we avoid the MDD being fired and causing
6886 * a reset in the case of small MSS+TSO.
6887 */
6888#define I40E_REG_MSS 0x000E64DC
6889#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6890#define I40E_64BYTE_MSS 0x400000
6891 val = rd32(hw, I40E_REG_MSS);
6892 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6893 val &= ~I40E_REG_MSS_MIN_MASK;
6894 val |= I40E_64BYTE_MSS;
6895 wr32(hw, I40E_REG_MSS, val);
6896 }
6897
8eed76fa 6898 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6899 msleep(75);
6900 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6901 if (ret)
f1c7e72e
SN		 6902 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6903 i40e_stat_str(&pf->hw, ret),
6904 i40e_aq_str(&pf->hw,
6905 pf->hw.aq.asq_last_status));
cafa2ee6 6906 }
41c445ff
JB		 6907 /* reinit the misc interrupt */
6908 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6909 ret = i40e_setup_misc_vector(pf);
6910
e7358f54
ASJ		 6911 /* Add a filter to drop all Flow control frames from any VSI from being
6912 * transmitted. By doing so we stop a malicious VF from sending out
6913 * PAUSE or PFC frames and potentially controlling traffic for other
6914 * PF/VF VSIs.
6915 * The FW can still send Flow control frames if enabled.
6916 */
6917 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6918 pf->main_vsi_seid);
6919
41c445ff
JB		 6920 /* restart the VSIs that were rebuilt and running before the reset */
6921 i40e_pf_unquiesce_all_vsi(pf);
6922
69f64b2b
MW		 6923 if (pf->num_alloc_vfs) {
6924 for (v = 0; v < pf->num_alloc_vfs; v++)
6925 i40e_reset_vf(&pf->vf[v], true);
6926 }
6927
41c445ff 6928 /* tell the firmware that we're starting */
44033fac 6929 i40e_send_version(pf);
41c445ff
JB		 6930
6931end_core_reset:
a316f651
ASJ		 6932 clear_bit(__I40E_RESET_FAILED, &pf->state);
6933clear_recovery:
41c445ff
JB		 6934 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6935}
6936
f650a38b 6937/**
b40c82e6 6938 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6939 * @pf: board private structure
6940 *
6941 * Close up the VFs and other things in prep for a Core Reset,
6942 * then get ready to rebuild the world.
6943 **/
6944static void i40e_handle_reset_warning(struct i40e_pf *pf)
6945{
23cfbe07
SN		 6946 i40e_prep_for_reset(pf);
6947 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6948}
6949
41c445ff
JB		 6950/**
6951 * i40e_handle_mdd_event
b40c82e6 6952 * @pf: pointer to the PF structure
41c445ff
JB		 6953 *
6954 * Called from the MDD irq handler to identify possibly malicious vfs
6955 **/
6956static void i40e_handle_mdd_event(struct i40e_pf *pf)
6957{
6958 struct i40e_hw *hw = &pf->hw;
6959 bool mdd_detected = false;
df430b12 6960 bool pf_mdd_detected = false;
41c445ff
JB		 6961 struct i40e_vf *vf;
6962 u32 reg;
6963 int i;
6964
6965 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6966 return;
6967
6968 /* find what triggered the MDD event */
6969 reg = rd32(hw, I40E_GL_MDET_TX);
6970 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6971 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6972 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6973 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6974 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6975 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6976 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6977 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6978 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6979 pf->hw.func_caps.base_queue;
faf32978 6980 if (netif_msg_tx_err(pf))
b40c82e6 6981 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6982 event, queue, pf_num, vf_num);
41c445ff
JB		 6983 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6984 mdd_detected = true;
6985 }
6986 reg = rd32(hw, I40E_GL_MDET_RX);
6987 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6988 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6989 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6990 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6991 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6992 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6993 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6994 pf->hw.func_caps.base_queue;
faf32978
JB		 6995 if (netif_msg_rx_err(pf))
6996 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6997 event, queue, func);
41c445ff
JB		 6998 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6999 mdd_detected = true;
7000 }
7001
df430b12
NP		 7002 if (mdd_detected) {
7003 reg = rd32(hw, I40E_PF_MDET_TX);
7004 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7005 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7006 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7007 pf_mdd_detected = true;
7008 }
7009 reg = rd32(hw, I40E_PF_MDET_RX);
7010 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7011 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7012 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7013 pf_mdd_detected = true;
7014 }
7015 /* Queue belongs to the PF, initiate a reset */
7016 if (pf_mdd_detected) {
7017 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7018 i40e_service_event_schedule(pf);
7019 }
7020 }
7021
41c445ff
JB		 7022 /* see if one of the VFs needs its hand slapped */
7023 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7024 vf = &(pf->vf[i]);
7025 reg = rd32(hw, I40E_VP_MDET_TX(i));
7026 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7027 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7028 vf->num_mdd_events++;
faf32978
JB		 7029 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7030 i);
41c445ff
JB		 7031 }
7032
7033 reg = rd32(hw, I40E_VP_MDET_RX(i));
7034 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7035 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7036 vf->num_mdd_events++;
faf32978
JB		 7037 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7038 i);
41c445ff
JB		 7039 }
7040
7041 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7042 dev_info(&pf->pdev->dev,
7043 "Too many MDD events on VF %d, disabled\n", i);
7044 dev_info(&pf->pdev->dev,
7045 "Use PF Control I/F to re-enable the VF\n");
7046 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7047 }
7048 }
7049
7050 /* re-enable mdd interrupt cause */
7051 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7052 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7053 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7054 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7055 i40e_flush(hw);
7056}
7057
a1c9a9d9 7058/**
6a899024 7059 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7060 * @pf: board private structure
7061 **/
6a899024 7062static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7063{
6a899024 7064#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9
JK		 7065 struct i40e_hw *hw = &pf->hw;
7066 i40e_status ret;
a1c9a9d9
JK		 7067 __be16 port;
7068 int i;
7069
6a899024 7070 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7071 return;
7072
6a899024 7073 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7074
7075 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7076 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7077 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7078 port = pf->udp_ports[i].index;
c22c06c8
SN		 7079 if (port)
7080 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7081 pf->udp_ports[i].type,
c22c06c8
SN		 7082 NULL, NULL);
7083 else
7084 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7085
7086 if (ret) {
c22c06c8 7087 dev_info(&pf->pdev->dev,
f1c7e72e 7088 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7089 port ? "add" : "delete",
f1c7e72e
SN		 7090 ntohs(port), i,
7091 i40e_stat_str(&pf->hw, ret),
7092 i40e_aq_str(&pf->hw,
7093 pf->hw.aq.asq_last_status));
6a899024 7094 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7095 }
7096 }
7097 }
6a899024 7098#endif
a1c9a9d9
JK		 7099}
7100
41c445ff
JB		 7101/**
7102 * i40e_service_task - Run the driver's async subtasks
7103 * @work: pointer to work_struct containing our data
7104 **/
7105static void i40e_service_task(struct work_struct *work)
7106{
7107 struct i40e_pf *pf = container_of(work,
7108 struct i40e_pf,
7109 service_task);
7110 unsigned long start_time = jiffies;
7111
e57a2fea
SN		 7112 /* don't bother with service tasks if a reset is in progress */
7113 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7114 i40e_service_event_complete(pf);
7115 return;
7116 }
7117
b03a8c1f 7118 i40e_detect_recover_hung(pf);
2818ccd9 7119 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7120 i40e_reset_subtask(pf);
7121 i40e_handle_mdd_event(pf);
7122 i40e_vc_process_vflr_event(pf);
7123 i40e_watchdog_subtask(pf);
7124 i40e_fdir_reinit_subtask(pf);
41c445ff 7125 i40e_sync_filters_subtask(pf);
6a899024 7126 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7127 i40e_clean_adminq_subtask(pf);
7128
7129 i40e_service_event_complete(pf);
7130
7131 /* If the tasks have taken longer than one timer cycle or there
7132 * is more work to be done, reschedule the service task now
7133 * rather than wait for the timer to tick again.
7134 */
7135 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7136 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7137 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7138 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7139 i40e_service_event_schedule(pf);
7140}
7141
7142/**
7143 * i40e_service_timer - timer callback
7144 * @data: pointer to PF struct
7145 **/
7146static void i40e_service_timer(unsigned long data)
7147{
7148 struct i40e_pf *pf = (struct i40e_pf *)data;
7149
7150 mod_timer(&pf->service_timer,
7151 round_jiffies(jiffies + pf->service_timer_period));
7152 i40e_service_event_schedule(pf);
7153}
7154
7155/**
7156 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7157 * @vsi: the VSI being configured
7158 **/
7159static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7160{
7161 struct i40e_pf *pf = vsi->back;
7162
7163 switch (vsi->type) {
7164 case I40E_VSI_MAIN:
7165 vsi->alloc_queue_pairs = pf->num_lan_qps;
7166 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7167 I40E_REQ_DESCRIPTOR_MULTIPLE);
7168 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7169 vsi->num_q_vectors = pf->num_lan_msix;
7170 else
7171 vsi->num_q_vectors = 1;
7172
7173 break;
7174
7175 case I40E_VSI_FDIR:
7176 vsi->alloc_queue_pairs = 1;
7177 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7178 I40E_REQ_DESCRIPTOR_MULTIPLE);
7179 vsi->num_q_vectors = 1;
7180 break;
7181
7182 case I40E_VSI_VMDQ2:
7183 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7184 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7185 I40E_REQ_DESCRIPTOR_MULTIPLE);
7186 vsi->num_q_vectors = pf->num_vmdq_msix;
7187 break;
7188
7189 case I40E_VSI_SRIOV:
7190 vsi->alloc_queue_pairs = pf->num_vf_qps;
7191 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7192 I40E_REQ_DESCRIPTOR_MULTIPLE);
7193 break;
7194
38e00438
VD		 7195#ifdef I40E_FCOE
7196 case I40E_VSI_FCOE:
7197 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7198 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7199 I40E_REQ_DESCRIPTOR_MULTIPLE);
7200 vsi->num_q_vectors = pf->num_fcoe_msix;
7201 break;
7202
7203#endif /* I40E_FCOE */
41c445ff
JB		 7204 default:
7205 WARN_ON(1);
7206 return -ENODATA;
7207 }
7208
7209 return 0;
7210}
7211
f650a38b
ASJ		 7212/**
7213 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7214 * @type: VSI pointer
bc7d338f 7215 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7216 *
7217 * On error: returns error code (negative)
7218 * On success: returns 0
7219 **/
bc7d338f 7220static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7221{
7222 int size;
7223 int ret = 0;
7224
ac6c5e3d 7225 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7226 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7227 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7228 if (!vsi->tx_rings)
7229 return -ENOMEM;
f650a38b
ASJ		 7230 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7231
bc7d338f
ASJ		 7232 if (alloc_qvectors) {
7233 /* allocate memory for q_vector pointers */
f57e4fbd 7234 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7235 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7236 if (!vsi->q_vectors) {
7237 ret = -ENOMEM;
7238 goto err_vectors;
7239 }
f650a38b
ASJ		 7240 }
7241 return ret;
7242
7243err_vectors:
7244 kfree(vsi->tx_rings);
7245 return ret;
7246}
7247
41c445ff
JB		 7248/**
7249 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7250 * @pf: board private structure
7251 * @type: type of VSI
7252 *
7253 * On error: returns error code (negative)
7254 * On success: returns vsi index in PF (positive)
7255 **/
7256static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7257{
7258 int ret = -ENODEV;
7259 struct i40e_vsi *vsi;
7260 int vsi_idx;
7261 int i;
7262
7263 /* Need to protect the allocation of the VSIs at the PF level */
7264 mutex_lock(&pf->switch_mutex);
7265
7266 /* VSI list may be fragmented if VSI creation/destruction has
7267 * been happening. We can afford to do a quick scan to look
7268 * for any free VSIs in the list.
7269 *
7270 * find next empty vsi slot, looping back around if necessary
7271 */
7272 i = pf->next_vsi;
505682cd 7273 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7274 i++;
505682cd 7275 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7276 i = 0;
7277 while (i < pf->next_vsi && pf->vsi[i])
7278 i++;
7279 }
7280
505682cd 7281 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7282 vsi_idx = i; /* Found one! */
7283 } else {
7284 ret = -ENODEV;
493fb300 7285 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7286 }
7287 pf->next_vsi = ++i;
7288
7289 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7290 if (!vsi) {
7291 ret = -ENOMEM;
493fb300 7292 goto unlock_pf;
41c445ff
JB		 7293 }
7294 vsi->type = type;
7295 vsi->back = pf;
7296 set_bit(__I40E_DOWN, &vsi->state);
7297 vsi->flags = 0;
7298 vsi->idx = vsi_idx;
7299 vsi->rx_itr_setting = pf->rx_itr_default;
7300 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7301 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7302 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7303 pf->rss_table_size : 64;
41c445ff
JB		 7304 vsi->netdev_registered = false;
7305 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7306 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7307 vsi->irqs_ready = false;
41c445ff 7308
9f65e15b
AD		 7309 ret = i40e_set_num_rings_in_vsi(vsi);
7310 if (ret)
7311 goto err_rings;
7312
bc7d338f 7313 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7314 if (ret)
9f65e15b 7315 goto err_rings;
493fb300 7316
41c445ff
JB		 7317 /* Setup default MSIX irq handler for VSI */
7318 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7319
21659035
KP		 7320 /* Initialize VSI lock */
7321 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7322 pf->vsi[vsi_idx] = vsi;
7323 ret = vsi_idx;
493fb300
AD		 7324 goto unlock_pf;
7325
9f65e15b 7326err_rings:
493fb300
AD		 7327 pf->next_vsi = i - 1;
7328 kfree(vsi);
7329unlock_pf:
41c445ff
JB		 7330 mutex_unlock(&pf->switch_mutex);
7331 return ret;
7332}
7333
f650a38b
ASJ		 7334/**
7335 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7336 * @type: VSI pointer
bc7d338f 7337 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7338 *
7339 * On error: returns error code (negative)
7340 * On success: returns 0
7341 **/
bc7d338f 7342static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7343{
7344 /* free the ring and vector containers */
bc7d338f
ASJ		 7345 if (free_qvectors) {
7346 kfree(vsi->q_vectors);
7347 vsi->q_vectors = NULL;
7348 }
f650a38b
ASJ		 7349 kfree(vsi->tx_rings);
7350 vsi->tx_rings = NULL;
7351 vsi->rx_rings = NULL;
7352}
7353
28c5869f
HZ		 7354/**
7355 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7356 * and lookup table
7357 * @vsi: Pointer to VSI structure
7358 */
7359static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7360{
7361 if (!vsi)
7362 return;
7363
7364 kfree(vsi->rss_hkey_user);
7365 vsi->rss_hkey_user = NULL;
7366
7367 kfree(vsi->rss_lut_user);
7368 vsi->rss_lut_user = NULL;
7369}
7370
41c445ff
JB		 7371/**
7372 * i40e_vsi_clear - Deallocate the VSI provided
7373 * @vsi: the VSI being un-configured
7374 **/
7375static int i40e_vsi_clear(struct i40e_vsi *vsi)
7376{
7377 struct i40e_pf *pf;
7378
7379 if (!vsi)
7380 return 0;
7381
7382 if (!vsi->back)
7383 goto free_vsi;
7384 pf = vsi->back;
7385
7386 mutex_lock(&pf->switch_mutex);
7387 if (!pf->vsi[vsi->idx]) {
7388 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7389 vsi->idx, vsi->idx, vsi, vsi->type);
7390 goto unlock_vsi;
7391 }
7392
7393 if (pf->vsi[vsi->idx] != vsi) {
7394 dev_err(&pf->pdev->dev,
7395 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7396 pf->vsi[vsi->idx]->idx,
7397 pf->vsi[vsi->idx],
7398 pf->vsi[vsi->idx]->type,
7399 vsi->idx, vsi, vsi->type);
7400 goto unlock_vsi;
7401 }
7402
b40c82e6 7403 /* updates the PF for this cleared vsi */
41c445ff
JB		 7404 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7405 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7406
bc7d338f 7407 i40e_vsi_free_arrays(vsi, true);
28c5869f 7408 i40e_clear_rss_config_user(vsi);
493fb300 7409
41c445ff
JB		 7410 pf->vsi[vsi->idx] = NULL;
7411 if (vsi->idx < pf->next_vsi)
7412 pf->next_vsi = vsi->idx;
7413
7414unlock_vsi:
7415 mutex_unlock(&pf->switch_mutex);
7416free_vsi:
7417 kfree(vsi);
7418
7419 return 0;
7420}
7421
9f65e15b
AD		 7422/**
7423 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7424 * @vsi: the VSI being cleaned
7425 **/
be1d5eea 7426static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7427{
7428 int i;
7429
8e9dca53 7430 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7431 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7432 kfree_rcu(vsi->tx_rings[i], rcu);
7433 vsi->tx_rings[i] = NULL;
7434 vsi->rx_rings[i] = NULL;
7435 }
be1d5eea 7436 }
9f65e15b
AD		 7437}
7438
41c445ff
JB		 7439/**
7440 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7441 * @vsi: the VSI being configured
7442 **/
7443static int i40e_alloc_rings(struct i40e_vsi *vsi)
7444{
e7046ee1 7445 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7446 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7447 int i;
7448
41c445ff 7449 /* Set basic values in the rings to be used later during open() */
d7397644 7450 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7451 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7452 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7453 if (!tx_ring)
7454 goto err_out;
41c445ff
JB		 7455
7456 tx_ring->queue_index = i;
7457 tx_ring->reg_idx = vsi->base_queue + i;
7458 tx_ring->ring_active = false;
7459 tx_ring->vsi = vsi;
7460 tx_ring->netdev = vsi->netdev;
7461 tx_ring->dev = &pf->pdev->dev;
7462 tx_ring->count = vsi->num_desc;
7463 tx_ring->size = 0;
7464 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7465 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7466 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7467 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7468 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7469 vsi->tx_rings[i] = tx_ring;
41c445ff 7470
9f65e15b 7471 rx_ring = &tx_ring[1];
41c445ff
JB		 7472 rx_ring->queue_index = i;
7473 rx_ring->reg_idx = vsi->base_queue + i;
7474 rx_ring->ring_active = false;
7475 rx_ring->vsi = vsi;
7476 rx_ring->netdev = vsi->netdev;
7477 rx_ring->dev = &pf->pdev->dev;
7478 rx_ring->count = vsi->num_desc;
7479 rx_ring->size = 0;
7480 rx_ring->dcb_tc = 0;
7481 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7482 set_ring_16byte_desc_enabled(rx_ring);
7483 else
7484 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7485 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7486 }
7487
7488 return 0;
9f65e15b
AD		 7489
7490err_out:
7491 i40e_vsi_clear_rings(vsi);
7492 return -ENOMEM;
41c445ff
JB		 7493}
7494
7495/**
7496 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7497 * @pf: board private structure
7498 * @vectors: the number of MSI-X vectors to request
7499 *
7500 * Returns the number of vectors reserved, or error
7501 **/
7502static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7503{
7b37f376
AG		 7504 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7505 I40E_MIN_MSIX, vectors);
7506 if (vectors < 0) {
41c445ff 7507 dev_info(&pf->pdev->dev,
7b37f376 7508 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7509 vectors = 0;
7510 }
7511
7512 return vectors;
7513}
7514
7515/**
7516 * i40e_init_msix - Setup the MSIX capability
7517 * @pf: board private structure
7518 *
7519 * Work with the OS to set up the MSIX vectors needed.
7520 *
3b444399 7521 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7522 **/
7523static int i40e_init_msix(struct i40e_pf *pf)
7524{
41c445ff 7525 struct i40e_hw *hw = &pf->hw;
1e200e4a 7526 int vectors_left;
41c445ff 7527 int v_budget, i;
3b444399 7528 int v_actual;
41c445ff
JB		 7529
7530 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7531 return -ENODEV;
7532
7533 /* The number of vectors we'll request will be comprised of:
7534 * - Add 1 for "other" cause for Admin Queue events, etc.
7535 * - The number of LAN queue pairs
f8ff1464
ASJ		 7536 * - Queues being used for RSS.
7537 * We don't need as many as max_rss_size vectors.
7538 * use rss_size instead in the calculation since that
7539 * is governed by number of cpus in the system.
7540 * - assumes symmetric Tx/Rx pairing
41c445ff 7541 * - The number of VMDq pairs
38e00438
VD		 7542#ifdef I40E_FCOE
7543 * - The number of FCOE qps.
7544#endif
41c445ff
JB		 7545 * Once we count this up, try the request.
7546 *
7547 * If we can't get what we want, we'll simplify to nearly nothing
7548 * and try again. If that still fails, we punt.
7549 */
1e200e4a
SN		 7550 vectors_left = hw->func_caps.num_msix_vectors;
7551 v_budget = 0;
7552
7553 /* reserve one vector for miscellaneous handler */
7554 if (vectors_left) {
7555 v_budget++;
7556 vectors_left--;
7557 }
7558
7559 /* reserve vectors for the main PF traffic queues */
7560 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7561 vectors_left -= pf->num_lan_msix;
7562 v_budget += pf->num_lan_msix;
7563
7564 /* reserve one vector for sideband flow director */
7565 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7566 if (vectors_left) {
7567 v_budget++;
7568 vectors_left--;
7569 } else {
7570 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7571 }
7572 }
83840e4b 7573
38e00438 7574#ifdef I40E_FCOE
1e200e4a 7575 /* can we reserve enough for FCoE? */
38e00438 7576 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7577 if (!vectors_left)
7578 pf->num_fcoe_msix = 0;
7579 else if (vectors_left >= pf->num_fcoe_qps)
7580 pf->num_fcoe_msix = pf->num_fcoe_qps;
7581 else
7582 pf->num_fcoe_msix = 1;
38e00438 7583 v_budget += pf->num_fcoe_msix;
1e200e4a 7584 vectors_left -= pf->num_fcoe_msix;
38e00438 7585 }
1e200e4a 7586
38e00438 7587#endif
1e200e4a
SN		 7588 /* any vectors left over go for VMDq support */
7589 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7590 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7591 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7592
7593 /* if we're short on vectors for what's desired, we limit
7594 * the queues per vmdq. If this is still more than are
7595 * available, the user will need to change the number of
7596 * queues/vectors used by the PF later with the ethtool
7597 * channels command
7598 */
7599 if (vmdq_vecs < vmdq_vecs_wanted)
7600 pf->num_vmdq_qps = 1;
7601 pf->num_vmdq_msix = pf->num_vmdq_qps;
7602
7603 v_budget += vmdq_vecs;
7604 vectors_left -= vmdq_vecs;
7605 }
41c445ff
JB		 7606
7607 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7608 GFP_KERNEL);
7609 if (!pf->msix_entries)
7610 return -ENOMEM;
7611
7612 for (i = 0; i < v_budget; i++)
7613 pf->msix_entries[i].entry = i;
3b444399 7614 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7615
3b444399 7616 if (v_actual != v_budget) {
a34977ba
ASJ		 7617 /* If we have limited resources, we will start with no vectors
7618 * for the special features and then allocate vectors to some
7619 * of these features based on the policy and at the end disable
7620 * the features that did not get any vectors.
7621 */
38e00438
VD		 7622#ifdef I40E_FCOE
7623 pf->num_fcoe_qps = 0;
7624 pf->num_fcoe_msix = 0;
7625#endif
a34977ba
ASJ		 7626 pf->num_vmdq_msix = 0;
7627 }
7628
3b444399 7629 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7630 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7631 kfree(pf->msix_entries);
7632 pf->msix_entries = NULL;
7633 return -ENODEV;
7634
3b444399 7635 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7636 /* Adjust for minimal MSIX use */
41c445ff
JB		 7637 pf->num_vmdq_vsis = 0;
7638 pf->num_vmdq_qps = 0;
41c445ff
JB		 7639 pf->num_lan_qps = 1;
7640 pf->num_lan_msix = 1;
7641
3b444399
SN		 7642 } else if (v_actual != v_budget) {
7643 int vec;
7644
a34977ba 7645 /* reserve the misc vector */
3b444399 7646 vec = v_actual - 1;
a34977ba 7647
41c445ff
JB		 7648 /* Scale vector usage down */
7649 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7650 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7651 pf->num_vmdq_qps = 1;
7652 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7653
7654 /* partition out the remaining vectors */
7655 switch (vec) {
7656 case 2:
41c445ff
JB		 7657 pf->num_lan_msix = 1;
7658 break;
7659 case 3:
38e00438
VD		 7660#ifdef I40E_FCOE
7661 /* give one vector to FCoE */
7662 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7663 pf->num_lan_msix = 1;
7664 pf->num_fcoe_msix = 1;
7665 }
7666#else
41c445ff 7667 pf->num_lan_msix = 2;
38e00438 7668#endif
41c445ff
JB		 7669 break;
7670 default:
38e00438
VD		 7671#ifdef I40E_FCOE
7672 /* give one vector to FCoE */
7673 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7674 pf->num_fcoe_msix = 1;
7675 vec--;
7676 }
7677#endif
1e200e4a
SN		 7678 /* give the rest to the PF */
7679 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7680 break;
7681 }
7682 }
7683
a34977ba
ASJ		 7684 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7685 (pf->num_vmdq_msix == 0)) {
7686 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7687 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7688 }
38e00438
VD		 7689#ifdef I40E_FCOE
7690
7691 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7692 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7693 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7694 }
7695#endif
3b444399 7696 return v_actual;
41c445ff
JB		 7697}
7698
493fb300 7699/**
90e04070 7700 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7701 * @vsi: the VSI being configured
7702 * @v_idx: index of the vector in the vsi struct
7703 *
7704 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7705 **/
90e04070 7706static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7707{
7708 struct i40e_q_vector *q_vector;
7709
7710 /* allocate q_vector */
7711 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7712 if (!q_vector)
7713 return -ENOMEM;
7714
7715 q_vector->vsi = vsi;
7716 q_vector->v_idx = v_idx;
7717 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7718 if (vsi->netdev)
7719 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7720 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7721
cd0b6fa6
AD		 7722 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7723 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7724
493fb300
AD		 7725 /* tie q_vector and vsi together */
7726 vsi->q_vectors[v_idx] = q_vector;
7727
7728 return 0;
7729}
7730
41c445ff 7731/**
90e04070 7732 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7733 * @vsi: the VSI being configured
7734 *
7735 * We allocate one q_vector per queue interrupt. If allocation fails we
7736 * return -ENOMEM.
7737 **/
90e04070 7738static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7739{
7740 struct i40e_pf *pf = vsi->back;
7741 int v_idx, num_q_vectors;
493fb300 7742 int err;
41c445ff
JB		 7743
7744 /* if not MSIX, give the one vector only to the LAN VSI */
7745 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7746 num_q_vectors = vsi->num_q_vectors;
7747 else if (vsi == pf->vsi[pf->lan_vsi])
7748 num_q_vectors = 1;
7749 else
7750 return -EINVAL;
7751
41c445ff 7752 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7753 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7754 if (err)
7755 goto err_out;
41c445ff
JB		 7756 }
7757
7758 return 0;
493fb300
AD		 7759
7760err_out:
7761 while (v_idx--)
7762 i40e_free_q_vector(vsi, v_idx);
7763
7764 return err;
41c445ff
JB		 7765}
7766
7767/**
7768 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7769 * @pf: board private structure to initialize
7770 **/
c1147280 7771static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7772{
3b444399
SN		 7773 int vectors = 0;
7774 ssize_t size;
41c445ff
JB		 7775
7776 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7777 vectors = i40e_init_msix(pf);
7778 if (vectors < 0) {
60ea5f83 7779 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7780#ifdef I40E_FCOE
7781 I40E_FLAG_FCOE_ENABLED |
7782#endif
60ea5f83 7783 I40E_FLAG_RSS_ENABLED |
4d9b6043 7784 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7785 I40E_FLAG_SRIOV_ENABLED |
7786 I40E_FLAG_FD_SB_ENABLED |
7787 I40E_FLAG_FD_ATR_ENABLED |
7788 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7789
7790 /* rework the queue expectations without MSIX */
7791 i40e_determine_queue_usage(pf);
7792 }
7793 }
7794
7795 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7796 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7797 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7798 vectors = pci_enable_msi(pf->pdev);
7799 if (vectors < 0) {
7800 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7801 vectors);
41c445ff
JB		 7802 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7803 }
3b444399 7804 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7805 }
7806
958a3e3b 7807 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7808 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7809
3b444399
SN		 7810 /* set up vector assignment tracking */
7811 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7812 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7813 if (!pf->irq_pile) {
7814 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7815 return -ENOMEM;
7816 }
3b444399
SN		 7817 pf->irq_pile->num_entries = vectors;
7818 pf->irq_pile->search_hint = 0;
7819
c1147280 7820 /* track first vector for misc interrupts, ignore return */
3b444399 7821 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7822
7823 return 0;
41c445ff
JB		 7824}
7825
7826/**
7827 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7828 * @pf: board private structure
7829 *
7830 * This sets up the handler for MSIX 0, which is used to manage the
7831 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7832 * when in MSI or Legacy interrupt mode.
7833 **/
7834static int i40e_setup_misc_vector(struct i40e_pf *pf)
7835{
7836 struct i40e_hw *hw = &pf->hw;
7837 int err = 0;
7838
7839 /* Only request the irq if this is the first time through, and
7840 * not when we're rebuilding after a Reset
7841 */
7842 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7843 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7844 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7845 if (err) {
7846 dev_info(&pf->pdev->dev,
77fa28be 7847 "request_irq for %s failed: %d\n",
b294ac70 7848 pf->int_name, err);
41c445ff
JB		 7849 return -EFAULT;
7850 }
7851 }
7852
ab437b5a 7853 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7854
7855 /* associate no queues to the misc vector */
7856 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7857 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7858
7859 i40e_flush(hw);
7860
7861 i40e_irq_dynamic_enable_icr0(pf);
7862
7863 return err;
7864}
7865
7866/**
e25d00b8
ASJ		 7867 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7868 * @vsi: vsi structure
7869 * @seed: RSS hash seed
7870 **/
e69ff813
HZ		 7871static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7872 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7873{
7874 struct i40e_aqc_get_set_rss_key_data rss_key;
7875 struct i40e_pf *pf = vsi->back;
7876 struct i40e_hw *hw = &pf->hw;
7877 bool pf_lut = false;
7878 u8 *rss_lut;
7879 int ret, i;
7880
7881 memset(&rss_key, 0, sizeof(rss_key));
7882 memcpy(&rss_key, seed, sizeof(rss_key));
7883
7884 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7885 if (!rss_lut)
7886 return -ENOMEM;
7887
7888 /* Populate the LUT with max no. of queues in round robin fashion */
7889 for (i = 0; i < vsi->rss_table_size; i++)
7890 rss_lut[i] = i % vsi->rss_size;
7891
7892 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7893 if (ret) {
7894 dev_info(&pf->pdev->dev,
7895 "Cannot set RSS key, err %s aq_err %s\n",
7896 i40e_stat_str(&pf->hw, ret),
7897 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7898 goto config_rss_aq_out;
e25d00b8
ASJ		 7899 }
7900
7901 if (vsi->type == I40E_VSI_MAIN)
7902 pf_lut = true;
7903
7904 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7905 vsi->rss_table_size);
7906 if (ret)
7907 dev_info(&pf->pdev->dev,
7908 "Cannot set RSS lut, err %s aq_err %s\n",
7909 i40e_stat_str(&pf->hw, ret),
7910 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7911
126b63d9
AS		 7912config_rss_aq_out:
7913 kfree(rss_lut);
e25d00b8
ASJ		 7914 return ret;
7915}
7916
7917/**
7918 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7919 * @vsi: VSI structure
7920 **/
7921static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7922{
7923 u8 seed[I40E_HKEY_ARRAY_SIZE];
7924 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7925 u8 *lut;
7926 int ret;
7927
7928 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7929 return 0;
7930
7931 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7932 if (!lut)
7933 return -ENOMEM;
e25d00b8 7934
e69ff813 7935 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7936 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7937 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7938 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7939 kfree(lut);
e25d00b8 7940
e69ff813 7941 return ret;
e25d00b8
ASJ		 7942}
7943
95a73780
ASJ		 7944/**
7945 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7946 * @vsi: Pointer to vsi structure
7947 * @seed: Buffter to store the hash keys
7948 * @lut: Buffer to store the lookup table entries
7949 * @lut_size: Size of buffer to store the lookup table entries
7950 *
7951 * Return 0 on success, negative on failure
7952 */
7953static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7954 u8 *lut, u16 lut_size)
7955{
7956 struct i40e_pf *pf = vsi->back;
7957 struct i40e_hw *hw = &pf->hw;
7958 int ret = 0;
7959
7960 if (seed) {
7961 ret = i40e_aq_get_rss_key(hw, vsi->id,
7962 (struct i40e_aqc_get_set_rss_key_data *)seed);
7963 if (ret) {
7964 dev_info(&pf->pdev->dev,
7965 "Cannot get RSS key, err %s aq_err %s\n",
7966 i40e_stat_str(&pf->hw, ret),
7967 i40e_aq_str(&pf->hw,
7968 pf->hw.aq.asq_last_status));
7969 return ret;
7970 }
7971 }
7972
7973 if (lut) {
7974 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
7975
7976 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
7977 if (ret) {
7978 dev_info(&pf->pdev->dev,
7979 "Cannot get RSS lut, err %s aq_err %s\n",
7980 i40e_stat_str(&pf->hw, ret),
7981 i40e_aq_str(&pf->hw,
7982 pf->hw.aq.asq_last_status));
7983 return ret;
7984 }
7985 }
7986
7987 return ret;
7988}
7989
e25d00b8 7990/**
043dd650 7991 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7992 * @vsi: Pointer to vsi structure
e25d00b8 7993 * @seed: RSS hash seed
e69ff813
HZ		 7994 * @lut: Lookup table
7995 * @lut_size: Lookup table size
7996 *
7997 * Returns 0 on success, negative on failure
41c445ff 7998 **/
e69ff813
HZ		 7999static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8000 const u8 *lut, u16 lut_size)
41c445ff 8001{
e69ff813 8002 struct i40e_pf *pf = vsi->back;
4617e8c0 8003 struct i40e_hw *hw = &pf->hw;
e69ff813 8004 u8 i;
41c445ff 8005
e25d00b8 8006 /* Fill out hash function seed */
e69ff813
HZ		 8007 if (seed) {
8008 u32 *seed_dw = (u32 *)seed;
8009
8010 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8011 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
8012 }
8013
8014 if (lut) {
8015 u32 *lut_dw = (u32 *)lut;
8016
8017 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8018 return -EINVAL;
8019
8020 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8021 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 8022 }
8023 i40e_flush(hw);
8024
8025 return 0;
8026}
8027
043dd650
HZ		 8028/**
8029 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8030 * @vsi: Pointer to VSI structure
8031 * @seed: Buffer to store the keys
8032 * @lut: Buffer to store the lookup table entries
8033 * @lut_size: Size of buffer to store the lookup table entries
8034 *
8035 * Returns 0 on success, negative on failure
8036 */
8037static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8038 u8 *lut, u16 lut_size)
8039{
8040 struct i40e_pf *pf = vsi->back;
8041 struct i40e_hw *hw = &pf->hw;
8042 u16 i;
8043
8044 if (seed) {
8045 u32 *seed_dw = (u32 *)seed;
8046
8047 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8048 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
8049 }
8050 if (lut) {
8051 u32 *lut_dw = (u32 *)lut;
8052
8053 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8054 return -EINVAL;
8055 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8056 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8057 }
8058
8059 return 0;
8060}
8061
8062/**
8063 * i40e_config_rss - Configure RSS keys and lut
8064 * @vsi: Pointer to VSI structure
8065 * @seed: RSS hash seed
8066 * @lut: Lookup table
8067 * @lut_size: Lookup table size
8068 *
8069 * Returns 0 on success, negative on failure
8070 */
8071int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8072{
8073 struct i40e_pf *pf = vsi->back;
8074
8075 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8076 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8077 else
8078 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8079}
8080
8081/**
8082 * i40e_get_rss - Get RSS keys and lut
8083 * @vsi: Pointer to VSI structure
8084 * @seed: Buffer to store the keys
8085 * @lut: Buffer to store the lookup table entries
8086 * lut_size: Size of buffer to store the lookup table entries
8087 *
8088 * Returns 0 on success, negative on failure
8089 */
8090int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8091{
95a73780
ASJ		 8092 struct i40e_pf *pf = vsi->back;
8093
8094 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8095 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8096 else
8097 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8098}
8099
e69ff813
HZ		 8100/**
8101 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8102 * @pf: Pointer to board private structure
8103 * @lut: Lookup table
8104 * @rss_table_size: Lookup table size
8105 * @rss_size: Range of queue number for hashing
8106 */
8107static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8108 u16 rss_table_size, u16 rss_size)
8109{
8110 u16 i;
8111
8112 for (i = 0; i < rss_table_size; i++)
8113 lut[i] = i % rss_size;
8114}
8115
e25d00b8 8116/**
043dd650 8117 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8118 * @pf: board private structure
8119 **/
043dd650 8120static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8121{
8122 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8123 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8124 u8 *lut;
e25d00b8
ASJ		 8125 struct i40e_hw *hw = &pf->hw;
8126 u32 reg_val;
8127 u64 hena;
e69ff813 8128 int ret;
e25d00b8 8129
41c445ff
JB		 8130 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8131 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8132 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8133 hena |= i40e_pf_get_default_rss_hena(pf);
8134
41c445ff
JB		 8135 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8136 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8137
e25d00b8 8138 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8139 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8140 reg_val = (pf->rss_table_size == 512) ?
8141 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8142 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8143 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8144
28c5869f
HZ		 8145 /* Determine the RSS size of the VSI */
8146 if (!vsi->rss_size)
acd65448
HZ		 8147 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8148 vsi->num_queue_pairs);
28c5869f 8149
e69ff813
HZ		 8150 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8151 if (!lut)
8152 return -ENOMEM;
8153
28c5869f
HZ		 8154 /* Use user configured lut if there is one, otherwise use default */
8155 if (vsi->rss_lut_user)
8156 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8157 else
8158 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8159
28c5869f
HZ		 8160 /* Use user configured hash key if there is one, otherwise
8161 * use default.
8162 */
8163 if (vsi->rss_hkey_user)
8164 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8165 else
8166 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8167 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8168 kfree(lut);
8169
8170 return ret;
41c445ff
JB		 8171}
8172
f8ff1464
ASJ		 8173/**
8174 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8175 * @pf: board private structure
8176 * @queue_count: the requested queue count for rss.
8177 *
8178 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8179 * count which may be different from the requested queue count.
8180 **/
8181int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8182{
9a3bd2f1
ASJ		 8183 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8184 int new_rss_size;
8185
f8ff1464
ASJ		 8186 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8187 return 0;
8188
9a3bd2f1 8189 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8190
9a3bd2f1
ASJ		 8191 if (queue_count != vsi->num_queue_pairs) {
8192 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8193 i40e_prep_for_reset(pf);
8194
acd65448 8195 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8196
8197 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8198
8199 /* Discard the user configured hash keys and lut, if less
8200 * queues are enabled.
8201 */
8202 if (queue_count < vsi->rss_size) {
8203 i40e_clear_rss_config_user(vsi);
8204 dev_dbg(&pf->pdev->dev,
8205 "discard user configured hash keys and lut\n");
8206 }
8207
8208 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8209 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8210 vsi->num_queue_pairs);
28c5869f 8211
043dd650 8212 i40e_pf_config_rss(pf);
f8ff1464 8213 }
e36b0b11
HZ		 8214 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8215 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8216 return pf->alloc_rss_size;
f8ff1464
ASJ		 8217}
8218
f4492db1
GR		 8219/**
8220 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8221 * @pf: board private structure
8222 **/
8223i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8224{
8225 i40e_status status;
8226 bool min_valid, max_valid;
8227 u32 max_bw, min_bw;
8228
8229 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8230 &min_valid, &max_valid);
8231
8232 if (!status) {
8233 if (min_valid)
8234 pf->npar_min_bw = min_bw;
8235 if (max_valid)
8236 pf->npar_max_bw = max_bw;
8237 }
8238
8239 return status;
8240}
8241
8242/**
8243 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8244 * @pf: board private structure
8245 **/
8246i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8247{
8248 struct i40e_aqc_configure_partition_bw_data bw_data;
8249 i40e_status status;
8250
b40c82e6 8251 /* Set the valid bit for this PF */
41a1d04b 8252 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8253 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8254 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8255
8256 /* Set the new bandwidths */
8257 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8258
8259 return status;
8260}
8261
8262/**
8263 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8264 * @pf: board private structure
8265 **/
8266i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8267{
8268 /* Commit temporary BW setting to permanent NVM image */
8269 enum i40e_admin_queue_err last_aq_status;
8270 i40e_status ret;
8271 u16 nvm_word;
8272
8273 if (pf->hw.partition_id != 1) {
8274 dev_info(&pf->pdev->dev,
8275 "Commit BW only works on partition 1! This is partition %d",
8276 pf->hw.partition_id);
8277 ret = I40E_NOT_SUPPORTED;
8278 goto bw_commit_out;
8279 }
8280
8281 /* Acquire NVM for read access */
8282 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8283 last_aq_status = pf->hw.aq.asq_last_status;
8284 if (ret) {
8285 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8286 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8287 i40e_stat_str(&pf->hw, ret),
8288 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8289 goto bw_commit_out;
8290 }
8291
8292 /* Read word 0x10 of NVM - SW compatibility word 1 */
8293 ret = i40e_aq_read_nvm(&pf->hw,
8294 I40E_SR_NVM_CONTROL_WORD,
8295 0x10, sizeof(nvm_word), &nvm_word,
8296 false, NULL);
8297 /* Save off last admin queue command status before releasing
8298 * the NVM
8299 */
8300 last_aq_status = pf->hw.aq.asq_last_status;
8301 i40e_release_nvm(&pf->hw);
8302 if (ret) {
f1c7e72e
SN		 8303 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8304 i40e_stat_str(&pf->hw, ret),
8305 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8306 goto bw_commit_out;
8307 }
8308
8309 /* Wait a bit for NVM release to complete */
8310 msleep(50);
8311
8312 /* Acquire NVM for write access */
8313 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8314 last_aq_status = pf->hw.aq.asq_last_status;
8315 if (ret) {
8316 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8317 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8318 i40e_stat_str(&pf->hw, ret),
8319 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8320 goto bw_commit_out;
8321 }
8322 /* Write it back out unchanged to initiate update NVM,
8323 * which will force a write of the shadow (alt) RAM to
8324 * the NVM - thus storing the bandwidth values permanently.
8325 */
8326 ret = i40e_aq_update_nvm(&pf->hw,
8327 I40E_SR_NVM_CONTROL_WORD,
8328 0x10, sizeof(nvm_word),
8329 &nvm_word, true, NULL);
8330 /* Save off last admin queue command status before releasing
8331 * the NVM
8332 */
8333 last_aq_status = pf->hw.aq.asq_last_status;
8334 i40e_release_nvm(&pf->hw);
8335 if (ret)
8336 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8337 "BW settings NOT SAVED, err %s aq_err %s\n",
8338 i40e_stat_str(&pf->hw, ret),
8339 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8340bw_commit_out:
8341
8342 return ret;
8343}
8344
41c445ff
JB		 8345/**
8346 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8347 * @pf: board private structure to initialize
8348 *
8349 * i40e_sw_init initializes the Adapter private data structure.
8350 * Fields are initialized based on PCI device information and
8351 * OS network device settings (MTU size).
8352 **/
8353static int i40e_sw_init(struct i40e_pf *pf)
8354{
8355 int err = 0;
8356 int size;
8357
8358 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8359 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8360 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8361 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8362 if (I40E_DEBUG_USER & debug)
8363 pf->hw.debug_mask = debug;
8364 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8365 I40E_DEFAULT_MSG_ENABLE);
8366 }
8367
8368 /* Set default capability flags */
8369 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8370 I40E_FLAG_MSI_ENABLED |
9ac77266 8371 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8372 I40E_FLAG_MSIX_ENABLED;
8373
8374 if (iommu_present(&pci_bus_type))
8375 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8376 else
8377 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8378
ca99eb99
MW		 8379 /* Set default ITR */
8380 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8381 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8382
7134f9ce
JB		 8383 /* Depending on PF configurations, it is possible that the RSS
8384 * maximum might end up larger than the available queues
8385 */
41a1d04b 8386 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8387 pf->alloc_rss_size = 1;
5db4cb59 8388 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8389 pf->rss_size_max = min_t(int, pf->rss_size_max,
8390 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8391 if (pf->hw.func_caps.rss) {
8392 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8393 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8394 num_online_cpus());
41c445ff
JB		 8395 }
8396
2050bc65 8397 /* MFP mode enabled */
c78b953e 8398 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8399 pf->flags |= I40E_FLAG_MFP_ENABLED;
8400 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8401 if (i40e_get_npar_bw_setting(pf))
8402 dev_warn(&pf->pdev->dev,
8403 "Could not get NPAR bw settings\n");
8404 else
8405 dev_info(&pf->pdev->dev,
8406 "Min BW = %8.8x, Max BW = %8.8x\n",
8407 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8408 }
8409
cbf61325
ASJ		 8410 /* FW/NVM is not yet fixed in this regard */
8411 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8412 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8413 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8414 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8415 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8416 pf->hw.num_partitions > 1)
cbf61325 8417 dev_info(&pf->pdev->dev,
0b67584f 8418 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8419 else
8420 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8421 pf->fdir_pf_filter_count =
8422 pf->hw.func_caps.fd_filters_guaranteed;
8423 pf->hw.fdir_shared_filter_count =
8424 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8425 }
8426
f1bbad33 8427 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8428 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8429 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8430 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8431 /* No DCB support for FW < v4.33 */
8432 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8433 }
8434
8435 /* Disable FW LLDP if FW < v4.3 */
8436 if (i40e_is_mac_710(&pf->hw) &&
8437 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8438 (pf->hw.aq.fw_maj_ver < 4)))
8439 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8440
8441 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8442 if (i40e_is_mac_710(&pf->hw) &&
8443 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8444 (pf->hw.aq.fw_maj_ver >= 5)))
8445 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8446
41c445ff 8447 if (pf->hw.func_caps.vmdq) {
41c445ff 8448 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8449 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8450 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8451 }
8452
38e00438 8453#ifdef I40E_FCOE
21364bcf 8454 i40e_init_pf_fcoe(pf);
38e00438
VD		 8455
8456#endif /* I40E_FCOE */
41c445ff 8457#ifdef CONFIG_PCI_IOV
ba252f13 8458 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8459 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8460 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8461 pf->num_req_vfs = min_t(int,
8462 pf->hw.func_caps.num_vfs,
8463 I40E_MAX_VF_COUNT);
8464 }
8465#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8466 if (pf->hw.mac.type == I40E_MAC_X722) {
8467 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8468 I40E_FLAG_128_QP_RSS_CAPABLE |
8469 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8470 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8471 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8472 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
f8db54cc 8473 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8474 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8475 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8476 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8477 ((pf->hw.aq.api_maj_ver == 1) &&
8478 (pf->hw.aq.api_min_ver > 4))) {
8479 /* Supported in FW API version higher than 1.4 */
8480 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8481 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8482 } else {
8483 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8484 }
a340c789 8485
41c445ff
JB		 8486 pf->eeprom_version = 0xDEAD;
8487 pf->lan_veb = I40E_NO_VEB;
8488 pf->lan_vsi = I40E_NO_VSI;
8489
d1a8d275
ASJ		 8490 /* By default FW has this off for performance reasons */
8491 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8492
41c445ff
JB		 8493 /* set up queue assignment tracking */
8494 size = sizeof(struct i40e_lump_tracking)
8495 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8496 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8497 if (!pf->qp_pile) {
8498 err = -ENOMEM;
8499 goto sw_init_done;
8500 }
8501 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8502 pf->qp_pile->search_hint = 0;
8503
327fe04b
ASJ		 8504 pf->tx_timeout_recovery_level = 1;
8505
41c445ff
JB		 8506 mutex_init(&pf->switch_mutex);
8507
c668a12c
GR		 8508 /* If NPAR is enabled nudge the Tx scheduler */
8509 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8510 i40e_set_npar_bw_setting(pf);
8511
41c445ff
JB		 8512sw_init_done:
8513 return err;
8514}
8515
7c3c288b
ASJ		 8516/**
8517 * i40e_set_ntuple - set the ntuple feature flag and take action
8518 * @pf: board private structure to initialize
8519 * @features: the feature set that the stack is suggesting
8520 *
8521 * returns a bool to indicate if reset needs to happen
8522 **/
8523bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8524{
8525 bool need_reset = false;
8526
8527 /* Check if Flow Director n-tuple support was enabled or disabled. If
8528 * the state changed, we need to reset.
8529 */
8530 if (features & NETIF_F_NTUPLE) {
8531 /* Enable filters and mark for reset */
8532 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8533 need_reset = true;
8534 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8535 } else {
8536 /* turn off filters, mark for reset and clear SW filter list */
8537 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8538 need_reset = true;
8539 i40e_fdir_filter_exit(pf);
8540 }
8541 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8542 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8543 /* reset fd counters */
8544 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8545 pf->fdir_pf_active_filters = 0;
8546 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8547 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8548 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8549 /* if ATR was auto disabled it can be re-enabled. */
8550 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8551 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8552 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8553 }
8554 return need_reset;
8555}
8556
41c445ff
JB		 8557/**
8558 * i40e_set_features - set the netdev feature flags
8559 * @netdev: ptr to the netdev being adjusted
8560 * @features: the feature set that the stack is suggesting
8561 **/
8562static int i40e_set_features(struct net_device *netdev,
8563 netdev_features_t features)
8564{
8565 struct i40e_netdev_priv *np = netdev_priv(netdev);
8566 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8567 struct i40e_pf *pf = vsi->back;
8568 bool need_reset;
41c445ff
JB		 8569
8570 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8571 i40e_vlan_stripping_enable(vsi);
8572 else
8573 i40e_vlan_stripping_disable(vsi);
8574
7c3c288b
ASJ		 8575 need_reset = i40e_set_ntuple(pf, features);
8576
8577 if (need_reset)
41a1d04b 8578 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8579
41c445ff
JB		 8580 return 0;
8581}
8582
6a899024 8583#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9 8584/**
6a899024 8585 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8586 * @pf: board private structure
8587 * @port: The UDP port to look up
8588 *
8589 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8590 **/
6a899024 8591static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8592{
8593 u8 i;
8594
8595 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8596 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8597 return i;
8598 }
8599
8600 return i;
8601}
8602
6a899024 8603#endif
5cae7615
ED		 8604
8605#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8606/**
8607 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8608 * @netdev: This physical port's netdev
8609 * @sa_family: Socket Family that VXLAN is notifying us about
8610 * @port: New UDP port number that VXLAN started listening to
8611 **/
8612static void i40e_add_vxlan_port(struct net_device *netdev,
8613 sa_family_t sa_family, __be16 port)
8614{
8615 struct i40e_netdev_priv *np = netdev_priv(netdev);
8616 struct i40e_vsi *vsi = np->vsi;
8617 struct i40e_pf *pf = vsi->back;
8618 u8 next_idx;
8619 u8 idx;
8620
8621 if (sa_family == AF_INET6)
8622 return;
8623
6a899024 8624 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8625
8626 /* Check if port already exists */
8627 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8628 netdev_info(netdev, "vxlan port %d already offloaded\n",
8629 ntohs(port));
a1c9a9d9
JK		 8630 return;
8631 }
8632
8633 /* Now check if there is space to add the new port */
6a899024 8634 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8635
8636 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8637 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8638 ntohs(port));
8639 return;
8640 }
8641
8642 /* New port: add it and mark its index in the bitmap */
6a899024
SA		 8643 pf->udp_ports[next_idx].index = port;
8644 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8645 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8646 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8647}
8648
8649/**
8650 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8651 * @netdev: This physical port's netdev
8652 * @sa_family: Socket Family that VXLAN is notifying us about
8653 * @port: UDP port number that VXLAN stopped listening to
8654 **/
8655static void i40e_del_vxlan_port(struct net_device *netdev,
8656 sa_family_t sa_family, __be16 port)
8657{
8658 struct i40e_netdev_priv *np = netdev_priv(netdev);
8659 struct i40e_vsi *vsi = np->vsi;
8660 struct i40e_pf *pf = vsi->back;
8661 u8 idx;
8662
8663 if (sa_family == AF_INET6)
8664 return;
8665
6a899024 8666 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8667
8668 /* Check if port already exists */
8669 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8670 /* if port exists, set it to 0 (mark for deletion)
8671 * and make it pending
8672 */
6a899024
SA		 8673 pf->udp_ports[idx].index = 0;
8674 pf->pending_udp_bitmap |= BIT_ULL(idx);
8675 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9 8676 } else {
c22c06c8 8677 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8678 ntohs(port));
8679 }
6a899024 8680}
5cae7615 8681#endif
6a899024 8682
5cae7615 8683#if IS_ENABLED(CONFIG_GENEVE)
6a899024
SA		 8684/**
8685 * i40e_add_geneve_port - Get notifications about GENEVE ports that come up
8686 * @netdev: This physical port's netdev
8687 * @sa_family: Socket Family that GENEVE is notifying us about
8688 * @port: New UDP port number that GENEVE started listening to
8689 **/
8690static void i40e_add_geneve_port(struct net_device *netdev,
8691 sa_family_t sa_family, __be16 port)
8692{
6a899024
SA		 8693 struct i40e_netdev_priv *np = netdev_priv(netdev);
8694 struct i40e_vsi *vsi = np->vsi;
8695 struct i40e_pf *pf = vsi->back;
8696 u8 next_idx;
8697 u8 idx;
8698
a340c789
AS		 8699 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8700 return;
8701
6a899024
SA		 8702 if (sa_family == AF_INET6)
8703 return;
8704
8705 idx = i40e_get_udp_port_idx(pf, port);
8706
8707 /* Check if port already exists */
8708 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8709 netdev_info(netdev, "udp port %d already offloaded\n",
8710 ntohs(port));
8711 return;
8712 }
8713
8714 /* Now check if there is space to add the new port */
8715 next_idx = i40e_get_udp_port_idx(pf, 0);
8716
8717 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8718 netdev_info(netdev, "maximum number of UDP ports reached, not adding port %d\n",
8719 ntohs(port));
8720 return;
8721 }
8722
8723 /* New port: add it and mark its index in the bitmap */
8724 pf->udp_ports[next_idx].index = port;
8725 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8726 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8727 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8728
8729 dev_info(&pf->pdev->dev, "adding geneve port %d\n", ntohs(port));
a1c9a9d9
JK		 8730}
8731
6a899024
SA		 8732/**
8733 * i40e_del_geneve_port - Get notifications about GENEVE ports that go away
8734 * @netdev: This physical port's netdev
8735 * @sa_family: Socket Family that GENEVE is notifying us about
8736 * @port: UDP port number that GENEVE stopped listening to
8737 **/
8738static void i40e_del_geneve_port(struct net_device *netdev,
8739 sa_family_t sa_family, __be16 port)
8740{
6a899024
SA		 8741 struct i40e_netdev_priv *np = netdev_priv(netdev);
8742 struct i40e_vsi *vsi = np->vsi;
8743 struct i40e_pf *pf = vsi->back;
8744 u8 idx;
8745
8746 if (sa_family == AF_INET6)
8747 return;
8748
a340c789
AS		 8749 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8750 return;
8751
6a899024
SA		 8752 idx = i40e_get_udp_port_idx(pf, port);
8753
8754 /* Check if port already exists */
8755 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8756 /* if port exists, set it to 0 (mark for deletion)
8757 * and make it pending
8758 */
8759 pf->udp_ports[idx].index = 0;
8760 pf->pending_udp_bitmap |= BIT_ULL(idx);
8761 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8762
8763 dev_info(&pf->pdev->dev, "deleting geneve port %d\n",
8764 ntohs(port));
8765 } else {
8766 netdev_warn(netdev, "geneve port %d was not found, not deleting\n",
8767 ntohs(port));
8768 }
6a899024 8769}
5cae7615 8770#endif
6a899024 8771
1f224ad2 8772static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8773 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8774{
8775 struct i40e_netdev_priv *np = netdev_priv(netdev);
8776 struct i40e_pf *pf = np->vsi->back;
8777 struct i40e_hw *hw = &pf->hw;
8778
8779 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8780 return -EOPNOTSUPP;
8781
8782 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8783 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8784
8785 return 0;
8786}
8787
2f90ade6
JB		 8788/**
8789 * i40e_ndo_fdb_add - add an entry to the hardware database
8790 * @ndm: the input from the stack
8791 * @tb: pointer to array of nladdr (unused)
8792 * @dev: the net device pointer
8793 * @addr: the MAC address entry being added
8794 * @flags: instructions from stack about fdb operation
8795 */
4ba0dea5
GR		 8796static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8797 struct net_device *dev,
f6f6424b 8798 const unsigned char *addr, u16 vid,
4ba0dea5 8799 u16 flags)
4ba0dea5
GR		 8800{
8801 struct i40e_netdev_priv *np = netdev_priv(dev);
8802 struct i40e_pf *pf = np->vsi->back;
8803 int err = 0;
8804
8805 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8806 return -EOPNOTSUPP;
8807
65891fea
OG		 8808 if (vid) {
8809 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8810 return -EINVAL;
8811 }
8812
4ba0dea5
GR		 8813 /* Hardware does not support aging addresses so if a
8814 * ndm_state is given only allow permanent addresses
8815 */
8816 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8817 netdev_info(dev, "FDB only supports static addresses\n");
8818 return -EINVAL;
8819 }
8820
8821 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8822 err = dev_uc_add_excl(dev, addr);
8823 else if (is_multicast_ether_addr(addr))
8824 err = dev_mc_add_excl(dev, addr);
8825 else
8826 err = -EINVAL;
8827
8828 /* Only return duplicate errors if NLM_F_EXCL is set */
8829 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8830 err = 0;
8831
8832 return err;
8833}
8834
51616018
NP		 8835/**
8836 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8837 * @dev: the netdev being configured
8838 * @nlh: RTNL message
8839 *
8840 * Inserts a new hardware bridge if not already created and
8841 * enables the bridging mode requested (VEB or VEPA). If the
8842 * hardware bridge has already been inserted and the request
8843 * is to change the mode then that requires a PF reset to
8844 * allow rebuild of the components with required hardware
8845 * bridge mode enabled.
8846 **/
8847static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8848 struct nlmsghdr *nlh,
8849 u16 flags)
51616018
NP		 8850{
8851 struct i40e_netdev_priv *np = netdev_priv(dev);
8852 struct i40e_vsi *vsi = np->vsi;
8853 struct i40e_pf *pf = vsi->back;
8854 struct i40e_veb *veb = NULL;
8855 struct nlattr *attr, *br_spec;
8856 int i, rem;
8857
8858 /* Only for PF VSI for now */
8859 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8860 return -EOPNOTSUPP;
8861
8862 /* Find the HW bridge for PF VSI */
8863 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8864 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8865 veb = pf->veb[i];
8866 }
8867
8868 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8869
8870 nla_for_each_nested(attr, br_spec, rem) {
8871 __u16 mode;
8872
8873 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8874 continue;
8875
8876 mode = nla_get_u16(attr);
8877 if ((mode != BRIDGE_MODE_VEPA) &&
8878 (mode != BRIDGE_MODE_VEB))
8879 return -EINVAL;
8880
8881 /* Insert a new HW bridge */
8882 if (!veb) {
8883 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8884 vsi->tc_config.enabled_tc);
8885 if (veb) {
8886 veb->bridge_mode = mode;
8887 i40e_config_bridge_mode(veb);
8888 } else {
8889 /* No Bridge HW offload available */
8890 return -ENOENT;
8891 }
8892 break;
8893 } else if (mode != veb->bridge_mode) {
8894 /* Existing HW bridge but different mode needs reset */
8895 veb->bridge_mode = mode;
fc60861e
ASJ		 8896 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8897 if (mode == BRIDGE_MODE_VEB)
8898 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8899 else
8900 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8901 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8902 break;
8903 }
8904 }
8905
8906 return 0;
8907}
8908
8909/**
8910 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8911 * @skb: skb buff
8912 * @pid: process id
8913 * @seq: RTNL message seq #
8914 * @dev: the netdev being configured
8915 * @filter_mask: unused
d4b2f9fe 8916 * @nlflags: netlink flags passed in
51616018
NP		 8917 *
8918 * Return the mode in which the hardware bridge is operating in
8919 * i.e VEB or VEPA.
8920 **/
51616018
NP		 8921static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8922 struct net_device *dev,
9f4ffc44
CW		 8923 u32 __always_unused filter_mask,
8924 int nlflags)
51616018
NP		 8925{
8926 struct i40e_netdev_priv *np = netdev_priv(dev);
8927 struct i40e_vsi *vsi = np->vsi;
8928 struct i40e_pf *pf = vsi->back;
8929 struct i40e_veb *veb = NULL;
8930 int i;
8931
8932 /* Only for PF VSI for now */
8933 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8934 return -EOPNOTSUPP;
8935
8936 /* Find the HW bridge for the PF VSI */
8937 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8938 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8939 veb = pf->veb[i];
8940 }
8941
8942 if (!veb)
8943 return 0;
8944
46c264da 8945 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8946 nlflags, 0, 0, filter_mask, NULL);
51616018 8947}
51616018 8948
6a899024
SA		 8949/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8950 * inner mac plus all inner ethertypes.
8951 */
8952#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8953/**
8954 * i40e_features_check - Validate encapsulated packet conforms to limits
8955 * @skb: skb buff
2bc11c63 8956 * @dev: This physical port's netdev
f44a75e2
JS		 8957 * @features: Offload features that the stack believes apply
8958 **/
8959static netdev_features_t i40e_features_check(struct sk_buff *skb,
8960 struct net_device *dev,
8961 netdev_features_t features)
8962{
8963 if (skb->encapsulation &&
6a899024 8964 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8965 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8966 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8967
8968 return features;
8969}
8970
37a2973a 8971static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8972 .ndo_open = i40e_open,
8973 .ndo_stop = i40e_close,
8974 .ndo_start_xmit = i40e_lan_xmit_frame,
8975 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8976 .ndo_set_rx_mode = i40e_set_rx_mode,
8977 .ndo_validate_addr = eth_validate_addr,
8978 .ndo_set_mac_address = i40e_set_mac,
8979 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8980 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8981 .ndo_tx_timeout = i40e_tx_timeout,
8982 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8983 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8984#ifdef CONFIG_NET_POLL_CONTROLLER
8985 .ndo_poll_controller = i40e_netpoll,
8986#endif
e4c6734e 8987 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 8988#ifdef I40E_FCOE
8989 .ndo_fcoe_enable = i40e_fcoe_enable,
8990 .ndo_fcoe_disable = i40e_fcoe_disable,
8991#endif
41c445ff
JB		 8992 .ndo_set_features = i40e_set_features,
8993 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8994 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8995 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8996 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8997 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8998 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6a899024 8999#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 9000 .ndo_add_vxlan_port = i40e_add_vxlan_port,
9001 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6a899024
SA		 9002#endif
9003#if IS_ENABLED(CONFIG_GENEVE)
9004 .ndo_add_geneve_port = i40e_add_geneve_port,
9005 .ndo_del_geneve_port = i40e_del_geneve_port,
a1c9a9d9 9006#endif
1f224ad2 9007 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 9008 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 9009 .ndo_features_check = i40e_features_check,
51616018
NP		 9010 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
9011 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 9012};
9013
9014/**
9015 * i40e_config_netdev - Setup the netdev flags
9016 * @vsi: the VSI being configured
9017 *
9018 * Returns 0 on success, negative value on failure
9019 **/
9020static int i40e_config_netdev(struct i40e_vsi *vsi)
9021{
1a10370a 9022 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 9023 struct i40e_pf *pf = vsi->back;
9024 struct i40e_hw *hw = &pf->hw;
9025 struct i40e_netdev_priv *np;
9026 struct net_device *netdev;
9027 u8 mac_addr[ETH_ALEN];
9028 int etherdev_size;
9029
9030 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9031 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9032 if (!netdev)
9033 return -ENOMEM;
9034
9035 vsi->netdev = netdev;
9036 np = netdev_priv(netdev);
9037 np->vsi = vsi;
9038
5afdaaa0
JB		 9039 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
9040 NETIF_F_GSO_UDP_TUNNEL |
9041 NETIF_F_GSO_GRE |
9042 NETIF_F_TSO |
9043 0;
41c445ff
JB		 9044
9045 netdev->features = NETIF_F_SG |
9046 NETIF_F_IP_CSUM |
53692b1d 9047 NETIF_F_SCTP_CRC |
41c445ff
JB		 9048 NETIF_F_HIGHDMA |
9049 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 9050 NETIF_F_GSO_GRE |
41c445ff
JB		 9051 NETIF_F_HW_VLAN_CTAG_TX |
9052 NETIF_F_HW_VLAN_CTAG_RX |
9053 NETIF_F_HW_VLAN_CTAG_FILTER |
9054 NETIF_F_IPV6_CSUM |
9055 NETIF_F_TSO |
059dab69 9056 NETIF_F_TSO_ECN |
41c445ff
JB		 9057 NETIF_F_TSO6 |
9058 NETIF_F_RXCSUM |
9059 NETIF_F_RXHASH |
9060 0;
9061
2e86a0b6
ASJ		 9062 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
9063 netdev->features |= NETIF_F_NTUPLE;
9064
41c445ff
JB		 9065 /* copy netdev features into list of user selectable features */
9066 netdev->hw_features |= netdev->features;
9067
9068 if (vsi->type == I40E_VSI_MAIN) {
9069 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9070 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9071 /* The following steps are necessary to prevent reception
9072 * of tagged packets - some older NVM configurations load a
9073 * default a MAC-VLAN filter that accepts any tagged packet
9074 * which must be replaced by a normal filter.
8c27d42e 9075 */
21659035
KP		 9076 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9077 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9078 i40e_add_filter(vsi, mac_addr,
9079 I40E_VLAN_ANY, false, true);
21659035
KP		 9080 spin_unlock_bh(&vsi->mac_filter_list_lock);
9081 }
41c445ff
JB		 9082 } else {
9083 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9084 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9085 pf->vsi[pf->lan_vsi]->netdev->name);
9086 random_ether_addr(mac_addr);
21659035
KP		 9087
9088 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9089 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9090 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9091 }
21659035
KP		 9092
9093 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9094 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9095 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9096
9a173901
GR		 9097 ether_addr_copy(netdev->dev_addr, mac_addr);
9098 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 9099 /* vlan gets same features (except vlan offload)
9100 * after any tweaks for specific VSI types
9101 */
9102 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
9103 NETIF_F_HW_VLAN_CTAG_RX |
9104 NETIF_F_HW_VLAN_CTAG_FILTER);
9105 netdev->priv_flags |= IFF_UNICAST_FLT;
9106 netdev->priv_flags |= IFF_SUPP_NOFCS;
9107 /* Setup netdev TC information */
9108 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9109
9110 netdev->netdev_ops = &i40e_netdev_ops;
9111 netdev->watchdog_timeo = 5 * HZ;
9112 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9113#ifdef I40E_FCOE
9114 i40e_fcoe_config_netdev(netdev, vsi);
9115#endif
41c445ff
JB		 9116
9117 return 0;
9118}
9119
9120/**
9121 * i40e_vsi_delete - Delete a VSI from the switch
9122 * @vsi: the VSI being removed
9123 *
9124 * Returns 0 on success, negative value on failure
9125 **/
9126static void i40e_vsi_delete(struct i40e_vsi *vsi)
9127{
9128 /* remove default VSI is not allowed */
9129 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9130 return;
9131
41c445ff 9132 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9133}
9134
51616018
NP		 9135/**
9136 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9137 * @vsi: the VSI being queried
9138 *
9139 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9140 **/
9141int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9142{
9143 struct i40e_veb *veb;
9144 struct i40e_pf *pf = vsi->back;
9145
9146 /* Uplink is not a bridge so default to VEB */
9147 if (vsi->veb_idx == I40E_NO_VEB)
9148 return 1;
9149
9150 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9151 if (!veb) {
9152 dev_info(&pf->pdev->dev,
9153 "There is no veb associated with the bridge\n");
9154 return -ENOENT;
9155 }
9156
51616018 9157 /* Uplink is a bridge in VEPA mode */
09603eaa 9158 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9159 return 0;
09603eaa
AA		 9160 } else {
9161 /* Uplink is a bridge in VEB mode */
9162 return 1;
9163 }
51616018 9164
09603eaa
AA		 9165 /* VEPA is now default bridge, so return 0 */
9166 return 0;
51616018
NP		 9167}
9168
41c445ff
JB		 9169/**
9170 * i40e_add_vsi - Add a VSI to the switch
9171 * @vsi: the VSI being configured
9172 *
9173 * This initializes a VSI context depending on the VSI type to be added and
9174 * passes it down to the add_vsi aq command.
9175 **/
9176static int i40e_add_vsi(struct i40e_vsi *vsi)
9177{
9178 int ret = -ENODEV;
21659035
KP		 9179 u8 laa_macaddr[ETH_ALEN];
9180 bool found_laa_mac_filter = false;
41c445ff
JB		 9181 struct i40e_pf *pf = vsi->back;
9182 struct i40e_hw *hw = &pf->hw;
9183 struct i40e_vsi_context ctxt;
21659035
KP		 9184 struct i40e_mac_filter *f, *ftmp;
9185
41c445ff
JB		 9186 u8 enabled_tc = 0x1; /* TC0 enabled */
9187 int f_count = 0;
9188
9189 memset(&ctxt, 0, sizeof(ctxt));
9190 switch (vsi->type) {
9191 case I40E_VSI_MAIN:
9192 /* The PF's main VSI is already setup as part of the
9193 * device initialization, so we'll not bother with
9194 * the add_vsi call, but we will retrieve the current
9195 * VSI context.
9196 */
9197 ctxt.seid = pf->main_vsi_seid;
9198 ctxt.pf_num = pf->hw.pf_id;
9199 ctxt.vf_num = 0;
9200 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9201 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9202 if (ret) {
9203 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9204 "couldn't get PF vsi config, err %s aq_err %s\n",
9205 i40e_stat_str(&pf->hw, ret),
9206 i40e_aq_str(&pf->hw,
9207 pf->hw.aq.asq_last_status));
41c445ff
JB		 9208 return -ENOENT;
9209 }
1a2f6248 9210 vsi->info = ctxt.info;
41c445ff
JB		 9211 vsi->info.valid_sections = 0;
9212
9213 vsi->seid = ctxt.seid;
9214 vsi->id = ctxt.vsi_number;
9215
9216 enabled_tc = i40e_pf_get_tc_map(pf);
9217
9218 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9219 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9220 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9221 memset(&ctxt, 0, sizeof(ctxt));
9222 ctxt.seid = pf->main_vsi_seid;
9223 ctxt.pf_num = pf->hw.pf_id;
9224 ctxt.vf_num = 0;
9225 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9226 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9227 if (ret) {
9228 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9229 "update vsi failed, err %s aq_err %s\n",
9230 i40e_stat_str(&pf->hw, ret),
9231 i40e_aq_str(&pf->hw,
9232 pf->hw.aq.asq_last_status));
41c445ff
JB		 9233 ret = -ENOENT;
9234 goto err;
9235 }
9236 /* update the local VSI info queue map */
9237 i40e_vsi_update_queue_map(vsi, &ctxt);
9238 vsi->info.valid_sections = 0;
9239 } else {
9240 /* Default/Main VSI is only enabled for TC0
9241 * reconfigure it to enable all TCs that are
9242 * available on the port in SFP mode.
63d7e5a4
NP		 9243 * For MFP case the iSCSI PF would use this
9244 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9245 */
9246 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9247 if (ret) {
9248 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9249 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9250 enabled_tc,
9251 i40e_stat_str(&pf->hw, ret),
9252 i40e_aq_str(&pf->hw,
9253 pf->hw.aq.asq_last_status));
41c445ff
JB		 9254 ret = -ENOENT;
9255 }
9256 }
9257 break;
9258
9259 case I40E_VSI_FDIR:
cbf61325
ASJ		 9260 ctxt.pf_num = hw->pf_id;
9261 ctxt.vf_num = 0;
9262 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9263 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9264 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9265 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9266 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9267 ctxt.info.valid_sections |=
fc60861e 9268 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9269 ctxt.info.switch_id =
fc60861e 9270 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9271 }
41c445ff 9272 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9273 break;
9274
9275 case I40E_VSI_VMDQ2:
9276 ctxt.pf_num = hw->pf_id;
9277 ctxt.vf_num = 0;
9278 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9279 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9280 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9281
41c445ff
JB		 9282 /* This VSI is connected to VEB so the switch_id
9283 * should be set to zero by default.
9284 */
51616018
NP		 9285 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9286 ctxt.info.valid_sections |=
9287 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9288 ctxt.info.switch_id =
9289 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9290 }
41c445ff
JB		 9291
9292 /* Setup the VSI tx/rx queue map for TC0 only for now */
9293 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9294 break;
9295
9296 case I40E_VSI_SRIOV:
9297 ctxt.pf_num = hw->pf_id;
9298 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9299 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9300 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9301 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9302
41c445ff
JB		 9303 /* This VSI is connected to VEB so the switch_id
9304 * should be set to zero by default.
9305 */
51616018
NP		 9306 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9307 ctxt.info.valid_sections |=
9308 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9309 ctxt.info.switch_id =
9310 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9311 }
41c445ff
JB		 9312
9313 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9314 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9315 if (pf->vf[vsi->vf_id].spoofchk) {
9316 ctxt.info.valid_sections |=
9317 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9318 ctxt.info.sec_flags |=
9319 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9320 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9321 }
41c445ff
JB		 9322 /* Setup the VSI tx/rx queue map for TC0 only for now */
9323 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9324 break;
9325
38e00438
VD		 9326#ifdef I40E_FCOE
9327 case I40E_VSI_FCOE:
9328 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9329 if (ret) {
9330 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9331 return ret;
9332 }
9333 break;
9334
9335#endif /* I40E_FCOE */
41c445ff
JB		 9336 default:
9337 return -ENODEV;
9338 }
9339
9340 if (vsi->type != I40E_VSI_MAIN) {
9341 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9342 if (ret) {
9343 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9344 "add vsi failed, err %s aq_err %s\n",
9345 i40e_stat_str(&pf->hw, ret),
9346 i40e_aq_str(&pf->hw,
9347 pf->hw.aq.asq_last_status));
41c445ff
JB		 9348 ret = -ENOENT;
9349 goto err;
9350 }
1a2f6248 9351 vsi->info = ctxt.info;
41c445ff
JB		 9352 vsi->info.valid_sections = 0;
9353 vsi->seid = ctxt.seid;
9354 vsi->id = ctxt.vsi_number;
9355 }
9356
21659035 9357 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9358 /* If macvlan filters already exist, force them to get loaded */
9359 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9360 f->changed = true;
9361 f_count++;
6252c7e4 9362
21659035 9363 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9364 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9365 ether_addr_copy(laa_macaddr, f->macaddr);
9366 found_laa_mac_filter = true;
9367 }
9368 }
9369 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9370
21659035
KP		 9371 if (found_laa_mac_filter) {
9372 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9373
21659035
KP		 9374 memset(&element, 0, sizeof(element));
9375 ether_addr_copy(element.mac_addr, laa_macaddr);
9376 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9377 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9378 &element, 1, NULL);
9379 if (ret) {
9380 /* some older FW has a different default */
9381 element.flags |=
9382 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9383 i40e_aq_remove_macvlan(hw, vsi->seid,
9384 &element, 1, NULL);
6252c7e4 9385 }
21659035
KP		 9386
9387 i40e_aq_mac_address_write(hw,
9388 I40E_AQC_WRITE_TYPE_LAA_WOL,
9389 laa_macaddr, NULL);
41c445ff 9390 }
21659035 9391
41c445ff
JB		 9392 if (f_count) {
9393 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9394 pf->flags |= I40E_FLAG_FILTER_SYNC;
9395 }
9396
9397 /* Update VSI BW information */
9398 ret = i40e_vsi_get_bw_info(vsi);
9399 if (ret) {
9400 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9401 "couldn't get vsi bw info, err %s aq_err %s\n",
9402 i40e_stat_str(&pf->hw, ret),
9403 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9404 /* VSI is already added so not tearing that up */
9405 ret = 0;
9406 }
9407
9408err:
9409 return ret;
9410}
9411
9412/**
9413 * i40e_vsi_release - Delete a VSI and free its resources
9414 * @vsi: the VSI being removed
9415 *
9416 * Returns 0 on success or < 0 on error
9417 **/
9418int i40e_vsi_release(struct i40e_vsi *vsi)
9419{
9420 struct i40e_mac_filter *f, *ftmp;
9421 struct i40e_veb *veb = NULL;
9422 struct i40e_pf *pf;
9423 u16 uplink_seid;
9424 int i, n;
9425
9426 pf = vsi->back;
9427
9428 /* release of a VEB-owner or last VSI is not allowed */
9429 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9430 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9431 vsi->seid, vsi->uplink_seid);
9432 return -ENODEV;
9433 }
9434 if (vsi == pf->vsi[pf->lan_vsi] &&
9435 !test_bit(__I40E_DOWN, &pf->state)) {
9436 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9437 return -ENODEV;
9438 }
9439
9440 uplink_seid = vsi->uplink_seid;
9441 if (vsi->type != I40E_VSI_SRIOV) {
9442 if (vsi->netdev_registered) {
9443 vsi->netdev_registered = false;
9444 if (vsi->netdev) {
9445 /* results in a call to i40e_close() */
9446 unregister_netdev(vsi->netdev);
41c445ff
JB		 9447 }
9448 } else {
90ef8d47 9449 i40e_vsi_close(vsi);
41c445ff
JB		 9450 }
9451 i40e_vsi_disable_irq(vsi);
9452 }
9453
21659035 9454 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9455 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9456 i40e_del_filter(vsi, f->macaddr, f->vlan,
9457 f->is_vf, f->is_netdev);
21659035
KP		 9458 spin_unlock_bh(&vsi->mac_filter_list_lock);
9459
17652c63 9460 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9461
9462 i40e_vsi_delete(vsi);
9463 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9464 if (vsi->netdev) {
9465 free_netdev(vsi->netdev);
9466 vsi->netdev = NULL;
9467 }
41c445ff
JB		 9468 i40e_vsi_clear_rings(vsi);
9469 i40e_vsi_clear(vsi);
9470
9471 /* If this was the last thing on the VEB, except for the
9472 * controlling VSI, remove the VEB, which puts the controlling
9473 * VSI onto the next level down in the switch.
9474 *
9475 * Well, okay, there's one more exception here: don't remove
9476 * the orphan VEBs yet. We'll wait for an explicit remove request
9477 * from up the network stack.
9478 */
505682cd 9479 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9480 if (pf->vsi[i] &&
9481 pf->vsi[i]->uplink_seid == uplink_seid &&
9482 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9483 n++; /* count the VSIs */
9484 }
9485 }
9486 for (i = 0; i < I40E_MAX_VEB; i++) {
9487 if (!pf->veb[i])
9488 continue;
9489 if (pf->veb[i]->uplink_seid == uplink_seid)
9490 n++; /* count the VEBs */
9491 if (pf->veb[i]->seid == uplink_seid)
9492 veb = pf->veb[i];
9493 }
9494 if (n == 0 && veb && veb->uplink_seid != 0)
9495 i40e_veb_release(veb);
9496
9497 return 0;
9498}
9499
9500/**
9501 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9502 * @vsi: ptr to the VSI
9503 *
9504 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9505 * corresponding SW VSI structure and initializes num_queue_pairs for the
9506 * newly allocated VSI.
9507 *
9508 * Returns 0 on success or negative on failure
9509 **/
9510static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9511{
9512 int ret = -ENOENT;
9513 struct i40e_pf *pf = vsi->back;
9514
493fb300 9515 if (vsi->q_vectors[0]) {
41c445ff
JB		 9516 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9517 vsi->seid);
9518 return -EEXIST;
9519 }
9520
9521 if (vsi->base_vector) {
f29eaa3d 9522 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9523 vsi->seid, vsi->base_vector);
9524 return -EEXIST;
9525 }
9526
90e04070 9527 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9528 if (ret) {
9529 dev_info(&pf->pdev->dev,
9530 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9531 vsi->num_q_vectors, vsi->seid, ret);
9532 vsi->num_q_vectors = 0;
9533 goto vector_setup_out;
9534 }
9535
26cdc443
ASJ		 9536 /* In Legacy mode, we do not have to get any other vector since we
9537 * piggyback on the misc/ICR0 for queue interrupts.
9538 */
9539 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9540 return ret;
958a3e3b
SN		 9541 if (vsi->num_q_vectors)
9542 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9543 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9544 if (vsi->base_vector < 0) {
9545 dev_info(&pf->pdev->dev,
049a2be8
SN		 9546 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9547 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9548 i40e_vsi_free_q_vectors(vsi);
9549 ret = -ENOENT;
9550 goto vector_setup_out;
9551 }
9552
9553vector_setup_out:
9554 return ret;
9555}
9556
bc7d338f
ASJ		 9557/**
9558 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9559 * @vsi: pointer to the vsi.
9560 *
9561 * This re-allocates a vsi's queue resources.
9562 *
9563 * Returns pointer to the successfully allocated and configured VSI sw struct
9564 * on success, otherwise returns NULL on failure.
9565 **/
9566static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9567{
9568 struct i40e_pf *pf = vsi->back;
9569 u8 enabled_tc;
9570 int ret;
9571
9572 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9573 i40e_vsi_clear_rings(vsi);
9574
9575 i40e_vsi_free_arrays(vsi, false);
9576 i40e_set_num_rings_in_vsi(vsi);
9577 ret = i40e_vsi_alloc_arrays(vsi, false);
9578 if (ret)
9579 goto err_vsi;
9580
9581 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9582 if (ret < 0) {
049a2be8 9583 dev_info(&pf->pdev->dev,
f1c7e72e 9584 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9585 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9586 goto err_vsi;
9587 }
9588 vsi->base_queue = ret;
9589
9590 /* Update the FW view of the VSI. Force a reset of TC and queue
9591 * layout configurations.
9592 */
9593 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9594 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9595 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9596 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9597
9598 /* assign it some queues */
9599 ret = i40e_alloc_rings(vsi);
9600 if (ret)
9601 goto err_rings;
9602
9603 /* map all of the rings to the q_vectors */
9604 i40e_vsi_map_rings_to_vectors(vsi);
9605 return vsi;
9606
9607err_rings:
9608 i40e_vsi_free_q_vectors(vsi);
9609 if (vsi->netdev_registered) {
9610 vsi->netdev_registered = false;
9611 unregister_netdev(vsi->netdev);
9612 free_netdev(vsi->netdev);
9613 vsi->netdev = NULL;
9614 }
9615 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9616err_vsi:
9617 i40e_vsi_clear(vsi);
9618 return NULL;
9619}
9620
b499ffb0
SV		 9621/**
9622 * i40e_macaddr_init - explicitly write the mac address filters.
9623 *
9624 * @vsi: pointer to the vsi.
9625 * @macaddr: the MAC address
9626 *
9627 * This is needed when the macaddr has been obtained by other
9628 * means than the default, e.g., from Open Firmware or IDPROM.
9629 * Returns 0 on success, negative on failure
9630 **/
9631static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9632{
9633 int ret;
9634 struct i40e_aqc_add_macvlan_element_data element;
9635
9636 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9637 I40E_AQC_WRITE_TYPE_LAA_WOL,
9638 macaddr, NULL);
9639 if (ret) {
9640 dev_info(&vsi->back->pdev->dev,
9641 "Addr change for VSI failed: %d\n", ret);
9642 return -EADDRNOTAVAIL;
9643 }
9644
9645 memset(&element, 0, sizeof(element));
9646 ether_addr_copy(element.mac_addr, macaddr);
9647 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9648 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9649 if (ret) {
9650 dev_info(&vsi->back->pdev->dev,
9651 "add filter failed err %s aq_err %s\n",
9652 i40e_stat_str(&vsi->back->hw, ret),
9653 i40e_aq_str(&vsi->back->hw,
9654 vsi->back->hw.aq.asq_last_status));
9655 }
9656 return ret;
9657}
9658
41c445ff
JB		 9659/**
9660 * i40e_vsi_setup - Set up a VSI by a given type
9661 * @pf: board private structure
9662 * @type: VSI type
9663 * @uplink_seid: the switch element to link to
9664 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9665 *
9666 * This allocates the sw VSI structure and its queue resources, then add a VSI
9667 * to the identified VEB.
9668 *
9669 * Returns pointer to the successfully allocated and configure VSI sw struct on
9670 * success, otherwise returns NULL on failure.
9671 **/
9672struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9673 u16 uplink_seid, u32 param1)
9674{
9675 struct i40e_vsi *vsi = NULL;
9676 struct i40e_veb *veb = NULL;
9677 int ret, i;
9678 int v_idx;
9679
9680 /* The requested uplink_seid must be either
9681 * - the PF's port seid
9682 * no VEB is needed because this is the PF
9683 * or this is a Flow Director special case VSI
9684 * - seid of an existing VEB
9685 * - seid of a VSI that owns an existing VEB
9686 * - seid of a VSI that doesn't own a VEB
9687 * a new VEB is created and the VSI becomes the owner
9688 * - seid of the PF VSI, which is what creates the first VEB
9689 * this is a special case of the previous
9690 *
9691 * Find which uplink_seid we were given and create a new VEB if needed
9692 */
9693 for (i = 0; i < I40E_MAX_VEB; i++) {
9694 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9695 veb = pf->veb[i];
9696 break;
9697 }
9698 }
9699
9700 if (!veb && uplink_seid != pf->mac_seid) {
9701
505682cd 9702 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9703 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9704 vsi = pf->vsi[i];
9705 break;
9706 }
9707 }
9708 if (!vsi) {
9709 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9710 uplink_seid);
9711 return NULL;
9712 }
9713
9714 if (vsi->uplink_seid == pf->mac_seid)
9715 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9716 vsi->tc_config.enabled_tc);
9717 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9718 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9719 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9720 if (veb) {
9721 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9722 dev_info(&vsi->back->pdev->dev,
fb43201f 9723 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9724 return NULL;
9725 }
fa11cb3d
ASJ		 9726 /* We come up by default in VEPA mode if SRIOV is not
9727 * already enabled, in which case we can't force VEPA
9728 * mode.
9729 */
9730 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9731 veb->bridge_mode = BRIDGE_MODE_VEPA;
9732 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9733 }
51616018 9734 i40e_config_bridge_mode(veb);
79c21a82 9735 }
41c445ff
JB		 9736 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9737 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9738 veb = pf->veb[i];
9739 }
9740 if (!veb) {
9741 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9742 return NULL;
9743 }
9744
9745 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9746 uplink_seid = veb->seid;
9747 }
9748
9749 /* get vsi sw struct */
9750 v_idx = i40e_vsi_mem_alloc(pf, type);
9751 if (v_idx < 0)
9752 goto err_alloc;
9753 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9754 if (!vsi)
9755 goto err_alloc;
41c445ff
JB		 9756 vsi->type = type;
9757 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9758
9759 if (type == I40E_VSI_MAIN)
9760 pf->lan_vsi = v_idx;
9761 else if (type == I40E_VSI_SRIOV)
9762 vsi->vf_id = param1;
9763 /* assign it some queues */
cbf61325
ASJ		 9764 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9765 vsi->idx);
41c445ff 9766 if (ret < 0) {
049a2be8
SN		 9767 dev_info(&pf->pdev->dev,
9768 "failed to get tracking for %d queues for VSI %d err=%d\n",
9769 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9770 goto err_vsi;
9771 }
9772 vsi->base_queue = ret;
9773
9774 /* get a VSI from the hardware */
9775 vsi->uplink_seid = uplink_seid;
9776 ret = i40e_add_vsi(vsi);
9777 if (ret)
9778 goto err_vsi;
9779
9780 switch (vsi->type) {
9781 /* setup the netdev if needed */
9782 case I40E_VSI_MAIN:
b499ffb0
SV		 9783 /* Apply relevant filters if a platform-specific mac
9784 * address was selected.
9785 */
9786 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9787 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9788 if (ret) {
9789 dev_warn(&pf->pdev->dev,
9790 "could not set up macaddr; err %d\n",
9791 ret);
9792 }
9793 }
41c445ff 9794 case I40E_VSI_VMDQ2:
38e00438 9795 case I40E_VSI_FCOE:
41c445ff
JB		 9796 ret = i40e_config_netdev(vsi);
9797 if (ret)
9798 goto err_netdev;
9799 ret = register_netdev(vsi->netdev);
9800 if (ret)
9801 goto err_netdev;
9802 vsi->netdev_registered = true;
9803 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9804#ifdef CONFIG_I40E_DCB
9805 /* Setup DCB netlink interface */
9806 i40e_dcbnl_setup(vsi);
9807#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9808 /* fall through */
9809
9810 case I40E_VSI_FDIR:
9811 /* set up vectors and rings if needed */
9812 ret = i40e_vsi_setup_vectors(vsi);
9813 if (ret)
9814 goto err_msix;
9815
9816 ret = i40e_alloc_rings(vsi);
9817 if (ret)
9818 goto err_rings;
9819
9820 /* map all of the rings to the q_vectors */
9821 i40e_vsi_map_rings_to_vectors(vsi);
9822
9823 i40e_vsi_reset_stats(vsi);
9824 break;
9825
9826 default:
9827 /* no netdev or rings for the other VSI types */
9828 break;
9829 }
9830
e25d00b8
ASJ		 9831 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9832 (vsi->type == I40E_VSI_VMDQ2)) {
9833 ret = i40e_vsi_config_rss(vsi);
9834 }
41c445ff
JB		 9835 return vsi;
9836
9837err_rings:
9838 i40e_vsi_free_q_vectors(vsi);
9839err_msix:
9840 if (vsi->netdev_registered) {
9841 vsi->netdev_registered = false;
9842 unregister_netdev(vsi->netdev);
9843 free_netdev(vsi->netdev);
9844 vsi->netdev = NULL;
9845 }
9846err_netdev:
9847 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9848err_vsi:
9849 i40e_vsi_clear(vsi);
9850err_alloc:
9851 return NULL;
9852}
9853
9854/**
9855 * i40e_veb_get_bw_info - Query VEB BW information
9856 * @veb: the veb to query
9857 *
9858 * Query the Tx scheduler BW configuration data for given VEB
9859 **/
9860static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9861{
9862 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9863 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9864 struct i40e_pf *pf = veb->pf;
9865 struct i40e_hw *hw = &pf->hw;
9866 u32 tc_bw_max;
9867 int ret = 0;
9868 int i;
9869
9870 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9871 &bw_data, NULL);
9872 if (ret) {
9873 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9874 "query veb bw config failed, err %s aq_err %s\n",
9875 i40e_stat_str(&pf->hw, ret),
9876 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9877 goto out;
9878 }
9879
9880 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9881 &ets_data, NULL);
9882 if (ret) {
9883 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9884 "query veb bw ets config failed, err %s aq_err %s\n",
9885 i40e_stat_str(&pf->hw, ret),
9886 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9887 goto out;
9888 }
9889
9890 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9891 veb->bw_max_quanta = ets_data.tc_bw_max;
9892 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9893 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9894 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9895 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9896 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9897 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9898 veb->bw_tc_limit_credits[i] =
9899 le16_to_cpu(bw_data.tc_bw_limits[i]);
9900 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9901 }
9902
9903out:
9904 return ret;
9905}
9906
9907/**
9908 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9909 * @pf: board private structure
9910 *
9911 * On error: returns error code (negative)
9912 * On success: returns vsi index in PF (positive)
9913 **/
9914static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9915{
9916 int ret = -ENOENT;
9917 struct i40e_veb *veb;
9918 int i;
9919
9920 /* Need to protect the allocation of switch elements at the PF level */
9921 mutex_lock(&pf->switch_mutex);
9922
9923 /* VEB list may be fragmented if VEB creation/destruction has
9924 * been happening. We can afford to do a quick scan to look
9925 * for any free slots in the list.
9926 *
9927 * find next empty veb slot, looping back around if necessary
9928 */
9929 i = 0;
9930 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9931 i++;
9932 if (i >= I40E_MAX_VEB) {
9933 ret = -ENOMEM;
9934 goto err_alloc_veb; /* out of VEB slots! */
9935 }
9936
9937 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9938 if (!veb) {
9939 ret = -ENOMEM;
9940 goto err_alloc_veb;
9941 }
9942 veb->pf = pf;
9943 veb->idx = i;
9944 veb->enabled_tc = 1;
9945
9946 pf->veb[i] = veb;
9947 ret = i;
9948err_alloc_veb:
9949 mutex_unlock(&pf->switch_mutex);
9950 return ret;
9951}
9952
9953/**
9954 * i40e_switch_branch_release - Delete a branch of the switch tree
9955 * @branch: where to start deleting
9956 *
9957 * This uses recursion to find the tips of the branch to be
9958 * removed, deleting until we get back to and can delete this VEB.
9959 **/
9960static void i40e_switch_branch_release(struct i40e_veb *branch)
9961{
9962 struct i40e_pf *pf = branch->pf;
9963 u16 branch_seid = branch->seid;
9964 u16 veb_idx = branch->idx;
9965 int i;
9966
9967 /* release any VEBs on this VEB - RECURSION */
9968 for (i = 0; i < I40E_MAX_VEB; i++) {
9969 if (!pf->veb[i])
9970 continue;
9971 if (pf->veb[i]->uplink_seid == branch->seid)
9972 i40e_switch_branch_release(pf->veb[i]);
9973 }
9974
9975 /* Release the VSIs on this VEB, but not the owner VSI.
9976 *
9977 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9978 * the VEB itself, so don't use (*branch) after this loop.
9979 */
505682cd 9980 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9981 if (!pf->vsi[i])
9982 continue;
9983 if (pf->vsi[i]->uplink_seid == branch_seid &&
9984 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9985 i40e_vsi_release(pf->vsi[i]);
9986 }
9987 }
9988
9989 /* There's one corner case where the VEB might not have been
9990 * removed, so double check it here and remove it if needed.
9991 * This case happens if the veb was created from the debugfs
9992 * commands and no VSIs were added to it.
9993 */
9994 if (pf->veb[veb_idx])
9995 i40e_veb_release(pf->veb[veb_idx]);
9996}
9997
9998/**
9999 * i40e_veb_clear - remove veb struct
10000 * @veb: the veb to remove
10001 **/
10002static void i40e_veb_clear(struct i40e_veb *veb)
10003{
10004 if (!veb)
10005 return;
10006
10007 if (veb->pf) {
10008 struct i40e_pf *pf = veb->pf;
10009
10010 mutex_lock(&pf->switch_mutex);
10011 if (pf->veb[veb->idx] == veb)
10012 pf->veb[veb->idx] = NULL;
10013 mutex_unlock(&pf->switch_mutex);
10014 }
10015
10016 kfree(veb);
10017}
10018
10019/**
10020 * i40e_veb_release - Delete a VEB and free its resources
10021 * @veb: the VEB being removed
10022 **/
10023void i40e_veb_release(struct i40e_veb *veb)
10024{
10025 struct i40e_vsi *vsi = NULL;
10026 struct i40e_pf *pf;
10027 int i, n = 0;
10028
10029 pf = veb->pf;
10030
10031 /* find the remaining VSI and check for extras */
505682cd 10032 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10033 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10034 n++;
10035 vsi = pf->vsi[i];
10036 }
10037 }
10038 if (n != 1) {
10039 dev_info(&pf->pdev->dev,
10040 "can't remove VEB %d with %d VSIs left\n",
10041 veb->seid, n);
10042 return;
10043 }
10044
10045 /* move the remaining VSI to uplink veb */
10046 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10047 if (veb->uplink_seid) {
10048 vsi->uplink_seid = veb->uplink_seid;
10049 if (veb->uplink_seid == pf->mac_seid)
10050 vsi->veb_idx = I40E_NO_VEB;
10051 else
10052 vsi->veb_idx = veb->veb_idx;
10053 } else {
10054 /* floating VEB */
10055 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10056 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10057 }
10058
10059 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10060 i40e_veb_clear(veb);
41c445ff
JB		 10061}
10062
10063/**
10064 * i40e_add_veb - create the VEB in the switch
10065 * @veb: the VEB to be instantiated
10066 * @vsi: the controlling VSI
10067 **/
10068static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10069{
f1c7e72e 10070 struct i40e_pf *pf = veb->pf;
92faef85 10071 bool is_default = veb->pf->cur_promisc;
e1c51b95 10072 bool is_cloud = false;
41c445ff
JB		 10073 int ret;
10074
10075 /* get a VEB from the hardware */
f1c7e72e 10076 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95 10077 veb->enabled_tc, is_default,
8a187f44 10078 &veb->seid, is_cloud, NULL);
41c445ff 10079 if (ret) {
f1c7e72e
SN		 10080 dev_info(&pf->pdev->dev,
10081 "couldn't add VEB, err %s aq_err %s\n",
10082 i40e_stat_str(&pf->hw, ret),
10083 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10084 return -EPERM;
10085 }
10086
10087 /* get statistics counter */
f1c7e72e 10088 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10089 &veb->stats_idx, NULL, NULL, NULL);
10090 if (ret) {
f1c7e72e
SN		 10091 dev_info(&pf->pdev->dev,
10092 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10093 i40e_stat_str(&pf->hw, ret),
10094 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10095 return -EPERM;
10096 }
10097 ret = i40e_veb_get_bw_info(veb);
10098 if (ret) {
f1c7e72e
SN		 10099 dev_info(&pf->pdev->dev,
10100 "couldn't get VEB bw info, err %s aq_err %s\n",
10101 i40e_stat_str(&pf->hw, ret),
10102 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10103 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10104 return -ENOENT;
10105 }
10106
10107 vsi->uplink_seid = veb->seid;
10108 vsi->veb_idx = veb->idx;
10109 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10110
10111 return 0;
10112}
10113
10114/**
10115 * i40e_veb_setup - Set up a VEB
10116 * @pf: board private structure
10117 * @flags: VEB setup flags
10118 * @uplink_seid: the switch element to link to
10119 * @vsi_seid: the initial VSI seid
10120 * @enabled_tc: Enabled TC bit-map
10121 *
10122 * This allocates the sw VEB structure and links it into the switch
10123 * It is possible and legal for this to be a duplicate of an already
10124 * existing VEB. It is also possible for both uplink and vsi seids
10125 * to be zero, in order to create a floating VEB.
10126 *
10127 * Returns pointer to the successfully allocated VEB sw struct on
10128 * success, otherwise returns NULL on failure.
10129 **/
10130struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10131 u16 uplink_seid, u16 vsi_seid,
10132 u8 enabled_tc)
10133{
10134 struct i40e_veb *veb, *uplink_veb = NULL;
10135 int vsi_idx, veb_idx;
10136 int ret;
10137
10138 /* if one seid is 0, the other must be 0 to create a floating relay */
10139 if ((uplink_seid == 0 || vsi_seid == 0) &&
10140 (uplink_seid + vsi_seid != 0)) {
10141 dev_info(&pf->pdev->dev,
10142 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10143 uplink_seid, vsi_seid);
10144 return NULL;
10145 }
10146
10147 /* make sure there is such a vsi and uplink */
505682cd 10148 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10149 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10150 break;
505682cd 10151 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10152 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10153 vsi_seid);
10154 return NULL;
10155 }
10156
10157 if (uplink_seid && uplink_seid != pf->mac_seid) {
10158 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10159 if (pf->veb[veb_idx] &&
10160 pf->veb[veb_idx]->seid == uplink_seid) {
10161 uplink_veb = pf->veb[veb_idx];
10162 break;
10163 }
10164 }
10165 if (!uplink_veb) {
10166 dev_info(&pf->pdev->dev,
10167 "uplink seid %d not found\n", uplink_seid);
10168 return NULL;
10169 }
10170 }
10171
10172 /* get veb sw struct */
10173 veb_idx = i40e_veb_mem_alloc(pf);
10174 if (veb_idx < 0)
10175 goto err_alloc;
10176 veb = pf->veb[veb_idx];
10177 veb->flags = flags;
10178 veb->uplink_seid = uplink_seid;
10179 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10180 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10181
10182 /* create the VEB in the switch */
10183 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10184 if (ret)
10185 goto err_veb;
1bb8b935
SN		 10186 if (vsi_idx == pf->lan_vsi)
10187 pf->lan_veb = veb->idx;
41c445ff
JB		 10188
10189 return veb;
10190
10191err_veb:
10192 i40e_veb_clear(veb);
10193err_alloc:
10194 return NULL;
10195}
10196
10197/**
b40c82e6 10198 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10199 * @pf: board private structure
10200 * @ele: element we are building info from
10201 * @num_reported: total number of elements
10202 * @printconfig: should we print the contents
10203 *
10204 * helper function to assist in extracting a few useful SEID values.
10205 **/
10206static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10207 struct i40e_aqc_switch_config_element_resp *ele,
10208 u16 num_reported, bool printconfig)
10209{
10210 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10211 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10212 u8 element_type = ele->element_type;
10213 u16 seid = le16_to_cpu(ele->seid);
10214
10215 if (printconfig)
10216 dev_info(&pf->pdev->dev,
10217 "type=%d seid=%d uplink=%d downlink=%d\n",
10218 element_type, seid, uplink_seid, downlink_seid);
10219
10220 switch (element_type) {
10221 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10222 pf->mac_seid = seid;
10223 break;
10224 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10225 /* Main VEB? */
10226 if (uplink_seid != pf->mac_seid)
10227 break;
10228 if (pf->lan_veb == I40E_NO_VEB) {
10229 int v;
10230
10231 /* find existing or else empty VEB */
10232 for (v = 0; v < I40E_MAX_VEB; v++) {
10233 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10234 pf->lan_veb = v;
10235 break;
10236 }
10237 }
10238 if (pf->lan_veb == I40E_NO_VEB) {
10239 v = i40e_veb_mem_alloc(pf);
10240 if (v < 0)
10241 break;
10242 pf->lan_veb = v;
10243 }
10244 }
10245
10246 pf->veb[pf->lan_veb]->seid = seid;
10247 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10248 pf->veb[pf->lan_veb]->pf = pf;
10249 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10250 break;
10251 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10252 if (num_reported != 1)
10253 break;
10254 /* This is immediately after a reset so we can assume this is
10255 * the PF's VSI
10256 */
10257 pf->mac_seid = uplink_seid;
10258 pf->pf_seid = downlink_seid;
10259 pf->main_vsi_seid = seid;
10260 if (printconfig)
10261 dev_info(&pf->pdev->dev,
10262 "pf_seid=%d main_vsi_seid=%d\n",
10263 pf->pf_seid, pf->main_vsi_seid);
10264 break;
10265 case I40E_SWITCH_ELEMENT_TYPE_PF:
10266 case I40E_SWITCH_ELEMENT_TYPE_VF:
10267 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10268 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10269 case I40E_SWITCH_ELEMENT_TYPE_PE:
10270 case I40E_SWITCH_ELEMENT_TYPE_PA:
10271 /* ignore these for now */
10272 break;
10273 default:
10274 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10275 element_type, seid);
10276 break;
10277 }
10278}
10279
10280/**
10281 * i40e_fetch_switch_configuration - Get switch config from firmware
10282 * @pf: board private structure
10283 * @printconfig: should we print the contents
10284 *
10285 * Get the current switch configuration from the device and
10286 * extract a few useful SEID values.
10287 **/
10288int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10289{
10290 struct i40e_aqc_get_switch_config_resp *sw_config;
10291 u16 next_seid = 0;
10292 int ret = 0;
10293 u8 *aq_buf;
10294 int i;
10295
10296 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10297 if (!aq_buf)
10298 return -ENOMEM;
10299
10300 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10301 do {
10302 u16 num_reported, num_total;
10303
10304 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10305 I40E_AQ_LARGE_BUF,
10306 &next_seid, NULL);
10307 if (ret) {
10308 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10309 "get switch config failed err %s aq_err %s\n",
10310 i40e_stat_str(&pf->hw, ret),
10311 i40e_aq_str(&pf->hw,
10312 pf->hw.aq.asq_last_status));
41c445ff
JB		 10313 kfree(aq_buf);
10314 return -ENOENT;
10315 }
10316
10317 num_reported = le16_to_cpu(sw_config->header.num_reported);
10318 num_total = le16_to_cpu(sw_config->header.num_total);
10319
10320 if (printconfig)
10321 dev_info(&pf->pdev->dev,
10322 "header: %d reported %d total\n",
10323 num_reported, num_total);
10324
41c445ff
JB		 10325 for (i = 0; i < num_reported; i++) {
10326 struct i40e_aqc_switch_config_element_resp *ele =
10327 &sw_config->element[i];
10328
10329 i40e_setup_pf_switch_element(pf, ele, num_reported,
10330 printconfig);
10331 }
10332 } while (next_seid != 0);
10333
10334 kfree(aq_buf);
10335 return ret;
10336}
10337
10338/**
10339 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10340 * @pf: board private structure
bc7d338f 10341 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10342 *
10343 * Returns 0 on success, negative value on failure
10344 **/
bc7d338f 10345static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10346{
10347 int ret;
10348
10349 /* find out what's out there already */
10350 ret = i40e_fetch_switch_configuration(pf, false);
10351 if (ret) {
10352 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10353 "couldn't fetch switch config, err %s aq_err %s\n",
10354 i40e_stat_str(&pf->hw, ret),
10355 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10356 return ret;
10357 }
10358 i40e_pf_reset_stats(pf);
10359
41c445ff 10360 /* first time setup */
bc7d338f 10361 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10362 struct i40e_vsi *vsi = NULL;
10363 u16 uplink_seid;
10364
10365 /* Set up the PF VSI associated with the PF's main VSI
10366 * that is already in the HW switch
10367 */
10368 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10369 uplink_seid = pf->veb[pf->lan_veb]->seid;
10370 else
10371 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10372 if (pf->lan_vsi == I40E_NO_VSI)
10373 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10374 else if (reinit)
10375 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10376 if (!vsi) {
10377 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10378 i40e_fdir_teardown(pf);
10379 return -EAGAIN;
10380 }
41c445ff
JB		 10381 } else {
10382 /* force a reset of TC and queue layout configurations */
10383 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10384
41c445ff
JB		 10385 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10386 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10387 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10388 }
10389 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10390
cbf61325
ASJ		 10391 i40e_fdir_sb_setup(pf);
10392
41c445ff
JB		 10393 /* Setup static PF queue filter control settings */
10394 ret = i40e_setup_pf_filter_control(pf);
10395 if (ret) {
10396 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10397 ret);
10398 /* Failure here should not stop continuing other steps */
10399 }
10400
10401 /* enable RSS in the HW, even for only one queue, as the stack can use
10402 * the hash
10403 */
10404 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10405 i40e_pf_config_rss(pf);
41c445ff
JB		 10406
10407 /* fill in link information and enable LSE reporting */
0a862b43 10408 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10409 i40e_link_event(pf);
10410
d52c20b7 10411 /* Initialize user-specific link properties */
41c445ff
JB		 10412 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10413 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10414
beb0dff1
JK		 10415 i40e_ptp_init(pf);
10416
41c445ff
JB		 10417 return ret;
10418}
10419
41c445ff
JB		 10420/**
10421 * i40e_determine_queue_usage - Work out queue distribution
10422 * @pf: board private structure
10423 **/
10424static void i40e_determine_queue_usage(struct i40e_pf *pf)
10425{
41c445ff
JB		 10426 int queues_left;
10427
10428 pf->num_lan_qps = 0;
38e00438
VD		 10429#ifdef I40E_FCOE
10430 pf->num_fcoe_qps = 0;
10431#endif
41c445ff
JB		 10432
10433 /* Find the max queues to be put into basic use. We'll always be
10434 * using TC0, whether or not DCB is running, and TC0 will get the
10435 * big RSS set.
10436 */
10437 queues_left = pf->hw.func_caps.num_tx_qp;
10438
cbf61325 10439 if ((queues_left == 1) ||
9aa7e935 10440 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10441 /* one qp for PF, no queues for anything else */
10442 queues_left = 0;
acd65448 10443 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10444
10445 /* make sure all the fancies are disabled */
60ea5f83 10446 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10447#ifdef I40E_FCOE
10448 I40E_FLAG_FCOE_ENABLED |
10449#endif
60ea5f83
JB		 10450 I40E_FLAG_FD_SB_ENABLED |
10451 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10452 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10453 I40E_FLAG_SRIOV_ENABLED |
10454 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10455 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10456 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10457 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10458 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10459 /* one qp for PF */
acd65448 10460 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10461 queues_left -= pf->num_lan_qps;
10462
10463 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10464#ifdef I40E_FCOE
10465 I40E_FLAG_FCOE_ENABLED |
10466#endif
9aa7e935
FZ		 10467 I40E_FLAG_FD_SB_ENABLED |
10468 I40E_FLAG_FD_ATR_ENABLED |
10469 I40E_FLAG_DCB_ENABLED |
10470 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10471 } else {
cbf61325 10472 /* Not enough queues for all TCs */
4d9b6043 10473 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10474 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10475 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10476 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10477 }
9a3bd2f1
ASJ		 10478 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10479 num_online_cpus());
10480 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10481 pf->hw.func_caps.num_tx_qp);
10482
cbf61325
ASJ		 10483 queues_left -= pf->num_lan_qps;
10484 }
10485
38e00438
VD		 10486#ifdef I40E_FCOE
10487 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10488 if (I40E_DEFAULT_FCOE <= queues_left) {
10489 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10490 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10491 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10492 } else {
10493 pf->num_fcoe_qps = 0;
10494 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10495 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10496 }
10497
10498 queues_left -= pf->num_fcoe_qps;
10499 }
10500
10501#endif
cbf61325
ASJ		 10502 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10503 if (queues_left > 1) {
10504 queues_left -= 1; /* save 1 queue for FD */
10505 } else {
10506 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10507 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10508 }
41c445ff
JB		 10509 }
10510
10511 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10512 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10513 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10514 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10515 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10516 }
10517
10518 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10519 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10520 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10521 (queues_left / pf->num_vmdq_qps));
10522 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10523 }
10524
f8ff1464 10525 pf->queues_left = queues_left;
8279e495
NP		 10526 dev_dbg(&pf->pdev->dev,
10527 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10528 pf->hw.func_caps.num_tx_qp,
10529 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10530 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10531 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10532 queues_left);
38e00438 10533#ifdef I40E_FCOE
8279e495 10534 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10535#endif
41c445ff
JB		 10536}
10537
10538/**
10539 * i40e_setup_pf_filter_control - Setup PF static filter control
10540 * @pf: PF to be setup
10541 *
b40c82e6 10542 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10543 * settings. If PE/FCoE are enabled then it will also set the per PF
10544 * based filter sizes required for them. It also enables Flow director,
10545 * ethertype and macvlan type filter settings for the pf.
10546 *
10547 * Returns 0 on success, negative on failure
10548 **/
10549static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10550{
10551 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10552
10553 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10554
10555 /* Flow Director is enabled */
60ea5f83 10556 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10557 settings->enable_fdir = true;
10558
10559 /* Ethtype and MACVLAN filters enabled for PF */
10560 settings->enable_ethtype = true;
10561 settings->enable_macvlan = true;
10562
10563 if (i40e_set_filter_control(&pf->hw, settings))
10564 return -ENOENT;
10565
10566 return 0;
10567}
10568
0c22b3dd 10569#define INFO_STRING_LEN 255
7fd89545 10570#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10571static void i40e_print_features(struct i40e_pf *pf)
10572{
10573 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10574 char *buf;
10575 int i;
0c22b3dd 10576
3b195843
JP		 10577 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10578 if (!buf)
0c22b3dd 10579 return;
0c22b3dd 10580
3b195843 10581 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10582#ifdef CONFIG_PCI_IOV
3b195843 10583 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10584#endif
3b195843 10585 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10586 pf->hw.func_caps.num_vsis,
10587 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10588 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10589
10590 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10591 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10592 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10593 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10594 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10595 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10596 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10597 }
4d9b6043 10598 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10599 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10600#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10601 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024
SA		 10602#endif
10603#if IS_ENABLED(CONFIG_GENEVE)
10604 i += snprintf(&buf[i], REMAIN(i), " Geneve");
ce6fcb3f 10605#endif
0c22b3dd 10606 if (pf->flags & I40E_FLAG_PTP)
3b195843 10607 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10608#ifdef I40E_FCOE
10609 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10610 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10611#endif
6dec1017 10612 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10613 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10614 else
3b195843 10615 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10616
3b195843
JP		 10617 dev_info(&pf->pdev->dev, "%s\n", buf);
10618 kfree(buf);
7fd89545 10619 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10620}
10621
b499ffb0
SV		 10622/**
10623 * i40e_get_platform_mac_addr - get platform-specific MAC address
10624 *
10625 * @pdev: PCI device information struct
10626 * @pf: board private structure
10627 *
10628 * Look up the MAC address in Open Firmware on systems that support it,
10629 * and use IDPROM on SPARC if no OF address is found. On return, the
10630 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10631 * has been selected.
10632 **/
10633static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10634{
b499ffb0 10635 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10636 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10637 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10638}
10639
41c445ff
JB		 10640/**
10641 * i40e_probe - Device initialization routine
10642 * @pdev: PCI device information struct
10643 * @ent: entry in i40e_pci_tbl
10644 *
b40c82e6
JK		 10645 * i40e_probe initializes a PF identified by a pci_dev structure.
10646 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10647 * and a hardware reset occur.
10648 *
10649 * Returns 0 on success, negative on failure
10650 **/
10651static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10652{
e827845c 10653 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10654 struct i40e_pf *pf;
10655 struct i40e_hw *hw;
93cd765b 10656 static u16 pfs_found;
1d5109d1 10657 u16 wol_nvm_bits;
d4dfb81a 10658 u16 link_status;
6f66a484 10659 int err;
4f2f017c 10660 u32 val;
8a9eb7d3 10661 u32 i;
58fc3267 10662 u8 set_fc_aq_fail;
41c445ff
JB		 10663
10664 err = pci_enable_device_mem(pdev);
10665 if (err)
10666 return err;
10667
10668 /* set up for high or low dma */
6494294f 10669 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10670 if (err) {
e3e3bfdd
JS		 10671 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10672 if (err) {
10673 dev_err(&pdev->dev,
10674 "DMA configuration failed: 0x%x\n", err);
10675 goto err_dma;
10676 }
41c445ff
JB		 10677 }
10678
10679 /* set up pci connections */
10680 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10681 IORESOURCE_MEM), i40e_driver_name);
10682 if (err) {
10683 dev_info(&pdev->dev,
10684 "pci_request_selected_regions failed %d\n", err);
10685 goto err_pci_reg;
10686 }
10687
10688 pci_enable_pcie_error_reporting(pdev);
10689 pci_set_master(pdev);
10690
10691 /* Now that we have a PCI connection, we need to do the
10692 * low level device setup. This is primarily setting up
10693 * the Admin Queue structures and then querying for the
10694 * device's current profile information.
10695 */
10696 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10697 if (!pf) {
10698 err = -ENOMEM;
10699 goto err_pf_alloc;
10700 }
10701 pf->next_vsi = 0;
10702 pf->pdev = pdev;
10703 set_bit(__I40E_DOWN, &pf->state);
10704
10705 hw = &pf->hw;
10706 hw->back = pf;
232f4706 10707
2ac8b675
SN		 10708 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10709 I40E_MAX_CSR_SPACE);
232f4706 10710
2ac8b675 10711 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10712 if (!hw->hw_addr) {
10713 err = -EIO;
10714 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10715 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10716 pf->ioremap_len, err);
41c445ff
JB		 10717 goto err_ioremap;
10718 }
10719 hw->vendor_id = pdev->vendor;
10720 hw->device_id = pdev->device;
10721 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10722 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10723 hw->subsystem_device_id = pdev->subsystem_device;
10724 hw->bus.device = PCI_SLOT(pdev->devfn);
10725 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10726 pf->instance = pfs_found;
41c445ff 10727
5b5faa43
SN		 10728 if (debug != -1) {
10729 pf->msg_enable = pf->hw.debug_mask;
10730 pf->msg_enable = debug;
10731 }
10732
7134f9ce
JB		 10733 /* do a special CORER for clearing PXE mode once at init */
10734 if (hw->revision_id == 0 &&
10735 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10736 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10737 i40e_flush(hw);
10738 msleep(200);
10739 pf->corer_count++;
10740
10741 i40e_clear_pxe_mode(hw);
10742 }
10743
41c445ff 10744 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10745 i40e_clear_hw(hw);
41c445ff
JB		 10746 err = i40e_pf_reset(hw);
10747 if (err) {
10748 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10749 goto err_pf_reset;
10750 }
10751 pf->pfr_count++;
10752
10753 hw->aq.num_arq_entries = I40E_AQ_LEN;
10754 hw->aq.num_asq_entries = I40E_AQ_LEN;
10755 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10756 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10757 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10758
b294ac70 10759 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10760 "%s-%s:misc",
10761 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10762
10763 err = i40e_init_shared_code(hw);
10764 if (err) {
b2a75c58
ASJ		 10765 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10766 err);
41c445ff
JB		 10767 goto err_pf_reset;
10768 }
10769
d52c20b7
JB		 10770 /* set up a default setting for link flow control */
10771 pf->hw.fc.requested_mode = I40E_FC_NONE;
10772
8ddb3326
JB		 10773 /* set up the locks for the AQ, do this only once in probe
10774 * and destroy them only once in remove
10775 */
10776 mutex_init(&hw->aq.asq_mutex);
10777 mutex_init(&hw->aq.arq_mutex);
10778
41c445ff 10779 err = i40e_init_adminq(hw);
2b2426a7
CW		 10780 if (err) {
10781 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10782 dev_info(&pdev->dev,
10783 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10784 else
10785 dev_info(&pdev->dev,
10786 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10787
10788 goto err_pf_reset;
10789 }
f0b44440 10790
6dec1017
SN		 10791 /* provide nvm, fw, api versions */
10792 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10793 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10794 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10795 i40e_nvm_version_str(hw));
f0b44440 10796
7aa67613
CS		 10797 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10798 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10799 dev_info(&pdev->dev,
7aa67613
CS		 10800 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10801 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10802 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10803 dev_info(&pdev->dev,
7aa67613 10804 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10805
4eb3f768
SN		 10806 i40e_verify_eeprom(pf);
10807
2c5fe33b
JB		 10808 /* Rev 0 hardware was never productized */
10809 if (hw->revision_id < 1)
10810 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10811
6ff4ef86 10812 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10813 err = i40e_get_capabilities(pf);
10814 if (err)
10815 goto err_adminq_setup;
10816
10817 err = i40e_sw_init(pf);
10818 if (err) {
10819 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10820 goto err_sw_init;
10821 }
10822
10823 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10824 hw->func_caps.num_rx_qp,
10825 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10826 if (err) {
10827 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10828 goto err_init_lan_hmc;
10829 }
10830
10831 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10832 if (err) {
10833 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10834 err = -ENOENT;
10835 goto err_configure_lan_hmc;
10836 }
10837
b686ece5
NP		 10838 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10839 * Ignore error return codes because if it was already disabled via
10840 * hardware settings this will fail
10841 */
f1bbad33 10842 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10843 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10844 i40e_aq_stop_lldp(hw, true, NULL);
10845 }
10846
41c445ff 10847 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10848 /* allow a platform config to override the HW addr */
10849 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10850 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10851 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10852 err = -EIO;
10853 goto err_mac_addr;
10854 }
10855 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10856 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10857 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10858 if (is_valid_ether_addr(hw->mac.port_addr))
10859 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10860#ifdef I40E_FCOE
10861 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10862 if (err)
10863 dev_info(&pdev->dev,
10864 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10865 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10866 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10867 hw->mac.san_addr);
10868 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10869 }
10870 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10871#endif /* I40E_FCOE */
41c445ff
JB		 10872
10873 pci_set_drvdata(pdev, pf);
10874 pci_save_state(pdev);
4e3b35b0
NP		 10875#ifdef CONFIG_I40E_DCB
10876 err = i40e_init_pf_dcb(pf);
10877 if (err) {
aebfc816 10878 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10879 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10880 /* Continue without DCB enabled */
4e3b35b0
NP		 10881 }
10882#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10883
10884 /* set up periodic task facility */
10885 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10886 pf->service_timer_period = HZ;
10887
10888 INIT_WORK(&pf->service_task, i40e_service_task);
10889 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10890 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10891
1d5109d1
SN		 10892 /* NVM bit on means WoL disabled for the port */
10893 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10894 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10895 pf->wol_en = false;
10896 else
10897 pf->wol_en = true;
8e2773ae
SN		 10898 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10899
41c445ff
JB		 10900 /* set up the main switch operations */
10901 i40e_determine_queue_usage(pf);
c1147280
JB		 10902 err = i40e_init_interrupt_scheme(pf);
10903 if (err)
10904 goto err_switch_setup;
41c445ff 10905
505682cd
MW		 10906 /* The number of VSIs reported by the FW is the minimum guaranteed
10907 * to us; HW supports far more and we share the remaining pool with
10908 * the other PFs. We allocate space for more than the guarantee with
10909 * the understanding that we might not get them all later.
41c445ff 10910 */
505682cd
MW		 10911 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10912 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10913 else
10914 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10915
10916 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10917 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10918 GFP_KERNEL);
ed87ac09
WY		 10919 if (!pf->vsi) {
10920 err = -ENOMEM;
41c445ff 10921 goto err_switch_setup;
ed87ac09 10922 }
41c445ff 10923
fa11cb3d
ASJ		 10924#ifdef CONFIG_PCI_IOV
10925 /* prep for VF support */
10926 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10927 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10928 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10929 if (pci_num_vf(pdev))
10930 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10931 }
10932#endif
bc7d338f 10933 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10934 if (err) {
10935 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10936 goto err_vsis;
10937 }
58fc3267
HZ		 10938
10939 /* Make sure flow control is set according to current settings */
10940 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10941 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10942 dev_dbg(&pf->pdev->dev,
10943 "Set fc with err %s aq_err %s on get_phy_cap\n",
10944 i40e_stat_str(hw, err),
10945 i40e_aq_str(hw, hw->aq.asq_last_status));
10946 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10947 dev_dbg(&pf->pdev->dev,
10948 "Set fc with err %s aq_err %s on set_phy_config\n",
10949 i40e_stat_str(hw, err),
10950 i40e_aq_str(hw, hw->aq.asq_last_status));
10951 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10952 dev_dbg(&pf->pdev->dev,
10953 "Set fc with err %s aq_err %s on get_link_info\n",
10954 i40e_stat_str(hw, err),
10955 i40e_aq_str(hw, hw->aq.asq_last_status));
10956
8a9eb7d3 10957 /* if FDIR VSI was set up, start it now */
505682cd 10958 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10959 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10960 i40e_vsi_open(pf->vsi[i]);
10961 break;
10962 }
10963 }
41c445ff 10964
2f0aff41
SN		 10965 /* The driver only wants link up/down and module qualification
10966 * reports from firmware. Note the negative logic.
7e2453fe
JB		 10967 */
10968 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41
SN		 10969 ~(I40E_AQ_EVENT_LINK_UPDOWN |
10970 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 10971 if (err)
f1c7e72e
SN		 10972 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10973 i40e_stat_str(&pf->hw, err),
10974 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10975
4f2f017c
ASJ		 10976 /* Reconfigure hardware for allowing smaller MSS in the case
10977 * of TSO, so that we avoid the MDD being fired and causing
10978 * a reset in the case of small MSS+TSO.
10979 */
10980 val = rd32(hw, I40E_REG_MSS);
10981 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10982 val &= ~I40E_REG_MSS_MIN_MASK;
10983 val |= I40E_64BYTE_MSS;
10984 wr32(hw, I40E_REG_MSS, val);
10985 }
10986
8eed76fa 10987 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 10988 msleep(75);
10989 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10990 if (err)
f1c7e72e
SN		 10991 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10992 i40e_stat_str(&pf->hw, err),
10993 i40e_aq_str(&pf->hw,
10994 pf->hw.aq.asq_last_status));
cafa2ee6 10995 }
41c445ff
JB		 10996 /* The main driver is (mostly) up and happy. We need to set this state
10997 * before setting up the misc vector or we get a race and the vector
10998 * ends up disabled forever.
10999 */
11000 clear_bit(__I40E_DOWN, &pf->state);
11001
11002 /* In case of MSIX we are going to setup the misc vector right here
11003 * to handle admin queue events etc. In case of legacy and MSI
11004 * the misc functionality and queue processing is combined in
11005 * the same vector and that gets setup at open.
11006 */
11007 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11008 err = i40e_setup_misc_vector(pf);
11009 if (err) {
11010 dev_info(&pdev->dev,
11011 "setup of misc vector failed: %d\n", err);
11012 goto err_vsis;
11013 }
11014 }
11015
df805f62 11016#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11017 /* prep for VF support */
11018 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11019 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11020 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11021 /* disable link interrupts for VFs */
11022 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11023 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11024 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11025 i40e_flush(hw);
4aeec010
MW		 11026
11027 if (pci_num_vf(pdev)) {
11028 dev_info(&pdev->dev,
11029 "Active VFs found, allocating resources.\n");
11030 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11031 if (err)
11032 dev_info(&pdev->dev,
11033 "Error %d allocating resources for existing VFs\n",
11034 err);
11035 }
41c445ff 11036 }
df805f62 11037#endif /* CONFIG_PCI_IOV */
41c445ff 11038
93cd765b
ASJ		 11039 pfs_found++;
11040
41c445ff
JB		 11041 i40e_dbg_pf_init(pf);
11042
11043 /* tell the firmware that we're starting */
44033fac 11044 i40e_send_version(pf);
41c445ff
JB		 11045
11046 /* since everything's happy, start the service_task timer */
11047 mod_timer(&pf->service_timer,
11048 round_jiffies(jiffies + pf->service_timer_period));
11049
38e00438
VD		 11050#ifdef I40E_FCOE
11051 /* create FCoE interface */
11052 i40e_fcoe_vsi_setup(pf);
11053
11054#endif
3fced535
ASJ		 11055#define PCI_SPEED_SIZE 8
11056#define PCI_WIDTH_SIZE 8
11057 /* Devices on the IOSF bus do not have this information
11058 * and will report PCI Gen 1 x 1 by default so don't bother
11059 * checking them.
11060 */
11061 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11062 char speed[PCI_SPEED_SIZE] = "Unknown";
11063 char width[PCI_WIDTH_SIZE] = "Unknown";
11064
11065 /* Get the negotiated link width and speed from PCI config
11066 * space
11067 */
11068 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11069 &link_status);
11070
11071 i40e_set_pci_config_data(hw, link_status);
11072
11073 switch (hw->bus.speed) {
11074 case i40e_bus_speed_8000:
11075 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11076 case i40e_bus_speed_5000:
11077 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11078 case i40e_bus_speed_2500:
11079 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11080 default:
11081 break;
11082 }
11083 switch (hw->bus.width) {
11084 case i40e_bus_width_pcie_x8:
11085 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11086 case i40e_bus_width_pcie_x4:
11087 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11088 case i40e_bus_width_pcie_x2:
11089 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11090 case i40e_bus_width_pcie_x1:
11091 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11092 default:
11093 break;
11094 }
11095
11096 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11097 speed, width);
11098
11099 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11100 hw->bus.speed < i40e_bus_speed_8000) {
11101 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11102 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11103 }
d4dfb81a
CS		 11104 }
11105
e827845c
CS		 11106 /* get the requested speeds from the fw */
11107 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11108 if (err)
8279e495
NP		 11109 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11110 i40e_stat_str(&pf->hw, err),
11111 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11112 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11113
fc72dbce
CS		 11114 /* get the supported phy types from the fw */
11115 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11116 if (err)
11117 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11118 i40e_stat_str(&pf->hw, err),
11119 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11120 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11121
e7358f54
ASJ		 11122 /* Add a filter to drop all Flow control frames from any VSI from being
11123 * transmitted. By doing so we stop a malicious VF from sending out
11124 * PAUSE or PFC frames and potentially controlling traffic for other
11125 * PF/VF VSIs.
11126 * The FW can still send Flow control frames if enabled.
11127 */
11128 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11129 pf->main_vsi_seid);
11130
0c22b3dd
JB		 11131 /* print a string summarizing features */
11132 i40e_print_features(pf);
11133
41c445ff
JB		 11134 return 0;
11135
11136 /* Unwind what we've done if something failed in the setup */
11137err_vsis:
11138 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11139 i40e_clear_interrupt_scheme(pf);
11140 kfree(pf->vsi);
04b03013
SN		 11141err_switch_setup:
11142 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11143 del_timer_sync(&pf->service_timer);
11144err_mac_addr:
11145err_configure_lan_hmc:
11146 (void)i40e_shutdown_lan_hmc(hw);
11147err_init_lan_hmc:
11148 kfree(pf->qp_pile);
41c445ff
JB		 11149err_sw_init:
11150err_adminq_setup:
11151 (void)i40e_shutdown_adminq(hw);
11152err_pf_reset:
11153 iounmap(hw->hw_addr);
11154err_ioremap:
11155 kfree(pf);
11156err_pf_alloc:
11157 pci_disable_pcie_error_reporting(pdev);
11158 pci_release_selected_regions(pdev,
11159 pci_select_bars(pdev, IORESOURCE_MEM));
11160err_pci_reg:
11161err_dma:
11162 pci_disable_device(pdev);
11163 return err;
11164}
11165
11166/**
11167 * i40e_remove - Device removal routine
11168 * @pdev: PCI device information struct
11169 *
11170 * i40e_remove is called by the PCI subsystem to alert the driver
11171 * that is should release a PCI device. This could be caused by a
11172 * Hot-Plug event, or because the driver is going to be removed from
11173 * memory.
11174 **/
11175static void i40e_remove(struct pci_dev *pdev)
11176{
11177 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11178 struct i40e_hw *hw = &pf->hw;
41c445ff 11179 i40e_status ret_code;
41c445ff
JB		 11180 int i;
11181
11182 i40e_dbg_pf_exit(pf);
11183
beb0dff1
JK		 11184 i40e_ptp_stop(pf);
11185
bcab2db9
CW		 11186 /* Disable RSS in hw */
11187 wr32(hw, I40E_PFQF_HENA(0), 0);
11188 wr32(hw, I40E_PFQF_HENA(1), 0);
11189
41c445ff
JB		 11190 /* no more scheduling of any task */
11191 set_bit(__I40E_DOWN, &pf->state);
11192 del_timer_sync(&pf->service_timer);
11193 cancel_work_sync(&pf->service_task);
11194
eb2d80bc
MW		 11195 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11196 i40e_free_vfs(pf);
11197 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11198 }
11199
41c445ff
JB		 11200 i40e_fdir_teardown(pf);
11201
11202 /* If there is a switch structure or any orphans, remove them.
11203 * This will leave only the PF's VSI remaining.
11204 */
11205 for (i = 0; i < I40E_MAX_VEB; i++) {
11206 if (!pf->veb[i])
11207 continue;
11208
11209 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11210 pf->veb[i]->uplink_seid == 0)
11211 i40e_switch_branch_release(pf->veb[i]);
11212 }
11213
11214 /* Now we can shutdown the PF's VSI, just before we kill
11215 * adminq and hmc.
11216 */
11217 if (pf->vsi[pf->lan_vsi])
11218 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11219
41c445ff 11220 /* shutdown and destroy the HMC */
60442dea
SN		 11221 if (pf->hw.hmc.hmc_obj) {
11222 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
11223 if (ret_code)
11224 dev_warn(&pdev->dev,
11225 "Failed to destroy the HMC resources: %d\n",
11226 ret_code);
11227 }
41c445ff
JB		 11228
11229 /* shutdown the adminq */
41c445ff
JB		 11230 ret_code = i40e_shutdown_adminq(&pf->hw);
11231 if (ret_code)
11232 dev_warn(&pdev->dev,
11233 "Failed to destroy the Admin Queue resources: %d\n",
11234 ret_code);
11235
8ddb3326
JB		 11236 /* destroy the locks only once, here */
11237 mutex_destroy(&hw->aq.arq_mutex);
11238 mutex_destroy(&hw->aq.asq_mutex);
11239
41c445ff
JB		 11240 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11241 i40e_clear_interrupt_scheme(pf);
505682cd 11242 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11243 if (pf->vsi[i]) {
11244 i40e_vsi_clear_rings(pf->vsi[i]);
11245 i40e_vsi_clear(pf->vsi[i]);
11246 pf->vsi[i] = NULL;
11247 }
11248 }
11249
11250 for (i = 0; i < I40E_MAX_VEB; i++) {
11251 kfree(pf->veb[i]);
11252 pf->veb[i] = NULL;
11253 }
11254
11255 kfree(pf->qp_pile);
41c445ff
JB		 11256 kfree(pf->vsi);
11257
41c445ff
JB		 11258 iounmap(pf->hw.hw_addr);
11259 kfree(pf);
11260 pci_release_selected_regions(pdev,
11261 pci_select_bars(pdev, IORESOURCE_MEM));
11262
11263 pci_disable_pcie_error_reporting(pdev);
11264 pci_disable_device(pdev);
11265}
11266
11267/**
11268 * i40e_pci_error_detected - warning that something funky happened in PCI land
11269 * @pdev: PCI device information struct
11270 *
11271 * Called to warn that something happened and the error handling steps
11272 * are in progress. Allows the driver to quiesce things, be ready for
11273 * remediation.
11274 **/
11275static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11276 enum pci_channel_state error)
11277{
11278 struct i40e_pf *pf = pci_get_drvdata(pdev);
11279
11280 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11281
11282 /* shutdown all operations */
9007bccd
SN		 11283 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11284 rtnl_lock();
11285 i40e_prep_for_reset(pf);
11286 rtnl_unlock();
11287 }
41c445ff
JB		 11288
11289 /* Request a slot reset */
11290 return PCI_ERS_RESULT_NEED_RESET;
11291}
11292
11293/**
11294 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11295 * @pdev: PCI device information struct
11296 *
11297 * Called to find if the driver can work with the device now that
11298 * the pci slot has been reset. If a basic connection seems good
11299 * (registers are readable and have sane content) then return a
11300 * happy little PCI_ERS_RESULT_xxx.
11301 **/
11302static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11303{
11304 struct i40e_pf *pf = pci_get_drvdata(pdev);
11305 pci_ers_result_t result;
11306 int err;
11307 u32 reg;
11308
fb43201f 11309 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11310 if (pci_enable_device_mem(pdev)) {
11311 dev_info(&pdev->dev,
11312 "Cannot re-enable PCI device after reset.\n");
11313 result = PCI_ERS_RESULT_DISCONNECT;
11314 } else {
11315 pci_set_master(pdev);
11316 pci_restore_state(pdev);
11317 pci_save_state(pdev);
11318 pci_wake_from_d3(pdev, false);
11319
11320 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11321 if (reg == 0)
11322 result = PCI_ERS_RESULT_RECOVERED;
11323 else
11324 result = PCI_ERS_RESULT_DISCONNECT;
11325 }
11326
11327 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11328 if (err) {
11329 dev_info(&pdev->dev,
11330 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11331 err);
11332 /* non-fatal, continue */
11333 }
11334
11335 return result;
11336}
11337
11338/**
11339 * i40e_pci_error_resume - restart operations after PCI error recovery
11340 * @pdev: PCI device information struct
11341 *
11342 * Called to allow the driver to bring things back up after PCI error
11343 * and/or reset recovery has finished.
11344 **/
11345static void i40e_pci_error_resume(struct pci_dev *pdev)
11346{
11347 struct i40e_pf *pf = pci_get_drvdata(pdev);
11348
fb43201f 11349 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11350 if (test_bit(__I40E_SUSPENDED, &pf->state))
11351 return;
11352
11353 rtnl_lock();
41c445ff 11354 i40e_handle_reset_warning(pf);
4c4935a9 11355 rtnl_unlock();
9007bccd
SN		 11356}
11357
11358/**
11359 * i40e_shutdown - PCI callback for shutting down
11360 * @pdev: PCI device information struct
11361 **/
11362static void i40e_shutdown(struct pci_dev *pdev)
11363{
11364 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11365 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11366
11367 set_bit(__I40E_SUSPENDED, &pf->state);
11368 set_bit(__I40E_DOWN, &pf->state);
11369 rtnl_lock();
11370 i40e_prep_for_reset(pf);
11371 rtnl_unlock();
11372
8e2773ae
SN		 11373 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11374 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11375
02b42498
CS		 11376 del_timer_sync(&pf->service_timer);
11377 cancel_work_sync(&pf->service_task);
11378 i40e_fdir_teardown(pf);
11379
11380 rtnl_lock();
11381 i40e_prep_for_reset(pf);
11382 rtnl_unlock();
11383
11384 wr32(hw, I40E_PFPM_APM,
11385 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11386 wr32(hw, I40E_PFPM_WUFC,
11387 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11388
e147758d
SN		 11389 i40e_clear_interrupt_scheme(pf);
11390
9007bccd 11391 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11392 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11393 pci_set_power_state(pdev, PCI_D3hot);
11394 }
11395}
11396
11397#ifdef CONFIG_PM
11398/**
11399 * i40e_suspend - PCI callback for moving to D3
11400 * @pdev: PCI device information struct
11401 **/
11402static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11403{
11404 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11405 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11406
11407 set_bit(__I40E_SUSPENDED, &pf->state);
11408 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11409
9007bccd
SN		 11410 rtnl_lock();
11411 i40e_prep_for_reset(pf);
11412 rtnl_unlock();
11413
8e2773ae
SN		 11414 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11415 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11416
11417 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11418 pci_set_power_state(pdev, PCI_D3hot);
11419
11420 return 0;
41c445ff
JB		 11421}
11422
9007bccd
SN		 11423/**
11424 * i40e_resume - PCI callback for waking up from D3
11425 * @pdev: PCI device information struct
11426 **/
11427static int i40e_resume(struct pci_dev *pdev)
11428{
11429 struct i40e_pf *pf = pci_get_drvdata(pdev);
11430 u32 err;
11431
11432 pci_set_power_state(pdev, PCI_D0);
11433 pci_restore_state(pdev);
11434 /* pci_restore_state() clears dev->state_saves, so
11435 * call pci_save_state() again to restore it.
11436 */
11437 pci_save_state(pdev);
11438
11439 err = pci_enable_device_mem(pdev);
11440 if (err) {
fb43201f 11441 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11442 return err;
11443 }
11444 pci_set_master(pdev);
11445
11446 /* no wakeup events while running */
11447 pci_wake_from_d3(pdev, false);
11448
11449 /* handling the reset will rebuild the device state */
11450 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11451 clear_bit(__I40E_DOWN, &pf->state);
11452 rtnl_lock();
11453 i40e_reset_and_rebuild(pf, false);
11454 rtnl_unlock();
11455 }
11456
11457 return 0;
11458}
11459
11460#endif
41c445ff
JB		 11461static const struct pci_error_handlers i40e_err_handler = {
11462 .error_detected = i40e_pci_error_detected,
11463 .slot_reset = i40e_pci_error_slot_reset,
11464 .resume = i40e_pci_error_resume,
11465};
11466
11467static struct pci_driver i40e_driver = {
11468 .name = i40e_driver_name,
11469 .id_table = i40e_pci_tbl,
11470 .probe = i40e_probe,
11471 .remove = i40e_remove,
9007bccd
SN		 11472#ifdef CONFIG_PM
11473 .suspend = i40e_suspend,
11474 .resume = i40e_resume,
11475#endif
11476 .shutdown = i40e_shutdown,
41c445ff
JB		 11477 .err_handler = &i40e_err_handler,
11478 .sriov_configure = i40e_pci_sriov_configure,
11479};
11480
11481/**
11482 * i40e_init_module - Driver registration routine
11483 *
11484 * i40e_init_module is the first routine called when the driver is
11485 * loaded. All it does is register with the PCI subsystem.
11486 **/
11487static int __init i40e_init_module(void)
11488{
11489 pr_info("%s: %s - version %s\n", i40e_driver_name,
11490 i40e_driver_string, i40e_driver_version_str);
11491 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11492
2803b16c
JB		 11493 /* we will see if single thread per module is enough for now,
11494 * it can't be any worse than using the system workqueue which
11495 * was already single threaded
11496 */
11497 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11498 if (!i40e_wq) {
11499 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11500 return -ENOMEM;
11501 }
11502
41c445ff
JB		 11503 i40e_dbg_init();
11504 return pci_register_driver(&i40e_driver);
11505}
11506module_init(i40e_init_module);
11507
11508/**
11509 * i40e_exit_module - Driver exit cleanup routine
11510 *
11511 * i40e_exit_module is called just before the driver is removed
11512 * from memory.
11513 **/
11514static void __exit i40e_exit_module(void)
11515{
11516 pci_unregister_driver(&i40e_driver);
2803b16c 11517 destroy_workqueue(i40e_wq);
41c445ff
JB		 11518 i40e_dbg_exit();
11519}
11520module_exit(i40e_exit_module);
Linux kernel - Deliverables
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