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i40e: Add support for non-willing Apps
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
164f7393 42#define DRV_VERSION_BUILD 28
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 85 /* required last entry */
86 {0, }
87};
88MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
89
90#define I40E_MAX_VF_COUNT 128
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
96MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100/**
101 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
102 * @hw: pointer to the HW structure
103 * @mem: ptr to mem struct to fill out
104 * @size: size of memory requested
105 * @alignment: what to align the allocation to
106 **/
107int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
108 u64 size, u32 alignment)
109{
110 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
111
112 mem->size = ALIGN(size, alignment);
113 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
114 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 115 if (!mem->va)
116 return -ENOMEM;
41c445ff 117
93bc73b8 118 return 0;
41c445ff
JB		 119}
120
121/**
122 * i40e_free_dma_mem_d - OS specific memory free for shared code
123 * @hw: pointer to the HW structure
124 * @mem: ptr to mem struct to free
125 **/
126int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
127{
128 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
129
130 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
131 mem->va = NULL;
132 mem->pa = 0;
133 mem->size = 0;
134
135 return 0;
136}
137
138/**
139 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to fill out
142 * @size: size of memory requested
143 **/
144int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
145 u32 size)
146{
147 mem->size = size;
148 mem->va = kzalloc(size, GFP_KERNEL);
149
93bc73b8
JB		 150 if (!mem->va)
151 return -ENOMEM;
41c445ff 152
93bc73b8 153 return 0;
41c445ff
JB		 154}
155
156/**
157 * i40e_free_virt_mem_d - OS specific memory free for shared code
158 * @hw: pointer to the HW structure
159 * @mem: ptr to mem struct to free
160 **/
161int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
162{
163 /* it's ok to kfree a NULL pointer */
164 kfree(mem->va);
165 mem->va = NULL;
166 mem->size = 0;
167
168 return 0;
169}
170
171/**
172 * i40e_get_lump - find a lump of free generic resource
173 * @pf: board private structure
174 * @pile: the pile of resource to search
175 * @needed: the number of items needed
176 * @id: an owner id to stick on the items assigned
177 *
178 * Returns the base item index of the lump, or negative for error
179 *
180 * The search_hint trick and lack of advanced fit-finding only work
181 * because we're highly likely to have all the same size lump requests.
182 * Linear search time and any fragmentation should be minimal.
183 **/
184static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
185 u16 needed, u16 id)
186{
187 int ret = -ENOMEM;
ddf434ac 188 int i, j;
41c445ff
JB		 189
190 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
191 dev_info(&pf->pdev->dev,
192 "param err: pile=%p needed=%d id=0x%04x\n",
193 pile, needed, id);
194 return -EINVAL;
195 }
196
197 /* start the linear search with an imperfect hint */
198 i = pile->search_hint;
ddf434ac 199 while (i < pile->num_entries) {
41c445ff
JB		 200 /* skip already allocated entries */
201 if (pile->list[i] & I40E_PILE_VALID_BIT) {
202 i++;
203 continue;
204 }
205
206 /* do we have enough in this lump? */
207 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
208 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
209 break;
210 }
211
212 if (j == needed) {
213 /* there was enough, so assign it to the requestor */
214 for (j = 0; j < needed; j++)
215 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
216 ret = i;
217 pile->search_hint = i + j;
ddf434ac 218 break;
41c445ff 219 }
6995b36c
JB		 220
221 /* not enough, so skip over it and continue looking */
222 i += j;
41c445ff
JB		 223 }
224
225 return ret;
226}
227
228/**
229 * i40e_put_lump - return a lump of generic resource
230 * @pile: the pile of resource to search
231 * @index: the base item index
232 * @id: the owner id of the items assigned
233 *
234 * Returns the count of items in the lump
235 **/
236static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
237{
238 int valid_id = (id | I40E_PILE_VALID_BIT);
239 int count = 0;
240 int i;
241
242 if (!pile || index >= pile->num_entries)
243 return -EINVAL;
244
245 for (i = index;
246 i < pile->num_entries && pile->list[i] == valid_id;
247 i++) {
248 pile->list[i] = 0;
249 count++;
250 }
251
252 if (count && index < pile->search_hint)
253 pile->search_hint = index;
254
255 return count;
256}
257
fdf0e0bf
ASJ		 258/**
259 * i40e_find_vsi_from_id - searches for the vsi with the given id
260 * @pf - the pf structure to search for the vsi
261 * @id - id of the vsi it is searching for
262 **/
263struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
264{
265 int i;
266
267 for (i = 0; i < pf->num_alloc_vsi; i++)
268 if (pf->vsi[i] && (pf->vsi[i]->id == id))
269 return pf->vsi[i];
270
271 return NULL;
272}
273
41c445ff
JB		 274/**
275 * i40e_service_event_schedule - Schedule the service task to wake up
276 * @pf: board private structure
277 *
278 * If not already scheduled, this puts the task into the work queue
279 **/
280static void i40e_service_event_schedule(struct i40e_pf *pf)
281{
282 if (!test_bit(__I40E_DOWN, &pf->state) &&
283 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
284 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
285 schedule_work(&pf->service_task);
286}
287
288/**
289 * i40e_tx_timeout - Respond to a Tx Hang
290 * @netdev: network interface device structure
291 *
292 * If any port has noticed a Tx timeout, it is likely that the whole
293 * device is munged, not just the one netdev port, so go for the full
294 * reset.
295 **/
38e00438
VD		 296#ifdef I40E_FCOE
297void i40e_tx_timeout(struct net_device *netdev)
298#else
41c445ff 299static void i40e_tx_timeout(struct net_device *netdev)
38e00438 300#endif
41c445ff
JB		 301{
302 struct i40e_netdev_priv *np = netdev_priv(netdev);
303 struct i40e_vsi *vsi = np->vsi;
304 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 305 struct i40e_ring *tx_ring = NULL;
306 unsigned int i, hung_queue = 0;
307 u32 head, val;
41c445ff
JB		 308
309 pf->tx_timeout_count++;
310
b03a8c1f
KP		 311 /* find the stopped queue the same way the stack does */
312 for (i = 0; i < netdev->num_tx_queues; i++) {
313 struct netdev_queue *q;
314 unsigned long trans_start;
315
316 q = netdev_get_tx_queue(netdev, i);
317 trans_start = q->trans_start ? : netdev->trans_start;
318 if (netif_xmit_stopped(q) &&
319 time_after(jiffies,
320 (trans_start + netdev->watchdog_timeo))) {
321 hung_queue = i;
322 break;
323 }
324 }
325
326 if (i == netdev->num_tx_queues) {
327 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
328 } else {
329 /* now that we have an index, find the tx_ring struct */
330 for (i = 0; i < vsi->num_queue_pairs; i++) {
331 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
332 if (hung_queue ==
333 vsi->tx_rings[i]->queue_index) {
334 tx_ring = vsi->tx_rings[i];
335 break;
336 }
337 }
338 }
339 }
340
41c445ff 341 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 342 pf->tx_timeout_recovery_level = 1; /* reset after some time */
343 else if (time_before(jiffies,
344 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
345 return; /* don't do any new action before the next timeout */
346
347 if (tx_ring) {
348 head = i40e_get_head(tx_ring);
349 /* Read interrupt register */
350 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
351 val = rd32(&pf->hw,
352 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
353 tx_ring->vsi->base_vector - 1));
354 else
355 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
356
357 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
358 vsi->seid, hung_queue, tx_ring->next_to_clean,
359 head, tx_ring->next_to_use,
360 readl(tx_ring->tail), val);
361 }
362
41c445ff 363 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 364 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
365 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 366
367 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 368 case 1:
369 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
370 break;
371 case 2:
372 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
373 break;
374 case 3:
375 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
376 break;
377 default:
378 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 379 break;
380 }
b03a8c1f 381
41c445ff
JB		 382 i40e_service_event_schedule(pf);
383 pf->tx_timeout_recovery_level++;
384}
385
386/**
387 * i40e_release_rx_desc - Store the new tail and head values
388 * @rx_ring: ring to bump
389 * @val: new head index
390 **/
391static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
392{
393 rx_ring->next_to_use = val;
394
395 /* Force memory writes to complete before letting h/w
396 * know there are new descriptors to fetch. (Only
397 * applicable for weak-ordered memory model archs,
398 * such as IA-64).
399 */
400 wmb();
401 writel(val, rx_ring->tail);
402}
403
404/**
405 * i40e_get_vsi_stats_struct - Get System Network Statistics
406 * @vsi: the VSI we care about
407 *
408 * Returns the address of the device statistics structure.
409 * The statistics are actually updated from the service task.
410 **/
411struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
412{
413 return &vsi->net_stats;
414}
415
416/**
417 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
418 * @netdev: network interface device structure
419 *
420 * Returns the address of the device statistics structure.
421 * The statistics are actually updated from the service task.
422 **/
38e00438
VD		 423#ifdef I40E_FCOE
424struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
425 struct net_device *netdev,
426 struct rtnl_link_stats64 *stats)
427#else
41c445ff
JB		 428static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
429 struct net_device *netdev,
980e9b11 430 struct rtnl_link_stats64 *stats)
38e00438 431#endif
41c445ff
JB		 432{
433 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 434 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 435 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 436 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
437 int i;
438
bc7d338f
ASJ		 439 if (test_bit(__I40E_DOWN, &vsi->state))
440 return stats;
441
3c325ced
JB		 442 if (!vsi->tx_rings)
443 return stats;
444
980e9b11
AD		 445 rcu_read_lock();
446 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 447 u64 bytes, packets;
448 unsigned int start;
449
450 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
451 if (!tx_ring)
452 continue;
453
454 do {
57a7744e 455 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 456 packets = tx_ring->stats.packets;
457 bytes = tx_ring->stats.bytes;
57a7744e 458 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 459
460 stats->tx_packets += packets;
461 stats->tx_bytes += bytes;
462 rx_ring = &tx_ring[1];
463
464 do {
57a7744e 465 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 466 packets = rx_ring->stats.packets;
467 bytes = rx_ring->stats.bytes;
57a7744e 468 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 469
980e9b11
AD		 470 stats->rx_packets += packets;
471 stats->rx_bytes += bytes;
472 }
473 rcu_read_unlock();
474
a5282f44 475 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 476 stats->multicast = vsi_stats->multicast;
477 stats->tx_errors = vsi_stats->tx_errors;
478 stats->tx_dropped = vsi_stats->tx_dropped;
479 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 480 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 481 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
482 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 483
980e9b11 484 return stats;
41c445ff
JB		 485}
486
487/**
488 * i40e_vsi_reset_stats - Resets all stats of the given vsi
489 * @vsi: the VSI to have its stats reset
490 **/
491void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
492{
493 struct rtnl_link_stats64 *ns;
494 int i;
495
496 if (!vsi)
497 return;
498
499 ns = i40e_get_vsi_stats_struct(vsi);
500 memset(ns, 0, sizeof(*ns));
501 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
502 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
503 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 504 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 505 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 506 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 507 sizeof(vsi->rx_rings[i]->stats));
6995b36c 508 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 510 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 511 sizeof(vsi->tx_rings[i]->stats));
512 memset(&vsi->tx_rings[i]->tx_stats, 0,
513 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 514 }
8e9dca53 515 }
41c445ff
JB		 516 vsi->stat_offsets_loaded = false;
517}
518
519/**
b40c82e6 520 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 521 * @pf: the PF to be reset
522 **/
523void i40e_pf_reset_stats(struct i40e_pf *pf)
524{
e91fdf76
SN		 525 int i;
526
41c445ff
JB		 527 memset(&pf->stats, 0, sizeof(pf->stats));
528 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
529 pf->stat_offsets_loaded = false;
e91fdf76
SN		 530
531 for (i = 0; i < I40E_MAX_VEB; i++) {
532 if (pf->veb[i]) {
533 memset(&pf->veb[i]->stats, 0,
534 sizeof(pf->veb[i]->stats));
535 memset(&pf->veb[i]->stats_offsets, 0,
536 sizeof(pf->veb[i]->stats_offsets));
537 pf->veb[i]->stat_offsets_loaded = false;
538 }
539 }
41c445ff
JB		 540}
541
542/**
543 * i40e_stat_update48 - read and update a 48 bit stat from the chip
544 * @hw: ptr to the hardware info
545 * @hireg: the high 32 bit reg to read
546 * @loreg: the low 32 bit reg to read
547 * @offset_loaded: has the initial offset been loaded yet
548 * @offset: ptr to current offset value
549 * @stat: ptr to the stat
550 *
551 * Since the device stats are not reset at PFReset, they likely will not
552 * be zeroed when the driver starts. We'll save the first values read
553 * and use them as offsets to be subtracted from the raw values in order
554 * to report stats that count from zero. In the process, we also manage
555 * the potential roll-over.
556 **/
557static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
558 bool offset_loaded, u64 *offset, u64 *stat)
559{
560 u64 new_data;
561
ab60085e 562 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 563 new_data = rd32(hw, loreg);
564 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
565 } else {
566 new_data = rd64(hw, loreg);
567 }
568 if (!offset_loaded)
569 *offset = new_data;
570 if (likely(new_data >= *offset))
571 *stat = new_data - *offset;
572 else
41a1d04b 573 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 574 *stat &= 0xFFFFFFFFFFFFULL;
575}
576
577/**
578 * i40e_stat_update32 - read and update a 32 bit stat from the chip
579 * @hw: ptr to the hardware info
580 * @reg: the hw reg to read
581 * @offset_loaded: has the initial offset been loaded yet
582 * @offset: ptr to current offset value
583 * @stat: ptr to the stat
584 **/
585static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
586 bool offset_loaded, u64 *offset, u64 *stat)
587{
588 u32 new_data;
589
590 new_data = rd32(hw, reg);
591 if (!offset_loaded)
592 *offset = new_data;
593 if (likely(new_data >= *offset))
594 *stat = (u32)(new_data - *offset);
595 else
41a1d04b 596 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 597}
598
599/**
600 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
601 * @vsi: the VSI to be updated
602 **/
603void i40e_update_eth_stats(struct i40e_vsi *vsi)
604{
605 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
606 struct i40e_pf *pf = vsi->back;
607 struct i40e_hw *hw = &pf->hw;
608 struct i40e_eth_stats *oes;
609 struct i40e_eth_stats *es; /* device's eth stats */
610
611 es = &vsi->eth_stats;
612 oes = &vsi->eth_stats_offsets;
613
614 /* Gather up the stats that the hw collects */
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
618 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
619 vsi->stat_offsets_loaded,
620 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 621 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
622 vsi->stat_offsets_loaded,
623 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
624 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 627
628 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
629 I40E_GLV_GORCL(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->rx_bytes, &es->rx_bytes);
632 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
633 I40E_GLV_UPRCL(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_unicast, &es->rx_unicast);
636 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
637 I40E_GLV_MPRCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->rx_multicast, &es->rx_multicast);
640 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
641 I40E_GLV_BPRCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->rx_broadcast, &es->rx_broadcast);
644
645 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
646 I40E_GLV_GOTCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->tx_bytes, &es->tx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
650 I40E_GLV_UPTCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->tx_unicast, &es->tx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
654 I40E_GLV_MPTCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->tx_multicast, &es->tx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
658 I40E_GLV_BPTCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->tx_broadcast, &es->tx_broadcast);
661 vsi->stat_offsets_loaded = true;
662}
663
664/**
665 * i40e_update_veb_stats - Update Switch component statistics
666 * @veb: the VEB being updated
667 **/
668static void i40e_update_veb_stats(struct i40e_veb *veb)
669{
670 struct i40e_pf *pf = veb->pf;
671 struct i40e_hw *hw = &pf->hw;
672 struct i40e_eth_stats *oes;
673 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 674 struct i40e_veb_tc_stats *veb_oes;
675 struct i40e_veb_tc_stats *veb_es;
676 int i, idx = 0;
41c445ff
JB		 677
678 idx = veb->stats_idx;
679 es = &veb->stats;
680 oes = &veb->stats_offsets;
fe860afb
NP		 681 veb_es = &veb->tc_stats;
682 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 683
684 /* Gather up the stats that the hw collects */
685 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
686 veb->stat_offsets_loaded,
687 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 688 if (hw->revision_id > 0)
689 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_unknown_protocol,
692 &es->rx_unknown_protocol);
41c445ff
JB		 693 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_bytes, &es->rx_bytes);
696 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->rx_unicast, &es->rx_unicast);
699 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->rx_multicast, &es->rx_multicast);
702 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->rx_broadcast, &es->rx_broadcast);
705
706 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_bytes, &es->tx_bytes);
709 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->tx_unicast, &es->tx_unicast);
712 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->tx_multicast, &es->tx_multicast);
715 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
716 veb->stat_offsets_loaded,
717 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 718 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
719 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
720 I40E_GLVEBTC_RPCL(i, idx),
721 veb->stat_offsets_loaded,
722 &veb_oes->tc_rx_packets[i],
723 &veb_es->tc_rx_packets[i]);
724 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
725 I40E_GLVEBTC_RBCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_rx_bytes[i],
728 &veb_es->tc_rx_bytes[i]);
729 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
730 I40E_GLVEBTC_TPCL(i, idx),
731 veb->stat_offsets_loaded,
732 &veb_oes->tc_tx_packets[i],
733 &veb_es->tc_tx_packets[i]);
734 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
735 I40E_GLVEBTC_TBCL(i, idx),
736 veb->stat_offsets_loaded,
737 &veb_oes->tc_tx_bytes[i],
738 &veb_es->tc_tx_bytes[i]);
739 }
41c445ff
JB		 740 veb->stat_offsets_loaded = true;
741}
742
38e00438
VD		 743#ifdef I40E_FCOE
744/**
745 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
746 * @vsi: the VSI that is capable of doing FCoE
747 **/
748static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
749{
750 struct i40e_pf *pf = vsi->back;
751 struct i40e_hw *hw = &pf->hw;
752 struct i40e_fcoe_stats *ofs;
753 struct i40e_fcoe_stats *fs; /* device's eth stats */
754 int idx;
755
756 if (vsi->type != I40E_VSI_FCOE)
757 return;
758
759 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
760 fs = &vsi->fcoe_stats;
761 ofs = &vsi->fcoe_stats_offsets;
762
763 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
772 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
775 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
778 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
781 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->fcoe_last_error, &fs->fcoe_last_error);
784 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
785 vsi->fcoe_stat_offsets_loaded,
786 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
787
788 vsi->fcoe_stat_offsets_loaded = true;
789}
790
791#endif
41c445ff
JB		 792/**
793 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
794 * @pf: the corresponding PF
795 *
796 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
797 **/
798static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
799{
800 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
801 struct i40e_hw_port_stats *nsd = &pf->stats;
802 struct i40e_hw *hw = &pf->hw;
803 u64 xoff = 0;
41c445ff
JB		 804
805 if ((hw->fc.current_mode != I40E_FC_FULL) &&
806 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
807 return;
808
809 xoff = nsd->link_xoff_rx;
810 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
811 pf->stat_offsets_loaded,
812 &osd->link_xoff_rx, &nsd->link_xoff_rx);
813
814 /* No new LFC xoff rx */
815 if (!(nsd->link_xoff_rx - xoff))
816 return;
817
41c445ff
JB		 818}
819
820/**
821 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
822 * @pf: the corresponding PF
823 *
824 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
825 **/
826static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
827{
828 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
829 struct i40e_hw_port_stats *nsd = &pf->stats;
830 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
831 struct i40e_dcbx_config *dcb_cfg;
832 struct i40e_hw *hw = &pf->hw;
b03a8c1f 833 u16 i;
41c445ff
JB		 834 u8 tc;
835
836 dcb_cfg = &hw->local_dcbx_config;
837
e120814d
NP		 838 /* Collect Link XOFF stats when PFC is disabled */
839 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 840 i40e_update_link_xoff_rx(pf);
841 return;
842 }
843
844 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
845 u64 prio_xoff = nsd->priority_xoff_rx[i];
6995b36c 846
41c445ff
JB		 847 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
848 pf->stat_offsets_loaded,
849 &osd->priority_xoff_rx[i],
850 &nsd->priority_xoff_rx[i]);
851
852 /* No new PFC xoff rx */
853 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
854 continue;
855 /* Get the TC for given priority */
856 tc = dcb_cfg->etscfg.prioritytable[i];
857 xoff[tc] = true;
858 }
41c445ff
JB		 859}
860
861/**
7812fddc 862 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 863 * @vsi: the VSI to be updated
864 *
865 * There are a few instances where we store the same stat in a
866 * couple of different structs. This is partly because we have
867 * the netdev stats that need to be filled out, which is slightly
868 * different from the "eth_stats" defined by the chip and used in
7812fddc 869 * VF communications. We sort it out here.
41c445ff 870 **/
7812fddc 871static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 872{
873 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 874 struct rtnl_link_stats64 *ons;
875 struct rtnl_link_stats64 *ns; /* netdev stats */
876 struct i40e_eth_stats *oes;
877 struct i40e_eth_stats *es; /* device's eth stats */
878 u32 tx_restart, tx_busy;
bf00b376 879 struct i40e_ring *p;
41c445ff 880 u32 rx_page, rx_buf;
bf00b376
AA		 881 u64 bytes, packets;
882 unsigned int start;
2fc3d715 883 u64 tx_linearize;
41c445ff
JB		 884 u64 rx_p, rx_b;
885 u64 tx_p, tx_b;
41c445ff
JB		 886 u16 q;
887
888 if (test_bit(__I40E_DOWN, &vsi->state) ||
889 test_bit(__I40E_CONFIG_BUSY, &pf->state))
890 return;
891
892 ns = i40e_get_vsi_stats_struct(vsi);
893 ons = &vsi->net_stats_offsets;
894 es = &vsi->eth_stats;
895 oes = &vsi->eth_stats_offsets;
896
897 /* Gather up the netdev and vsi stats that the driver collects
898 * on the fly during packet processing
899 */
900 rx_b = rx_p = 0;
901 tx_b = tx_p = 0;
2fc3d715 902 tx_restart = tx_busy = tx_linearize = 0;
41c445ff
JB		 903 rx_page = 0;
904 rx_buf = 0;
980e9b11 905 rcu_read_lock();
41c445ff 906 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 907 /* locate Tx ring */
908 p = ACCESS_ONCE(vsi->tx_rings[q]);
909
910 do {
57a7744e 911 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 912 packets = p->stats.packets;
913 bytes = p->stats.bytes;
57a7744e 914 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 915 tx_b += bytes;
916 tx_p += packets;
917 tx_restart += p->tx_stats.restart_queue;
918 tx_busy += p->tx_stats.tx_busy;
2fc3d715 919 tx_linearize += p->tx_stats.tx_linearize;
41c445ff 920
980e9b11
AD		 921 /* Rx queue is part of the same block as Tx queue */
922 p = &p[1];
923 do {
57a7744e 924 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 925 packets = p->stats.packets;
926 bytes = p->stats.bytes;
57a7744e 927 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 928 rx_b += bytes;
929 rx_p += packets;
420136cc
MW		 930 rx_buf += p->rx_stats.alloc_buff_failed;
931 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 932 }
980e9b11 933 rcu_read_unlock();
41c445ff
JB		 934 vsi->tx_restart = tx_restart;
935 vsi->tx_busy = tx_busy;
2fc3d715 936 vsi->tx_linearize = tx_linearize;
41c445ff
JB		 937 vsi->rx_page_failed = rx_page;
938 vsi->rx_buf_failed = rx_buf;
939
940 ns->rx_packets = rx_p;
941 ns->rx_bytes = rx_b;
942 ns->tx_packets = tx_p;
943 ns->tx_bytes = tx_b;
944
41c445ff 945 /* update netdev stats from eth stats */
7812fddc 946 i40e_update_eth_stats(vsi);
41c445ff
JB		 947 ons->tx_errors = oes->tx_errors;
948 ns->tx_errors = es->tx_errors;
949 ons->multicast = oes->rx_multicast;
950 ns->multicast = es->rx_multicast;
41a9e55c
SN		 951 ons->rx_dropped = oes->rx_discards;
952 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 953 ons->tx_dropped = oes->tx_discards;
954 ns->tx_dropped = es->tx_discards;
955
7812fddc 956 /* pull in a couple PF stats if this is the main vsi */
41c445ff 957 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 958 ns->rx_crc_errors = pf->stats.crc_errors;
959 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
960 ns->rx_length_errors = pf->stats.rx_length_errors;
961 }
962}
41c445ff 963
7812fddc 964/**
b40c82e6 965 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 966 * @pf: the PF to be updated
967 **/
968static void i40e_update_pf_stats(struct i40e_pf *pf)
969{
970 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
971 struct i40e_hw_port_stats *nsd = &pf->stats;
972 struct i40e_hw *hw = &pf->hw;
973 u32 val;
974 int i;
41c445ff 975
7812fddc
SN		 976 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
977 I40E_GLPRT_GORCL(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
980 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
981 I40E_GLPRT_GOTCL(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
984 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->eth.rx_discards,
987 &nsd->eth.rx_discards);
532d283d
SN		 988 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
989 I40E_GLPRT_UPRCL(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->eth.rx_unicast,
992 &nsd->eth.rx_unicast);
7812fddc
SN		 993 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
994 I40E_GLPRT_MPRCL(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->eth.rx_multicast,
997 &nsd->eth.rx_multicast);
532d283d
SN		 998 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
999 I40E_GLPRT_BPRCL(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->eth.rx_broadcast,
1002 &nsd->eth.rx_broadcast);
1003 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1004 I40E_GLPRT_UPTCL(hw->port),
1005 pf->stat_offsets_loaded,
1006 &osd->eth.tx_unicast,
1007 &nsd->eth.tx_unicast);
1008 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1009 I40E_GLPRT_MPTCL(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->eth.tx_multicast,
1012 &nsd->eth.tx_multicast);
1013 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1014 I40E_GLPRT_BPTCL(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->eth.tx_broadcast,
1017 &nsd->eth.tx_broadcast);
41c445ff 1018
7812fddc
SN		 1019 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->tx_dropped_link_down,
1022 &nsd->tx_dropped_link_down);
41c445ff 1023
7812fddc
SN		 1024 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1027
7812fddc
SN		 1028 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1031
7812fddc
SN		 1032 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->mac_local_faults,
1035 &nsd->mac_local_faults);
1036 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->mac_remote_faults,
1039 &nsd->mac_remote_faults);
41c445ff 1040
7812fddc
SN		 1041 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_length_errors,
1044 &nsd->rx_length_errors);
41c445ff 1045
7812fddc
SN		 1046 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->link_xon_rx, &nsd->link_xon_rx);
1049 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->link_xon_tx, &nsd->link_xon_tx);
1052 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1053 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1056
7812fddc
SN		 1057 for (i = 0; i < 8; i++) {
1058 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1059 pf->stat_offsets_loaded,
7812fddc
SN		 1060 &osd->priority_xon_rx[i],
1061 &nsd->priority_xon_rx[i]);
1062 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1063 pf->stat_offsets_loaded,
7812fddc
SN		 1064 &osd->priority_xon_tx[i],
1065 &nsd->priority_xon_tx[i]);
1066 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1067 pf->stat_offsets_loaded,
7812fddc
SN		 1068 &osd->priority_xoff_tx[i],
1069 &nsd->priority_xoff_tx[i]);
1070 i40e_stat_update32(hw,
1071 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1072 pf->stat_offsets_loaded,
7812fddc
SN		 1073 &osd->priority_xon_2_xoff[i],
1074 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1075 }
1076
7812fddc
SN		 1077 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1078 I40E_GLPRT_PRC64L(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_size_64, &nsd->rx_size_64);
1081 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1082 I40E_GLPRT_PRC127L(hw->port),
1083 pf->stat_offsets_loaded,
1084 &osd->rx_size_127, &nsd->rx_size_127);
1085 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1086 I40E_GLPRT_PRC255L(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_size_255, &nsd->rx_size_255);
1089 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1090 I40E_GLPRT_PRC511L(hw->port),
1091 pf->stat_offsets_loaded,
1092 &osd->rx_size_511, &nsd->rx_size_511);
1093 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1094 I40E_GLPRT_PRC1023L(hw->port),
1095 pf->stat_offsets_loaded,
1096 &osd->rx_size_1023, &nsd->rx_size_1023);
1097 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1098 I40E_GLPRT_PRC1522L(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_size_1522, &nsd->rx_size_1522);
1101 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1102 I40E_GLPRT_PRC9522L(hw->port),
1103 pf->stat_offsets_loaded,
1104 &osd->rx_size_big, &nsd->rx_size_big);
1105
1106 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1107 I40E_GLPRT_PTC64L(hw->port),
1108 pf->stat_offsets_loaded,
1109 &osd->tx_size_64, &nsd->tx_size_64);
1110 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1111 I40E_GLPRT_PTC127L(hw->port),
1112 pf->stat_offsets_loaded,
1113 &osd->tx_size_127, &nsd->tx_size_127);
1114 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1115 I40E_GLPRT_PTC255L(hw->port),
1116 pf->stat_offsets_loaded,
1117 &osd->tx_size_255, &nsd->tx_size_255);
1118 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1119 I40E_GLPRT_PTC511L(hw->port),
1120 pf->stat_offsets_loaded,
1121 &osd->tx_size_511, &nsd->tx_size_511);
1122 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1123 I40E_GLPRT_PTC1023L(hw->port),
1124 pf->stat_offsets_loaded,
1125 &osd->tx_size_1023, &nsd->tx_size_1023);
1126 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1127 I40E_GLPRT_PTC1522L(hw->port),
1128 pf->stat_offsets_loaded,
1129 &osd->tx_size_1522, &nsd->tx_size_1522);
1130 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1131 I40E_GLPRT_PTC9522L(hw->port),
1132 pf->stat_offsets_loaded,
1133 &osd->tx_size_big, &nsd->tx_size_big);
1134
1135 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1136 pf->stat_offsets_loaded,
1137 &osd->rx_undersize, &nsd->rx_undersize);
1138 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1139 pf->stat_offsets_loaded,
1140 &osd->rx_fragments, &nsd->rx_fragments);
1141 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1142 pf->stat_offsets_loaded,
1143 &osd->rx_oversize, &nsd->rx_oversize);
1144 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1145 pf->stat_offsets_loaded,
1146 &osd->rx_jabber, &nsd->rx_jabber);
1147
433c47de 1148 /* FDIR stats */
0bf4b1b0
ASJ		 1149 i40e_stat_update32(hw,
1150 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1151 pf->stat_offsets_loaded,
1152 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1153 i40e_stat_update32(hw,
1154 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1155 pf->stat_offsets_loaded,
1156 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1157 i40e_stat_update32(hw,
1158 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1159 pf->stat_offsets_loaded,
1160 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1161
7812fddc
SN		 1162 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1163 nsd->tx_lpi_status =
1164 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1165 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1166 nsd->rx_lpi_status =
1167 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1168 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1169 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1170 pf->stat_offsets_loaded,
1171 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1172 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1173 pf->stat_offsets_loaded,
1174 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1175
d0389e51
ASJ		 1176 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1177 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1178 nsd->fd_sb_status = true;
1179 else
1180 nsd->fd_sb_status = false;
1181
1182 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1183 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1184 nsd->fd_atr_status = true;
1185 else
1186 nsd->fd_atr_status = false;
1187
41c445ff
JB		 1188 pf->stat_offsets_loaded = true;
1189}
1190
7812fddc
SN		 1191/**
1192 * i40e_update_stats - Update the various statistics counters.
1193 * @vsi: the VSI to be updated
1194 *
1195 * Update the various stats for this VSI and its related entities.
1196 **/
1197void i40e_update_stats(struct i40e_vsi *vsi)
1198{
1199 struct i40e_pf *pf = vsi->back;
1200
1201 if (vsi == pf->vsi[pf->lan_vsi])
1202 i40e_update_pf_stats(pf);
1203
1204 i40e_update_vsi_stats(vsi);
38e00438
VD		 1205#ifdef I40E_FCOE
1206 i40e_update_fcoe_stats(vsi);
1207#endif
7812fddc
SN		 1208}
1209
41c445ff
JB		 1210/**
1211 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1212 * @vsi: the VSI to be searched
1213 * @macaddr: the MAC address
1214 * @vlan: the vlan
b40c82e6 1215 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1216 * @is_netdev: make sure its a netdev filter, else doesn't matter
1217 *
1218 * Returns ptr to the filter object or NULL
1219 **/
1220static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1221 u8 *macaddr, s16 vlan,
1222 bool is_vf, bool is_netdev)
1223{
1224 struct i40e_mac_filter *f;
1225
1226 if (!vsi || !macaddr)
1227 return NULL;
1228
1229 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1230 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1231 (vlan == f->vlan) &&
1232 (!is_vf || f->is_vf) &&
1233 (!is_netdev || f->is_netdev))
1234 return f;
1235 }
1236 return NULL;
1237}
1238
1239/**
1240 * i40e_find_mac - Find a mac addr in the macvlan filters list
1241 * @vsi: the VSI to be searched
1242 * @macaddr: the MAC address we are searching for
b40c82e6 1243 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1244 * @is_netdev: make sure its a netdev filter, else doesn't matter
1245 *
1246 * Returns the first filter with the provided MAC address or NULL if
1247 * MAC address was not found
1248 **/
1249struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1250 bool is_vf, bool is_netdev)
1251{
1252 struct i40e_mac_filter *f;
1253
1254 if (!vsi || !macaddr)
1255 return NULL;
1256
1257 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1258 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1259 (!is_vf || f->is_vf) &&
1260 (!is_netdev || f->is_netdev))
1261 return f;
1262 }
1263 return NULL;
1264}
1265
1266/**
1267 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1268 * @vsi: the VSI to be searched
1269 *
1270 * Returns true if VSI is in vlan mode or false otherwise
1271 **/
1272bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1273{
1274 struct i40e_mac_filter *f;
1275
1276 /* Only -1 for all the filters denotes not in vlan mode
1277 * so we have to go through all the list in order to make sure
1278 */
1279 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1280 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1281 return true;
1282 }
1283
1284 return false;
1285}
1286
1287/**
1288 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1289 * @vsi: the VSI to be searched
1290 * @macaddr: the mac address to be filtered
b40c82e6 1291 * @is_vf: true if it is a VF
41c445ff
JB		 1292 * @is_netdev: true if it is a netdev
1293 *
1294 * Goes through all the macvlan filters and adds a
1295 * macvlan filter for each unique vlan that already exists
1296 *
1297 * Returns first filter found on success, else NULL
1298 **/
1299struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1300 bool is_vf, bool is_netdev)
1301{
1302 struct i40e_mac_filter *f;
1303
1304 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1305 if (vsi->info.pvid)
1306 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1307 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1308 is_vf, is_netdev)) {
1309 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1310 is_vf, is_netdev))
41c445ff
JB		 1311 return NULL;
1312 }
1313 }
1314
1315 return list_first_entry_or_null(&vsi->mac_filter_list,
1316 struct i40e_mac_filter, list);
1317}
1318
8c27d42e
GR		 1319/**
1320 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1321 * @vsi: the PF Main VSI - inappropriate for any other VSI
1322 * @macaddr: the MAC address
30650cc5
SN		 1323 *
1324 * Some older firmware configurations set up a default promiscuous VLAN
1325 * filter that needs to be removed.
8c27d42e 1326 **/
30650cc5 1327static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1328{
1329 struct i40e_aqc_remove_macvlan_element_data element;
1330 struct i40e_pf *pf = vsi->back;
f1c7e72e 1331 i40e_status ret;
8c27d42e
GR		 1332
1333 /* Only appropriate for the PF main VSI */
1334 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1335 return -EINVAL;
8c27d42e 1336
30650cc5 1337 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1338 ether_addr_copy(element.mac_addr, macaddr);
1339 element.vlan_tag = 0;
1340 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1341 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1342 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1343 if (ret)
30650cc5
SN		 1344 return -ENOENT;
1345
1346 return 0;
8c27d42e
GR		 1347}
1348
41c445ff
JB		 1349/**
1350 * i40e_add_filter - Add a mac/vlan filter to the VSI
1351 * @vsi: the VSI to be searched
1352 * @macaddr: the MAC address
1353 * @vlan: the vlan
b40c82e6 1354 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1355 * @is_netdev: make sure its a netdev filter, else doesn't matter
1356 *
1357 * Returns ptr to the filter object or NULL when no memory available.
1358 **/
1359struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1360 u8 *macaddr, s16 vlan,
1361 bool is_vf, bool is_netdev)
1362{
1363 struct i40e_mac_filter *f;
1364
1365 if (!vsi || !macaddr)
1366 return NULL;
1367
1368 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1369 if (!f) {
1370 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1371 if (!f)
1372 goto add_filter_out;
1373
9a173901 1374 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1375 f->vlan = vlan;
1376 f->changed = true;
1377
1378 INIT_LIST_HEAD(&f->list);
1379 list_add(&f->list, &vsi->mac_filter_list);
1380 }
1381
1382 /* increment counter and add a new flag if needed */
1383 if (is_vf) {
1384 if (!f->is_vf) {
1385 f->is_vf = true;
1386 f->counter++;
1387 }
1388 } else if (is_netdev) {
1389 if (!f->is_netdev) {
1390 f->is_netdev = true;
1391 f->counter++;
1392 }
1393 } else {
1394 f->counter++;
1395 }
1396
1397 /* changed tells sync_filters_subtask to
1398 * push the filter down to the firmware
1399 */
1400 if (f->changed) {
1401 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1402 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1403 }
1404
1405add_filter_out:
1406 return f;
1407}
1408
1409/**
1410 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1411 * @vsi: the VSI to be searched
1412 * @macaddr: the MAC address
1413 * @vlan: the vlan
b40c82e6 1414 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1415 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1416 **/
1417void i40e_del_filter(struct i40e_vsi *vsi,
1418 u8 *macaddr, s16 vlan,
1419 bool is_vf, bool is_netdev)
1420{
1421 struct i40e_mac_filter *f;
1422
1423 if (!vsi || !macaddr)
1424 return;
1425
1426 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1427 if (!f || f->counter == 0)
1428 return;
1429
1430 if (is_vf) {
1431 if (f->is_vf) {
1432 f->is_vf = false;
1433 f->counter--;
1434 }
1435 } else if (is_netdev) {
1436 if (f->is_netdev) {
1437 f->is_netdev = false;
1438 f->counter--;
1439 }
1440 } else {
b40c82e6 1441 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1442 int min_f = 0;
6995b36c 1443
41c445ff
JB		 1444 min_f += (f->is_vf ? 1 : 0);
1445 min_f += (f->is_netdev ? 1 : 0);
1446
1447 if (f->counter > min_f)
1448 f->counter--;
1449 }
1450
1451 /* counter == 0 tells sync_filters_subtask to
1452 * remove the filter from the firmware's list
1453 */
1454 if (f->counter == 0) {
1455 f->changed = true;
1456 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1457 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1458 }
1459}
1460
1461/**
1462 * i40e_set_mac - NDO callback to set mac address
1463 * @netdev: network interface device structure
1464 * @p: pointer to an address structure
1465 *
1466 * Returns 0 on success, negative on failure
1467 **/
38e00438
VD		 1468#ifdef I40E_FCOE
1469int i40e_set_mac(struct net_device *netdev, void *p)
1470#else
41c445ff 1471static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1472#endif
41c445ff
JB		 1473{
1474 struct i40e_netdev_priv *np = netdev_priv(netdev);
1475 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1476 struct i40e_pf *pf = vsi->back;
1477 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1478 struct sockaddr *addr = p;
1479 struct i40e_mac_filter *f;
1480
1481 if (!is_valid_ether_addr(addr->sa_data))
1482 return -EADDRNOTAVAIL;
1483
30650cc5
SN		 1484 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1485 netdev_info(netdev, "already using mac address %pM\n",
1486 addr->sa_data);
1487 return 0;
1488 }
41c445ff 1489
80f6428f
ASJ		 1490 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1491 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1492 return -EADDRNOTAVAIL;
1493
30650cc5
SN		 1494 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1495 netdev_info(netdev, "returning to hw mac address %pM\n",
1496 hw->mac.addr);
1497 else
1498 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1499
41c445ff
JB		 1500 if (vsi->type == I40E_VSI_MAIN) {
1501 i40e_status ret;
6995b36c 1502
41c445ff 1503 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1504 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1505 addr->sa_data, NULL);
1506 if (ret) {
1507 netdev_info(netdev,
1508 "Addr change for Main VSI failed: %d\n",
1509 ret);
1510 return -EADDRNOTAVAIL;
1511 }
41c445ff
JB		 1512 }
1513
30650cc5
SN		 1514 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1515 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1516
30650cc5
SN		 1517 memset(&element, 0, sizeof(element));
1518 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1519 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1520 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1521 } else {
6c8ad1ba
SN		 1522 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1523 false, false);
6c8ad1ba 1524 }
41c445ff 1525
30650cc5
SN		 1526 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1527 struct i40e_aqc_add_macvlan_element_data element;
1528
1529 memset(&element, 0, sizeof(element));
1530 ether_addr_copy(element.mac_addr, hw->mac.addr);
1531 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1532 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1533 } else {
1534 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1535 false, false);
1536 if (f)
1537 f->is_laa = true;
1538 }
1539
30e2561b 1540 i40e_sync_vsi_filters(vsi, false);
30650cc5 1541 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1542
1543 return 0;
1544}
1545
1546/**
1547 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1548 * @vsi: the VSI being setup
1549 * @ctxt: VSI context structure
1550 * @enabled_tc: Enabled TCs bitmap
1551 * @is_add: True if called before Add VSI
1552 *
1553 * Setup VSI queue mapping for enabled traffic classes.
1554 **/
38e00438
VD		 1555#ifdef I40E_FCOE
1556void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1557 struct i40e_vsi_context *ctxt,
1558 u8 enabled_tc,
1559 bool is_add)
1560#else
41c445ff
JB		 1561static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1562 struct i40e_vsi_context *ctxt,
1563 u8 enabled_tc,
1564 bool is_add)
38e00438 1565#endif
41c445ff
JB		 1566{
1567 struct i40e_pf *pf = vsi->back;
1568 u16 sections = 0;
1569 u8 netdev_tc = 0;
1570 u16 numtc = 0;
1571 u16 qcount;
1572 u8 offset;
1573 u16 qmap;
1574 int i;
4e3b35b0 1575 u16 num_tc_qps = 0;
41c445ff
JB		 1576
1577 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1578 offset = 0;
1579
1580 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1581 /* Find numtc from enabled TC bitmap */
1582 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1583 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1584 numtc++;
1585 }
1586 if (!numtc) {
1587 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1588 numtc = 1;
1589 }
1590 } else {
1591 /* At least TC0 is enabled in case of non-DCB case */
1592 numtc = 1;
1593 }
1594
1595 vsi->tc_config.numtc = numtc;
1596 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1597 /* Number of queues per enabled TC */
7f9ff476
AS		 1598 /* In MFP case we can have a much lower count of MSIx
1599 * vectors available and so we need to lower the used
1600 * q count.
1601 */
26cdc443
ASJ		 1602 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1603 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1604 else
1605 qcount = vsi->alloc_queue_pairs;
7f9ff476 1606 num_tc_qps = qcount / numtc;
e25d00b8 1607 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1608
1609 /* Setup queue offset/count for all TCs for given VSI */
1610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1611 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1612 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1613 /* TC is enabled */
41c445ff
JB		 1614 int pow, num_qps;
1615
41c445ff
JB		 1616 switch (vsi->type) {
1617 case I40E_VSI_MAIN:
4e3b35b0 1618 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1619 break;
38e00438
VD		 1620#ifdef I40E_FCOE
1621 case I40E_VSI_FCOE:
1622 qcount = num_tc_qps;
1623 break;
1624#endif
41c445ff
JB		 1625 case I40E_VSI_FDIR:
1626 case I40E_VSI_SRIOV:
1627 case I40E_VSI_VMDQ2:
1628 default:
4e3b35b0 1629 qcount = num_tc_qps;
41c445ff
JB		 1630 WARN_ON(i != 0);
1631 break;
1632 }
4e3b35b0
NP		 1633 vsi->tc_config.tc_info[i].qoffset = offset;
1634 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1635
1e200e4a 1636 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1637 num_qps = qcount;
41c445ff 1638 pow = 0;
41a1d04b 1639 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1640 pow++;
1641 num_qps >>= 1;
1642 }
1643
1644 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1645 qmap =
1646 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1647 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1648
4e3b35b0 1649 offset += qcount;
41c445ff
JB		 1650 } else {
1651 /* TC is not enabled so set the offset to
1652 * default queue and allocate one queue
1653 * for the given TC.
1654 */
1655 vsi->tc_config.tc_info[i].qoffset = 0;
1656 vsi->tc_config.tc_info[i].qcount = 1;
1657 vsi->tc_config.tc_info[i].netdev_tc = 0;
1658
1659 qmap = 0;
1660 }
1661 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1662 }
1663
1664 /* Set actual Tx/Rx queue pairs */
1665 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1666 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1667 if (vsi->req_queue_pairs > 0)
1668 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1669 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1670 vsi->num_queue_pairs = pf->num_lan_msix;
1671 }
41c445ff
JB		 1672
1673 /* Scheduler section valid can only be set for ADD VSI */
1674 if (is_add) {
1675 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1676
1677 ctxt->info.up_enable_bits = enabled_tc;
1678 }
1679 if (vsi->type == I40E_VSI_SRIOV) {
1680 ctxt->info.mapping_flags |=
1681 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1682 for (i = 0; i < vsi->num_queue_pairs; i++)
1683 ctxt->info.queue_mapping[i] =
1684 cpu_to_le16(vsi->base_queue + i);
1685 } else {
1686 ctxt->info.mapping_flags |=
1687 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1688 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1689 }
1690 ctxt->info.valid_sections |= cpu_to_le16(sections);
1691}
1692
1693/**
1694 * i40e_set_rx_mode - NDO callback to set the netdev filters
1695 * @netdev: network interface device structure
1696 **/
38e00438
VD		 1697#ifdef I40E_FCOE
1698void i40e_set_rx_mode(struct net_device *netdev)
1699#else
41c445ff 1700static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1701#endif
41c445ff
JB		 1702{
1703 struct i40e_netdev_priv *np = netdev_priv(netdev);
1704 struct i40e_mac_filter *f, *ftmp;
1705 struct i40e_vsi *vsi = np->vsi;
1706 struct netdev_hw_addr *uca;
1707 struct netdev_hw_addr *mca;
1708 struct netdev_hw_addr *ha;
1709
1710 /* add addr if not already in the filter list */
1711 netdev_for_each_uc_addr(uca, netdev) {
1712 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1713 if (i40e_is_vsi_in_vlan(vsi))
1714 i40e_put_mac_in_vlan(vsi, uca->addr,
1715 false, true);
1716 else
1717 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1718 false, true);
1719 }
1720 }
1721
1722 netdev_for_each_mc_addr(mca, netdev) {
1723 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1724 if (i40e_is_vsi_in_vlan(vsi))
1725 i40e_put_mac_in_vlan(vsi, mca->addr,
1726 false, true);
1727 else
1728 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1729 false, true);
1730 }
1731 }
1732
1733 /* remove filter if not in netdev list */
1734 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1735
1736 if (!f->is_netdev)
1737 continue;
1738
2f41f335
SN		 1739 netdev_for_each_mc_addr(mca, netdev)
1740 if (ether_addr_equal(mca->addr, f->macaddr))
1741 goto bottom_of_search_loop;
41c445ff 1742
2f41f335
SN		 1743 netdev_for_each_uc_addr(uca, netdev)
1744 if (ether_addr_equal(uca->addr, f->macaddr))
1745 goto bottom_of_search_loop;
1746
1747 for_each_dev_addr(netdev, ha)
1748 if (ether_addr_equal(ha->addr, f->macaddr))
1749 goto bottom_of_search_loop;
1750
1751 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1752 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1753
1754bottom_of_search_loop:
1755 continue;
41c445ff
JB		 1756 }
1757
1758 /* check for other flag changes */
1759 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1760 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1761 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1762 }
1763}
1764
1765/**
1766 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1767 * @vsi: ptr to the VSI
30e2561b 1768 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1769 *
1770 * Push any outstanding VSI filter changes through the AdminQ.
1771 *
1772 * Returns 0 or error value
1773 **/
30e2561b 1774int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff
JB		 1775{
1776 struct i40e_mac_filter *f, *ftmp;
1777 bool promisc_forced_on = false;
1778 bool add_happened = false;
1779 int filter_list_len = 0;
1780 u32 changed_flags = 0;
f1c7e72e 1781 i40e_status ret = 0;
41c445ff
JB		 1782 struct i40e_pf *pf;
1783 int num_add = 0;
1784 int num_del = 0;
f1c7e72e 1785 int aq_err = 0;
41c445ff
JB		 1786 u16 cmd_flags;
1787
1788 /* empty array typed pointers, kcalloc later */
1789 struct i40e_aqc_add_macvlan_element_data *add_list;
1790 struct i40e_aqc_remove_macvlan_element_data *del_list;
1791
1792 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1793 usleep_range(1000, 2000);
1794 pf = vsi->back;
1795
1796 if (vsi->netdev) {
1797 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1798 vsi->current_netdev_flags = vsi->netdev->flags;
1799 }
1800
1801 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1802 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1803
1804 filter_list_len = pf->hw.aq.asq_buf_size /
1805 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1806 del_list = kcalloc(filter_list_len,
1807 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1808 GFP_KERNEL);
1809 if (!del_list)
1810 return -ENOMEM;
1811
1812 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1813 if (!f->changed)
1814 continue;
1815
1816 if (f->counter != 0)
1817 continue;
1818 f->changed = false;
1819 cmd_flags = 0;
1820
1821 /* add to delete list */
9a173901 1822 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1823 del_list[num_del].vlan_tag =
1824 cpu_to_le16((u16)(f->vlan ==
1825 I40E_VLAN_ANY ? 0 : f->vlan));
1826
41c445ff
JB		 1827 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1828 del_list[num_del].flags = cmd_flags;
1829 num_del++;
1830
1831 /* unlink from filter list */
1832 list_del(&f->list);
1833 kfree(f);
1834
1835 /* flush a full buffer */
1836 if (num_del == filter_list_len) {
f1c7e72e
SN		 1837 ret = i40e_aq_remove_macvlan(&pf->hw,
1838 vsi->seid, del_list, num_del,
1839 NULL);
1840 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1841 num_del = 0;
1842 memset(del_list, 0, sizeof(*del_list));
1843
f1c7e72e 1844 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1845 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1846 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1847 i40e_stat_str(&pf->hw, ret),
1848 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1849 }
1850 }
1851 if (num_del) {
f1c7e72e 1852 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1853 del_list, num_del, NULL);
f1c7e72e 1854 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1855 num_del = 0;
1856
f1c7e72e 1857 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1859 "ignoring delete macvlan error, err %s aq_err %s\n",
1860 i40e_stat_str(&pf->hw, ret),
1861 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1862 }
1863
1864 kfree(del_list);
1865 del_list = NULL;
1866
1867 /* do all the adds now */
1868 filter_list_len = pf->hw.aq.asq_buf_size /
1869 sizeof(struct i40e_aqc_add_macvlan_element_data),
1870 add_list = kcalloc(filter_list_len,
1871 sizeof(struct i40e_aqc_add_macvlan_element_data),
1872 GFP_KERNEL);
1873 if (!add_list)
1874 return -ENOMEM;
1875
1876 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1877 if (!f->changed)
1878 continue;
1879
1880 if (f->counter == 0)
1881 continue;
1882 f->changed = false;
1883 add_happened = true;
1884 cmd_flags = 0;
1885
1886 /* add to add array */
9a173901 1887 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1888 add_list[num_add].vlan_tag =
1889 cpu_to_le16(
1890 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1891 add_list[num_add].queue_number = 0;
1892
1893 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1894 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1895 num_add++;
1896
1897 /* flush a full buffer */
1898 if (num_add == filter_list_len) {
f1c7e72e
SN		 1899 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1900 add_list, num_add,
1901 NULL);
1902 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1903 num_add = 0;
1904
f1c7e72e 1905 if (ret)
41c445ff
JB		 1906 break;
1907 memset(add_list, 0, sizeof(*add_list));
1908 }
1909 }
1910 if (num_add) {
f1c7e72e
SN		 1911 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1912 add_list, num_add, NULL);
1913 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1914 num_add = 0;
1915 }
1916 kfree(add_list);
1917 add_list = NULL;
1918
f1c7e72e 1919 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1920 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1921 "add filter failed, err %s aq_err %s\n",
1922 i40e_stat_str(&pf->hw, ret),
1923 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1924 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1925 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1926 &vsi->state)) {
1927 promisc_forced_on = true;
1928 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1929 &vsi->state);
1930 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1931 }
1932 }
1933 }
1934
1935 /* check for changes in promiscuous modes */
1936 if (changed_flags & IFF_ALLMULTI) {
1937 bool cur_multipromisc;
6995b36c 1938
41c445ff 1939 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1940 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1941 vsi->seid,
1942 cur_multipromisc,
1943 NULL);
1944 if (ret)
41c445ff 1945 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1946 "set multi promisc failed, err %s aq_err %s\n",
1947 i40e_stat_str(&pf->hw, ret),
1948 i40e_aq_str(&pf->hw,
1949 pf->hw.aq.asq_last_status));
41c445ff
JB		 1950 }
1951 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1952 bool cur_promisc;
6995b36c 1953
41c445ff
JB		 1954 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1955 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1956 &vsi->state));
92faef85
ASJ		 1957 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
1958 /* set defport ON for Main VSI instead of true promisc
1959 * this way we will get all unicast/multicast and VLAN
1960 * promisc behavior but will not get VF or VMDq traffic
1961 * replicated on the Main VSI.
1962 */
1963 if (pf->cur_promisc != cur_promisc) {
1964 pf->cur_promisc = cur_promisc;
30e2561b
AS		 1965 if (grab_rtnl)
1966 i40e_do_reset_safe(pf,
1967 BIT(__I40E_PF_RESET_REQUESTED));
1968 else
1969 i40e_do_reset(pf,
92faef85
ASJ		 1970 BIT(__I40E_PF_RESET_REQUESTED));
1971 }
1972 } else {
1973 ret = i40e_aq_set_vsi_unicast_promiscuous(
1974 &vsi->back->hw,
f1c7e72e
SN		 1975 vsi->seid,
1976 cur_promisc, NULL);
92faef85
ASJ		 1977 if (ret)
1978 dev_info(&pf->pdev->dev,
1979 "set unicast promisc failed, err %d, aq_err %d\n",
1980 ret, pf->hw.aq.asq_last_status);
1981 ret = i40e_aq_set_vsi_multicast_promiscuous(
1982 &vsi->back->hw,
1983 vsi->seid,
1984 cur_promisc, NULL);
1985 if (ret)
1986 dev_info(&pf->pdev->dev,
1987 "set multicast promisc failed, err %d, aq_err %d\n",
1988 ret, pf->hw.aq.asq_last_status);
1989 }
f1c7e72e
SN		 1990 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1991 vsi->seid,
1992 cur_promisc, NULL);
1993 if (ret)
1a10370a 1994 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1995 "set brdcast promisc failed, err %s, aq_err %s\n",
1996 i40e_stat_str(&pf->hw, ret),
1997 i40e_aq_str(&pf->hw,
1998 pf->hw.aq.asq_last_status));
41c445ff
JB		 1999 }
2000
2001 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2002 return 0;
2003}
2004
2005/**
2006 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2007 * @pf: board private structure
2008 **/
2009static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2010{
2011 int v;
2012
2013 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2014 return;
2015 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2016
505682cd 2017 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2018 if (pf->vsi[v] &&
2019 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2020 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2021 }
2022}
2023
2024/**
2025 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2026 * @netdev: network interface device structure
2027 * @new_mtu: new value for maximum frame size
2028 *
2029 * Returns 0 on success, negative on failure
2030 **/
2031static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2032{
2033 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2034 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2035 struct i40e_vsi *vsi = np->vsi;
2036
2037 /* MTU < 68 is an error and causes problems on some kernels */
2038 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2039 return -EINVAL;
2040
2041 netdev_info(netdev, "changing MTU from %d to %d\n",
2042 netdev->mtu, new_mtu);
2043 netdev->mtu = new_mtu;
2044 if (netif_running(netdev))
2045 i40e_vsi_reinit_locked(vsi);
2046
2047 return 0;
2048}
2049
beb0dff1
JK		 2050/**
2051 * i40e_ioctl - Access the hwtstamp interface
2052 * @netdev: network interface device structure
2053 * @ifr: interface request data
2054 * @cmd: ioctl command
2055 **/
2056int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2057{
2058 struct i40e_netdev_priv *np = netdev_priv(netdev);
2059 struct i40e_pf *pf = np->vsi->back;
2060
2061 switch (cmd) {
2062 case SIOCGHWTSTAMP:
2063 return i40e_ptp_get_ts_config(pf, ifr);
2064 case SIOCSHWTSTAMP:
2065 return i40e_ptp_set_ts_config(pf, ifr);
2066 default:
2067 return -EOPNOTSUPP;
2068 }
2069}
2070
41c445ff
JB		 2071/**
2072 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2073 * @vsi: the vsi being adjusted
2074 **/
2075void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2076{
2077 struct i40e_vsi_context ctxt;
2078 i40e_status ret;
2079
2080 if ((vsi->info.valid_sections &
2081 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2082 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2083 return; /* already enabled */
2084
2085 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2086 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2087 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2088
2089 ctxt.seid = vsi->seid;
1a2f6248 2090 ctxt.info = vsi->info;
41c445ff
JB		 2091 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2092 if (ret) {
2093 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2094 "update vlan stripping failed, err %s aq_err %s\n",
2095 i40e_stat_str(&vsi->back->hw, ret),
2096 i40e_aq_str(&vsi->back->hw,
2097 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2098 }
2099}
2100
2101/**
2102 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2103 * @vsi: the vsi being adjusted
2104 **/
2105void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2106{
2107 struct i40e_vsi_context ctxt;
2108 i40e_status ret;
2109
2110 if ((vsi->info.valid_sections &
2111 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2112 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2113 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2114 return; /* already disabled */
2115
2116 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2117 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2118 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2119
2120 ctxt.seid = vsi->seid;
1a2f6248 2121 ctxt.info = vsi->info;
41c445ff
JB		 2122 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2123 if (ret) {
2124 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2125 "update vlan stripping failed, err %s aq_err %s\n",
2126 i40e_stat_str(&vsi->back->hw, ret),
2127 i40e_aq_str(&vsi->back->hw,
2128 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2129 }
2130}
2131
2132/**
2133 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2134 * @netdev: network interface to be adjusted
2135 * @features: netdev features to test if VLAN offload is enabled or not
2136 **/
2137static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2138{
2139 struct i40e_netdev_priv *np = netdev_priv(netdev);
2140 struct i40e_vsi *vsi = np->vsi;
2141
2142 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2143 i40e_vlan_stripping_enable(vsi);
2144 else
2145 i40e_vlan_stripping_disable(vsi);
2146}
2147
2148/**
2149 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2150 * @vsi: the vsi being configured
2151 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2152 **/
2153int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2154{
2155 struct i40e_mac_filter *f, *add_f;
2156 bool is_netdev, is_vf;
41c445ff
JB		 2157
2158 is_vf = (vsi->type == I40E_VSI_SRIOV);
2159 is_netdev = !!(vsi->netdev);
2160
2161 if (is_netdev) {
2162 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2163 is_vf, is_netdev);
2164 if (!add_f) {
2165 dev_info(&vsi->back->pdev->dev,
2166 "Could not add vlan filter %d for %pM\n",
2167 vid, vsi->netdev->dev_addr);
2168 return -ENOMEM;
2169 }
2170 }
2171
2172 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2173 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2174 if (!add_f) {
2175 dev_info(&vsi->back->pdev->dev,
2176 "Could not add vlan filter %d for %pM\n",
2177 vid, f->macaddr);
2178 return -ENOMEM;
2179 }
2180 }
2181
41c445ff
JB		 2182 /* Now if we add a vlan tag, make sure to check if it is the first
2183 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2184 * with 0, so we now accept untagged and specified tagged traffic
2185 * (and not any taged and untagged)
2186 */
2187 if (vid > 0) {
2188 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2189 I40E_VLAN_ANY,
2190 is_vf, is_netdev)) {
2191 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2192 I40E_VLAN_ANY, is_vf, is_netdev);
2193 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2194 is_vf, is_netdev);
2195 if (!add_f) {
2196 dev_info(&vsi->back->pdev->dev,
2197 "Could not add filter 0 for %pM\n",
2198 vsi->netdev->dev_addr);
2199 return -ENOMEM;
2200 }
2201 }
8d82a7c5 2202 }
41c445ff 2203
8d82a7c5
GR		 2204 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2205 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2206 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2207 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2208 is_vf, is_netdev)) {
2209 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2210 is_vf, is_netdev);
2211 add_f = i40e_add_filter(vsi, f->macaddr,
2212 0, is_vf, is_netdev);
2213 if (!add_f) {
2214 dev_info(&vsi->back->pdev->dev,
2215 "Could not add filter 0 for %pM\n",
2216 f->macaddr);
2217 return -ENOMEM;
2218 }
2219 }
2220 }
41c445ff
JB		 2221 }
2222
80f6428f
ASJ		 2223 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2224 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2225 return 0;
2226
30e2561b 2227 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2228}
2229
2230/**
2231 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2232 * @vsi: the vsi being configured
2233 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2234 *
2235 * Return: 0 on success or negative otherwise
41c445ff
JB		 2236 **/
2237int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2238{
2239 struct net_device *netdev = vsi->netdev;
2240 struct i40e_mac_filter *f, *add_f;
2241 bool is_vf, is_netdev;
2242 int filter_count = 0;
41c445ff
JB		 2243
2244 is_vf = (vsi->type == I40E_VSI_SRIOV);
2245 is_netdev = !!(netdev);
2246
2247 if (is_netdev)
2248 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2249
2250 list_for_each_entry(f, &vsi->mac_filter_list, list)
2251 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2252
41c445ff
JB		 2253 /* go through all the filters for this VSI and if there is only
2254 * vid == 0 it means there are no other filters, so vid 0 must
2255 * be replaced with -1. This signifies that we should from now
2256 * on accept any traffic (with any tag present, or untagged)
2257 */
2258 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2259 if (is_netdev) {
2260 if (f->vlan &&
2261 ether_addr_equal(netdev->dev_addr, f->macaddr))
2262 filter_count++;
2263 }
2264
2265 if (f->vlan)
2266 filter_count++;
2267 }
2268
2269 if (!filter_count && is_netdev) {
2270 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2271 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2272 is_vf, is_netdev);
2273 if (!f) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Could not add filter %d for %pM\n",
2276 I40E_VLAN_ANY, netdev->dev_addr);
2277 return -ENOMEM;
2278 }
2279 }
2280
2281 if (!filter_count) {
2282 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2283 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2284 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2285 is_vf, is_netdev);
2286 if (!add_f) {
2287 dev_info(&vsi->back->pdev->dev,
2288 "Could not add filter %d for %pM\n",
2289 I40E_VLAN_ANY, f->macaddr);
2290 return -ENOMEM;
2291 }
2292 }
2293 }
2294
80f6428f
ASJ		 2295 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2296 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2297 return 0;
2298
30e2561b 2299 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2300}
2301
2302/**
2303 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2304 * @netdev: network interface to be adjusted
2305 * @vid: vlan id to be added
078b5876
JB		 2306 *
2307 * net_device_ops implementation for adding vlan ids
41c445ff 2308 **/
38e00438
VD		 2309#ifdef I40E_FCOE
2310int i40e_vlan_rx_add_vid(struct net_device *netdev,
2311 __always_unused __be16 proto, u16 vid)
2312#else
41c445ff
JB		 2313static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2314 __always_unused __be16 proto, u16 vid)
38e00438 2315#endif
41c445ff
JB		 2316{
2317 struct i40e_netdev_priv *np = netdev_priv(netdev);
2318 struct i40e_vsi *vsi = np->vsi;
078b5876 2319 int ret = 0;
41c445ff
JB		 2320
2321 if (vid > 4095)
078b5876
JB		 2322 return -EINVAL;
2323
2324 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2325
6982d429
ASJ		 2326 /* If the network stack called us with vid = 0 then
2327 * it is asking to receive priority tagged packets with
2328 * vlan id 0. Our HW receives them by default when configured
2329 * to receive untagged packets so there is no need to add an
2330 * extra filter for vlan 0 tagged packets.
41c445ff 2331 */
6982d429
ASJ		 2332 if (vid)
2333 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2334
078b5876
JB		 2335 if (!ret && (vid < VLAN_N_VID))
2336 set_bit(vid, vsi->active_vlans);
41c445ff 2337
078b5876 2338 return ret;
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2343 * @netdev: network interface to be adjusted
2344 * @vid: vlan id to be removed
078b5876 2345 *
fdfd943e 2346 * net_device_ops implementation for removing vlan ids
41c445ff 2347 **/
38e00438
VD		 2348#ifdef I40E_FCOE
2349int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2350 __always_unused __be16 proto, u16 vid)
2351#else
41c445ff
JB		 2352static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2353 __always_unused __be16 proto, u16 vid)
38e00438 2354#endif
41c445ff
JB		 2355{
2356 struct i40e_netdev_priv *np = netdev_priv(netdev);
2357 struct i40e_vsi *vsi = np->vsi;
2358
078b5876
JB		 2359 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2360
41c445ff
JB		 2361 /* return code is ignored as there is nothing a user
2362 * can do about failure to remove and a log message was
078b5876 2363 * already printed from the other function
41c445ff
JB		 2364 */
2365 i40e_vsi_kill_vlan(vsi, vid);
2366
2367 clear_bit(vid, vsi->active_vlans);
078b5876 2368
41c445ff
JB		 2369 return 0;
2370}
2371
2372/**
2373 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2374 * @vsi: the vsi being brought back up
2375 **/
2376static void i40e_restore_vlan(struct i40e_vsi *vsi)
2377{
2378 u16 vid;
2379
2380 if (!vsi->netdev)
2381 return;
2382
2383 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2384
2385 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2386 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2387 vid);
2388}
2389
2390/**
2391 * i40e_vsi_add_pvid - Add pvid for the VSI
2392 * @vsi: the vsi being adjusted
2393 * @vid: the vlan id to set as a PVID
2394 **/
dcae29be 2395int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2396{
2397 struct i40e_vsi_context ctxt;
f1c7e72e 2398 i40e_status ret;
41c445ff
JB		 2399
2400 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2401 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2402 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2403 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2404 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2405
2406 ctxt.seid = vsi->seid;
1a2f6248 2407 ctxt.info = vsi->info;
f1c7e72e
SN		 2408 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2409 if (ret) {
41c445ff 2410 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2411 "add pvid failed, err %s aq_err %s\n",
2412 i40e_stat_str(&vsi->back->hw, ret),
2413 i40e_aq_str(&vsi->back->hw,
2414 vsi->back->hw.aq.asq_last_status));
dcae29be 2415 return -ENOENT;
41c445ff
JB		 2416 }
2417
dcae29be 2418 return 0;
41c445ff
JB		 2419}
2420
2421/**
2422 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2423 * @vsi: the vsi being adjusted
2424 *
2425 * Just use the vlan_rx_register() service to put it back to normal
2426 **/
2427void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2428{
6c12fcbf
GR		 2429 i40e_vlan_stripping_disable(vsi);
2430
41c445ff 2431 vsi->info.pvid = 0;
41c445ff
JB		 2432}
2433
2434/**
2435 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2436 * @vsi: ptr to the VSI
2437 *
2438 * If this function returns with an error, then it's possible one or
2439 * more of the rings is populated (while the rest are not). It is the
2440 * callers duty to clean those orphaned rings.
2441 *
2442 * Return 0 on success, negative on failure
2443 **/
2444static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2445{
2446 int i, err = 0;
2447
2448 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2449 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2450
2451 return err;
2452}
2453
2454/**
2455 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2456 * @vsi: ptr to the VSI
2457 *
2458 * Free VSI's transmit software resources
2459 **/
2460static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2461{
2462 int i;
2463
8e9dca53
GR		 2464 if (!vsi->tx_rings)
2465 return;
2466
41c445ff 2467 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2468 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2469 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2470}
2471
2472/**
2473 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2474 * @vsi: ptr to the VSI
2475 *
2476 * If this function returns with an error, then it's possible one or
2477 * more of the rings is populated (while the rest are not). It is the
2478 * callers duty to clean those orphaned rings.
2479 *
2480 * Return 0 on success, negative on failure
2481 **/
2482static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2483{
2484 int i, err = 0;
2485
2486 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2487 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2488#ifdef I40E_FCOE
2489 i40e_fcoe_setup_ddp_resources(vsi);
2490#endif
41c445ff
JB		 2491 return err;
2492}
2493
2494/**
2495 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2496 * @vsi: ptr to the VSI
2497 *
2498 * Free all receive software resources
2499 **/
2500static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2501{
2502 int i;
2503
8e9dca53
GR		 2504 if (!vsi->rx_rings)
2505 return;
2506
41c445ff 2507 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2508 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2509 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2510#ifdef I40E_FCOE
2511 i40e_fcoe_free_ddp_resources(vsi);
2512#endif
41c445ff
JB		 2513}
2514
3ffa037d
NP		 2515/**
2516 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2517 * @ring: The Tx ring to configure
2518 *
2519 * This enables/disables XPS for a given Tx descriptor ring
2520 * based on the TCs enabled for the VSI that ring belongs to.
2521 **/
2522static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2523{
2524 struct i40e_vsi *vsi = ring->vsi;
2525 cpumask_var_t mask;
2526
9a660eea
JB		 2527 if (!ring->q_vector || !ring->netdev)
2528 return;
2529
2530 /* Single TC mode enable XPS */
2531 if (vsi->tc_config.numtc <= 1) {
2532 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2533 netif_set_xps_queue(ring->netdev,
2534 &ring->q_vector->affinity_mask,
2535 ring->queue_index);
9a660eea
JB		 2536 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2537 /* Disable XPS to allow selection based on TC */
2538 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2539 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2540 free_cpumask_var(mask);
3ffa037d
NP		 2541 }
2542}
2543
41c445ff
JB		 2544/**
2545 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2546 * @ring: The Tx ring to configure
2547 *
2548 * Configure the Tx descriptor ring in the HMC context.
2549 **/
2550static int i40e_configure_tx_ring(struct i40e_ring *ring)
2551{
2552 struct i40e_vsi *vsi = ring->vsi;
2553 u16 pf_q = vsi->base_queue + ring->queue_index;
2554 struct i40e_hw *hw = &vsi->back->hw;
2555 struct i40e_hmc_obj_txq tx_ctx;
2556 i40e_status err = 0;
2557 u32 qtx_ctl = 0;
2558
2559 /* some ATR related tx ring init */
60ea5f83 2560 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2561 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2562 ring->atr_count = 0;
2563 } else {
2564 ring->atr_sample_rate = 0;
2565 }
2566
3ffa037d
NP		 2567 /* configure XPS */
2568 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2569
2570 /* clear the context structure first */
2571 memset(&tx_ctx, 0, sizeof(tx_ctx));
2572
2573 tx_ctx.new_context = 1;
2574 tx_ctx.base = (ring->dma / 128);
2575 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2576 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2577 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2578#ifdef I40E_FCOE
2579 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2580#endif
beb0dff1 2581 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2582 /* FDIR VSI tx ring can still use RS bit and writebacks */
2583 if (vsi->type != I40E_VSI_FDIR)
2584 tx_ctx.head_wb_ena = 1;
2585 tx_ctx.head_wb_addr = ring->dma +
2586 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2587
2588 /* As part of VSI creation/update, FW allocates certain
2589 * Tx arbitration queue sets for each TC enabled for
2590 * the VSI. The FW returns the handles to these queue
2591 * sets as part of the response buffer to Add VSI,
2592 * Update VSI, etc. AQ commands. It is expected that
2593 * these queue set handles be associated with the Tx
2594 * queues by the driver as part of the TX queue context
2595 * initialization. This has to be done regardless of
2596 * DCB as by default everything is mapped to TC0.
2597 */
2598 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2599 tx_ctx.rdylist_act = 0;
2600
2601 /* clear the context in the HMC */
2602 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2603 if (err) {
2604 dev_info(&vsi->back->pdev->dev,
2605 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2606 ring->queue_index, pf_q, err);
2607 return -ENOMEM;
2608 }
2609
2610 /* set the context in the HMC */
2611 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2612 if (err) {
2613 dev_info(&vsi->back->pdev->dev,
2614 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2615 ring->queue_index, pf_q, err);
2616 return -ENOMEM;
2617 }
2618
2619 /* Now associate this queue with this PCI function */
7a28d885 2620 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2621 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2622 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2623 I40E_QTX_CTL_VFVM_INDX_MASK;
2624 } else {
9d8bf547 2625 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2626 }
2627
13fd9774
SN		 2628 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2629 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2630 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2631 i40e_flush(hw);
2632
41c445ff
JB		 2633 /* cache tail off for easier writes later */
2634 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2635
2636 return 0;
2637}
2638
2639/**
2640 * i40e_configure_rx_ring - Configure a receive ring context
2641 * @ring: The Rx ring to configure
2642 *
2643 * Configure the Rx descriptor ring in the HMC context.
2644 **/
2645static int i40e_configure_rx_ring(struct i40e_ring *ring)
2646{
2647 struct i40e_vsi *vsi = ring->vsi;
2648 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2649 u16 pf_q = vsi->base_queue + ring->queue_index;
2650 struct i40e_hw *hw = &vsi->back->hw;
2651 struct i40e_hmc_obj_rxq rx_ctx;
2652 i40e_status err = 0;
2653
2654 ring->state = 0;
2655
2656 /* clear the context structure first */
2657 memset(&rx_ctx, 0, sizeof(rx_ctx));
2658
2659 ring->rx_buf_len = vsi->rx_buf_len;
2660 ring->rx_hdr_len = vsi->rx_hdr_len;
2661
2662 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2663 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2664
2665 rx_ctx.base = (ring->dma / 128);
2666 rx_ctx.qlen = ring->count;
2667
2668 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2669 set_ring_16byte_desc_enabled(ring);
2670 rx_ctx.dsize = 0;
2671 } else {
2672 rx_ctx.dsize = 1;
2673 }
2674
2675 rx_ctx.dtype = vsi->dtype;
2676 if (vsi->dtype) {
2677 set_ring_ps_enabled(ring);
2678 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2679 I40E_RX_SPLIT_IP |
2680 I40E_RX_SPLIT_TCP_UDP |
2681 I40E_RX_SPLIT_SCTP;
2682 } else {
2683 rx_ctx.hsplit_0 = 0;
2684 }
2685
2686 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2687 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2688 if (hw->revision_id == 0)
2689 rx_ctx.lrxqthresh = 0;
2690 else
2691 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2692 rx_ctx.crcstrip = 1;
2693 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2694 /* this controls whether VLAN is stripped from inner headers */
2695 rx_ctx.showiv = 0;
38e00438
VD		 2696#ifdef I40E_FCOE
2697 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2698#endif
acb3676b
CS		 2699 /* set the prefena field to 1 because the manual says to */
2700 rx_ctx.prefena = 1;
41c445ff
JB		 2701
2702 /* clear the context in the HMC */
2703 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2704 if (err) {
2705 dev_info(&vsi->back->pdev->dev,
2706 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2707 ring->queue_index, pf_q, err);
2708 return -ENOMEM;
2709 }
2710
2711 /* set the context in the HMC */
2712 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2713 if (err) {
2714 dev_info(&vsi->back->pdev->dev,
2715 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2716 ring->queue_index, pf_q, err);
2717 return -ENOMEM;
2718 }
2719
2720 /* cache tail for quicker writes, and clear the reg before use */
2721 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2722 writel(0, ring->tail);
2723
a132af24
MW		 2724 if (ring_is_ps_enabled(ring)) {
2725 i40e_alloc_rx_headers(ring);
2726 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2727 } else {
2728 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2729 }
41c445ff
JB		 2730
2731 return 0;
2732}
2733
2734/**
2735 * i40e_vsi_configure_tx - Configure the VSI for Tx
2736 * @vsi: VSI structure describing this set of rings and resources
2737 *
2738 * Configure the Tx VSI for operation.
2739 **/
2740static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2741{
2742 int err = 0;
2743 u16 i;
2744
9f65e15b
AD		 2745 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2746 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2747
2748 return err;
2749}
2750
2751/**
2752 * i40e_vsi_configure_rx - Configure the VSI for Rx
2753 * @vsi: the VSI being configured
2754 *
2755 * Configure the Rx VSI for operation.
2756 **/
2757static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2758{
2759 int err = 0;
2760 u16 i;
2761
2762 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2763 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2764 + ETH_FCS_LEN + VLAN_HLEN;
2765 else
2766 vsi->max_frame = I40E_RXBUFFER_2048;
2767
2768 /* figure out correct receive buffer length */
2769 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2770 I40E_FLAG_RX_PS_ENABLED)) {
2771 case I40E_FLAG_RX_1BUF_ENABLED:
2772 vsi->rx_hdr_len = 0;
2773 vsi->rx_buf_len = vsi->max_frame;
2774 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2775 break;
2776 case I40E_FLAG_RX_PS_ENABLED:
2777 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2778 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2779 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2780 break;
2781 default:
2782 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2783 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2784 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2785 break;
2786 }
2787
38e00438
VD		 2788#ifdef I40E_FCOE
2789 /* setup rx buffer for FCoE */
2790 if ((vsi->type == I40E_VSI_FCOE) &&
2791 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2792 vsi->rx_hdr_len = 0;
2793 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2794 vsi->max_frame = I40E_RXBUFFER_3072;
2795 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2796 }
2797
2798#endif /* I40E_FCOE */
41c445ff
JB		 2799 /* round up for the chip's needs */
2800 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2801 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2802 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2803 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2804
2805 /* set up individual rings */
2806 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2807 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2808
2809 return err;
2810}
2811
2812/**
2813 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2814 * @vsi: ptr to the VSI
2815 **/
2816static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2817{
e7046ee1 2818 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2819 u16 qoffset, qcount;
2820 int i, n;
2821
cd238a3e
PN		 2822 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2823 /* Reset the TC information */
2824 for (i = 0; i < vsi->num_queue_pairs; i++) {
2825 rx_ring = vsi->rx_rings[i];
2826 tx_ring = vsi->tx_rings[i];
2827 rx_ring->dcb_tc = 0;
2828 tx_ring->dcb_tc = 0;
2829 }
2830 }
41c445ff
JB		 2831
2832 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2833 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2834 continue;
2835
2836 qoffset = vsi->tc_config.tc_info[n].qoffset;
2837 qcount = vsi->tc_config.tc_info[n].qcount;
2838 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2839 rx_ring = vsi->rx_rings[i];
2840 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2841 rx_ring->dcb_tc = n;
2842 tx_ring->dcb_tc = n;
2843 }
2844 }
2845}
2846
2847/**
2848 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2849 * @vsi: ptr to the VSI
2850 **/
2851static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2852{
2853 if (vsi->netdev)
2854 i40e_set_rx_mode(vsi->netdev);
2855}
2856
17a73f6b
JG		 2857/**
2858 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2859 * @vsi: Pointer to the targeted VSI
2860 *
2861 * This function replays the hlist on the hw where all the SB Flow Director
2862 * filters were saved.
2863 **/
2864static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2865{
2866 struct i40e_fdir_filter *filter;
2867 struct i40e_pf *pf = vsi->back;
2868 struct hlist_node *node;
2869
55a5e60b
ASJ		 2870 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2871 return;
2872
17a73f6b
JG		 2873 hlist_for_each_entry_safe(filter, node,
2874 &pf->fdir_filter_list, fdir_node) {
2875 i40e_add_del_fdir(vsi, filter, true);
2876 }
2877}
2878
41c445ff
JB		 2879/**
2880 * i40e_vsi_configure - Set up the VSI for action
2881 * @vsi: the VSI being configured
2882 **/
2883static int i40e_vsi_configure(struct i40e_vsi *vsi)
2884{
2885 int err;
2886
2887 i40e_set_vsi_rx_mode(vsi);
2888 i40e_restore_vlan(vsi);
2889 i40e_vsi_config_dcb_rings(vsi);
2890 err = i40e_vsi_configure_tx(vsi);
2891 if (!err)
2892 err = i40e_vsi_configure_rx(vsi);
2893
2894 return err;
2895}
2896
2897/**
2898 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2899 * @vsi: the VSI being configured
2900 **/
2901static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2902{
2903 struct i40e_pf *pf = vsi->back;
2904 struct i40e_q_vector *q_vector;
2905 struct i40e_hw *hw = &pf->hw;
2906 u16 vector;
2907 int i, q;
2908 u32 val;
2909 u32 qp;
2910
2911 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2912 * and PFINT_LNKLSTn registers, e.g.:
2913 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2914 */
2915 qp = vsi->base_queue;
2916 vector = vsi->base_vector;
493fb300
AD		 2917 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2918 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2919 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2920 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2921 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2922 q_vector->rx.itr);
2923 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2924 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2925 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2926 q_vector->tx.itr);
2927
2928 /* Linked list for the queuepairs assigned to this vector */
2929 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2930 for (q = 0; q < q_vector->num_ringpairs; q++) {
2931 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2932 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2933 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2934 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2935 (I40E_QUEUE_TYPE_TX
2936 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2937
2938 wr32(hw, I40E_QINT_RQCTL(qp), val);
2939
2940 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2941 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2942 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2943 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2944 (I40E_QUEUE_TYPE_RX
2945 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2946
2947 /* Terminate the linked list */
2948 if (q == (q_vector->num_ringpairs - 1))
2949 val |= (I40E_QUEUE_END_OF_LIST
2950 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2951
2952 wr32(hw, I40E_QINT_TQCTL(qp), val);
2953 qp++;
2954 }
2955 }
2956
2957 i40e_flush(hw);
2958}
2959
2960/**
2961 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2962 * @hw: ptr to the hardware info
2963 **/
ab437b5a 2964static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2965{
ab437b5a 2966 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2967 u32 val;
2968
2969 /* clear things first */
2970 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2971 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2972
2973 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2974 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2975 I40E_PFINT_ICR0_ENA_GRST_MASK |
2976 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2977 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2978 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2979 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2980 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2981
0d8e1439
ASJ		 2982 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
2983 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
2984
ab437b5a
JK		 2985 if (pf->flags & I40E_FLAG_PTP)
2986 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2987
41c445ff
JB		 2988 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2989
2990 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2991 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2992 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2993
2994 /* OTHER_ITR_IDX = 0 */
2995 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2996}
2997
2998/**
2999 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3000 * @vsi: the VSI being configured
3001 **/
3002static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3003{
493fb300 3004 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3005 struct i40e_pf *pf = vsi->back;
3006 struct i40e_hw *hw = &pf->hw;
3007 u32 val;
3008
3009 /* set the ITR configuration */
3010 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3011 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3012 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3013 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3014 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3015 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3016
ab437b5a 3017 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3018
3019 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3020 wr32(hw, I40E_PFINT_LNKLST0, 0);
3021
f29eaa3d 3022 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3023 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3024 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3025 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3026
3027 wr32(hw, I40E_QINT_RQCTL(0), val);
3028
3029 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3030 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3031 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3032
3033 wr32(hw, I40E_QINT_TQCTL(0), val);
3034 i40e_flush(hw);
3035}
3036
2ef28cfb
MW		 3037/**
3038 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3039 * @pf: board private structure
3040 **/
3041void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3042{
3043 struct i40e_hw *hw = &pf->hw;
3044
3045 wr32(hw, I40E_PFINT_DYN_CTL0,
3046 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3047 i40e_flush(hw);
3048}
3049
41c445ff
JB		 3050/**
3051 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3052 * @pf: board private structure
3053 **/
116a57d4 3054void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3055{
3056 struct i40e_hw *hw = &pf->hw;
3057 u32 val;
3058
3059 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3060 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3061 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3062
3063 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3064 i40e_flush(hw);
3065}
3066
5c2cebda
CW		 3067/**
3068 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3069 * @vsi: pointer to a vsi
03147773 3070 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3071 **/
3072void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3073{
3074 struct i40e_pf *pf = vsi->back;
3075 struct i40e_hw *hw = &pf->hw;
3076 u32 val;
3077
3078 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3079 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3080 i40e_flush(hw);
3081}
3082
41c445ff
JB		 3083/**
3084 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3085 * @irq: interrupt number
3086 * @data: pointer to a q_vector
3087 **/
3088static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3089{
3090 struct i40e_q_vector *q_vector = data;
3091
cd0b6fa6 3092 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3093 return IRQ_HANDLED;
3094
3095 napi_schedule(&q_vector->napi);
3096
3097 return IRQ_HANDLED;
3098}
3099
41c445ff
JB		 3100/**
3101 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3102 * @vsi: the VSI being configured
3103 * @basename: name for the vector
3104 *
3105 * Allocates MSI-X vectors and requests interrupts from the kernel.
3106 **/
3107static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3108{
3109 int q_vectors = vsi->num_q_vectors;
3110 struct i40e_pf *pf = vsi->back;
3111 int base = vsi->base_vector;
3112 int rx_int_idx = 0;
3113 int tx_int_idx = 0;
3114 int vector, err;
3115
3116 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3117 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3118
cd0b6fa6 3119 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3120 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3121 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3122 tx_int_idx++;
cd0b6fa6 3123 } else if (q_vector->rx.ring) {
41c445ff
JB		 3124 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3125 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3126 } else if (q_vector->tx.ring) {
41c445ff
JB		 3127 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3128 "%s-%s-%d", basename, "tx", tx_int_idx++);
3129 } else {
3130 /* skip this unused q_vector */
3131 continue;
3132 }
3133 err = request_irq(pf->msix_entries[base + vector].vector,
3134 vsi->irq_handler,
3135 0,
3136 q_vector->name,
3137 q_vector);
3138 if (err) {
3139 dev_info(&pf->pdev->dev,
fb43201f 3140 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3141 goto free_queue_irqs;
3142 }
3143 /* assign the mask for this irq */
3144 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3145 &q_vector->affinity_mask);
3146 }
3147
63741846 3148 vsi->irqs_ready = true;
41c445ff
JB		 3149 return 0;
3150
3151free_queue_irqs:
3152 while (vector) {
3153 vector--;
3154 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3155 NULL);
3156 free_irq(pf->msix_entries[base + vector].vector,
3157 &(vsi->q_vectors[vector]));
3158 }
3159 return err;
3160}
3161
3162/**
3163 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3164 * @vsi: the VSI being un-configured
3165 **/
3166static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3167{
3168 struct i40e_pf *pf = vsi->back;
3169 struct i40e_hw *hw = &pf->hw;
3170 int base = vsi->base_vector;
3171 int i;
3172
3173 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3174 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3175 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3176 }
3177
3178 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3179 for (i = vsi->base_vector;
3180 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3181 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3182
3183 i40e_flush(hw);
3184 for (i = 0; i < vsi->num_q_vectors; i++)
3185 synchronize_irq(pf->msix_entries[i + base].vector);
3186 } else {
3187 /* Legacy and MSI mode - this stops all interrupt handling */
3188 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3189 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3190 i40e_flush(hw);
3191 synchronize_irq(pf->pdev->irq);
3192 }
3193}
3194
3195/**
3196 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3197 * @vsi: the VSI being configured
3198 **/
3199static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3200{
3201 struct i40e_pf *pf = vsi->back;
3202 int i;
3203
3204 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3205 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3206 i40e_irq_dynamic_enable(vsi, i);
3207 } else {
3208 i40e_irq_dynamic_enable_icr0(pf);
3209 }
3210
1022cb6c 3211 i40e_flush(&pf->hw);
41c445ff
JB		 3212 return 0;
3213}
3214
3215/**
3216 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3217 * @pf: board private structure
3218 **/
3219static void i40e_stop_misc_vector(struct i40e_pf *pf)
3220{
3221 /* Disable ICR 0 */
3222 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3223 i40e_flush(&pf->hw);
3224}
3225
3226/**
3227 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3228 * @irq: interrupt number
3229 * @data: pointer to a q_vector
3230 *
3231 * This is the handler used for all MSI/Legacy interrupts, and deals
3232 * with both queue and non-queue interrupts. This is also used in
3233 * MSIX mode to handle the non-queue interrupts.
3234 **/
3235static irqreturn_t i40e_intr(int irq, void *data)
3236{
3237 struct i40e_pf *pf = (struct i40e_pf *)data;
3238 struct i40e_hw *hw = &pf->hw;
5e823066 3239 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3240 u32 icr0, icr0_remaining;
3241 u32 val, ena_mask;
3242
3243 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3244 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3245
116a57d4
SN		 3246 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3247 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3248 goto enable_intr;
41c445ff 3249
cd92e72f
SN		 3250 /* if interrupt but no bits showing, must be SWINT */
3251 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3252 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3253 pf->sw_int_count++;
3254
0d8e1439
ASJ		 3255 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3256 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3257 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3258 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3259 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3260 }
3261
41c445ff
JB		 3262 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3263 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3264
3265 /* temporarily disable queue cause for NAPI processing */
3266 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3267
41c445ff
JB		 3268 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3269 wr32(hw, I40E_QINT_RQCTL(0), qval);
3270
3271 qval = rd32(hw, I40E_QINT_TQCTL(0));
3272 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3273 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3274
3275 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3276 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3277 }
3278
3279 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3280 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3281 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3282 }
3283
3284 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3285 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3286 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3287 }
3288
3289 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3290 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3291 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3292 }
3293
3294 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3295 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3296 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3297 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3298 val = rd32(hw, I40E_GLGEN_RSTAT);
3299 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3300 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3301 if (val == I40E_RESET_CORER) {
41c445ff 3302 pf->corer_count++;
4eb3f768 3303 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3304 pf->globr_count++;
4eb3f768 3305 } else if (val == I40E_RESET_EMPR) {
41c445ff 3306 pf->empr_count++;
9df42d1a 3307 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3308 }
41c445ff
JB		 3309 }
3310
9c010ee0
ASJ		 3311 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3312 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3313 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3314 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3315 rd32(hw, I40E_PFHMC_ERRORINFO),
3316 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3317 }
3318
beb0dff1
JK		 3319 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3320 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3321
3322 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3323 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3324 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3325 }
beb0dff1
JK		 3326 }
3327
41c445ff
JB		 3328 /* If a critical error is pending we have no choice but to reset the
3329 * device.
3330 * Report and mask out any remaining unexpected interrupts.
3331 */
3332 icr0_remaining = icr0 & ena_mask;
3333 if (icr0_remaining) {
3334 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3335 icr0_remaining);
9c010ee0 3336 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3337 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3338 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3339 dev_info(&pf->pdev->dev, "device will be reset\n");
3340 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3341 i40e_service_event_schedule(pf);
41c445ff
JB		 3342 }
3343 ena_mask &= ~icr0_remaining;
3344 }
5e823066 3345 ret = IRQ_HANDLED;
41c445ff 3346
5e823066 3347enable_intr:
41c445ff
JB		 3348 /* re-enable interrupt causes */
3349 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3350 if (!test_bit(__I40E_DOWN, &pf->state)) {
3351 i40e_service_event_schedule(pf);
3352 i40e_irq_dynamic_enable_icr0(pf);
3353 }
3354
5e823066 3355 return ret;
41c445ff
JB		 3356}
3357
cbf61325
ASJ		 3358/**
3359 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3360 * @tx_ring: tx ring to clean
3361 * @budget: how many cleans we're allowed
3362 *
3363 * Returns true if there's any budget left (e.g. the clean is finished)
3364 **/
3365static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3366{
3367 struct i40e_vsi *vsi = tx_ring->vsi;
3368 u16 i = tx_ring->next_to_clean;
3369 struct i40e_tx_buffer *tx_buf;
3370 struct i40e_tx_desc *tx_desc;
3371
3372 tx_buf = &tx_ring->tx_bi[i];
3373 tx_desc = I40E_TX_DESC(tx_ring, i);
3374 i -= tx_ring->count;
3375
3376 do {
3377 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3378
3379 /* if next_to_watch is not set then there is no work pending */
3380 if (!eop_desc)
3381 break;
3382
3383 /* prevent any other reads prior to eop_desc */
3384 read_barrier_depends();
3385
3386 /* if the descriptor isn't done, no work yet to do */
3387 if (!(eop_desc->cmd_type_offset_bsz &
3388 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3389 break;
3390
3391 /* clear next_to_watch to prevent false hangs */
3392 tx_buf->next_to_watch = NULL;
3393
49d7d933
ASJ		 3394 tx_desc->buffer_addr = 0;
3395 tx_desc->cmd_type_offset_bsz = 0;
3396 /* move past filter desc */
3397 tx_buf++;
3398 tx_desc++;
3399 i++;
3400 if (unlikely(!i)) {
3401 i -= tx_ring->count;
3402 tx_buf = tx_ring->tx_bi;
3403 tx_desc = I40E_TX_DESC(tx_ring, 0);
3404 }
cbf61325
ASJ		 3405 /* unmap skb header data */
3406 dma_unmap_single(tx_ring->dev,
3407 dma_unmap_addr(tx_buf, dma),
3408 dma_unmap_len(tx_buf, len),
3409 DMA_TO_DEVICE);
49d7d933
ASJ		 3410 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3411 kfree(tx_buf->raw_buf);
cbf61325 3412
49d7d933
ASJ		 3413 tx_buf->raw_buf = NULL;
3414 tx_buf->tx_flags = 0;
3415 tx_buf->next_to_watch = NULL;
cbf61325 3416 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3417 tx_desc->buffer_addr = 0;
3418 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3419
49d7d933 3420 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3421 tx_buf++;
3422 tx_desc++;
3423 i++;
3424 if (unlikely(!i)) {
3425 i -= tx_ring->count;
3426 tx_buf = tx_ring->tx_bi;
3427 tx_desc = I40E_TX_DESC(tx_ring, 0);
3428 }
3429
3430 /* update budget accounting */
3431 budget--;
3432 } while (likely(budget));
3433
3434 i += tx_ring->count;
3435 tx_ring->next_to_clean = i;
3436
6995b36c 3437 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3438 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3439
cbf61325
ASJ		 3440 return budget > 0;
3441}
3442
3443/**
3444 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3445 * @irq: interrupt number
3446 * @data: pointer to a q_vector
3447 **/
3448static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3449{
3450 struct i40e_q_vector *q_vector = data;
3451 struct i40e_vsi *vsi;
3452
3453 if (!q_vector->tx.ring)
3454 return IRQ_HANDLED;
3455
3456 vsi = q_vector->tx.ring->vsi;
3457 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3458
3459 return IRQ_HANDLED;
3460}
3461
41c445ff 3462/**
cd0b6fa6 3463 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3464 * @vsi: the VSI being configured
3465 * @v_idx: vector index
cd0b6fa6 3466 * @qp_idx: queue pair index
41c445ff 3467 **/
26cdc443 3468static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3469{
493fb300 3470 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3471 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3472 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3473
3474 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3475 tx_ring->next = q_vector->tx.ring;
3476 q_vector->tx.ring = tx_ring;
41c445ff 3477 q_vector->tx.count++;
cd0b6fa6
AD		 3478
3479 rx_ring->q_vector = q_vector;
3480 rx_ring->next = q_vector->rx.ring;
3481 q_vector->rx.ring = rx_ring;
3482 q_vector->rx.count++;
41c445ff
JB		 3483}
3484
3485/**
3486 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3487 * @vsi: the VSI being configured
3488 *
3489 * This function maps descriptor rings to the queue-specific vectors
3490 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3491 * one vector per queue pair, but on a constrained vector budget, we
3492 * group the queue pairs as "efficiently" as possible.
3493 **/
3494static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3495{
3496 int qp_remaining = vsi->num_queue_pairs;
3497 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3498 int num_ringpairs;
41c445ff
JB		 3499 int v_start = 0;
3500 int qp_idx = 0;
3501
3502 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3503 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3504 * It is also important to go through all the vectors available to be
3505 * sure that if we don't use all the vectors, that the remaining vectors
3506 * are cleared. This is especially important when decreasing the
3507 * number of queues in use.
41c445ff 3508 */
70114ec4 3509 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3510 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3511
3512 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3513
3514 q_vector->num_ringpairs = num_ringpairs;
3515
3516 q_vector->rx.count = 0;
3517 q_vector->tx.count = 0;
3518 q_vector->rx.ring = NULL;
3519 q_vector->tx.ring = NULL;
3520
3521 while (num_ringpairs--) {
26cdc443 3522 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3523 qp_idx++;
3524 qp_remaining--;
41c445ff
JB		 3525 }
3526 }
3527}
3528
3529/**
3530 * i40e_vsi_request_irq - Request IRQ from the OS
3531 * @vsi: the VSI being configured
3532 * @basename: name for the vector
3533 **/
3534static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3535{
3536 struct i40e_pf *pf = vsi->back;
3537 int err;
3538
3539 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3540 err = i40e_vsi_request_irq_msix(vsi, basename);
3541 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3542 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3543 pf->int_name, pf);
41c445ff
JB		 3544 else
3545 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3546 pf->int_name, pf);
41c445ff
JB		 3547
3548 if (err)
3549 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3550
3551 return err;
3552}
3553
3554#ifdef CONFIG_NET_POLL_CONTROLLER
3555/**
3556 * i40e_netpoll - A Polling 'interrupt'handler
3557 * @netdev: network interface device structure
3558 *
3559 * This is used by netconsole to send skbs without having to re-enable
3560 * interrupts. It's not called while the normal interrupt routine is executing.
3561 **/
38e00438
VD		 3562#ifdef I40E_FCOE
3563void i40e_netpoll(struct net_device *netdev)
3564#else
41c445ff 3565static void i40e_netpoll(struct net_device *netdev)
38e00438 3566#endif
41c445ff
JB		 3567{
3568 struct i40e_netdev_priv *np = netdev_priv(netdev);
3569 struct i40e_vsi *vsi = np->vsi;
3570 struct i40e_pf *pf = vsi->back;
3571 int i;
3572
3573 /* if interface is down do nothing */
3574 if (test_bit(__I40E_DOWN, &vsi->state))
3575 return;
3576
41c445ff
JB		 3577 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3578 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3579 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3580 } else {
3581 i40e_intr(pf->pdev->irq, netdev);
3582 }
41c445ff
JB		 3583}
3584#endif
3585
23527308
NP		 3586/**
3587 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3588 * @pf: the PF being configured
3589 * @pf_q: the PF queue
3590 * @enable: enable or disable state of the queue
3591 *
3592 * This routine will wait for the given Tx queue of the PF to reach the
3593 * enabled or disabled state.
3594 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3595 * multiple retries; else will return 0 in case of success.
3596 **/
3597static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3598{
3599 int i;
3600 u32 tx_reg;
3601
3602 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3603 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3604 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3605 break;
3606
f98a2006 3607 usleep_range(10, 20);
23527308
NP		 3608 }
3609 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3610 return -ETIMEDOUT;
3611
3612 return 0;
3613}
3614
41c445ff
JB		 3615/**
3616 * i40e_vsi_control_tx - Start or stop a VSI's rings
3617 * @vsi: the VSI being configured
3618 * @enable: start or stop the rings
3619 **/
3620static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3621{
3622 struct i40e_pf *pf = vsi->back;
3623 struct i40e_hw *hw = &pf->hw;
23527308 3624 int i, j, pf_q, ret = 0;
41c445ff
JB		 3625 u32 tx_reg;
3626
3627 pf_q = vsi->base_queue;
3628 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3629
3630 /* warn the TX unit of coming changes */
3631 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3632 if (!enable)
f98a2006 3633 usleep_range(10, 20);
351499ab 3634
6c5ef620 3635 for (j = 0; j < 50; j++) {
41c445ff 3636 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3637 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3638 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3639 break;
3640 usleep_range(1000, 2000);
3641 }
fda972f6 3642 /* Skip if the queue is already in the requested state */
7c122007 3643 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3644 continue;
41c445ff
JB		 3645
3646 /* turn on/off the queue */
c5c9eb9e
SN		 3647 if (enable) {
3648 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3649 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3650 } else {
41c445ff 3651 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3652 }
41c445ff
JB		 3653
3654 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3655 /* No waiting for the Tx queue to disable */
3656 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3657 continue;
41c445ff
JB		 3658
3659 /* wait for the change to finish */
23527308
NP		 3660 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3661 if (ret) {
3662 dev_info(&pf->pdev->dev,
fb43201f
SN		 3663 "VSI seid %d Tx ring %d %sable timeout\n",
3664 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3665 break;
41c445ff
JB		 3666 }
3667 }
3668
7134f9ce
JB		 3669 if (hw->revision_id == 0)
3670 mdelay(50);
23527308
NP		 3671 return ret;
3672}
3673
3674/**
3675 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3676 * @pf: the PF being configured
3677 * @pf_q: the PF queue
3678 * @enable: enable or disable state of the queue
3679 *
3680 * This routine will wait for the given Rx queue of the PF to reach the
3681 * enabled or disabled state.
3682 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3683 * multiple retries; else will return 0 in case of success.
3684 **/
3685static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3686{
3687 int i;
3688 u32 rx_reg;
3689
3690 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3691 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3692 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3693 break;
3694
f98a2006 3695 usleep_range(10, 20);
23527308
NP		 3696 }
3697 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3698 return -ETIMEDOUT;
7134f9ce 3699
41c445ff
JB		 3700 return 0;
3701}
3702
3703/**
3704 * i40e_vsi_control_rx - Start or stop a VSI's rings
3705 * @vsi: the VSI being configured
3706 * @enable: start or stop the rings
3707 **/
3708static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3709{
3710 struct i40e_pf *pf = vsi->back;
3711 struct i40e_hw *hw = &pf->hw;
23527308 3712 int i, j, pf_q, ret = 0;
41c445ff
JB		 3713 u32 rx_reg;
3714
3715 pf_q = vsi->base_queue;
3716 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3717 for (j = 0; j < 50; j++) {
41c445ff 3718 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3719 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3720 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3721 break;
3722 usleep_range(1000, 2000);
3723 }
41c445ff 3724
7c122007
CS		 3725 /* Skip if the queue is already in the requested state */
3726 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3727 continue;
41c445ff
JB		 3728
3729 /* turn on/off the queue */
3730 if (enable)
6c5ef620 3731 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3732 else
6c5ef620 3733 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3734 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3735
3736 /* wait for the change to finish */
23527308
NP		 3737 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3738 if (ret) {
3739 dev_info(&pf->pdev->dev,
fb43201f
SN		 3740 "VSI seid %d Rx ring %d %sable timeout\n",
3741 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3742 break;
41c445ff
JB		 3743 }
3744 }
3745
23527308 3746 return ret;
41c445ff
JB		 3747}
3748
3749/**
3750 * i40e_vsi_control_rings - Start or stop a VSI's rings
3751 * @vsi: the VSI being configured
3752 * @enable: start or stop the rings
3753 **/
fc18eaa0 3754int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3755{
3b867b28 3756 int ret = 0;
41c445ff
JB		 3757
3758 /* do rx first for enable and last for disable */
3759 if (request) {
3760 ret = i40e_vsi_control_rx(vsi, request);
3761 if (ret)
3762 return ret;
3763 ret = i40e_vsi_control_tx(vsi, request);
3764 } else {
3b867b28
ASJ		 3765 /* Ignore return value, we need to shutdown whatever we can */
3766 i40e_vsi_control_tx(vsi, request);
3767 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3768 }
3769
3770 return ret;
3771}
3772
3773/**
3774 * i40e_vsi_free_irq - Free the irq association with the OS
3775 * @vsi: the VSI being configured
3776 **/
3777static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3778{
3779 struct i40e_pf *pf = vsi->back;
3780 struct i40e_hw *hw = &pf->hw;
3781 int base = vsi->base_vector;
3782 u32 val, qp;
3783 int i;
3784
3785 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3786 if (!vsi->q_vectors)
3787 return;
3788
63741846
SN		 3789 if (!vsi->irqs_ready)
3790 return;
3791
3792 vsi->irqs_ready = false;
41c445ff
JB		 3793 for (i = 0; i < vsi->num_q_vectors; i++) {
3794 u16 vector = i + base;
3795
3796 /* free only the irqs that were actually requested */
78681b1f
SN		 3797 if (!vsi->q_vectors[i] ||
3798 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3799 continue;
3800
3801 /* clear the affinity_mask in the IRQ descriptor */
3802 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3803 NULL);
3804 free_irq(pf->msix_entries[vector].vector,
493fb300 3805 vsi->q_vectors[i]);
41c445ff
JB		 3806
3807 /* Tear down the interrupt queue link list
3808 *
3809 * We know that they come in pairs and always
3810 * the Rx first, then the Tx. To clear the
3811 * link list, stick the EOL value into the
3812 * next_q field of the registers.
3813 */
3814 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3815 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3816 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3817 val |= I40E_QUEUE_END_OF_LIST
3818 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3819 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3820
3821 while (qp != I40E_QUEUE_END_OF_LIST) {
3822 u32 next;
3823
3824 val = rd32(hw, I40E_QINT_RQCTL(qp));
3825
3826 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3827 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3828 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3829 I40E_QINT_RQCTL_INTEVENT_MASK);
3830
3831 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3832 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3833
3834 wr32(hw, I40E_QINT_RQCTL(qp), val);
3835
3836 val = rd32(hw, I40E_QINT_TQCTL(qp));
3837
3838 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3839 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3840
3841 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3842 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3843 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3844 I40E_QINT_TQCTL_INTEVENT_MASK);
3845
3846 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3847 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3848
3849 wr32(hw, I40E_QINT_TQCTL(qp), val);
3850 qp = next;
3851 }
3852 }
3853 } else {
3854 free_irq(pf->pdev->irq, pf);
3855
3856 val = rd32(hw, I40E_PFINT_LNKLST0);
3857 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3858 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3859 val |= I40E_QUEUE_END_OF_LIST
3860 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3861 wr32(hw, I40E_PFINT_LNKLST0, val);
3862
3863 val = rd32(hw, I40E_QINT_RQCTL(qp));
3864 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3865 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3866 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3867 I40E_QINT_RQCTL_INTEVENT_MASK);
3868
3869 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3870 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3871
3872 wr32(hw, I40E_QINT_RQCTL(qp), val);
3873
3874 val = rd32(hw, I40E_QINT_TQCTL(qp));
3875
3876 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3877 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3878 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3879 I40E_QINT_TQCTL_INTEVENT_MASK);
3880
3881 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3882 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3883
3884 wr32(hw, I40E_QINT_TQCTL(qp), val);
3885 }
3886}
3887
493fb300
AD		 3888/**
3889 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3890 * @vsi: the VSI being configured
3891 * @v_idx: Index of vector to be freed
3892 *
3893 * This function frees the memory allocated to the q_vector. In addition if
3894 * NAPI is enabled it will delete any references to the NAPI struct prior
3895 * to freeing the q_vector.
3896 **/
3897static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3898{
3899 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3900 struct i40e_ring *ring;
493fb300
AD		 3901
3902 if (!q_vector)
3903 return;
3904
3905 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3906 i40e_for_each_ring(ring, q_vector->tx)
3907 ring->q_vector = NULL;
3908
3909 i40e_for_each_ring(ring, q_vector->rx)
3910 ring->q_vector = NULL;
493fb300
AD		 3911
3912 /* only VSI w/ an associated netdev is set up w/ NAPI */
3913 if (vsi->netdev)
3914 netif_napi_del(&q_vector->napi);
3915
3916 vsi->q_vectors[v_idx] = NULL;
3917
3918 kfree_rcu(q_vector, rcu);
3919}
3920
41c445ff
JB		 3921/**
3922 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3923 * @vsi: the VSI being un-configured
3924 *
3925 * This frees the memory allocated to the q_vectors and
3926 * deletes references to the NAPI struct.
3927 **/
3928static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3929{
3930 int v_idx;
3931
493fb300
AD		 3932 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3933 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3934}
3935
3936/**
3937 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3938 * @pf: board private structure
3939 **/
3940static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3941{
3942 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3943 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3944 pci_disable_msix(pf->pdev);
3945 kfree(pf->msix_entries);
3946 pf->msix_entries = NULL;
3b444399
SN		 3947 kfree(pf->irq_pile);
3948 pf->irq_pile = NULL;
41c445ff
JB		 3949 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3950 pci_disable_msi(pf->pdev);
3951 }
3952 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3953}
3954
3955/**
3956 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3957 * @pf: board private structure
3958 *
3959 * We go through and clear interrupt specific resources and reset the structure
3960 * to pre-load conditions
3961 **/
3962static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3963{
3964 int i;
3965
e147758d
SN		 3966 i40e_stop_misc_vector(pf);
3967 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3968 synchronize_irq(pf->msix_entries[0].vector);
3969 free_irq(pf->msix_entries[0].vector, pf);
3970 }
3971
41c445ff 3972 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3973 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3974 if (pf->vsi[i])
3975 i40e_vsi_free_q_vectors(pf->vsi[i]);
3976 i40e_reset_interrupt_capability(pf);
3977}
3978
3979/**
3980 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3981 * @vsi: the VSI being configured
3982 **/
3983static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3984{
3985 int q_idx;
3986
3987 if (!vsi->netdev)
3988 return;
3989
3990 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3991 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3992}
3993
3994/**
3995 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3996 * @vsi: the VSI being configured
3997 **/
3998static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3999{
4000 int q_idx;
4001
4002 if (!vsi->netdev)
4003 return;
4004
4005 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4006 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4007}
4008
90ef8d47
SN		 4009/**
4010 * i40e_vsi_close - Shut down a VSI
4011 * @vsi: the vsi to be quelled
4012 **/
4013static void i40e_vsi_close(struct i40e_vsi *vsi)
4014{
4015 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4016 i40e_down(vsi);
4017 i40e_vsi_free_irq(vsi);
4018 i40e_vsi_free_tx_resources(vsi);
4019 i40e_vsi_free_rx_resources(vsi);
92faef85 4020 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4021}
4022
41c445ff
JB		 4023/**
4024 * i40e_quiesce_vsi - Pause a given VSI
4025 * @vsi: the VSI being paused
4026 **/
4027static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4028{
4029 if (test_bit(__I40E_DOWN, &vsi->state))
4030 return;
4031
d341b7a5
NP		 4032 /* No need to disable FCoE VSI when Tx suspended */
4033 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4034 vsi->type == I40E_VSI_FCOE) {
4035 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4036 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4037 return;
4038 }
4039
41c445ff 4040 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4041 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4042 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4043 else
90ef8d47 4044 i40e_vsi_close(vsi);
41c445ff
JB		 4045}
4046
4047/**
4048 * i40e_unquiesce_vsi - Resume a given VSI
4049 * @vsi: the VSI being resumed
4050 **/
4051static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4052{
4053 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4054 return;
4055
4056 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4057 if (vsi->netdev && netif_running(vsi->netdev))
4058 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4059 else
8276f757 4060 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4061}
4062
4063/**
4064 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4065 * @pf: the PF
4066 **/
4067static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4068{
4069 int v;
4070
505682cd 4071 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4072 if (pf->vsi[v])
4073 i40e_quiesce_vsi(pf->vsi[v]);
4074 }
4075}
4076
4077/**
4078 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4079 * @pf: the PF
4080 **/
4081static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4082{
4083 int v;
4084
505682cd 4085 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4086 if (pf->vsi[v])
4087 i40e_unquiesce_vsi(pf->vsi[v]);
4088 }
4089}
4090
69129dc3
NP		 4091#ifdef CONFIG_I40E_DCB
4092/**
4093 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4094 * @vsi: the VSI being configured
4095 *
4096 * This function waits for the given VSI's Tx queues to be disabled.
4097 **/
4098static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4099{
4100 struct i40e_pf *pf = vsi->back;
4101 int i, pf_q, ret;
4102
4103 pf_q = vsi->base_queue;
4104 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4105 /* Check and wait for the disable status of the queue */
4106 ret = i40e_pf_txq_wait(pf, pf_q, false);
4107 if (ret) {
4108 dev_info(&pf->pdev->dev,
fb43201f
SN		 4109 "VSI seid %d Tx ring %d disable timeout\n",
4110 vsi->seid, pf_q);
69129dc3
NP		 4111 return ret;
4112 }
4113 }
4114
4115 return 0;
4116}
4117
4118/**
4119 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4120 * @pf: the PF
4121 *
4122 * This function waits for the Tx queues to be in disabled state for all the
4123 * VSIs that are managed by this PF.
4124 **/
4125static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4126{
4127 int v, ret = 0;
4128
4129 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4130 /* No need to wait for FCoE VSI queues */
4131 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4132 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4133 if (ret)
4134 break;
4135 }
4136 }
4137
4138 return ret;
4139}
4140
4141#endif
b03a8c1f
KP		 4142
4143/**
4144 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4145 * @q_idx: TX queue number
4146 * @vsi: Pointer to VSI struct
4147 *
4148 * This function checks specified queue for given VSI. Detects hung condition.
4149 * Sets hung bit since it is two step process. Before next run of service task
4150 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4151 * hung condition remain unchanged and during subsequent run, this function
4152 * issues SW interrupt to recover from hung condition.
4153 **/
4154static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4155{
4156 struct i40e_ring *tx_ring = NULL;
4157 struct i40e_pf *pf;
4158 u32 head, val, tx_pending;
4159 int i;
4160
4161 pf = vsi->back;
4162
4163 /* now that we have an index, find the tx_ring struct */
4164 for (i = 0; i < vsi->num_queue_pairs; i++) {
4165 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4166 if (q_idx == vsi->tx_rings[i]->queue_index) {
4167 tx_ring = vsi->tx_rings[i];
4168 break;
4169 }
4170 }
4171 }
4172
4173 if (!tx_ring)
4174 return;
4175
4176 /* Read interrupt register */
4177 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4178 val = rd32(&pf->hw,
4179 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4180 tx_ring->vsi->base_vector - 1));
4181 else
4182 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4183
4184 head = i40e_get_head(tx_ring);
4185
4186 tx_pending = i40e_get_tx_pending(tx_ring);
4187
4188 /* Interrupts are disabled and TX pending is non-zero,
4189 * trigger the SW interrupt (don't wait). Worst case
4190 * there will be one extra interrupt which may result
4191 * into not cleaning any queues because queues are cleaned.
4192 */
4193 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4194 i40e_force_wb(vsi, tx_ring->q_vector);
4195}
4196
4197/**
4198 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4199 * @pf: pointer to PF struct
4200 *
4201 * LAN VSI has netdev and netdev has TX queues. This function is to check
4202 * each of those TX queues if they are hung, trigger recovery by issuing
4203 * SW interrupt.
4204 **/
4205static void i40e_detect_recover_hung(struct i40e_pf *pf)
4206{
4207 struct net_device *netdev;
4208 struct i40e_vsi *vsi;
4209 int i;
4210
4211 /* Only for LAN VSI */
4212 vsi = pf->vsi[pf->lan_vsi];
4213
4214 if (!vsi)
4215 return;
4216
4217 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4218 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4219 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4220 return;
4221
4222 /* Make sure type is MAIN VSI */
4223 if (vsi->type != I40E_VSI_MAIN)
4224 return;
4225
4226 netdev = vsi->netdev;
4227 if (!netdev)
4228 return;
4229
4230 /* Bail out if netif_carrier is not OK */
4231 if (!netif_carrier_ok(netdev))
4232 return;
4233
4234 /* Go thru' TX queues for netdev */
4235 for (i = 0; i < netdev->num_tx_queues; i++) {
4236 struct netdev_queue *q;
4237
4238 q = netdev_get_tx_queue(netdev, i);
4239 if (q)
4240 i40e_detect_recover_hung_queue(i, vsi);
4241 }
4242}
4243
63d7e5a4
NP		 4244/**
4245 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4246 * @pf: pointer to PF
63d7e5a4
NP		 4247 *
4248 * Get TC map for ISCSI PF type that will include iSCSI TC
4249 * and LAN TC.
4250 **/
4251static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4252{
4253 struct i40e_dcb_app_priority_table app;
4254 struct i40e_hw *hw = &pf->hw;
4255 u8 enabled_tc = 1; /* TC0 is always enabled */
4256 u8 tc, i;
4257 /* Get the iSCSI APP TLV */
4258 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4259
4260 for (i = 0; i < dcbcfg->numapps; i++) {
4261 app = dcbcfg->app[i];
4262 if (app.selector == I40E_APP_SEL_TCPIP &&
4263 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4264 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4265 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4266 break;
4267 }
4268 }
4269
4270 return enabled_tc;
4271}
4272
41c445ff
JB		 4273/**
4274 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4275 * @dcbcfg: the corresponding DCBx configuration structure
4276 *
4277 * Return the number of TCs from given DCBx configuration
4278 **/
4279static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4280{
078b5876
JB		 4281 u8 num_tc = 0;
4282 int i;
41c445ff
JB		 4283
4284 /* Scan the ETS Config Priority Table to find
4285 * traffic class enabled for a given priority
4286 * and use the traffic class index to get the
4287 * number of traffic classes enabled
4288 */
4289 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4290 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4291 num_tc = dcbcfg->etscfg.prioritytable[i];
4292 }
4293
4294 /* Traffic class index starts from zero so
4295 * increment to return the actual count
4296 */
078b5876 4297 return num_tc + 1;
41c445ff
JB		 4298}
4299
4300/**
4301 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4302 * @dcbcfg: the corresponding DCBx configuration structure
4303 *
4304 * Query the current DCB configuration and return the number of
4305 * traffic classes enabled from the given DCBX config
4306 **/
4307static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4308{
4309 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4310 u8 enabled_tc = 1;
4311 u8 i;
4312
4313 for (i = 0; i < num_tc; i++)
41a1d04b 4314 enabled_tc |= BIT(i);
41c445ff
JB		 4315
4316 return enabled_tc;
4317}
4318
4319/**
4320 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4321 * @pf: PF being queried
4322 *
4323 * Return number of traffic classes enabled for the given PF
4324 **/
4325static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4326{
4327 struct i40e_hw *hw = &pf->hw;
4328 u8 i, enabled_tc;
4329 u8 num_tc = 0;
4330 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4331
4332 /* If DCB is not enabled then always in single TC */
4333 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4334 return 1;
4335
63d7e5a4
NP		 4336 /* SFP mode will be enabled for all TCs on port */
4337 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4338 return i40e_dcb_get_num_tc(dcbcfg);
4339
41c445ff 4340 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4341 if (pf->hw.func_caps.iscsi)
4342 enabled_tc = i40e_get_iscsi_tc_map(pf);
4343 else
fc51de96 4344 return 1; /* Only TC0 */
41c445ff 4345
63d7e5a4
NP		 4346 /* At least have TC0 */
4347 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4348 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4349 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4350 num_tc++;
4351 }
4352 return num_tc;
41c445ff
JB		 4353}
4354
4355/**
4356 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4357 * @pf: PF being queried
4358 *
4359 * Return a bitmap for first enabled traffic class for this PF.
4360 **/
4361static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4362{
4363 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4364 u8 i = 0;
4365
4366 if (!enabled_tc)
4367 return 0x1; /* TC0 */
4368
4369 /* Find the first enabled TC */
4370 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4371 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4372 break;
4373 }
4374
41a1d04b 4375 return BIT(i);
41c445ff
JB		 4376}
4377
4378/**
4379 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4380 * @pf: PF being queried
4381 *
4382 * Return a bitmap for enabled traffic classes for this PF.
4383 **/
4384static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4385{
4386 /* If DCB is not enabled for this PF then just return default TC */
4387 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4388 return i40e_pf_get_default_tc(pf);
4389
41c445ff 4390 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4391 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4392 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4393
fc51de96 4394 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4395 if (pf->hw.func_caps.iscsi)
4396 return i40e_get_iscsi_tc_map(pf);
4397 else
fc51de96 4398 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4399}
4400
4401/**
4402 * i40e_vsi_get_bw_info - Query VSI BW Information
4403 * @vsi: the VSI being queried
4404 *
4405 * Returns 0 on success, negative value on failure
4406 **/
4407static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4408{
4409 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4410 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4411 struct i40e_pf *pf = vsi->back;
4412 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4413 i40e_status ret;
41c445ff 4414 u32 tc_bw_max;
41c445ff
JB		 4415 int i;
4416
4417 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4418 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4419 if (ret) {
41c445ff 4420 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4421 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4422 i40e_stat_str(&pf->hw, ret),
4423 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4424 return -EINVAL;
41c445ff
JB		 4425 }
4426
4427 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4428 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4429 NULL);
4430 if (ret) {
41c445ff 4431 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4432 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4433 i40e_stat_str(&pf->hw, ret),
4434 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4435 return -EINVAL;
41c445ff
JB		 4436 }
4437
4438 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4439 dev_info(&pf->pdev->dev,
4440 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4441 bw_config.tc_valid_bits,
4442 bw_ets_config.tc_valid_bits);
4443 /* Still continuing */
4444 }
4445
4446 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4447 vsi->bw_max_quanta = bw_config.max_bw;
4448 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4449 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4450 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4451 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4452 vsi->bw_ets_limit_credits[i] =
4453 le16_to_cpu(bw_ets_config.credits[i]);
4454 /* 3 bits out of 4 for each TC */
4455 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4456 }
078b5876 4457
dcae29be 4458 return 0;
41c445ff
JB		 4459}
4460
4461/**
4462 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4463 * @vsi: the VSI being configured
4464 * @enabled_tc: TC bitmap
4465 * @bw_credits: BW shared credits per TC
4466 *
4467 * Returns 0 on success, negative value on failure
4468 **/
dcae29be 4469static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4470 u8 *bw_share)
4471{
4472 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4473 i40e_status ret;
dcae29be 4474 int i;
41c445ff
JB		 4475
4476 bw_data.tc_valid_bits = enabled_tc;
4477 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4478 bw_data.tc_bw_credits[i] = bw_share[i];
4479
f1c7e72e
SN		 4480 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4481 NULL);
4482 if (ret) {
41c445ff 4483 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4484 "AQ command Config VSI BW allocation per TC failed = %d\n",
4485 vsi->back->hw.aq.asq_last_status);
dcae29be 4486 return -EINVAL;
41c445ff
JB		 4487 }
4488
4489 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4490 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4491
dcae29be 4492 return 0;
41c445ff
JB		 4493}
4494
4495/**
4496 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4497 * @vsi: the VSI being configured
4498 * @enabled_tc: TC map to be enabled
4499 *
4500 **/
4501static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4502{
4503 struct net_device *netdev = vsi->netdev;
4504 struct i40e_pf *pf = vsi->back;
4505 struct i40e_hw *hw = &pf->hw;
4506 u8 netdev_tc = 0;
4507 int i;
4508 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4509
4510 if (!netdev)
4511 return;
4512
4513 if (!enabled_tc) {
4514 netdev_reset_tc(netdev);
4515 return;
4516 }
4517
4518 /* Set up actual enabled TCs on the VSI */
4519 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4520 return;
4521
4522 /* set per TC queues for the VSI */
4523 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4524 /* Only set TC queues for enabled tcs
4525 *
4526 * e.g. For a VSI that has TC0 and TC3 enabled the
4527 * enabled_tc bitmap would be 0x00001001; the driver
4528 * will set the numtc for netdev as 2 that will be
4529 * referenced by the netdev layer as TC 0 and 1.
4530 */
41a1d04b 4531 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4532 netdev_set_tc_queue(netdev,
4533 vsi->tc_config.tc_info[i].netdev_tc,
4534 vsi->tc_config.tc_info[i].qcount,
4535 vsi->tc_config.tc_info[i].qoffset);
4536 }
4537
4538 /* Assign UP2TC map for the VSI */
4539 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4540 /* Get the actual TC# for the UP */
4541 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4542 /* Get the mapped netdev TC# for the UP */
4543 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4544 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4545 }
4546}
4547
4548/**
4549 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4550 * @vsi: the VSI being configured
4551 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4552 **/
4553static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4554 struct i40e_vsi_context *ctxt)
4555{
4556 /* copy just the sections touched not the entire info
4557 * since not all sections are valid as returned by
4558 * update vsi params
4559 */
4560 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4561 memcpy(&vsi->info.queue_mapping,
4562 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4563 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4564 sizeof(vsi->info.tc_mapping));
4565}
4566
4567/**
4568 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4569 * @vsi: VSI to be configured
4570 * @enabled_tc: TC bitmap
4571 *
4572 * This configures a particular VSI for TCs that are mapped to the
4573 * given TC bitmap. It uses default bandwidth share for TCs across
4574 * VSIs to configure TC for a particular VSI.
4575 *
4576 * NOTE:
4577 * It is expected that the VSI queues have been quisced before calling
4578 * this function.
4579 **/
4580static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4581{
4582 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4583 struct i40e_vsi_context ctxt;
4584 int ret = 0;
4585 int i;
4586
4587 /* Check if enabled_tc is same as existing or new TCs */
4588 if (vsi->tc_config.enabled_tc == enabled_tc)
4589 return ret;
4590
4591 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4592 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4593 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4594 bw_share[i] = 1;
4595 }
4596
4597 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4598 if (ret) {
4599 dev_info(&vsi->back->pdev->dev,
4600 "Failed configuring TC map %d for VSI %d\n",
4601 enabled_tc, vsi->seid);
4602 goto out;
4603 }
4604
4605 /* Update Queue Pairs Mapping for currently enabled UPs */
4606 ctxt.seid = vsi->seid;
4607 ctxt.pf_num = vsi->back->hw.pf_id;
4608 ctxt.vf_num = 0;
4609 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4610 ctxt.info = vsi->info;
41c445ff
JB		 4611 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4612
4613 /* Update the VSI after updating the VSI queue-mapping information */
4614 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4615 if (ret) {
4616 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4617 "Update vsi tc config failed, err %s aq_err %s\n",
4618 i40e_stat_str(&vsi->back->hw, ret),
4619 i40e_aq_str(&vsi->back->hw,
4620 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4621 goto out;
4622 }
4623 /* update the local VSI info with updated queue map */
4624 i40e_vsi_update_queue_map(vsi, &ctxt);
4625 vsi->info.valid_sections = 0;
4626
4627 /* Update current VSI BW information */
4628 ret = i40e_vsi_get_bw_info(vsi);
4629 if (ret) {
4630 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4631 "Failed updating vsi bw info, err %s aq_err %s\n",
4632 i40e_stat_str(&vsi->back->hw, ret),
4633 i40e_aq_str(&vsi->back->hw,
4634 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4635 goto out;
4636 }
4637
4638 /* Update the netdev TC setup */
4639 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4640out:
4641 return ret;
4642}
4643
4e3b35b0
NP		 4644/**
4645 * i40e_veb_config_tc - Configure TCs for given VEB
4646 * @veb: given VEB
4647 * @enabled_tc: TC bitmap
4648 *
4649 * Configures given TC bitmap for VEB (switching) element
4650 **/
4651int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4652{
4653 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4654 struct i40e_pf *pf = veb->pf;
4655 int ret = 0;
4656 int i;
4657
4658 /* No TCs or already enabled TCs just return */
4659 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4660 return ret;
4661
4662 bw_data.tc_valid_bits = enabled_tc;
4663 /* bw_data.absolute_credits is not set (relative) */
4664
4665 /* Enable ETS TCs with equal BW Share for now */
4666 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4667 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4668 bw_data.tc_bw_share_credits[i] = 1;
4669 }
4670
4671 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4672 &bw_data, NULL);
4673 if (ret) {
4674 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4675 "VEB bw config failed, err %s aq_err %s\n",
4676 i40e_stat_str(&pf->hw, ret),
4677 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4678 goto out;
4679 }
4680
4681 /* Update the BW information */
4682 ret = i40e_veb_get_bw_info(veb);
4683 if (ret) {
4684 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4685 "Failed getting veb bw config, err %s aq_err %s\n",
4686 i40e_stat_str(&pf->hw, ret),
4687 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4688 }
4689
4690out:
4691 return ret;
4692}
4693
4694#ifdef CONFIG_I40E_DCB
4695/**
4696 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4697 * @pf: PF struct
4698 *
4699 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4700 * the caller would've quiesce all the VSIs before calling
4701 * this function
4702 **/
4703static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4704{
4705 u8 tc_map = 0;
4706 int ret;
4707 u8 v;
4708
4709 /* Enable the TCs available on PF to all VEBs */
4710 tc_map = i40e_pf_get_tc_map(pf);
4711 for (v = 0; v < I40E_MAX_VEB; v++) {
4712 if (!pf->veb[v])
4713 continue;
4714 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4715 if (ret) {
4716 dev_info(&pf->pdev->dev,
4717 "Failed configuring TC for VEB seid=%d\n",
4718 pf->veb[v]->seid);
4719 /* Will try to configure as many components */
4720 }
4721 }
4722
4723 /* Update each VSI */
505682cd 4724 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4725 if (!pf->vsi[v])
4726 continue;
4727
4728 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4729#ifdef I40E_FCOE
4730 * - For FCoE VSI only enable the TC configured
4731 * as per the APP TLV
4732#endif
4e3b35b0
NP		 4733 * - For all others keep them at TC0 for now
4734 */
4735 if (v == pf->lan_vsi)
4736 tc_map = i40e_pf_get_tc_map(pf);
4737 else
4738 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4739#ifdef I40E_FCOE
4740 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4741 tc_map = i40e_get_fcoe_tc_map(pf);
4742#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4743
4744 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4745 if (ret) {
4746 dev_info(&pf->pdev->dev,
4747 "Failed configuring TC for VSI seid=%d\n",
4748 pf->vsi[v]->seid);
4749 /* Will try to configure as many components */
4750 } else {
0672a091
NP		 4751 /* Re-configure VSI vectors based on updated TC map */
4752 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4753 if (pf->vsi[v]->netdev)
4754 i40e_dcbnl_set_all(pf->vsi[v]);
4755 }
4756 }
4757}
4758
2fd75f31
NP		 4759/**
4760 * i40e_resume_port_tx - Resume port Tx
4761 * @pf: PF struct
4762 *
4763 * Resume a port's Tx and issue a PF reset in case of failure to
4764 * resume.
4765 **/
4766static int i40e_resume_port_tx(struct i40e_pf *pf)
4767{
4768 struct i40e_hw *hw = &pf->hw;
4769 int ret;
4770
4771 ret = i40e_aq_resume_port_tx(hw, NULL);
4772 if (ret) {
4773 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4774 "Resume Port Tx failed, err %s aq_err %s\n",
4775 i40e_stat_str(&pf->hw, ret),
4776 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4777 /* Schedule PF reset to recover */
4778 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4779 i40e_service_event_schedule(pf);
4780 }
4781
4782 return ret;
4783}
4784
4e3b35b0
NP		 4785/**
4786 * i40e_init_pf_dcb - Initialize DCB configuration
4787 * @pf: PF being configured
4788 *
4789 * Query the current DCB configuration and cache it
4790 * in the hardware structure
4791 **/
4792static int i40e_init_pf_dcb(struct i40e_pf *pf)
4793{
4794 struct i40e_hw *hw = &pf->hw;
4795 int err = 0;
4796
025b4a54
ASJ		 4797 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4798 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4799 (pf->hw.aq.fw_maj_ver < 4))
4800 goto out;
4801
4e3b35b0
NP		 4802 /* Get the initial DCB configuration */
4803 err = i40e_init_dcb(hw);
4804 if (!err) {
4805 /* Device/Function is not DCBX capable */
4806 if ((!hw->func_caps.dcb) ||
4807 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4808 dev_info(&pf->pdev->dev,
4809 "DCBX offload is not supported or is disabled for this PF.\n");
4810
4811 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4812 goto out;
4813
4814 } else {
4815 /* When status is not DISABLED then DCBX in FW */
4816 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4817 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4818
4819 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4820 /* Enable DCB tagging only when more than one TC */
4821 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4822 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4823 dev_dbg(&pf->pdev->dev,
4824 "DCBX offload is supported for this PF.\n");
4e3b35b0 4825 }
014269ff 4826 } else {
aebfc816 4827 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4828 "Query for DCB configuration failed, err %s aq_err %s\n",
4829 i40e_stat_str(&pf->hw, err),
4830 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4831 }
4832
4833out:
4834 return err;
4835}
4836#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4837#define SPEED_SIZE 14
4838#define FC_SIZE 8
4839/**
4840 * i40e_print_link_message - print link up or down
4841 * @vsi: the VSI for which link needs a message
4842 */
c156f856 4843void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 4844{
a9165490
SN		 4845 char *speed = "Unknown";
4846 char *fc = "Unknown";
cf05ed08 4847
c156f856
MJ		 4848 if (vsi->current_isup == isup)
4849 return;
4850 vsi->current_isup = isup;
cf05ed08
JB		 4851 if (!isup) {
4852 netdev_info(vsi->netdev, "NIC Link is Down\n");
4853 return;
4854 }
4855
148c2d80
GR		 4856 /* Warn user if link speed on NPAR enabled partition is not at
4857 * least 10GB
4858 */
4859 if (vsi->back->hw.func_caps.npar_enable &&
4860 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4861 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4862 netdev_warn(vsi->netdev,
4863 "The partition detected link speed that is less than 10Gbps\n");
4864
cf05ed08
JB		 4865 switch (vsi->back->hw.phy.link_info.link_speed) {
4866 case I40E_LINK_SPEED_40GB:
a9165490 4867 speed = "40 G";
cf05ed08 4868 break;
ae24b409 4869 case I40E_LINK_SPEED_20GB:
a9165490 4870 speed = "20 G";
ae24b409 4871 break;
cf05ed08 4872 case I40E_LINK_SPEED_10GB:
a9165490 4873 speed = "10 G";
cf05ed08
JB		 4874 break;
4875 case I40E_LINK_SPEED_1GB:
a9165490 4876 speed = "1000 M";
cf05ed08 4877 break;
5960d33f 4878 case I40E_LINK_SPEED_100MB:
a9165490 4879 speed = "100 M";
5960d33f 4880 break;
cf05ed08
JB		 4881 default:
4882 break;
4883 }
4884
4885 switch (vsi->back->hw.fc.current_mode) {
4886 case I40E_FC_FULL:
a9165490 4887 fc = "RX/TX";
cf05ed08
JB		 4888 break;
4889 case I40E_FC_TX_PAUSE:
a9165490 4890 fc = "TX";
cf05ed08
JB		 4891 break;
4892 case I40E_FC_RX_PAUSE:
a9165490 4893 fc = "RX";
cf05ed08
JB		 4894 break;
4895 default:
a9165490 4896 fc = "None";
cf05ed08
JB		 4897 break;
4898 }
4899
a9165490 4900 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 4901 speed, fc);
4902}
4e3b35b0 4903
41c445ff
JB		 4904/**
4905 * i40e_up_complete - Finish the last steps of bringing up a connection
4906 * @vsi: the VSI being configured
4907 **/
4908static int i40e_up_complete(struct i40e_vsi *vsi)
4909{
4910 struct i40e_pf *pf = vsi->back;
4911 int err;
4912
4913 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4914 i40e_vsi_configure_msix(vsi);
4915 else
4916 i40e_configure_msi_and_legacy(vsi);
4917
4918 /* start rings */
4919 err = i40e_vsi_control_rings(vsi, true);
4920 if (err)
4921 return err;
4922
4923 clear_bit(__I40E_DOWN, &vsi->state);
4924 i40e_napi_enable_all(vsi);
4925 i40e_vsi_enable_irq(vsi);
4926
4927 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4928 (vsi->netdev)) {
cf05ed08 4929 i40e_print_link_message(vsi, true);
41c445ff
JB		 4930 netif_tx_start_all_queues(vsi->netdev);
4931 netif_carrier_on(vsi->netdev);
6d779b41 4932 } else if (vsi->netdev) {
cf05ed08 4933 i40e_print_link_message(vsi, false);
7b592f61
CW		 4934 /* need to check for qualified module here*/
4935 if ((pf->hw.phy.link_info.link_info &
4936 I40E_AQ_MEDIA_AVAILABLE) &&
4937 (!(pf->hw.phy.link_info.an_info &
4938 I40E_AQ_QUALIFIED_MODULE)))
4939 netdev_err(vsi->netdev,
4940 "the driver failed to link because an unqualified module was detected.");
41c445ff 4941 }
ca64fa4e
ASJ		 4942
4943 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4944 if (vsi->type == I40E_VSI_FDIR) {
4945 /* reset fd counters */
4946 pf->fd_add_err = pf->fd_atr_cnt = 0;
4947 if (pf->fd_tcp_rule > 0) {
4948 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4949 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4950 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4951 pf->fd_tcp_rule = 0;
4952 }
ca64fa4e 4953 i40e_fdir_filter_restore(vsi);
1e1be8f6 4954 }
41c445ff
JB		 4955 i40e_service_event_schedule(pf);
4956
4957 return 0;
4958}
4959
4960/**
4961 * i40e_vsi_reinit_locked - Reset the VSI
4962 * @vsi: the VSI being configured
4963 *
4964 * Rebuild the ring structs after some configuration
4965 * has changed, e.g. MTU size.
4966 **/
4967static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4968{
4969 struct i40e_pf *pf = vsi->back;
4970
4971 WARN_ON(in_interrupt());
4972 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4973 usleep_range(1000, 2000);
4974 i40e_down(vsi);
4975
4976 /* Give a VF some time to respond to the reset. The
4977 * two second wait is based upon the watchdog cycle in
4978 * the VF driver.
4979 */
4980 if (vsi->type == I40E_VSI_SRIOV)
4981 msleep(2000);
4982 i40e_up(vsi);
4983 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4984}
4985
4986/**
4987 * i40e_up - Bring the connection back up after being down
4988 * @vsi: the VSI being configured
4989 **/
4990int i40e_up(struct i40e_vsi *vsi)
4991{
4992 int err;
4993
4994 err = i40e_vsi_configure(vsi);
4995 if (!err)
4996 err = i40e_up_complete(vsi);
4997
4998 return err;
4999}
5000
5001/**
5002 * i40e_down - Shutdown the connection processing
5003 * @vsi: the VSI being stopped
5004 **/
5005void i40e_down(struct i40e_vsi *vsi)
5006{
5007 int i;
5008
5009 /* It is assumed that the caller of this function
5010 * sets the vsi->state __I40E_DOWN bit.
5011 */
5012 if (vsi->netdev) {
5013 netif_carrier_off(vsi->netdev);
5014 netif_tx_disable(vsi->netdev);
5015 }
5016 i40e_vsi_disable_irq(vsi);
5017 i40e_vsi_control_rings(vsi, false);
5018 i40e_napi_disable_all(vsi);
5019
5020 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5021 i40e_clean_tx_ring(vsi->tx_rings[i]);
5022 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5023 }
5024}
5025
5026/**
5027 * i40e_setup_tc - configure multiple traffic classes
5028 * @netdev: net device to configure
5029 * @tc: number of traffic classes to enable
5030 **/
38e00438
VD		 5031#ifdef I40E_FCOE
5032int i40e_setup_tc(struct net_device *netdev, u8 tc)
5033#else
41c445ff 5034static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5035#endif
41c445ff
JB		 5036{
5037 struct i40e_netdev_priv *np = netdev_priv(netdev);
5038 struct i40e_vsi *vsi = np->vsi;
5039 struct i40e_pf *pf = vsi->back;
5040 u8 enabled_tc = 0;
5041 int ret = -EINVAL;
5042 int i;
5043
5044 /* Check if DCB enabled to continue */
5045 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5046 netdev_info(netdev, "DCB is not enabled for adapter\n");
5047 goto exit;
5048 }
5049
5050 /* Check if MFP enabled */
5051 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5052 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5053 goto exit;
5054 }
5055
5056 /* Check whether tc count is within enabled limit */
5057 if (tc > i40e_pf_get_num_tc(pf)) {
5058 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5059 goto exit;
5060 }
5061
5062 /* Generate TC map for number of tc requested */
5063 for (i = 0; i < tc; i++)
41a1d04b 5064 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5065
5066 /* Requesting same TC configuration as already enabled */
5067 if (enabled_tc == vsi->tc_config.enabled_tc)
5068 return 0;
5069
5070 /* Quiesce VSI queues */
5071 i40e_quiesce_vsi(vsi);
5072
5073 /* Configure VSI for enabled TCs */
5074 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5075 if (ret) {
5076 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5077 vsi->seid);
5078 goto exit;
5079 }
5080
5081 /* Unquiesce VSI */
5082 i40e_unquiesce_vsi(vsi);
5083
5084exit:
5085 return ret;
5086}
5087
5088/**
5089 * i40e_open - Called when a network interface is made active
5090 * @netdev: network interface device structure
5091 *
5092 * The open entry point is called when a network interface is made
5093 * active by the system (IFF_UP). At this point all resources needed
5094 * for transmit and receive operations are allocated, the interrupt
5095 * handler is registered with the OS, the netdev watchdog subtask is
5096 * enabled, and the stack is notified that the interface is ready.
5097 *
5098 * Returns 0 on success, negative value on failure
5099 **/
38e00438 5100int i40e_open(struct net_device *netdev)
41c445ff
JB		 5101{
5102 struct i40e_netdev_priv *np = netdev_priv(netdev);
5103 struct i40e_vsi *vsi = np->vsi;
5104 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5105 int err;
5106
4eb3f768
SN		 5107 /* disallow open during test or if eeprom is broken */
5108 if (test_bit(__I40E_TESTING, &pf->state) ||
5109 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5110 return -EBUSY;
5111
5112 netif_carrier_off(netdev);
5113
6c167f58
EK		 5114 err = i40e_vsi_open(vsi);
5115 if (err)
5116 return err;
5117
059dab69
JB		 5118 /* configure global TSO hardware offload settings */
5119 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5120 TCP_FLAG_FIN) >> 16);
5121 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5122 TCP_FLAG_FIN |
5123 TCP_FLAG_CWR) >> 16);
5124 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5125
6c167f58
EK		 5126#ifdef CONFIG_I40E_VXLAN
5127 vxlan_get_rx_port(netdev);
5128#endif
5129
5130 return 0;
5131}
5132
5133/**
5134 * i40e_vsi_open -
5135 * @vsi: the VSI to open
5136 *
5137 * Finish initialization of the VSI.
5138 *
5139 * Returns 0 on success, negative value on failure
5140 **/
5141int i40e_vsi_open(struct i40e_vsi *vsi)
5142{
5143 struct i40e_pf *pf = vsi->back;
b294ac70 5144 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5145 int err;
5146
41c445ff
JB		 5147 /* allocate descriptors */
5148 err = i40e_vsi_setup_tx_resources(vsi);
5149 if (err)
5150 goto err_setup_tx;
5151 err = i40e_vsi_setup_rx_resources(vsi);
5152 if (err)
5153 goto err_setup_rx;
5154
5155 err = i40e_vsi_configure(vsi);
5156 if (err)
5157 goto err_setup_rx;
5158
c22e3c6c
SN		 5159 if (vsi->netdev) {
5160 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5161 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5162 err = i40e_vsi_request_irq(vsi, int_name);
5163 if (err)
5164 goto err_setup_rx;
41c445ff 5165
c22e3c6c
SN		 5166 /* Notify the stack of the actual queue counts. */
5167 err = netif_set_real_num_tx_queues(vsi->netdev,
5168 vsi->num_queue_pairs);
5169 if (err)
5170 goto err_set_queues;
25946ddb 5171
c22e3c6c
SN		 5172 err = netif_set_real_num_rx_queues(vsi->netdev,
5173 vsi->num_queue_pairs);
5174 if (err)
5175 goto err_set_queues;
8a9eb7d3
SN		 5176
5177 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5178 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5179 dev_driver_string(&pf->pdev->dev),
5180 dev_name(&pf->pdev->dev));
8a9eb7d3 5181 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5182
c22e3c6c 5183 } else {
ce9ccb17 5184 err = -EINVAL;
6c167f58
EK		 5185 goto err_setup_rx;
5186 }
25946ddb 5187
41c445ff
JB		 5188 err = i40e_up_complete(vsi);
5189 if (err)
5190 goto err_up_complete;
5191
41c445ff
JB		 5192 return 0;
5193
5194err_up_complete:
5195 i40e_down(vsi);
25946ddb 5196err_set_queues:
41c445ff
JB		 5197 i40e_vsi_free_irq(vsi);
5198err_setup_rx:
5199 i40e_vsi_free_rx_resources(vsi);
5200err_setup_tx:
5201 i40e_vsi_free_tx_resources(vsi);
5202 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5203 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5204
5205 return err;
5206}
5207
17a73f6b
JG		 5208/**
5209 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5210 * @pf: Pointer to PF
17a73f6b
JG		 5211 *
5212 * This function destroys the hlist where all the Flow Director
5213 * filters were saved.
5214 **/
5215static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5216{
5217 struct i40e_fdir_filter *filter;
5218 struct hlist_node *node2;
5219
5220 hlist_for_each_entry_safe(filter, node2,
5221 &pf->fdir_filter_list, fdir_node) {
5222 hlist_del(&filter->fdir_node);
5223 kfree(filter);
5224 }
5225 pf->fdir_pf_active_filters = 0;
5226}
5227
41c445ff
JB		 5228/**
5229 * i40e_close - Disables a network interface
5230 * @netdev: network interface device structure
5231 *
5232 * The close entry point is called when an interface is de-activated
5233 * by the OS. The hardware is still under the driver's control, but
5234 * this netdev interface is disabled.
5235 *
5236 * Returns 0, this is not allowed to fail
5237 **/
38e00438
VD		 5238#ifdef I40E_FCOE
5239int i40e_close(struct net_device *netdev)
5240#else
41c445ff 5241static int i40e_close(struct net_device *netdev)
38e00438 5242#endif
41c445ff
JB		 5243{
5244 struct i40e_netdev_priv *np = netdev_priv(netdev);
5245 struct i40e_vsi *vsi = np->vsi;
5246
90ef8d47 5247 i40e_vsi_close(vsi);
41c445ff
JB		 5248
5249 return 0;
5250}
5251
5252/**
5253 * i40e_do_reset - Start a PF or Core Reset sequence
5254 * @pf: board private structure
5255 * @reset_flags: which reset is requested
5256 *
5257 * The essential difference in resets is that the PF Reset
5258 * doesn't clear the packet buffers, doesn't reset the PE
5259 * firmware, and doesn't bother the other PFs on the chip.
5260 **/
5261void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5262{
5263 u32 val;
5264
5265 WARN_ON(in_interrupt());
5266
263fc48f
MW		 5267 if (i40e_check_asq_alive(&pf->hw))
5268 i40e_vc_notify_reset(pf);
5269
41c445ff 5270 /* do the biggest reset indicated */
41a1d04b 5271 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5272
5273 /* Request a Global Reset
5274 *
5275 * This will start the chip's countdown to the actual full
5276 * chip reset event, and a warning interrupt to be sent
5277 * to all PFs, including the requestor. Our handler
5278 * for the warning interrupt will deal with the shutdown
5279 * and recovery of the switch setup.
5280 */
69bfb110 5281 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5282 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5283 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5284 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5285
41a1d04b 5286 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5287
5288 /* Request a Core Reset
5289 *
5290 * Same as Global Reset, except does *not* include the MAC/PHY
5291 */
69bfb110 5292 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5293 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5294 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5295 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5296 i40e_flush(&pf->hw);
5297
41a1d04b 5298 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5299
5300 /* Request a PF Reset
5301 *
5302 * Resets only the PF-specific registers
5303 *
5304 * This goes directly to the tear-down and rebuild of
5305 * the switch, since we need to do all the recovery as
5306 * for the Core Reset.
5307 */
69bfb110 5308 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5309 i40e_handle_reset_warning(pf);
5310
41a1d04b 5311 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5312 int v;
5313
5314 /* Find the VSI(s) that requested a re-init */
5315 dev_info(&pf->pdev->dev,
5316 "VSI reinit requested\n");
505682cd 5317 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5318 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5319
41c445ff
JB		 5320 if (vsi != NULL &&
5321 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5322 i40e_vsi_reinit_locked(pf->vsi[v]);
5323 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5324 }
5325 }
41a1d04b 5326 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5327 int v;
5328
5329 /* Find the VSI(s) that needs to be brought down */
5330 dev_info(&pf->pdev->dev, "VSI down requested\n");
5331 for (v = 0; v < pf->num_alloc_vsi; v++) {
5332 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5333
b5d06f05
NP		 5334 if (vsi != NULL &&
5335 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5336 set_bit(__I40E_DOWN, &vsi->state);
5337 i40e_down(vsi);
5338 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5339 }
5340 }
41c445ff
JB		 5341 } else {
5342 dev_info(&pf->pdev->dev,
5343 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5344 }
5345}
5346
4e3b35b0
NP		 5347#ifdef CONFIG_I40E_DCB
5348/**
5349 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5350 * @pf: board private structure
5351 * @old_cfg: current DCB config
5352 * @new_cfg: new DCB config
5353 **/
5354bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5355 struct i40e_dcbx_config *old_cfg,
5356 struct i40e_dcbx_config *new_cfg)
5357{
5358 bool need_reconfig = false;
5359
5360 /* Check if ETS configuration has changed */
5361 if (memcmp(&new_cfg->etscfg,
5362 &old_cfg->etscfg,
5363 sizeof(new_cfg->etscfg))) {
5364 /* If Priority Table has changed reconfig is needed */
5365 if (memcmp(&new_cfg->etscfg.prioritytable,
5366 &old_cfg->etscfg.prioritytable,
5367 sizeof(new_cfg->etscfg.prioritytable))) {
5368 need_reconfig = true;
69bfb110 5369 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5370 }
5371
5372 if (memcmp(&new_cfg->etscfg.tcbwtable,
5373 &old_cfg->etscfg.tcbwtable,
5374 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5375 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5376
5377 if (memcmp(&new_cfg->etscfg.tsatable,
5378 &old_cfg->etscfg.tsatable,
5379 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5380 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5381 }
5382
5383 /* Check if PFC configuration has changed */
5384 if (memcmp(&new_cfg->pfc,
5385 &old_cfg->pfc,
5386 sizeof(new_cfg->pfc))) {
5387 need_reconfig = true;
69bfb110 5388 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5389 }
5390
5391 /* Check if APP Table has changed */
5392 if (memcmp(&new_cfg->app,
5393 &old_cfg->app,
3d9667a9 5394 sizeof(new_cfg->app))) {
4e3b35b0 5395 need_reconfig = true;
69bfb110 5396 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5397 }
4e3b35b0 5398
fb43201f 5399 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5400 return need_reconfig;
5401}
5402
5403/**
5404 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5405 * @pf: board private structure
5406 * @e: event info posted on ARQ
5407 **/
5408static int i40e_handle_lldp_event(struct i40e_pf *pf,
5409 struct i40e_arq_event_info *e)
5410{
5411 struct i40e_aqc_lldp_get_mib *mib =
5412 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5413 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5414 struct i40e_dcbx_config tmp_dcbx_cfg;
5415 bool need_reconfig = false;
5416 int ret = 0;
5417 u8 type;
5418
4d9b6043
NP		 5419 /* Not DCB capable or capability disabled */
5420 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5421 return ret;
5422
4e3b35b0
NP		 5423 /* Ignore if event is not for Nearest Bridge */
5424 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5425 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5426 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5427 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5428 return ret;
5429
5430 /* Check MIB Type and return if event for Remote MIB update */
5431 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5432 dev_dbg(&pf->pdev->dev,
fb43201f 5433 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5434 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5435 /* Update the remote cached instance and return */
5436 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5437 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5438 &hw->remote_dcbx_config);
5439 goto exit;
5440 }
5441
9fa61dd2 5442 /* Store the old configuration */
1a2f6248 5443 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5444
750fcbcf
NP		 5445 /* Reset the old DCBx configuration data */
5446 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5447 /* Get updated DCBX data from firmware */
5448 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5449 if (ret) {
f1c7e72e
SN		 5450 dev_info(&pf->pdev->dev,
5451 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5452 i40e_stat_str(&pf->hw, ret),
5453 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5454 goto exit;
5455 }
5456
5457 /* No change detected in DCBX configs */
750fcbcf
NP		 5458 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5459 sizeof(tmp_dcbx_cfg))) {
69bfb110 5460 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5461 goto exit;
5462 }
5463
750fcbcf
NP		 5464 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5465 &hw->local_dcbx_config);
4e3b35b0 5466
750fcbcf 5467 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5468
5469 if (!need_reconfig)
5470 goto exit;
5471
4d9b6043 5472 /* Enable DCB tagging only when more than one TC */
750fcbcf 5473 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5474 pf->flags |= I40E_FLAG_DCB_ENABLED;
5475 else
5476 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5477
69129dc3 5478 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5479 /* Reconfiguration needed quiesce all VSIs */
5480 i40e_pf_quiesce_all_vsi(pf);
5481
5482 /* Changes in configuration update VEB/VSI */
5483 i40e_dcb_reconfigure(pf);
5484
2fd75f31
NP		 5485 ret = i40e_resume_port_tx(pf);
5486
69129dc3 5487 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5488 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5489 if (ret)
5490 goto exit;
5491
5492 /* Wait for the PF's Tx queues to be disabled */
5493 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5494 if (ret) {
5495 /* Schedule PF reset to recover */
5496 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5497 i40e_service_event_schedule(pf);
5498 } else {
2fd75f31 5499 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5500 }
5501
4e3b35b0
NP		 5502exit:
5503 return ret;
5504}
5505#endif /* CONFIG_I40E_DCB */
5506
23326186
ASJ		 5507/**
5508 * i40e_do_reset_safe - Protected reset path for userland calls.
5509 * @pf: board private structure
5510 * @reset_flags: which reset is requested
5511 *
5512 **/
5513void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5514{
5515 rtnl_lock();
5516 i40e_do_reset(pf, reset_flags);
5517 rtnl_unlock();
5518}
5519
41c445ff
JB		 5520/**
5521 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5522 * @pf: board private structure
5523 * @e: event info posted on ARQ
5524 *
5525 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5526 * and VF queues
5527 **/
5528static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5529 struct i40e_arq_event_info *e)
5530{
5531 struct i40e_aqc_lan_overflow *data =
5532 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5533 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5534 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5535 struct i40e_hw *hw = &pf->hw;
5536 struct i40e_vf *vf;
5537 u16 vf_id;
5538
69bfb110
JB		 5539 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5540 queue, qtx_ctl);
41c445ff
JB		 5541
5542 /* Queue belongs to VF, find the VF and issue VF reset */
5543 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5544 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5545 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5546 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5547 vf_id -= hw->func_caps.vf_base_id;
5548 vf = &pf->vf[vf_id];
5549 i40e_vc_notify_vf_reset(vf);
5550 /* Allow VF to process pending reset notification */
5551 msleep(20);
5552 i40e_reset_vf(vf, false);
5553 }
5554}
5555
5556/**
5557 * i40e_service_event_complete - Finish up the service event
5558 * @pf: board private structure
5559 **/
5560static void i40e_service_event_complete(struct i40e_pf *pf)
5561{
5562 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5563
5564 /* flush memory to make sure state is correct before next watchog */
4e857c58 5565 smp_mb__before_atomic();
41c445ff
JB		 5566 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5567}
5568
55a5e60b 5569/**
12957388
ASJ		 5570 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5571 * @pf: board private structure
5572 **/
04294e38 5573u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5574{
04294e38 5575 u32 val, fcnt_prog;
12957388
ASJ		 5576
5577 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5578 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5579 return fcnt_prog;
5580}
5581
5582/**
04294e38 5583 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5584 * @pf: board private structure
5585 **/
04294e38 5586u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5587{
04294e38
ASJ		 5588 u32 val, fcnt_prog;
5589
55a5e60b
ASJ		 5590 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5591 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5592 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5593 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5594 return fcnt_prog;
5595}
1e1be8f6 5596
04294e38
ASJ		 5597/**
5598 * i40e_get_global_fd_count - Get total FD filters programmed on device
5599 * @pf: board private structure
5600 **/
5601u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5602{
5603 u32 val, fcnt_prog;
5604
5605 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5606 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5607 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5608 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5609 return fcnt_prog;
5610}
5611
55a5e60b
ASJ		 5612/**
5613 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5614 * @pf: board private structure
5615 **/
5616void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5617{
3487b6c3 5618 struct i40e_fdir_filter *filter;
55a5e60b 5619 u32 fcnt_prog, fcnt_avail;
3487b6c3 5620 struct hlist_node *node;
55a5e60b 5621
1e1be8f6
ASJ		 5622 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5623 return;
5624
55a5e60b
ASJ		 5625 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5626 * to re-enable
5627 */
04294e38 5628 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5629 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5630 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5631 (pf->fd_add_err == 0) ||
5632 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5633 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5634 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5635 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5636 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5637 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5638 }
5639 }
5640 /* Wait for some more space to be available to turn on ATR */
5641 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5642 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5643 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5644 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5645 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5646 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5647 }
5648 }
3487b6c3
CW		 5649
5650 /* if hw had a problem adding a filter, delete it */
5651 if (pf->fd_inv > 0) {
5652 hlist_for_each_entry_safe(filter, node,
5653 &pf->fdir_filter_list, fdir_node) {
5654 if (filter->fd_id == pf->fd_inv) {
5655 hlist_del(&filter->fdir_node);
5656 kfree(filter);
5657 pf->fdir_pf_active_filters--;
5658 }
5659 }
5660 }
55a5e60b
ASJ		 5661}
5662
1e1be8f6 5663#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5664#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5665/**
5666 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5667 * @pf: board private structure
5668 **/
5669static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5670{
04294e38 5671 unsigned long min_flush_time;
1e1be8f6 5672 int flush_wait_retry = 50;
04294e38
ASJ		 5673 bool disable_atr = false;
5674 int fd_room;
1e1be8f6
ASJ		 5675 int reg;
5676
1790ed0c
AA		 5677 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5678 return;
5679
a5fdaf34
JB		 5680 if (!time_after(jiffies, pf->fd_flush_timestamp +
5681 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5682 return;
04294e38 5683
a5fdaf34
JB		 5684 /* If the flush is happening too quick and we have mostly SB rules we
5685 * should not re-enable ATR for some time.
5686 */
5687 min_flush_time = pf->fd_flush_timestamp +
5688 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5689 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5690
5691 if (!(time_after(jiffies, min_flush_time)) &&
5692 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5693 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5694 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5695 disable_atr = true;
5696 }
5697
5698 pf->fd_flush_timestamp = jiffies;
5699 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5700 /* flush all filters */
5701 wr32(&pf->hw, I40E_PFQF_CTL_1,
5702 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5703 i40e_flush(&pf->hw);
5704 pf->fd_flush_cnt++;
5705 pf->fd_add_err = 0;
5706 do {
5707 /* Check FD flush status every 5-6msec */
5708 usleep_range(5000, 6000);
5709 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5710 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5711 break;
5712 } while (flush_wait_retry--);
5713 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5714 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5715 } else {
5716 /* replay sideband filters */
5717 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5718 if (!disable_atr)
5719 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5720 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5721 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5722 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5723 }
a5fdaf34 5724
1e1be8f6
ASJ		 5725}
5726
5727/**
5728 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5729 * @pf: board private structure
5730 **/
04294e38 5731u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5732{
5733 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5734}
5735
5736/* We can see up to 256 filter programming desc in transit if the filters are
5737 * being applied really fast; before we see the first
5738 * filter miss error on Rx queue 0. Accumulating enough error messages before
5739 * reacting will make sure we don't cause flush too often.
5740 */
5741#define I40E_MAX_FD_PROGRAM_ERROR 256
5742
41c445ff
JB		 5743/**
5744 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5745 * @pf: board private structure
5746 **/
5747static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5748{
41c445ff 5749
41c445ff
JB		 5750 /* if interface is down do nothing */
5751 if (test_bit(__I40E_DOWN, &pf->state))
5752 return;
1e1be8f6 5753
1790ed0c
AA		 5754 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5755 return;
5756
04294e38 5757 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5758 i40e_fdir_flush_and_replay(pf);
5759
55a5e60b
ASJ		 5760 i40e_fdir_check_and_reenable(pf);
5761
41c445ff
JB		 5762}
5763
5764/**
5765 * i40e_vsi_link_event - notify VSI of a link event
5766 * @vsi: vsi to be notified
5767 * @link_up: link up or down
5768 **/
5769static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5770{
32b5b811 5771 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5772 return;
5773
5774 switch (vsi->type) {
5775 case I40E_VSI_MAIN:
38e00438
VD		 5776#ifdef I40E_FCOE
5777 case I40E_VSI_FCOE:
5778#endif
41c445ff
JB		 5779 if (!vsi->netdev || !vsi->netdev_registered)
5780 break;
5781
5782 if (link_up) {
5783 netif_carrier_on(vsi->netdev);
5784 netif_tx_wake_all_queues(vsi->netdev);
5785 } else {
5786 netif_carrier_off(vsi->netdev);
5787 netif_tx_stop_all_queues(vsi->netdev);
5788 }
5789 break;
5790
5791 case I40E_VSI_SRIOV:
41c445ff
JB		 5792 case I40E_VSI_VMDQ2:
5793 case I40E_VSI_CTRL:
5794 case I40E_VSI_MIRROR:
5795 default:
5796 /* there is no notification for other VSIs */
5797 break;
5798 }
5799}
5800
5801/**
5802 * i40e_veb_link_event - notify elements on the veb of a link event
5803 * @veb: veb to be notified
5804 * @link_up: link up or down
5805 **/
5806static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5807{
5808 struct i40e_pf *pf;
5809 int i;
5810
5811 if (!veb || !veb->pf)
5812 return;
5813 pf = veb->pf;
5814
5815 /* depth first... */
5816 for (i = 0; i < I40E_MAX_VEB; i++)
5817 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5818 i40e_veb_link_event(pf->veb[i], link_up);
5819
5820 /* ... now the local VSIs */
505682cd 5821 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5822 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5823 i40e_vsi_link_event(pf->vsi[i], link_up);
5824}
5825
5826/**
5827 * i40e_link_event - Update netif_carrier status
5828 * @pf: board private structure
5829 **/
5830static void i40e_link_event(struct i40e_pf *pf)
5831{
320684cd 5832 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5833 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 5834 i40e_status status;
5835 bool new_link, old_link;
41c445ff 5836
1e701e09
JB		 5837 /* set this to force the get_link_status call to refresh state */
5838 pf->hw.phy.get_link_info = true;
5839
41c445ff 5840 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 5841
5842 status = i40e_get_link_status(&pf->hw, &new_link);
5843 if (status) {
5844 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
5845 status);
5846 return;
5847 }
5848
fef59ddf
CS		 5849 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5850 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5851
1e701e09 5852 if (new_link == old_link &&
fef59ddf 5853 new_link_speed == old_link_speed &&
320684cd
MW		 5854 (test_bit(__I40E_DOWN, &vsi->state) ||
5855 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5856 return;
320684cd
MW		 5857
5858 if (!test_bit(__I40E_DOWN, &vsi->state))
5859 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5860
5861 /* Notify the base of the switch tree connected to
5862 * the link. Floating VEBs are not notified.
5863 */
5864 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5865 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5866 else
320684cd 5867 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5868
5869 if (pf->vf)
5870 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5871
5872 if (pf->flags & I40E_FLAG_PTP)
5873 i40e_ptp_set_increment(pf);
41c445ff
JB		 5874}
5875
41c445ff 5876/**
21536717 5877 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5878 * @pf: board private structure
5879 **/
5880static void i40e_watchdog_subtask(struct i40e_pf *pf)
5881{
5882 int i;
5883
5884 /* if interface is down do nothing */
5885 if (test_bit(__I40E_DOWN, &pf->state) ||
5886 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5887 return;
5888
21536717
SN		 5889 /* make sure we don't do these things too often */
5890 if (time_before(jiffies, (pf->service_timer_previous +
5891 pf->service_timer_period)))
5892 return;
5893 pf->service_timer_previous = jiffies;
5894
9ac77266
SN		 5895 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
5896 i40e_link_event(pf);
21536717 5897
41c445ff
JB		 5898 /* Update the stats for active netdevs so the network stack
5899 * can look at updated numbers whenever it cares to
5900 */
505682cd 5901 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5902 if (pf->vsi[i] && pf->vsi[i]->netdev)
5903 i40e_update_stats(pf->vsi[i]);
5904
d1a8d275
ASJ		 5905 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
5906 /* Update the stats for the active switching components */
5907 for (i = 0; i < I40E_MAX_VEB; i++)
5908 if (pf->veb[i])
5909 i40e_update_veb_stats(pf->veb[i]);
5910 }
beb0dff1
JK		 5911
5912 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5913}
5914
5915/**
5916 * i40e_reset_subtask - Set up for resetting the device and driver
5917 * @pf: board private structure
5918 **/
5919static void i40e_reset_subtask(struct i40e_pf *pf)
5920{
5921 u32 reset_flags = 0;
5922
23326186 5923 rtnl_lock();
41c445ff 5924 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5925 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5926 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5927 }
5928 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5929 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5930 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5931 }
5932 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5933 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5934 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5935 }
5936 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5937 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5938 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5939 }
b5d06f05 5940 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5941 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5942 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5943 }
41c445ff
JB		 5944
5945 /* If there's a recovery already waiting, it takes
5946 * precedence before starting a new reset sequence.
5947 */
5948 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5949 i40e_handle_reset_warning(pf);
23326186 5950 goto unlock;
41c445ff
JB		 5951 }
5952
5953 /* If we're already down or resetting, just bail */
5954 if (reset_flags &&
5955 !test_bit(__I40E_DOWN, &pf->state) &&
5956 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5957 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5958
5959unlock:
5960 rtnl_unlock();
41c445ff
JB		 5961}
5962
5963/**
5964 * i40e_handle_link_event - Handle link event
5965 * @pf: board private structure
5966 * @e: event info posted on ARQ
5967 **/
5968static void i40e_handle_link_event(struct i40e_pf *pf,
5969 struct i40e_arq_event_info *e)
5970{
5971 struct i40e_hw *hw = &pf->hw;
5972 struct i40e_aqc_get_link_status *status =
5973 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5974
5975 /* save off old link status information */
1a2f6248 5976 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5977
1e701e09
JB		 5978 /* Do a new status request to re-enable LSE reporting
5979 * and load new status information into the hw struct
5980 * This completely ignores any state information
5981 * in the ARQ event info, instead choosing to always
5982 * issue the AQ update link status command.
5983 */
5984 i40e_link_event(pf);
5985
7b592f61
CW		 5986 /* check for unqualified module, if link is down */
5987 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5988 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5989 (!(status->link_info & I40E_AQ_LINK_UP)))
5990 dev_err(&pf->pdev->dev,
5991 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5992}
5993
5994/**
5995 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5996 * @pf: board private structure
5997 **/
5998static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5999{
6000 struct i40e_arq_event_info event;
6001 struct i40e_hw *hw = &pf->hw;
6002 u16 pending, i = 0;
6003 i40e_status ret;
6004 u16 opcode;
86df242b 6005 u32 oldval;
41c445ff
JB		 6006 u32 val;
6007
a316f651
ASJ		 6008 /* Do not run clean AQ when PF reset fails */
6009 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6010 return;
6011
86df242b
SN		 6012 /* check for error indications */
6013 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6014 oldval = val;
6015 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6016 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6017 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6018 }
6019 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6020 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6021 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6022 }
6023 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6024 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6025 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6026 }
6027 if (oldval != val)
6028 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6029
6030 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6031 oldval = val;
6032 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6033 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6034 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6035 }
6036 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6037 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6038 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6039 }
6040 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6041 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6042 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6043 }
6044 if (oldval != val)
6045 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6046
1001dc37
MW		 6047 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6048 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6049 if (!event.msg_buf)
6050 return;
6051
6052 do {
6053 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6054 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6055 break;
56497978 6056 else if (ret) {
41c445ff
JB		 6057 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6058 break;
6059 }
6060
6061 opcode = le16_to_cpu(event.desc.opcode);
6062 switch (opcode) {
6063
6064 case i40e_aqc_opc_get_link_status:
6065 i40e_handle_link_event(pf, &event);
6066 break;
6067 case i40e_aqc_opc_send_msg_to_pf:
6068 ret = i40e_vc_process_vf_msg(pf,
6069 le16_to_cpu(event.desc.retval),
6070 le32_to_cpu(event.desc.cookie_high),
6071 le32_to_cpu(event.desc.cookie_low),
6072 event.msg_buf,
1001dc37 6073 event.msg_len);
41c445ff
JB		 6074 break;
6075 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6076 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6077#ifdef CONFIG_I40E_DCB
6078 rtnl_lock();
6079 ret = i40e_handle_lldp_event(pf, &event);
6080 rtnl_unlock();
6081#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6082 break;
6083 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6084 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6085 i40e_handle_lan_overflow_event(pf, &event);
6086 break;
0467bc91
SN		 6087 case i40e_aqc_opc_send_msg_to_peer:
6088 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6089 break;
91a0f930
SN		 6090 case i40e_aqc_opc_nvm_erase:
6091 case i40e_aqc_opc_nvm_update:
6092 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6093 break;
41c445ff
JB		 6094 default:
6095 dev_info(&pf->pdev->dev,
0467bc91
SN		 6096 "ARQ Error: Unknown event 0x%04x received\n",
6097 opcode);
41c445ff
JB		 6098 break;
6099 }
6100 } while (pending && (i++ < pf->adminq_work_limit));
6101
6102 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6103 /* re-enable Admin queue interrupt cause */
6104 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6105 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6106 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6107 i40e_flush(hw);
6108
6109 kfree(event.msg_buf);
6110}
6111
4eb3f768
SN		 6112/**
6113 * i40e_verify_eeprom - make sure eeprom is good to use
6114 * @pf: board private structure
6115 **/
6116static void i40e_verify_eeprom(struct i40e_pf *pf)
6117{
6118 int err;
6119
6120 err = i40e_diag_eeprom_test(&pf->hw);
6121 if (err) {
6122 /* retry in case of garbage read */
6123 err = i40e_diag_eeprom_test(&pf->hw);
6124 if (err) {
6125 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6126 err);
6127 set_bit(__I40E_BAD_EEPROM, &pf->state);
6128 }
6129 }
6130
6131 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6132 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6133 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6134 }
6135}
6136
386a0afa
AA		 6137/**
6138 * i40e_enable_pf_switch_lb
b40c82e6 6139 * @pf: pointer to the PF structure
386a0afa
AA		 6140 *
6141 * enable switch loop back or die - no point in a return value
6142 **/
6143static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6144{
6145 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6146 struct i40e_vsi_context ctxt;
f1c7e72e 6147 int ret;
386a0afa
AA		 6148
6149 ctxt.seid = pf->main_vsi_seid;
6150 ctxt.pf_num = pf->hw.pf_id;
6151 ctxt.vf_num = 0;
f1c7e72e
SN		 6152 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6153 if (ret) {
386a0afa 6154 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6155 "couldn't get PF vsi config, err %s aq_err %s\n",
6156 i40e_stat_str(&pf->hw, ret),
6157 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6158 return;
6159 }
6160 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6161 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6162 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6163
f1c7e72e
SN		 6164 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6165 if (ret) {
386a0afa 6166 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6167 "update vsi switch failed, err %s aq_err %s\n",
6168 i40e_stat_str(&pf->hw, ret),
6169 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6170 }
6171}
6172
6173/**
6174 * i40e_disable_pf_switch_lb
b40c82e6 6175 * @pf: pointer to the PF structure
386a0afa
AA		 6176 *
6177 * disable switch loop back or die - no point in a return value
6178 **/
6179static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6180{
6181 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6182 struct i40e_vsi_context ctxt;
f1c7e72e 6183 int ret;
386a0afa
AA		 6184
6185 ctxt.seid = pf->main_vsi_seid;
6186 ctxt.pf_num = pf->hw.pf_id;
6187 ctxt.vf_num = 0;
f1c7e72e
SN		 6188 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6189 if (ret) {
386a0afa 6190 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6191 "couldn't get PF vsi config, err %s aq_err %s\n",
6192 i40e_stat_str(&pf->hw, ret),
6193 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6194 return;
6195 }
6196 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6197 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6198 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6199
f1c7e72e
SN		 6200 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6201 if (ret) {
386a0afa 6202 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6203 "update vsi switch failed, err %s aq_err %s\n",
6204 i40e_stat_str(&pf->hw, ret),
6205 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6206 }
6207}
6208
51616018
NP		 6209/**
6210 * i40e_config_bridge_mode - Configure the HW bridge mode
6211 * @veb: pointer to the bridge instance
6212 *
6213 * Configure the loop back mode for the LAN VSI that is downlink to the
6214 * specified HW bridge instance. It is expected this function is called
6215 * when a new HW bridge is instantiated.
6216 **/
6217static void i40e_config_bridge_mode(struct i40e_veb *veb)
6218{
6219 struct i40e_pf *pf = veb->pf;
6220
6dec1017
SN		 6221 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6222 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6223 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6224 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6225 i40e_disable_pf_switch_lb(pf);
6226 else
6227 i40e_enable_pf_switch_lb(pf);
6228}
6229
41c445ff
JB		 6230/**
6231 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6232 * @veb: pointer to the VEB instance
6233 *
6234 * This is a recursive function that first builds the attached VSIs then
6235 * recurses in to build the next layer of VEB. We track the connections
6236 * through our own index numbers because the seid's from the HW could
6237 * change across the reset.
6238 **/
6239static int i40e_reconstitute_veb(struct i40e_veb *veb)
6240{
6241 struct i40e_vsi *ctl_vsi = NULL;
6242 struct i40e_pf *pf = veb->pf;
6243 int v, veb_idx;
6244 int ret;
6245
6246 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6247 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6248 if (pf->vsi[v] &&
6249 pf->vsi[v]->veb_idx == veb->idx &&
6250 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6251 ctl_vsi = pf->vsi[v];
6252 break;
6253 }
6254 }
6255 if (!ctl_vsi) {
6256 dev_info(&pf->pdev->dev,
6257 "missing owner VSI for veb_idx %d\n", veb->idx);
6258 ret = -ENOENT;
6259 goto end_reconstitute;
6260 }
6261 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6262 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6263 ret = i40e_add_vsi(ctl_vsi);
6264 if (ret) {
6265 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6266 "rebuild of veb_idx %d owner VSI failed: %d\n",
6267 veb->idx, ret);
41c445ff
JB		 6268 goto end_reconstitute;
6269 }
6270 i40e_vsi_reset_stats(ctl_vsi);
6271
6272 /* create the VEB in the switch and move the VSI onto the VEB */
6273 ret = i40e_add_veb(veb, ctl_vsi);
6274 if (ret)
6275 goto end_reconstitute;
6276
fc60861e
ASJ		 6277 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6278 veb->bridge_mode = BRIDGE_MODE_VEB;
6279 else
6280 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6281 i40e_config_bridge_mode(veb);
b64ba084 6282
41c445ff 6283 /* create the remaining VSIs attached to this VEB */
505682cd 6284 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6285 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6286 continue;
6287
6288 if (pf->vsi[v]->veb_idx == veb->idx) {
6289 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6290
41c445ff
JB		 6291 vsi->uplink_seid = veb->seid;
6292 ret = i40e_add_vsi(vsi);
6293 if (ret) {
6294 dev_info(&pf->pdev->dev,
6295 "rebuild of vsi_idx %d failed: %d\n",
6296 v, ret);
6297 goto end_reconstitute;
6298 }
6299 i40e_vsi_reset_stats(vsi);
6300 }
6301 }
6302
6303 /* create any VEBs attached to this VEB - RECURSION */
6304 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6305 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6306 pf->veb[veb_idx]->uplink_seid = veb->seid;
6307 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6308 if (ret)
6309 break;
6310 }
6311 }
6312
6313end_reconstitute:
6314 return ret;
6315}
6316
6317/**
6318 * i40e_get_capabilities - get info about the HW
6319 * @pf: the PF struct
6320 **/
6321static int i40e_get_capabilities(struct i40e_pf *pf)
6322{
6323 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6324 u16 data_size;
6325 int buf_len;
6326 int err;
6327
6328 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6329 do {
6330 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6331 if (!cap_buf)
6332 return -ENOMEM;
6333
6334 /* this loads the data into the hw struct for us */
6335 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6336 &data_size,
6337 i40e_aqc_opc_list_func_capabilities,
6338 NULL);
6339 /* data loaded, buffer no longer needed */
6340 kfree(cap_buf);
6341
6342 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6343 /* retry with a larger buffer */
6344 buf_len = data_size;
6345 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6346 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6347 "capability discovery failed, err %s aq_err %s\n",
6348 i40e_stat_str(&pf->hw, err),
6349 i40e_aq_str(&pf->hw,
6350 pf->hw.aq.asq_last_status));
41c445ff
JB		 6351 return -ENODEV;
6352 }
6353 } while (err);
6354
6355 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6356 dev_info(&pf->pdev->dev,
6357 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6358 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6359 pf->hw.func_caps.num_msix_vectors,
6360 pf->hw.func_caps.num_msix_vectors_vf,
6361 pf->hw.func_caps.fd_filters_guaranteed,
6362 pf->hw.func_caps.fd_filters_best_effort,
6363 pf->hw.func_caps.num_tx_qp,
6364 pf->hw.func_caps.num_vsis);
6365
7134f9ce
JB		 6366#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6367 + pf->hw.func_caps.num_vfs)
6368 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6369 dev_info(&pf->pdev->dev,
6370 "got num_vsis %d, setting num_vsis to %d\n",
6371 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6372 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6373 }
6374
41c445ff
JB		 6375 return 0;
6376}
6377
cbf61325
ASJ		 6378static int i40e_vsi_clear(struct i40e_vsi *vsi);
6379
41c445ff 6380/**
cbf61325 6381 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6382 * @pf: board private structure
6383 **/
cbf61325 6384static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6385{
6386 struct i40e_vsi *vsi;
8a9eb7d3 6387 int i;
41c445ff 6388
407e063c
JB		 6389 /* quick workaround for an NVM issue that leaves a critical register
6390 * uninitialized
6391 */
6392 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6393 static const u32 hkey[] = {
6394 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6395 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6396 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6397 0x95b3a76d};
6398
6399 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6400 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6401 }
6402
cbf61325 6403 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6404 return;
6405
cbf61325 6406 /* find existing VSI and see if it needs configuring */
41c445ff 6407 vsi = NULL;
505682cd 6408 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6409 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6410 vsi = pf->vsi[i];
cbf61325
ASJ		 6411 break;
6412 }
6413 }
6414
6415 /* create a new VSI if none exists */
41c445ff 6416 if (!vsi) {
cbf61325
ASJ		 6417 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6418 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6419 if (!vsi) {
6420 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6421 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6422 return;
41c445ff 6423 }
cbf61325 6424 }
41c445ff 6425
8a9eb7d3 6426 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6427}
6428
6429/**
6430 * i40e_fdir_teardown - release the Flow Director resources
6431 * @pf: board private structure
6432 **/
6433static void i40e_fdir_teardown(struct i40e_pf *pf)
6434{
6435 int i;
6436
17a73f6b 6437 i40e_fdir_filter_exit(pf);
505682cd 6438 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6439 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6440 i40e_vsi_release(pf->vsi[i]);
6441 break;
6442 }
6443 }
6444}
6445
6446/**
f650a38b 6447 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6448 * @pf: board private structure
6449 *
b40c82e6 6450 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6451 **/
23cfbe07 6452static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6453{
41c445ff 6454 struct i40e_hw *hw = &pf->hw;
60442dea 6455 i40e_status ret = 0;
41c445ff
JB		 6456 u32 v;
6457
6458 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6459 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6460 return;
41c445ff 6461
69bfb110 6462 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6463
41c445ff
JB		 6464 /* quiesce the VSIs and their queues that are not already DOWN */
6465 i40e_pf_quiesce_all_vsi(pf);
6466
505682cd 6467 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6468 if (pf->vsi[v])
6469 pf->vsi[v]->seid = 0;
6470 }
6471
6472 i40e_shutdown_adminq(&pf->hw);
6473
f650a38b 6474 /* call shutdown HMC */
60442dea
SN		 6475 if (hw->hmc.hmc_obj) {
6476 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6477 if (ret)
60442dea
SN		 6478 dev_warn(&pf->pdev->dev,
6479 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6480 }
f650a38b
ASJ		 6481}
6482
44033fac
JB		 6483/**
6484 * i40e_send_version - update firmware with driver version
6485 * @pf: PF struct
6486 */
6487static void i40e_send_version(struct i40e_pf *pf)
6488{
6489 struct i40e_driver_version dv;
6490
6491 dv.major_version = DRV_VERSION_MAJOR;
6492 dv.minor_version = DRV_VERSION_MINOR;
6493 dv.build_version = DRV_VERSION_BUILD;
6494 dv.subbuild_version = 0;
35a7d804 6495 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6496 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6497}
6498
f650a38b 6499/**
4dda12e6 6500 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6501 * @pf: board private structure
bc7d338f 6502 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6503 **/
bc7d338f 6504static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6505{
f650a38b 6506 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6507 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6508 i40e_status ret;
6509 u32 v;
6510
41c445ff
JB		 6511 /* Now we wait for GRST to settle out.
6512 * We don't have to delete the VEBs or VSIs from the hw switch
6513 * because the reset will make them disappear.
6514 */
6515 ret = i40e_pf_reset(hw);
b5565400 6516 if (ret) {
41c445ff 6517 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6518 set_bit(__I40E_RESET_FAILED, &pf->state);
6519 goto clear_recovery;
b5565400 6520 }
41c445ff
JB		 6521 pf->pfr_count++;
6522
6523 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6524 goto clear_recovery;
69bfb110 6525 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6526
6527 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6528 ret = i40e_init_adminq(&pf->hw);
6529 if (ret) {
f1c7e72e
SN		 6530 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6531 i40e_stat_str(&pf->hw, ret),
6532 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6533 goto clear_recovery;
41c445ff
JB		 6534 }
6535
4eb3f768 6536 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6537 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6538 i40e_verify_eeprom(pf);
4eb3f768 6539
e78ac4bf 6540 i40e_clear_pxe_mode(hw);
41c445ff 6541 ret = i40e_get_capabilities(pf);
f1c7e72e 6542 if (ret)
41c445ff 6543 goto end_core_reset;
41c445ff 6544
41c445ff
JB		 6545 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6546 hw->func_caps.num_rx_qp,
6547 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6548 if (ret) {
6549 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6550 goto end_core_reset;
6551 }
6552 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6553 if (ret) {
6554 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6555 goto end_core_reset;
6556 }
6557
4e3b35b0
NP		 6558#ifdef CONFIG_I40E_DCB
6559 ret = i40e_init_pf_dcb(pf);
6560 if (ret) {
aebfc816
SN		 6561 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6562 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6563 /* Continue without DCB enabled */
4e3b35b0
NP		 6564 }
6565#endif /* CONFIG_I40E_DCB */
38e00438 6566#ifdef I40E_FCOE
21364bcf 6567 i40e_init_pf_fcoe(pf);
4e3b35b0 6568
38e00438 6569#endif
41c445ff 6570 /* do basic switch setup */
bc7d338f 6571 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6572 if (ret)
6573 goto end_core_reset;
6574
7e2453fe
JB		 6575 /* driver is only interested in link up/down and module qualification
6576 * reports from firmware
6577 */
6578 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6579 I40E_AQ_EVENT_LINK_UPDOWN |
6580 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6581 if (ret)
f1c7e72e
SN		 6582 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6583 i40e_stat_str(&pf->hw, ret),
6584 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6585
cafa2ee6
ASJ		 6586 /* make sure our flow control settings are restored */
6587 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6588 if (ret)
8279e495
NP		 6589 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6590 i40e_stat_str(&pf->hw, ret),
6591 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6592
41c445ff
JB		 6593 /* Rebuild the VSIs and VEBs that existed before reset.
6594 * They are still in our local switch element arrays, so only
6595 * need to rebuild the switch model in the HW.
6596 *
6597 * If there were VEBs but the reconstitution failed, we'll try
6598 * try to recover minimal use by getting the basic PF VSI working.
6599 */
6600 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6601 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6602 /* find the one VEB connected to the MAC, and find orphans */
6603 for (v = 0; v < I40E_MAX_VEB; v++) {
6604 if (!pf->veb[v])
6605 continue;
6606
6607 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6608 pf->veb[v]->uplink_seid == 0) {
6609 ret = i40e_reconstitute_veb(pf->veb[v]);
6610
6611 if (!ret)
6612 continue;
6613
6614 /* If Main VEB failed, we're in deep doodoo,
6615 * so give up rebuilding the switch and set up
6616 * for minimal rebuild of PF VSI.
6617 * If orphan failed, we'll report the error
6618 * but try to keep going.
6619 */
6620 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6621 dev_info(&pf->pdev->dev,
6622 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6623 ret);
6624 pf->vsi[pf->lan_vsi]->uplink_seid
6625 = pf->mac_seid;
6626 break;
6627 } else if (pf->veb[v]->uplink_seid == 0) {
6628 dev_info(&pf->pdev->dev,
6629 "rebuild of orphan VEB failed: %d\n",
6630 ret);
6631 }
6632 }
6633 }
6634 }
6635
6636 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6637 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6638 /* no VEB, so rebuild only the Main VSI */
6639 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6640 if (ret) {
6641 dev_info(&pf->pdev->dev,
6642 "rebuild of Main VSI failed: %d\n", ret);
6643 goto end_core_reset;
6644 }
6645 }
6646
025b4a54
ASJ		 6647 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6648 (pf->hw.aq.fw_maj_ver < 4)) {
6649 msleep(75);
6650 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6651 if (ret)
f1c7e72e
SN		 6652 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6653 i40e_stat_str(&pf->hw, ret),
6654 i40e_aq_str(&pf->hw,
6655 pf->hw.aq.asq_last_status));
cafa2ee6 6656 }
41c445ff
JB		 6657 /* reinit the misc interrupt */
6658 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6659 ret = i40e_setup_misc_vector(pf);
6660
6661 /* restart the VSIs that were rebuilt and running before the reset */
6662 i40e_pf_unquiesce_all_vsi(pf);
6663
69f64b2b
MW		 6664 if (pf->num_alloc_vfs) {
6665 for (v = 0; v < pf->num_alloc_vfs; v++)
6666 i40e_reset_vf(&pf->vf[v], true);
6667 }
6668
41c445ff 6669 /* tell the firmware that we're starting */
44033fac 6670 i40e_send_version(pf);
41c445ff
JB		 6671
6672end_core_reset:
a316f651
ASJ		 6673 clear_bit(__I40E_RESET_FAILED, &pf->state);
6674clear_recovery:
41c445ff
JB		 6675 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6676}
6677
f650a38b 6678/**
b40c82e6 6679 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6680 * @pf: board private structure
6681 *
6682 * Close up the VFs and other things in prep for a Core Reset,
6683 * then get ready to rebuild the world.
6684 **/
6685static void i40e_handle_reset_warning(struct i40e_pf *pf)
6686{
23cfbe07
SN		 6687 i40e_prep_for_reset(pf);
6688 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6689}
6690
41c445ff
JB		 6691/**
6692 * i40e_handle_mdd_event
b40c82e6 6693 * @pf: pointer to the PF structure
41c445ff
JB		 6694 *
6695 * Called from the MDD irq handler to identify possibly malicious vfs
6696 **/
6697static void i40e_handle_mdd_event(struct i40e_pf *pf)
6698{
6699 struct i40e_hw *hw = &pf->hw;
6700 bool mdd_detected = false;
df430b12 6701 bool pf_mdd_detected = false;
41c445ff
JB		 6702 struct i40e_vf *vf;
6703 u32 reg;
6704 int i;
6705
6706 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6707 return;
6708
6709 /* find what triggered the MDD event */
6710 reg = rd32(hw, I40E_GL_MDET_TX);
6711 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6712 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6713 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6714 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6715 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6716 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6717 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6718 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6719 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6720 pf->hw.func_caps.base_queue;
faf32978 6721 if (netif_msg_tx_err(pf))
b40c82e6 6722 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6723 event, queue, pf_num, vf_num);
41c445ff
JB		 6724 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6725 mdd_detected = true;
6726 }
6727 reg = rd32(hw, I40E_GL_MDET_RX);
6728 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6729 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6730 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6731 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6732 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6733 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6734 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6735 pf->hw.func_caps.base_queue;
faf32978
JB		 6736 if (netif_msg_rx_err(pf))
6737 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6738 event, queue, func);
41c445ff
JB		 6739 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6740 mdd_detected = true;
6741 }
6742
df430b12
NP		 6743 if (mdd_detected) {
6744 reg = rd32(hw, I40E_PF_MDET_TX);
6745 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6746 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6747 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6748 pf_mdd_detected = true;
6749 }
6750 reg = rd32(hw, I40E_PF_MDET_RX);
6751 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6752 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6753 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6754 pf_mdd_detected = true;
6755 }
6756 /* Queue belongs to the PF, initiate a reset */
6757 if (pf_mdd_detected) {
6758 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6759 i40e_service_event_schedule(pf);
6760 }
6761 }
6762
41c445ff
JB		 6763 /* see if one of the VFs needs its hand slapped */
6764 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6765 vf = &(pf->vf[i]);
6766 reg = rd32(hw, I40E_VP_MDET_TX(i));
6767 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6768 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6769 vf->num_mdd_events++;
faf32978
JB		 6770 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6771 i);
41c445ff
JB		 6772 }
6773
6774 reg = rd32(hw, I40E_VP_MDET_RX(i));
6775 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6776 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6777 vf->num_mdd_events++;
faf32978
JB		 6778 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6779 i);
41c445ff
JB		 6780 }
6781
6782 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6783 dev_info(&pf->pdev->dev,
6784 "Too many MDD events on VF %d, disabled\n", i);
6785 dev_info(&pf->pdev->dev,
6786 "Use PF Control I/F to re-enable the VF\n");
6787 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6788 }
6789 }
6790
6791 /* re-enable mdd interrupt cause */
6792 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6793 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6794 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6795 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6796 i40e_flush(hw);
6797}
6798
a1c9a9d9
JK		 6799#ifdef CONFIG_I40E_VXLAN
6800/**
6801 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6802 * @pf: board private structure
6803 **/
6804static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6805{
a1c9a9d9
JK		 6806 struct i40e_hw *hw = &pf->hw;
6807 i40e_status ret;
a1c9a9d9
JK		 6808 __be16 port;
6809 int i;
6810
6811 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6812 return;
6813
6814 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6815
6816 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6817 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6818 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6819 port = pf->vxlan_ports[i];
c22c06c8
SN		 6820 if (port)
6821 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6822 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6823 NULL, NULL);
6824 else
6825 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6826
6827 if (ret) {
c22c06c8 6828 dev_info(&pf->pdev->dev,
f1c7e72e 6829 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6830 port ? "add" : "delete",
f1c7e72e
SN		 6831 ntohs(port), i,
6832 i40e_stat_str(&pf->hw, ret),
6833 i40e_aq_str(&pf->hw,
6834 pf->hw.aq.asq_last_status));
a1c9a9d9 6835 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6836 }
6837 }
6838 }
6839}
6840
6841#endif
41c445ff
JB		 6842/**
6843 * i40e_service_task - Run the driver's async subtasks
6844 * @work: pointer to work_struct containing our data
6845 **/
6846static void i40e_service_task(struct work_struct *work)
6847{
6848 struct i40e_pf *pf = container_of(work,
6849 struct i40e_pf,
6850 service_task);
6851 unsigned long start_time = jiffies;
6852
e57a2fea
SN		 6853 /* don't bother with service tasks if a reset is in progress */
6854 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6855 i40e_service_event_complete(pf);
6856 return;
6857 }
6858
b03a8c1f 6859 i40e_detect_recover_hung(pf);
41c445ff
JB		 6860 i40e_reset_subtask(pf);
6861 i40e_handle_mdd_event(pf);
6862 i40e_vc_process_vflr_event(pf);
6863 i40e_watchdog_subtask(pf);
6864 i40e_fdir_reinit_subtask(pf);
41c445ff 6865 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6866#ifdef CONFIG_I40E_VXLAN
6867 i40e_sync_vxlan_filters_subtask(pf);
6868#endif
41c445ff
JB		 6869 i40e_clean_adminq_subtask(pf);
6870
6871 i40e_service_event_complete(pf);
6872
6873 /* If the tasks have taken longer than one timer cycle or there
6874 * is more work to be done, reschedule the service task now
6875 * rather than wait for the timer to tick again.
6876 */
6877 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6878 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6879 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6880 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6881 i40e_service_event_schedule(pf);
6882}
6883
6884/**
6885 * i40e_service_timer - timer callback
6886 * @data: pointer to PF struct
6887 **/
6888static void i40e_service_timer(unsigned long data)
6889{
6890 struct i40e_pf *pf = (struct i40e_pf *)data;
6891
6892 mod_timer(&pf->service_timer,
6893 round_jiffies(jiffies + pf->service_timer_period));
6894 i40e_service_event_schedule(pf);
6895}
6896
6897/**
6898 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6899 * @vsi: the VSI being configured
6900 **/
6901static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6902{
6903 struct i40e_pf *pf = vsi->back;
6904
6905 switch (vsi->type) {
6906 case I40E_VSI_MAIN:
6907 vsi->alloc_queue_pairs = pf->num_lan_qps;
6908 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6909 I40E_REQ_DESCRIPTOR_MULTIPLE);
6910 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6911 vsi->num_q_vectors = pf->num_lan_msix;
6912 else
6913 vsi->num_q_vectors = 1;
6914
6915 break;
6916
6917 case I40E_VSI_FDIR:
6918 vsi->alloc_queue_pairs = 1;
6919 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6920 I40E_REQ_DESCRIPTOR_MULTIPLE);
6921 vsi->num_q_vectors = 1;
6922 break;
6923
6924 case I40E_VSI_VMDQ2:
6925 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6926 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6927 I40E_REQ_DESCRIPTOR_MULTIPLE);
6928 vsi->num_q_vectors = pf->num_vmdq_msix;
6929 break;
6930
6931 case I40E_VSI_SRIOV:
6932 vsi->alloc_queue_pairs = pf->num_vf_qps;
6933 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6934 I40E_REQ_DESCRIPTOR_MULTIPLE);
6935 break;
6936
38e00438
VD		 6937#ifdef I40E_FCOE
6938 case I40E_VSI_FCOE:
6939 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6940 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6941 I40E_REQ_DESCRIPTOR_MULTIPLE);
6942 vsi->num_q_vectors = pf->num_fcoe_msix;
6943 break;
6944
6945#endif /* I40E_FCOE */
41c445ff
JB		 6946 default:
6947 WARN_ON(1);
6948 return -ENODATA;
6949 }
6950
6951 return 0;
6952}
6953
f650a38b
ASJ		 6954/**
6955 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6956 * @type: VSI pointer
bc7d338f 6957 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6958 *
6959 * On error: returns error code (negative)
6960 * On success: returns 0
6961 **/
bc7d338f 6962static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6963{
6964 int size;
6965 int ret = 0;
6966
ac6c5e3d 6967 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6968 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6969 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6970 if (!vsi->tx_rings)
6971 return -ENOMEM;
f650a38b
ASJ		 6972 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6973
bc7d338f
ASJ		 6974 if (alloc_qvectors) {
6975 /* allocate memory for q_vector pointers */
f57e4fbd 6976 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6977 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6978 if (!vsi->q_vectors) {
6979 ret = -ENOMEM;
6980 goto err_vectors;
6981 }
f650a38b
ASJ		 6982 }
6983 return ret;
6984
6985err_vectors:
6986 kfree(vsi->tx_rings);
6987 return ret;
6988}
6989
41c445ff
JB		 6990/**
6991 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6992 * @pf: board private structure
6993 * @type: type of VSI
6994 *
6995 * On error: returns error code (negative)
6996 * On success: returns vsi index in PF (positive)
6997 **/
6998static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6999{
7000 int ret = -ENODEV;
7001 struct i40e_vsi *vsi;
7002 int vsi_idx;
7003 int i;
7004
7005 /* Need to protect the allocation of the VSIs at the PF level */
7006 mutex_lock(&pf->switch_mutex);
7007
7008 /* VSI list may be fragmented if VSI creation/destruction has
7009 * been happening. We can afford to do a quick scan to look
7010 * for any free VSIs in the list.
7011 *
7012 * find next empty vsi slot, looping back around if necessary
7013 */
7014 i = pf->next_vsi;
505682cd 7015 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7016 i++;
505682cd 7017 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7018 i = 0;
7019 while (i < pf->next_vsi && pf->vsi[i])
7020 i++;
7021 }
7022
505682cd 7023 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7024 vsi_idx = i; /* Found one! */
7025 } else {
7026 ret = -ENODEV;
493fb300 7027 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7028 }
7029 pf->next_vsi = ++i;
7030
7031 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7032 if (!vsi) {
7033 ret = -ENOMEM;
493fb300 7034 goto unlock_pf;
41c445ff
JB		 7035 }
7036 vsi->type = type;
7037 vsi->back = pf;
7038 set_bit(__I40E_DOWN, &vsi->state);
7039 vsi->flags = 0;
7040 vsi->idx = vsi_idx;
7041 vsi->rx_itr_setting = pf->rx_itr_default;
7042 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 7043 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7044 pf->rss_table_size : 64;
41c445ff
JB		 7045 vsi->netdev_registered = false;
7046 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7047 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7048 vsi->irqs_ready = false;
41c445ff 7049
9f65e15b
AD		 7050 ret = i40e_set_num_rings_in_vsi(vsi);
7051 if (ret)
7052 goto err_rings;
7053
bc7d338f 7054 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7055 if (ret)
9f65e15b 7056 goto err_rings;
493fb300 7057
41c445ff
JB		 7058 /* Setup default MSIX irq handler for VSI */
7059 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7060
7061 pf->vsi[vsi_idx] = vsi;
7062 ret = vsi_idx;
493fb300
AD		 7063 goto unlock_pf;
7064
9f65e15b 7065err_rings:
493fb300
AD		 7066 pf->next_vsi = i - 1;
7067 kfree(vsi);
7068unlock_pf:
41c445ff
JB		 7069 mutex_unlock(&pf->switch_mutex);
7070 return ret;
7071}
7072
f650a38b
ASJ		 7073/**
7074 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7075 * @type: VSI pointer
bc7d338f 7076 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7077 *
7078 * On error: returns error code (negative)
7079 * On success: returns 0
7080 **/
bc7d338f 7081static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7082{
7083 /* free the ring and vector containers */
bc7d338f
ASJ		 7084 if (free_qvectors) {
7085 kfree(vsi->q_vectors);
7086 vsi->q_vectors = NULL;
7087 }
f650a38b
ASJ		 7088 kfree(vsi->tx_rings);
7089 vsi->tx_rings = NULL;
7090 vsi->rx_rings = NULL;
7091}
7092
41c445ff
JB		 7093/**
7094 * i40e_vsi_clear - Deallocate the VSI provided
7095 * @vsi: the VSI being un-configured
7096 **/
7097static int i40e_vsi_clear(struct i40e_vsi *vsi)
7098{
7099 struct i40e_pf *pf;
7100
7101 if (!vsi)
7102 return 0;
7103
7104 if (!vsi->back)
7105 goto free_vsi;
7106 pf = vsi->back;
7107
7108 mutex_lock(&pf->switch_mutex);
7109 if (!pf->vsi[vsi->idx]) {
7110 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7111 vsi->idx, vsi->idx, vsi, vsi->type);
7112 goto unlock_vsi;
7113 }
7114
7115 if (pf->vsi[vsi->idx] != vsi) {
7116 dev_err(&pf->pdev->dev,
7117 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7118 pf->vsi[vsi->idx]->idx,
7119 pf->vsi[vsi->idx],
7120 pf->vsi[vsi->idx]->type,
7121 vsi->idx, vsi, vsi->type);
7122 goto unlock_vsi;
7123 }
7124
b40c82e6 7125 /* updates the PF for this cleared vsi */
41c445ff
JB		 7126 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7127 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7128
bc7d338f 7129 i40e_vsi_free_arrays(vsi, true);
493fb300 7130
41c445ff
JB		 7131 pf->vsi[vsi->idx] = NULL;
7132 if (vsi->idx < pf->next_vsi)
7133 pf->next_vsi = vsi->idx;
7134
7135unlock_vsi:
7136 mutex_unlock(&pf->switch_mutex);
7137free_vsi:
7138 kfree(vsi);
7139
7140 return 0;
7141}
7142
9f65e15b
AD		 7143/**
7144 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7145 * @vsi: the VSI being cleaned
7146 **/
be1d5eea 7147static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7148{
7149 int i;
7150
8e9dca53 7151 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7152 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7153 kfree_rcu(vsi->tx_rings[i], rcu);
7154 vsi->tx_rings[i] = NULL;
7155 vsi->rx_rings[i] = NULL;
7156 }
be1d5eea 7157 }
9f65e15b
AD		 7158}
7159
41c445ff
JB		 7160/**
7161 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7162 * @vsi: the VSI being configured
7163 **/
7164static int i40e_alloc_rings(struct i40e_vsi *vsi)
7165{
e7046ee1 7166 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7167 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7168 int i;
7169
41c445ff 7170 /* Set basic values in the rings to be used later during open() */
d7397644 7171 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7172 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7173 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7174 if (!tx_ring)
7175 goto err_out;
41c445ff
JB		 7176
7177 tx_ring->queue_index = i;
7178 tx_ring->reg_idx = vsi->base_queue + i;
7179 tx_ring->ring_active = false;
7180 tx_ring->vsi = vsi;
7181 tx_ring->netdev = vsi->netdev;
7182 tx_ring->dev = &pf->pdev->dev;
7183 tx_ring->count = vsi->num_desc;
7184 tx_ring->size = 0;
7185 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7186 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7187 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7188 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7189 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7190 vsi->tx_rings[i] = tx_ring;
41c445ff 7191
9f65e15b 7192 rx_ring = &tx_ring[1];
41c445ff
JB		 7193 rx_ring->queue_index = i;
7194 rx_ring->reg_idx = vsi->base_queue + i;
7195 rx_ring->ring_active = false;
7196 rx_ring->vsi = vsi;
7197 rx_ring->netdev = vsi->netdev;
7198 rx_ring->dev = &pf->pdev->dev;
7199 rx_ring->count = vsi->num_desc;
7200 rx_ring->size = 0;
7201 rx_ring->dcb_tc = 0;
7202 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7203 set_ring_16byte_desc_enabled(rx_ring);
7204 else
7205 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7206 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7207 }
7208
7209 return 0;
9f65e15b
AD		 7210
7211err_out:
7212 i40e_vsi_clear_rings(vsi);
7213 return -ENOMEM;
41c445ff
JB		 7214}
7215
7216/**
7217 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7218 * @pf: board private structure
7219 * @vectors: the number of MSI-X vectors to request
7220 *
7221 * Returns the number of vectors reserved, or error
7222 **/
7223static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7224{
7b37f376
AG		 7225 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7226 I40E_MIN_MSIX, vectors);
7227 if (vectors < 0) {
41c445ff 7228 dev_info(&pf->pdev->dev,
7b37f376 7229 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7230 vectors = 0;
7231 }
7232
7233 return vectors;
7234}
7235
7236/**
7237 * i40e_init_msix - Setup the MSIX capability
7238 * @pf: board private structure
7239 *
7240 * Work with the OS to set up the MSIX vectors needed.
7241 *
3b444399 7242 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7243 **/
7244static int i40e_init_msix(struct i40e_pf *pf)
7245{
41c445ff 7246 struct i40e_hw *hw = &pf->hw;
1e200e4a 7247 int vectors_left;
41c445ff 7248 int v_budget, i;
3b444399 7249 int v_actual;
41c445ff
JB		 7250
7251 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7252 return -ENODEV;
7253
7254 /* The number of vectors we'll request will be comprised of:
7255 * - Add 1 for "other" cause for Admin Queue events, etc.
7256 * - The number of LAN queue pairs
f8ff1464
ASJ		 7257 * - Queues being used for RSS.
7258 * We don't need as many as max_rss_size vectors.
7259 * use rss_size instead in the calculation since that
7260 * is governed by number of cpus in the system.
7261 * - assumes symmetric Tx/Rx pairing
41c445ff 7262 * - The number of VMDq pairs
38e00438
VD		 7263#ifdef I40E_FCOE
7264 * - The number of FCOE qps.
7265#endif
41c445ff
JB		 7266 * Once we count this up, try the request.
7267 *
7268 * If we can't get what we want, we'll simplify to nearly nothing
7269 * and try again. If that still fails, we punt.
7270 */
1e200e4a
SN		 7271 vectors_left = hw->func_caps.num_msix_vectors;
7272 v_budget = 0;
7273
7274 /* reserve one vector for miscellaneous handler */
7275 if (vectors_left) {
7276 v_budget++;
7277 vectors_left--;
7278 }
7279
7280 /* reserve vectors for the main PF traffic queues */
7281 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7282 vectors_left -= pf->num_lan_msix;
7283 v_budget += pf->num_lan_msix;
7284
7285 /* reserve one vector for sideband flow director */
7286 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7287 if (vectors_left) {
7288 v_budget++;
7289 vectors_left--;
7290 } else {
7291 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7292 }
7293 }
83840e4b 7294
38e00438 7295#ifdef I40E_FCOE
1e200e4a 7296 /* can we reserve enough for FCoE? */
38e00438 7297 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7298 if (!vectors_left)
7299 pf->num_fcoe_msix = 0;
7300 else if (vectors_left >= pf->num_fcoe_qps)
7301 pf->num_fcoe_msix = pf->num_fcoe_qps;
7302 else
7303 pf->num_fcoe_msix = 1;
38e00438 7304 v_budget += pf->num_fcoe_msix;
1e200e4a 7305 vectors_left -= pf->num_fcoe_msix;
38e00438 7306 }
1e200e4a 7307
38e00438 7308#endif
1e200e4a
SN		 7309 /* any vectors left over go for VMDq support */
7310 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7311 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7312 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7313
7314 /* if we're short on vectors for what's desired, we limit
7315 * the queues per vmdq. If this is still more than are
7316 * available, the user will need to change the number of
7317 * queues/vectors used by the PF later with the ethtool
7318 * channels command
7319 */
7320 if (vmdq_vecs < vmdq_vecs_wanted)
7321 pf->num_vmdq_qps = 1;
7322 pf->num_vmdq_msix = pf->num_vmdq_qps;
7323
7324 v_budget += vmdq_vecs;
7325 vectors_left -= vmdq_vecs;
7326 }
41c445ff
JB		 7327
7328 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7329 GFP_KERNEL);
7330 if (!pf->msix_entries)
7331 return -ENOMEM;
7332
7333 for (i = 0; i < v_budget; i++)
7334 pf->msix_entries[i].entry = i;
3b444399 7335 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7336
3b444399 7337 if (v_actual != v_budget) {
a34977ba
ASJ		 7338 /* If we have limited resources, we will start with no vectors
7339 * for the special features and then allocate vectors to some
7340 * of these features based on the policy and at the end disable
7341 * the features that did not get any vectors.
7342 */
38e00438
VD		 7343#ifdef I40E_FCOE
7344 pf->num_fcoe_qps = 0;
7345 pf->num_fcoe_msix = 0;
7346#endif
a34977ba
ASJ		 7347 pf->num_vmdq_msix = 0;
7348 }
7349
3b444399 7350 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7351 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7352 kfree(pf->msix_entries);
7353 pf->msix_entries = NULL;
7354 return -ENODEV;
7355
3b444399 7356 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7357 /* Adjust for minimal MSIX use */
41c445ff
JB		 7358 pf->num_vmdq_vsis = 0;
7359 pf->num_vmdq_qps = 0;
41c445ff
JB		 7360 pf->num_lan_qps = 1;
7361 pf->num_lan_msix = 1;
7362
3b444399
SN		 7363 } else if (v_actual != v_budget) {
7364 int vec;
7365
a34977ba 7366 /* reserve the misc vector */
3b444399 7367 vec = v_actual - 1;
a34977ba 7368
41c445ff
JB		 7369 /* Scale vector usage down */
7370 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7371 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7372 pf->num_vmdq_qps = 1;
7373 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7374
7375 /* partition out the remaining vectors */
7376 switch (vec) {
7377 case 2:
41c445ff
JB		 7378 pf->num_lan_msix = 1;
7379 break;
7380 case 3:
38e00438
VD		 7381#ifdef I40E_FCOE
7382 /* give one vector to FCoE */
7383 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7384 pf->num_lan_msix = 1;
7385 pf->num_fcoe_msix = 1;
7386 }
7387#else
41c445ff 7388 pf->num_lan_msix = 2;
38e00438 7389#endif
41c445ff
JB		 7390 break;
7391 default:
38e00438
VD		 7392#ifdef I40E_FCOE
7393 /* give one vector to FCoE */
7394 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7395 pf->num_fcoe_msix = 1;
7396 vec--;
7397 }
7398#endif
1e200e4a
SN		 7399 /* give the rest to the PF */
7400 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7401 break;
7402 }
7403 }
7404
a34977ba
ASJ		 7405 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7406 (pf->num_vmdq_msix == 0)) {
7407 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7408 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7409 }
38e00438
VD		 7410#ifdef I40E_FCOE
7411
7412 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7413 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7414 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7415 }
7416#endif
3b444399 7417 return v_actual;
41c445ff
JB		 7418}
7419
493fb300 7420/**
90e04070 7421 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7422 * @vsi: the VSI being configured
7423 * @v_idx: index of the vector in the vsi struct
7424 *
7425 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7426 **/
90e04070 7427static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7428{
7429 struct i40e_q_vector *q_vector;
7430
7431 /* allocate q_vector */
7432 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7433 if (!q_vector)
7434 return -ENOMEM;
7435
7436 q_vector->vsi = vsi;
7437 q_vector->v_idx = v_idx;
7438 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7439 if (vsi->netdev)
7440 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7441 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7442
cd0b6fa6
AD		 7443 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7444 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7445
493fb300
AD		 7446 /* tie q_vector and vsi together */
7447 vsi->q_vectors[v_idx] = q_vector;
7448
7449 return 0;
7450}
7451
41c445ff 7452/**
90e04070 7453 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7454 * @vsi: the VSI being configured
7455 *
7456 * We allocate one q_vector per queue interrupt. If allocation fails we
7457 * return -ENOMEM.
7458 **/
90e04070 7459static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7460{
7461 struct i40e_pf *pf = vsi->back;
7462 int v_idx, num_q_vectors;
493fb300 7463 int err;
41c445ff
JB		 7464
7465 /* if not MSIX, give the one vector only to the LAN VSI */
7466 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7467 num_q_vectors = vsi->num_q_vectors;
7468 else if (vsi == pf->vsi[pf->lan_vsi])
7469 num_q_vectors = 1;
7470 else
7471 return -EINVAL;
7472
41c445ff 7473 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7474 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7475 if (err)
7476 goto err_out;
41c445ff
JB		 7477 }
7478
7479 return 0;
493fb300
AD		 7480
7481err_out:
7482 while (v_idx--)
7483 i40e_free_q_vector(vsi, v_idx);
7484
7485 return err;
41c445ff
JB		 7486}
7487
7488/**
7489 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7490 * @pf: board private structure to initialize
7491 **/
c1147280 7492static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7493{
3b444399
SN		 7494 int vectors = 0;
7495 ssize_t size;
41c445ff
JB		 7496
7497 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7498 vectors = i40e_init_msix(pf);
7499 if (vectors < 0) {
60ea5f83 7500 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7501#ifdef I40E_FCOE
7502 I40E_FLAG_FCOE_ENABLED |
7503#endif
60ea5f83 7504 I40E_FLAG_RSS_ENABLED |
4d9b6043 7505 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7506 I40E_FLAG_SRIOV_ENABLED |
7507 I40E_FLAG_FD_SB_ENABLED |
7508 I40E_FLAG_FD_ATR_ENABLED |
7509 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7510
7511 /* rework the queue expectations without MSIX */
7512 i40e_determine_queue_usage(pf);
7513 }
7514 }
7515
7516 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7517 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7518 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7519 vectors = pci_enable_msi(pf->pdev);
7520 if (vectors < 0) {
7521 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7522 vectors);
41c445ff
JB		 7523 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7524 }
3b444399 7525 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7526 }
7527
958a3e3b 7528 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7529 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7530
3b444399
SN		 7531 /* set up vector assignment tracking */
7532 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7533 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7534 if (!pf->irq_pile) {
7535 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7536 return -ENOMEM;
7537 }
3b444399
SN		 7538 pf->irq_pile->num_entries = vectors;
7539 pf->irq_pile->search_hint = 0;
7540
c1147280 7541 /* track first vector for misc interrupts, ignore return */
3b444399 7542 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7543
7544 return 0;
41c445ff
JB		 7545}
7546
7547/**
7548 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7549 * @pf: board private structure
7550 *
7551 * This sets up the handler for MSIX 0, which is used to manage the
7552 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7553 * when in MSI or Legacy interrupt mode.
7554 **/
7555static int i40e_setup_misc_vector(struct i40e_pf *pf)
7556{
7557 struct i40e_hw *hw = &pf->hw;
7558 int err = 0;
7559
7560 /* Only request the irq if this is the first time through, and
7561 * not when we're rebuilding after a Reset
7562 */
7563 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7564 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7565 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7566 if (err) {
7567 dev_info(&pf->pdev->dev,
77fa28be 7568 "request_irq for %s failed: %d\n",
b294ac70 7569 pf->int_name, err);
41c445ff
JB		 7570 return -EFAULT;
7571 }
7572 }
7573
ab437b5a 7574 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7575
7576 /* associate no queues to the misc vector */
7577 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7578 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7579
7580 i40e_flush(hw);
7581
7582 i40e_irq_dynamic_enable_icr0(pf);
7583
7584 return err;
7585}
7586
7587/**
e25d00b8
ASJ		 7588 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7589 * @vsi: vsi structure
7590 * @seed: RSS hash seed
7591 **/
7592static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7593{
7594 struct i40e_aqc_get_set_rss_key_data rss_key;
7595 struct i40e_pf *pf = vsi->back;
7596 struct i40e_hw *hw = &pf->hw;
7597 bool pf_lut = false;
7598 u8 *rss_lut;
7599 int ret, i;
7600
7601 memset(&rss_key, 0, sizeof(rss_key));
7602 memcpy(&rss_key, seed, sizeof(rss_key));
7603
7604 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7605 if (!rss_lut)
7606 return -ENOMEM;
7607
7608 /* Populate the LUT with max no. of queues in round robin fashion */
7609 for (i = 0; i < vsi->rss_table_size; i++)
7610 rss_lut[i] = i % vsi->rss_size;
7611
7612 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7613 if (ret) {
7614 dev_info(&pf->pdev->dev,
7615 "Cannot set RSS key, err %s aq_err %s\n",
7616 i40e_stat_str(&pf->hw, ret),
7617 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7618 goto config_rss_aq_out;
e25d00b8
ASJ		 7619 }
7620
7621 if (vsi->type == I40E_VSI_MAIN)
7622 pf_lut = true;
7623
7624 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7625 vsi->rss_table_size);
7626 if (ret)
7627 dev_info(&pf->pdev->dev,
7628 "Cannot set RSS lut, err %s aq_err %s\n",
7629 i40e_stat_str(&pf->hw, ret),
7630 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7631
126b63d9
AS		 7632config_rss_aq_out:
7633 kfree(rss_lut);
e25d00b8
ASJ		 7634 return ret;
7635}
7636
7637/**
7638 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7639 * @vsi: VSI structure
7640 **/
7641static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7642{
7643 u8 seed[I40E_HKEY_ARRAY_SIZE];
7644 struct i40e_pf *pf = vsi->back;
7645
7646 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7647 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7648
7649 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7650 return i40e_config_rss_aq(vsi, seed);
7651
7652 return 0;
7653}
7654
7655/**
7656 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7657 * @pf: board private structure
e25d00b8 7658 * @seed: RSS hash seed
41c445ff 7659 **/
e25d00b8 7660static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7661{
66ddcffb 7662 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7663 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7664 u32 *seed_dw = (u32 *)seed;
7665 u32 current_queue = 0;
4617e8c0
ASJ		 7666 u32 lut = 0;
7667 int i, j;
41c445ff 7668
e25d00b8 7669 /* Fill out hash function seed */
41c445ff 7670 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7671 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7672
7673 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7674 lut = 0;
7675 for (j = 0; j < 4; j++) {
7676 if (current_queue == vsi->rss_size)
7677 current_queue = 0;
7678 lut |= ((current_queue) << (8 * j));
7679 current_queue++;
7680 }
7681 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7682 }
7683 i40e_flush(hw);
7684
7685 return 0;
7686}
7687
7688/**
7689 * i40e_config_rss - Prepare for RSS if used
7690 * @pf: board private structure
7691 **/
7692static int i40e_config_rss(struct i40e_pf *pf)
7693{
7694 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7695 u8 seed[I40E_HKEY_ARRAY_SIZE];
7696 struct i40e_hw *hw = &pf->hw;
7697 u32 reg_val;
7698 u64 hena;
7699
7700 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7701
7702 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7703 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7704 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7705 hena |= i40e_pf_get_default_rss_hena(pf);
7706
41c445ff
JB		 7707 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7708 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7709
66ddcffb
ASJ		 7710 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7711
e25d00b8 7712 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7713 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7714 reg_val = (pf->rss_table_size == 512) ?
7715 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7716 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7717 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7718
e25d00b8
ASJ		 7719 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7720 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7721 else
7722 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7723}
7724
f8ff1464
ASJ		 7725/**
7726 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7727 * @pf: board private structure
7728 * @queue_count: the requested queue count for rss.
7729 *
7730 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7731 * count which may be different from the requested queue count.
7732 **/
7733int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7734{
9a3bd2f1
ASJ		 7735 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7736 int new_rss_size;
7737
f8ff1464
ASJ		 7738 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7739 return 0;
7740
9a3bd2f1 7741 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7742
9a3bd2f1
ASJ		 7743 if (queue_count != vsi->num_queue_pairs) {
7744 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7745 i40e_prep_for_reset(pf);
7746
9a3bd2f1 7747 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7748
7749 i40e_reset_and_rebuild(pf, true);
7750 i40e_config_rss(pf);
7751 }
7752 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7753 return pf->rss_size;
7754}
7755
f4492db1
GR		 7756/**
7757 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7758 * @pf: board private structure
7759 **/
7760i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7761{
7762 i40e_status status;
7763 bool min_valid, max_valid;
7764 u32 max_bw, min_bw;
7765
7766 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7767 &min_valid, &max_valid);
7768
7769 if (!status) {
7770 if (min_valid)
7771 pf->npar_min_bw = min_bw;
7772 if (max_valid)
7773 pf->npar_max_bw = max_bw;
7774 }
7775
7776 return status;
7777}
7778
7779/**
7780 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7781 * @pf: board private structure
7782 **/
7783i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7784{
7785 struct i40e_aqc_configure_partition_bw_data bw_data;
7786 i40e_status status;
7787
b40c82e6 7788 /* Set the valid bit for this PF */
41a1d04b 7789 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7790 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7791 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7792
7793 /* Set the new bandwidths */
7794 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7795
7796 return status;
7797}
7798
7799/**
7800 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7801 * @pf: board private structure
7802 **/
7803i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7804{
7805 /* Commit temporary BW setting to permanent NVM image */
7806 enum i40e_admin_queue_err last_aq_status;
7807 i40e_status ret;
7808 u16 nvm_word;
7809
7810 if (pf->hw.partition_id != 1) {
7811 dev_info(&pf->pdev->dev,
7812 "Commit BW only works on partition 1! This is partition %d",
7813 pf->hw.partition_id);
7814 ret = I40E_NOT_SUPPORTED;
7815 goto bw_commit_out;
7816 }
7817
7818 /* Acquire NVM for read access */
7819 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7820 last_aq_status = pf->hw.aq.asq_last_status;
7821 if (ret) {
7822 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7823 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7824 i40e_stat_str(&pf->hw, ret),
7825 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7826 goto bw_commit_out;
7827 }
7828
7829 /* Read word 0x10 of NVM - SW compatibility word 1 */
7830 ret = i40e_aq_read_nvm(&pf->hw,
7831 I40E_SR_NVM_CONTROL_WORD,
7832 0x10, sizeof(nvm_word), &nvm_word,
7833 false, NULL);
7834 /* Save off last admin queue command status before releasing
7835 * the NVM
7836 */
7837 last_aq_status = pf->hw.aq.asq_last_status;
7838 i40e_release_nvm(&pf->hw);
7839 if (ret) {
f1c7e72e
SN		 7840 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7841 i40e_stat_str(&pf->hw, ret),
7842 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7843 goto bw_commit_out;
7844 }
7845
7846 /* Wait a bit for NVM release to complete */
7847 msleep(50);
7848
7849 /* Acquire NVM for write access */
7850 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7851 last_aq_status = pf->hw.aq.asq_last_status;
7852 if (ret) {
7853 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7854 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7855 i40e_stat_str(&pf->hw, ret),
7856 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7857 goto bw_commit_out;
7858 }
7859 /* Write it back out unchanged to initiate update NVM,
7860 * which will force a write of the shadow (alt) RAM to
7861 * the NVM - thus storing the bandwidth values permanently.
7862 */
7863 ret = i40e_aq_update_nvm(&pf->hw,
7864 I40E_SR_NVM_CONTROL_WORD,
7865 0x10, sizeof(nvm_word),
7866 &nvm_word, true, NULL);
7867 /* Save off last admin queue command status before releasing
7868 * the NVM
7869 */
7870 last_aq_status = pf->hw.aq.asq_last_status;
7871 i40e_release_nvm(&pf->hw);
7872 if (ret)
7873 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7874 "BW settings NOT SAVED, err %s aq_err %s\n",
7875 i40e_stat_str(&pf->hw, ret),
7876 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7877bw_commit_out:
7878
7879 return ret;
7880}
7881
41c445ff
JB		 7882/**
7883 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7884 * @pf: board private structure to initialize
7885 *
7886 * i40e_sw_init initializes the Adapter private data structure.
7887 * Fields are initialized based on PCI device information and
7888 * OS network device settings (MTU size).
7889 **/
7890static int i40e_sw_init(struct i40e_pf *pf)
7891{
7892 int err = 0;
7893 int size;
7894
7895 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7896 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7897 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7898 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7899 if (I40E_DEBUG_USER & debug)
7900 pf->hw.debug_mask = debug;
7901 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7902 I40E_DEFAULT_MSG_ENABLE);
7903 }
7904
7905 /* Set default capability flags */
7906 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7907 I40E_FLAG_MSI_ENABLED |
9ac77266 7908 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 7909 I40E_FLAG_MSIX_ENABLED;
7910
7911 if (iommu_present(&pci_bus_type))
7912 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7913 else
7914 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7915
ca99eb99
MW		 7916 /* Set default ITR */
7917 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7918 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7919
7134f9ce
JB		 7920 /* Depending on PF configurations, it is possible that the RSS
7921 * maximum might end up larger than the available queues
7922 */
41a1d04b 7923 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7924 pf->rss_size = 1;
5db4cb59 7925 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7926 pf->rss_size_max = min_t(int, pf->rss_size_max,
7927 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7928 if (pf->hw.func_caps.rss) {
7929 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7930 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7931 }
7932
2050bc65 7933 /* MFP mode enabled */
c78b953e 7934 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7935 pf->flags |= I40E_FLAG_MFP_ENABLED;
7936 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7937 if (i40e_get_npar_bw_setting(pf))
7938 dev_warn(&pf->pdev->dev,
7939 "Could not get NPAR bw settings\n");
7940 else
7941 dev_info(&pf->pdev->dev,
7942 "Min BW = %8.8x, Max BW = %8.8x\n",
7943 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7944 }
7945
cbf61325
ASJ		 7946 /* FW/NVM is not yet fixed in this regard */
7947 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7948 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7949 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7950 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 7951 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
7952 pf->hw.num_partitions > 1)
cbf61325 7953 dev_info(&pf->pdev->dev,
0b67584f 7954 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 7955 else
7956 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7957 pf->fdir_pf_filter_count =
7958 pf->hw.func_caps.fd_filters_guaranteed;
7959 pf->hw.fdir_shared_filter_count =
7960 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7961 }
7962
7963 if (pf->hw.func_caps.vmdq) {
41c445ff 7964 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 7965 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
41c445ff
JB		 7966 }
7967
38e00438 7968#ifdef I40E_FCOE
21364bcf 7969 i40e_init_pf_fcoe(pf);
38e00438
VD		 7970
7971#endif /* I40E_FCOE */
41c445ff 7972#ifdef CONFIG_PCI_IOV
ba252f13 7973 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7974 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7975 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7976 pf->num_req_vfs = min_t(int,
7977 pf->hw.func_caps.num_vfs,
7978 I40E_MAX_VF_COUNT);
7979 }
7980#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7981 if (pf->hw.mac.type == I40E_MAC_X722) {
7982 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7983 I40E_FLAG_128_QP_RSS_CAPABLE |
7984 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7985 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7986 I40E_FLAG_WB_ON_ITR_CAPABLE |
7987 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
7988 }
41c445ff
JB		 7989 pf->eeprom_version = 0xDEAD;
7990 pf->lan_veb = I40E_NO_VEB;
7991 pf->lan_vsi = I40E_NO_VSI;
7992
d1a8d275
ASJ		 7993 /* By default FW has this off for performance reasons */
7994 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
7995
41c445ff
JB		 7996 /* set up queue assignment tracking */
7997 size = sizeof(struct i40e_lump_tracking)
7998 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7999 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8000 if (!pf->qp_pile) {
8001 err = -ENOMEM;
8002 goto sw_init_done;
8003 }
8004 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8005 pf->qp_pile->search_hint = 0;
8006
327fe04b
ASJ		 8007 pf->tx_timeout_recovery_level = 1;
8008
41c445ff
JB		 8009 mutex_init(&pf->switch_mutex);
8010
c668a12c
GR		 8011 /* If NPAR is enabled nudge the Tx scheduler */
8012 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8013 i40e_set_npar_bw_setting(pf);
8014
41c445ff
JB		 8015sw_init_done:
8016 return err;
8017}
8018
7c3c288b
ASJ		 8019/**
8020 * i40e_set_ntuple - set the ntuple feature flag and take action
8021 * @pf: board private structure to initialize
8022 * @features: the feature set that the stack is suggesting
8023 *
8024 * returns a bool to indicate if reset needs to happen
8025 **/
8026bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8027{
8028 bool need_reset = false;
8029
8030 /* Check if Flow Director n-tuple support was enabled or disabled. If
8031 * the state changed, we need to reset.
8032 */
8033 if (features & NETIF_F_NTUPLE) {
8034 /* Enable filters and mark for reset */
8035 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8036 need_reset = true;
8037 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8038 } else {
8039 /* turn off filters, mark for reset and clear SW filter list */
8040 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8041 need_reset = true;
8042 i40e_fdir_filter_exit(pf);
8043 }
8044 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8045 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8046 /* reset fd counters */
8047 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8048 pf->fdir_pf_active_filters = 0;
8049 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8050 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8051 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8052 /* if ATR was auto disabled it can be re-enabled. */
8053 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8054 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8055 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8056 }
8057 return need_reset;
8058}
8059
41c445ff
JB		 8060/**
8061 * i40e_set_features - set the netdev feature flags
8062 * @netdev: ptr to the netdev being adjusted
8063 * @features: the feature set that the stack is suggesting
8064 **/
8065static int i40e_set_features(struct net_device *netdev,
8066 netdev_features_t features)
8067{
8068 struct i40e_netdev_priv *np = netdev_priv(netdev);
8069 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8070 struct i40e_pf *pf = vsi->back;
8071 bool need_reset;
41c445ff
JB		 8072
8073 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8074 i40e_vlan_stripping_enable(vsi);
8075 else
8076 i40e_vlan_stripping_disable(vsi);
8077
7c3c288b
ASJ		 8078 need_reset = i40e_set_ntuple(pf, features);
8079
8080 if (need_reset)
41a1d04b 8081 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8082
41c445ff
JB		 8083 return 0;
8084}
8085
a1c9a9d9
JK		 8086#ifdef CONFIG_I40E_VXLAN
8087/**
8088 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8089 * @pf: board private structure
8090 * @port: The UDP port to look up
8091 *
8092 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8093 **/
8094static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8095{
8096 u8 i;
8097
8098 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8099 if (pf->vxlan_ports[i] == port)
8100 return i;
8101 }
8102
8103 return i;
8104}
8105
8106/**
8107 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8108 * @netdev: This physical port's netdev
8109 * @sa_family: Socket Family that VXLAN is notifying us about
8110 * @port: New UDP port number that VXLAN started listening to
8111 **/
8112static void i40e_add_vxlan_port(struct net_device *netdev,
8113 sa_family_t sa_family, __be16 port)
8114{
8115 struct i40e_netdev_priv *np = netdev_priv(netdev);
8116 struct i40e_vsi *vsi = np->vsi;
8117 struct i40e_pf *pf = vsi->back;
8118 u8 next_idx;
8119 u8 idx;
8120
8121 if (sa_family == AF_INET6)
8122 return;
8123
8124 idx = i40e_get_vxlan_port_idx(pf, port);
8125
8126 /* Check if port already exists */
8127 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8128 netdev_info(netdev, "vxlan port %d already offloaded\n",
8129 ntohs(port));
a1c9a9d9
JK		 8130 return;
8131 }
8132
8133 /* Now check if there is space to add the new port */
8134 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8135
8136 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8137 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8138 ntohs(port));
8139 return;
8140 }
8141
8142 /* New port: add it and mark its index in the bitmap */
8143 pf->vxlan_ports[next_idx] = port;
41a1d04b 8144 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8145 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8146}
8147
8148/**
8149 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8150 * @netdev: This physical port's netdev
8151 * @sa_family: Socket Family that VXLAN is notifying us about
8152 * @port: UDP port number that VXLAN stopped listening to
8153 **/
8154static void i40e_del_vxlan_port(struct net_device *netdev,
8155 sa_family_t sa_family, __be16 port)
8156{
8157 struct i40e_netdev_priv *np = netdev_priv(netdev);
8158 struct i40e_vsi *vsi = np->vsi;
8159 struct i40e_pf *pf = vsi->back;
8160 u8 idx;
8161
8162 if (sa_family == AF_INET6)
8163 return;
8164
8165 idx = i40e_get_vxlan_port_idx(pf, port);
8166
8167 /* Check if port already exists */
8168 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8169 /* if port exists, set it to 0 (mark for deletion)
8170 * and make it pending
8171 */
8172 pf->vxlan_ports[idx] = 0;
41a1d04b 8173 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8174 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8175 } else {
c22c06c8 8176 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8177 ntohs(port));
8178 }
8179}
8180
8181#endif
1f224ad2 8182static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8183 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8184{
8185 struct i40e_netdev_priv *np = netdev_priv(netdev);
8186 struct i40e_pf *pf = np->vsi->back;
8187 struct i40e_hw *hw = &pf->hw;
8188
8189 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8190 return -EOPNOTSUPP;
8191
8192 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8193 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8194
8195 return 0;
8196}
8197
2f90ade6
JB		 8198/**
8199 * i40e_ndo_fdb_add - add an entry to the hardware database
8200 * @ndm: the input from the stack
8201 * @tb: pointer to array of nladdr (unused)
8202 * @dev: the net device pointer
8203 * @addr: the MAC address entry being added
8204 * @flags: instructions from stack about fdb operation
8205 */
4ba0dea5
GR		 8206static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8207 struct net_device *dev,
f6f6424b 8208 const unsigned char *addr, u16 vid,
4ba0dea5 8209 u16 flags)
4ba0dea5
GR		 8210{
8211 struct i40e_netdev_priv *np = netdev_priv(dev);
8212 struct i40e_pf *pf = np->vsi->back;
8213 int err = 0;
8214
8215 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8216 return -EOPNOTSUPP;
8217
65891fea
OG		 8218 if (vid) {
8219 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8220 return -EINVAL;
8221 }
8222
4ba0dea5
GR		 8223 /* Hardware does not support aging addresses so if a
8224 * ndm_state is given only allow permanent addresses
8225 */
8226 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8227 netdev_info(dev, "FDB only supports static addresses\n");
8228 return -EINVAL;
8229 }
8230
8231 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8232 err = dev_uc_add_excl(dev, addr);
8233 else if (is_multicast_ether_addr(addr))
8234 err = dev_mc_add_excl(dev, addr);
8235 else
8236 err = -EINVAL;
8237
8238 /* Only return duplicate errors if NLM_F_EXCL is set */
8239 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8240 err = 0;
8241
8242 return err;
8243}
8244
51616018
NP		 8245/**
8246 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8247 * @dev: the netdev being configured
8248 * @nlh: RTNL message
8249 *
8250 * Inserts a new hardware bridge if not already created and
8251 * enables the bridging mode requested (VEB or VEPA). If the
8252 * hardware bridge has already been inserted and the request
8253 * is to change the mode then that requires a PF reset to
8254 * allow rebuild of the components with required hardware
8255 * bridge mode enabled.
8256 **/
8257static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8258 struct nlmsghdr *nlh,
8259 u16 flags)
51616018
NP		 8260{
8261 struct i40e_netdev_priv *np = netdev_priv(dev);
8262 struct i40e_vsi *vsi = np->vsi;
8263 struct i40e_pf *pf = vsi->back;
8264 struct i40e_veb *veb = NULL;
8265 struct nlattr *attr, *br_spec;
8266 int i, rem;
8267
8268 /* Only for PF VSI for now */
8269 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8270 return -EOPNOTSUPP;
8271
8272 /* Find the HW bridge for PF VSI */
8273 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8274 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8275 veb = pf->veb[i];
8276 }
8277
8278 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8279
8280 nla_for_each_nested(attr, br_spec, rem) {
8281 __u16 mode;
8282
8283 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8284 continue;
8285
8286 mode = nla_get_u16(attr);
8287 if ((mode != BRIDGE_MODE_VEPA) &&
8288 (mode != BRIDGE_MODE_VEB))
8289 return -EINVAL;
8290
8291 /* Insert a new HW bridge */
8292 if (!veb) {
8293 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8294 vsi->tc_config.enabled_tc);
8295 if (veb) {
8296 veb->bridge_mode = mode;
8297 i40e_config_bridge_mode(veb);
8298 } else {
8299 /* No Bridge HW offload available */
8300 return -ENOENT;
8301 }
8302 break;
8303 } else if (mode != veb->bridge_mode) {
8304 /* Existing HW bridge but different mode needs reset */
8305 veb->bridge_mode = mode;
fc60861e
ASJ		 8306 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8307 if (mode == BRIDGE_MODE_VEB)
8308 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8309 else
8310 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8311 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8312 break;
8313 }
8314 }
8315
8316 return 0;
8317}
8318
8319/**
8320 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8321 * @skb: skb buff
8322 * @pid: process id
8323 * @seq: RTNL message seq #
8324 * @dev: the netdev being configured
8325 * @filter_mask: unused
d4b2f9fe 8326 * @nlflags: netlink flags passed in
51616018
NP		 8327 *
8328 * Return the mode in which the hardware bridge is operating in
8329 * i.e VEB or VEPA.
8330 **/
51616018
NP		 8331static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8332 struct net_device *dev,
9f4ffc44
CW		 8333 u32 __always_unused filter_mask,
8334 int nlflags)
51616018
NP		 8335{
8336 struct i40e_netdev_priv *np = netdev_priv(dev);
8337 struct i40e_vsi *vsi = np->vsi;
8338 struct i40e_pf *pf = vsi->back;
8339 struct i40e_veb *veb = NULL;
8340 int i;
8341
8342 /* Only for PF VSI for now */
8343 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8344 return -EOPNOTSUPP;
8345
8346 /* Find the HW bridge for the PF VSI */
8347 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8348 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8349 veb = pf->veb[i];
8350 }
8351
8352 if (!veb)
8353 return 0;
8354
46c264da 8355 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8356 nlflags, 0, 0, filter_mask, NULL);
51616018 8357}
51616018 8358
f44a75e2
JS		 8359#define I40E_MAX_TUNNEL_HDR_LEN 80
8360/**
8361 * i40e_features_check - Validate encapsulated packet conforms to limits
8362 * @skb: skb buff
8363 * @netdev: This physical port's netdev
8364 * @features: Offload features that the stack believes apply
8365 **/
8366static netdev_features_t i40e_features_check(struct sk_buff *skb,
8367 struct net_device *dev,
8368 netdev_features_t features)
8369{
8370 if (skb->encapsulation &&
8371 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8372 I40E_MAX_TUNNEL_HDR_LEN))
8373 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8374
8375 return features;
8376}
8377
37a2973a 8378static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8379 .ndo_open = i40e_open,
8380 .ndo_stop = i40e_close,
8381 .ndo_start_xmit = i40e_lan_xmit_frame,
8382 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8383 .ndo_set_rx_mode = i40e_set_rx_mode,
8384 .ndo_validate_addr = eth_validate_addr,
8385 .ndo_set_mac_address = i40e_set_mac,
8386 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8387 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8388 .ndo_tx_timeout = i40e_tx_timeout,
8389 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8390 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8391#ifdef CONFIG_NET_POLL_CONTROLLER
8392 .ndo_poll_controller = i40e_netpoll,
8393#endif
8394 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8395#ifdef I40E_FCOE
8396 .ndo_fcoe_enable = i40e_fcoe_enable,
8397 .ndo_fcoe_disable = i40e_fcoe_disable,
8398#endif
41c445ff
JB		 8399 .ndo_set_features = i40e_set_features,
8400 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8401 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8402 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8403 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8404 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8405 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8406#ifdef CONFIG_I40E_VXLAN
8407 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8408 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8409#endif
1f224ad2 8410 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8411 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8412 .ndo_features_check = i40e_features_check,
51616018
NP		 8413 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8414 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8415};
8416
8417/**
8418 * i40e_config_netdev - Setup the netdev flags
8419 * @vsi: the VSI being configured
8420 *
8421 * Returns 0 on success, negative value on failure
8422 **/
8423static int i40e_config_netdev(struct i40e_vsi *vsi)
8424{
1a10370a 8425 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8426 struct i40e_pf *pf = vsi->back;
8427 struct i40e_hw *hw = &pf->hw;
8428 struct i40e_netdev_priv *np;
8429 struct net_device *netdev;
8430 u8 mac_addr[ETH_ALEN];
8431 int etherdev_size;
8432
8433 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8434 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8435 if (!netdev)
8436 return -ENOMEM;
8437
8438 vsi->netdev = netdev;
8439 np = netdev_priv(netdev);
8440 np->vsi = vsi;
8441
d70e941b 8442 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8443 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8444 NETIF_F_TSO;
41c445ff
JB		 8445
8446 netdev->features = NETIF_F_SG |
8447 NETIF_F_IP_CSUM |
8448 NETIF_F_SCTP_CSUM |
8449 NETIF_F_HIGHDMA |
8450 NETIF_F_GSO_UDP_TUNNEL |
8451 NETIF_F_HW_VLAN_CTAG_TX |
8452 NETIF_F_HW_VLAN_CTAG_RX |
8453 NETIF_F_HW_VLAN_CTAG_FILTER |
8454 NETIF_F_IPV6_CSUM |
8455 NETIF_F_TSO |
059dab69 8456 NETIF_F_TSO_ECN |
41c445ff
JB		 8457 NETIF_F_TSO6 |
8458 NETIF_F_RXCSUM |
8459 NETIF_F_RXHASH |
8460 0;
8461
2e86a0b6
ASJ		 8462 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8463 netdev->features |= NETIF_F_NTUPLE;
8464
41c445ff
JB		 8465 /* copy netdev features into list of user selectable features */
8466 netdev->hw_features |= netdev->features;
8467
8468 if (vsi->type == I40E_VSI_MAIN) {
8469 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8470 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8471 /* The following steps are necessary to prevent reception
8472 * of tagged packets - some older NVM configurations load a
8473 * default a MAC-VLAN filter that accepts any tagged packet
8474 * which must be replaced by a normal filter.
8c27d42e 8475 */
30650cc5
SN		 8476 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8477 i40e_add_filter(vsi, mac_addr,
8478 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8479 } else {
8480 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8481 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8482 pf->vsi[pf->lan_vsi]->netdev->name);
8483 random_ether_addr(mac_addr);
8484 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8485 }
1a10370a 8486 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8487
9a173901
GR		 8488 ether_addr_copy(netdev->dev_addr, mac_addr);
8489 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8490 /* vlan gets same features (except vlan offload)
8491 * after any tweaks for specific VSI types
8492 */
8493 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8494 NETIF_F_HW_VLAN_CTAG_RX |
8495 NETIF_F_HW_VLAN_CTAG_FILTER);
8496 netdev->priv_flags |= IFF_UNICAST_FLT;
8497 netdev->priv_flags |= IFF_SUPP_NOFCS;
8498 /* Setup netdev TC information */
8499 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8500
8501 netdev->netdev_ops = &i40e_netdev_ops;
8502 netdev->watchdog_timeo = 5 * HZ;
8503 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8504#ifdef I40E_FCOE
8505 i40e_fcoe_config_netdev(netdev, vsi);
8506#endif
41c445ff
JB		 8507
8508 return 0;
8509}
8510
8511/**
8512 * i40e_vsi_delete - Delete a VSI from the switch
8513 * @vsi: the VSI being removed
8514 *
8515 * Returns 0 on success, negative value on failure
8516 **/
8517static void i40e_vsi_delete(struct i40e_vsi *vsi)
8518{
8519 /* remove default VSI is not allowed */
8520 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8521 return;
8522
41c445ff 8523 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8524}
8525
51616018
NP		 8526/**
8527 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8528 * @vsi: the VSI being queried
8529 *
8530 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8531 **/
8532int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8533{
8534 struct i40e_veb *veb;
8535 struct i40e_pf *pf = vsi->back;
8536
8537 /* Uplink is not a bridge so default to VEB */
8538 if (vsi->veb_idx == I40E_NO_VEB)
8539 return 1;
8540
8541 veb = pf->veb[vsi->veb_idx];
8542 /* Uplink is a bridge in VEPA mode */
8543 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8544 return 0;
8545
8546 /* Uplink is a bridge in VEB mode */
8547 return 1;
8548}
8549
41c445ff
JB		 8550/**
8551 * i40e_add_vsi - Add a VSI to the switch
8552 * @vsi: the VSI being configured
8553 *
8554 * This initializes a VSI context depending on the VSI type to be added and
8555 * passes it down to the add_vsi aq command.
8556 **/
8557static int i40e_add_vsi(struct i40e_vsi *vsi)
8558{
8559 int ret = -ENODEV;
8560 struct i40e_mac_filter *f, *ftmp;
8561 struct i40e_pf *pf = vsi->back;
8562 struct i40e_hw *hw = &pf->hw;
8563 struct i40e_vsi_context ctxt;
8564 u8 enabled_tc = 0x1; /* TC0 enabled */
8565 int f_count = 0;
8566
8567 memset(&ctxt, 0, sizeof(ctxt));
8568 switch (vsi->type) {
8569 case I40E_VSI_MAIN:
8570 /* The PF's main VSI is already setup as part of the
8571 * device initialization, so we'll not bother with
8572 * the add_vsi call, but we will retrieve the current
8573 * VSI context.
8574 */
8575 ctxt.seid = pf->main_vsi_seid;
8576 ctxt.pf_num = pf->hw.pf_id;
8577 ctxt.vf_num = 0;
8578 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8579 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8580 if (ret) {
8581 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8582 "couldn't get PF vsi config, err %s aq_err %s\n",
8583 i40e_stat_str(&pf->hw, ret),
8584 i40e_aq_str(&pf->hw,
8585 pf->hw.aq.asq_last_status));
41c445ff
JB		 8586 return -ENOENT;
8587 }
1a2f6248 8588 vsi->info = ctxt.info;
41c445ff
JB		 8589 vsi->info.valid_sections = 0;
8590
8591 vsi->seid = ctxt.seid;
8592 vsi->id = ctxt.vsi_number;
8593
8594 enabled_tc = i40e_pf_get_tc_map(pf);
8595
8596 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8597 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8598 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8599 memset(&ctxt, 0, sizeof(ctxt));
8600 ctxt.seid = pf->main_vsi_seid;
8601 ctxt.pf_num = pf->hw.pf_id;
8602 ctxt.vf_num = 0;
8603 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8604 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8605 if (ret) {
8606 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8607 "update vsi failed, err %s aq_err %s\n",
8608 i40e_stat_str(&pf->hw, ret),
8609 i40e_aq_str(&pf->hw,
8610 pf->hw.aq.asq_last_status));
41c445ff
JB		 8611 ret = -ENOENT;
8612 goto err;
8613 }
8614 /* update the local VSI info queue map */
8615 i40e_vsi_update_queue_map(vsi, &ctxt);
8616 vsi->info.valid_sections = 0;
8617 } else {
8618 /* Default/Main VSI is only enabled for TC0
8619 * reconfigure it to enable all TCs that are
8620 * available on the port in SFP mode.
63d7e5a4
NP		 8621 * For MFP case the iSCSI PF would use this
8622 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8623 */
8624 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8625 if (ret) {
8626 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8627 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8628 enabled_tc,
8629 i40e_stat_str(&pf->hw, ret),
8630 i40e_aq_str(&pf->hw,
8631 pf->hw.aq.asq_last_status));
41c445ff
JB		 8632 ret = -ENOENT;
8633 }
8634 }
8635 break;
8636
8637 case I40E_VSI_FDIR:
cbf61325
ASJ		 8638 ctxt.pf_num = hw->pf_id;
8639 ctxt.vf_num = 0;
8640 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8641 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8642 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8643 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8644 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8645 ctxt.info.valid_sections |=
fc60861e 8646 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8647 ctxt.info.switch_id =
fc60861e 8648 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8649 }
41c445ff 8650 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8651 break;
8652
8653 case I40E_VSI_VMDQ2:
8654 ctxt.pf_num = hw->pf_id;
8655 ctxt.vf_num = 0;
8656 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8657 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8658 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8659
41c445ff
JB		 8660 /* This VSI is connected to VEB so the switch_id
8661 * should be set to zero by default.
8662 */
51616018
NP		 8663 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8664 ctxt.info.valid_sections |=
8665 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8666 ctxt.info.switch_id =
8667 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8668 }
41c445ff
JB		 8669
8670 /* Setup the VSI tx/rx queue map for TC0 only for now */
8671 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8672 break;
8673
8674 case I40E_VSI_SRIOV:
8675 ctxt.pf_num = hw->pf_id;
8676 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8677 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8678 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8679 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8680
41c445ff
JB		 8681 /* This VSI is connected to VEB so the switch_id
8682 * should be set to zero by default.
8683 */
51616018
NP		 8684 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8685 ctxt.info.valid_sections |=
8686 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8687 ctxt.info.switch_id =
8688 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8689 }
41c445ff
JB		 8690
8691 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8692 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8693 if (pf->vf[vsi->vf_id].spoofchk) {
8694 ctxt.info.valid_sections |=
8695 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8696 ctxt.info.sec_flags |=
8697 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8698 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8699 }
41c445ff
JB		 8700 /* Setup the VSI tx/rx queue map for TC0 only for now */
8701 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8702 break;
8703
38e00438
VD		 8704#ifdef I40E_FCOE
8705 case I40E_VSI_FCOE:
8706 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8707 if (ret) {
8708 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8709 return ret;
8710 }
8711 break;
8712
8713#endif /* I40E_FCOE */
41c445ff
JB		 8714 default:
8715 return -ENODEV;
8716 }
8717
8718 if (vsi->type != I40E_VSI_MAIN) {
8719 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8720 if (ret) {
8721 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8722 "add vsi failed, err %s aq_err %s\n",
8723 i40e_stat_str(&pf->hw, ret),
8724 i40e_aq_str(&pf->hw,
8725 pf->hw.aq.asq_last_status));
41c445ff
JB		 8726 ret = -ENOENT;
8727 goto err;
8728 }
1a2f6248 8729 vsi->info = ctxt.info;
41c445ff
JB		 8730 vsi->info.valid_sections = 0;
8731 vsi->seid = ctxt.seid;
8732 vsi->id = ctxt.vsi_number;
8733 }
8734
8735 /* If macvlan filters already exist, force them to get loaded */
8736 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8737 f->changed = true;
8738 f_count++;
6252c7e4
SN		 8739
8740 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8741 struct i40e_aqc_remove_macvlan_element_data element;
8742
8743 memset(&element, 0, sizeof(element));
8744 ether_addr_copy(element.mac_addr, f->macaddr);
8745 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8746 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8747 &element, 1, NULL);
8748 if (ret) {
8749 /* some older FW has a different default */
8750 element.flags |=
8751 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8752 i40e_aq_remove_macvlan(hw, vsi->seid,
8753 &element, 1, NULL);
8754 }
8755
8756 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8757 I40E_AQC_WRITE_TYPE_LAA_WOL,
8758 f->macaddr, NULL);
8759 }
41c445ff
JB		 8760 }
8761 if (f_count) {
8762 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8763 pf->flags |= I40E_FLAG_FILTER_SYNC;
8764 }
8765
8766 /* Update VSI BW information */
8767 ret = i40e_vsi_get_bw_info(vsi);
8768 if (ret) {
8769 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8770 "couldn't get vsi bw info, err %s aq_err %s\n",
8771 i40e_stat_str(&pf->hw, ret),
8772 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8773 /* VSI is already added so not tearing that up */
8774 ret = 0;
8775 }
8776
8777err:
8778 return ret;
8779}
8780
8781/**
8782 * i40e_vsi_release - Delete a VSI and free its resources
8783 * @vsi: the VSI being removed
8784 *
8785 * Returns 0 on success or < 0 on error
8786 **/
8787int i40e_vsi_release(struct i40e_vsi *vsi)
8788{
8789 struct i40e_mac_filter *f, *ftmp;
8790 struct i40e_veb *veb = NULL;
8791 struct i40e_pf *pf;
8792 u16 uplink_seid;
8793 int i, n;
8794
8795 pf = vsi->back;
8796
8797 /* release of a VEB-owner or last VSI is not allowed */
8798 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8799 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8800 vsi->seid, vsi->uplink_seid);
8801 return -ENODEV;
8802 }
8803 if (vsi == pf->vsi[pf->lan_vsi] &&
8804 !test_bit(__I40E_DOWN, &pf->state)) {
8805 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8806 return -ENODEV;
8807 }
8808
8809 uplink_seid = vsi->uplink_seid;
8810 if (vsi->type != I40E_VSI_SRIOV) {
8811 if (vsi->netdev_registered) {
8812 vsi->netdev_registered = false;
8813 if (vsi->netdev) {
8814 /* results in a call to i40e_close() */
8815 unregister_netdev(vsi->netdev);
41c445ff
JB		 8816 }
8817 } else {
90ef8d47 8818 i40e_vsi_close(vsi);
41c445ff
JB		 8819 }
8820 i40e_vsi_disable_irq(vsi);
8821 }
8822
8823 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8824 i40e_del_filter(vsi, f->macaddr, f->vlan,
8825 f->is_vf, f->is_netdev);
30e2561b 8826 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 8827
8828 i40e_vsi_delete(vsi);
8829 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8830 if (vsi->netdev) {
8831 free_netdev(vsi->netdev);
8832 vsi->netdev = NULL;
8833 }
41c445ff
JB		 8834 i40e_vsi_clear_rings(vsi);
8835 i40e_vsi_clear(vsi);
8836
8837 /* If this was the last thing on the VEB, except for the
8838 * controlling VSI, remove the VEB, which puts the controlling
8839 * VSI onto the next level down in the switch.
8840 *
8841 * Well, okay, there's one more exception here: don't remove
8842 * the orphan VEBs yet. We'll wait for an explicit remove request
8843 * from up the network stack.
8844 */
505682cd 8845 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8846 if (pf->vsi[i] &&
8847 pf->vsi[i]->uplink_seid == uplink_seid &&
8848 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8849 n++; /* count the VSIs */
8850 }
8851 }
8852 for (i = 0; i < I40E_MAX_VEB; i++) {
8853 if (!pf->veb[i])
8854 continue;
8855 if (pf->veb[i]->uplink_seid == uplink_seid)
8856 n++; /* count the VEBs */
8857 if (pf->veb[i]->seid == uplink_seid)
8858 veb = pf->veb[i];
8859 }
8860 if (n == 0 && veb && veb->uplink_seid != 0)
8861 i40e_veb_release(veb);
8862
8863 return 0;
8864}
8865
8866/**
8867 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8868 * @vsi: ptr to the VSI
8869 *
8870 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8871 * corresponding SW VSI structure and initializes num_queue_pairs for the
8872 * newly allocated VSI.
8873 *
8874 * Returns 0 on success or negative on failure
8875 **/
8876static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8877{
8878 int ret = -ENOENT;
8879 struct i40e_pf *pf = vsi->back;
8880
493fb300 8881 if (vsi->q_vectors[0]) {
41c445ff
JB		 8882 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8883 vsi->seid);
8884 return -EEXIST;
8885 }
8886
8887 if (vsi->base_vector) {
f29eaa3d 8888 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8889 vsi->seid, vsi->base_vector);
8890 return -EEXIST;
8891 }
8892
90e04070 8893 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8894 if (ret) {
8895 dev_info(&pf->pdev->dev,
8896 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8897 vsi->num_q_vectors, vsi->seid, ret);
8898 vsi->num_q_vectors = 0;
8899 goto vector_setup_out;
8900 }
8901
26cdc443
ASJ		 8902 /* In Legacy mode, we do not have to get any other vector since we
8903 * piggyback on the misc/ICR0 for queue interrupts.
8904 */
8905 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
8906 return ret;
958a3e3b
SN		 8907 if (vsi->num_q_vectors)
8908 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8909 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8910 if (vsi->base_vector < 0) {
8911 dev_info(&pf->pdev->dev,
049a2be8
SN		 8912 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8913 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8914 i40e_vsi_free_q_vectors(vsi);
8915 ret = -ENOENT;
8916 goto vector_setup_out;
8917 }
8918
8919vector_setup_out:
8920 return ret;
8921}
8922
bc7d338f
ASJ		 8923/**
8924 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8925 * @vsi: pointer to the vsi.
8926 *
8927 * This re-allocates a vsi's queue resources.
8928 *
8929 * Returns pointer to the successfully allocated and configured VSI sw struct
8930 * on success, otherwise returns NULL on failure.
8931 **/
8932static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8933{
8934 struct i40e_pf *pf = vsi->back;
8935 u8 enabled_tc;
8936 int ret;
8937
8938 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8939 i40e_vsi_clear_rings(vsi);
8940
8941 i40e_vsi_free_arrays(vsi, false);
8942 i40e_set_num_rings_in_vsi(vsi);
8943 ret = i40e_vsi_alloc_arrays(vsi, false);
8944 if (ret)
8945 goto err_vsi;
8946
8947 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8948 if (ret < 0) {
049a2be8 8949 dev_info(&pf->pdev->dev,
f1c7e72e 8950 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8951 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8952 goto err_vsi;
8953 }
8954 vsi->base_queue = ret;
8955
8956 /* Update the FW view of the VSI. Force a reset of TC and queue
8957 * layout configurations.
8958 */
8959 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8960 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8961 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8962 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8963
8964 /* assign it some queues */
8965 ret = i40e_alloc_rings(vsi);
8966 if (ret)
8967 goto err_rings;
8968
8969 /* map all of the rings to the q_vectors */
8970 i40e_vsi_map_rings_to_vectors(vsi);
8971 return vsi;
8972
8973err_rings:
8974 i40e_vsi_free_q_vectors(vsi);
8975 if (vsi->netdev_registered) {
8976 vsi->netdev_registered = false;
8977 unregister_netdev(vsi->netdev);
8978 free_netdev(vsi->netdev);
8979 vsi->netdev = NULL;
8980 }
8981 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8982err_vsi:
8983 i40e_vsi_clear(vsi);
8984 return NULL;
8985}
8986
41c445ff
JB		 8987/**
8988 * i40e_vsi_setup - Set up a VSI by a given type
8989 * @pf: board private structure
8990 * @type: VSI type
8991 * @uplink_seid: the switch element to link to
8992 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8993 *
8994 * This allocates the sw VSI structure and its queue resources, then add a VSI
8995 * to the identified VEB.
8996 *
8997 * Returns pointer to the successfully allocated and configure VSI sw struct on
8998 * success, otherwise returns NULL on failure.
8999 **/
9000struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9001 u16 uplink_seid, u32 param1)
9002{
9003 struct i40e_vsi *vsi = NULL;
9004 struct i40e_veb *veb = NULL;
9005 int ret, i;
9006 int v_idx;
9007
9008 /* The requested uplink_seid must be either
9009 * - the PF's port seid
9010 * no VEB is needed because this is the PF
9011 * or this is a Flow Director special case VSI
9012 * - seid of an existing VEB
9013 * - seid of a VSI that owns an existing VEB
9014 * - seid of a VSI that doesn't own a VEB
9015 * a new VEB is created and the VSI becomes the owner
9016 * - seid of the PF VSI, which is what creates the first VEB
9017 * this is a special case of the previous
9018 *
9019 * Find which uplink_seid we were given and create a new VEB if needed
9020 */
9021 for (i = 0; i < I40E_MAX_VEB; i++) {
9022 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9023 veb = pf->veb[i];
9024 break;
9025 }
9026 }
9027
9028 if (!veb && uplink_seid != pf->mac_seid) {
9029
505682cd 9030 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9031 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9032 vsi = pf->vsi[i];
9033 break;
9034 }
9035 }
9036 if (!vsi) {
9037 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9038 uplink_seid);
9039 return NULL;
9040 }
9041
9042 if (vsi->uplink_seid == pf->mac_seid)
9043 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9044 vsi->tc_config.enabled_tc);
9045 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9046 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9047 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9048 if (veb) {
9049 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9050 dev_info(&vsi->back->pdev->dev,
fb43201f 9051 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9052 return NULL;
9053 }
fa11cb3d
ASJ		 9054 /* We come up by default in VEPA mode if SRIOV is not
9055 * already enabled, in which case we can't force VEPA
9056 * mode.
9057 */
9058 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9059 veb->bridge_mode = BRIDGE_MODE_VEPA;
9060 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9061 }
51616018 9062 i40e_config_bridge_mode(veb);
79c21a82 9063 }
41c445ff
JB		 9064 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9065 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9066 veb = pf->veb[i];
9067 }
9068 if (!veb) {
9069 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9070 return NULL;
9071 }
9072
9073 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9074 uplink_seid = veb->seid;
9075 }
9076
9077 /* get vsi sw struct */
9078 v_idx = i40e_vsi_mem_alloc(pf, type);
9079 if (v_idx < 0)
9080 goto err_alloc;
9081 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9082 if (!vsi)
9083 goto err_alloc;
41c445ff
JB		 9084 vsi->type = type;
9085 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9086
9087 if (type == I40E_VSI_MAIN)
9088 pf->lan_vsi = v_idx;
9089 else if (type == I40E_VSI_SRIOV)
9090 vsi->vf_id = param1;
9091 /* assign it some queues */
cbf61325
ASJ		 9092 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9093 vsi->idx);
41c445ff 9094 if (ret < 0) {
049a2be8
SN		 9095 dev_info(&pf->pdev->dev,
9096 "failed to get tracking for %d queues for VSI %d err=%d\n",
9097 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9098 goto err_vsi;
9099 }
9100 vsi->base_queue = ret;
9101
9102 /* get a VSI from the hardware */
9103 vsi->uplink_seid = uplink_seid;
9104 ret = i40e_add_vsi(vsi);
9105 if (ret)
9106 goto err_vsi;
9107
9108 switch (vsi->type) {
9109 /* setup the netdev if needed */
9110 case I40E_VSI_MAIN:
9111 case I40E_VSI_VMDQ2:
38e00438 9112 case I40E_VSI_FCOE:
41c445ff
JB		 9113 ret = i40e_config_netdev(vsi);
9114 if (ret)
9115 goto err_netdev;
9116 ret = register_netdev(vsi->netdev);
9117 if (ret)
9118 goto err_netdev;
9119 vsi->netdev_registered = true;
9120 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9121#ifdef CONFIG_I40E_DCB
9122 /* Setup DCB netlink interface */
9123 i40e_dcbnl_setup(vsi);
9124#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9125 /* fall through */
9126
9127 case I40E_VSI_FDIR:
9128 /* set up vectors and rings if needed */
9129 ret = i40e_vsi_setup_vectors(vsi);
9130 if (ret)
9131 goto err_msix;
9132
9133 ret = i40e_alloc_rings(vsi);
9134 if (ret)
9135 goto err_rings;
9136
9137 /* map all of the rings to the q_vectors */
9138 i40e_vsi_map_rings_to_vectors(vsi);
9139
9140 i40e_vsi_reset_stats(vsi);
9141 break;
9142
9143 default:
9144 /* no netdev or rings for the other VSI types */
9145 break;
9146 }
9147
e25d00b8
ASJ		 9148 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9149 (vsi->type == I40E_VSI_VMDQ2)) {
9150 ret = i40e_vsi_config_rss(vsi);
9151 }
41c445ff
JB		 9152 return vsi;
9153
9154err_rings:
9155 i40e_vsi_free_q_vectors(vsi);
9156err_msix:
9157 if (vsi->netdev_registered) {
9158 vsi->netdev_registered = false;
9159 unregister_netdev(vsi->netdev);
9160 free_netdev(vsi->netdev);
9161 vsi->netdev = NULL;
9162 }
9163err_netdev:
9164 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9165err_vsi:
9166 i40e_vsi_clear(vsi);
9167err_alloc:
9168 return NULL;
9169}
9170
9171/**
9172 * i40e_veb_get_bw_info - Query VEB BW information
9173 * @veb: the veb to query
9174 *
9175 * Query the Tx scheduler BW configuration data for given VEB
9176 **/
9177static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9178{
9179 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9180 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9181 struct i40e_pf *pf = veb->pf;
9182 struct i40e_hw *hw = &pf->hw;
9183 u32 tc_bw_max;
9184 int ret = 0;
9185 int i;
9186
9187 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9188 &bw_data, NULL);
9189 if (ret) {
9190 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9191 "query veb bw config failed, err %s aq_err %s\n",
9192 i40e_stat_str(&pf->hw, ret),
9193 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9194 goto out;
9195 }
9196
9197 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9198 &ets_data, NULL);
9199 if (ret) {
9200 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9201 "query veb bw ets config failed, err %s aq_err %s\n",
9202 i40e_stat_str(&pf->hw, ret),
9203 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9204 goto out;
9205 }
9206
9207 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9208 veb->bw_max_quanta = ets_data.tc_bw_max;
9209 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9210 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9211 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9212 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9213 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9214 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9215 veb->bw_tc_limit_credits[i] =
9216 le16_to_cpu(bw_data.tc_bw_limits[i]);
9217 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9218 }
9219
9220out:
9221 return ret;
9222}
9223
9224/**
9225 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9226 * @pf: board private structure
9227 *
9228 * On error: returns error code (negative)
9229 * On success: returns vsi index in PF (positive)
9230 **/
9231static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9232{
9233 int ret = -ENOENT;
9234 struct i40e_veb *veb;
9235 int i;
9236
9237 /* Need to protect the allocation of switch elements at the PF level */
9238 mutex_lock(&pf->switch_mutex);
9239
9240 /* VEB list may be fragmented if VEB creation/destruction has
9241 * been happening. We can afford to do a quick scan to look
9242 * for any free slots in the list.
9243 *
9244 * find next empty veb slot, looping back around if necessary
9245 */
9246 i = 0;
9247 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9248 i++;
9249 if (i >= I40E_MAX_VEB) {
9250 ret = -ENOMEM;
9251 goto err_alloc_veb; /* out of VEB slots! */
9252 }
9253
9254 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9255 if (!veb) {
9256 ret = -ENOMEM;
9257 goto err_alloc_veb;
9258 }
9259 veb->pf = pf;
9260 veb->idx = i;
9261 veb->enabled_tc = 1;
9262
9263 pf->veb[i] = veb;
9264 ret = i;
9265err_alloc_veb:
9266 mutex_unlock(&pf->switch_mutex);
9267 return ret;
9268}
9269
9270/**
9271 * i40e_switch_branch_release - Delete a branch of the switch tree
9272 * @branch: where to start deleting
9273 *
9274 * This uses recursion to find the tips of the branch to be
9275 * removed, deleting until we get back to and can delete this VEB.
9276 **/
9277static void i40e_switch_branch_release(struct i40e_veb *branch)
9278{
9279 struct i40e_pf *pf = branch->pf;
9280 u16 branch_seid = branch->seid;
9281 u16 veb_idx = branch->idx;
9282 int i;
9283
9284 /* release any VEBs on this VEB - RECURSION */
9285 for (i = 0; i < I40E_MAX_VEB; i++) {
9286 if (!pf->veb[i])
9287 continue;
9288 if (pf->veb[i]->uplink_seid == branch->seid)
9289 i40e_switch_branch_release(pf->veb[i]);
9290 }
9291
9292 /* Release the VSIs on this VEB, but not the owner VSI.
9293 *
9294 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9295 * the VEB itself, so don't use (*branch) after this loop.
9296 */
505682cd 9297 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9298 if (!pf->vsi[i])
9299 continue;
9300 if (pf->vsi[i]->uplink_seid == branch_seid &&
9301 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9302 i40e_vsi_release(pf->vsi[i]);
9303 }
9304 }
9305
9306 /* There's one corner case where the VEB might not have been
9307 * removed, so double check it here and remove it if needed.
9308 * This case happens if the veb was created from the debugfs
9309 * commands and no VSIs were added to it.
9310 */
9311 if (pf->veb[veb_idx])
9312 i40e_veb_release(pf->veb[veb_idx]);
9313}
9314
9315/**
9316 * i40e_veb_clear - remove veb struct
9317 * @veb: the veb to remove
9318 **/
9319static void i40e_veb_clear(struct i40e_veb *veb)
9320{
9321 if (!veb)
9322 return;
9323
9324 if (veb->pf) {
9325 struct i40e_pf *pf = veb->pf;
9326
9327 mutex_lock(&pf->switch_mutex);
9328 if (pf->veb[veb->idx] == veb)
9329 pf->veb[veb->idx] = NULL;
9330 mutex_unlock(&pf->switch_mutex);
9331 }
9332
9333 kfree(veb);
9334}
9335
9336/**
9337 * i40e_veb_release - Delete a VEB and free its resources
9338 * @veb: the VEB being removed
9339 **/
9340void i40e_veb_release(struct i40e_veb *veb)
9341{
9342 struct i40e_vsi *vsi = NULL;
9343 struct i40e_pf *pf;
9344 int i, n = 0;
9345
9346 pf = veb->pf;
9347
9348 /* find the remaining VSI and check for extras */
505682cd 9349 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9350 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9351 n++;
9352 vsi = pf->vsi[i];
9353 }
9354 }
9355 if (n != 1) {
9356 dev_info(&pf->pdev->dev,
9357 "can't remove VEB %d with %d VSIs left\n",
9358 veb->seid, n);
9359 return;
9360 }
9361
9362 /* move the remaining VSI to uplink veb */
9363 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9364 if (veb->uplink_seid) {
9365 vsi->uplink_seid = veb->uplink_seid;
9366 if (veb->uplink_seid == pf->mac_seid)
9367 vsi->veb_idx = I40E_NO_VEB;
9368 else
9369 vsi->veb_idx = veb->veb_idx;
9370 } else {
9371 /* floating VEB */
9372 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9373 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9374 }
9375
9376 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9377 i40e_veb_clear(veb);
41c445ff
JB		 9378}
9379
9380/**
9381 * i40e_add_veb - create the VEB in the switch
9382 * @veb: the VEB to be instantiated
9383 * @vsi: the controlling VSI
9384 **/
9385static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9386{
f1c7e72e 9387 struct i40e_pf *pf = veb->pf;
92faef85 9388 bool is_default = veb->pf->cur_promisc;
e1c51b95 9389 bool is_cloud = false;
41c445ff
JB		 9390 int ret;
9391
9392 /* get a VEB from the hardware */
f1c7e72e 9393 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9394 veb->enabled_tc, is_default,
9395 is_cloud, &veb->seid, NULL);
41c445ff 9396 if (ret) {
f1c7e72e
SN		 9397 dev_info(&pf->pdev->dev,
9398 "couldn't add VEB, err %s aq_err %s\n",
9399 i40e_stat_str(&pf->hw, ret),
9400 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9401 return -EPERM;
9402 }
9403
9404 /* get statistics counter */
f1c7e72e 9405 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9406 &veb->stats_idx, NULL, NULL, NULL);
9407 if (ret) {
f1c7e72e
SN		 9408 dev_info(&pf->pdev->dev,
9409 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9410 i40e_stat_str(&pf->hw, ret),
9411 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9412 return -EPERM;
9413 }
9414 ret = i40e_veb_get_bw_info(veb);
9415 if (ret) {
f1c7e72e
SN		 9416 dev_info(&pf->pdev->dev,
9417 "couldn't get VEB bw info, err %s aq_err %s\n",
9418 i40e_stat_str(&pf->hw, ret),
9419 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9420 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9421 return -ENOENT;
9422 }
9423
9424 vsi->uplink_seid = veb->seid;
9425 vsi->veb_idx = veb->idx;
9426 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9427
9428 return 0;
9429}
9430
9431/**
9432 * i40e_veb_setup - Set up a VEB
9433 * @pf: board private structure
9434 * @flags: VEB setup flags
9435 * @uplink_seid: the switch element to link to
9436 * @vsi_seid: the initial VSI seid
9437 * @enabled_tc: Enabled TC bit-map
9438 *
9439 * This allocates the sw VEB structure and links it into the switch
9440 * It is possible and legal for this to be a duplicate of an already
9441 * existing VEB. It is also possible for both uplink and vsi seids
9442 * to be zero, in order to create a floating VEB.
9443 *
9444 * Returns pointer to the successfully allocated VEB sw struct on
9445 * success, otherwise returns NULL on failure.
9446 **/
9447struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9448 u16 uplink_seid, u16 vsi_seid,
9449 u8 enabled_tc)
9450{
9451 struct i40e_veb *veb, *uplink_veb = NULL;
9452 int vsi_idx, veb_idx;
9453 int ret;
9454
9455 /* if one seid is 0, the other must be 0 to create a floating relay */
9456 if ((uplink_seid == 0 || vsi_seid == 0) &&
9457 (uplink_seid + vsi_seid != 0)) {
9458 dev_info(&pf->pdev->dev,
9459 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9460 uplink_seid, vsi_seid);
9461 return NULL;
9462 }
9463
9464 /* make sure there is such a vsi and uplink */
505682cd 9465 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9466 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9467 break;
505682cd 9468 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9469 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9470 vsi_seid);
9471 return NULL;
9472 }
9473
9474 if (uplink_seid && uplink_seid != pf->mac_seid) {
9475 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9476 if (pf->veb[veb_idx] &&
9477 pf->veb[veb_idx]->seid == uplink_seid) {
9478 uplink_veb = pf->veb[veb_idx];
9479 break;
9480 }
9481 }
9482 if (!uplink_veb) {
9483 dev_info(&pf->pdev->dev,
9484 "uplink seid %d not found\n", uplink_seid);
9485 return NULL;
9486 }
9487 }
9488
9489 /* get veb sw struct */
9490 veb_idx = i40e_veb_mem_alloc(pf);
9491 if (veb_idx < 0)
9492 goto err_alloc;
9493 veb = pf->veb[veb_idx];
9494 veb->flags = flags;
9495 veb->uplink_seid = uplink_seid;
9496 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9497 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9498
9499 /* create the VEB in the switch */
9500 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9501 if (ret)
9502 goto err_veb;
1bb8b935
SN		 9503 if (vsi_idx == pf->lan_vsi)
9504 pf->lan_veb = veb->idx;
41c445ff
JB		 9505
9506 return veb;
9507
9508err_veb:
9509 i40e_veb_clear(veb);
9510err_alloc:
9511 return NULL;
9512}
9513
9514/**
b40c82e6 9515 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9516 * @pf: board private structure
9517 * @ele: element we are building info from
9518 * @num_reported: total number of elements
9519 * @printconfig: should we print the contents
9520 *
9521 * helper function to assist in extracting a few useful SEID values.
9522 **/
9523static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9524 struct i40e_aqc_switch_config_element_resp *ele,
9525 u16 num_reported, bool printconfig)
9526{
9527 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9528 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9529 u8 element_type = ele->element_type;
9530 u16 seid = le16_to_cpu(ele->seid);
9531
9532 if (printconfig)
9533 dev_info(&pf->pdev->dev,
9534 "type=%d seid=%d uplink=%d downlink=%d\n",
9535 element_type, seid, uplink_seid, downlink_seid);
9536
9537 switch (element_type) {
9538 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9539 pf->mac_seid = seid;
9540 break;
9541 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9542 /* Main VEB? */
9543 if (uplink_seid != pf->mac_seid)
9544 break;
9545 if (pf->lan_veb == I40E_NO_VEB) {
9546 int v;
9547
9548 /* find existing or else empty VEB */
9549 for (v = 0; v < I40E_MAX_VEB; v++) {
9550 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9551 pf->lan_veb = v;
9552 break;
9553 }
9554 }
9555 if (pf->lan_veb == I40E_NO_VEB) {
9556 v = i40e_veb_mem_alloc(pf);
9557 if (v < 0)
9558 break;
9559 pf->lan_veb = v;
9560 }
9561 }
9562
9563 pf->veb[pf->lan_veb]->seid = seid;
9564 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9565 pf->veb[pf->lan_veb]->pf = pf;
9566 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9567 break;
9568 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9569 if (num_reported != 1)
9570 break;
9571 /* This is immediately after a reset so we can assume this is
9572 * the PF's VSI
9573 */
9574 pf->mac_seid = uplink_seid;
9575 pf->pf_seid = downlink_seid;
9576 pf->main_vsi_seid = seid;
9577 if (printconfig)
9578 dev_info(&pf->pdev->dev,
9579 "pf_seid=%d main_vsi_seid=%d\n",
9580 pf->pf_seid, pf->main_vsi_seid);
9581 break;
9582 case I40E_SWITCH_ELEMENT_TYPE_PF:
9583 case I40E_SWITCH_ELEMENT_TYPE_VF:
9584 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9585 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9586 case I40E_SWITCH_ELEMENT_TYPE_PE:
9587 case I40E_SWITCH_ELEMENT_TYPE_PA:
9588 /* ignore these for now */
9589 break;
9590 default:
9591 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9592 element_type, seid);
9593 break;
9594 }
9595}
9596
9597/**
9598 * i40e_fetch_switch_configuration - Get switch config from firmware
9599 * @pf: board private structure
9600 * @printconfig: should we print the contents
9601 *
9602 * Get the current switch configuration from the device and
9603 * extract a few useful SEID values.
9604 **/
9605int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9606{
9607 struct i40e_aqc_get_switch_config_resp *sw_config;
9608 u16 next_seid = 0;
9609 int ret = 0;
9610 u8 *aq_buf;
9611 int i;
9612
9613 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9614 if (!aq_buf)
9615 return -ENOMEM;
9616
9617 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9618 do {
9619 u16 num_reported, num_total;
9620
9621 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9622 I40E_AQ_LARGE_BUF,
9623 &next_seid, NULL);
9624 if (ret) {
9625 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9626 "get switch config failed err %s aq_err %s\n",
9627 i40e_stat_str(&pf->hw, ret),
9628 i40e_aq_str(&pf->hw,
9629 pf->hw.aq.asq_last_status));
41c445ff
JB		 9630 kfree(aq_buf);
9631 return -ENOENT;
9632 }
9633
9634 num_reported = le16_to_cpu(sw_config->header.num_reported);
9635 num_total = le16_to_cpu(sw_config->header.num_total);
9636
9637 if (printconfig)
9638 dev_info(&pf->pdev->dev,
9639 "header: %d reported %d total\n",
9640 num_reported, num_total);
9641
41c445ff
JB		 9642 for (i = 0; i < num_reported; i++) {
9643 struct i40e_aqc_switch_config_element_resp *ele =
9644 &sw_config->element[i];
9645
9646 i40e_setup_pf_switch_element(pf, ele, num_reported,
9647 printconfig);
9648 }
9649 } while (next_seid != 0);
9650
9651 kfree(aq_buf);
9652 return ret;
9653}
9654
9655/**
9656 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9657 * @pf: board private structure
bc7d338f 9658 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9659 *
9660 * Returns 0 on success, negative value on failure
9661 **/
bc7d338f 9662static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9663{
9664 int ret;
9665
9666 /* find out what's out there already */
9667 ret = i40e_fetch_switch_configuration(pf, false);
9668 if (ret) {
9669 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9670 "couldn't fetch switch config, err %s aq_err %s\n",
9671 i40e_stat_str(&pf->hw, ret),
9672 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9673 return ret;
9674 }
9675 i40e_pf_reset_stats(pf);
9676
41c445ff 9677 /* first time setup */
bc7d338f 9678 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9679 struct i40e_vsi *vsi = NULL;
9680 u16 uplink_seid;
9681
9682 /* Set up the PF VSI associated with the PF's main VSI
9683 * that is already in the HW switch
9684 */
9685 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9686 uplink_seid = pf->veb[pf->lan_veb]->seid;
9687 else
9688 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9689 if (pf->lan_vsi == I40E_NO_VSI)
9690 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9691 else if (reinit)
9692 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9693 if (!vsi) {
9694 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9695 i40e_fdir_teardown(pf);
9696 return -EAGAIN;
9697 }
41c445ff
JB		 9698 } else {
9699 /* force a reset of TC and queue layout configurations */
9700 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 9701
41c445ff
JB		 9702 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9703 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9704 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9705 }
9706 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9707
cbf61325
ASJ		 9708 i40e_fdir_sb_setup(pf);
9709
41c445ff
JB		 9710 /* Setup static PF queue filter control settings */
9711 ret = i40e_setup_pf_filter_control(pf);
9712 if (ret) {
9713 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9714 ret);
9715 /* Failure here should not stop continuing other steps */
9716 }
9717
9718 /* enable RSS in the HW, even for only one queue, as the stack can use
9719 * the hash
9720 */
9721 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9722 i40e_config_rss(pf);
9723
9724 /* fill in link information and enable LSE reporting */
0a862b43 9725 i40e_update_link_info(&pf->hw);
a34a6711
MW		 9726 i40e_link_event(pf);
9727
d52c20b7 9728 /* Initialize user-specific link properties */
41c445ff
JB		 9729 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9730 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9731
beb0dff1
JK		 9732 i40e_ptp_init(pf);
9733
41c445ff
JB		 9734 return ret;
9735}
9736
41c445ff
JB		 9737/**
9738 * i40e_determine_queue_usage - Work out queue distribution
9739 * @pf: board private structure
9740 **/
9741static void i40e_determine_queue_usage(struct i40e_pf *pf)
9742{
41c445ff
JB		 9743 int queues_left;
9744
9745 pf->num_lan_qps = 0;
38e00438
VD		 9746#ifdef I40E_FCOE
9747 pf->num_fcoe_qps = 0;
9748#endif
41c445ff
JB		 9749
9750 /* Find the max queues to be put into basic use. We'll always be
9751 * using TC0, whether or not DCB is running, and TC0 will get the
9752 * big RSS set.
9753 */
9754 queues_left = pf->hw.func_caps.num_tx_qp;
9755
cbf61325 9756 if ((queues_left == 1) ||
9aa7e935 9757 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9758 /* one qp for PF, no queues for anything else */
9759 queues_left = 0;
9760 pf->rss_size = pf->num_lan_qps = 1;
9761
9762 /* make sure all the fancies are disabled */
60ea5f83 9763 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9764#ifdef I40E_FCOE
9765 I40E_FLAG_FCOE_ENABLED |
9766#endif
60ea5f83
JB		 9767 I40E_FLAG_FD_SB_ENABLED |
9768 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9769 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9770 I40E_FLAG_SRIOV_ENABLED |
9771 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9772 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9773 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9774 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9775 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9776 /* one qp for PF */
9777 pf->rss_size = pf->num_lan_qps = 1;
9778 queues_left -= pf->num_lan_qps;
9779
9780 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9781#ifdef I40E_FCOE
9782 I40E_FLAG_FCOE_ENABLED |
9783#endif
9aa7e935
FZ		 9784 I40E_FLAG_FD_SB_ENABLED |
9785 I40E_FLAG_FD_ATR_ENABLED |
9786 I40E_FLAG_DCB_ENABLED |
9787 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9788 } else {
cbf61325 9789 /* Not enough queues for all TCs */
4d9b6043 9790 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9791 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9792 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9793 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9794 }
9a3bd2f1
ASJ		 9795 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9796 num_online_cpus());
9797 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9798 pf->hw.func_caps.num_tx_qp);
9799
cbf61325
ASJ		 9800 queues_left -= pf->num_lan_qps;
9801 }
9802
38e00438
VD		 9803#ifdef I40E_FCOE
9804 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9805 if (I40E_DEFAULT_FCOE <= queues_left) {
9806 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9807 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9808 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9809 } else {
9810 pf->num_fcoe_qps = 0;
9811 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9812 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9813 }
9814
9815 queues_left -= pf->num_fcoe_qps;
9816 }
9817
9818#endif
cbf61325
ASJ		 9819 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9820 if (queues_left > 1) {
9821 queues_left -= 1; /* save 1 queue for FD */
9822 } else {
9823 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9824 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9825 }
41c445ff
JB		 9826 }
9827
9828 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9829 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9830 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9831 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9832 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9833 }
9834
9835 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9836 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9837 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9838 (queues_left / pf->num_vmdq_qps));
9839 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9840 }
9841
f8ff1464 9842 pf->queues_left = queues_left;
8279e495
NP		 9843 dev_dbg(&pf->pdev->dev,
9844 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
9845 pf->hw.func_caps.num_tx_qp,
9846 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
9847 pf->num_lan_qps, pf->rss_size, pf->num_req_vfs, pf->num_vf_qps,
9848 pf->num_vmdq_vsis, pf->num_vmdq_qps, queues_left);
38e00438 9849#ifdef I40E_FCOE
8279e495 9850 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 9851#endif
41c445ff
JB		 9852}
9853
9854/**
9855 * i40e_setup_pf_filter_control - Setup PF static filter control
9856 * @pf: PF to be setup
9857 *
b40c82e6 9858 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9859 * settings. If PE/FCoE are enabled then it will also set the per PF
9860 * based filter sizes required for them. It also enables Flow director,
9861 * ethertype and macvlan type filter settings for the pf.
9862 *
9863 * Returns 0 on success, negative on failure
9864 **/
9865static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9866{
9867 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9868
9869 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9870
9871 /* Flow Director is enabled */
60ea5f83 9872 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9873 settings->enable_fdir = true;
9874
9875 /* Ethtype and MACVLAN filters enabled for PF */
9876 settings->enable_ethtype = true;
9877 settings->enable_macvlan = true;
9878
9879 if (i40e_set_filter_control(&pf->hw, settings))
9880 return -ENOENT;
9881
9882 return 0;
9883}
9884
0c22b3dd
JB		 9885#define INFO_STRING_LEN 255
9886static void i40e_print_features(struct i40e_pf *pf)
9887{
9888 struct i40e_hw *hw = &pf->hw;
9889 char *buf, *string;
9890
9891 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9892 if (!string) {
9893 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9894 return;
9895 }
9896
9897 buf = string;
9898
9899 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9900#ifdef CONFIG_PCI_IOV
9901 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9902#endif
aba237d1
MW		 9903 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9904 pf->hw.func_caps.num_vsis,
9905 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9906 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9907
9908 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9909 buf += sprintf(buf, "RSS ");
0c22b3dd 9910 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9911 buf += sprintf(buf, "FD_ATR ");
9912 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9913 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9914 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9915 }
4d9b6043 9916 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd 9917 buf += sprintf(buf, "DCB ");
ce6fcb3f
JB		 9918#if IS_ENABLED(CONFIG_VXLAN)
9919 buf += sprintf(buf, "VxLAN ");
9920#endif
0c22b3dd
JB		 9921 if (pf->flags & I40E_FLAG_PTP)
9922 buf += sprintf(buf, "PTP ");
38e00438
VD		 9923#ifdef I40E_FCOE
9924 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9925 buf += sprintf(buf, "FCOE ");
9926#endif
6dec1017
SN		 9927 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
9928 buf += sprintf(buf, "VEB ");
9929 else
9930 buf += sprintf(buf, "VEPA ");
0c22b3dd
JB		 9931
9932 BUG_ON(buf > (string + INFO_STRING_LEN));
9933 dev_info(&pf->pdev->dev, "%s\n", string);
9934 kfree(string);
9935}
9936
41c445ff
JB		 9937/**
9938 * i40e_probe - Device initialization routine
9939 * @pdev: PCI device information struct
9940 * @ent: entry in i40e_pci_tbl
9941 *
b40c82e6
JK		 9942 * i40e_probe initializes a PF identified by a pci_dev structure.
9943 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9944 * and a hardware reset occur.
9945 *
9946 * Returns 0 on success, negative on failure
9947 **/
9948static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9949{
e827845c 9950 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9951 struct i40e_pf *pf;
9952 struct i40e_hw *hw;
93cd765b 9953 static u16 pfs_found;
1d5109d1 9954 u16 wol_nvm_bits;
d4dfb81a 9955 u16 link_status;
41c445ff
JB		 9956 int err = 0;
9957 u32 len;
8a9eb7d3 9958 u32 i;
41c445ff
JB		 9959
9960 err = pci_enable_device_mem(pdev);
9961 if (err)
9962 return err;
9963
9964 /* set up for high or low dma */
6494294f 9965 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9966 if (err) {
e3e3bfdd
JS		 9967 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9968 if (err) {
9969 dev_err(&pdev->dev,
9970 "DMA configuration failed: 0x%x\n", err);
9971 goto err_dma;
9972 }
41c445ff
JB		 9973 }
9974
9975 /* set up pci connections */
9976 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9977 IORESOURCE_MEM), i40e_driver_name);
9978 if (err) {
9979 dev_info(&pdev->dev,
9980 "pci_request_selected_regions failed %d\n", err);
9981 goto err_pci_reg;
9982 }
9983
9984 pci_enable_pcie_error_reporting(pdev);
9985 pci_set_master(pdev);
9986
9987 /* Now that we have a PCI connection, we need to do the
9988 * low level device setup. This is primarily setting up
9989 * the Admin Queue structures and then querying for the
9990 * device's current profile information.
9991 */
9992 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9993 if (!pf) {
9994 err = -ENOMEM;
9995 goto err_pf_alloc;
9996 }
9997 pf->next_vsi = 0;
9998 pf->pdev = pdev;
9999 set_bit(__I40E_DOWN, &pf->state);
10000
10001 hw = &pf->hw;
10002 hw->back = pf;
232f4706 10003
2ac8b675
SN		 10004 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10005 I40E_MAX_CSR_SPACE);
232f4706 10006
2ac8b675 10007 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10008 if (!hw->hw_addr) {
10009 err = -EIO;
10010 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10011 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10012 pf->ioremap_len, err);
41c445ff
JB		 10013 goto err_ioremap;
10014 }
10015 hw->vendor_id = pdev->vendor;
10016 hw->device_id = pdev->device;
10017 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10018 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10019 hw->subsystem_device_id = pdev->subsystem_device;
10020 hw->bus.device = PCI_SLOT(pdev->devfn);
10021 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10022 pf->instance = pfs_found;
41c445ff 10023
5b5faa43
SN		 10024 if (debug != -1) {
10025 pf->msg_enable = pf->hw.debug_mask;
10026 pf->msg_enable = debug;
10027 }
10028
7134f9ce
JB		 10029 /* do a special CORER for clearing PXE mode once at init */
10030 if (hw->revision_id == 0 &&
10031 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10032 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10033 i40e_flush(hw);
10034 msleep(200);
10035 pf->corer_count++;
10036
10037 i40e_clear_pxe_mode(hw);
10038 }
10039
41c445ff 10040 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10041 i40e_clear_hw(hw);
41c445ff
JB		 10042 err = i40e_pf_reset(hw);
10043 if (err) {
10044 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10045 goto err_pf_reset;
10046 }
10047 pf->pfr_count++;
10048
10049 hw->aq.num_arq_entries = I40E_AQ_LEN;
10050 hw->aq.num_asq_entries = I40E_AQ_LEN;
10051 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10052 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10053 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10054
b294ac70 10055 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10056 "%s-%s:misc",
10057 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10058
10059 err = i40e_init_shared_code(hw);
10060 if (err) {
b2a75c58
ASJ		 10061 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10062 err);
41c445ff
JB		 10063 goto err_pf_reset;
10064 }
10065
d52c20b7
JB		 10066 /* set up a default setting for link flow control */
10067 pf->hw.fc.requested_mode = I40E_FC_NONE;
10068
41c445ff 10069 err = i40e_init_adminq(hw);
f0b44440 10070
6dec1017
SN		 10071 /* provide nvm, fw, api versions */
10072 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10073 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10074 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10075 i40e_nvm_version_str(hw));
f0b44440 10076
41c445ff
JB		 10077 if (err) {
10078 dev_info(&pdev->dev,
7aa67613 10079 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10080 goto err_pf_reset;
10081 }
10082
7aa67613
CS		 10083 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10084 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10085 dev_info(&pdev->dev,
7aa67613
CS		 10086 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10087 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10088 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10089 dev_info(&pdev->dev,
7aa67613 10090 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10091
4eb3f768
SN		 10092 i40e_verify_eeprom(pf);
10093
2c5fe33b
JB		 10094 /* Rev 0 hardware was never productized */
10095 if (hw->revision_id < 1)
10096 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10097
6ff4ef86 10098 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10099 err = i40e_get_capabilities(pf);
10100 if (err)
10101 goto err_adminq_setup;
10102
10103 err = i40e_sw_init(pf);
10104 if (err) {
10105 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10106 goto err_sw_init;
10107 }
10108
10109 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10110 hw->func_caps.num_rx_qp,
10111 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10112 if (err) {
10113 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10114 goto err_init_lan_hmc;
10115 }
10116
10117 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10118 if (err) {
10119 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10120 err = -ENOENT;
10121 goto err_configure_lan_hmc;
10122 }
10123
b686ece5
NP		 10124 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10125 * Ignore error return codes because if it was already disabled via
10126 * hardware settings this will fail
10127 */
10128 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10129 (pf->hw.aq.fw_maj_ver < 4)) {
10130 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10131 i40e_aq_stop_lldp(hw, true, NULL);
10132 }
10133
41c445ff 10134 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10135 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10136 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10137 err = -EIO;
10138 goto err_mac_addr;
10139 }
10140 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10141 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10142 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10143 if (is_valid_ether_addr(hw->mac.port_addr))
10144 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10145#ifdef I40E_FCOE
10146 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10147 if (err)
10148 dev_info(&pdev->dev,
10149 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10150 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10151 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10152 hw->mac.san_addr);
10153 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10154 }
10155 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10156#endif /* I40E_FCOE */
41c445ff
JB		 10157
10158 pci_set_drvdata(pdev, pf);
10159 pci_save_state(pdev);
4e3b35b0
NP		 10160#ifdef CONFIG_I40E_DCB
10161 err = i40e_init_pf_dcb(pf);
10162 if (err) {
aebfc816 10163 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10164 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10165 /* Continue without DCB enabled */
4e3b35b0
NP		 10166 }
10167#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10168
10169 /* set up periodic task facility */
10170 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10171 pf->service_timer_period = HZ;
10172
10173 INIT_WORK(&pf->service_task, i40e_service_task);
10174 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10175 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10176
1d5109d1
SN		 10177 /* NVM bit on means WoL disabled for the port */
10178 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10179 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10180 pf->wol_en = false;
10181 else
10182 pf->wol_en = true;
8e2773ae
SN		 10183 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10184
41c445ff
JB		 10185 /* set up the main switch operations */
10186 i40e_determine_queue_usage(pf);
c1147280
JB		 10187 err = i40e_init_interrupt_scheme(pf);
10188 if (err)
10189 goto err_switch_setup;
41c445ff 10190
505682cd
MW		 10191 /* The number of VSIs reported by the FW is the minimum guaranteed
10192 * to us; HW supports far more and we share the remaining pool with
10193 * the other PFs. We allocate space for more than the guarantee with
10194 * the understanding that we might not get them all later.
41c445ff 10195 */
505682cd
MW		 10196 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10197 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10198 else
10199 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10200
10201 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10202 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10203 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10204 if (!pf->vsi) {
10205 err = -ENOMEM;
41c445ff 10206 goto err_switch_setup;
ed87ac09 10207 }
41c445ff 10208
fa11cb3d
ASJ		 10209#ifdef CONFIG_PCI_IOV
10210 /* prep for VF support */
10211 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10212 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10213 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10214 if (pci_num_vf(pdev))
10215 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10216 }
10217#endif
bc7d338f 10218 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10219 if (err) {
10220 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10221 goto err_vsis;
10222 }
8a9eb7d3 10223 /* if FDIR VSI was set up, start it now */
505682cd 10224 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10225 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10226 i40e_vsi_open(pf->vsi[i]);
10227 break;
10228 }
10229 }
41c445ff 10230
7e2453fe
JB		 10231 /* driver is only interested in link up/down and module qualification
10232 * reports from firmware
10233 */
10234 err = i40e_aq_set_phy_int_mask(&pf->hw,
10235 I40E_AQ_EVENT_LINK_UPDOWN |
10236 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10237 if (err)
f1c7e72e
SN		 10238 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10239 i40e_stat_str(&pf->hw, err),
10240 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10241
025b4a54
ASJ		 10242 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10243 (pf->hw.aq.fw_maj_ver < 4)) {
10244 msleep(75);
10245 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10246 if (err)
f1c7e72e
SN		 10247 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10248 i40e_stat_str(&pf->hw, err),
10249 i40e_aq_str(&pf->hw,
10250 pf->hw.aq.asq_last_status));
cafa2ee6 10251 }
41c445ff
JB		 10252 /* The main driver is (mostly) up and happy. We need to set this state
10253 * before setting up the misc vector or we get a race and the vector
10254 * ends up disabled forever.
10255 */
10256 clear_bit(__I40E_DOWN, &pf->state);
10257
10258 /* In case of MSIX we are going to setup the misc vector right here
10259 * to handle admin queue events etc. In case of legacy and MSI
10260 * the misc functionality and queue processing is combined in
10261 * the same vector and that gets setup at open.
10262 */
10263 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10264 err = i40e_setup_misc_vector(pf);
10265 if (err) {
10266 dev_info(&pdev->dev,
10267 "setup of misc vector failed: %d\n", err);
10268 goto err_vsis;
10269 }
10270 }
10271
df805f62 10272#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10273 /* prep for VF support */
10274 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10275 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10276 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10277 u32 val;
10278
10279 /* disable link interrupts for VFs */
10280 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10281 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10282 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10283 i40e_flush(hw);
4aeec010
MW		 10284
10285 if (pci_num_vf(pdev)) {
10286 dev_info(&pdev->dev,
10287 "Active VFs found, allocating resources.\n");
10288 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10289 if (err)
10290 dev_info(&pdev->dev,
10291 "Error %d allocating resources for existing VFs\n",
10292 err);
10293 }
41c445ff 10294 }
df805f62 10295#endif /* CONFIG_PCI_IOV */
41c445ff 10296
93cd765b
ASJ		 10297 pfs_found++;
10298
41c445ff
JB		 10299 i40e_dbg_pf_init(pf);
10300
10301 /* tell the firmware that we're starting */
44033fac 10302 i40e_send_version(pf);
41c445ff
JB		 10303
10304 /* since everything's happy, start the service_task timer */
10305 mod_timer(&pf->service_timer,
10306 round_jiffies(jiffies + pf->service_timer_period));
10307
38e00438
VD		 10308#ifdef I40E_FCOE
10309 /* create FCoE interface */
10310 i40e_fcoe_vsi_setup(pf);
10311
10312#endif
3fced535
ASJ		 10313#define PCI_SPEED_SIZE 8
10314#define PCI_WIDTH_SIZE 8
10315 /* Devices on the IOSF bus do not have this information
10316 * and will report PCI Gen 1 x 1 by default so don't bother
10317 * checking them.
10318 */
10319 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10320 char speed[PCI_SPEED_SIZE] = "Unknown";
10321 char width[PCI_WIDTH_SIZE] = "Unknown";
10322
10323 /* Get the negotiated link width and speed from PCI config
10324 * space
10325 */
10326 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10327 &link_status);
10328
10329 i40e_set_pci_config_data(hw, link_status);
10330
10331 switch (hw->bus.speed) {
10332 case i40e_bus_speed_8000:
10333 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10334 case i40e_bus_speed_5000:
10335 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10336 case i40e_bus_speed_2500:
10337 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10338 default:
10339 break;
10340 }
10341 switch (hw->bus.width) {
10342 case i40e_bus_width_pcie_x8:
10343 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10344 case i40e_bus_width_pcie_x4:
10345 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10346 case i40e_bus_width_pcie_x2:
10347 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10348 case i40e_bus_width_pcie_x1:
10349 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10350 default:
10351 break;
10352 }
10353
10354 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10355 speed, width);
10356
10357 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10358 hw->bus.speed < i40e_bus_speed_8000) {
10359 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10360 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10361 }
d4dfb81a
CS		 10362 }
10363
e827845c
CS		 10364 /* get the requested speeds from the fw */
10365 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10366 if (err)
8279e495
NP		 10367 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10368 i40e_stat_str(&pf->hw, err),
10369 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10370 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10371
fc72dbce
CS		 10372 /* get the supported phy types from the fw */
10373 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10374 if (err)
10375 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10376 i40e_stat_str(&pf->hw, err),
10377 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10378 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10379
0c22b3dd
JB		 10380 /* print a string summarizing features */
10381 i40e_print_features(pf);
10382
41c445ff
JB		 10383 return 0;
10384
10385 /* Unwind what we've done if something failed in the setup */
10386err_vsis:
10387 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10388 i40e_clear_interrupt_scheme(pf);
10389 kfree(pf->vsi);
04b03013
SN		 10390err_switch_setup:
10391 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10392 del_timer_sync(&pf->service_timer);
10393err_mac_addr:
10394err_configure_lan_hmc:
10395 (void)i40e_shutdown_lan_hmc(hw);
10396err_init_lan_hmc:
10397 kfree(pf->qp_pile);
41c445ff
JB		 10398err_sw_init:
10399err_adminq_setup:
10400 (void)i40e_shutdown_adminq(hw);
10401err_pf_reset:
10402 iounmap(hw->hw_addr);
10403err_ioremap:
10404 kfree(pf);
10405err_pf_alloc:
10406 pci_disable_pcie_error_reporting(pdev);
10407 pci_release_selected_regions(pdev,
10408 pci_select_bars(pdev, IORESOURCE_MEM));
10409err_pci_reg:
10410err_dma:
10411 pci_disable_device(pdev);
10412 return err;
10413}
10414
10415/**
10416 * i40e_remove - Device removal routine
10417 * @pdev: PCI device information struct
10418 *
10419 * i40e_remove is called by the PCI subsystem to alert the driver
10420 * that is should release a PCI device. This could be caused by a
10421 * Hot-Plug event, or because the driver is going to be removed from
10422 * memory.
10423 **/
10424static void i40e_remove(struct pci_dev *pdev)
10425{
10426 struct i40e_pf *pf = pci_get_drvdata(pdev);
10427 i40e_status ret_code;
41c445ff
JB		 10428 int i;
10429
10430 i40e_dbg_pf_exit(pf);
10431
beb0dff1
JK		 10432 i40e_ptp_stop(pf);
10433
41c445ff
JB		 10434 /* no more scheduling of any task */
10435 set_bit(__I40E_DOWN, &pf->state);
10436 del_timer_sync(&pf->service_timer);
10437 cancel_work_sync(&pf->service_task);
33c62b34 10438 i40e_fdir_teardown(pf);
41c445ff 10439
eb2d80bc
MW		 10440 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10441 i40e_free_vfs(pf);
10442 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10443 }
10444
41c445ff
JB		 10445 i40e_fdir_teardown(pf);
10446
10447 /* If there is a switch structure or any orphans, remove them.
10448 * This will leave only the PF's VSI remaining.
10449 */
10450 for (i = 0; i < I40E_MAX_VEB; i++) {
10451 if (!pf->veb[i])
10452 continue;
10453
10454 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10455 pf->veb[i]->uplink_seid == 0)
10456 i40e_switch_branch_release(pf->veb[i]);
10457 }
10458
10459 /* Now we can shutdown the PF's VSI, just before we kill
10460 * adminq and hmc.
10461 */
10462 if (pf->vsi[pf->lan_vsi])
10463 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10464
41c445ff 10465 /* shutdown and destroy the HMC */
60442dea
SN		 10466 if (pf->hw.hmc.hmc_obj) {
10467 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10468 if (ret_code)
10469 dev_warn(&pdev->dev,
10470 "Failed to destroy the HMC resources: %d\n",
10471 ret_code);
10472 }
41c445ff
JB		 10473
10474 /* shutdown the adminq */
41c445ff
JB		 10475 ret_code = i40e_shutdown_adminq(&pf->hw);
10476 if (ret_code)
10477 dev_warn(&pdev->dev,
10478 "Failed to destroy the Admin Queue resources: %d\n",
10479 ret_code);
10480
10481 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10482 i40e_clear_interrupt_scheme(pf);
505682cd 10483 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10484 if (pf->vsi[i]) {
10485 i40e_vsi_clear_rings(pf->vsi[i]);
10486 i40e_vsi_clear(pf->vsi[i]);
10487 pf->vsi[i] = NULL;
10488 }
10489 }
10490
10491 for (i = 0; i < I40E_MAX_VEB; i++) {
10492 kfree(pf->veb[i]);
10493 pf->veb[i] = NULL;
10494 }
10495
10496 kfree(pf->qp_pile);
41c445ff
JB		 10497 kfree(pf->vsi);
10498
41c445ff
JB		 10499 iounmap(pf->hw.hw_addr);
10500 kfree(pf);
10501 pci_release_selected_regions(pdev,
10502 pci_select_bars(pdev, IORESOURCE_MEM));
10503
10504 pci_disable_pcie_error_reporting(pdev);
10505 pci_disable_device(pdev);
10506}
10507
10508/**
10509 * i40e_pci_error_detected - warning that something funky happened in PCI land
10510 * @pdev: PCI device information struct
10511 *
10512 * Called to warn that something happened and the error handling steps
10513 * are in progress. Allows the driver to quiesce things, be ready for
10514 * remediation.
10515 **/
10516static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10517 enum pci_channel_state error)
10518{
10519 struct i40e_pf *pf = pci_get_drvdata(pdev);
10520
10521 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10522
10523 /* shutdown all operations */
9007bccd
SN		 10524 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10525 rtnl_lock();
10526 i40e_prep_for_reset(pf);
10527 rtnl_unlock();
10528 }
41c445ff
JB		 10529
10530 /* Request a slot reset */
10531 return PCI_ERS_RESULT_NEED_RESET;
10532}
10533
10534/**
10535 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10536 * @pdev: PCI device information struct
10537 *
10538 * Called to find if the driver can work with the device now that
10539 * the pci slot has been reset. If a basic connection seems good
10540 * (registers are readable and have sane content) then return a
10541 * happy little PCI_ERS_RESULT_xxx.
10542 **/
10543static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10544{
10545 struct i40e_pf *pf = pci_get_drvdata(pdev);
10546 pci_ers_result_t result;
10547 int err;
10548 u32 reg;
10549
fb43201f 10550 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 10551 if (pci_enable_device_mem(pdev)) {
10552 dev_info(&pdev->dev,
10553 "Cannot re-enable PCI device after reset.\n");
10554 result = PCI_ERS_RESULT_DISCONNECT;
10555 } else {
10556 pci_set_master(pdev);
10557 pci_restore_state(pdev);
10558 pci_save_state(pdev);
10559 pci_wake_from_d3(pdev, false);
10560
10561 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10562 if (reg == 0)
10563 result = PCI_ERS_RESULT_RECOVERED;
10564 else
10565 result = PCI_ERS_RESULT_DISCONNECT;
10566 }
10567
10568 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10569 if (err) {
10570 dev_info(&pdev->dev,
10571 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10572 err);
10573 /* non-fatal, continue */
10574 }
10575
10576 return result;
10577}
10578
10579/**
10580 * i40e_pci_error_resume - restart operations after PCI error recovery
10581 * @pdev: PCI device information struct
10582 *
10583 * Called to allow the driver to bring things back up after PCI error
10584 * and/or reset recovery has finished.
10585 **/
10586static void i40e_pci_error_resume(struct pci_dev *pdev)
10587{
10588 struct i40e_pf *pf = pci_get_drvdata(pdev);
10589
fb43201f 10590 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10591 if (test_bit(__I40E_SUSPENDED, &pf->state))
10592 return;
10593
10594 rtnl_lock();
41c445ff 10595 i40e_handle_reset_warning(pf);
4c4935a9 10596 rtnl_unlock();
9007bccd
SN		 10597}
10598
10599/**
10600 * i40e_shutdown - PCI callback for shutting down
10601 * @pdev: PCI device information struct
10602 **/
10603static void i40e_shutdown(struct pci_dev *pdev)
10604{
10605 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10606 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10607
10608 set_bit(__I40E_SUSPENDED, &pf->state);
10609 set_bit(__I40E_DOWN, &pf->state);
10610 rtnl_lock();
10611 i40e_prep_for_reset(pf);
10612 rtnl_unlock();
10613
8e2773ae
SN		 10614 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10615 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10616
02b42498
CS		 10617 del_timer_sync(&pf->service_timer);
10618 cancel_work_sync(&pf->service_task);
10619 i40e_fdir_teardown(pf);
10620
10621 rtnl_lock();
10622 i40e_prep_for_reset(pf);
10623 rtnl_unlock();
10624
10625 wr32(hw, I40E_PFPM_APM,
10626 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10627 wr32(hw, I40E_PFPM_WUFC,
10628 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10629
e147758d
SN		 10630 i40e_clear_interrupt_scheme(pf);
10631
9007bccd 10632 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10633 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10634 pci_set_power_state(pdev, PCI_D3hot);
10635 }
10636}
10637
10638#ifdef CONFIG_PM
10639/**
10640 * i40e_suspend - PCI callback for moving to D3
10641 * @pdev: PCI device information struct
10642 **/
10643static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10644{
10645 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10646 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10647
10648 set_bit(__I40E_SUSPENDED, &pf->state);
10649 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10650
9007bccd
SN		 10651 rtnl_lock();
10652 i40e_prep_for_reset(pf);
10653 rtnl_unlock();
10654
8e2773ae
SN		 10655 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10656 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10657
10658 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10659 pci_set_power_state(pdev, PCI_D3hot);
10660
10661 return 0;
41c445ff
JB		 10662}
10663
9007bccd
SN		 10664/**
10665 * i40e_resume - PCI callback for waking up from D3
10666 * @pdev: PCI device information struct
10667 **/
10668static int i40e_resume(struct pci_dev *pdev)
10669{
10670 struct i40e_pf *pf = pci_get_drvdata(pdev);
10671 u32 err;
10672
10673 pci_set_power_state(pdev, PCI_D0);
10674 pci_restore_state(pdev);
10675 /* pci_restore_state() clears dev->state_saves, so
10676 * call pci_save_state() again to restore it.
10677 */
10678 pci_save_state(pdev);
10679
10680 err = pci_enable_device_mem(pdev);
10681 if (err) {
fb43201f 10682 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 10683 return err;
10684 }
10685 pci_set_master(pdev);
10686
10687 /* no wakeup events while running */
10688 pci_wake_from_d3(pdev, false);
10689
10690 /* handling the reset will rebuild the device state */
10691 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10692 clear_bit(__I40E_DOWN, &pf->state);
10693 rtnl_lock();
10694 i40e_reset_and_rebuild(pf, false);
10695 rtnl_unlock();
10696 }
10697
10698 return 0;
10699}
10700
10701#endif
41c445ff
JB		 10702static const struct pci_error_handlers i40e_err_handler = {
10703 .error_detected = i40e_pci_error_detected,
10704 .slot_reset = i40e_pci_error_slot_reset,
10705 .resume = i40e_pci_error_resume,
10706};
10707
10708static struct pci_driver i40e_driver = {
10709 .name = i40e_driver_name,
10710 .id_table = i40e_pci_tbl,
10711 .probe = i40e_probe,
10712 .remove = i40e_remove,
9007bccd
SN		 10713#ifdef CONFIG_PM
10714 .suspend = i40e_suspend,
10715 .resume = i40e_resume,
10716#endif
10717 .shutdown = i40e_shutdown,
41c445ff
JB		 10718 .err_handler = &i40e_err_handler,
10719 .sriov_configure = i40e_pci_sriov_configure,
10720};
10721
10722/**
10723 * i40e_init_module - Driver registration routine
10724 *
10725 * i40e_init_module is the first routine called when the driver is
10726 * loaded. All it does is register with the PCI subsystem.
10727 **/
10728static int __init i40e_init_module(void)
10729{
10730 pr_info("%s: %s - version %s\n", i40e_driver_name,
10731 i40e_driver_string, i40e_driver_version_str);
10732 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10733
41c445ff
JB		 10734 i40e_dbg_init();
10735 return pci_register_driver(&i40e_driver);
10736}
10737module_init(i40e_init_module);
10738
10739/**
10740 * i40e_exit_module - Driver exit cleanup routine
10741 *
10742 * i40e_exit_module is called just before the driver is removed
10743 * from memory.
10744 **/
10745static void __exit i40e_exit_module(void)
10746{
10747 pci_unregister_driver(&i40e_driver);
10748 i40e_dbg_exit();
10749}
10750module_exit(i40e_exit_module);
Linux kernel - Deliverables
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