[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_lan_hmc.h

/*******************************************************************************
 *
 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
 * Copyright(c) 2013 - 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 ******************************************************************************/

#ifndef _I40E_LAN_HMC_H_
#define _I40E_LAN_HMC_H_

/* forward-declare the HW struct for the compiler */
struct i40e_hw;

/* HMC element context information */

/* Rx queue context data */
struct i40e_hmc_obj_rxq {
	u16 head;
	u8  cpuid;
	u64 base;
	u16 qlen;
#define I40E_RXQ_CTX_DBUFF_SHIFT 7
	u8  dbuff;
#define I40E_RXQ_CTX_HBUFF_SHIFT 6
	u8  hbuff;
	u8  dtype;
	u8  dsize;
	u8  crcstrip;
	u8  fc_ena;
	u8  l2tsel;
	u8  hsplit_0;
	u8  hsplit_1;
	u8  showiv;
	u16 rxmax;
	u8  tphrdesc_ena;
	u8  tphwdesc_ena;
	u8  tphdata_ena;
	u8  tphhead_ena;
	u8  lrxqthresh;
	u8  prefena;	/* NOTE: normally must be set to 1 at init */
};

/* Tx queue context data */
struct i40e_hmc_obj_txq {
	u16 head;
	u8  new_context;
	u64 base;
	u8  fc_ena;
	u8  timesync_ena;
	u8  fd_ena;
	u8  alt_vlan_ena;
	u16 thead_wb;
	u16 cpuid;
	u8  head_wb_ena;
	u16 qlen;
	u8  tphrdesc_ena;
	u8  tphrpacket_ena;
	u8  tphwdesc_ena;
	u64 head_wb_addr;
	u32 crc;
	u16 rdylist;
	u8  rdylist_act;
};

/* for hsplit_0 field of Rx HMC context */
enum i40e_hmc_obj_rx_hsplit_0 {
	I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT      = 0,
	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2      = 1,
	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP      = 2,
	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP    = 8,
};

/* fcoe_cntx and fcoe_filt are for debugging purpose only */
struct i40e_hmc_obj_fcoe_cntx {
	u32 rsv[32];
};

struct i40e_hmc_obj_fcoe_filt {
	u32 rsv[8];
};

/* Context sizes for LAN objects */
enum i40e_hmc_lan_object_size {
	I40E_HMC_LAN_OBJ_SZ_8   = 0x3,
	I40E_HMC_LAN_OBJ_SZ_16  = 0x4,
	I40E_HMC_LAN_OBJ_SZ_32  = 0x5,
	I40E_HMC_LAN_OBJ_SZ_64  = 0x6,
	I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
	I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
	I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
};

#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
#define I40E_HMC_OBJ_SIZE_TXQ         128
#define I40E_HMC_OBJ_SIZE_RXQ         32
#define I40E_HMC_OBJ_SIZE_FCOE_CNTX   128
#define I40E_HMC_OBJ_SIZE_FCOE_FILT   64

enum i40e_hmc_lan_rsrc_type {
	I40E_HMC_LAN_FULL  = 0,
	I40E_HMC_LAN_TX    = 1,
	I40E_HMC_LAN_RX    = 2,
	I40E_HMC_FCOE_CTX  = 3,
	I40E_HMC_FCOE_FILT = 4,
	I40E_HMC_LAN_MAX   = 5
};

enum i40e_hmc_model {
	I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
	I40E_HMC_MODEL_DIRECT_ONLY      = 1,
	I40E_HMC_MODEL_PAGED_ONLY       = 2,
	I40E_HMC_MODEL_UNKNOWN,
};

struct i40e_hmc_lan_create_obj_info {
	struct i40e_hmc_info *hmc_info;
	u32 rsrc_type;
	u32 start_idx;
	u32 count;
	enum i40e_sd_entry_type entry_type;
	u64 direct_mode_sz;
};

struct i40e_hmc_lan_delete_obj_info {
	struct i40e_hmc_info *hmc_info;
	u32 rsrc_type;
	u32 start_idx;
	u32 count;
};

i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
					u32 rxq_num, u32 fcoe_cntx_num,
					u32 fcoe_filt_num);
i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
					     enum i40e_hmc_model model);
i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);

i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
						      u16 queue);
i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
						    u16 queue,
						    struct i40e_hmc_obj_txq *s);
i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
						      u16 queue);
i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
						    u16 queue,
						    struct i40e_hmc_obj_rxq *s);

#endif /* _I40E_LAN_HMC_H_ */
Commit	Line	Data
d358aa9a GR	1	/*******************************************************************************
	2	*
	3	* Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
b831607d	4	* Copyright(c) 2013 - 2014 Intel Corporation.
d358aa9a GR	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
b831607d JB	15	* You should have received a copy of the GNU General Public License along
	16	* with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
d358aa9a GR	18	* The full GNU General Public License is included in this distribution in
	19	* the file called "COPYING".
	20	*
	21	* Contact Information:
	22	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	23	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	24	*
	25	******************************************************************************/
	26
	27	#ifndef _I40E_LAN_HMC_H_
	28	#define _I40E_LAN_HMC_H_
	29
	30	/* forward-declare the HW struct for the compiler */
	31	struct i40e_hw;
	32
	33	/* HMC element context information */
	34
	35	/* Rx queue context data */
	36	struct i40e_hmc_obj_rxq {
	37	u16 head;
	38	u8 cpuid;
	39	u64 base;
	40	u16 qlen;
	41	#define I40E_RXQ_CTX_DBUFF_SHIFT 7
	42	u8 dbuff;
	43	#define I40E_RXQ_CTX_HBUFF_SHIFT 6
	44	u8 hbuff;
	45	u8 dtype;
	46	u8 dsize;
	47	u8 crcstrip;
	48	u8 fc_ena;
	49	u8 l2tsel;
	50	u8 hsplit_0;
	51	u8 hsplit_1;
	52	u8 showiv;
	53	u16 rxmax;
	54	u8 tphrdesc_ena;
	55	u8 tphwdesc_ena;
	56	u8 tphdata_ena;
	57	u8 tphhead_ena;
	58	u8 lrxqthresh;
0b3aec85	59	u8 prefena; /* NOTE: normally must be set to 1 at init */
d358aa9a GR	60	};
	61
	62	/* Tx queue context data */
	63	struct i40e_hmc_obj_txq {
	64	u16 head;
	65	u8 new_context;
	66	u64 base;
	67	u8 fc_ena;
	68	u8 timesync_ena;
	69	u8 fd_ena;
	70	u8 alt_vlan_ena;
	71	u16 thead_wb;
	72	u16 cpuid;
	73	u8 head_wb_ena;
	74	u16 qlen;
	75	u8 tphrdesc_ena;
	76	u8 tphrpacket_ena;
	77	u8 tphwdesc_ena;
	78	u64 head_wb_addr;
	79	u32 crc;
	80	u16 rdylist;
	81	u8 rdylist_act;
	82	};
	83
	84	/* for hsplit_0 field of Rx HMC context */
	85	enum i40e_hmc_obj_rx_hsplit_0 {
	86	I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
	87	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
	88	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
	89	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
	90	I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
	91	};
	92
	93	/* fcoe_cntx and fcoe_filt are for debugging purpose only */
	94	struct i40e_hmc_obj_fcoe_cntx {
	95	u32 rsv[32];
	96	};
	97
	98	struct i40e_hmc_obj_fcoe_filt {
	99	u32 rsv[8];
	100	};
	101
	102	/* Context sizes for LAN objects */
	103	enum i40e_hmc_lan_object_size {
	104	I40E_HMC_LAN_OBJ_SZ_8 = 0x3,
	105	I40E_HMC_LAN_OBJ_SZ_16 = 0x4,
	106	I40E_HMC_LAN_OBJ_SZ_32 = 0x5,
	107	I40E_HMC_LAN_OBJ_SZ_64 = 0x6,
	108	I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
	109	I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
	110	I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
	111	};
	112
	113	#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
	114	#define I40E_HMC_OBJ_SIZE_TXQ 128
	115	#define I40E_HMC_OBJ_SIZE_RXQ 32
90327e7d	116	#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
d358aa9a GR	117	#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64
	118
	119	enum i40e_hmc_lan_rsrc_type {
	120	I40E_HMC_LAN_FULL = 0,
	121	I40E_HMC_LAN_TX = 1,
	122	I40E_HMC_LAN_RX = 2,
	123	I40E_HMC_FCOE_CTX = 3,
	124	I40E_HMC_FCOE_FILT = 4,
	125	I40E_HMC_LAN_MAX = 5
	126	};
	127
	128	enum i40e_hmc_model {
	129	I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
	130	I40E_HMC_MODEL_DIRECT_ONLY = 1,
	131	I40E_HMC_MODEL_PAGED_ONLY = 2,
	132	I40E_HMC_MODEL_UNKNOWN,
	133	};
	134
	135	struct i40e_hmc_lan_create_obj_info {
	136	struct i40e_hmc_info *hmc_info;
	137	u32 rsrc_type;
	138	u32 start_idx;
	139	u32 count;
	140	enum i40e_sd_entry_type entry_type;
	141	u64 direct_mode_sz;
	142	};
	143
	144	struct i40e_hmc_lan_delete_obj_info {
	145	struct i40e_hmc_info *hmc_info;
	146	u32 rsrc_type;
	147	u32 start_idx;
	148	u32 count;
	149	};
	150
	151	i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
	152	u32 rxq_num, u32 fcoe_cntx_num,
	153	u32 fcoe_filt_num);
	154	i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
	155	enum i40e_hmc_model model);
	156	i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
	157
	158	i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
	159	u16 queue);
	160	i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
	161	u16 queue,
	162	struct i40e_hmc_obj_txq *s);
	163	i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
	164	u16 queue);
	165	i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
	166	u16 queue,
	167	struct i40e_hmc_obj_rxq *s);
	168
	169	#endif /* _I40E_LAN_HMC_H_ */