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igb: implement igb_ptp_suspend
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
806ffb1d 53#include <linux/etherdevice.h>
421e02f0 54#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 55#include <linux/dca.h>
56#endif
441fc6fd 57#include <linux/i2c.h>
9d5c8243
AK		 58#include "igb.h"
59
67b1b903 60#define MAJ 5
6fb46902
TF		 61#define MIN 3
62#define BUILD 0
0d1fe82d 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 64__stringify(BUILD) "-k"
9d5c8243
AK		 65char igb_driver_name[] = "igb";
66char igb_driver_version[] = DRV_VERSION;
67static const char igb_driver_string[] =
68 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 69static const char igb_copyright[] =
74cfb2e1 70 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 71
9d5c8243
AK		 72static const struct e1000_info *igb_info_tbl[] = {
73 [board_82575] = &e1000_82575_info,
74};
75
cd1631ce 76static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
112 /* required last entry */
113 {0, }
114};
115
116MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
117
9d5c8243
AK		 118static int igb_setup_all_tx_resources(struct igb_adapter *);
119static int igb_setup_all_rx_resources(struct igb_adapter *);
120static void igb_free_all_tx_resources(struct igb_adapter *);
121static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 122static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 123static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 124static void igb_remove(struct pci_dev *pdev);
9d5c8243 125static int igb_sw_init(struct igb_adapter *);
46eafa59
SA		 126int igb_open(struct net_device *);
127int igb_close(struct net_device *);
53c7d064 128static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 129static void igb_configure_tx(struct igb_adapter *);
130static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 131static void igb_clean_all_tx_rings(struct igb_adapter *);
132static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 133static void igb_clean_tx_ring(struct igb_ring *);
134static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 135static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 136static void igb_update_phy_info(unsigned long);
137static void igb_watchdog(unsigned long);
138static void igb_watchdog_task(struct work_struct *);
cd392f5c 139static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 140static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 141 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 142static int igb_change_mtu(struct net_device *, int);
143static int igb_set_mac(struct net_device *, void *);
bf456abb 144static void igb_set_uta(struct igb_adapter *adapter, bool set);
9d5c8243
AK		 145static irqreturn_t igb_intr(int irq, void *);
146static irqreturn_t igb_intr_msi(int irq, void *);
147static irqreturn_t igb_msix_other(int irq, void *);
047e0030 148static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 149#ifdef CONFIG_IGB_DCA
047e0030 150static void igb_update_dca(struct igb_q_vector *);
fe4506b6 151static void igb_setup_dca(struct igb_adapter *);
421e02f0 152#endif /* CONFIG_IGB_DCA */
661086df 153static int igb_poll(struct napi_struct *, int);
7f0ba845 154static bool igb_clean_tx_irq(struct igb_q_vector *, int);
32b3e08f 155static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 156static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
157static void igb_tx_timeout(struct net_device *);
158static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 159static void igb_vlan_mode(struct net_device *netdev,
160 netdev_features_t features);
80d5c368
PM		 161static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
162static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 163static void igb_restore_vlan(struct igb_adapter *);
26ad9178 164static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 165static void igb_ping_all_vfs(struct igb_adapter *);
166static void igb_msg_task(struct igb_adapter *);
4ae196df 167static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 168static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 169static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 170static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
171static int igb_ndo_set_vf_vlan(struct net_device *netdev,
172 int vf, u16 vlan, u8 qos);
ed616689 173static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 174static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 bool setting);
8151d294
WM		 176static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
177 struct ifla_vf_info *ivi);
17dc566c 178static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 179
180#ifdef CONFIG_PCI_IOV
0224d663 181static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 182static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 183static int igb_disable_sriov(struct pci_dev *dev);
184static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd 191static int igb_resume(struct device *);
749ab2cd
YZ		 192static int igb_runtime_suspend(struct device *dev);
193static int igb_runtime_resume(struct device *dev);
194static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 195static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199};
9d5c8243
AK		 200#endif
201static void igb_shutdown(struct pci_dev *);
fa44f2f1 202static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 203#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 204static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209};
210#endif
9d5c8243
AK		 211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void igb_netpoll(struct net_device *);
214#endif
37680117 215#ifdef CONFIG_PCI_IOV
6dd6d2b7 216static unsigned int max_vfs;
2a3abf6d 217module_param(max_vfs, uint, 0);
c75c4edf 218MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 219#endif /* CONFIG_PCI_IOV */
220
9d5c8243
AK		 221static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
222 pci_channel_state_t);
223static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
224static void igb_io_resume(struct pci_dev *);
225
3646f0e5 226static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 227 .error_detected = igb_io_error_detected,
228 .slot_reset = igb_io_slot_reset,
229 .resume = igb_io_resume,
230};
231
b6e0c419 232static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 233
234static struct pci_driver igb_driver = {
235 .name = igb_driver_name,
236 .id_table = igb_pci_tbl,
237 .probe = igb_probe,
9f9a12f8 238 .remove = igb_remove,
9d5c8243 239#ifdef CONFIG_PM
749ab2cd 240 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 241#endif
242 .shutdown = igb_shutdown,
fa44f2f1 243 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 244 .err_handler = &igb_err_handler
245};
246
247MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
248MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
249MODULE_LICENSE("GPL");
250MODULE_VERSION(DRV_VERSION);
251
b3f4d599 252#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
253static int debug = -1;
254module_param(debug, int, 0);
255MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256
c97ec42a
TI		 257struct igb_reg_info {
258 u32 ofs;
259 char *name;
260};
261
262static const struct igb_reg_info igb_reg_info_tbl[] = {
263
264 /* General Registers */
265 {E1000_CTRL, "CTRL"},
266 {E1000_STATUS, "STATUS"},
267 {E1000_CTRL_EXT, "CTRL_EXT"},
268
269 /* Interrupt Registers */
270 {E1000_ICR, "ICR"},
271
272 /* RX Registers */
273 {E1000_RCTL, "RCTL"},
274 {E1000_RDLEN(0), "RDLEN"},
275 {E1000_RDH(0), "RDH"},
276 {E1000_RDT(0), "RDT"},
277 {E1000_RXDCTL(0), "RXDCTL"},
278 {E1000_RDBAL(0), "RDBAL"},
279 {E1000_RDBAH(0), "RDBAH"},
280
281 /* TX Registers */
282 {E1000_TCTL, "TCTL"},
283 {E1000_TDBAL(0), "TDBAL"},
284 {E1000_TDBAH(0), "TDBAH"},
285 {E1000_TDLEN(0), "TDLEN"},
286 {E1000_TDH(0), "TDH"},
287 {E1000_TDT(0), "TDT"},
288 {E1000_TXDCTL(0), "TXDCTL"},
289 {E1000_TDFH, "TDFH"},
290 {E1000_TDFT, "TDFT"},
291 {E1000_TDFHS, "TDFHS"},
292 {E1000_TDFPC, "TDFPC"},
293
294 /* List Terminator */
295 {}
296};
297
b980ac18 298/* igb_regdump - register printout routine */
c97ec42a
TI		 299static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
300{
301 int n = 0;
302 char rname[16];
303 u32 regs[8];
304
305 switch (reginfo->ofs) {
306 case E1000_RDLEN(0):
307 for (n = 0; n < 4; n++)
308 regs[n] = rd32(E1000_RDLEN(n));
309 break;
310 case E1000_RDH(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDH(n));
313 break;
314 case E1000_RDT(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDT(n));
317 break;
318 case E1000_RXDCTL(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RXDCTL(n));
321 break;
322 case E1000_RDBAL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RDBAL(n));
325 break;
326 case E1000_RDBAH(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAH(n));
329 break;
330 case E1000_TDBAL(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAL(n));
333 break;
334 case E1000_TDBAH(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_TDBAH(n));
337 break;
338 case E1000_TDLEN(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDLEN(n));
341 break;
342 case E1000_TDH(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDH(n));
345 break;
346 case E1000_TDT(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDT(n));
349 break;
350 case E1000_TXDCTL(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TXDCTL(n));
353 break;
354 default:
876d2d6f 355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 356 return;
357 }
358
359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
361 regs[2], regs[3]);
c97ec42a
TI		 362}
363
b980ac18 364/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 365static void igb_dump(struct igb_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
c97ec42a
TI		 370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
6ad4edfc 376 u16 i, n;
c97ec42a
TI		 377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 384 pr_info("Device Name state trans_start last_rx\n");
876d2d6f 385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
4d0e9657 386 netdev->state, dev_trans_start(netdev), netdev->last_rx);
c97ec42a
TI		 387 }
388
389 /* Print Registers */
390 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 391 pr_info(" Register Name Value\n");
c97ec42a
TI		 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
393 reginfo->name; reginfo++) {
394 igb_regdump(hw, reginfo);
395 }
396
397 /* Print TX Ring Summary */
398 if (!netdev || !netif_running(netdev))
399 goto exit;
400
401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 403 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 404 struct igb_tx_buffer *buffer_info;
c97ec42a 405 tx_ring = adapter->tx_ring[n];
06034649 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
408 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 409 (u64)dma_unmap_addr(buffer_info, dma),
410 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp);
c97ec42a
TI		 413 }
414
415 /* Print TX Rings */
416 if (!netif_msg_tx_done(adapter))
417 goto rx_ring_summary;
418
419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420
421 /* Transmit Descriptor Formats
422 *
423 * Advanced Transmit Descriptor
424 * +--------------------------------------------------------------+
425 * 0 | Buffer Address [63:0] |
426 * +--------------------------------------------------------------+
427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
428 * +--------------------------------------------------------------+
429 * 63 46 45 40 39 38 36 35 32 31 24 15 0
430 */
431
432 for (n = 0; n < adapter->num_tx_queues; n++) {
433 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 434 pr_info("------------------------------------\n");
435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
436 pr_info("------------------------------------\n");
c75c4edf 437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
c75c4edf
CW		 455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
456 i, le64_to_cpu(u0->a),
c97ec42a 457 le64_to_cpu(u0->b),
c9f14bf3
AD		 458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
876d2d6f 462 buffer_info->skb, next_desc);
c97ec42a 463
b669588a 464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
b669588a 467 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 468 dma_unmap_len(buffer_info, len),
469 true);
c97ec42a
TI		 470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 476 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
c75c4edf
CW		 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 517
518 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 519 const char *next_desc;
06034649
AD		 520 struct igb_rx_buffer *buffer_info;
521 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 522 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 523 u0 = (struct my_u0 *)rx_desc;
524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 525
526 if (i == rx_ring->next_to_use)
527 next_desc = " NTU";
528 else if (i == rx_ring->next_to_clean)
529 next_desc = " NTC";
530 else
531 next_desc = "";
532
c97ec42a
TI		 533 if (staterr & E1000_RXD_STAT_DD) {
534 /* Descriptor Done */
1a1c225b
AD		 535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
536 "RWB", i,
c97ec42a
TI		 537 le64_to_cpu(u0->a),
538 le64_to_cpu(u0->b),
1a1c225b 539 next_desc);
c97ec42a 540 } else {
1a1c225b
AD		 541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
542 "R ", i,
c97ec42a
TI		 543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
545 (u64)buffer_info->dma,
1a1c225b 546 next_desc);
c97ec42a 547
b669588a 548 if (netif_msg_pktdata(adapter) &&
1a1c225b 549 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 550 print_hex_dump(KERN_INFO, "",
551 DUMP_PREFIX_ADDRESS,
552 16, 1,
b669588a
ET		 553 page_address(buffer_info->page) +
554 buffer_info->page_offset,
de78d1f9 555 IGB_RX_BUFSZ, true);
c97ec42a
TI		 556 }
557 }
c97ec42a
TI		 558 }
559 }
560
561exit:
562 return;
563}
564
b980ac18
JK		 565/**
566 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 567 * @hw: pointer to hardware structure
568 * @i2cctl: Current value of I2CCTL register
569 *
570 * Returns the I2C data bit value
b980ac18 571 **/
441fc6fd
CW		 572static int igb_get_i2c_data(void *data)
573{
574 struct igb_adapter *adapter = (struct igb_adapter *)data;
575 struct e1000_hw *hw = &adapter->hw;
576 s32 i2cctl = rd32(E1000_I2CPARAMS);
577
da1f1dfe 578 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 579}
580
b980ac18
JK		 581/**
582 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 583 * @data: pointer to hardware structure
584 * @state: I2C data value (0 or 1) to set
585 *
586 * Sets the I2C data bit
b980ac18 587 **/
441fc6fd
CW		 588static void igb_set_i2c_data(void *data, int state)
589{
590 struct igb_adapter *adapter = (struct igb_adapter *)data;
591 struct e1000_hw *hw = &adapter->hw;
592 s32 i2cctl = rd32(E1000_I2CPARAMS);
593
594 if (state)
595 i2cctl |= E1000_I2C_DATA_OUT;
596 else
597 i2cctl &= ~E1000_I2C_DATA_OUT;
598
599 i2cctl &= ~E1000_I2C_DATA_OE_N;
600 i2cctl |= E1000_I2C_CLK_OE_N;
601 wr32(E1000_I2CPARAMS, i2cctl);
602 wrfl();
603
604}
605
b980ac18
JK		 606/**
607 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 608 * @data: pointer to hardware structure
609 * @state: state to set clock
610 *
611 * Sets the I2C clock line to state
b980ac18 612 **/
441fc6fd
CW		 613static void igb_set_i2c_clk(void *data, int state)
614{
615 struct igb_adapter *adapter = (struct igb_adapter *)data;
616 struct e1000_hw *hw = &adapter->hw;
617 s32 i2cctl = rd32(E1000_I2CPARAMS);
618
619 if (state) {
620 i2cctl |= E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 } else {
623 i2cctl &= ~E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 }
626 wr32(E1000_I2CPARAMS, i2cctl);
627 wrfl();
628}
629
b980ac18
JK		 630/**
631 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 632 * @data: pointer to hardware structure
633 *
634 * Gets the I2C clock state
b980ac18 635 **/
441fc6fd
CW		 636static int igb_get_i2c_clk(void *data)
637{
638 struct igb_adapter *adapter = (struct igb_adapter *)data;
639 struct e1000_hw *hw = &adapter->hw;
640 s32 i2cctl = rd32(E1000_I2CPARAMS);
641
da1f1dfe 642 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 643}
644
645static const struct i2c_algo_bit_data igb_i2c_algo = {
646 .setsda = igb_set_i2c_data,
647 .setscl = igb_set_i2c_clk,
648 .getsda = igb_get_i2c_data,
649 .getscl = igb_get_i2c_clk,
650 .udelay = 5,
651 .timeout = 20,
652};
653
9d5c8243 654/**
b980ac18
JK		 655 * igb_get_hw_dev - return device
656 * @hw: pointer to hardware structure
657 *
658 * used by hardware layer to print debugging information
9d5c8243 659 **/
c041076a 660struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 661{
662 struct igb_adapter *adapter = hw->back;
c041076a 663 return adapter->netdev;
9d5c8243 664}
38c845c7 665
9d5c8243 666/**
b980ac18 667 * igb_init_module - Driver Registration Routine
9d5c8243 668 *
b980ac18
JK		 669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 671 **/
672static int __init igb_init_module(void)
673{
674 int ret;
9005df38 675
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243 677 igb_driver_string, igb_driver_version);
876d2d6f 678 pr_info("%s\n", igb_copyright);
9d5c8243 679
421e02f0 680#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 681 dca_register_notify(&dca_notifier);
682#endif
bbd98fe4 683 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 684 return ret;
685}
686
687module_init(igb_init_module);
688
689/**
b980ac18 690 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 691 *
b980ac18
JK		 692 * igb_exit_module is called just before the driver is removed
693 * from memory.
9d5c8243
AK		 694 **/
695static void __exit igb_exit_module(void)
696{
421e02f0 697#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 698 dca_unregister_notify(&dca_notifier);
699#endif
9d5c8243
AK		 700 pci_unregister_driver(&igb_driver);
701}
702
703module_exit(igb_exit_module);
704
26bc19ec
AD		 705#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706/**
b980ac18
JK		 707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
26bc19ec 709 *
b980ac18
JK		 710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 712 **/
713static void igb_cache_ring_register(struct igb_adapter *adapter)
714{
ee1b9f06 715 int i = 0, j = 0;
047e0030 716 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
ee1b9f06 725 if (adapter->vfs_allocated_count) {
a99955fc 726 for (; i < adapter->rss_queues; i++)
3025a446 727 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 728 Q_IDX_82576(i);
ee1b9f06 729 }
b26141d4 730 /* Fall through */
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
ceb5f13b 734 case e1000_i354:
f96a8a0b
CW		 735 case e1000_i210:
736 case e1000_i211:
b26141d4 737 /* Fall through */
26bc19ec 738 default:
ee1b9f06 739 for (; i < adapter->num_rx_queues; i++)
3025a446 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 741 for (; j < adapter->num_tx_queues; j++)
3025a446 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 743 break;
744 }
745}
746
22a8b291
FT		 747u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748{
749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
751 u32 value = 0;
752
753 if (E1000_REMOVED(hw_addr))
754 return ~value;
755
756 value = readl(&hw_addr[reg]);
757
758 /* reads should not return all F's */
759 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
760 struct net_device *netdev = igb->netdev;
761 hw->hw_addr = NULL;
762 netif_device_detach(netdev);
763 netdev_err(netdev, "PCIe link lost, device now detached\n");
764 }
765
766 return value;
767}
768
4be000c8
AD		 769/**
770 * igb_write_ivar - configure ivar for given MSI-X vector
771 * @hw: pointer to the HW structure
772 * @msix_vector: vector number we are allocating to a given ring
773 * @index: row index of IVAR register to write within IVAR table
774 * @offset: column offset of in IVAR, should be multiple of 8
775 *
776 * This function is intended to handle the writing of the IVAR register
777 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
778 * each containing an cause allocation for an Rx and Tx ring, and a
779 * variable number of rows depending on the number of queues supported.
780 **/
781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
782 int index, int offset)
783{
784 u32 ivar = array_rd32(E1000_IVAR0, index);
785
786 /* clear any bits that are currently set */
787 ivar &= ~((u32)0xFF << offset);
788
789 /* write vector and valid bit */
790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791
792 array_wr32(E1000_IVAR0, index, ivar);
793}
794
9d5c8243 795#define IGB_N0_QUEUE -1
047e0030 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 797{
047e0030 798 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 799 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 800 int rx_queue = IGB_N0_QUEUE;
801 int tx_queue = IGB_N0_QUEUE;
4be000c8 802 u32 msixbm = 0;
047e0030 803
0ba82994
AD		 804 if (q_vector->rx.ring)
805 rx_queue = q_vector->rx.ring->reg_idx;
806 if (q_vector->tx.ring)
807 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 808
809 switch (hw->mac.type) {
810 case e1000_82575:
9d5c8243 811 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one
813 * or more queues to a vector, we write the appropriate bits
814 * into the MSIXBM register for that vector.
815 */
047e0030 816 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 818 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 821 msixbm |= E1000_EIMS_OTHER;
9d5c8243 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 823 q_vector->eims_value = msixbm;
2d064c06
AD		 824 break;
825 case e1000_82576:
b980ac18 826 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 827 * with 8 rows. The ordering is column-major so we use the
828 * lower 3 bits as the row index, and the 4th bit as the
829 * column offset.
830 */
831 if (rx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 rx_queue & 0x7,
834 (rx_queue & 0x8) << 1);
835 if (tx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8);
a51d8c21 839 q_vector->eims_value = BIT(msix_vector);
2d064c06 840 break;
55cac248 841 case e1000_82580:
d2ba2ed8 842 case e1000_i350:
ceb5f13b 843 case e1000_i354:
f96a8a0b
CW		 844 case e1000_i210:
845 case e1000_i211:
b980ac18 846 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 847 * however instead of ordering column-major we have things
848 * ordered row-major. So we traverse the table by using
849 * bit 0 as the column offset, and the remaining bits as the
850 * row index.
851 */
852 if (rx_queue > IGB_N0_QUEUE)
853 igb_write_ivar(hw, msix_vector,
854 rx_queue >> 1,
855 (rx_queue & 0x1) << 4);
856 if (tx_queue > IGB_N0_QUEUE)
857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8);
a51d8c21 860 q_vector->eims_value = BIT(msix_vector);
55cac248 861 break;
2d064c06
AD		 862 default:
863 BUG();
864 break;
865 }
26b39276
AD		 866
867 /* add q_vector eims value to global eims_enable_mask */
868 adapter->eims_enable_mask |= q_vector->eims_value;
869
870 /* configure q_vector to set itr on first interrupt */
871 q_vector->set_itr = 1;
9d5c8243
AK		 872}
873
874/**
b980ac18
JK		 875 * igb_configure_msix - Configure MSI-X hardware
876 * @adapter: board private structure to initialize
9d5c8243 877 *
b980ac18
JK		 878 * igb_configure_msix sets up the hardware to properly
879 * generate MSI-X interrupts.
9d5c8243
AK		 880 **/
881static void igb_configure_msix(struct igb_adapter *adapter)
882{
883 u32 tmp;
884 int i, vector = 0;
885 struct e1000_hw *hw = &adapter->hw;
886
887 adapter->eims_enable_mask = 0;
9d5c8243
AK		 888
889 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 890 switch (hw->mac.type) {
891 case e1000_82575:
9d5c8243
AK		 892 tmp = rd32(E1000_CTRL_EXT);
893 /* enable MSI-X PBA support*/
894 tmp |= E1000_CTRL_EXT_PBA_CLR;
895
896 /* Auto-Mask interrupts upon ICR read. */
897 tmp |= E1000_CTRL_EXT_EIAME;
898 tmp |= E1000_CTRL_EXT_IRCA;
899
900 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 901
902 /* enable msix_other interrupt */
b980ac18 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 904 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 905
2d064c06
AD		 906 break;
907
908 case e1000_82576:
55cac248 909 case e1000_82580:
d2ba2ed8 910 case e1000_i350:
ceb5f13b 911 case e1000_i354:
f96a8a0b
CW		 912 case e1000_i210:
913 case e1000_i211:
047e0030 914 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 915 * won't stick. And it will take days to debug.
916 */
047e0030 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 918 E1000_GPIE_PBA | E1000_GPIE_EIAME |
919 E1000_GPIE_NSICR);
047e0030
AD		 920
921 /* enable msix_other interrupt */
a51d8c21 922 adapter->eims_other = BIT(vector);
2d064c06 923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 924
047e0030 925 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 926 break;
927 default:
928 /* do nothing, since nothing else supports MSI-X */
929 break;
930 } /* switch (hw->mac.type) */
047e0030
AD		 931
932 adapter->eims_enable_mask |= adapter->eims_other;
933
26b39276
AD		 934 for (i = 0; i < adapter->num_q_vectors; i++)
935 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 936
9d5c8243
AK		 937 wrfl();
938}
939
940/**
b980ac18
JK		 941 * igb_request_msix - Initialize MSI-X interrupts
942 * @adapter: board private structure to initialize
9d5c8243 943 *
b980ac18
JK		 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
945 * kernel.
9d5c8243
AK		 946 **/
947static int igb_request_msix(struct igb_adapter *adapter)
948{
949 struct net_device *netdev = adapter->netdev;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
7b06a690 962 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
17a402a0
CW		 1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
2439fc4d 1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d 1209 q_vector = adapter->q_vector[v_idx];
72ddef05 1210 if (!q_vector) {
02ef6e1d 1211 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1215 } else {
c0a06ee1 1216 memset(q_vector, 0, size);
72ddef05 1217 }
5536d210
AD		 1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232 /* initialize ITR configuration */
7b06a690 1233 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1234 q_vector->itr_val = IGB_START_ITR;
1235
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1238
4e227667
AD		 1239 /* intialize ITR */
1240 if (rxr_count) {
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
5536d210
AD		 1250 if (txr_count) {
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1257
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
827da44c
JS		 1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
5536d210
AD		 1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
047e0030 1277 }
81c2fc22 1278
5536d210
AD		 1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
047e0030 1283
5536d210
AD		 1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
047e0030 1286
5536d210
AD		 1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
047e0030 1289
5536d210
AD		 1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1293
e52c0f96 1294 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1295 * have the tag byte-swapped.
b980ac18 1296 */
5536d210
AD		 1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1299
5536d210
AD		 1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
827da44c
JS		 1304 u64_stats_init(&ring->rx_syncp);
1305
5536d210
AD		 1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
047e0030
AD		 1311}
1312
5536d210 1313
047e0030 1314/**
b980ac18
JK		 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
047e0030 1317 *
b980ac18
JK		 1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1319 * return -ENOMEM.
047e0030 1320 **/
5536d210 1321static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1322{
5536d210
AD		 1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
047e0030 1328
5536d210
AD		 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
047e0030 1333
5536d210
AD		 1334 if (err)
1335 goto err_out;
1336
1337 /* update counts and index */
1338 rxr_remaining--;
1339 rxr_idx++;
047e0030 1340 }
047e0030 1341 }
5536d210
AD		 1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1346
5536d210
AD		 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
047e0030 1360 return 0;
5536d210
AD		 1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
047e0030
AD		 1371}
1372
1373/**
b980ac18
JK		 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
047e0030 1377 *
b980ac18 1378 * This function initializes the interrupts and allocates all of the queues.
047e0030 1379 **/
53c7d064 1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
53c7d064 1385 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
5536d210 1393 igb_cache_ring_register(adapter);
047e0030
AD		 1394
1395 return 0;
5536d210 1396
047e0030
AD		 1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
9d5c8243 1402/**
b980ac18
JK		 1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
9d5c8243 1405 *
b980ac18
JK		 1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
9d5c8243
AK		 1408 **/
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
047e0030 1412 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1413 int err = 0;
1414
cd14ef54 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1416 err = igb_request_msix(adapter);
844290e5 1417 if (!err)
9d5c8243 1418 goto request_done;
9d5c8243 1419 /* fall back to MSI */
5536d210
AD		 1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
53c7d064 1422
047e0030 1423 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
047e0030 1426 goto request_done;
53c7d064 1427
047e0030
AD		 1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
53c7d064 1430 igb_configure(adapter);
9d5c8243 1431 }
844290e5 1432
c74d588e
AD		 1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
7dfc16fa 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1437 netdev->name, adapter);
9d5c8243
AK		 1438 if (!err)
1439 goto request_done;
047e0030 1440
9d5c8243
AK		 1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
7dfc16fa 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1444 }
1445
c74d588e 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1447 netdev->name, adapter);
9d5c8243 1448
6cb5e577 1449 if (err)
c74d588e 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1451 err);
9d5c8243
AK		 1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
cd14ef54 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1460 int vector = 0, i;
1461
047e0030 1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1463
0d1ae7f4 1464 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1465 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1466 adapter->q_vector[i]);
047e0030
AD		 1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1469 }
9d5c8243
AK		 1470}
1471
1472/**
b980ac18
JK		 1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
9d5c8243
AK		 1475 **/
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
b980ac18 1480 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
cd14ef54 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1485 u32 regval = rd32(E1000_EIAM);
9005df38 1486
2dfd1212
AD		 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1491 }
844290e5
PW		 1492
1493 wr32(E1000_IAM, 0);
9d5c8243
AK		 1494 wr32(E1000_IMC, ~0);
1495 wrfl();
cd14ef54 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1497 int i;
9005df38 1498
81a61859
ET		 1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
9d5c8243
AK		 1504}
1505
1506/**
b980ac18
JK		 1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
9d5c8243
AK		 1509 **/
1510static void igb_irq_enable(struct igb_adapter *adapter)
1511{
1512 struct e1000_hw *hw = &adapter->hw;
1513
cd14ef54 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1516 u32 regval = rd32(E1000_EIAC);
9005df38 1517
2dfd1212
AD		 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1522 if (adapter->vfs_allocated_count) {
4ae196df 1523 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
844290e5 1527 } else {
55cac248
AD		 1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
844290e5 1532 }
9d5c8243
AK		 1533}
1534
1535static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536{
51466239 1537 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1538 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1539 u16 vid = adapter->hw.mng_cookie.vlan_id;
1540 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1541
1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543 /* add VID to filter table */
8b77c6b2 1544 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1545 adapter->mng_vlan_id = vid;
1546 } else {
1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548 }
1549
1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551 (vid != old_vid) &&
b2cb09b1 1552 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1553 /* remove VID from filter table */
8b77c6b2 1554 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1555 }
1556}
1557
1558/**
b980ac18
JK		 1559 * igb_release_hw_control - release control of the h/w to f/w
1560 * @adapter: address of board private structure
9d5c8243 1561 *
b980ac18
JK		 1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563 * For ASF and Pass Through versions of f/w this means that the
1564 * driver is no longer loaded.
9d5c8243
AK		 1565 **/
1566static void igb_release_hw_control(struct igb_adapter *adapter)
1567{
1568 struct e1000_hw *hw = &adapter->hw;
1569 u32 ctrl_ext;
1570
1571 /* Let firmware take over control of h/w */
1572 ctrl_ext = rd32(E1000_CTRL_EXT);
1573 wr32(E1000_CTRL_EXT,
1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575}
1576
9d5c8243 1577/**
b980ac18
JK		 1578 * igb_get_hw_control - get control of the h/w from f/w
1579 * @adapter: address of board private structure
9d5c8243 1580 *
b980ac18
JK		 1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582 * For ASF and Pass Through versions of f/w this means that
1583 * the driver is loaded.
9d5c8243
AK		 1584 **/
1585static void igb_get_hw_control(struct igb_adapter *adapter)
1586{
1587 struct e1000_hw *hw = &adapter->hw;
1588 u32 ctrl_ext;
1589
1590 /* Let firmware know the driver has taken over */
1591 ctrl_ext = rd32(E1000_CTRL_EXT);
1592 wr32(E1000_CTRL_EXT,
1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594}
1595
9d5c8243 1596/**
b980ac18
JK		 1597 * igb_configure - configure the hardware for RX and TX
1598 * @adapter: private board structure
9d5c8243
AK		 1599 **/
1600static void igb_configure(struct igb_adapter *adapter)
1601{
1602 struct net_device *netdev = adapter->netdev;
1603 int i;
1604
1605 igb_get_hw_control(adapter);
ff41f8dc 1606 igb_set_rx_mode(netdev);
9d5c8243
AK		 1607
1608 igb_restore_vlan(adapter);
9d5c8243 1609
85b430b4 1610 igb_setup_tctl(adapter);
06cf2666 1611 igb_setup_mrqc(adapter);
9d5c8243 1612 igb_setup_rctl(adapter);
85b430b4
AD		 1613
1614 igb_configure_tx(adapter);
9d5c8243 1615 igb_configure_rx(adapter);
662d7205
AD		 1616
1617 igb_rx_fifo_flush_82575(&adapter->hw);
1618
c493ea45 1619 /* call igb_desc_unused which always leaves
9d5c8243 1620 * at least 1 descriptor unused to make sure
b980ac18
JK		 1621 * next_to_use != next_to_clean
1622 */
9d5c8243 1623 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1624 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1625 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1626 }
9d5c8243
AK		 1627}
1628
88a268c1 1629/**
b980ac18
JK		 1630 * igb_power_up_link - Power up the phy/serdes link
1631 * @adapter: address of board private structure
88a268c1
NN		 1632 **/
1633void igb_power_up_link(struct igb_adapter *adapter)
1634{
76886596
AA		 1635 igb_reset_phy(&adapter->hw);
1636
88a268c1
NN		 1637 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1638 igb_power_up_phy_copper(&adapter->hw);
1639 else
1640 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1641
1642 igb_setup_link(&adapter->hw);
88a268c1
NN		 1643}
1644
1645/**
b980ac18
JK		 1646 * igb_power_down_link - Power down the phy/serdes link
1647 * @adapter: address of board private structure
88a268c1
NN		 1648 */
1649static void igb_power_down_link(struct igb_adapter *adapter)
1650{
1651 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1652 igb_power_down_phy_copper_82575(&adapter->hw);
1653 else
1654 igb_shutdown_serdes_link_82575(&adapter->hw);
1655}
9d5c8243 1656
56cec249
CW		 1657/**
1658 * Detect and switch function for Media Auto Sense
1659 * @adapter: address of the board private structure
1660 **/
1661static void igb_check_swap_media(struct igb_adapter *adapter)
1662{
1663 struct e1000_hw *hw = &adapter->hw;
1664 u32 ctrl_ext, connsw;
1665 bool swap_now = false;
1666
1667 ctrl_ext = rd32(E1000_CTRL_EXT);
1668 connsw = rd32(E1000_CONNSW);
1669
1670 /* need to live swap if current media is copper and we have fiber/serdes
1671 * to go to.
1672 */
1673
1674 if ((hw->phy.media_type == e1000_media_type_copper) &&
1675 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1676 swap_now = true;
1677 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1678 /* copper signal takes time to appear */
1679 if (adapter->copper_tries < 4) {
1680 adapter->copper_tries++;
1681 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1682 wr32(E1000_CONNSW, connsw);
1683 return;
1684 } else {
1685 adapter->copper_tries = 0;
1686 if ((connsw & E1000_CONNSW_PHYSD) &&
1687 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1688 swap_now = true;
1689 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1690 wr32(E1000_CONNSW, connsw);
1691 }
1692 }
1693 }
1694
1695 if (!swap_now)
1696 return;
1697
1698 switch (hw->phy.media_type) {
1699 case e1000_media_type_copper:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to fiber/serdes\n");
1702 ctrl_ext |=
1703 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 adapter->copper_tries = 0;
1706 break;
1707 case e1000_media_type_internal_serdes:
1708 case e1000_media_type_fiber:
1709 netdev_info(adapter->netdev,
1710 "MAS: changing media to copper\n");
1711 ctrl_ext &=
1712 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1713 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1714 break;
1715 default:
1716 /* shouldn't get here during regular operation */
1717 netdev_err(adapter->netdev,
1718 "AMS: Invalid media type found, returning\n");
1719 break;
1720 }
1721 wr32(E1000_CTRL_EXT, ctrl_ext);
1722}
1723
9d5c8243 1724/**
b980ac18
JK		 1725 * igb_up - Open the interface and prepare it to handle traffic
1726 * @adapter: board private structure
9d5c8243 1727 **/
9d5c8243
AK		 1728int igb_up(struct igb_adapter *adapter)
1729{
1730 struct e1000_hw *hw = &adapter->hw;
1731 int i;
1732
1733 /* hardware has been reset, we need to reload some things */
1734 igb_configure(adapter);
1735
1736 clear_bit(__IGB_DOWN, &adapter->state);
1737
0d1ae7f4
AD		 1738 for (i = 0; i < adapter->num_q_vectors; i++)
1739 napi_enable(&(adapter->q_vector[i]->napi));
1740
cd14ef54 1741 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1742 igb_configure_msix(adapter);
feeb2721
AD		 1743 else
1744 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1745
1746 /* Clear any pending interrupts. */
1747 rd32(E1000_ICR);
1748 igb_irq_enable(adapter);
1749
d4960307
AD		 1750 /* notify VFs that reset has been completed */
1751 if (adapter->vfs_allocated_count) {
1752 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1753
d4960307
AD		 1754 reg_data |= E1000_CTRL_EXT_PFRSTD;
1755 wr32(E1000_CTRL_EXT, reg_data);
1756 }
1757
4cb9be7a
JB		 1758 netif_tx_start_all_queues(adapter->netdev);
1759
25568a53
AD		 1760 /* start the watchdog. */
1761 hw->mac.get_link_status = 1;
1762 schedule_work(&adapter->watchdog_task);
1763
f4c01e96
CW		 1764 if ((adapter->flags & IGB_FLAG_EEE) &&
1765 (!hw->dev_spec._82575.eee_disable))
1766 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1767
9d5c8243
AK		 1768 return 0;
1769}
1770
1771void igb_down(struct igb_adapter *adapter)
1772{
9d5c8243 1773 struct net_device *netdev = adapter->netdev;
330a6d6a 1774 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1775 u32 tctl, rctl;
1776 int i;
1777
1778 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1779 * reschedule our watchdog timer
1780 */
9d5c8243
AK		 1781 set_bit(__IGB_DOWN, &adapter->state);
1782
1783 /* disable receives in the hardware */
1784 rctl = rd32(E1000_RCTL);
1785 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1786 /* flush and sleep below */
1787
f28ea083 1788 netif_carrier_off(netdev);
fd2ea0a7 1789 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1790
1791 /* disable transmits in the hardware */
1792 tctl = rd32(E1000_TCTL);
1793 tctl &= ~E1000_TCTL_EN;
1794 wr32(E1000_TCTL, tctl);
1795 /* flush both disables and wait for them to finish */
1796 wrfl();
0d451e79 1797 usleep_range(10000, 11000);
9d5c8243 1798
41f149a2
CW		 1799 igb_irq_disable(adapter);
1800
aa9b8cc4
AA		 1801 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1802
41f149a2 1803 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1804 if (adapter->q_vector[i]) {
1805 napi_synchronize(&adapter->q_vector[i]->napi);
1806 napi_disable(&adapter->q_vector[i]->napi);
1807 }
41f149a2 1808 }
9d5c8243 1809
9d5c8243
AK		 1810 del_timer_sync(&adapter->watchdog_timer);
1811 del_timer_sync(&adapter->phy_info_timer);
1812
04fe6358 1813 /* record the stats before reset*/
12dcd86b
ED		 1814 spin_lock(&adapter->stats64_lock);
1815 igb_update_stats(adapter, &adapter->stats64);
1816 spin_unlock(&adapter->stats64_lock);
04fe6358 1817
9d5c8243
AK		 1818 adapter->link_speed = 0;
1819 adapter->link_duplex = 0;
1820
3023682e
JK		 1821 if (!pci_channel_offline(adapter->pdev))
1822 igb_reset(adapter);
16903caa
AD		 1823
1824 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1825 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1826
9d5c8243
AK		 1827 igb_clean_all_tx_rings(adapter);
1828 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1829#ifdef CONFIG_IGB_DCA
1830
1831 /* since we reset the hardware DCA settings were cleared */
1832 igb_setup_dca(adapter);
1833#endif
9d5c8243
AK		 1834}
1835
1836void igb_reinit_locked(struct igb_adapter *adapter)
1837{
1838 WARN_ON(in_interrupt());
1839 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1840 usleep_range(1000, 2000);
9d5c8243
AK		 1841 igb_down(adapter);
1842 igb_up(adapter);
1843 clear_bit(__IGB_RESETTING, &adapter->state);
1844}
1845
56cec249
CW		 1846/** igb_enable_mas - Media Autosense re-enable after swap
1847 *
1848 * @adapter: adapter struct
1849 **/
8cfb879d 1850static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1851{
1852 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1853 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1854
1855 /* configure for SerDes media detect */
8cfb879d
TF		 1856 if ((hw->phy.media_type == e1000_media_type_copper) &&
1857 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1858 connsw |= E1000_CONNSW_ENRGSRC;
1859 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1860 wr32(E1000_CONNSW, connsw);
1861 wrfl();
56cec249 1862 }
56cec249
CW		 1863}
1864
9d5c8243
AK		 1865void igb_reset(struct igb_adapter *adapter)
1866{
090b1795 1867 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1868 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1869 struct e1000_mac_info *mac = &hw->mac;
1870 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1871 u32 pba, hwm;
9d5c8243
AK		 1872
1873 /* Repartition Pba for greater than 9k mtu
1874 * To take effect CTRL.RST is required.
1875 */
fa4dfae0 1876 switch (mac->type) {
d2ba2ed8 1877 case e1000_i350:
ceb5f13b 1878 case e1000_i354:
55cac248
AD		 1879 case e1000_82580:
1880 pba = rd32(E1000_RXPBS);
1881 pba = igb_rxpbs_adjust_82580(pba);
1882 break;
fa4dfae0 1883 case e1000_82576:
d249be54
AD		 1884 pba = rd32(E1000_RXPBS);
1885 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1886 break;
1887 case e1000_82575:
f96a8a0b
CW		 1888 case e1000_i210:
1889 case e1000_i211:
fa4dfae0
AD		 1890 default:
1891 pba = E1000_PBA_34K;
1892 break;
2d064c06 1893 }
9d5c8243 1894
45693bcb
AD		 1895 if (mac->type == e1000_82575) {
1896 u32 min_rx_space, min_tx_space, needed_tx_space;
1897
1898 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1906 * expressed in KB.
1907 */
45693bcb
AD		 1908 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1909
1910 /* The Tx FIFO also stores 16 bytes of information about the Tx
1911 * but don't include Ethernet FCS because hardware appends it.
1912 * We only need to round down to the nearest 512 byte block
1913 * count since the value we care about is 2 frames, not 1.
b980ac18 1914 */
45693bcb
AD		 1915 min_tx_space = adapter->max_frame_size;
1916 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1917 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1918
1919 /* upper 16 bits has Tx packet buffer allocation size in KB */
1920 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1921
1922 /* If current Tx allocation is less than the min Tx FIFO size,
1923 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1924 * allocation, take space away from current Rx allocation.
b980ac18 1925 */
45693bcb
AD		 1926 if (needed_tx_space < pba) {
1927 pba -= needed_tx_space;
9d5c8243 1928
b980ac18
JK		 1929 /* if short on Rx space, Rx wins and must trump Tx
1930 * adjustment
1931 */
9d5c8243
AK		 1932 if (pba < min_rx_space)
1933 pba = min_rx_space;
1934 }
45693bcb
AD		 1935
1936 /* adjust PBA for jumbo frames */
2d064c06 1937 wr32(E1000_PBA, pba);
9d5c8243 1938 }
9d5c8243 1939
45693bcb
AD		 1940 /* flow control settings
1941 * The high water mark must be low enough to fit one full frame
1942 * after transmitting the pause frame. As such we must have enough
1943 * space to allow for us to complete our current transmit and then
1944 * receive the frame that is in progress from the link partner.
1945 * Set it to:
1946 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1947 */
45693bcb 1948 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1949
d48507fe 1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1951 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1952 fc->pause_time = 0xFFFF;
1953 fc->send_xon = 1;
0cce119a 1954 fc->current_mode = fc->requested_mode;
9d5c8243 1955
4ae196df
AD		 1956 /* disable receive for all VFs and wait one second */
1957 if (adapter->vfs_allocated_count) {
1958 int i;
9005df38 1959
4ae196df 1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1962
1963 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1964 igb_ping_all_vfs(adapter);
4ae196df
AD		 1965
1966 /* disable transmits and receives */
1967 wr32(E1000_VFRE, 0);
1968 wr32(E1000_VFTE, 0);
1969 }
1970
9d5c8243 1971 /* Allow time for pending master requests to run */
330a6d6a 1972 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1973 wr32(E1000_WUC, 0);
1974
56cec249
CW		 1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1976 /* need to resetup here after media swap */
1977 adapter->ei.get_invariants(hw);
1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1979 }
8cfb879d
TF		 1980 if ((mac->type == e1000_82575) &&
1981 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1982 igb_enable_mas(adapter);
56cec249 1983 }
330a6d6a 1984 if (hw->mac.ops.init_hw(hw))
090b1795 1985 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1986
b980ac18 1987 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1988 * control is off when forcing speed.
1989 */
1990 if (!hw->mac.autoneg)
1991 igb_force_mac_fc(hw);
1992
b6e0c419 1993 igb_init_dmac(adapter, pba);
e428893b
CW		 1994#ifdef CONFIG_IGB_HWMON
1995 /* Re-initialize the thermal sensor on i350 devices. */
1996 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1997 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1998 /* If present, re-initialize the external thermal sensor
1999 * interface.
2000 */
2001 if (adapter->ets)
2002 mac->ops.init_thermal_sensor_thresh(hw);
2003 }
2004 }
2005#endif
b936136d 2006 /* Re-establish EEE setting */
f4c01e96
CW		 2007 if (hw->phy.media_type == e1000_media_type_copper) {
2008 switch (mac->type) {
2009 case e1000_i350:
2010 case e1000_i210:
2011 case e1000_i211:
c4c112f1 2012 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2013 break;
2014 case e1000_i354:
c4c112f1 2015 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2016 break;
2017 default:
2018 break;
2019 }
2020 }
88a268c1
NN		 2021 if (!netif_running(adapter->netdev))
2022 igb_power_down_link(adapter);
2023
9d5c8243
AK		 2024 igb_update_mng_vlan(adapter);
2025
2026 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2027 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2028
1f6e8178 2029 /* Re-enable PTP, where applicable. */
4f3ce71b
JK		 2030 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2031 igb_ptp_reset(adapter);
1f6e8178 2032
330a6d6a 2033 igb_get_phy_info(hw);
9d5c8243
AK		 2034}
2035
c8f44aff
MM		 2036static netdev_features_t igb_fix_features(struct net_device *netdev,
2037 netdev_features_t features)
b2cb09b1 2038{
b980ac18
JK		 2039 /* Since there is no support for separate Rx/Tx vlan accel
2040 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2041 */
f646968f
PM		 2042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2043 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2044 else
f646968f 2045 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2046
2047 return features;
2048}
2049
c8f44aff
MM		 2050static int igb_set_features(struct net_device *netdev,
2051 netdev_features_t features)
ac52caa3 2052{
c8f44aff 2053 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2054 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2055
f646968f 2056 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2057 igb_vlan_mode(netdev, features);
2058
16903caa 2059 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2060 return 0;
2061
2062 netdev->features = features;
2063
2064 if (netif_running(netdev))
2065 igb_reinit_locked(adapter);
2066 else
2067 igb_reset(adapter);
2068
ac52caa3
MM		 2069 return 0;
2070}
2071
268f9d33
AD		 2072static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2073 struct net_device *dev,
2074 const unsigned char *addr, u16 vid,
2075 u16 flags)
2076{
2077 /* guarantee we can provide a unique filter for the unicast address */
2078 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2079 struct igb_adapter *adapter = netdev_priv(dev);
2080 struct e1000_hw *hw = &adapter->hw;
2081 int vfn = adapter->vfs_allocated_count;
2082 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2083
2084 if (netdev_uc_count(dev) >= rar_entries)
2085 return -ENOMEM;
2086 }
2087
2088 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2089}
2090
e10715d3
AD		 2091#define IGB_MAX_MAC_HDR_LEN 127
2092#define IGB_MAX_NETWORK_HDR_LEN 511
2093
2094static netdev_features_t
2095igb_features_check(struct sk_buff *skb, struct net_device *dev,
2096 netdev_features_t features)
2097{
2098 unsigned int network_hdr_len, mac_hdr_len;
2099
2100 /* Make certain the headers can be described by a context descriptor */
2101 mac_hdr_len = skb_network_header(skb) - skb->data;
2102 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2103 return features & ~(NETIF_F_HW_CSUM |
2104 NETIF_F_SCTP_CRC |
2105 NETIF_F_HW_VLAN_CTAG_TX |
2106 NETIF_F_TSO |
2107 NETIF_F_TSO6);
2108
2109 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2110 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2111 return features & ~(NETIF_F_HW_CSUM |
2112 NETIF_F_SCTP_CRC |
2113 NETIF_F_TSO |
2114 NETIF_F_TSO6);
2115
2116 /* We can only support IPV4 TSO in tunnels if we can mangle the
2117 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2118 */
2119 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2120 features &= ~NETIF_F_TSO;
2121
2122 return features;
2123}
2124
2e5c6922 2125static const struct net_device_ops igb_netdev_ops = {
559e9c49 2126 .ndo_open = igb_open,
2e5c6922 2127 .ndo_stop = igb_close,
cd392f5c 2128 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2129 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2130 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2131 .ndo_set_mac_address = igb_set_mac,
2132 .ndo_change_mtu = igb_change_mtu,
2133 .ndo_do_ioctl = igb_ioctl,
2134 .ndo_tx_timeout = igb_tx_timeout,
2135 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2136 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2137 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2138 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2139 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2140 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2141 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2142 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2143#ifdef CONFIG_NET_POLL_CONTROLLER
2144 .ndo_poll_controller = igb_netpoll,
2145#endif
b2cb09b1
JP		 2146 .ndo_fix_features = igb_fix_features,
2147 .ndo_set_features = igb_set_features,
268f9d33 2148 .ndo_fdb_add = igb_ndo_fdb_add,
e10715d3 2149 .ndo_features_check = igb_features_check,
2e5c6922
SH		 2150};
2151
d67974f0
CW		 2152/**
2153 * igb_set_fw_version - Configure version string for ethtool
2154 * @adapter: adapter struct
d67974f0
CW		 2155 **/
2156void igb_set_fw_version(struct igb_adapter *adapter)
2157{
2158 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2159 struct e1000_fw_version fw;
2160
2161 igb_get_fw_version(hw, &fw);
2162
2163 switch (hw->mac.type) {
7dc98a62 2164 case e1000_i210:
0b1a6f2e 2165 case e1000_i211:
7dc98a62
CW		 2166 if (!(igb_get_flash_presence_i210(hw))) {
2167 snprintf(adapter->fw_version,
2168 sizeof(adapter->fw_version),
2169 "%2d.%2d-%d",
2170 fw.invm_major, fw.invm_minor,
2171 fw.invm_img_type);
2172 break;
2173 }
2174 /* fall through */
0b1a6f2e
CW		 2175 default:
2176 /* if option is rom valid, display its version too */
2177 if (fw.or_valid) {
2178 snprintf(adapter->fw_version,
2179 sizeof(adapter->fw_version),
2180 "%d.%d, 0x%08x, %d.%d.%d",
2181 fw.eep_major, fw.eep_minor, fw.etrack_id,
2182 fw.or_major, fw.or_build, fw.or_patch);
2183 /* no option rom */
7dc98a62 2184 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2185 snprintf(adapter->fw_version,
7dc98a62
CW		 2186 sizeof(adapter->fw_version),
2187 "%d.%d, 0x%08x",
2188 fw.eep_major, fw.eep_minor, fw.etrack_id);
2189 } else {
2190 snprintf(adapter->fw_version,
2191 sizeof(adapter->fw_version),
2192 "%d.%d.%d",
2193 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2194 }
2195 break;
d67974f0 2196 }
d67974f0
CW		 2197}
2198
56cec249
CW		 2199/**
2200 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2201 *
2202 * @adapter: adapter struct
2203 **/
2204static void igb_init_mas(struct igb_adapter *adapter)
2205{
2206 struct e1000_hw *hw = &adapter->hw;
2207 u16 eeprom_data;
2208
2209 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2210 switch (hw->bus.func) {
2211 case E1000_FUNC_0:
2212 if (eeprom_data & IGB_MAS_ENABLE_0) {
2213 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2214 netdev_info(adapter->netdev,
2215 "MAS: Enabling Media Autosense for port %d\n",
2216 hw->bus.func);
2217 }
2218 break;
2219 case E1000_FUNC_1:
2220 if (eeprom_data & IGB_MAS_ENABLE_1) {
2221 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2222 netdev_info(adapter->netdev,
2223 "MAS: Enabling Media Autosense for port %d\n",
2224 hw->bus.func);
2225 }
2226 break;
2227 case E1000_FUNC_2:
2228 if (eeprom_data & IGB_MAS_ENABLE_2) {
2229 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2230 netdev_info(adapter->netdev,
2231 "MAS: Enabling Media Autosense for port %d\n",
2232 hw->bus.func);
2233 }
2234 break;
2235 case E1000_FUNC_3:
2236 if (eeprom_data & IGB_MAS_ENABLE_3) {
2237 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2238 netdev_info(adapter->netdev,
2239 "MAS: Enabling Media Autosense for port %d\n",
2240 hw->bus.func);
2241 }
2242 break;
2243 default:
2244 /* Shouldn't get here */
2245 netdev_err(adapter->netdev,
2246 "MAS: Invalid port configuration, returning\n");
2247 break;
2248 }
2249}
2250
b980ac18
JK		 2251/**
2252 * igb_init_i2c - Init I2C interface
441fc6fd 2253 * @adapter: pointer to adapter structure
b980ac18 2254 **/
441fc6fd
CW		 2255static s32 igb_init_i2c(struct igb_adapter *adapter)
2256{
23d87824 2257 s32 status = 0;
441fc6fd
CW		 2258
2259 /* I2C interface supported on i350 devices */
2260 if (adapter->hw.mac.type != e1000_i350)
23d87824 2261 return 0;
441fc6fd
CW		 2262
2263 /* Initialize the i2c bus which is controlled by the registers.
2264 * This bus will use the i2c_algo_bit structue that implements
2265 * the protocol through toggling of the 4 bits in the register.
2266 */
2267 adapter->i2c_adap.owner = THIS_MODULE;
2268 adapter->i2c_algo = igb_i2c_algo;
2269 adapter->i2c_algo.data = adapter;
2270 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2271 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2272 strlcpy(adapter->i2c_adap.name, "igb BB",
2273 sizeof(adapter->i2c_adap.name));
2274 status = i2c_bit_add_bus(&adapter->i2c_adap);
2275 return status;
2276}
2277
9d5c8243 2278/**
b980ac18
JK		 2279 * igb_probe - Device Initialization Routine
2280 * @pdev: PCI device information struct
2281 * @ent: entry in igb_pci_tbl
9d5c8243 2282 *
b980ac18 2283 * Returns 0 on success, negative on failure
9d5c8243 2284 *
b980ac18
JK		 2285 * igb_probe initializes an adapter identified by a pci_dev structure.
2286 * The OS initialization, configuring of the adapter private structure,
2287 * and a hardware reset occur.
9d5c8243 2288 **/
1dd06ae8 2289static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2290{
2291 struct net_device *netdev;
2292 struct igb_adapter *adapter;
2293 struct e1000_hw *hw;
4337e993 2294 u16 eeprom_data = 0;
9835fd73 2295 s32 ret_val;
4337e993 2296 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2297 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2298 int err, pci_using_dac;
9835fd73 2299 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2300
bded64a7
AG		 2301 /* Catch broken hardware that put the wrong VF device ID in
2302 * the PCIe SR-IOV capability.
2303 */
2304 if (pdev->is_virtfn) {
2305 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2306 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2307 return -EINVAL;
2308 }
2309
aed5dec3 2310 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2311 if (err)
2312 return err;
2313
2314 pci_using_dac = 0;
dc4ff9bb 2315 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2316 if (!err) {
dc4ff9bb 2317 pci_using_dac = 1;
9d5c8243 2318 } else {
dc4ff9bb 2319 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2320 if (err) {
dc4ff9bb
RK		 2321 dev_err(&pdev->dev,
2322 "No usable DMA configuration, aborting\n");
2323 goto err_dma;
9d5c8243
AK		 2324 }
2325 }
2326
aed5dec3 2327 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2328 IORESOURCE_MEM),
2329 igb_driver_name);
9d5c8243
AK		 2330 if (err)
2331 goto err_pci_reg;
2332
19d5afd4 2333 pci_enable_pcie_error_reporting(pdev);
40a914fa 2334
9d5c8243 2335 pci_set_master(pdev);
c682fc23 2336 pci_save_state(pdev);
9d5c8243
AK		 2337
2338 err = -ENOMEM;
1bfaf07b 2339 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2340 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2341 if (!netdev)
2342 goto err_alloc_etherdev;
2343
2344 SET_NETDEV_DEV(netdev, &pdev->dev);
2345
2346 pci_set_drvdata(pdev, netdev);
2347 adapter = netdev_priv(netdev);
2348 adapter->netdev = netdev;
2349 adapter->pdev = pdev;
2350 hw = &adapter->hw;
2351 hw->back = adapter;
b3f4d599 2352 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2353
9d5c8243 2354 err = -EIO;
73bf8048
JW		 2355 adapter->io_addr = pci_iomap(pdev, 0, 0);
2356 if (!adapter->io_addr)
9d5c8243 2357 goto err_ioremap;
73bf8048
JW		 2358 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2359 hw->hw_addr = adapter->io_addr;
9d5c8243 2360
2e5c6922 2361 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2362 igb_set_ethtool_ops(netdev);
9d5c8243 2363 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2364
2365 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2366
89dbefb2
AS		 2367 netdev->mem_start = pci_resource_start(pdev, 0);
2368 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2369
9d5c8243
AK		 2370 /* PCI config space info */
2371 hw->vendor_id = pdev->vendor;
2372 hw->device_id = pdev->device;
2373 hw->revision_id = pdev->revision;
2374 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2375 hw->subsystem_device_id = pdev->subsystem_device;
2376
9d5c8243
AK		 2377 /* Copy the default MAC, PHY and NVM function pointers */
2378 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2379 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2380 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2381 /* Initialize skew-specific constants */
2382 err = ei->get_invariants(hw);
2383 if (err)
450c87c8 2384 goto err_sw_init;
9d5c8243 2385
450c87c8 2386 /* setup the private structure */
9d5c8243
AK		 2387 err = igb_sw_init(adapter);
2388 if (err)
2389 goto err_sw_init;
2390
2391 igb_get_bus_info_pcie(hw);
2392
2393 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2394
2395 /* Copper options */
2396 if (hw->phy.media_type == e1000_media_type_copper) {
2397 hw->phy.mdix = AUTO_ALL_MODES;
2398 hw->phy.disable_polarity_correction = false;
2399 hw->phy.ms_type = e1000_ms_hw_default;
2400 }
2401
2402 if (igb_check_reset_block(hw))
2403 dev_info(&pdev->dev,
2404 "PHY reset is blocked due to SOL/IDER session.\n");
2405
b980ac18 2406 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2407 * set by igb_sw_init so we should use an or instead of an
2408 * assignment.
2409 */
2410 netdev->features |= NETIF_F_SG |
077887c3
AD		 2411 NETIF_F_TSO |
2412 NETIF_F_TSO6 |
2413 NETIF_F_RXHASH |
2414 NETIF_F_RXCSUM |
e10715d3 2415 NETIF_F_HW_CSUM;
077887c3 2416
6e033700
AD		 2417 if (hw->mac.type >= e1000_82576)
2418 netdev->features |= NETIF_F_SCTP_CRC;
2419
e10715d3
AD		 2420#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2421 NETIF_F_GSO_GRE_CSUM | \
7e13318d 2422 NETIF_F_GSO_IPXIP4 | \
bf2d1df3 2423 NETIF_F_GSO_IPXIP6 | \
e10715d3
AD		 2424 NETIF_F_GSO_UDP_TUNNEL | \
2425 NETIF_F_GSO_UDP_TUNNEL_CSUM)
2426
2427 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
2428 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
2429
077887c3 2430 /* copy netdev features into list of user selectable features */
e10715d3
AD		 2431 netdev->hw_features |= netdev->features |
2432 NETIF_F_HW_VLAN_CTAG_RX |
2433 NETIF_F_HW_VLAN_CTAG_TX |
2434 NETIF_F_RXALL;
077887c3 2435
6e033700
AD		 2436 if (hw->mac.type >= e1000_i350)
2437 netdev->hw_features |= NETIF_F_NTUPLE;
2438
e10715d3
AD		 2439 if (pci_using_dac)
2440 netdev->features |= NETIF_F_HIGHDMA;
6e033700 2441
e10715d3 2442 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
6e033700 2443 netdev->mpls_features |= NETIF_F_HW_CSUM;
e10715d3 2444 netdev->hw_enc_features |= netdev->vlan_features;
48f29ffc 2445
e10715d3
AD		 2446 /* set this bit last since it cannot be part of vlan_features */
2447 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2448 NETIF_F_HW_VLAN_CTAG_RX |
2449 NETIF_F_HW_VLAN_CTAG_TX;
6b8f0922 2450
e10715d3 2451 netdev->priv_flags |= IFF_SUPP_NOFCS;
9d5c8243 2452
01789349
JP		 2453 netdev->priv_flags |= IFF_UNICAST_FLT;
2454
330a6d6a 2455 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2456
2457 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2458 * known good starting state
2459 */
9d5c8243
AK		 2460 hw->mac.ops.reset_hw(hw);
2461
ef3a0092
CW		 2462 /* make sure the NVM is good , i211/i210 parts can have special NVM
2463 * that doesn't contain a checksum
f96a8a0b 2464 */
ef3a0092
CW		 2465 switch (hw->mac.type) {
2466 case e1000_i210:
2467 case e1000_i211:
2468 if (igb_get_flash_presence_i210(hw)) {
2469 if (hw->nvm.ops.validate(hw) < 0) {
2470 dev_err(&pdev->dev,
2471 "The NVM Checksum Is Not Valid\n");
2472 err = -EIO;
2473 goto err_eeprom;
2474 }
2475 }
2476 break;
2477 default:
f96a8a0b
CW		 2478 if (hw->nvm.ops.validate(hw) < 0) {
2479 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2480 err = -EIO;
2481 goto err_eeprom;
2482 }
ef3a0092 2483 break;
9d5c8243
AK		 2484 }
2485
806ffb1d
JH		 2486 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
2487 /* copy the MAC address out of the NVM */
2488 if (hw->mac.ops.read_mac_addr(hw))
2489 dev_err(&pdev->dev, "NVM Read Error\n");
2490 }
9d5c8243
AK		 2491
2492 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2493
aaeb6cdf 2494 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2495 dev_err(&pdev->dev, "Invalid MAC Address\n");
2496 err = -EIO;
2497 goto err_eeprom;
2498 }
2499
d67974f0
CW		 2500 /* get firmware version for ethtool -i */
2501 igb_set_fw_version(adapter);
2502
27dff8b2
TF		 2503 /* configure RXPBSIZE and TXPBSIZE */
2504 if (hw->mac.type == e1000_i210) {
2505 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2506 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2507 }
2508
c061b18d 2509 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2510 (unsigned long) adapter);
c061b18d 2511 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2512 (unsigned long) adapter);
9d5c8243
AK		 2513
2514 INIT_WORK(&adapter->reset_task, igb_reset_task);
2515 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2516
450c87c8 2517 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2518 adapter->fc_autoneg = true;
2519 hw->mac.autoneg = true;
2520 hw->phy.autoneg_advertised = 0x2f;
2521
0cce119a
AD		 2522 hw->fc.requested_mode = e1000_fc_default;
2523 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2524
9d5c8243
AK		 2525 igb_validate_mdi_setting(hw);
2526
63d4a8f9 2527 /* By default, support wake on port A */
a2cf8b6c 2528 if (hw->bus.func == 0)
63d4a8f9
MV		 2529 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2530
2531 /* Check the NVM for wake support on non-port A ports */
2532 if (hw->mac.type >= e1000_82580)
55cac248 2533 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2534 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2535 &eeprom_data);
a2cf8b6c
AD		 2536 else if (hw->bus.func == 1)
2537 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2538
63d4a8f9
MV		 2539 if (eeprom_data & IGB_EEPROM_APME)
2540 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2541
2542 /* now that we have the eeprom settings, apply the special cases where
2543 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2544 * lan on a particular port
2545 */
9d5c8243
AK		 2546 switch (pdev->device) {
2547 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2548 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2549 break;
2550 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2551 case E1000_DEV_ID_82576_FIBER:
2552 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2553 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2554 * regardless of eeprom setting
2555 */
9d5c8243 2556 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2557 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2558 break;
c8ea5ea9 2559 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2560 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2561 /* if quad port adapter, disable WoL on all but port A */
2562 if (global_quad_port_a != 0)
63d4a8f9 2563 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2564 else
2565 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2566 /* Reset for multiple quad port adapters */
2567 if (++global_quad_port_a == 4)
2568 global_quad_port_a = 0;
2569 break;
63d4a8f9
MV		 2570 default:
2571 /* If the device can't wake, don't set software support */
2572 if (!device_can_wakeup(&adapter->pdev->dev))
2573 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2574 }
2575
2576 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2577 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2578 adapter->wol |= E1000_WUFC_MAG;
2579
2580 /* Some vendors want WoL disabled by default, but still supported */
2581 if ((hw->mac.type == e1000_i350) &&
2582 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2583 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2584 adapter->wol = 0;
2585 }
2586
5e350b92
TF		 2587 /* Some vendors want the ability to Use the EEPROM setting as
2588 * enable/disable only, and not for capability
2589 */
2590 if (((hw->mac.type == e1000_i350) ||
2591 (hw->mac.type == e1000_i354)) &&
2592 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2593 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2594 adapter->wol = 0;
2595 }
2596 if (hw->mac.type == e1000_i350) {
2597 if (((pdev->subsystem_device == 0x5001) ||
2598 (pdev->subsystem_device == 0x5002)) &&
2599 (hw->bus.func == 0)) {
2600 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2601 adapter->wol = 0;
2602 }
2603 if (pdev->subsystem_device == 0x1F52)
2604 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2605 }
2606
63d4a8f9
MV		 2607 device_set_wakeup_enable(&adapter->pdev->dev,
2608 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2609
2610 /* reset the hardware with the new settings */
2611 igb_reset(adapter);
2612
441fc6fd
CW		 2613 /* Init the I2C interface */
2614 err = igb_init_i2c(adapter);
2615 if (err) {
2616 dev_err(&pdev->dev, "failed to init i2c interface\n");
2617 goto err_eeprom;
2618 }
2619
9d5c8243 2620 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2621 * driver.
2622 */
9d5c8243
AK		 2623 igb_get_hw_control(adapter);
2624
9d5c8243
AK		 2625 strcpy(netdev->name, "eth%d");
2626 err = register_netdev(netdev);
2627 if (err)
2628 goto err_register;
2629
b168dfc5
JB		 2630 /* carrier off reporting is important to ethtool even BEFORE open */
2631 netif_carrier_off(netdev);
2632
421e02f0 2633#ifdef CONFIG_IGB_DCA
bbd98fe4 2634 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2635 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2636 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2637 igb_setup_dca(adapter);
2638 }
fe4506b6 2639
38c845c7 2640#endif
e428893b
CW		 2641#ifdef CONFIG_IGB_HWMON
2642 /* Initialize the thermal sensor on i350 devices. */
2643 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2644 u16 ets_word;
3c89f6d0 2645
b980ac18 2646 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2647 * external thermal sensor.
2648 */
2649 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2650 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2651 adapter->ets = true;
2652 else
2653 adapter->ets = false;
2654 if (igb_sysfs_init(adapter))
2655 dev_err(&pdev->dev,
2656 "failed to allocate sysfs resources\n");
2657 } else {
2658 adapter->ets = false;
2659 }
2660#endif
56cec249
CW		 2661 /* Check if Media Autosense is enabled */
2662 adapter->ei = *ei;
2663 if (hw->dev_spec._82575.mas_capable)
2664 igb_init_mas(adapter);
2665
673b8b70 2666 /* do hw tstamp init after resetting */
7ebae817 2667 igb_ptp_init(adapter);
673b8b70 2668
9d5c8243 2669 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2670 /* print bus type/speed/width info, not applicable to i354 */
2671 if (hw->mac.type != e1000_i354) {
2672 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2673 netdev->name,
2674 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2675 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2676 "unknown"),
2677 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2678 "Width x4" :
2679 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2680 "Width x2" :
2681 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2682 "Width x1" : "unknown"), netdev->dev_addr);
2683 }
9d5c8243 2684
53ea6c7e
TF		 2685 if ((hw->mac.type >= e1000_i210 ||
2686 igb_get_flash_presence_i210(hw))) {
2687 ret_val = igb_read_part_string(hw, part_str,
2688 E1000_PBANUM_LENGTH);
2689 } else {
2690 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2691 }
2692
9835fd73
CW		 2693 if (ret_val)
2694 strcpy(part_str, "Unknown");
2695 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2696 dev_info(&pdev->dev,
2697 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2698 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2699 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2700 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2701 if (hw->phy.media_type == e1000_media_type_copper) {
2702 switch (hw->mac.type) {
2703 case e1000_i350:
2704 case e1000_i210:
2705 case e1000_i211:
2706 /* Enable EEE for internal copper PHY devices */
c4c112f1 2707 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2708 if ((!err) &&
2709 (!hw->dev_spec._82575.eee_disable)) {
2710 adapter->eee_advert =
2711 MDIO_EEE_100TX | MDIO_EEE_1000T;
2712 adapter->flags |= IGB_FLAG_EEE;
2713 }
2714 break;
2715 case e1000_i354:
ceb5f13b 2716 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2717 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2718 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2719 if ((!err) &&
2720 (!hw->dev_spec._82575.eee_disable)) {
2721 adapter->eee_advert =
2722 MDIO_EEE_100TX | MDIO_EEE_1000T;
2723 adapter->flags |= IGB_FLAG_EEE;
2724 }
2725 }
2726 break;
2727 default:
2728 break;
ceb5f13b 2729 }
09b068d4 2730 }
749ab2cd 2731 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2732 return 0;
2733
2734err_register:
2735 igb_release_hw_control(adapter);
441fc6fd 2736 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2737err_eeprom:
2738 if (!igb_check_reset_block(hw))
f5f4cf08 2739 igb_reset_phy(hw);
9d5c8243
AK		 2740
2741 if (hw->flash_address)
2742 iounmap(hw->flash_address);
9d5c8243 2743err_sw_init:
42ad1a03 2744 kfree(adapter->shadow_vfta);
047e0030 2745 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2746#ifdef CONFIG_PCI_IOV
2747 igb_disable_sriov(pdev);
2748#endif
73bf8048 2749 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2750err_ioremap:
2751 free_netdev(netdev);
2752err_alloc_etherdev:
559e9c49 2753 pci_release_selected_regions(pdev,
b980ac18 2754 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2755err_pci_reg:
2756err_dma:
2757 pci_disable_device(pdev);
2758 return err;
2759}
2760
fa44f2f1 2761#ifdef CONFIG_PCI_IOV
781798a1 2762static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2763{
2764 struct net_device *netdev = pci_get_drvdata(pdev);
2765 struct igb_adapter *adapter = netdev_priv(netdev);
2766 struct e1000_hw *hw = &adapter->hw;
2767
2768 /* reclaim resources allocated to VFs */
2769 if (adapter->vf_data) {
2770 /* disable iov and allow time for transactions to clear */
b09186d2 2771 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2772 dev_warn(&pdev->dev,
2773 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2774 return -EPERM;
2775 } else {
2776 pci_disable_sriov(pdev);
2777 msleep(500);
2778 }
2779
2780 kfree(adapter->vf_data);
2781 adapter->vf_data = NULL;
2782 adapter->vfs_allocated_count = 0;
2783 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2784 wrfl();
2785 msleep(100);
2786 dev_info(&pdev->dev, "IOV Disabled\n");
2787
2788 /* Re-enable DMA Coalescing flag since IOV is turned off */
2789 adapter->flags |= IGB_FLAG_DMAC;
2790 }
2791
2792 return 0;
2793}
2794
2795static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2796{
2797 struct net_device *netdev = pci_get_drvdata(pdev);
2798 struct igb_adapter *adapter = netdev_priv(netdev);
2799 int old_vfs = pci_num_vf(pdev);
2800 int err = 0;
2801 int i;
2802
cd14ef54 2803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2804 err = -EPERM;
2805 goto out;
2806 }
fa44f2f1
GR		 2807 if (!num_vfs)
2808 goto out;
fa44f2f1 2809
781798a1
SA		 2810 if (old_vfs) {
2811 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2812 old_vfs, max_vfs);
2813 adapter->vfs_allocated_count = old_vfs;
2814 } else
2815 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2816
2817 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2818 sizeof(struct vf_data_storage), GFP_KERNEL);
2819
2820 /* if allocation failed then we do not support SR-IOV */
2821 if (!adapter->vf_data) {
2822 adapter->vfs_allocated_count = 0;
2823 dev_err(&pdev->dev,
2824 "Unable to allocate memory for VF Data Storage\n");
2825 err = -ENOMEM;
2826 goto out;
2827 }
2828
781798a1
SA		 2829 /* only call pci_enable_sriov() if no VFs are allocated already */
2830 if (!old_vfs) {
2831 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2832 if (err)
2833 goto err_out;
2834 }
fa44f2f1
GR		 2835 dev_info(&pdev->dev, "%d VFs allocated\n",
2836 adapter->vfs_allocated_count);
2837 for (i = 0; i < adapter->vfs_allocated_count; i++)
2838 igb_vf_configure(adapter, i);
2839
2840 /* DMA Coalescing is not supported in IOV mode. */
2841 adapter->flags &= ~IGB_FLAG_DMAC;
2842 goto out;
2843
2844err_out:
2845 kfree(adapter->vf_data);
2846 adapter->vf_data = NULL;
2847 adapter->vfs_allocated_count = 0;
2848out:
2849 return err;
2850}
2851
2852#endif
b980ac18 2853/**
441fc6fd
CW		 2854 * igb_remove_i2c - Cleanup I2C interface
2855 * @adapter: pointer to adapter structure
b980ac18 2856 **/
441fc6fd
CW		 2857static void igb_remove_i2c(struct igb_adapter *adapter)
2858{
441fc6fd
CW		 2859 /* free the adapter bus structure */
2860 i2c_del_adapter(&adapter->i2c_adap);
2861}
2862
9d5c8243 2863/**
b980ac18
JK		 2864 * igb_remove - Device Removal Routine
2865 * @pdev: PCI device information struct
9d5c8243 2866 *
b980ac18
JK		 2867 * igb_remove is called by the PCI subsystem to alert the driver
2868 * that it should release a PCI device. The could be caused by a
2869 * Hot-Plug event, or because the driver is going to be removed from
2870 * memory.
9d5c8243 2871 **/
9f9a12f8 2872static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2873{
2874 struct net_device *netdev = pci_get_drvdata(pdev);
2875 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2876 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2877
749ab2cd 2878 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2879#ifdef CONFIG_IGB_HWMON
2880 igb_sysfs_exit(adapter);
2881#endif
441fc6fd 2882 igb_remove_i2c(adapter);
a79f4f88 2883 igb_ptp_stop(adapter);
b980ac18 2884 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2885 * disable watchdog from being rescheduled.
2886 */
9d5c8243
AK		 2887 set_bit(__IGB_DOWN, &adapter->state);
2888 del_timer_sync(&adapter->watchdog_timer);
2889 del_timer_sync(&adapter->phy_info_timer);
2890
760141a5
TH		 2891 cancel_work_sync(&adapter->reset_task);
2892 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2893
421e02f0 2894#ifdef CONFIG_IGB_DCA
7dfc16fa 2895 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2896 dev_info(&pdev->dev, "DCA disabled\n");
2897 dca_remove_requester(&pdev->dev);
7dfc16fa 2898 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2899 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2900 }
2901#endif
2902
9d5c8243 2903 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2904 * would have already happened in close and is redundant.
2905 */
9d5c8243
AK		 2906 igb_release_hw_control(adapter);
2907
37680117 2908#ifdef CONFIG_PCI_IOV
fa44f2f1 2909 igb_disable_sriov(pdev);
37680117 2910#endif
559e9c49 2911
c23d92b8
AW		 2912 unregister_netdev(netdev);
2913
2914 igb_clear_interrupt_scheme(adapter);
2915
73bf8048 2916 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2917 if (hw->flash_address)
2918 iounmap(hw->flash_address);
559e9c49 2919 pci_release_selected_regions(pdev,
b980ac18 2920 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2921
1128c756 2922 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2923 free_netdev(netdev);
2924
19d5afd4 2925 pci_disable_pcie_error_reporting(pdev);
40a914fa 2926
9d5c8243
AK		 2927 pci_disable_device(pdev);
2928}
2929
a6b623e0 2930/**
b980ac18
JK		 2931 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2932 * @adapter: board private structure to initialize
a6b623e0 2933 *
b980ac18
JK		 2934 * This function initializes the vf specific data storage and then attempts to
2935 * allocate the VFs. The reason for ordering it this way is because it is much
2936 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2937 * the memory for the VFs.
a6b623e0 2938 **/
9f9a12f8 2939static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2940{
2941#ifdef CONFIG_PCI_IOV
2942 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2943 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2944
f96a8a0b
CW		 2945 /* Virtualization features not supported on i210 family. */
2946 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2947 return;
2948
be06998f
JB		 2949 /* Of the below we really only want the effect of getting
2950 * IGB_FLAG_HAS_MSIX set (if available), without which
2951 * igb_enable_sriov() has no effect.
2952 */
2953 igb_set_interrupt_capability(adapter, true);
2954 igb_reset_interrupt_capability(adapter);
2955
fa44f2f1 2956 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2957 igb_enable_sriov(pdev, max_vfs);
0224d663 2958
a6b623e0
AD		 2959#endif /* CONFIG_PCI_IOV */
2960}
2961
fa44f2f1 2962static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2963{
2964 struct e1000_hw *hw = &adapter->hw;
374a542d 2965 u32 max_rss_queues;
9d5c8243 2966
374a542d 2967 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2968 switch (hw->mac.type) {
374a542d
MV		 2969 case e1000_i211:
2970 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2971 break;
2972 case e1000_82575:
f96a8a0b 2973 case e1000_i210:
374a542d
MV		 2974 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2975 break;
2976 case e1000_i350:
2977 /* I350 cannot do RSS and SR-IOV at the same time */
2978 if (!!adapter->vfs_allocated_count) {
2979 max_rss_queues = 1;
2980 break;
2981 }
2982 /* fall through */
2983 case e1000_82576:
2984 if (!!adapter->vfs_allocated_count) {
2985 max_rss_queues = 2;
2986 break;
2987 }
2988 /* fall through */
2989 case e1000_82580:
ceb5f13b 2990 case e1000_i354:
374a542d
MV		 2991 default:
2992 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2993 break;
374a542d
MV		 2994 }
2995
2996 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2997
72ddef05
SS		 2998 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2999}
3000
3001void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3002 const u32 max_rss_queues)
3003{
3004 struct e1000_hw *hw = &adapter->hw;
3005
374a542d
MV		 3006 /* Determine if we need to pair queues. */
3007 switch (hw->mac.type) {
3008 case e1000_82575:
f96a8a0b 3009 case e1000_i211:
374a542d 3010 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 3011 break;
374a542d 3012 case e1000_82576:
374a542d
MV		 3013 case e1000_82580:
3014 case e1000_i350:
ceb5f13b 3015 case e1000_i354:
374a542d 3016 case e1000_i210:
f96a8a0b 3017 default:
b980ac18 3018 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 3019 * order to conserve interrupts due to limited supply.
3020 */
3021 if (adapter->rss_queues > (max_rss_queues / 2))
3022 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 3023 else
3024 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 3025 break;
3026 }
fa44f2f1
GR		 3027}
3028
3029/**
b980ac18
JK		 3030 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3031 * @adapter: board private structure to initialize
fa44f2f1 3032 *
b980ac18
JK		 3033 * igb_sw_init initializes the Adapter private data structure.
3034 * Fields are initialized based on PCI device information and
3035 * OS network device settings (MTU size).
fa44f2f1
GR		 3036 **/
3037static int igb_sw_init(struct igb_adapter *adapter)
3038{
3039 struct e1000_hw *hw = &adapter->hw;
3040 struct net_device *netdev = adapter->netdev;
3041 struct pci_dev *pdev = adapter->pdev;
3042
3043 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3044
3045 /* set default ring sizes */
3046 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3047 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3048
3049 /* set default ITR values */
3050 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3051 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3052
3053 /* set default work limits */
3054 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3055
3056 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3057 VLAN_HLEN;
3058 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3059
3060 spin_lock_init(&adapter->stats64_lock);
3061#ifdef CONFIG_PCI_IOV
3062 switch (hw->mac.type) {
3063 case e1000_82576:
3064 case e1000_i350:
3065 if (max_vfs > 7) {
3066 dev_warn(&pdev->dev,
3067 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 3068 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 3069 } else
3070 adapter->vfs_allocated_count = max_vfs;
3071 if (adapter->vfs_allocated_count)
3072 dev_warn(&pdev->dev,
3073 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3074 break;
3075 default:
3076 break;
3077 }
3078#endif /* CONFIG_PCI_IOV */
3079
cbfe360a
SA		 3080 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3081 adapter->flags |= IGB_FLAG_HAS_MSIX;
3082
ceee3450
TF		 3083 igb_probe_vfs(adapter);
3084
fa44f2f1 3085 igb_init_queue_configuration(adapter);
a99955fc 3086
1128c756 3087 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3088 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3089 GFP_ATOMIC);
1128c756 3090
a6b623e0 3091 /* This call may decrease the number of queues */
53c7d064 3092 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3093 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3094 return -ENOMEM;
3095 }
3096
3097 /* Explicitly disable IRQ since the NIC can be in any state. */
3098 igb_irq_disable(adapter);
3099
f96a8a0b 3100 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3101 adapter->flags &= ~IGB_FLAG_DMAC;
3102
9d5c8243
AK		 3103 set_bit(__IGB_DOWN, &adapter->state);
3104 return 0;
3105}
3106
3107/**
b980ac18
JK		 3108 * igb_open - Called when a network interface is made active
3109 * @netdev: network interface device structure
9d5c8243 3110 *
b980ac18 3111 * Returns 0 on success, negative value on failure
9d5c8243 3112 *
b980ac18
JK		 3113 * The open entry point is called when a network interface is made
3114 * active by the system (IFF_UP). At this point all resources needed
3115 * for transmit and receive operations are allocated, the interrupt
3116 * handler is registered with the OS, the watchdog timer is started,
3117 * and the stack is notified that the interface is ready.
9d5c8243 3118 **/
749ab2cd 3119static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3120{
3121 struct igb_adapter *adapter = netdev_priv(netdev);
3122 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3123 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3124 int err;
3125 int i;
3126
3127 /* disallow open during test */
749ab2cd
YZ		 3128 if (test_bit(__IGB_TESTING, &adapter->state)) {
3129 WARN_ON(resuming);
9d5c8243 3130 return -EBUSY;
749ab2cd
YZ		 3131 }
3132
3133 if (!resuming)
3134 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3135
b168dfc5
JB		 3136 netif_carrier_off(netdev);
3137
9d5c8243
AK		 3138 /* allocate transmit descriptors */
3139 err = igb_setup_all_tx_resources(adapter);
3140 if (err)
3141 goto err_setup_tx;
3142
3143 /* allocate receive descriptors */
3144 err = igb_setup_all_rx_resources(adapter);
3145 if (err)
3146 goto err_setup_rx;
3147
88a268c1 3148 igb_power_up_link(adapter);
9d5c8243 3149
9d5c8243
AK		 3150 /* before we allocate an interrupt, we must be ready to handle it.
3151 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3152 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3153 * clean_rx handler before we do so.
3154 */
9d5c8243
AK		 3155 igb_configure(adapter);
3156
3157 err = igb_request_irq(adapter);
3158 if (err)
3159 goto err_req_irq;
3160
0c2cc02e
AD		 3161 /* Notify the stack of the actual queue counts. */
3162 err = netif_set_real_num_tx_queues(adapter->netdev,
3163 adapter->num_tx_queues);
3164 if (err)
3165 goto err_set_queues;
3166
3167 err = netif_set_real_num_rx_queues(adapter->netdev,
3168 adapter->num_rx_queues);
3169 if (err)
3170 goto err_set_queues;
3171
9d5c8243
AK		 3172 /* From here on the code is the same as igb_up() */
3173 clear_bit(__IGB_DOWN, &adapter->state);
3174
0d1ae7f4
AD		 3175 for (i = 0; i < adapter->num_q_vectors; i++)
3176 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3177
3178 /* Clear any pending interrupts. */
3179 rd32(E1000_ICR);
844290e5
PW		 3180
3181 igb_irq_enable(adapter);
3182
d4960307
AD		 3183 /* notify VFs that reset has been completed */
3184 if (adapter->vfs_allocated_count) {
3185 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3186
d4960307
AD		 3187 reg_data |= E1000_CTRL_EXT_PFRSTD;
3188 wr32(E1000_CTRL_EXT, reg_data);
3189 }
3190
d55b53ff
JK		 3191 netif_tx_start_all_queues(netdev);
3192
749ab2cd
YZ		 3193 if (!resuming)
3194 pm_runtime_put(&pdev->dev);
3195
25568a53
AD		 3196 /* start the watchdog. */
3197 hw->mac.get_link_status = 1;
3198 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3199
3200 return 0;
3201
0c2cc02e
AD		 3202err_set_queues:
3203 igb_free_irq(adapter);
9d5c8243
AK		 3204err_req_irq:
3205 igb_release_hw_control(adapter);
88a268c1 3206 igb_power_down_link(adapter);
9d5c8243
AK		 3207 igb_free_all_rx_resources(adapter);
3208err_setup_rx:
3209 igb_free_all_tx_resources(adapter);
3210err_setup_tx:
3211 igb_reset(adapter);
749ab2cd
YZ		 3212 if (!resuming)
3213 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3214
3215 return err;
3216}
3217
46eafa59 3218int igb_open(struct net_device *netdev)
749ab2cd
YZ		 3219{
3220 return __igb_open(netdev, false);
3221}
3222
9d5c8243 3223/**
b980ac18
JK		 3224 * igb_close - Disables a network interface
3225 * @netdev: network interface device structure
9d5c8243 3226 *
b980ac18 3227 * Returns 0, this is not allowed to fail
9d5c8243 3228 *
b980ac18
JK		 3229 * The close entry point is called when an interface is de-activated
3230 * by the OS. The hardware is still under the driver's control, but
3231 * needs to be disabled. A global MAC reset is issued to stop the
3232 * hardware, and all transmit and receive resources are freed.
9d5c8243 3233 **/
749ab2cd 3234static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3235{
3236 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3237 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3238
3239 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3240
749ab2cd
YZ		 3241 if (!suspending)
3242 pm_runtime_get_sync(&pdev->dev);
3243
3244 igb_down(adapter);
9d5c8243
AK		 3245 igb_free_irq(adapter);
3246
3247 igb_free_all_tx_resources(adapter);
3248 igb_free_all_rx_resources(adapter);
3249
749ab2cd
YZ		 3250 if (!suspending)
3251 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3252 return 0;
3253}
3254
46eafa59 3255int igb_close(struct net_device *netdev)
749ab2cd
YZ		 3256{
3257 return __igb_close(netdev, false);
3258}
3259
9d5c8243 3260/**
b980ac18
JK		 3261 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3262 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3263 *
b980ac18 3264 * Return 0 on success, negative on failure
9d5c8243 3265 **/
80785298 3266int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3267{
59d71989 3268 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3269 int size;
3270
06034649 3271 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3272
3273 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3274 if (!tx_ring->tx_buffer_info)
9d5c8243 3275 goto err;
9d5c8243
AK		 3276
3277 /* round up to nearest 4K */
85e8d004 3278 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3279 tx_ring->size = ALIGN(tx_ring->size, 4096);
3280
5536d210
AD		 3281 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3282 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3283 if (!tx_ring->desc)
3284 goto err;
3285
9d5c8243
AK		 3286 tx_ring->next_to_use = 0;
3287 tx_ring->next_to_clean = 0;
81c2fc22 3288
9d5c8243
AK		 3289 return 0;
3290
3291err:
06034649 3292 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3293 tx_ring->tx_buffer_info = NULL;
3294 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3295 return -ENOMEM;
3296}
3297
3298/**
b980ac18
JK		 3299 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3300 * (Descriptors) for all queues
3301 * @adapter: board private structure
9d5c8243 3302 *
b980ac18 3303 * Return 0 on success, negative on failure
9d5c8243
AK		 3304 **/
3305static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3306{
439705e1 3307 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3308 int i, err = 0;
3309
3310 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3311 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3312 if (err) {
439705e1 3313 dev_err(&pdev->dev,
9d5c8243
AK		 3314 "Allocation for Tx Queue %u failed\n", i);
3315 for (i--; i >= 0; i--)
3025a446 3316 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3317 break;
3318 }
3319 }
3320
3321 return err;
3322}
3323
3324/**
b980ac18
JK		 3325 * igb_setup_tctl - configure the transmit control registers
3326 * @adapter: Board private structure
9d5c8243 3327 **/
d7ee5b3a 3328void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3329{
9d5c8243
AK		 3330 struct e1000_hw *hw = &adapter->hw;
3331 u32 tctl;
9d5c8243 3332
85b430b4
AD		 3333 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3334 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3335
3336 /* Program the Transmit Control Register */
9d5c8243
AK		 3337 tctl = rd32(E1000_TCTL);
3338 tctl &= ~E1000_TCTL_CT;
3339 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3340 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3341
3342 igb_config_collision_dist(hw);
3343
9d5c8243
AK		 3344 /* Enable transmits */
3345 tctl |= E1000_TCTL_EN;
3346
3347 wr32(E1000_TCTL, tctl);
3348}
3349
85b430b4 3350/**
b980ac18
JK		 3351 * igb_configure_tx_ring - Configure transmit ring after Reset
3352 * @adapter: board private structure
3353 * @ring: tx ring to configure
85b430b4 3354 *
b980ac18 3355 * Configure a transmit ring after a reset.
85b430b4 3356 **/
d7ee5b3a 3357void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3358 struct igb_ring *ring)
85b430b4
AD		 3359{
3360 struct e1000_hw *hw = &adapter->hw;
a74420e0 3361 u32 txdctl = 0;
85b430b4
AD		 3362 u64 tdba = ring->dma;
3363 int reg_idx = ring->reg_idx;
3364
3365 /* disable the queue */
a74420e0 3366 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3367 wrfl();
3368 mdelay(10);
3369
3370 wr32(E1000_TDLEN(reg_idx),
b980ac18 3371 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3372 wr32(E1000_TDBAL(reg_idx),
b980ac18 3373 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3374 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3375
fce99e34 3376 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3377 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3378 writel(0, ring->tail);
85b430b4
AD		 3379
3380 txdctl |= IGB_TX_PTHRESH;
3381 txdctl |= IGB_TX_HTHRESH << 8;
3382 txdctl |= IGB_TX_WTHRESH << 16;
3383
3384 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3385 wr32(E1000_TXDCTL(reg_idx), txdctl);
3386}
3387
3388/**
b980ac18
JK		 3389 * igb_configure_tx - Configure transmit Unit after Reset
3390 * @adapter: board private structure
85b430b4 3391 *
b980ac18 3392 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3393 **/
3394static void igb_configure_tx(struct igb_adapter *adapter)
3395{
3396 int i;
3397
3398 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3399 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3400}
3401
9d5c8243 3402/**
b980ac18
JK		 3403 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3404 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3405 *
b980ac18 3406 * Returns 0 on success, negative on failure
9d5c8243 3407 **/
80785298 3408int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3409{
59d71989 3410 struct device *dev = rx_ring->dev;
f33005a6 3411 int size;
9d5c8243 3412
06034649 3413 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3414
3415 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3416 if (!rx_ring->rx_buffer_info)
9d5c8243 3417 goto err;
9d5c8243 3418
9d5c8243 3419 /* Round up to nearest 4K */
f33005a6 3420 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3421 rx_ring->size = ALIGN(rx_ring->size, 4096);
3422
5536d210
AD		 3423 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3424 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3425 if (!rx_ring->desc)
3426 goto err;
3427
cbc8e55f 3428 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3429 rx_ring->next_to_clean = 0;
3430 rx_ring->next_to_use = 0;
9d5c8243 3431
9d5c8243
AK		 3432 return 0;
3433
3434err:
06034649
AD		 3435 vfree(rx_ring->rx_buffer_info);
3436 rx_ring->rx_buffer_info = NULL;
f33005a6 3437 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3438 return -ENOMEM;
3439}
3440
3441/**
b980ac18
JK		 3442 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3443 * (Descriptors) for all queues
3444 * @adapter: board private structure
9d5c8243 3445 *
b980ac18 3446 * Return 0 on success, negative on failure
9d5c8243
AK		 3447 **/
3448static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3449{
439705e1 3450 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3451 int i, err = 0;
3452
3453 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3454 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3455 if (err) {
439705e1 3456 dev_err(&pdev->dev,
9d5c8243
AK		 3457 "Allocation for Rx Queue %u failed\n", i);
3458 for (i--; i >= 0; i--)
3025a446 3459 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3460 break;
3461 }
3462 }
3463
3464 return err;
3465}
3466
06cf2666 3467/**
b980ac18
JK		 3468 * igb_setup_mrqc - configure the multiple receive queue control registers
3469 * @adapter: Board private structure
06cf2666
AD		 3470 **/
3471static void igb_setup_mrqc(struct igb_adapter *adapter)
3472{
3473 struct e1000_hw *hw = &adapter->hw;
3474 u32 mrqc, rxcsum;
ed12cc9a 3475 u32 j, num_rx_queues;
eb31f849 3476 u32 rss_key[10];
06cf2666 3477
eb31f849 3478 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3479 for (j = 0; j < 10; j++)
eb31f849 3480 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3481
a99955fc 3482 num_rx_queues = adapter->rss_queues;
06cf2666 3483
797fd4be 3484 switch (hw->mac.type) {
797fd4be
AD		 3485 case e1000_82576:
3486 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3487 if (adapter->vfs_allocated_count)
06cf2666 3488 num_rx_queues = 2;
797fd4be
AD		 3489 break;
3490 default:
3491 break;
06cf2666
AD		 3492 }
3493
ed12cc9a
LMV		 3494 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3495 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3496 adapter->rss_indir_tbl[j] =
3497 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3498 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3499 }
ed12cc9a 3500 igb_write_rss_indir_tbl(adapter);
06cf2666 3501
b980ac18 3502 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3503 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3504 * offloads as they are enabled by default
3505 */
3506 rxcsum = rd32(E1000_RXCSUM);
3507 rxcsum |= E1000_RXCSUM_PCSD;
3508
3509 if (adapter->hw.mac.type >= e1000_82576)
3510 /* Enable Receive Checksum Offload for SCTP */
3511 rxcsum |= E1000_RXCSUM_CRCOFL;
3512
3513 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3514 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3515
039454a8
AA		 3516 /* Generate RSS hash based on packet types, TCP/UDP
3517 * port numbers and/or IPv4/v6 src and dst addresses
3518 */
f96a8a0b
CW		 3519 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3520 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3521 E1000_MRQC_RSS_FIELD_IPV6 |
3522 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3523 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3524
039454a8
AA		 3525 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3526 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3527 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3528 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3529
06cf2666
AD		 3530 /* If VMDq is enabled then we set the appropriate mode for that, else
3531 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3532 * if we are only using one queue
3533 */
06cf2666
AD		 3534 if (adapter->vfs_allocated_count) {
3535 if (hw->mac.type > e1000_82575) {
3536 /* Set the default pool for the PF's first queue */
3537 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3538
06cf2666
AD		 3539 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3540 E1000_VT_CTL_DISABLE_DEF_POOL);
3541 vtctl |= adapter->vfs_allocated_count <<
3542 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3543 wr32(E1000_VT_CTL, vtctl);
3544 }
a99955fc 3545 if (adapter->rss_queues > 1)
c883de9f 3546 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
06cf2666 3547 else
f96a8a0b 3548 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3549 } else {
f96a8a0b 3550 if (hw->mac.type != e1000_i211)
c883de9f 3551 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
06cf2666
AD		 3552 }
3553 igb_vmm_control(adapter);
3554
06cf2666
AD		 3555 wr32(E1000_MRQC, mrqc);
3556}
3557
9d5c8243 3558/**
b980ac18
JK		 3559 * igb_setup_rctl - configure the receive control registers
3560 * @adapter: Board private structure
9d5c8243 3561 **/
d7ee5b3a 3562void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3563{
3564 struct e1000_hw *hw = &adapter->hw;
3565 u32 rctl;
9d5c8243
AK		 3566
3567 rctl = rd32(E1000_RCTL);
3568
3569 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3570 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3571
69d728ba 3572 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3573 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3574
b980ac18 3575 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3576 * redirection as it did with e1000. Newer features require
3577 * that the HW strips the CRC.
73cd78f1 3578 */
87cb7e8c 3579 rctl |= E1000_RCTL_SECRC;
9d5c8243 3580
559e9c49 3581 /* disable store bad packets and clear size bits. */
ec54d7d6 3582 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3583
45693bcb 3584 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3585 rctl |= E1000_RCTL_LPE;
9d5c8243 3586
952f72a8
AD		 3587 /* disable queue 0 to prevent tail write w/o re-config */
3588 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3589
e1739522
AD		 3590 /* Attention!!! For SR-IOV PF driver operations you must enable
3591 * queue drop for all VF and PF queues to prevent head of line blocking
3592 * if an un-trusted VF does not provide descriptors to hardware.
3593 */
3594 if (adapter->vfs_allocated_count) {
e1739522
AD		 3595 /* set all queue drop enable bits */
3596 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3597 }
3598
89eaefb6
BG		 3599 /* This is useful for sniffing bad packets. */
3600 if (adapter->netdev->features & NETIF_F_RXALL) {
3601 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3602 * in e1000e_set_rx_mode
3603 */
89eaefb6
BG		 3604 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3605 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3606 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3607
16903caa 3608 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3609 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3610 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3611 * and that breaks VLANs.
3612 */
3613 }
3614
9d5c8243
AK		 3615 wr32(E1000_RCTL, rctl);
3616}
3617
7d5753f0 3618static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3619 int vfn)
7d5753f0
AD		 3620{
3621 struct e1000_hw *hw = &adapter->hw;
3622 u32 vmolr;
3623
d3836f8e
AD		 3624 if (size > MAX_JUMBO_FRAME_SIZE)
3625 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3626
3627 vmolr = rd32(E1000_VMOLR(vfn));
3628 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3629 vmolr |= size | E1000_VMOLR_LPE;
3630 wr32(E1000_VMOLR(vfn), vmolr);
3631
3632 return 0;
3633}
3634
030f9f52
CV		 3635static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
3636 int vfn, bool enable)
e1739522 3637{
e1739522 3638 struct e1000_hw *hw = &adapter->hw;
030f9f52 3639 u32 val, reg;
e1739522 3640
030f9f52
CV		 3641 if (hw->mac.type < e1000_82576)
3642 return;
e1739522 3643
030f9f52
CV		 3644 if (hw->mac.type == e1000_i350)
3645 reg = E1000_DVMOLR(vfn);
3646 else
3647 reg = E1000_VMOLR(vfn);
3648
3649 val = rd32(reg);
3650 if (enable)
3651 val |= E1000_VMOLR_STRVLAN;
3652 else
3653 val &= ~(E1000_VMOLR_STRVLAN);
3654 wr32(reg, val);
e1739522
AD		 3655}
3656
8151d294
WM		 3657static inline void igb_set_vmolr(struct igb_adapter *adapter,
3658 int vfn, bool aupe)
7d5753f0
AD		 3659{
3660 struct e1000_hw *hw = &adapter->hw;
3661 u32 vmolr;
3662
b980ac18 3663 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3664 * we should exit and do nothing
3665 */
3666 if (hw->mac.type < e1000_82576)
3667 return;
3668
3669 vmolr = rd32(E1000_VMOLR(vfn));
8151d294 3670 if (aupe)
b980ac18 3671 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3672 else
3673 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3674
3675 /* clear all bits that might not be set */
3676 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3677
a99955fc 3678 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3679 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3680 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3681 * multicast packets
3682 */
3683 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3684 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3685
3686 wr32(E1000_VMOLR(vfn), vmolr);
3687}
3688
85b430b4 3689/**
b980ac18
JK		 3690 * igb_configure_rx_ring - Configure a receive ring after Reset
3691 * @adapter: board private structure
3692 * @ring: receive ring to be configured
85b430b4 3693 *
b980ac18 3694 * Configure the Rx unit of the MAC after a reset.
85b430b4 3695 **/
d7ee5b3a 3696void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3697 struct igb_ring *ring)
85b430b4
AD		 3698{
3699 struct e1000_hw *hw = &adapter->hw;
3700 u64 rdba = ring->dma;
3701 int reg_idx = ring->reg_idx;
a74420e0 3702 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3703
3704 /* disable the queue */
a74420e0 3705 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3706
3707 /* Set DMA base address registers */
3708 wr32(E1000_RDBAL(reg_idx),
3709 rdba & 0x00000000ffffffffULL);
3710 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3711 wr32(E1000_RDLEN(reg_idx),
b980ac18 3712 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3713
3714 /* initialize head and tail */
fce99e34 3715 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3716 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3717 writel(0, ring->tail);
85b430b4 3718
952f72a8 3719 /* set descriptor configuration */
44390ca6 3720 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3721 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3722 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3723 if (hw->mac.type >= e1000_82580)
757b77e2 3724 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3725 /* Only set Drop Enable if we are supporting multiple queues */
3726 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3727 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3728
3729 wr32(E1000_SRRCTL(reg_idx), srrctl);
3730
7d5753f0 3731 /* set filtering for VMDQ pools */
8151d294 3732 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3733
85b430b4
AD		 3734 rxdctl |= IGB_RX_PTHRESH;
3735 rxdctl |= IGB_RX_HTHRESH << 8;
3736 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3737
3738 /* enable receive descriptor fetching */
3739 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3740 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3741}
3742
9d5c8243 3743/**
b980ac18
JK		 3744 * igb_configure_rx - Configure receive Unit after Reset
3745 * @adapter: board private structure
9d5c8243 3746 *
b980ac18 3747 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3748 **/
3749static void igb_configure_rx(struct igb_adapter *adapter)
3750{
9107584e 3751 int i;
9d5c8243 3752
26ad9178
AD		 3753 /* set the correct pool for the PF default MAC address in entry 0 */
3754 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3755 adapter->vfs_allocated_count);
26ad9178 3756
06cf2666 3757 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3758 * the Base and Length of the Rx Descriptor Ring
3759 */
f9d40f6a
AD		 3760 for (i = 0; i < adapter->num_rx_queues; i++)
3761 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3762}
3763
3764/**
b980ac18
JK		 3765 * igb_free_tx_resources - Free Tx Resources per Queue
3766 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3767 *
b980ac18 3768 * Free all transmit software resources
9d5c8243 3769 **/
68fd9910 3770void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3771{
3b644cf6 3772 igb_clean_tx_ring(tx_ring);
9d5c8243 3773
06034649
AD		 3774 vfree(tx_ring->tx_buffer_info);
3775 tx_ring->tx_buffer_info = NULL;
9d5c8243 3776
439705e1
AD		 3777 /* if not set, then don't free */
3778 if (!tx_ring->desc)
3779 return;
3780
59d71989
AD		 3781 dma_free_coherent(tx_ring->dev, tx_ring->size,
3782 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3783
3784 tx_ring->desc = NULL;
3785}
3786
3787/**
b980ac18
JK		 3788 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3789 * @adapter: board private structure
9d5c8243 3790 *
b980ac18 3791 * Free all transmit software resources
9d5c8243
AK		 3792 **/
3793static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3794{
3795 int i;
3796
3797 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3798 if (adapter->tx_ring[i])
3799 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3800}
3801
ebe42d16
AD		 3802void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3803 struct igb_tx_buffer *tx_buffer)
3804{
3805 if (tx_buffer->skb) {
3806 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3807 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3808 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3809 dma_unmap_addr(tx_buffer, dma),
3810 dma_unmap_len(tx_buffer, len),
ebe42d16 3811 DMA_TO_DEVICE);
c9f14bf3 3812 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3813 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3814 dma_unmap_addr(tx_buffer, dma),
3815 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3816 DMA_TO_DEVICE);
3817 }
3818 tx_buffer->next_to_watch = NULL;
3819 tx_buffer->skb = NULL;
c9f14bf3 3820 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3821 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3822}
3823
3824/**
b980ac18
JK		 3825 * igb_clean_tx_ring - Free Tx Buffers
3826 * @tx_ring: ring to be cleaned
9d5c8243 3827 **/
3b644cf6 3828static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3829{
06034649 3830 struct igb_tx_buffer *buffer_info;
9d5c8243 3831 unsigned long size;
6ad4edfc 3832 u16 i;
9d5c8243 3833
06034649 3834 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3835 return;
3836 /* Free all the Tx ring sk_buffs */
3837
3838 for (i = 0; i < tx_ring->count; i++) {
06034649 3839 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3840 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3841 }
3842
dad8a3b3
JF		 3843 netdev_tx_reset_queue(txring_txq(tx_ring));
3844
06034649
AD		 3845 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3846 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3847
3848 /* Zero out the descriptor ring */
9d5c8243
AK		 3849 memset(tx_ring->desc, 0, tx_ring->size);
3850
3851 tx_ring->next_to_use = 0;
3852 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3853}
3854
3855/**
b980ac18
JK		 3856 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3857 * @adapter: board private structure
9d5c8243
AK		 3858 **/
3859static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3860{
3861 int i;
3862
3863 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3864 if (adapter->tx_ring[i])
3865 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3866}
3867
3868/**
b980ac18
JK		 3869 * igb_free_rx_resources - Free Rx Resources
3870 * @rx_ring: ring to clean the resources from
9d5c8243 3871 *
b980ac18 3872 * Free all receive software resources
9d5c8243 3873 **/
68fd9910 3874void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3875{
3b644cf6 3876 igb_clean_rx_ring(rx_ring);
9d5c8243 3877
06034649
AD		 3878 vfree(rx_ring->rx_buffer_info);
3879 rx_ring->rx_buffer_info = NULL;
9d5c8243 3880
439705e1
AD		 3881 /* if not set, then don't free */
3882 if (!rx_ring->desc)
3883 return;
3884
59d71989
AD		 3885 dma_free_coherent(rx_ring->dev, rx_ring->size,
3886 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3887
3888 rx_ring->desc = NULL;
3889}
3890
3891/**
b980ac18
JK		 3892 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3893 * @adapter: board private structure
9d5c8243 3894 *
b980ac18 3895 * Free all receive software resources
9d5c8243
AK		 3896 **/
3897static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3898{
3899 int i;
3900
3901 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3902 if (adapter->rx_ring[i])
3903 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3904}
3905
3906/**
b980ac18
JK		 3907 * igb_clean_rx_ring - Free Rx Buffers per Queue
3908 * @rx_ring: ring to free buffers from
9d5c8243 3909 **/
3b644cf6 3910static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3911{
9d5c8243 3912 unsigned long size;
c023cd88 3913 u16 i;
9d5c8243 3914
1a1c225b
AD		 3915 if (rx_ring->skb)
3916 dev_kfree_skb(rx_ring->skb);
3917 rx_ring->skb = NULL;
3918
06034649 3919 if (!rx_ring->rx_buffer_info)
9d5c8243 3920 return;
439705e1 3921
9d5c8243
AK		 3922 /* Free all the Rx ring sk_buffs */
3923 for (i = 0; i < rx_ring->count; i++) {
06034649 3924 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3925
cbc8e55f
AD		 3926 if (!buffer_info->page)
3927 continue;
3928
3929 dma_unmap_page(rx_ring->dev,
3930 buffer_info->dma,
3931 PAGE_SIZE,
3932 DMA_FROM_DEVICE);
3933 __free_page(buffer_info->page);
3934
1a1c225b 3935 buffer_info->page = NULL;
9d5c8243
AK		 3936 }
3937
06034649
AD		 3938 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3939 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3940
3941 /* Zero out the descriptor ring */
3942 memset(rx_ring->desc, 0, rx_ring->size);
3943
cbc8e55f 3944 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3945 rx_ring->next_to_clean = 0;
3946 rx_ring->next_to_use = 0;
9d5c8243
AK		 3947}
3948
3949/**
b980ac18
JK		 3950 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3951 * @adapter: board private structure
9d5c8243
AK		 3952 **/
3953static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3954{
3955 int i;
3956
3957 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3958 if (adapter->rx_ring[i])
3959 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3960}
3961
3962/**
b980ac18
JK		 3963 * igb_set_mac - Change the Ethernet Address of the NIC
3964 * @netdev: network interface device structure
3965 * @p: pointer to an address structure
9d5c8243 3966 *
b980ac18 3967 * Returns 0 on success, negative on failure
9d5c8243
AK		 3968 **/
3969static int igb_set_mac(struct net_device *netdev, void *p)
3970{
3971 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3972 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3973 struct sockaddr *addr = p;
3974
3975 if (!is_valid_ether_addr(addr->sa_data))
3976 return -EADDRNOTAVAIL;
3977
3978 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3979 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3980
26ad9178
AD		 3981 /* set the correct pool for the new PF MAC address in entry 0 */
3982 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3983 adapter->vfs_allocated_count);
e1739522 3984
9d5c8243
AK		 3985 return 0;
3986}
3987
3988/**
b980ac18
JK		 3989 * igb_write_mc_addr_list - write multicast addresses to MTA
3990 * @netdev: network interface device structure
9d5c8243 3991 *
b980ac18
JK		 3992 * Writes multicast address list to the MTA hash table.
3993 * Returns: -ENOMEM on failure
3994 * 0 on no addresses written
3995 * X on writing X addresses to MTA
9d5c8243 3996 **/
68d480c4 3997static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3998{
3999 struct igb_adapter *adapter = netdev_priv(netdev);
4000 struct e1000_hw *hw = &adapter->hw;
22bedad3 4001 struct netdev_hw_addr *ha;
68d480c4 4002 u8 *mta_list;
9d5c8243
AK		 4003 int i;
4004
4cd24eaf 4005 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 4006 /* nothing to program, so clear mc list */
4007 igb_update_mc_addr_list(hw, NULL, 0);
4008 igb_restore_vf_multicasts(adapter);
4009 return 0;
4010 }
9d5c8243 4011
4cd24eaf 4012 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 4013 if (!mta_list)
4014 return -ENOMEM;
ff41f8dc 4015
68d480c4 4016 /* The shared function expects a packed array of only addresses. */
48e2f183 4017 i = 0;
22bedad3
JP		 4018 netdev_for_each_mc_addr(ha, netdev)
4019 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 4020
68d480c4
AD		 4021 igb_update_mc_addr_list(hw, mta_list, i);
4022 kfree(mta_list);
4023
4cd24eaf 4024 return netdev_mc_count(netdev);
68d480c4
AD		 4025}
4026
4027/**
b980ac18
JK		 4028 * igb_write_uc_addr_list - write unicast addresses to RAR table
4029 * @netdev: network interface device structure
68d480c4 4030 *
b980ac18
JK		 4031 * Writes unicast address list to the RAR table.
4032 * Returns: -ENOMEM on failure/insufficient address space
4033 * 0 on no addresses written
4034 * X on writing X addresses to the RAR table
68d480c4
AD		 4035 **/
4036static int igb_write_uc_addr_list(struct net_device *netdev)
4037{
4038 struct igb_adapter *adapter = netdev_priv(netdev);
4039 struct e1000_hw *hw = &adapter->hw;
4040 unsigned int vfn = adapter->vfs_allocated_count;
4041 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
4042 int count = 0;
4043
4044 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 4045 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 4046 return -ENOMEM;
9d5c8243 4047
32e7bfc4 4048 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 4049 struct netdev_hw_addr *ha;
32e7bfc4
JP		 4050
4051 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 4052 if (!rar_entries)
4053 break;
26ad9178 4054 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 4055 rar_entries--,
4056 vfn);
68d480c4 4057 count++;
ff41f8dc
AD		 4058 }
4059 }
4060 /* write the addresses in reverse order to avoid write combining */
4061 for (; rar_entries > 0 ; rar_entries--) {
4062 wr32(E1000_RAH(rar_entries), 0);
4063 wr32(E1000_RAL(rar_entries), 0);
4064 }
4065 wrfl();
4066
68d480c4
AD		 4067 return count;
4068}
4069
16903caa
AD		 4070static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4071{
4072 struct e1000_hw *hw = &adapter->hw;
4073 u32 i, pf_id;
4074
4075 switch (hw->mac.type) {
4076 case e1000_i210:
4077 case e1000_i211:
4078 case e1000_i350:
4079 /* VLAN filtering needed for VLAN prio filter */
4080 if (adapter->netdev->features & NETIF_F_NTUPLE)
4081 break;
4082 /* fall through */
4083 case e1000_82576:
4084 case e1000_82580:
4085 case e1000_i354:
4086 /* VLAN filtering needed for pool filtering */
4087 if (adapter->vfs_allocated_count)
4088 break;
4089 /* fall through */
4090 default:
4091 return 1;
4092 }
4093
4094 /* We are already in VLAN promisc, nothing to do */
4095 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4096 return 0;
4097
4098 if (!adapter->vfs_allocated_count)
4099 goto set_vfta;
4100
4101 /* Add PF to all active pools */
4102 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4103
4104 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4105 u32 vlvf = rd32(E1000_VLVF(i));
4106
a51d8c21 4107 vlvf |= BIT(pf_id);
16903caa
AD		 4108 wr32(E1000_VLVF(i), vlvf);
4109 }
4110
4111set_vfta:
4112 /* Set all bits in the VLAN filter table array */
4113 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4114 hw->mac.ops.write_vfta(hw, i, ~0U);
4115
4116 /* Set flag so we don't redo unnecessary work */
4117 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4118
4119 return 0;
4120}
4121
4122#define VFTA_BLOCK_SIZE 8
4123static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4124{
4125 struct e1000_hw *hw = &adapter->hw;
4126 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4127 u32 vid_start = vfta_offset * 32;
4128 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4129 u32 i, vid, word, bits, pf_id;
4130
4131 /* guarantee that we don't scrub out management VLAN */
4132 vid = adapter->mng_vlan_id;
4133 if (vid >= vid_start && vid < vid_end)
a51d8c21 4134 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16903caa
AD		 4135
4136 if (!adapter->vfs_allocated_count)
4137 goto set_vfta;
4138
4139 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4140
4141 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4142 u32 vlvf = rd32(E1000_VLVF(i));
4143
4144 /* pull VLAN ID from VLVF */
4145 vid = vlvf & VLAN_VID_MASK;
4146
4147 /* only concern ourselves with a certain range */
4148 if (vid < vid_start || vid >= vid_end)
4149 continue;
4150
4151 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4152 /* record VLAN ID in VFTA */
a51d8c21 4153 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16903caa
AD		 4154
4155 /* if PF is part of this then continue */
4156 if (test_bit(vid, adapter->active_vlans))
4157 continue;
4158 }
4159
4160 /* remove PF from the pool */
a51d8c21 4161 bits = ~BIT(pf_id);
16903caa
AD		 4162 bits &= rd32(E1000_VLVF(i));
4163 wr32(E1000_VLVF(i), bits);
4164 }
4165
4166set_vfta:
4167 /* extract values from active_vlans and write back to VFTA */
4168 for (i = VFTA_BLOCK_SIZE; i--;) {
4169 vid = (vfta_offset + i) * 32;
4170 word = vid / BITS_PER_LONG;
4171 bits = vid % BITS_PER_LONG;
4172
4173 vfta[i] |= adapter->active_vlans[word] >> bits;
4174
4175 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4176 }
4177}
4178
4179static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4180{
4181 u32 i;
4182
4183 /* We are not in VLAN promisc, nothing to do */
4184 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4185 return;
4186
4187 /* Set flag so we don't redo unnecessary work */
4188 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4189
4190 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4191 igb_scrub_vfta(adapter, i);
4192}
4193
68d480c4 4194/**
b980ac18
JK		 4195 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4196 * @netdev: network interface device structure
68d480c4 4197 *
b980ac18
JK		 4198 * The set_rx_mode entry point is called whenever the unicast or multicast
4199 * address lists or the network interface flags are updated. This routine is
4200 * responsible for configuring the hardware for proper unicast, multicast,
4201 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4202 **/
4203static void igb_set_rx_mode(struct net_device *netdev)
4204{
4205 struct igb_adapter *adapter = netdev_priv(netdev);
4206 struct e1000_hw *hw = &adapter->hw;
4207 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4208 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4209 int count;
4210
4211 /* Check for Promiscuous and All Multicast modes */
68d480c4 4212 if (netdev->flags & IFF_PROMISC) {
16903caa 4213 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
bf456abb
AD		 4214 vmolr |= E1000_VMOLR_MPME;
4215
4216 /* enable use of UTA filter to force packets to default pool */
4217 if (hw->mac.type == e1000_82576)
4218 vmolr |= E1000_VMOLR_ROPE;
68d480c4
AD		 4219 } else {
4220 if (netdev->flags & IFF_ALLMULTI) {
4221 rctl |= E1000_RCTL_MPE;
4222 vmolr |= E1000_VMOLR_MPME;
4223 } else {
b980ac18 4224 /* Write addresses to the MTA, if the attempt fails
25985edc 4225 * then we should just turn on promiscuous mode so
68d480c4
AD		 4226 * that we can at least receive multicast traffic
4227 */
4228 count = igb_write_mc_addr_list(netdev);
4229 if (count < 0) {
4230 rctl |= E1000_RCTL_MPE;
4231 vmolr |= E1000_VMOLR_MPME;
4232 } else if (count) {
4233 vmolr |= E1000_VMOLR_ROMPE;
4234 }
4235 }
28fc06f5 4236 }
268f9d33
AD		 4237
4238 /* Write addresses to available RAR registers, if there is not
4239 * sufficient space to store all the addresses then enable
4240 * unicast promiscuous mode
4241 */
4242 count = igb_write_uc_addr_list(netdev);
4243 if (count < 0) {
4244 rctl |= E1000_RCTL_UPE;
4245 vmolr |= E1000_VMOLR_ROPE;
28fc06f5 4246 }
16903caa
AD		 4247
4248 /* enable VLAN filtering by default */
4249 rctl |= E1000_RCTL_VFE;
4250
4251 /* disable VLAN filtering for modes that require it */
4252 if ((netdev->flags & IFF_PROMISC) ||
4253 (netdev->features & NETIF_F_RXALL)) {
4254 /* if we fail to set all rules then just clear VFE */
4255 if (igb_vlan_promisc_enable(adapter))
4256 rctl &= ~E1000_RCTL_VFE;
4257 } else {
4258 igb_vlan_promisc_disable(adapter);
4259 }
4260
4261 /* update state of unicast, multicast, and VLAN filtering modes */
4262 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4263 E1000_RCTL_VFE);
68d480c4 4264 wr32(E1000_RCTL, rctl);
28fc06f5 4265
b980ac18 4266 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4267 * the VMOLR to enable the appropriate modes. Without this workaround
4268 * we will have issues with VLAN tag stripping not being done for frames
4269 * that are only arriving because we are the default pool
4270 */
f96a8a0b 4271 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4272 return;
9d5c8243 4273
bf456abb
AD		 4274 /* set UTA to appropriate mode */
4275 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4276
68d480c4 4277 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4278 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4279
4280 /* enable Rx jumbo frames, no need for restriction */
4281 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4282 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4283
68d480c4 4284 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4285 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4286
28fc06f5 4287 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4288}
4289
13800469
GR		 4290static void igb_check_wvbr(struct igb_adapter *adapter)
4291{
4292 struct e1000_hw *hw = &adapter->hw;
4293 u32 wvbr = 0;
4294
4295 switch (hw->mac.type) {
4296 case e1000_82576:
4297 case e1000_i350:
81ad807b
CW		 4298 wvbr = rd32(E1000_WVBR);
4299 if (!wvbr)
13800469
GR		 4300 return;
4301 break;
4302 default:
4303 break;
4304 }
4305
4306 adapter->wvbr |= wvbr;
4307}
4308
4309#define IGB_STAGGERED_QUEUE_OFFSET 8
4310
4311static void igb_spoof_check(struct igb_adapter *adapter)
4312{
4313 int j;
4314
4315 if (!adapter->wvbr)
4316 return;
4317
9005df38 4318 for (j = 0; j < adapter->vfs_allocated_count; j++) {
a51d8c21
JK		 4319 if (adapter->wvbr & BIT(j) ||
4320 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
13800469
GR		 4321 dev_warn(&adapter->pdev->dev,
4322 "Spoof event(s) detected on VF %d\n", j);
4323 adapter->wvbr &=
a51d8c21
JK		 4324 ~(BIT(j) |
4325 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
13800469
GR		 4326 }
4327 }
4328}
4329
9d5c8243 4330/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4331 * the phy
4332 */
9d5c8243
AK		 4333static void igb_update_phy_info(unsigned long data)
4334{
4335 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4336 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4337}
4338
4d6b725e 4339/**
b980ac18
JK		 4340 * igb_has_link - check shared code for link and determine up/down
4341 * @adapter: pointer to driver private info
4d6b725e 4342 **/
3145535a 4343bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4344{
4345 struct e1000_hw *hw = &adapter->hw;
4346 bool link_active = false;
4d6b725e
AD		 4347
4348 /* get_link_status is set on LSC (link status) interrupt or
4349 * rx sequence error interrupt. get_link_status will stay
4350 * false until the e1000_check_for_link establishes link
4351 * for copper adapters ONLY
4352 */
4353 switch (hw->phy.media_type) {
4354 case e1000_media_type_copper:
e5c3370f
AA		 4355 if (!hw->mac.get_link_status)
4356 return true;
4d6b725e 4357 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4358 hw->mac.ops.check_for_link(hw);
4359 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4360 break;
4361 default:
4362 case e1000_media_type_unknown:
4363 break;
4364 }
4365
aa9b8cc4
AA		 4366 if (((hw->mac.type == e1000_i210) ||
4367 (hw->mac.type == e1000_i211)) &&
4368 (hw->phy.id == I210_I_PHY_ID)) {
4369 if (!netif_carrier_ok(adapter->netdev)) {
4370 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4371 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4372 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4373 adapter->link_check_timeout = jiffies;
4374 }
4375 }
4376
4d6b725e
AD		 4377 return link_active;
4378}
4379
563988dc
SA		 4380static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4381{
4382 bool ret = false;
4383 u32 ctrl_ext, thstat;
4384
f96a8a0b 4385 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4386 if (hw->mac.type == e1000_i350) {
4387 thstat = rd32(E1000_THSTAT);
4388 ctrl_ext = rd32(E1000_CTRL_EXT);
4389
4390 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4391 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4392 ret = !!(thstat & event);
563988dc
SA		 4393 }
4394
4395 return ret;
4396}
4397
1516f0a6
CW		 4398/**
4399 * igb_check_lvmmc - check for malformed packets received
4400 * and indicated in LVMMC register
4401 * @adapter: pointer to adapter
4402 **/
4403static void igb_check_lvmmc(struct igb_adapter *adapter)
4404{
4405 struct e1000_hw *hw = &adapter->hw;
4406 u32 lvmmc;
4407
4408 lvmmc = rd32(E1000_LVMMC);
4409 if (lvmmc) {
4410 if (unlikely(net_ratelimit())) {
4411 netdev_warn(adapter->netdev,
4412 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4413 lvmmc);
4414 }
4415 }
4416}
4417
9d5c8243 4418/**
b980ac18
JK		 4419 * igb_watchdog - Timer Call-back
4420 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4421 **/
4422static void igb_watchdog(unsigned long data)
4423{
4424 struct igb_adapter *adapter = (struct igb_adapter *)data;
4425 /* Do the rest outside of interrupt context */
4426 schedule_work(&adapter->watchdog_task);
4427}
4428
4429static void igb_watchdog_task(struct work_struct *work)
4430{
4431 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4432 struct igb_adapter,
4433 watchdog_task);
9d5c8243 4434 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4435 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4436 struct net_device *netdev = adapter->netdev;
563988dc 4437 u32 link;
7a6ea550 4438 int i;
56cec249 4439 u32 connsw;
b72f3f72 4440 u16 phy_data, retry_count = 20;
9d5c8243 4441
4d6b725e 4442 link = igb_has_link(adapter);
aa9b8cc4
AA		 4443
4444 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4445 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4446 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4447 else
4448 link = false;
4449 }
4450
56cec249
CW		 4451 /* Force link down if we have fiber to swap to */
4452 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4453 if (hw->phy.media_type == e1000_media_type_copper) {
4454 connsw = rd32(E1000_CONNSW);
4455 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4456 link = 0;
4457 }
4458 }
9d5c8243 4459 if (link) {
2bdfc4e2
CW		 4460 /* Perform a reset if the media type changed. */
4461 if (hw->dev_spec._82575.media_changed) {
4462 hw->dev_spec._82575.media_changed = false;
4463 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4464 igb_reset(adapter);
4465 }
749ab2cd
YZ		 4466 /* Cancel scheduled suspend requests. */
4467 pm_runtime_resume(netdev->dev.parent);
4468
9d5c8243
AK		 4469 if (!netif_carrier_ok(netdev)) {
4470 u32 ctrl;
9005df38 4471
330a6d6a 4472 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4473 &adapter->link_speed,
4474 &adapter->link_duplex);
9d5c8243
AK		 4475
4476 ctrl = rd32(E1000_CTRL);
527d47c1 4477 /* Links status message must follow this format */
c75c4edf
CW		 4478 netdev_info(netdev,
4479 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4480 netdev->name,
4481 adapter->link_speed,
4482 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4483 "Full" : "Half",
4484 (ctrl & E1000_CTRL_TFCE) &&
4485 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4486 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4487 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4488
f4c01e96
CW		 4489 /* disable EEE if enabled */
4490 if ((adapter->flags & IGB_FLAG_EEE) &&
4491 (adapter->link_duplex == HALF_DUPLEX)) {
4492 dev_info(&adapter->pdev->dev,
4493 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4494 adapter->hw.dev_spec._82575.eee_disable = true;
4495 adapter->flags &= ~IGB_FLAG_EEE;
4496 }
4497
c0ba4778
KS		 4498 /* check if SmartSpeed worked */
4499 igb_check_downshift(hw);
4500 if (phy->speed_downgraded)
4501 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4502
563988dc 4503 /* check for thermal sensor event */
876d2d6f 4504 if (igb_thermal_sensor_event(hw,
d34a15ab 4505 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4506 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4507
d07f3e37 4508 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4509 adapter->tx_timeout_factor = 1;
4510 switch (adapter->link_speed) {
4511 case SPEED_10:
9d5c8243
AK		 4512 adapter->tx_timeout_factor = 14;
4513 break;
4514 case SPEED_100:
9d5c8243
AK		 4515 /* maybe add some timeout factor ? */
4516 break;
4517 }
4518
b72f3f72
TU		 4519 if (adapter->link_speed != SPEED_1000)
4520 goto no_wait;
4521
4522 /* wait for Remote receiver status OK */
4523retry_read_status:
4524 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4525 &phy_data)) {
4526 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4527 retry_count) {
4528 msleep(100);
4529 retry_count--;
4530 goto retry_read_status;
4531 } else if (!retry_count) {
4532 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4533 }
4534 } else {
4535 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4536 }
4537no_wait:
9d5c8243 4538 netif_carrier_on(netdev);
9d5c8243 4539
4ae196df 4540 igb_ping_all_vfs(adapter);
17dc566c 4541 igb_check_vf_rate_limit(adapter);
4ae196df 4542
4b1a9877 4543 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4544 if (!test_bit(__IGB_DOWN, &adapter->state))
4545 mod_timer(&adapter->phy_info_timer,
4546 round_jiffies(jiffies + 2 * HZ));
4547 }
4548 } else {
4549 if (netif_carrier_ok(netdev)) {
4550 adapter->link_speed = 0;
4551 adapter->link_duplex = 0;
563988dc
SA		 4552
4553 /* check for thermal sensor event */
876d2d6f
JK		 4554 if (igb_thermal_sensor_event(hw,
4555 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4556 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4557 }
563988dc 4558
527d47c1 4559 /* Links status message must follow this format */
c75c4edf 4560 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4561 netdev->name);
9d5c8243 4562 netif_carrier_off(netdev);
4b1a9877 4563
4ae196df
AD		 4564 igb_ping_all_vfs(adapter);
4565
4b1a9877 4566 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4567 if (!test_bit(__IGB_DOWN, &adapter->state))
4568 mod_timer(&adapter->phy_info_timer,
4569 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4570
56cec249
CW		 4571 /* link is down, time to check for alternate media */
4572 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4573 igb_check_swap_media(adapter);
4574 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4575 schedule_work(&adapter->reset_task);
4576 /* return immediately */
4577 return;
4578 }
4579 }
749ab2cd
YZ		 4580 pm_schedule_suspend(netdev->dev.parent,
4581 MSEC_PER_SEC * 5);
56cec249
CW		 4582
4583 /* also check for alternate media here */
4584 } else if (!netif_carrier_ok(netdev) &&
4585 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4586 igb_check_swap_media(adapter);
4587 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4588 schedule_work(&adapter->reset_task);
4589 /* return immediately */
4590 return;
4591 }
9d5c8243
AK		 4592 }
4593 }
4594
12dcd86b
ED		 4595 spin_lock(&adapter->stats64_lock);
4596 igb_update_stats(adapter, &adapter->stats64);
4597 spin_unlock(&adapter->stats64_lock);
9d5c8243 4598
dbabb065 4599 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4600 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4601 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4602 /* We've lost link, so the controller stops DMA,
4603 * but we've got queued Tx work that's never going
4604 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4605 * (Do the reset outside of interrupt context).
4606 */
dbabb065
AD		 4607 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4608 adapter->tx_timeout_count++;
4609 schedule_work(&adapter->reset_task);
4610 /* return immediately since reset is imminent */
4611 return;
4612 }
9d5c8243 4613 }
9d5c8243 4614
dbabb065 4615 /* Force detection of hung controller every watchdog period */
6d095fa8 4616 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4617 }
f7ba205e 4618
b980ac18 4619 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4620 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4621 u32 eics = 0;
9005df38 4622
0d1ae7f4
AD		 4623 for (i = 0; i < adapter->num_q_vectors; i++)
4624 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4625 wr32(E1000_EICS, eics);
4626 } else {
4627 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4628 }
9d5c8243 4629
13800469 4630 igb_spoof_check(adapter);
fc580751 4631 igb_ptp_rx_hang(adapter);
13800469 4632
1516f0a6
CW		 4633 /* Check LVMMC register on i350/i354 only */
4634 if ((adapter->hw.mac.type == e1000_i350) ||
4635 (adapter->hw.mac.type == e1000_i354))
4636 igb_check_lvmmc(adapter);
4637
9d5c8243 4638 /* Reset the timer */
aa9b8cc4
AA		 4639 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4640 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4641 mod_timer(&adapter->watchdog_timer,
4642 round_jiffies(jiffies + HZ));
4643 else
4644 mod_timer(&adapter->watchdog_timer,
4645 round_jiffies(jiffies + 2 * HZ));
4646 }
9d5c8243
AK		 4647}
4648
4649enum latency_range {
4650 lowest_latency = 0,
4651 low_latency = 1,
4652 bulk_latency = 2,
4653 latency_invalid = 255
4654};
4655
6eb5a7f1 4656/**
b980ac18
JK		 4657 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4658 * @q_vector: pointer to q_vector
6eb5a7f1 4659 *
b980ac18
JK		 4660 * Stores a new ITR value based on strictly on packet size. This
4661 * algorithm is less sophisticated than that used in igb_update_itr,
4662 * due to the difficulty of synchronizing statistics across multiple
4663 * receive rings. The divisors and thresholds used by this function
4664 * were determined based on theoretical maximum wire speed and testing
4665 * data, in order to minimize response time while increasing bulk
4666 * throughput.
406d4965 4667 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4668 * NOTE: This function is called only when operating in a multiqueue
4669 * receive environment.
6eb5a7f1 4670 **/
047e0030 4671static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4672{
047e0030 4673 int new_val = q_vector->itr_val;
6eb5a7f1 4674 int avg_wire_size = 0;
047e0030 4675 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4676 unsigned int packets;
9d5c8243 4677
6eb5a7f1
AD		 4678 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4679 * ints/sec - ITR timer value of 120 ticks.
4680 */
4681 if (adapter->link_speed != SPEED_1000) {
0ba82994 4682 new_val = IGB_4K_ITR;
6eb5a7f1 4683 goto set_itr_val;
9d5c8243 4684 }
047e0030 4685
0ba82994
AD		 4686 packets = q_vector->rx.total_packets;
4687 if (packets)
4688 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4689
0ba82994
AD		 4690 packets = q_vector->tx.total_packets;
4691 if (packets)
4692 avg_wire_size = max_t(u32, avg_wire_size,
4693 q_vector->tx.total_bytes / packets);
047e0030
AD		 4694
4695 /* if avg_wire_size isn't set no work was done */
4696 if (!avg_wire_size)
4697 goto clear_counts;
9d5c8243 4698
6eb5a7f1
AD		 4699 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4700 avg_wire_size += 24;
4701
4702 /* Don't starve jumbo frames */
4703 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4704
6eb5a7f1
AD		 4705 /* Give a little boost to mid-size frames */
4706 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4707 new_val = avg_wire_size / 3;
4708 else
4709 new_val = avg_wire_size / 2;
9d5c8243 4710
0ba82994
AD		 4711 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4712 if (new_val < IGB_20K_ITR &&
4713 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4714 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4715 new_val = IGB_20K_ITR;
abe1c363 4716
6eb5a7f1 4717set_itr_val:
047e0030
AD		 4718 if (new_val != q_vector->itr_val) {
4719 q_vector->itr_val = new_val;
4720 q_vector->set_itr = 1;
9d5c8243 4721 }
6eb5a7f1 4722clear_counts:
0ba82994
AD		 4723 q_vector->rx.total_bytes = 0;
4724 q_vector->rx.total_packets = 0;
4725 q_vector->tx.total_bytes = 0;
4726 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4727}
4728
4729/**
b980ac18
JK		 4730 * igb_update_itr - update the dynamic ITR value based on statistics
4731 * @q_vector: pointer to q_vector
4732 * @ring_container: ring info to update the itr for
4733 *
4734 * Stores a new ITR value based on packets and byte
4735 * counts during the last interrupt. The advantage of per interrupt
4736 * computation is faster updates and more accurate ITR for the current
4737 * traffic pattern. Constants in this function were computed
4738 * based on theoretical maximum wire speed and thresholds were set based
4739 * on testing data as well as attempting to minimize response time
4740 * while increasing bulk throughput.
406d4965 4741 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4742 * NOTE: These calculations are only valid when operating in a single-
4743 * queue environment.
9d5c8243 4744 **/
0ba82994
AD		 4745static void igb_update_itr(struct igb_q_vector *q_vector,
4746 struct igb_ring_container *ring_container)
9d5c8243 4747{
0ba82994
AD		 4748 unsigned int packets = ring_container->total_packets;
4749 unsigned int bytes = ring_container->total_bytes;
4750 u8 itrval = ring_container->itr;
9d5c8243 4751
0ba82994 4752 /* no packets, exit with status unchanged */
9d5c8243 4753 if (packets == 0)
0ba82994 4754 return;
9d5c8243 4755
0ba82994 4756 switch (itrval) {
9d5c8243
AK		 4757 case lowest_latency:
4758 /* handle TSO and jumbo frames */
4759 if (bytes/packets > 8000)
0ba82994 4760 itrval = bulk_latency;
9d5c8243 4761 else if ((packets < 5) && (bytes > 512))
0ba82994 4762 itrval = low_latency;
9d5c8243
AK		 4763 break;
4764 case low_latency: /* 50 usec aka 20000 ints/s */
4765 if (bytes > 10000) {
4766 /* this if handles the TSO accounting */
d34a15ab 4767 if (bytes/packets > 8000)
0ba82994 4768 itrval = bulk_latency;
d34a15ab 4769 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4770 itrval = bulk_latency;
d34a15ab 4771 else if ((packets > 35))
0ba82994 4772 itrval = lowest_latency;
9d5c8243 4773 } else if (bytes/packets > 2000) {
0ba82994 4774 itrval = bulk_latency;
9d5c8243 4775 } else if (packets <= 2 && bytes < 512) {
0ba82994 4776 itrval = lowest_latency;
9d5c8243
AK		 4777 }
4778 break;
4779 case bulk_latency: /* 250 usec aka 4000 ints/s */
4780 if (bytes > 25000) {
4781 if (packets > 35)
0ba82994 4782 itrval = low_latency;
1e5c3d21 4783 } else if (bytes < 1500) {
0ba82994 4784 itrval = low_latency;
9d5c8243
AK		 4785 }
4786 break;
4787 }
4788
0ba82994
AD		 4789 /* clear work counters since we have the values we need */
4790 ring_container->total_bytes = 0;
4791 ring_container->total_packets = 0;
4792
4793 /* write updated itr to ring container */
4794 ring_container->itr = itrval;
9d5c8243
AK		 4795}
4796
0ba82994 4797static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4798{
0ba82994 4799 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4800 u32 new_itr = q_vector->itr_val;
0ba82994 4801 u8 current_itr = 0;
9d5c8243
AK		 4802
4803 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4804 if (adapter->link_speed != SPEED_1000) {
4805 current_itr = 0;
0ba82994 4806 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4807 goto set_itr_now;
4808 }
4809
0ba82994
AD		 4810 igb_update_itr(q_vector, &q_vector->tx);
4811 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4812
0ba82994 4813 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4814
6eb5a7f1 4815 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4816 if (current_itr == lowest_latency &&
4817 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4818 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4819 current_itr = low_latency;
4820
9d5c8243
AK		 4821 switch (current_itr) {
4822 /* counts and packets in update_itr are dependent on these numbers */
4823 case lowest_latency:
0ba82994 4824 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4825 break;
4826 case low_latency:
0ba82994 4827 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4828 break;
4829 case bulk_latency:
0ba82994 4830 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4831 break;
4832 default:
4833 break;
4834 }
4835
4836set_itr_now:
047e0030 4837 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4838 /* this attempts to bias the interrupt rate towards Bulk
4839 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4840 * increasing
4841 */
047e0030 4842 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4843 max((new_itr * q_vector->itr_val) /
4844 (new_itr + (q_vector->itr_val >> 2)),
4845 new_itr) : new_itr;
9d5c8243
AK		 4846 /* Don't write the value here; it resets the adapter's
4847 * internal timer, and causes us to delay far longer than
4848 * we should between interrupts. Instead, we write the ITR
4849 * value at the beginning of the next interrupt so the timing
4850 * ends up being correct.
4851 */
047e0030
AD		 4852 q_vector->itr_val = new_itr;
4853 q_vector->set_itr = 1;
9d5c8243 4854 }
9d5c8243
AK		 4855}
4856
c50b52a0
SH		 4857static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4858 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4859{
4860 struct e1000_adv_tx_context_desc *context_desc;
4861 u16 i = tx_ring->next_to_use;
4862
4863 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4864
4865 i++;
4866 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4867
4868 /* set bits to identify this as an advanced context descriptor */
4869 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4870
4871 /* For 82575, context index must be unique per ring. */
866cff06 4872 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4873 mss_l4len_idx |= tx_ring->reg_idx << 4;
4874
4875 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4876 context_desc->seqnum_seed = 0;
4877 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4878 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4879}
4880
7af40ad9
AD		 4881static int igb_tso(struct igb_ring *tx_ring,
4882 struct igb_tx_buffer *first,
4883 u8 *hdr_len)
9d5c8243 4884{
e10715d3 4885 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7af40ad9 4886 struct sk_buff *skb = first->skb;
e10715d3
AD		 4887 union {
4888 struct iphdr *v4;
4889 struct ipv6hdr *v6;
4890 unsigned char *hdr;
4891 } ip;
4892 union {
4893 struct tcphdr *tcp;
4894 unsigned char *hdr;
4895 } l4;
4896 u32 paylen, l4_offset;
06c14e5a 4897 int err;
7d13a7d0 4898
ed6aa105
AD		 4899 if (skb->ip_summed != CHECKSUM_PARTIAL)
4900 return 0;
4901
7d13a7d0
AD		 4902 if (!skb_is_gso(skb))
4903 return 0;
9d5c8243 4904
06c14e5a
FR		 4905 err = skb_cow_head(skb, 0);
4906 if (err < 0)
4907 return err;
9d5c8243 4908
e10715d3
AD		 4909 ip.hdr = skb_network_header(skb);
4910 l4.hdr = skb_checksum_start(skb);
4911
7d13a7d0
AD		 4912 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4913 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4914
e10715d3
AD		 4915 /* initialize outer IP header fields */
4916 if (ip.v4->version == 4) {
4917 /* IP header will have to cancel out any data that
4918 * is not a part of the outer IP header
4919 */
4920 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
4921 csum_unfold(l4.tcp->check)));
7d13a7d0 4922 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
e10715d3
AD		 4923
4924 ip.v4->tot_len = 0;
7af40ad9
AD		 4925 first->tx_flags |= IGB_TX_FLAGS_TSO |
4926 IGB_TX_FLAGS_CSUM |
4927 IGB_TX_FLAGS_IPV4;
e10715d3
AD		 4928 } else {
4929 ip.v6->payload_len = 0;
7af40ad9
AD		 4930 first->tx_flags |= IGB_TX_FLAGS_TSO |
4931 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4932 }
4933
e10715d3
AD		 4934 /* determine offset of inner transport header */
4935 l4_offset = l4.hdr - skb->data;
4936
4937 /* compute length of segmentation header */
4938 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
4939
4940 /* remove payload length from inner checksum */
4941 paylen = skb->len - l4_offset;
4942 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
9d5c8243 4943
7af40ad9
AD		 4944 /* update gso size and bytecount with header size */
4945 first->gso_segs = skb_shinfo(skb)->gso_segs;
4946 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4947
9d5c8243 4948 /* MSS L4LEN IDX */
e10715d3 4949 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
7d13a7d0 4950 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4951
7d13a7d0 4952 /* VLAN MACLEN IPLEN */
e10715d3
AD		 4953 vlan_macip_lens = l4.hdr - ip.hdr;
4954 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4955 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4956
7d13a7d0 4957 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4958
7d13a7d0 4959 return 1;
9d5c8243
AK		 4960}
4961
6e033700
AD		 4962static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
4963{
4964 unsigned int offset = 0;
4965
4966 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
4967
4968 return offset == skb_checksum_start_offset(skb);
4969}
4970
7af40ad9 4971static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4972{
7af40ad9 4973 struct sk_buff *skb = first->skb;
7d13a7d0 4974 u32 vlan_macip_lens = 0;
7d13a7d0 4975 u32 type_tucmd = 0;
9d5c8243 4976
7d13a7d0 4977 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6e033700 4978csum_failed:
7af40ad9
AD		 4979 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4980 return;
6e033700
AD		 4981 goto no_csum;
4982 }
fa4a7ef3 4983
6e033700
AD		 4984 switch (skb->csum_offset) {
4985 case offsetof(struct tcphdr, check):
4986 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4987 /* fall through */
4988 case offsetof(struct udphdr, check):
4989 break;
4990 case offsetof(struct sctphdr, checksum):
4991 /* validate that this is actually an SCTP request */
4992 if (((first->protocol == htons(ETH_P_IP)) &&
4993 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
4994 ((first->protocol == htons(ETH_P_IPV6)) &&
4995 igb_ipv6_csum_is_sctp(skb))) {
4996 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
7d13a7d0 4997 break;
9d5c8243 4998 }
6e033700
AD		 4999 default:
5000 skb_checksum_help(skb);
5001 goto csum_failed;
7d13a7d0 5002 }
9d5c8243 5003
6e033700
AD		 5004 /* update TX checksum flag */
5005 first->tx_flags |= IGB_TX_FLAGS_CSUM;
5006 vlan_macip_lens = skb_checksum_start_offset(skb) -
5007 skb_network_offset(skb);
5008no_csum:
7d13a7d0 5009 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 5010 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 5011
6e033700 5012 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
9d5c8243
AK		 5013}
5014
1d9daf45
AD		 5015#define IGB_SET_FLAG(_input, _flag, _result) \
5016 ((_flag <= _result) ? \
5017 ((u32)(_input & _flag) * (_result / _flag)) : \
5018 ((u32)(_input & _flag) / (_flag / _result)))
5019
5020static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 5021{
5022 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 5023 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5024 E1000_ADVTXD_DCMD_DEXT |
5025 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 5026
5027 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 5028 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5029 (E1000_ADVTXD_DCMD_VLE));
5030
5031 /* set segmentation bits for TSO */
5032 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5033 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 5034
5035 /* set timestamp bit if present */
1d9daf45
AD		 5036 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5037 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 5038
1d9daf45
AD		 5039 /* insert frame checksum */
5040 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 5041
5042 return cmd_type;
5043}
5044
7af40ad9
AD		 5045static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5046 union e1000_adv_tx_desc *tx_desc,
5047 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 5048{
5049 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5050
1d9daf45
AD		 5051 /* 82575 requires a unique index per ring */
5052 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 5053 olinfo_status |= tx_ring->reg_idx << 4;
5054
5055 /* insert L4 checksum */
1d9daf45
AD		 5056 olinfo_status |= IGB_SET_FLAG(tx_flags,
5057 IGB_TX_FLAGS_CSUM,
5058 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 5059
1d9daf45
AD		 5060 /* insert IPv4 checksum */
5061 olinfo_status |= IGB_SET_FLAG(tx_flags,
5062 IGB_TX_FLAGS_IPV4,
5063 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 5064
7af40ad9 5065 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 5066}
5067
6f19e12f
DM		 5068static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5069{
5070 struct net_device *netdev = tx_ring->netdev;
5071
5072 netif_stop_subqueue(netdev, tx_ring->queue_index);
5073
5074 /* Herbert's original patch had:
5075 * smp_mb__after_netif_stop_queue();
5076 * but since that doesn't exist yet, just open code it.
5077 */
5078 smp_mb();
5079
5080 /* We need to check again in a case another CPU has just
5081 * made room available.
5082 */
5083 if (igb_desc_unused(tx_ring) < size)
5084 return -EBUSY;
5085
5086 /* A reprieve! */
5087 netif_wake_subqueue(netdev, tx_ring->queue_index);
5088
5089 u64_stats_update_begin(&tx_ring->tx_syncp2);
5090 tx_ring->tx_stats.restart_queue2++;
5091 u64_stats_update_end(&tx_ring->tx_syncp2);
5092
5093 return 0;
5094}
5095
5096static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5097{
5098 if (igb_desc_unused(tx_ring) >= size)
5099 return 0;
5100 return __igb_maybe_stop_tx(tx_ring, size);
5101}
5102
7af40ad9
AD		 5103static void igb_tx_map(struct igb_ring *tx_ring,
5104 struct igb_tx_buffer *first,
ebe42d16 5105 const u8 hdr_len)
9d5c8243 5106{
7af40ad9 5107 struct sk_buff *skb = first->skb;
c9f14bf3 5108 struct igb_tx_buffer *tx_buffer;
ebe42d16 5109 union e1000_adv_tx_desc *tx_desc;
80d0759e 5110 struct skb_frag_struct *frag;
ebe42d16 5111 dma_addr_t dma;
80d0759e 5112 unsigned int data_len, size;
7af40ad9 5113 u32 tx_flags = first->tx_flags;
1d9daf45 5114 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 5115 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 5116
5117 tx_desc = IGB_TX_DESC(tx_ring, i);
5118
80d0759e
AD		 5119 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5120
5121 size = skb_headlen(skb);
5122 data_len = skb->data_len;
ebe42d16
AD		 5123
5124 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 5125
80d0759e
AD		 5126 tx_buffer = first;
5127
5128 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5129 if (dma_mapping_error(tx_ring->dev, dma))
5130 goto dma_error;
5131
5132 /* record length, and DMA address */
5133 dma_unmap_len_set(tx_buffer, len, size);
5134 dma_unmap_addr_set(tx_buffer, dma, dma);
5135
5136 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5137
ebe42d16
AD		 5138 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5139 tx_desc->read.cmd_type_len =
1d9daf45 5140 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5141
5142 i++;
5143 tx_desc++;
5144 if (i == tx_ring->count) {
5145 tx_desc = IGB_TX_DESC(tx_ring, 0);
5146 i = 0;
5147 }
80d0759e 5148 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5149
5150 dma += IGB_MAX_DATA_PER_TXD;
5151 size -= IGB_MAX_DATA_PER_TXD;
5152
ebe42d16
AD		 5153 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5154 }
5155
5156 if (likely(!data_len))
5157 break;
2bbfebe2 5158
1d9daf45 5159 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5160
65689fef 5161 i++;
ebe42d16
AD		 5162 tx_desc++;
5163 if (i == tx_ring->count) {
5164 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5165 i = 0;
ebe42d16 5166 }
80d0759e 5167 tx_desc->read.olinfo_status = 0;
65689fef 5168
9e903e08 5169 size = skb_frag_size(frag);
ebe42d16
AD		 5170 data_len -= size;
5171
5172 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5173 size, DMA_TO_DEVICE);
6366ad33 5174
c9f14bf3 5175 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5176 }
5177
ebe42d16 5178 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5179 cmd_type |= size | IGB_TXD_DCMD;
5180 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5181
80d0759e
AD		 5182 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5183
8542db05
AD		 5184 /* set the timestamp */
5185 first->time_stamp = jiffies;
5186
b980ac18 5187 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5188 * are new descriptors to fetch. (Only applicable for weak-ordered
5189 * memory model archs, such as IA-64).
5190 *
5191 * We also need this memory barrier to make certain all of the
5192 * status bits have been updated before next_to_watch is written.
5193 */
5194 wmb();
5195
8542db05 5196 /* set next_to_watch value indicating a packet is present */
ebe42d16 5197 first->next_to_watch = tx_desc;
9d5c8243 5198
ebe42d16
AD		 5199 i++;
5200 if (i == tx_ring->count)
5201 i = 0;
6366ad33 5202
ebe42d16 5203 tx_ring->next_to_use = i;
6366ad33 5204
6f19e12f
DM		 5205 /* Make sure there is space in the ring for the next send. */
5206 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5207
5208 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5209 writel(i, tx_ring->tail);
5210
5211 /* we need this if more than one processor can write to our tail
5212 * at a time, it synchronizes IO on IA64/Altix systems
5213 */
5214 mmiowb();
5215 }
ebe42d16
AD		 5216 return;
5217
5218dma_error:
5219 dev_err(tx_ring->dev, "TX DMA map failed\n");
5220
5221 /* clear dma mappings for failed tx_buffer_info map */
5222 for (;;) {
c9f14bf3
AD		 5223 tx_buffer = &tx_ring->tx_buffer_info[i];
5224 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5225 if (tx_buffer == first)
ebe42d16 5226 break;
a77ff709
NN		 5227 if (i == 0)
5228 i = tx_ring->count;
6366ad33 5229 i--;
6366ad33
AD		 5230 }
5231
9d5c8243 5232 tx_ring->next_to_use = i;
9d5c8243
AK		 5233}
5234
cd392f5c
AD		 5235netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5236 struct igb_ring *tx_ring)
9d5c8243 5237{
8542db05 5238 struct igb_tx_buffer *first;
ebe42d16 5239 int tso;
91d4ee33 5240 u32 tx_flags = 0;
2ee52ad4 5241 unsigned short f;
21ba6fe1 5242 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5243 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5244 u8 hdr_len = 0;
9d5c8243 5245
21ba6fe1
AD		 5246 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5247 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5248 * + 2 desc gap to keep tail from touching head,
9d5c8243 5249 * + 1 desc for context descriptor,
21ba6fe1
AD		 5250 * otherwise try next time
5251 */
2ee52ad4
AD		 5252 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5253 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5254
5255 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5256 /* this is a hard error */
9d5c8243
AK		 5257 return NETDEV_TX_BUSY;
5258 }
33af6bcc 5259
7af40ad9
AD		 5260 /* record the location of the first descriptor for this packet */
5261 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5262 first->skb = skb;
5263 first->bytecount = skb->len;
5264 first->gso_segs = 1;
5265
b646c22e
AD		 5266 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5267 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5268
ed4420a3
JK		 5269 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5270 &adapter->state)) {
b646c22e
AD		 5271 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5272 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5273
5274 adapter->ptp_tx_skb = skb_get(skb);
5275 adapter->ptp_tx_start = jiffies;
5276 if (adapter->hw.mac.type == e1000_82576)
5277 schedule_work(&adapter->ptp_tx_work);
5278 }
33af6bcc 5279 }
9d5c8243 5280
afc835d1
JK		 5281 skb_tx_timestamp(skb);
5282
df8a39de 5283 if (skb_vlan_tag_present(skb)) {
9d5c8243 5284 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5285 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5286 }
5287
7af40ad9
AD		 5288 /* record initial flags and protocol */
5289 first->tx_flags = tx_flags;
5290 first->protocol = protocol;
cdfd01fc 5291
7af40ad9
AD		 5292 tso = igb_tso(tx_ring, first, &hdr_len);
5293 if (tso < 0)
7d13a7d0 5294 goto out_drop;
7af40ad9
AD		 5295 else if (!tso)
5296 igb_tx_csum(tx_ring, first);
9d5c8243 5297
7af40ad9 5298 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5299
9d5c8243 5300 return NETDEV_TX_OK;
7d13a7d0
AD		 5301
5302out_drop:
7af40ad9
AD		 5303 igb_unmap_and_free_tx_resource(tx_ring, first);
5304
7d13a7d0 5305 return NETDEV_TX_OK;
9d5c8243
AK		 5306}
5307
0b725a2c
DM		 5308static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5309 struct sk_buff *skb)
1cc3bd87 5310{
0b725a2c
DM		 5311 unsigned int r_idx = skb->queue_mapping;
5312
1cc3bd87
AD		 5313 if (r_idx >= adapter->num_tx_queues)
5314 r_idx = r_idx % adapter->num_tx_queues;
5315
5316 return adapter->tx_ring[r_idx];
5317}
5318
cd392f5c
AD		 5319static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5320 struct net_device *netdev)
9d5c8243
AK		 5321{
5322 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3 5323
b980ac18 5324 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5325 * in order to meet this minimum size requirement.
5326 */
a94d9e22
AD		 5327 if (skb_put_padto(skb, 17))
5328 return NETDEV_TX_OK;
9d5c8243 5329
1cc3bd87 5330 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5331}
5332
5333/**
b980ac18
JK		 5334 * igb_tx_timeout - Respond to a Tx Hang
5335 * @netdev: network interface device structure
9d5c8243
AK		 5336 **/
5337static void igb_tx_timeout(struct net_device *netdev)
5338{
5339 struct igb_adapter *adapter = netdev_priv(netdev);
5340 struct e1000_hw *hw = &adapter->hw;
5341
5342 /* Do the reset outside of interrupt context */
5343 adapter->tx_timeout_count++;
f7ba205e 5344
06218a8d 5345 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5346 hw->dev_spec._82575.global_device_reset = true;
5347
9d5c8243 5348 schedule_work(&adapter->reset_task);
265de409
AD		 5349 wr32(E1000_EICS,
5350 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5351}
5352
5353static void igb_reset_task(struct work_struct *work)
5354{
5355 struct igb_adapter *adapter;
5356 adapter = container_of(work, struct igb_adapter, reset_task);
5357
c97ec42a
TI		 5358 igb_dump(adapter);
5359 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5360 igb_reinit_locked(adapter);
5361}
5362
5363/**
b980ac18
JK		 5364 * igb_get_stats64 - Get System Network Statistics
5365 * @netdev: network interface device structure
5366 * @stats: rtnl_link_stats64 pointer
9d5c8243 5367 **/
12dcd86b 5368static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5369 struct rtnl_link_stats64 *stats)
9d5c8243 5370{
12dcd86b
ED		 5371 struct igb_adapter *adapter = netdev_priv(netdev);
5372
5373 spin_lock(&adapter->stats64_lock);
5374 igb_update_stats(adapter, &adapter->stats64);
5375 memcpy(stats, &adapter->stats64, sizeof(*stats));
5376 spin_unlock(&adapter->stats64_lock);
5377
5378 return stats;
9d5c8243
AK		 5379}
5380
5381/**
b980ac18
JK		 5382 * igb_change_mtu - Change the Maximum Transfer Unit
5383 * @netdev: network interface device structure
5384 * @new_mtu: new value for maximum frame size
9d5c8243 5385 *
b980ac18 5386 * Returns 0 on success, negative on failure
9d5c8243
AK		 5387 **/
5388static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5389{
5390 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5391 struct pci_dev *pdev = adapter->pdev;
153285f9 5392 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5393
c809d227 5394 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5395 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5396 return -EINVAL;
5397 }
5398
153285f9 5399#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5400 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5401 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5402 return -EINVAL;
5403 }
5404
2ccd994c
AD		 5405 /* adjust max frame to be at least the size of a standard frame */
5406 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5407 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5408
9d5c8243 5409 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5410 usleep_range(1000, 2000);
73cd78f1 5411
9d5c8243
AK		 5412 /* igb_down has a dependency on max_frame_size */
5413 adapter->max_frame_size = max_frame;
559e9c49 5414
4c844851
AD		 5415 if (netif_running(netdev))
5416 igb_down(adapter);
9d5c8243 5417
090b1795 5418 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5419 netdev->mtu, new_mtu);
5420 netdev->mtu = new_mtu;
5421
5422 if (netif_running(netdev))
5423 igb_up(adapter);
5424 else
5425 igb_reset(adapter);
5426
5427 clear_bit(__IGB_RESETTING, &adapter->state);
5428
5429 return 0;
5430}
5431
5432/**
b980ac18
JK		 5433 * igb_update_stats - Update the board statistics counters
5434 * @adapter: board private structure
9d5c8243 5435 **/
12dcd86b
ED		 5436void igb_update_stats(struct igb_adapter *adapter,
5437 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5438{
5439 struct e1000_hw *hw = &adapter->hw;
5440 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5441 u32 reg, mpc;
3f9c0164
AD		 5442 int i;
5443 u64 bytes, packets;
12dcd86b
ED		 5444 unsigned int start;
5445 u64 _bytes, _packets;
9d5c8243 5446
b980ac18 5447 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5448 * connection is down.
5449 */
5450 if (adapter->link_speed == 0)
5451 return;
5452 if (pci_channel_offline(pdev))
5453 return;
5454
3f9c0164
AD		 5455 bytes = 0;
5456 packets = 0;
7f90128e
AA		 5457
5458 rcu_read_lock();
3f9c0164 5459 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5460 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5461 u32 rqdpc = rd32(E1000_RQDPC(i));
5462 if (hw->mac.type >= e1000_i210)
5463 wr32(E1000_RQDPC(i), 0);
12dcd86b 5464
ae1c07a6
AD		 5465 if (rqdpc) {
5466 ring->rx_stats.drops += rqdpc;
5467 net_stats->rx_fifo_errors += rqdpc;
5468 }
12dcd86b
ED		 5469
5470 do {
57a7744e 5471 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5472 _bytes = ring->rx_stats.bytes;
5473 _packets = ring->rx_stats.packets;
57a7744e 5474 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5475 bytes += _bytes;
5476 packets += _packets;
3f9c0164
AD		 5477 }
5478
128e45eb
AD		 5479 net_stats->rx_bytes = bytes;
5480 net_stats->rx_packets = packets;
3f9c0164
AD		 5481
5482 bytes = 0;
5483 packets = 0;
5484 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5485 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5486 do {
57a7744e 5487 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5488 _bytes = ring->tx_stats.bytes;
5489 _packets = ring->tx_stats.packets;
57a7744e 5490 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5491 bytes += _bytes;
5492 packets += _packets;
3f9c0164 5493 }
128e45eb
AD		 5494 net_stats->tx_bytes = bytes;
5495 net_stats->tx_packets = packets;
7f90128e 5496 rcu_read_unlock();
3f9c0164
AD		 5497
5498 /* read stats registers */
9d5c8243
AK		 5499 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5500 adapter->stats.gprc += rd32(E1000_GPRC);
5501 adapter->stats.gorc += rd32(E1000_GORCL);
5502 rd32(E1000_GORCH); /* clear GORCL */
5503 adapter->stats.bprc += rd32(E1000_BPRC);
5504 adapter->stats.mprc += rd32(E1000_MPRC);
5505 adapter->stats.roc += rd32(E1000_ROC);
5506
5507 adapter->stats.prc64 += rd32(E1000_PRC64);
5508 adapter->stats.prc127 += rd32(E1000_PRC127);
5509 adapter->stats.prc255 += rd32(E1000_PRC255);
5510 adapter->stats.prc511 += rd32(E1000_PRC511);
5511 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5512 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5513 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5514 adapter->stats.sec += rd32(E1000_SEC);
5515
fa3d9a6d
MW		 5516 mpc = rd32(E1000_MPC);
5517 adapter->stats.mpc += mpc;
5518 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5519 adapter->stats.scc += rd32(E1000_SCC);
5520 adapter->stats.ecol += rd32(E1000_ECOL);
5521 adapter->stats.mcc += rd32(E1000_MCC);
5522 adapter->stats.latecol += rd32(E1000_LATECOL);
5523 adapter->stats.dc += rd32(E1000_DC);
5524 adapter->stats.rlec += rd32(E1000_RLEC);
5525 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5526 adapter->stats.xontxc += rd32(E1000_XONTXC);
5527 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5528 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5529 adapter->stats.fcruc += rd32(E1000_FCRUC);
5530 adapter->stats.gptc += rd32(E1000_GPTC);
5531 adapter->stats.gotc += rd32(E1000_GOTCL);
5532 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5533 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5534 adapter->stats.ruc += rd32(E1000_RUC);
5535 adapter->stats.rfc += rd32(E1000_RFC);
5536 adapter->stats.rjc += rd32(E1000_RJC);
5537 adapter->stats.tor += rd32(E1000_TORH);
5538 adapter->stats.tot += rd32(E1000_TOTH);
5539 adapter->stats.tpr += rd32(E1000_TPR);
5540
5541 adapter->stats.ptc64 += rd32(E1000_PTC64);
5542 adapter->stats.ptc127 += rd32(E1000_PTC127);
5543 adapter->stats.ptc255 += rd32(E1000_PTC255);
5544 adapter->stats.ptc511 += rd32(E1000_PTC511);
5545 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5546 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5547
5548 adapter->stats.mptc += rd32(E1000_MPTC);
5549 adapter->stats.bptc += rd32(E1000_BPTC);
5550
2d0b0f69
NN		 5551 adapter->stats.tpt += rd32(E1000_TPT);
5552 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5553
5554 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5555 /* read internal phy specific stats */
5556 reg = rd32(E1000_CTRL_EXT);
5557 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5558 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5559
5560 /* this stat has invalid values on i210/i211 */
5561 if ((hw->mac.type != e1000_i210) &&
5562 (hw->mac.type != e1000_i211))
5563 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5564 }
5565
9d5c8243
AK		 5566 adapter->stats.tsctc += rd32(E1000_TSCTC);
5567 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5568
5569 adapter->stats.iac += rd32(E1000_IAC);
5570 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5571 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5572 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5573 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5574 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5575 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5576 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5577 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5578
5579 /* Fill out the OS statistics structure */
128e45eb
AD		 5580 net_stats->multicast = adapter->stats.mprc;
5581 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5582
5583 /* Rx Errors */
5584
5585 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5586 * our own version based on RUC and ROC
5587 */
128e45eb 5588 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5589 adapter->stats.crcerrs + adapter->stats.algnerrc +
5590 adapter->stats.ruc + adapter->stats.roc +
5591 adapter->stats.cexterr;
128e45eb
AD		 5592 net_stats->rx_length_errors = adapter->stats.ruc +
5593 adapter->stats.roc;
5594 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5595 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5596 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5597
5598 /* Tx Errors */
128e45eb
AD		 5599 net_stats->tx_errors = adapter->stats.ecol +
5600 adapter->stats.latecol;
5601 net_stats->tx_aborted_errors = adapter->stats.ecol;
5602 net_stats->tx_window_errors = adapter->stats.latecol;
5603 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5604
5605 /* Tx Dropped needs to be maintained elsewhere */
5606
9d5c8243
AK		 5607 /* Management Stats */
5608 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5609 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5610 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5611
5612 /* OS2BMC Stats */
5613 reg = rd32(E1000_MANC);
5614 if (reg & E1000_MANC_EN_BMC2OS) {
5615 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5616 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5617 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5618 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5619 }
9d5c8243
AK		 5620}
5621
61d7f75f
RC		 5622static void igb_tsync_interrupt(struct igb_adapter *adapter)
5623{
5624 struct e1000_hw *hw = &adapter->hw;
00c65578 5625 struct ptp_clock_event event;
40c9b079 5626 struct timespec64 ts;
720db4ff 5627 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5628
5629 if (tsicr & TSINTR_SYS_WRAP) {
5630 event.type = PTP_CLOCK_PPS;
5631 if (adapter->ptp_caps.pps)
5632 ptp_clock_event(adapter->ptp_clock, &event);
5633 else
5634 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5635 ack |= TSINTR_SYS_WRAP;
5636 }
61d7f75f
RC		 5637
5638 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5639 /* retrieve hardware timestamp */
5640 schedule_work(&adapter->ptp_tx_work);
00c65578 5641 ack |= E1000_TSICR_TXTS;
61d7f75f 5642 }
00c65578 5643
720db4ff
RC		 5644 if (tsicr & TSINTR_TT0) {
5645 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5646 ts = timespec64_add(adapter->perout[0].start,
5647 adapter->perout[0].period);
5648 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5649 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5650 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5651 tsauxc = rd32(E1000_TSAUXC);
5652 tsauxc |= TSAUXC_EN_TT0;
5653 wr32(E1000_TSAUXC, tsauxc);
5654 adapter->perout[0].start = ts;
5655 spin_unlock(&adapter->tmreg_lock);
5656 ack |= TSINTR_TT0;
5657 }
5658
5659 if (tsicr & TSINTR_TT1) {
5660 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5661 ts = timespec64_add(adapter->perout[1].start,
5662 adapter->perout[1].period);
720db4ff 5663 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5664 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5665 tsauxc = rd32(E1000_TSAUXC);
5666 tsauxc |= TSAUXC_EN_TT1;
5667 wr32(E1000_TSAUXC, tsauxc);
5668 adapter->perout[1].start = ts;
5669 spin_unlock(&adapter->tmreg_lock);
5670 ack |= TSINTR_TT1;
5671 }
5672
5673 if (tsicr & TSINTR_AUTT0) {
5674 nsec = rd32(E1000_AUXSTMPL0);
5675 sec = rd32(E1000_AUXSTMPH0);
5676 event.type = PTP_CLOCK_EXTTS;
5677 event.index = 0;
5678 event.timestamp = sec * 1000000000ULL + nsec;
5679 ptp_clock_event(adapter->ptp_clock, &event);
5680 ack |= TSINTR_AUTT0;
5681 }
5682
5683 if (tsicr & TSINTR_AUTT1) {
5684 nsec = rd32(E1000_AUXSTMPL1);
5685 sec = rd32(E1000_AUXSTMPH1);
5686 event.type = PTP_CLOCK_EXTTS;
5687 event.index = 1;
5688 event.timestamp = sec * 1000000000ULL + nsec;
5689 ptp_clock_event(adapter->ptp_clock, &event);
5690 ack |= TSINTR_AUTT1;
5691 }
5692
00c65578
RC		 5693 /* acknowledge the interrupts */
5694 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5695}
5696
9d5c8243
AK		 5697static irqreturn_t igb_msix_other(int irq, void *data)
5698{
047e0030 5699 struct igb_adapter *adapter = data;
9d5c8243 5700 struct e1000_hw *hw = &adapter->hw;
844290e5 5701 u32 icr = rd32(E1000_ICR);
844290e5 5702 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5703
7f081d40
AD		 5704 if (icr & E1000_ICR_DRSTA)
5705 schedule_work(&adapter->reset_task);
5706
047e0030 5707 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5708 /* HW is reporting DMA is out of sync */
5709 adapter->stats.doosync++;
13800469
GR		 5710 /* The DMA Out of Sync is also indication of a spoof event
5711 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5712 * see if it is really a spoof event.
5713 */
13800469 5714 igb_check_wvbr(adapter);
dda0e083 5715 }
eebbbdba 5716
4ae196df
AD		 5717 /* Check for a mailbox event */
5718 if (icr & E1000_ICR_VMMB)
5719 igb_msg_task(adapter);
5720
5721 if (icr & E1000_ICR_LSC) {
5722 hw->mac.get_link_status = 1;
5723 /* guard against interrupt when we're going down */
5724 if (!test_bit(__IGB_DOWN, &adapter->state))
5725 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5726 }
5727
61d7f75f
RC		 5728 if (icr & E1000_ICR_TS)
5729 igb_tsync_interrupt(adapter);
1f6e8178 5730
844290e5 5731 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5732
5733 return IRQ_HANDLED;
5734}
5735
047e0030 5736static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5737{
26b39276 5738 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5739 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5740
047e0030
AD		 5741 if (!q_vector->set_itr)
5742 return;
73cd78f1 5743
047e0030
AD		 5744 if (!itr_val)
5745 itr_val = 0x4;
661086df 5746
26b39276
AD		 5747 if (adapter->hw.mac.type == e1000_82575)
5748 itr_val |= itr_val << 16;
661086df 5749 else
0ba82994 5750 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5751
047e0030
AD		 5752 writel(itr_val, q_vector->itr_register);
5753 q_vector->set_itr = 0;
6eb5a7f1
AD		 5754}
5755
047e0030 5756static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5757{
047e0030 5758 struct igb_q_vector *q_vector = data;
9d5c8243 5759
047e0030
AD		 5760 /* Write the ITR value calculated from the previous interrupt. */
5761 igb_write_itr(q_vector);
9d5c8243 5762
047e0030 5763 napi_schedule(&q_vector->napi);
844290e5 5764
047e0030 5765 return IRQ_HANDLED;
fe4506b6
JC		 5766}
5767
421e02f0 5768#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5769static void igb_update_tx_dca(struct igb_adapter *adapter,
5770 struct igb_ring *tx_ring,
5771 int cpu)
5772{
5773 struct e1000_hw *hw = &adapter->hw;
5774 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5775
5776 if (hw->mac.type != e1000_82575)
5777 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5778
b980ac18 5779 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5780 * DCA is enabled. This is due to a known issue in some chipsets
5781 * which will cause the DCA tag to be cleared.
5782 */
5783 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5784 E1000_DCA_TXCTRL_DATA_RRO_EN |
5785 E1000_DCA_TXCTRL_DESC_DCA_EN;
5786
5787 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5788}
5789
5790static void igb_update_rx_dca(struct igb_adapter *adapter,
5791 struct igb_ring *rx_ring,
5792 int cpu)
5793{
5794 struct e1000_hw *hw = &adapter->hw;
5795 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5796
5797 if (hw->mac.type != e1000_82575)
5798 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5799
b980ac18 5800 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5801 * DCA is enabled. This is due to a known issue in some chipsets
5802 * which will cause the DCA tag to be cleared.
5803 */
5804 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5805 E1000_DCA_RXCTRL_DESC_DCA_EN;
5806
5807 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5808}
5809
047e0030 5810static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5811{
047e0030 5812 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5813 int cpu = get_cpu();
fe4506b6 5814
047e0030
AD		 5815 if (q_vector->cpu == cpu)
5816 goto out_no_update;
5817
6a05004a
AD		 5818 if (q_vector->tx.ring)
5819 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5820
5821 if (q_vector->rx.ring)
5822 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5823
047e0030
AD		 5824 q_vector->cpu = cpu;
5825out_no_update:
fe4506b6
JC		 5826 put_cpu();
5827}
5828
5829static void igb_setup_dca(struct igb_adapter *adapter)
5830{
7e0e99ef 5831 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5832 int i;
5833
7dfc16fa 5834 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5835 return;
5836
7e0e99ef
AD		 5837 /* Always use CB2 mode, difference is masked in the CB driver. */
5838 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5839
047e0030 5840 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5841 adapter->q_vector[i]->cpu = -1;
5842 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5843 }
5844}
5845
5846static int __igb_notify_dca(struct device *dev, void *data)
5847{
5848 struct net_device *netdev = dev_get_drvdata(dev);
5849 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5850 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5851 struct e1000_hw *hw = &adapter->hw;
5852 unsigned long event = *(unsigned long *)data;
5853
5854 switch (event) {
5855 case DCA_PROVIDER_ADD:
5856 /* if already enabled, don't do it again */
7dfc16fa 5857 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5858 break;
fe4506b6 5859 if (dca_add_requester(dev) == 0) {
bbd98fe4 5860 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5861 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5862 igb_setup_dca(adapter);
5863 break;
5864 }
5865 /* Fall Through since DCA is disabled. */
5866 case DCA_PROVIDER_REMOVE:
7dfc16fa 5867 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5868 /* without this a class_device is left
b980ac18
JK		 5869 * hanging around in the sysfs model
5870 */
fe4506b6 5871 dca_remove_requester(dev);
090b1795 5872 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5873 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5874 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5875 }
5876 break;
5877 }
bbd98fe4 5878
fe4506b6 5879 return 0;
9d5c8243
AK		 5880}
5881
fe4506b6 5882static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5883 void *p)
fe4506b6
JC		 5884{
5885 int ret_val;
5886
5887 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5888 __igb_notify_dca);
fe4506b6
JC		 5889
5890 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5891}
421e02f0 5892#endif /* CONFIG_IGB_DCA */
9d5c8243 5893
0224d663
GR		 5894#ifdef CONFIG_PCI_IOV
5895static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5896{
5897 unsigned char mac_addr[ETH_ALEN];
0224d663 5898
5ac6f91d 5899 eth_zero_addr(mac_addr);
0224d663
GR		 5900 igb_set_vf_mac(adapter, vf, mac_addr);
5901
70ea4783
LL		 5902 /* By default spoof check is enabled for all VFs */
5903 adapter->vf_data[vf].spoofchk_enabled = true;
5904
f557147c 5905 return 0;
0224d663
GR		 5906}
5907
0224d663 5908#endif
4ae196df
AD		 5909static void igb_ping_all_vfs(struct igb_adapter *adapter)
5910{
5911 struct e1000_hw *hw = &adapter->hw;
5912 u32 ping;
5913 int i;
5914
5915 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5916 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5917 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5918 ping |= E1000_VT_MSGTYPE_CTS;
5919 igb_write_mbx(hw, &ping, 1, i);
5920 }
5921}
5922
7d5753f0
AD		 5923static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5924{
5925 struct e1000_hw *hw = &adapter->hw;
5926 u32 vmolr = rd32(E1000_VMOLR(vf));
5927 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5928
d85b9004 5929 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5930 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5931 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5932
5933 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5934 vmolr |= E1000_VMOLR_MPME;
d85b9004 5935 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5936 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5937 } else {
b980ac18 5938 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5939 * flag we need to write the hashes to the MTA as this step
5940 * was previously skipped
5941 */
5942 if (vf_data->num_vf_mc_hashes > 30) {
5943 vmolr |= E1000_VMOLR_MPME;
5944 } else if (vf_data->num_vf_mc_hashes) {
5945 int j;
9005df38 5946
7d5753f0
AD		 5947 vmolr |= E1000_VMOLR_ROMPE;
5948 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5949 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5950 }
5951 }
5952
5953 wr32(E1000_VMOLR(vf), vmolr);
5954
5955 /* there are flags left unprocessed, likely not supported */
5956 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5957 return -EINVAL;
5958
5959 return 0;
7d5753f0
AD		 5960}
5961
4ae196df
AD		 5962static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5963 u32 *msgbuf, u32 vf)
5964{
5965 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5966 u16 *hash_list = (u16 *)&msgbuf[1];
5967 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5968 int i;
5969
7d5753f0 5970 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5971 * to this VF for later use to restore when the PF multi cast
5972 * list changes
5973 */
5974 vf_data->num_vf_mc_hashes = n;
5975
7d5753f0
AD		 5976 /* only up to 30 hash values supported */
5977 if (n > 30)
5978 n = 30;
5979
5980 /* store the hashes for later use */
4ae196df 5981 for (i = 0; i < n; i++)
a419aef8 5982 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5983
5984 /* Flush and reset the mta with the new values */
ff41f8dc 5985 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5986
5987 return 0;
5988}
5989
5990static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5991{
5992 struct e1000_hw *hw = &adapter->hw;
5993 struct vf_data_storage *vf_data;
5994 int i, j;
5995
5996 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5997 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5998
7d5753f0
AD		 5999 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6000
4ae196df 6001 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 6002
6003 if ((vf_data->num_vf_mc_hashes > 30) ||
6004 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6005 vmolr |= E1000_VMOLR_MPME;
6006 } else if (vf_data->num_vf_mc_hashes) {
6007 vmolr |= E1000_VMOLR_ROMPE;
6008 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6009 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6010 }
6011 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 6012 }
6013}
6014
6015static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6016{
6017 struct e1000_hw *hw = &adapter->hw;
16903caa 6018 u32 pool_mask, vlvf_mask, i;
4ae196df 6019
16903caa
AD		 6020 /* create mask for VF and other pools */
6021 pool_mask = E1000_VLVF_POOLSEL_MASK;
a51d8c21 6022 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
16903caa
AD		 6023
6024 /* drop PF from pool bits */
a51d8c21
JK		 6025 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6026 adapter->vfs_allocated_count);
4ae196df
AD		 6027
6028 /* Find the vlan filter for this id */
16903caa
AD		 6029 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6030 u32 vlvf = rd32(E1000_VLVF(i));
6031 u32 vfta_mask, vid, vfta;
4ae196df
AD		 6032
6033 /* remove the vf from the pool */
16903caa
AD		 6034 if (!(vlvf & vlvf_mask))
6035 continue;
6036
6037 /* clear out bit from VLVF */
6038 vlvf ^= vlvf_mask;
6039
6040 /* if other pools are present, just remove ourselves */
6041 if (vlvf & pool_mask)
6042 goto update_vlvfb;
4ae196df 6043
16903caa
AD		 6044 /* if PF is present, leave VFTA */
6045 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6046 goto update_vlvf;
4ae196df 6047
16903caa 6048 vid = vlvf & E1000_VLVF_VLANID_MASK;
a51d8c21 6049 vfta_mask = BIT(vid % 32);
16903caa
AD		 6050
6051 /* clear bit from VFTA */
6052 vfta = adapter->shadow_vfta[vid / 32];
6053 if (vfta & vfta_mask)
6054 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6055update_vlvf:
6056 /* clear pool selection enable */
6057 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6058 vlvf &= E1000_VLVF_POOLSEL_MASK;
6059 else
6060 vlvf = 0;
6061update_vlvfb:
6062 /* clear pool bits */
6063 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 6064 }
6065}
ae641bdc 6066
16903caa 6067static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 6068{
16903caa
AD		 6069 u32 vlvf;
6070 int idx;
6f3dc319 6071
16903caa
AD		 6072 /* short cut the special case */
6073 if (vlan == 0)
6074 return 0;
6075
6076 /* Search for the VLAN id in the VLVF entries */
6077 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6078 vlvf = rd32(E1000_VLVF(idx));
6079 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 6080 break;
6081 }
6082
16903caa 6083 return idx;
4ae196df
AD		 6084}
6085
8008f68c 6086static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
4ae196df
AD		 6087{
6088 struct e1000_hw *hw = &adapter->hw;
16903caa
AD		 6089 u32 bits, pf_id;
6090 int idx;
51466239 6091
16903caa
AD		 6092 idx = igb_find_vlvf_entry(hw, vid);
6093 if (!idx)
6094 return;
4ae196df 6095
16903caa
AD		 6096 /* See if any other pools are set for this VLAN filter
6097 * entry other than the PF.
6098 */
6099 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
a51d8c21 6100 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
16903caa
AD		 6101 bits &= rd32(E1000_VLVF(idx));
6102
6103 /* Disable the filter so this falls into the default pool. */
6104 if (!bits) {
6105 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
a51d8c21 6106 wr32(E1000_VLVF(idx), BIT(pf_id));
16903caa
AD		 6107 else
6108 wr32(E1000_VLVF(idx), 0);
4ae196df 6109 }
6f3dc319 6110}
4ae196df 6111
a15d9259
AD		 6112static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6113 bool add, u32 vf)
4ae196df 6114{
a15d9259 6115 int pf_id = adapter->vfs_allocated_count;
6f3dc319 6116 struct e1000_hw *hw = &adapter->hw;
a15d9259 6117 int err;
ae641bdc 6118
a15d9259
AD		 6119 /* If VLAN overlaps with one the PF is currently monitoring make
6120 * sure that we are able to allocate a VLVF entry. This may be
6121 * redundant but it guarantees PF will maintain visibility to
6122 * the VLAN.
6f3dc319 6123 */
16903caa 6124 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6125 err = igb_vfta_set(hw, vid, pf_id, true, false);
6126 if (err)
6127 return err;
4ae196df 6128 }
6f3dc319 6129
a15d9259 6130 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6131
16903caa
AD		 6132 if (add && !err)
6133 return err;
6f3dc319 6134
16903caa
AD		 6135 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6136 * we may need to drop the PF pool bit in order to allow us to free
6137 * up the VLVF resources.
6f3dc319 6138 */
16903caa
AD		 6139 if (test_bit(vid, adapter->active_vlans) ||
6140 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6141 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6142
6f3dc319 6143 return err;
8151d294
WM		 6144}
6145
6146static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6147{
6148 struct e1000_hw *hw = &adapter->hw;
6149
6150 if (vid)
6151 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6152 else
6153 wr32(E1000_VMVIR(vf), 0);
6154}
6155
a15d9259
AD		 6156static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6157 u16 vlan, u8 qos)
8151d294 6158{
a15d9259 6159 int err;
8151d294 6160
a15d9259
AD		 6161 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6162 if (err)
6163 return err;
6164
6165 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6166 igb_set_vmolr(adapter, vf, !vlan);
6167
6168 /* revoke access to previous VLAN */
6169 if (vlan != adapter->vf_data[vf].pf_vlan)
6170 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6171 false, vf);
6172
6173 adapter->vf_data[vf].pf_vlan = vlan;
6174 adapter->vf_data[vf].pf_qos = qos;
030f9f52 6175 igb_set_vf_vlan_strip(adapter, vf, true);
a15d9259
AD		 6176 dev_info(&adapter->pdev->dev,
6177 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6178 if (test_bit(__IGB_DOWN, &adapter->state)) {
6179 dev_warn(&adapter->pdev->dev,
6180 "The VF VLAN has been set, but the PF device is not up.\n");
6181 dev_warn(&adapter->pdev->dev,
6182 "Bring the PF device up before attempting to use the VF device.\n");
b980ac18 6183 }
a15d9259 6184
b980ac18 6185 return err;
4ae196df
AD		 6186}
6187
a15d9259 6188static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6f3dc319 6189{
a15d9259
AD		 6190 /* Restore tagless access via VLAN 0 */
6191 igb_set_vf_vlan(adapter, 0, true, vf);
6f3dc319 6192
a15d9259 6193 igb_set_vmvir(adapter, 0, vf);
8151d294 6194 igb_set_vmolr(adapter, vf, true);
4ae196df 6195
a15d9259
AD		 6196 /* Remove any PF assigned VLAN */
6197 if (adapter->vf_data[vf].pf_vlan)
6198 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6199 false, vf);
6f3dc319 6200
a15d9259
AD		 6201 adapter->vf_data[vf].pf_vlan = 0;
6202 adapter->vf_data[vf].pf_qos = 0;
030f9f52 6203 igb_set_vf_vlan_strip(adapter, vf, false);
6f3dc319 6204
a15d9259 6205 return 0;
6f3dc319
GR		 6206}
6207
a15d9259
AD		 6208static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6209 int vf, u16 vlan, u8 qos)
4ae196df 6210{
a15d9259 6211 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 6212
a15d9259
AD		 6213 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6214 return -EINVAL;
6f3dc319 6215
a15d9259
AD		 6216 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6217 igb_disable_port_vlan(adapter, vf);
6218}
6f3dc319 6219
a15d9259
AD		 6220static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6221{
6222 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6223 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
030f9f52 6224 int ret;
6f3dc319 6225
a15d9259
AD		 6226 if (adapter->vf_data[vf].pf_vlan)
6227 return -1;
6f3dc319 6228
a15d9259
AD		 6229 /* VLAN 0 is a special case, don't allow it to be removed */
6230 if (!vid && !add)
6231 return 0;
6232
030f9f52
CV		 6233 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
6234 if (!ret)
6235 igb_set_vf_vlan_strip(adapter, vf, !!vid);
6236 return ret;
4ae196df
AD		 6237}
6238
f2ca0dbe 6239static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6240{
a15d9259 6241 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df 6242
a15d9259
AD		 6243 /* clear flags - except flag that indicates PF has set the MAC */
6244 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6245 vf_data->last_nack = jiffies;
4ae196df
AD		 6246
6247 /* reset vlans for device */
6248 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6249 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6250 igb_set_vmvir(adapter, vf_data->pf_vlan |
6251 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6252 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
030f9f52 6253 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
4ae196df
AD		 6254
6255 /* reset multicast table array for vf */
6256 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6257
6258 /* Flush and reset the mta with the new values */
ff41f8dc 6259 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6260}
6261
f2ca0dbe
AD		 6262static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6263{
6264 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6265
5ac6f91d 6266 /* clear mac address as we were hotplug removed/added */
8151d294 6267 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6268 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6269
6270 /* process remaining reset events */
6271 igb_vf_reset(adapter, vf);
6272}
6273
6274static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6275{
6276 struct e1000_hw *hw = &adapter->hw;
6277 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6278 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6279 u32 reg, msgbuf[3];
6280 u8 *addr = (u8 *)(&msgbuf[1]);
6281
6282 /* process all the same items cleared in a function level reset */
f2ca0dbe 6283 igb_vf_reset(adapter, vf);
4ae196df
AD		 6284
6285 /* set vf mac address */
26ad9178 6286 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6287
6288 /* enable transmit and receive for vf */
6289 reg = rd32(E1000_VFTE);
a51d8c21 6290 wr32(E1000_VFTE, reg | BIT(vf));
4ae196df 6291 reg = rd32(E1000_VFRE);
a51d8c21 6292 wr32(E1000_VFRE, reg | BIT(vf));
4ae196df 6293
8fa7e0f7 6294 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6295
6296 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6297 if (!is_zero_ether_addr(vf_mac)) {
6298 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6299 memcpy(addr, vf_mac, ETH_ALEN);
6300 } else {
6301 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6302 }
4ae196df
AD		 6303 igb_write_mbx(hw, msgbuf, 3, vf);
6304}
6305
6306static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6307{
b980ac18 6308 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6309 * starting at the second 32 bit word of the msg array
6310 */
f2ca0dbe
AD		 6311 unsigned char *addr = (char *)&msg[1];
6312 int err = -1;
4ae196df 6313
f2ca0dbe
AD		 6314 if (is_valid_ether_addr(addr))
6315 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6316
f2ca0dbe 6317 return err;
4ae196df
AD		 6318}
6319
6320static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6321{
6322 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6323 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6324 u32 msg = E1000_VT_MSGTYPE_NACK;
6325
6326 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6327 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6328 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6329 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6330 vf_data->last_nack = jiffies;
4ae196df
AD		 6331 }
6332}
6333
f2ca0dbe 6334static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6335{
f2ca0dbe
AD		 6336 struct pci_dev *pdev = adapter->pdev;
6337 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6338 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6339 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6340 s32 retval;
6341
f2ca0dbe 6342 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6343
fef45f4c
AD		 6344 if (retval) {
6345 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6346 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6347 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6348 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6349 return;
6350 goto out;
6351 }
4ae196df
AD		 6352
6353 /* this is a message we already processed, do nothing */
6354 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6355 return;
4ae196df 6356
b980ac18 6357 /* until the vf completes a reset it should not be
4ae196df
AD		 6358 * allowed to start any configuration.
6359 */
4ae196df
AD		 6360 if (msgbuf[0] == E1000_VF_RESET) {
6361 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6362 return;
4ae196df
AD		 6363 }
6364
f2ca0dbe 6365 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6366 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6367 return;
6368 retval = -1;
6369 goto out;
4ae196df
AD		 6370 }
6371
6372 switch ((msgbuf[0] & 0xFFFF)) {
6373 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6374 retval = -EINVAL;
6375 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6376 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6377 else
6378 dev_warn(&pdev->dev,
b980ac18
JK		 6379 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6380 vf);
4ae196df 6381 break;
7d5753f0
AD		 6382 case E1000_VF_SET_PROMISC:
6383 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6384 break;
4ae196df
AD		 6385 case E1000_VF_SET_MULTICAST:
6386 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6387 break;
6388 case E1000_VF_SET_LPE:
6389 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6390 break;
6391 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6392 retval = -1;
6393 if (vf_data->pf_vlan)
6394 dev_warn(&pdev->dev,
b980ac18
JK		 6395 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6396 vf);
8151d294 6397 else
a15d9259 6398 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6399 break;
6400 default:
090b1795 6401 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6402 retval = -1;
6403 break;
6404 }
6405
fef45f4c
AD		 6406 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6407out:
4ae196df
AD		 6408 /* notify the VF of the results of what it sent us */
6409 if (retval)
6410 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6411 else
6412 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6413
4ae196df 6414 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6415}
4ae196df 6416
f2ca0dbe
AD		 6417static void igb_msg_task(struct igb_adapter *adapter)
6418{
6419 struct e1000_hw *hw = &adapter->hw;
6420 u32 vf;
6421
6422 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6423 /* process any reset requests */
6424 if (!igb_check_for_rst(hw, vf))
6425 igb_vf_reset_event(adapter, vf);
6426
6427 /* process any messages pending */
6428 if (!igb_check_for_msg(hw, vf))
6429 igb_rcv_msg_from_vf(adapter, vf);
6430
6431 /* process any acks */
6432 if (!igb_check_for_ack(hw, vf))
6433 igb_rcv_ack_from_vf(adapter, vf);
6434 }
4ae196df
AD		 6435}
6436
68d480c4
AD		 6437/**
6438 * igb_set_uta - Set unicast filter table address
6439 * @adapter: board private structure
bf456abb 6440 * @set: boolean indicating if we are setting or clearing bits
68d480c4
AD		 6441 *
6442 * The unicast table address is a register array of 32-bit registers.
6443 * The table is meant to be used in a way similar to how the MTA is used
6444 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6445 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6446 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4 6447 **/
bf456abb 6448static void igb_set_uta(struct igb_adapter *adapter, bool set)
68d480c4
AD		 6449{
6450 struct e1000_hw *hw = &adapter->hw;
bf456abb 6451 u32 uta = set ? ~0 : 0;
68d480c4
AD		 6452 int i;
6453
68d480c4
AD		 6454 /* we only need to do this if VMDq is enabled */
6455 if (!adapter->vfs_allocated_count)
6456 return;
6457
bf456abb
AD		 6458 for (i = hw->mac.uta_reg_count; i--;)
6459 array_wr32(E1000_UTA, i, uta);
68d480c4
AD		 6460}
6461
9d5c8243 6462/**
b980ac18
JK		 6463 * igb_intr_msi - Interrupt Handler
6464 * @irq: interrupt number
6465 * @data: pointer to a network interface device structure
9d5c8243
AK		 6466 **/
6467static irqreturn_t igb_intr_msi(int irq, void *data)
6468{
047e0030
AD		 6469 struct igb_adapter *adapter = data;
6470 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6471 struct e1000_hw *hw = &adapter->hw;
6472 /* read ICR disables interrupts using IAM */
6473 u32 icr = rd32(E1000_ICR);
6474
047e0030 6475 igb_write_itr(q_vector);
9d5c8243 6476
7f081d40
AD		 6477 if (icr & E1000_ICR_DRSTA)
6478 schedule_work(&adapter->reset_task);
6479
047e0030 6480 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6481 /* HW is reporting DMA is out of sync */
6482 adapter->stats.doosync++;
6483 }
6484
9d5c8243
AK		 6485 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6486 hw->mac.get_link_status = 1;
6487 if (!test_bit(__IGB_DOWN, &adapter->state))
6488 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6489 }
6490
61d7f75f
RC		 6491 if (icr & E1000_ICR_TS)
6492 igb_tsync_interrupt(adapter);
1f6e8178 6493
047e0030 6494 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6495
6496 return IRQ_HANDLED;
6497}
6498
6499/**
b980ac18
JK		 6500 * igb_intr - Legacy Interrupt Handler
6501 * @irq: interrupt number
6502 * @data: pointer to a network interface device structure
9d5c8243
AK		 6503 **/
6504static irqreturn_t igb_intr(int irq, void *data)
6505{
047e0030
AD		 6506 struct igb_adapter *adapter = data;
6507 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6508 struct e1000_hw *hw = &adapter->hw;
6509 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6510 * need for the IMC write
6511 */
9d5c8243 6512 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6513
6514 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6515 * not set, then the adapter didn't send an interrupt
6516 */
9d5c8243
AK		 6517 if (!(icr & E1000_ICR_INT_ASSERTED))
6518 return IRQ_NONE;
6519
0ba82994
AD		 6520 igb_write_itr(q_vector);
6521
7f081d40
AD		 6522 if (icr & E1000_ICR_DRSTA)
6523 schedule_work(&adapter->reset_task);
6524
047e0030 6525 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6526 /* HW is reporting DMA is out of sync */
6527 adapter->stats.doosync++;
6528 }
6529
9d5c8243
AK		 6530 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6531 hw->mac.get_link_status = 1;
6532 /* guard against interrupt when we're going down */
6533 if (!test_bit(__IGB_DOWN, &adapter->state))
6534 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6535 }
6536
61d7f75f
RC		 6537 if (icr & E1000_ICR_TS)
6538 igb_tsync_interrupt(adapter);
1f6e8178 6539
047e0030 6540 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6541
6542 return IRQ_HANDLED;
6543}
6544
c50b52a0 6545static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6546{
047e0030 6547 struct igb_adapter *adapter = q_vector->adapter;
46544258 6548 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6549
0ba82994
AD		 6550 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6551 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6552 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6553 igb_set_itr(q_vector);
46544258 6554 else
047e0030 6555 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6556 }
6557
46544258 6558 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6559 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6560 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6561 else
6562 igb_irq_enable(adapter);
6563 }
9d5c8243
AK		 6564}
6565
46544258 6566/**
b980ac18
JK		 6567 * igb_poll - NAPI Rx polling callback
6568 * @napi: napi polling structure
6569 * @budget: count of how many packets we should handle
46544258
AD		 6570 **/
6571static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6572{
047e0030 6573 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6574 struct igb_q_vector,
6575 napi);
16eb8815 6576 bool clean_complete = true;
32b3e08f 6577 int work_done = 0;
9d5c8243 6578
421e02f0 6579#ifdef CONFIG_IGB_DCA
047e0030
AD		 6580 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6581 igb_update_dca(q_vector);
fe4506b6 6582#endif
0ba82994 6583 if (q_vector->tx.ring)
7f0ba845 6584 clean_complete = igb_clean_tx_irq(q_vector, budget);
9d5c8243 6585
32b3e08f
JB		 6586 if (q_vector->rx.ring) {
6587 int cleaned = igb_clean_rx_irq(q_vector, budget);
6588
6589 work_done += cleaned;
7f0ba845
AD		 6590 if (cleaned >= budget)
6591 clean_complete = false;
32b3e08f 6592 }
047e0030 6593
16eb8815
AD		 6594 /* If all work not completed, return budget and keep polling */
6595 if (!clean_complete)
6596 return budget;
46544258 6597
9d5c8243 6598 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6599 napi_complete_done(napi, work_done);
16eb8815 6600 igb_ring_irq_enable(q_vector);
9d5c8243 6601
16eb8815 6602 return 0;
9d5c8243 6603}
6d8126f9 6604
9d5c8243 6605/**
b980ac18
JK		 6606 * igb_clean_tx_irq - Reclaim resources after transmit completes
6607 * @q_vector: pointer to q_vector containing needed info
7f0ba845 6608 * @napi_budget: Used to determine if we are in netpoll
49ce9c2c 6609 *
b980ac18 6610 * returns true if ring is completely cleaned
9d5c8243 6611 **/
7f0ba845 6612static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
9d5c8243 6613{
047e0030 6614 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6615 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6616 struct igb_tx_buffer *tx_buffer;
f4128785 6617 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6618 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6619 unsigned int budget = q_vector->tx.work_limit;
8542db05 6620 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6621
13fde97a
AD		 6622 if (test_bit(__IGB_DOWN, &adapter->state))
6623 return true;
0e014cb1 6624
06034649 6625 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6626 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6627 i -= tx_ring->count;
9d5c8243 6628
f4128785
AD		 6629 do {
6630 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6631
6632 /* if next_to_watch is not set then there is no work pending */
6633 if (!eop_desc)
6634 break;
13fde97a 6635
f4128785 6636 /* prevent any other reads prior to eop_desc */
70d289bc 6637 read_barrier_depends();
f4128785 6638
13fde97a
AD		 6639 /* if DD is not set pending work has not been completed */
6640 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6641 break;
6642
8542db05
AD		 6643 /* clear next_to_watch to prevent false hangs */
6644 tx_buffer->next_to_watch = NULL;
9d5c8243 6645
ebe42d16
AD		 6646 /* update the statistics for this packet */
6647 total_bytes += tx_buffer->bytecount;
6648 total_packets += tx_buffer->gso_segs;
13fde97a 6649
ebe42d16 6650 /* free the skb */
7f0ba845 6651 napi_consume_skb(tx_buffer->skb, napi_budget);
13fde97a 6652
ebe42d16
AD		 6653 /* unmap skb header data */
6654 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6655 dma_unmap_addr(tx_buffer, dma),
6656 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6657 DMA_TO_DEVICE);
6658
c9f14bf3
AD		 6659 /* clear tx_buffer data */
6660 tx_buffer->skb = NULL;
6661 dma_unmap_len_set(tx_buffer, len, 0);
6662
ebe42d16
AD		 6663 /* clear last DMA location and unmap remaining buffers */
6664 while (tx_desc != eop_desc) {
13fde97a
AD		 6665 tx_buffer++;
6666 tx_desc++;
9d5c8243 6667 i++;
8542db05
AD		 6668 if (unlikely(!i)) {
6669 i -= tx_ring->count;
06034649 6670 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6671 tx_desc = IGB_TX_DESC(tx_ring, 0);
6672 }
ebe42d16
AD		 6673
6674 /* unmap any remaining paged data */
c9f14bf3 6675 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6676 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6677 dma_unmap_addr(tx_buffer, dma),
6678 dma_unmap_len(tx_buffer, len),
ebe42d16 6679 DMA_TO_DEVICE);
c9f14bf3 6680 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6681 }
6682 }
6683
ebe42d16
AD		 6684 /* move us one more past the eop_desc for start of next pkt */
6685 tx_buffer++;
6686 tx_desc++;
6687 i++;
6688 if (unlikely(!i)) {
6689 i -= tx_ring->count;
6690 tx_buffer = tx_ring->tx_buffer_info;
6691 tx_desc = IGB_TX_DESC(tx_ring, 0);
6692 }
f4128785
AD		 6693
6694 /* issue prefetch for next Tx descriptor */
6695 prefetch(tx_desc);
6696
6697 /* update budget accounting */
6698 budget--;
6699 } while (likely(budget));
0e014cb1 6700
bdbc0631
ED		 6701 netdev_tx_completed_queue(txring_txq(tx_ring),
6702 total_packets, total_bytes);
8542db05 6703 i += tx_ring->count;
9d5c8243 6704 tx_ring->next_to_clean = i;
13fde97a
AD		 6705 u64_stats_update_begin(&tx_ring->tx_syncp);
6706 tx_ring->tx_stats.bytes += total_bytes;
6707 tx_ring->tx_stats.packets += total_packets;
6708 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6709 q_vector->tx.total_bytes += total_bytes;
6710 q_vector->tx.total_packets += total_packets;
9d5c8243 6711
6d095fa8 6712 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6713 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6714
9d5c8243 6715 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6716 * check with the clearing of time_stamp and movement of i
6717 */
6d095fa8 6718 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6719 if (tx_buffer->next_to_watch &&
8542db05 6720 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6721 (adapter->tx_timeout_factor * HZ)) &&
6722 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6723
9d5c8243 6724 /* detected Tx unit hang */
59d71989 6725 dev_err(tx_ring->dev,
9d5c8243 6726 "Detected Tx Unit Hang\n"
2d064c06 6727 " Tx Queue <%d>\n"
9d5c8243
AK		 6728 " TDH <%x>\n"
6729 " TDT <%x>\n"
6730 " next_to_use <%x>\n"
6731 " next_to_clean <%x>\n"
9d5c8243
AK		 6732 "buffer_info[next_to_clean]\n"
6733 " time_stamp <%lx>\n"
8542db05 6734 " next_to_watch <%p>\n"
9d5c8243
AK		 6735 " jiffies <%lx>\n"
6736 " desc.status <%x>\n",
2d064c06 6737 tx_ring->queue_index,
238ac817 6738 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6739 readl(tx_ring->tail),
9d5c8243
AK		 6740 tx_ring->next_to_use,
6741 tx_ring->next_to_clean,
8542db05 6742 tx_buffer->time_stamp,
f4128785 6743 tx_buffer->next_to_watch,
9d5c8243 6744 jiffies,
f4128785 6745 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6746 netif_stop_subqueue(tx_ring->netdev,
6747 tx_ring->queue_index);
6748
6749 /* we are about to reset, no point in enabling stuff */
6750 return true;
9d5c8243
AK		 6751 }
6752 }
13fde97a 6753
21ba6fe1 6754#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6755 if (unlikely(total_packets &&
b980ac18
JK		 6756 netif_carrier_ok(tx_ring->netdev) &&
6757 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6758 /* Make sure that anybody stopping the queue after this
6759 * sees the new next_to_clean.
6760 */
6761 smp_mb();
6762 if (__netif_subqueue_stopped(tx_ring->netdev,
6763 tx_ring->queue_index) &&
6764 !(test_bit(__IGB_DOWN, &adapter->state))) {
6765 netif_wake_subqueue(tx_ring->netdev,
6766 tx_ring->queue_index);
6767
6768 u64_stats_update_begin(&tx_ring->tx_syncp);
6769 tx_ring->tx_stats.restart_queue++;
6770 u64_stats_update_end(&tx_ring->tx_syncp);
6771 }
6772 }
6773
6774 return !!budget;
9d5c8243
AK		 6775}
6776
cbc8e55f 6777/**
b980ac18
JK		 6778 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6779 * @rx_ring: rx descriptor ring to store buffers on
6780 * @old_buff: donor buffer to have page reused
cbc8e55f 6781 *
b980ac18 6782 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6783 **/
6784static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6785 struct igb_rx_buffer *old_buff)
6786{
6787 struct igb_rx_buffer *new_buff;
6788 u16 nta = rx_ring->next_to_alloc;
6789
6790 new_buff = &rx_ring->rx_buffer_info[nta];
6791
6792 /* update, and store next to alloc */
6793 nta++;
6794 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6795
6796 /* transfer page from old buffer to new buffer */
a1f63473 6797 *new_buff = *old_buff;
cbc8e55f
AD		 6798
6799 /* sync the buffer for use by the device */
6800 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6801 old_buff->page_offset,
de78d1f9 6802 IGB_RX_BUFSZ,
cbc8e55f
AD		 6803 DMA_FROM_DEVICE);
6804}
6805
95dd44b4
AD		 6806static inline bool igb_page_is_reserved(struct page *page)
6807{
2f064f34 6808 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6809}
6810
74e238ea
AD		 6811static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6812 struct page *page,
6813 unsigned int truesize)
6814{
6815 /* avoid re-using remote pages */
95dd44b4 6816 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6817 return false;
6818
74e238ea
AD		 6819#if (PAGE_SIZE < 8192)
6820 /* if we are only owner of page we can reuse it */
6821 if (unlikely(page_count(page) != 1))
6822 return false;
6823
6824 /* flip page offset to other buffer */
6825 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6826#else
6827 /* move offset up to the next cache line */
6828 rx_buffer->page_offset += truesize;
6829
6830 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6831 return false;
74e238ea
AD		 6832#endif
6833
95dd44b4
AD		 6834 /* Even if we own the page, we are not allowed to use atomic_set()
6835 * This would break get_page_unless_zero() users.
6836 */
fe896d18 6837 page_ref_inc(page);
95dd44b4 6838
74e238ea
AD		 6839 return true;
6840}
6841
cbc8e55f 6842/**
b980ac18
JK		 6843 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6844 * @rx_ring: rx descriptor ring to transact packets on
6845 * @rx_buffer: buffer containing page to add
6846 * @rx_desc: descriptor containing length of buffer written by hardware
6847 * @skb: sk_buff to place the data into
cbc8e55f 6848 *
b980ac18
JK		 6849 * This function will add the data contained in rx_buffer->page to the skb.
6850 * This is done either through a direct copy if the data in the buffer is
6851 * less than the skb header size, otherwise it will just attach the page as
6852 * a frag to the skb.
cbc8e55f 6853 *
b980ac18
JK		 6854 * The function will then update the page offset if necessary and return
6855 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6856 **/
6857static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6858 struct igb_rx_buffer *rx_buffer,
6859 union e1000_adv_rx_desc *rx_desc,
6860 struct sk_buff *skb)
6861{
6862 struct page *page = rx_buffer->page;
f56e7bba 6863 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6864 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6865#if (PAGE_SIZE < 8192)
6866 unsigned int truesize = IGB_RX_BUFSZ;
6867#else
f56e7bba 6868 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6869#endif
f56e7bba 6870 unsigned int pull_len;
cbc8e55f 6871
f56e7bba
AD		 6872 if (unlikely(skb_is_nonlinear(skb)))
6873 goto add_tail_frag;
cbc8e55f 6874
f56e7bba
AD		 6875 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6876 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6877 va += IGB_TS_HDR_LEN;
6878 size -= IGB_TS_HDR_LEN;
6879 }
cbc8e55f 6880
f56e7bba 6881 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6882 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6883
95dd44b4
AD		 6884 /* page is not reserved, we can reuse buffer as-is */
6885 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6886 return true;
6887
6888 /* this page cannot be reused so discard it */
95dd44b4 6889 __free_page(page);
cbc8e55f
AD		 6890 return false;
6891 }
6892
f56e7bba
AD		 6893 /* we need the header to contain the greater of either ETH_HLEN or
6894 * 60 bytes if the skb->len is less than 60 for skb_pad.
6895 */
6896 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6897
6898 /* align pull length to size of long to optimize memcpy performance */
6899 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6900
6901 /* update all of the pointers */
6902 va += pull_len;
6903 size -= pull_len;
6904
6905add_tail_frag:
cbc8e55f 6906 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6907 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6908
74e238ea
AD		 6909 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6910}
cbc8e55f 6911
2e334eee
AD		 6912static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6913 union e1000_adv_rx_desc *rx_desc,
6914 struct sk_buff *skb)
6915{
6916 struct igb_rx_buffer *rx_buffer;
6917 struct page *page;
6918
6919 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6920 page = rx_buffer->page;
6921 prefetchw(page);
6922
6923 if (likely(!skb)) {
6924 void *page_addr = page_address(page) +
6925 rx_buffer->page_offset;
6926
6927 /* prefetch first cache line of first page */
6928 prefetch(page_addr);
6929#if L1_CACHE_BYTES < 128
6930 prefetch(page_addr + L1_CACHE_BYTES);
6931#endif
6932
6933 /* allocate a skb to store the frags */
67fd893e 6934 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6935 if (unlikely(!skb)) {
6936 rx_ring->rx_stats.alloc_failed++;
6937 return NULL;
6938 }
6939
b980ac18 6940 /* we will be copying header into skb->data in
2e334eee
AD		 6941 * pskb_may_pull so it is in our interest to prefetch
6942 * it now to avoid a possible cache miss
6943 */
6944 prefetchw(skb->data);
6945 }
6946
6947 /* we are reusing so sync this buffer for CPU use */
6948 dma_sync_single_range_for_cpu(rx_ring->dev,
6949 rx_buffer->dma,
6950 rx_buffer->page_offset,
de78d1f9 6951 IGB_RX_BUFSZ,
2e334eee
AD		 6952 DMA_FROM_DEVICE);
6953
6954 /* pull page into skb */
6955 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6956 /* hand second half of page back to the ring */
6957 igb_reuse_rx_page(rx_ring, rx_buffer);
6958 } else {
6959 /* we are not reusing the buffer so unmap it */
6960 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6961 PAGE_SIZE, DMA_FROM_DEVICE);
6962 }
6963
6964 /* clear contents of rx_buffer */
6965 rx_buffer->page = NULL;
6966
6967 return skb;
6968}
6969
cd392f5c 6970static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6971 union e1000_adv_rx_desc *rx_desc,
6972 struct sk_buff *skb)
9d5c8243 6973{
bc8acf2c 6974 skb_checksum_none_assert(skb);
9d5c8243 6975
294e7d78 6976 /* Ignore Checksum bit is set */
3ceb90fd 6977 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6978 return;
6979
6980 /* Rx checksum disabled via ethtool */
6981 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6982 return;
85ad76b2 6983
9d5c8243 6984 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6985 if (igb_test_staterr(rx_desc,
6986 E1000_RXDEXT_STATERR_TCPE |
6987 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6988 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6989 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6990 * packets, (aka let the stack check the crc32c)
6991 */
866cff06
AD		 6992 if (!((skb->len == 60) &&
6993 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6994 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6995 ring->rx_stats.csum_err++;
12dcd86b
ED		 6996 u64_stats_update_end(&ring->rx_syncp);
6997 }
9d5c8243 6998 /* let the stack verify checksum errors */
9d5c8243
AK		 6999 return;
7000 }
7001 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 7002 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
7003 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 7004 skb->ip_summed = CHECKSUM_UNNECESSARY;
7005
3ceb90fd
AD		 7006 dev_dbg(ring->dev, "cksum success: bits %08X\n",
7007 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 7008}
7009
077887c3
AD		 7010static inline void igb_rx_hash(struct igb_ring *ring,
7011 union e1000_adv_rx_desc *rx_desc,
7012 struct sk_buff *skb)
7013{
7014 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 7015 skb_set_hash(skb,
7016 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
7017 PKT_HASH_TYPE_L3);
077887c3
AD		 7018}
7019
2e334eee 7020/**
b980ac18
JK		 7021 * igb_is_non_eop - process handling of non-EOP buffers
7022 * @rx_ring: Rx ring being processed
7023 * @rx_desc: Rx descriptor for current buffer
7024 * @skb: current socket buffer containing buffer in progress
2e334eee 7025 *
b980ac18
JK		 7026 * This function updates next to clean. If the buffer is an EOP buffer
7027 * this function exits returning false, otherwise it will place the
7028 * sk_buff in the next buffer to be chained and return true indicating
7029 * that this is in fact a non-EOP buffer.
2e334eee
AD		 7030 **/
7031static bool igb_is_non_eop(struct igb_ring *rx_ring,
7032 union e1000_adv_rx_desc *rx_desc)
7033{
7034 u32 ntc = rx_ring->next_to_clean + 1;
7035
7036 /* fetch, update, and store next to clean */
7037 ntc = (ntc < rx_ring->count) ? ntc : 0;
7038 rx_ring->next_to_clean = ntc;
7039
7040 prefetch(IGB_RX_DESC(rx_ring, ntc));
7041
7042 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
7043 return false;
7044
7045 return true;
7046}
7047
1a1c225b 7048/**
b980ac18
JK		 7049 * igb_cleanup_headers - Correct corrupted or empty headers
7050 * @rx_ring: rx descriptor ring packet is being transacted on
7051 * @rx_desc: pointer to the EOP Rx descriptor
7052 * @skb: pointer to current skb being fixed
1a1c225b 7053 *
b980ac18
JK		 7054 * Address the case where we are pulling data in on pages only
7055 * and as such no data is present in the skb header.
1a1c225b 7056 *
b980ac18
JK		 7057 * In addition if skb is not at least 60 bytes we need to pad it so that
7058 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 7059 *
b980ac18 7060 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 7061 **/
7062static bool igb_cleanup_headers(struct igb_ring *rx_ring,
7063 union e1000_adv_rx_desc *rx_desc,
7064 struct sk_buff *skb)
7065{
1a1c225b
AD		 7066 if (unlikely((igb_test_staterr(rx_desc,
7067 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
7068 struct net_device *netdev = rx_ring->netdev;
7069 if (!(netdev->features & NETIF_F_RXALL)) {
7070 dev_kfree_skb_any(skb);
7071 return true;
7072 }
7073 }
7074
a94d9e22
AD		 7075 /* if eth_skb_pad returns an error the skb was freed */
7076 if (eth_skb_pad(skb))
7077 return true;
1a1c225b
AD		 7078
7079 return false;
2d94d8ab
AD		 7080}
7081
db2ee5bd 7082/**
b980ac18
JK		 7083 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7084 * @rx_ring: rx descriptor ring packet is being transacted on
7085 * @rx_desc: pointer to the EOP Rx descriptor
7086 * @skb: pointer to current skb being populated
db2ee5bd 7087 *
b980ac18
JK		 7088 * This function checks the ring, descriptor, and packet information in
7089 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7090 * other fields within the skb.
db2ee5bd
AD		 7091 **/
7092static void igb_process_skb_fields(struct igb_ring *rx_ring,
7093 union e1000_adv_rx_desc *rx_desc,
7094 struct sk_buff *skb)
7095{
7096 struct net_device *dev = rx_ring->netdev;
7097
7098 igb_rx_hash(rx_ring, rx_desc, skb);
7099
7100 igb_rx_checksum(rx_ring, rx_desc, skb);
7101
5499a968
JK		 7102 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7103 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7104 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 7105
f646968f 7106 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 7107 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7108 u16 vid;
9005df38 7109
db2ee5bd
AD		 7110 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7111 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7112 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7113 else
7114 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7115
86a9bad3 7116 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7117 }
7118
7119 skb_record_rx_queue(skb, rx_ring->queue_index);
7120
7121 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7122}
7123
32b3e08f 7124static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7125{
0ba82994 7126 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7127 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7128 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7129 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7130
57ba34c9 7131 while (likely(total_packets < budget)) {
2e334eee 7132 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7133
2e334eee
AD		 7134 /* return some buffers to hardware, one at a time is too slow */
7135 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7136 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7137 cleaned_count = 0;
7138 }
bf36c1a0 7139
2e334eee 7140 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7141
124b74c1 7142 if (!rx_desc->wb.upper.status_error)
2e334eee 7143 break;
9d5c8243 7144
74e238ea
AD		 7145 /* This memory barrier is needed to keep us from reading
7146 * any other fields out of the rx_desc until we know the
124b74c1 7147 * descriptor has been written back
74e238ea 7148 */
124b74c1 7149 dma_rmb();
74e238ea 7150
2e334eee 7151 /* retrieve a buffer from the ring */
f9d40f6a 7152 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7153
2e334eee
AD		 7154 /* exit if we failed to retrieve a buffer */
7155 if (!skb)
7156 break;
1a1c225b 7157
2e334eee 7158 cleaned_count++;
1a1c225b 7159
2e334eee
AD		 7160 /* fetch next buffer in frame if non-eop */
7161 if (igb_is_non_eop(rx_ring, rx_desc))
7162 continue;
1a1c225b
AD		 7163
7164 /* verify the packet layout is correct */
7165 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7166 skb = NULL;
7167 continue;
9d5c8243 7168 }
9d5c8243 7169
db2ee5bd 7170 /* probably a little skewed due to removing CRC */
3ceb90fd 7171 total_bytes += skb->len;
3ceb90fd 7172
db2ee5bd
AD		 7173 /* populate checksum, timestamp, VLAN, and protocol */
7174 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7175
b2cb09b1 7176 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7177
1a1c225b
AD		 7178 /* reset skb pointer */
7179 skb = NULL;
7180
2e334eee
AD		 7181 /* update budget accounting */
7182 total_packets++;
57ba34c9 7183 }
bf36c1a0 7184
1a1c225b
AD		 7185 /* place incomplete frames back on ring for completion */
7186 rx_ring->skb = skb;
7187
12dcd86b 7188 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7189 rx_ring->rx_stats.packets += total_packets;
7190 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7191 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7192 q_vector->rx.total_packets += total_packets;
7193 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7194
7195 if (cleaned_count)
cd392f5c 7196 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7197
32b3e08f 7198 return total_packets;
9d5c8243
AK		 7199}
7200
c023cd88 7201static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7202 struct igb_rx_buffer *bi)
c023cd88
AD		 7203{
7204 struct page *page = bi->page;
cbc8e55f 7205 dma_addr_t dma;
c023cd88 7206
cbc8e55f
AD		 7207 /* since we are recycling buffers we should seldom need to alloc */
7208 if (likely(page))
c023cd88
AD		 7209 return true;
7210
cbc8e55f 7211 /* alloc new page for storage */
42b17f09 7212 page = dev_alloc_page();
cbc8e55f
AD		 7213 if (unlikely(!page)) {
7214 rx_ring->rx_stats.alloc_failed++;
7215 return false;
c023cd88
AD		 7216 }
7217
cbc8e55f
AD		 7218 /* map page for use */
7219 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7220
b980ac18 7221 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7222 * there isn't much point in holding memory we can't use
7223 */
1a1c225b 7224 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7225 __free_page(page);
7226
c023cd88
AD		 7227 rx_ring->rx_stats.alloc_failed++;
7228 return false;
7229 }
7230
1a1c225b 7231 bi->dma = dma;
cbc8e55f
AD		 7232 bi->page = page;
7233 bi->page_offset = 0;
1a1c225b 7234
c023cd88
AD		 7235 return true;
7236}
7237
9d5c8243 7238/**
b980ac18
JK		 7239 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7240 * @adapter: address of board private structure
9d5c8243 7241 **/
cd392f5c 7242void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7243{
9d5c8243 7244 union e1000_adv_rx_desc *rx_desc;
06034649 7245 struct igb_rx_buffer *bi;
c023cd88 7246 u16 i = rx_ring->next_to_use;
9d5c8243 7247
cbc8e55f
AD		 7248 /* nothing to do */
7249 if (!cleaned_count)
7250 return;
7251
60136906 7252 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7253 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7254 i -= rx_ring->count;
9d5c8243 7255
cbc8e55f 7256 do {
1a1c225b 7257 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7258 break;
9d5c8243 7259
b980ac18 7260 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7261 * because each write-back erases this info.
7262 */
f9d40f6a 7263 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7264
c023cd88
AD		 7265 rx_desc++;
7266 bi++;
9d5c8243 7267 i++;
c023cd88 7268 if (unlikely(!i)) {
60136906 7269 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7270 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7271 i -= rx_ring->count;
7272 }
7273
95dd44b4
AD		 7274 /* clear the status bits for the next_to_use descriptor */
7275 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7276
7277 cleaned_count--;
7278 } while (cleaned_count);
9d5c8243 7279
c023cd88
AD		 7280 i += rx_ring->count;
7281
9d5c8243 7282 if (rx_ring->next_to_use != i) {
cbc8e55f 7283 /* record the next descriptor to use */
9d5c8243 7284 rx_ring->next_to_use = i;
9d5c8243 7285
cbc8e55f
AD		 7286 /* update next to alloc since we have filled the ring */
7287 rx_ring->next_to_alloc = i;
7288
b980ac18 7289 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7290 * know there are new descriptors to fetch. (Only
7291 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7292 * such as IA-64).
7293 */
9d5c8243 7294 wmb();
fce99e34 7295 writel(i, rx_ring->tail);
9d5c8243
AK		 7296 }
7297}
7298
7299/**
7300 * igb_mii_ioctl -
7301 * @netdev:
7302 * @ifreq:
7303 * @cmd:
7304 **/
7305static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7306{
7307 struct igb_adapter *adapter = netdev_priv(netdev);
7308 struct mii_ioctl_data *data = if_mii(ifr);
7309
7310 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7311 return -EOPNOTSUPP;
7312
7313 switch (cmd) {
7314 case SIOCGMIIPHY:
7315 data->phy_id = adapter->hw.phy.addr;
7316 break;
7317 case SIOCGMIIREG:
f5f4cf08 7318 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7319 &data->val_out))
9d5c8243
AK		 7320 return -EIO;
7321 break;
7322 case SIOCSMIIREG:
7323 default:
7324 return -EOPNOTSUPP;
7325 }
7326 return 0;
7327}
7328
7329/**
7330 * igb_ioctl -
7331 * @netdev:
7332 * @ifreq:
7333 * @cmd:
7334 **/
7335static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7336{
7337 switch (cmd) {
7338 case SIOCGMIIPHY:
7339 case SIOCGMIIREG:
7340 case SIOCSMIIREG:
7341 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7342 case SIOCGHWTSTAMP:
7343 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7344 case SIOCSHWTSTAMP:
6ab5f7b2 7345 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7346 default:
7347 return -EOPNOTSUPP;
7348 }
7349}
7350
94826487
TF		 7351void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7352{
7353 struct igb_adapter *adapter = hw->back;
7354
7355 pci_read_config_word(adapter->pdev, reg, value);
7356}
7357
7358void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7359{
7360 struct igb_adapter *adapter = hw->back;
7361
7362 pci_write_config_word(adapter->pdev, reg, *value);
7363}
7364
009bc06e
AD		 7365s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7366{
7367 struct igb_adapter *adapter = hw->back;
009bc06e 7368
23d028cc 7369 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7370 return -E1000_ERR_CONFIG;
7371
009bc06e
AD		 7372 return 0;
7373}
7374
7375s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7376{
7377 struct igb_adapter *adapter = hw->back;
009bc06e 7378
23d028cc 7379 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7380 return -E1000_ERR_CONFIG;
7381
009bc06e
AD		 7382 return 0;
7383}
7384
c8f44aff 7385static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7386{
7387 struct igb_adapter *adapter = netdev_priv(netdev);
7388 struct e1000_hw *hw = &adapter->hw;
7389 u32 ctrl, rctl;
f646968f 7390 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7391
5faf030c 7392 if (enable) {
9d5c8243
AK		 7393 /* enable VLAN tag insert/strip */
7394 ctrl = rd32(E1000_CTRL);
7395 ctrl |= E1000_CTRL_VME;
7396 wr32(E1000_CTRL, ctrl);
7397
51466239 7398 /* Disable CFI check */
9d5c8243 7399 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7400 rctl &= ~E1000_RCTL_CFIEN;
7401 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7402 } else {
7403 /* disable VLAN tag insert/strip */
7404 ctrl = rd32(E1000_CTRL);
7405 ctrl &= ~E1000_CTRL_VME;
7406 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7407 }
7408
030f9f52 7409 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9d5c8243
AK		 7410}
7411
80d5c368
PM		 7412static int igb_vlan_rx_add_vid(struct net_device *netdev,
7413 __be16 proto, u16 vid)
9d5c8243
AK		 7414{
7415 struct igb_adapter *adapter = netdev_priv(netdev);
7416 struct e1000_hw *hw = &adapter->hw;
4ae196df 7417 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7418
51466239 7419 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7420 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7421 igb_vfta_set(hw, vid, pf_id, true, !!vid);
b2cb09b1
JP		 7422
7423 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7424
7425 return 0;
9d5c8243
AK		 7426}
7427
80d5c368
PM		 7428static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7429 __be16 proto, u16 vid)
9d5c8243
AK		 7430{
7431 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7432 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7433 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7434
8b77c6b2 7435 /* remove VID from filter table */
16903caa
AD		 7436 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7437 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7438
7439 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7440
7441 return 0;
9d5c8243
AK		 7442}
7443
7444static void igb_restore_vlan(struct igb_adapter *adapter)
7445{
5982a556 7446 u16 vid = 1;
9d5c8243 7447
5faf030c 7448 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7449 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7450
5982a556 7451 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7452 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7453}
7454
14ad2513 7455int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7456{
090b1795 7457 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7458 struct e1000_mac_info *mac = &adapter->hw.mac;
7459
7460 mac->autoneg = 0;
7461
14ad2513 7462 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7463 * for the switch() below to work
7464 */
14ad2513
DD		 7465 if ((spd & 1) || (dplx & ~1))
7466 goto err_inval;
7467
f502ef7d
AA		 7468 /* Fiber NIC's only allow 1000 gbps Full duplex
7469 * and 100Mbps Full duplex for 100baseFx sfp
7470 */
7471 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7472 switch (spd + dplx) {
7473 case SPEED_10 + DUPLEX_HALF:
7474 case SPEED_10 + DUPLEX_FULL:
7475 case SPEED_100 + DUPLEX_HALF:
7476 goto err_inval;
7477 default:
7478 break;
7479 }
7480 }
cd2638a8 7481
14ad2513 7482 switch (spd + dplx) {
9d5c8243
AK		 7483 case SPEED_10 + DUPLEX_HALF:
7484 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7485 break;
7486 case SPEED_10 + DUPLEX_FULL:
7487 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7488 break;
7489 case SPEED_100 + DUPLEX_HALF:
7490 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7491 break;
7492 case SPEED_100 + DUPLEX_FULL:
7493 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7494 break;
7495 case SPEED_1000 + DUPLEX_FULL:
7496 mac->autoneg = 1;
7497 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7498 break;
7499 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7500 default:
14ad2513 7501 goto err_inval;
9d5c8243 7502 }
8376dad0
JB		 7503
7504 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7505 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7506
9d5c8243 7507 return 0;
14ad2513
DD		 7508
7509err_inval:
7510 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7511 return -EINVAL;
9d5c8243
AK		 7512}
7513
749ab2cd
YZ		 7514static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7515 bool runtime)
9d5c8243
AK		 7516{
7517 struct net_device *netdev = pci_get_drvdata(pdev);
7518 struct igb_adapter *adapter = netdev_priv(netdev);
7519 struct e1000_hw *hw = &adapter->hw;
2d064c06 7520 u32 ctrl, rctl, status;
749ab2cd 7521 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7522#ifdef CONFIG_PM
7523 int retval = 0;
7524#endif
7525
7526 netif_device_detach(netdev);
7527
a88f10ec 7528 if (netif_running(netdev))
749ab2cd 7529 __igb_close(netdev, true);
a88f10ec 7530
047e0030 7531 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7532
7533#ifdef CONFIG_PM
7534 retval = pci_save_state(pdev);
7535 if (retval)
7536 return retval;
7537#endif
7538
7539 status = rd32(E1000_STATUS);
7540 if (status & E1000_STATUS_LU)
7541 wufc &= ~E1000_WUFC_LNKC;
7542
7543 if (wufc) {
7544 igb_setup_rctl(adapter);
ff41f8dc 7545 igb_set_rx_mode(netdev);
9d5c8243
AK		 7546
7547 /* turn on all-multi mode if wake on multicast is enabled */
7548 if (wufc & E1000_WUFC_MC) {
7549 rctl = rd32(E1000_RCTL);
7550 rctl |= E1000_RCTL_MPE;
7551 wr32(E1000_RCTL, rctl);
7552 }
7553
7554 ctrl = rd32(E1000_CTRL);
7555 /* advertise wake from D3Cold */
7556 #define E1000_CTRL_ADVD3WUC 0x00100000
7557 /* phy power management enable */
7558 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7559 ctrl |= E1000_CTRL_ADVD3WUC;
7560 wr32(E1000_CTRL, ctrl);
7561
9d5c8243 7562 /* Allow time for pending master requests to run */
330a6d6a 7563 igb_disable_pcie_master(hw);
9d5c8243
AK		 7564
7565 wr32(E1000_WUC, E1000_WUC_PME_EN);
7566 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7567 } else {
7568 wr32(E1000_WUC, 0);
7569 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7570 }
7571
3fe7c4c9
RW		 7572 *enable_wake = wufc || adapter->en_mng_pt;
7573 if (!*enable_wake)
88a268c1
NN		 7574 igb_power_down_link(adapter);
7575 else
7576 igb_power_up_link(adapter);
9d5c8243
AK		 7577
7578 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7579 * would have already happened in close and is redundant.
7580 */
9d5c8243
AK		 7581 igb_release_hw_control(adapter);
7582
7583 pci_disable_device(pdev);
7584
9d5c8243
AK		 7585 return 0;
7586}
7587
7588#ifdef CONFIG_PM
d9dd966d 7589#ifdef CONFIG_PM_SLEEP
749ab2cd 7590static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7591{
7592 int retval;
7593 bool wake;
749ab2cd 7594 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7595
749ab2cd 7596 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7597 if (retval)
7598 return retval;
7599
7600 if (wake) {
7601 pci_prepare_to_sleep(pdev);
7602 } else {
7603 pci_wake_from_d3(pdev, false);
7604 pci_set_power_state(pdev, PCI_D3hot);
7605 }
7606
7607 return 0;
7608}
d9dd966d 7609#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7610
749ab2cd 7611static int igb_resume(struct device *dev)
9d5c8243 7612{
749ab2cd 7613 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7614 struct net_device *netdev = pci_get_drvdata(pdev);
7615 struct igb_adapter *adapter = netdev_priv(netdev);
7616 struct e1000_hw *hw = &adapter->hw;
7617 u32 err;
7618
7619 pci_set_power_state(pdev, PCI_D0);
7620 pci_restore_state(pdev);
b94f2d77 7621 pci_save_state(pdev);
42bfd33a 7622
17a402a0
CW		 7623 if (!pci_device_is_present(pdev))
7624 return -ENODEV;
aed5dec3 7625 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7626 if (err) {
7627 dev_err(&pdev->dev,
7628 "igb: Cannot enable PCI device from suspend\n");
7629 return err;
7630 }
7631 pci_set_master(pdev);
7632
7633 pci_enable_wake(pdev, PCI_D3hot, 0);
7634 pci_enable_wake(pdev, PCI_D3cold, 0);
7635
53c7d064 7636 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7637 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7638 return -ENOMEM;
9d5c8243
AK		 7639 }
7640
9d5c8243 7641 igb_reset(adapter);
a8564f03
AD		 7642
7643 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7644 * driver.
7645 */
a8564f03
AD		 7646 igb_get_hw_control(adapter);
7647
9d5c8243
AK		 7648 wr32(E1000_WUS, ~0);
7649
749ab2cd 7650 if (netdev->flags & IFF_UP) {
0c2cc02e 7651 rtnl_lock();
749ab2cd 7652 err = __igb_open(netdev, true);
0c2cc02e 7653 rtnl_unlock();
a88f10ec
AD		 7654 if (err)
7655 return err;
7656 }
9d5c8243
AK		 7657
7658 netif_device_attach(netdev);
749ab2cd
YZ		 7659 return 0;
7660}
7661
749ab2cd
YZ		 7662static int igb_runtime_idle(struct device *dev)
7663{
7664 struct pci_dev *pdev = to_pci_dev(dev);
7665 struct net_device *netdev = pci_get_drvdata(pdev);
7666 struct igb_adapter *adapter = netdev_priv(netdev);
7667
7668 if (!igb_has_link(adapter))
7669 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7670
7671 return -EBUSY;
7672}
7673
7674static int igb_runtime_suspend(struct device *dev)
7675{
7676 struct pci_dev *pdev = to_pci_dev(dev);
7677 int retval;
7678 bool wake;
7679
7680 retval = __igb_shutdown(pdev, &wake, 1);
7681 if (retval)
7682 return retval;
7683
7684 if (wake) {
7685 pci_prepare_to_sleep(pdev);
7686 } else {
7687 pci_wake_from_d3(pdev, false);
7688 pci_set_power_state(pdev, PCI_D3hot);
7689 }
9d5c8243 7690
9d5c8243
AK		 7691 return 0;
7692}
749ab2cd
YZ		 7693
7694static int igb_runtime_resume(struct device *dev)
7695{
7696 return igb_resume(dev);
7697}
d61c81cb 7698#endif /* CONFIG_PM */
9d5c8243
AK		 7699
7700static void igb_shutdown(struct pci_dev *pdev)
7701{
3fe7c4c9
RW		 7702 bool wake;
7703
749ab2cd 7704 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7705
7706 if (system_state == SYSTEM_POWER_OFF) {
7707 pci_wake_from_d3(pdev, wake);
7708 pci_set_power_state(pdev, PCI_D3hot);
7709 }
9d5c8243
AK		 7710}
7711
fa44f2f1
GR		 7712#ifdef CONFIG_PCI_IOV
7713static int igb_sriov_reinit(struct pci_dev *dev)
7714{
7715 struct net_device *netdev = pci_get_drvdata(dev);
7716 struct igb_adapter *adapter = netdev_priv(netdev);
7717 struct pci_dev *pdev = adapter->pdev;
7718
7719 rtnl_lock();
7720
7721 if (netif_running(netdev))
7722 igb_close(netdev);
76252723
SA		 7723 else
7724 igb_reset(adapter);
fa44f2f1
GR		 7725
7726 igb_clear_interrupt_scheme(adapter);
7727
7728 igb_init_queue_configuration(adapter);
7729
7730 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7731 rtnl_unlock();
fa44f2f1
GR		 7732 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7733 return -ENOMEM;
7734 }
7735
7736 if (netif_running(netdev))
7737 igb_open(netdev);
7738
7739 rtnl_unlock();
7740
7741 return 0;
7742}
7743
7744static int igb_pci_disable_sriov(struct pci_dev *dev)
7745{
7746 int err = igb_disable_sriov(dev);
7747
7748 if (!err)
7749 err = igb_sriov_reinit(dev);
7750
7751 return err;
7752}
7753
7754static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7755{
7756 int err = igb_enable_sriov(dev, num_vfs);
7757
7758 if (err)
7759 goto out;
7760
7761 err = igb_sriov_reinit(dev);
7762 if (!err)
7763 return num_vfs;
7764
7765out:
7766 return err;
7767}
7768
7769#endif
7770static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7771{
7772#ifdef CONFIG_PCI_IOV
7773 if (num_vfs == 0)
7774 return igb_pci_disable_sriov(dev);
7775 else
7776 return igb_pci_enable_sriov(dev, num_vfs);
7777#endif
7778 return 0;
7779}
7780
9d5c8243 7781#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7782/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7783 * without having to re-enable interrupts. It's not called while
7784 * the interrupt routine is executing.
7785 */
7786static void igb_netpoll(struct net_device *netdev)
7787{
7788 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7789 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7790 struct igb_q_vector *q_vector;
9d5c8243 7791 int i;
9d5c8243 7792
047e0030 7793 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7794 q_vector = adapter->q_vector[i];
cd14ef54 7795 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7796 wr32(E1000_EIMC, q_vector->eims_value);
7797 else
7798 igb_irq_disable(adapter);
047e0030 7799 napi_schedule(&q_vector->napi);
eebbbdba 7800 }
9d5c8243
AK		 7801}
7802#endif /* CONFIG_NET_POLL_CONTROLLER */
7803
7804/**
b980ac18
JK		 7805 * igb_io_error_detected - called when PCI error is detected
7806 * @pdev: Pointer to PCI device
7807 * @state: The current pci connection state
9d5c8243 7808 *
b980ac18
JK		 7809 * This function is called after a PCI bus error affecting
7810 * this device has been detected.
7811 **/
9d5c8243
AK		 7812static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7813 pci_channel_state_t state)
7814{
7815 struct net_device *netdev = pci_get_drvdata(pdev);
7816 struct igb_adapter *adapter = netdev_priv(netdev);
7817
7818 netif_device_detach(netdev);
7819
59ed6eec
AD		 7820 if (state == pci_channel_io_perm_failure)
7821 return PCI_ERS_RESULT_DISCONNECT;
7822
9d5c8243
AK		 7823 if (netif_running(netdev))
7824 igb_down(adapter);
7825 pci_disable_device(pdev);
7826
7827 /* Request a slot slot reset. */
7828 return PCI_ERS_RESULT_NEED_RESET;
7829}
7830
7831/**
b980ac18
JK		 7832 * igb_io_slot_reset - called after the pci bus has been reset.
7833 * @pdev: Pointer to PCI device
9d5c8243 7834 *
b980ac18
JK		 7835 * Restart the card from scratch, as if from a cold-boot. Implementation
7836 * resembles the first-half of the igb_resume routine.
7837 **/
9d5c8243
AK		 7838static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7839{
7840 struct net_device *netdev = pci_get_drvdata(pdev);
7841 struct igb_adapter *adapter = netdev_priv(netdev);
7842 struct e1000_hw *hw = &adapter->hw;
40a914fa 7843 pci_ers_result_t result;
42bfd33a 7844 int err;
9d5c8243 7845
aed5dec3 7846 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7847 dev_err(&pdev->dev,
7848 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7849 result = PCI_ERS_RESULT_DISCONNECT;
7850 } else {
7851 pci_set_master(pdev);
7852 pci_restore_state(pdev);
b94f2d77 7853 pci_save_state(pdev);
9d5c8243 7854
40a914fa
AD		 7855 pci_enable_wake(pdev, PCI_D3hot, 0);
7856 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7857
40a914fa
AD		 7858 igb_reset(adapter);
7859 wr32(E1000_WUS, ~0);
7860 result = PCI_ERS_RESULT_RECOVERED;
7861 }
9d5c8243 7862
ea943d41
JK		 7863 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7864 if (err) {
b980ac18
JK		 7865 dev_err(&pdev->dev,
7866 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7867 err);
ea943d41
JK		 7868 /* non-fatal, continue */
7869 }
40a914fa
AD		 7870
7871 return result;
9d5c8243
AK		 7872}
7873
7874/**
b980ac18
JK		 7875 * igb_io_resume - called when traffic can start flowing again.
7876 * @pdev: Pointer to PCI device
9d5c8243 7877 *
b980ac18
JK		 7878 * This callback is called when the error recovery driver tells us that
7879 * its OK to resume normal operation. Implementation resembles the
7880 * second-half of the igb_resume routine.
9d5c8243
AK		 7881 */
7882static void igb_io_resume(struct pci_dev *pdev)
7883{
7884 struct net_device *netdev = pci_get_drvdata(pdev);
7885 struct igb_adapter *adapter = netdev_priv(netdev);
7886
9d5c8243
AK		 7887 if (netif_running(netdev)) {
7888 if (igb_up(adapter)) {
7889 dev_err(&pdev->dev, "igb_up failed after reset\n");
7890 return;
7891 }
7892 }
7893
7894 netif_device_attach(netdev);
7895
7896 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7897 * driver.
7898 */
9d5c8243 7899 igb_get_hw_control(adapter);
9d5c8243
AK		 7900}
7901
26ad9178 7902static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7903 u8 qsel)
26ad9178 7904{
26ad9178 7905 struct e1000_hw *hw = &adapter->hw;
c3278587 7906 u32 rar_low, rar_high;
26ad9178 7907
415cd2a6
AD		 7908 /* HW expects these to be in network order when they are plugged
7909 * into the registers which are little endian. In order to guarantee
7910 * that ordering we need to do an leXX_to_cpup here in order to be
7911 * ready for the byteswap that occurs with writel
26ad9178 7912 */
415cd2a6
AD		 7913 rar_low = le32_to_cpup((__le32 *)(addr));
7914 rar_high = le16_to_cpup((__le16 *)(addr + 4));
26ad9178
AD		 7915
7916 /* Indicate to hardware the Address is Valid. */
7917 rar_high |= E1000_RAH_AV;
7918
7919 if (hw->mac.type == e1000_82575)
7920 rar_high |= E1000_RAH_POOL_1 * qsel;
7921 else
7922 rar_high |= E1000_RAH_POOL_1 << qsel;
7923
7924 wr32(E1000_RAL(index), rar_low);
7925 wrfl();
7926 wr32(E1000_RAH(index), rar_high);
7927 wrfl();
7928}
7929
4ae196df 7930static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7931 int vf, unsigned char *mac_addr)
4ae196df
AD		 7932{
7933 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7934 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7935 * towards the first, as a result a collision should not be possible
7936 */
ff41f8dc 7937 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7938
37680117 7939 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7940
26ad9178 7941 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7942
7943 return 0;
7944}
7945
8151d294
WM		 7946static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7947{
7948 struct igb_adapter *adapter = netdev_priv(netdev);
7949 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7950 return -EINVAL;
7951 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7952 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7953 dev_info(&adapter->pdev->dev,
7954 "Reload the VF driver to make this change effective.");
8151d294 7955 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7956 dev_warn(&adapter->pdev->dev,
7957 "The VF MAC address has been set, but the PF device is not up.\n");
7958 dev_warn(&adapter->pdev->dev,
7959 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7960 }
7961 return igb_set_vf_mac(adapter, vf, mac);
7962}
7963
17dc566c
LL		 7964static int igb_link_mbps(int internal_link_speed)
7965{
7966 switch (internal_link_speed) {
7967 case SPEED_100:
7968 return 100;
7969 case SPEED_1000:
7970 return 1000;
7971 default:
7972 return 0;
7973 }
7974}
7975
7976static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7977 int link_speed)
7978{
7979 int rf_dec, rf_int;
7980 u32 bcnrc_val;
7981
7982 if (tx_rate != 0) {
7983 /* Calculate the rate factor values to set */
7984 rf_int = link_speed / tx_rate;
7985 rf_dec = (link_speed - (rf_int * tx_rate));
a51d8c21 7986 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
b980ac18 7987 tx_rate;
17dc566c
LL		 7988
7989 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7990 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7991 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7992 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7993 } else {
7994 bcnrc_val = 0;
7995 }
7996
7997 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7998 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7999 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
8000 */
8001 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 8002 wr32(E1000_RTTBCNRC, bcnrc_val);
8003}
8004
8005static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
8006{
8007 int actual_link_speed, i;
8008 bool reset_rate = false;
8009
8010 /* VF TX rate limit was not set or not supported */
8011 if ((adapter->vf_rate_link_speed == 0) ||
8012 (adapter->hw.mac.type != e1000_82576))
8013 return;
8014
8015 actual_link_speed = igb_link_mbps(adapter->link_speed);
8016 if (actual_link_speed != adapter->vf_rate_link_speed) {
8017 reset_rate = true;
8018 adapter->vf_rate_link_speed = 0;
8019 dev_info(&adapter->pdev->dev,
b980ac18 8020 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 8021 }
8022
8023 for (i = 0; i < adapter->vfs_allocated_count; i++) {
8024 if (reset_rate)
8025 adapter->vf_data[i].tx_rate = 0;
8026
8027 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 8028 adapter->vf_data[i].tx_rate,
8029 actual_link_speed);
17dc566c
LL		 8030 }
8031}
8032
ed616689
SC		 8033static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
8034 int min_tx_rate, int max_tx_rate)
8151d294 8035{
17dc566c
LL		 8036 struct igb_adapter *adapter = netdev_priv(netdev);
8037 struct e1000_hw *hw = &adapter->hw;
8038 int actual_link_speed;
8039
8040 if (hw->mac.type != e1000_82576)
8041 return -EOPNOTSUPP;
8042
ed616689
SC		 8043 if (min_tx_rate)
8044 return -EINVAL;
8045
17dc566c
LL		 8046 actual_link_speed = igb_link_mbps(adapter->link_speed);
8047 if ((vf >= adapter->vfs_allocated_count) ||
8048 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 8049 (max_tx_rate < 0) ||
8050 (max_tx_rate > actual_link_speed))
17dc566c
LL		 8051 return -EINVAL;
8052
8053 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 8054 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
8055 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 8056
8057 return 0;
8151d294
WM		 8058}
8059
70ea4783
LL		 8060static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8061 bool setting)
8062{
8063 struct igb_adapter *adapter = netdev_priv(netdev);
8064 struct e1000_hw *hw = &adapter->hw;
8065 u32 reg_val, reg_offset;
8066
8067 if (!adapter->vfs_allocated_count)
8068 return -EOPNOTSUPP;
8069
8070 if (vf >= adapter->vfs_allocated_count)
8071 return -EINVAL;
8072
8073 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8074 reg_val = rd32(reg_offset);
8075 if (setting)
a51d8c21
JK		 8076 reg_val |= (BIT(vf) |
8077 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
70ea4783 8078 else
a51d8c21
JK		 8079 reg_val &= ~(BIT(vf) |
8080 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
70ea4783
LL		 8081 wr32(reg_offset, reg_val);
8082
8083 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 8084 return 0;
70ea4783
LL		 8085}
8086
8151d294
WM		 8087static int igb_ndo_get_vf_config(struct net_device *netdev,
8088 int vf, struct ifla_vf_info *ivi)
8089{
8090 struct igb_adapter *adapter = netdev_priv(netdev);
8091 if (vf >= adapter->vfs_allocated_count)
8092 return -EINVAL;
8093 ivi->vf = vf;
8094 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 8095 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8096 ivi->min_tx_rate = 0;
8151d294
WM		 8097 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8098 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 8099 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 8100 return 0;
8101}
8102
4ae196df
AD		 8103static void igb_vmm_control(struct igb_adapter *adapter)
8104{
8105 struct e1000_hw *hw = &adapter->hw;
10d8e907 8106 u32 reg;
4ae196df 8107
52a1dd4d
AD		 8108 switch (hw->mac.type) {
8109 case e1000_82575:
f96a8a0b
CW		 8110 case e1000_i210:
8111 case e1000_i211:
ceb5f13b 8112 case e1000_i354:
52a1dd4d
AD		 8113 default:
8114 /* replication is not supported for 82575 */
4ae196df 8115 return;
52a1dd4d
AD		 8116 case e1000_82576:
8117 /* notify HW that the MAC is adding vlan tags */
8118 reg = rd32(E1000_DTXCTL);
8119 reg |= E1000_DTXCTL_VLAN_ADDED;
8120 wr32(E1000_DTXCTL, reg);
b26141d4 8121 /* Fall through */
52a1dd4d
AD		 8122 case e1000_82580:
8123 /* enable replication vlan tag stripping */
8124 reg = rd32(E1000_RPLOLR);
8125 reg |= E1000_RPLOLR_STRVLAN;
8126 wr32(E1000_RPLOLR, reg);
b26141d4 8127 /* Fall through */
d2ba2ed8
AD		 8128 case e1000_i350:
8129 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8130 break;
8131 }
10d8e907 8132
d4960307
AD		 8133 if (adapter->vfs_allocated_count) {
8134 igb_vmdq_set_loopback_pf(hw, true);
8135 igb_vmdq_set_replication_pf(hw, true);
13800469 8136 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8137 adapter->vfs_allocated_count);
d4960307
AD		 8138 } else {
8139 igb_vmdq_set_loopback_pf(hw, false);
8140 igb_vmdq_set_replication_pf(hw, false);
8141 }
4ae196df
AD		 8142}
8143
b6e0c419
CW		 8144static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8145{
8146 struct e1000_hw *hw = &adapter->hw;
8147 u32 dmac_thr;
8148 u16 hwm;
8149
8150 if (hw->mac.type > e1000_82580) {
8151 if (adapter->flags & IGB_FLAG_DMAC) {
8152 u32 reg;
8153
8154 /* force threshold to 0. */
8155 wr32(E1000_DMCTXTH, 0);
8156
b980ac18 8157 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8158 * than the Rx threshold. Set hwm to PBA - max frame
8159 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8160 */
45693bcb 8161 hwm = 64 * (pba - 6);
e8c626e9
MV		 8162 reg = rd32(E1000_FCRTC);
8163 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8164 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8165 & E1000_FCRTC_RTH_COAL_MASK);
8166 wr32(E1000_FCRTC, reg);
8167
b980ac18 8168 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8169 * frame size, capping it at PBA - 10KB.
8170 */
45693bcb 8171 dmac_thr = pba - 10;
b6e0c419
CW		 8172 reg = rd32(E1000_DMACR);
8173 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8174 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8175 & E1000_DMACR_DMACTHR_MASK);
8176
8177 /* transition to L0x or L1 if available..*/
8178 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8179
8180 /* watchdog timer= +-1000 usec in 32usec intervals */
8181 reg |= (1000 >> 5);
0c02dd98
MV		 8182
8183 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8184 if (hw->mac.type != e1000_i354)
8185 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8186
b6e0c419
CW		 8187 wr32(E1000_DMACR, reg);
8188
b980ac18 8189 /* no lower threshold to disable
b6e0c419
CW		 8190 * coalescing(smart fifb)-UTRESH=0
8191 */
8192 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8193
8194 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8195
8196 wr32(E1000_DMCTLX, reg);
8197
b980ac18 8198 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8199 * DMA coal
8200 */
8201 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8202 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8203
b980ac18 8204 /* make low power state decision controlled
b6e0c419
CW		 8205 * by DMA coal
8206 */
8207 reg = rd32(E1000_PCIEMISC);
8208 reg &= ~E1000_PCIEMISC_LX_DECISION;
8209 wr32(E1000_PCIEMISC, reg);
8210 } /* endif adapter->dmac is not disabled */
8211 } else if (hw->mac.type == e1000_82580) {
8212 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8213
b6e0c419
CW		 8214 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8215 wr32(E1000_DMACR, 0);
8216 }
8217}
8218
b980ac18
JK		 8219/**
8220 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8221 * @hw: pointer to hardware structure
8222 * @byte_offset: byte offset to read
8223 * @dev_addr: device address
8224 * @data: value read
8225 *
8226 * Performs byte read operation over I2C interface at
8227 * a specified device address.
b980ac18 8228 **/
441fc6fd 8229s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8230 u8 dev_addr, u8 *data)
441fc6fd
CW		 8231{
8232 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8233 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8234 s32 status;
8235 u16 swfw_mask = 0;
8236
8237 if (!this_client)
8238 return E1000_ERR_I2C;
8239
8240 swfw_mask = E1000_SWFW_PHY0_SM;
8241
23d87824 8242 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8243 return E1000_ERR_SWFW_SYNC;
8244
8245 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8246 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8247
8248 if (status < 0)
8249 return E1000_ERR_I2C;
8250 else {
8251 *data = status;
23d87824 8252 return 0;
441fc6fd
CW		 8253 }
8254}
8255
b980ac18
JK		 8256/**
8257 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8258 * @hw: pointer to hardware structure
8259 * @byte_offset: byte offset to write
8260 * @dev_addr: device address
8261 * @data: value to write
8262 *
8263 * Performs byte write operation over I2C interface at
8264 * a specified device address.
b980ac18 8265 **/
441fc6fd 8266s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8267 u8 dev_addr, u8 data)
441fc6fd
CW		 8268{
8269 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8270 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8271 s32 status;
8272 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8273
8274 if (!this_client)
8275 return E1000_ERR_I2C;
8276
23d87824 8277 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8278 return E1000_ERR_SWFW_SYNC;
8279 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8280 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8281
8282 if (status)
8283 return E1000_ERR_I2C;
8284 else
23d87824 8285 return 0;
441fc6fd
CW		 8286
8287}
907b7835
LMV		 8288
8289int igb_reinit_queues(struct igb_adapter *adapter)
8290{
8291 struct net_device *netdev = adapter->netdev;
8292 struct pci_dev *pdev = adapter->pdev;
8293 int err = 0;
8294
8295 if (netif_running(netdev))
8296 igb_close(netdev);
8297
02ef6e1d 8298 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8299
8300 if (igb_init_interrupt_scheme(adapter, true)) {
8301 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8302 return -ENOMEM;
8303 }
8304
8305 if (netif_running(netdev))
8306 err = igb_open(netdev);
8307
8308 return err;
8309}
9d5c8243 8310/* igb_main.c */
Linux kernel - Deliverables
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