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ixgbe: add array of MAC type dependent values
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
14438464 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
ccffad25 32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 44 u16 count);
c44ade9e
JB		 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 49
9a799d71 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
ff9d1a5a 58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 59
9a900eca
DS		 60/* Base table for registers values that change by MAC */
61const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
62 IXGBE_MVALS_INIT(8259X)
63};
64
67a79df2
AD		 65/**
66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
67 * control
68 * @hw: pointer to hardware structure
69 *
70 * There are several phys that do not support autoneg flow control. This
71 * function check the device id to see if the associated phy supports
72 * autoneg flow control.
73 **/
73d80953 74bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2 75{
73d80953
DS		 76 bool supported = false;
77 ixgbe_link_speed speed;
78 bool link_up;
67a79df2 79
73d80953
DS		 80 switch (hw->phy.media_type) {
81 case ixgbe_media_type_fiber:
82 hw->mac.ops.check_link(hw, &speed, &link_up, false);
83 /* if link is down, assume supported */
84 if (link_up)
85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
86 true : false;
87 else
88 supported = true;
89 break;
90 case ixgbe_media_type_backplane:
91 supported = true;
92 break;
93 case ixgbe_media_type_copper:
94 /* only some copper devices support flow control autoneg */
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82599_T3_LOM:
97 case IXGBE_DEV_ID_X540T:
98 case IXGBE_DEV_ID_X540T1:
99 supported = true;
100 break;
101 default:
102 break;
103 }
67a79df2 104 default:
73d80953 105 break;
67a79df2 106 }
73d80953
DS		 107
108 return supported;
67a79df2
AD		 109}
110
111/**
112 * ixgbe_setup_fc - Set up flow control
113 * @hw: pointer to hardware structure
114 *
115 * Called at init time to set up flow control.
116 **/
041441d0 117static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 118{
119 s32 ret_val = 0;
120 u32 reg = 0, reg_bp = 0;
121 u16 reg_cu = 0;
429d6a3b 122 bool locked = false;
67a79df2 123
67a79df2
AD		 124 /*
125 * Validate the requested mode. Strict IEEE mode does not allow
126 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
127 */
128 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
129 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
e90dd264 130 return IXGBE_ERR_INVALID_LINK_SETTINGS;
67a79df2
AD		 131 }
132
133 /*
134 * 10gig parts do not have a word in the EEPROM to determine the
135 * default flow control setting, so we explicitly set it to full.
136 */
137 if (hw->fc.requested_mode == ixgbe_fc_default)
138 hw->fc.requested_mode = ixgbe_fc_full;
139
140 /*
141 * Set up the 1G and 10G flow control advertisement registers so the
142 * HW will be able to do fc autoneg once the cable is plugged in. If
143 * we link at 10G, the 1G advertisement is harmless and vice versa.
144 */
67a79df2 145 switch (hw->phy.media_type) {
429d6a3b
DS		 146 case ixgbe_media_type_backplane:
147 /* some MAC's need RMW protection on AUTOC */
148 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
f8cf7a00 149 if (ret_val)
e90dd264 150 return ret_val;
429d6a3b
DS		 151
152 /* only backplane uses autoc so fall though */
67a79df2 153 case ixgbe_media_type_fiber:
67a79df2 154 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
429d6a3b 155
67a79df2 156 break;
67a79df2
AD		 157 case ixgbe_media_type_copper:
158 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
159 MDIO_MMD_AN, &reg_cu);
160 break;
67a79df2 161 default:
041441d0 162 break;
67a79df2
AD		 163 }
164
165 /*
166 * The possible values of fc.requested_mode are:
167 * 0: Flow control is completely disabled
168 * 1: Rx flow control is enabled (we can receive pause frames,
169 * but not send pause frames).
170 * 2: Tx flow control is enabled (we can send pause frames but
171 * we do not support receiving pause frames).
172 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 173 * other: Invalid.
174 */
175 switch (hw->fc.requested_mode) {
176 case ixgbe_fc_none:
177 /* Flow control completely disabled by software override. */
178 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
179 if (hw->phy.media_type == ixgbe_media_type_backplane)
180 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
181 IXGBE_AUTOC_ASM_PAUSE);
182 else if (hw->phy.media_type == ixgbe_media_type_copper)
183 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
184 break;
67a79df2
AD		 185 case ixgbe_fc_tx_pause:
186 /*
187 * Tx Flow control is enabled, and Rx Flow control is
188 * disabled by software override.
189 */
041441d0
AD		 190 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
191 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 192 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 193 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
194 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 195 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 196 reg_cu |= IXGBE_TAF_ASM_PAUSE;
197 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 198 }
199 break;
041441d0
AD		 200 case ixgbe_fc_rx_pause:
201 /*
202 * Rx Flow control is enabled and Tx Flow control is
203 * disabled by software override. Since there really
204 * isn't a way to advertise that we are capable of RX
205 * Pause ONLY, we will advertise that we support both
206 * symmetric and asymmetric Rx PAUSE, as such we fall
207 * through to the fc_full statement. Later, we will
208 * disable the adapter's ability to send PAUSE frames.
209 */
67a79df2
AD		 210 case ixgbe_fc_full:
211 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 212 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 213 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 214 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
215 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 216 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 217 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 218 break;
67a79df2
AD		 219 default:
220 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 221 return IXGBE_ERR_CONFIG;
67a79df2
AD		 222 }
223
224 if (hw->mac.type != ixgbe_mac_X540) {
225 /*
226 * Enable auto-negotiation between the MAC & PHY;
227 * the MAC will advertise clause 37 flow control.
228 */
229 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
230 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
231
232 /* Disable AN timeout */
233 if (hw->fc.strict_ieee)
234 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
235
236 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
237 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
238 }
239
240 /*
241 * AUTOC restart handles negotiation of 1G and 10G on backplane
242 * and copper. There is no need to set the PCS1GCTL register.
243 *
244 */
245 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 246 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
247 * LESM is on, likewise reset_pipeline requries the lock as
248 * it also writes AUTOC.
249 */
429d6a3b
DS		 250 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
251 if (ret_val)
e90dd264 252 return ret_val;
d7bbcd32 253
67a79df2 254 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
429d6a3b 255 ixgbe_device_supports_autoneg_fc(hw)) {
67a79df2
AD		 256 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
257 MDIO_MMD_AN, reg_cu);
258 }
259
260 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
67a79df2
AD		 261 return ret_val;
262}
263
9a799d71 264/**
c44ade9e 265 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 266 * @hw: pointer to hardware structure
267 *
268 * Starts the hardware by filling the bus info structure and media type, clears
269 * all on chip counters, initializes receive address registers, multicast
270 * table, VLAN filter table, calls routine to set up link and flow control
271 * settings, and leaves transmit and receive units disabled and uninitialized
272 **/
c44ade9e 273s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71 274{
e5776620 275 s32 ret_val;
9a799d71
AK		 276 u32 ctrl_ext;
277
278 /* Set the media type */
279 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
280
281 /* Identify the PHY */
c44ade9e 282 hw->phy.ops.identify(hw);
9a799d71 283
9a799d71 284 /* Clear the VLAN filter table */
c44ade9e 285 hw->mac.ops.clear_vfta(hw);
9a799d71 286
9a799d71 287 /* Clear statistics registers */
c44ade9e 288 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 289
290 /* Set No Snoop Disable */
291 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
292 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
293 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 294 IXGBE_WRITE_FLUSH(hw);
9a799d71 295
620fa036 296 /* Setup flow control */
e5776620
JK		 297 ret_val = ixgbe_setup_fc(hw);
298 if (!ret_val)
e90dd264 299 return 0;
620fa036 300
9a799d71
AK		 301 /* Clear adapter stopped flag */
302 hw->adapter_stopped = false;
303
e5776620 304 return ret_val;
9a799d71
AK		 305}
306
7184b7cf
ET		 307/**
308 * ixgbe_start_hw_gen2 - Init sequence for common device family
309 * @hw: pointer to hw structure
310 *
311 * Performs the init sequence common to the second generation
312 * of 10 GbE devices.
313 * Devices in the second generation:
314 * 82599
315 * X540
316 **/
317s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
318{
319 u32 i;
320
321 /* Clear the rate limiters */
322 for (i = 0; i < hw->mac.max_tx_queues; i++) {
323 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
324 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
325 }
326 IXGBE_WRITE_FLUSH(hw);
327
887012e8 328#ifndef CONFIG_SPARC
3d5c5207
ET		 329 /* Disable relaxed ordering */
330 for (i = 0; i < hw->mac.max_tx_queues; i++) {
887012e8
JK		 331 u32 regval;
332
3d5c5207 333 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 334 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 335 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
336 }
337
338 for (i = 0; i < hw->mac.max_rx_queues; i++) {
887012e8
JK		 339 u32 regval;
340
3d5c5207 341 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 342 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
343 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 344 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
345 }
887012e8 346#endif
7184b7cf
ET		 347 return 0;
348}
349
9a799d71 350/**
c44ade9e 351 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 352 * @hw: pointer to hardware structure
353 *
c44ade9e 354 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 355 * structure and media type, clears all on chip counters, initializes receive
356 * address registers, multicast table, VLAN filter table, calls routine to set
357 * up link and flow control settings, and leaves transmit and receive units
358 * disabled and uninitialized
359 **/
c44ade9e 360s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 361{
794caeb2
PWJ		 362 s32 status;
363
9a799d71 364 /* Reset the hardware */
794caeb2 365 status = hw->mac.ops.reset_hw(hw);
9a799d71 366
794caeb2
PWJ		 367 if (status == 0) {
368 /* Start the HW */
369 status = hw->mac.ops.start_hw(hw);
370 }
9a799d71 371
794caeb2 372 return status;
9a799d71
AK		 373}
374
375/**
c44ade9e 376 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 377 * @hw: pointer to hardware structure
378 *
379 * Clears all hardware statistics counters by reading them from the hardware
380 * Statistics counters are clear on read.
381 **/
c44ade9e 382s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 383{
384 u16 i = 0;
385
386 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
387 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
388 IXGBE_READ_REG(hw, IXGBE_ERRBC);
389 IXGBE_READ_REG(hw, IXGBE_MSPDC);
390 for (i = 0; i < 8; i++)
391 IXGBE_READ_REG(hw, IXGBE_MPC(i));
392
393 IXGBE_READ_REG(hw, IXGBE_MLFC);
394 IXGBE_READ_REG(hw, IXGBE_MRFC);
395 IXGBE_READ_REG(hw, IXGBE_RLEC);
396 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 397 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 398 if (hw->mac.type >= ixgbe_mac_82599EB) {
399 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
400 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
401 } else {
402 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
403 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
404 }
9a799d71
AK		 405
406 for (i = 0; i < 8; i++) {
407 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 408 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 409 if (hw->mac.type >= ixgbe_mac_82599EB) {
410 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
411 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
412 } else {
413 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
414 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
415 }
9a799d71 416 }
667c7565
ET		 417 if (hw->mac.type >= ixgbe_mac_82599EB)
418 for (i = 0; i < 8; i++)
419 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 420 IXGBE_READ_REG(hw, IXGBE_PRC64);
421 IXGBE_READ_REG(hw, IXGBE_PRC127);
422 IXGBE_READ_REG(hw, IXGBE_PRC255);
423 IXGBE_READ_REG(hw, IXGBE_PRC511);
424 IXGBE_READ_REG(hw, IXGBE_PRC1023);
425 IXGBE_READ_REG(hw, IXGBE_PRC1522);
426 IXGBE_READ_REG(hw, IXGBE_GPRC);
427 IXGBE_READ_REG(hw, IXGBE_BPRC);
428 IXGBE_READ_REG(hw, IXGBE_MPRC);
429 IXGBE_READ_REG(hw, IXGBE_GPTC);
430 IXGBE_READ_REG(hw, IXGBE_GORCL);
431 IXGBE_READ_REG(hw, IXGBE_GORCH);
432 IXGBE_READ_REG(hw, IXGBE_GOTCL);
433 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 434 if (hw->mac.type == ixgbe_mac_82598EB)
435 for (i = 0; i < 8; i++)
436 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 437 IXGBE_READ_REG(hw, IXGBE_RUC);
438 IXGBE_READ_REG(hw, IXGBE_RFC);
439 IXGBE_READ_REG(hw, IXGBE_ROC);
440 IXGBE_READ_REG(hw, IXGBE_RJC);
441 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
442 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
443 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
444 IXGBE_READ_REG(hw, IXGBE_TORL);
445 IXGBE_READ_REG(hw, IXGBE_TORH);
446 IXGBE_READ_REG(hw, IXGBE_TPR);
447 IXGBE_READ_REG(hw, IXGBE_TPT);
448 IXGBE_READ_REG(hw, IXGBE_PTC64);
449 IXGBE_READ_REG(hw, IXGBE_PTC127);
450 IXGBE_READ_REG(hw, IXGBE_PTC255);
451 IXGBE_READ_REG(hw, IXGBE_PTC511);
452 IXGBE_READ_REG(hw, IXGBE_PTC1023);
453 IXGBE_READ_REG(hw, IXGBE_PTC1522);
454 IXGBE_READ_REG(hw, IXGBE_MPTC);
455 IXGBE_READ_REG(hw, IXGBE_BPTC);
456 for (i = 0; i < 16; i++) {
457 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 458 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 459 if (hw->mac.type >= ixgbe_mac_82599EB) {
460 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
461 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
462 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
463 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
464 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
465 } else {
466 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
467 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
468 }
9a799d71
AK		 469 }
470
a3aeea0e
ET		 471 if (hw->mac.type == ixgbe_mac_X540) {
472 if (hw->phy.id == 0)
473 hw->phy.ops.identify(hw);
c1085b10
ET		 474 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
475 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
476 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
477 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 478 }
479
9a799d71
AK		 480 return 0;
481}
482
483/**
289700db 484 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 485 * @hw: pointer to hardware structure
289700db
DS		 486 * @pba_num: stores the part number string from the EEPROM
487 * @pba_num_size: part number string buffer length
c44ade9e 488 *
289700db 489 * Reads the part number string from the EEPROM.
c44ade9e 490 **/
289700db 491s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 492 u32 pba_num_size)
c44ade9e
JB		 493{
494 s32 ret_val;
495 u16 data;
289700db
DS		 496 u16 pba_ptr;
497 u16 offset;
498 u16 length;
499
500 if (pba_num == NULL) {
501 hw_dbg(hw, "PBA string buffer was null\n");
502 return IXGBE_ERR_INVALID_ARGUMENT;
503 }
c44ade9e
JB		 504
505 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
506 if (ret_val) {
507 hw_dbg(hw, "NVM Read Error\n");
508 return ret_val;
509 }
c44ade9e 510
289700db 511 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 512 if (ret_val) {
513 hw_dbg(hw, "NVM Read Error\n");
514 return ret_val;
515 }
289700db
DS		 516
517 /*
518 * if data is not ptr guard the PBA must be in legacy format which
519 * means pba_ptr is actually our second data word for the PBA number
520 * and we can decode it into an ascii string
521 */
522 if (data != IXGBE_PBANUM_PTR_GUARD) {
523 hw_dbg(hw, "NVM PBA number is not stored as string\n");
524
525 /* we will need 11 characters to store the PBA */
526 if (pba_num_size < 11) {
527 hw_dbg(hw, "PBA string buffer too small\n");
528 return IXGBE_ERR_NO_SPACE;
529 }
530
531 /* extract hex string from data and pba_ptr */
532 pba_num[0] = (data >> 12) & 0xF;
533 pba_num[1] = (data >> 8) & 0xF;
534 pba_num[2] = (data >> 4) & 0xF;
535 pba_num[3] = data & 0xF;
536 pba_num[4] = (pba_ptr >> 12) & 0xF;
537 pba_num[5] = (pba_ptr >> 8) & 0xF;
538 pba_num[6] = '-';
539 pba_num[7] = 0;
540 pba_num[8] = (pba_ptr >> 4) & 0xF;
541 pba_num[9] = pba_ptr & 0xF;
542
543 /* put a null character on the end of our string */
544 pba_num[10] = '\0';
545
546 /* switch all the data but the '-' to hex char */
547 for (offset = 0; offset < 10; offset++) {
548 if (pba_num[offset] < 0xA)
549 pba_num[offset] += '0';
550 else if (pba_num[offset] < 0x10)
551 pba_num[offset] += 'A' - 0xA;
552 }
553
554 return 0;
555 }
556
557 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
558 if (ret_val) {
559 hw_dbg(hw, "NVM Read Error\n");
560 return ret_val;
561 }
562
563 if (length == 0xFFFF || length == 0) {
564 hw_dbg(hw, "NVM PBA number section invalid length\n");
565 return IXGBE_ERR_PBA_SECTION;
566 }
567
568 /* check if pba_num buffer is big enough */
569 if (pba_num_size < (((u32)length * 2) - 1)) {
570 hw_dbg(hw, "PBA string buffer too small\n");
571 return IXGBE_ERR_NO_SPACE;
572 }
573
574 /* trim pba length from start of string */
575 pba_ptr++;
576 length--;
577
578 for (offset = 0; offset < length; offset++) {
579 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
580 if (ret_val) {
581 hw_dbg(hw, "NVM Read Error\n");
582 return ret_val;
583 }
584 pba_num[offset * 2] = (u8)(data >> 8);
585 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
586 }
587 pba_num[offset * 2] = '\0';
c44ade9e
JB		 588
589 return 0;
590}
591
592/**
593 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 594 * @hw: pointer to hardware structure
595 * @mac_addr: Adapter MAC address
596 *
597 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
598 * A reset of the adapter must be performed prior to calling this function
599 * in order for the MAC address to have been loaded from the EEPROM into RAR0
600 **/
c44ade9e 601s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 602{
603 u32 rar_high;
604 u32 rar_low;
605 u16 i;
606
607 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
608 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
609
610 for (i = 0; i < 4; i++)
611 mac_addr[i] = (u8)(rar_low >> (i*8));
612
613 for (i = 0; i < 2; i++)
614 mac_addr[i+4] = (u8)(rar_high >> (i*8));
615
616 return 0;
617}
618
ef1889d5
JK		 619enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
620{
621 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
622 case IXGBE_PCI_LINK_WIDTH_1:
623 return ixgbe_bus_width_pcie_x1;
624 case IXGBE_PCI_LINK_WIDTH_2:
625 return ixgbe_bus_width_pcie_x2;
626 case IXGBE_PCI_LINK_WIDTH_4:
627 return ixgbe_bus_width_pcie_x4;
628 case IXGBE_PCI_LINK_WIDTH_8:
629 return ixgbe_bus_width_pcie_x8;
630 default:
631 return ixgbe_bus_width_unknown;
632 }
633}
634
635enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
636{
637 switch (link_status & IXGBE_PCI_LINK_SPEED) {
638 case IXGBE_PCI_LINK_SPEED_2500:
639 return ixgbe_bus_speed_2500;
640 case IXGBE_PCI_LINK_SPEED_5000:
641 return ixgbe_bus_speed_5000;
642 case IXGBE_PCI_LINK_SPEED_8000:
643 return ixgbe_bus_speed_8000;
644 default:
645 return ixgbe_bus_speed_unknown;
646 }
647}
648
11afc1b1
PW		 649/**
650 * ixgbe_get_bus_info_generic - Generic set PCI bus info
651 * @hw: pointer to hardware structure
652 *
653 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
654 **/
655s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
656{
11afc1b1
PW		 657 u16 link_status;
658
659 hw->bus.type = ixgbe_bus_type_pci_express;
660
661 /* Get the negotiated link width and speed from PCI config space */
0d7c6e00 662 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
11afc1b1 663
ef1889d5
JK		 664 hw->bus.width = ixgbe_convert_bus_width(link_status);
665 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1 666
0d7c6e00 667 hw->mac.ops.set_lan_id(hw);
11afc1b1
PW		 668
669 return 0;
670}
671
672/**
673 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
674 * @hw: pointer to the HW structure
675 *
676 * Determines the LAN function id by reading memory-mapped registers
677 * and swaps the port value if requested.
678 **/
679void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
680{
681 struct ixgbe_bus_info *bus = &hw->bus;
682 u32 reg;
683
684 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
685 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
686 bus->lan_id = bus->func;
687
688 /* check for a port swap */
9a900eca 689 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
11afc1b1
PW		 690 if (reg & IXGBE_FACTPS_LFS)
691 bus->func ^= 0x1;
692}
693
9a799d71 694/**
c44ade9e 695 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 696 * @hw: pointer to hardware structure
697 *
698 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
699 * disables transmit and receive units. The adapter_stopped flag is used by
700 * the shared code and drivers to determine if the adapter is in a stopped
701 * state and should not touch the hardware.
702 **/
c44ade9e 703s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 704{
9a799d71
AK		 705 u32 reg_val;
706 u16 i;
707
708 /*
709 * Set the adapter_stopped flag so other driver functions stop touching
710 * the hardware
711 */
712 hw->adapter_stopped = true;
713
714 /* Disable the receive unit */
1f9ac57c 715 hw->mac.ops.disable_rx(hw);
9a799d71 716
ff9d1a5a 717 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 718 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
719
ff9d1a5a 720 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 721 IXGBE_READ_REG(hw, IXGBE_EICR);
722
723 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 724 for (i = 0; i < hw->mac.max_tx_queues; i++)
725 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
726
727 /* Disable the receive unit by stopping each queue */
728 for (i = 0; i < hw->mac.max_rx_queues; i++) {
729 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
730 reg_val &= ~IXGBE_RXDCTL_ENABLE;
731 reg_val |= IXGBE_RXDCTL_SWFLSH;
732 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 733 }
734
ff9d1a5a
ET		 735 /* flush all queues disables */
736 IXGBE_WRITE_FLUSH(hw);
737 usleep_range(1000, 2000);
738
c44ade9e
JB		 739 /*
740 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
741 * access and verify no pending requests
742 */
ff9d1a5a 743 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 744}
745
746/**
c44ade9e 747 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 748 * @hw: pointer to hardware structure
749 * @index: led number to turn on
750 **/
c44ade9e 751s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 752{
753 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
754
755 /* To turn on the LED, set mode to ON. */
756 led_reg &= ~IXGBE_LED_MODE_MASK(index);
757 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
758 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 759 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 760
761 return 0;
762}
763
764/**
c44ade9e 765 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 766 * @hw: pointer to hardware structure
767 * @index: led number to turn off
768 **/
c44ade9e 769s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 770{
771 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
772
773 /* To turn off the LED, set mode to OFF. */
774 led_reg &= ~IXGBE_LED_MODE_MASK(index);
775 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
776 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 777 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 778
779 return 0;
780}
781
9a799d71 782/**
c44ade9e 783 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 784 * @hw: pointer to hardware structure
785 *
786 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
787 * ixgbe_hw struct in order to set up EEPROM access.
788 **/
c44ade9e 789s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 790{
791 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
792 u32 eec;
793 u16 eeprom_size;
794
795 if (eeprom->type == ixgbe_eeprom_uninitialized) {
796 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 797 /* Set default semaphore delay to 10ms which is a well
798 * tested value */
799 eeprom->semaphore_delay = 10;
68c7005d
ET		 800 /* Clear EEPROM page size, it will be initialized as needed */
801 eeprom->word_page_size = 0;
9a799d71
AK		 802
803 /*
804 * Check for EEPROM present first.
805 * If not present leave as none
806 */
9a900eca 807 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9a799d71
AK		 808 if (eec & IXGBE_EEC_PRES) {
809 eeprom->type = ixgbe_eeprom_spi;
810
811 /*
812 * SPI EEPROM is assumed here. This code would need to
813 * change if a future EEPROM is not SPI.
814 */
815 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
816 IXGBE_EEC_SIZE_SHIFT);
817 eeprom->word_size = 1 << (eeprom_size +
818 IXGBE_EEPROM_WORD_SIZE_SHIFT);
819 }
820
821 if (eec & IXGBE_EEC_ADDR_SIZE)
822 eeprom->address_bits = 16;
823 else
824 eeprom->address_bits = 8;
6ec1b71f
JK		 825 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
826 eeprom->type, eeprom->word_size, eeprom->address_bits);
9a799d71
AK		 827 }
828
829 return 0;
830}
831
11afc1b1 832/**
68c7005d 833 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 834 * @hw: pointer to hardware structure
68c7005d
ET		 835 * @offset: offset within the EEPROM to write
836 * @words: number of words
837 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 838 *
68c7005d 839 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 840 **/
68c7005d
ET		 841s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
842 u16 words, u16 *data)
11afc1b1 843{
e90dd264 844 s32 status;
68c7005d 845 u16 i, count;
11afc1b1
PW		 846
847 hw->eeprom.ops.init_params(hw);
848
e90dd264
MR		 849 if (words == 0)
850 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 851
e90dd264
MR		 852 if (offset + words > hw->eeprom.word_size)
853 return IXGBE_ERR_EEPROM;
11afc1b1 854
68c7005d
ET		 855 /*
856 * The EEPROM page size cannot be queried from the chip. We do lazy
857 * initialization. It is worth to do that when we write large buffer.
858 */
859 if ((hw->eeprom.word_page_size == 0) &&
860 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
861 ixgbe_detect_eeprom_page_size_generic(hw, offset);
862
863 /*
864 * We cannot hold synchronization semaphores for too long
865 * to avoid other entity starvation. However it is more efficient
866 * to read in bursts than synchronizing access for each word.
867 */
868 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
869 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
870 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
871 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
872 count, &data[i]);
873
874 if (status != 0)
875 break;
876 }
877
68c7005d
ET		 878 return status;
879}
880
881/**
882 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
883 * @hw: pointer to hardware structure
884 * @offset: offset within the EEPROM to be written to
885 * @words: number of word(s)
886 * @data: 16 bit word(s) to be written to the EEPROM
887 *
888 * If ixgbe_eeprom_update_checksum is not called after this function, the
889 * EEPROM will most likely contain an invalid checksum.
890 **/
891static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
892 u16 words, u16 *data)
893{
894 s32 status;
895 u16 word;
896 u16 page_size;
897 u16 i;
898 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
899
11afc1b1
PW		 900 /* Prepare the EEPROM for writing */
901 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 902 if (status)
903 return status;
11afc1b1 904
e90dd264
MR		 905 if (ixgbe_ready_eeprom(hw) != 0) {
906 ixgbe_release_eeprom(hw);
907 return IXGBE_ERR_EEPROM;
11afc1b1
PW		 908 }
909
e90dd264
MR		 910 for (i = 0; i < words; i++) {
911 ixgbe_standby_eeprom(hw);
912
913 /* Send the WRITE ENABLE command (8 bit opcode) */
914 ixgbe_shift_out_eeprom_bits(hw,
915 IXGBE_EEPROM_WREN_OPCODE_SPI,
916 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 917
e90dd264 918 ixgbe_standby_eeprom(hw);
11afc1b1 919
e90dd264
MR		 920 /* Some SPI eeproms use the 8th address bit embedded
921 * in the opcode
922 */
923 if ((hw->eeprom.address_bits == 8) &&
924 ((offset + i) >= 128))
925 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
11afc1b1 926
e90dd264
MR		 927 /* Send the Write command (8-bit opcode + addr) */
928 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
929 IXGBE_EEPROM_OPCODE_BITS);
930 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
931 hw->eeprom.address_bits);
932
933 page_size = hw->eeprom.word_page_size;
934
935 /* Send the data in burst via SPI */
936 do {
937 word = data[i];
938 word = (word >> 8) | (word << 8);
939 ixgbe_shift_out_eeprom_bits(hw, word, 16);
940
941 if (page_size == 0)
942 break;
943
944 /* do not wrap around page */
945 if (((offset + i) & (page_size - 1)) ==
946 (page_size - 1))
947 break;
948 } while (++i < words);
949
950 ixgbe_standby_eeprom(hw);
951 usleep_range(10000, 20000);
68c7005d 952 }
e90dd264
MR		 953 /* Done with writing - release the EEPROM */
954 ixgbe_release_eeprom(hw);
11afc1b1 955
e90dd264 956 return 0;
68c7005d
ET		 957}
958
959/**
960 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
961 * @hw: pointer to hardware structure
962 * @offset: offset within the EEPROM to be written to
963 * @data: 16 bit word to be written to the EEPROM
964 *
965 * If ixgbe_eeprom_update_checksum is not called after this function, the
966 * EEPROM will most likely contain an invalid checksum.
967 **/
968s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
969{
68c7005d 970 hw->eeprom.ops.init_params(hw);
11afc1b1 971
e90dd264
MR		 972 if (offset >= hw->eeprom.word_size)
973 return IXGBE_ERR_EEPROM;
11afc1b1 974
e90dd264 975 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
11afc1b1
PW		 976}
977
9a799d71 978/**
68c7005d 979 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 980 * @hw: pointer to hardware structure
981 * @offset: offset within the EEPROM to be read
68c7005d
ET		 982 * @words: number of word(s)
983 * @data: read 16 bit words(s) from EEPROM
c44ade9e 984 *
68c7005d 985 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 986 **/
68c7005d
ET		 987s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
988 u16 words, u16 *data)
c44ade9e 989{
e90dd264 990 s32 status;
68c7005d 991 u16 i, count;
c44ade9e
JB		 992
993 hw->eeprom.ops.init_params(hw);
994
e90dd264
MR		 995 if (words == 0)
996 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 997
e90dd264
MR		 998 if (offset + words > hw->eeprom.word_size)
999 return IXGBE_ERR_EEPROM;
c44ade9e 1000
68c7005d
ET		 1001 /*
1002 * We cannot hold synchronization semaphores for too long
1003 * to avoid other entity starvation. However it is more efficient
1004 * to read in bursts than synchronizing access for each word.
1005 */
1006 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1007 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1008 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1009
1010 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1011 count, &data[i]);
1012
e90dd264
MR		 1013 if (status)
1014 return status;
68c7005d
ET		 1015 }
1016
e90dd264 1017 return 0;
68c7005d
ET		 1018}
1019
1020/**
1021 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1022 * @hw: pointer to hardware structure
1023 * @offset: offset within the EEPROM to be read
1024 * @words: number of word(s)
1025 * @data: read 16 bit word(s) from EEPROM
1026 *
1027 * Reads 16 bit word(s) from EEPROM through bit-bang method
1028 **/
1029static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1030 u16 words, u16 *data)
1031{
1032 s32 status;
1033 u16 word_in;
1034 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1035 u16 i;
1036
c44ade9e
JB		 1037 /* Prepare the EEPROM for reading */
1038 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 1039 if (status)
1040 return status;
c44ade9e 1041
e90dd264
MR		 1042 if (ixgbe_ready_eeprom(hw) != 0) {
1043 ixgbe_release_eeprom(hw);
1044 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1045 }
1046
e90dd264
MR		 1047 for (i = 0; i < words; i++) {
1048 ixgbe_standby_eeprom(hw);
1049 /* Some SPI eeproms use the 8th address bit embedded
1050 * in the opcode
1051 */
1052 if ((hw->eeprom.address_bits == 8) &&
1053 ((offset + i) >= 128))
1054 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
c44ade9e 1055
e90dd264
MR		 1056 /* Send the READ command (opcode + addr) */
1057 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1058 IXGBE_EEPROM_OPCODE_BITS);
1059 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1060 hw->eeprom.address_bits);
1061
1062 /* Read the data. */
1063 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1064 data[i] = (word_in >> 8) | (word_in << 8);
68c7005d 1065 }
c44ade9e 1066
e90dd264
MR		 1067 /* End this read operation */
1068 ixgbe_release_eeprom(hw);
1069
1070 return 0;
68c7005d 1071}
c44ade9e 1072
68c7005d
ET		 1073/**
1074 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1075 * @hw: pointer to hardware structure
1076 * @offset: offset within the EEPROM to be read
1077 * @data: read 16 bit value from EEPROM
1078 *
1079 * Reads 16 bit value from EEPROM through bit-bang method
1080 **/
1081s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1082 u16 *data)
1083{
68c7005d
ET		 1084 hw->eeprom.ops.init_params(hw);
1085
e90dd264
MR		 1086 if (offset >= hw->eeprom.word_size)
1087 return IXGBE_ERR_EEPROM;
68c7005d 1088
e90dd264 1089 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
c44ade9e
JB		 1090}
1091
1092/**
68c7005d 1093 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1094 * @hw: pointer to hardware structure
68c7005d
ET		 1095 * @offset: offset of word in the EEPROM to read
1096 * @words: number of word(s)
1097 * @data: 16 bit word(s) from the EEPROM
9a799d71 1098 *
68c7005d 1099 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1100 **/
68c7005d
ET		 1101s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1102 u16 words, u16 *data)
9a799d71
AK		 1103{
1104 u32 eerd;
e90dd264 1105 s32 status;
68c7005d 1106 u32 i;
9a799d71 1107
c44ade9e
JB		 1108 hw->eeprom.ops.init_params(hw);
1109
e90dd264
MR		 1110 if (words == 0)
1111 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1112
e90dd264
MR		 1113 if (offset >= hw->eeprom.word_size)
1114 return IXGBE_ERR_EEPROM;
c44ade9e 1115
68c7005d 1116 for (i = 0; i < words; i++) {
d0111575 1117 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1118 IXGBE_EEPROM_RW_REG_START;
9a799d71 1119
68c7005d
ET		 1120 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1121 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1122
68c7005d
ET		 1123 if (status == 0) {
1124 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1125 IXGBE_EEPROM_RW_REG_DATA);
1126 } else {
1127 hw_dbg(hw, "Eeprom read timed out\n");
e90dd264 1128 return status;
68c7005d
ET		 1129 }
1130 }
e90dd264
MR		 1131
1132 return 0;
68c7005d 1133}
9a799d71 1134
68c7005d
ET		 1135/**
1136 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1137 * @hw: pointer to hardware structure
1138 * @offset: offset within the EEPROM to be used as a scratch pad
1139 *
1140 * Discover EEPROM page size by writing marching data at given offset.
1141 * This function is called only when we are writing a new large buffer
1142 * at given offset so the data would be overwritten anyway.
1143 **/
1144static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1145 u16 offset)
1146{
1147 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
e90dd264 1148 s32 status;
68c7005d
ET		 1149 u16 i;
1150
1151 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1152 data[i] = i;
1153
1154 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1155 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1156 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1157 hw->eeprom.word_page_size = 0;
e90dd264
MR		 1158 if (status)
1159 return status;
68c7005d
ET		 1160
1161 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
e90dd264
MR		 1162 if (status)
1163 return status;
68c7005d
ET		 1164
1165 /*
1166 * When writing in burst more than the actual page size
1167 * EEPROM address wraps around current page.
1168 */
1169 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1170
c5ffe7e1 1171 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
68c7005d 1172 hw->eeprom.word_page_size);
e90dd264 1173 return 0;
9a799d71
AK		 1174}
1175
eb9c3e3e 1176/**
68c7005d
ET		 1177 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1178 * @hw: pointer to hardware structure
1179 * @offset: offset of word in the EEPROM to read
1180 * @data: word read from the EEPROM
1181 *
1182 * Reads a 16 bit word from the EEPROM using the EERD register.
1183 **/
1184s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1185{
1186 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1187}
1188
1189/**
1190 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1191 * @hw: pointer to hardware structure
1192 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1193 * @words: number of words
1194 * @data: word(s) write to the EEPROM
eb9c3e3e 1195 *
68c7005d 1196 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1197 **/
68c7005d
ET		 1198s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1199 u16 words, u16 *data)
eb9c3e3e
ET		 1200{
1201 u32 eewr;
e90dd264 1202 s32 status;
68c7005d 1203 u16 i;
eb9c3e3e
ET		 1204
1205 hw->eeprom.ops.init_params(hw);
1206
e90dd264
MR		 1207 if (words == 0)
1208 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1209
e90dd264
MR		 1210 if (offset >= hw->eeprom.word_size)
1211 return IXGBE_ERR_EEPROM;
eb9c3e3e 1212
68c7005d
ET		 1213 for (i = 0; i < words; i++) {
1214 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1215 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1216 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1217
68c7005d 1218 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1219 if (status) {
68c7005d 1220 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1221 return status;
68c7005d 1222 }
eb9c3e3e 1223
68c7005d 1224 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1225
68c7005d 1226 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1227 if (status) {
68c7005d 1228 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1229 return status;
68c7005d 1230 }
eb9c3e3e
ET		 1231 }
1232
e90dd264 1233 return 0;
eb9c3e3e
ET		 1234}
1235
68c7005d
ET		 1236/**
1237 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1238 * @hw: pointer to hardware structure
1239 * @offset: offset of word in the EEPROM to write
1240 * @data: word write to the EEPROM
1241 *
1242 * Write a 16 bit word to the EEPROM using the EEWR register.
1243 **/
1244s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1245{
1246 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1247}
1248
9a799d71 1249/**
21ce849b 1250 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1251 * @hw: pointer to hardware structure
21ce849b 1252 * @ee_reg: EEPROM flag for polling
9a799d71 1253 *
21ce849b
MC		 1254 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1255 * read or write is done respectively.
9a799d71 1256 **/
eb9c3e3e 1257static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1258{
1259 u32 i;
1260 u32 reg;
9a799d71 1261
21ce849b
MC		 1262 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1263 if (ee_reg == IXGBE_NVM_POLL_READ)
1264 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1265 else
1266 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1267
1268 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
e90dd264 1269 return 0;
9a799d71
AK		 1270 }
1271 udelay(5);
1272 }
e90dd264 1273 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1274}
1275
c44ade9e
JB		 1276/**
1277 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1278 * @hw: pointer to hardware structure
1279 *
1280 * Prepares EEPROM for access using bit-bang method. This function should
1281 * be called before issuing a command to the EEPROM.
1282 **/
1283static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1284{
dbf893ee 1285 u32 eec;
c44ade9e
JB		 1286 u32 i;
1287
5e655105 1288 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
e90dd264 1289 return IXGBE_ERR_SWFW_SYNC;
c44ade9e 1290
9a900eca 1291 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e 1292
e90dd264
MR		 1293 /* Request EEPROM Access */
1294 eec |= IXGBE_EEC_REQ;
9a900eca 1295 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e 1296
e90dd264 1297 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
9a900eca 1298 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
e90dd264
MR		 1299 if (eec & IXGBE_EEC_GNT)
1300 break;
1301 udelay(5);
1302 }
c44ade9e 1303
e90dd264
MR		 1304 /* Release if grant not acquired */
1305 if (!(eec & IXGBE_EEC_GNT)) {
1306 eec &= ~IXGBE_EEC_REQ;
9a900eca 1307 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
e90dd264 1308 hw_dbg(hw, "Could not acquire EEPROM grant\n");
c44ade9e 1309
e90dd264
MR		 1310 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1311 return IXGBE_ERR_EEPROM;
c44ade9e 1312 }
e90dd264
MR		 1313
1314 /* Setup EEPROM for Read/Write */
1315 /* Clear CS and SK */
1316 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
9a900eca 1317 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
e90dd264
MR		 1318 IXGBE_WRITE_FLUSH(hw);
1319 udelay(1);
1320 return 0;
c44ade9e
JB		 1321}
1322
9a799d71
AK		 1323/**
1324 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1325 * @hw: pointer to hardware structure
1326 *
1327 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1328 **/
1329static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1330{
dbf893ee 1331 u32 timeout = 2000;
9a799d71
AK		 1332 u32 i;
1333 u32 swsm;
1334
9a799d71
AK		 1335 /* Get SMBI software semaphore between device drivers first */
1336 for (i = 0; i < timeout; i++) {
1337 /*
1338 * If the SMBI bit is 0 when we read it, then the bit will be
1339 * set and we have the semaphore
1340 */
9a900eca 1341 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264 1342 if (!(swsm & IXGBE_SWSM_SMBI))
9a799d71 1343 break;
d819fc52 1344 usleep_range(50, 100);
9a799d71
AK		 1345 }
1346
51275d37 1347 if (i == timeout) {
6ec1b71f 1348 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
e90dd264 1349 /* this release is particularly important because our attempts
51275d37
ET		 1350 * above to get the semaphore may have succeeded, and if there
1351 * was a timeout, we should unconditionally clear the semaphore
1352 * bits to free the driver to make progress
1353 */
1354 ixgbe_release_eeprom_semaphore(hw);
1355
d819fc52 1356 usleep_range(50, 100);
e90dd264 1357 /* one last try
51275d37
ET		 1358 * If the SMBI bit is 0 when we read it, then the bit will be
1359 * set and we have the semaphore
1360 */
9a900eca 1361 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264
MR		 1362 if (swsm & IXGBE_SWSM_SMBI) {
1363 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1364 return IXGBE_ERR_EEPROM;
1365 }
51275d37
ET		 1366 }
1367
9a799d71 1368 /* Now get the semaphore between SW/FW through the SWESMBI bit */
e90dd264 1369 for (i = 0; i < timeout; i++) {
9a900eca 1370 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
9a799d71 1371
e90dd264
MR		 1372 /* Set the SW EEPROM semaphore bit to request access */
1373 swsm |= IXGBE_SWSM_SWESMBI;
9a900eca 1374 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
9a799d71 1375
e90dd264
MR		 1376 /* If we set the bit successfully then we got the
1377 * semaphore.
1378 */
9a900eca 1379 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264
MR		 1380 if (swsm & IXGBE_SWSM_SWESMBI)
1381 break;
9a799d71 1382
e90dd264
MR		 1383 usleep_range(50, 100);
1384 }
9a799d71 1385
e90dd264
MR		 1386 /* Release semaphores and return error if SW EEPROM semaphore
1387 * was not granted because we don't have access to the EEPROM
1388 */
1389 if (i >= timeout) {
1390 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1391 ixgbe_release_eeprom_semaphore(hw);
1392 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1393 }
1394
e90dd264 1395 return 0;
9a799d71
AK		 1396}
1397
1398/**
1399 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1400 * @hw: pointer to hardware structure
1401 *
1402 * This function clears hardware semaphore bits.
1403 **/
1404static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1405{
1406 u32 swsm;
1407
9a900eca 1408 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
9a799d71
AK		 1409
1410 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1411 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
9a900eca 1412 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
3957d63d 1413 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1414}
1415
c44ade9e
JB		 1416/**
1417 * ixgbe_ready_eeprom - Polls for EEPROM ready
1418 * @hw: pointer to hardware structure
1419 **/
1420static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1421{
c44ade9e
JB		 1422 u16 i;
1423 u8 spi_stat_reg;
1424
1425 /*
1426 * Read "Status Register" repeatedly until the LSB is cleared. The
1427 * EEPROM will signal that the command has been completed by clearing
1428 * bit 0 of the internal status register. If it's not cleared within
1429 * 5 milliseconds, then error out.
1430 */
1431 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1432 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
e7cf745b 1433 IXGBE_EEPROM_OPCODE_BITS);
c44ade9e
JB		 1434 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1435 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1436 break;
1437
1438 udelay(5);
1439 ixgbe_standby_eeprom(hw);
6403eab1 1440 }
c44ade9e
JB		 1441
1442 /*
1443 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1444 * devices (and only 0-5mSec on 5V devices)
1445 */
1446 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1447 hw_dbg(hw, "SPI EEPROM Status error\n");
e90dd264 1448 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1449 }
1450
e90dd264 1451 return 0;
c44ade9e
JB		 1452}
1453
1454/**
1455 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1456 * @hw: pointer to hardware structure
1457 **/
1458static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1459{
1460 u32 eec;
1461
9a900eca 1462 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1463
1464 /* Toggle CS to flush commands */
1465 eec |= IXGBE_EEC_CS;
9a900eca 1466 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1467 IXGBE_WRITE_FLUSH(hw);
1468 udelay(1);
1469 eec &= ~IXGBE_EEC_CS;
9a900eca 1470 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1471 IXGBE_WRITE_FLUSH(hw);
1472 udelay(1);
1473}
1474
1475/**
1476 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1477 * @hw: pointer to hardware structure
1478 * @data: data to send to the EEPROM
1479 * @count: number of bits to shift out
1480 **/
1481static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 1482 u16 count)
c44ade9e
JB		 1483{
1484 u32 eec;
1485 u32 mask;
1486 u32 i;
1487
9a900eca 1488 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1489
1490 /*
1491 * Mask is used to shift "count" bits of "data" out to the EEPROM
1492 * one bit at a time. Determine the starting bit based on count
1493 */
1494 mask = 0x01 << (count - 1);
1495
1496 for (i = 0; i < count; i++) {
1497 /*
1498 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1499 * "1", and then raising and then lowering the clock (the SK
1500 * bit controls the clock input to the EEPROM). A "0" is
1501 * shifted out to the EEPROM by setting "DI" to "0" and then
1502 * raising and then lowering the clock.
1503 */
1504 if (data & mask)
1505 eec |= IXGBE_EEC_DI;
1506 else
1507 eec &= ~IXGBE_EEC_DI;
1508
9a900eca 1509 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1510 IXGBE_WRITE_FLUSH(hw);
1511
1512 udelay(1);
1513
1514 ixgbe_raise_eeprom_clk(hw, &eec);
1515 ixgbe_lower_eeprom_clk(hw, &eec);
1516
1517 /*
1518 * Shift mask to signify next bit of data to shift in to the
1519 * EEPROM
1520 */
1521 mask = mask >> 1;
6403eab1 1522 }
c44ade9e
JB		 1523
1524 /* We leave the "DI" bit set to "0" when we leave this routine. */
1525 eec &= ~IXGBE_EEC_DI;
9a900eca 1526 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1527 IXGBE_WRITE_FLUSH(hw);
1528}
1529
1530/**
1531 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1532 * @hw: pointer to hardware structure
1533 **/
1534static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1535{
1536 u32 eec;
1537 u32 i;
1538 u16 data = 0;
1539
1540 /*
1541 * In order to read a register from the EEPROM, we need to shift
1542 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1543 * the clock input to the EEPROM (setting the SK bit), and then reading
1544 * the value of the "DO" bit. During this "shifting in" process the
1545 * "DI" bit should always be clear.
1546 */
9a900eca 1547 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1548
1549 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1550
1551 for (i = 0; i < count; i++) {
1552 data = data << 1;
1553 ixgbe_raise_eeprom_clk(hw, &eec);
1554
9a900eca 1555 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1556
1557 eec &= ~(IXGBE_EEC_DI);
1558 if (eec & IXGBE_EEC_DO)
1559 data |= 1;
1560
1561 ixgbe_lower_eeprom_clk(hw, &eec);
1562 }
1563
1564 return data;
1565}
1566
1567/**
1568 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1569 * @hw: pointer to hardware structure
1570 * @eec: EEC register's current value
1571 **/
1572static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1573{
1574 /*
1575 * Raise the clock input to the EEPROM
1576 * (setting the SK bit), then delay
1577 */
1578 *eec = *eec | IXGBE_EEC_SK;
9a900eca 1579 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
c44ade9e
JB		 1580 IXGBE_WRITE_FLUSH(hw);
1581 udelay(1);
1582}
1583
1584/**
1585 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1586 * @hw: pointer to hardware structure
1587 * @eecd: EECD's current value
1588 **/
1589static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1590{
1591 /*
1592 * Lower the clock input to the EEPROM (clearing the SK bit), then
1593 * delay
1594 */
1595 *eec = *eec & ~IXGBE_EEC_SK;
9a900eca 1596 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
c44ade9e
JB		 1597 IXGBE_WRITE_FLUSH(hw);
1598 udelay(1);
1599}
1600
1601/**
1602 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1603 * @hw: pointer to hardware structure
1604 **/
1605static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1606{
1607 u32 eec;
1608
9a900eca 1609 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1610
1611 eec |= IXGBE_EEC_CS; /* Pull CS high */
1612 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1613
9a900eca 1614 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1615 IXGBE_WRITE_FLUSH(hw);
1616
1617 udelay(1);
1618
1619 /* Stop requesting EEPROM access */
1620 eec &= ~IXGBE_EEC_REQ;
9a900eca 1621 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e 1622
90827996 1623 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1624
032b4325
DS		 1625 /*
1626 * Delay before attempt to obtain semaphore again to allow FW
1627 * access. semaphore_delay is in ms we need us for usleep_range
1628 */
1629 usleep_range(hw->eeprom.semaphore_delay * 1000,
1630 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1631}
1632
9a799d71 1633/**
dbf893ee 1634 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1635 * @hw: pointer to hardware structure
1636 **/
735c35af 1637s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1638{
1639 u16 i;
1640 u16 j;
1641 u16 checksum = 0;
1642 u16 length = 0;
1643 u16 pointer = 0;
1644 u16 word = 0;
1645
1646 /* Include 0x0-0x3F in the checksum */
1647 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
735c35af 1648 if (hw->eeprom.ops.read(hw, i, &word)) {
9a799d71
AK		 1649 hw_dbg(hw, "EEPROM read failed\n");
1650 break;
1651 }
1652 checksum += word;
1653 }
1654
1655 /* Include all data from pointers except for the fw pointer */
1656 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
735c35af
DS		 1657 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1658 hw_dbg(hw, "EEPROM read failed\n");
1659 return IXGBE_ERR_EEPROM;
1660 }
1661
1662 /* If the pointer seems invalid */
1663 if (pointer == 0xFFFF || pointer == 0)
1664 continue;
1665
1666 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1667 hw_dbg(hw, "EEPROM read failed\n");
1668 return IXGBE_ERR_EEPROM;
1669 }
9a799d71 1670
735c35af
DS		 1671 if (length == 0xFFFF || length == 0)
1672 continue;
9a799d71 1673
735c35af
DS		 1674 for (j = pointer + 1; j <= pointer + length; j++) {
1675 if (hw->eeprom.ops.read(hw, j, &word)) {
1676 hw_dbg(hw, "EEPROM read failed\n");
1677 return IXGBE_ERR_EEPROM;
9a799d71 1678 }
735c35af 1679 checksum += word;
9a799d71
AK		 1680 }
1681 }
1682
1683 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1684
735c35af 1685 return (s32)checksum;
9a799d71
AK		 1686}
1687
1688/**
c44ade9e 1689 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1690 * @hw: pointer to hardware structure
1691 * @checksum_val: calculated checksum
1692 *
1693 * Performs checksum calculation and validates the EEPROM checksum. If the
1694 * caller does not need checksum_val, the value can be NULL.
1695 **/
c44ade9e 1696s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 1697 u16 *checksum_val)
9a799d71
AK		 1698{
1699 s32 status;
1700 u16 checksum;
1701 u16 read_checksum = 0;
1702
1703 /*
1704 * Read the first word from the EEPROM. If this times out or fails, do
1705 * not continue or we could be in for a very long wait while every
1706 * EEPROM read fails
1707 */
c44ade9e 1708 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af
DS		 1709 if (status) {
1710 hw_dbg(hw, "EEPROM read failed\n");
1711 return status;
1712 }
9a799d71 1713
735c35af
DS		 1714 status = hw->eeprom.ops.calc_checksum(hw);
1715 if (status < 0)
1716 return status;
9a799d71 1717
735c35af 1718 checksum = (u16)(status & 0xffff);
9a799d71 1719
735c35af
DS		 1720 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1721 if (status) {
9a799d71 1722 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1723 return status;
9a799d71
AK		 1724 }
1725
735c35af
DS		 1726 /* Verify read checksum from EEPROM is the same as
1727 * calculated checksum
1728 */
1729 if (read_checksum != checksum)
1730 status = IXGBE_ERR_EEPROM_CHECKSUM;
1731
1732 /* If the user cares, return the calculated checksum */
1733 if (checksum_val)
1734 *checksum_val = checksum;
1735
9a799d71
AK		 1736 return status;
1737}
1738
c44ade9e
JB		 1739/**
1740 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1741 * @hw: pointer to hardware structure
1742 **/
1743s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1744{
1745 s32 status;
1746 u16 checksum;
1747
1748 /*
1749 * Read the first word from the EEPROM. If this times out or fails, do
1750 * not continue or we could be in for a very long wait while every
1751 * EEPROM read fails
1752 */
1753 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af 1754 if (status) {
c44ade9e 1755 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1756 return status;
c44ade9e
JB		 1757 }
1758
735c35af
DS		 1759 status = hw->eeprom.ops.calc_checksum(hw);
1760 if (status < 0)
1761 return status;
1762
1763 checksum = (u16)(status & 0xffff);
1764
1765 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1766
c44ade9e
JB		 1767 return status;
1768}
1769
9a799d71 1770/**
c44ade9e 1771 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1772 * @hw: pointer to hardware structure
9a799d71 1773 * @index: Receive address register to write
c44ade9e
JB		 1774 * @addr: Address to put into receive address register
1775 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1776 * @enable_addr: set flag that address is active
1777 *
1778 * Puts an ethernet address into a receive address register.
1779 **/
c44ade9e 1780s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 1781 u32 enable_addr)
9a799d71
AK		 1782{
1783 u32 rar_low, rar_high;
c44ade9e
JB		 1784 u32 rar_entries = hw->mac.num_rar_entries;
1785
c700f4e6
ET		 1786 /* Make sure we are using a valid rar index range */
1787 if (index >= rar_entries) {
1788 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1789 return IXGBE_ERR_INVALID_ARGUMENT;
1790 }
1791
c44ade9e
JB		 1792 /* setup VMDq pool selection before this RAR gets enabled */
1793 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1794
c700f4e6
ET		 1795 /*
1796 * HW expects these in little endian so we reverse the byte
1797 * order from network order (big endian) to little endian
1798 */
1799 rar_low = ((u32)addr[0] |
1800 ((u32)addr[1] << 8) |
1801 ((u32)addr[2] << 16) |
1802 ((u32)addr[3] << 24));
1803 /*
1804 * Some parts put the VMDq setting in the extra RAH bits,
1805 * so save everything except the lower 16 bits that hold part
1806 * of the address and the address valid bit.
1807 */
1808 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1809 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1810 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1811
c700f4e6
ET		 1812 if (enable_addr != 0)
1813 rar_high |= IXGBE_RAH_AV;
9a799d71 1814
c700f4e6
ET		 1815 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1816 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1817
1818 return 0;
1819}
1820
1821/**
1822 * ixgbe_clear_rar_generic - Remove Rx address register
1823 * @hw: pointer to hardware structure
1824 * @index: Receive address register to write
1825 *
1826 * Clears an ethernet address from a receive address register.
1827 **/
1828s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1829{
1830 u32 rar_high;
1831 u32 rar_entries = hw->mac.num_rar_entries;
1832
1833 /* Make sure we are using a valid rar index range */
c700f4e6 1834 if (index >= rar_entries) {
c44ade9e 1835 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1836 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1837 }
1838
c700f4e6
ET		 1839 /*
1840 * Some parts put the VMDq setting in the extra RAH bits,
1841 * so save everything except the lower 16 bits that hold part
1842 * of the address and the address valid bit.
1843 */
1844 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1845 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1846
1847 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1848 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1849
c44ade9e
JB		 1850 /* clear VMDq pool/queue selection for this RAR */
1851 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1852
1853 return 0;
1854}
1855
c44ade9e
JB		 1856/**
1857 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1858 * @hw: pointer to hardware structure
1859 *
1860 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1861 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1862 * the receiver is in reset when the routine is called.
1863 **/
c44ade9e 1864s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1865{
1866 u32 i;
2c5645cf 1867 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1868
1869 /*
1870 * If the current mac address is valid, assume it is a software override
1871 * to the permanent address.
1872 * Otherwise, use the permanent address from the eeprom.
1873 */
f8ebc683 1874 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1875 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1876 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1877
ce7194d8 1878 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1879 } else {
1880 /* Setup the receive address. */
1881 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1882 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1883
c44ade9e 1884 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1885
1886 /* clear VMDq pool/queue selection for RAR 0 */
1887 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1888 }
c44ade9e 1889 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1890
1891 hw->addr_ctrl.rar_used_count = 1;
1892
1893 /* Zero out the other receive addresses. */
c44ade9e 1894 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1895 for (i = 1; i < rar_entries; i++) {
1896 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1897 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1898 }
1899
1900 /* Clear the MTA */
9a799d71
AK		 1901 hw->addr_ctrl.mta_in_use = 0;
1902 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1903
1904 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1905 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1906 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1907
c44ade9e
JB		 1908 if (hw->mac.ops.init_uta_tables)
1909 hw->mac.ops.init_uta_tables(hw);
1910
9a799d71
AK		 1911 return 0;
1912}
1913
1914/**
1915 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1916 * @hw: pointer to hardware structure
1917 * @mc_addr: the multicast address
1918 *
1919 * Extracts the 12 bits, from a multicast address, to determine which
1920 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1921 * incoming rx multicast addresses, to determine the bit-vector to check in
1922 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1923 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1924 * to mc_filter_type.
1925 **/
1926static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1927{
1928 u32 vector = 0;
1929
1930 switch (hw->mac.mc_filter_type) {
b4617240 1931 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1932 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1933 break;
b4617240 1934 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1935 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1936 break;
b4617240 1937 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1938 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1939 break;
b4617240 1940 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1941 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1942 break;
b4617240 1943 default: /* Invalid mc_filter_type */
9a799d71
AK		 1944 hw_dbg(hw, "MC filter type param set incorrectly\n");
1945 break;
1946 }
1947
1948 /* vector can only be 12-bits or boundary will be exceeded */
1949 vector &= 0xFFF;
1950 return vector;
1951}
1952
1953/**
1954 * ixgbe_set_mta - Set bit-vector in multicast table
1955 * @hw: pointer to hardware structure
1956 * @hash_value: Multicast address hash value
1957 *
1958 * Sets the bit-vector in the multicast table.
1959 **/
1960static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1961{
1962 u32 vector;
1963 u32 vector_bit;
1964 u32 vector_reg;
9a799d71
AK		 1965
1966 hw->addr_ctrl.mta_in_use++;
1967
1968 vector = ixgbe_mta_vector(hw, mc_addr);
1969 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1970
1971 /*
1972 * The MTA is a register array of 128 32-bit registers. It is treated
1973 * like an array of 4096 bits. We want to set bit
1974 * BitArray[vector_value]. So we figure out what register the bit is
1975 * in, read it, OR in the new bit, then write back the new value. The
1976 * register is determined by the upper 7 bits of the vector value and
1977 * the bit within that register are determined by the lower 5 bits of
1978 * the value.
1979 */
1980 vector_reg = (vector >> 5) & 0x7F;
1981 vector_bit = vector & 0x1F;
80960ab0 1982 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1983}
1984
9a799d71 1985/**
c44ade9e 1986 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1987 * @hw: pointer to hardware structure
2853eb89 1988 * @netdev: pointer to net device structure
9a799d71
AK		 1989 *
1990 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1991 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1992 * registers for the first multicast addresses, and hashes the rest into the
1993 * multicast table.
1994 **/
2853eb89
JP		 1995s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1996 struct net_device *netdev)
9a799d71 1997{
22bedad3 1998 struct netdev_hw_addr *ha;
9a799d71 1999 u32 i;
9a799d71
AK		 2000
2001 /*
2002 * Set the new number of MC addresses that we are being requested to
2003 * use.
2004 */
2853eb89 2005 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2006 hw->addr_ctrl.mta_in_use = 0;
2007
80960ab0 2008 /* Clear mta_shadow */
9a799d71 2009 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2010 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2011
80960ab0 2012 /* Update mta shadow */
22bedad3 2013 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2014 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2015 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2016 }
2017
2018 /* Enable mta */
80960ab0
ET		 2019 for (i = 0; i < hw->mac.mcft_size; i++)
2020 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2021 hw->mac.mta_shadow[i]);
2022
9a799d71
AK		 2023 if (hw->addr_ctrl.mta_in_use > 0)
2024 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
e7cf745b 2025 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2026
c44ade9e 2027 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2028 return 0;
2029}
2030
2031/**
c44ade9e 2032 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2033 * @hw: pointer to hardware structure
2034 *
c44ade9e 2035 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2036 **/
c44ade9e 2037s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2038{
c44ade9e 2039 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2040
c44ade9e
JB		 2041 if (a->mta_in_use > 0)
2042 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
e7cf745b 2043 hw->mac.mc_filter_type);
9a799d71
AK		 2044
2045 return 0;
2046}
2047
2048/**
c44ade9e 2049 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2050 * @hw: pointer to hardware structure
9a799d71 2051 *
c44ade9e 2052 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2053 **/
c44ade9e 2054s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2055{
c44ade9e 2056 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2057
c44ade9e
JB		 2058 if (a->mta_in_use > 0)
2059 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2060
2061 return 0;
2062}
2063
11afc1b1 2064/**
620fa036 2065 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2066 * @hw: pointer to hardware structure
11afc1b1
PW		 2067 *
2068 * Enable flow control according to the current settings.
2069 **/
041441d0 2070s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1 2071{
620fa036 2072 u32 mflcn_reg, fccfg_reg;
11afc1b1 2073 u32 reg;
16b61beb 2074 u32 fcrtl, fcrth;
041441d0 2075 int i;
70b77628 2076
e5776620 2077 /* Validate the water mark configuration. */
e90dd264
MR		 2078 if (!hw->fc.pause_time)
2079 return IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2080
e5776620
JK		 2081 /* Low water mark of zero causes XOFF floods */
2082 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2083 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2084 hw->fc.high_water[i]) {
2085 if (!hw->fc.low_water[i] ||
2086 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2087 hw_dbg(hw, "Invalid water mark configuration\n");
e90dd264 2088 return IXGBE_ERR_INVALID_LINK_SETTINGS;
e5776620
JK		 2089 }
2090 }
2091 }
2092
620fa036 2093 /* Negotiate the fc mode to use */
786e9a5f 2094 ixgbe_fc_autoneg(hw);
11afc1b1 2095
620fa036 2096 /* Disable any previous flow control settings */
11afc1b1 2097 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2098 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2099
2100 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2101 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2102
2103 /*
2104 * The possible values of fc.current_mode are:
2105 * 0: Flow control is completely disabled
2106 * 1: Rx flow control is enabled (we can receive pause frames,
2107 * but not send pause frames).
bb3daa4a
PW		 2108 * 2: Tx flow control is enabled (we can send pause frames but
2109 * we do not support receiving pause frames).
11afc1b1
PW		 2110 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2111 * other: Invalid.
2112 */
2113 switch (hw->fc.current_mode) {
2114 case ixgbe_fc_none:
620fa036
MC		 2115 /*
2116 * Flow control is disabled by software override or autoneg.
2117 * The code below will actually disable it in the HW.
2118 */
11afc1b1
PW		 2119 break;
2120 case ixgbe_fc_rx_pause:
2121 /*
2122 * Rx Flow control is enabled and Tx Flow control is
2123 * disabled by software override. Since there really
2124 * isn't a way to advertise that we are capable of RX
2125 * Pause ONLY, we will advertise that we support both
2126 * symmetric and asymmetric Rx PAUSE. Later, we will
2127 * disable the adapter's ability to send PAUSE frames.
2128 */
2129 mflcn_reg |= IXGBE_MFLCN_RFCE;
2130 break;
2131 case ixgbe_fc_tx_pause:
2132 /*
2133 * Tx Flow control is enabled, and Rx Flow control is
2134 * disabled by software override.
2135 */
2136 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2137 break;
2138 case ixgbe_fc_full:
2139 /* Flow control (both Rx and Tx) is enabled by SW override. */
2140 mflcn_reg |= IXGBE_MFLCN_RFCE;
2141 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2142 break;
2143 default:
2144 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 2145 return IXGBE_ERR_CONFIG;
11afc1b1
PW		 2146 }
2147
620fa036 2148 /* Set 802.3x based flow control settings. */
2132d381 2149 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2150 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2151 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2152
041441d0
AD		 2153 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2154 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2155 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2156 hw->fc.high_water[i]) {
e5776620 2157 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
041441d0
AD		 2158 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2159 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2160 } else {
2161 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2162 /*
2163 * In order to prevent Tx hangs when the internal Tx
2164 * switch is enabled we must set the high water mark
2165 * to the maximum FCRTH value. This allows the Tx
2166 * switch to function even under heavy Rx workloads.
2167 */
2168 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2169 }
11afc1b1 2170
041441d0
AD		 2171 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2172 }
16b61beb 2173
11afc1b1 2174 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2175 reg = hw->fc.pause_time * 0x00010001;
2176 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2177 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2178
2179 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1 2180
e90dd264 2181 return 0;
11afc1b1
PW		 2182}
2183
0ecc061d 2184/**
67a79df2 2185 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2186 * @hw: pointer to hardware structure
67a79df2
AD		 2187 * @adv_reg: flow control advertised settings
2188 * @lp_reg: link partner's flow control settings
2189 * @adv_sym: symmetric pause bit in advertisement
2190 * @adv_asm: asymmetric pause bit in advertisement
2191 * @lp_sym: symmetric pause bit in link partner advertisement
2192 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2193 *
67a79df2
AD		 2194 * Find the intersection between advertised settings and link partner's
2195 * advertised settings
0ecc061d 2196 **/
67a79df2
AD		 2197static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2198 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2199{
67a79df2
AD		 2200 if ((!(adv_reg)) || (!(lp_reg)))
2201 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2202
67a79df2
AD		 2203 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2204 /*
2205 * Now we need to check if the user selected Rx ONLY
2206 * of pause frames. In this case, we had to advertise
2207 * FULL flow control because we could not advertise RX
2208 * ONLY. Hence, we must now check to see if we need to
2209 * turn OFF the TRANSMISSION of PAUSE frames.
2210 */
2211 if (hw->fc.requested_mode == ixgbe_fc_full) {
2212 hw->fc.current_mode = ixgbe_fc_full;
2213 hw_dbg(hw, "Flow Control = FULL.\n");
2214 } else {
2215 hw->fc.current_mode = ixgbe_fc_rx_pause;
2216 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2217 }
2218 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2219 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2220 hw->fc.current_mode = ixgbe_fc_tx_pause;
2221 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2222 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2223 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2224 hw->fc.current_mode = ixgbe_fc_rx_pause;
2225 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2226 } else {
67a79df2
AD		 2227 hw->fc.current_mode = ixgbe_fc_none;
2228 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2229 }
67a79df2 2230 return 0;
0b0c2b31
ET		 2231}
2232
2233/**
2234 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2235 * @hw: pointer to hardware structure
2236 *
2237 * Enable flow control according on 1 gig fiber.
2238 **/
2239static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2240{
2241 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
e90dd264 2242 s32 ret_val;
539e5f02
PWJ		 2243
2244 /*
2245 * On multispeed fiber at 1g, bail out if
2246 * - link is up but AN did not complete, or if
2247 * - link is up and AN completed but timed out
2248 */
0b0c2b31
ET		 2249
2250 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2251 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2252 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
e90dd264 2253 return IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02 2254
0b0c2b31
ET		 2255 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2256 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2257
2258 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2259 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2260 IXGBE_PCS1GANA_ASM_PAUSE,
2261 IXGBE_PCS1GANA_SYM_PAUSE,
2262 IXGBE_PCS1GANA_ASM_PAUSE);
2263
0b0c2b31
ET		 2264 return ret_val;
2265}
2266
2267/**
2268 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2269 * @hw: pointer to hardware structure
2270 *
2271 * Enable flow control according to IEEE clause 37.
2272 **/
2273static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2274{
2275 u32 links2, anlp1_reg, autoc_reg, links;
e90dd264 2276 s32 ret_val;
0b0c2b31 2277
9bbe3a57 2278 /*
0b0c2b31
ET		 2279 * On backplane, bail out if
2280 * - backplane autoneg was not completed, or if
2281 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2282 */
0b0c2b31 2283 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2284 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
e90dd264 2285 return IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57 2286
0b0c2b31
ET		 2287 if (hw->mac.type == ixgbe_mac_82599EB) {
2288 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2289 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
e90dd264 2290 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2291 }
0ecc061d 2292 /*
0b0c2b31 2293 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2294 * local flow control settings accordingly
2295 */
0b0c2b31
ET		 2296 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2297 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2298
0b0c2b31
ET		 2299 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2300 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2301 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2302
0b0c2b31
ET		 2303 return ret_val;
2304}
2305
2306/**
2307 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2308 * @hw: pointer to hardware structure
2309 *
2310 * Enable flow control according to IEEE clause 37.
2311 **/
2312static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2313{
2314 u16 technology_ability_reg = 0;
2315 u16 lp_technology_ability_reg = 0;
2316
2317 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2318 MDIO_MMD_AN,
2319 &technology_ability_reg);
2320 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2321 MDIO_MMD_AN,
2322 &lp_technology_ability_reg);
2323
2324 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2325 (u32)lp_technology_ability_reg,
2326 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2327 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2328}
2329
2330/**
67a79df2 2331 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2332 * @hw: pointer to hardware structure
2333 *
67a79df2
AD		 2334 * Compares our advertised flow control capabilities to those advertised by
2335 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2336 **/
67a79df2 2337void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2338{
67a79df2
AD		 2339 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2340 ixgbe_link_speed speed;
2341 bool link_up;
11afc1b1
PW		 2342
2343 /*
67a79df2
AD		 2344 * AN should have completed when the cable was plugged in.
2345 * Look for reasons to bail out. Bail out if:
2346 * - FC autoneg is disabled, or if
2347 * - link is not up.
2348 *
2349 * Since we're being called from an LSC, link is already known to be up.
2350 * So use link_up_wait_to_complete=false.
11afc1b1 2351 */
67a79df2 2352 if (hw->fc.disable_fc_autoneg)
620fa036 2353 goto out;
11afc1b1 2354
67a79df2
AD		 2355 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2356 if (!link_up)
11afc1b1 2357 goto out;
0b0c2b31
ET		 2358
2359 switch (hw->phy.media_type) {
67a79df2 2360 /* Autoneg flow control on fiber adapters */
0b0c2b31 2361 case ixgbe_media_type_fiber:
67a79df2
AD		 2362 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2363 ret_val = ixgbe_fc_autoneg_fiber(hw);
2364 break;
2365
2366 /* Autoneg flow control on backplane adapters */
0b0c2b31 2367 case ixgbe_media_type_backplane:
67a79df2 2368 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2369 break;
2370
67a79df2 2371 /* Autoneg flow control on copper adapters */
0b0c2b31 2372 case ixgbe_media_type_copper:
73d80953 2373 if (ixgbe_device_supports_autoneg_fc(hw))
67a79df2 2374 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2375 break;
2376
2377 default:
620fa036 2378 break;
0b0c2b31 2379 }
539e5f02 2380
11afc1b1 2381out:
67a79df2
AD		 2382 if (ret_val == 0) {
2383 hw->fc.fc_was_autonegged = true;
2384 } else {
2385 hw->fc.fc_was_autonegged = false;
2386 hw->fc.current_mode = hw->fc.requested_mode;
2387 }
11afc1b1
PW		 2388}
2389
1f86c983
DS		 2390/**
2391 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2392 * @hw: pointer to hardware structure
2393 *
2394 * System-wide timeout range is encoded in PCIe Device Control2 register.
2395 *
2396 * Add 10% to specified maximum and return the number of times to poll for
2397 * completion timeout, in units of 100 microsec. Never return less than
2398 * 800 = 80 millisec.
2399 **/
2400static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2401{
1f86c983
DS		 2402 s16 devctl2;
2403 u32 pollcnt;
2404
0d7c6e00 2405 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
1f86c983
DS		 2406 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2407
2408 switch (devctl2) {
2409 case IXGBE_PCIDEVCTRL2_65_130ms:
2410 pollcnt = 1300; /* 130 millisec */
2411 break;
2412 case IXGBE_PCIDEVCTRL2_260_520ms:
2413 pollcnt = 5200; /* 520 millisec */
2414 break;
2415 case IXGBE_PCIDEVCTRL2_1_2s:
2416 pollcnt = 20000; /* 2 sec */
2417 break;
2418 case IXGBE_PCIDEVCTRL2_4_8s:
2419 pollcnt = 80000; /* 8 sec */
2420 break;
2421 case IXGBE_PCIDEVCTRL2_17_34s:
2422 pollcnt = 34000; /* 34 sec */
2423 break;
2424 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2425 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2426 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2427 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2428 default:
2429 pollcnt = 800; /* 80 millisec minimum */
2430 break;
2431 }
2432
2433 /* add 10% to spec maximum */
2434 return (pollcnt * 11) / 10;
2435}
2436
9a799d71
AK		 2437/**
2438 * ixgbe_disable_pcie_master - Disable PCI-express master access
2439 * @hw: pointer to hardware structure
2440 *
2441 * Disables PCI-Express master access and verifies there are no pending
2442 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2443 * bit hasn't caused the master requests to be disabled, else 0
2444 * is returned signifying master requests disabled.
2445 **/
ff9d1a5a 2446static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2447{
1f86c983 2448 u32 i, poll;
ff9d1a5a
ET		 2449 u16 value;
2450
2451 /* Always set this bit to ensure any future transactions are blocked */
2452 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2453
ff9d1a5a 2454 /* Exit if master requests are blocked */
14438464
MR		 2455 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2456 ixgbe_removed(hw->hw_addr))
e90dd264 2457 return 0;
9a799d71 2458
ff9d1a5a 2459 /* Poll for master request bit to clear */
9a799d71 2460 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2461 udelay(100);
ff9d1a5a 2462 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
e90dd264 2463 return 0;
a4297dc2
ET		 2464 }
2465
ff9d1a5a
ET		 2466 /*
2467 * Two consecutive resets are required via CTRL.RST per datasheet
2468 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2469 * of this need. The first reset prevents new master requests from
2470 * being issued by our device. We then must wait 1usec or more for any
2471 * remaining completions from the PCIe bus to trickle in, and then reset
2472 * again to clear out any effects they may have had on our device.
2473 */
a4297dc2 2474 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2475 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2476
2477 /*
2478 * Before proceeding, make sure that the PCIe block does not have
2479 * transactions pending.
2480 */
1f86c983
DS		 2481 poll = ixgbe_pcie_timeout_poll(hw);
2482 for (i = 0; i < poll; i++) {
9a799d71 2483 udelay(100);
14438464
MR		 2484 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2485 if (ixgbe_removed(hw->hw_addr))
e90dd264 2486 return 0;
ff9d1a5a 2487 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
e90dd264 2488 return 0;
9a799d71
AK		 2489 }
2490
ff9d1a5a 2491 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
e90dd264 2492 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
9a799d71
AK		 2493}
2494
9a799d71 2495/**
c44ade9e 2496 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2497 * @hw: pointer to hardware structure
c44ade9e 2498 * @mask: Mask to specify which semaphore to acquire
9a799d71 2499 *
da74cd4a 2500 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2501 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2502 **/
030eaece 2503s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71 2504{
674c18b2 2505 u32 gssr = 0;
9a799d71
AK		 2506 u32 swmask = mask;
2507 u32 fwmask = mask << 5;
674c18b2
ET		 2508 u32 timeout = 200;
2509 u32 i;
9a799d71 2510
674c18b2 2511 for (i = 0; i < timeout; i++) {
dbf893ee 2512 /*
674c18b2
ET		 2513 * SW NVM semaphore bit is used for access to all
2514 * SW_FW_SYNC bits (not just NVM)
dbf893ee 2515 */
9a799d71 2516 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2517 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2518
2519 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
674c18b2
ET		 2520 if (!(gssr & (fwmask | swmask))) {
2521 gssr |= swmask;
2522 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2523 ixgbe_release_eeprom_semaphore(hw);
2524 return 0;
2525 } else {
2526 /* Resource is currently in use by FW or SW */
2527 ixgbe_release_eeprom_semaphore(hw);
2528 usleep_range(5000, 10000);
2529 }
9a799d71
AK		 2530 }
2531
674c18b2
ET		 2532 /* If time expired clear the bits holding the lock and retry */
2533 if (gssr & (fwmask | swmask))
2534 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
9a799d71 2535
674c18b2
ET		 2536 usleep_range(5000, 10000);
2537 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2538}
2539
2540/**
2541 * ixgbe_release_swfw_sync - Release SWFW semaphore
2542 * @hw: pointer to hardware structure
c44ade9e 2543 * @mask: Mask to specify which semaphore to release
9a799d71 2544 *
da74cd4a 2545 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2546 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2547 **/
030eaece 2548void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71
AK		 2549{
2550 u32 gssr;
2551 u32 swmask = mask;
2552
2553 ixgbe_get_eeprom_semaphore(hw);
2554
2555 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2556 gssr &= ~swmask;
2557 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2558
2559 ixgbe_release_eeprom_semaphore(hw);
2560}
2561
429d6a3b
DS		 2562/**
2563 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2564 * @hw: pointer to hardware structure
2565 * @reg_val: Value we read from AUTOC
2566 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2567 * true in this the generic case.
2568 *
2569 * The default case requires no protection so just to the register read.
2570 **/
2571s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2572{
2573 *locked = false;
2574 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2575 return 0;
2576}
2577
2578/**
2579 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2580 * @hw: pointer to hardware structure
2581 * @reg_val: value to write to AUTOC
2582 * @locked: bool to indicate whether the SW/FW lock was already taken by
2583 * previous read.
2584 **/
2585s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2586{
2587 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2588 return 0;
2589}
2590
d2f5e7f3
AS		 2591/**
2592 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2593 * @hw: pointer to hardware structure
2594 *
2595 * Stops the receive data path and waits for the HW to internally
2596 * empty the Rx security block.
2597 **/
2598s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2599{
2600#define IXGBE_MAX_SECRX_POLL 40
2601 int i;
2602 int secrxreg;
2603
2604 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2605 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2606 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2607 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2608 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2609 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2610 break;
2611 else
2612 /* Use interrupt-safe sleep just in case */
db76ad47 2613 udelay(1000);
d2f5e7f3
AS		 2614 }
2615
2616 /* For informational purposes only */
2617 if (i >= IXGBE_MAX_SECRX_POLL)
6ec1b71f 2618 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
d2f5e7f3
AS		 2619
2620 return 0;
2621
2622}
2623
2624/**
2625 * ixgbe_enable_rx_buff - Enables the receive data path
2626 * @hw: pointer to hardware structure
2627 *
2628 * Enables the receive data path
2629 **/
2630s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2631{
2632 int secrxreg;
2633
2634 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2635 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2636 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2637 IXGBE_WRITE_FLUSH(hw);
2638
2639 return 0;
2640}
2641
11afc1b1
PW		 2642/**
2643 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2644 * @hw: pointer to hardware structure
2645 * @regval: register value to write to RXCTRL
2646 *
2647 * Enables the Rx DMA unit
2648 **/
2649s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2650{
1f9ac57c
DS		 2651 if (regval & IXGBE_RXCTRL_RXEN)
2652 hw->mac.ops.enable_rx(hw);
2653 else
2654 hw->mac.ops.disable_rx(hw);
11afc1b1
PW		 2655
2656 return 0;
2657}
87c12017
PW		 2658
2659/**
2660 * ixgbe_blink_led_start_generic - Blink LED based on index.
2661 * @hw: pointer to hardware structure
2662 * @index: led number to blink
2663 **/
2664s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2665{
2666 ixgbe_link_speed speed = 0;
3db1cd5c 2667 bool link_up = false;
87c12017
PW		 2668 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2669 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2670 bool locked = false;
e90dd264 2671 s32 ret_val;
87c12017
PW		 2672
2673 /*
2674 * Link must be up to auto-blink the LEDs;
2675 * Force it if link is down.
2676 */
2677 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2678
2679 if (!link_up) {
429d6a3b 2680 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2681 if (ret_val)
e90dd264 2682 return ret_val;
d7bbcd32 2683
50ac58ba 2684 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2685 autoc_reg |= IXGBE_AUTOC_FLU;
429d6a3b
DS		 2686
2687 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2688 if (ret_val)
e90dd264 2689 return ret_val;
429d6a3b 2690
945a5151 2691 IXGBE_WRITE_FLUSH(hw);
d7bbcd32 2692
032b4325 2693 usleep_range(10000, 20000);
87c12017
PW		 2694 }
2695
2696 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2697 led_reg |= IXGBE_LED_BLINK(index);
2698 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2699 IXGBE_WRITE_FLUSH(hw);
2700
e90dd264 2701 return 0;
87c12017
PW		 2702}
2703
2704/**
2705 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2706 * @hw: pointer to hardware structure
2707 * @index: led number to stop blinking
2708 **/
2709s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2710{
429d6a3b 2711 u32 autoc_reg = 0;
87c12017 2712 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2713 bool locked = false;
e90dd264 2714 s32 ret_val;
d7bbcd32 2715
429d6a3b 2716 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2717 if (ret_val)
e90dd264 2718 return ret_val;
87c12017
PW		 2719
2720 autoc_reg &= ~IXGBE_AUTOC_FLU;
2721 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2722
429d6a3b 2723 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2724 if (ret_val)
e90dd264 2725 return ret_val;
d7bbcd32 2726
87c12017
PW		 2727 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2728 led_reg &= ~IXGBE_LED_BLINK(index);
2729 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2730 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2731 IXGBE_WRITE_FLUSH(hw);
2732
e90dd264 2733 return 0;
87c12017 2734}
21ce849b
MC		 2735
2736/**
2737 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2738 * @hw: pointer to hardware structure
2739 * @san_mac_offset: SAN MAC address offset
2740 *
2741 * This function will read the EEPROM location for the SAN MAC address
2742 * pointer, and returns the value at that location. This is used in both
2743 * get and set mac_addr routines.
2744 **/
2745static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
e7cf745b 2746 u16 *san_mac_offset)
21ce849b 2747{
be0c27b4
MR		 2748 s32 ret_val;
2749
21ce849b
MC		 2750 /*
2751 * First read the EEPROM pointer to see if the MAC addresses are
2752 * available.
2753 */
be0c27b4
MR		 2754 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2755 san_mac_offset);
2756 if (ret_val)
2757 hw_err(hw, "eeprom read at offset %d failed\n",
2758 IXGBE_SAN_MAC_ADDR_PTR);
21ce849b 2759
be0c27b4 2760 return ret_val;
21ce849b
MC		 2761}
2762
2763/**
2764 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2765 * @hw: pointer to hardware structure
2766 * @san_mac_addr: SAN MAC address
2767 *
2768 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2769 * per-port, so set_lan_id() must be called before reading the addresses.
2770 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2771 * upon for non-SFP connections, so we must call it here.
2772 **/
2773s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2774{
2775 u16 san_mac_data, san_mac_offset;
2776 u8 i;
be0c27b4 2777 s32 ret_val;
21ce849b
MC		 2778
2779 /*
2780 * First read the EEPROM pointer to see if the MAC addresses are
2781 * available. If they're not, no point in calling set_lan_id() here.
2782 */
be0c27b4
MR		 2783 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2784 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
21ce849b 2785
be0c27b4 2786 goto san_mac_addr_clr;
21ce849b
MC		 2787
2788 /* make sure we know which port we need to program */
2789 hw->mac.ops.set_lan_id(hw);
2790 /* apply the port offset to the address offset */
2791 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
e7cf745b 2792 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
21ce849b 2793 for (i = 0; i < 3; i++) {
be0c27b4
MR		 2794 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2795 &san_mac_data);
2796 if (ret_val) {
2797 hw_err(hw, "eeprom read at offset %d failed\n",
2798 san_mac_offset);
2799 goto san_mac_addr_clr;
2800 }
21ce849b
MC		 2801 san_mac_addr[i * 2] = (u8)(san_mac_data);
2802 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2803 san_mac_offset++;
2804 }
21ce849b 2805 return 0;
be0c27b4
MR		 2806
2807san_mac_addr_clr:
2808 /* No addresses available in this EEPROM. It's not necessarily an
2809 * error though, so just wipe the local address and return.
2810 */
2811 for (i = 0; i < 6; i++)
2812 san_mac_addr[i] = 0xFF;
2813 return ret_val;
21ce849b
MC		 2814}
2815
2816/**
2817 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2818 * @hw: pointer to hardware structure
2819 *
2820 * Read PCIe configuration space, and get the MSI-X vector count from
2821 * the capabilities table.
2822 **/
71161302 2823u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b 2824{
e90dd264 2825 u16 msix_count;
71161302
ET		 2826 u16 max_msix_count;
2827 u16 pcie_offset;
2828
2829 switch (hw->mac.type) {
2830 case ixgbe_mac_82598EB:
2831 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2832 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2833 break;
2834 case ixgbe_mac_82599EB:
2835 case ixgbe_mac_X540:
9a75a1ac
DS		 2836 case ixgbe_mac_X550:
2837 case ixgbe_mac_X550EM_x:
71161302
ET		 2838 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2839 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2840 break;
2841 default:
e90dd264 2842 return 1;
71161302
ET		 2843 }
2844
14438464
MR		 2845 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2846 if (ixgbe_removed(hw->hw_addr))
2847 msix_count = 0;
21ce849b
MC		 2848 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2849
71161302 2850 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2851 msix_count++;
2852
71161302
ET		 2853 if (msix_count > max_msix_count)
2854 msix_count = max_msix_count;
2855
21ce849b
MC		 2856 return msix_count;
2857}
2858
2859/**
2860 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2861 * @hw: pointer to hardware struct
2862 * @rar: receive address register index to disassociate
2863 * @vmdq: VMDq pool index to remove from the rar
2864 **/
2865s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2866{
2867 u32 mpsar_lo, mpsar_hi;
2868 u32 rar_entries = hw->mac.num_rar_entries;
2869
c700f4e6
ET		 2870 /* Make sure we are using a valid rar index range */
2871 if (rar >= rar_entries) {
2872 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2873 return IXGBE_ERR_INVALID_ARGUMENT;
2874 }
21ce849b 2875
c700f4e6
ET		 2876 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2877 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2878
19458bd4 2879 if (ixgbe_removed(hw->hw_addr))
e90dd264 2880 return 0;
19458bd4 2881
c700f4e6 2882 if (!mpsar_lo && !mpsar_hi)
e90dd264 2883 return 0;
21ce849b 2884
c700f4e6
ET		 2885 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2886 if (mpsar_lo) {
2887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2888 mpsar_lo = 0;
2889 }
2890 if (mpsar_hi) {
2891 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2892 mpsar_hi = 0;
2893 }
2894 } else if (vmdq < 32) {
2895 mpsar_lo &= ~(1 << vmdq);
2896 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2897 } else {
c700f4e6
ET		 2898 mpsar_hi &= ~(1 << (vmdq - 32));
2899 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2900 }
2901
c700f4e6
ET		 2902 /* was that the last pool using this rar? */
2903 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2904 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2905 return 0;
2906}
2907
2908/**
2909 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2910 * @hw: pointer to hardware struct
2911 * @rar: receive address register index to associate with a VMDq index
2912 * @vmdq: VMDq pool index
2913 **/
2914s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2915{
2916 u32 mpsar;
2917 u32 rar_entries = hw->mac.num_rar_entries;
2918
c700f4e6
ET		 2919 /* Make sure we are using a valid rar index range */
2920 if (rar >= rar_entries) {
21ce849b 2921 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2922 return IXGBE_ERR_INVALID_ARGUMENT;
2923 }
2924
2925 if (vmdq < 32) {
2926 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2927 mpsar |= 1 << vmdq;
2928 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2929 } else {
2930 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2931 mpsar |= 1 << (vmdq - 32);
2932 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2933 }
2934 return 0;
2935}
2936
7fa7c9dc
AD		 2937/**
2938 * This function should only be involved in the IOV mode.
2939 * In IOV mode, Default pool is next pool after the number of
2940 * VFs advertized and not 0.
2941 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2942 *
2943 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2944 * @hw: pointer to hardware struct
2945 * @vmdq: VMDq pool index
2946 **/
2947s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2948{
2949 u32 rar = hw->mac.san_mac_rar_index;
2950
2951 if (vmdq < 32) {
2952 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2953 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2954 } else {
2955 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2956 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2957 }
2958
2959 return 0;
2960}
2961
21ce849b
MC		 2962/**
2963 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2964 * @hw: pointer to hardware structure
2965 **/
2966s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2967{
2968 int i;
2969
21ce849b
MC		 2970 for (i = 0; i < 128; i++)
2971 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2972
2973 return 0;
2974}
2975
2976/**
2977 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2978 * @hw: pointer to hardware structure
2979 * @vlan: VLAN id to write to VLAN filter
2980 *
2981 * return the VLVF index where this VLAN id should be placed
2982 *
2983 **/
5d5b7c39 2984static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2985{
2986 u32 bits = 0;
2987 u32 first_empty_slot = 0;
2988 s32 regindex;
2989
2990 /* short cut the special case */
2991 if (vlan == 0)
2992 return 0;
2993
2994 /*
2995 * Search for the vlan id in the VLVF entries. Save off the first empty
2996 * slot found along the way
2997 */
2998 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2999 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3000 if (!bits && !(first_empty_slot))
3001 first_empty_slot = regindex;
3002 else if ((bits & 0x0FFF) == vlan)
3003 break;
3004 }
3005
3006 /*
3007 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3008 * in the VLVF. Else use the first empty VLVF register for this
3009 * vlan id.
3010 */
3011 if (regindex >= IXGBE_VLVF_ENTRIES) {
3012 if (first_empty_slot)
3013 regindex = first_empty_slot;
3014 else {
3015 hw_dbg(hw, "No space in VLVF.\n");
3016 regindex = IXGBE_ERR_NO_SPACE;
3017 }
3018 }
3019
3020 return regindex;
3021}
3022
3023/**
3024 * ixgbe_set_vfta_generic - Set VLAN filter table
3025 * @hw: pointer to hardware structure
3026 * @vlan: VLAN id to write to VLAN filter
3027 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3028 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3029 *
3030 * Turn on/off specified VLAN in the VLAN filter table.
3031 **/
3032s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
e7cf745b 3033 bool vlan_on)
21ce849b
MC		 3034{
3035 s32 regindex;
3036 u32 bitindex;
3037 u32 vfta;
3038 u32 bits;
3039 u32 vt;
3040 u32 targetbit;
3041 bool vfta_changed = false;
3042
3043 if (vlan > 4095)
3044 return IXGBE_ERR_PARAM;
3045
3046 /*
3047 * this is a 2 part operation - first the VFTA, then the
3048 * VLVF and VLVFB if VT Mode is set
3049 * We don't write the VFTA until we know the VLVF part succeeded.
3050 */
3051
3052 /* Part 1
3053 * The VFTA is a bitstring made up of 128 32-bit registers
3054 * that enable the particular VLAN id, much like the MTA:
3055 * bits[11-5]: which register
3056 * bits[4-0]: which bit in the register
3057 */
3058 regindex = (vlan >> 5) & 0x7F;
3059 bitindex = vlan & 0x1F;
3060 targetbit = (1 << bitindex);
3061 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3062
3063 if (vlan_on) {
3064 if (!(vfta & targetbit)) {
3065 vfta |= targetbit;
3066 vfta_changed = true;
3067 }
3068 } else {
3069 if ((vfta & targetbit)) {
3070 vfta &= ~targetbit;
3071 vfta_changed = true;
3072 }
3073 }
3074
3075 /* Part 2
3076 * If VT Mode is set
3077 * Either vlan_on
3078 * make sure the vlan is in VLVF
3079 * set the vind bit in the matching VLVFB
3080 * Or !vlan_on
3081 * clear the pool bit and possibly the vind
3082 */
3083 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3084 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3085 s32 vlvf_index;
3086
3087 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3088 if (vlvf_index < 0)
3089 return vlvf_index;
3090
3091 if (vlan_on) {
3092 /* set the pool bit */
3093 if (vind < 32) {
3094 bits = IXGBE_READ_REG(hw,
3095 IXGBE_VLVFB(vlvf_index*2));
3096 bits |= (1 << vind);
3097 IXGBE_WRITE_REG(hw,
3098 IXGBE_VLVFB(vlvf_index*2),
3099 bits);
3100 } else {
3101 bits = IXGBE_READ_REG(hw,
3102 IXGBE_VLVFB((vlvf_index*2)+1));
3103 bits |= (1 << (vind-32));
3104 IXGBE_WRITE_REG(hw,
3105 IXGBE_VLVFB((vlvf_index*2)+1),
3106 bits);
3107 }
3108 } else {
3109 /* clear the pool bit */
3110 if (vind < 32) {
3111 bits = IXGBE_READ_REG(hw,
3112 IXGBE_VLVFB(vlvf_index*2));
3113 bits &= ~(1 << vind);
3114 IXGBE_WRITE_REG(hw,
3115 IXGBE_VLVFB(vlvf_index*2),
3116 bits);
3117 bits |= IXGBE_READ_REG(hw,
3118 IXGBE_VLVFB((vlvf_index*2)+1));
3119 } else {
3120 bits = IXGBE_READ_REG(hw,
3121 IXGBE_VLVFB((vlvf_index*2)+1));
3122 bits &= ~(1 << (vind-32));
3123 IXGBE_WRITE_REG(hw,
3124 IXGBE_VLVFB((vlvf_index*2)+1),
3125 bits);
3126 bits |= IXGBE_READ_REG(hw,
3127 IXGBE_VLVFB(vlvf_index*2));
3128 }
3129 }
3130
3131 /*
3132 * If there are still bits set in the VLVFB registers
3133 * for the VLAN ID indicated we need to see if the
3134 * caller is requesting that we clear the VFTA entry bit.
3135 * If the caller has requested that we clear the VFTA
3136 * entry bit but there are still pools/VFs using this VLAN
3137 * ID entry then ignore the request. We're not worried
3138 * about the case where we're turning the VFTA VLAN ID
3139 * entry bit on, only when requested to turn it off as
3140 * there may be multiple pools and/or VFs using the
3141 * VLAN ID entry. In that case we cannot clear the
3142 * VFTA bit until all pools/VFs using that VLAN ID have also
3143 * been cleared. This will be indicated by "bits" being
3144 * zero.
3145 */
3146 if (bits) {
3147 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3148 (IXGBE_VLVF_VIEN | vlan));
3149 if (!vlan_on) {
3150 /* someone wants to clear the vfta entry
3151 * but some pools/VFs are still using it.
3152 * Ignore it. */
3153 vfta_changed = false;
3154 }
63b64de3 3155 } else {
21ce849b 3156 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
63b64de3 3157 }
21ce849b
MC		 3158 }
3159
3160 if (vfta_changed)
3161 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3162
3163 return 0;
3164}
3165
3166/**
3167 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3168 * @hw: pointer to hardware structure
3169 *
3170 * Clears the VLAN filer table, and the VMDq index associated with the filter
3171 **/
3172s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3173{
3174 u32 offset;
3175
3176 for (offset = 0; offset < hw->mac.vft_size; offset++)
3177 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3178
3179 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3180 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3181 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3182 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3183 }
3184
3185 return 0;
3186}
3187
3188/**
3189 * ixgbe_check_mac_link_generic - Determine link and speed status
3190 * @hw: pointer to hardware structure
3191 * @speed: pointer to link speed
3192 * @link_up: true when link is up
3193 * @link_up_wait_to_complete: bool used to wait for link up or not
3194 *
3195 * Reads the links register to determine if link is up and the current speed
3196 **/
3197s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3198 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3199{
48de36c5 3200 u32 links_reg, links_orig;
21ce849b
MC		 3201 u32 i;
3202
48de36c5
ET		 3203 /* clear the old state */
3204 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3205
21ce849b 3206 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3207
3208 if (links_orig != links_reg) {
3209 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3210 links_orig, links_reg);
3211 }
3212
21ce849b
MC		 3213 if (link_up_wait_to_complete) {
3214 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3215 if (links_reg & IXGBE_LINKS_UP) {
3216 *link_up = true;
3217 break;
3218 } else {
3219 *link_up = false;
3220 }
3221 msleep(100);
3222 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3223 }
3224 } else {
3225 if (links_reg & IXGBE_LINKS_UP)
3226 *link_up = true;
3227 else
3228 *link_up = false;
3229 }
3230
9a75a1ac
DS		 3231 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3232 case IXGBE_LINKS_SPEED_10G_82599:
3233 if ((hw->mac.type >= ixgbe_mac_X550) &&
3234 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3235 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3236 else
3237 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3238 break;
3239 case IXGBE_LINKS_SPEED_1G_82599:
21ce849b 3240 *speed = IXGBE_LINK_SPEED_1GB_FULL;
9a75a1ac
DS		 3241 break;
3242 case IXGBE_LINKS_SPEED_100_82599:
3243 if ((hw->mac.type >= ixgbe_mac_X550) &&
3244 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3245 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3246 else
3247 *speed = IXGBE_LINK_SPEED_100_FULL;
3248 break;
3249 default:
63d778df 3250 *speed = IXGBE_LINK_SPEED_UNKNOWN;
9a75a1ac 3251 }
21ce849b 3252
21ce849b
MC		 3253 return 0;
3254}
a391f1d5
DS		 3255
3256/**
49ce9c2c 3257 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3258 * the EEPROM
3259 * @hw: pointer to hardware structure
3260 * @wwnn_prefix: the alternative WWNN prefix
3261 * @wwpn_prefix: the alternative WWPN prefix
3262 *
3263 * This function will read the EEPROM from the alternative SAN MAC address
3264 * block to check the support for the alternative WWNN/WWPN prefix support.
3265 **/
3266s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 3267 u16 *wwpn_prefix)
a391f1d5
DS		 3268{
3269 u16 offset, caps;
3270 u16 alt_san_mac_blk_offset;
3271
3272 /* clear output first */
3273 *wwnn_prefix = 0xFFFF;
3274 *wwpn_prefix = 0xFFFF;
3275
3276 /* check if alternative SAN MAC is supported */
be0c27b4
MR		 3277 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3278 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3279 goto wwn_prefix_err;
a391f1d5
DS		 3280
3281 if ((alt_san_mac_blk_offset == 0) ||
3282 (alt_san_mac_blk_offset == 0xFFFF))
e90dd264 3283 return 0;
a391f1d5
DS		 3284
3285 /* check capability in alternative san mac address block */
3286 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
be0c27b4
MR		 3287 if (hw->eeprom.ops.read(hw, offset, &caps))
3288 goto wwn_prefix_err;
a391f1d5 3289 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
e90dd264 3290 return 0;
a391f1d5
DS		 3291
3292 /* get the corresponding prefix for WWNN/WWPN */
3293 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
be0c27b4
MR		 3294 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3295 hw_err(hw, "eeprom read at offset %d failed\n", offset);
a391f1d5
DS		 3296
3297 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
be0c27b4
MR		 3298 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3299 goto wwn_prefix_err;
a391f1d5 3300
a391f1d5 3301 return 0;
be0c27b4
MR		 3302
3303wwn_prefix_err:
3304 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3305 return 0;
a391f1d5 3306}
a985b6c3
GR		 3307
3308/**
3309 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3310 * @hw: pointer to hardware structure
3311 * @enable: enable or disable switch for anti-spoofing
3312 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3313 *
3314 **/
3315void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3316{
3317 int j;
3318 int pf_target_reg = pf >> 3;
3319 int pf_target_shift = pf % 8;
3320 u32 pfvfspoof = 0;
3321
3322 if (hw->mac.type == ixgbe_mac_82598EB)
3323 return;
3324
3325 if (enable)
3326 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3327
3328 /*
3329 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3330 * MAC anti-spoof enables in each register array element.
3331 */
ef89e0a2 3332 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3333 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3334
a985b6c3
GR		 3335 /*
3336 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3337 * emulation mode NICs. Do not set the bits assigned to the PF
3338 */
3339 pfvfspoof &= (1 << pf_target_shift) - 1;
3340 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3341
3342 /*
3343 * Remaining pools belong to the PF so they do not need to have
3344 * anti-spoofing enabled.
a985b6c3 3345 */
ef89e0a2
AD		 3346 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3347 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3348}
3349
3350/**
3351 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3352 * @hw: pointer to hardware structure
3353 * @enable: enable or disable switch for VLAN anti-spoofing
3354 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3355 *
3356 **/
3357void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3358{
3359 int vf_target_reg = vf >> 3;
3360 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3361 u32 pfvfspoof;
3362
3363 if (hw->mac.type == ixgbe_mac_82598EB)
3364 return;
3365
3366 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3367 if (enable)
3368 pfvfspoof |= (1 << vf_target_shift);
3369 else
3370 pfvfspoof &= ~(1 << vf_target_shift);
3371 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3372}
b776d104
ET		 3373
3374/**
3375 * ixgbe_get_device_caps_generic - Get additional device capabilities
3376 * @hw: pointer to hardware structure
3377 * @device_caps: the EEPROM word with the extra device capabilities
3378 *
3379 * This function will read the EEPROM location for the device capabilities,
3380 * and return the word through device_caps.
3381 **/
3382s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3383{
3384 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3385
3386 return 0;
3387}
80605c65
JF		 3388
3389/**
3390 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3391 * @hw: pointer to hardware structure
3392 * @num_pb: number of packet buffers to allocate
3393 * @headroom: reserve n KB of headroom
3394 * @strategy: packet buffer allocation strategy
3395 **/
3396void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3397 int num_pb,
3398 u32 headroom,
3399 int strategy)
3400{
3401 u32 pbsize = hw->mac.rx_pb_size;
3402 int i = 0;
3403 u32 rxpktsize, txpktsize, txpbthresh;
3404
3405 /* Reserve headroom */
3406 pbsize -= headroom;
3407
3408 if (!num_pb)
3409 num_pb = 1;
3410
3411 /* Divide remaining packet buffer space amongst the number
3412 * of packet buffers requested using supplied strategy.
3413 */
3414 switch (strategy) {
3415 case (PBA_STRATEGY_WEIGHTED):
3416 /* pba_80_48 strategy weight first half of packet buffer with
3417 * 5/8 of the packet buffer space.
3418 */
3419 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3420 pbsize -= rxpktsize * (num_pb / 2);
3421 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3422 for (; i < (num_pb / 2); i++)
3423 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3424 /* Fall through to configure remaining packet buffers */
3425 case (PBA_STRATEGY_EQUAL):
3426 /* Divide the remaining Rx packet buffer evenly among the TCs */
3427 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3428 for (; i < num_pb; i++)
3429 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3430 break;
3431 default:
3432 break;
3433 }
3434
3435 /*
3436 * Setup Tx packet buffer and threshold equally for all TCs
3437 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3438 * 10 since the largest packet we support is just over 9K.
3439 */
3440 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3441 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3442 for (i = 0; i < num_pb; i++) {
3443 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3444 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3445 }
3446
3447 /* Clear unused TCs, if any, to zero buffer size*/
3448 for (; i < IXGBE_MAX_PB; i++) {
3449 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3450 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3451 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3452 }
3453}
9612de92
ET		 3454
3455/**
3456 * ixgbe_calculate_checksum - Calculate checksum for buffer
3457 * @buffer: pointer to EEPROM
3458 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3459 *
9612de92
ET		 3460 * Calculates the checksum for some buffer on a specified length. The
3461 * checksum calculated is returned.
3462 **/
3463static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3464{
3465 u32 i;
3466 u8 sum = 0;
3467
3468 if (!buffer)
3469 return 0;
3470
3471 for (i = 0; i < length; i++)
3472 sum += buffer[i];
3473
3474 return (u8) (0 - sum);
3475}
3476
3477/**
3478 * ixgbe_host_interface_command - Issue command to manageability block
3479 * @hw: pointer to the HW structure
3480 * @buffer: contains the command to write and where the return status will
3481 * be placed
c466d7a7 3482 * @length: length of buffer, must be multiple of 4 bytes
b48e4aa3
DS		 3483 * @timeout: time in ms to wait for command completion
3484 * @return_data: read and return data from the buffer (true) or not (false)
3485 * Needed because FW structures are big endian and decoding of
3486 * these fields can be 8 bit or 16 bit based on command. Decoding
3487 * is not easily understood without making a table of commands.
3488 * So we will leave this up to the caller to read back the data
3489 * in these cases.
9612de92
ET		 3490 *
3491 * Communicates with the manageability block. On success return 0
3492 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3493 **/
6a14ee0c
DS		 3494s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3495 u32 length, u32 timeout,
3496 bool return_data)
9612de92 3497{
b48e4aa3 3498 u32 hicr, i, bi, fwsts;
9612de92 3499 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
b48e4aa3 3500 u16 buf_len, dword_len;
9612de92 3501
b48e4aa3
DS		 3502 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3503 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
e90dd264 3504 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3505 }
3506
b48e4aa3
DS		 3507 /* Set bit 9 of FWSTS clearing FW reset indication */
3508 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3509 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3510
9612de92
ET		 3511 /* Check that the host interface is enabled. */
3512 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3513 if ((hicr & IXGBE_HICR_EN) == 0) {
3514 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
e90dd264 3515 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3516 }
3517
b48e4aa3
DS		 3518 /* Calculate length in DWORDs. We must be DWORD aligned */
3519 if ((length % (sizeof(u32))) != 0) {
3520 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3521 return IXGBE_ERR_INVALID_ARGUMENT;
3522 }
3523
9612de92
ET		 3524 dword_len = length >> 2;
3525
3526 /*
3527 * The device driver writes the relevant command block
3528 * into the ram area.
3529 */
3530 for (i = 0; i < dword_len; i++)
3531 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3532 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3533
3534 /* Setting this bit tells the ARC that a new command is pending. */
3535 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3536
b48e4aa3 3537 for (i = 0; i < timeout; i++) {
9612de92
ET		 3538 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3539 if (!(hicr & IXGBE_HICR_C))
3540 break;
3541 usleep_range(1000, 2000);
3542 }
3543
3544 /* Check command successful completion. */
b48e4aa3 3545 if ((timeout != 0 && i == timeout) ||
9612de92
ET		 3546 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3547 hw_dbg(hw, "Command has failed with no status valid.\n");
e90dd264 3548 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3549 }
3550
b48e4aa3
DS		 3551 if (!return_data)
3552 return 0;
3553
9612de92
ET		 3554 /* Calculate length in DWORDs */
3555 dword_len = hdr_size >> 2;
3556
3557 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3558 for (bi = 0; bi < dword_len; bi++) {
3559 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3560 le32_to_cpus(&buffer[bi]);
79488c58 3561 }
9612de92
ET		 3562
3563 /* If there is any thing in data position pull it in */
3564 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3565 if (buf_len == 0)
e90dd264 3566 return 0;
9612de92
ET		 3567
3568 if (length < (buf_len + hdr_size)) {
3569 hw_dbg(hw, "Buffer not large enough for reply message.\n");
e90dd264 3570 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3571 }
3572
331bcf45
ET		 3573 /* Calculate length in DWORDs, add 3 for odd lengths */
3574 dword_len = (buf_len + 3) >> 2;
9612de92 3575
331bcf45
ET		 3576 /* Pull in the rest of the buffer (bi is where we left off)*/
3577 for (; bi <= dword_len; bi++) {
3578 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3579 le32_to_cpus(&buffer[bi]);
3580 }
9612de92 3581
e90dd264 3582 return 0;
9612de92
ET		 3583}
3584
3585/**
3586 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3587 * @hw: pointer to the HW structure
3588 * @maj: driver version major number
3589 * @min: driver version minor number
3590 * @build: driver version build number
3591 * @sub: driver version sub build number
3592 *
3593 * Sends driver version number to firmware through the manageability
3594 * block. On success return 0
3595 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3596 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3597 **/
3598s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3599 u8 build, u8 sub)
3600{
3601 struct ixgbe_hic_drv_info fw_cmd;
3602 int i;
e90dd264 3603 s32 ret_val;
9612de92 3604
e90dd264
MR		 3605 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
3606 return IXGBE_ERR_SWFW_SYNC;
9612de92
ET		 3607
3608 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3609 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3610 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3611 fw_cmd.port_num = (u8)hw->bus.func;
3612 fw_cmd.ver_maj = maj;
3613 fw_cmd.ver_min = min;
3614 fw_cmd.ver_build = build;
3615 fw_cmd.ver_sub = sub;
3616 fw_cmd.hdr.checksum = 0;
3617 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3618 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3619 fw_cmd.pad = 0;
3620 fw_cmd.pad2 = 0;
3621
3622 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3623 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
b48e4aa3
DS		 3624 sizeof(fw_cmd),
3625 IXGBE_HI_COMMAND_TIMEOUT,
3626 true);
9612de92
ET		 3627 if (ret_val != 0)
3628 continue;
3629
3630 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3631 FW_CEM_RESP_STATUS_SUCCESS)
3632 ret_val = 0;
3633 else
3634 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3635
3636 break;
3637 }
3638
3639 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
9612de92
ET		 3640 return ret_val;
3641}
ff9d1a5a
ET		 3642
3643/**
3644 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3645 * @hw: pointer to the hardware structure
3646 *
3647 * The 82599 and x540 MACs can experience issues if TX work is still pending
3648 * when a reset occurs. This function prevents this by flushing the PCIe
3649 * buffers on the system.
3650 **/
3651void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3652{
71bde601
DS		 3653 u32 gcr_ext, hlreg0, i, poll;
3654 u16 value;
ff9d1a5a
ET		 3655
3656 /*
3657 * If double reset is not requested then all transactions should
3658 * already be clear and as such there is no work to do
3659 */
3660 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3661 return;
3662
3663 /*
3664 * Set loopback enable to prevent any transmits from being sent
3665 * should the link come up. This assumes that the RXCTRL.RXEN bit
3666 * has already been cleared.
3667 */
3668 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3669 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3670
71bde601
DS		 3671 /* wait for a last completion before clearing buffers */
3672 IXGBE_WRITE_FLUSH(hw);
3673 usleep_range(3000, 6000);
3674
3675 /* Before proceeding, make sure that the PCIe block does not have
3676 * transactions pending.
3677 */
3678 poll = ixgbe_pcie_timeout_poll(hw);
3679 for (i = 0; i < poll; i++) {
3680 usleep_range(100, 200);
3681 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3682 if (ixgbe_removed(hw->hw_addr))
3683 break;
3684 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3685 break;
3686 }
3687
ff9d1a5a
ET		 3688 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3689 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3690 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3691 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3692
3693 /* Flush all writes and allow 20usec for all transactions to clear */
3694 IXGBE_WRITE_FLUSH(hw);
3695 udelay(20);
3696
3697 /* restore previous register values */
3698 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3699 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3700}
e1ea9158
DS		 3701
3702static const u8 ixgbe_emc_temp_data[4] = {
3703 IXGBE_EMC_INTERNAL_DATA,
3704 IXGBE_EMC_DIODE1_DATA,
3705 IXGBE_EMC_DIODE2_DATA,
3706 IXGBE_EMC_DIODE3_DATA
3707};
3708static const u8 ixgbe_emc_therm_limit[4] = {
3709 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3710 IXGBE_EMC_DIODE1_THERM_LIMIT,
3711 IXGBE_EMC_DIODE2_THERM_LIMIT,
3712 IXGBE_EMC_DIODE3_THERM_LIMIT
3713};
3714
3715/**
3716 * ixgbe_get_ets_data - Extracts the ETS bit data
3717 * @hw: pointer to hardware structure
3718 * @ets_cfg: extected ETS data
3719 * @ets_offset: offset of ETS data
3720 *
3721 * Returns error code.
3722 **/
3723static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3724 u16 *ets_offset)
3725{
e90dd264 3726 s32 status;
e1ea9158
DS		 3727
3728 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3729 if (status)
e90dd264 3730 return status;
e1ea9158 3731
e90dd264
MR		 3732 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3733 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3734
3735 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3736 if (status)
e90dd264 3737 return status;
e1ea9158 3738
e90dd264
MR		 3739 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3740 return IXGBE_NOT_IMPLEMENTED;
e1ea9158 3741
e90dd264 3742 return 0;
e1ea9158
DS		 3743}
3744
3745/**
3746 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3747 * @hw: pointer to hardware structure
3748 *
3749 * Returns the thermal sensor data structure
3750 **/
3751s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3752{
e90dd264 3753 s32 status;
e1ea9158
DS		 3754 u16 ets_offset;
3755 u16 ets_cfg;
3756 u16 ets_sensor;
3757 u8 num_sensors;
3758 u8 i;
3759 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3760
3ca8bc6d 3761 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3762 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3763 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3764
3765 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3766 if (status)
e90dd264 3767 return status;
e1ea9158
DS		 3768
3769 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3770 if (num_sensors > IXGBE_MAX_SENSORS)
3771 num_sensors = IXGBE_MAX_SENSORS;
3772
3773 for (i = 0; i < num_sensors; i++) {
3774 u8 sensor_index;
3775 u8 sensor_location;
3776
3777 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3778 &ets_sensor);
3779 if (status)
e90dd264 3780 return status;
e1ea9158
DS		 3781
3782 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3783 IXGBE_ETS_DATA_INDEX_SHIFT);
3784 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3785 IXGBE_ETS_DATA_LOC_SHIFT);
3786
3787 if (sensor_location != 0) {
3788 status = hw->phy.ops.read_i2c_byte(hw,
3789 ixgbe_emc_temp_data[sensor_index],
3790 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3791 &data->sensor[i].temp);
3792 if (status)
e90dd264 3793 return status;
e1ea9158
DS		 3794 }
3795 }
e90dd264
MR		 3796
3797 return 0;
e1ea9158
DS		 3798}
3799
3800/**
3801 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3802 * @hw: pointer to hardware structure
3803 *
3804 * Inits the thermal sensor thresholds according to the NVM map
3805 * and save off the threshold and location values into mac.thermal_sensor_data
3806 **/
3807s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3808{
e90dd264 3809 s32 status;
e1ea9158
DS		 3810 u16 ets_offset;
3811 u16 ets_cfg;
3812 u16 ets_sensor;
3813 u8 low_thresh_delta;
3814 u8 num_sensors;
3815 u8 therm_limit;
3816 u8 i;
3817 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3818
3819 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3820
3ca8bc6d 3821 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3822 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3823 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3824
3825 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3826 if (status)
e90dd264 3827 return status;
e1ea9158
DS		 3828
3829 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3830 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3831 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3832 if (num_sensors > IXGBE_MAX_SENSORS)
3833 num_sensors = IXGBE_MAX_SENSORS;
3834
3835 for (i = 0; i < num_sensors; i++) {
3836 u8 sensor_index;
3837 u8 sensor_location;
3838
be0c27b4
MR		 3839 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3840 hw_err(hw, "eeprom read at offset %d failed\n",
3841 ets_offset + 1 + i);
3842 continue;
3843 }
e1ea9158
DS		 3844 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3845 IXGBE_ETS_DATA_INDEX_SHIFT);
3846 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3847 IXGBE_ETS_DATA_LOC_SHIFT);
3848 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3849
3850 hw->phy.ops.write_i2c_byte(hw,
3851 ixgbe_emc_therm_limit[sensor_index],
3852 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3853
3854 if (sensor_location == 0)
3855 continue;
3856
3857 data->sensor[i].location = sensor_location;
3858 data->sensor[i].caution_thresh = therm_limit;
3859 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3860 }
e90dd264
MR		 3861
3862 return 0;
e1ea9158
DS		 3863}
3864
1f9ac57c
DS		 3865void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
3866{
3867 u32 rxctrl;
3868
3869 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3870 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3871 if (hw->mac.type != ixgbe_mac_82598EB) {
3872 u32 pfdtxgswc;
3873
3874 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3875 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3876 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3877 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3878 hw->mac.set_lben = true;
3879 } else {
3880 hw->mac.set_lben = false;
3881 }
3882 }
3883 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3884 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3885 }
3886}
3887
3888void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
3889{
3890 u32 rxctrl;
3891
3892 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3893 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
3894
3895 if (hw->mac.type != ixgbe_mac_82598EB) {
3896 if (hw->mac.set_lben) {
3897 u32 pfdtxgswc;
3898
3899 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3900 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
3901 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3902 hw->mac.set_lben = false;
3903 }
3904 }
3905}
Linux kernel - Deliverables
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