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ixgbe: dcb, set priority to traffic class mappings
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
0b0c2b31
ET		 50static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
51static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
52static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
53static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
54static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
7b25cdba 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
eb9c3e3e 57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 58static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
61 u16 words, u16 *data);
62static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 u16 offset);
9a799d71
AK		 64
65/**
c44ade9e 66 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 67 * @hw: pointer to hardware structure
68 *
69 * Starts the hardware by filling the bus info structure and media type, clears
70 * all on chip counters, initializes receive address registers, multicast
71 * table, VLAN filter table, calls routine to set up link and flow control
72 * settings, and leaves transmit and receive units disabled and uninitialized
73 **/
c44ade9e 74s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 75{
76 u32 ctrl_ext;
77
78 /* Set the media type */
79 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
80
81 /* Identify the PHY */
c44ade9e 82 hw->phy.ops.identify(hw);
9a799d71 83
9a799d71 84 /* Clear the VLAN filter table */
c44ade9e 85 hw->mac.ops.clear_vfta(hw);
9a799d71 86
9a799d71 87 /* Clear statistics registers */
c44ade9e 88 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 89
90 /* Set No Snoop Disable */
91 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
92 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
93 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 94 IXGBE_WRITE_FLUSH(hw);
9a799d71 95
620fa036
MC		 96 /* Setup flow control */
97 ixgbe_setup_fc(hw, 0);
98
9a799d71
AK		 99 /* Clear adapter stopped flag */
100 hw->adapter_stopped = false;
101
102 return 0;
103}
104
7184b7cf
ET		 105/**
106 * ixgbe_start_hw_gen2 - Init sequence for common device family
107 * @hw: pointer to hw structure
108 *
109 * Performs the init sequence common to the second generation
110 * of 10 GbE devices.
111 * Devices in the second generation:
112 * 82599
113 * X540
114 **/
115s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
116{
117 u32 i;
3d5c5207 118 u32 regval;
7184b7cf
ET		 119
120 /* Clear the rate limiters */
121 for (i = 0; i < hw->mac.max_tx_queues; i++) {
122 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
123 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
124 }
125 IXGBE_WRITE_FLUSH(hw);
126
3d5c5207
ET		 127 /* Disable relaxed ordering */
128 for (i = 0; i < hw->mac.max_tx_queues; i++) {
129 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
130 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
131 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
132 }
133
134 for (i = 0; i < hw->mac.max_rx_queues; i++) {
135 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
136 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
137 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
138 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
139 }
140
7184b7cf
ET		 141 return 0;
142}
143
9a799d71 144/**
c44ade9e 145 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 146 * @hw: pointer to hardware structure
147 *
c44ade9e 148 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 149 * structure and media type, clears all on chip counters, initializes receive
150 * address registers, multicast table, VLAN filter table, calls routine to set
151 * up link and flow control settings, and leaves transmit and receive units
152 * disabled and uninitialized
153 **/
c44ade9e 154s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 155{
794caeb2
PWJ		 156 s32 status;
157
9a799d71 158 /* Reset the hardware */
794caeb2 159 status = hw->mac.ops.reset_hw(hw);
9a799d71 160
794caeb2
PWJ		 161 if (status == 0) {
162 /* Start the HW */
163 status = hw->mac.ops.start_hw(hw);
164 }
9a799d71 165
794caeb2 166 return status;
9a799d71
AK		 167}
168
169/**
c44ade9e 170 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 171 * @hw: pointer to hardware structure
172 *
173 * Clears all hardware statistics counters by reading them from the hardware
174 * Statistics counters are clear on read.
175 **/
c44ade9e 176s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 177{
178 u16 i = 0;
179
180 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
181 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
182 IXGBE_READ_REG(hw, IXGBE_ERRBC);
183 IXGBE_READ_REG(hw, IXGBE_MSPDC);
184 for (i = 0; i < 8; i++)
185 IXGBE_READ_REG(hw, IXGBE_MPC(i));
186
187 IXGBE_READ_REG(hw, IXGBE_MLFC);
188 IXGBE_READ_REG(hw, IXGBE_MRFC);
189 IXGBE_READ_REG(hw, IXGBE_RLEC);
190 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 191 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 192 if (hw->mac.type >= ixgbe_mac_82599EB) {
193 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
194 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
195 } else {
196 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
197 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
198 }
9a799d71
AK		 199
200 for (i = 0; i < 8; i++) {
201 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 202 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 203 if (hw->mac.type >= ixgbe_mac_82599EB) {
204 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
205 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
206 } else {
207 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
208 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
209 }
9a799d71 210 }
667c7565
ET		 211 if (hw->mac.type >= ixgbe_mac_82599EB)
212 for (i = 0; i < 8; i++)
213 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 214 IXGBE_READ_REG(hw, IXGBE_PRC64);
215 IXGBE_READ_REG(hw, IXGBE_PRC127);
216 IXGBE_READ_REG(hw, IXGBE_PRC255);
217 IXGBE_READ_REG(hw, IXGBE_PRC511);
218 IXGBE_READ_REG(hw, IXGBE_PRC1023);
219 IXGBE_READ_REG(hw, IXGBE_PRC1522);
220 IXGBE_READ_REG(hw, IXGBE_GPRC);
221 IXGBE_READ_REG(hw, IXGBE_BPRC);
222 IXGBE_READ_REG(hw, IXGBE_MPRC);
223 IXGBE_READ_REG(hw, IXGBE_GPTC);
224 IXGBE_READ_REG(hw, IXGBE_GORCL);
225 IXGBE_READ_REG(hw, IXGBE_GORCH);
226 IXGBE_READ_REG(hw, IXGBE_GOTCL);
227 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 228 if (hw->mac.type == ixgbe_mac_82598EB)
229 for (i = 0; i < 8; i++)
230 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 231 IXGBE_READ_REG(hw, IXGBE_RUC);
232 IXGBE_READ_REG(hw, IXGBE_RFC);
233 IXGBE_READ_REG(hw, IXGBE_ROC);
234 IXGBE_READ_REG(hw, IXGBE_RJC);
235 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
236 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
237 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
238 IXGBE_READ_REG(hw, IXGBE_TORL);
239 IXGBE_READ_REG(hw, IXGBE_TORH);
240 IXGBE_READ_REG(hw, IXGBE_TPR);
241 IXGBE_READ_REG(hw, IXGBE_TPT);
242 IXGBE_READ_REG(hw, IXGBE_PTC64);
243 IXGBE_READ_REG(hw, IXGBE_PTC127);
244 IXGBE_READ_REG(hw, IXGBE_PTC255);
245 IXGBE_READ_REG(hw, IXGBE_PTC511);
246 IXGBE_READ_REG(hw, IXGBE_PTC1023);
247 IXGBE_READ_REG(hw, IXGBE_PTC1522);
248 IXGBE_READ_REG(hw, IXGBE_MPTC);
249 IXGBE_READ_REG(hw, IXGBE_BPTC);
250 for (i = 0; i < 16; i++) {
251 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 252 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 253 if (hw->mac.type >= ixgbe_mac_82599EB) {
254 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
255 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
256 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
257 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
258 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
259 } else {
260 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
261 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
262 }
9a799d71
AK		 263 }
264
a3aeea0e
ET		 265 if (hw->mac.type == ixgbe_mac_X540) {
266 if (hw->phy.id == 0)
267 hw->phy.ops.identify(hw);
268 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
269 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
270 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
271 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
272 }
273
9a799d71
AK		 274 return 0;
275}
276
277/**
289700db 278 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 279 * @hw: pointer to hardware structure
289700db
DS		 280 * @pba_num: stores the part number string from the EEPROM
281 * @pba_num_size: part number string buffer length
c44ade9e 282 *
289700db 283 * Reads the part number string from the EEPROM.
c44ade9e 284 **/
289700db
DS		 285s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
286 u32 pba_num_size)
c44ade9e
JB		 287{
288 s32 ret_val;
289 u16 data;
289700db
DS		 290 u16 pba_ptr;
291 u16 offset;
292 u16 length;
293
294 if (pba_num == NULL) {
295 hw_dbg(hw, "PBA string buffer was null\n");
296 return IXGBE_ERR_INVALID_ARGUMENT;
297 }
c44ade9e
JB		 298
299 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
300 if (ret_val) {
301 hw_dbg(hw, "NVM Read Error\n");
302 return ret_val;
303 }
c44ade9e 304
289700db 305 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 306 if (ret_val) {
307 hw_dbg(hw, "NVM Read Error\n");
308 return ret_val;
309 }
289700db
DS		 310
311 /*
312 * if data is not ptr guard the PBA must be in legacy format which
313 * means pba_ptr is actually our second data word for the PBA number
314 * and we can decode it into an ascii string
315 */
316 if (data != IXGBE_PBANUM_PTR_GUARD) {
317 hw_dbg(hw, "NVM PBA number is not stored as string\n");
318
319 /* we will need 11 characters to store the PBA */
320 if (pba_num_size < 11) {
321 hw_dbg(hw, "PBA string buffer too small\n");
322 return IXGBE_ERR_NO_SPACE;
323 }
324
325 /* extract hex string from data and pba_ptr */
326 pba_num[0] = (data >> 12) & 0xF;
327 pba_num[1] = (data >> 8) & 0xF;
328 pba_num[2] = (data >> 4) & 0xF;
329 pba_num[3] = data & 0xF;
330 pba_num[4] = (pba_ptr >> 12) & 0xF;
331 pba_num[5] = (pba_ptr >> 8) & 0xF;
332 pba_num[6] = '-';
333 pba_num[7] = 0;
334 pba_num[8] = (pba_ptr >> 4) & 0xF;
335 pba_num[9] = pba_ptr & 0xF;
336
337 /* put a null character on the end of our string */
338 pba_num[10] = '\0';
339
340 /* switch all the data but the '-' to hex char */
341 for (offset = 0; offset < 10; offset++) {
342 if (pba_num[offset] < 0xA)
343 pba_num[offset] += '0';
344 else if (pba_num[offset] < 0x10)
345 pba_num[offset] += 'A' - 0xA;
346 }
347
348 return 0;
349 }
350
351 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
352 if (ret_val) {
353 hw_dbg(hw, "NVM Read Error\n");
354 return ret_val;
355 }
356
357 if (length == 0xFFFF || length == 0) {
358 hw_dbg(hw, "NVM PBA number section invalid length\n");
359 return IXGBE_ERR_PBA_SECTION;
360 }
361
362 /* check if pba_num buffer is big enough */
363 if (pba_num_size < (((u32)length * 2) - 1)) {
364 hw_dbg(hw, "PBA string buffer too small\n");
365 return IXGBE_ERR_NO_SPACE;
366 }
367
368 /* trim pba length from start of string */
369 pba_ptr++;
370 length--;
371
372 for (offset = 0; offset < length; offset++) {
373 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
374 if (ret_val) {
375 hw_dbg(hw, "NVM Read Error\n");
376 return ret_val;
377 }
378 pba_num[offset * 2] = (u8)(data >> 8);
379 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
380 }
381 pba_num[offset * 2] = '\0';
c44ade9e
JB		 382
383 return 0;
384}
385
386/**
387 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 388 * @hw: pointer to hardware structure
389 * @mac_addr: Adapter MAC address
390 *
391 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
392 * A reset of the adapter must be performed prior to calling this function
393 * in order for the MAC address to have been loaded from the EEPROM into RAR0
394 **/
c44ade9e 395s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 396{
397 u32 rar_high;
398 u32 rar_low;
399 u16 i;
400
401 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
402 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
403
404 for (i = 0; i < 4; i++)
405 mac_addr[i] = (u8)(rar_low >> (i*8));
406
407 for (i = 0; i < 2; i++)
408 mac_addr[i+4] = (u8)(rar_high >> (i*8));
409
410 return 0;
411}
412
11afc1b1
PW		 413/**
414 * ixgbe_get_bus_info_generic - Generic set PCI bus info
415 * @hw: pointer to hardware structure
416 *
417 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
418 **/
419s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
420{
421 struct ixgbe_adapter *adapter = hw->back;
422 struct ixgbe_mac_info *mac = &hw->mac;
423 u16 link_status;
424
425 hw->bus.type = ixgbe_bus_type_pci_express;
426
427 /* Get the negotiated link width and speed from PCI config space */
428 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
429 &link_status);
430
431 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
432 case IXGBE_PCI_LINK_WIDTH_1:
433 hw->bus.width = ixgbe_bus_width_pcie_x1;
434 break;
435 case IXGBE_PCI_LINK_WIDTH_2:
436 hw->bus.width = ixgbe_bus_width_pcie_x2;
437 break;
438 case IXGBE_PCI_LINK_WIDTH_4:
439 hw->bus.width = ixgbe_bus_width_pcie_x4;
440 break;
441 case IXGBE_PCI_LINK_WIDTH_8:
442 hw->bus.width = ixgbe_bus_width_pcie_x8;
443 break;
444 default:
445 hw->bus.width = ixgbe_bus_width_unknown;
446 break;
447 }
448
449 switch (link_status & IXGBE_PCI_LINK_SPEED) {
450 case IXGBE_PCI_LINK_SPEED_2500:
451 hw->bus.speed = ixgbe_bus_speed_2500;
452 break;
453 case IXGBE_PCI_LINK_SPEED_5000:
454 hw->bus.speed = ixgbe_bus_speed_5000;
455 break;
456 default:
457 hw->bus.speed = ixgbe_bus_speed_unknown;
458 break;
459 }
460
461 mac->ops.set_lan_id(hw);
462
463 return 0;
464}
465
466/**
467 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
468 * @hw: pointer to the HW structure
469 *
470 * Determines the LAN function id by reading memory-mapped registers
471 * and swaps the port value if requested.
472 **/
473void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
474{
475 struct ixgbe_bus_info *bus = &hw->bus;
476 u32 reg;
477
478 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
479 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
480 bus->lan_id = bus->func;
481
482 /* check for a port swap */
483 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
484 if (reg & IXGBE_FACTPS_LFS)
485 bus->func ^= 0x1;
486}
487
9a799d71 488/**
c44ade9e 489 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 490 * @hw: pointer to hardware structure
491 *
492 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
493 * disables transmit and receive units. The adapter_stopped flag is used by
494 * the shared code and drivers to determine if the adapter is in a stopped
495 * state and should not touch the hardware.
496 **/
c44ade9e 497s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 498{
499 u32 number_of_queues;
500 u32 reg_val;
501 u16 i;
502
503 /*
504 * Set the adapter_stopped flag so other driver functions stop touching
505 * the hardware
506 */
507 hw->adapter_stopped = true;
508
509 /* Disable the receive unit */
510 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
511 reg_val &= ~(IXGBE_RXCTRL_RXEN);
512 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 513 IXGBE_WRITE_FLUSH(hw);
032b4325 514 usleep_range(2000, 4000);
9a799d71
AK		 515
516 /* Clear interrupt mask to stop from interrupts being generated */
517 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
518
519 /* Clear any pending interrupts */
520 IXGBE_READ_REG(hw, IXGBE_EICR);
521
522 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 523 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 524 for (i = 0; i < number_of_queues; i++) {
525 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
526 if (reg_val & IXGBE_TXDCTL_ENABLE) {
527 reg_val &= ~IXGBE_TXDCTL_ENABLE;
528 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
529 }
530 }
531
c44ade9e
JB		 532 /*
533 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
534 * access and verify no pending requests
535 */
a4297dc2 536 ixgbe_disable_pcie_master(hw);
c44ade9e 537
9a799d71
AK		 538 return 0;
539}
540
541/**
c44ade9e 542 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 543 * @hw: pointer to hardware structure
544 * @index: led number to turn on
545 **/
c44ade9e 546s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 547{
548 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
549
550 /* To turn on the LED, set mode to ON. */
551 led_reg &= ~IXGBE_LED_MODE_MASK(index);
552 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
553 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 554 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 555
556 return 0;
557}
558
559/**
c44ade9e 560 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 561 * @hw: pointer to hardware structure
562 * @index: led number to turn off
563 **/
c44ade9e 564s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 565{
566 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
567
568 /* To turn off the LED, set mode to OFF. */
569 led_reg &= ~IXGBE_LED_MODE_MASK(index);
570 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
571 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 572 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 573
574 return 0;
575}
576
9a799d71 577/**
c44ade9e 578 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 579 * @hw: pointer to hardware structure
580 *
581 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
582 * ixgbe_hw struct in order to set up EEPROM access.
583 **/
c44ade9e 584s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 585{
586 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
587 u32 eec;
588 u16 eeprom_size;
589
590 if (eeprom->type == ixgbe_eeprom_uninitialized) {
591 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 592 /* Set default semaphore delay to 10ms which is a well
593 * tested value */
594 eeprom->semaphore_delay = 10;
68c7005d
ET		 595 /* Clear EEPROM page size, it will be initialized as needed */
596 eeprom->word_page_size = 0;
9a799d71
AK		 597
598 /*
599 * Check for EEPROM present first.
600 * If not present leave as none
601 */
602 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
603 if (eec & IXGBE_EEC_PRES) {
604 eeprom->type = ixgbe_eeprom_spi;
605
606 /*
607 * SPI EEPROM is assumed here. This code would need to
608 * change if a future EEPROM is not SPI.
609 */
610 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
611 IXGBE_EEC_SIZE_SHIFT);
612 eeprom->word_size = 1 << (eeprom_size +
613 IXGBE_EEPROM_WORD_SIZE_SHIFT);
614 }
615
616 if (eec & IXGBE_EEC_ADDR_SIZE)
617 eeprom->address_bits = 16;
618 else
619 eeprom->address_bits = 8;
620 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
621 "%d\n", eeprom->type, eeprom->word_size,
622 eeprom->address_bits);
623 }
624
625 return 0;
626}
627
11afc1b1 628/**
68c7005d 629 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 630 * @hw: pointer to hardware structure
68c7005d
ET		 631 * @offset: offset within the EEPROM to write
632 * @words: number of words
633 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 634 *
68c7005d 635 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 636 **/
68c7005d
ET		 637s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
638 u16 words, u16 *data)
11afc1b1 639{
68c7005d
ET		 640 s32 status = 0;
641 u16 i, count;
11afc1b1
PW		 642
643 hw->eeprom.ops.init_params(hw);
644
68c7005d
ET		 645 if (words == 0) {
646 status = IXGBE_ERR_INVALID_ARGUMENT;
647 goto out;
648 }
649
650 if (offset + words > hw->eeprom.word_size) {
11afc1b1
PW		 651 status = IXGBE_ERR_EEPROM;
652 goto out;
653 }
654
68c7005d
ET		 655 /*
656 * The EEPROM page size cannot be queried from the chip. We do lazy
657 * initialization. It is worth to do that when we write large buffer.
658 */
659 if ((hw->eeprom.word_page_size == 0) &&
660 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
661 ixgbe_detect_eeprom_page_size_generic(hw, offset);
662
663 /*
664 * We cannot hold synchronization semaphores for too long
665 * to avoid other entity starvation. However it is more efficient
666 * to read in bursts than synchronizing access for each word.
667 */
668 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
669 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
670 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
672 count, &data[i]);
673
674 if (status != 0)
675 break;
676 }
677
678out:
679 return status;
680}
681
682/**
683 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
684 * @hw: pointer to hardware structure
685 * @offset: offset within the EEPROM to be written to
686 * @words: number of word(s)
687 * @data: 16 bit word(s) to be written to the EEPROM
688 *
689 * If ixgbe_eeprom_update_checksum is not called after this function, the
690 * EEPROM will most likely contain an invalid checksum.
691 **/
692static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
693 u16 words, u16 *data)
694{
695 s32 status;
696 u16 word;
697 u16 page_size;
698 u16 i;
699 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
700
11afc1b1
PW		 701 /* Prepare the EEPROM for writing */
702 status = ixgbe_acquire_eeprom(hw);
703
704 if (status == 0) {
705 if (ixgbe_ready_eeprom(hw) != 0) {
706 ixgbe_release_eeprom(hw);
707 status = IXGBE_ERR_EEPROM;
708 }
709 }
710
711 if (status == 0) {
68c7005d
ET		 712 for (i = 0; i < words; i++) {
713 ixgbe_standby_eeprom(hw);
11afc1b1 714
68c7005d
ET		 715 /* Send the WRITE ENABLE command (8 bit opcode ) */
716 ixgbe_shift_out_eeprom_bits(hw,
717 IXGBE_EEPROM_WREN_OPCODE_SPI,
718 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 719
68c7005d 720 ixgbe_standby_eeprom(hw);
11afc1b1 721
68c7005d
ET		 722 /*
723 * Some SPI eeproms use the 8th address bit embedded
724 * in the opcode
725 */
726 if ((hw->eeprom.address_bits == 8) &&
727 ((offset + i) >= 128))
728 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
729
730 /* Send the Write command (8-bit opcode + addr) */
731 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
732 IXGBE_EEPROM_OPCODE_BITS);
733 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
734 hw->eeprom.address_bits);
735
736 page_size = hw->eeprom.word_page_size;
737
738 /* Send the data in burst via SPI*/
739 do {
740 word = data[i];
741 word = (word >> 8) | (word << 8);
742 ixgbe_shift_out_eeprom_bits(hw, word, 16);
743
744 if (page_size == 0)
745 break;
746
747 /* do not wrap around page */
748 if (((offset + i) & (page_size - 1)) ==
749 (page_size - 1))
750 break;
751 } while (++i < words);
752
753 ixgbe_standby_eeprom(hw);
754 usleep_range(10000, 20000);
755 }
756 /* Done with writing - release the EEPROM */
757 ixgbe_release_eeprom(hw);
758 }
11afc1b1 759
68c7005d
ET		 760 return status;
761}
762
763/**
764 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
765 * @hw: pointer to hardware structure
766 * @offset: offset within the EEPROM to be written to
767 * @data: 16 bit word to be written to the EEPROM
768 *
769 * If ixgbe_eeprom_update_checksum is not called after this function, the
770 * EEPROM will most likely contain an invalid checksum.
771 **/
772s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
773{
774 s32 status;
11afc1b1 775
68c7005d 776 hw->eeprom.ops.init_params(hw);
11afc1b1 777
68c7005d
ET		 778 if (offset >= hw->eeprom.word_size) {
779 status = IXGBE_ERR_EEPROM;
780 goto out;
11afc1b1
PW		 781 }
782
68c7005d
ET		 783 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
784
11afc1b1
PW		 785out:
786 return status;
787}
788
9a799d71 789/**
68c7005d 790 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 791 * @hw: pointer to hardware structure
792 * @offset: offset within the EEPROM to be read
68c7005d
ET		 793 * @words: number of word(s)
794 * @data: read 16 bit words(s) from EEPROM
c44ade9e 795 *
68c7005d 796 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 797 **/
68c7005d
ET		 798s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
799 u16 words, u16 *data)
c44ade9e 800{
68c7005d
ET		 801 s32 status = 0;
802 u16 i, count;
c44ade9e
JB		 803
804 hw->eeprom.ops.init_params(hw);
805
68c7005d
ET		 806 if (words == 0) {
807 status = IXGBE_ERR_INVALID_ARGUMENT;
808 goto out;
809 }
810
811 if (offset + words > hw->eeprom.word_size) {
c44ade9e
JB		 812 status = IXGBE_ERR_EEPROM;
813 goto out;
814 }
815
68c7005d
ET		 816 /*
817 * We cannot hold synchronization semaphores for too long
818 * to avoid other entity starvation. However it is more efficient
819 * to read in bursts than synchronizing access for each word.
820 */
821 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
822 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
823 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
824
825 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
826 count, &data[i]);
827
828 if (status != 0)
829 break;
830 }
831
832out:
833 return status;
834}
835
836/**
837 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
838 * @hw: pointer to hardware structure
839 * @offset: offset within the EEPROM to be read
840 * @words: number of word(s)
841 * @data: read 16 bit word(s) from EEPROM
842 *
843 * Reads 16 bit word(s) from EEPROM through bit-bang method
844 **/
845static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
846 u16 words, u16 *data)
847{
848 s32 status;
849 u16 word_in;
850 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
851 u16 i;
852
c44ade9e
JB		 853 /* Prepare the EEPROM for reading */
854 status = ixgbe_acquire_eeprom(hw);
855
856 if (status == 0) {
857 if (ixgbe_ready_eeprom(hw) != 0) {
858 ixgbe_release_eeprom(hw);
859 status = IXGBE_ERR_EEPROM;
860 }
861 }
862
863 if (status == 0) {
68c7005d
ET		 864 for (i = 0; i < words; i++) {
865 ixgbe_standby_eeprom(hw);
866 /*
867 * Some SPI eeproms use the 8th address bit embedded
868 * in the opcode
869 */
870 if ((hw->eeprom.address_bits == 8) &&
871 ((offset + i) >= 128))
872 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
873
874 /* Send the READ command (opcode + addr) */
875 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
876 IXGBE_EEPROM_OPCODE_BITS);
877 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
878 hw->eeprom.address_bits);
879
880 /* Read the data. */
881 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
882 data[i] = (word_in >> 8) | (word_in << 8);
883 }
c44ade9e 884
68c7005d
ET		 885 /* End this read operation */
886 ixgbe_release_eeprom(hw);
887 }
c44ade9e 888
68c7005d
ET		 889 return status;
890}
c44ade9e 891
68c7005d
ET		 892/**
893 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
894 * @hw: pointer to hardware structure
895 * @offset: offset within the EEPROM to be read
896 * @data: read 16 bit value from EEPROM
897 *
898 * Reads 16 bit value from EEPROM through bit-bang method
899 **/
900s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
901 u16 *data)
902{
903 s32 status;
c44ade9e 904
68c7005d
ET		 905 hw->eeprom.ops.init_params(hw);
906
907 if (offset >= hw->eeprom.word_size) {
908 status = IXGBE_ERR_EEPROM;
909 goto out;
c44ade9e
JB		 910 }
911
68c7005d
ET		 912 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
913
c44ade9e
JB		 914out:
915 return status;
916}
917
918/**
68c7005d 919 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 920 * @hw: pointer to hardware structure
68c7005d
ET		 921 * @offset: offset of word in the EEPROM to read
922 * @words: number of word(s)
923 * @data: 16 bit word(s) from the EEPROM
9a799d71 924 *
68c7005d 925 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 926 **/
68c7005d
ET		 927s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
928 u16 words, u16 *data)
9a799d71
AK		 929{
930 u32 eerd;
68c7005d
ET		 931 s32 status = 0;
932 u32 i;
9a799d71 933
c44ade9e
JB		 934 hw->eeprom.ops.init_params(hw);
935
68c7005d
ET		 936 if (words == 0) {
937 status = IXGBE_ERR_INVALID_ARGUMENT;
938 goto out;
939 }
940
c44ade9e
JB		 941 if (offset >= hw->eeprom.word_size) {
942 status = IXGBE_ERR_EEPROM;
943 goto out;
944 }
945
68c7005d
ET		 946 for (i = 0; i < words; i++) {
947 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
948 IXGBE_EEPROM_RW_REG_START;
9a799d71 949
68c7005d
ET		 950 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
951 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 952
68c7005d
ET		 953 if (status == 0) {
954 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
955 IXGBE_EEPROM_RW_REG_DATA);
956 } else {
957 hw_dbg(hw, "Eeprom read timed out\n");
958 goto out;
959 }
960 }
961out:
962 return status;
963}
9a799d71 964
68c7005d
ET		 965/**
966 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
967 * @hw: pointer to hardware structure
968 * @offset: offset within the EEPROM to be used as a scratch pad
969 *
970 * Discover EEPROM page size by writing marching data at given offset.
971 * This function is called only when we are writing a new large buffer
972 * at given offset so the data would be overwritten anyway.
973 **/
974static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
975 u16 offset)
976{
977 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
978 s32 status = 0;
979 u16 i;
980
981 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
982 data[i] = i;
983
984 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
985 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
986 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
987 hw->eeprom.word_page_size = 0;
988 if (status != 0)
989 goto out;
990
991 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
992 if (status != 0)
993 goto out;
994
995 /*
996 * When writing in burst more than the actual page size
997 * EEPROM address wraps around current page.
998 */
999 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1000
1001 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1002 hw->eeprom.word_page_size);
c44ade9e 1003out:
9a799d71
AK		 1004 return status;
1005}
1006
eb9c3e3e 1007/**
68c7005d
ET		 1008 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1009 * @hw: pointer to hardware structure
1010 * @offset: offset of word in the EEPROM to read
1011 * @data: word read from the EEPROM
1012 *
1013 * Reads a 16 bit word from the EEPROM using the EERD register.
1014 **/
1015s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1016{
1017 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1018}
1019
1020/**
1021 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1022 * @hw: pointer to hardware structure
1023 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1024 * @words: number of words
1025 * @data: word(s) write to the EEPROM
eb9c3e3e 1026 *
68c7005d 1027 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1028 **/
68c7005d
ET		 1029s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1030 u16 words, u16 *data)
eb9c3e3e
ET		 1031{
1032 u32 eewr;
68c7005d
ET		 1033 s32 status = 0;
1034 u16 i;
eb9c3e3e
ET		 1035
1036 hw->eeprom.ops.init_params(hw);
1037
68c7005d
ET		 1038 if (words == 0) {
1039 status = IXGBE_ERR_INVALID_ARGUMENT;
1040 goto out;
1041 }
1042
eb9c3e3e
ET		 1043 if (offset >= hw->eeprom.word_size) {
1044 status = IXGBE_ERR_EEPROM;
1045 goto out;
1046 }
1047
68c7005d
ET		 1048 for (i = 0; i < words; i++) {
1049 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1050 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1051 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1052
68c7005d
ET		 1053 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1054 if (status != 0) {
1055 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1056 goto out;
1057 }
eb9c3e3e 1058
68c7005d 1059 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1060
68c7005d
ET		 1061 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1062 if (status != 0) {
1063 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1064 goto out;
1065 }
eb9c3e3e
ET		 1066 }
1067
1068out:
1069 return status;
1070}
1071
68c7005d
ET		 1072/**
1073 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1074 * @hw: pointer to hardware structure
1075 * @offset: offset of word in the EEPROM to write
1076 * @data: word write to the EEPROM
1077 *
1078 * Write a 16 bit word to the EEPROM using the EEWR register.
1079 **/
1080s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1081{
1082 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1083}
1084
9a799d71 1085/**
21ce849b 1086 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1087 * @hw: pointer to hardware structure
21ce849b 1088 * @ee_reg: EEPROM flag for polling
9a799d71 1089 *
21ce849b
MC		 1090 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1091 * read or write is done respectively.
9a799d71 1092 **/
eb9c3e3e 1093static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1094{
1095 u32 i;
1096 u32 reg;
1097 s32 status = IXGBE_ERR_EEPROM;
1098
21ce849b
MC		 1099 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1100 if (ee_reg == IXGBE_NVM_POLL_READ)
1101 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1102 else
1103 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1104
1105 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 1106 status = 0;
1107 break;
1108 }
1109 udelay(5);
1110 }
1111 return status;
1112}
1113
c44ade9e
JB		 1114/**
1115 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1116 * @hw: pointer to hardware structure
1117 *
1118 * Prepares EEPROM for access using bit-bang method. This function should
1119 * be called before issuing a command to the EEPROM.
1120 **/
1121static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1122{
1123 s32 status = 0;
dbf893ee 1124 u32 eec;
c44ade9e
JB		 1125 u32 i;
1126
5e655105 1127 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 1128 status = IXGBE_ERR_SWFW_SYNC;
1129
1130 if (status == 0) {
1131 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1132
1133 /* Request EEPROM Access */
1134 eec |= IXGBE_EEC_REQ;
1135 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1136
1137 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1138 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1139 if (eec & IXGBE_EEC_GNT)
1140 break;
1141 udelay(5);
1142 }
1143
1144 /* Release if grant not acquired */
1145 if (!(eec & IXGBE_EEC_GNT)) {
1146 eec &= ~IXGBE_EEC_REQ;
1147 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1148 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1149
5e655105 1150 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 1151 status = IXGBE_ERR_EEPROM;
1152 }
c44ade9e 1153
dbf893ee
ET		 1154 /* Setup EEPROM for Read/Write */
1155 if (status == 0) {
1156 /* Clear CS and SK */
1157 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1158 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1159 IXGBE_WRITE_FLUSH(hw);
1160 udelay(1);
1161 }
c44ade9e
JB		 1162 }
1163 return status;
1164}
1165
9a799d71
AK		 1166/**
1167 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1168 * @hw: pointer to hardware structure
1169 *
1170 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1171 **/
1172static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1173{
1174 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 1175 u32 timeout = 2000;
9a799d71
AK		 1176 u32 i;
1177 u32 swsm;
1178
9a799d71
AK		 1179 /* Get SMBI software semaphore between device drivers first */
1180 for (i = 0; i < timeout; i++) {
1181 /*
1182 * If the SMBI bit is 0 when we read it, then the bit will be
1183 * set and we have the semaphore
1184 */
1185 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1186 if (!(swsm & IXGBE_SWSM_SMBI)) {
1187 status = 0;
1188 break;
1189 }
dbf893ee 1190 udelay(50);
9a799d71
AK		 1191 }
1192
51275d37
ET		 1193 if (i == timeout) {
1194 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1195 "not granted.\n");
1196 /*
1197 * this release is particularly important because our attempts
1198 * above to get the semaphore may have succeeded, and if there
1199 * was a timeout, we should unconditionally clear the semaphore
1200 * bits to free the driver to make progress
1201 */
1202 ixgbe_release_eeprom_semaphore(hw);
1203
1204 udelay(50);
1205 /*
1206 * one last try
1207 * If the SMBI bit is 0 when we read it, then the bit will be
1208 * set and we have the semaphore
1209 */
1210 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1211 if (!(swsm & IXGBE_SWSM_SMBI))
1212 status = 0;
1213 }
1214
9a799d71
AK		 1215 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1216 if (status == 0) {
1217 for (i = 0; i < timeout; i++) {
1218 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1219
1220 /* Set the SW EEPROM semaphore bit to request access */
1221 swsm |= IXGBE_SWSM_SWESMBI;
1222 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1223
1224 /*
1225 * If we set the bit successfully then we got the
1226 * semaphore.
1227 */
1228 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1229 if (swsm & IXGBE_SWSM_SWESMBI)
1230 break;
1231
1232 udelay(50);
1233 }
1234
1235 /*
1236 * Release semaphores and return error if SW EEPROM semaphore
1237 * was not granted because we don't have access to the EEPROM
1238 */
1239 if (i >= timeout) {
dbf893ee 1240 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 1241 "not granted.\n");
9a799d71
AK		 1242 ixgbe_release_eeprom_semaphore(hw);
1243 status = IXGBE_ERR_EEPROM;
1244 }
dbf893ee
ET		 1245 } else {
1246 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1247 "not granted.\n");
9a799d71
AK		 1248 }
1249
1250 return status;
1251}
1252
1253/**
1254 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1255 * @hw: pointer to hardware structure
1256 *
1257 * This function clears hardware semaphore bits.
1258 **/
1259static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1260{
1261 u32 swsm;
1262
1263 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1264
1265 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1266 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1267 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1268 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1269}
1270
c44ade9e
JB		 1271/**
1272 * ixgbe_ready_eeprom - Polls for EEPROM ready
1273 * @hw: pointer to hardware structure
1274 **/
1275static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1276{
1277 s32 status = 0;
1278 u16 i;
1279 u8 spi_stat_reg;
1280
1281 /*
1282 * Read "Status Register" repeatedly until the LSB is cleared. The
1283 * EEPROM will signal that the command has been completed by clearing
1284 * bit 0 of the internal status register. If it's not cleared within
1285 * 5 milliseconds, then error out.
1286 */
1287 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1288 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1289 IXGBE_EEPROM_OPCODE_BITS);
1290 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1291 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1292 break;
1293
1294 udelay(5);
1295 ixgbe_standby_eeprom(hw);
6403eab1 1296 }
c44ade9e
JB		 1297
1298 /*
1299 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1300 * devices (and only 0-5mSec on 5V devices)
1301 */
1302 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1303 hw_dbg(hw, "SPI EEPROM Status error\n");
1304 status = IXGBE_ERR_EEPROM;
1305 }
1306
1307 return status;
1308}
1309
1310/**
1311 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1312 * @hw: pointer to hardware structure
1313 **/
1314static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1315{
1316 u32 eec;
1317
1318 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1319
1320 /* Toggle CS to flush commands */
1321 eec |= IXGBE_EEC_CS;
1322 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1323 IXGBE_WRITE_FLUSH(hw);
1324 udelay(1);
1325 eec &= ~IXGBE_EEC_CS;
1326 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1327 IXGBE_WRITE_FLUSH(hw);
1328 udelay(1);
1329}
1330
1331/**
1332 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1333 * @hw: pointer to hardware structure
1334 * @data: data to send to the EEPROM
1335 * @count: number of bits to shift out
1336 **/
1337static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1338 u16 count)
1339{
1340 u32 eec;
1341 u32 mask;
1342 u32 i;
1343
1344 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1345
1346 /*
1347 * Mask is used to shift "count" bits of "data" out to the EEPROM
1348 * one bit at a time. Determine the starting bit based on count
1349 */
1350 mask = 0x01 << (count - 1);
1351
1352 for (i = 0; i < count; i++) {
1353 /*
1354 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1355 * "1", and then raising and then lowering the clock (the SK
1356 * bit controls the clock input to the EEPROM). A "0" is
1357 * shifted out to the EEPROM by setting "DI" to "0" and then
1358 * raising and then lowering the clock.
1359 */
1360 if (data & mask)
1361 eec |= IXGBE_EEC_DI;
1362 else
1363 eec &= ~IXGBE_EEC_DI;
1364
1365 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1366 IXGBE_WRITE_FLUSH(hw);
1367
1368 udelay(1);
1369
1370 ixgbe_raise_eeprom_clk(hw, &eec);
1371 ixgbe_lower_eeprom_clk(hw, &eec);
1372
1373 /*
1374 * Shift mask to signify next bit of data to shift in to the
1375 * EEPROM
1376 */
1377 mask = mask >> 1;
6403eab1 1378 }
c44ade9e
JB		 1379
1380 /* We leave the "DI" bit set to "0" when we leave this routine. */
1381 eec &= ~IXGBE_EEC_DI;
1382 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1383 IXGBE_WRITE_FLUSH(hw);
1384}
1385
1386/**
1387 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1388 * @hw: pointer to hardware structure
1389 **/
1390static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1391{
1392 u32 eec;
1393 u32 i;
1394 u16 data = 0;
1395
1396 /*
1397 * In order to read a register from the EEPROM, we need to shift
1398 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1399 * the clock input to the EEPROM (setting the SK bit), and then reading
1400 * the value of the "DO" bit. During this "shifting in" process the
1401 * "DI" bit should always be clear.
1402 */
1403 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1404
1405 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1406
1407 for (i = 0; i < count; i++) {
1408 data = data << 1;
1409 ixgbe_raise_eeprom_clk(hw, &eec);
1410
1411 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1412
1413 eec &= ~(IXGBE_EEC_DI);
1414 if (eec & IXGBE_EEC_DO)
1415 data |= 1;
1416
1417 ixgbe_lower_eeprom_clk(hw, &eec);
1418 }
1419
1420 return data;
1421}
1422
1423/**
1424 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1425 * @hw: pointer to hardware structure
1426 * @eec: EEC register's current value
1427 **/
1428static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1429{
1430 /*
1431 * Raise the clock input to the EEPROM
1432 * (setting the SK bit), then delay
1433 */
1434 *eec = *eec | IXGBE_EEC_SK;
1435 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1436 IXGBE_WRITE_FLUSH(hw);
1437 udelay(1);
1438}
1439
1440/**
1441 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1442 * @hw: pointer to hardware structure
1443 * @eecd: EECD's current value
1444 **/
1445static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1446{
1447 /*
1448 * Lower the clock input to the EEPROM (clearing the SK bit), then
1449 * delay
1450 */
1451 *eec = *eec & ~IXGBE_EEC_SK;
1452 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1453 IXGBE_WRITE_FLUSH(hw);
1454 udelay(1);
1455}
1456
1457/**
1458 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1459 * @hw: pointer to hardware structure
1460 **/
1461static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1462{
1463 u32 eec;
1464
1465 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1466
1467 eec |= IXGBE_EEC_CS; /* Pull CS high */
1468 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1469
1470 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1471 IXGBE_WRITE_FLUSH(hw);
1472
1473 udelay(1);
1474
1475 /* Stop requesting EEPROM access */
1476 eec &= ~IXGBE_EEC_REQ;
1477 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1478
90827996 1479 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1480
032b4325
DS		 1481 /*
1482 * Delay before attempt to obtain semaphore again to allow FW
1483 * access. semaphore_delay is in ms we need us for usleep_range
1484 */
1485 usleep_range(hw->eeprom.semaphore_delay * 1000,
1486 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1487}
1488
9a799d71 1489/**
dbf893ee 1490 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1491 * @hw: pointer to hardware structure
1492 **/
a391f1d5 1493u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1494{
1495 u16 i;
1496 u16 j;
1497 u16 checksum = 0;
1498 u16 length = 0;
1499 u16 pointer = 0;
1500 u16 word = 0;
1501
1502 /* Include 0x0-0x3F in the checksum */
1503 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1504 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1505 hw_dbg(hw, "EEPROM read failed\n");
1506 break;
1507 }
1508 checksum += word;
1509 }
1510
1511 /* Include all data from pointers except for the fw pointer */
1512 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1513 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1514
1515 /* Make sure the pointer seems valid */
1516 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1517 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1518
1519 if (length != 0xFFFF && length != 0) {
1520 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1521 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1522 checksum += word;
1523 }
1524 }
1525 }
1526 }
1527
1528 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1529
1530 return checksum;
1531}
1532
1533/**
c44ade9e 1534 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1535 * @hw: pointer to hardware structure
1536 * @checksum_val: calculated checksum
1537 *
1538 * Performs checksum calculation and validates the EEPROM checksum. If the
1539 * caller does not need checksum_val, the value can be NULL.
1540 **/
c44ade9e
JB		 1541s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1542 u16 *checksum_val)
9a799d71
AK		 1543{
1544 s32 status;
1545 u16 checksum;
1546 u16 read_checksum = 0;
1547
1548 /*
1549 * Read the first word from the EEPROM. If this times out or fails, do
1550 * not continue or we could be in for a very long wait while every
1551 * EEPROM read fails
1552 */
c44ade9e 1553 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1554
1555 if (status == 0) {
a391f1d5 1556 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1557
c44ade9e 1558 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1559
1560 /*
1561 * Verify read checksum from EEPROM is the same as
1562 * calculated checksum
1563 */
1564 if (read_checksum != checksum)
1565 status = IXGBE_ERR_EEPROM_CHECKSUM;
1566
1567 /* If the user cares, return the calculated checksum */
1568 if (checksum_val)
1569 *checksum_val = checksum;
1570 } else {
1571 hw_dbg(hw, "EEPROM read failed\n");
1572 }
1573
1574 return status;
1575}
1576
c44ade9e
JB		 1577/**
1578 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1579 * @hw: pointer to hardware structure
1580 **/
1581s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1582{
1583 s32 status;
1584 u16 checksum;
1585
1586 /*
1587 * Read the first word from the EEPROM. If this times out or fails, do
1588 * not continue or we could be in for a very long wait while every
1589 * EEPROM read fails
1590 */
1591 status = hw->eeprom.ops.read(hw, 0, &checksum);
1592
1593 if (status == 0) {
a391f1d5 1594 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1595 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1596 checksum);
c44ade9e
JB		 1597 } else {
1598 hw_dbg(hw, "EEPROM read failed\n");
1599 }
1600
1601 return status;
1602}
1603
9a799d71
AK		 1604/**
1605 * ixgbe_validate_mac_addr - Validate MAC address
1606 * @mac_addr: pointer to MAC address.
1607 *
1608 * Tests a MAC address to ensure it is a valid Individual Address
1609 **/
1610s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1611{
1612 s32 status = 0;
1613
1614 /* Make sure it is not a multicast address */
1615 if (IXGBE_IS_MULTICAST(mac_addr))
1616 status = IXGBE_ERR_INVALID_MAC_ADDR;
1617 /* Not a broadcast address */
1618 else if (IXGBE_IS_BROADCAST(mac_addr))
1619 status = IXGBE_ERR_INVALID_MAC_ADDR;
1620 /* Reject the zero address */
1621 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1622 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1623 status = IXGBE_ERR_INVALID_MAC_ADDR;
1624
1625 return status;
1626}
1627
1628/**
c44ade9e 1629 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1630 * @hw: pointer to hardware structure
9a799d71 1631 * @index: Receive address register to write
c44ade9e
JB		 1632 * @addr: Address to put into receive address register
1633 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1634 * @enable_addr: set flag that address is active
1635 *
1636 * Puts an ethernet address into a receive address register.
1637 **/
c44ade9e
JB		 1638s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1639 u32 enable_addr)
9a799d71
AK		 1640{
1641 u32 rar_low, rar_high;
c44ade9e
JB		 1642 u32 rar_entries = hw->mac.num_rar_entries;
1643
c700f4e6
ET		 1644 /* Make sure we are using a valid rar index range */
1645 if (index >= rar_entries) {
1646 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1647 return IXGBE_ERR_INVALID_ARGUMENT;
1648 }
1649
c44ade9e
JB		 1650 /* setup VMDq pool selection before this RAR gets enabled */
1651 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1652
c700f4e6
ET		 1653 /*
1654 * HW expects these in little endian so we reverse the byte
1655 * order from network order (big endian) to little endian
1656 */
1657 rar_low = ((u32)addr[0] |
1658 ((u32)addr[1] << 8) |
1659 ((u32)addr[2] << 16) |
1660 ((u32)addr[3] << 24));
1661 /*
1662 * Some parts put the VMDq setting in the extra RAH bits,
1663 * so save everything except the lower 16 bits that hold part
1664 * of the address and the address valid bit.
1665 */
1666 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1667 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1668 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1669
c700f4e6
ET		 1670 if (enable_addr != 0)
1671 rar_high |= IXGBE_RAH_AV;
9a799d71 1672
c700f4e6
ET		 1673 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1674 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1675
1676 return 0;
1677}
1678
1679/**
1680 * ixgbe_clear_rar_generic - Remove Rx address register
1681 * @hw: pointer to hardware structure
1682 * @index: Receive address register to write
1683 *
1684 * Clears an ethernet address from a receive address register.
1685 **/
1686s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1687{
1688 u32 rar_high;
1689 u32 rar_entries = hw->mac.num_rar_entries;
1690
1691 /* Make sure we are using a valid rar index range */
c700f4e6 1692 if (index >= rar_entries) {
c44ade9e 1693 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1694 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1695 }
1696
c700f4e6
ET		 1697 /*
1698 * Some parts put the VMDq setting in the extra RAH bits,
1699 * so save everything except the lower 16 bits that hold part
1700 * of the address and the address valid bit.
1701 */
1702 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1703 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1704
1705 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1706 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1707
c44ade9e
JB		 1708 /* clear VMDq pool/queue selection for this RAR */
1709 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1710
1711 return 0;
1712}
1713
c44ade9e
JB		 1714/**
1715 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1716 * @hw: pointer to hardware structure
1717 *
1718 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1719 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1720 * the receiver is in reset when the routine is called.
1721 **/
c44ade9e 1722s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1723{
1724 u32 i;
2c5645cf 1725 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1726
1727 /*
1728 * If the current mac address is valid, assume it is a software override
1729 * to the permanent address.
1730 * Otherwise, use the permanent address from the eeprom.
1731 */
1732 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1733 IXGBE_ERR_INVALID_MAC_ADDR) {
1734 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1735 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1736
ce7194d8 1737 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1738 } else {
1739 /* Setup the receive address. */
1740 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1741 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1742
c44ade9e 1743 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1744
1745 /* clear VMDq pool/queue selection for RAR 0 */
1746 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1747 }
c44ade9e 1748 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1749
1750 hw->addr_ctrl.rar_used_count = 1;
1751
1752 /* Zero out the other receive addresses. */
c44ade9e 1753 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1754 for (i = 1; i < rar_entries; i++) {
1755 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1756 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1757 }
1758
1759 /* Clear the MTA */
9a799d71
AK		 1760 hw->addr_ctrl.mta_in_use = 0;
1761 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1762
1763 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1764 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1765 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1766
c44ade9e
JB		 1767 if (hw->mac.ops.init_uta_tables)
1768 hw->mac.ops.init_uta_tables(hw);
1769
9a799d71
AK		 1770 return 0;
1771}
1772
1773/**
1774 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1775 * @hw: pointer to hardware structure
1776 * @mc_addr: the multicast address
1777 *
1778 * Extracts the 12 bits, from a multicast address, to determine which
1779 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1780 * incoming rx multicast addresses, to determine the bit-vector to check in
1781 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1782 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1783 * to mc_filter_type.
1784 **/
1785static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1786{
1787 u32 vector = 0;
1788
1789 switch (hw->mac.mc_filter_type) {
b4617240 1790 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1791 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1792 break;
b4617240 1793 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1794 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1795 break;
b4617240 1796 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1797 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1798 break;
b4617240 1799 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1800 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1801 break;
b4617240 1802 default: /* Invalid mc_filter_type */
9a799d71
AK		 1803 hw_dbg(hw, "MC filter type param set incorrectly\n");
1804 break;
1805 }
1806
1807 /* vector can only be 12-bits or boundary will be exceeded */
1808 vector &= 0xFFF;
1809 return vector;
1810}
1811
1812/**
1813 * ixgbe_set_mta - Set bit-vector in multicast table
1814 * @hw: pointer to hardware structure
1815 * @hash_value: Multicast address hash value
1816 *
1817 * Sets the bit-vector in the multicast table.
1818 **/
1819static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1820{
1821 u32 vector;
1822 u32 vector_bit;
1823 u32 vector_reg;
9a799d71
AK		 1824
1825 hw->addr_ctrl.mta_in_use++;
1826
1827 vector = ixgbe_mta_vector(hw, mc_addr);
1828 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1829
1830 /*
1831 * The MTA is a register array of 128 32-bit registers. It is treated
1832 * like an array of 4096 bits. We want to set bit
1833 * BitArray[vector_value]. So we figure out what register the bit is
1834 * in, read it, OR in the new bit, then write back the new value. The
1835 * register is determined by the upper 7 bits of the vector value and
1836 * the bit within that register are determined by the lower 5 bits of
1837 * the value.
1838 */
1839 vector_reg = (vector >> 5) & 0x7F;
1840 vector_bit = vector & 0x1F;
80960ab0 1841 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1842}
1843
9a799d71 1844/**
c44ade9e 1845 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1846 * @hw: pointer to hardware structure
2853eb89 1847 * @netdev: pointer to net device structure
9a799d71
AK		 1848 *
1849 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1850 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1851 * registers for the first multicast addresses, and hashes the rest into the
1852 * multicast table.
1853 **/
2853eb89
JP		 1854s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1855 struct net_device *netdev)
9a799d71 1856{
22bedad3 1857 struct netdev_hw_addr *ha;
9a799d71 1858 u32 i;
9a799d71
AK		 1859
1860 /*
1861 * Set the new number of MC addresses that we are being requested to
1862 * use.
1863 */
2853eb89 1864 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1865 hw->addr_ctrl.mta_in_use = 0;
1866
80960ab0 1867 /* Clear mta_shadow */
9a799d71 1868 hw_dbg(hw, " Clearing MTA\n");
80960ab0 1869 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 1870
80960ab0 1871 /* Update mta shadow */
22bedad3 1872 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1873 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1874 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1875 }
1876
1877 /* Enable mta */
80960ab0
ET		 1878 for (i = 0; i < hw->mac.mcft_size; i++)
1879 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1880 hw->mac.mta_shadow[i]);
1881
9a799d71
AK		 1882 if (hw->addr_ctrl.mta_in_use > 0)
1883 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1884 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1885
c44ade9e 1886 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1887 return 0;
1888}
1889
1890/**
c44ade9e 1891 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1892 * @hw: pointer to hardware structure
1893 *
c44ade9e 1894 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1895 **/
c44ade9e 1896s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1897{
c44ade9e 1898 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1899
c44ade9e
JB		 1900 if (a->mta_in_use > 0)
1901 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1902 hw->mac.mc_filter_type);
9a799d71
AK		 1903
1904 return 0;
1905}
1906
1907/**
c44ade9e 1908 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1909 * @hw: pointer to hardware structure
9a799d71 1910 *
c44ade9e 1911 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1912 **/
c44ade9e 1913s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1914{
c44ade9e 1915 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1916
c44ade9e
JB		 1917 if (a->mta_in_use > 0)
1918 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1919
1920 return 0;
1921}
1922
11afc1b1 1923/**
620fa036 1924 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1925 * @hw: pointer to hardware structure
1926 * @packetbuf_num: packet buffer number (0-7)
1927 *
1928 * Enable flow control according to the current settings.
1929 **/
620fa036 1930s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1931{
1932 s32 ret_val = 0;
620fa036 1933 u32 mflcn_reg, fccfg_reg;
11afc1b1 1934 u32 reg;
70b77628 1935 u32 rx_pba_size;
16b61beb 1936 u32 fcrtl, fcrth;
70b77628
PWJ		 1937
1938#ifdef CONFIG_DCB
1939 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1940 goto out;
1941
1942#endif /* CONFIG_DCB */
620fa036
MC		 1943 /* Negotiate the fc mode to use */
1944 ret_val = ixgbe_fc_autoneg(hw);
0b0c2b31 1945 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
620fa036 1946 goto out;
11afc1b1 1947
620fa036 1948 /* Disable any previous flow control settings */
11afc1b1
PW		 1949 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1950 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1951
1952 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1953 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1954
1955 /*
1956 * The possible values of fc.current_mode are:
1957 * 0: Flow control is completely disabled
1958 * 1: Rx flow control is enabled (we can receive pause frames,
1959 * but not send pause frames).
bb3daa4a
PW		 1960 * 2: Tx flow control is enabled (we can send pause frames but
1961 * we do not support receiving pause frames).
11afc1b1 1962 * 3: Both Rx and Tx flow control (symmetric) are enabled.
8c7bea32 1963#ifdef CONFIG_DCB
bb3daa4a 1964 * 4: Priority Flow Control is enabled.
8c7bea32 1965#endif
11afc1b1
PW		 1966 * other: Invalid.
1967 */
1968 switch (hw->fc.current_mode) {
1969 case ixgbe_fc_none:
620fa036
MC		 1970 /*
1971 * Flow control is disabled by software override or autoneg.
1972 * The code below will actually disable it in the HW.
1973 */
11afc1b1
PW		 1974 break;
1975 case ixgbe_fc_rx_pause:
1976 /*
1977 * Rx Flow control is enabled and Tx Flow control is
1978 * disabled by software override. Since there really
1979 * isn't a way to advertise that we are capable of RX
1980 * Pause ONLY, we will advertise that we support both
1981 * symmetric and asymmetric Rx PAUSE. Later, we will
1982 * disable the adapter's ability to send PAUSE frames.
1983 */
1984 mflcn_reg |= IXGBE_MFLCN_RFCE;
1985 break;
1986 case ixgbe_fc_tx_pause:
1987 /*
1988 * Tx Flow control is enabled, and Rx Flow control is
1989 * disabled by software override.
1990 */
1991 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1992 break;
1993 case ixgbe_fc_full:
1994 /* Flow control (both Rx and Tx) is enabled by SW override. */
1995 mflcn_reg |= IXGBE_MFLCN_RFCE;
1996 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1997 break;
bb3daa4a
PW		 1998#ifdef CONFIG_DCB
1999 case ixgbe_fc_pfc:
2000 goto out;
2001 break;
620fa036 2002#endif /* CONFIG_DCB */
11afc1b1
PW		 2003 default:
2004 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2005 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 2006 goto out;
2007 break;
2008 }
2009
620fa036 2010 /* Set 802.3x based flow control settings. */
2132d381 2011 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2012 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2013 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2014
16b61beb
JF		 2015 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
2016 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
620fa036 2017
16b61beb
JF		 2018 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
2019 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
264857b8 2020
16b61beb
JF		 2021 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2022 fcrth |= IXGBE_FCRTH_FCEN;
2023 if (hw->fc.send_xon)
2024 fcrtl |= IXGBE_FCRTL_XONE;
11afc1b1
PW		 2025 }
2026
16b61beb
JF		 2027 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2028 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2029
11afc1b1 2030 /* Configure pause time (2 TCs per register) */
70b77628 2031 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 2032 if ((packetbuf_num & 1) == 0)
2033 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2034 else
2035 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2036 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2037
2038 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2039
2040out:
2041 return ret_val;
2042}
2043
0ecc061d
PWJ		 2044/**
2045 * ixgbe_fc_autoneg - Configure flow control
2046 * @hw: pointer to hardware structure
2047 *
620fa036
MC		 2048 * Compares our advertised flow control capabilities to those advertised by
2049 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 2050 **/
2051s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2052{
0b0c2b31 2053 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
620fa036 2054 ixgbe_link_speed speed;
620fa036 2055 bool link_up;
0ecc061d 2056
0b0c2b31
ET		 2057 if (hw->fc.disable_fc_autoneg)
2058 goto out;
2059
0ecc061d 2060 /*
620fa036
MC		 2061 * AN should have completed when the cable was plugged in.
2062 * Look for reasons to bail out. Bail out if:
2063 * - FC autoneg is disabled, or if
539e5f02 2064 * - link is not up.
620fa036 2065 *
539e5f02 2066 * Since we're being called from an LSC, link is already known to be up.
620fa036 2067 * So use link_up_wait_to_complete=false.
0ecc061d 2068 */
620fa036 2069 hw->mac.ops.check_link(hw, &speed, &link_up, false);
0b0c2b31
ET		 2070 if (!link_up) {
2071 ret_val = IXGBE_ERR_FLOW_CONTROL;
0ecc061d
PWJ		 2072 goto out;
2073 }
2074
0b0c2b31
ET		 2075 switch (hw->phy.media_type) {
2076 /* Autoneg flow control on fiber adapters */
2077 case ixgbe_media_type_fiber:
2078 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2079 ret_val = ixgbe_fc_autoneg_fiber(hw);
2080 break;
000c486d 2081
0b0c2b31
ET		 2082 /* Autoneg flow control on backplane adapters */
2083 case ixgbe_media_type_backplane:
2084 ret_val = ixgbe_fc_autoneg_backplane(hw);
2085 break;
2086
2087 /* Autoneg flow control on copper adapters */
2088 case ixgbe_media_type_copper:
2089 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2090 ret_val = ixgbe_fc_autoneg_copper(hw);
2091 break;
2092
2093 default:
2094 break;
2095 }
2096
2097out:
2098 if (ret_val == 0) {
2099 hw->fc.fc_was_autonegged = true;
2100 } else {
2101 hw->fc.fc_was_autonegged = false;
2102 hw->fc.current_mode = hw->fc.requested_mode;
539e5f02 2103 }
0b0c2b31
ET		 2104 return ret_val;
2105}
2106
2107/**
2108 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2109 * @hw: pointer to hardware structure
2110 *
2111 * Enable flow control according on 1 gig fiber.
2112 **/
2113static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2114{
2115 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2116 s32 ret_val;
539e5f02
PWJ		 2117
2118 /*
2119 * On multispeed fiber at 1g, bail out if
2120 * - link is up but AN did not complete, or if
2121 * - link is up and AN completed but timed out
2122 */
0b0c2b31
ET		 2123
2124 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de
DS		 2125 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2126 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
0b0c2b31
ET		 2127 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2128 goto out;
539e5f02
PWJ		 2129 }
2130
0b0c2b31
ET		 2131 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2132 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2133
2134 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2135 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2136 IXGBE_PCS1GANA_ASM_PAUSE,
2137 IXGBE_PCS1GANA_SYM_PAUSE,
2138 IXGBE_PCS1GANA_ASM_PAUSE);
2139
2140out:
2141 return ret_val;
2142}
2143
2144/**
2145 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2146 * @hw: pointer to hardware structure
2147 *
2148 * Enable flow control according to IEEE clause 37.
2149 **/
2150static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2151{
2152 u32 links2, anlp1_reg, autoc_reg, links;
2153 s32 ret_val;
2154
9bbe3a57 2155 /*
0b0c2b31
ET		 2156 * On backplane, bail out if
2157 * - backplane autoneg was not completed, or if
2158 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2159 */
0b0c2b31
ET		 2160 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2161 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
9bbe3a57
PW		 2162 hw->fc.fc_was_autonegged = false;
2163 hw->fc.current_mode = hw->fc.requested_mode;
0b0c2b31 2164 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57
PW		 2165 goto out;
2166 }
2167
0b0c2b31
ET		 2168 if (hw->mac.type == ixgbe_mac_82599EB) {
2169 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2170 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2171 hw->fc.fc_was_autonegged = false;
2172 hw->fc.current_mode = hw->fc.requested_mode;
2173 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2174 goto out;
2175 }
2176 }
0ecc061d 2177 /*
0b0c2b31 2178 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2179 * local flow control settings accordingly
2180 */
0b0c2b31
ET		 2181 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2182 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2183
0b0c2b31
ET		 2184 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2185 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2186 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2187
2188out:
2189 return ret_val;
2190}
2191
2192/**
2193 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2194 * @hw: pointer to hardware structure
2195 *
2196 * Enable flow control according to IEEE clause 37.
2197 **/
2198static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2199{
2200 u16 technology_ability_reg = 0;
2201 u16 lp_technology_ability_reg = 0;
2202
2203 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2204 MDIO_MMD_AN,
2205 &technology_ability_reg);
2206 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2207 MDIO_MMD_AN,
2208 &lp_technology_ability_reg);
2209
2210 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2211 (u32)lp_technology_ability_reg,
2212 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2213 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2214}
2215
2216/**
2217 * ixgbe_negotiate_fc - Negotiate flow control
2218 * @hw: pointer to hardware structure
2219 * @adv_reg: flow control advertised settings
2220 * @lp_reg: link partner's flow control settings
2221 * @adv_sym: symmetric pause bit in advertisement
2222 * @adv_asm: asymmetric pause bit in advertisement
2223 * @lp_sym: symmetric pause bit in link partner advertisement
2224 * @lp_asm: asymmetric pause bit in link partner advertisement
2225 *
2226 * Find the intersection between advertised settings and link partner's
2227 * advertised settings
2228 **/
2229static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2230 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2231{
2232 if ((!(adv_reg)) || (!(lp_reg)))
2233 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2234
2235 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
0ecc061d 2236 /*
0b0c2b31
ET		 2237 * Now we need to check if the user selected Rx ONLY
2238 * of pause frames. In this case, we had to advertise
2239 * FULL flow control because we could not advertise RX
2240 * ONLY. Hence, we must now check to see if we need to
2241 * turn OFF the TRANSMISSION of PAUSE frames.
0ecc061d 2242 */
0b0c2b31
ET		 2243 if (hw->fc.requested_mode == ixgbe_fc_full) {
2244 hw->fc.current_mode = ixgbe_fc_full;
2245 hw_dbg(hw, "Flow Control = FULL.\n");
539e5f02 2246 } else {
0b0c2b31
ET		 2247 hw->fc.current_mode = ixgbe_fc_rx_pause;
2248 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
0ecc061d 2249 }
0b0c2b31
ET		 2250 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2251 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2252 hw->fc.current_mode = ixgbe_fc_tx_pause;
2253 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2254 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2255 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2256 hw->fc.current_mode = ixgbe_fc_rx_pause;
2257 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2258 } else {
2259 hw->fc.current_mode = ixgbe_fc_none;
2260 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 2261 }
0b0c2b31 2262 return 0;
0ecc061d
PWJ		 2263}
2264
11afc1b1 2265/**
620fa036 2266 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 2267 * @hw: pointer to hardware structure
2268 *
620fa036 2269 * Called at init time to set up flow control.
11afc1b1 2270 **/
7b25cdba 2271static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 2272{
2273 s32 ret_val = 0;
0b0c2b31
ET		 2274 u32 reg = 0, reg_bp = 0;
2275 u16 reg_cu = 0;
11afc1b1 2276
bb3daa4a
PW		 2277#ifdef CONFIG_DCB
2278 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
2279 hw->fc.current_mode = hw->fc.requested_mode;
2280 goto out;
2281 }
2282
0b0c2b31 2283#endif /* CONFIG_DCB */
11afc1b1
PW		 2284 /* Validate the packetbuf configuration */
2285 if (packetbuf_num < 0 || packetbuf_num > 7) {
2286 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
2287 "is 0-7\n", packetbuf_num);
2288 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2289 goto out;
2290 }
2291
2292 /*
2293 * Validate the water mark configuration. Zero water marks are invalid
2294 * because it causes the controller to just blast out fc packets.
2295 */
2296 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 2297 hw_dbg(hw, "Invalid water mark configuration\n");
2298 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2299 goto out;
11afc1b1
PW		 2300 }
2301
2302 /*
2303 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 2304 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 2305 */
2306 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2307 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
2308 "IEEE mode\n");
2309 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2310 goto out;
2311 }
2312
2313 /*
2314 * 10gig parts do not have a word in the EEPROM to determine the
2315 * default flow control setting, so we explicitly set it to full.
2316 */
2317 if (hw->fc.requested_mode == ixgbe_fc_default)
2318 hw->fc.requested_mode = ixgbe_fc_full;
2319
2320 /*
0b0c2b31
ET		 2321 * Set up the 1G and 10G flow control advertisement registers so the
2322 * HW will be able to do fc autoneg once the cable is plugged in. If
2323 * we link at 10G, the 1G advertisement is harmless and vice versa.
11afc1b1 2324 */
0b0c2b31
ET		 2325
2326 switch (hw->phy.media_type) {
2327 case ixgbe_media_type_fiber:
2328 case ixgbe_media_type_backplane:
2329 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2330 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2331 break;
2332
2333 case ixgbe_media_type_copper:
2334 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2335 MDIO_MMD_AN, &reg_cu);
2336 break;
2337
2338 default:
2339 ;
2340 }
11afc1b1 2341
620fa036
MC		 2342 /*
2343 * The possible values of fc.requested_mode are:
2344 * 0: Flow control is completely disabled
2345 * 1: Rx flow control is enabled (we can receive pause frames,
2346 * but not send pause frames).
2347 * 2: Tx flow control is enabled (we can send pause frames but
2348 * we do not support receiving pause frames).
2349 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2350#ifdef CONFIG_DCB
2351 * 4: Priority Flow Control is enabled.
2352#endif
2353 * other: Invalid.
2354 */
2355 switch (hw->fc.requested_mode) {
2356 case ixgbe_fc_none:
2357 /* Flow control completely disabled by software override. */
2358 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2359 if (hw->phy.media_type == ixgbe_media_type_backplane)
2360 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2361 IXGBE_AUTOC_ASM_PAUSE);
2362 else if (hw->phy.media_type == ixgbe_media_type_copper)
2363 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2364 break;
2365 case ixgbe_fc_rx_pause:
2366 /*
2367 * Rx Flow control is enabled and Tx Flow control is
2368 * disabled by software override. Since there really
2369 * isn't a way to advertise that we are capable of RX
2370 * Pause ONLY, we will advertise that we support both
2371 * symmetric and asymmetric Rx PAUSE. Later, we will
2372 * disable the adapter's ability to send PAUSE frames.
2373 */
2374 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2375 if (hw->phy.media_type == ixgbe_media_type_backplane)
2376 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2377 IXGBE_AUTOC_ASM_PAUSE);
2378 else if (hw->phy.media_type == ixgbe_media_type_copper)
2379 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2380 break;
2381 case ixgbe_fc_tx_pause:
2382 /*
2383 * Tx Flow control is enabled, and Rx Flow control is
2384 * disabled by software override.
2385 */
2386 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2387 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
0b0c2b31
ET		 2388 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2389 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2390 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2391 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2392 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2393 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2394 }
620fa036
MC		 2395 break;
2396 case ixgbe_fc_full:
2397 /* Flow control (both Rx and Tx) is enabled by SW override. */
2398 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2399 if (hw->phy.media_type == ixgbe_media_type_backplane)
2400 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2401 IXGBE_AUTOC_ASM_PAUSE);
2402 else if (hw->phy.media_type == ixgbe_media_type_copper)
2403 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2404 break;
2405#ifdef CONFIG_DCB
2406 case ixgbe_fc_pfc:
11afc1b1 2407 goto out;
620fa036
MC		 2408 break;
2409#endif /* CONFIG_DCB */
2410 default:
2411 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2412 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 2413 goto out;
2414 break;
2415 }
2416
0b0c2b31
ET		 2417 if (hw->mac.type != ixgbe_mac_X540) {
2418 /*
2419 * Enable auto-negotiation between the MAC & PHY;
2420 * the MAC will advertise clause 37 flow control.
2421 */
2422 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2423 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
620fa036 2424
0b0c2b31
ET		 2425 /* Disable AN timeout */
2426 if (hw->fc.strict_ieee)
2427 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
11afc1b1 2428
0b0c2b31
ET		 2429 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2430 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2431 }
539e5f02
PWJ		 2432
2433 /*
0b0c2b31
ET		 2434 * AUTOC restart handles negotiation of 1G and 10G on backplane
2435 * and copper. There is no need to set the PCS1GCTL register.
2436 *
539e5f02 2437 */
0b0c2b31
ET		 2438 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2439 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2440 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2441 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2442 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
2443 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
2444 MDIO_MMD_AN, reg_cu);
539e5f02 2445 }
539e5f02 2446
0b0c2b31 2447 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
11afc1b1
PW		 2448out:
2449 return ret_val;
2450}
2451
9a799d71
AK		 2452/**
2453 * ixgbe_disable_pcie_master - Disable PCI-express master access
2454 * @hw: pointer to hardware structure
2455 *
2456 * Disables PCI-Express master access and verifies there are no pending
2457 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2458 * bit hasn't caused the master requests to be disabled, else 0
2459 * is returned signifying master requests disabled.
2460 **/
2461s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2462{
a4297dc2 2463 struct ixgbe_adapter *adapter = hw->back;
c44ade9e
JB		 2464 u32 i;
2465 u32 reg_val;
2466 u32 number_of_queues;
a4297dc2
ET		 2467 s32 status = 0;
2468 u16 dev_status = 0;
2469
2470 /* Just jump out if bus mastering is already disabled */
2471 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2472 goto out;
9a799d71 2473
c44ade9e
JB		 2474 /* Disable the receive unit by stopping each queue */
2475 number_of_queues = hw->mac.max_rx_queues;
2476 for (i = 0; i < number_of_queues; i++) {
2477 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2478 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2479 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2480 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2481 }
2482 }
2483
2484 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2485 reg_val |= IXGBE_CTRL_GIO_DIS;
2486 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2487
2488 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2
ET		 2489 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2490 goto check_device_status;
2491 udelay(100);
2492 }
2493
2494 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2495 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2496
2497 /*
2498 * Before proceeding, make sure that the PCIe block does not have
2499 * transactions pending.
2500 */
2501check_device_status:
2502 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2503 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2504 &dev_status);
2505 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
9a799d71 2506 break;
9a799d71
AK		 2507 udelay(100);
2508 }
2509
a4297dc2
ET		 2510 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2511 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2512 else
2513 goto out;
2514
2515 /*
2516 * Two consecutive resets are required via CTRL.RST per datasheet
2517 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2518 * of this need. The first reset prevents new master requests from
2519 * being issued by our device. We then must wait 1usec for any
2520 * remaining completions from the PCIe bus to trickle in, and then reset
2521 * again to clear out any effects they may have had on our device.
2522 */
2523 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2524
2525out:
9a799d71
AK		 2526 return status;
2527}
2528
2529
2530/**
c44ade9e 2531 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2532 * @hw: pointer to hardware structure
c44ade9e 2533 * @mask: Mask to specify which semaphore to acquire
9a799d71 2534 *
da74cd4a 2535 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2536 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2537 **/
2538s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2539{
2540 u32 gssr;
2541 u32 swmask = mask;
2542 u32 fwmask = mask << 5;
2543 s32 timeout = 200;
2544
2545 while (timeout) {
dbf893ee
ET		 2546 /*
2547 * SW EEPROM semaphore bit is used for access to all
2548 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2549 */
9a799d71 2550 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2551 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2552
2553 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2554 if (!(gssr & (fwmask | swmask)))
2555 break;
2556
2557 /*
2558 * Firmware currently using resource (fwmask) or other software
2559 * thread currently using resource (swmask)
2560 */
2561 ixgbe_release_eeprom_semaphore(hw);
032b4325 2562 usleep_range(5000, 10000);
9a799d71
AK		 2563 timeout--;
2564 }
2565
2566 if (!timeout) {
dbf893ee 2567 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2568 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2569 }
2570
2571 gssr |= swmask;
2572 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2573
2574 ixgbe_release_eeprom_semaphore(hw);
2575 return 0;
2576}
2577
2578/**
2579 * ixgbe_release_swfw_sync - Release SWFW semaphore
2580 * @hw: pointer to hardware structure
c44ade9e 2581 * @mask: Mask to specify which semaphore to release
9a799d71 2582 *
da74cd4a 2583 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2584 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2585 **/
2586void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2587{
2588 u32 gssr;
2589 u32 swmask = mask;
2590
2591 ixgbe_get_eeprom_semaphore(hw);
2592
2593 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2594 gssr &= ~swmask;
2595 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2596
2597 ixgbe_release_eeprom_semaphore(hw);
2598}
2599
11afc1b1
PW		 2600/**
2601 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2602 * @hw: pointer to hardware structure
2603 * @regval: register value to write to RXCTRL
2604 *
2605 * Enables the Rx DMA unit
2606 **/
2607s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2608{
2609 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2610
2611 return 0;
2612}
87c12017
PW		 2613
2614/**
2615 * ixgbe_blink_led_start_generic - Blink LED based on index.
2616 * @hw: pointer to hardware structure
2617 * @index: led number to blink
2618 **/
2619s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2620{
2621 ixgbe_link_speed speed = 0;
2622 bool link_up = 0;
2623 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2624 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2625
2626 /*
2627 * Link must be up to auto-blink the LEDs;
2628 * Force it if link is down.
2629 */
2630 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2631
2632 if (!link_up) {
50ac58ba 2633 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2634 autoc_reg |= IXGBE_AUTOC_FLU;
2635 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
945a5151 2636 IXGBE_WRITE_FLUSH(hw);
032b4325 2637 usleep_range(10000, 20000);
87c12017
PW		 2638 }
2639
2640 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2641 led_reg |= IXGBE_LED_BLINK(index);
2642 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2643 IXGBE_WRITE_FLUSH(hw);
2644
2645 return 0;
2646}
2647
2648/**
2649 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2650 * @hw: pointer to hardware structure
2651 * @index: led number to stop blinking
2652 **/
2653s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2654{
2655 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2656 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2657
2658 autoc_reg &= ~IXGBE_AUTOC_FLU;
2659 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2660 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2661
2662 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2663 led_reg &= ~IXGBE_LED_BLINK(index);
2664 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2665 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2666 IXGBE_WRITE_FLUSH(hw);
2667
2668 return 0;
2669}
21ce849b
MC		 2670
2671/**
2672 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2673 * @hw: pointer to hardware structure
2674 * @san_mac_offset: SAN MAC address offset
2675 *
2676 * This function will read the EEPROM location for the SAN MAC address
2677 * pointer, and returns the value at that location. This is used in both
2678 * get and set mac_addr routines.
2679 **/
2680static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2681 u16 *san_mac_offset)
2682{
2683 /*
2684 * First read the EEPROM pointer to see if the MAC addresses are
2685 * available.
2686 */
2687 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2688
2689 return 0;
2690}
2691
2692/**
2693 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2694 * @hw: pointer to hardware structure
2695 * @san_mac_addr: SAN MAC address
2696 *
2697 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2698 * per-port, so set_lan_id() must be called before reading the addresses.
2699 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2700 * upon for non-SFP connections, so we must call it here.
2701 **/
2702s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2703{
2704 u16 san_mac_data, san_mac_offset;
2705 u8 i;
2706
2707 /*
2708 * First read the EEPROM pointer to see if the MAC addresses are
2709 * available. If they're not, no point in calling set_lan_id() here.
2710 */
2711 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2712
2713 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2714 /*
2715 * No addresses available in this EEPROM. It's not an
2716 * error though, so just wipe the local address and return.
2717 */
2718 for (i = 0; i < 6; i++)
2719 san_mac_addr[i] = 0xFF;
2720
2721 goto san_mac_addr_out;
2722 }
2723
2724 /* make sure we know which port we need to program */
2725 hw->mac.ops.set_lan_id(hw);
2726 /* apply the port offset to the address offset */
2727 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2728 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2729 for (i = 0; i < 3; i++) {
2730 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2731 san_mac_addr[i * 2] = (u8)(san_mac_data);
2732 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2733 san_mac_offset++;
2734 }
2735
2736san_mac_addr_out:
2737 return 0;
2738}
2739
2740/**
2741 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2742 * @hw: pointer to hardware structure
2743 *
2744 * Read PCIe configuration space, and get the MSI-X vector count from
2745 * the capabilities table.
2746 **/
2747u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2748{
2749 struct ixgbe_adapter *adapter = hw->back;
2750 u16 msix_count;
2751 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2752 &msix_count);
2753 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2754
2755 /* MSI-X count is zero-based in HW, so increment to give proper value */
2756 msix_count++;
2757
2758 return msix_count;
2759}
2760
2761/**
2762 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2763 * @hw: pointer to hardware struct
2764 * @rar: receive address register index to disassociate
2765 * @vmdq: VMDq pool index to remove from the rar
2766 **/
2767s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2768{
2769 u32 mpsar_lo, mpsar_hi;
2770 u32 rar_entries = hw->mac.num_rar_entries;
2771
c700f4e6
ET		 2772 /* Make sure we are using a valid rar index range */
2773 if (rar >= rar_entries) {
2774 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2775 return IXGBE_ERR_INVALID_ARGUMENT;
2776 }
21ce849b 2777
c700f4e6
ET		 2778 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2779 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2780
c700f4e6
ET		 2781 if (!mpsar_lo && !mpsar_hi)
2782 goto done;
21ce849b 2783
c700f4e6
ET		 2784 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2785 if (mpsar_lo) {
2786 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2787 mpsar_lo = 0;
2788 }
2789 if (mpsar_hi) {
2790 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2791 mpsar_hi = 0;
2792 }
2793 } else if (vmdq < 32) {
2794 mpsar_lo &= ~(1 << vmdq);
2795 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2796 } else {
c700f4e6
ET		 2797 mpsar_hi &= ~(1 << (vmdq - 32));
2798 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2799 }
2800
c700f4e6
ET		 2801 /* was that the last pool using this rar? */
2802 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2803 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2804done:
2805 return 0;
2806}
2807
2808/**
2809 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2810 * @hw: pointer to hardware struct
2811 * @rar: receive address register index to associate with a VMDq index
2812 * @vmdq: VMDq pool index
2813 **/
2814s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2815{
2816 u32 mpsar;
2817 u32 rar_entries = hw->mac.num_rar_entries;
2818
c700f4e6
ET		 2819 /* Make sure we are using a valid rar index range */
2820 if (rar >= rar_entries) {
21ce849b 2821 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2822 return IXGBE_ERR_INVALID_ARGUMENT;
2823 }
2824
2825 if (vmdq < 32) {
2826 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2827 mpsar |= 1 << vmdq;
2828 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2829 } else {
2830 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2831 mpsar |= 1 << (vmdq - 32);
2832 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2833 }
2834 return 0;
2835}
2836
2837/**
2838 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2839 * @hw: pointer to hardware structure
2840 **/
2841s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2842{
2843 int i;
2844
21ce849b
MC		 2845 for (i = 0; i < 128; i++)
2846 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2847
2848 return 0;
2849}
2850
2851/**
2852 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2853 * @hw: pointer to hardware structure
2854 * @vlan: VLAN id to write to VLAN filter
2855 *
2856 * return the VLVF index where this VLAN id should be placed
2857 *
2858 **/
5d5b7c39 2859static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2860{
2861 u32 bits = 0;
2862 u32 first_empty_slot = 0;
2863 s32 regindex;
2864
2865 /* short cut the special case */
2866 if (vlan == 0)
2867 return 0;
2868
2869 /*
2870 * Search for the vlan id in the VLVF entries. Save off the first empty
2871 * slot found along the way
2872 */
2873 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2874 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2875 if (!bits && !(first_empty_slot))
2876 first_empty_slot = regindex;
2877 else if ((bits & 0x0FFF) == vlan)
2878 break;
2879 }
2880
2881 /*
2882 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2883 * in the VLVF. Else use the first empty VLVF register for this
2884 * vlan id.
2885 */
2886 if (regindex >= IXGBE_VLVF_ENTRIES) {
2887 if (first_empty_slot)
2888 regindex = first_empty_slot;
2889 else {
2890 hw_dbg(hw, "No space in VLVF.\n");
2891 regindex = IXGBE_ERR_NO_SPACE;
2892 }
2893 }
2894
2895 return regindex;
2896}
2897
2898/**
2899 * ixgbe_set_vfta_generic - Set VLAN filter table
2900 * @hw: pointer to hardware structure
2901 * @vlan: VLAN id to write to VLAN filter
2902 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2903 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2904 *
2905 * Turn on/off specified VLAN in the VLAN filter table.
2906 **/
2907s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2908 bool vlan_on)
2909{
2910 s32 regindex;
2911 u32 bitindex;
2912 u32 vfta;
2913 u32 bits;
2914 u32 vt;
2915 u32 targetbit;
2916 bool vfta_changed = false;
2917
2918 if (vlan > 4095)
2919 return IXGBE_ERR_PARAM;
2920
2921 /*
2922 * this is a 2 part operation - first the VFTA, then the
2923 * VLVF and VLVFB if VT Mode is set
2924 * We don't write the VFTA until we know the VLVF part succeeded.
2925 */
2926
2927 /* Part 1
2928 * The VFTA is a bitstring made up of 128 32-bit registers
2929 * that enable the particular VLAN id, much like the MTA:
2930 * bits[11-5]: which register
2931 * bits[4-0]: which bit in the register
2932 */
2933 regindex = (vlan >> 5) & 0x7F;
2934 bitindex = vlan & 0x1F;
2935 targetbit = (1 << bitindex);
2936 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2937
2938 if (vlan_on) {
2939 if (!(vfta & targetbit)) {
2940 vfta |= targetbit;
2941 vfta_changed = true;
2942 }
2943 } else {
2944 if ((vfta & targetbit)) {
2945 vfta &= ~targetbit;
2946 vfta_changed = true;
2947 }
2948 }
2949
2950 /* Part 2
2951 * If VT Mode is set
2952 * Either vlan_on
2953 * make sure the vlan is in VLVF
2954 * set the vind bit in the matching VLVFB
2955 * Or !vlan_on
2956 * clear the pool bit and possibly the vind
2957 */
2958 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2959 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2960 s32 vlvf_index;
2961
2962 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2963 if (vlvf_index < 0)
2964 return vlvf_index;
2965
2966 if (vlan_on) {
2967 /* set the pool bit */
2968 if (vind < 32) {
2969 bits = IXGBE_READ_REG(hw,
2970 IXGBE_VLVFB(vlvf_index*2));
2971 bits |= (1 << vind);
2972 IXGBE_WRITE_REG(hw,
2973 IXGBE_VLVFB(vlvf_index*2),
2974 bits);
2975 } else {
2976 bits = IXGBE_READ_REG(hw,
2977 IXGBE_VLVFB((vlvf_index*2)+1));
2978 bits |= (1 << (vind-32));
2979 IXGBE_WRITE_REG(hw,
2980 IXGBE_VLVFB((vlvf_index*2)+1),
2981 bits);
2982 }
2983 } else {
2984 /* clear the pool bit */
2985 if (vind < 32) {
2986 bits = IXGBE_READ_REG(hw,
2987 IXGBE_VLVFB(vlvf_index*2));
2988 bits &= ~(1 << vind);
2989 IXGBE_WRITE_REG(hw,
2990 IXGBE_VLVFB(vlvf_index*2),
2991 bits);
2992 bits |= IXGBE_READ_REG(hw,
2993 IXGBE_VLVFB((vlvf_index*2)+1));
2994 } else {
2995 bits = IXGBE_READ_REG(hw,
2996 IXGBE_VLVFB((vlvf_index*2)+1));
2997 bits &= ~(1 << (vind-32));
2998 IXGBE_WRITE_REG(hw,
2999 IXGBE_VLVFB((vlvf_index*2)+1),
3000 bits);
3001 bits |= IXGBE_READ_REG(hw,
3002 IXGBE_VLVFB(vlvf_index*2));
3003 }
3004 }
3005
3006 /*
3007 * If there are still bits set in the VLVFB registers
3008 * for the VLAN ID indicated we need to see if the
3009 * caller is requesting that we clear the VFTA entry bit.
3010 * If the caller has requested that we clear the VFTA
3011 * entry bit but there are still pools/VFs using this VLAN
3012 * ID entry then ignore the request. We're not worried
3013 * about the case where we're turning the VFTA VLAN ID
3014 * entry bit on, only when requested to turn it off as
3015 * there may be multiple pools and/or VFs using the
3016 * VLAN ID entry. In that case we cannot clear the
3017 * VFTA bit until all pools/VFs using that VLAN ID have also
3018 * been cleared. This will be indicated by "bits" being
3019 * zero.
3020 */
3021 if (bits) {
3022 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3023 (IXGBE_VLVF_VIEN | vlan));
3024 if (!vlan_on) {
3025 /* someone wants to clear the vfta entry
3026 * but some pools/VFs are still using it.
3027 * Ignore it. */
3028 vfta_changed = false;
3029 }
3030 }
3031 else
3032 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3033 }
3034
3035 if (vfta_changed)
3036 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3037
3038 return 0;
3039}
3040
3041/**
3042 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3043 * @hw: pointer to hardware structure
3044 *
3045 * Clears the VLAN filer table, and the VMDq index associated with the filter
3046 **/
3047s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3048{
3049 u32 offset;
3050
3051 for (offset = 0; offset < hw->mac.vft_size; offset++)
3052 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3053
3054 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3055 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3056 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3057 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3058 }
3059
3060 return 0;
3061}
3062
3063/**
3064 * ixgbe_check_mac_link_generic - Determine link and speed status
3065 * @hw: pointer to hardware structure
3066 * @speed: pointer to link speed
3067 * @link_up: true when link is up
3068 * @link_up_wait_to_complete: bool used to wait for link up or not
3069 *
3070 * Reads the links register to determine if link is up and the current speed
3071 **/
3072s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3073 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3074{
48de36c5 3075 u32 links_reg, links_orig;
21ce849b
MC		 3076 u32 i;
3077
48de36c5
ET		 3078 /* clear the old state */
3079 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3080
21ce849b 3081 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3082
3083 if (links_orig != links_reg) {
3084 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3085 links_orig, links_reg);
3086 }
3087
21ce849b
MC		 3088 if (link_up_wait_to_complete) {
3089 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3090 if (links_reg & IXGBE_LINKS_UP) {
3091 *link_up = true;
3092 break;
3093 } else {
3094 *link_up = false;
3095 }
3096 msleep(100);
3097 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3098 }
3099 } else {
3100 if (links_reg & IXGBE_LINKS_UP)
3101 *link_up = true;
3102 else
3103 *link_up = false;
3104 }
3105
3106 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3107 IXGBE_LINKS_SPEED_10G_82599)
3108 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3109 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 3110 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 3111 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 3112 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3113 IXGBE_LINKS_SPEED_100_82599)
21ce849b 3114 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 3115 else
3116 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b
MC		 3117
3118 /* if link is down, zero out the current_mode */
3119 if (*link_up == false) {
3120 hw->fc.current_mode = ixgbe_fc_none;
3121 hw->fc.fc_was_autonegged = false;
3122 }
3123
3124 return 0;
3125}
a391f1d5
DS		 3126
3127/**
3128 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
3129 * the EEPROM
3130 * @hw: pointer to hardware structure
3131 * @wwnn_prefix: the alternative WWNN prefix
3132 * @wwpn_prefix: the alternative WWPN prefix
3133 *
3134 * This function will read the EEPROM from the alternative SAN MAC address
3135 * block to check the support for the alternative WWNN/WWPN prefix support.
3136 **/
3137s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3138 u16 *wwpn_prefix)
3139{
3140 u16 offset, caps;
3141 u16 alt_san_mac_blk_offset;
3142
3143 /* clear output first */
3144 *wwnn_prefix = 0xFFFF;
3145 *wwpn_prefix = 0xFFFF;
3146
3147 /* check if alternative SAN MAC is supported */
3148 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3149 &alt_san_mac_blk_offset);
3150
3151 if ((alt_san_mac_blk_offset == 0) ||
3152 (alt_san_mac_blk_offset == 0xFFFF))
3153 goto wwn_prefix_out;
3154
3155 /* check capability in alternative san mac address block */
3156 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3157 hw->eeprom.ops.read(hw, offset, &caps);
3158 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3159 goto wwn_prefix_out;
3160
3161 /* get the corresponding prefix for WWNN/WWPN */
3162 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3163 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3164
3165 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3166 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3167
3168wwn_prefix_out:
3169 return 0;
3170}
a985b6c3 3171
0b0c2b31
ET		 3172/**
3173 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
3174 * control
3175 * @hw: pointer to hardware structure
3176 *
3177 * There are several phys that do not support autoneg flow control. This
3178 * function check the device id to see if the associated phy supports
3179 * autoneg flow control.
3180 **/
3181static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
3182{
3183
3184 switch (hw->device_id) {
3185 case IXGBE_DEV_ID_X540T:
3186 return 0;
3187 case IXGBE_DEV_ID_82599_T3_LOM:
3188 return 0;
3189 default:
3190 return IXGBE_ERR_FC_NOT_SUPPORTED;
3191 }
3192}
3193
a985b6c3
GR		 3194/**
3195 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3196 * @hw: pointer to hardware structure
3197 * @enable: enable or disable switch for anti-spoofing
3198 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3199 *
3200 **/
3201void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3202{
3203 int j;
3204 int pf_target_reg = pf >> 3;
3205 int pf_target_shift = pf % 8;
3206 u32 pfvfspoof = 0;
3207
3208 if (hw->mac.type == ixgbe_mac_82598EB)
3209 return;
3210
3211 if (enable)
3212 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3213
3214 /*
3215 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3216 * MAC anti-spoof enables in each register array element.
3217 */
3218 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3219 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3220
3221 /* If not enabling anti-spoofing then done */
3222 if (!enable)
3223 return;
3224
3225 /*
3226 * The PF should be allowed to spoof so that it can support
3227 * emulation mode NICs. Reset the bit assigned to the PF
3228 */
3229 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3230 pfvfspoof ^= (1 << pf_target_shift);
3231 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3232}
3233
3234/**
3235 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3236 * @hw: pointer to hardware structure
3237 * @enable: enable or disable switch for VLAN anti-spoofing
3238 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3239 *
3240 **/
3241void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3242{
3243 int vf_target_reg = vf >> 3;
3244 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3245 u32 pfvfspoof;
3246
3247 if (hw->mac.type == ixgbe_mac_82598EB)
3248 return;
3249
3250 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3251 if (enable)
3252 pfvfspoof |= (1 << vf_target_shift);
3253 else
3254 pfvfspoof &= ~(1 << vf_target_shift);
3255 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3256}
b776d104
ET		 3257
3258/**
3259 * ixgbe_get_device_caps_generic - Get additional device capabilities
3260 * @hw: pointer to hardware structure
3261 * @device_caps: the EEPROM word with the extra device capabilities
3262 *
3263 * This function will read the EEPROM location for the device capabilities,
3264 * and return the word through device_caps.
3265 **/
3266s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3267{
3268 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3269
3270 return 0;
3271}
80605c65
JF		 3272
3273/**
3274 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3275 * @hw: pointer to hardware structure
3276 * @num_pb: number of packet buffers to allocate
3277 * @headroom: reserve n KB of headroom
3278 * @strategy: packet buffer allocation strategy
3279 **/
3280void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3281 int num_pb,
3282 u32 headroom,
3283 int strategy)
3284{
3285 u32 pbsize = hw->mac.rx_pb_size;
3286 int i = 0;
3287 u32 rxpktsize, txpktsize, txpbthresh;
3288
3289 /* Reserve headroom */
3290 pbsize -= headroom;
3291
3292 if (!num_pb)
3293 num_pb = 1;
3294
3295 /* Divide remaining packet buffer space amongst the number
3296 * of packet buffers requested using supplied strategy.
3297 */
3298 switch (strategy) {
3299 case (PBA_STRATEGY_WEIGHTED):
3300 /* pba_80_48 strategy weight first half of packet buffer with
3301 * 5/8 of the packet buffer space.
3302 */
3303 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3304 pbsize -= rxpktsize * (num_pb / 2);
3305 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3306 for (; i < (num_pb / 2); i++)
3307 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3308 /* Fall through to configure remaining packet buffers */
3309 case (PBA_STRATEGY_EQUAL):
3310 /* Divide the remaining Rx packet buffer evenly among the TCs */
3311 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3312 for (; i < num_pb; i++)
3313 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3314 break;
3315 default:
3316 break;
3317 }
3318
3319 /*
3320 * Setup Tx packet buffer and threshold equally for all TCs
3321 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3322 * 10 since the largest packet we support is just over 9K.
3323 */
3324 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3325 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3326 for (i = 0; i < num_pb; i++) {
3327 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3328 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3329 }
3330
3331 /* Clear unused TCs, if any, to zero buffer size*/
3332 for (; i < IXGBE_MAX_PB; i++) {
3333 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3334 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3335 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3336 }
3337}
9612de92
ET		 3338
3339/**
3340 * ixgbe_calculate_checksum - Calculate checksum for buffer
3341 * @buffer: pointer to EEPROM
3342 * @length: size of EEPROM to calculate a checksum for
3343 * Calculates the checksum for some buffer on a specified length. The
3344 * checksum calculated is returned.
3345 **/
3346static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3347{
3348 u32 i;
3349 u8 sum = 0;
3350
3351 if (!buffer)
3352 return 0;
3353
3354 for (i = 0; i < length; i++)
3355 sum += buffer[i];
3356
3357 return (u8) (0 - sum);
3358}
3359
3360/**
3361 * ixgbe_host_interface_command - Issue command to manageability block
3362 * @hw: pointer to the HW structure
3363 * @buffer: contains the command to write and where the return status will
3364 * be placed
3365 * @lenght: lenght of buffer, must be multiple of 4 bytes
3366 *
3367 * Communicates with the manageability block. On success return 0
3368 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3369 **/
3370static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u8 *buffer,
3371 u32 length)
3372{
3373 u32 hicr, i;
3374 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3375 u8 buf_len, dword_len;
3376
3377 s32 ret_val = 0;
3378
3379 if (length == 0 || length & 0x3 ||
3380 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3381 hw_dbg(hw, "Buffer length failure.\n");
3382 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3383 goto out;
3384 }
3385
3386 /* Check that the host interface is enabled. */
3387 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3388 if ((hicr & IXGBE_HICR_EN) == 0) {
3389 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3390 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3391 goto out;
3392 }
3393
3394 /* Calculate length in DWORDs */
3395 dword_len = length >> 2;
3396
3397 /*
3398 * The device driver writes the relevant command block
3399 * into the ram area.
3400 */
3401 for (i = 0; i < dword_len; i++)
3402 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3403 i, *((u32 *)buffer + i));
3404
3405 /* Setting this bit tells the ARC that a new command is pending. */
3406 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3407
3408 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3409 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3410 if (!(hicr & IXGBE_HICR_C))
3411 break;
3412 usleep_range(1000, 2000);
3413 }
3414
3415 /* Check command successful completion. */
3416 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3417 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3418 hw_dbg(hw, "Command has failed with no status valid.\n");
3419 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3420 goto out;
3421 }
3422
3423 /* Calculate length in DWORDs */
3424 dword_len = hdr_size >> 2;
3425
3426 /* first pull in the header so we know the buffer length */
3427 for (i = 0; i < dword_len; i++)
3428 *((u32 *)buffer + i) =
3429 IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3430
3431 /* If there is any thing in data position pull it in */
3432 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3433 if (buf_len == 0)
3434 goto out;
3435
3436 if (length < (buf_len + hdr_size)) {
3437 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3438 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3439 goto out;
3440 }
3441
3442 /* Calculate length in DWORDs, add one for odd lengths */
3443 dword_len = (buf_len + 1) >> 2;
3444
3445 /* Pull in the rest of the buffer (i is where we left off)*/
3446 for (; i < buf_len; i++)
3447 *((u32 *)buffer + i) =
3448 IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3449
3450out:
3451 return ret_val;
3452}
3453
3454/**
3455 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3456 * @hw: pointer to the HW structure
3457 * @maj: driver version major number
3458 * @min: driver version minor number
3459 * @build: driver version build number
3460 * @sub: driver version sub build number
3461 *
3462 * Sends driver version number to firmware through the manageability
3463 * block. On success return 0
3464 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3465 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3466 **/
3467s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3468 u8 build, u8 sub)
3469{
3470 struct ixgbe_hic_drv_info fw_cmd;
3471 int i;
3472 s32 ret_val = 0;
3473
3474 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3475 ret_val = IXGBE_ERR_SWFW_SYNC;
3476 goto out;
3477 }
3478
3479 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3480 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3481 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3482 fw_cmd.port_num = (u8)hw->bus.func;
3483 fw_cmd.ver_maj = maj;
3484 fw_cmd.ver_min = min;
3485 fw_cmd.ver_build = build;
3486 fw_cmd.ver_sub = sub;
3487 fw_cmd.hdr.checksum = 0;
3488 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3489 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3490 fw_cmd.pad = 0;
3491 fw_cmd.pad2 = 0;
3492
3493 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3494 ret_val = ixgbe_host_interface_command(hw, (u8 *)&fw_cmd,
3495 sizeof(fw_cmd));
3496 if (ret_val != 0)
3497 continue;
3498
3499 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3500 FW_CEM_RESP_STATUS_SUCCESS)
3501 ret_val = 0;
3502 else
3503 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3504
3505 break;
3506 }
3507
3508 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3509out:
3510 return ret_val;
3511}
Linux kernel - Deliverables
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