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ixgbe: fix build err, num_rx_queues is only available with CONFIG_RPS
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
2a47fa45 47#include <linux/if_macvlan.h>
815cccbf 48#include <linux/if_bridge.h>
70c71606 49#include <linux/prefetch.h>
eacd73f7 50#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 51
52#include "ixgbe.h"
53#include "ixgbe_common.h"
ee5f784a 54#include "ixgbe_dcb_82599.h"
1cdd1ec8 55#include "ixgbe_sriov.h"
9a799d71
AK		 56
57char ixgbe_driver_name[] = "ixgbe";
9c8eb720 58static const char ixgbe_driver_string[] =
e8e9f696 59 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 60#ifdef IXGBE_FCOE
ea81875a
NP		 61char ixgbe_default_device_descr[] =
62 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 63#else
64static char ixgbe_default_device_descr[] =
65 "Intel(R) 10 Gigabit Network Connection";
66#endif
93ac03be 67#define DRV_VERSION "3.15.1-k"
9c8eb720 68const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 69static const char ixgbe_copyright[] =
434c5e39 70 "Copyright (c) 1999-2013 Intel Corporation.";
9a799d71
AK		 71
72static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 73 [board_82598] = &ixgbe_82598_info,
e8e26350 74 [board_82599] = &ixgbe_82599_info,
fe15e8e1 75 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 76};
77
78/* ixgbe_pci_tbl - PCI Device ID Table
79 *
80 * Wildcard entries (PCI_ANY_ID) should come last
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
a3aa1884 86static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
b8e82001
JK		 154static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
155 u32 reg, u16 *value)
156{
b8e82001
JK		 157 struct pci_dev *parent_dev;
158 struct pci_bus *parent_bus;
159
160 parent_bus = adapter->pdev->bus->parent;
161 if (!parent_bus)
162 return -1;
163
164 parent_dev = parent_bus->self;
165 if (!parent_dev)
166 return -1;
167
c0798edf 168 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 169 return -1;
170
c0798edf 171 pcie_capability_read_word(parent_dev, reg, value);
b8e82001
JK		 172 return 0;
173}
174
175static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176{
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196}
197
e027d1ae
JK		 198/**
199 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
200 * @hw: hw specific details
201 *
202 * This function is used by probe to determine whether a device's PCI-Express
203 * bandwidth details should be gathered from the parent bus instead of from the
204 * device. Used to ensure that various locations all have the correct device ID
205 * checks.
206 */
207static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
208{
209 switch (hw->device_id) {
210 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 211 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 212 return true;
213 default:
214 return false;
215 }
216}
217
218static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
219 int expected_gts)
220{
221 int max_gts = 0;
222 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
223 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
224 struct pci_dev *pdev;
225
226 /* determine whether to use the the parent device
227 */
228 if (ixgbe_pcie_from_parent(&adapter->hw))
229 pdev = adapter->pdev->bus->parent->self;
230 else
231 pdev = adapter->pdev;
232
233 if (pcie_get_minimum_link(pdev, &speed, &width) ||
234 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
235 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
236 return;
237 }
238
239 switch (speed) {
240 case PCIE_SPEED_2_5GT:
241 /* 8b/10b encoding reduces max throughput by 20% */
242 max_gts = 2 * width;
243 break;
244 case PCIE_SPEED_5_0GT:
245 /* 8b/10b encoding reduces max throughput by 20% */
246 max_gts = 4 * width;
247 break;
248 case PCIE_SPEED_8_0GT:
9f0a433c 249 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 250 max_gts = 8 * width;
251 break;
252 default:
253 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
254 return;
255 }
256
257 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
258 max_gts);
259 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
260 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
261 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
262 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
263 "Unknown"),
264 width,
265 (speed == PCIE_SPEED_2_5GT ? "20%" :
266 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 267 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 268 "Unknown"));
269
270 if (max_gts < expected_gts) {
271 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
272 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
273 expected_gts);
274 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
275 }
276}
277
7086400d
AD		 278static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
279{
280 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
281 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
282 schedule_work(&adapter->service_task);
283}
284
285static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
286{
287 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
288
52f33af8 289 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 290 smp_mb__before_clear_bit();
291 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
292}
293
dcd79aeb
TI		 294struct ixgbe_reg_info {
295 u32 ofs;
296 char *name;
297};
298
299static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
300
301 /* General Registers */
302 {IXGBE_CTRL, "CTRL"},
303 {IXGBE_STATUS, "STATUS"},
304 {IXGBE_CTRL_EXT, "CTRL_EXT"},
305
306 /* Interrupt Registers */
307 {IXGBE_EICR, "EICR"},
308
309 /* RX Registers */
310 {IXGBE_SRRCTL(0), "SRRCTL"},
311 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
312 {IXGBE_RDLEN(0), "RDLEN"},
313 {IXGBE_RDH(0), "RDH"},
314 {IXGBE_RDT(0), "RDT"},
315 {IXGBE_RXDCTL(0), "RXDCTL"},
316 {IXGBE_RDBAL(0), "RDBAL"},
317 {IXGBE_RDBAH(0), "RDBAH"},
318
319 /* TX Registers */
320 {IXGBE_TDBAL(0), "TDBAL"},
321 {IXGBE_TDBAH(0), "TDBAH"},
322 {IXGBE_TDLEN(0), "TDLEN"},
323 {IXGBE_TDH(0), "TDH"},
324 {IXGBE_TDT(0), "TDT"},
325 {IXGBE_TXDCTL(0), "TXDCTL"},
326
327 /* List Terminator */
328 {}
329};
330
331
332/*
333 * ixgbe_regdump - register printout routine
334 */
335static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
336{
337 int i = 0, j = 0;
338 char rname[16];
339 u32 regs[64];
340
341 switch (reginfo->ofs) {
342 case IXGBE_SRRCTL(0):
343 for (i = 0; i < 64; i++)
344 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
345 break;
346 case IXGBE_DCA_RXCTRL(0):
347 for (i = 0; i < 64; i++)
348 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
349 break;
350 case IXGBE_RDLEN(0):
351 for (i = 0; i < 64; i++)
352 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
353 break;
354 case IXGBE_RDH(0):
355 for (i = 0; i < 64; i++)
356 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
357 break;
358 case IXGBE_RDT(0):
359 for (i = 0; i < 64; i++)
360 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
361 break;
362 case IXGBE_RXDCTL(0):
363 for (i = 0; i < 64; i++)
364 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
365 break;
366 case IXGBE_RDBAL(0):
367 for (i = 0; i < 64; i++)
368 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
369 break;
370 case IXGBE_RDBAH(0):
371 for (i = 0; i < 64; i++)
372 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
373 break;
374 case IXGBE_TDBAL(0):
375 for (i = 0; i < 64; i++)
376 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
377 break;
378 case IXGBE_TDBAH(0):
379 for (i = 0; i < 64; i++)
380 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
381 break;
382 case IXGBE_TDLEN(0):
383 for (i = 0; i < 64; i++)
384 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
385 break;
386 case IXGBE_TDH(0):
387 for (i = 0; i < 64; i++)
388 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
389 break;
390 case IXGBE_TDT(0):
391 for (i = 0; i < 64; i++)
392 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
393 break;
394 case IXGBE_TXDCTL(0):
395 for (i = 0; i < 64; i++)
396 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
397 break;
398 default:
c7689578 399 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 400 IXGBE_READ_REG(hw, reginfo->ofs));
401 return;
402 }
403
404 for (i = 0; i < 8; i++) {
405 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 406 pr_err("%-15s", rname);
dcd79aeb 407 for (j = 0; j < 8; j++)
c7689578
JP		 408 pr_cont(" %08x", regs[i*8+j]);
409 pr_cont("\n");
dcd79aeb
TI		 410 }
411
412}
413
414/*
415 * ixgbe_dump - Print registers, tx-rings and rx-rings
416 */
417static void ixgbe_dump(struct ixgbe_adapter *adapter)
418{
419 struct net_device *netdev = adapter->netdev;
420 struct ixgbe_hw *hw = &adapter->hw;
421 struct ixgbe_reg_info *reginfo;
422 int n = 0;
423 struct ixgbe_ring *tx_ring;
729739b7 424 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 425 union ixgbe_adv_tx_desc *tx_desc;
426 struct my_u0 { u64 a; u64 b; } *u0;
427 struct ixgbe_ring *rx_ring;
428 union ixgbe_adv_rx_desc *rx_desc;
429 struct ixgbe_rx_buffer *rx_buffer_info;
430 u32 staterr;
431 int i = 0;
432
433 if (!netif_msg_hw(adapter))
434 return;
435
436 /* Print netdevice Info */
437 if (netdev) {
438 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 439 pr_info("Device Name state "
dcd79aeb 440 "trans_start last_rx\n");
c7689578
JP		 441 pr_info("%-15s %016lX %016lX %016lX\n",
442 netdev->name,
443 netdev->state,
444 netdev->trans_start,
445 netdev->last_rx);
dcd79aeb
TI		 446 }
447
448 /* Print Registers */
449 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 450 pr_info(" Register Name Value\n");
dcd79aeb
TI		 451 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
452 reginfo->name; reginfo++) {
453 ixgbe_regdump(hw, reginfo);
454 }
455
456 /* Print TX Ring Summary */
457 if (!netdev || !netif_running(netdev))
458 goto exit;
459
460 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 461 pr_info(" %s %s %s %s\n",
462 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
463 "leng", "ntw", "timestamp");
dcd79aeb
TI		 464 for (n = 0; n < adapter->num_tx_queues; n++) {
465 tx_ring = adapter->tx_ring[n];
729739b7 466 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 467 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 468 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 469 (u64)dma_unmap_addr(tx_buffer, dma),
470 dma_unmap_len(tx_buffer, len),
471 tx_buffer->next_to_watch,
472 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 473 }
474
475 /* Print TX Rings */
476 if (!netif_msg_tx_done(adapter))
477 goto rx_ring_summary;
478
479 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
480
481 /* Transmit Descriptor Formats
482 *
39ac868a 483 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 484 * +--------------------------------------------------------------+
485 * 0 | Buffer Address [63:0] |
486 * +--------------------------------------------------------------+
39ac868a 487 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 488 * +--------------------------------------------------------------+
489 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 490 *
491 * 82598 Advanced Transmit Descriptor (Write-Back Format)
492 * +--------------------------------------------------------------+
493 * 0 | RSV [63:0] |
494 * +--------------------------------------------------------------+
495 * 8 | RSV | STA | NXTSEQ |
496 * +--------------------------------------------------------------+
497 * 63 36 35 32 31 0
498 *
499 * 82599+ Advanced Transmit Descriptor
500 * +--------------------------------------------------------------+
501 * 0 | Buffer Address [63:0] |
502 * +--------------------------------------------------------------+
503 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
504 * +--------------------------------------------------------------+
505 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
506 *
507 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
508 * +--------------------------------------------------------------+
509 * 0 | RSV [63:0] |
510 * +--------------------------------------------------------------+
511 * 8 | RSV | STA | RSV |
512 * +--------------------------------------------------------------+
513 * 63 36 35 32 31 0
dcd79aeb
TI		 514 */
515
516 for (n = 0; n < adapter->num_tx_queues; n++) {
517 tx_ring = adapter->tx_ring[n];
c7689578
JP		 518 pr_info("------------------------------------\n");
519 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
520 pr_info("------------------------------------\n");
8ad88e37
JH		 521 pr_info("%s%s %s %s %s %s\n",
522 "T [desc] [address 63:0 ] ",
523 "[PlPOIdStDDt Ln] [bi->dma ] ",
524 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 525
526 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 527 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 528 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 529 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 530 if (dma_unmap_len(tx_buffer, len) > 0) {
531 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
532 i,
533 le64_to_cpu(u0->a),
534 le64_to_cpu(u0->b),
535 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 536 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 537 tx_buffer->next_to_watch,
538 (u64)tx_buffer->time_stamp,
539 tx_buffer->skb);
540 if (i == tx_ring->next_to_use &&
541 i == tx_ring->next_to_clean)
542 pr_cont(" NTC/U\n");
543 else if (i == tx_ring->next_to_use)
544 pr_cont(" NTU\n");
545 else if (i == tx_ring->next_to_clean)
546 pr_cont(" NTC\n");
547 else
548 pr_cont("\n");
549
550 if (netif_msg_pktdata(adapter) &&
551 tx_buffer->skb)
552 print_hex_dump(KERN_INFO, "",
553 DUMP_PREFIX_ADDRESS, 16, 1,
554 tx_buffer->skb->data,
555 dma_unmap_len(tx_buffer, len),
556 true);
557 }
dcd79aeb
TI		 558 }
559 }
560
561 /* Print RX Rings Summary */
562rx_ring_summary:
563 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 564 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 565 for (n = 0; n < adapter->num_rx_queues; n++) {
566 rx_ring = adapter->rx_ring[n];
c7689578
JP		 567 pr_info("%5d %5X %5X\n",
568 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 569 }
570
571 /* Print RX Rings */
572 if (!netif_msg_rx_status(adapter))
573 goto exit;
574
575 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
576
39ac868a
JH		 577 /* Receive Descriptor Formats
578 *
579 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 580 * 63 1 0
581 * +-----------------------------------------------------+
582 * 0 | Packet Buffer Address [63:1] |A0/NSE|
583 * +----------------------------------------------+------+
584 * 8 | Header Buffer Address [63:1] | DD |
585 * +-----------------------------------------------------+
586 *
587 *
39ac868a 588 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 589 *
590 * 63 48 47 32 31 30 21 20 16 15 4 3 0
591 * +------------------------------------------------------+
39ac868a
JH		 592 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
593 * | Packet | IP | | | | Type | Type |
594 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 595 * +------------------------------------------------------+
596 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
597 * +------------------------------------------------------+
598 * 63 48 47 32 31 20 19 0
39ac868a
JH		 599 *
600 * 82599+ Advanced Receive Descriptor (Read) Format
601 * 63 1 0
602 * +-----------------------------------------------------+
603 * 0 | Packet Buffer Address [63:1] |A0/NSE|
604 * +----------------------------------------------+------+
605 * 8 | Header Buffer Address [63:1] | DD |
606 * +-----------------------------------------------------+
607 *
608 *
609 * 82599+ Advanced Receive Descriptor (Write-Back) Format
610 *
611 * 63 48 47 32 31 30 21 20 17 16 4 3 0
612 * +------------------------------------------------------+
613 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
614 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
615 * |/ Flow Dir Flt ID | | | | | |
616 * +------------------------------------------------------+
617 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
618 * +------------------------------------------------------+
619 * 63 48 47 32 31 20 19 0
dcd79aeb 620 */
39ac868a 621
dcd79aeb
TI		 622 for (n = 0; n < adapter->num_rx_queues; n++) {
623 rx_ring = adapter->rx_ring[n];
c7689578
JP		 624 pr_info("------------------------------------\n");
625 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
626 pr_info("------------------------------------\n");
8ad88e37
JH		 627 pr_info("%s%s%s",
628 "R [desc] [ PktBuf A0] ",
629 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 630 "<-- Adv Rx Read format\n");
8ad88e37
JH		 631 pr_info("%s%s%s",
632 "RWB[desc] [PcsmIpSHl PtRs] ",
633 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 634 "<-- Adv Rx Write-Back format\n");
635
636 for (i = 0; i < rx_ring->count; i++) {
637 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 638 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 639 u0 = (struct my_u0 *)rx_desc;
640 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
641 if (staterr & IXGBE_RXD_STAT_DD) {
642 /* Descriptor Done */
c7689578 643 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 644 "%016llX ---------------- %p", i,
645 le64_to_cpu(u0->a),
646 le64_to_cpu(u0->b),
647 rx_buffer_info->skb);
648 } else {
c7689578 649 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 650 "%016llX %016llX %p", i,
651 le64_to_cpu(u0->a),
652 le64_to_cpu(u0->b),
653 (u64)rx_buffer_info->dma,
654 rx_buffer_info->skb);
655
9c50c035
ET		 656 if (netif_msg_pktdata(adapter) &&
657 rx_buffer_info->dma) {
dcd79aeb
TI		 658 print_hex_dump(KERN_INFO, "",
659 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 660 page_address(rx_buffer_info->page) +
661 rx_buffer_info->page_offset,
f800326d 662 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 663 }
664 }
665
666 if (i == rx_ring->next_to_use)
c7689578 667 pr_cont(" NTU\n");
dcd79aeb 668 else if (i == rx_ring->next_to_clean)
c7689578 669 pr_cont(" NTC\n");
dcd79aeb 670 else
c7689578 671 pr_cont("\n");
dcd79aeb
TI		 672
673 }
674 }
675
676exit:
677 return;
678}
679
5eba3699
AV		 680static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
681{
682 u32 ctrl_ext;
683
684 /* Let firmware take over control of h/w */
685 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
686 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 687 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 688}
689
690static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
691{
692 u32 ctrl_ext;
693
694 /* Let firmware know the driver has taken over */
695 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 697 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 698}
9a799d71 699
49ce9c2c 700/**
e8e26350
PW		 701 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
702 * @adapter: pointer to adapter struct
703 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
704 * @queue: queue to map the corresponding interrupt to
705 * @msix_vector: the vector to map to the corresponding queue
706 *
707 */
708static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 709 u8 queue, u8 msix_vector)
9a799d71
AK		 710{
711 u32 ivar, index;
e8e26350
PW		 712 struct ixgbe_hw *hw = &adapter->hw;
713 switch (hw->mac.type) {
714 case ixgbe_mac_82598EB:
715 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
716 if (direction == -1)
717 direction = 0;
718 index = (((direction * 64) + queue) >> 2) & 0x1F;
719 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
720 ivar &= ~(0xFF << (8 * (queue & 0x3)));
721 ivar |= (msix_vector << (8 * (queue & 0x3)));
722 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
723 break;
724 case ixgbe_mac_82599EB:
b93a2226 725 case ixgbe_mac_X540:
e8e26350
PW		 726 if (direction == -1) {
727 /* other causes */
728 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
729 index = ((queue & 1) * 8);
730 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
731 ivar &= ~(0xFF << index);
732 ivar |= (msix_vector << index);
733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
734 break;
735 } else {
736 /* tx or rx causes */
737 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
738 index = ((16 * (queue & 1)) + (8 * direction));
739 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
740 ivar &= ~(0xFF << index);
741 ivar |= (msix_vector << index);
742 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
743 break;
744 }
745 default:
746 break;
747 }
9a799d71
AK		 748}
749
fe49f04a 750static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 751 u64 qmask)
fe49f04a
AD		 752{
753 u32 mask;
754
bd508178
AD		 755 switch (adapter->hw.mac.type) {
756 case ixgbe_mac_82598EB:
fe49f04a
AD		 757 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 759 break;
760 case ixgbe_mac_82599EB:
b93a2226 761 case ixgbe_mac_X540:
fe49f04a
AD		 762 mask = (qmask & 0xFFFFFFFF);
763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
764 mask = (qmask >> 32);
765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 766 break;
767 default:
768 break;
fe49f04a
AD		 769 }
770}
771
729739b7
AD		 772void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
773 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 774{
729739b7
AD		 775 if (tx_buffer->skb) {
776 dev_kfree_skb_any(tx_buffer->skb);
777 if (dma_unmap_len(tx_buffer, len))
d3d00239 778 dma_unmap_single(ring->dev,
729739b7
AD		 779 dma_unmap_addr(tx_buffer, dma),
780 dma_unmap_len(tx_buffer, len),
781 DMA_TO_DEVICE);
782 } else if (dma_unmap_len(tx_buffer, len)) {
783 dma_unmap_page(ring->dev,
784 dma_unmap_addr(tx_buffer, dma),
785 dma_unmap_len(tx_buffer, len),
786 DMA_TO_DEVICE);
e5a43549 787 }
729739b7
AD		 788 tx_buffer->next_to_watch = NULL;
789 tx_buffer->skb = NULL;
790 dma_unmap_len_set(tx_buffer, len, 0);
791 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 792}
793
943561d3 794static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 795{
796 struct ixgbe_hw *hw = &adapter->hw;
797 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 798 int i;
943561d3 799 u32 data;
c84d324c 800
943561d3
AD		 801 if ((hw->fc.current_mode != ixgbe_fc_full) &&
802 (hw->fc.current_mode != ixgbe_fc_rx_pause))
803 return;
c84d324c 804
943561d3
AD		 805 switch (hw->mac.type) {
806 case ixgbe_mac_82598EB:
807 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
808 break;
809 default:
810 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
811 }
812 hwstats->lxoffrxc += data;
c84d324c 813
943561d3
AD		 814 /* refill credits (no tx hang) if we received xoff */
815 if (!data)
c84d324c 816 return;
943561d3
AD		 817
818 for (i = 0; i < adapter->num_tx_queues; i++)
819 clear_bit(__IXGBE_HANG_CHECK_ARMED,
820 &adapter->tx_ring[i]->state);
821}
822
823static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
824{
825 struct ixgbe_hw *hw = &adapter->hw;
826 struct ixgbe_hw_stats *hwstats = &adapter->stats;
827 u32 xoff[8] = {0};
2afaa00d 828 u8 tc;
943561d3
AD		 829 int i;
830 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
831
832 if (adapter->ixgbe_ieee_pfc)
833 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
834
835 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
836 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 837 return;
943561d3 838 }
c84d324c
JF		 839
840 /* update stats for each tc, only valid with PFC enabled */
841 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 842 u32 pxoffrxc;
843
c84d324c
JF		 844 switch (hw->mac.type) {
845 case ixgbe_mac_82598EB:
2afaa00d 846 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 847 break;
c84d324c 848 default:
2afaa00d 849 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 850 }
2afaa00d
PN		 851 hwstats->pxoffrxc[i] += pxoffrxc;
852 /* Get the TC for given UP */
853 tc = netdev_get_prio_tc_map(adapter->netdev, i);
854 xoff[tc] += pxoffrxc;
c84d324c
JF		 855 }
856
857 /* disarm tx queues that have received xoff frames */
858 for (i = 0; i < adapter->num_tx_queues; i++) {
859 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 860
2afaa00d 861 tc = tx_ring->dcb_tc;
c84d324c
JF		 862 if (xoff[tc])
863 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 864 }
26f23d82
YZ		 865}
866
c84d324c 867static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 868{
7d7ce682 869 return ring->stats.packets;
c84d324c
JF		 870}
871
872static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
873{
2a47fa45
JF		 874 struct ixgbe_adapter *adapter;
875 struct ixgbe_hw *hw;
876 u32 head, tail;
877
878 if (ring->l2_accel_priv)
879 adapter = ring->l2_accel_priv->real_adapter;
880 else
881 adapter = netdev_priv(ring->netdev);
e01c31a5 882
2a47fa45
JF		 883 hw = &adapter->hw;
884 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
885 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 886
887 if (head != tail)
888 return (head < tail) ?
889 tail - head : (tail + ring->count - head);
890
891 return 0;
892}
893
894static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
895{
896 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
897 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
898 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
899 bool ret = false;
900
7d637bcc 901 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 902
903 /*
904 * Check for a hung queue, but be thorough. This verifies
905 * that a transmit has been completed since the previous
906 * check AND there is at least one packet pending. The
907 * ARMED bit is set to indicate a potential hang. The
908 * bit is cleared if a pause frame is received to remove
909 * false hang detection due to PFC or 802.3x frames. By
910 * requiring this to fail twice we avoid races with
911 * pfc clearing the ARMED bit and conditions where we
912 * run the check_tx_hang logic with a transmit completion
913 * pending but without time to complete it yet.
914 */
915 if ((tx_done_old == tx_done) && tx_pending) {
916 /* make sure it is true for two checks in a row */
917 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
918 &tx_ring->state);
919 } else {
920 /* update completed stats and continue */
921 tx_ring->tx_stats.tx_done_old = tx_done;
922 /* reset the countdown */
923 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 924 }
925
c84d324c 926 return ret;
9a799d71
AK		 927}
928
c83c6cbd
AD		 929/**
930 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
931 * @adapter: driver private struct
932 **/
933static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
934{
935
936 /* Do the reset outside of interrupt context */
937 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
938 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 939 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 940 ixgbe_service_event_schedule(adapter);
941 }
942}
e01c31a5 943
9a799d71
AK		 944/**
945 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 946 * @q_vector: structure containing interrupt and ring information
e01c31a5 947 * @tx_ring: tx ring to clean
9a799d71 948 **/
fe49f04a 949static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 950 struct ixgbe_ring *tx_ring)
9a799d71 951{
fe49f04a 952 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 953 struct ixgbe_tx_buffer *tx_buffer;
954 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 955 unsigned int total_bytes = 0, total_packets = 0;
59224555 956 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 957 unsigned int i = tx_ring->next_to_clean;
958
959 if (test_bit(__IXGBE_DOWN, &adapter->state))
960 return true;
9a799d71 961
d3d00239 962 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 963 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 964 i -= tx_ring->count;
12207e49 965
729739b7 966 do {
d3d00239
AD		 967 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
968
969 /* if next_to_watch is not set then there is no work pending */
970 if (!eop_desc)
971 break;
972
7f83a9e6 973 /* prevent any other reads prior to eop_desc */
7e63bf49 974 read_barrier_depends();
7f83a9e6 975
d3d00239
AD		 976 /* if DD is not set pending work has not been completed */
977 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
978 break;
8ad494b0 979
d3d00239
AD		 980 /* clear next_to_watch to prevent false hangs */
981 tx_buffer->next_to_watch = NULL;
8ad494b0 982
091a6246
AD		 983 /* update the statistics for this packet */
984 total_bytes += tx_buffer->bytecount;
985 total_packets += tx_buffer->gso_segs;
986
fd0db0ed
AD		 987 /* free the skb */
988 dev_kfree_skb_any(tx_buffer->skb);
989
729739b7
AD		 990 /* unmap skb header data */
991 dma_unmap_single(tx_ring->dev,
992 dma_unmap_addr(tx_buffer, dma),
993 dma_unmap_len(tx_buffer, len),
994 DMA_TO_DEVICE);
995
fd0db0ed
AD		 996 /* clear tx_buffer data */
997 tx_buffer->skb = NULL;
729739b7 998 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 999
729739b7
AD		 1000 /* unmap remaining buffers */
1001 while (tx_desc != eop_desc) {
d3d00239
AD		 1002 tx_buffer++;
1003 tx_desc++;
8ad494b0 1004 i++;
729739b7
AD		 1005 if (unlikely(!i)) {
1006 i -= tx_ring->count;
d3d00239 1007 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1008 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1009 }
e01c31a5 1010
729739b7
AD		 1011 /* unmap any remaining paged data */
1012 if (dma_unmap_len(tx_buffer, len)) {
1013 dma_unmap_page(tx_ring->dev,
1014 dma_unmap_addr(tx_buffer, dma),
1015 dma_unmap_len(tx_buffer, len),
1016 DMA_TO_DEVICE);
1017 dma_unmap_len_set(tx_buffer, len, 0);
1018 }
1019 }
1020
1021 /* move us one more past the eop_desc for start of next pkt */
1022 tx_buffer++;
1023 tx_desc++;
1024 i++;
1025 if (unlikely(!i)) {
1026 i -= tx_ring->count;
1027 tx_buffer = tx_ring->tx_buffer_info;
1028 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1029 }
1030
1031 /* issue prefetch for next Tx descriptor */
1032 prefetch(tx_desc);
12207e49 1033
729739b7
AD		 1034 /* update budget accounting */
1035 budget--;
1036 } while (likely(budget));
1037
1038 i += tx_ring->count;
9a799d71 1039 tx_ring->next_to_clean = i;
d3d00239 1040 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1041 tx_ring->stats.bytes += total_bytes;
bd198058 1042 tx_ring->stats.packets += total_packets;
d3d00239 1043 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1044 q_vector->tx.total_bytes += total_bytes;
1045 q_vector->tx.total_packets += total_packets;
b953799e 1046
c84d324c
JF		 1047 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1048 /* schedule immediate reset if we believe we hung */
1049 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1050 e_err(drv, "Detected Tx Unit Hang\n"
1051 " Tx Queue <%d>\n"
1052 " TDH, TDT <%x>, <%x>\n"
1053 " next_to_use <%x>\n"
1054 " next_to_clean <%x>\n"
1055 "tx_buffer_info[next_to_clean]\n"
1056 " time_stamp <%lx>\n"
1057 " jiffies <%lx>\n",
1058 tx_ring->queue_index,
1059 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1060 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1061 tx_ring->next_to_use, i,
1062 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1063
1064 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1065
1066 e_info(probe,
1067 "tx hang %d detected on queue %d, resetting adapter\n",
1068 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1069
b953799e 1070 /* schedule immediate reset if we believe we hung */
c83c6cbd 1071 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1072
1073 /* the adapter is about to reset, no point in enabling stuff */
59224555 1074 return true;
b953799e 1075 }
9a799d71 1076
b2d96e0a
AD		 1077 netdev_tx_completed_queue(txring_txq(tx_ring),
1078 total_packets, total_bytes);
1079
e092be60 1080#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1081 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1082 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1083 /* Make sure that anybody stopping the queue after this
1084 * sees the new next_to_clean.
1085 */
1086 smp_mb();
729739b7
AD		 1087 if (__netif_subqueue_stopped(tx_ring->netdev,
1088 tx_ring->queue_index)
1089 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1090 netif_wake_subqueue(tx_ring->netdev,
1091 tx_ring->queue_index);
5b7da515 1092 ++tx_ring->tx_stats.restart_queue;
30eba97a 1093 }
e092be60 1094 }
9a799d71 1095
59224555 1096 return !!budget;
9a799d71
AK		 1097}
1098
5dd2d332 1099#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1100static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1101 struct ixgbe_ring *tx_ring,
33cf09c9 1102 int cpu)
bd0362dd 1103{
33cf09c9 1104 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1105 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1106 u16 reg_offset;
33cf09c9 1107
33cf09c9
AD		 1108 switch (hw->mac.type) {
1109 case ixgbe_mac_82598EB:
bdda1a61 1110 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1111 break;
1112 case ixgbe_mac_82599EB:
b93a2226 1113 case ixgbe_mac_X540:
bdda1a61
AD		 1114 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1115 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1116 break;
1117 default:
bdda1a61
AD		 1118 /* for unknown hardware do not write register */
1119 return;
bd0362dd 1120 }
bdda1a61
AD		 1121
1122 /*
1123 * We can enable relaxed ordering for reads, but not writes when
1124 * DCA is enabled. This is due to a known issue in some chipsets
1125 * which will cause the DCA tag to be cleared.
1126 */
1127 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1128 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1129 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1130
1131 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1132}
1133
bdda1a61
AD		 1134static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1135 struct ixgbe_ring *rx_ring,
33cf09c9 1136 int cpu)
bd0362dd 1137{
33cf09c9 1138 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1139 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1140 u8 reg_idx = rx_ring->reg_idx;
1141
33cf09c9
AD		 1142
1143 switch (hw->mac.type) {
33cf09c9 1144 case ixgbe_mac_82599EB:
b93a2226 1145 case ixgbe_mac_X540:
bdda1a61 1146 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1147 break;
1148 default:
1149 break;
1150 }
bdda1a61
AD		 1151
1152 /*
1153 * We can enable relaxed ordering for reads, but not writes when
1154 * DCA is enabled. This is due to a known issue in some chipsets
1155 * which will cause the DCA tag to be cleared.
1156 */
1157 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1158 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1159
1160 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1161}
1162
1163static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1164{
1165 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1166 struct ixgbe_ring *ring;
bd0362dd 1167 int cpu = get_cpu();
bd0362dd 1168
33cf09c9
AD		 1169 if (q_vector->cpu == cpu)
1170 goto out_no_update;
1171
a557928e 1172 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1173 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1174
a557928e 1175 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1176 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1177
1178 q_vector->cpu = cpu;
1179out_no_update:
bd0362dd
JC		 1180 put_cpu();
1181}
1182
1183static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1184{
1185 int i;
1186
1187 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1188 return;
1189
e35ec126
AD		 1190 /* always use CB2 mode, difference is masked in the CB driver */
1191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1192
49c7ffbe 1193 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1194 adapter->q_vector[i]->cpu = -1;
1195 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1196 }
1197}
1198
1199static int __ixgbe_notify_dca(struct device *dev, void *data)
1200{
c60fbb00 1201 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1202 unsigned long event = *(unsigned long *)data;
1203
2a72c31e 1204 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1205 return 0;
1206
bd0362dd
JC		 1207 switch (event) {
1208 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1209 /* if we're already enabled, don't do it again */
1210 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1211 break;
652f093f 1212 if (dca_add_requester(dev) == 0) {
96b0e0f6 1213 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1214 ixgbe_setup_dca(adapter);
1215 break;
1216 }
1217 /* Fall Through since DCA is disabled. */
1218 case DCA_PROVIDER_REMOVE:
1219 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1220 dca_remove_requester(dev);
1221 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1222 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1223 }
1224 break;
1225 }
1226
652f093f 1227 return 0;
bd0362dd 1228}
67a74ee2 1229
bdda1a61 1230#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1231static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1232 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1233 struct sk_buff *skb)
1234{
8a0da21b
AD		 1235 if (ring->netdev->features & NETIF_F_RXHASH)
1236 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1237}
1238
f800326d 1239#ifdef IXGBE_FCOE
ff886dfc
AD		 1240/**
1241 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1242 * @ring: structure containing ring specific data
ff886dfc
AD		 1243 * @rx_desc: advanced rx descriptor
1244 *
1245 * Returns : true if it is FCoE pkt
1246 */
57efd44c 1247static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1248 union ixgbe_adv_rx_desc *rx_desc)
1249{
1250 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1251
57efd44c 1252 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1253 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1254 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1255 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1256}
1257
f800326d 1258#endif /* IXGBE_FCOE */
e59bd25d
AV		 1259/**
1260 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1261 * @ring: structure containing ring specific data
1262 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1263 * @skb: skb currently being received and modified
1264 **/
8a0da21b 1265static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1266 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1267 struct sk_buff *skb)
9a799d71 1268{
8a0da21b 1269 skb_checksum_none_assert(skb);
9a799d71 1270
712744be 1271 /* Rx csum disabled */
8a0da21b 1272 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1273 return;
e59bd25d
AV		 1274
1275 /* if IP and error */
f56e0cb1
AD		 1276 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1277 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1278 ring->rx_stats.csum_err++;
9a799d71
AK		 1279 return;
1280 }
e59bd25d 1281
f56e0cb1 1282 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1283 return;
1284
f56e0cb1 1285 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1286 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1287
1288 /*
1289 * 82599 errata, UDP frames with a 0 checksum can be marked as
1290 * checksum errors.
1291 */
8a0da21b
AD		 1292 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1293 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1294 return;
1295
8a0da21b 1296 ring->rx_stats.csum_err++;
e59bd25d
AV		 1297 return;
1298 }
1299
9a799d71 1300 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1301 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1302}
1303
84ea2591 1304static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1305{
f56e0cb1 1306 rx_ring->next_to_use = val;
f800326d
AD		 1307
1308 /* update next to alloc since we have filled the ring */
1309 rx_ring->next_to_alloc = val;
e8e26350
PW		 1310 /*
1311 * Force memory writes to complete before letting h/w
1312 * know there are new descriptors to fetch. (Only
1313 * applicable for weak-ordered memory model archs,
1314 * such as IA-64).
1315 */
1316 wmb();
84ea2591 1317 writel(val, rx_ring->tail);
e8e26350
PW		 1318}
1319
f990b79b
AD		 1320static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1321 struct ixgbe_rx_buffer *bi)
1322{
1323 struct page *page = bi->page;
f800326d 1324 dma_addr_t dma = bi->dma;
f990b79b 1325
f800326d
AD		 1326 /* since we are recycling buffers we should seldom need to alloc */
1327 if (likely(dma))
f990b79b
AD		 1328 return true;
1329
f800326d
AD		 1330 /* alloc new page for storage */
1331 if (likely(!page)) {
0614002b
MG		 1332 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1333 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1334 if (unlikely(!page)) {
1335 rx_ring->rx_stats.alloc_rx_page_failed++;
1336 return false;
1337 }
f800326d 1338 bi->page = page;
f990b79b
AD		 1339 }
1340
f800326d
AD		 1341 /* map page for use */
1342 dma = dma_map_page(rx_ring->dev, page, 0,
1343 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1344
1345 /*
1346 * if mapping failed free memory back to system since
1347 * there isn't much point in holding memory we can't use
1348 */
1349 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1350 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1351 bi->page = NULL;
f990b79b 1352
f990b79b
AD		 1353 rx_ring->rx_stats.alloc_rx_page_failed++;
1354 return false;
1355 }
1356
f800326d 1357 bi->dma = dma;
afaa9459 1358 bi->page_offset = 0;
f800326d 1359
f990b79b
AD		 1360 return true;
1361}
1362
9a799d71 1363/**
f990b79b 1364 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1365 * @rx_ring: ring to place buffers on
1366 * @cleaned_count: number of buffers to replace
9a799d71 1367 **/
fc77dc3c 1368void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1369{
9a799d71 1370 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1371 struct ixgbe_rx_buffer *bi;
d5f398ed 1372 u16 i = rx_ring->next_to_use;
9a799d71 1373
f800326d
AD		 1374 /* nothing to do */
1375 if (!cleaned_count)
fc77dc3c
AD		 1376 return;
1377
e4f74028 1378 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1379 bi = &rx_ring->rx_buffer_info[i];
1380 i -= rx_ring->count;
9a799d71 1381
f800326d
AD		 1382 do {
1383 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1384 break;
d5f398ed 1385
f800326d
AD		 1386 /*
1387 * Refresh the desc even if buffer_addrs didn't change
1388 * because each write-back erases this info.
1389 */
1390 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1391
f990b79b
AD		 1392 rx_desc++;
1393 bi++;
9a799d71 1394 i++;
f990b79b 1395 if (unlikely(!i)) {
e4f74028 1396 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1397 bi = rx_ring->rx_buffer_info;
1398 i -= rx_ring->count;
1399 }
1400
1401 /* clear the hdr_addr for the next_to_use descriptor */
1402 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1403
1404 cleaned_count--;
1405 } while (cleaned_count);
7c6e0a43 1406
f990b79b
AD		 1407 i += rx_ring->count;
1408
f56e0cb1 1409 if (rx_ring->next_to_use != i)
84ea2591 1410 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1411}
1412
1d2024f6
AD		 1413/**
1414 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1415 * @data: pointer to the start of the headers
1416 * @max_len: total length of section to find headers in
1417 *
1418 * This function is meant to determine the length of headers that will
1419 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1420 * motivation of doing this is to only perform one pull for IPv4 TCP
1421 * packets so that we can do basic things like calculating the gso_size
1422 * based on the average data per packet.
1423 **/
1424static unsigned int ixgbe_get_headlen(unsigned char *data,
1425 unsigned int max_len)
1426{
1427 union {
1428 unsigned char *network;
1429 /* l2 headers */
1430 struct ethhdr *eth;
1431 struct vlan_hdr *vlan;
1432 /* l3 headers */
1433 struct iphdr *ipv4;
a048b40e 1434 struct ipv6hdr *ipv6;
1d2024f6
AD		 1435 } hdr;
1436 __be16 protocol;
1437 u8 nexthdr = 0; /* default to not TCP */
1438 u8 hlen;
1439
1440 /* this should never happen, but better safe than sorry */
1441 if (max_len < ETH_HLEN)
1442 return max_len;
1443
1444 /* initialize network frame pointer */
1445 hdr.network = data;
1446
1447 /* set first protocol and move network header forward */
1448 protocol = hdr.eth->h_proto;
1449 hdr.network += ETH_HLEN;
1450
1451 /* handle any vlan tag if present */
1452 if (protocol == __constant_htons(ETH_P_8021Q)) {
1453 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1454 return max_len;
1455
1456 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1457 hdr.network += VLAN_HLEN;
1458 }
1459
1460 /* handle L3 protocols */
1461 if (protocol == __constant_htons(ETH_P_IP)) {
1462 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1463 return max_len;
1464
1465 /* access ihl as a u8 to avoid unaligned access on ia64 */
1466 hlen = (hdr.network[0] & 0x0F) << 2;
1467
1468 /* verify hlen meets minimum size requirements */
1469 if (hlen < sizeof(struct iphdr))
1470 return hdr.network - data;
1471
ed83da12 1472 /* record next protocol if header is present */
20967f42 1473 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1474 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1475 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1476 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1477 return max_len;
1478
1479 /* record next protocol */
1480 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1481 hlen = sizeof(struct ipv6hdr);
f800326d 1482#ifdef IXGBE_FCOE
1d2024f6
AD		 1483 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1484 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1485 return max_len;
ed83da12 1486 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1487#endif
1488 } else {
1489 return hdr.network - data;
1490 }
1491
ed83da12
AD		 1492 /* relocate pointer to start of L4 header */
1493 hdr.network += hlen;
1494
a048b40e 1495 /* finally sort out TCP/UDP */
1d2024f6
AD		 1496 if (nexthdr == IPPROTO_TCP) {
1497 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1498 return max_len;
1499
1500 /* access doff as a u8 to avoid unaligned access on ia64 */
1501 hlen = (hdr.network[12] & 0xF0) >> 2;
1502
1503 /* verify hlen meets minimum size requirements */
1504 if (hlen < sizeof(struct tcphdr))
1505 return hdr.network - data;
1506
1507 hdr.network += hlen;
a048b40e
AD		 1508 } else if (nexthdr == IPPROTO_UDP) {
1509 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1510 return max_len;
1511
1512 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1513 }
1514
1515 /*
1516 * If everything has gone correctly hdr.network should be the
1517 * data section of the packet and will be the end of the header.
1518 * If not then it probably represents the end of the last recognized
1519 * header.
1520 */
1521 if ((hdr.network - data) < max_len)
1522 return hdr.network - data;
1523 else
1524 return max_len;
1525}
1526
1d2024f6
AD		 1527static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1528 struct sk_buff *skb)
1529{
f800326d 1530 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1531
1532 /* set gso_size to avoid messing up TCP MSS */
1533 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1534 IXGBE_CB(skb)->append_cnt);
96be80ab 1535 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1536}
1537
1538static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1539 struct sk_buff *skb)
1540{
1541 /* if append_cnt is 0 then frame is not RSC */
1542 if (!IXGBE_CB(skb)->append_cnt)
1543 return;
1544
1545 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1546 rx_ring->rx_stats.rsc_flush++;
1547
1548 ixgbe_set_rsc_gso_size(rx_ring, skb);
1549
1550 /* gso_size is computed using append_cnt so always clear it last */
1551 IXGBE_CB(skb)->append_cnt = 0;
1552}
1553
8a0da21b
AD		 1554/**
1555 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1556 * @rx_ring: rx descriptor ring packet is being transacted on
1557 * @rx_desc: pointer to the EOP Rx descriptor
1558 * @skb: pointer to current skb being populated
f8212f97 1559 *
8a0da21b
AD		 1560 * This function checks the ring, descriptor, and packet information in
1561 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1562 * other fields within the skb.
f8212f97 1563 **/
8a0da21b
AD		 1564static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1565 union ixgbe_adv_rx_desc *rx_desc,
1566 struct sk_buff *skb)
f8212f97 1567{
43e95f11
JF		 1568 struct net_device *dev = rx_ring->netdev;
1569
8a0da21b
AD		 1570 ixgbe_update_rsc_stats(rx_ring, skb);
1571
1572 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1573
8a0da21b
AD		 1574 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1575
6cb562d6 1576 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1577
f646968f 1578 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1579 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1580 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1581 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1582 }
1583
8a0da21b 1584 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1585
43e95f11 1586 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1587}
1588
8a0da21b
AD		 1589static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1590 struct sk_buff *skb)
aa80175a 1591{
8a0da21b
AD		 1592 struct ixgbe_adapter *adapter = q_vector->adapter;
1593
b4640030 1594 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1595 netif_receive_skb(skb);
1596 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1597 napi_gro_receive(&q_vector->napi, skb);
1598 else
1599 netif_rx(skb);
aa80175a 1600}
43634e82 1601
f800326d
AD		 1602/**
1603 * ixgbe_is_non_eop - process handling of non-EOP buffers
1604 * @rx_ring: Rx ring being processed
1605 * @rx_desc: Rx descriptor for current buffer
1606 * @skb: Current socket buffer containing buffer in progress
1607 *
1608 * This function updates next to clean. If the buffer is an EOP buffer
1609 * this function exits returning false, otherwise it will place the
1610 * sk_buff in the next buffer to be chained and return true indicating
1611 * that this is in fact a non-EOP buffer.
1612 **/
1613static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1614 union ixgbe_adv_rx_desc *rx_desc,
1615 struct sk_buff *skb)
1616{
1617 u32 ntc = rx_ring->next_to_clean + 1;
1618
1619 /* fetch, update, and store next to clean */
1620 ntc = (ntc < rx_ring->count) ? ntc : 0;
1621 rx_ring->next_to_clean = ntc;
1622
1623 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1624
5a02cbd1
AD		 1625 /* update RSC append count if present */
1626 if (ring_is_rsc_enabled(rx_ring)) {
1627 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1628 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1629
1630 if (unlikely(rsc_enabled)) {
1631 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1632
1633 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1634 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1635
5a02cbd1
AD		 1636 /* update ntc based on RSC value */
1637 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1638 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1639 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1640 }
f800326d
AD		 1641 }
1642
5a02cbd1
AD		 1643 /* if we are the last buffer then there is nothing else to do */
1644 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1645 return false;
1646
f800326d
AD		 1647 /* place skb in next buffer to be received */
1648 rx_ring->rx_buffer_info[ntc].skb = skb;
1649 rx_ring->rx_stats.non_eop_descs++;
1650
1651 return true;
1652}
1653
19861ce2
AD		 1654/**
1655 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1656 * @rx_ring: rx descriptor ring packet is being transacted on
1657 * @skb: pointer to current skb being adjusted
1658 *
1659 * This function is an ixgbe specific version of __pskb_pull_tail. The
1660 * main difference between this version and the original function is that
1661 * this function can make several assumptions about the state of things
1662 * that allow for significant optimizations versus the standard function.
1663 * As a result we can do things like drop a frag and maintain an accurate
1664 * truesize for the skb.
1665 */
1666static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1667 struct sk_buff *skb)
1668{
1669 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1670 unsigned char *va;
1671 unsigned int pull_len;
1672
1673 /*
1674 * it is valid to use page_address instead of kmap since we are
1675 * working with pages allocated out of the lomem pool per
1676 * alloc_page(GFP_ATOMIC)
1677 */
1678 va = skb_frag_address(frag);
1679
1680 /*
1681 * we need the header to contain the greater of either ETH_HLEN or
1682 * 60 bytes if the skb->len is less than 60 for skb_pad.
1683 */
cf3fe7ac 1684 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1685
1686 /* align pull length to size of long to optimize memcpy performance */
1687 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1688
1689 /* update all of the pointers */
1690 skb_frag_size_sub(frag, pull_len);
1691 frag->page_offset += pull_len;
1692 skb->data_len -= pull_len;
1693 skb->tail += pull_len;
19861ce2
AD		 1694}
1695
42073d91
AD		 1696/**
1697 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1698 * @rx_ring: rx descriptor ring packet is being transacted on
1699 * @skb: pointer to current skb being updated
1700 *
1701 * This function provides a basic DMA sync up for the first fragment of an
1702 * skb. The reason for doing this is that the first fragment cannot be
1703 * unmapped until we have reached the end of packet descriptor for a buffer
1704 * chain.
1705 */
1706static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1707 struct sk_buff *skb)
1708{
1709 /* if the page was released unmap it, else just sync our portion */
1710 if (unlikely(IXGBE_CB(skb)->page_released)) {
1711 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1712 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1713 IXGBE_CB(skb)->page_released = false;
1714 } else {
1715 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1716
1717 dma_sync_single_range_for_cpu(rx_ring->dev,
1718 IXGBE_CB(skb)->dma,
1719 frag->page_offset,
1720 ixgbe_rx_bufsz(rx_ring),
1721 DMA_FROM_DEVICE);
1722 }
1723 IXGBE_CB(skb)->dma = 0;
1724}
1725
f800326d
AD		 1726/**
1727 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1728 * @rx_ring: rx descriptor ring packet is being transacted on
1729 * @rx_desc: pointer to the EOP Rx descriptor
1730 * @skb: pointer to current skb being fixed
1731 *
1732 * Check for corrupted packet headers caused by senders on the local L2
1733 * embedded NIC switch not setting up their Tx Descriptors right. These
1734 * should be very rare.
1735 *
1736 * Also address the case where we are pulling data in on pages only
1737 * and as such no data is present in the skb header.
1738 *
1739 * In addition if skb is not at least 60 bytes we need to pad it so that
1740 * it is large enough to qualify as a valid Ethernet frame.
1741 *
1742 * Returns true if an error was encountered and skb was freed.
1743 **/
1744static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1745 union ixgbe_adv_rx_desc *rx_desc,
1746 struct sk_buff *skb)
1747{
f800326d 1748 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1749
1750 /* verify that the packet does not have any known errors */
1751 if (unlikely(ixgbe_test_staterr(rx_desc,
1752 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1753 !(netdev->features & NETIF_F_RXALL))) {
1754 dev_kfree_skb_any(skb);
1755 return true;
1756 }
1757
19861ce2 1758 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1759 if (skb_is_nonlinear(skb))
1760 ixgbe_pull_tail(rx_ring, skb);
f800326d 1761
57efd44c
AD		 1762#ifdef IXGBE_FCOE
1763 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1764 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1765 return false;
1766
1767#endif
f800326d
AD		 1768 /* if skb_pad returns an error the skb was freed */
1769 if (unlikely(skb->len < 60)) {
1770 int pad_len = 60 - skb->len;
1771
1772 if (skb_pad(skb, pad_len))
1773 return true;
1774 __skb_put(skb, pad_len);
1775 }
1776
1777 return false;
1778}
1779
f800326d
AD		 1780/**
1781 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1782 * @rx_ring: rx descriptor ring to store buffers on
1783 * @old_buff: donor buffer to have page reused
1784 *
0549ae20 1785 * Synchronizes page for reuse by the adapter
f800326d
AD		 1786 **/
1787static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1788 struct ixgbe_rx_buffer *old_buff)
1789{
1790 struct ixgbe_rx_buffer *new_buff;
1791 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1792
1793 new_buff = &rx_ring->rx_buffer_info[nta];
1794
1795 /* update, and store next to alloc */
1796 nta++;
1797 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1798
1799 /* transfer page from old buffer to new buffer */
1800 new_buff->page = old_buff->page;
1801 new_buff->dma = old_buff->dma;
0549ae20 1802 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1803
1804 /* sync the buffer for use by the device */
1805 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1806 new_buff->page_offset,
1807 ixgbe_rx_bufsz(rx_ring),
f800326d 1808 DMA_FROM_DEVICE);
f800326d
AD		 1809}
1810
1811/**
1812 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1813 * @rx_ring: rx descriptor ring to transact packets on
1814 * @rx_buffer: buffer containing page to add
1815 * @rx_desc: descriptor containing length of buffer written by hardware
1816 * @skb: sk_buff to place the data into
1817 *
0549ae20
AD		 1818 * This function will add the data contained in rx_buffer->page to the skb.
1819 * This is done either through a direct copy if the data in the buffer is
1820 * less than the skb header size, otherwise it will just attach the page as
1821 * a frag to the skb.
1822 *
1823 * The function will then update the page offset if necessary and return
1824 * true if the buffer can be reused by the adapter.
f800326d 1825 **/
0549ae20 1826static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1827 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1828 union ixgbe_adv_rx_desc *rx_desc,
1829 struct sk_buff *skb)
f800326d 1830{
0549ae20
AD		 1831 struct page *page = rx_buffer->page;
1832 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1833#if (PAGE_SIZE < 8192)
0549ae20 1834 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1835#else
1836 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1837 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1838 ixgbe_rx_bufsz(rx_ring);
1839#endif
0549ae20 1840
cf3fe7ac
AD		 1841 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1842 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1843
1844 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1845
1846 /* we can reuse buffer as-is, just make sure it is local */
1847 if (likely(page_to_nid(page) == numa_node_id()))
1848 return true;
1849
1850 /* this page cannot be reused so discard it */
1851 put_page(page);
1852 return false;
1853 }
1854
0549ae20
AD		 1855 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1856 rx_buffer->page_offset, size, truesize);
1857
09816fbe
AD		 1858 /* avoid re-using remote pages */
1859 if (unlikely(page_to_nid(page) != numa_node_id()))
1860 return false;
1861
1862#if (PAGE_SIZE < 8192)
1863 /* if we are only owner of page we can reuse it */
1864 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1865 return false;
1866
1867 /* flip page offset to other buffer */
1868 rx_buffer->page_offset ^= truesize;
1869
09816fbe
AD		 1870 /*
1871 * since we are the only owner of the page and we need to
1872 * increment it, just set the value to 2 in order to avoid
1873 * an unecessary locked operation
1874 */
1875 atomic_set(&page->_count, 2);
1876#else
1877 /* move offset up to the next cache line */
1878 rx_buffer->page_offset += truesize;
1879
1880 if (rx_buffer->page_offset > last_offset)
1881 return false;
1882
0549ae20
AD		 1883 /* bump ref count on page before it is given to the stack */
1884 get_page(page);
09816fbe 1885#endif
0549ae20
AD		 1886
1887 return true;
f800326d
AD		 1888}
1889
18806c9e
AD		 1890static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1891 union ixgbe_adv_rx_desc *rx_desc)
1892{
1893 struct ixgbe_rx_buffer *rx_buffer;
1894 struct sk_buff *skb;
1895 struct page *page;
1896
1897 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1898 page = rx_buffer->page;
1899 prefetchw(page);
1900
1901 skb = rx_buffer->skb;
1902
1903 if (likely(!skb)) {
1904 void *page_addr = page_address(page) +
1905 rx_buffer->page_offset;
1906
1907 /* prefetch first cache line of first page */
1908 prefetch(page_addr);
1909#if L1_CACHE_BYTES < 128
1910 prefetch(page_addr + L1_CACHE_BYTES);
1911#endif
1912
1913 /* allocate a skb to store the frags */
1914 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1915 IXGBE_RX_HDR_SIZE);
1916 if (unlikely(!skb)) {
1917 rx_ring->rx_stats.alloc_rx_buff_failed++;
1918 return NULL;
1919 }
1920
1921 /*
1922 * we will be copying header into skb->data in
1923 * pskb_may_pull so it is in our interest to prefetch
1924 * it now to avoid a possible cache miss
1925 */
1926 prefetchw(skb->data);
1927
1928 /*
1929 * Delay unmapping of the first packet. It carries the
1930 * header information, HW may still access the header
1931 * after the writeback. Only unmap it when EOP is
1932 * reached
1933 */
1934 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1935 goto dma_sync;
1936
1937 IXGBE_CB(skb)->dma = rx_buffer->dma;
1938 } else {
1939 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1940 ixgbe_dma_sync_frag(rx_ring, skb);
1941
1942dma_sync:
1943 /* we are reusing so sync this buffer for CPU use */
1944 dma_sync_single_range_for_cpu(rx_ring->dev,
1945 rx_buffer->dma,
1946 rx_buffer->page_offset,
1947 ixgbe_rx_bufsz(rx_ring),
1948 DMA_FROM_DEVICE);
1949 }
1950
1951 /* pull page into skb */
1952 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1953 /* hand second half of page back to the ring */
1954 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1955 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1956 /* the page has been released from the ring */
1957 IXGBE_CB(skb)->page_released = true;
1958 } else {
1959 /* we are not reusing the buffer so unmap it */
1960 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1961 ixgbe_rx_pg_size(rx_ring),
1962 DMA_FROM_DEVICE);
1963 }
1964
1965 /* clear contents of buffer_info */
1966 rx_buffer->skb = NULL;
1967 rx_buffer->dma = 0;
1968 rx_buffer->page = NULL;
1969
1970 return skb;
f800326d
AD		 1971}
1972
1973/**
1974 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1975 * @q_vector: structure containing interrupt and ring information
1976 * @rx_ring: rx descriptor ring to transact packets on
1977 * @budget: Total limit on number of packets to process
1978 *
1979 * This function provides a "bounce buffer" approach to Rx interrupt
1980 * processing. The advantage to this is that on systems that have
1981 * expensive overhead for IOMMU access this provides a means of avoiding
1982 * it by maintaining the mapping of the page to the syste.
1983 *
5a85e737 1984 * Returns amount of work completed
f800326d 1985 **/
5a85e737 1986static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1987 struct ixgbe_ring *rx_ring,
f4de00ed 1988 const int budget)
9a799d71 1989{
d2f4fbe2 1990 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1991#ifdef IXGBE_FCOE
f800326d 1992 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1993 int ddp_bytes;
1994 unsigned int mss = 0;
3d8fd385 1995#endif /* IXGBE_FCOE */
f800326d 1996 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1997
f800326d 1998 do {
f800326d
AD		 1999 union ixgbe_adv_rx_desc *rx_desc;
2000 struct sk_buff *skb;
f800326d
AD		 2001
2002 /* return some buffers to hardware, one at a time is too slow */
2003 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2004 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2005 cleaned_count = 0;
2006 }
2007
18806c9e 2008 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2009
2010 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2011 break;
9a799d71 2012
f800326d
AD		 2013 /*
2014 * This memory barrier is needed to keep us from reading
2015 * any other fields out of the rx_desc until we know the
2016 * RXD_STAT_DD bit is set
2017 */
2018 rmb();
9a799d71 2019
18806c9e
AD		 2020 /* retrieve a buffer from the ring */
2021 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2022
18806c9e
AD		 2023 /* exit if we failed to retrieve a buffer */
2024 if (!skb)
2025 break;
9a799d71 2026
9a799d71 2027 cleaned_count++;
f8212f97 2028
f800326d
AD		 2029 /* place incomplete frames back on ring for completion */
2030 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2031 continue;
c267fc16 2032
f800326d
AD		 2033 /* verify the packet layout is correct */
2034 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2035 continue;
9a799d71 2036
d2f4fbe2
AV		 2037 /* probably a little skewed due to removing CRC */
2038 total_rx_bytes += skb->len;
d2f4fbe2 2039
8a0da21b
AD		 2040 /* populate checksum, timestamp, VLAN, and protocol */
2041 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2042
332d4a7d
YZ		 2043#ifdef IXGBE_FCOE
2044 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2045 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2046 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2047 /* include DDPed FCoE data */
2048 if (ddp_bytes > 0) {
2049 if (!mss) {
2050 mss = rx_ring->netdev->mtu -
2051 sizeof(struct fcoe_hdr) -
2052 sizeof(struct fc_frame_header) -
2053 sizeof(struct fcoe_crc_eof);
2054 if (mss > 512)
2055 mss &= ~511;
2056 }
2057 total_rx_bytes += ddp_bytes;
2058 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2059 mss);
2060 }
63d635b2
AD		 2061 if (!ddp_bytes) {
2062 dev_kfree_skb_any(skb);
f800326d 2063 continue;
63d635b2 2064 }
3d8fd385 2065 }
f800326d 2066
332d4a7d 2067#endif /* IXGBE_FCOE */
8b80cda5 2068 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2069 ixgbe_rx_skb(q_vector, skb);
9a799d71 2070
f800326d 2071 /* update budget accounting */
f4de00ed
AD		 2072 total_rx_packets++;
2073 } while (likely(total_rx_packets < budget));
9a799d71 2074
c267fc16
AD		 2075 u64_stats_update_begin(&rx_ring->syncp);
2076 rx_ring->stats.packets += total_rx_packets;
2077 rx_ring->stats.bytes += total_rx_bytes;
2078 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2079 q_vector->rx.total_packets += total_rx_packets;
2080 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2081
f800326d
AD		 2082 if (cleaned_count)
2083 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2084
5a85e737 2085 return total_rx_packets;
9a799d71
AK		 2086}
2087
e0d1095a 2088#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2089/* must be called with local_bh_disable()d */
2090static int ixgbe_low_latency_recv(struct napi_struct *napi)
2091{
2092 struct ixgbe_q_vector *q_vector =
2093 container_of(napi, struct ixgbe_q_vector, napi);
2094 struct ixgbe_adapter *adapter = q_vector->adapter;
2095 struct ixgbe_ring *ring;
2096 int found = 0;
2097
2098 if (test_bit(__IXGBE_DOWN, &adapter->state))
2099 return LL_FLUSH_FAILED;
2100
2101 if (!ixgbe_qv_lock_poll(q_vector))
2102 return LL_FLUSH_BUSY;
2103
2104 ixgbe_for_each_ring(ring, q_vector->rx) {
2105 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2106#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2107 if (found)
2108 ring->stats.cleaned += found;
2109 else
2110 ring->stats.misses++;
2111#endif
5a85e737
ET		 2112 if (found)
2113 break;
2114 }
2115
2116 ixgbe_qv_unlock_poll(q_vector);
2117
2118 return found;
2119}
e0d1095a 2120#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2121
9a799d71
AK		 2122/**
2123 * ixgbe_configure_msix - Configure MSI-X hardware
2124 * @adapter: board private structure
2125 *
2126 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2127 * interrupts.
2128 **/
2129static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2130{
021230d4 2131 struct ixgbe_q_vector *q_vector;
49c7ffbe 2132 int v_idx;
021230d4 2133 u32 mask;
9a799d71 2134
8e34d1aa
AD		 2135 /* Populate MSIX to EITR Select */
2136 if (adapter->num_vfs > 32) {
2137 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2138 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2139 }
2140
4df10466
JB		 2141 /*
2142 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2143 * corresponding register.
2144 */
49c7ffbe 2145 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2146 struct ixgbe_ring *ring;
7a921c93 2147 q_vector = adapter->q_vector[v_idx];
021230d4 2148
a557928e 2149 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2150 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2151
a557928e 2152 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2153 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2154
fe49f04a 2155 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2156 }
2157
bd508178
AD		 2158 switch (adapter->hw.mac.type) {
2159 case ixgbe_mac_82598EB:
e8e26350 2160 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2161 v_idx);
bd508178
AD		 2162 break;
2163 case ixgbe_mac_82599EB:
b93a2226 2164 case ixgbe_mac_X540:
e8e26350 2165 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2166 break;
bd508178
AD		 2167 default:
2168 break;
2169 }
021230d4
AV		 2170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2171
41fb9248 2172 /* set up to autoclear timer, and the vectors */
021230d4 2173 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2174 mask &= ~(IXGBE_EIMS_OTHER |
2175 IXGBE_EIMS_MAILBOX |
2176 IXGBE_EIMS_LSC);
2177
021230d4 2178 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2179}
2180
f494e8fa
AV		 2181enum latency_range {
2182 lowest_latency = 0,
2183 low_latency = 1,
2184 bulk_latency = 2,
2185 latency_invalid = 255
2186};
2187
2188/**
2189 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2190 * @q_vector: structure containing interrupt and ring information
2191 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2192 *
2193 * Stores a new ITR value based on packets and byte
2194 * counts during the last interrupt. The advantage of per interrupt
2195 * computation is faster updates and more accurate ITR for the current
2196 * traffic pattern. Constants in this function were computed
2197 * based on theoretical maximum wire speed and thresholds were set based
2198 * on testing data as well as attempting to minimize response time
2199 * while increasing bulk throughput.
2200 * this functionality is controlled by the InterruptThrottleRate module
2201 * parameter (see ixgbe_param.c)
2202 **/
bd198058
AD		 2203static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2204 struct ixgbe_ring_container *ring_container)
f494e8fa 2205{
bd198058
AD		 2206 int bytes = ring_container->total_bytes;
2207 int packets = ring_container->total_packets;
2208 u32 timepassed_us;
621bd70e 2209 u64 bytes_perint;
bd198058 2210 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2211
2212 if (packets == 0)
bd198058 2213 return;
f494e8fa
AV		 2214
2215 /* simple throttlerate management
621bd70e
AD		 2216 * 0-10MB/s lowest (100000 ints/s)
2217 * 10-20MB/s low (20000 ints/s)
2218 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2219 */
2220 /* what was last interrupt timeslice? */
d5bf4f67 2221 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2222 if (timepassed_us == 0)
2223 return;
2224
f494e8fa
AV		 2225 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2226
2227 switch (itr_setting) {
2228 case lowest_latency:
621bd70e 2229 if (bytes_perint > 10)
bd198058 2230 itr_setting = low_latency;
f494e8fa
AV		 2231 break;
2232 case low_latency:
621bd70e 2233 if (bytes_perint > 20)
bd198058 2234 itr_setting = bulk_latency;
621bd70e 2235 else if (bytes_perint <= 10)
bd198058 2236 itr_setting = lowest_latency;
f494e8fa
AV		 2237 break;
2238 case bulk_latency:
621bd70e 2239 if (bytes_perint <= 20)
bd198058 2240 itr_setting = low_latency;
f494e8fa
AV		 2241 break;
2242 }
2243
bd198058
AD		 2244 /* clear work counters since we have the values we need */
2245 ring_container->total_bytes = 0;
2246 ring_container->total_packets = 0;
2247
2248 /* write updated itr to ring container */
2249 ring_container->itr = itr_setting;
f494e8fa
AV		 2250}
2251
509ee935
JB		 2252/**
2253 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2254 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2255 *
2256 * This function is made to be called by ethtool and by the driver
2257 * when it needs to update EITR registers at runtime. Hardware
2258 * specific quirks/differences are taken care of here.
2259 */
fe49f04a 2260void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2261{
fe49f04a 2262 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2263 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2264 int v_idx = q_vector->v_idx;
5d967eb7 2265 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2266
bd508178
AD		 2267 switch (adapter->hw.mac.type) {
2268 case ixgbe_mac_82598EB:
509ee935
JB		 2269 /* must write high and low 16 bits to reset counter */
2270 itr_reg |= (itr_reg << 16);
bd508178
AD		 2271 break;
2272 case ixgbe_mac_82599EB:
b93a2226 2273 case ixgbe_mac_X540:
509ee935
JB		 2274 /*
2275 * set the WDIS bit to not clear the timer bits and cause an
2276 * immediate assertion of the interrupt
2277 */
2278 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2279 break;
2280 default:
2281 break;
509ee935
JB		 2282 }
2283 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2284}
2285
bd198058 2286static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2287{
d5bf4f67 2288 u32 new_itr = q_vector->itr;
bd198058 2289 u8 current_itr;
f494e8fa 2290
bd198058
AD		 2291 ixgbe_update_itr(q_vector, &q_vector->tx);
2292 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2293
08c8833b 2294 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2295
2296 switch (current_itr) {
2297 /* counts and packets in update_itr are dependent on these numbers */
2298 case lowest_latency:
d5bf4f67 2299 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2300 break;
2301 case low_latency:
d5bf4f67 2302 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2303 break;
2304 case bulk_latency:
d5bf4f67 2305 new_itr = IXGBE_8K_ITR;
f494e8fa 2306 break;
bd198058
AD		 2307 default:
2308 break;
f494e8fa
AV		 2309 }
2310
d5bf4f67 2311 if (new_itr != q_vector->itr) {
fe49f04a 2312 /* do an exponential smoothing */
d5bf4f67
ET		 2313 new_itr = (10 * new_itr * q_vector->itr) /
2314 ((9 * new_itr) + q_vector->itr);
509ee935 2315
bd198058 2316 /* save the algorithm value here */
5d967eb7 2317 q_vector->itr = new_itr;
fe49f04a
AD		 2318
2319 ixgbe_write_eitr(q_vector);
f494e8fa 2320 }
f494e8fa
AV		 2321}
2322
119fc60a 2323/**
de88eeeb 2324 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2325 * @adapter: pointer to adapter
119fc60a 2326 **/
f0f9778d 2327static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2328{
119fc60a
MC		 2329 struct ixgbe_hw *hw = &adapter->hw;
2330 u32 eicr = adapter->interrupt_event;
2331
f0f9778d 2332 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2333 return;
2334
f0f9778d
AD		 2335 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2336 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2337 return;
2338
2339 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2340
7ca647bd 2341 switch (hw->device_id) {
f0f9778d
AD		 2342 case IXGBE_DEV_ID_82599_T3_LOM:
2343 /*
2344 * Since the warning interrupt is for both ports
2345 * we don't have to check if:
2346 * - This interrupt wasn't for our port.
2347 * - We may have missed the interrupt so always have to
2348 * check if we got a LSC
2349 */
2350 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2351 !(eicr & IXGBE_EICR_LSC))
2352 return;
2353
2354 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2355 u32 speed;
f0f9778d 2356 bool link_up = false;
7ca647bd 2357
3d292265 2358 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2359
f0f9778d
AD		 2360 if (link_up)
2361 return;
2362 }
2363
2364 /* Check if this is not due to overtemp */
2365 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2366 return;
2367
2368 break;
7ca647bd
JP		 2369 default:
2370 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2371 return;
7ca647bd 2372 break;
119fc60a 2373 }
7ca647bd
JP		 2374 e_crit(drv,
2375 "Network adapter has been stopped because it has over heated. "
2376 "Restart the computer. If the problem persists, "
2377 "power off the system and replace the adapter\n");
f0f9778d
AD		 2378
2379 adapter->interrupt_event = 0;
119fc60a
MC		 2380}
2381
0befdb3e
JB		 2382static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2383{
2384 struct ixgbe_hw *hw = &adapter->hw;
2385
2386 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2387 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2388 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2389 /* write to clear the interrupt */
2390 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2391 }
2392}
cf8280ee 2393
4f51bf70
JK		 2394static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2395{
2396 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2397 return;
2398
2399 switch (adapter->hw.mac.type) {
2400 case ixgbe_mac_82599EB:
2401 /*
2402 * Need to check link state so complete overtemp check
2403 * on service task
2404 */
2405 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2406 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2407 adapter->interrupt_event = eicr;
2408 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2409 ixgbe_service_event_schedule(adapter);
2410 return;
2411 }
2412 return;
2413 case ixgbe_mac_X540:
2414 if (!(eicr & IXGBE_EICR_TS))
2415 return;
2416 break;
2417 default:
2418 return;
2419 }
2420
2421 e_crit(drv,
2422 "Network adapter has been stopped because it has over heated. "
2423 "Restart the computer. If the problem persists, "
2424 "power off the system and replace the adapter\n");
2425}
2426
e8e26350
PW		 2427static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2428{
2429 struct ixgbe_hw *hw = &adapter->hw;
2430
73c4b7cd
AD		 2431 if (eicr & IXGBE_EICR_GPI_SDP2) {
2432 /* Clear the interrupt */
2433 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2434 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2435 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2436 ixgbe_service_event_schedule(adapter);
2437 }
73c4b7cd
AD		 2438 }
2439
e8e26350
PW		 2440 if (eicr & IXGBE_EICR_GPI_SDP1) {
2441 /* Clear the interrupt */
2442 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2443 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2444 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2445 ixgbe_service_event_schedule(adapter);
2446 }
e8e26350
PW		 2447 }
2448}
2449
cf8280ee
JB		 2450static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2451{
2452 struct ixgbe_hw *hw = &adapter->hw;
2453
2454 adapter->lsc_int++;
2455 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2456 adapter->link_check_timeout = jiffies;
2457 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2458 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2459 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2460 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2461 }
2462}
2463
fe49f04a
AD		 2464static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2465 u64 qmask)
2466{
2467 u32 mask;
bd508178 2468 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2469
bd508178
AD		 2470 switch (hw->mac.type) {
2471 case ixgbe_mac_82598EB:
fe49f04a 2472 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2473 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2474 break;
2475 case ixgbe_mac_82599EB:
b93a2226 2476 case ixgbe_mac_X540:
fe49f04a 2477 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2478 if (mask)
2479 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2480 mask = (qmask >> 32);
bd508178
AD		 2481 if (mask)
2482 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2483 break;
2484 default:
2485 break;
fe49f04a
AD		 2486 }
2487 /* skip the flush */
2488}
2489
2490static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2491 u64 qmask)
fe49f04a
AD		 2492{
2493 u32 mask;
bd508178 2494 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2495
bd508178
AD		 2496 switch (hw->mac.type) {
2497 case ixgbe_mac_82598EB:
fe49f04a 2498 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2499 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2500 break;
2501 case ixgbe_mac_82599EB:
b93a2226 2502 case ixgbe_mac_X540:
fe49f04a 2503 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2504 if (mask)
2505 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2506 mask = (qmask >> 32);
bd508178
AD		 2507 if (mask)
2508 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2509 break;
2510 default:
2511 break;
fe49f04a
AD		 2512 }
2513 /* skip the flush */
2514}
2515
021230d4 2516/**
2c4af694
AD		 2517 * ixgbe_irq_enable - Enable default interrupt generation settings
2518 * @adapter: board private structure
021230d4 2519 **/
2c4af694
AD		 2520static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2521 bool flush)
9a799d71 2522{
2c4af694 2523 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2524
2c4af694
AD		 2525 /* don't reenable LSC while waiting for link */
2526 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2527 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2528
2c4af694 2529 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2530 switch (adapter->hw.mac.type) {
2531 case ixgbe_mac_82599EB:
2532 mask |= IXGBE_EIMS_GPI_SDP0;
2533 break;
2534 case ixgbe_mac_X540:
2535 mask |= IXGBE_EIMS_TS;
2536 break;
2537 default:
2538 break;
2539 }
2c4af694
AD		 2540 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2541 mask |= IXGBE_EIMS_GPI_SDP1;
2542 switch (adapter->hw.mac.type) {
2543 case ixgbe_mac_82599EB:
2c4af694
AD		 2544 mask |= IXGBE_EIMS_GPI_SDP1;
2545 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2546 case ixgbe_mac_X540:
2547 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2548 mask |= IXGBE_EIMS_MAILBOX;
2549 break;
2550 default:
2551 break;
9a799d71 2552 }
db0677fa 2553
db0677fa
JK		 2554 if (adapter->hw.mac.type == ixgbe_mac_X540)
2555 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2556
2c4af694
AD		 2557 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2558 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2559 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2560
2c4af694
AD		 2561 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2562 if (queues)
2563 ixgbe_irq_enable_queues(adapter, ~0);
2564 if (flush)
2565 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2566}
2567
2c4af694 2568static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2569{
a65151ba 2570 struct ixgbe_adapter *adapter = data;
9a799d71 2571 struct ixgbe_hw *hw = &adapter->hw;
54037505 2572 u32 eicr;
91281fd3 2573
54037505
DS		 2574 /*
2575 * Workaround for Silicon errata. Use clear-by-write instead
2576 * of clear-by-read. Reading with EICS will return the
2577 * interrupt causes without clearing, which later be done
2578 * with the write to EICR.
2579 */
2580 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2581
2582 /* The lower 16bits of the EICR register are for the queue interrupts
2583 * which should be masked here in order to not accidently clear them if
2584 * the bits are high when ixgbe_msix_other is called. There is a race
2585 * condition otherwise which results in possible performance loss
2586 * especially if the ixgbe_msix_other interrupt is triggering
2587 * consistently (as it would when PPS is turned on for the X540 device)
2588 */
2589 eicr &= 0xFFFF0000;
2590
54037505 2591 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2592
cf8280ee
JB		 2593 if (eicr & IXGBE_EICR_LSC)
2594 ixgbe_check_lsc(adapter);
f0848276 2595
1cdd1ec8
GR		 2596 if (eicr & IXGBE_EICR_MAILBOX)
2597 ixgbe_msg_task(adapter);
efe3d3c8 2598
bd508178
AD		 2599 switch (hw->mac.type) {
2600 case ixgbe_mac_82599EB:
b93a2226 2601 case ixgbe_mac_X540:
2c4af694
AD		 2602 if (eicr & IXGBE_EICR_ECC)
2603 e_info(link, "Received unrecoverable ECC Err, please "
2604 "reboot\n");
c4cf55e5
PWJ		 2605 /* Handle Flow Director Full threshold interrupt */
2606 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2607 int reinit_count = 0;
c4cf55e5 2608 int i;
c4cf55e5 2609 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2610 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2611 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2612 &ring->state))
2613 reinit_count++;
2614 }
2615 if (reinit_count) {
2616 /* no more flow director interrupts until after init */
2617 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2618 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2619 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2620 }
2621 }
f0f9778d 2622 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2623 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2624 break;
2625 default:
2626 break;
c4cf55e5 2627 }
f0848276 2628
bd508178 2629 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2630
db0677fa
JK		 2631 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2632 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2633
7086400d 2634 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2635 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2636 ixgbe_irq_enable(adapter, false, false);
f0848276 2637
9a799d71 2638 return IRQ_HANDLED;
f0848276 2639}
91281fd3 2640
4ff7fb12 2641static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2642{
021230d4 2643 struct ixgbe_q_vector *q_vector = data;
91281fd3 2644
9b471446 2645 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2646
4ff7fb12
AD		 2647 if (q_vector->rx.ring || q_vector->tx.ring)
2648 napi_schedule(&q_vector->napi);
91281fd3 2649
9a799d71 2650 return IRQ_HANDLED;
91281fd3
AD		 2651}
2652
eb01b975
AD		 2653/**
2654 * ixgbe_poll - NAPI Rx polling callback
2655 * @napi: structure for representing this polling device
2656 * @budget: how many packets driver is allowed to clean
2657 *
2658 * This function is used for legacy and MSI, NAPI mode
2659 **/
8af3c33f 2660int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2661{
2662 struct ixgbe_q_vector *q_vector =
2663 container_of(napi, struct ixgbe_q_vector, napi);
2664 struct ixgbe_adapter *adapter = q_vector->adapter;
2665 struct ixgbe_ring *ring;
2666 int per_ring_budget;
2667 bool clean_complete = true;
2668
2669#ifdef CONFIG_IXGBE_DCA
2670 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2671 ixgbe_update_dca(q_vector);
2672#endif
2673
2674 ixgbe_for_each_ring(ring, q_vector->tx)
2675 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2676
5a85e737
ET		 2677 if (!ixgbe_qv_lock_napi(q_vector))
2678 return budget;
2679
eb01b975
AD		 2680 /* attempt to distribute budget to each queue fairly, but don't allow
2681 * the budget to go below 1 because we'll exit polling */
2682 if (q_vector->rx.count > 1)
2683 per_ring_budget = max(budget/q_vector->rx.count, 1);
2684 else
2685 per_ring_budget = budget;
2686
2687 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2688 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2689 per_ring_budget) < per_ring_budget);
eb01b975 2690
5a85e737 2691 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2692 /* If all work not completed, return budget and keep polling */
2693 if (!clean_complete)
2694 return budget;
2695
2696 /* all work done, exit the polling mode */
2697 napi_complete(napi);
2698 if (adapter->rx_itr_setting & 1)
2699 ixgbe_set_itr(q_vector);
2700 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2701 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2702
2703 return 0;
2704}
2705
021230d4
AV		 2706/**
2707 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2708 * @adapter: board private structure
2709 *
2710 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2711 * interrupts from the kernel.
2712 **/
2713static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2714{
2715 struct net_device *netdev = adapter->netdev;
207867f5 2716 int vector, err;
e8e9f696 2717 int ri = 0, ti = 0;
021230d4 2718
49c7ffbe 2719 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2720 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2721 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2722
4ff7fb12 2723 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2724 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2725 "%s-%s-%d", netdev->name, "TxRx", ri++);
2726 ti++;
2727 } else if (q_vector->rx.ring) {
9fe93afd 2728 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2729 "%s-%s-%d", netdev->name, "rx", ri++);
2730 } else if (q_vector->tx.ring) {
9fe93afd 2731 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2732 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2733 } else {
2734 /* skip this unused q_vector */
2735 continue;
32aa77a4 2736 }
207867f5
AD		 2737 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2738 q_vector->name, q_vector);
9a799d71 2739 if (err) {
396e799c 2740 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2741 "Error: %d\n", err);
021230d4 2742 goto free_queue_irqs;
9a799d71 2743 }
207867f5
AD		 2744 /* If Flow Director is enabled, set interrupt affinity */
2745 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2746 /* assign the mask for this irq */
2747 irq_set_affinity_hint(entry->vector,
de88eeeb 2748 &q_vector->affinity_mask);
207867f5 2749 }
9a799d71
AK		 2750 }
2751
021230d4 2752 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2753 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2754 if (err) {
de88eeeb 2755 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2756 goto free_queue_irqs;
9a799d71
AK		 2757 }
2758
9a799d71
AK		 2759 return 0;
2760
021230d4 2761free_queue_irqs:
207867f5
AD		 2762 while (vector) {
2763 vector--;
2764 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2765 NULL);
2766 free_irq(adapter->msix_entries[vector].vector,
2767 adapter->q_vector[vector]);
2768 }
021230d4
AV		 2769 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2770 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2771 kfree(adapter->msix_entries);
2772 adapter->msix_entries = NULL;
9a799d71
AK		 2773 return err;
2774}
2775
2776/**
021230d4 2777 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2778 * @irq: interrupt number
2779 * @data: pointer to a network interface device structure
9a799d71
AK		 2780 **/
2781static irqreturn_t ixgbe_intr(int irq, void *data)
2782{
a65151ba 2783 struct ixgbe_adapter *adapter = data;
9a799d71 2784 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2785 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2786 u32 eicr;
2787
54037505 2788 /*
24ddd967 2789 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2790 * before the read of EICR.
2791 */
2792 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2793
021230d4 2794 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2795 * therefore no explicit interrupt disable is necessary */
021230d4 2796 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2797 if (!eicr) {
6af3b9eb
ET		 2798 /*
2799 * shared interrupt alert!
f47cf66e 2800 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2801 * have disabled interrupts due to EIAM
2802 * finish the workaround of silicon errata on 82598. Unmask
2803 * the interrupt that we masked before the EICR read.
2804 */
2805 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2806 ixgbe_irq_enable(adapter, true, true);
9a799d71 2807 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2808 }
9a799d71 2809
cf8280ee
JB		 2810 if (eicr & IXGBE_EICR_LSC)
2811 ixgbe_check_lsc(adapter);
021230d4 2812
bd508178
AD		 2813 switch (hw->mac.type) {
2814 case ixgbe_mac_82599EB:
e8e26350 2815 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2816 /* Fall through */
2817 case ixgbe_mac_X540:
2818 if (eicr & IXGBE_EICR_ECC)
2819 e_info(link, "Received unrecoverable ECC err, please "
2820 "reboot\n");
4f51bf70 2821 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2822 break;
2823 default:
2824 break;
2825 }
e8e26350 2826
0befdb3e 2827 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2828 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2829 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2830
b9f6ed2b
AD		 2831 /* would disable interrupts here but EIAM disabled it */
2832 napi_schedule(&q_vector->napi);
9a799d71 2833
6af3b9eb
ET		 2834 /*
2835 * re-enable link(maybe) and non-queue interrupts, no flush.
2836 * ixgbe_poll will re-enable the queue interrupts
2837 */
6af3b9eb
ET		 2838 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2839 ixgbe_irq_enable(adapter, false, false);
2840
9a799d71
AK		 2841 return IRQ_HANDLED;
2842}
2843
2844/**
2845 * ixgbe_request_irq - initialize interrupts
2846 * @adapter: board private structure
2847 *
2848 * Attempts to configure interrupts using the best available
2849 * capabilities of the hardware and kernel.
2850 **/
021230d4 2851static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2852{
2853 struct net_device *netdev = adapter->netdev;
021230d4 2854 int err;
9a799d71 2855
4cc6df29 2856 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2857 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2858 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2859 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2860 netdev->name, adapter);
4cc6df29 2861 else
a0607fd3 2862 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2863 netdev->name, adapter);
9a799d71 2864
de88eeeb 2865 if (err)
396e799c 2866 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2867
9a799d71
AK		 2868 return err;
2869}
2870
2871static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2872{
49c7ffbe 2873 int vector;
9a799d71 2874
49c7ffbe
AD		 2875 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2876 free_irq(adapter->pdev->irq, adapter);
2877 return;
2878 }
4cc6df29 2879
49c7ffbe
AD		 2880 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2881 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2882 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2883
49c7ffbe
AD		 2884 /* free only the irqs that were actually requested */
2885 if (!q_vector->rx.ring && !q_vector->tx.ring)
2886 continue;
207867f5 2887
49c7ffbe
AD		 2888 /* clear the affinity_mask in the IRQ descriptor */
2889 irq_set_affinity_hint(entry->vector, NULL);
2890
2891 free_irq(entry->vector, q_vector);
9a799d71 2892 }
49c7ffbe
AD		 2893
2894 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2895}
2896
22d5a71b
JB		 2897/**
2898 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2899 * @adapter: board private structure
2900 **/
2901static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2902{
bd508178
AD		 2903 switch (adapter->hw.mac.type) {
2904 case ixgbe_mac_82598EB:
835462fc 2905 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2906 break;
2907 case ixgbe_mac_82599EB:
b93a2226 2908 case ixgbe_mac_X540:
835462fc
NS		 2909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2912 break;
2913 default:
2914 break;
22d5a71b
JB		 2915 }
2916 IXGBE_WRITE_FLUSH(&adapter->hw);
2917 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2918 int vector;
2919
2920 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2921 synchronize_irq(adapter->msix_entries[vector].vector);
2922
2923 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2924 } else {
2925 synchronize_irq(adapter->pdev->irq);
2926 }
2927}
2928
9a799d71
AK		 2929/**
2930 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2931 *
2932 **/
2933static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2934{
d5bf4f67 2935 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2936
d5bf4f67 2937 ixgbe_write_eitr(q_vector);
9a799d71 2938
e8e26350
PW		 2939 ixgbe_set_ivar(adapter, 0, 0, 0);
2940 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2941
396e799c 2942 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2943}
2944
43e69bf0
AD		 2945/**
2946 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2947 * @adapter: board private structure
2948 * @ring: structure containing ring specific data
2949 *
2950 * Configure the Tx descriptor ring after a reset.
2951 **/
84418e3b
AD		 2952void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2953 struct ixgbe_ring *ring)
43e69bf0
AD		 2954{
2955 struct ixgbe_hw *hw = &adapter->hw;
2956 u64 tdba = ring->dma;
2f1860b8 2957 int wait_loop = 10;
b88c6de2 2958 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2959 u8 reg_idx = ring->reg_idx;
43e69bf0 2960
2f1860b8 2961 /* disable queue to avoid issues while updating state */
b88c6de2 2962 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2963 IXGBE_WRITE_FLUSH(hw);
2964
43e69bf0 2965 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2966 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2967 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2968 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2969 ring->count * sizeof(union ixgbe_adv_tx_desc));
2970 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2971 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2972 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2973
b88c6de2
AD		 2974 /*
2975 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 2976 * higher than 1 when:
2977 * - ITR is 0 as it could cause false TX hangs
2978 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 2979 *
2980 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2981 * to or less than the number of on chip descriptors, which is
2982 * currently 40.
2983 */
67da097e
ET		 2984#if IS_ENABLED(CONFIG_BQL)
2985 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2986#else
e954b374 2987 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 2988#endif
b88c6de2
AD		 2989 txdctl |= (1 << 16); /* WTHRESH = 1 */
2990 else
2991 txdctl |= (8 << 16); /* WTHRESH = 8 */
2992
e954b374
AD		 2993 /*
2994 * Setting PTHRESH to 32 both improves performance
2995 * and avoids a TX hang with DFP enabled
2996 */
b88c6de2
AD		 2997 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2998 32; /* PTHRESH = 32 */
2f1860b8
AD		 2999
3000 /* reinitialize flowdirector state */
39cb681b 3001 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3002 ring->atr_sample_rate = adapter->atr_sample_rate;
3003 ring->atr_count = 0;
3004 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3005 } else {
3006 ring->atr_sample_rate = 0;
3007 }
2f1860b8 3008
fd786b7b
AD		 3009 /* initialize XPS */
3010 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3011 struct ixgbe_q_vector *q_vector = ring->q_vector;
3012
3013 if (q_vector)
2a47fa45 3014 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3015 &q_vector->affinity_mask,
3016 ring->queue_index);
3017 }
3018
c84d324c
JF		 3019 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3020
2f1860b8 3021 /* enable queue */
2f1860b8
AD		 3022 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3023
3024 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3025 if (hw->mac.type == ixgbe_mac_82598EB &&
3026 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3027 return;
3028
3029 /* poll to verify queue is enabled */
3030 do {
032b4325 3031 usleep_range(1000, 2000);
2f1860b8
AD		 3032 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3033 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3034 if (!wait_loop)
3035 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3036}
3037
120ff942
AD		 3038static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3039{
3040 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3041 u32 rttdcs, mtqc;
8b1c0b24 3042 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3043
3044 if (hw->mac.type == ixgbe_mac_82598EB)
3045 return;
3046
3047 /* disable the arbiter while setting MTQC */
3048 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3049 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3050 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3051
3052 /* set transmit pool layout */
671c0adb
AD		 3053 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3054 mtqc = IXGBE_MTQC_VT_ENA;
3055 if (tcs > 4)
3056 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3057 else if (tcs > 1)
3058 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3059 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3060 mtqc |= IXGBE_MTQC_32VF;
3061 else
3062 mtqc |= IXGBE_MTQC_64VF;
3063 } else {
3064 if (tcs > 4)
3065 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3066 else if (tcs > 1)
3067 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3068 else
671c0adb
AD		 3069 mtqc = IXGBE_MTQC_64Q_1PB;
3070 }
120ff942 3071
671c0adb 3072 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3073
671c0adb
AD		 3074 /* Enable Security TX Buffer IFG for multiple pb */
3075 if (tcs) {
3076 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3077 sectx |= IXGBE_SECTX_DCB;
3078 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3079 }
3080
3081 /* re-enable the arbiter */
3082 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3083 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3084}
3085
9a799d71 3086/**
3a581073 3087 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3088 * @adapter: board private structure
3089 *
3090 * Configure the Tx unit of the MAC after a reset.
3091 **/
3092static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3093{
2f1860b8
AD		 3094 struct ixgbe_hw *hw = &adapter->hw;
3095 u32 dmatxctl;
43e69bf0 3096 u32 i;
9a799d71 3097
2f1860b8
AD		 3098 ixgbe_setup_mtqc(adapter);
3099
3100 if (hw->mac.type != ixgbe_mac_82598EB) {
3101 /* DMATXCTL.EN must be before Tx queues are enabled */
3102 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3103 dmatxctl |= IXGBE_DMATXCTL_TE;
3104 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3105 }
3106
9a799d71 3107 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3108 for (i = 0; i < adapter->num_tx_queues; i++)
3109 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3110}
3111
3ebe8fde
AD		 3112static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3113 struct ixgbe_ring *ring)
3114{
3115 struct ixgbe_hw *hw = &adapter->hw;
3116 u8 reg_idx = ring->reg_idx;
3117 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3118
3119 srrctl |= IXGBE_SRRCTL_DROP_EN;
3120
3121 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3122}
3123
3124static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3125 struct ixgbe_ring *ring)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
3128 u8 reg_idx = ring->reg_idx;
3129 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3130
3131 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3132
3133 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3134}
3135
3136#ifdef CONFIG_IXGBE_DCB
3137void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3138#else
3139static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3140#endif
3141{
3142 int i;
3143 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3144
3145 if (adapter->ixgbe_ieee_pfc)
3146 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3147
3148 /*
3149 * We should set the drop enable bit if:
3150 * SR-IOV is enabled
3151 * or
3152 * Number of Rx queues > 1 and flow control is disabled
3153 *
3154 * This allows us to avoid head of line blocking for security
3155 * and performance reasons.
3156 */
3157 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3158 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3159 for (i = 0; i < adapter->num_rx_queues; i++)
3160 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3161 } else {
3162 for (i = 0; i < adapter->num_rx_queues; i++)
3163 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3164 }
3165}
3166
e8e26350 3167#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3168
a6616b42 3169static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3170 struct ixgbe_ring *rx_ring)
cc41ac7c 3171{
45e9baa5 3172 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3173 u32 srrctl;
bf29ee6c 3174 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3175
45e9baa5
AD		 3176 if (hw->mac.type == ixgbe_mac_82598EB) {
3177 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3178
45e9baa5
AD		 3179 /*
3180 * if VMDq is not active we must program one srrctl register
3181 * per RSS queue since we have enabled RDRXCTL.MVMEN
3182 */
3183 reg_idx &= mask;
3184 }
cc41ac7c 3185
45e9baa5
AD		 3186 /* configure header buffer length, needed for RSC */
3187 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3188
45e9baa5 3189 /* configure the packet buffer length */
f800326d 3190 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3191
3192 /* configure descriptor type */
f800326d 3193 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3194
45e9baa5 3195 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3196}
9a799d71 3197
05abb126 3198static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3199{
05abb126
AD		 3200 struct ixgbe_hw *hw = &adapter->hw;
3201 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3202 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3203 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3204 u32 mrqc = 0, reta = 0;
3205 u32 rxcsum;
3206 int i, j;
671c0adb
AD		 3207 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3208
671c0adb
AD		 3209 /*
3210 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3211 * make full use of any rings they may have. We will use the
3212 * PSRTYPE register to control how many rings we use within the PF.
3213 */
3214 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3215 rss_i = 2;
0cefafad 3216
05abb126
AD		 3217 /* Fill out hash function seeds */
3218 for (i = 0; i < 10; i++)
3219 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3220
3221 /* Fill out redirection table */
3222 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3223 if (j == rss_i)
05abb126
AD		 3224 j = 0;
3225 /* reta = 4-byte sliding window of
3226 * 0x00..(indices-1)(indices-1)00..etc. */
3227 reta = (reta << 8) | (j * 0x11);
3228 if ((i & 3) == 3)
3229 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3230 }
0cefafad 3231
05abb126
AD		 3232 /* Disable indicating checksum in descriptor, enables RSS hash */
3233 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3234 rxcsum |= IXGBE_RXCSUM_PCSD;
3235 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3236
671c0adb 3237 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3238 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3239 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3240 } else {
671c0adb
AD		 3241 u8 tcs = netdev_get_num_tc(adapter->netdev);
3242
3243 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3244 if (tcs > 4)
3245 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3246 else if (tcs > 1)
3247 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3248 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3249 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3250 else
671c0adb
AD		 3251 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3252 } else {
3253 if (tcs > 4)
8b1c0b24 3254 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3255 else if (tcs > 1)
3256 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3257 else
3258 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3259 }
0cefafad
JB		 3260 }
3261
05abb126 3262 /* Perform hash on these packet types */
671c0adb
AD		 3263 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3264 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3265 IXGBE_MRQC_RSS_FIELD_IPV6 |
3266 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3267
ef6afc0c
AD		 3268 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3269 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3270 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3271 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3272
05abb126 3273 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3274}
3275
bb5a9ad2
NS		 3276/**
3277 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3278 * @adapter: address of board private structure
3279 * @index: index of ring to set
bb5a9ad2 3280 **/
082757af 3281static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3282 struct ixgbe_ring *ring)
bb5a9ad2 3283{
bb5a9ad2 3284 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3285 u32 rscctrl;
bf29ee6c 3286 u8 reg_idx = ring->reg_idx;
7367096a 3287
7d637bcc 3288 if (!ring_is_rsc_enabled(ring))
7367096a 3289 return;
bb5a9ad2 3290
7367096a 3291 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3292 rscctrl |= IXGBE_RSCCTL_RSCEN;
3293 /*
3294 * we must limit the number of descriptors so that the
3295 * total size of max desc * buf_len is not greater
642c680e 3296 * than 65536
bb5a9ad2 3297 */
f800326d 3298 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3299 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3300}
3301
9e10e045
AD		 3302#define IXGBE_MAX_RX_DESC_POLL 10
3303static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3304 struct ixgbe_ring *ring)
3305{
3306 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3307 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3308 u32 rxdctl;
bf29ee6c 3309 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3310
3311 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3312 if (hw->mac.type == ixgbe_mac_82598EB &&
3313 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3314 return;
3315
3316 do {
032b4325 3317 usleep_range(1000, 2000);
9e10e045
AD		 3318 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3319 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3320
3321 if (!wait_loop) {
3322 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3323 "the polling period\n", reg_idx);
3324 }
3325}
3326
2d39d576
YZ		 3327void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3328 struct ixgbe_ring *ring)
3329{
3330 struct ixgbe_hw *hw = &adapter->hw;
3331 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3332 u32 rxdctl;
3333 u8 reg_idx = ring->reg_idx;
3334
3335 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3336 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3337
3338 /* write value back with RXDCTL.ENABLE bit cleared */
3339 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3340
3341 if (hw->mac.type == ixgbe_mac_82598EB &&
3342 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3343 return;
3344
3345 /* the hardware may take up to 100us to really disable the rx queue */
3346 do {
3347 udelay(10);
3348 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3349 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3350
3351 if (!wait_loop) {
3352 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3353 "the polling period\n", reg_idx);
3354 }
3355}
3356
84418e3b
AD		 3357void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3358 struct ixgbe_ring *ring)
acd37177
AD		 3359{
3360 struct ixgbe_hw *hw = &adapter->hw;
3361 u64 rdba = ring->dma;
9e10e045 3362 u32 rxdctl;
bf29ee6c 3363 u8 reg_idx = ring->reg_idx;
acd37177 3364
9e10e045
AD		 3365 /* disable queue to avoid issues while updating state */
3366 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3367 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3368
acd37177
AD		 3369 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3370 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3371 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3372 ring->count * sizeof(union ixgbe_adv_rx_desc));
3373 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3374 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3375 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3376
3377 ixgbe_configure_srrctl(adapter, ring);
3378 ixgbe_configure_rscctl(adapter, ring);
3379
3380 if (hw->mac.type == ixgbe_mac_82598EB) {
3381 /*
3382 * enable cache line friendly hardware writes:
3383 * PTHRESH=32 descriptors (half the internal cache),
3384 * this also removes ugly rx_no_buffer_count increment
3385 * HTHRESH=4 descriptors (to minimize latency on fetch)
3386 * WTHRESH=8 burst writeback up to two cache lines
3387 */
3388 rxdctl &= ~0x3FFFFF;
3389 rxdctl |= 0x080420;
3390 }
3391
3392 /* enable receive descriptor ring */
3393 rxdctl |= IXGBE_RXDCTL_ENABLE;
3394 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3395
3396 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3397 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3398}
3399
48654521
AD		 3400static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3401{
3402 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3403 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3404 u16 pool;
48654521
AD		 3405
3406 /* PSRTYPE must be initialized in non 82598 adapters */
3407 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3408 IXGBE_PSRTYPE_UDPHDR |
3409 IXGBE_PSRTYPE_IPV4HDR |
48654521 3410 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3411 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3412
3413 if (hw->mac.type == ixgbe_mac_82598EB)
3414 return;
3415
fbe7ca7f
AD		 3416 if (rss_i > 3)
3417 psrtype |= 2 << 29;
3418 else if (rss_i > 1)
3419 psrtype |= 1 << 29;
48654521 3420
2a47fa45
JF		 3421 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3422 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3423}
3424
f5b4a52e
AD		 3425static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3426{
3427 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3428 u32 reg_offset, vf_shift;
435b19f6 3429 u32 gcr_ext, vmdctl;
de4c7f65 3430 int i;
f5b4a52e
AD		 3431
3432 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3433 return;
3434
3435 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3436 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3437 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3438 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3439 vmdctl |= IXGBE_VT_CTL_REPLEN;
3440 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3441
1d9c0bfd
AD		 3442 vf_shift = VMDQ_P(0) % 32;
3443 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3444
3445 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3446 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3447 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3448 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3449 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3450 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3451 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3452
3453 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3454 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3455
3456 /*
3457 * Set up VF register offsets for selected VT Mode,
3458 * i.e. 32 or 64 VFs for SR-IOV
3459 */
73079ea0
AD		 3460 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3461 case IXGBE_82599_VMDQ_8Q_MASK:
3462 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3463 break;
3464 case IXGBE_82599_VMDQ_4Q_MASK:
3465 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3466 break;
3467 default:
3468 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3469 break;
3470 }
3471
f5b4a52e
AD		 3472 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3473
435b19f6 3474
a985b6c3 3475 /* Enable MAC Anti-Spoofing */
435b19f6 3476 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3477 adapter->num_vfs);
de4c7f65
GR		 3478 /* For VFs that have spoof checking turned off */
3479 for (i = 0; i < adapter->num_vfs; i++) {
3480 if (!adapter->vfinfo[i].spoofchk_enabled)
3481 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3482 }
f5b4a52e
AD		 3483}
3484
477de6ed 3485static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3486{
9a799d71
AK		 3487 struct ixgbe_hw *hw = &adapter->hw;
3488 struct net_device *netdev = adapter->netdev;
3489 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3490 struct ixgbe_ring *rx_ring;
3491 int i;
3492 u32 mhadd, hlreg0;
48654521 3493
63f39bd1 3494#ifdef IXGBE_FCOE
477de6ed
AD		 3495 /* adjust max frame to be able to do baby jumbo for FCoE */
3496 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3497 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3498 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3499
477de6ed 3500#endif /* IXGBE_FCOE */
872844dd
AD		 3501
3502 /* adjust max frame to be at least the size of a standard frame */
3503 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3504 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3505
477de6ed
AD		 3506 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3507 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3508 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3509 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3510
3511 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3512 }
3513
3514 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3515 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3516 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3517 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3518
0cefafad
JB		 3519 /*
3520 * Setup the HW Rx Head and Tail Descriptor Pointers and
3521 * the Base and Length of the Rx Descriptor Ring
3522 */
9a799d71 3523 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3524 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3525 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3526 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3527 else
7d637bcc 3528 clear_ring_rsc_enabled(rx_ring);
477de6ed 3529 }
477de6ed
AD		 3530}
3531
7367096a
AD		 3532static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3533{
3534 struct ixgbe_hw *hw = &adapter->hw;
3535 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3536
3537 switch (hw->mac.type) {
3538 case ixgbe_mac_82598EB:
3539 /*
3540 * For VMDq support of different descriptor types or
3541 * buffer sizes through the use of multiple SRRCTL
3542 * registers, RDRXCTL.MVMEN must be set to 1
3543 *
3544 * also, the manual doesn't mention it clearly but DCA hints
3545 * will only use queue 0's tags unless this bit is set. Side
3546 * effects of setting this bit are only that SRRCTL must be
3547 * fully programmed [0..15]
3548 */
3549 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3550 break;
3551 case ixgbe_mac_82599EB:
b93a2226 3552 case ixgbe_mac_X540:
7367096a
AD		 3553 /* Disable RSC for ACK packets */
3554 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3555 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3556 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3557 /* hardware requires some bits to be set by default */
3558 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3559 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3560 break;
3561 default:
3562 /* We should do nothing since we don't know this hardware */
3563 return;
3564 }
3565
3566 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3567}
3568
477de6ed
AD		 3569/**
3570 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3571 * @adapter: board private structure
3572 *
3573 * Configure the Rx unit of the MAC after a reset.
3574 **/
3575static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3576{
3577 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3578 int i;
6dcc28b9 3579 u32 rxctrl, rfctl;
477de6ed
AD		 3580
3581 /* disable receives while setting up the descriptors */
3582 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3583 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3584
3585 ixgbe_setup_psrtype(adapter);
7367096a 3586 ixgbe_setup_rdrxctl(adapter);
477de6ed 3587
6dcc28b9
JK		 3588 /* RSC Setup */
3589 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3590 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3591 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3592 rfctl |= IXGBE_RFCTL_RSC_DIS;
3593 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3594
9e10e045 3595 /* Program registers for the distribution of queues */
f5b4a52e 3596 ixgbe_setup_mrqc(adapter);
f5b4a52e 3597
477de6ed
AD		 3598 /* set_rx_buffer_len must be called before ring initialization */
3599 ixgbe_set_rx_buffer_len(adapter);
3600
3601 /*
3602 * Setup the HW Rx Head and Tail Descriptor Pointers and
3603 * the Base and Length of the Rx Descriptor Ring
3604 */
9e10e045
AD		 3605 for (i = 0; i < adapter->num_rx_queues; i++)
3606 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3607
9e10e045
AD		 3608 /* disable drop enable for 82598 parts */
3609 if (hw->mac.type == ixgbe_mac_82598EB)
3610 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3611
3612 /* enable all receives */
3613 rxctrl |= IXGBE_RXCTRL_RXEN;
3614 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3615}
3616
80d5c368
PM		 3617static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3618 __be16 proto, u16 vid)
068c89b0
DS		 3619{
3620 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3621 struct ixgbe_hw *hw = &adapter->hw;
3622
3623 /* add VID to filter table */
1d9c0bfd 3624 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3625 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3626
3627 return 0;
068c89b0
DS		 3628}
3629
80d5c368
PM		 3630static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3631 __be16 proto, u16 vid)
068c89b0
DS		 3632{
3633 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3634 struct ixgbe_hw *hw = &adapter->hw;
3635
068c89b0 3636 /* remove VID from filter table */
1d9c0bfd 3637 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3638 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3639
3640 return 0;
068c89b0
DS		 3641}
3642
5f6c0181
JB		 3643/**
3644 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3645 * @adapter: driver data
3646 */
3647static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3648{
3649 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3650 u32 vlnctrl;
3651
3652 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3653 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3654 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3655}
3656
3657/**
3658 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3659 * @adapter: driver data
3660 */
3661static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3662{
3663 struct ixgbe_hw *hw = &adapter->hw;
3664 u32 vlnctrl;
3665
3666 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3667 vlnctrl |= IXGBE_VLNCTRL_VFE;
3668 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3669 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3670}
3671
3672/**
3673 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3674 * @adapter: driver data
3675 */
3676static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3677{
3678 struct ixgbe_hw *hw = &adapter->hw;
3679 u32 vlnctrl;
5f6c0181
JB		 3680 int i, j;
3681
3682 switch (hw->mac.type) {
3683 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3684 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3685 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3686 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3687 break;
3688 case ixgbe_mac_82599EB:
b93a2226 3689 case ixgbe_mac_X540:
5f6c0181 3690 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3691 struct ixgbe_ring *ring = adapter->rx_ring[i];
3692
3693 if (ring->l2_accel_priv)
3694 continue;
3695 j = ring->reg_idx;
5f6c0181
JB		 3696 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3697 vlnctrl &= ~IXGBE_RXDCTL_VME;
3698 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3699 }
3700 break;
3701 default:
3702 break;
3703 }
3704}
3705
3706/**
f62bbb5e 3707 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3708 * @adapter: driver data
3709 */
f62bbb5e 3710static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3711{
3712 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3713 u32 vlnctrl;
5f6c0181
JB		 3714 int i, j;
3715
3716 switch (hw->mac.type) {
3717 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3718 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3719 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3720 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3721 break;
3722 case ixgbe_mac_82599EB:
b93a2226 3723 case ixgbe_mac_X540:
5f6c0181 3724 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3725 struct ixgbe_ring *ring = adapter->rx_ring[i];
3726
3727 if (ring->l2_accel_priv)
3728 continue;
3729 j = ring->reg_idx;
5f6c0181
JB		 3730 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3731 vlnctrl |= IXGBE_RXDCTL_VME;
3732 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3733 }
3734 break;
3735 default:
3736 break;
3737 }
3738}
3739
9a799d71
AK		 3740static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3741{
f62bbb5e 3742 u16 vid;
9a799d71 3743
80d5c368 3744 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3745
3746 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3747 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3748}
3749
2850062a
AD		 3750/**
3751 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3752 * @netdev: network interface device structure
3753 *
3754 * Writes unicast address list to the RAR table.
3755 * Returns: -ENOMEM on failure/insufficient address space
3756 * 0 on no addresses written
3757 * X on writing X addresses to the RAR table
3758 **/
3759static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3760{
3761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3762 struct ixgbe_hw *hw = &adapter->hw;
95447461 3763 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3764 int count = 0;
3765
2a47fa45 3766 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3767 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3768 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3769
2850062a
AD		 3770 /* return ENOMEM indicating insufficient memory for addresses */
3771 if (netdev_uc_count(netdev) > rar_entries)
3772 return -ENOMEM;
3773
95447461 3774 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3775 struct netdev_hw_addr *ha;
3776 /* return error if we do not support writing to RAR table */
3777 if (!hw->mac.ops.set_rar)
3778 return -ENOMEM;
3779
3780 netdev_for_each_uc_addr(ha, netdev) {
3781 if (!rar_entries)
3782 break;
3783 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3784 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3785 count++;
3786 }
3787 }
3788 /* write the addresses in reverse order to avoid write combining */
3789 for (; rar_entries > 0 ; rar_entries--)
3790 hw->mac.ops.clear_rar(hw, rar_entries);
3791
3792 return count;
3793}
3794
9a799d71 3795/**
2c5645cf 3796 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3797 * @netdev: network interface device structure
3798 *
2c5645cf
CL		 3799 * The set_rx_method entry point is called whenever the unicast/multicast
3800 * address list or the network interface flags are updated. This routine is
3801 * responsible for configuring the hardware for proper unicast, multicast and
3802 * promiscuous mode.
9a799d71 3803 **/
7f870475 3804void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3805{
3806 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3807 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3808 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3809 int count;
9a799d71
AK		 3810
3811 /* Check for Promiscuous and All Multicast modes */
3812
3813 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3814
f5dc442b 3815 /* set all bits that we expect to always be set */
3f2d1c0f 3816 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3817 fctrl |= IXGBE_FCTRL_BAM;
3818 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3819 fctrl |= IXGBE_FCTRL_PMCF;
3820
2850062a
AD		 3821 /* clear the bits we are changing the status of */
3822 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3823
9a799d71 3824 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3825 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3826 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3827 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3828 /* Only disable hardware filter vlans in promiscuous mode
3829 * if SR-IOV and VMDQ are disabled - otherwise ensure
3830 * that hardware VLAN filters remain enabled.
3831 */
3832 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3833 IXGBE_FLAG_SRIOV_ENABLED)))
3834 ixgbe_vlan_filter_disable(adapter);
3835 else
3836 ixgbe_vlan_filter_enable(adapter);
9a799d71 3837 } else {
746b9f02
PM		 3838 if (netdev->flags & IFF_ALLMULTI) {
3839 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3840 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3841 }
5f6c0181 3842 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3843 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3844 }
3845
3846 /*
3847 * Write addresses to available RAR registers, if there is not
3848 * sufficient space to store all the addresses then enable
3849 * unicast promiscuous mode
3850 */
3851 count = ixgbe_write_uc_addr_list(netdev);
3852 if (count < 0) {
3853 fctrl |= IXGBE_FCTRL_UPE;
3854 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3855 }
3856
cf78959c
ET		 3857 /* Write addresses to the MTA, if the attempt fails
3858 * then we should just turn on promiscuous mode so
3859 * that we can at least receive multicast traffic
3860 */
3861 hw->mac.ops.update_mc_addr_list(hw, netdev);
3862 vmolr |= IXGBE_VMOLR_ROMPE;
3863
1d9c0bfd 3864 if (adapter->num_vfs)
1cdd1ec8 3865 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3866
3867 if (hw->mac.type != ixgbe_mac_82598EB) {
3868 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3869 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3870 IXGBE_VMOLR_ROPE);
1d9c0bfd 3871 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3872 }
3873
3f2d1c0f
BG		 3874 /* This is useful for sniffing bad packets. */
3875 if (adapter->netdev->features & NETIF_F_RXALL) {
3876 /* UPE and MPE will be handled by normal PROMISC logic
3877 * in e1000e_set_rx_mode */
3878 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3879 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3880 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3881
3882 fctrl &= ~(IXGBE_FCTRL_DPF);
3883 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3884 }
3885
2850062a 3886 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3887
f646968f 3888 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3889 ixgbe_vlan_strip_enable(adapter);
3890 else
3891 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3892}
3893
021230d4
AV		 3894static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3895{
3896 int q_idx;
021230d4 3897
5a85e737
ET		 3898 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3899 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 3900 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 3901 }
021230d4
AV		 3902}
3903
3904static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3905{
3906 int q_idx;
021230d4 3907
5a85e737 3908 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 3909 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 3910 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 3911 pr_info("QV %d locked\n", q_idx);
27d9ce4f 3912 usleep_range(1000, 20000);
5a85e737
ET		 3913 }
3914 }
021230d4
AV		 3915}
3916
7a6b6f51 3917#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3918/**
2f90b865
AD		 3919 * ixgbe_configure_dcb - Configure DCB hardware
3920 * @adapter: ixgbe adapter struct
3921 *
3922 * This is called by the driver on open to configure the DCB hardware.
3923 * This is also called by the gennetlink interface when reconfiguring
3924 * the DCB state.
3925 */
3926static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3927{
3928 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3929 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3930
67ebd791
AD		 3931 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3932 if (hw->mac.type == ixgbe_mac_82598EB)
3933 netif_set_gso_max_size(adapter->netdev, 65536);
3934 return;
3935 }
3936
3937 if (hw->mac.type == ixgbe_mac_82598EB)
3938 netif_set_gso_max_size(adapter->netdev, 32768);
3939
971060b1 3940#ifdef IXGBE_FCOE
b120818e
JF		 3941 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3942 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3943#endif
b120818e
JF		 3944
3945 /* reconfigure the hardware */
3946 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3947 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3948 DCB_TX_CONFIG);
3949 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3950 DCB_RX_CONFIG);
3951 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3952 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3953 ixgbe_dcb_hw_ets(&adapter->hw,
3954 adapter->ixgbe_ieee_ets,
3955 max_frame);
3956 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3957 adapter->ixgbe_ieee_pfc->pfc_en,
3958 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3959 }
8187cd48
JF		 3960
3961 /* Enable RSS Hash per TC */
3962 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3963 u32 msb = 0;
3964 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3965
d411a936
AD		 3966 while (rss_i) {
3967 msb++;
3968 rss_i >>= 1;
3969 }
8187cd48 3970
4ae63730
AD		 3971 /* write msb to all 8 TCs in one write */
3972 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3973 }
2f90b865 3974}
9da712d2
JF		 3975#endif
3976
3977/* Additional bittime to account for IXGBE framing */
3978#define IXGBE_ETH_FRAMING 20
3979
49ce9c2c 3980/**
9da712d2
JF		 3981 * ixgbe_hpbthresh - calculate high water mark for flow control
3982 *
3983 * @adapter: board private structure to calculate for
49ce9c2c 3984 * @pb: packet buffer to calculate
9da712d2
JF		 3985 */
3986static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3987{
3988 struct ixgbe_hw *hw = &adapter->hw;
3989 struct net_device *dev = adapter->netdev;
3990 int link, tc, kb, marker;
3991 u32 dv_id, rx_pba;
3992
3993 /* Calculate max LAN frame size */
3994 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3995
3996#ifdef IXGBE_FCOE
3997 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3998 if ((dev->features & NETIF_F_FCOE_MTU) &&
3999 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4000 (pb == ixgbe_fcoe_get_tc(adapter)))
4001 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 4002
4003#endif
9da712d2
JF		 4004 /* Calculate delay value for device */
4005 switch (hw->mac.type) {
4006 case ixgbe_mac_X540:
4007 dv_id = IXGBE_DV_X540(link, tc);
4008 break;
4009 default:
4010 dv_id = IXGBE_DV(link, tc);
4011 break;
4012 }
4013
4014 /* Loopback switch introduces additional latency */
4015 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4016 dv_id += IXGBE_B2BT(tc);
4017
4018 /* Delay value is calculated in bit times convert to KB */
4019 kb = IXGBE_BT2KB(dv_id);
4020 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4021
4022 marker = rx_pba - kb;
4023
4024 /* It is possible that the packet buffer is not large enough
4025 * to provide required headroom. In this case throw an error
4026 * to user and a do the best we can.
4027 */
4028 if (marker < 0) {
4029 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4030 "headroom to support flow control."
4031 "Decrease MTU or number of traffic classes\n", pb);
4032 marker = tc + 1;
4033 }
4034
4035 return marker;
4036}
4037
49ce9c2c 4038/**
9da712d2
JF		 4039 * ixgbe_lpbthresh - calculate low water mark for for flow control
4040 *
4041 * @adapter: board private structure to calculate for
49ce9c2c 4042 * @pb: packet buffer to calculate
9da712d2
JF		 4043 */
4044static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4045{
4046 struct ixgbe_hw *hw = &adapter->hw;
4047 struct net_device *dev = adapter->netdev;
4048 int tc;
4049 u32 dv_id;
4050
4051 /* Calculate max LAN frame size */
4052 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4053
4054 /* Calculate delay value for device */
4055 switch (hw->mac.type) {
4056 case ixgbe_mac_X540:
4057 dv_id = IXGBE_LOW_DV_X540(tc);
4058 break;
4059 default:
4060 dv_id = IXGBE_LOW_DV(tc);
4061 break;
4062 }
4063
4064 /* Delay value is calculated in bit times convert to KB */
4065 return IXGBE_BT2KB(dv_id);
4066}
4067
4068/*
4069 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4070 */
4071static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4072{
4073 struct ixgbe_hw *hw = &adapter->hw;
4074 int num_tc = netdev_get_num_tc(adapter->netdev);
4075 int i;
4076
4077 if (!num_tc)
4078 num_tc = 1;
4079
4080 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4081
4082 for (i = 0; i < num_tc; i++) {
4083 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4084
4085 /* Low water marks must not be larger than high water marks */
4086 if (hw->fc.low_water > hw->fc.high_water[i])
4087 hw->fc.low_water = 0;
4088 }
4089}
4090
80605c65
JF		 4091static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4092{
80605c65 4093 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4094 int hdrm;
4095 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4096
4097 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4098 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4099 hdrm = 32 << adapter->fdir_pballoc;
4100 else
4101 hdrm = 0;
80605c65 4102
f7e1027f 4103 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4104 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4105}
4106
e4911d57
AD		 4107static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4108{
4109 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4110 struct hlist_node *node2;
e4911d57
AD		 4111 struct ixgbe_fdir_filter *filter;
4112
4113 spin_lock(&adapter->fdir_perfect_lock);
4114
4115 if (!hlist_empty(&adapter->fdir_filter_list))
4116 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4117
b67bfe0d 4118 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4119 &adapter->fdir_filter_list, fdir_node) {
4120 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4121 &filter->filter,
4122 filter->sw_idx,
4123 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4124 IXGBE_FDIR_DROP_QUEUE :
4125 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4126 }
4127
4128 spin_unlock(&adapter->fdir_perfect_lock);
4129}
4130
2a47fa45
JF		 4131static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4132 struct ixgbe_adapter *adapter)
4133{
4134 struct ixgbe_hw *hw = &adapter->hw;
4135 u32 vmolr;
4136
4137 /* No unicast promiscuous support for VMDQ devices. */
4138 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4139 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4140
4141 /* clear the affected bit */
4142 vmolr &= ~IXGBE_VMOLR_MPE;
4143
4144 if (dev->flags & IFF_ALLMULTI) {
4145 vmolr |= IXGBE_VMOLR_MPE;
4146 } else {
4147 vmolr |= IXGBE_VMOLR_ROMPE;
4148 hw->mac.ops.update_mc_addr_list(hw, dev);
4149 }
4150 ixgbe_write_uc_addr_list(adapter->netdev);
4151 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4152}
4153
4154static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4155 u8 *addr, u16 pool)
4156{
4157 struct ixgbe_hw *hw = &adapter->hw;
4158 unsigned int entry;
4159
4160 entry = hw->mac.num_rar_entries - pool;
4161 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4162}
4163
4164static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4165{
4166 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4167 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4168 struct ixgbe_hw *hw = &adapter->hw;
4169 u16 pool = vadapter->pool;
4170 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4171 IXGBE_PSRTYPE_UDPHDR |
4172 IXGBE_PSRTYPE_IPV4HDR |
4173 IXGBE_PSRTYPE_L2HDR |
4174 IXGBE_PSRTYPE_IPV6HDR;
4175
4176 if (hw->mac.type == ixgbe_mac_82598EB)
4177 return;
4178
4179 if (rss_i > 3)
4180 psrtype |= 2 << 29;
4181 else if (rss_i > 1)
4182 psrtype |= 1 << 29;
4183
4184 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4185}
4186
4187/**
4188 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4189 * @rx_ring: ring to free buffers from
4190 **/
4191static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4192{
4193 struct device *dev = rx_ring->dev;
4194 unsigned long size;
4195 u16 i;
4196
4197 /* ring already cleared, nothing to do */
4198 if (!rx_ring->rx_buffer_info)
4199 return;
4200
4201 /* Free all the Rx ring sk_buffs */
4202 for (i = 0; i < rx_ring->count; i++) {
4203 struct ixgbe_rx_buffer *rx_buffer;
4204
4205 rx_buffer = &rx_ring->rx_buffer_info[i];
4206 if (rx_buffer->skb) {
4207 struct sk_buff *skb = rx_buffer->skb;
4208 if (IXGBE_CB(skb)->page_released) {
4209 dma_unmap_page(dev,
4210 IXGBE_CB(skb)->dma,
4211 ixgbe_rx_bufsz(rx_ring),
4212 DMA_FROM_DEVICE);
4213 IXGBE_CB(skb)->page_released = false;
4214 }
4215 dev_kfree_skb(skb);
4216 }
4217 rx_buffer->skb = NULL;
4218 if (rx_buffer->dma)
4219 dma_unmap_page(dev, rx_buffer->dma,
4220 ixgbe_rx_pg_size(rx_ring),
4221 DMA_FROM_DEVICE);
4222 rx_buffer->dma = 0;
4223 if (rx_buffer->page)
4224 __free_pages(rx_buffer->page,
4225 ixgbe_rx_pg_order(rx_ring));
4226 rx_buffer->page = NULL;
4227 }
4228
4229 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4230 memset(rx_ring->rx_buffer_info, 0, size);
4231
4232 /* Zero out the descriptor ring */
4233 memset(rx_ring->desc, 0, rx_ring->size);
4234
4235 rx_ring->next_to_alloc = 0;
4236 rx_ring->next_to_clean = 0;
4237 rx_ring->next_to_use = 0;
4238}
4239
4240static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4241 struct ixgbe_ring *rx_ring)
4242{
4243 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4244 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4245
4246 /* shutdown specific queue receive and wait for dma to settle */
4247 ixgbe_disable_rx_queue(adapter, rx_ring);
4248 usleep_range(10000, 20000);
4249 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4250 ixgbe_clean_rx_ring(rx_ring);
4251 rx_ring->l2_accel_priv = NULL;
4252}
4253
4254int ixgbe_fwd_ring_down(struct net_device *vdev,
4255 struct ixgbe_fwd_adapter *accel)
4256{
4257 struct ixgbe_adapter *adapter = accel->real_adapter;
4258 unsigned int rxbase = accel->rx_base_queue;
4259 unsigned int txbase = accel->tx_base_queue;
4260 int i;
4261
4262 netif_tx_stop_all_queues(vdev);
4263
4264 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4265 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4266 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4267 }
4268
4269 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4270 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4271 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4272 }
4273
4274
4275 return 0;
4276}
4277
4278static int ixgbe_fwd_ring_up(struct net_device *vdev,
4279 struct ixgbe_fwd_adapter *accel)
4280{
4281 struct ixgbe_adapter *adapter = accel->real_adapter;
4282 unsigned int rxbase, txbase, queues;
4283 int i, baseq, err = 0;
4284
4285 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4286 return 0;
4287
4288 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4289 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4290 accel->pool, adapter->num_rx_pools,
4291 baseq, baseq + adapter->num_rx_queues_per_pool,
4292 adapter->fwd_bitmask);
4293
4294 accel->netdev = vdev;
4295 accel->rx_base_queue = rxbase = baseq;
4296 accel->tx_base_queue = txbase = baseq;
4297
4298 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4299 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4300
4301 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4302 adapter->rx_ring[rxbase + i]->netdev = vdev;
4303 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4304 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4305 }
4306
4307 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4308 adapter->tx_ring[txbase + i]->netdev = vdev;
4309 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4310 }
4311
4312 queues = min_t(unsigned int,
4313 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4314 err = netif_set_real_num_tx_queues(vdev, queues);
4315 if (err)
4316 goto fwd_queue_err;
4317
2a47fa45
JF		 4318 err = netif_set_real_num_rx_queues(vdev, queues);
4319 if (err)
4320 goto fwd_queue_err;
4321
4322 if (is_valid_ether_addr(vdev->dev_addr))
4323 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4324
4325 ixgbe_fwd_psrtype(accel);
4326 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4327 return err;
4328fwd_queue_err:
4329 ixgbe_fwd_ring_down(vdev, accel);
4330 return err;
4331}
4332
4333static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4334{
4335 struct net_device *upper;
4336 struct list_head *iter;
4337 int err;
4338
4339 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4340 if (netif_is_macvlan(upper)) {
4341 struct macvlan_dev *dfwd = netdev_priv(upper);
4342 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4343
4344 if (dfwd->fwd_priv) {
4345 err = ixgbe_fwd_ring_up(upper, vadapter);
4346 if (err)
4347 continue;
4348 }
4349 }
4350 }
4351}
4352
9a799d71
AK		 4353static void ixgbe_configure(struct ixgbe_adapter *adapter)
4354{
d2f5e7f3
AS		 4355 struct ixgbe_hw *hw = &adapter->hw;
4356
80605c65 4357 ixgbe_configure_pb(adapter);
7a6b6f51 4358#ifdef CONFIG_IXGBE_DCB
67ebd791 4359 ixgbe_configure_dcb(adapter);
2f90b865 4360#endif
b35d4d42
AD		 4361 /*
4362 * We must restore virtualization before VLANs or else
4363 * the VLVF registers will not be populated
4364 */
4365 ixgbe_configure_virtualization(adapter);
9a799d71 4366
4c1d7b4b 4367 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4368 ixgbe_restore_vlan(adapter);
4369
d2f5e7f3
AS		 4370 switch (hw->mac.type) {
4371 case ixgbe_mac_82599EB:
4372 case ixgbe_mac_X540:
4373 hw->mac.ops.disable_rx_buff(hw);
4374 break;
4375 default:
4376 break;
4377 }
4378
c4cf55e5 4379 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4380 ixgbe_init_fdir_signature_82599(&adapter->hw,
4381 adapter->fdir_pballoc);
e4911d57
AD		 4382 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4383 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4384 adapter->fdir_pballoc);
4385 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4386 }
4c1d7b4b 4387
d2f5e7f3
AS		 4388 switch (hw->mac.type) {
4389 case ixgbe_mac_82599EB:
4390 case ixgbe_mac_X540:
4391 hw->mac.ops.enable_rx_buff(hw);
4392 break;
4393 default:
4394 break;
4395 }
4396
7c8ae65a
AD		 4397#ifdef IXGBE_FCOE
4398 /* configure FCoE L2 filters, redirection table, and Rx control */
4399 ixgbe_configure_fcoe(adapter);
4400
4401#endif /* IXGBE_FCOE */
9a799d71
AK		 4402 ixgbe_configure_tx(adapter);
4403 ixgbe_configure_rx(adapter);
2a47fa45 4404 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4405}
4406
e8e26350
PW		 4407static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4408{
4409 switch (hw->phy.type) {
4410 case ixgbe_phy_sfp_avago:
4411 case ixgbe_phy_sfp_ftl:
4412 case ixgbe_phy_sfp_intel:
4413 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4414 case ixgbe_phy_sfp_passive_tyco:
4415 case ixgbe_phy_sfp_passive_unknown:
4416 case ixgbe_phy_sfp_active_unknown:
4417 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4418 case ixgbe_phy_qsfp_passive_unknown:
4419 case ixgbe_phy_qsfp_active_unknown:
4420 case ixgbe_phy_qsfp_intel:
4421 case ixgbe_phy_qsfp_unknown:
e8e26350 4422 return true;
8917b447
AD		 4423 case ixgbe_phy_nl:
4424 if (hw->mac.type == ixgbe_mac_82598EB)
4425 return true;
e8e26350
PW		 4426 default:
4427 return false;
4428 }
4429}
4430
0ecc061d 4431/**
e8e26350
PW		 4432 * ixgbe_sfp_link_config - set up SFP+ link
4433 * @adapter: pointer to private adapter struct
4434 **/
4435static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4436{
7086400d 4437 /*
52f33af8 4438 * We are assuming the worst case scenario here, and that
7086400d
AD		 4439 * is that an SFP was inserted/removed after the reset
4440 * but before SFP detection was enabled. As such the best
4441 * solution is to just start searching as soon as we start
4442 */
4443 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4444 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4445
7086400d 4446 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4447}
4448
4449/**
4450 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4451 * @hw: pointer to private hardware struct
4452 *
4453 * Returns 0 on success, negative on failure
4454 **/
e8e26350 4455static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4456{
3d292265
JH		 4457 u32 speed;
4458 bool autoneg, link_up = false;
0ecc061d
PWJ		 4459 u32 ret = IXGBE_ERR_LINK_SETUP;
4460
4461 if (hw->mac.ops.check_link)
3d292265 4462 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4463
4464 if (ret)
4465 goto link_cfg_out;
4466
3d292265
JH		 4467 speed = hw->phy.autoneg_advertised;
4468 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4469 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4470 &autoneg);
0ecc061d
PWJ		 4471 if (ret)
4472 goto link_cfg_out;
4473
8620a103 4474 if (hw->mac.ops.setup_link)
fd0326f2 4475 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4476link_cfg_out:
4477 return ret;
4478}
4479
a34bcfff 4480static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4481{
9a799d71 4482 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4483 u32 gpie = 0;
9a799d71 4484
9b471446 4485 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4486 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4487 IXGBE_GPIE_OCD;
4488 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4489 /*
4490 * use EIAM to auto-mask when MSI-X interrupt is asserted
4491 * this saves a register write for every interrupt
4492 */
4493 switch (hw->mac.type) {
4494 case ixgbe_mac_82598EB:
4495 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4496 break;
9b471446 4497 case ixgbe_mac_82599EB:
b93a2226
DS		 4498 case ixgbe_mac_X540:
4499 default:
9b471446
JB		 4500 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4501 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4502 break;
4503 }
4504 } else {
021230d4
AV		 4505 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4506 * specifically only auto mask tx and rx interrupts */
4507 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4508 }
9a799d71 4509
a34bcfff
AD		 4510 /* XXX: to interrupt immediately for EICS writes, enable this */
4511 /* gpie |= IXGBE_GPIE_EIMEN; */
4512
4513 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4514 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4515
4516 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4517 case IXGBE_82599_VMDQ_8Q_MASK:
4518 gpie |= IXGBE_GPIE_VTMODE_16;
4519 break;
4520 case IXGBE_82599_VMDQ_4Q_MASK:
4521 gpie |= IXGBE_GPIE_VTMODE_32;
4522 break;
4523 default:
4524 gpie |= IXGBE_GPIE_VTMODE_64;
4525 break;
4526 }
119fc60a
MC		 4527 }
4528
5fdd31f9 4529 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4530 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4531 switch (adapter->hw.mac.type) {
4532 case ixgbe_mac_82599EB:
4533 gpie |= IXGBE_SDP0_GPIEN;
4534 break;
4535 case ixgbe_mac_X540:
4536 gpie |= IXGBE_EIMS_TS;
4537 break;
4538 default:
4539 break;
4540 }
4541 }
5fdd31f9 4542
a34bcfff
AD		 4543 /* Enable fan failure interrupt */
4544 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4545 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4546
2698b208 4547 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4548 gpie |= IXGBE_SDP1_GPIEN;
4549 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4550 }
a34bcfff
AD		 4551
4552 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4553}
4554
c7ccde0f 4555static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4556{
4557 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4558 struct net_device *upper;
4559 struct list_head *iter;
a34bcfff 4560 int err;
a34bcfff
AD		 4561 u32 ctrl_ext;
4562
4563 ixgbe_get_hw_control(adapter);
4564 ixgbe_setup_gpie(adapter);
e8e26350 4565
9a799d71
AK		 4566 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4567 ixgbe_configure_msix(adapter);
4568 else
4569 ixgbe_configure_msi_and_legacy(adapter);
4570
ec74a471
ET		 4571 /* enable the optics for 82599 SFP+ fiber */
4572 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4573 hw->mac.ops.enable_tx_laser(hw);
4574
9a799d71 4575 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4576 ixgbe_napi_enable_all(adapter);
4577
73c4b7cd
AD		 4578 if (ixgbe_is_sfp(hw)) {
4579 ixgbe_sfp_link_config(adapter);
4580 } else {
4581 err = ixgbe_non_sfp_link_config(hw);
4582 if (err)
4583 e_err(probe, "link_config FAILED %d\n", err);
4584 }
4585
021230d4
AV		 4586 /* clear any pending interrupts, may auto mask */
4587 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4588 ixgbe_irq_enable(adapter, true, true);
9a799d71 4589
bf069c97
DS		 4590 /*
4591 * If this adapter has a fan, check to see if we had a failure
4592 * before we enabled the interrupt.
4593 */
4594 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4595 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4596 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4597 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4598 }
4599
1da100bb 4600 /* enable transmits */
477de6ed 4601 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4602
2a47fa45
JF		 4603 /* enable any upper devices */
4604 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4605 if (netif_is_macvlan(upper)) {
4606 struct macvlan_dev *vlan = netdev_priv(upper);
4607
4608 if (vlan->fwd_priv)
4609 netif_tx_start_all_queues(upper);
4610 }
4611 }
4612
9a799d71
AK		 4613 /* bring the link up in the watchdog, this could race with our first
4614 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4615 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4616 adapter->link_check_timeout = jiffies;
7086400d 4617 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4618
4619 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4620 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4621 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4622 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4623}
4624
d4f80882
AV		 4625void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4626{
4627 WARN_ON(in_interrupt());
7086400d
AD		 4628 /* put off any impending NetWatchDogTimeout */
4629 adapter->netdev->trans_start = jiffies;
4630
d4f80882 4631 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4632 usleep_range(1000, 2000);
d4f80882 4633 ixgbe_down(adapter);
5809a1ae
GR		 4634 /*
4635 * If SR-IOV enabled then wait a bit before bringing the adapter
4636 * back up to give the VFs time to respond to the reset. The
4637 * two second wait is based upon the watchdog timer cycle in
4638 * the VF driver.
4639 */
4640 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4641 msleep(2000);
d4f80882
AV		 4642 ixgbe_up(adapter);
4643 clear_bit(__IXGBE_RESETTING, &adapter->state);
4644}
4645
c7ccde0f 4646void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4647{
4648 /* hardware has been reset, we need to reload some things */
4649 ixgbe_configure(adapter);
4650
c7ccde0f 4651 ixgbe_up_complete(adapter);
9a799d71
AK		 4652}
4653
4654void ixgbe_reset(struct ixgbe_adapter *adapter)
4655{
c44ade9e 4656 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4657 int err;
4658
7086400d
AD		 4659 /* lock SFP init bit to prevent race conditions with the watchdog */
4660 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4661 usleep_range(1000, 2000);
4662
4663 /* clear all SFP and link config related flags while holding SFP_INIT */
4664 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4665 IXGBE_FLAG2_SFP_NEEDS_RESET);
4666 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4667
8ca783ab 4668 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4669 switch (err) {
4670 case 0:
4671 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4672 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4673 break;
4674 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4675 e_dev_err("master disable timed out\n");
da4dd0f7 4676 break;
794caeb2
PWJ		 4677 case IXGBE_ERR_EEPROM_VERSION:
4678 /* We are running on a pre-production device, log a warning */
849c4542 4679 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4680 "Please be aware there may be issues associated with "
849c4542
ET		 4681 "your hardware. If you are experiencing problems "
4682 "please contact your Intel or hardware "
4683 "representative who provided you with this "
4684 "hardware.\n");
794caeb2 4685 break;
da4dd0f7 4686 default:
849c4542 4687 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4688 }
9a799d71 4689
7086400d
AD		 4690 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4691
9a799d71 4692 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4693 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4694
4695 /* update SAN MAC vmdq pool selection */
4696 if (hw->mac.san_mac_rar_index)
4697 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4698
8fecf67c 4699 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4700 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4701}
4702
9a799d71
AK		 4703/**
4704 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4705 * @tx_ring: ring to be cleaned
4706 **/
b6ec895e 4707static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4708{
4709 struct ixgbe_tx_buffer *tx_buffer_info;
4710 unsigned long size;
b6ec895e 4711 u16 i;
9a799d71 4712
84418e3b
AD		 4713 /* ring already cleared, nothing to do */
4714 if (!tx_ring->tx_buffer_info)
4715 return;
9a799d71 4716
84418e3b 4717 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4718 for (i = 0; i < tx_ring->count; i++) {
4719 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4720 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4721 }
4722
dad8a3b3
JF		 4723 netdev_tx_reset_queue(txring_txq(tx_ring));
4724
9a799d71
AK		 4725 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4726 memset(tx_ring->tx_buffer_info, 0, size);
4727
4728 /* Zero out the descriptor ring */
4729 memset(tx_ring->desc, 0, tx_ring->size);
4730
4731 tx_ring->next_to_use = 0;
4732 tx_ring->next_to_clean = 0;
9a799d71
AK		 4733}
4734
4735/**
021230d4 4736 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4737 * @adapter: board private structure
4738 **/
021230d4 4739static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4740{
4741 int i;
4742
021230d4 4743 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4744 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4745}
4746
4747/**
021230d4 4748 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4749 * @adapter: board private structure
4750 **/
021230d4 4751static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4752{
4753 int i;
4754
021230d4 4755 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4756 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4757}
4758
e4911d57
AD		 4759static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4760{
b67bfe0d 4761 struct hlist_node *node2;
e4911d57
AD		 4762 struct ixgbe_fdir_filter *filter;
4763
4764 spin_lock(&adapter->fdir_perfect_lock);
4765
b67bfe0d 4766 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4767 &adapter->fdir_filter_list, fdir_node) {
4768 hlist_del(&filter->fdir_node);
4769 kfree(filter);
4770 }
4771 adapter->fdir_filter_count = 0;
4772
4773 spin_unlock(&adapter->fdir_perfect_lock);
4774}
4775
9a799d71
AK		 4776void ixgbe_down(struct ixgbe_adapter *adapter)
4777{
4778 struct net_device *netdev = adapter->netdev;
7f821875 4779 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4780 struct net_device *upper;
4781 struct list_head *iter;
9a799d71 4782 u32 rxctrl;
bf29ee6c 4783 int i;
9a799d71
AK		 4784
4785 /* signal that we are down to the interrupt handler */
4786 set_bit(__IXGBE_DOWN, &adapter->state);
4787
4788 /* disable receives */
7f821875
JB		 4789 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4790 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4791
2d39d576
YZ		 4792 /* disable all enabled rx queues */
4793 for (i = 0; i < adapter->num_rx_queues; i++)
4794 /* this call also flushes the previous write */
4795 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4796
032b4325 4797 usleep_range(10000, 20000);
9a799d71 4798
7f821875
JB		 4799 netif_tx_stop_all_queues(netdev);
4800
7086400d 4801 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4802 netif_carrier_off(netdev);
4803 netif_tx_disable(netdev);
4804
2a47fa45
JF		 4805 /* disable any upper devices */
4806 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4807 if (netif_is_macvlan(upper)) {
4808 struct macvlan_dev *vlan = netdev_priv(upper);
4809
4810 if (vlan->fwd_priv) {
4811 netif_tx_stop_all_queues(upper);
4812 netif_carrier_off(upper);
4813 netif_tx_disable(upper);
4814 }
4815 }
4816 }
4817
c0dfb90e
JF		 4818 ixgbe_irq_disable(adapter);
4819
4820 ixgbe_napi_disable_all(adapter);
4821
d034acf1
AD		 4822 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4823 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4824 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4825
4826 del_timer_sync(&adapter->service_timer);
4827
34cecbbf 4828 if (adapter->num_vfs) {
8e34d1aa
AD		 4829 /* Clear EITR Select mapping */
4830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4831
4832 /* Mark all the VFs as inactive */
4833 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4834 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4835
34cecbbf
AD		 4836 /* ping all the active vfs to let them know we are going down */
4837 ixgbe_ping_all_vfs(adapter);
4838
4839 /* Disable all VFTE/VFRE TX/RX */
4840 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4841 }
4842
7f821875
JB		 4843 /* disable transmits in the hardware now that interrupts are off */
4844 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4845 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4846 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4847 }
34cecbbf
AD		 4848
4849 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4850 switch (hw->mac.type) {
4851 case ixgbe_mac_82599EB:
b93a2226 4852 case ixgbe_mac_X540:
88512539 4853 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4854 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4855 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4856 break;
4857 default:
4858 break;
4859 }
7f821875 4860
6f4a0e45
PL		 4861 if (!pci_channel_offline(adapter->pdev))
4862 ixgbe_reset(adapter);
c6ecf39a 4863
ec74a471
ET		 4864 /* power down the optics for 82599 SFP+ fiber */
4865 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4866 hw->mac.ops.disable_tx_laser(hw);
4867
9a799d71
AK		 4868 ixgbe_clean_all_tx_rings(adapter);
4869 ixgbe_clean_all_rx_rings(adapter);
4870
5dd2d332 4871#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4872 /* since we reset the hardware DCA settings were cleared */
e35ec126 4873 ixgbe_setup_dca(adapter);
96b0e0f6 4874#endif
9a799d71
AK		 4875}
4876
9a799d71
AK		 4877/**
4878 * ixgbe_tx_timeout - Respond to a Tx Hang
4879 * @netdev: network interface device structure
4880 **/
4881static void ixgbe_tx_timeout(struct net_device *netdev)
4882{
4883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4884
4885 /* Do the reset outside of interrupt context */
c83c6cbd 4886 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4887}
4888
9a799d71
AK		 4889/**
4890 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4891 * @adapter: board private structure to initialize
4892 *
4893 * ixgbe_sw_init initializes the Adapter private data structure.
4894 * Fields are initialized based on PCI device information and
4895 * OS network device settings (MTU size).
4896 **/
9f9a12f8 4897static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4898{
4899 struct ixgbe_hw *hw = &adapter->hw;
4900 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4901 unsigned int rss, fdir;
cb6d0f5e 4902 u32 fwsm;
7a6b6f51 4903#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4904 int j;
4905 struct tc_configuration *tc;
4906#endif
021230d4 4907
c44ade9e
JB		 4908 /* PCI config space info */
4909
4910 hw->vendor_id = pdev->vendor;
4911 hw->device_id = pdev->device;
4912 hw->revision_id = pdev->revision;
4913 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4914 hw->subsystem_device_id = pdev->subsystem_device;
4915
8fc3bb6d 4916 /* Set common capability flags and settings */
3ed69d7e 4917 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4918 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 4919 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4920 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 4921 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4922 adapter->atr_sample_rate = 20;
d3cb9869
AD		 4923 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4924 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 4925 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4926#ifdef CONFIG_IXGBE_DCA
4927 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4928#endif
4929#ifdef IXGBE_FCOE
4930 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4931 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4932#ifdef CONFIG_IXGBE_DCB
4933 /* Default traffic class to use for FCoE */
4934 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4935#endif /* CONFIG_IXGBE_DCB */
4936#endif /* IXGBE_FCOE */
4937
4938 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 4939 switch (hw->mac.type) {
4940 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 4941 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4942 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4943
bf069c97
DS		 4944 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4945 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 4946
49c7ffbe 4947 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 4948 adapter->ring_feature[RING_F_FDIR].limit = 0;
4949 adapter->atr_sample_rate = 0;
4950 adapter->fdir_pballoc = 0;
4951#ifdef IXGBE_FCOE
4952 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4953 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4954#ifdef CONFIG_IXGBE_DCB
4955 adapter->fcoe.up = 0;
4956#endif /* IXGBE_DCB */
4957#endif /* IXGBE_FCOE */
4958 break;
4959 case ixgbe_mac_82599EB:
4960 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4961 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 4962 break;
b93a2226 4963 case ixgbe_mac_X540:
cb6d0f5e
JK		 4964 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4965 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4966 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 4967 break;
4968 default:
4969 break;
f8212f97 4970 }
2f90b865 4971
7c8ae65a
AD		 4972#ifdef IXGBE_FCOE
4973 /* FCoE support exists, always init the FCoE lock */
4974 spin_lock_init(&adapter->fcoe.lock);
4975
4976#endif
1fc5f038
AD		 4977 /* n-tuple support exists, always init our spinlock */
4978 spin_lock_init(&adapter->fdir_perfect_lock);
4979
7a6b6f51 4980#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4981 switch (hw->mac.type) {
4982 case ixgbe_mac_X540:
4983 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4984 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4985 break;
4986 default:
4987 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4988 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4989 break;
4990 }
4991
2f90b865
AD		 4992 /* Configure DCB traffic classes */
4993 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4994 tc = &adapter->dcb_cfg.tc_config[j];
4995 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4996 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4997 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4998 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4999 tc->dcb_pfc = pfc_disabled;
5000 }
4de2a022
JF		 5001
5002 /* Initialize default user to priority mapping, UPx->TC0 */
5003 tc = &adapter->dcb_cfg.tc_config[0];
5004 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5005 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5006
2f90b865
AD		 5007 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5008 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5009 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5010 adapter->dcb_set_bitmap = 0x00;
3032309b 5011 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5012 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5013 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5014
5015#endif
9a799d71
AK		 5016
5017 /* default flow control settings */
cd7664f6 5018 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5019 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5020 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5021 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5022 hw->fc.send_xon = true;
73d80953 5023 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5024
99d74487
AD		 5025#ifdef CONFIG_PCI_IOV
5026 /* assign number of SR-IOV VFs */
5027 if (hw->mac.type != ixgbe_mac_82598EB)
5028 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
5029
5030#endif
30efa5a3 5031 /* enable itr by default in dynamic mode */
f7554a2b 5032 adapter->rx_itr_setting = 1;
f7554a2b 5033 adapter->tx_itr_setting = 1;
30efa5a3 5034
30efa5a3
JB		 5035 /* set default ring sizes */
5036 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5037 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5038
bd198058 5039 /* set default work limits */
59224555 5040 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5041
9a799d71 5042 /* initialize eeprom parameters */
c44ade9e 5043 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5044 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5045 return -EIO;
5046 }
5047
2a47fa45
JF		 5048 /* PF holds first pool slot */
5049 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5050 set_bit(__IXGBE_DOWN, &adapter->state);
5051
5052 return 0;
5053}
5054
5055/**
5056 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5057 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5058 *
5059 * Return 0 on success, negative on failure
5060 **/
b6ec895e 5061int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5062{
b6ec895e 5063 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5064 int orig_node = dev_to_node(dev);
5065 int numa_node = -1;
9a799d71
AK		 5066 int size;
5067
3a581073 5068 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5069
5070 if (tx_ring->q_vector)
5071 numa_node = tx_ring->q_vector->numa_node;
5072
5073 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5074 if (!tx_ring->tx_buffer_info)
89bf67f1 5075 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5076 if (!tx_ring->tx_buffer_info)
5077 goto err;
9a799d71
AK		 5078
5079 /* round up to nearest 4K */
12207e49 5080 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5081 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5082
de88eeeb
AD		 5083 set_dev_node(dev, numa_node);
5084 tx_ring->desc = dma_alloc_coherent(dev,
5085 tx_ring->size,
5086 &tx_ring->dma,
5087 GFP_KERNEL);
5088 set_dev_node(dev, orig_node);
5089 if (!tx_ring->desc)
5090 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5091 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5092 if (!tx_ring->desc)
5093 goto err;
9a799d71 5094
3a581073
JB		 5095 tx_ring->next_to_use = 0;
5096 tx_ring->next_to_clean = 0;
9a799d71 5097 return 0;
e01c31a5
JB		 5098
5099err:
5100 vfree(tx_ring->tx_buffer_info);
5101 tx_ring->tx_buffer_info = NULL;
b6ec895e 5102 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5103 return -ENOMEM;
9a799d71
AK		 5104}
5105
69888674
AD		 5106/**
5107 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5108 * @adapter: board private structure
5109 *
5110 * If this function returns with an error, then it's possible one or
5111 * more of the rings is populated (while the rest are not). It is the
5112 * callers duty to clean those orphaned rings.
5113 *
5114 * Return 0 on success, negative on failure
5115 **/
5116static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5117{
5118 int i, err = 0;
5119
5120 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5121 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5122 if (!err)
5123 continue;
de3d5b94 5124
396e799c 5125 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5126 goto err_setup_tx;
69888674
AD		 5127 }
5128
de3d5b94
AD		 5129 return 0;
5130err_setup_tx:
5131 /* rewind the index freeing the rings as we go */
5132 while (i--)
5133 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5134 return err;
5135}
5136
9a799d71
AK		 5137/**
5138 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5139 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5140 *
5141 * Returns 0 on success, negative on failure
5142 **/
b6ec895e 5143int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5144{
b6ec895e 5145 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5146 int orig_node = dev_to_node(dev);
5147 int numa_node = -1;
021230d4 5148 int size;
9a799d71 5149
3a581073 5150 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5151
5152 if (rx_ring->q_vector)
5153 numa_node = rx_ring->q_vector->numa_node;
5154
5155 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5156 if (!rx_ring->rx_buffer_info)
89bf67f1 5157 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5158 if (!rx_ring->rx_buffer_info)
5159 goto err;
9a799d71 5160
9a799d71 5161 /* Round up to nearest 4K */
3a581073
JB		 5162 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5163 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5164
de88eeeb
AD		 5165 set_dev_node(dev, numa_node);
5166 rx_ring->desc = dma_alloc_coherent(dev,
5167 rx_ring->size,
5168 &rx_ring->dma,
5169 GFP_KERNEL);
5170 set_dev_node(dev, orig_node);
5171 if (!rx_ring->desc)
5172 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5173 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5174 if (!rx_ring->desc)
5175 goto err;
9a799d71 5176
3a581073
JB		 5177 rx_ring->next_to_clean = 0;
5178 rx_ring->next_to_use = 0;
9a799d71
AK		 5179
5180 return 0;
b6ec895e
AD		 5181err:
5182 vfree(rx_ring->rx_buffer_info);
5183 rx_ring->rx_buffer_info = NULL;
5184 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5185 return -ENOMEM;
9a799d71
AK		 5186}
5187
69888674
AD		 5188/**
5189 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5190 * @adapter: board private structure
5191 *
5192 * If this function returns with an error, then it's possible one or
5193 * more of the rings is populated (while the rest are not). It is the
5194 * callers duty to clean those orphaned rings.
5195 *
5196 * Return 0 on success, negative on failure
5197 **/
69888674
AD		 5198static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5199{
5200 int i, err = 0;
5201
5202 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5203 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5204 if (!err)
5205 continue;
de3d5b94 5206
396e799c 5207 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5208 goto err_setup_rx;
69888674
AD		 5209 }
5210
7c8ae65a
AD		 5211#ifdef IXGBE_FCOE
5212 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5213 if (!err)
5214#endif
5215 return 0;
de3d5b94
AD		 5216err_setup_rx:
5217 /* rewind the index freeing the rings as we go */
5218 while (i--)
5219 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5220 return err;
5221}
5222
9a799d71
AK		 5223/**
5224 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5225 * @tx_ring: Tx descriptor ring for a specific queue
5226 *
5227 * Free all transmit software resources
5228 **/
b6ec895e 5229void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5230{
b6ec895e 5231 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5232
5233 vfree(tx_ring->tx_buffer_info);
5234 tx_ring->tx_buffer_info = NULL;
5235
b6ec895e
AD		 5236 /* if not set, then don't free */
5237 if (!tx_ring->desc)
5238 return;
5239
5240 dma_free_coherent(tx_ring->dev, tx_ring->size,
5241 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5242
5243 tx_ring->desc = NULL;
5244}
5245
5246/**
5247 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5248 * @adapter: board private structure
5249 *
5250 * Free all transmit software resources
5251 **/
5252static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5253{
5254 int i;
5255
5256 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5257 if (adapter->tx_ring[i]->desc)
b6ec895e 5258 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5259}
5260
5261/**
b4617240 5262 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5263 * @rx_ring: ring to clean the resources from
5264 *
5265 * Free all receive software resources
5266 **/
b6ec895e 5267void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5268{
b6ec895e 5269 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5270
5271 vfree(rx_ring->rx_buffer_info);
5272 rx_ring->rx_buffer_info = NULL;
5273
b6ec895e
AD		 5274 /* if not set, then don't free */
5275 if (!rx_ring->desc)
5276 return;
5277
5278 dma_free_coherent(rx_ring->dev, rx_ring->size,
5279 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5280
5281 rx_ring->desc = NULL;
5282}
5283
5284/**
5285 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5286 * @adapter: board private structure
5287 *
5288 * Free all receive software resources
5289 **/
5290static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5291{
5292 int i;
5293
7c8ae65a
AD		 5294#ifdef IXGBE_FCOE
5295 ixgbe_free_fcoe_ddp_resources(adapter);
5296
5297#endif
9a799d71 5298 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5299 if (adapter->rx_ring[i]->desc)
b6ec895e 5300 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5301}
5302
9a799d71
AK		 5303/**
5304 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5305 * @netdev: network interface device structure
5306 * @new_mtu: new value for maximum frame size
5307 *
5308 * Returns 0 on success, negative on failure
5309 **/
5310static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5311{
5312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5313 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5314
42c783c5 5315 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5316 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5317 return -EINVAL;
5318
5319 /*
872844dd
AD		 5320 * For 82599EB we cannot allow legacy VFs to enable their receive
5321 * paths when MTU greater than 1500 is configured. So display a
5322 * warning that legacy VFs will be disabled.
655309e9
AD		 5323 */
5324 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5325 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5326 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5327 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5328
396e799c 5329 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5330
021230d4 5331 /* must set new MTU before calling down or up */
9a799d71
AK		 5332 netdev->mtu = new_mtu;
5333
d4f80882
AV		 5334 if (netif_running(netdev))
5335 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5336
5337 return 0;
5338}
5339
5340/**
5341 * ixgbe_open - Called when a network interface is made active
5342 * @netdev: network interface device structure
5343 *
5344 * Returns 0 on success, negative value on failure
5345 *
5346 * The open entry point is called when a network interface is made
5347 * active by the system (IFF_UP). At this point all resources needed
5348 * for transmit and receive operations are allocated, the interrupt
5349 * handler is registered with the OS, the watchdog timer is started,
5350 * and the stack is notified that the interface is ready.
5351 **/
5352static int ixgbe_open(struct net_device *netdev)
5353{
5354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5355 int err, queues;
4bebfaa5
AK		 5356
5357 /* disallow open during test */
5358 if (test_bit(__IXGBE_TESTING, &adapter->state))
5359 return -EBUSY;
9a799d71 5360
54386467
JB		 5361 netif_carrier_off(netdev);
5362
9a799d71
AK		 5363 /* allocate transmit descriptors */
5364 err = ixgbe_setup_all_tx_resources(adapter);
5365 if (err)
5366 goto err_setup_tx;
5367
9a799d71
AK		 5368 /* allocate receive descriptors */
5369 err = ixgbe_setup_all_rx_resources(adapter);
5370 if (err)
5371 goto err_setup_rx;
5372
5373 ixgbe_configure(adapter);
5374
021230d4 5375 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5376 if (err)
5377 goto err_req_irq;
5378
ac802f5d 5379 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5380 if (adapter->num_rx_pools > 1)
5381 queues = adapter->num_rx_queues_per_pool;
5382 else
5383 queues = adapter->num_tx_queues;
5384
5385 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5386 if (err)
5387 goto err_set_queues;
5388
2a47fa45
JF		 5389 if (adapter->num_rx_pools > 1 &&
5390 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5391 queues = IXGBE_MAX_L2A_QUEUES;
5392 else
5393 queues = adapter->num_rx_queues;
5394 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5395 if (err)
5396 goto err_set_queues;
5397
1a71ab24 5398 ixgbe_ptp_init(adapter);
1a71ab24 5399
c7ccde0f 5400 ixgbe_up_complete(adapter);
9a799d71
AK		 5401
5402 return 0;
5403
ac802f5d
AD		 5404err_set_queues:
5405 ixgbe_free_irq(adapter);
9a799d71 5406err_req_irq:
a20a1199 5407 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5408err_setup_rx:
a20a1199 5409 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5410err_setup_tx:
9a799d71
AK		 5411 ixgbe_reset(adapter);
5412
5413 return err;
5414}
5415
5416/**
5417 * ixgbe_close - Disables a network interface
5418 * @netdev: network interface device structure
5419 *
5420 * Returns 0, this is not allowed to fail
5421 *
5422 * The close entry point is called when an interface is de-activated
5423 * by the OS. The hardware is still under the drivers control, but
5424 * needs to be disabled. A global MAC reset is issued to stop the
5425 * hardware, and all transmit and receive resources are freed.
5426 **/
5427static int ixgbe_close(struct net_device *netdev)
5428{
5429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5430
1a71ab24 5431 ixgbe_ptp_stop(adapter);
1a71ab24 5432
9a799d71
AK		 5433 ixgbe_down(adapter);
5434 ixgbe_free_irq(adapter);
5435
e4911d57
AD		 5436 ixgbe_fdir_filter_exit(adapter);
5437
9a799d71
AK		 5438 ixgbe_free_all_tx_resources(adapter);
5439 ixgbe_free_all_rx_resources(adapter);
5440
5eba3699 5441 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5442
5443 return 0;
5444}
5445
b3c8b4ba
AD		 5446#ifdef CONFIG_PM
5447static int ixgbe_resume(struct pci_dev *pdev)
5448{
c60fbb00
AD		 5449 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5450 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5451 u32 err;
5452
5453 pci_set_power_state(pdev, PCI_D0);
5454 pci_restore_state(pdev);
656ab817
DS		 5455 /*
5456 * pci_restore_state clears dev->state_saved so call
5457 * pci_save_state to restore it.
5458 */
5459 pci_save_state(pdev);
9ce77666 5460
5461 err = pci_enable_device_mem(pdev);
b3c8b4ba 5462 if (err) {
849c4542 5463 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5464 return err;
5465 }
5466 pci_set_master(pdev);
5467
dd4d8ca6 5468 pci_wake_from_d3(pdev, false);
b3c8b4ba 5469
b3c8b4ba
AD		 5470 ixgbe_reset(adapter);
5471
495dce12
WJP		 5472 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5473
ac802f5d
AD		 5474 rtnl_lock();
5475 err = ixgbe_init_interrupt_scheme(adapter);
5476 if (!err && netif_running(netdev))
c60fbb00 5477 err = ixgbe_open(netdev);
ac802f5d
AD		 5478
5479 rtnl_unlock();
5480
5481 if (err)
5482 return err;
b3c8b4ba
AD		 5483
5484 netif_device_attach(netdev);
5485
5486 return 0;
5487}
b3c8b4ba 5488#endif /* CONFIG_PM */
9d8d05ae
RW		 5489
5490static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5491{
c60fbb00
AD		 5492 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5493 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5494 struct ixgbe_hw *hw = &adapter->hw;
5495 u32 ctrl, fctrl;
5496 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5497#ifdef CONFIG_PM
5498 int retval = 0;
5499#endif
5500
5501 netif_device_detach(netdev);
5502
499ab5cc 5503 rtnl_lock();
b3c8b4ba
AD		 5504 if (netif_running(netdev)) {
5505 ixgbe_down(adapter);
5506 ixgbe_free_irq(adapter);
5507 ixgbe_free_all_tx_resources(adapter);
5508 ixgbe_free_all_rx_resources(adapter);
5509 }
499ab5cc 5510 rtnl_unlock();
b3c8b4ba 5511
5f5ae6fc
AD		 5512 ixgbe_clear_interrupt_scheme(adapter);
5513
b3c8b4ba
AD		 5514#ifdef CONFIG_PM
5515 retval = pci_save_state(pdev);
5516 if (retval)
5517 return retval;
4df10466 5518
b3c8b4ba 5519#endif
f4f1040a
JK		 5520 if (hw->mac.ops.stop_link_on_d3)
5521 hw->mac.ops.stop_link_on_d3(hw);
5522
e8e26350
PW		 5523 if (wufc) {
5524 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5525
ec74a471
ET		 5526 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5527 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5528 hw->mac.ops.enable_tx_laser(hw);
5529
e8e26350
PW		 5530 /* turn on all-multi mode if wake on multicast is enabled */
5531 if (wufc & IXGBE_WUFC_MC) {
5532 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5533 fctrl |= IXGBE_FCTRL_MPE;
5534 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5535 }
5536
5537 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5538 ctrl |= IXGBE_CTRL_GIO_DIS;
5539 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5540
5541 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5542 } else {
5543 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5544 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5545 }
5546
bd508178
AD		 5547 switch (hw->mac.type) {
5548 case ixgbe_mac_82598EB:
dd4d8ca6 5549 pci_wake_from_d3(pdev, false);
bd508178
AD		 5550 break;
5551 case ixgbe_mac_82599EB:
b93a2226 5552 case ixgbe_mac_X540:
bd508178
AD		 5553 pci_wake_from_d3(pdev, !!wufc);
5554 break;
5555 default:
5556 break;
5557 }
b3c8b4ba 5558
9d8d05ae
RW		 5559 *enable_wake = !!wufc;
5560
b3c8b4ba
AD		 5561 ixgbe_release_hw_control(adapter);
5562
5563 pci_disable_device(pdev);
5564
9d8d05ae
RW		 5565 return 0;
5566}
5567
5568#ifdef CONFIG_PM
5569static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5570{
5571 int retval;
5572 bool wake;
5573
5574 retval = __ixgbe_shutdown(pdev, &wake);
5575 if (retval)
5576 return retval;
5577
5578 if (wake) {
5579 pci_prepare_to_sleep(pdev);
5580 } else {
5581 pci_wake_from_d3(pdev, false);
5582 pci_set_power_state(pdev, PCI_D3hot);
5583 }
b3c8b4ba
AD		 5584
5585 return 0;
5586}
9d8d05ae 5587#endif /* CONFIG_PM */
b3c8b4ba
AD		 5588
5589static void ixgbe_shutdown(struct pci_dev *pdev)
5590{
9d8d05ae
RW		 5591 bool wake;
5592
5593 __ixgbe_shutdown(pdev, &wake);
5594
5595 if (system_state == SYSTEM_POWER_OFF) {
5596 pci_wake_from_d3(pdev, wake);
5597 pci_set_power_state(pdev, PCI_D3hot);
5598 }
b3c8b4ba
AD		 5599}
5600
9a799d71
AK		 5601/**
5602 * ixgbe_update_stats - Update the board statistics counters.
5603 * @adapter: board private structure
5604 **/
5605void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5606{
2d86f139 5607 struct net_device *netdev = adapter->netdev;
9a799d71 5608 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5609 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5610 u64 total_mpc = 0;
5611 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5612 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5613 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5614 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5615
d08935c2
DS		 5616 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5617 test_bit(__IXGBE_RESETTING, &adapter->state))
5618 return;
5619
94b982b2 5620 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5621 u64 rsc_count = 0;
94b982b2 5622 u64 rsc_flush = 0;
94b982b2 5623 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5624 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5625 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5626 }
5627 adapter->rsc_total_count = rsc_count;
5628 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5629 }
5630
5b7da515
AD		 5631 for (i = 0; i < adapter->num_rx_queues; i++) {
5632 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5633 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5634 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5635 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5636 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5637 bytes += rx_ring->stats.bytes;
5638 packets += rx_ring->stats.packets;
5639 }
5640 adapter->non_eop_descs = non_eop_descs;
5641 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5642 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5643 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5644 netdev->stats.rx_bytes = bytes;
5645 netdev->stats.rx_packets = packets;
5646
5647 bytes = 0;
5648 packets = 0;
7ca3bc58 5649 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5650 for (i = 0; i < adapter->num_tx_queues; i++) {
5651 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5652 restart_queue += tx_ring->tx_stats.restart_queue;
5653 tx_busy += tx_ring->tx_stats.tx_busy;
5654 bytes += tx_ring->stats.bytes;
5655 packets += tx_ring->stats.packets;
5656 }
eb985f09 5657 adapter->restart_queue = restart_queue;
5b7da515
AD		 5658 adapter->tx_busy = tx_busy;
5659 netdev->stats.tx_bytes = bytes;
5660 netdev->stats.tx_packets = packets;
7ca3bc58 5661
7ca647bd 5662 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5663
5664 /* 8 register reads */
6f11eef7
AV		 5665 for (i = 0; i < 8; i++) {
5666 /* for packet buffers not used, the register should read 0 */
5667 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5668 missed_rx += mpc;
7ca647bd
JP		 5669 hwstats->mpc[i] += mpc;
5670 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5671 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5672 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5673 switch (hw->mac.type) {
5674 case ixgbe_mac_82598EB:
1a70db4b
ET		 5675 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5676 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5677 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5678 hwstats->pxonrxc[i] +=
5679 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5680 break;
5681 case ixgbe_mac_82599EB:
b93a2226 5682 case ixgbe_mac_X540:
bd508178
AD		 5683 hwstats->pxonrxc[i] +=
5684 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5685 break;
5686 default:
5687 break;
e8e26350 5688 }
6f11eef7 5689 }
1a70db4b
ET		 5690
5691 /*16 register reads */
5692 for (i = 0; i < 16; i++) {
5693 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5694 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5695 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5696 (hw->mac.type == ixgbe_mac_X540)) {
5697 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5698 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5699 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5700 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5701 }
5702 }
5703
7ca647bd 5704 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5705 /* work around hardware counting issue */
7ca647bd 5706 hwstats->gprc -= missed_rx;
6f11eef7 5707
c84d324c
JF		 5708 ixgbe_update_xoff_received(adapter);
5709
6f11eef7 5710 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5711 switch (hw->mac.type) {
5712 case ixgbe_mac_82598EB:
5713 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5714 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5715 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5716 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5717 break;
b93a2226 5718 case ixgbe_mac_X540:
58f6bcf9
ET		 5719 /* OS2BMC stats are X540 only*/
5720 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5721 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5722 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5723 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5724 case ixgbe_mac_82599EB:
a4d4f629
AD		 5725 for (i = 0; i < 16; i++)
5726 adapter->hw_rx_no_dma_resources +=
5727 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5728 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5729 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5730 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5731 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5732 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5733 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5734 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5735 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5736 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5737#ifdef IXGBE_FCOE
7ca647bd
JP		 5738 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5739 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5740 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5741 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5742 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5743 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5744 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5745 if (adapter->fcoe.ddp_pool) {
5746 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5747 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5748 unsigned int cpu;
5749 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5750 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5751 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5752 noddp += ddp_pool->noddp;
5753 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5754 }
5a1ee270
AD		 5755 hwstats->fcoe_noddp = noddp;
5756 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5757 }
6d45522c 5758#endif /* IXGBE_FCOE */
bd508178
AD		 5759 break;
5760 default:
5761 break;
e8e26350 5762 }
9a799d71 5763 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5764 hwstats->bprc += bprc;
5765 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5766 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5767 hwstats->mprc -= bprc;
5768 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5769 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5770 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5771 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5772 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5773 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5774 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5775 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5776 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5777 hwstats->lxontxc += lxon;
6f11eef7 5778 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5779 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5780 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5781 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5782 /*
5783 * 82598 errata - tx of flow control packets is included in tx counters
5784 */
5785 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5786 hwstats->gptc -= xon_off_tot;
5787 hwstats->mptc -= xon_off_tot;
5788 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5789 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5790 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5791 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5792 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5793 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5794 hwstats->ptc64 -= xon_off_tot;
5795 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5796 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5797 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5798 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5799 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5800 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5801
5802 /* Fill out the OS statistics structure */
7ca647bd 5803 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5804
5805 /* Rx Errors */
7ca647bd 5806 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5807 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5808 netdev->stats.rx_length_errors = hwstats->rlec;
5809 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5810 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5811}
5812
5813/**
d034acf1 5814 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5815 * @adapter: pointer to the device adapter structure
9a799d71 5816 **/
d034acf1 5817static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5818{
cf8280ee 5819 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5820 int i;
cf8280ee 5821
d034acf1
AD		 5822 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5823 return;
5824
5825 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5826
d034acf1 5827 /* if interface is down do nothing */
fe49f04a 5828 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5829 return;
5830
5831 /* do nothing if we are not using signature filters */
5832 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5833 return;
5834
5835 adapter->fdir_overflow++;
5836
93c52dd0
AD		 5837 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5838 for (i = 0; i < adapter->num_tx_queues; i++)
5839 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5840 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5841 /* re-enable flow director interrupts */
5842 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5843 } else {
5844 e_err(probe, "failed to finish FDIR re-initialization, "
5845 "ignored adding FDIR ATR filters\n");
5846 }
93c52dd0
AD		 5847}
5848
5849/**
5850 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5851 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5852 *
5853 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5854 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5855 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5856 * determine if a hang has occurred.
93c52dd0
AD		 5857 */
5858static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5859{
cf8280ee 5860 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5861 u64 eics = 0;
5862 int i;
cf8280ee 5863
93c52dd0
AD		 5864 /* If we're down or resetting, just bail */
5865 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5866 test_bit(__IXGBE_RESETTING, &adapter->state))
5867 return;
22d5a71b 5868
93c52dd0
AD		 5869 /* Force detection of hung controller */
5870 if (netif_carrier_ok(adapter->netdev)) {
5871 for (i = 0; i < adapter->num_tx_queues; i++)
5872 set_check_for_tx_hang(adapter->tx_ring[i]);
5873 }
22d5a71b 5874
fe49f04a
AD		 5875 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5876 /*
5877 * for legacy and MSI interrupts don't set any bits
5878 * that are enabled for EIAM, because this operation
5879 * would set *both* EIMS and EICS for any bit in EIAM
5880 */
5881 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5882 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5883 } else {
5884 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5885 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5886 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5887 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5888 eics |= ((u64)1 << i);
5889 }
cf8280ee 5890 }
9a799d71 5891
93c52dd0 5892 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5893 ixgbe_irq_rearm_queues(adapter, eics);
5894
cf8280ee
JB		 5895}
5896
e8e26350 5897/**
93c52dd0 5898 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5899 * @adapter: pointer to the device adapter structure
5900 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5901 **/
93c52dd0 5902static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5903{
e8e26350 5904 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5905 u32 link_speed = adapter->link_speed;
5906 bool link_up = adapter->link_up;
041441d0 5907 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5908
93c52dd0
AD		 5909 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5910 return;
5911
5912 if (hw->mac.ops.check_link) {
5913 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5914 } else {
93c52dd0
AD		 5915 /* always assume link is up, if no check link function */
5916 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5917 link_up = true;
c4cf55e5 5918 }
041441d0
AD		 5919
5920 if (adapter->ixgbe_ieee_pfc)
5921 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5922
3ebe8fde 5923 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5924 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5925 ixgbe_set_rx_drop_en(adapter);
5926 }
93c52dd0
AD		 5927
5928 if (link_up ||
5929 time_after(jiffies, (adapter->link_check_timeout +
5930 IXGBE_TRY_LINK_TIMEOUT))) {
5931 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5932 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5933 IXGBE_WRITE_FLUSH(hw);
5934 }
5935
5936 adapter->link_up = link_up;
5937 adapter->link_speed = link_speed;
e8e26350
PW		 5938}
5939
107d3018
AD		 5940static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5941{
5942#ifdef CONFIG_IXGBE_DCB
5943 struct net_device *netdev = adapter->netdev;
5944 struct dcb_app app = {
5945 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5946 .protocol = 0,
5947 };
5948 u8 up = 0;
5949
5950 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5951 up = dcb_ieee_getapp_mask(netdev, &app);
5952
5953 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5954#endif
5955}
5956
e8e26350 5957/**
93c52dd0
AD		 5958 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5959 * print link up message
49ce9c2c 5960 * @adapter: pointer to the device adapter structure
e8e26350 5961 **/
93c52dd0 5962static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5963{
93c52dd0 5964 struct net_device *netdev = adapter->netdev;
e8e26350 5965 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5966 u32 link_speed = adapter->link_speed;
5967 bool flow_rx, flow_tx;
e8e26350 5968
93c52dd0
AD		 5969 /* only continue if link was previously down */
5970 if (netif_carrier_ok(netdev))
a985b6c3 5971 return;
63d6e1d8 5972
93c52dd0 5973 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5974
93c52dd0
AD		 5975 switch (hw->mac.type) {
5976 case ixgbe_mac_82598EB: {
5977 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5978 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5979 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5980 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5981 }
5982 break;
5983 case ixgbe_mac_X540:
5984 case ixgbe_mac_82599EB: {
5985 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5986 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5987 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5988 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5989 }
5990 break;
5991 default:
5992 flow_tx = false;
5993 flow_rx = false;
5994 break;
e8e26350 5995 }
3a6a4eda 5996
6cb562d6
JK		 5997 adapter->last_rx_ptp_check = jiffies;
5998
8fecf67c 5999 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6000 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6001
93c52dd0
AD		 6002 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6003 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6004 "10 Gbps" :
6005 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6006 "1 Gbps" :
6007 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6008 "100 Mbps" :
6009 "unknown speed"))),
6010 ((flow_rx && flow_tx) ? "RX/TX" :
6011 (flow_rx ? "RX" :
6012 (flow_tx ? "TX" : "None"))));
e8e26350 6013
93c52dd0 6014 netif_carrier_on(netdev);
93c52dd0 6015 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6016
107d3018
AD		 6017 /* update the default user priority for VFs */
6018 ixgbe_update_default_up(adapter);
6019
befa2af7
AD		 6020 /* ping all the active vfs to let them know link has changed */
6021 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6022}
6023
c4cf55e5 6024/**
93c52dd0
AD		 6025 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6026 * print link down message
49ce9c2c 6027 * @adapter: pointer to the adapter structure
c4cf55e5 6028 **/
581330ba 6029static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6030{
cf8280ee 6031 struct net_device *netdev = adapter->netdev;
c4cf55e5 6032 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6033
93c52dd0
AD		 6034 adapter->link_up = false;
6035 adapter->link_speed = 0;
cf8280ee 6036
93c52dd0
AD		 6037 /* only continue if link was up previously */
6038 if (!netif_carrier_ok(netdev))
6039 return;
264857b8 6040
93c52dd0
AD		 6041 /* poll for SFP+ cable when link is down */
6042 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6043 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6044
8fecf67c 6045 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6046 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6047
93c52dd0
AD		 6048 e_info(drv, "NIC Link is Down\n");
6049 netif_carrier_off(netdev);
befa2af7
AD		 6050
6051 /* ping all the active vfs to let them know link has changed */
6052 ixgbe_ping_all_vfs(adapter);
93c52dd0 6053}
e8e26350 6054
93c52dd0
AD		 6055/**
6056 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6057 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6058 **/
6059static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6060{
c4cf55e5 6061 int i;
93c52dd0 6062 int some_tx_pending = 0;
c4cf55e5 6063
93c52dd0 6064 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6065 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6066 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6067 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6068 some_tx_pending = 1;
6069 break;
6070 }
6071 }
6072
6073 if (some_tx_pending) {
6074 /* We've lost link, so the controller stops DMA,
6075 * but we've got queued Tx work that's never going
6076 * to get done, so reset controller to flush Tx.
6077 * (Do the reset outside of interrupt context).
6078 */
12ff3f3b 6079 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6081 }
c4cf55e5 6082 }
c4cf55e5
PWJ		 6083}
6084
a985b6c3
GR		 6085static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6086{
6087 u32 ssvpc;
6088
0584d999
GR		 6089 /* Do not perform spoof check for 82598 or if not in IOV mode */
6090 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6091 adapter->num_vfs == 0)
a985b6c3
GR		 6092 return;
6093
6094 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6095
6096 /*
6097 * ssvpc register is cleared on read, if zero then no
6098 * spoofed packets in the last interval.
6099 */
6100 if (!ssvpc)
6101 return;
6102
d6ea0754 6103 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6104}
6105
93c52dd0
AD		 6106/**
6107 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6108 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6109 **/
6110static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6111{
6112 /* if interface is down do nothing */
7edebf9a
ET		 6113 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6114 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6115 return;
6116
6117 ixgbe_watchdog_update_link(adapter);
6118
6119 if (adapter->link_up)
6120 ixgbe_watchdog_link_is_up(adapter);
6121 else
6122 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6123
a985b6c3 6124 ixgbe_spoof_check(adapter);
9a799d71 6125 ixgbe_update_stats(adapter);
93c52dd0
AD		 6126
6127 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6128}
10eec955 6129
cf8280ee 6130/**
7086400d 6131 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6132 * @adapter: the ixgbe adapter structure
cf8280ee 6133 **/
7086400d 6134static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6135{
cf8280ee 6136 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6137 s32 err;
cf8280ee 6138
7086400d
AD		 6139 /* not searching for SFP so there is nothing to do here */
6140 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6141 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6142 return;
10eec955 6143
7086400d
AD		 6144 /* someone else is in init, wait until next service event */
6145 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6146 return;
cf8280ee 6147
7086400d
AD		 6148 err = hw->phy.ops.identify_sfp(hw);
6149 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6150 goto sfp_out;
264857b8 6151
7086400d
AD		 6152 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6153 /* If no cable is present, then we need to reset
6154 * the next time we find a good cable. */
6155 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6156 }
9a799d71 6157
7086400d
AD		 6158 /* exit on error */
6159 if (err)
6160 goto sfp_out;
e8e26350 6161
7086400d
AD		 6162 /* exit if reset not needed */
6163 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6164 goto sfp_out;
9a799d71 6165
7086400d 6166 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6167
7086400d
AD		 6168 /*
6169 * A module may be identified correctly, but the EEPROM may not have
6170 * support for that module. setup_sfp() will fail in that case, so
6171 * we should not allow that module to load.
6172 */
6173 if (hw->mac.type == ixgbe_mac_82598EB)
6174 err = hw->phy.ops.reset(hw);
6175 else
6176 err = hw->mac.ops.setup_sfp(hw);
6177
6178 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6179 goto sfp_out;
6180
6181 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6182 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6183
6184sfp_out:
6185 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6186
6187 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6188 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6189 e_dev_err("failed to initialize because an unsupported "
6190 "SFP+ module type was detected.\n");
6191 e_dev_err("Reload the driver after installing a "
6192 "supported module.\n");
6193 unregister_netdev(adapter->netdev);
bc59fcda 6194 }
7086400d 6195}
bc59fcda 6196
7086400d
AD		 6197/**
6198 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6199 * @adapter: the ixgbe adapter structure
7086400d
AD		 6200 **/
6201static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6202{
6203 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6204 u32 speed;
6205 bool autoneg = false;
7086400d
AD		 6206
6207 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6208 return;
6209
6210 /* someone else is in init, wait until next service event */
6211 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6212 return;
6213
6214 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6215
3d292265 6216 speed = hw->phy.autoneg_advertised;
ed33ff66 6217 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6218 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6219
6220 /* setup the highest link when no autoneg */
6221 if (!autoneg) {
6222 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6223 speed = IXGBE_LINK_SPEED_10GB_FULL;
6224 }
6225 }
6226
7086400d 6227 if (hw->mac.ops.setup_link)
fd0326f2 6228 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6229
6230 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6231 adapter->link_check_timeout = jiffies;
6232 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6233}
6234
83c61fa9
GR		 6235#ifdef CONFIG_PCI_IOV
6236static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6237{
6238 int vf;
6239 struct ixgbe_hw *hw = &adapter->hw;
6240 struct net_device *netdev = adapter->netdev;
6241 u32 gpc;
6242 u32 ciaa, ciad;
6243
6244 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6245 if (gpc) /* If incrementing then no need for the check below */
6246 return;
6247 /*
6248 * Check to see if a bad DMA write target from an errant or
6249 * malicious VF has caused a PCIe error. If so then we can
6250 * issue a VFLR to the offending VF(s) and then resume without
6251 * requesting a full slot reset.
6252 */
6253
6254 for (vf = 0; vf < adapter->num_vfs; vf++) {
6255 ciaa = (vf << 16) | 0x80000000;
6256 /* 32 bit read so align, we really want status at offset 6 */
6257 ciaa |= PCI_COMMAND;
6258 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6259 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6260 ciaa &= 0x7FFFFFFF;
6261 /* disable debug mode asap after reading data */
6262 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6263 /* Get the upper 16 bits which will be the PCI status reg */
6264 ciad >>= 16;
6265 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6266 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6267 /* Issue VFLR */
6268 ciaa = (vf << 16) | 0x80000000;
6269 ciaa |= 0xA8;
6270 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6271 ciad = 0x00008000; /* VFLR */
6272 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6273 ciaa &= 0x7FFFFFFF;
6274 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6275 }
6276 }
6277}
6278
6279#endif
7086400d
AD		 6280/**
6281 * ixgbe_service_timer - Timer Call-back
6282 * @data: pointer to adapter cast into an unsigned long
6283 **/
6284static void ixgbe_service_timer(unsigned long data)
6285{
6286 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6287 unsigned long next_event_offset;
83c61fa9 6288 bool ready = true;
7086400d 6289
6bb78cfb
AD		 6290 /* poll faster when waiting for link */
6291 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6292 next_event_offset = HZ / 10;
6293 else
6294 next_event_offset = HZ * 2;
83c61fa9 6295
6bb78cfb 6296#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6297 /*
6298 * don't bother with SR-IOV VF DMA hang check if there are
6299 * no VFs or the link is down
6300 */
6301 if (!adapter->num_vfs ||
6bb78cfb 6302 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6303 goto normal_timer_service;
83c61fa9
GR		 6304
6305 /* If we have VFs allocated then we must check for DMA hangs */
6306 ixgbe_check_for_bad_vf(adapter);
6307 next_event_offset = HZ / 50;
6308 adapter->timer_event_accumulator++;
6309
6bb78cfb 6310 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6311 adapter->timer_event_accumulator = 0;
7086400d 6312 else
6bb78cfb 6313 ready = false;
7086400d 6314
6bb78cfb 6315normal_timer_service:
83c61fa9 6316#endif
7086400d
AD		 6317 /* Reset the timer */
6318 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6319
83c61fa9
GR		 6320 if (ready)
6321 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6322}
6323
c83c6cbd
AD		 6324static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6325{
6326 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6327 return;
6328
6329 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6330
6331 /* If we're already down or resetting, just bail */
6332 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6333 test_bit(__IXGBE_RESETTING, &adapter->state))
6334 return;
6335
6336 ixgbe_dump(adapter);
6337 netdev_err(adapter->netdev, "Reset adapter\n");
6338 adapter->tx_timeout_count++;
6339
6340 ixgbe_reinit_locked(adapter);
6341}
6342
7086400d
AD		 6343/**
6344 * ixgbe_service_task - manages and runs subtasks
6345 * @work: pointer to work_struct containing our data
6346 **/
6347static void ixgbe_service_task(struct work_struct *work)
6348{
6349 struct ixgbe_adapter *adapter = container_of(work,
6350 struct ixgbe_adapter,
6351 service_task);
c83c6cbd 6352 ixgbe_reset_subtask(adapter);
7086400d
AD		 6353 ixgbe_sfp_detection_subtask(adapter);
6354 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6355 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6356 ixgbe_watchdog_subtask(adapter);
d034acf1 6357 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6358 ixgbe_check_hang_subtask(adapter);
891dc082 6359
8fecf67c 6360 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6361 ixgbe_ptp_overflow_check(adapter);
6362 ixgbe_ptp_rx_hang(adapter);
6363 }
7086400d
AD		 6364
6365 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6366}
6367
fd0db0ed
AD		 6368static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6369 struct ixgbe_tx_buffer *first,
244e27ad 6370 u8 *hdr_len)
897ab156 6371{
fd0db0ed 6372 struct sk_buff *skb = first->skb;
897ab156
AD		 6373 u32 vlan_macip_lens, type_tucmd;
6374 u32 mss_l4len_idx, l4len;
9a799d71 6375
8f4fbb9b
AD		 6376 if (skb->ip_summed != CHECKSUM_PARTIAL)
6377 return 0;
6378
897ab156
AD		 6379 if (!skb_is_gso(skb))
6380 return 0;
9a799d71 6381
897ab156 6382 if (skb_header_cloned(skb)) {
244e27ad 6383 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6384 if (err)
6385 return err;
9a799d71 6386 }
9a799d71 6387
897ab156
AD		 6388 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6389 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6390
244e27ad 6391 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6392 struct iphdr *iph = ip_hdr(skb);
6393 iph->tot_len = 0;
6394 iph->check = 0;
6395 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6396 iph->daddr, 0,
6397 IPPROTO_TCP,
6398 0);
6399 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6400 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6401 IXGBE_TX_FLAGS_CSUM |
6402 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6403 } else if (skb_is_gso_v6(skb)) {
6404 ipv6_hdr(skb)->payload_len = 0;
6405 tcp_hdr(skb)->check =
6406 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6407 &ipv6_hdr(skb)->daddr,
6408 0, IPPROTO_TCP, 0);
244e27ad
AD		 6409 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6410 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6411 }
6412
091a6246 6413 /* compute header lengths */
897ab156
AD		 6414 l4len = tcp_hdrlen(skb);
6415 *hdr_len = skb_transport_offset(skb) + l4len;
6416
091a6246
AD		 6417 /* update gso size and bytecount with header size */
6418 first->gso_segs = skb_shinfo(skb)->gso_segs;
6419 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6420
c44f5f51 6421 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6422 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6423 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6424
6425 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6426 vlan_macip_lens = skb_network_header_len(skb);
6427 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6428 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6429
6430 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6431 mss_l4len_idx);
897ab156
AD		 6432
6433 return 1;
6434}
6435
244e27ad
AD		 6436static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6437 struct ixgbe_tx_buffer *first)
7ca647bd 6438{
fd0db0ed 6439 struct sk_buff *skb = first->skb;
897ab156
AD		 6440 u32 vlan_macip_lens = 0;
6441 u32 mss_l4len_idx = 0;
6442 u32 type_tucmd = 0;
7ca647bd 6443
897ab156 6444 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6445 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6446 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6447 return;
897ab156
AD		 6448 } else {
6449 u8 l4_hdr = 0;
244e27ad 6450 switch (first->protocol) {
897ab156
AD		 6451 case __constant_htons(ETH_P_IP):
6452 vlan_macip_lens |= skb_network_header_len(skb);
6453 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6454 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6455 break;
897ab156
AD		 6456 case __constant_htons(ETH_P_IPV6):
6457 vlan_macip_lens |= skb_network_header_len(skb);
6458 l4_hdr = ipv6_hdr(skb)->nexthdr;
6459 break;
6460 default:
6461 if (unlikely(net_ratelimit())) {
6462 dev_warn(tx_ring->dev,
6463 "partial checksum but proto=%x!\n",
244e27ad 6464 first->protocol);
897ab156 6465 }
7ca647bd
JP		 6466 break;
6467 }
897ab156
AD		 6468
6469 switch (l4_hdr) {
7ca647bd 6470 case IPPROTO_TCP:
897ab156
AD		 6471 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6472 mss_l4len_idx = tcp_hdrlen(skb) <<
6473 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6474 break;
6475 case IPPROTO_SCTP:
897ab156
AD		 6476 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6477 mss_l4len_idx = sizeof(struct sctphdr) <<
6478 IXGBE_ADVTXD_L4LEN_SHIFT;
6479 break;
6480 case IPPROTO_UDP:
6481 mss_l4len_idx = sizeof(struct udphdr) <<
6482 IXGBE_ADVTXD_L4LEN_SHIFT;
6483 break;
6484 default:
6485 if (unlikely(net_ratelimit())) {
6486 dev_warn(tx_ring->dev,
6487 "partial checksum but l4 proto=%x!\n",
244e27ad 6488 l4_hdr);
897ab156 6489 }
7ca647bd
JP		 6490 break;
6491 }
244e27ad
AD		 6492
6493 /* update TX checksum flag */
6494 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6495 }
6496
244e27ad 6497 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6498 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6499 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6500
897ab156
AD		 6501 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6502 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6503}
6504
472148c3
AD		 6505#define IXGBE_SET_FLAG(_input, _flag, _result) \
6506 ((_flag <= _result) ? \
6507 ((u32)(_input & _flag) * (_result / _flag)) : \
6508 ((u32)(_input & _flag) / (_flag / _result)))
6509
6510static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6511{
d3d00239 6512 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6513 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6514 IXGBE_ADVTXD_DCMD_DEXT |
6515 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6516
d3d00239 6517 /* set HW vlan bit if vlan is present */
472148c3
AD		 6518 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6519 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6520
d3d00239 6521 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6522 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6523 IXGBE_ADVTXD_DCMD_TSE);
6524
6525 /* set timestamp bit if present */
6526 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6527 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6528
62748b7b 6529 /* insert frame checksum */
472148c3 6530 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6531
d3d00239
AD		 6532 return cmd_type;
6533}
9a799d71 6534
729739b7
AD		 6535static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6536 u32 tx_flags, unsigned int paylen)
d3d00239 6537{
472148c3 6538 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6539
d3d00239 6540 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6541 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6542 IXGBE_TX_FLAGS_CSUM,
6543 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6544
93f5b3c1 6545 /* enble IPv4 checksum for TSO */
472148c3
AD		 6546 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6547 IXGBE_TX_FLAGS_IPV4,
6548 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6549
7f9643fd
AD		 6550 /*
6551 * Check Context must be set if Tx switch is enabled, which it
6552 * always is for case where virtual functions are running
6553 */
472148c3
AD		 6554 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6555 IXGBE_TX_FLAGS_CC,
6556 IXGBE_ADVTXD_CC);
7f9643fd 6557
472148c3 6558 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6559}
44df32c5 6560
d3d00239
AD		 6561#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6562 IXGBE_TXD_CMD_RS)
6563
6564static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6565 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6566 const u8 hdr_len)
6567{
fd0db0ed 6568 struct sk_buff *skb = first->skb;
729739b7 6569 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6570 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6571 struct skb_frag_struct *frag;
6572 dma_addr_t dma;
6573 unsigned int data_len, size;
244e27ad 6574 u32 tx_flags = first->tx_flags;
472148c3 6575 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6576 u16 i = tx_ring->next_to_use;
d3d00239 6577
729739b7
AD		 6578 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6579
ec718254
AD		 6580 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6581
6582 size = skb_headlen(skb);
6583 data_len = skb->data_len;
729739b7 6584
d3d00239
AD		 6585#ifdef IXGBE_FCOE
6586 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6587 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6588 size -= sizeof(struct fcoe_crc_eof) - data_len;
6589 data_len = 0;
729739b7
AD		 6590 } else {
6591 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6592 }
6593 }
44df32c5 6594
d3d00239 6595#endif
729739b7 6596 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6597
ec718254 6598 tx_buffer = first;
9a799d71 6599
ec718254
AD		 6600 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6601 if (dma_mapping_error(tx_ring->dev, dma))
6602 goto dma_error;
6603
6604 /* record length, and DMA address */
6605 dma_unmap_len_set(tx_buffer, len, size);
6606 dma_unmap_addr_set(tx_buffer, dma, dma);
6607
6608 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6609
729739b7 6610 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6611 tx_desc->read.cmd_type_len =
472148c3 6612 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6613
d3d00239 6614 i++;
729739b7 6615 tx_desc++;
d3d00239 6616 if (i == tx_ring->count) {
e4f74028 6617 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6618 i = 0;
6619 }
ec718254 6620 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6621
6622 dma += IXGBE_MAX_DATA_PER_TXD;
6623 size -= IXGBE_MAX_DATA_PER_TXD;
6624
6625 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6626 }
e5a43549 6627
729739b7
AD		 6628 if (likely(!data_len))
6629 break;
9a799d71 6630
472148c3 6631 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6632
729739b7
AD		 6633 i++;
6634 tx_desc++;
6635 if (i == tx_ring->count) {
6636 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6637 i = 0;
6638 }
ec718254 6639 tx_desc->read.olinfo_status = 0;
9a799d71 6640
d3d00239 6641#ifdef IXGBE_FCOE
9e903e08 6642 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6643#else
9e903e08 6644 size = skb_frag_size(frag);
d3d00239
AD		 6645#endif
6646 data_len -= size;
9a799d71 6647
729739b7
AD		 6648 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6649 DMA_TO_DEVICE);
9a799d71 6650
729739b7 6651 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6652 }
9a799d71 6653
729739b7 6654 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6655 cmd_type |= size | IXGBE_TXD_CMD;
6656 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6657
091a6246 6658 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6659
d3d00239
AD		 6660 /* set the timestamp */
6661 first->time_stamp = jiffies;
9a799d71
AK		 6662
6663 /*
729739b7
AD		 6664 * Force memory writes to complete before letting h/w know there
6665 * are new descriptors to fetch. (Only applicable for weak-ordered
6666 * memory model archs, such as IA-64).
6667 *
6668 * We also need this memory barrier to make certain all of the
6669 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6670 */
6671 wmb();
6672
d3d00239
AD		 6673 /* set next_to_watch value indicating a packet is present */
6674 first->next_to_watch = tx_desc;
6675
729739b7
AD		 6676 i++;
6677 if (i == tx_ring->count)
6678 i = 0;
6679
6680 tx_ring->next_to_use = i;
6681
d3d00239 6682 /* notify HW of packet */
84ea2591 6683 writel(i, tx_ring->tail);
d3d00239
AD		 6684
6685 return;
6686dma_error:
729739b7 6687 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6688
6689 /* clear dma mappings for failed tx_buffer_info map */
6690 for (;;) {
729739b7
AD		 6691 tx_buffer = &tx_ring->tx_buffer_info[i];
6692 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6693 if (tx_buffer == first)
d3d00239
AD		 6694 break;
6695 if (i == 0)
6696 i = tx_ring->count;
6697 i--;
6698 }
6699
d3d00239 6700 tx_ring->next_to_use = i;
9a799d71
AK		 6701}
6702
fd0db0ed 6703static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6704 struct ixgbe_tx_buffer *first)
69830529
AD		 6705{
6706 struct ixgbe_q_vector *q_vector = ring->q_vector;
6707 union ixgbe_atr_hash_dword input = { .dword = 0 };
6708 union ixgbe_atr_hash_dword common = { .dword = 0 };
6709 union {
6710 unsigned char *network;
6711 struct iphdr *ipv4;
6712 struct ipv6hdr *ipv6;
6713 } hdr;
ee9e0f0b 6714 struct tcphdr *th;
905e4a41 6715 __be16 vlan_id;
c4cf55e5 6716
69830529
AD		 6717 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6718 if (!q_vector)
6719 return;
6720
6721 /* do nothing if sampling is disabled */
6722 if (!ring->atr_sample_rate)
d3ead241 6723 return;
c4cf55e5 6724
69830529 6725 ring->atr_count++;
c4cf55e5 6726
69830529 6727 /* snag network header to get L4 type and address */
fd0db0ed 6728 hdr.network = skb_network_header(first->skb);
69830529
AD		 6729
6730 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6731 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6732 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6733 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6734 hdr.ipv4->protocol != IPPROTO_TCP))
6735 return;
ee9e0f0b 6736
fd0db0ed 6737 th = tcp_hdr(first->skb);
c4cf55e5 6738
66f32a8b
AD		 6739 /* skip this packet since it is invalid or the socket is closing */
6740 if (!th || th->fin)
69830529
AD		 6741 return;
6742
6743 /* sample on all syn packets or once every atr sample count */
6744 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6745 return;
6746
6747 /* reset sample count */
6748 ring->atr_count = 0;
6749
244e27ad 6750 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6751
6752 /*
6753 * src and dst are inverted, think how the receiver sees them
6754 *
6755 * The input is broken into two sections, a non-compressed section
6756 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6757 * is XORed together and stored in the compressed dword.
6758 */
6759 input.formatted.vlan_id = vlan_id;
6760
6761 /*
6762 * since src port and flex bytes occupy the same word XOR them together
6763 * and write the value to source port portion of compressed dword
6764 */
244e27ad 6765 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6766 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6767 else
244e27ad 6768 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6769 common.port.dst ^= th->source;
6770
244e27ad 6771 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6772 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6773 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6774 } else {
6775 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6776 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6777 hdr.ipv6->saddr.s6_addr32[1] ^
6778 hdr.ipv6->saddr.s6_addr32[2] ^
6779 hdr.ipv6->saddr.s6_addr32[3] ^
6780 hdr.ipv6->daddr.s6_addr32[0] ^
6781 hdr.ipv6->daddr.s6_addr32[1] ^
6782 hdr.ipv6->daddr.s6_addr32[2] ^
6783 hdr.ipv6->daddr.s6_addr32[3];
6784 }
c4cf55e5
PWJ		 6785
6786 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6787 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6788 input, common, ring->queue_index);
c4cf55e5
PWJ		 6789}
6790
63544e9c 6791static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6792{
fc77dc3c 6793 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6794 /* Herbert's original patch had:
6795 * smp_mb__after_netif_stop_queue();
6796 * but since that doesn't exist yet, just open code it. */
6797 smp_mb();
6798
6799 /* We need to check again in a case another CPU has just
6800 * made room available. */
7d4987de 6801 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6802 return -EBUSY;
6803
6804 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6805 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6806 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6807 return 0;
6808}
6809
82d4e46e 6810static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6811{
7d4987de 6812 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6813 return 0;
fc77dc3c 6814 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6815}
6816
97488bd1 6817#ifdef IXGBE_FCOE
09a3b1f8
SH		 6818static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6819{
97488bd1
AD		 6820 struct ixgbe_adapter *adapter;
6821 struct ixgbe_ring_feature *f;
6822 int txq;
5e09a105 6823
97488bd1
AD		 6824 /*
6825 * only execute the code below if protocol is FCoE
6826 * or FIP and we have FCoE enabled on the adapter
6827 */
6828 switch (vlan_get_protocol(skb)) {
6829 case __constant_htons(ETH_P_FCOE):
6830 case __constant_htons(ETH_P_FIP):
6831 adapter = netdev_priv(dev);
c087663e 6832
97488bd1
AD		 6833 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6834 break;
6835 default:
6836 return __netdev_pick_tx(dev, skb);
6837 }
c087663e 6838
97488bd1 6839 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6840
97488bd1
AD		 6841 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6842 smp_processor_id();
56075a98 6843
97488bd1
AD		 6844 while (txq >= f->indices)
6845 txq -= f->indices;
c4cf55e5 6846
97488bd1 6847 return txq + f->offset;
09a3b1f8
SH		 6848}
6849
97488bd1 6850#endif
fc77dc3c 6851netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6852 struct ixgbe_adapter *adapter,
6853 struct ixgbe_ring *tx_ring)
9a799d71 6854{
d3d00239 6855 struct ixgbe_tx_buffer *first;
5f715823 6856 int tso;
d3d00239 6857 u32 tx_flags = 0;
a535c30e 6858 unsigned short f;
a535c30e 6859 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6860 __be16 protocol = skb->protocol;
63544e9c 6861 u8 hdr_len = 0;
5e09a105 6862
a535c30e
AD		 6863 /*
6864 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6865 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6866 * + 2 desc gap to keep tail from touching head,
6867 * + 1 desc for context descriptor,
6868 * otherwise try next time
6869 */
a535c30e
AD		 6870 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6871 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 6872
a535c30e
AD		 6873 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6874 tx_ring->tx_stats.tx_busy++;
6875 return NETDEV_TX_BUSY;
6876 }
6877
fd0db0ed
AD		 6878 /* record the location of the first descriptor for this packet */
6879 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6880 first->skb = skb;
091a6246
AD		 6881 first->bytecount = skb->len;
6882 first->gso_segs = 1;
fd0db0ed 6883
66f32a8b 6884 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6885 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6886 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6887 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6888 /* else if it is a SW VLAN check the next protocol and store the tag */
6889 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6890 struct vlan_hdr *vhdr, _vhdr;
6891 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6892 if (!vhdr)
6893 goto out_drop;
6894
6895 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6896 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6897 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6898 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6899 }
6900
aa7bd467
JK		 6901 skb_tx_timestamp(skb);
6902
3a6a4eda
JK		 6903 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6904 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6905 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 6906
6907 /* schedule check for Tx timestamp */
6908 adapter->ptp_tx_skb = skb_get(skb);
6909 adapter->ptp_tx_start = jiffies;
6910 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 6911 }
3a6a4eda 6912
9e0c5648
AD		 6913#ifdef CONFIG_PCI_IOV
6914 /*
6915 * Use the l2switch_enable flag - would be false if the DMA
6916 * Tx switch had been disabled.
6917 */
6918 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 6919 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 6920
6921#endif
32701dc2 6922 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6923 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6924 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6925 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6926 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6927 tx_flags |= (skb->priority & 0x7) <<
6928 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6929 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6930 struct vlan_ethhdr *vhdr;
6931 if (skb_header_cloned(skb) &&
6932 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6933 goto out_drop;
6934 vhdr = (struct vlan_ethhdr *)skb->data;
6935 vhdr->h_vlan_TCI = htons(tx_flags >>
6936 IXGBE_TX_FLAGS_VLAN_SHIFT);
6937 } else {
6938 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6939 }
9a799d71 6940 }
eacd73f7 6941
244e27ad
AD		 6942 /* record initial flags and protocol */
6943 first->tx_flags = tx_flags;
6944 first->protocol = protocol;
6945
eacd73f7 6946#ifdef IXGBE_FCOE
66f32a8b
AD		 6947 /* setup tx offload for FCoE */
6948 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6949 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6950 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6951 if (tso < 0)
6952 goto out_drop;
9a799d71 6953
66f32a8b 6954 goto xmit_fcoe;
eacd73f7 6955 }
9a799d71 6956
66f32a8b 6957#endif /* IXGBE_FCOE */
244e27ad 6958 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6959 if (tso < 0)
897ab156 6960 goto out_drop;
244e27ad
AD		 6961 else if (!tso)
6962 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6963
6964 /* add the ATR filter if ATR is on */
6965 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6966 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6967
6968#ifdef IXGBE_FCOE
6969xmit_fcoe:
6970#endif /* IXGBE_FCOE */
244e27ad 6971 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6972
6973 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6974
6975 return NETDEV_TX_OK;
897ab156
AD		 6976
6977out_drop:
fd0db0ed
AD		 6978 dev_kfree_skb_any(first->skb);
6979 first->skb = NULL;
6980
897ab156 6981 return NETDEV_TX_OK;
9a799d71
AK		 6982}
6983
2a47fa45
JF		 6984static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
6985 struct net_device *netdev,
6986 struct ixgbe_ring *ring)
84418e3b
AD		 6987{
6988 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6989 struct ixgbe_ring *tx_ring;
6990
a50c29dd
AD		 6991 /*
6992 * The minimum packet size for olinfo paylen is 17 so pad the skb
6993 * in order to meet this minimum size requirement.
6994 */
f73332fc
SH		 6995 if (unlikely(skb->len < 17)) {
6996 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6997 return NETDEV_TX_OK;
6998 skb->len = 17;
71a49f77 6999 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7000 }
7001
2a47fa45
JF		 7002 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7003
fc77dc3c 7004 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7005}
7006
2a47fa45
JF		 7007static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7008 struct net_device *netdev)
7009{
7010 return __ixgbe_xmit_frame(skb, netdev, NULL);
7011}
7012
9a799d71
AK		 7013/**
7014 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7015 * @netdev: network interface device structure
7016 * @p: pointer to an address structure
7017 *
7018 * Returns 0 on success, negative on failure
7019 **/
7020static int ixgbe_set_mac(struct net_device *netdev, void *p)
7021{
7022 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7023 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7024 struct sockaddr *addr = p;
7025
7026 if (!is_valid_ether_addr(addr->sa_data))
7027 return -EADDRNOTAVAIL;
7028
7029 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7030 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7031
1d9c0bfd 7032 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7033
7034 return 0;
7035}
7036
6b73e10d
BH		 7037static int
7038ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7039{
7040 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7041 struct ixgbe_hw *hw = &adapter->hw;
7042 u16 value;
7043 int rc;
7044
7045 if (prtad != hw->phy.mdio.prtad)
7046 return -EINVAL;
7047 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7048 if (!rc)
7049 rc = value;
7050 return rc;
7051}
7052
7053static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7054 u16 addr, u16 value)
7055{
7056 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7057 struct ixgbe_hw *hw = &adapter->hw;
7058
7059 if (prtad != hw->phy.mdio.prtad)
7060 return -EINVAL;
7061 return hw->phy.ops.write_reg(hw, addr, devad, value);
7062}
7063
7064static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7065{
7066 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7067
3a6a4eda 7068 switch (cmd) {
3a6a4eda
JK		 7069 case SIOCSHWTSTAMP:
7070 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 7071 default:
7072 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7073 }
6b73e10d
BH		 7074}
7075
0365e6e4
PW		 7076/**
7077 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7078 * netdev->dev_addrs
0365e6e4
PW		 7079 * @netdev: network interface device structure
7080 *
7081 * Returns non-zero on failure
7082 **/
7083static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7084{
7085 int err = 0;
7086 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7087 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7088
7fa7c9dc 7089 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7090 rtnl_lock();
7fa7c9dc 7091 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7092 rtnl_unlock();
7fa7c9dc
AD		 7093
7094 /* update SAN MAC vmdq pool selection */
7095 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7096 }
7097 return err;
7098}
7099
7100/**
7101 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7102 * netdev->dev_addrs
0365e6e4
PW		 7103 * @netdev: network interface device structure
7104 *
7105 * Returns non-zero on failure
7106 **/
7107static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7108{
7109 int err = 0;
7110 struct ixgbe_adapter *adapter = netdev_priv(dev);
7111 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7112
7113 if (is_valid_ether_addr(mac->san_addr)) {
7114 rtnl_lock();
7115 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7116 rtnl_unlock();
7117 }
7118 return err;
7119}
7120
9a799d71
AK		 7121#ifdef CONFIG_NET_POLL_CONTROLLER
7122/*
7123 * Polling 'interrupt' - used by things like netconsole to send skbs
7124 * without having to re-enable interrupts. It's not called while
7125 * the interrupt routine is executing.
7126 */
7127static void ixgbe_netpoll(struct net_device *netdev)
7128{
7129 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7130 int i;
9a799d71 7131
1a647bd2
AD		 7132 /* if interface is down do nothing */
7133 if (test_bit(__IXGBE_DOWN, &adapter->state))
7134 return;
7135
9a799d71 7136 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7137 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7138 for (i = 0; i < adapter->num_q_vectors; i++)
7139 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7140 } else {
7141 ixgbe_intr(adapter->pdev->irq, netdev);
7142 }
9a799d71 7143 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7144}
9a799d71 7145
581330ba 7146#endif
de1036b1
ED		 7147static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7148 struct rtnl_link_stats64 *stats)
7149{
7150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7151 int i;
7152
1a51502b 7153 rcu_read_lock();
de1036b1 7154 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7155 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7156 u64 bytes, packets;
7157 unsigned int start;
7158
1a51502b
ED		 7159 if (ring) {
7160 do {
7161 start = u64_stats_fetch_begin_bh(&ring->syncp);
7162 packets = ring->stats.packets;
7163 bytes = ring->stats.bytes;
7164 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7165 stats->rx_packets += packets;
7166 stats->rx_bytes += bytes;
7167 }
de1036b1 7168 }
1ac9ad13
ED		 7169
7170 for (i = 0; i < adapter->num_tx_queues; i++) {
7171 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7172 u64 bytes, packets;
7173 unsigned int start;
7174
7175 if (ring) {
7176 do {
7177 start = u64_stats_fetch_begin_bh(&ring->syncp);
7178 packets = ring->stats.packets;
7179 bytes = ring->stats.bytes;
7180 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7181 stats->tx_packets += packets;
7182 stats->tx_bytes += bytes;
7183 }
7184 }
1a51502b 7185 rcu_read_unlock();
de1036b1
ED		 7186 /* following stats updated by ixgbe_watchdog_task() */
7187 stats->multicast = netdev->stats.multicast;
7188 stats->rx_errors = netdev->stats.rx_errors;
7189 stats->rx_length_errors = netdev->stats.rx_length_errors;
7190 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7191 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7192 return stats;
7193}
7194
8af3c33f 7195#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7196/**
7197 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7198 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7199 * @tc: number of traffic classes currently enabled
7200 *
7201 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7202 * 802.1Q priority maps to a packet buffer that exists.
7203 */
7204static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7205{
7206 struct ixgbe_hw *hw = &adapter->hw;
7207 u32 reg, rsave;
7208 int i;
7209
7210 /* 82598 have a static priority to TC mapping that can not
7211 * be changed so no validation is needed.
7212 */
7213 if (hw->mac.type == ixgbe_mac_82598EB)
7214 return;
7215
7216 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7217 rsave = reg;
7218
7219 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7220 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7221
7222 /* If up2tc is out of bounds default to zero */
7223 if (up2tc > tc)
7224 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7225 }
7226
7227 if (reg != rsave)
7228 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7229
7230 return;
7231}
7232
02debdc9
AD		 7233/**
7234 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7235 * @adapter: Pointer to adapter struct
7236 *
7237 * Populate the netdev user priority to tc map
7238 */
7239static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7240{
7241 struct net_device *dev = adapter->netdev;
7242 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7243 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7244 u8 prio;
7245
7246 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7247 u8 tc = 0;
7248
7249 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7250 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7251 else if (ets)
7252 tc = ets->prio_tc[prio];
7253
7254 netdev_set_prio_tc_map(dev, prio, tc);
7255 }
7256}
7257
cca73c59 7258#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7259/**
7260 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7261 *
7262 * @netdev: net device to configure
7263 * @tc: number of traffic classes to enable
7264 */
7265int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7266{
8b1c0b24
JF		 7267 struct ixgbe_adapter *adapter = netdev_priv(dev);
7268 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7269 bool pools;
8b1c0b24 7270
8b1c0b24 7271 /* Hardware supports up to 8 traffic classes */
4de2a022 7272 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7273 (hw->mac.type == ixgbe_mac_82598EB &&
7274 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7275 return -EINVAL;
7276
2a47fa45
JF		 7277 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7278 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7279 return -EBUSY;
7280
8b1c0b24 7281 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7282 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7283 * hardware is not flexible enough to do this dynamically.
7284 */
7285 if (netif_running(dev))
7286 ixgbe_close(dev);
7287 ixgbe_clear_interrupt_scheme(adapter);
7288
cca73c59 7289#ifdef CONFIG_IXGBE_DCB
e7589eab 7290 if (tc) {
8b1c0b24 7291 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7292 ixgbe_set_prio_tc_map(adapter);
7293
e7589eab 7294 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7295
943561d3
AD		 7296 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7297 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7298 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7299 }
e7589eab 7300 } else {
8b1c0b24 7301 netdev_reset_tc(dev);
02debdc9 7302
943561d3
AD		 7303 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7304 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7305
7306 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7307
7308 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7309 adapter->dcb_cfg.pfc_mode_enable = false;
7310 }
7311
8b1c0b24 7312 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7313
7314#endif /* CONFIG_IXGBE_DCB */
7315 ixgbe_init_interrupt_scheme(adapter);
7316
8b1c0b24 7317 if (netif_running(dev))
cca73c59 7318 return ixgbe_open(dev);
8b1c0b24
JF		 7319
7320 return 0;
7321}
de1036b1 7322
da36b647
GR		 7323#ifdef CONFIG_PCI_IOV
7324void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7325{
7326 struct net_device *netdev = adapter->netdev;
7327
7328 rtnl_lock();
da36b647 7329 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7330 rtnl_unlock();
7331}
7332
7333#endif
082757af
DS		 7334void ixgbe_do_reset(struct net_device *netdev)
7335{
7336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7337
7338 if (netif_running(netdev))
7339 ixgbe_reinit_locked(adapter);
7340 else
7341 ixgbe_reset(adapter);
7342}
7343
c8f44aff 7344static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7345 netdev_features_t features)
082757af
DS		 7346{
7347 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7348
082757af 7349 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7350 if (!(features & NETIF_F_RXCSUM))
7351 features &= ~NETIF_F_LRO;
082757af 7352
567d2de2
AD		 7353 /* Turn off LRO if not RSC capable */
7354 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7355 features &= ~NETIF_F_LRO;
8e2813f5 7356
567d2de2 7357 return features;
082757af
DS		 7358}
7359
c8f44aff 7360static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7361 netdev_features_t features)
082757af
DS		 7362{
7363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7364 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7365 bool need_reset = false;
7366
082757af 7367 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7368 if (!(features & NETIF_F_LRO)) {
7369 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7370 need_reset = true;
567d2de2
AD		 7371 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7372 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7373 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7374 if (adapter->rx_itr_setting == 1 ||
7375 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7376 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7377 need_reset = true;
7378 } else if ((changed ^ features) & NETIF_F_LRO) {
7379 e_info(probe, "rx-usecs set too low, "
7380 "disabling RSC\n");
082757af
DS		 7381 }
7382 }
7383
7384 /*
7385 * Check if Flow Director n-tuple support was enabled or disabled. If
7386 * the state changed, we need to reset.
7387 */
39cb681b
AD		 7388 switch (features & NETIF_F_NTUPLE) {
7389 case NETIF_F_NTUPLE:
567d2de2 7390 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7391 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7392 need_reset = true;
7393
567d2de2
AD		 7394 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7395 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7396 break;
7397 default:
7398 /* turn off perfect filters, enable ATR and reset */
7399 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7400 need_reset = true;
7401
7402 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7403
7404 /* We cannot enable ATR if SR-IOV is enabled */
7405 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7406 break;
7407
7408 /* We cannot enable ATR if we have 2 or more traffic classes */
7409 if (netdev_get_num_tc(netdev) > 1)
7410 break;
7411
7412 /* We cannot enable ATR if RSS is disabled */
7413 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7414 break;
7415
7416 /* A sample rate of 0 indicates ATR disabled */
7417 if (!adapter->atr_sample_rate)
7418 break;
7419
7420 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7421 break;
082757af
DS		 7422 }
7423
f646968f 7424 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7425 ixgbe_vlan_strip_enable(adapter);
7426 else
7427 ixgbe_vlan_strip_disable(adapter);
7428
3f2d1c0f
BG		 7429 if (changed & NETIF_F_RXALL)
7430 need_reset = true;
7431
567d2de2 7432 netdev->features = features;
082757af
DS		 7433 if (need_reset)
7434 ixgbe_do_reset(netdev);
7435
7436 return 0;
082757af
DS		 7437}
7438
edc7d573 7439static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7440 struct net_device *dev,
6b6e2725 7441 const unsigned char *addr,
0f4b0add
JF		 7442 u16 flags)
7443{
7444 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7445 int err;
7446
7447 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7448 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7449
b1ac1ef7
JF		 7450 /* Hardware does not support aging addresses so if a
7451 * ndm_state is given only allow permanent addresses
7452 */
7453 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7454 pr_info("%s: FDB only supports static addresses\n",
7455 ixgbe_driver_name);
7456 return -EINVAL;
7457 }
7458
46acc460 7459 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7460 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7461
7462 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7463 err = dev_uc_add_excl(dev, addr);
0f4b0add 7464 else
95447461
JF		 7465 err = -ENOMEM;
7466 } else if (is_multicast_ether_addr(addr)) {
7467 err = dev_mc_add_excl(dev, addr);
7468 } else {
7469 err = -EINVAL;
0f4b0add
JF		 7470 }
7471
7472 /* Only return duplicate errors if NLM_F_EXCL is set */
7473 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7474 err = 0;
7475
7476 return err;
7477}
7478
815cccbf
JF		 7479static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7480 struct nlmsghdr *nlh)
7481{
7482 struct ixgbe_adapter *adapter = netdev_priv(dev);
7483 struct nlattr *attr, *br_spec;
7484 int rem;
7485
7486 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7487 return -EOPNOTSUPP;
7488
7489 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7490
7491 nla_for_each_nested(attr, br_spec, rem) {
7492 __u16 mode;
7493 u32 reg = 0;
7494
7495 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7496 continue;
7497
7498 mode = nla_get_u16(attr);
9b735984 7499 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7500 reg = 0;
9b735984
GR		 7501 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7502 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7503 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7504 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7505 } else
815cccbf
JF		 7506 return -EINVAL;
7507
7508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7509
7510 e_info(drv, "enabling bridge mode: %s\n",
7511 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7512 }
7513
7514 return 0;
7515}
7516
7517static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7518 struct net_device *dev,
7519 u32 filter_mask)
815cccbf
JF		 7520{
7521 struct ixgbe_adapter *adapter = netdev_priv(dev);
7522 u16 mode;
7523
7524 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7525 return 0;
7526
9b735984 7527 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7528 mode = BRIDGE_MODE_VEB;
7529 else
7530 mode = BRIDGE_MODE_VEPA;
7531
7532 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7533}
7534
2a47fa45
JF		 7535static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7536{
7537 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7538 struct ixgbe_adapter *adapter = netdev_priv(pdev);
7539 int pool, err;
7540
219354d4
JF		 7541#ifdef CONFIG_RPS
7542 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7543 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7544 vdev->name);
7545 return ERR_PTR(-EINVAL);
7546 }
7547#endif
2a47fa45 7548 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7549 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7550 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7551 netdev_info(pdev,
7552 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7553 pdev->name);
7554 return ERR_PTR(-EINVAL);
7555 }
7556
7557 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7558 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7559 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7560 return ERR_PTR(-EBUSY);
7561
7562 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7563 if (!fwd_adapter)
7564 return ERR_PTR(-ENOMEM);
7565
7566 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7567 adapter->num_rx_pools++;
7568 set_bit(pool, &adapter->fwd_bitmask);
7569
7570 /* Enable VMDq flag so device will be set in VM mode */
7571 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7572 adapter->ring_feature[RING_F_VMDQ].limit = adapter->num_rx_pools;
219354d4 7573 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7574
7575 /* Force reinit of ring allocation with VMDQ enabled */
7576 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7577 if (err)
7578 goto fwd_add_err;
7579 fwd_adapter->pool = pool;
7580 fwd_adapter->real_adapter = adapter;
7581 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7582 if (err)
7583 goto fwd_add_err;
7584 netif_tx_start_all_queues(vdev);
7585 return fwd_adapter;
7586fwd_add_err:
7587 /* unwind counter and free adapter struct */
7588 netdev_info(pdev,
7589 "%s: dfwd hardware acceleration failed\n", vdev->name);
7590 clear_bit(pool, &adapter->fwd_bitmask);
7591 adapter->num_rx_pools--;
7592 kfree(fwd_adapter);
7593 return ERR_PTR(err);
7594}
7595
7596static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7597{
7598 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7599 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7600
7601 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7602 adapter->num_rx_pools--;
7603
7604 adapter->ring_feature[RING_F_VMDQ].limit = adapter->num_rx_pools;
7605 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7606 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7607 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7608 fwd_adapter->pool, adapter->num_rx_pools,
7609 fwd_adapter->rx_base_queue,
7610 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7611 adapter->fwd_bitmask);
7612 kfree(fwd_adapter);
7613}
7614
7615static netdev_tx_t ixgbe_fwd_xmit(struct sk_buff *skb,
7616 struct net_device *dev,
7617 void *priv)
7618{
7619 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7620 unsigned int queue;
7621 struct ixgbe_ring *tx_ring;
7622
7623 queue = skb->queue_mapping + fwd_adapter->tx_base_queue;
7624 tx_ring = fwd_adapter->real_adapter->tx_ring[queue];
7625
7626 return __ixgbe_xmit_frame(skb, dev, tx_ring);
7627}
7628
0edc3527 7629static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7630 .ndo_open = ixgbe_open,
0edc3527 7631 .ndo_stop = ixgbe_close,
00829823 7632 .ndo_start_xmit = ixgbe_xmit_frame,
97488bd1 7633#ifdef IXGBE_FCOE
09a3b1f8 7634 .ndo_select_queue = ixgbe_select_queue,
97488bd1 7635#endif
581330ba 7636 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7637 .ndo_validate_addr = eth_validate_addr,
7638 .ndo_set_mac_address = ixgbe_set_mac,
7639 .ndo_change_mtu = ixgbe_change_mtu,
7640 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7641 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7642 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7643 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7644 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7645 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7646 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7647 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7648 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7649 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7650#ifdef CONFIG_IXGBE_DCB
24095aa3 7651 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7652#endif
0edc3527
SH		 7653#ifdef CONFIG_NET_POLL_CONTROLLER
7654 .ndo_poll_controller = ixgbe_netpoll,
7655#endif
e0d1095a 7656#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7657 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7658#endif
332d4a7d
YZ		 7659#ifdef IXGBE_FCOE
7660 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7661 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7662 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7663 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7664 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7665 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7666 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7667#endif /* IXGBE_FCOE */
082757af
DS		 7668 .ndo_set_features = ixgbe_set_features,
7669 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7670 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7671 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7672 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7673 .ndo_dfwd_add_station = ixgbe_fwd_add,
7674 .ndo_dfwd_del_station = ixgbe_fwd_del,
7675 .ndo_dfwd_start_xmit = ixgbe_fwd_xmit,
0edc3527
SH		 7676};
7677
e027d1ae
JK		 7678/**
7679 * ixgbe_enumerate_functions - Get the number of ports this device has
7680 * @adapter: adapter structure
7681 *
7682 * This function enumerates the phsyical functions co-located on a single slot,
7683 * in order to determine how many ports a device has. This is most useful in
7684 * determining the required GT/s of PCIe bandwidth necessary for optimal
7685 * performance.
7686 **/
7687static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7688{
e027d1ae
JK		 7689 struct list_head *entry;
7690 int physfns = 0;
7691
f1f96579
JK		 7692 /* Some cards can not use the generic count PCIe functions method,
7693 * because they are behind a parent switch, so we hardcode these with
7694 * the correct number of functions.
e027d1ae 7695 */
f1f96579 7696 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7697 physfns = 4;
f1f96579 7698 } else {
e027d1ae
JK		 7699 list_for_each(entry, &adapter->pdev->bus_list) {
7700 struct pci_dev *pdev =
7701 list_entry(entry, struct pci_dev, bus_list);
7702 /* don't count virtual functions */
7703 if (!pdev->is_virtfn)
7704 physfns++;
7705 }
7706 }
7707
7708 return physfns;
7709}
7710
8e2813f5
JK		 7711/**
7712 * ixgbe_wol_supported - Check whether device supports WoL
7713 * @hw: hw specific details
7714 * @device_id: the device ID
7715 * @subdev_id: the subsystem device ID
7716 *
7717 * This function is used by probe and ethtool to determine
7718 * which devices have WoL support
7719 *
7720 **/
7721int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7722 u16 subdevice_id)
7723{
7724 struct ixgbe_hw *hw = &adapter->hw;
7725 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7726 int is_wol_supported = 0;
7727
7728 switch (device_id) {
7729 case IXGBE_DEV_ID_82599_SFP:
7730 /* Only these subdevices could supports WOL */
7731 switch (subdevice_id) {
7732 case IXGBE_SUBDEV_ID_82599_560FLR:
7733 /* only support first port */
7734 if (hw->bus.func != 0)
7735 break;
5700ff26 7736 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7737 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7738 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7739 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7740 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7741 is_wol_supported = 1;
7742 break;
7743 }
7744 break;
5daebbb0
DS		 7745 case IXGBE_DEV_ID_82599EN_SFP:
7746 /* Only this subdevice supports WOL */
7747 switch (subdevice_id) {
7748 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7749 is_wol_supported = 1;
7750 break;
7751 }
7752 break;
8e2813f5
JK		 7753 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7754 /* All except this subdevice support WOL */
7755 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7756 is_wol_supported = 1;
7757 break;
7758 case IXGBE_DEV_ID_82599_KX4:
7759 is_wol_supported = 1;
7760 break;
7761 case IXGBE_DEV_ID_X540T:
df376f0d 7762 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7763 /* check eeprom to see if enabled wol */
7764 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7765 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7766 (hw->bus.func == 0))) {
7767 is_wol_supported = 1;
7768 }
7769 break;
7770 }
7771
7772 return is_wol_supported;
7773}
7774
9a799d71
AK		 7775/**
7776 * ixgbe_probe - Device Initialization Routine
7777 * @pdev: PCI device information struct
7778 * @ent: entry in ixgbe_pci_tbl
7779 *
7780 * Returns 0 on success, negative on failure
7781 *
7782 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7783 * The OS initialization, configuring of the adapter private structure,
7784 * and a hardware reset occur.
7785 **/
1dd06ae8 7786static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7787{
7788 struct net_device *netdev;
7789 struct ixgbe_adapter *adapter = NULL;
7790 struct ixgbe_hw *hw;
7791 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7792 static int cards_found;
e027d1ae 7793 int i, err, pci_using_dac, expected_gts;
d3cb9869 7794 unsigned int indices = MAX_TX_QUEUES;
289700db 7795 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7796#ifdef IXGBE_FCOE
7797 u16 device_caps;
7798#endif
289700db 7799 u32 eec;
9a799d71 7800
bded64a7
AG		 7801 /* Catch broken hardware that put the wrong VF device ID in
7802 * the PCIe SR-IOV capability.
7803 */
7804 if (pdev->is_virtfn) {
7805 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7806 pci_name(pdev), pdev->vendor, pdev->device);
7807 return -EINVAL;
7808 }
7809
9ce77666 7810 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7811 if (err)
7812 return err;
7813
1b507730
NN		 7814 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7815 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7816 pci_using_dac = 1;
7817 } else {
1b507730 7818 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7819 if (err) {
1b507730
NN		 7820 err = dma_set_coherent_mask(&pdev->dev,
7821 DMA_BIT_MASK(32));
9a799d71 7822 if (err) {
b8bc0421
DC		 7823 dev_err(&pdev->dev,
7824 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7825 goto err_dma;
7826 }
7827 }
7828 pci_using_dac = 0;
7829 }
7830
9ce77666 7831 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7832 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7833 if (err) {
b8bc0421
DC		 7834 dev_err(&pdev->dev,
7835 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7836 goto err_pci_reg;
7837 }
7838
19d5afd4 7839 pci_enable_pcie_error_reporting(pdev);
6fabd715 7840
9a799d71 7841 pci_set_master(pdev);
fb3b27bc 7842 pci_save_state(pdev);
9a799d71 7843
d3cb9869 7844 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7845#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7846 /* 8 TC w/ 4 queues per TC */
7847 indices = 4 * MAX_TRAFFIC_CLASS;
7848#else
7849 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7850#endif
d3cb9869 7851 }
e901acd6 7852
c85a2618 7853 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7854 if (!netdev) {
7855 err = -ENOMEM;
7856 goto err_alloc_etherdev;
7857 }
7858
9a799d71
AK		 7859 SET_NETDEV_DEV(netdev, &pdev->dev);
7860
9a799d71 7861 adapter = netdev_priv(netdev);
c60fbb00 7862 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7863
7864 adapter->netdev = netdev;
7865 adapter->pdev = pdev;
7866 hw = &adapter->hw;
7867 hw->back = adapter;
b3f4d599 7868 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7869
05857980 7870 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7871 pci_resource_len(pdev, 0));
9a799d71
AK		 7872 if (!hw->hw_addr) {
7873 err = -EIO;
7874 goto err_ioremap;
7875 }
7876
0edc3527 7877 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7878 ixgbe_set_ethtool_ops(netdev);
9a799d71 7879 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7880 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7881
9a799d71
AK		 7882 adapter->bd_number = cards_found;
7883
9a799d71
AK		 7884 /* Setup hw api */
7885 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7886 hw->mac.type = ii->mac;
9a799d71 7887
c44ade9e
JB		 7888 /* EEPROM */
7889 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7890 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7891 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7892 if (!(eec & (1 << 8)))
7893 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7894
7895 /* PHY */
7896 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7897 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7898 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7899 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7900 hw->phy.mdio.mmds = 0;
7901 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7902 hw->phy.mdio.dev = netdev;
7903 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7904 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7905
8ca783ab 7906 ii->get_invariants(hw);
9a799d71
AK		 7907
7908 /* setup the private structure */
7909 err = ixgbe_sw_init(adapter);
7910 if (err)
7911 goto err_sw_init;
7912
0b2679d6
DS		 7913 /* Cache if MNG FW is up so we don't have to read the REG later */
7914 if (hw->mac.ops.mng_fw_enabled)
7915 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7916
e86bff0e 7917 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7918 switch (adapter->hw.mac.type) {
7919 case ixgbe_mac_82599EB:
7920 case ixgbe_mac_X540:
e86bff0e 7921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7922 break;
7923 default:
7924 break;
7925 }
e86bff0e 7926
bf069c97
DS		 7927 /*
7928 * If there is a fan on this device and it has failed log the
7929 * failure.
7930 */
7931 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7932 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7933 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7934 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7935 }
7936
8ef78adc
PWJ		 7937 if (allow_unsupported_sfp)
7938 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7939
c44ade9e 7940 /* reset_hw fills in the perm_addr as well */
119fc60a 7941 hw->phy.reset_if_overtemp = true;
c44ade9e 7942 err = hw->mac.ops.reset_hw(hw);
119fc60a 7943 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7944 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7945 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7946 err = 0;
7947 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 7948 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
7949 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 7950 goto err_sw_init;
7951 } else if (err) {
849c4542 7952 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7953 goto err_sw_init;
7954 }
7955
99d74487 7956#ifdef CONFIG_PCI_IOV
60a1a680
GR		 7957 /* SR-IOV not supported on the 82598 */
7958 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7959 goto skip_sriov;
7960 /* Mailbox */
7961 ixgbe_init_mbx_params_pf(hw);
7962 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7963 ixgbe_enable_sriov(adapter);
43dc4e01 7964 pci_sriov_set_totalvfs(pdev, 63);
60a1a680 7965skip_sriov:
1cdd1ec8 7966
99d74487 7967#endif
396e799c 7968 netdev->features = NETIF_F_SG |
e8e9f696 7969 NETIF_F_IP_CSUM |
082757af 7970 NETIF_F_IPV6_CSUM |
f646968f
PM		 7971 NETIF_F_HW_VLAN_CTAG_TX |
7972 NETIF_F_HW_VLAN_CTAG_RX |
7973 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 7974 NETIF_F_TSO |
7975 NETIF_F_TSO6 |
082757af 7976 NETIF_F_RXHASH |
2a47fa45
JF		 7977 NETIF_F_RXCSUM |
7978 NETIF_F_HW_L2FW_DOFFLOAD;
9a799d71 7979
082757af 7980 netdev->hw_features = netdev->features;
ad31c402 7981
58be7666
DS		 7982 switch (adapter->hw.mac.type) {
7983 case ixgbe_mac_82599EB:
7984 case ixgbe_mac_X540:
45a5ead0 7985 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7986 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7987 NETIF_F_NTUPLE;
58be7666
DS		 7988 break;
7989 default:
7990 break;
7991 }
45a5ead0 7992
3f2d1c0f
BG		 7993 netdev->hw_features |= NETIF_F_RXALL;
7994
ad31c402
JK		 7995 netdev->vlan_features |= NETIF_F_TSO;
7996 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7997 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7998 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7999 netdev->vlan_features |= NETIF_F_SG;
8000
01789349 8001 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8002 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8003
7a6b6f51 8004#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8005 netdev->dcbnl_ops = &dcbnl_ops;
8006#endif
8007
eacd73f7 8008#ifdef IXGBE_FCOE
0d551589 8009 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8010 unsigned int fcoe_l;
8011
eacd73f7
YZ		 8012 if (hw->mac.ops.get_device_caps) {
8013 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8014 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8015 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8016 }
7c8ae65a 8017
d3cb9869
AD		 8018
8019 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8020 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8021
a58915c7
AD		 8022 netdev->features |= NETIF_F_FSO |
8023 NETIF_F_FCOE_CRC;
8024
7c8ae65a
AD		 8025 netdev->vlan_features |= NETIF_F_FSO |
8026 NETIF_F_FCOE_CRC |
8027 NETIF_F_FCOE_MTU;
5e09d7f6 8028 }
eacd73f7 8029#endif /* IXGBE_FCOE */
7b872a55 8030 if (pci_using_dac) {
9a799d71 8031 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8032 netdev->vlan_features |= NETIF_F_HIGHDMA;
8033 }
9a799d71 8034
082757af
DS		 8035 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8036 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8037 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8038 netdev->features |= NETIF_F_LRO;
8039
9a799d71 8040 /* make sure the EEPROM is good */
c44ade9e 8041 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8042 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8043 err = -EIO;
35937c05 8044 goto err_sw_init;
9a799d71
AK		 8045 }
8046
8047 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8048
aaeb6cdf 8049 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8050 e_dev_err("invalid MAC address\n");
9a799d71 8051 err = -EIO;
35937c05 8052 goto err_sw_init;
9a799d71
AK		 8053 }
8054
7086400d 8055 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8056 (unsigned long) adapter);
9a799d71 8057
7086400d
AD		 8058 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8059 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8060
021230d4
AV		 8061 err = ixgbe_init_interrupt_scheme(adapter);
8062 if (err)
8063 goto err_sw_init;
9a799d71 8064
8e2813f5 8065 /* WOL not supported for all devices */
c23f5b6b 8066 adapter->wol = 0;
8e2813f5 8067 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8068 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8069 pdev->subsystem_device);
6b92b0ba 8070 if (hw->wol_enabled)
9417c464 8071 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8072
e8e26350
PW		 8073 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8074
15e5209f
ET		 8075 /* save off EEPROM version number */
8076 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8077 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8078
04f165ef
PW		 8079 /* pick up the PCI bus settings for reporting later */
8080 hw->mac.ops.get_bus_info(hw);
e027d1ae 8081 if (ixgbe_pcie_from_parent(hw))
b8e82001 8082 ixgbe_get_parent_bus_info(adapter);
04f165ef 8083
e027d1ae
JK		 8084 /* calculate the expected PCIe bandwidth required for optimal
8085 * performance. Note that some older parts will never have enough
8086 * bandwidth due to being older generation PCIe parts. We clamp these
8087 * parts to ensure no warning is displayed if it can't be fixed.
8088 */
8089 switch (hw->mac.type) {
8090 case ixgbe_mac_82598EB:
8091 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8092 break;
8093 default:
8094 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8095 break;
0c254d86 8096 }
e027d1ae 8097 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8098
6a2aae5a
JK		 8099 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8100 if (err)
8101 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8102 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8103 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8104 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8105 part_str);
8106 else
8107 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8108 hw->mac.type, hw->phy.type, part_str);
8109
8110 e_dev_info("%pM\n", netdev->dev_addr);
8111
9a799d71 8112 /* reset the hardware with the new settings */
794caeb2 8113 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8114 if (err == IXGBE_ERR_EEPROM_VERSION) {
8115 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8116 e_dev_warn("This device is a pre-production adapter/LOM. "
8117 "Please be aware there may be issues associated "
8118 "with your hardware. If you are experiencing "
8119 "problems please contact your Intel or hardware "
8120 "representative who provided you with this "
8121 "hardware.\n");
794caeb2 8122 }
9a799d71
AK		 8123 strcpy(netdev->name, "eth%d");
8124 err = register_netdev(netdev);
8125 if (err)
8126 goto err_register;
8127
ec74a471
ET		 8128 /* power down the optics for 82599 SFP+ fiber */
8129 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8130 hw->mac.ops.disable_tx_laser(hw);
8131
54386467
JB		 8132 /* carrier off reporting is important to ethtool even BEFORE open */
8133 netif_carrier_off(netdev);
8134
5dd2d332 8135#ifdef CONFIG_IXGBE_DCA
652f093f 8136 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8137 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8138 ixgbe_setup_dca(adapter);
8139 }
8140#endif
1cdd1ec8 8141 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8142 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8143 for (i = 0; i < adapter->num_vfs; i++)
8144 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8145 }
8146
2466dd9c
JK		 8147 /* firmware requires driver version to be 0xFFFFFFFF
8148 * since os does not support feature
8149 */
9612de92 8150 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8151 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8152 0xFF);
9612de92 8153
0365e6e4
PW		 8154 /* add san mac addr to netdev */
8155 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8156
ea81875a 8157 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8158 cards_found++;
3ca8bc6d 8159
1210982b 8160#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8161 if (ixgbe_sysfs_init(adapter))
8162 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8163#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8164
00949167 8165 ixgbe_dbg_adapter_init(adapter);
00949167 8166
0b2679d6
DS		 8167 /* Need link setup for MNG FW, else wait for IXGBE_UP */
8168 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
8169 hw->mac.ops.setup_link(hw,
8170 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8171 true);
8172
9a799d71
AK		 8173 return 0;
8174
8175err_register:
5eba3699 8176 ixgbe_release_hw_control(adapter);
7a921c93 8177 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8178err_sw_init:
99d74487 8179 ixgbe_disable_sriov(adapter);
7086400d 8180 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 8181 iounmap(hw->hw_addr);
8182err_ioremap:
8183 free_netdev(netdev);
8184err_alloc_etherdev:
e8e9f696
JP		 8185 pci_release_selected_regions(pdev,
8186 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8187err_pci_reg:
8188err_dma:
8189 pci_disable_device(pdev);
8190 return err;
8191}
8192
8193/**
8194 * ixgbe_remove - Device Removal Routine
8195 * @pdev: PCI device information struct
8196 *
8197 * ixgbe_remove is called by the PCI subsystem to alert the driver
8198 * that it should release a PCI device. The could be caused by a
8199 * Hot-Plug event, or because the driver is going to be removed from
8200 * memory.
8201 **/
9f9a12f8 8202static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8203{
c60fbb00
AD		 8204 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8205 struct net_device *netdev = adapter->netdev;
9a799d71 8206
00949167 8207 ixgbe_dbg_adapter_exit(adapter);
00949167 8208
9a799d71 8209 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 8210 cancel_work_sync(&adapter->service_task);
9a799d71 8211
3a6a4eda 8212
5dd2d332 8213#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8214 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8215 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8216 dca_remove_requester(&pdev->dev);
8217 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8218 }
8219
8220#endif
1210982b 8221#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8222 ixgbe_sysfs_exit(adapter);
1210982b 8223#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8224
0365e6e4
PW		 8225 /* remove the added san mac */
8226 ixgbe_del_sanmac_netdev(netdev);
8227
c4900be0
DS		 8228 if (netdev->reg_state == NETREG_REGISTERED)
8229 unregister_netdev(netdev);
9a799d71 8230
da36b647
GR		 8231#ifdef CONFIG_PCI_IOV
8232 /*
8233 * Only disable SR-IOV on unload if the user specified the now
8234 * deprecated max_vfs module parameter.
8235 */
8236 if (max_vfs)
8237 ixgbe_disable_sriov(adapter);
8238#endif
7a921c93 8239 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8240
021230d4 8241 ixgbe_release_hw_control(adapter);
9a799d71 8242
2b1588c3
AD		 8243#ifdef CONFIG_DCB
8244 kfree(adapter->ixgbe_ieee_pfc);
8245 kfree(adapter->ixgbe_ieee_ets);
8246
8247#endif
9a799d71 8248 iounmap(adapter->hw.hw_addr);
9ce77666 8249 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8250 IORESOURCE_MEM));
9a799d71 8251
849c4542 8252 e_dev_info("complete\n");
021230d4 8253
9a799d71
AK		 8254 free_netdev(netdev);
8255
19d5afd4 8256 pci_disable_pcie_error_reporting(pdev);
6fabd715 8257
9a799d71
AK		 8258 pci_disable_device(pdev);
8259}
8260
8261/**
8262 * ixgbe_io_error_detected - called when PCI error is detected
8263 * @pdev: Pointer to PCI device
8264 * @state: The current pci connection state
8265 *
8266 * This function is called after a PCI bus error affecting
8267 * this device has been detected.
8268 */
8269static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8270 pci_channel_state_t state)
9a799d71 8271{
c60fbb00
AD		 8272 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8273 struct net_device *netdev = adapter->netdev;
9a799d71 8274
83c61fa9
GR		 8275#ifdef CONFIG_PCI_IOV
8276 struct pci_dev *bdev, *vfdev;
8277 u32 dw0, dw1, dw2, dw3;
8278 int vf, pos;
8279 u16 req_id, pf_func;
8280
8281 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8282 adapter->num_vfs == 0)
8283 goto skip_bad_vf_detection;
8284
8285 bdev = pdev->bus->self;
62f87c0e 8286 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8287 bdev = bdev->bus->self;
8288
8289 if (!bdev)
8290 goto skip_bad_vf_detection;
8291
8292 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8293 if (!pos)
8294 goto skip_bad_vf_detection;
8295
8296 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8297 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8298 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8299 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8300
8301 req_id = dw1 >> 16;
8302 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8303 if (!(req_id & 0x0080))
8304 goto skip_bad_vf_detection;
8305
8306 pf_func = req_id & 0x01;
8307 if ((pf_func & 1) == (pdev->devfn & 1)) {
8308 unsigned int device_id;
8309
8310 vf = (req_id & 0x7F) >> 1;
8311 e_dev_err("VF %d has caused a PCIe error\n", vf);
8312 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8313 "%8.8x\tdw3: %8.8x\n",
8314 dw0, dw1, dw2, dw3);
8315 switch (adapter->hw.mac.type) {
8316 case ixgbe_mac_82599EB:
8317 device_id = IXGBE_82599_VF_DEVICE_ID;
8318 break;
8319 case ixgbe_mac_X540:
8320 device_id = IXGBE_X540_VF_DEVICE_ID;
8321 break;
8322 default:
8323 device_id = 0;
8324 break;
8325 }
8326
8327 /* Find the pci device of the offending VF */
36e90319 8328 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8329 while (vfdev) {
8330 if (vfdev->devfn == (req_id & 0xFF))
8331 break;
36e90319 8332 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8333 device_id, vfdev);
8334 }
8335 /*
8336 * There's a slim chance the VF could have been hot plugged,
8337 * so if it is no longer present we don't need to issue the
8338 * VFLR. Just clean up the AER in that case.
8339 */
8340 if (vfdev) {
8341 e_dev_err("Issuing VFLR to VF %d\n", vf);
8342 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8343 /* Free device reference count */
8344 pci_dev_put(vfdev);
83c61fa9
GR		 8345 }
8346
8347 pci_cleanup_aer_uncorrect_error_status(pdev);
8348 }
8349
8350 /*
8351 * Even though the error may have occurred on the other port
8352 * we still need to increment the vf error reference count for
8353 * both ports because the I/O resume function will be called
8354 * for both of them.
8355 */
8356 adapter->vferr_refcount++;
8357
8358 return PCI_ERS_RESULT_RECOVERED;
8359
8360skip_bad_vf_detection:
8361#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8362 netif_device_detach(netdev);
8363
3044b8d1
BL		 8364 if (state == pci_channel_io_perm_failure)
8365 return PCI_ERS_RESULT_DISCONNECT;
8366
9a799d71
AK		 8367 if (netif_running(netdev))
8368 ixgbe_down(adapter);
8369 pci_disable_device(pdev);
8370
b4617240 8371 /* Request a slot reset. */
9a799d71
AK		 8372 return PCI_ERS_RESULT_NEED_RESET;
8373}
8374
8375/**
8376 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8377 * @pdev: Pointer to PCI device
8378 *
8379 * Restart the card from scratch, as if from a cold-boot.
8380 */
8381static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8382{
c60fbb00 8383 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8384 pci_ers_result_t result;
8385 int err;
9a799d71 8386
9ce77666 8387 if (pci_enable_device_mem(pdev)) {
396e799c 8388 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8389 result = PCI_ERS_RESULT_DISCONNECT;
8390 } else {
8391 pci_set_master(pdev);
8392 pci_restore_state(pdev);
c0e1f68b 8393 pci_save_state(pdev);
9a799d71 8394
dd4d8ca6 8395 pci_wake_from_d3(pdev, false);
9a799d71 8396
6fabd715 8397 ixgbe_reset(adapter);
88512539 8398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8399 result = PCI_ERS_RESULT_RECOVERED;
8400 }
8401
8402 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8403 if (err) {
849c4542
ET		 8404 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8405 "failed 0x%0x\n", err);
6fabd715
PWJ		 8406 /* non-fatal, continue */
8407 }
9a799d71 8408
6fabd715 8409 return result;
9a799d71
AK		 8410}
8411
8412/**
8413 * ixgbe_io_resume - called when traffic can start flowing again.
8414 * @pdev: Pointer to PCI device
8415 *
8416 * This callback is called when the error recovery driver tells us that
8417 * its OK to resume normal operation.
8418 */
8419static void ixgbe_io_resume(struct pci_dev *pdev)
8420{
c60fbb00
AD		 8421 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8422 struct net_device *netdev = adapter->netdev;
9a799d71 8423
83c61fa9
GR		 8424#ifdef CONFIG_PCI_IOV
8425 if (adapter->vferr_refcount) {
8426 e_info(drv, "Resuming after VF err\n");
8427 adapter->vferr_refcount--;
8428 return;
8429 }
8430
8431#endif
c7ccde0f
AD		 8432 if (netif_running(netdev))
8433 ixgbe_up(adapter);
9a799d71
AK		 8434
8435 netif_device_attach(netdev);
9a799d71
AK		 8436}
8437
3646f0e5 8438static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8439 .error_detected = ixgbe_io_error_detected,
8440 .slot_reset = ixgbe_io_slot_reset,
8441 .resume = ixgbe_io_resume,
8442};
8443
8444static struct pci_driver ixgbe_driver = {
8445 .name = ixgbe_driver_name,
8446 .id_table = ixgbe_pci_tbl,
8447 .probe = ixgbe_probe,
9f9a12f8 8448 .remove = ixgbe_remove,
9a799d71
AK		 8449#ifdef CONFIG_PM
8450 .suspend = ixgbe_suspend,
8451 .resume = ixgbe_resume,
8452#endif
8453 .shutdown = ixgbe_shutdown,
da36b647 8454 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8455 .err_handler = &ixgbe_err_handler
8456};
8457
8458/**
8459 * ixgbe_init_module - Driver Registration Routine
8460 *
8461 * ixgbe_init_module is the first routine called when the driver is
8462 * loaded. All it does is register with the PCI subsystem.
8463 **/
8464static int __init ixgbe_init_module(void)
8465{
8466 int ret;
c7689578 8467 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8468 pr_info("%s\n", ixgbe_copyright);
9a799d71 8469
00949167 8470 ixgbe_dbg_init();
00949167 8471
f01fc1a8
JK		 8472 ret = pci_register_driver(&ixgbe_driver);
8473 if (ret) {
f01fc1a8 8474 ixgbe_dbg_exit();
f01fc1a8
JK		 8475 return ret;
8476 }
8477
5dd2d332 8478#ifdef CONFIG_IXGBE_DCA
bd0362dd 8479 dca_register_notify(&dca_notifier);
bd0362dd 8480#endif
5dd2d332 8481
f01fc1a8 8482 return 0;
9a799d71 8483}
b4617240 8484
9a799d71
AK		 8485module_init(ixgbe_init_module);
8486
8487/**
8488 * ixgbe_exit_module - Driver Exit Cleanup Routine
8489 *
8490 * ixgbe_exit_module is called just before the driver is removed
8491 * from memory.
8492 **/
8493static void __exit ixgbe_exit_module(void)
8494{
5dd2d332 8495#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8496 dca_unregister_notify(&dca_notifier);
8497#endif
9a799d71 8498 pci_unregister_driver(&ixgbe_driver);
00949167 8499
00949167 8500 ixgbe_dbg_exit();
00949167 8501
1a51502b 8502 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8503}
bd0362dd 8504
5dd2d332 8505#ifdef CONFIG_IXGBE_DCA
bd0362dd 8506static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8507 void *p)
bd0362dd
JC		 8508{
8509 int ret_val;
8510
8511 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8512 __ixgbe_notify_dca);
bd0362dd
JC		 8513
8514 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8515}
b453368d 8516
5dd2d332 8517#endif /* CONFIG_IXGBE_DCA */
849c4542 8518
9a799d71
AK		 8519module_exit(ixgbe_exit_module);
8520
8521/* ixgbe_main.c */
Linux kernel - Deliverables
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