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ixgbe: count q_vectors instead of MSI-X vectors
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
729739b7 399 dma_unmap_len(tx_buffer, len) != 0)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
729739b7
AD		 402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
dcd79aeb
TI		 406 }
407 }
408
409 /* Print RX Rings Summary */
410rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 412 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
c7689578
JP		 415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
c7689578
JP		 447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
c7689578 453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
c7689578 464 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
c7689578 470 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
f800326d 481 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 482 }
483 }
484
485 if (i == rx_ring->next_to_use)
c7689578 486 pr_cont(" NTU\n");
dcd79aeb 487 else if (i == rx_ring->next_to_clean)
c7689578 488 pr_cont(" NTC\n");
dcd79aeb 489 else
c7689578 490 pr_cont("\n");
dcd79aeb
TI		 491
492 }
493 }
494
495exit:
496 return;
497}
498
5eba3699
AV		 499static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500{
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 507}
508
509static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510{
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 517}
9a799d71 518
49ce9c2c 519/**
e8e26350
PW		 520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 528 u8 queue, u8 msix_vector)
9a799d71
AK		 529{
530 u32 ivar, index;
e8e26350
PW		 531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
b93a2226 544 case ixgbe_mac_X540:
e8e26350
PW		 545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
9a799d71
AK		 567}
568
fe49f04a 569static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 570 u64 qmask)
fe49f04a
AD		 571{
572 u32 mask;
573
bd508178
AD		 574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
fe49f04a
AD		 576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 578 break;
579 case ixgbe_mac_82599EB:
b93a2226 580 case ixgbe_mac_X540:
fe49f04a
AD		 581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 585 break;
586 default:
587 break;
fe49f04a
AD		 588 }
589}
590
729739b7
AD		 591void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 593{
729739b7
AD		 594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
d3d00239 597 dma_unmap_single(ring->dev,
729739b7
AD		 598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
e5a43549 606 }
729739b7
AD		 607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 611}
612
943561d3 613static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 614{
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 617 int i;
943561d3 618 u32 data;
c84d324c 619
943561d3
AD		 620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
c84d324c 623
943561d3
AD		 624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
c84d324c 632
943561d3
AD		 633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
c84d324c 635 return;
943561d3
AD		 636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640}
641
642static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643{
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 655 return;
943561d3 656 }
c84d324c
JF		 657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 663 break;
c84d324c
JF		 664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 666 }
c84d324c
JF		 667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 673 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 677 }
26f23d82
YZ		 678}
679
c84d324c 680static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 681{
7d7ce682 682 return ring->stats.packets;
c84d324c
JF		 683}
684
685static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686{
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
c84d324c
JF		 690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698}
699
700static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701{
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
7d637bcc 707 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 730 }
731
c84d324c 732 return ret;
9a799d71
AK		 733}
734
c83c6cbd
AD		 735/**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740{
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747}
e01c31a5 748
9a799d71
AK		 749/**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 751 * @q_vector: structure containing interrupt and ring information
e01c31a5 752 * @tx_ring: tx ring to clean
9a799d71 753 **/
fe49f04a 754static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 755 struct ixgbe_ring *tx_ring)
9a799d71 756{
fe49f04a 757 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 760 unsigned int total_bytes = 0, total_packets = 0;
59224555 761 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
9a799d71 766
d3d00239 767 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 769 i -= tx_ring->count;
12207e49 770
729739b7 771 do {
d3d00239
AD		 772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
7f83a9e6
AD		 778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
d3d00239
AD		 781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
8ad494b0 784
d3d00239
AD		 785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
8ad494b0 787
091a6246
AD		 788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
3a6a4eda 792#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 793 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
794 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 795#endif
0ede4a60 796
fd0db0ed
AD		 797 /* free the skb */
798 dev_kfree_skb_any(tx_buffer->skb);
799
729739b7
AD		 800 /* unmap skb header data */
801 dma_unmap_single(tx_ring->dev,
802 dma_unmap_addr(tx_buffer, dma),
803 dma_unmap_len(tx_buffer, len),
804 DMA_TO_DEVICE);
805
fd0db0ed
AD		 806 /* clear tx_buffer data */
807 tx_buffer->skb = NULL;
729739b7 808 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 809
729739b7
AD		 810 /* unmap remaining buffers */
811 while (tx_desc != eop_desc) {
d3d00239
AD		 812 tx_buffer++;
813 tx_desc++;
8ad494b0 814 i++;
729739b7
AD		 815 if (unlikely(!i)) {
816 i -= tx_ring->count;
d3d00239 817 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 819 }
e01c31a5 820
729739b7
AD		 821 /* unmap any remaining paged data */
822 if (dma_unmap_len(tx_buffer, len)) {
823 dma_unmap_page(tx_ring->dev,
824 dma_unmap_addr(tx_buffer, dma),
825 dma_unmap_len(tx_buffer, len),
826 DMA_TO_DEVICE);
827 dma_unmap_len_set(tx_buffer, len, 0);
828 }
829 }
830
831 /* move us one more past the eop_desc for start of next pkt */
832 tx_buffer++;
833 tx_desc++;
834 i++;
835 if (unlikely(!i)) {
836 i -= tx_ring->count;
837 tx_buffer = tx_ring->tx_buffer_info;
838 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
839 }
840
841 /* issue prefetch for next Tx descriptor */
842 prefetch(tx_desc);
12207e49 843
729739b7
AD		 844 /* update budget accounting */
845 budget--;
846 } while (likely(budget));
847
848 i += tx_ring->count;
9a799d71 849 tx_ring->next_to_clean = i;
d3d00239 850 u64_stats_update_begin(&tx_ring->syncp);
b953799e 851 tx_ring->stats.bytes += total_bytes;
bd198058 852 tx_ring->stats.packets += total_packets;
d3d00239 853 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 854 q_vector->tx.total_bytes += total_bytes;
855 q_vector->tx.total_packets += total_packets;
b953799e 856
c84d324c
JF		 857 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
858 /* schedule immediate reset if we believe we hung */
859 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 860 e_err(drv, "Detected Tx Unit Hang\n"
861 " Tx Queue <%d>\n"
862 " TDH, TDT <%x>, <%x>\n"
863 " next_to_use <%x>\n"
864 " next_to_clean <%x>\n"
865 "tx_buffer_info[next_to_clean]\n"
866 " time_stamp <%lx>\n"
867 " jiffies <%lx>\n",
868 tx_ring->queue_index,
869 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
870 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 871 tx_ring->next_to_use, i,
872 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 873
874 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
875
876 e_info(probe,
877 "tx hang %d detected on queue %d, resetting adapter\n",
878 adapter->tx_timeout_count + 1, tx_ring->queue_index);
879
b953799e 880 /* schedule immediate reset if we believe we hung */
c83c6cbd 881 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 882
883 /* the adapter is about to reset, no point in enabling stuff */
59224555 884 return true;
b953799e 885 }
9a799d71 886
b2d96e0a
AD		 887 netdev_tx_completed_queue(txring_txq(tx_ring),
888 total_packets, total_bytes);
889
e092be60 890#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 891 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 892 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 893 /* Make sure that anybody stopping the queue after this
894 * sees the new next_to_clean.
895 */
896 smp_mb();
729739b7
AD		 897 if (__netif_subqueue_stopped(tx_ring->netdev,
898 tx_ring->queue_index)
899 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
900 netif_wake_subqueue(tx_ring->netdev,
901 tx_ring->queue_index);
5b7da515 902 ++tx_ring->tx_stats.restart_queue;
30eba97a 903 }
e092be60 904 }
9a799d71 905
59224555 906 return !!budget;
9a799d71
AK		 907}
908
5dd2d332 909#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 910static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
911 struct ixgbe_ring *tx_ring,
33cf09c9 912 int cpu)
bd0362dd 913{
33cf09c9 914 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 915 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
916 u16 reg_offset;
33cf09c9 917
33cf09c9
AD		 918 switch (hw->mac.type) {
919 case ixgbe_mac_82598EB:
bdda1a61 920 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 921 break;
922 case ixgbe_mac_82599EB:
b93a2226 923 case ixgbe_mac_X540:
bdda1a61
AD		 924 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
925 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 926 break;
927 default:
bdda1a61
AD		 928 /* for unknown hardware do not write register */
929 return;
bd0362dd 930 }
bdda1a61
AD		 931
932 /*
933 * We can enable relaxed ordering for reads, but not writes when
934 * DCA is enabled. This is due to a known issue in some chipsets
935 * which will cause the DCA tag to be cleared.
936 */
937 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
938 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
939 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940
941 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 942}
943
bdda1a61
AD		 944static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *rx_ring,
33cf09c9 946 int cpu)
bd0362dd 947{
33cf09c9 948 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 949 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
950 u8 reg_idx = rx_ring->reg_idx;
951
33cf09c9
AD		 952
953 switch (hw->mac.type) {
33cf09c9 954 case ixgbe_mac_82599EB:
b93a2226 955 case ixgbe_mac_X540:
bdda1a61 956 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 957 break;
958 default:
959 break;
960 }
bdda1a61
AD		 961
962 /*
963 * We can enable relaxed ordering for reads, but not writes when
964 * DCA is enabled. This is due to a known issue in some chipsets
965 * which will cause the DCA tag to be cleared.
966 */
967 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
968 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
969 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
970
971 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 972}
973
974static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975{
976 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 977 struct ixgbe_ring *ring;
bd0362dd 978 int cpu = get_cpu();
bd0362dd 979
33cf09c9
AD		 980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
a557928e 983 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 984 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 985
a557928e 986 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 987 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 988
989 q_vector->cpu = cpu;
990out_no_update:
bd0362dd
JC		 991 put_cpu();
992}
993
994static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995{
996 int i;
997
998 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
999 return;
1000
e35ec126
AD		 1001 /* always use CB2 mode, difference is masked in the CB driver */
1002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1003
49c7ffbe 1004 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1005 adapter->q_vector[i]->cpu = -1;
1006 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1007 }
1008}
1009
1010static int __ixgbe_notify_dca(struct device *dev, void *data)
1011{
c60fbb00 1012 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1013 unsigned long event = *(unsigned long *)data;
1014
2a72c31e 1015 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1016 return 0;
1017
bd0362dd
JC		 1018 switch (event) {
1019 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1020 /* if we're already enabled, don't do it again */
1021 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1022 break;
652f093f 1023 if (dca_add_requester(dev) == 0) {
96b0e0f6 1024 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1025 ixgbe_setup_dca(adapter);
1026 break;
1027 }
1028 /* Fall Through since DCA is disabled. */
1029 case DCA_PROVIDER_REMOVE:
1030 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1031 dca_remove_requester(dev);
1032 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1034 }
1035 break;
1036 }
1037
652f093f 1038 return 0;
bd0362dd 1039}
67a74ee2 1040
bdda1a61 1041#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1042static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1043 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1044 struct sk_buff *skb)
1045{
8a0da21b
AD		 1046 if (ring->netdev->features & NETIF_F_RXHASH)
1047 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1048}
1049
f800326d 1050#ifdef IXGBE_FCOE
ff886dfc
AD		 1051/**
1052 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1053 * @ring: structure containing ring specific data
ff886dfc
AD		 1054 * @rx_desc: advanced rx descriptor
1055 *
1056 * Returns : true if it is FCoE pkt
1057 */
57efd44c 1058static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1059 union ixgbe_adv_rx_desc *rx_desc)
1060{
1061 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1062
57efd44c 1063 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1064 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1065 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1066 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1067}
1068
f800326d 1069#endif /* IXGBE_FCOE */
e59bd25d
AV		 1070/**
1071 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1072 * @ring: structure containing ring specific data
1073 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1074 * @skb: skb currently being received and modified
1075 **/
8a0da21b 1076static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1077 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1078 struct sk_buff *skb)
9a799d71 1079{
8a0da21b 1080 skb_checksum_none_assert(skb);
9a799d71 1081
712744be 1082 /* Rx csum disabled */
8a0da21b 1083 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1084 return;
e59bd25d
AV		 1085
1086 /* if IP and error */
f56e0cb1
AD		 1087 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1088 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1089 ring->rx_stats.csum_err++;
9a799d71
AK		 1090 return;
1091 }
e59bd25d 1092
f56e0cb1 1093 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1094 return;
1095
f56e0cb1 1096 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1097 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1098
1099 /*
1100 * 82599 errata, UDP frames with a 0 checksum can be marked as
1101 * checksum errors.
1102 */
8a0da21b
AD		 1103 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1104 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1105 return;
1106
8a0da21b 1107 ring->rx_stats.csum_err++;
e59bd25d
AV		 1108 return;
1109 }
1110
9a799d71 1111 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1113}
1114
84ea2591 1115static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1116{
f56e0cb1 1117 rx_ring->next_to_use = val;
f800326d
AD		 1118
1119 /* update next to alloc since we have filled the ring */
1120 rx_ring->next_to_alloc = val;
e8e26350
PW		 1121 /*
1122 * Force memory writes to complete before letting h/w
1123 * know there are new descriptors to fetch. (Only
1124 * applicable for weak-ordered memory model archs,
1125 * such as IA-64).
1126 */
1127 wmb();
84ea2591 1128 writel(val, rx_ring->tail);
e8e26350
PW		 1129}
1130
f990b79b
AD		 1131static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1132 struct ixgbe_rx_buffer *bi)
1133{
1134 struct page *page = bi->page;
f800326d 1135 dma_addr_t dma = bi->dma;
f990b79b 1136
f800326d
AD		 1137 /* since we are recycling buffers we should seldom need to alloc */
1138 if (likely(dma))
f990b79b
AD		 1139 return true;
1140
f800326d
AD		 1141 /* alloc new page for storage */
1142 if (likely(!page)) {
8633c084 1143 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
f800326d 1144 ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1145 if (unlikely(!page)) {
1146 rx_ring->rx_stats.alloc_rx_page_failed++;
1147 return false;
1148 }
f800326d 1149 bi->page = page;
f990b79b
AD		 1150 }
1151
f800326d
AD		 1152 /* map page for use */
1153 dma = dma_map_page(rx_ring->dev, page, 0,
1154 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1155
1156 /*
1157 * if mapping failed free memory back to system since
1158 * there isn't much point in holding memory we can't use
1159 */
1160 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1161 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1162 bi->page = NULL;
f990b79b 1163
f990b79b
AD		 1164 rx_ring->rx_stats.alloc_rx_page_failed++;
1165 return false;
1166 }
1167
f800326d
AD		 1168 bi->dma = dma;
1169 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1170
f990b79b
AD		 1171 return true;
1172}
1173
9a799d71 1174/**
f990b79b 1175 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1176 * @rx_ring: ring to place buffers on
1177 * @cleaned_count: number of buffers to replace
9a799d71 1178 **/
fc77dc3c 1179void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1180{
9a799d71 1181 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1182 struct ixgbe_rx_buffer *bi;
d5f398ed 1183 u16 i = rx_ring->next_to_use;
9a799d71 1184
f800326d
AD		 1185 /* nothing to do */
1186 if (!cleaned_count)
fc77dc3c
AD		 1187 return;
1188
e4f74028 1189 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1190 bi = &rx_ring->rx_buffer_info[i];
1191 i -= rx_ring->count;
9a799d71 1192
f800326d
AD		 1193 do {
1194 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1195 break;
d5f398ed 1196
f800326d
AD		 1197 /*
1198 * Refresh the desc even if buffer_addrs didn't change
1199 * because each write-back erases this info.
1200 */
1201 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1202
f990b79b
AD		 1203 rx_desc++;
1204 bi++;
9a799d71 1205 i++;
f990b79b 1206 if (unlikely(!i)) {
e4f74028 1207 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1208 bi = rx_ring->rx_buffer_info;
1209 i -= rx_ring->count;
1210 }
1211
1212 /* clear the hdr_addr for the next_to_use descriptor */
1213 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1214
1215 cleaned_count--;
1216 } while (cleaned_count);
7c6e0a43 1217
f990b79b
AD		 1218 i += rx_ring->count;
1219
f56e0cb1 1220 if (rx_ring->next_to_use != i)
84ea2591 1221 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1222}
1223
1d2024f6
AD		 1224/**
1225 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1226 * @data: pointer to the start of the headers
1227 * @max_len: total length of section to find headers in
1228 *
1229 * This function is meant to determine the length of headers that will
1230 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1231 * motivation of doing this is to only perform one pull for IPv4 TCP
1232 * packets so that we can do basic things like calculating the gso_size
1233 * based on the average data per packet.
1234 **/
1235static unsigned int ixgbe_get_headlen(unsigned char *data,
1236 unsigned int max_len)
1237{
1238 union {
1239 unsigned char *network;
1240 /* l2 headers */
1241 struct ethhdr *eth;
1242 struct vlan_hdr *vlan;
1243 /* l3 headers */
1244 struct iphdr *ipv4;
1245 } hdr;
1246 __be16 protocol;
1247 u8 nexthdr = 0; /* default to not TCP */
1248 u8 hlen;
1249
1250 /* this should never happen, but better safe than sorry */
1251 if (max_len < ETH_HLEN)
1252 return max_len;
1253
1254 /* initialize network frame pointer */
1255 hdr.network = data;
1256
1257 /* set first protocol and move network header forward */
1258 protocol = hdr.eth->h_proto;
1259 hdr.network += ETH_HLEN;
1260
1261 /* handle any vlan tag if present */
1262 if (protocol == __constant_htons(ETH_P_8021Q)) {
1263 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1264 return max_len;
1265
1266 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1267 hdr.network += VLAN_HLEN;
1268 }
1269
1270 /* handle L3 protocols */
1271 if (protocol == __constant_htons(ETH_P_IP)) {
1272 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1273 return max_len;
1274
1275 /* access ihl as a u8 to avoid unaligned access on ia64 */
1276 hlen = (hdr.network[0] & 0x0F) << 2;
1277
1278 /* verify hlen meets minimum size requirements */
1279 if (hlen < sizeof(struct iphdr))
1280 return hdr.network - data;
1281
1282 /* record next protocol */
1283 nexthdr = hdr.ipv4->protocol;
1284 hdr.network += hlen;
f800326d 1285#ifdef IXGBE_FCOE
1d2024f6
AD		 1286 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1287 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1288 return max_len;
1289 hdr.network += FCOE_HEADER_LEN;
1290#endif
1291 } else {
1292 return hdr.network - data;
1293 }
1294
1295 /* finally sort out TCP */
1296 if (nexthdr == IPPROTO_TCP) {
1297 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1298 return max_len;
1299
1300 /* access doff as a u8 to avoid unaligned access on ia64 */
1301 hlen = (hdr.network[12] & 0xF0) >> 2;
1302
1303 /* verify hlen meets minimum size requirements */
1304 if (hlen < sizeof(struct tcphdr))
1305 return hdr.network - data;
1306
1307 hdr.network += hlen;
1308 }
1309
1310 /*
1311 * If everything has gone correctly hdr.network should be the
1312 * data section of the packet and will be the end of the header.
1313 * If not then it probably represents the end of the last recognized
1314 * header.
1315 */
1316 if ((hdr.network - data) < max_len)
1317 return hdr.network - data;
1318 else
1319 return max_len;
1320}
1321
4c1975d7
AD		 1322static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1323 union ixgbe_adv_rx_desc *rx_desc,
1324 struct sk_buff *skb)
aa80175a 1325{
4c1975d7
AD		 1326 __le32 rsc_enabled;
1327 u32 rsc_cnt;
1328
1329 if (!ring_is_rsc_enabled(rx_ring))
1330 return;
1331
1332 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1333 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1334
1335 /* If this is an RSC frame rsc_cnt should be non-zero */
1336 if (!rsc_enabled)
1337 return;
1338
1339 rsc_cnt = le32_to_cpu(rsc_enabled);
1340 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1341
1342 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1343}
43634e82 1344
1d2024f6
AD		 1345static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1346 struct sk_buff *skb)
1347{
f800326d 1348 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1349
1350 /* set gso_size to avoid messing up TCP MSS */
1351 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1352 IXGBE_CB(skb)->append_cnt);
1353}
1354
1355static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1356 struct sk_buff *skb)
1357{
1358 /* if append_cnt is 0 then frame is not RSC */
1359 if (!IXGBE_CB(skb)->append_cnt)
1360 return;
1361
1362 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1363 rx_ring->rx_stats.rsc_flush++;
1364
1365 ixgbe_set_rsc_gso_size(rx_ring, skb);
1366
1367 /* gso_size is computed using append_cnt so always clear it last */
1368 IXGBE_CB(skb)->append_cnt = 0;
1369}
1370
8a0da21b
AD		 1371/**
1372 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1373 * @rx_ring: rx descriptor ring packet is being transacted on
1374 * @rx_desc: pointer to the EOP Rx descriptor
1375 * @skb: pointer to current skb being populated
f8212f97 1376 *
8a0da21b
AD		 1377 * This function checks the ring, descriptor, and packet information in
1378 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1379 * other fields within the skb.
f8212f97 1380 **/
8a0da21b
AD		 1381static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1382 union ixgbe_adv_rx_desc *rx_desc,
1383 struct sk_buff *skb)
f8212f97 1384{
43e95f11
JF		 1385 struct net_device *dev = rx_ring->netdev;
1386
8a0da21b
AD		 1387 ixgbe_update_rsc_stats(rx_ring, skb);
1388
1389 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1390
8a0da21b
AD		 1391 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1392
3a6a4eda 1393#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1394 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1395#endif
1396
43e95f11
JF		 1397 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1398 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1399 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1400 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1401 }
1402
8a0da21b 1403 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1404
43e95f11 1405 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1406}
1407
8a0da21b
AD		 1408static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1409 struct sk_buff *skb)
aa80175a 1410{
8a0da21b
AD		 1411 struct ixgbe_adapter *adapter = q_vector->adapter;
1412
1413 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1414 napi_gro_receive(&q_vector->napi, skb);
1415 else
1416 netif_rx(skb);
aa80175a 1417}
43634e82 1418
f800326d
AD		 1419/**
1420 * ixgbe_is_non_eop - process handling of non-EOP buffers
1421 * @rx_ring: Rx ring being processed
1422 * @rx_desc: Rx descriptor for current buffer
1423 * @skb: Current socket buffer containing buffer in progress
1424 *
1425 * This function updates next to clean. If the buffer is an EOP buffer
1426 * this function exits returning false, otherwise it will place the
1427 * sk_buff in the next buffer to be chained and return true indicating
1428 * that this is in fact a non-EOP buffer.
1429 **/
1430static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1431 union ixgbe_adv_rx_desc *rx_desc,
1432 struct sk_buff *skb)
1433{
1434 u32 ntc = rx_ring->next_to_clean + 1;
1435
1436 /* fetch, update, and store next to clean */
1437 ntc = (ntc < rx_ring->count) ? ntc : 0;
1438 rx_ring->next_to_clean = ntc;
1439
1440 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1441
1442 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1443 return false;
1444
1445 /* append_cnt indicates packet is RSC, if so fetch nextp */
1446 if (IXGBE_CB(skb)->append_cnt) {
1447 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1448 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1449 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1450 }
1451
1452 /* place skb in next buffer to be received */
1453 rx_ring->rx_buffer_info[ntc].skb = skb;
1454 rx_ring->rx_stats.non_eop_descs++;
1455
1456 return true;
1457}
1458
1459/**
1460 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1461 * @rx_ring: rx descriptor ring packet is being transacted on
1462 * @rx_desc: pointer to the EOP Rx descriptor
1463 * @skb: pointer to current skb being fixed
1464 *
1465 * Check for corrupted packet headers caused by senders on the local L2
1466 * embedded NIC switch not setting up their Tx Descriptors right. These
1467 * should be very rare.
1468 *
1469 * Also address the case where we are pulling data in on pages only
1470 * and as such no data is present in the skb header.
1471 *
1472 * In addition if skb is not at least 60 bytes we need to pad it so that
1473 * it is large enough to qualify as a valid Ethernet frame.
1474 *
1475 * Returns true if an error was encountered and skb was freed.
1476 **/
1477static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480{
1481 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1482 struct net_device *netdev = rx_ring->netdev;
1483 unsigned char *va;
1484 unsigned int pull_len;
1485
1486 /* if the page was released unmap it, else just sync our portion */
1487 if (unlikely(IXGBE_CB(skb)->page_released)) {
1488 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1489 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1490 IXGBE_CB(skb)->page_released = false;
1491 } else {
1492 dma_sync_single_range_for_cpu(rx_ring->dev,
1493 IXGBE_CB(skb)->dma,
1494 frag->page_offset,
1495 ixgbe_rx_bufsz(rx_ring),
1496 DMA_FROM_DEVICE);
1497 }
1498 IXGBE_CB(skb)->dma = 0;
1499
1500 /* verify that the packet does not have any known errors */
1501 if (unlikely(ixgbe_test_staterr(rx_desc,
1502 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1503 !(netdev->features & NETIF_F_RXALL))) {
1504 dev_kfree_skb_any(skb);
1505 return true;
1506 }
1507
1508 /*
1509 * it is valid to use page_address instead of kmap since we are
1510 * working with pages allocated out of the lomem pool per
1511 * alloc_page(GFP_ATOMIC)
1512 */
1513 va = skb_frag_address(frag);
1514
1515 /*
1516 * we need the header to contain the greater of either ETH_HLEN or
1517 * 60 bytes if the skb->len is less than 60 for skb_pad.
1518 */
1519 pull_len = skb_frag_size(frag);
1520 if (pull_len > 256)
1521 pull_len = ixgbe_get_headlen(va, pull_len);
1522
1523 /* align pull length to size of long to optimize memcpy performance */
1524 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1525
1526 /* update all of the pointers */
1527 skb_frag_size_sub(frag, pull_len);
1528 frag->page_offset += pull_len;
1529 skb->data_len -= pull_len;
1530 skb->tail += pull_len;
1531
1532 /*
1533 * if we sucked the frag empty then we should free it,
1534 * if there are other frags here something is screwed up in hardware
1535 */
1536 if (skb_frag_size(frag) == 0) {
1537 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1538 skb_shinfo(skb)->nr_frags = 0;
1539 __skb_frag_unref(frag);
1540 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1541 }
1542
57efd44c
AD		 1543#ifdef IXGBE_FCOE
1544 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1545 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1546 return false;
1547
1548#endif
f800326d
AD		 1549 /* if skb_pad returns an error the skb was freed */
1550 if (unlikely(skb->len < 60)) {
1551 int pad_len = 60 - skb->len;
1552
1553 if (skb_pad(skb, pad_len))
1554 return true;
1555 __skb_put(skb, pad_len);
1556 }
1557
1558 return false;
1559}
1560
1561/**
1562 * ixgbe_can_reuse_page - determine if we can reuse a page
1563 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1564 *
1565 * Returns true if page can be reused in another Rx buffer
1566 **/
1567static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1568{
1569 struct page *page = rx_buffer->page;
1570
1571 /* if we are only owner of page and it is local we can reuse it */
1572 return likely(page_count(page) == 1) &&
1573 likely(page_to_nid(page) == numa_node_id());
1574}
1575
1576/**
1577 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1578 * @rx_ring: rx descriptor ring to store buffers on
1579 * @old_buff: donor buffer to have page reused
1580 *
1581 * Syncronizes page for reuse by the adapter
1582 **/
1583static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1584 struct ixgbe_rx_buffer *old_buff)
1585{
1586 struct ixgbe_rx_buffer *new_buff;
1587 u16 nta = rx_ring->next_to_alloc;
1588 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1589
1590 new_buff = &rx_ring->rx_buffer_info[nta];
1591
1592 /* update, and store next to alloc */
1593 nta++;
1594 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1595
1596 /* transfer page from old buffer to new buffer */
1597 new_buff->page = old_buff->page;
1598 new_buff->dma = old_buff->dma;
1599
1600 /* flip page offset to other buffer and store to new_buff */
1601 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1602
1603 /* sync the buffer for use by the device */
1604 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1605 new_buff->page_offset, bufsz,
1606 DMA_FROM_DEVICE);
1607
1608 /* bump ref count on page before it is given to the stack */
1609 get_page(new_buff->page);
1610}
1611
1612/**
1613 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1614 * @rx_ring: rx descriptor ring to transact packets on
1615 * @rx_buffer: buffer containing page to add
1616 * @rx_desc: descriptor containing length of buffer written by hardware
1617 * @skb: sk_buff to place the data into
1618 *
1619 * This function is based on skb_add_rx_frag. I would have used that
1620 * function however it doesn't handle the truesize case correctly since we
1621 * are allocating more memory than might be used for a single receive.
1622 **/
1623static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1624 struct ixgbe_rx_buffer *rx_buffer,
1625 struct sk_buff *skb, int size)
1626{
1627 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1628 rx_buffer->page, rx_buffer->page_offset,
1629 size);
1630 skb->len += size;
1631 skb->data_len += size;
1632 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1633}
1634
1635/**
1636 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1637 * @q_vector: structure containing interrupt and ring information
1638 * @rx_ring: rx descriptor ring to transact packets on
1639 * @budget: Total limit on number of packets to process
1640 *
1641 * This function provides a "bounce buffer" approach to Rx interrupt
1642 * processing. The advantage to this is that on systems that have
1643 * expensive overhead for IOMMU access this provides a means of avoiding
1644 * it by maintaining the mapping of the page to the syste.
1645 *
1646 * Returns true if all work is completed without reaching budget
1647 **/
4ff7fb12 1648static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1649 struct ixgbe_ring *rx_ring,
4ff7fb12 1650 int budget)
9a799d71 1651{
d2f4fbe2 1652 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1653#ifdef IXGBE_FCOE
f800326d 1654 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1655 int ddp_bytes = 0;
1656#endif /* IXGBE_FCOE */
f800326d 1657 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1658
f800326d
AD		 1659 do {
1660 struct ixgbe_rx_buffer *rx_buffer;
1661 union ixgbe_adv_rx_desc *rx_desc;
1662 struct sk_buff *skb;
1663 struct page *page;
1664 u16 ntc;
1665
1666 /* return some buffers to hardware, one at a time is too slow */
1667 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1668 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1669 cleaned_count = 0;
1670 }
1671
1672 ntc = rx_ring->next_to_clean;
1673 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1674 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1675
1676 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1677 break;
9a799d71 1678
f800326d
AD		 1679 /*
1680 * This memory barrier is needed to keep us from reading
1681 * any other fields out of the rx_desc until we know the
1682 * RXD_STAT_DD bit is set
1683 */
1684 rmb();
9a799d71 1685
f800326d
AD		 1686 page = rx_buffer->page;
1687 prefetchw(page);
9a799d71 1688
f800326d 1689 skb = rx_buffer->skb;
c267fc16 1690
f800326d
AD		 1691 if (likely(!skb)) {
1692 void *page_addr = page_address(page) +
1693 rx_buffer->page_offset;
9a799d71 1694
f800326d
AD		 1695 /* prefetch first cache line of first page */
1696 prefetch(page_addr);
1697#if L1_CACHE_BYTES < 128
1698 prefetch(page_addr + L1_CACHE_BYTES);
1699#endif
1700
1701 /* allocate a skb to store the frags */
1702 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1703 IXGBE_RX_HDR_SIZE);
1704 if (unlikely(!skb)) {
1705 rx_ring->rx_stats.alloc_rx_buff_failed++;
1706 break;
c267fc16
AD		 1707 }
1708
f800326d
AD		 1709 /*
1710 * we will be copying header into skb->data in
1711 * pskb_may_pull so it is in our interest to prefetch
1712 * it now to avoid a possible cache miss
1713 */
1714 prefetchw(skb->data);
4c1975d7
AD		 1715
1716 /*
1717 * Delay unmapping of the first packet. It carries the
1718 * header information, HW may still access the header
f800326d
AD		 1719 * after the writeback. Only unmap it when EOP is
1720 * reached
4c1975d7 1721 */
f800326d 1722 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1723 } else {
f800326d
AD		 1724 /* we are reusing so sync this buffer for CPU use */
1725 dma_sync_single_range_for_cpu(rx_ring->dev,
1726 rx_buffer->dma,
1727 rx_buffer->page_offset,
1728 ixgbe_rx_bufsz(rx_ring),
1729 DMA_FROM_DEVICE);
9a799d71
AK		 1730 }
1731
f800326d
AD		 1732 /* pull page into skb */
1733 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1734 le16_to_cpu(rx_desc->wb.upper.length));
9a799d71 1735
f800326d
AD		 1736 if (ixgbe_can_reuse_page(rx_buffer)) {
1737 /* hand second half of page back to the ring */
1738 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1739 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1740 /* the page has been released from the ring */
1741 IXGBE_CB(skb)->page_released = true;
1742 } else {
1743 /* we are not reusing the buffer so unmap it */
1744 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1745 ixgbe_rx_pg_size(rx_ring),
1746 DMA_FROM_DEVICE);
9a799d71
AK		 1747 }
1748
f800326d
AD		 1749 /* clear contents of buffer_info */
1750 rx_buffer->skb = NULL;
1751 rx_buffer->dma = 0;
1752 rx_buffer->page = NULL;
4c1975d7 1753
f800326d 1754 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1755
9a799d71 1756 cleaned_count++;
f8212f97 1757
f800326d
AD		 1758 /* place incomplete frames back on ring for completion */
1759 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1760 continue;
c267fc16 1761
f800326d
AD		 1762 /* verify the packet layout is correct */
1763 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1764 continue;
9a799d71 1765
d2f4fbe2
AV		 1766 /* probably a little skewed due to removing CRC */
1767 total_rx_bytes += skb->len;
1768 total_rx_packets++;
1769
8a0da21b
AD		 1770 /* populate checksum, timestamp, VLAN, and protocol */
1771 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1772
332d4a7d
YZ		 1773#ifdef IXGBE_FCOE
1774 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1775 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1776 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1777 if (!ddp_bytes) {
1778 dev_kfree_skb_any(skb);
f800326d 1779 continue;
63d635b2 1780 }
3d8fd385 1781 }
f800326d 1782
332d4a7d 1783#endif /* IXGBE_FCOE */
8a0da21b 1784 ixgbe_rx_skb(q_vector, skb);
9a799d71 1785
f800326d 1786 /* update budget accounting */
4ff7fb12 1787 budget--;
f800326d 1788 } while (likely(budget));
9a799d71 1789
3d8fd385
YZ		 1790#ifdef IXGBE_FCOE
1791 /* include DDPed FCoE data */
1792 if (ddp_bytes > 0) {
1793 unsigned int mss;
1794
fc77dc3c 1795 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1796 sizeof(struct fc_frame_header) -
1797 sizeof(struct fcoe_crc_eof);
1798 if (mss > 512)
1799 mss &= ~511;
1800 total_rx_bytes += ddp_bytes;
1801 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1802 }
3d8fd385 1803
f800326d 1804#endif /* IXGBE_FCOE */
c267fc16
AD		 1805 u64_stats_update_begin(&rx_ring->syncp);
1806 rx_ring->stats.packets += total_rx_packets;
1807 rx_ring->stats.bytes += total_rx_bytes;
1808 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1809 q_vector->rx.total_packets += total_rx_packets;
1810 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1811
f800326d
AD		 1812 if (cleaned_count)
1813 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1814
4ff7fb12 1815 return !!budget;
9a799d71
AK		 1816}
1817
9a799d71
AK		 1818/**
1819 * ixgbe_configure_msix - Configure MSI-X hardware
1820 * @adapter: board private structure
1821 *
1822 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1823 * interrupts.
1824 **/
1825static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1826{
021230d4 1827 struct ixgbe_q_vector *q_vector;
49c7ffbe 1828 int v_idx;
021230d4 1829 u32 mask;
9a799d71 1830
8e34d1aa
AD		 1831 /* Populate MSIX to EITR Select */
1832 if (adapter->num_vfs > 32) {
1833 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1835 }
1836
4df10466
JB		 1837 /*
1838 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1839 * corresponding register.
1840 */
49c7ffbe 1841 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1842 struct ixgbe_ring *ring;
7a921c93 1843 q_vector = adapter->q_vector[v_idx];
021230d4 1844
a557928e 1845 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1846 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1847
a557928e 1848 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1849 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1850
d5bf4f67
ET		 1851 if (q_vector->tx.ring && !q_vector->rx.ring) {
1852 /* tx only vector */
1853 if (adapter->tx_itr_setting == 1)
1854 q_vector->itr = IXGBE_10K_ITR;
1855 else
1856 q_vector->itr = adapter->tx_itr_setting;
1857 } else {
1858 /* rx or rx/tx vector */
1859 if (adapter->rx_itr_setting == 1)
1860 q_vector->itr = IXGBE_20K_ITR;
1861 else
1862 q_vector->itr = adapter->rx_itr_setting;
1863 }
021230d4 1864
fe49f04a 1865 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1866 }
1867
bd508178
AD		 1868 switch (adapter->hw.mac.type) {
1869 case ixgbe_mac_82598EB:
e8e26350 1870 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1871 v_idx);
bd508178
AD		 1872 break;
1873 case ixgbe_mac_82599EB:
b93a2226 1874 case ixgbe_mac_X540:
e8e26350 1875 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1876 break;
bd508178
AD		 1877 default:
1878 break;
1879 }
021230d4
AV		 1880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1881
41fb9248 1882 /* set up to autoclear timer, and the vectors */
021230d4 1883 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1884 mask &= ~(IXGBE_EIMS_OTHER |
1885 IXGBE_EIMS_MAILBOX |
1886 IXGBE_EIMS_LSC);
1887
021230d4 1888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1889}
1890
f494e8fa
AV		 1891enum latency_range {
1892 lowest_latency = 0,
1893 low_latency = 1,
1894 bulk_latency = 2,
1895 latency_invalid = 255
1896};
1897
1898/**
1899 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1900 * @q_vector: structure containing interrupt and ring information
1901 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1902 *
1903 * Stores a new ITR value based on packets and byte
1904 * counts during the last interrupt. The advantage of per interrupt
1905 * computation is faster updates and more accurate ITR for the current
1906 * traffic pattern. Constants in this function were computed
1907 * based on theoretical maximum wire speed and thresholds were set based
1908 * on testing data as well as attempting to minimize response time
1909 * while increasing bulk throughput.
1910 * this functionality is controlled by the InterruptThrottleRate module
1911 * parameter (see ixgbe_param.c)
1912 **/
bd198058
AD		 1913static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1914 struct ixgbe_ring_container *ring_container)
f494e8fa 1915{
bd198058
AD		 1916 int bytes = ring_container->total_bytes;
1917 int packets = ring_container->total_packets;
1918 u32 timepassed_us;
621bd70e 1919 u64 bytes_perint;
bd198058 1920 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1921
1922 if (packets == 0)
bd198058 1923 return;
f494e8fa
AV		 1924
1925 /* simple throttlerate management
621bd70e
AD		 1926 * 0-10MB/s lowest (100000 ints/s)
1927 * 10-20MB/s low (20000 ints/s)
1928 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1929 */
1930 /* what was last interrupt timeslice? */
d5bf4f67 1931 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1932 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1933
1934 switch (itr_setting) {
1935 case lowest_latency:
621bd70e 1936 if (bytes_perint > 10)
bd198058 1937 itr_setting = low_latency;
f494e8fa
AV		 1938 break;
1939 case low_latency:
621bd70e 1940 if (bytes_perint > 20)
bd198058 1941 itr_setting = bulk_latency;
621bd70e 1942 else if (bytes_perint <= 10)
bd198058 1943 itr_setting = lowest_latency;
f494e8fa
AV		 1944 break;
1945 case bulk_latency:
621bd70e 1946 if (bytes_perint <= 20)
bd198058 1947 itr_setting = low_latency;
f494e8fa
AV		 1948 break;
1949 }
1950
bd198058
AD		 1951 /* clear work counters since we have the values we need */
1952 ring_container->total_bytes = 0;
1953 ring_container->total_packets = 0;
1954
1955 /* write updated itr to ring container */
1956 ring_container->itr = itr_setting;
f494e8fa
AV		 1957}
1958
509ee935
JB		 1959/**
1960 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1961 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1962 *
1963 * This function is made to be called by ethtool and by the driver
1964 * when it needs to update EITR registers at runtime. Hardware
1965 * specific quirks/differences are taken care of here.
1966 */
fe49f04a 1967void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1968{
fe49f04a 1969 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1970 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1971 int v_idx = q_vector->v_idx;
5d967eb7 1972 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1973
bd508178
AD		 1974 switch (adapter->hw.mac.type) {
1975 case ixgbe_mac_82598EB:
509ee935
JB		 1976 /* must write high and low 16 bits to reset counter */
1977 itr_reg |= (itr_reg << 16);
bd508178
AD		 1978 break;
1979 case ixgbe_mac_82599EB:
b93a2226 1980 case ixgbe_mac_X540:
509ee935
JB		 1981 /*
1982 * set the WDIS bit to not clear the timer bits and cause an
1983 * immediate assertion of the interrupt
1984 */
1985 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1986 break;
1987 default:
1988 break;
509ee935
JB		 1989 }
1990 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1991}
1992
bd198058 1993static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1994{
d5bf4f67 1995 u32 new_itr = q_vector->itr;
bd198058 1996 u8 current_itr;
f494e8fa 1997
bd198058
AD		 1998 ixgbe_update_itr(q_vector, &q_vector->tx);
1999 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2000
08c8833b 2001 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2002
2003 switch (current_itr) {
2004 /* counts and packets in update_itr are dependent on these numbers */
2005 case lowest_latency:
d5bf4f67 2006 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2007 break;
2008 case low_latency:
d5bf4f67 2009 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2010 break;
2011 case bulk_latency:
d5bf4f67 2012 new_itr = IXGBE_8K_ITR;
f494e8fa 2013 break;
bd198058
AD		 2014 default:
2015 break;
f494e8fa
AV		 2016 }
2017
d5bf4f67 2018 if (new_itr != q_vector->itr) {
fe49f04a 2019 /* do an exponential smoothing */
d5bf4f67
ET		 2020 new_itr = (10 * new_itr * q_vector->itr) /
2021 ((9 * new_itr) + q_vector->itr);
509ee935 2022
bd198058 2023 /* save the algorithm value here */
5d967eb7 2024 q_vector->itr = new_itr;
fe49f04a
AD		 2025
2026 ixgbe_write_eitr(q_vector);
f494e8fa 2027 }
f494e8fa
AV		 2028}
2029
119fc60a 2030/**
de88eeeb 2031 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2032 * @adapter: pointer to adapter
119fc60a 2033 **/
f0f9778d 2034static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2035{
119fc60a
MC		 2036 struct ixgbe_hw *hw = &adapter->hw;
2037 u32 eicr = adapter->interrupt_event;
2038
f0f9778d 2039 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2040 return;
2041
f0f9778d
AD		 2042 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2043 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2044 return;
2045
2046 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2047
7ca647bd 2048 switch (hw->device_id) {
f0f9778d
AD		 2049 case IXGBE_DEV_ID_82599_T3_LOM:
2050 /*
2051 * Since the warning interrupt is for both ports
2052 * we don't have to check if:
2053 * - This interrupt wasn't for our port.
2054 * - We may have missed the interrupt so always have to
2055 * check if we got a LSC
2056 */
2057 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2058 !(eicr & IXGBE_EICR_LSC))
2059 return;
2060
2061 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2062 u32 autoneg;
2063 bool link_up = false;
7ca647bd 2064
7ca647bd
JP		 2065 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2066
f0f9778d
AD		 2067 if (link_up)
2068 return;
2069 }
2070
2071 /* Check if this is not due to overtemp */
2072 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2073 return;
2074
2075 break;
7ca647bd
JP		 2076 default:
2077 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2078 return;
7ca647bd 2079 break;
119fc60a 2080 }
7ca647bd
JP		 2081 e_crit(drv,
2082 "Network adapter has been stopped because it has over heated. "
2083 "Restart the computer. If the problem persists, "
2084 "power off the system and replace the adapter\n");
f0f9778d
AD		 2085
2086 adapter->interrupt_event = 0;
119fc60a
MC		 2087}
2088
0befdb3e
JB		 2089static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2090{
2091 struct ixgbe_hw *hw = &adapter->hw;
2092
2093 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2094 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2095 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2096 /* write to clear the interrupt */
2097 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2098 }
2099}
cf8280ee 2100
4f51bf70
JK		 2101static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2102{
2103 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2104 return;
2105
2106 switch (adapter->hw.mac.type) {
2107 case ixgbe_mac_82599EB:
2108 /*
2109 * Need to check link state so complete overtemp check
2110 * on service task
2111 */
2112 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2113 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2114 adapter->interrupt_event = eicr;
2115 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2116 ixgbe_service_event_schedule(adapter);
2117 return;
2118 }
2119 return;
2120 case ixgbe_mac_X540:
2121 if (!(eicr & IXGBE_EICR_TS))
2122 return;
2123 break;
2124 default:
2125 return;
2126 }
2127
2128 e_crit(drv,
2129 "Network adapter has been stopped because it has over heated. "
2130 "Restart the computer. If the problem persists, "
2131 "power off the system and replace the adapter\n");
2132}
2133
e8e26350
PW		 2134static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2135{
2136 struct ixgbe_hw *hw = &adapter->hw;
2137
73c4b7cd
AD		 2138 if (eicr & IXGBE_EICR_GPI_SDP2) {
2139 /* Clear the interrupt */
2140 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2141 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2142 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2143 ixgbe_service_event_schedule(adapter);
2144 }
73c4b7cd
AD		 2145 }
2146
e8e26350
PW		 2147 if (eicr & IXGBE_EICR_GPI_SDP1) {
2148 /* Clear the interrupt */
2149 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2150 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2151 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2152 ixgbe_service_event_schedule(adapter);
2153 }
e8e26350
PW		 2154 }
2155}
2156
cf8280ee
JB		 2157static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2158{
2159 struct ixgbe_hw *hw = &adapter->hw;
2160
2161 adapter->lsc_int++;
2162 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2163 adapter->link_check_timeout = jiffies;
2164 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2165 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2166 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2167 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2168 }
2169}
2170
fe49f04a
AD		 2171static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2172 u64 qmask)
2173{
2174 u32 mask;
bd508178 2175 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2176
bd508178
AD		 2177 switch (hw->mac.type) {
2178 case ixgbe_mac_82598EB:
fe49f04a 2179 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2180 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2181 break;
2182 case ixgbe_mac_82599EB:
b93a2226 2183 case ixgbe_mac_X540:
fe49f04a 2184 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2185 if (mask)
2186 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2187 mask = (qmask >> 32);
bd508178
AD		 2188 if (mask)
2189 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2190 break;
2191 default:
2192 break;
fe49f04a
AD		 2193 }
2194 /* skip the flush */
2195}
2196
2197static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2198 u64 qmask)
fe49f04a
AD		 2199{
2200 u32 mask;
bd508178 2201 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2202
bd508178
AD		 2203 switch (hw->mac.type) {
2204 case ixgbe_mac_82598EB:
fe49f04a 2205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2206 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2207 break;
2208 case ixgbe_mac_82599EB:
b93a2226 2209 case ixgbe_mac_X540:
fe49f04a 2210 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2211 if (mask)
2212 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2213 mask = (qmask >> 32);
bd508178
AD		 2214 if (mask)
2215 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2216 break;
2217 default:
2218 break;
fe49f04a
AD		 2219 }
2220 /* skip the flush */
2221}
2222
021230d4 2223/**
2c4af694
AD		 2224 * ixgbe_irq_enable - Enable default interrupt generation settings
2225 * @adapter: board private structure
021230d4 2226 **/
2c4af694
AD		 2227static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2228 bool flush)
9a799d71 2229{
2c4af694 2230 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2231
2c4af694
AD		 2232 /* don't reenable LSC while waiting for link */
2233 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2234 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2235
2c4af694 2236 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2237 switch (adapter->hw.mac.type) {
2238 case ixgbe_mac_82599EB:
2239 mask |= IXGBE_EIMS_GPI_SDP0;
2240 break;
2241 case ixgbe_mac_X540:
2242 mask |= IXGBE_EIMS_TS;
2243 break;
2244 default:
2245 break;
2246 }
2c4af694
AD		 2247 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2248 mask |= IXGBE_EIMS_GPI_SDP1;
2249 switch (adapter->hw.mac.type) {
2250 case ixgbe_mac_82599EB:
2c4af694
AD		 2251 mask |= IXGBE_EIMS_GPI_SDP1;
2252 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2253 case ixgbe_mac_X540:
2254 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2255 mask |= IXGBE_EIMS_MAILBOX;
2256 break;
2257 default:
2258 break;
9a799d71 2259 }
2c4af694
AD		 2260 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2261 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2262 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2263
2c4af694
AD		 2264 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2265 if (queues)
2266 ixgbe_irq_enable_queues(adapter, ~0);
2267 if (flush)
2268 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2269}
2270
2c4af694 2271static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2272{
a65151ba 2273 struct ixgbe_adapter *adapter = data;
9a799d71 2274 struct ixgbe_hw *hw = &adapter->hw;
54037505 2275 u32 eicr;
91281fd3 2276
54037505
DS		 2277 /*
2278 * Workaround for Silicon errata. Use clear-by-write instead
2279 * of clear-by-read. Reading with EICS will return the
2280 * interrupt causes without clearing, which later be done
2281 * with the write to EICR.
2282 */
2283 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2284 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2285
cf8280ee
JB		 2286 if (eicr & IXGBE_EICR_LSC)
2287 ixgbe_check_lsc(adapter);
f0848276 2288
1cdd1ec8
GR		 2289 if (eicr & IXGBE_EICR_MAILBOX)
2290 ixgbe_msg_task(adapter);
efe3d3c8 2291
bd508178
AD		 2292 switch (hw->mac.type) {
2293 case ixgbe_mac_82599EB:
b93a2226 2294 case ixgbe_mac_X540:
2c4af694
AD		 2295 if (eicr & IXGBE_EICR_ECC)
2296 e_info(link, "Received unrecoverable ECC Err, please "
2297 "reboot\n");
c4cf55e5
PWJ		 2298 /* Handle Flow Director Full threshold interrupt */
2299 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2300 int reinit_count = 0;
c4cf55e5 2301 int i;
c4cf55e5 2302 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2303 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2304 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2305 &ring->state))
2306 reinit_count++;
2307 }
2308 if (reinit_count) {
2309 /* no more flow director interrupts until after init */
2310 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2311 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2312 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2313 }
2314 }
f0f9778d 2315 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2316 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2317 break;
2318 default:
2319 break;
c4cf55e5 2320 }
f0848276 2321
bd508178 2322 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2323#ifdef CONFIG_IXGBE_PTP
2324 ixgbe_ptp_check_pps_event(adapter, eicr);
2325#endif
efe3d3c8 2326
7086400d 2327 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2328 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2329 ixgbe_irq_enable(adapter, false, false);
f0848276 2330
9a799d71 2331 return IRQ_HANDLED;
f0848276 2332}
91281fd3 2333
4ff7fb12 2334static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2335{
021230d4 2336 struct ixgbe_q_vector *q_vector = data;
91281fd3 2337
9b471446 2338 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2339
4ff7fb12
AD		 2340 if (q_vector->rx.ring || q_vector->tx.ring)
2341 napi_schedule(&q_vector->napi);
91281fd3 2342
9a799d71 2343 return IRQ_HANDLED;
91281fd3
AD		 2344}
2345
eb01b975
AD		 2346/**
2347 * ixgbe_poll - NAPI Rx polling callback
2348 * @napi: structure for representing this polling device
2349 * @budget: how many packets driver is allowed to clean
2350 *
2351 * This function is used for legacy and MSI, NAPI mode
2352 **/
8af3c33f 2353int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2354{
2355 struct ixgbe_q_vector *q_vector =
2356 container_of(napi, struct ixgbe_q_vector, napi);
2357 struct ixgbe_adapter *adapter = q_vector->adapter;
2358 struct ixgbe_ring *ring;
2359 int per_ring_budget;
2360 bool clean_complete = true;
2361
2362#ifdef CONFIG_IXGBE_DCA
2363 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2364 ixgbe_update_dca(q_vector);
2365#endif
2366
2367 ixgbe_for_each_ring(ring, q_vector->tx)
2368 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2369
2370 /* attempt to distribute budget to each queue fairly, but don't allow
2371 * the budget to go below 1 because we'll exit polling */
2372 if (q_vector->rx.count > 1)
2373 per_ring_budget = max(budget/q_vector->rx.count, 1);
2374 else
2375 per_ring_budget = budget;
2376
2377 ixgbe_for_each_ring(ring, q_vector->rx)
2378 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2379 per_ring_budget);
2380
2381 /* If all work not completed, return budget and keep polling */
2382 if (!clean_complete)
2383 return budget;
2384
2385 /* all work done, exit the polling mode */
2386 napi_complete(napi);
2387 if (adapter->rx_itr_setting & 1)
2388 ixgbe_set_itr(q_vector);
2389 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2390 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2391
2392 return 0;
2393}
2394
021230d4
AV		 2395/**
2396 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2397 * @adapter: board private structure
2398 *
2399 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2400 * interrupts from the kernel.
2401 **/
2402static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2403{
2404 struct net_device *netdev = adapter->netdev;
207867f5 2405 int vector, err;
e8e9f696 2406 int ri = 0, ti = 0;
021230d4 2407
49c7ffbe 2408 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2409 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2410 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2411
4ff7fb12 2412 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2413 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2414 "%s-%s-%d", netdev->name, "TxRx", ri++);
2415 ti++;
2416 } else if (q_vector->rx.ring) {
9fe93afd 2417 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2418 "%s-%s-%d", netdev->name, "rx", ri++);
2419 } else if (q_vector->tx.ring) {
9fe93afd 2420 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2421 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2422 } else {
2423 /* skip this unused q_vector */
2424 continue;
32aa77a4 2425 }
207867f5
AD		 2426 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2427 q_vector->name, q_vector);
9a799d71 2428 if (err) {
396e799c 2429 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2430 "Error: %d\n", err);
021230d4 2431 goto free_queue_irqs;
9a799d71 2432 }
207867f5
AD		 2433 /* If Flow Director is enabled, set interrupt affinity */
2434 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2435 /* assign the mask for this irq */
2436 irq_set_affinity_hint(entry->vector,
de88eeeb 2437 &q_vector->affinity_mask);
207867f5 2438 }
9a799d71
AK		 2439 }
2440
021230d4 2441 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2442 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2443 if (err) {
de88eeeb 2444 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2445 goto free_queue_irqs;
9a799d71
AK		 2446 }
2447
9a799d71
AK		 2448 return 0;
2449
021230d4 2450free_queue_irqs:
207867f5
AD		 2451 while (vector) {
2452 vector--;
2453 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2454 NULL);
2455 free_irq(adapter->msix_entries[vector].vector,
2456 adapter->q_vector[vector]);
2457 }
021230d4
AV		 2458 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2459 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2460 kfree(adapter->msix_entries);
2461 adapter->msix_entries = NULL;
9a799d71
AK		 2462 return err;
2463}
2464
2465/**
021230d4 2466 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2467 * @irq: interrupt number
2468 * @data: pointer to a network interface device structure
9a799d71
AK		 2469 **/
2470static irqreturn_t ixgbe_intr(int irq, void *data)
2471{
a65151ba 2472 struct ixgbe_adapter *adapter = data;
9a799d71 2473 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2474 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2475 u32 eicr;
2476
54037505 2477 /*
24ddd967 2478 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2479 * before the read of EICR.
2480 */
2481 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2482
021230d4 2483 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2484 * therefore no explicit interrupt disable is necessary */
021230d4 2485 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2486 if (!eicr) {
6af3b9eb
ET		 2487 /*
2488 * shared interrupt alert!
f47cf66e 2489 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2490 * have disabled interrupts due to EIAM
2491 * finish the workaround of silicon errata on 82598. Unmask
2492 * the interrupt that we masked before the EICR read.
2493 */
2494 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2495 ixgbe_irq_enable(adapter, true, true);
9a799d71 2496 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2497 }
9a799d71 2498
cf8280ee
JB		 2499 if (eicr & IXGBE_EICR_LSC)
2500 ixgbe_check_lsc(adapter);
021230d4 2501
bd508178
AD		 2502 switch (hw->mac.type) {
2503 case ixgbe_mac_82599EB:
e8e26350 2504 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2505 /* Fall through */
2506 case ixgbe_mac_X540:
2507 if (eicr & IXGBE_EICR_ECC)
2508 e_info(link, "Received unrecoverable ECC err, please "
2509 "reboot\n");
4f51bf70 2510 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2511 break;
2512 default:
2513 break;
2514 }
e8e26350 2515
0befdb3e 2516 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2517#ifdef CONFIG_IXGBE_PTP
2518 ixgbe_ptp_check_pps_event(adapter, eicr);
2519#endif
0befdb3e 2520
b9f6ed2b
AD		 2521 /* would disable interrupts here but EIAM disabled it */
2522 napi_schedule(&q_vector->napi);
9a799d71 2523
6af3b9eb
ET		 2524 /*
2525 * re-enable link(maybe) and non-queue interrupts, no flush.
2526 * ixgbe_poll will re-enable the queue interrupts
2527 */
6af3b9eb
ET		 2528 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2529 ixgbe_irq_enable(adapter, false, false);
2530
9a799d71
AK		 2531 return IRQ_HANDLED;
2532}
2533
2534/**
2535 * ixgbe_request_irq - initialize interrupts
2536 * @adapter: board private structure
2537 *
2538 * Attempts to configure interrupts using the best available
2539 * capabilities of the hardware and kernel.
2540 **/
021230d4 2541static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2542{
2543 struct net_device *netdev = adapter->netdev;
021230d4 2544 int err;
9a799d71 2545
4cc6df29 2546 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2547 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2548 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2549 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2550 netdev->name, adapter);
4cc6df29 2551 else
a0607fd3 2552 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2553 netdev->name, adapter);
9a799d71 2554
de88eeeb 2555 if (err)
396e799c 2556 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2557
9a799d71
AK		 2558 return err;
2559}
2560
2561static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2562{
49c7ffbe 2563 int vector;
9a799d71 2564
49c7ffbe
AD		 2565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2566 free_irq(adapter->pdev->irq, adapter);
2567 return;
2568 }
4cc6df29 2569
49c7ffbe
AD		 2570 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2571 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2572 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2573
49c7ffbe
AD		 2574 /* free only the irqs that were actually requested */
2575 if (!q_vector->rx.ring && !q_vector->tx.ring)
2576 continue;
207867f5 2577
49c7ffbe
AD		 2578 /* clear the affinity_mask in the IRQ descriptor */
2579 irq_set_affinity_hint(entry->vector, NULL);
2580
2581 free_irq(entry->vector, q_vector);
9a799d71 2582 }
49c7ffbe
AD		 2583
2584 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2585}
2586
22d5a71b
JB		 2587/**
2588 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2589 * @adapter: board private structure
2590 **/
2591static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2592{
bd508178
AD		 2593 switch (adapter->hw.mac.type) {
2594 case ixgbe_mac_82598EB:
835462fc 2595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2596 break;
2597 case ixgbe_mac_82599EB:
b93a2226 2598 case ixgbe_mac_X540:
835462fc
NS		 2599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2602 break;
2603 default:
2604 break;
22d5a71b
JB		 2605 }
2606 IXGBE_WRITE_FLUSH(&adapter->hw);
2607 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2608 int vector;
2609
2610 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2611 synchronize_irq(adapter->msix_entries[vector].vector);
2612
2613 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2614 } else {
2615 synchronize_irq(adapter->pdev->irq);
2616 }
2617}
2618
9a799d71
AK		 2619/**
2620 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2621 *
2622 **/
2623static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2624{
d5bf4f67 2625 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2626
d5bf4f67
ET		 2627 /* rx/tx vector */
2628 if (adapter->rx_itr_setting == 1)
2629 q_vector->itr = IXGBE_20K_ITR;
2630 else
2631 q_vector->itr = adapter->rx_itr_setting;
2632
2633 ixgbe_write_eitr(q_vector);
9a799d71 2634
e8e26350
PW		 2635 ixgbe_set_ivar(adapter, 0, 0, 0);
2636 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2637
396e799c 2638 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2639}
2640
43e69bf0
AD		 2641/**
2642 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2643 * @adapter: board private structure
2644 * @ring: structure containing ring specific data
2645 *
2646 * Configure the Tx descriptor ring after a reset.
2647 **/
84418e3b
AD		 2648void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2649 struct ixgbe_ring *ring)
43e69bf0
AD		 2650{
2651 struct ixgbe_hw *hw = &adapter->hw;
2652 u64 tdba = ring->dma;
2f1860b8 2653 int wait_loop = 10;
b88c6de2 2654 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2655 u8 reg_idx = ring->reg_idx;
43e69bf0 2656
2f1860b8 2657 /* disable queue to avoid issues while updating state */
b88c6de2 2658 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2659 IXGBE_WRITE_FLUSH(hw);
2660
43e69bf0 2661 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2662 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2663 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2664 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2665 ring->count * sizeof(union ixgbe_adv_tx_desc));
2666 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2667 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2668 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2669
b88c6de2
AD		 2670 /*
2671 * set WTHRESH to encourage burst writeback, it should not be set
2672 * higher than 1 when ITR is 0 as it could cause false TX hangs
2673 *
2674 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2675 * to or less than the number of on chip descriptors, which is
2676 * currently 40.
2677 */
e954b374 2678 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2679 txdctl |= (1 << 16); /* WTHRESH = 1 */
2680 else
2681 txdctl |= (8 << 16); /* WTHRESH = 8 */
2682
e954b374
AD		 2683 /*
2684 * Setting PTHRESH to 32 both improves performance
2685 * and avoids a TX hang with DFP enabled
2686 */
b88c6de2
AD		 2687 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2688 32; /* PTHRESH = 32 */
2f1860b8
AD		 2689
2690 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2691 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2692 adapter->atr_sample_rate) {
2693 ring->atr_sample_rate = adapter->atr_sample_rate;
2694 ring->atr_count = 0;
2695 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2696 } else {
2697 ring->atr_sample_rate = 0;
2698 }
2f1860b8 2699
c84d324c
JF		 2700 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2701
2f1860b8 2702 /* enable queue */
2f1860b8
AD		 2703 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2704
2705 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2706 if (hw->mac.type == ixgbe_mac_82598EB &&
2707 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2708 return;
2709
2710 /* poll to verify queue is enabled */
2711 do {
032b4325 2712 usleep_range(1000, 2000);
2f1860b8
AD		 2713 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2714 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2715 if (!wait_loop)
2716 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2717}
2718
120ff942
AD		 2719static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2720{
2721 struct ixgbe_hw *hw = &adapter->hw;
2722 u32 rttdcs;
72a32f1f 2723 u32 reg;
8b1c0b24 2724 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2725
2726 if (hw->mac.type == ixgbe_mac_82598EB)
2727 return;
2728
2729 /* disable the arbiter while setting MTQC */
2730 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2731 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2732 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2733
2734 /* set transmit pool layout */
8b1c0b24 2735 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2736 case (IXGBE_FLAG_SRIOV_ENABLED):
2737 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2738 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2739 break;
8b1c0b24
JF		 2740 default:
2741 if (!tcs)
2742 reg = IXGBE_MTQC_64Q_1PB;
2743 else if (tcs <= 4)
2744 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2745 else
2746 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2747
8b1c0b24 2748 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2749
8b1c0b24
JF		 2750 /* Enable Security TX Buffer IFG for multiple pb */
2751 if (tcs) {
2752 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2753 reg |= IXGBE_SECTX_DCB;
2754 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2755 }
120ff942
AD		 2756 break;
2757 }
2758
2759 /* re-enable the arbiter */
2760 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2761 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2762}
2763
9a799d71 2764/**
3a581073 2765 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2766 * @adapter: board private structure
2767 *
2768 * Configure the Tx unit of the MAC after a reset.
2769 **/
2770static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2771{
2f1860b8
AD		 2772 struct ixgbe_hw *hw = &adapter->hw;
2773 u32 dmatxctl;
43e69bf0 2774 u32 i;
9a799d71 2775
2f1860b8
AD		 2776 ixgbe_setup_mtqc(adapter);
2777
2778 if (hw->mac.type != ixgbe_mac_82598EB) {
2779 /* DMATXCTL.EN must be before Tx queues are enabled */
2780 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2781 dmatxctl |= IXGBE_DMATXCTL_TE;
2782 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2783 }
2784
9a799d71 2785 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2786 for (i = 0; i < adapter->num_tx_queues; i++)
2787 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2788}
2789
3ebe8fde
AD		 2790static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2791 struct ixgbe_ring *ring)
2792{
2793 struct ixgbe_hw *hw = &adapter->hw;
2794 u8 reg_idx = ring->reg_idx;
2795 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2796
2797 srrctl |= IXGBE_SRRCTL_DROP_EN;
2798
2799 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2800}
2801
2802static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *ring)
2804{
2805 struct ixgbe_hw *hw = &adapter->hw;
2806 u8 reg_idx = ring->reg_idx;
2807 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2808
2809 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2810
2811 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2812}
2813
2814#ifdef CONFIG_IXGBE_DCB
2815void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2816#else
2817static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2818#endif
2819{
2820 int i;
2821 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2822
2823 if (adapter->ixgbe_ieee_pfc)
2824 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2825
2826 /*
2827 * We should set the drop enable bit if:
2828 * SR-IOV is enabled
2829 * or
2830 * Number of Rx queues > 1 and flow control is disabled
2831 *
2832 * This allows us to avoid head of line blocking for security
2833 * and performance reasons.
2834 */
2835 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2836 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2837 for (i = 0; i < adapter->num_rx_queues; i++)
2838 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2839 } else {
2840 for (i = 0; i < adapter->num_rx_queues; i++)
2841 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2842 }
2843}
2844
e8e26350 2845#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2846
a6616b42 2847static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2848 struct ixgbe_ring *rx_ring)
cc41ac7c 2849{
cc41ac7c 2850 u32 srrctl;
bf29ee6c 2851 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2852
bd508178
AD		 2853 switch (adapter->hw.mac.type) {
2854 case ixgbe_mac_82598EB: {
2855 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2856 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2857 reg_idx = reg_idx & mask;
cc41ac7c 2858 }
bd508178
AD		 2859 break;
2860 case ixgbe_mac_82599EB:
b93a2226 2861 case ixgbe_mac_X540:
bd508178
AD		 2862 default:
2863 break;
2864 }
2865
bf29ee6c 2866 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2867
2868 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2869 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2870 if (adapter->num_vfs)
2871 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2872
afafd5b0
AD		 2873 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2874 IXGBE_SRRCTL_BSIZEHDR_MASK;
2875
f800326d
AD		 2876#if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2877 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2878#else
f800326d 2879 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2880#endif
f800326d 2881 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2882
bf29ee6c 2883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2884}
9a799d71 2885
05abb126 2886static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2887{
05abb126
AD		 2888 struct ixgbe_hw *hw = &adapter->hw;
2889 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2890 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2891 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2892 u32 mrqc = 0, reta = 0;
2893 u32 rxcsum;
2894 int i, j;
8b1c0b24 2895 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2896 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2897
2898 if (tcs)
2899 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2900
05abb126
AD		 2901 /* Fill out hash function seeds */
2902 for (i = 0; i < 10; i++)
2903 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2904
2905 /* Fill out redirection table */
2906 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2907 if (j == maxq)
05abb126
AD		 2908 j = 0;
2909 /* reta = 4-byte sliding window of
2910 * 0x00..(indices-1)(indices-1)00..etc. */
2911 reta = (reta << 8) | (j * 0x11);
2912 if ((i & 3) == 3)
2913 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2914 }
0cefafad 2915
05abb126
AD		 2916 /* Disable indicating checksum in descriptor, enables RSS hash */
2917 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2918 rxcsum |= IXGBE_RXCSUM_PCSD;
2919 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2920
8b1c0b24
JF		 2921 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2922 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2923 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2924 } else {
2925 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2926 | IXGBE_FLAG_SRIOV_ENABLED);
2927
2928 switch (mask) {
2929 case (IXGBE_FLAG_RSS_ENABLED):
2930 if (!tcs)
2931 mrqc = IXGBE_MRQC_RSSEN;
2932 else if (tcs <= 4)
2933 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2934 else
2935 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2936 break;
2937 case (IXGBE_FLAG_SRIOV_ENABLED):
2938 mrqc = IXGBE_MRQC_VMDQEN;
2939 break;
2940 default:
2941 break;
2942 }
0cefafad
JB		 2943 }
2944
05abb126
AD		 2945 /* Perform hash on these packet types */
2946 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2947 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2948 | IXGBE_MRQC_RSS_FIELD_IPV6
2949 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2950
ef6afc0c
AD		 2951 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2952 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2953 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2954 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2955
05abb126 2956 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2957}
2958
bb5a9ad2
NS		 2959/**
2960 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2961 * @adapter: address of board private structure
2962 * @index: index of ring to set
bb5a9ad2 2963 **/
082757af 2964static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2965 struct ixgbe_ring *ring)
bb5a9ad2 2966{
bb5a9ad2 2967 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2968 u32 rscctrl;
bf29ee6c 2969 u8 reg_idx = ring->reg_idx;
7367096a 2970
7d637bcc 2971 if (!ring_is_rsc_enabled(ring))
7367096a 2972 return;
bb5a9ad2 2973
7367096a 2974 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2975 rscctrl |= IXGBE_RSCCTL_RSCEN;
2976 /*
2977 * we must limit the number of descriptors so that the
2978 * total size of max desc * buf_len is not greater
642c680e 2979 * than 65536
bb5a9ad2 2980 */
f800326d
AD		 2981#if (PAGE_SIZE <= 8192)
2982 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2983#elif (PAGE_SIZE <= 16384)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
bb5a9ad2 2985#else
f800326d 2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
bb5a9ad2 2987#endif
7367096a 2988 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2989}
2990
9e10e045
AD		 2991#define IXGBE_MAX_RX_DESC_POLL 10
2992static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2993 struct ixgbe_ring *ring)
2994{
2995 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2996 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2997 u32 rxdctl;
bf29ee6c 2998 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2999
3000 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3001 if (hw->mac.type == ixgbe_mac_82598EB &&
3002 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3003 return;
3004
3005 do {
032b4325 3006 usleep_range(1000, 2000);
9e10e045
AD		 3007 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3008 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3009
3010 if (!wait_loop) {
3011 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3012 "the polling period\n", reg_idx);
3013 }
3014}
3015
2d39d576
YZ		 3016void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3017 struct ixgbe_ring *ring)
3018{
3019 struct ixgbe_hw *hw = &adapter->hw;
3020 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3021 u32 rxdctl;
3022 u8 reg_idx = ring->reg_idx;
3023
3024 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3025 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3026
3027 /* write value back with RXDCTL.ENABLE bit cleared */
3028 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3029
3030 if (hw->mac.type == ixgbe_mac_82598EB &&
3031 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3032 return;
3033
3034 /* the hardware may take up to 100us to really disable the rx queue */
3035 do {
3036 udelay(10);
3037 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3038 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3039
3040 if (!wait_loop) {
3041 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3042 "the polling period\n", reg_idx);
3043 }
3044}
3045
84418e3b
AD		 3046void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3047 struct ixgbe_ring *ring)
acd37177
AD		 3048{
3049 struct ixgbe_hw *hw = &adapter->hw;
3050 u64 rdba = ring->dma;
9e10e045 3051 u32 rxdctl;
bf29ee6c 3052 u8 reg_idx = ring->reg_idx;
acd37177 3053
9e10e045
AD		 3054 /* disable queue to avoid issues while updating state */
3055 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3056 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3057
acd37177
AD		 3058 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3059 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3060 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3061 ring->count * sizeof(union ixgbe_adv_rx_desc));
3062 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3063 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3064 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3065
3066 ixgbe_configure_srrctl(adapter, ring);
3067 ixgbe_configure_rscctl(adapter, ring);
3068
e9f98072
GR		 3069 /* If operating in IOV mode set RLPML for X540 */
3070 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3071 hw->mac.type == ixgbe_mac_X540) {
3072 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3073 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3074 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3075 }
3076
9e10e045
AD		 3077 if (hw->mac.type == ixgbe_mac_82598EB) {
3078 /*
3079 * enable cache line friendly hardware writes:
3080 * PTHRESH=32 descriptors (half the internal cache),
3081 * this also removes ugly rx_no_buffer_count increment
3082 * HTHRESH=4 descriptors (to minimize latency on fetch)
3083 * WTHRESH=8 burst writeback up to two cache lines
3084 */
3085 rxdctl &= ~0x3FFFFF;
3086 rxdctl |= 0x080420;
3087 }
3088
3089 /* enable receive descriptor ring */
3090 rxdctl |= IXGBE_RXDCTL_ENABLE;
3091 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3092
3093 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3094 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3095}
3096
48654521
AD		 3097static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3098{
3099 struct ixgbe_hw *hw = &adapter->hw;
3100 int p;
3101
3102 /* PSRTYPE must be initialized in non 82598 adapters */
3103 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3104 IXGBE_PSRTYPE_UDPHDR |
3105 IXGBE_PSRTYPE_IPV4HDR |
48654521 3106 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3107 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3108
3109 if (hw->mac.type == ixgbe_mac_82598EB)
3110 return;
3111
3112 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3113 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3114
3115 for (p = 0; p < adapter->num_rx_pools; p++)
3116 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3117 psrtype);
3118}
3119
f5b4a52e
AD		 3120static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3121{
3122 struct ixgbe_hw *hw = &adapter->hw;
3123 u32 gcr_ext;
3124 u32 vt_reg_bits;
3125 u32 reg_offset, vf_shift;
3126 u32 vmdctl;
de4c7f65 3127 int i;
f5b4a52e
AD		 3128
3129 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3130 return;
3131
3132 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3133 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3134 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3135 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3136
3137 vf_shift = adapter->num_vfs % 32;
4cd6923d 3138 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 3139
3140 /* Enable only the PF's pool for Tx/Rx */
3141 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3142 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3143 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3144 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3145 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3146
3147 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3148 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3149
3150 /*
3151 * Set up VF register offsets for selected VT Mode,
3152 * i.e. 32 or 64 VFs for SR-IOV
3153 */
3154 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3155 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3156 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3158
3159 /* enable Tx loopback for VF/PF communication */
3160 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3161 /* Enable MAC Anti-Spoofing */
a1cbb15c 3162 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 3163 (adapter->num_vfs != 0),
a985b6c3 3164 adapter->num_vfs);
de4c7f65
GR		 3165 /* For VFs that have spoof checking turned off */
3166 for (i = 0; i < adapter->num_vfs; i++) {
3167 if (!adapter->vfinfo[i].spoofchk_enabled)
3168 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3169 }
f5b4a52e
AD		 3170}
3171
477de6ed 3172static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3173{
9a799d71
AK		 3174 struct ixgbe_hw *hw = &adapter->hw;
3175 struct net_device *netdev = adapter->netdev;
3176 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3177 struct ixgbe_ring *rx_ring;
3178 int i;
3179 u32 mhadd, hlreg0;
48654521 3180
63f39bd1 3181#ifdef IXGBE_FCOE
477de6ed
AD		 3182 /* adjust max frame to be able to do baby jumbo for FCoE */
3183 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3184 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3185 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3186
477de6ed
AD		 3187#endif /* IXGBE_FCOE */
3188 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3189 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3190 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3191 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3192
3193 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3194 }
3195
919e78a6
AD		 3196 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3197 max_frame += VLAN_HLEN;
3198
477de6ed
AD		 3199 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3200 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3201 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3202 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3203
0cefafad
JB		 3204 /*
3205 * Setup the HW Rx Head and Tail Descriptor Pointers and
3206 * the Base and Length of the Rx Descriptor Ring
3207 */
9a799d71 3208 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3209 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3210 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3211 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3212 else
7d637bcc 3213 clear_ring_rsc_enabled(rx_ring);
477de6ed 3214 }
477de6ed
AD		 3215}
3216
7367096a
AD		 3217static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3218{
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3221
3222 switch (hw->mac.type) {
3223 case ixgbe_mac_82598EB:
3224 /*
3225 * For VMDq support of different descriptor types or
3226 * buffer sizes through the use of multiple SRRCTL
3227 * registers, RDRXCTL.MVMEN must be set to 1
3228 *
3229 * also, the manual doesn't mention it clearly but DCA hints
3230 * will only use queue 0's tags unless this bit is set. Side
3231 * effects of setting this bit are only that SRRCTL must be
3232 * fully programmed [0..15]
3233 */
3234 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3235 break;
3236 case ixgbe_mac_82599EB:
b93a2226 3237 case ixgbe_mac_X540:
7367096a
AD		 3238 /* Disable RSC for ACK packets */
3239 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3240 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3241 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3242 /* hardware requires some bits to be set by default */
3243 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3244 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3245 break;
3246 default:
3247 /* We should do nothing since we don't know this hardware */
3248 return;
3249 }
3250
3251 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3252}
3253
477de6ed
AD		 3254/**
3255 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3256 * @adapter: board private structure
3257 *
3258 * Configure the Rx unit of the MAC after a reset.
3259 **/
3260static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3261{
3262 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3263 int i;
3264 u32 rxctrl;
477de6ed
AD		 3265
3266 /* disable receives while setting up the descriptors */
3267 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3268 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3269
3270 ixgbe_setup_psrtype(adapter);
7367096a 3271 ixgbe_setup_rdrxctl(adapter);
477de6ed 3272
9e10e045 3273 /* Program registers for the distribution of queues */
f5b4a52e 3274 ixgbe_setup_mrqc(adapter);
f5b4a52e 3275
477de6ed
AD		 3276 /* set_rx_buffer_len must be called before ring initialization */
3277 ixgbe_set_rx_buffer_len(adapter);
3278
3279 /*
3280 * Setup the HW Rx Head and Tail Descriptor Pointers and
3281 * the Base and Length of the Rx Descriptor Ring
3282 */
9e10e045
AD		 3283 for (i = 0; i < adapter->num_rx_queues; i++)
3284 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3285
9e10e045
AD		 3286 /* disable drop enable for 82598 parts */
3287 if (hw->mac.type == ixgbe_mac_82598EB)
3288 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3289
3290 /* enable all receives */
3291 rxctrl |= IXGBE_RXCTRL_RXEN;
3292 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3293}
3294
8e586137 3295static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3296{
3297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3298 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3299 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3300
3301 /* add VID to filter table */
1ada1b1b 3302 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3303 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3304
3305 return 0;
068c89b0
DS		 3306}
3307
8e586137 3308static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3309{
3310 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3311 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3312 int pool_ndx = adapter->num_vfs;
068c89b0 3313
068c89b0 3314 /* remove VID from filter table */
1ada1b1b 3315 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3316 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3317
3318 return 0;
068c89b0
DS		 3319}
3320
5f6c0181
JB		 3321/**
3322 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3323 * @adapter: driver data
3324 */
3325static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3326{
3327 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3328 u32 vlnctrl;
3329
3330 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3331 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3332 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3333}
3334
3335/**
3336 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3337 * @adapter: driver data
3338 */
3339static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3340{
3341 struct ixgbe_hw *hw = &adapter->hw;
3342 u32 vlnctrl;
3343
3344 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3345 vlnctrl |= IXGBE_VLNCTRL_VFE;
3346 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3347 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3348}
3349
3350/**
3351 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3352 * @adapter: driver data
3353 */
3354static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3355{
3356 struct ixgbe_hw *hw = &adapter->hw;
3357 u32 vlnctrl;
5f6c0181
JB		 3358 int i, j;
3359
3360 switch (hw->mac.type) {
3361 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3362 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3363 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3364 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3365 break;
3366 case ixgbe_mac_82599EB:
b93a2226 3367 case ixgbe_mac_X540:
5f6c0181
JB		 3368 for (i = 0; i < adapter->num_rx_queues; i++) {
3369 j = adapter->rx_ring[i]->reg_idx;
3370 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3371 vlnctrl &= ~IXGBE_RXDCTL_VME;
3372 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3373 }
3374 break;
3375 default:
3376 break;
3377 }
3378}
3379
3380/**
f62bbb5e 3381 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3382 * @adapter: driver data
3383 */
f62bbb5e 3384static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3385{
3386 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3387 u32 vlnctrl;
5f6c0181
JB		 3388 int i, j;
3389
3390 switch (hw->mac.type) {
3391 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3392 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3393 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3394 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3395 break;
3396 case ixgbe_mac_82599EB:
b93a2226 3397 case ixgbe_mac_X540:
5f6c0181
JB		 3398 for (i = 0; i < adapter->num_rx_queues; i++) {
3399 j = adapter->rx_ring[i]->reg_idx;
3400 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3401 vlnctrl |= IXGBE_RXDCTL_VME;
3402 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3403 }
3404 break;
3405 default:
3406 break;
3407 }
3408}
3409
9a799d71
AK		 3410static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3411{
f62bbb5e 3412 u16 vid;
9a799d71 3413
f62bbb5e
JG		 3414 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3415
3416 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3417 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3418}
3419
2850062a
AD		 3420/**
3421 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3422 * @netdev: network interface device structure
3423 *
3424 * Writes unicast address list to the RAR table.
3425 * Returns: -ENOMEM on failure/insufficient address space
3426 * 0 on no addresses written
3427 * X on writing X addresses to the RAR table
3428 **/
3429static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3430{
3431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3432 struct ixgbe_hw *hw = &adapter->hw;
3433 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3434 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3435 int count = 0;
3436
3437 /* return ENOMEM indicating insufficient memory for addresses */
3438 if (netdev_uc_count(netdev) > rar_entries)
3439 return -ENOMEM;
3440
3441 if (!netdev_uc_empty(netdev) && rar_entries) {
3442 struct netdev_hw_addr *ha;
3443 /* return error if we do not support writing to RAR table */
3444 if (!hw->mac.ops.set_rar)
3445 return -ENOMEM;
3446
3447 netdev_for_each_uc_addr(ha, netdev) {
3448 if (!rar_entries)
3449 break;
3450 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3451 vfn, IXGBE_RAH_AV);
3452 count++;
3453 }
3454 }
3455 /* write the addresses in reverse order to avoid write combining */
3456 for (; rar_entries > 0 ; rar_entries--)
3457 hw->mac.ops.clear_rar(hw, rar_entries);
3458
3459 return count;
3460}
3461
9a799d71 3462/**
2c5645cf 3463 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3464 * @netdev: network interface device structure
3465 *
2c5645cf
CL		 3466 * The set_rx_method entry point is called whenever the unicast/multicast
3467 * address list or the network interface flags are updated. This routine is
3468 * responsible for configuring the hardware for proper unicast, multicast and
3469 * promiscuous mode.
9a799d71 3470 **/
7f870475 3471void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3472{
3473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3474 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3475 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3476 int count;
9a799d71
AK		 3477
3478 /* Check for Promiscuous and All Multicast modes */
3479
3480 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3481
f5dc442b 3482 /* set all bits that we expect to always be set */
3f2d1c0f 3483 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3484 fctrl |= IXGBE_FCTRL_BAM;
3485 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3486 fctrl |= IXGBE_FCTRL_PMCF;
3487
2850062a
AD		 3488 /* clear the bits we are changing the status of */
3489 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3490
9a799d71 3491 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3492 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3493 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3494 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3495 /* don't hardware filter vlans in promisc mode */
3496 ixgbe_vlan_filter_disable(adapter);
9a799d71 3497 } else {
746b9f02
PM		 3498 if (netdev->flags & IFF_ALLMULTI) {
3499 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3500 vmolr |= IXGBE_VMOLR_MPE;
3501 } else {
3502 /*
3503 * Write addresses to the MTA, if the attempt fails
25985edc 3504 * then we should just turn on promiscuous mode so
2850062a
AD		 3505 * that we can at least receive multicast traffic
3506 */
3507 hw->mac.ops.update_mc_addr_list(hw, netdev);
3508 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3509 }
5f6c0181 3510 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3511 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3512 }
3513
3514 /*
3515 * Write addresses to available RAR registers, if there is not
3516 * sufficient space to store all the addresses then enable
3517 * unicast promiscuous mode
3518 */
3519 count = ixgbe_write_uc_addr_list(netdev);
3520 if (count < 0) {
3521 fctrl |= IXGBE_FCTRL_UPE;
3522 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3523 }
3524
2850062a 3525 if (adapter->num_vfs) {
1cdd1ec8 3526 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3527 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3528 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3529 IXGBE_VMOLR_ROPE);
3530 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3531 }
3532
3f2d1c0f
BG		 3533 /* This is useful for sniffing bad packets. */
3534 if (adapter->netdev->features & NETIF_F_RXALL) {
3535 /* UPE and MPE will be handled by normal PROMISC logic
3536 * in e1000e_set_rx_mode */
3537 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3538 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3539 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3540
3541 fctrl &= ~(IXGBE_FCTRL_DPF);
3542 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3543 }
3544
2850062a 3545 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3546
3547 if (netdev->features & NETIF_F_HW_VLAN_RX)
3548 ixgbe_vlan_strip_enable(adapter);
3549 else
3550 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3551}
3552
021230d4
AV		 3553static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3554{
3555 int q_idx;
021230d4 3556
49c7ffbe
AD		 3557 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3558 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3559}
3560
3561static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3562{
3563 int q_idx;
021230d4 3564
49c7ffbe
AD		 3565 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3566 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3567}
3568
7a6b6f51 3569#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3570/**
2f90b865
AD		 3571 * ixgbe_configure_dcb - Configure DCB hardware
3572 * @adapter: ixgbe adapter struct
3573 *
3574 * This is called by the driver on open to configure the DCB hardware.
3575 * This is also called by the gennetlink interface when reconfiguring
3576 * the DCB state.
3577 */
3578static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3579{
3580 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3581 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3582
67ebd791
AD		 3583 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3584 if (hw->mac.type == ixgbe_mac_82598EB)
3585 netif_set_gso_max_size(adapter->netdev, 65536);
3586 return;
3587 }
3588
3589 if (hw->mac.type == ixgbe_mac_82598EB)
3590 netif_set_gso_max_size(adapter->netdev, 32768);
3591
2f90b865 3592 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3593
971060b1 3594#ifdef IXGBE_FCOE
b120818e
JF		 3595 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3596 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3597#endif
b120818e
JF		 3598
3599 /* reconfigure the hardware */
3600 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3601 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3602 DCB_TX_CONFIG);
3603 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3604 DCB_RX_CONFIG);
3605 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3606 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3607 ixgbe_dcb_hw_ets(&adapter->hw,
3608 adapter->ixgbe_ieee_ets,
3609 max_frame);
3610 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3611 adapter->ixgbe_ieee_pfc->pfc_en,
3612 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3613 }
8187cd48
JF		 3614
3615 /* Enable RSS Hash per TC */
3616 if (hw->mac.type != ixgbe_mac_82598EB) {
3617 int i;
3618 u32 reg = 0;
3619
3620 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3621 u8 msb = 0;
3622 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3623
3624 while (cnt >>= 1)
3625 msb++;
3626
3627 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3628 }
3629 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3630 }
2f90b865 3631}
9da712d2
JF		 3632#endif
3633
3634/* Additional bittime to account for IXGBE framing */
3635#define IXGBE_ETH_FRAMING 20
3636
49ce9c2c 3637/**
9da712d2
JF		 3638 * ixgbe_hpbthresh - calculate high water mark for flow control
3639 *
3640 * @adapter: board private structure to calculate for
49ce9c2c 3641 * @pb: packet buffer to calculate
9da712d2
JF		 3642 */
3643static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3644{
3645 struct ixgbe_hw *hw = &adapter->hw;
3646 struct net_device *dev = adapter->netdev;
3647 int link, tc, kb, marker;
3648 u32 dv_id, rx_pba;
3649
3650 /* Calculate max LAN frame size */
3651 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3652
3653#ifdef IXGBE_FCOE
3654 /* FCoE traffic class uses FCOE jumbo frames */
3655 if (dev->features & NETIF_F_FCOE_MTU) {
3656 int fcoe_pb = 0;
2f90b865 3657
9da712d2
JF		 3658#ifdef CONFIG_IXGBE_DCB
3659 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3660
3661#endif
3662 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3663 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3664 }
2f90b865 3665#endif
80605c65 3666
9da712d2
JF		 3667 /* Calculate delay value for device */
3668 switch (hw->mac.type) {
3669 case ixgbe_mac_X540:
3670 dv_id = IXGBE_DV_X540(link, tc);
3671 break;
3672 default:
3673 dv_id = IXGBE_DV(link, tc);
3674 break;
3675 }
3676
3677 /* Loopback switch introduces additional latency */
3678 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3679 dv_id += IXGBE_B2BT(tc);
3680
3681 /* Delay value is calculated in bit times convert to KB */
3682 kb = IXGBE_BT2KB(dv_id);
3683 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3684
3685 marker = rx_pba - kb;
3686
3687 /* It is possible that the packet buffer is not large enough
3688 * to provide required headroom. In this case throw an error
3689 * to user and a do the best we can.
3690 */
3691 if (marker < 0) {
3692 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3693 "headroom to support flow control."
3694 "Decrease MTU or number of traffic classes\n", pb);
3695 marker = tc + 1;
3696 }
3697
3698 return marker;
3699}
3700
49ce9c2c 3701/**
9da712d2
JF		 3702 * ixgbe_lpbthresh - calculate low water mark for for flow control
3703 *
3704 * @adapter: board private structure to calculate for
49ce9c2c 3705 * @pb: packet buffer to calculate
9da712d2
JF		 3706 */
3707static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3708{
3709 struct ixgbe_hw *hw = &adapter->hw;
3710 struct net_device *dev = adapter->netdev;
3711 int tc;
3712 u32 dv_id;
3713
3714 /* Calculate max LAN frame size */
3715 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3716
3717 /* Calculate delay value for device */
3718 switch (hw->mac.type) {
3719 case ixgbe_mac_X540:
3720 dv_id = IXGBE_LOW_DV_X540(tc);
3721 break;
3722 default:
3723 dv_id = IXGBE_LOW_DV(tc);
3724 break;
3725 }
3726
3727 /* Delay value is calculated in bit times convert to KB */
3728 return IXGBE_BT2KB(dv_id);
3729}
3730
3731/*
3732 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3733 */
3734static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3735{
3736 struct ixgbe_hw *hw = &adapter->hw;
3737 int num_tc = netdev_get_num_tc(adapter->netdev);
3738 int i;
3739
3740 if (!num_tc)
3741 num_tc = 1;
3742
3743 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3744
3745 for (i = 0; i < num_tc; i++) {
3746 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3747
3748 /* Low water marks must not be larger than high water marks */
3749 if (hw->fc.low_water > hw->fc.high_water[i])
3750 hw->fc.low_water = 0;
3751 }
3752}
3753
80605c65
JF		 3754static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3755{
80605c65 3756 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3757 int hdrm;
3758 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3759
3760 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3761 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3762 hdrm = 32 << adapter->fdir_pballoc;
3763 else
3764 hdrm = 0;
80605c65 3765
f7e1027f 3766 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3767 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3768}
3769
e4911d57
AD		 3770static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3771{
3772 struct ixgbe_hw *hw = &adapter->hw;
3773 struct hlist_node *node, *node2;
3774 struct ixgbe_fdir_filter *filter;
3775
3776 spin_lock(&adapter->fdir_perfect_lock);
3777
3778 if (!hlist_empty(&adapter->fdir_filter_list))
3779 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3780
3781 hlist_for_each_entry_safe(filter, node, node2,
3782 &adapter->fdir_filter_list, fdir_node) {
3783 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3784 &filter->filter,
3785 filter->sw_idx,
3786 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3787 IXGBE_FDIR_DROP_QUEUE :
3788 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3789 }
3790
3791 spin_unlock(&adapter->fdir_perfect_lock);
3792}
3793
9a799d71
AK		 3794static void ixgbe_configure(struct ixgbe_adapter *adapter)
3795{
d2f5e7f3
AS		 3796 struct ixgbe_hw *hw = &adapter->hw;
3797
80605c65 3798 ixgbe_configure_pb(adapter);
7a6b6f51 3799#ifdef CONFIG_IXGBE_DCB
67ebd791 3800 ixgbe_configure_dcb(adapter);
2f90b865 3801#endif
9a799d71 3802
4c1d7b4b 3803 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3804 ixgbe_restore_vlan(adapter);
3805
eacd73f7
YZ		 3806#ifdef IXGBE_FCOE
3807 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3808 ixgbe_configure_fcoe(adapter);
3809
3810#endif /* IXGBE_FCOE */
d2f5e7f3
AS		 3811
3812 switch (hw->mac.type) {
3813 case ixgbe_mac_82599EB:
3814 case ixgbe_mac_X540:
3815 hw->mac.ops.disable_rx_buff(hw);
3816 break;
3817 default:
3818 break;
3819 }
3820
c4cf55e5 3821 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3822 ixgbe_init_fdir_signature_82599(&adapter->hw,
3823 adapter->fdir_pballoc);
e4911d57
AD		 3824 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3825 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3826 adapter->fdir_pballoc);
3827 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3828 }
4c1d7b4b 3829
d2f5e7f3
AS		 3830 switch (hw->mac.type) {
3831 case ixgbe_mac_82599EB:
3832 case ixgbe_mac_X540:
3833 hw->mac.ops.enable_rx_buff(hw);
3834 break;
3835 default:
3836 break;
3837 }
3838
933d41f1 3839 ixgbe_configure_virtualization(adapter);
c4cf55e5 3840
9a799d71
AK		 3841 ixgbe_configure_tx(adapter);
3842 ixgbe_configure_rx(adapter);
9a799d71
AK		 3843}
3844
e8e26350
PW		 3845static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3846{
3847 switch (hw->phy.type) {
3848 case ixgbe_phy_sfp_avago:
3849 case ixgbe_phy_sfp_ftl:
3850 case ixgbe_phy_sfp_intel:
3851 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3852 case ixgbe_phy_sfp_passive_tyco:
3853 case ixgbe_phy_sfp_passive_unknown:
3854 case ixgbe_phy_sfp_active_unknown:
3855 case ixgbe_phy_sfp_ftl_active:
e8e26350 3856 return true;
8917b447
AD		 3857 case ixgbe_phy_nl:
3858 if (hw->mac.type == ixgbe_mac_82598EB)
3859 return true;
e8e26350
PW		 3860 default:
3861 return false;
3862 }
3863}
3864
0ecc061d 3865/**
e8e26350
PW		 3866 * ixgbe_sfp_link_config - set up SFP+ link
3867 * @adapter: pointer to private adapter struct
3868 **/
3869static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3870{
7086400d 3871 /*
52f33af8 3872 * We are assuming the worst case scenario here, and that
7086400d
AD		 3873 * is that an SFP was inserted/removed after the reset
3874 * but before SFP detection was enabled. As such the best
3875 * solution is to just start searching as soon as we start
3876 */
3877 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3878 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3879
7086400d 3880 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3881}
3882
3883/**
3884 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3885 * @hw: pointer to private hardware struct
3886 *
3887 * Returns 0 on success, negative on failure
3888 **/
e8e26350 3889static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3890{
3891 u32 autoneg;
8620a103 3892 bool negotiation, link_up = false;
0ecc061d
PWJ		 3893 u32 ret = IXGBE_ERR_LINK_SETUP;
3894
3895 if (hw->mac.ops.check_link)
3896 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3897
3898 if (ret)
3899 goto link_cfg_out;
3900
0b0c2b31
ET		 3901 autoneg = hw->phy.autoneg_advertised;
3902 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3903 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3904 &negotiation);
0ecc061d
PWJ		 3905 if (ret)
3906 goto link_cfg_out;
3907
8620a103
MC		 3908 if (hw->mac.ops.setup_link)
3909 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3910link_cfg_out:
3911 return ret;
3912}
3913
a34bcfff 3914static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3915{
9a799d71 3916 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3917 u32 gpie = 0;
9a799d71 3918
9b471446 3919 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3920 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3921 IXGBE_GPIE_OCD;
3922 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3923 /*
3924 * use EIAM to auto-mask when MSI-X interrupt is asserted
3925 * this saves a register write for every interrupt
3926 */
3927 switch (hw->mac.type) {
3928 case ixgbe_mac_82598EB:
3929 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3930 break;
9b471446 3931 case ixgbe_mac_82599EB:
b93a2226
DS		 3932 case ixgbe_mac_X540:
3933 default:
9b471446
JB		 3934 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3935 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3936 break;
3937 }
3938 } else {
021230d4
AV		 3939 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3940 * specifically only auto mask tx and rx interrupts */
3941 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3942 }
9a799d71 3943
a34bcfff
AD		 3944 /* XXX: to interrupt immediately for EICS writes, enable this */
3945 /* gpie |= IXGBE_GPIE_EIMEN; */
3946
3947 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3948 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3949 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3950 }
3951
5fdd31f9 3952 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3953 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3954 switch (adapter->hw.mac.type) {
3955 case ixgbe_mac_82599EB:
3956 gpie |= IXGBE_SDP0_GPIEN;
3957 break;
3958 case ixgbe_mac_X540:
3959 gpie |= IXGBE_EIMS_TS;
3960 break;
3961 default:
3962 break;
3963 }
3964 }
5fdd31f9 3965
a34bcfff
AD		 3966 /* Enable fan failure interrupt */
3967 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3968 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3969
2698b208 3970 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3971 gpie |= IXGBE_SDP1_GPIEN;
3972 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3973 }
a34bcfff
AD		 3974
3975 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3976}
3977
c7ccde0f 3978static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3979{
3980 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3981 int err;
a34bcfff
AD		 3982 u32 ctrl_ext;
3983
3984 ixgbe_get_hw_control(adapter);
3985 ixgbe_setup_gpie(adapter);
e8e26350 3986
9a799d71
AK		 3987 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3988 ixgbe_configure_msix(adapter);
3989 else
3990 ixgbe_configure_msi_and_legacy(adapter);
3991
c6ecf39a
DS		 3992 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3993 if (hw->mac.ops.enable_tx_laser &&
3994 ((hw->phy.multispeed_fiber) ||
9f911707 3995 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3996 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3997 hw->mac.ops.enable_tx_laser(hw);
3998
9a799d71 3999 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4000 ixgbe_napi_enable_all(adapter);
4001
73c4b7cd
AD		 4002 if (ixgbe_is_sfp(hw)) {
4003 ixgbe_sfp_link_config(adapter);
4004 } else {
4005 err = ixgbe_non_sfp_link_config(hw);
4006 if (err)
4007 e_err(probe, "link_config FAILED %d\n", err);
4008 }
4009
021230d4
AV		 4010 /* clear any pending interrupts, may auto mask */
4011 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4012 ixgbe_irq_enable(adapter, true, true);
9a799d71 4013
bf069c97
DS		 4014 /*
4015 * If this adapter has a fan, check to see if we had a failure
4016 * before we enabled the interrupt.
4017 */
4018 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4019 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4020 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4021 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4022 }
4023
1da100bb 4024 /* enable transmits */
477de6ed 4025 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4026
9a799d71
AK		 4027 /* bring the link up in the watchdog, this could race with our first
4028 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4029 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4030 adapter->link_check_timeout = jiffies;
7086400d 4031 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4032
4033 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4034 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4035 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4036 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4037}
4038
d4f80882
AV		 4039void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4040{
4041 WARN_ON(in_interrupt());
7086400d
AD		 4042 /* put off any impending NetWatchDogTimeout */
4043 adapter->netdev->trans_start = jiffies;
4044
d4f80882 4045 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4046 usleep_range(1000, 2000);
d4f80882 4047 ixgbe_down(adapter);
5809a1ae
GR		 4048 /*
4049 * If SR-IOV enabled then wait a bit before bringing the adapter
4050 * back up to give the VFs time to respond to the reset. The
4051 * two second wait is based upon the watchdog timer cycle in
4052 * the VF driver.
4053 */
4054 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4055 msleep(2000);
d4f80882
AV		 4056 ixgbe_up(adapter);
4057 clear_bit(__IXGBE_RESETTING, &adapter->state);
4058}
4059
c7ccde0f 4060void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4061{
4062 /* hardware has been reset, we need to reload some things */
4063 ixgbe_configure(adapter);
4064
c7ccde0f 4065 ixgbe_up_complete(adapter);
9a799d71
AK		 4066}
4067
4068void ixgbe_reset(struct ixgbe_adapter *adapter)
4069{
c44ade9e 4070 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4071 int err;
4072
7086400d
AD		 4073 /* lock SFP init bit to prevent race conditions with the watchdog */
4074 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4075 usleep_range(1000, 2000);
4076
4077 /* clear all SFP and link config related flags while holding SFP_INIT */
4078 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4079 IXGBE_FLAG2_SFP_NEEDS_RESET);
4080 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4081
8ca783ab 4082 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4083 switch (err) {
4084 case 0:
4085 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4086 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4087 break;
4088 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4089 e_dev_err("master disable timed out\n");
da4dd0f7 4090 break;
794caeb2
PWJ		 4091 case IXGBE_ERR_EEPROM_VERSION:
4092 /* We are running on a pre-production device, log a warning */
849c4542 4093 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4094 "Please be aware there may be issues associated with "
849c4542
ET		 4095 "your hardware. If you are experiencing problems "
4096 "please contact your Intel or hardware "
4097 "representative who provided you with this "
4098 "hardware.\n");
794caeb2 4099 break;
da4dd0f7 4100 default:
849c4542 4101 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4102 }
9a799d71 4103
7086400d
AD		 4104 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4105
9a799d71 4106 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4107 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4108 IXGBE_RAH_AV);
9a799d71
AK		 4109}
4110
f800326d
AD		 4111/**
4112 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4113 * @rx_ring: ring to setup
4114 *
4115 * On many IA platforms the L1 cache has a critical stride of 4K, this
4116 * results in each receive buffer starting in the same cache set. To help
4117 * reduce the pressure on this cache set we can interleave the offsets so
4118 * that only every other buffer will be in the same cache set.
4119 **/
4120static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4121{
4122 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4123 u16 i;
4124
4125 for (i = 0; i < rx_ring->count; i += 2) {
4126 rx_buffer[0].page_offset = 0;
4127 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4128 rx_buffer = &rx_buffer[2];
4129 }
4130}
4131
9a799d71
AK		 4132/**
4133 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4134 * @rx_ring: ring to free buffers from
4135 **/
b6ec895e 4136static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4137{
b6ec895e 4138 struct device *dev = rx_ring->dev;
9a799d71 4139 unsigned long size;
b6ec895e 4140 u16 i;
9a799d71 4141
84418e3b
AD		 4142 /* ring already cleared, nothing to do */
4143 if (!rx_ring->rx_buffer_info)
4144 return;
9a799d71 4145
84418e3b 4146 /* Free all the Rx ring sk_buffs */
9a799d71 4147 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4148 struct ixgbe_rx_buffer *rx_buffer;
4149
4150 rx_buffer = &rx_ring->rx_buffer_info[i];
4151 if (rx_buffer->skb) {
4152 struct sk_buff *skb = rx_buffer->skb;
4153 if (IXGBE_CB(skb)->page_released) {
4154 dma_unmap_page(dev,
4155 IXGBE_CB(skb)->dma,
4156 ixgbe_rx_bufsz(rx_ring),
4157 DMA_FROM_DEVICE);
4158 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4159 }
4160 dev_kfree_skb(skb);
9a799d71 4161 }
f800326d
AD		 4162 rx_buffer->skb = NULL;
4163 if (rx_buffer->dma)
4164 dma_unmap_page(dev, rx_buffer->dma,
4165 ixgbe_rx_pg_size(rx_ring),
4166 DMA_FROM_DEVICE);
4167 rx_buffer->dma = 0;
4168 if (rx_buffer->page)
dd411ec4
AD		 4169 __free_pages(rx_buffer->page,
4170 ixgbe_rx_pg_order(rx_ring));
f800326d 4171 rx_buffer->page = NULL;
9a799d71
AK		 4172 }
4173
4174 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4175 memset(rx_ring->rx_buffer_info, 0, size);
4176
f800326d
AD		 4177 ixgbe_init_rx_page_offset(rx_ring);
4178
9a799d71
AK		 4179 /* Zero out the descriptor ring */
4180 memset(rx_ring->desc, 0, rx_ring->size);
4181
f800326d 4182 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4183 rx_ring->next_to_clean = 0;
4184 rx_ring->next_to_use = 0;
9a799d71
AK		 4185}
4186
4187/**
4188 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4189 * @tx_ring: ring to be cleaned
4190 **/
b6ec895e 4191static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4192{
4193 struct ixgbe_tx_buffer *tx_buffer_info;
4194 unsigned long size;
b6ec895e 4195 u16 i;
9a799d71 4196
84418e3b
AD		 4197 /* ring already cleared, nothing to do */
4198 if (!tx_ring->tx_buffer_info)
4199 return;
9a799d71 4200
84418e3b 4201 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4202 for (i = 0; i < tx_ring->count; i++) {
4203 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4204 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4205 }
4206
dad8a3b3
JF		 4207 netdev_tx_reset_queue(txring_txq(tx_ring));
4208
9a799d71
AK		 4209 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4210 memset(tx_ring->tx_buffer_info, 0, size);
4211
4212 /* Zero out the descriptor ring */
4213 memset(tx_ring->desc, 0, tx_ring->size);
4214
4215 tx_ring->next_to_use = 0;
4216 tx_ring->next_to_clean = 0;
9a799d71
AK		 4217}
4218
4219/**
021230d4 4220 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4221 * @adapter: board private structure
4222 **/
021230d4 4223static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4224{
4225 int i;
4226
021230d4 4227 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4228 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4229}
4230
4231/**
021230d4 4232 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4233 * @adapter: board private structure
4234 **/
021230d4 4235static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4236{
4237 int i;
4238
021230d4 4239 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4240 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4241}
4242
e4911d57
AD		 4243static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4244{
4245 struct hlist_node *node, *node2;
4246 struct ixgbe_fdir_filter *filter;
4247
4248 spin_lock(&adapter->fdir_perfect_lock);
4249
4250 hlist_for_each_entry_safe(filter, node, node2,
4251 &adapter->fdir_filter_list, fdir_node) {
4252 hlist_del(&filter->fdir_node);
4253 kfree(filter);
4254 }
4255 adapter->fdir_filter_count = 0;
4256
4257 spin_unlock(&adapter->fdir_perfect_lock);
4258}
4259
9a799d71
AK		 4260void ixgbe_down(struct ixgbe_adapter *adapter)
4261{
4262 struct net_device *netdev = adapter->netdev;
7f821875 4263 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4264 u32 rxctrl;
bf29ee6c 4265 int i;
9a799d71
AK		 4266
4267 /* signal that we are down to the interrupt handler */
4268 set_bit(__IXGBE_DOWN, &adapter->state);
4269
4270 /* disable receives */
7f821875
JB		 4271 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4272 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4273
2d39d576
YZ		 4274 /* disable all enabled rx queues */
4275 for (i = 0; i < adapter->num_rx_queues; i++)
4276 /* this call also flushes the previous write */
4277 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4278
032b4325 4279 usleep_range(10000, 20000);
9a799d71 4280
7f821875
JB		 4281 netif_tx_stop_all_queues(netdev);
4282
7086400d 4283 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4284 netif_carrier_off(netdev);
4285 netif_tx_disable(netdev);
4286
4287 ixgbe_irq_disable(adapter);
4288
4289 ixgbe_napi_disable_all(adapter);
4290
d034acf1
AD		 4291 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4292 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4293 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4294
4295 del_timer_sync(&adapter->service_timer);
4296
34cecbbf 4297 if (adapter->num_vfs) {
8e34d1aa
AD		 4298 /* Clear EITR Select mapping */
4299 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4300
4301 /* Mark all the VFs as inactive */
4302 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4303 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4304
34cecbbf
AD		 4305 /* ping all the active vfs to let them know we are going down */
4306 ixgbe_ping_all_vfs(adapter);
4307
4308 /* Disable all VFTE/VFRE TX/RX */
4309 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4310 }
4311
7f821875
JB		 4312 /* disable transmits in the hardware now that interrupts are off */
4313 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4314 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4315 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4316 }
34cecbbf
AD		 4317
4318 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4319 switch (hw->mac.type) {
4320 case ixgbe_mac_82599EB:
b93a2226 4321 case ixgbe_mac_X540:
88512539 4322 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4323 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4324 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4325 break;
4326 default:
4327 break;
4328 }
7f821875 4329
6f4a0e45
PL		 4330 if (!pci_channel_offline(adapter->pdev))
4331 ixgbe_reset(adapter);
c6ecf39a
DS		 4332
4333 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4334 if (hw->mac.ops.disable_tx_laser &&
4335 ((hw->phy.multispeed_fiber) ||
9f911707 4336 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4337 (hw->mac.type == ixgbe_mac_82599EB))))
4338 hw->mac.ops.disable_tx_laser(hw);
4339
9a799d71
AK		 4340 ixgbe_clean_all_tx_rings(adapter);
4341 ixgbe_clean_all_rx_rings(adapter);
4342
5dd2d332 4343#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4344 /* since we reset the hardware DCA settings were cleared */
e35ec126 4345 ixgbe_setup_dca(adapter);
96b0e0f6 4346#endif
9a799d71
AK		 4347}
4348
9a799d71
AK		 4349/**
4350 * ixgbe_tx_timeout - Respond to a Tx Hang
4351 * @netdev: network interface device structure
4352 **/
4353static void ixgbe_tx_timeout(struct net_device *netdev)
4354{
4355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4356
4357 /* Do the reset outside of interrupt context */
c83c6cbd 4358 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4359}
4360
9a799d71
AK		 4361/**
4362 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4363 * @adapter: board private structure to initialize
4364 *
4365 * ixgbe_sw_init initializes the Adapter private data structure.
4366 * Fields are initialized based on PCI device information and
4367 * OS network device settings (MTU size).
4368 **/
4369static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4370{
4371 struct ixgbe_hw *hw = &adapter->hw;
4372 struct pci_dev *pdev = adapter->pdev;
021230d4 4373 unsigned int rss;
7a6b6f51 4374#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4375 int j;
4376 struct tc_configuration *tc;
4377#endif
021230d4 4378
c44ade9e
JB		 4379 /* PCI config space info */
4380
4381 hw->vendor_id = pdev->vendor;
4382 hw->device_id = pdev->device;
4383 hw->revision_id = pdev->revision;
4384 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4385 hw->subsystem_device_id = pdev->subsystem_device;
4386
021230d4 4387 /* Set capability flags */
3ed69d7e 4388 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
021230d4
AV		 4389 adapter->ring_feature[RING_F_RSS].indices = rss;
4390 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4391 switch (hw->mac.type) {
4392 case ixgbe_mac_82598EB:
bf069c97
DS		 4393 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4394 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4395 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4396 break;
b93a2226 4397 case ixgbe_mac_X540:
4f51bf70
JK		 4398 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4399 case ixgbe_mac_82599EB:
49c7ffbe 4400 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4401 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4402 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4403 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4404 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4405 /* Flow Director hash filters enabled */
4406 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4407 adapter->atr_sample_rate = 20;
c4cf55e5 4408 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4409 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4410 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4411#ifdef IXGBE_FCOE
0d551589
YZ		 4412 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4413 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4414 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4415#ifdef CONFIG_IXGBE_DCB
6ee16520 4416 /* Default traffic class to use for FCoE */
56075a98 4417 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4418#endif
eacd73f7 4419#endif /* IXGBE_FCOE */
bd508178
AD		 4420 break;
4421 default:
4422 break;
f8212f97 4423 }
2f90b865 4424
1fc5f038
AD		 4425 /* n-tuple support exists, always init our spinlock */
4426 spin_lock_init(&adapter->fdir_perfect_lock);
4427
7a6b6f51 4428#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4429 switch (hw->mac.type) {
4430 case ixgbe_mac_X540:
4431 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4432 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4433 break;
4434 default:
4435 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4436 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4437 break;
4438 }
4439
2f90b865
AD		 4440 /* Configure DCB traffic classes */
4441 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4442 tc = &adapter->dcb_cfg.tc_config[j];
4443 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4444 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4445 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4446 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4447 tc->dcb_pfc = pfc_disabled;
4448 }
4de2a022
JF		 4449
4450 /* Initialize default user to priority mapping, UPx->TC0 */
4451 tc = &adapter->dcb_cfg.tc_config[0];
4452 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4453 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4454
2f90b865
AD		 4455 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4456 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4457 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4458 adapter->dcb_set_bitmap = 0x00;
3032309b 4459 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4460 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4461 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4462
4463#endif
9a799d71
AK		 4464
4465 /* default flow control settings */
cd7664f6 4466 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4467 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4468 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4469 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4470 hw->fc.send_xon = true;
71fd570b 4471 hw->fc.disable_fc_autoneg = false;
9a799d71 4472
30efa5a3 4473 /* enable itr by default in dynamic mode */
f7554a2b 4474 adapter->rx_itr_setting = 1;
f7554a2b 4475 adapter->tx_itr_setting = 1;
30efa5a3 4476
30efa5a3
JB		 4477 /* set default ring sizes */
4478 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4479 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4480
bd198058 4481 /* set default work limits */
59224555 4482 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4483
9a799d71 4484 /* initialize eeprom parameters */
c44ade9e 4485 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4486 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4487 return -EIO;
4488 }
4489
9a799d71
AK		 4490 set_bit(__IXGBE_DOWN, &adapter->state);
4491
4492 return 0;
4493}
4494
4495/**
4496 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4497 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4498 *
4499 * Return 0 on success, negative on failure
4500 **/
b6ec895e 4501int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4502{
b6ec895e 4503 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4504 int orig_node = dev_to_node(dev);
4505 int numa_node = -1;
9a799d71
AK		 4506 int size;
4507
3a581073 4508 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4509
4510 if (tx_ring->q_vector)
4511 numa_node = tx_ring->q_vector->numa_node;
4512
4513 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4514 if (!tx_ring->tx_buffer_info)
89bf67f1 4515 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4516 if (!tx_ring->tx_buffer_info)
4517 goto err;
9a799d71
AK		 4518
4519 /* round up to nearest 4K */
12207e49 4520 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4521 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4522
de88eeeb
AD		 4523 set_dev_node(dev, numa_node);
4524 tx_ring->desc = dma_alloc_coherent(dev,
4525 tx_ring->size,
4526 &tx_ring->dma,
4527 GFP_KERNEL);
4528 set_dev_node(dev, orig_node);
4529 if (!tx_ring->desc)
4530 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4531 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4532 if (!tx_ring->desc)
4533 goto err;
9a799d71 4534
3a581073
JB		 4535 tx_ring->next_to_use = 0;
4536 tx_ring->next_to_clean = 0;
9a799d71 4537 return 0;
e01c31a5
JB		 4538
4539err:
4540 vfree(tx_ring->tx_buffer_info);
4541 tx_ring->tx_buffer_info = NULL;
b6ec895e 4542 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4543 return -ENOMEM;
9a799d71
AK		 4544}
4545
69888674
AD		 4546/**
4547 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4548 * @adapter: board private structure
4549 *
4550 * If this function returns with an error, then it's possible one or
4551 * more of the rings is populated (while the rest are not). It is the
4552 * callers duty to clean those orphaned rings.
4553 *
4554 * Return 0 on success, negative on failure
4555 **/
4556static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4557{
4558 int i, err = 0;
4559
4560 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4561 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4562 if (!err)
4563 continue;
396e799c 4564 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4565 break;
4566 }
4567
4568 return err;
4569}
4570
9a799d71
AK		 4571/**
4572 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4573 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4574 *
4575 * Returns 0 on success, negative on failure
4576 **/
b6ec895e 4577int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4578{
b6ec895e 4579 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4580 int orig_node = dev_to_node(dev);
4581 int numa_node = -1;
021230d4 4582 int size;
9a799d71 4583
3a581073 4584 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4585
4586 if (rx_ring->q_vector)
4587 numa_node = rx_ring->q_vector->numa_node;
4588
4589 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4590 if (!rx_ring->rx_buffer_info)
89bf67f1 4591 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4592 if (!rx_ring->rx_buffer_info)
4593 goto err;
9a799d71 4594
9a799d71 4595 /* Round up to nearest 4K */
3a581073
JB		 4596 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4597 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4598
de88eeeb
AD		 4599 set_dev_node(dev, numa_node);
4600 rx_ring->desc = dma_alloc_coherent(dev,
4601 rx_ring->size,
4602 &rx_ring->dma,
4603 GFP_KERNEL);
4604 set_dev_node(dev, orig_node);
4605 if (!rx_ring->desc)
4606 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4607 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4608 if (!rx_ring->desc)
4609 goto err;
9a799d71 4610
3a581073
JB		 4611 rx_ring->next_to_clean = 0;
4612 rx_ring->next_to_use = 0;
9a799d71 4613
f800326d
AD		 4614 ixgbe_init_rx_page_offset(rx_ring);
4615
9a799d71 4616 return 0;
b6ec895e
AD		 4617err:
4618 vfree(rx_ring->rx_buffer_info);
4619 rx_ring->rx_buffer_info = NULL;
4620 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4621 return -ENOMEM;
9a799d71
AK		 4622}
4623
69888674
AD		 4624/**
4625 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4626 * @adapter: board private structure
4627 *
4628 * If this function returns with an error, then it's possible one or
4629 * more of the rings is populated (while the rest are not). It is the
4630 * callers duty to clean those orphaned rings.
4631 *
4632 * Return 0 on success, negative on failure
4633 **/
69888674
AD		 4634static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4635{
4636 int i, err = 0;
4637
4638 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4639 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4640 if (!err)
4641 continue;
396e799c 4642 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 4643 break;
4644 }
4645
4646 return err;
4647}
4648
9a799d71
AK		 4649/**
4650 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4651 * @tx_ring: Tx descriptor ring for a specific queue
4652 *
4653 * Free all transmit software resources
4654 **/
b6ec895e 4655void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4656{
b6ec895e 4657 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4658
4659 vfree(tx_ring->tx_buffer_info);
4660 tx_ring->tx_buffer_info = NULL;
4661
b6ec895e
AD		 4662 /* if not set, then don't free */
4663 if (!tx_ring->desc)
4664 return;
4665
4666 dma_free_coherent(tx_ring->dev, tx_ring->size,
4667 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4668
4669 tx_ring->desc = NULL;
4670}
4671
4672/**
4673 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4674 * @adapter: board private structure
4675 *
4676 * Free all transmit software resources
4677 **/
4678static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4679{
4680 int i;
4681
4682 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4683 if (adapter->tx_ring[i]->desc)
b6ec895e 4684 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4685}
4686
4687/**
b4617240 4688 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4689 * @rx_ring: ring to clean the resources from
4690 *
4691 * Free all receive software resources
4692 **/
b6ec895e 4693void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4694{
b6ec895e 4695 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4696
4697 vfree(rx_ring->rx_buffer_info);
4698 rx_ring->rx_buffer_info = NULL;
4699
b6ec895e
AD		 4700 /* if not set, then don't free */
4701 if (!rx_ring->desc)
4702 return;
4703
4704 dma_free_coherent(rx_ring->dev, rx_ring->size,
4705 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4706
4707 rx_ring->desc = NULL;
4708}
4709
4710/**
4711 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4712 * @adapter: board private structure
4713 *
4714 * Free all receive software resources
4715 **/
4716static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4717{
4718 int i;
4719
4720 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4721 if (adapter->rx_ring[i]->desc)
b6ec895e 4722 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4723}
4724
9a799d71
AK		 4725/**
4726 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4727 * @netdev: network interface device structure
4728 * @new_mtu: new value for maximum frame size
4729 *
4730 * Returns 0 on success, negative on failure
4731 **/
4732static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4733{
4734 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4735 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4736
42c783c5 4737 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4738 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4739 return -EINVAL;
4740
4741 /*
4742 * For 82599EB we cannot allow PF to change MTU greater than 1500
4743 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4744 * don't allocate and chain buffers correctly.
4745 */
4746 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4747 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4748 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4749 return -EINVAL;
9a799d71 4750
396e799c 4751 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4752
021230d4 4753 /* must set new MTU before calling down or up */
9a799d71
AK		 4754 netdev->mtu = new_mtu;
4755
d4f80882
AV		 4756 if (netif_running(netdev))
4757 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4758
4759 return 0;
4760}
4761
4762/**
4763 * ixgbe_open - Called when a network interface is made active
4764 * @netdev: network interface device structure
4765 *
4766 * Returns 0 on success, negative value on failure
4767 *
4768 * The open entry point is called when a network interface is made
4769 * active by the system (IFF_UP). At this point all resources needed
4770 * for transmit and receive operations are allocated, the interrupt
4771 * handler is registered with the OS, the watchdog timer is started,
4772 * and the stack is notified that the interface is ready.
4773 **/
4774static int ixgbe_open(struct net_device *netdev)
4775{
4776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4777 int err;
4bebfaa5
AK		 4778
4779 /* disallow open during test */
4780 if (test_bit(__IXGBE_TESTING, &adapter->state))
4781 return -EBUSY;
9a799d71 4782
54386467
JB		 4783 netif_carrier_off(netdev);
4784
9a799d71
AK		 4785 /* allocate transmit descriptors */
4786 err = ixgbe_setup_all_tx_resources(adapter);
4787 if (err)
4788 goto err_setup_tx;
4789
9a799d71
AK		 4790 /* allocate receive descriptors */
4791 err = ixgbe_setup_all_rx_resources(adapter);
4792 if (err)
4793 goto err_setup_rx;
4794
4795 ixgbe_configure(adapter);
4796
021230d4 4797 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4798 if (err)
4799 goto err_req_irq;
4800
c7ccde0f 4801 ixgbe_up_complete(adapter);
9a799d71
AK		 4802
4803 return 0;
4804
9a799d71 4805err_req_irq:
9a799d71 4806err_setup_rx:
a20a1199 4807 ixgbe_free_all_rx_resources(adapter);
9a799d71 4808err_setup_tx:
a20a1199 4809 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4810 ixgbe_reset(adapter);
4811
4812 return err;
4813}
4814
4815/**
4816 * ixgbe_close - Disables a network interface
4817 * @netdev: network interface device structure
4818 *
4819 * Returns 0, this is not allowed to fail
4820 *
4821 * The close entry point is called when an interface is de-activated
4822 * by the OS. The hardware is still under the drivers control, but
4823 * needs to be disabled. A global MAC reset is issued to stop the
4824 * hardware, and all transmit and receive resources are freed.
4825 **/
4826static int ixgbe_close(struct net_device *netdev)
4827{
4828 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4829
4830 ixgbe_down(adapter);
4831 ixgbe_free_irq(adapter);
4832
e4911d57
AD		 4833 ixgbe_fdir_filter_exit(adapter);
4834
9a799d71
AK		 4835 ixgbe_free_all_tx_resources(adapter);
4836 ixgbe_free_all_rx_resources(adapter);
4837
5eba3699 4838 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4839
4840 return 0;
4841}
4842
b3c8b4ba
AD		 4843#ifdef CONFIG_PM
4844static int ixgbe_resume(struct pci_dev *pdev)
4845{
c60fbb00
AD		 4846 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4847 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4848 u32 err;
4849
4850 pci_set_power_state(pdev, PCI_D0);
4851 pci_restore_state(pdev);
656ab817
DS		 4852 /*
4853 * pci_restore_state clears dev->state_saved so call
4854 * pci_save_state to restore it.
4855 */
4856 pci_save_state(pdev);
9ce77666 4857
4858 err = pci_enable_device_mem(pdev);
b3c8b4ba 4859 if (err) {
849c4542 4860 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4861 return err;
4862 }
4863 pci_set_master(pdev);
4864
dd4d8ca6 4865 pci_wake_from_d3(pdev, false);
b3c8b4ba 4866
34948a94 4867 rtnl_lock();
b3c8b4ba 4868 err = ixgbe_init_interrupt_scheme(adapter);
34948a94 4869 rtnl_unlock();
b3c8b4ba 4870 if (err) {
849c4542 4871 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 4872 return err;
4873 }
4874
b3c8b4ba
AD		 4875 ixgbe_reset(adapter);
4876
495dce12
WJP		 4877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4878
b3c8b4ba 4879 if (netif_running(netdev)) {
c60fbb00 4880 err = ixgbe_open(netdev);
b3c8b4ba
AD		 4881 if (err)
4882 return err;
4883 }
4884
4885 netif_device_attach(netdev);
4886
4887 return 0;
4888}
b3c8b4ba 4889#endif /* CONFIG_PM */
9d8d05ae
RW		 4890
4891static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4892{
c60fbb00
AD		 4893 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4894 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4895 struct ixgbe_hw *hw = &adapter->hw;
4896 u32 ctrl, fctrl;
4897 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4898#ifdef CONFIG_PM
4899 int retval = 0;
4900#endif
4901
4902 netif_device_detach(netdev);
4903
4904 if (netif_running(netdev)) {
ab6039a7 4905 rtnl_lock();
b3c8b4ba
AD		 4906 ixgbe_down(adapter);
4907 ixgbe_free_irq(adapter);
4908 ixgbe_free_all_tx_resources(adapter);
4909 ixgbe_free_all_rx_resources(adapter);
ab6039a7 4910 rtnl_unlock();
b3c8b4ba 4911 }
b3c8b4ba 4912
5f5ae6fc
AD		 4913 ixgbe_clear_interrupt_scheme(adapter);
4914
b3c8b4ba
AD		 4915#ifdef CONFIG_PM
4916 retval = pci_save_state(pdev);
4917 if (retval)
4918 return retval;
4df10466 4919
b3c8b4ba 4920#endif
e8e26350
PW		 4921 if (wufc) {
4922 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4923
c509e754
DS		 4924 /*
4925 * enable the optics for both mult-speed fiber and
4926 * 82599 SFP+ fiber as we can WoL.
4927 */
4928 if (hw->mac.ops.enable_tx_laser &&
4929 (hw->phy.multispeed_fiber ||
4930 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4931 hw->mac.type == ixgbe_mac_82599EB)))
4932 hw->mac.ops.enable_tx_laser(hw);
4933
e8e26350
PW		 4934 /* turn on all-multi mode if wake on multicast is enabled */
4935 if (wufc & IXGBE_WUFC_MC) {
4936 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4937 fctrl |= IXGBE_FCTRL_MPE;
4938 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4939 }
4940
4941 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4942 ctrl |= IXGBE_CTRL_GIO_DIS;
4943 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4944
4945 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4946 } else {
4947 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4948 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4949 }
4950
bd508178
AD		 4951 switch (hw->mac.type) {
4952 case ixgbe_mac_82598EB:
dd4d8ca6 4953 pci_wake_from_d3(pdev, false);
bd508178
AD		 4954 break;
4955 case ixgbe_mac_82599EB:
b93a2226 4956 case ixgbe_mac_X540:
bd508178
AD		 4957 pci_wake_from_d3(pdev, !!wufc);
4958 break;
4959 default:
4960 break;
4961 }
b3c8b4ba 4962
9d8d05ae
RW		 4963 *enable_wake = !!wufc;
4964
b3c8b4ba
AD		 4965 ixgbe_release_hw_control(adapter);
4966
4967 pci_disable_device(pdev);
4968
9d8d05ae
RW		 4969 return 0;
4970}
4971
4972#ifdef CONFIG_PM
4973static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4974{
4975 int retval;
4976 bool wake;
4977
4978 retval = __ixgbe_shutdown(pdev, &wake);
4979 if (retval)
4980 return retval;
4981
4982 if (wake) {
4983 pci_prepare_to_sleep(pdev);
4984 } else {
4985 pci_wake_from_d3(pdev, false);
4986 pci_set_power_state(pdev, PCI_D3hot);
4987 }
b3c8b4ba
AD		 4988
4989 return 0;
4990}
9d8d05ae 4991#endif /* CONFIG_PM */
b3c8b4ba
AD		 4992
4993static void ixgbe_shutdown(struct pci_dev *pdev)
4994{
9d8d05ae
RW		 4995 bool wake;
4996
4997 __ixgbe_shutdown(pdev, &wake);
4998
4999 if (system_state == SYSTEM_POWER_OFF) {
5000 pci_wake_from_d3(pdev, wake);
5001 pci_set_power_state(pdev, PCI_D3hot);
5002 }
b3c8b4ba
AD		 5003}
5004
9a799d71
AK		 5005/**
5006 * ixgbe_update_stats - Update the board statistics counters.
5007 * @adapter: board private structure
5008 **/
5009void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5010{
2d86f139 5011 struct net_device *netdev = adapter->netdev;
9a799d71 5012 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5013 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5014 u64 total_mpc = 0;
5015 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5016 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5017 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5018 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5019#ifdef IXGBE_FCOE
5020 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5021 unsigned int cpu;
5022 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5023#endif /* IXGBE_FCOE */
9a799d71 5024
d08935c2
DS		 5025 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5026 test_bit(__IXGBE_RESETTING, &adapter->state))
5027 return;
5028
94b982b2 5029 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5030 u64 rsc_count = 0;
94b982b2 5031 u64 rsc_flush = 0;
94b982b2 5032 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5033 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5034 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5035 }
5036 adapter->rsc_total_count = rsc_count;
5037 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5038 }
5039
5b7da515
AD		 5040 for (i = 0; i < adapter->num_rx_queues; i++) {
5041 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5042 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5043 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5044 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5045 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5046 bytes += rx_ring->stats.bytes;
5047 packets += rx_ring->stats.packets;
5048 }
5049 adapter->non_eop_descs = non_eop_descs;
5050 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5051 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5052 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5053 netdev->stats.rx_bytes = bytes;
5054 netdev->stats.rx_packets = packets;
5055
5056 bytes = 0;
5057 packets = 0;
7ca3bc58 5058 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5059 for (i = 0; i < adapter->num_tx_queues; i++) {
5060 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5061 restart_queue += tx_ring->tx_stats.restart_queue;
5062 tx_busy += tx_ring->tx_stats.tx_busy;
5063 bytes += tx_ring->stats.bytes;
5064 packets += tx_ring->stats.packets;
5065 }
eb985f09 5066 adapter->restart_queue = restart_queue;
5b7da515
AD		 5067 adapter->tx_busy = tx_busy;
5068 netdev->stats.tx_bytes = bytes;
5069 netdev->stats.tx_packets = packets;
7ca3bc58 5070
7ca647bd 5071 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5072
5073 /* 8 register reads */
6f11eef7
AV		 5074 for (i = 0; i < 8; i++) {
5075 /* for packet buffers not used, the register should read 0 */
5076 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5077 missed_rx += mpc;
7ca647bd
JP		 5078 hwstats->mpc[i] += mpc;
5079 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5080 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5081 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5082 switch (hw->mac.type) {
5083 case ixgbe_mac_82598EB:
1a70db4b
ET		 5084 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5085 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5086 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5087 hwstats->pxonrxc[i] +=
5088 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5089 break;
5090 case ixgbe_mac_82599EB:
b93a2226 5091 case ixgbe_mac_X540:
bd508178
AD		 5092 hwstats->pxonrxc[i] +=
5093 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5094 break;
5095 default:
5096 break;
e8e26350 5097 }
6f11eef7 5098 }
1a70db4b
ET		 5099
5100 /*16 register reads */
5101 for (i = 0; i < 16; i++) {
5102 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5103 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5104 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5105 (hw->mac.type == ixgbe_mac_X540)) {
5106 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5107 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5108 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5109 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5110 }
5111 }
5112
7ca647bd 5113 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5114 /* work around hardware counting issue */
7ca647bd 5115 hwstats->gprc -= missed_rx;
6f11eef7 5116
c84d324c
JF		 5117 ixgbe_update_xoff_received(adapter);
5118
6f11eef7 5119 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5120 switch (hw->mac.type) {
5121 case ixgbe_mac_82598EB:
5122 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5123 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5124 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5125 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5126 break;
b93a2226 5127 case ixgbe_mac_X540:
58f6bcf9
ET		 5128 /* OS2BMC stats are X540 only*/
5129 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5130 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5131 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5132 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5133 case ixgbe_mac_82599EB:
a4d4f629
AD		 5134 for (i = 0; i < 16; i++)
5135 adapter->hw_rx_no_dma_resources +=
5136 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5137 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5138 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5139 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5140 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5141 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5142 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5143 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5144 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5145 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5146#ifdef IXGBE_FCOE
7ca647bd
JP		 5147 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5148 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5149 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5150 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5151 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5152 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5153 /* Add up per cpu counters for total ddp aloc fail */
5154 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5155 for_each_possible_cpu(cpu) {
5156 fcoe_noddp_counts_sum +=
5157 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5158 fcoe_noddp_ext_buff_counts_sum +=
5159 *per_cpu_ptr(fcoe->
5160 pcpu_noddp_ext_buff, cpu);
5161 }
5162 }
5163 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5164 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5165#endif /* IXGBE_FCOE */
bd508178
AD		 5166 break;
5167 default:
5168 break;
e8e26350 5169 }
9a799d71 5170 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5171 hwstats->bprc += bprc;
5172 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5173 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5174 hwstats->mprc -= bprc;
5175 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5176 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5177 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5178 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5179 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5180 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5181 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5182 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5183 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5184 hwstats->lxontxc += lxon;
6f11eef7 5185 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5186 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5187 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5188 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5189 /*
5190 * 82598 errata - tx of flow control packets is included in tx counters
5191 */
5192 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5193 hwstats->gptc -= xon_off_tot;
5194 hwstats->mptc -= xon_off_tot;
5195 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5196 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5197 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5198 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5199 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5200 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5201 hwstats->ptc64 -= xon_off_tot;
5202 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5203 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5204 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5205 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5206 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5207 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5208
5209 /* Fill out the OS statistics structure */
7ca647bd 5210 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5211
5212 /* Rx Errors */
7ca647bd 5213 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5214 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5215 netdev->stats.rx_length_errors = hwstats->rlec;
5216 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5217 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5218}
5219
5220/**
d034acf1 5221 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5222 * @adapter: pointer to the device adapter structure
9a799d71 5223 **/
d034acf1 5224static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5225{
cf8280ee 5226 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5227 int i;
cf8280ee 5228
d034acf1
AD		 5229 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5230 return;
5231
5232 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5233
d034acf1 5234 /* if interface is down do nothing */
fe49f04a 5235 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5236 return;
5237
5238 /* do nothing if we are not using signature filters */
5239 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5240 return;
5241
5242 adapter->fdir_overflow++;
5243
93c52dd0
AD		 5244 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5245 for (i = 0; i < adapter->num_tx_queues; i++)
5246 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5247 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5248 /* re-enable flow director interrupts */
5249 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5250 } else {
5251 e_err(probe, "failed to finish FDIR re-initialization, "
5252 "ignored adding FDIR ATR filters\n");
5253 }
93c52dd0
AD		 5254}
5255
5256/**
5257 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5258 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5259 *
5260 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5261 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5262 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5263 * determine if a hang has occurred.
93c52dd0
AD		 5264 */
5265static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5266{
cf8280ee 5267 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5268 u64 eics = 0;
5269 int i;
cf8280ee 5270
93c52dd0
AD		 5271 /* If we're down or resetting, just bail */
5272 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5273 test_bit(__IXGBE_RESETTING, &adapter->state))
5274 return;
22d5a71b 5275
93c52dd0
AD		 5276 /* Force detection of hung controller */
5277 if (netif_carrier_ok(adapter->netdev)) {
5278 for (i = 0; i < adapter->num_tx_queues; i++)
5279 set_check_for_tx_hang(adapter->tx_ring[i]);
5280 }
22d5a71b 5281
fe49f04a
AD		 5282 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5283 /*
5284 * for legacy and MSI interrupts don't set any bits
5285 * that are enabled for EIAM, because this operation
5286 * would set *both* EIMS and EICS for any bit in EIAM
5287 */
5288 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5289 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5290 } else {
5291 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5292 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5293 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5294 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5295 eics |= ((u64)1 << i);
5296 }
cf8280ee 5297 }
9a799d71 5298
93c52dd0 5299 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5300 ixgbe_irq_rearm_queues(adapter, eics);
5301
cf8280ee
JB		 5302}
5303
e8e26350 5304/**
93c52dd0 5305 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5306 * @adapter: pointer to the device adapter structure
5307 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5308 **/
93c52dd0 5309static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5310{
e8e26350 5311 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5312 u32 link_speed = adapter->link_speed;
5313 bool link_up = adapter->link_up;
041441d0 5314 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5315
93c52dd0
AD		 5316 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5317 return;
5318
5319 if (hw->mac.ops.check_link) {
5320 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5321 } else {
93c52dd0
AD		 5322 /* always assume link is up, if no check link function */
5323 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5324 link_up = true;
c4cf55e5 5325 }
041441d0
AD		 5326
5327 if (adapter->ixgbe_ieee_pfc)
5328 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5329
3ebe8fde 5330 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5331 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5332 ixgbe_set_rx_drop_en(adapter);
5333 }
93c52dd0
AD		 5334
5335 if (link_up ||
5336 time_after(jiffies, (adapter->link_check_timeout +
5337 IXGBE_TRY_LINK_TIMEOUT))) {
5338 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5339 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5340 IXGBE_WRITE_FLUSH(hw);
5341 }
5342
5343 adapter->link_up = link_up;
5344 adapter->link_speed = link_speed;
e8e26350
PW		 5345}
5346
5347/**
93c52dd0
AD		 5348 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5349 * print link up message
49ce9c2c 5350 * @adapter: pointer to the device adapter structure
e8e26350 5351 **/
93c52dd0 5352static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5353{
93c52dd0 5354 struct net_device *netdev = adapter->netdev;
e8e26350 5355 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5356 u32 link_speed = adapter->link_speed;
5357 bool flow_rx, flow_tx;
e8e26350 5358
93c52dd0
AD		 5359 /* only continue if link was previously down */
5360 if (netif_carrier_ok(netdev))
a985b6c3 5361 return;
63d6e1d8 5362
93c52dd0 5363 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5364
93c52dd0
AD		 5365 switch (hw->mac.type) {
5366 case ixgbe_mac_82598EB: {
5367 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5368 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5369 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5370 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5371 }
5372 break;
5373 case ixgbe_mac_X540:
5374 case ixgbe_mac_82599EB: {
5375 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5376 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5377 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5378 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5379 }
5380 break;
5381 default:
5382 flow_tx = false;
5383 flow_rx = false;
5384 break;
e8e26350 5385 }
3a6a4eda
JK		 5386
5387#ifdef CONFIG_IXGBE_PTP
5388 ixgbe_ptp_start_cyclecounter(adapter);
5389#endif
5390
93c52dd0
AD		 5391 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5392 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5393 "10 Gbps" :
5394 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5395 "1 Gbps" :
5396 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5397 "100 Mbps" :
5398 "unknown speed"))),
5399 ((flow_rx && flow_tx) ? "RX/TX" :
5400 (flow_rx ? "RX" :
5401 (flow_tx ? "TX" : "None"))));
e8e26350 5402
93c52dd0 5403 netif_carrier_on(netdev);
93c52dd0 5404 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5405}
5406
c4cf55e5 5407/**
93c52dd0
AD		 5408 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5409 * print link down message
49ce9c2c 5410 * @adapter: pointer to the adapter structure
c4cf55e5 5411 **/
581330ba 5412static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5413{
cf8280ee 5414 struct net_device *netdev = adapter->netdev;
c4cf55e5 5415 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5416
93c52dd0
AD		 5417 adapter->link_up = false;
5418 adapter->link_speed = 0;
cf8280ee 5419
93c52dd0
AD		 5420 /* only continue if link was up previously */
5421 if (!netif_carrier_ok(netdev))
5422 return;
264857b8 5423
93c52dd0
AD		 5424 /* poll for SFP+ cable when link is down */
5425 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5426 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5427
3a6a4eda
JK		 5428#ifdef CONFIG_IXGBE_PTP
5429 ixgbe_ptp_start_cyclecounter(adapter);
5430#endif
5431
93c52dd0
AD		 5432 e_info(drv, "NIC Link is Down\n");
5433 netif_carrier_off(netdev);
5434}
e8e26350 5435
93c52dd0
AD		 5436/**
5437 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5438 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5439 **/
5440static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5441{
c4cf55e5 5442 int i;
93c52dd0 5443 int some_tx_pending = 0;
c4cf55e5 5444
93c52dd0 5445 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5446 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5447 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5448 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5449 some_tx_pending = 1;
5450 break;
5451 }
5452 }
5453
5454 if (some_tx_pending) {
5455 /* We've lost link, so the controller stops DMA,
5456 * but we've got queued Tx work that's never going
5457 * to get done, so reset controller to flush Tx.
5458 * (Do the reset outside of interrupt context).
5459 */
c83c6cbd 5460 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5461 }
c4cf55e5 5462 }
c4cf55e5
PWJ		 5463}
5464
a985b6c3
GR		 5465static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5466{
5467 u32 ssvpc;
5468
5469 /* Do not perform spoof check for 82598 */
5470 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5471 return;
5472
5473 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5474
5475 /*
5476 * ssvpc register is cleared on read, if zero then no
5477 * spoofed packets in the last interval.
5478 */
5479 if (!ssvpc)
5480 return;
5481
5482 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5483}
5484
93c52dd0
AD		 5485/**
5486 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5487 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5488 **/
5489static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5490{
5491 /* if interface is down do nothing */
7edebf9a
ET		 5492 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5493 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5494 return;
5495
5496 ixgbe_watchdog_update_link(adapter);
5497
5498 if (adapter->link_up)
5499 ixgbe_watchdog_link_is_up(adapter);
5500 else
5501 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5502
a985b6c3 5503 ixgbe_spoof_check(adapter);
9a799d71 5504 ixgbe_update_stats(adapter);
93c52dd0
AD		 5505
5506 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5507}
10eec955 5508
cf8280ee 5509/**
7086400d 5510 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5511 * @adapter: the ixgbe adapter structure
cf8280ee 5512 **/
7086400d 5513static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5514{
cf8280ee 5515 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5516 s32 err;
cf8280ee 5517
7086400d
AD		 5518 /* not searching for SFP so there is nothing to do here */
5519 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5520 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5521 return;
10eec955 5522
7086400d
AD		 5523 /* someone else is in init, wait until next service event */
5524 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5525 return;
cf8280ee 5526
7086400d
AD		 5527 err = hw->phy.ops.identify_sfp(hw);
5528 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5529 goto sfp_out;
264857b8 5530
7086400d
AD		 5531 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5532 /* If no cable is present, then we need to reset
5533 * the next time we find a good cable. */
5534 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5535 }
9a799d71 5536
7086400d
AD		 5537 /* exit on error */
5538 if (err)
5539 goto sfp_out;
e8e26350 5540
7086400d
AD		 5541 /* exit if reset not needed */
5542 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5543 goto sfp_out;
9a799d71 5544
7086400d 5545 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5546
7086400d
AD		 5547 /*
5548 * A module may be identified correctly, but the EEPROM may not have
5549 * support for that module. setup_sfp() will fail in that case, so
5550 * we should not allow that module to load.
5551 */
5552 if (hw->mac.type == ixgbe_mac_82598EB)
5553 err = hw->phy.ops.reset(hw);
5554 else
5555 err = hw->mac.ops.setup_sfp(hw);
5556
5557 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5558 goto sfp_out;
5559
5560 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5561 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5562
5563sfp_out:
5564 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5565
5566 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5567 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5568 e_dev_err("failed to initialize because an unsupported "
5569 "SFP+ module type was detected.\n");
5570 e_dev_err("Reload the driver after installing a "
5571 "supported module.\n");
5572 unregister_netdev(adapter->netdev);
bc59fcda 5573 }
7086400d 5574}
bc59fcda 5575
7086400d
AD		 5576/**
5577 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5578 * @adapter: the ixgbe adapter structure
7086400d
AD		 5579 **/
5580static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5581{
5582 struct ixgbe_hw *hw = &adapter->hw;
5583 u32 autoneg;
5584 bool negotiation;
5585
5586 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5587 return;
5588
5589 /* someone else is in init, wait until next service event */
5590 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5591 return;
5592
5593 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5594
5595 autoneg = hw->phy.autoneg_advertised;
5596 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5597 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5598 if (hw->mac.ops.setup_link)
5599 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5600
5601 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5602 adapter->link_check_timeout = jiffies;
5603 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5604}
5605
83c61fa9
GR		 5606#ifdef CONFIG_PCI_IOV
5607static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5608{
5609 int vf;
5610 struct ixgbe_hw *hw = &adapter->hw;
5611 struct net_device *netdev = adapter->netdev;
5612 u32 gpc;
5613 u32 ciaa, ciad;
5614
5615 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5616 if (gpc) /* If incrementing then no need for the check below */
5617 return;
5618 /*
5619 * Check to see if a bad DMA write target from an errant or
5620 * malicious VF has caused a PCIe error. If so then we can
5621 * issue a VFLR to the offending VF(s) and then resume without
5622 * requesting a full slot reset.
5623 */
5624
5625 for (vf = 0; vf < adapter->num_vfs; vf++) {
5626 ciaa = (vf << 16) | 0x80000000;
5627 /* 32 bit read so align, we really want status at offset 6 */
5628 ciaa |= PCI_COMMAND;
5629 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5630 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5631 ciaa &= 0x7FFFFFFF;
5632 /* disable debug mode asap after reading data */
5633 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5634 /* Get the upper 16 bits which will be the PCI status reg */
5635 ciad >>= 16;
5636 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5637 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5638 /* Issue VFLR */
5639 ciaa = (vf << 16) | 0x80000000;
5640 ciaa |= 0xA8;
5641 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5642 ciad = 0x00008000; /* VFLR */
5643 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5644 ciaa &= 0x7FFFFFFF;
5645 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5646 }
5647 }
5648}
5649
5650#endif
7086400d
AD		 5651/**
5652 * ixgbe_service_timer - Timer Call-back
5653 * @data: pointer to adapter cast into an unsigned long
5654 **/
5655static void ixgbe_service_timer(unsigned long data)
5656{
5657 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5658 unsigned long next_event_offset;
83c61fa9 5659 bool ready = true;
7086400d 5660
6bb78cfb
AD		 5661 /* poll faster when waiting for link */
5662 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5663 next_event_offset = HZ / 10;
5664 else
5665 next_event_offset = HZ * 2;
83c61fa9 5666
6bb78cfb 5667#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5668 /*
5669 * don't bother with SR-IOV VF DMA hang check if there are
5670 * no VFs or the link is down
5671 */
5672 if (!adapter->num_vfs ||
6bb78cfb 5673 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5674 goto normal_timer_service;
83c61fa9
GR		 5675
5676 /* If we have VFs allocated then we must check for DMA hangs */
5677 ixgbe_check_for_bad_vf(adapter);
5678 next_event_offset = HZ / 50;
5679 adapter->timer_event_accumulator++;
5680
6bb78cfb 5681 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5682 adapter->timer_event_accumulator = 0;
7086400d 5683 else
6bb78cfb 5684 ready = false;
7086400d 5685
6bb78cfb 5686normal_timer_service:
83c61fa9 5687#endif
7086400d
AD		 5688 /* Reset the timer */
5689 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5690
83c61fa9
GR		 5691 if (ready)
5692 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5693}
5694
c83c6cbd
AD		 5695static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5696{
5697 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5698 return;
5699
5700 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5701
5702 /* If we're already down or resetting, just bail */
5703 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5704 test_bit(__IXGBE_RESETTING, &adapter->state))
5705 return;
5706
5707 ixgbe_dump(adapter);
5708 netdev_err(adapter->netdev, "Reset adapter\n");
5709 adapter->tx_timeout_count++;
5710
5711 ixgbe_reinit_locked(adapter);
5712}
5713
7086400d
AD		 5714/**
5715 * ixgbe_service_task - manages and runs subtasks
5716 * @work: pointer to work_struct containing our data
5717 **/
5718static void ixgbe_service_task(struct work_struct *work)
5719{
5720 struct ixgbe_adapter *adapter = container_of(work,
5721 struct ixgbe_adapter,
5722 service_task);
5723
c83c6cbd 5724 ixgbe_reset_subtask(adapter);
7086400d
AD		 5725 ixgbe_sfp_detection_subtask(adapter);
5726 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5727 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5728 ixgbe_watchdog_subtask(adapter);
d034acf1 5729 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5730 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5731#ifdef CONFIG_IXGBE_PTP
5732 ixgbe_ptp_overflow_check(adapter);
5733#endif
7086400d
AD		 5734
5735 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5736}
5737
fd0db0ed
AD		 5738static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5739 struct ixgbe_tx_buffer *first,
244e27ad 5740 u8 *hdr_len)
897ab156 5741{
fd0db0ed 5742 struct sk_buff *skb = first->skb;
897ab156
AD		 5743 u32 vlan_macip_lens, type_tucmd;
5744 u32 mss_l4len_idx, l4len;
9a799d71 5745
897ab156
AD		 5746 if (!skb_is_gso(skb))
5747 return 0;
9a799d71 5748
897ab156 5749 if (skb_header_cloned(skb)) {
244e27ad 5750 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5751 if (err)
5752 return err;
9a799d71 5753 }
9a799d71 5754
897ab156
AD		 5755 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5756 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5757
244e27ad 5758 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5759 struct iphdr *iph = ip_hdr(skb);
5760 iph->tot_len = 0;
5761 iph->check = 0;
5762 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5763 iph->daddr, 0,
5764 IPPROTO_TCP,
5765 0);
5766 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5767 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5768 IXGBE_TX_FLAGS_CSUM |
5769 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5770 } else if (skb_is_gso_v6(skb)) {
5771 ipv6_hdr(skb)->payload_len = 0;
5772 tcp_hdr(skb)->check =
5773 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5774 &ipv6_hdr(skb)->daddr,
5775 0, IPPROTO_TCP, 0);
244e27ad
AD		 5776 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5777 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5778 }
5779
091a6246 5780 /* compute header lengths */
897ab156
AD		 5781 l4len = tcp_hdrlen(skb);
5782 *hdr_len = skb_transport_offset(skb) + l4len;
5783
091a6246
AD		 5784 /* update gso size and bytecount with header size */
5785 first->gso_segs = skb_shinfo(skb)->gso_segs;
5786 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5787
897ab156
AD		 5788 /* mss_l4len_id: use 1 as index for TSO */
5789 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5790 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5791 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5792
5793 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5794 vlan_macip_lens = skb_network_header_len(skb);
5795 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5796 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5797
5798 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5799 mss_l4len_idx);
897ab156
AD		 5800
5801 return 1;
5802}
5803
244e27ad
AD		 5804static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5805 struct ixgbe_tx_buffer *first)
7ca647bd 5806{
fd0db0ed 5807 struct sk_buff *skb = first->skb;
897ab156
AD		 5808 u32 vlan_macip_lens = 0;
5809 u32 mss_l4len_idx = 0;
5810 u32 type_tucmd = 0;
7ca647bd 5811
897ab156 5812 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5813 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5814 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5815 return;
897ab156
AD		 5816 } else {
5817 u8 l4_hdr = 0;
244e27ad 5818 switch (first->protocol) {
897ab156
AD		 5819 case __constant_htons(ETH_P_IP):
5820 vlan_macip_lens |= skb_network_header_len(skb);
5821 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5822 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5823 break;
897ab156
AD		 5824 case __constant_htons(ETH_P_IPV6):
5825 vlan_macip_lens |= skb_network_header_len(skb);
5826 l4_hdr = ipv6_hdr(skb)->nexthdr;
5827 break;
5828 default:
5829 if (unlikely(net_ratelimit())) {
5830 dev_warn(tx_ring->dev,
5831 "partial checksum but proto=%x!\n",
244e27ad 5832 first->protocol);
897ab156 5833 }
7ca647bd
JP		 5834 break;
5835 }
897ab156
AD		 5836
5837 switch (l4_hdr) {
7ca647bd 5838 case IPPROTO_TCP:
897ab156
AD		 5839 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5840 mss_l4len_idx = tcp_hdrlen(skb) <<
5841 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5842 break;
5843 case IPPROTO_SCTP:
897ab156
AD		 5844 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5845 mss_l4len_idx = sizeof(struct sctphdr) <<
5846 IXGBE_ADVTXD_L4LEN_SHIFT;
5847 break;
5848 case IPPROTO_UDP:
5849 mss_l4len_idx = sizeof(struct udphdr) <<
5850 IXGBE_ADVTXD_L4LEN_SHIFT;
5851 break;
5852 default:
5853 if (unlikely(net_ratelimit())) {
5854 dev_warn(tx_ring->dev,
5855 "partial checksum but l4 proto=%x!\n",
244e27ad 5856 l4_hdr);
897ab156 5857 }
7ca647bd
JP		 5858 break;
5859 }
244e27ad
AD		 5860
5861 /* update TX checksum flag */
5862 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5863 }
5864
244e27ad 5865 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5866 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5867 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5868
897ab156
AD		 5869 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5870 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5871}
5872
d3d00239 5873static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5874{
d3d00239
AD		 5875 /* set type for advanced descriptor with frame checksum insertion */
5876 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5877 IXGBE_ADVTXD_DCMD_IFCS |
5878 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5879
d3d00239 5880 /* set HW vlan bit if vlan is present */
66f32a8b 5881 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5882 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5883
3a6a4eda
JK		 5884#ifdef CONFIG_IXGBE_PTP
5885 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5886 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5887#endif
5888
d3d00239
AD		 5889 /* set segmentation enable bits for TSO/FSO */
5890#ifdef IXGBE_FCOE
93f5b3c1 5891 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5892#else
5893 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5894#endif
5895 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5896
d3d00239
AD		 5897 return cmd_type;
5898}
9a799d71 5899
729739b7
AD		 5900static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5901 u32 tx_flags, unsigned int paylen)
d3d00239 5902{
93f5b3c1 5903 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5904
d3d00239
AD		 5905 /* enable L4 checksum for TSO and TX checksum offload */
5906 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5907 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 5908
93f5b3c1
AD		 5909 /* enble IPv4 checksum for TSO */
5910 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5911 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 5912
93f5b3c1
AD		 5913 /* use index 1 context for TSO/FSO/FCOE */
5914#ifdef IXGBE_FCOE
5915 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5916#else
5917 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 5918#endif
93f5b3c1
AD		 5919 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5920
7f9643fd
AD		 5921 /*
5922 * Check Context must be set if Tx switch is enabled, which it
5923 * always is for case where virtual functions are running
5924 */
93f5b3c1
AD		 5925#ifdef IXGBE_FCOE
5926 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5927#else
7f9643fd 5928 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 5929#endif
7f9643fd
AD		 5930 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5931
729739b7 5932 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 5933}
44df32c5 5934
d3d00239
AD		 5935#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5936 IXGBE_TXD_CMD_RS)
5937
5938static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 5939 struct ixgbe_tx_buffer *first,
d3d00239
AD		 5940 const u8 hdr_len)
5941{
729739b7 5942 dma_addr_t dma;
fd0db0ed 5943 struct sk_buff *skb = first->skb;
729739b7 5944 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 5945 union ixgbe_adv_tx_desc *tx_desc;
729739b7 5946 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 5947 unsigned int data_len = skb->data_len;
5948 unsigned int size = skb_headlen(skb);
729739b7 5949 unsigned int paylen = skb->len - hdr_len;
244e27ad 5950 u32 tx_flags = first->tx_flags;
729739b7 5951 __le32 cmd_type;
d3d00239 5952 u16 i = tx_ring->next_to_use;
d3d00239 5953
729739b7
AD		 5954 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5955
5956 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5957 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5958
d3d00239
AD		 5959#ifdef IXGBE_FCOE
5960 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 5961 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 5962 size -= sizeof(struct fcoe_crc_eof) - data_len;
5963 data_len = 0;
729739b7
AD		 5964 } else {
5965 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 5966 }
5967 }
44df32c5 5968
d3d00239 5969#endif
729739b7
AD		 5970 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5971 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 5972 goto dma_error;
8ad494b0 5973
729739b7
AD		 5974 /* record length, and DMA address */
5975 dma_unmap_len_set(first, len, size);
5976 dma_unmap_addr_set(first, dma, dma);
9a799d71 5977
729739b7 5978 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 5979
d3d00239 5980 for (;;) {
729739b7 5981 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 5982 tx_desc->read.cmd_type_len =
5983 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 5984
d3d00239 5985 i++;
729739b7 5986 tx_desc++;
d3d00239 5987 if (i == tx_ring->count) {
e4f74028 5988 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 5989 i = 0;
5990 }
729739b7
AD		 5991
5992 dma += IXGBE_MAX_DATA_PER_TXD;
5993 size -= IXGBE_MAX_DATA_PER_TXD;
5994
5995 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5996 tx_desc->read.olinfo_status = 0;
d3d00239 5997 }
e5a43549 5998
729739b7
AD		 5999 if (likely(!data_len))
6000 break;
9a799d71 6001
f43f313e
BG		 6002 if (unlikely(skb->no_fcs))
6003 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6004 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6005
729739b7
AD		 6006 i++;
6007 tx_desc++;
6008 if (i == tx_ring->count) {
6009 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6010 i = 0;
6011 }
9a799d71 6012
d3d00239 6013#ifdef IXGBE_FCOE
9e903e08 6014 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6015#else
9e903e08 6016 size = skb_frag_size(frag);
d3d00239
AD		 6017#endif
6018 data_len -= size;
9a799d71 6019
729739b7
AD		 6020 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6021 DMA_TO_DEVICE);
6022 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6023 goto dma_error;
9a799d71 6024
729739b7
AD		 6025 tx_buffer = &tx_ring->tx_buffer_info[i];
6026 dma_unmap_len_set(tx_buffer, len, size);
6027 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6028
729739b7
AD		 6029 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6030 tx_desc->read.olinfo_status = 0;
9a799d71 6031
729739b7
AD		 6032 frag++;
6033 }
9a799d71 6034
729739b7
AD		 6035 /* write last descriptor with RS and EOP bits */
6036 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6037 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6038
091a6246 6039 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6040
d3d00239
AD		 6041 /* set the timestamp */
6042 first->time_stamp = jiffies;
9a799d71
AK		 6043
6044 /*
729739b7
AD		 6045 * Force memory writes to complete before letting h/w know there
6046 * are new descriptors to fetch. (Only applicable for weak-ordered
6047 * memory model archs, such as IA-64).
6048 *
6049 * We also need this memory barrier to make certain all of the
6050 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6051 */
6052 wmb();
6053
d3d00239
AD		 6054 /* set next_to_watch value indicating a packet is present */
6055 first->next_to_watch = tx_desc;
6056
729739b7
AD		 6057 i++;
6058 if (i == tx_ring->count)
6059 i = 0;
6060
6061 tx_ring->next_to_use = i;
6062
d3d00239 6063 /* notify HW of packet */
84ea2591 6064 writel(i, tx_ring->tail);
d3d00239
AD		 6065
6066 return;
6067dma_error:
729739b7 6068 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6069
6070 /* clear dma mappings for failed tx_buffer_info map */
6071 for (;;) {
729739b7
AD		 6072 tx_buffer = &tx_ring->tx_buffer_info[i];
6073 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6074 if (tx_buffer == first)
d3d00239
AD		 6075 break;
6076 if (i == 0)
6077 i = tx_ring->count;
6078 i--;
6079 }
6080
d3d00239 6081 tx_ring->next_to_use = i;
9a799d71
AK		 6082}
6083
fd0db0ed 6084static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6085 struct ixgbe_tx_buffer *first)
69830529
AD		 6086{
6087 struct ixgbe_q_vector *q_vector = ring->q_vector;
6088 union ixgbe_atr_hash_dword input = { .dword = 0 };
6089 union ixgbe_atr_hash_dword common = { .dword = 0 };
6090 union {
6091 unsigned char *network;
6092 struct iphdr *ipv4;
6093 struct ipv6hdr *ipv6;
6094 } hdr;
ee9e0f0b 6095 struct tcphdr *th;
905e4a41 6096 __be16 vlan_id;
c4cf55e5 6097
69830529
AD		 6098 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6099 if (!q_vector)
6100 return;
6101
6102 /* do nothing if sampling is disabled */
6103 if (!ring->atr_sample_rate)
d3ead241 6104 return;
c4cf55e5 6105
69830529 6106 ring->atr_count++;
c4cf55e5 6107
69830529 6108 /* snag network header to get L4 type and address */
fd0db0ed 6109 hdr.network = skb_network_header(first->skb);
69830529
AD		 6110
6111 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6112 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6113 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6114 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6115 hdr.ipv4->protocol != IPPROTO_TCP))
6116 return;
ee9e0f0b 6117
fd0db0ed 6118 th = tcp_hdr(first->skb);
c4cf55e5 6119
66f32a8b
AD		 6120 /* skip this packet since it is invalid or the socket is closing */
6121 if (!th || th->fin)
69830529
AD		 6122 return;
6123
6124 /* sample on all syn packets or once every atr sample count */
6125 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6126 return;
6127
6128 /* reset sample count */
6129 ring->atr_count = 0;
6130
244e27ad 6131 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6132
6133 /*
6134 * src and dst are inverted, think how the receiver sees them
6135 *
6136 * The input is broken into two sections, a non-compressed section
6137 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6138 * is XORed together and stored in the compressed dword.
6139 */
6140 input.formatted.vlan_id = vlan_id;
6141
6142 /*
6143 * since src port and flex bytes occupy the same word XOR them together
6144 * and write the value to source port portion of compressed dword
6145 */
244e27ad 6146 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6147 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6148 else
244e27ad 6149 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6150 common.port.dst ^= th->source;
6151
244e27ad 6152 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6153 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6154 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6155 } else {
6156 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6157 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6158 hdr.ipv6->saddr.s6_addr32[1] ^
6159 hdr.ipv6->saddr.s6_addr32[2] ^
6160 hdr.ipv6->saddr.s6_addr32[3] ^
6161 hdr.ipv6->daddr.s6_addr32[0] ^
6162 hdr.ipv6->daddr.s6_addr32[1] ^
6163 hdr.ipv6->daddr.s6_addr32[2] ^
6164 hdr.ipv6->daddr.s6_addr32[3];
6165 }
c4cf55e5
PWJ		 6166
6167 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6168 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6169 input, common, ring->queue_index);
c4cf55e5
PWJ		 6170}
6171
63544e9c 6172static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6173{
fc77dc3c 6174 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6175 /* Herbert's original patch had:
6176 * smp_mb__after_netif_stop_queue();
6177 * but since that doesn't exist yet, just open code it. */
6178 smp_mb();
6179
6180 /* We need to check again in a case another CPU has just
6181 * made room available. */
7d4987de 6182 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6183 return -EBUSY;
6184
6185 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6186 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6187 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6188 return 0;
6189}
6190
82d4e46e 6191static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6192{
7d4987de 6193 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6194 return 0;
fc77dc3c 6195 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6196}
6197
09a3b1f8
SH		 6198static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6199{
6200 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6201 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6202 smp_processor_id();
56075a98 6203#ifdef IXGBE_FCOE
6440752c 6204 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6205
e5b64635
JF		 6206 if (((protocol == htons(ETH_P_FCOE)) ||
6207 (protocol == htons(ETH_P_FIP))) &&
6208 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6209 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6210 txq += adapter->ring_feature[RING_F_FCOE].mask;
6211 return txq;
56075a98
JF		 6212 }
6213#endif
6214
fdd3d631
KK		 6215 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6216 while (unlikely(txq >= dev->real_num_tx_queues))
6217 txq -= dev->real_num_tx_queues;
5f715823 6218 return txq;
fdd3d631 6219 }
c4cf55e5 6220
09a3b1f8
SH		 6221 return skb_tx_hash(dev, skb);
6222}
6223
fc77dc3c 6224netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6225 struct ixgbe_adapter *adapter,
6226 struct ixgbe_ring *tx_ring)
9a799d71 6227{
d3d00239 6228 struct ixgbe_tx_buffer *first;
5f715823 6229 int tso;
d3d00239 6230 u32 tx_flags = 0;
a535c30e
AD		 6231#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6232 unsigned short f;
6233#endif
a535c30e 6234 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6235 __be16 protocol = skb->protocol;
63544e9c 6236 u8 hdr_len = 0;
5e09a105 6237
a535c30e
AD		 6238 /*
6239 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6240 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6241 * + 2 desc gap to keep tail from touching head,
6242 * + 1 desc for context descriptor,
6243 * otherwise try next time
6244 */
6245#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6246 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6247 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6248#else
6249 count += skb_shinfo(skb)->nr_frags;
6250#endif
6251 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6252 tx_ring->tx_stats.tx_busy++;
6253 return NETDEV_TX_BUSY;
6254 }
6255
fd0db0ed
AD		 6256 /* record the location of the first descriptor for this packet */
6257 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6258 first->skb = skb;
091a6246
AD		 6259 first->bytecount = skb->len;
6260 first->gso_segs = 1;
fd0db0ed 6261
66f32a8b 6262 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6263 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6264 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6265 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6266 /* else if it is a SW VLAN check the next protocol and store the tag */
6267 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6268 struct vlan_hdr *vhdr, _vhdr;
6269 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6270 if (!vhdr)
6271 goto out_drop;
6272
6273 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6274 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6275 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6276 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6277 }
6278
aa7bd467
JK		 6279 skb_tx_timestamp(skb);
6280
3a6a4eda
JK		 6281#ifdef CONFIG_IXGBE_PTP
6282 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6283 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6284 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6285 }
6286#endif
6287
9e0c5648
AD		 6288#ifdef CONFIG_PCI_IOV
6289 /*
6290 * Use the l2switch_enable flag - would be false if the DMA
6291 * Tx switch had been disabled.
6292 */
6293 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6294 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6295
6296#endif
32701dc2 6297 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6298 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6299 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6300 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6301 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6302 tx_flags |= (skb->priority & 0x7) <<
6303 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6304 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6305 struct vlan_ethhdr *vhdr;
6306 if (skb_header_cloned(skb) &&
6307 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6308 goto out_drop;
6309 vhdr = (struct vlan_ethhdr *)skb->data;
6310 vhdr->h_vlan_TCI = htons(tx_flags >>
6311 IXGBE_TX_FLAGS_VLAN_SHIFT);
6312 } else {
6313 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6314 }
9a799d71 6315 }
eacd73f7 6316
244e27ad
AD		 6317 /* record initial flags and protocol */
6318 first->tx_flags = tx_flags;
6319 first->protocol = protocol;
6320
eacd73f7 6321#ifdef IXGBE_FCOE
66f32a8b
AD		 6322 /* setup tx offload for FCoE */
6323 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6324 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
244e27ad 6325 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6326 if (tso < 0)
6327 goto out_drop;
9a799d71 6328
66f32a8b 6329 goto xmit_fcoe;
eacd73f7 6330 }
9a799d71 6331
66f32a8b 6332#endif /* IXGBE_FCOE */
244e27ad 6333 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6334 if (tso < 0)
897ab156 6335 goto out_drop;
244e27ad
AD		 6336 else if (!tso)
6337 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6338
6339 /* add the ATR filter if ATR is on */
6340 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6341 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6342
6343#ifdef IXGBE_FCOE
6344xmit_fcoe:
6345#endif /* IXGBE_FCOE */
244e27ad 6346 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6347
6348 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6349
6350 return NETDEV_TX_OK;
897ab156
AD		 6351
6352out_drop:
fd0db0ed
AD		 6353 dev_kfree_skb_any(first->skb);
6354 first->skb = NULL;
6355
897ab156 6356 return NETDEV_TX_OK;
9a799d71
AK		 6357}
6358
a50c29dd
AD		 6359static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6360 struct net_device *netdev)
84418e3b
AD		 6361{
6362 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6363 struct ixgbe_ring *tx_ring;
6364
a50c29dd
AD		 6365 /*
6366 * The minimum packet size for olinfo paylen is 17 so pad the skb
6367 * in order to meet this minimum size requirement.
6368 */
f73332fc
SH		 6369 if (unlikely(skb->len < 17)) {
6370 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6371 return NETDEV_TX_OK;
6372 skb->len = 17;
6373 }
6374
84418e3b 6375 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6376 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6377}
6378
9a799d71
AK		 6379/**
6380 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6381 * @netdev: network interface device structure
6382 * @p: pointer to an address structure
6383 *
6384 * Returns 0 on success, negative on failure
6385 **/
6386static int ixgbe_set_mac(struct net_device *netdev, void *p)
6387{
6388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6389 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6390 struct sockaddr *addr = p;
6391
6392 if (!is_valid_ether_addr(addr->sa_data))
6393 return -EADDRNOTAVAIL;
6394
6395 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6396 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6397
1cdd1ec8
GR		 6398 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6399 IXGBE_RAH_AV);
9a799d71
AK		 6400
6401 return 0;
6402}
6403
6b73e10d
BH		 6404static int
6405ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6406{
6407 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6408 struct ixgbe_hw *hw = &adapter->hw;
6409 u16 value;
6410 int rc;
6411
6412 if (prtad != hw->phy.mdio.prtad)
6413 return -EINVAL;
6414 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6415 if (!rc)
6416 rc = value;
6417 return rc;
6418}
6419
6420static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6421 u16 addr, u16 value)
6422{
6423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6424 struct ixgbe_hw *hw = &adapter->hw;
6425
6426 if (prtad != hw->phy.mdio.prtad)
6427 return -EINVAL;
6428 return hw->phy.ops.write_reg(hw, addr, devad, value);
6429}
6430
6431static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6432{
6433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6434
3a6a4eda
JK		 6435 switch (cmd) {
6436#ifdef CONFIG_IXGBE_PTP
6437 case SIOCSHWTSTAMP:
6438 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6439#endif
6440 default:
6441 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6442 }
6b73e10d
BH		 6443}
6444
0365e6e4
PW		 6445/**
6446 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6447 * netdev->dev_addrs
0365e6e4
PW		 6448 * @netdev: network interface device structure
6449 *
6450 * Returns non-zero on failure
6451 **/
6452static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6453{
6454 int err = 0;
6455 struct ixgbe_adapter *adapter = netdev_priv(dev);
6456 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6457
6458 if (is_valid_ether_addr(mac->san_addr)) {
6459 rtnl_lock();
6460 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6461 rtnl_unlock();
6462 }
6463 return err;
6464}
6465
6466/**
6467 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6468 * netdev->dev_addrs
0365e6e4
PW		 6469 * @netdev: network interface device structure
6470 *
6471 * Returns non-zero on failure
6472 **/
6473static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6474{
6475 int err = 0;
6476 struct ixgbe_adapter *adapter = netdev_priv(dev);
6477 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6478
6479 if (is_valid_ether_addr(mac->san_addr)) {
6480 rtnl_lock();
6481 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6482 rtnl_unlock();
6483 }
6484 return err;
6485}
6486
9a799d71
AK		 6487#ifdef CONFIG_NET_POLL_CONTROLLER
6488/*
6489 * Polling 'interrupt' - used by things like netconsole to send skbs
6490 * without having to re-enable interrupts. It's not called while
6491 * the interrupt routine is executing.
6492 */
6493static void ixgbe_netpoll(struct net_device *netdev)
6494{
6495 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6496 int i;
9a799d71 6497
1a647bd2
AD		 6498 /* if interface is down do nothing */
6499 if (test_bit(__IXGBE_DOWN, &adapter->state))
6500 return;
6501
9a799d71 6502 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6503 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6504 for (i = 0; i < adapter->num_q_vectors; i++)
6505 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6506 } else {
6507 ixgbe_intr(adapter->pdev->irq, netdev);
6508 }
9a799d71 6509 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6510}
9a799d71 6511
581330ba 6512#endif
de1036b1
ED		 6513static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6514 struct rtnl_link_stats64 *stats)
6515{
6516 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6517 int i;
6518
1a51502b 6519 rcu_read_lock();
de1036b1 6520 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6521 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6522 u64 bytes, packets;
6523 unsigned int start;
6524
1a51502b
ED		 6525 if (ring) {
6526 do {
6527 start = u64_stats_fetch_begin_bh(&ring->syncp);
6528 packets = ring->stats.packets;
6529 bytes = ring->stats.bytes;
6530 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6531 stats->rx_packets += packets;
6532 stats->rx_bytes += bytes;
6533 }
de1036b1 6534 }
1ac9ad13
ED		 6535
6536 for (i = 0; i < adapter->num_tx_queues; i++) {
6537 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6538 u64 bytes, packets;
6539 unsigned int start;
6540
6541 if (ring) {
6542 do {
6543 start = u64_stats_fetch_begin_bh(&ring->syncp);
6544 packets = ring->stats.packets;
6545 bytes = ring->stats.bytes;
6546 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6547 stats->tx_packets += packets;
6548 stats->tx_bytes += bytes;
6549 }
6550 }
1a51502b 6551 rcu_read_unlock();
de1036b1
ED		 6552 /* following stats updated by ixgbe_watchdog_task() */
6553 stats->multicast = netdev->stats.multicast;
6554 stats->rx_errors = netdev->stats.rx_errors;
6555 stats->rx_length_errors = netdev->stats.rx_length_errors;
6556 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6557 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6558 return stats;
6559}
6560
8af3c33f 6561#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6562/**
6563 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6564 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6565 * @tc: number of traffic classes currently enabled
6566 *
6567 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6568 * 802.1Q priority maps to a packet buffer that exists.
6569 */
6570static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6571{
6572 struct ixgbe_hw *hw = &adapter->hw;
6573 u32 reg, rsave;
6574 int i;
6575
6576 /* 82598 have a static priority to TC mapping that can not
6577 * be changed so no validation is needed.
6578 */
6579 if (hw->mac.type == ixgbe_mac_82598EB)
6580 return;
6581
6582 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6583 rsave = reg;
6584
6585 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6586 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6587
6588 /* If up2tc is out of bounds default to zero */
6589 if (up2tc > tc)
6590 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6591 }
6592
6593 if (reg != rsave)
6594 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6595
6596 return;
6597}
6598
49ce9c2c
BH		 6599/**
6600 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6601 *
6602 * @netdev: net device to configure
6603 * @tc: number of traffic classes to enable
6604 */
6605int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6606{
8b1c0b24
JF		 6607 struct ixgbe_adapter *adapter = netdev_priv(dev);
6608 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6609
e7589eab
JF		 6610 /* Multiple traffic classes requires multiple queues */
6611 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6612 e_err(drv, "Enable failed, needs MSI-X\n");
6613 return -EINVAL;
6614 }
8b1c0b24 6615
d4e41649
AD		 6616 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6617 e_err(drv, "Enable failed, SR-IOV enabled\n");
6618 return -EINVAL;
6619 }
6620
8b1c0b24 6621 /* Hardware supports up to 8 traffic classes */
4de2a022 6622 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6623 (hw->mac.type == ixgbe_mac_82598EB &&
6624 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6625 return -EINVAL;
6626
6627 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6628 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6629 * hardware is not flexible enough to do this dynamically.
6630 */
6631 if (netif_running(dev))
6632 ixgbe_close(dev);
6633 ixgbe_clear_interrupt_scheme(adapter);
6634
e7589eab 6635 if (tc) {
8b1c0b24 6636 netdev_set_num_tc(dev, tc);
e7589eab
JF		 6637 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6638 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6639
943561d3
AD		 6640 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6641 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6642 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6643 }
e7589eab 6644 } else {
8b1c0b24 6645 netdev_reset_tc(dev);
943561d3
AD		 6646 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6647 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6648
6649 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6650 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6651
6652 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6653 adapter->dcb_cfg.pfc_mode_enable = false;
6654 }
6655
8b1c0b24
JF		 6656 ixgbe_init_interrupt_scheme(adapter);
6657 ixgbe_validate_rtr(adapter, tc);
6658 if (netif_running(dev))
6659 ixgbe_open(dev);
6660
6661 return 0;
6662}
de1036b1 6663
8af3c33f 6664#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6665void ixgbe_do_reset(struct net_device *netdev)
6666{
6667 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6668
6669 if (netif_running(netdev))
6670 ixgbe_reinit_locked(adapter);
6671 else
6672 ixgbe_reset(adapter);
6673}
6674
c8f44aff 6675static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6676 netdev_features_t features)
082757af
DS		 6677{
6678 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6679
082757af
DS		 6680 /* return error if RXHASH is being enabled when RSS is not supported */
6681 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
567d2de2 6682 features &= ~NETIF_F_RXHASH;
082757af
DS		 6683
6684 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6685 if (!(features & NETIF_F_RXCSUM))
6686 features &= ~NETIF_F_LRO;
082757af 6687
567d2de2
AD		 6688 /* Turn off LRO if not RSC capable */
6689 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6690 features &= ~NETIF_F_LRO;
8e2813f5 6691
567d2de2 6692 return features;
082757af
DS		 6693}
6694
c8f44aff 6695static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6696 netdev_features_t features)
082757af
DS		 6697{
6698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6699 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6700 bool need_reset = false;
6701
082757af 6702 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6703 if (!(features & NETIF_F_LRO)) {
6704 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6705 need_reset = true;
567d2de2
AD		 6706 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6707 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6708 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6709 if (adapter->rx_itr_setting == 1 ||
6710 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6711 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6712 need_reset = true;
6713 } else if ((changed ^ features) & NETIF_F_LRO) {
6714 e_info(probe, "rx-usecs set too low, "
6715 "disabling RSC\n");
082757af
DS		 6716 }
6717 }
6718
6719 /*
6720 * Check if Flow Director n-tuple support was enabled or disabled. If
6721 * the state changed, we need to reset.
6722 */
567d2de2
AD		 6723 if (!(features & NETIF_F_NTUPLE)) {
6724 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6725 /* turn off Flow Director, set ATR and reset */
6726 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6727 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6728 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 6729 need_reset = true;
6730 }
082757af 6731 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
567d2de2
AD		 6732 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6733 /* turn off ATR, enable perfect filters and reset */
6734 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6735 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
082757af
DS		 6736 need_reset = true;
6737 }
6738
146d4cc9
JF		 6739 if (features & NETIF_F_HW_VLAN_RX)
6740 ixgbe_vlan_strip_enable(adapter);
6741 else
6742 ixgbe_vlan_strip_disable(adapter);
6743
3f2d1c0f
BG		 6744 if (changed & NETIF_F_RXALL)
6745 need_reset = true;
6746
567d2de2 6747 netdev->features = features;
082757af
DS		 6748 if (need_reset)
6749 ixgbe_do_reset(netdev);
6750
6751 return 0;
082757af
DS		 6752}
6753
0f4b0add
JF		 6754static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6755 struct net_device *dev,
6756 unsigned char *addr,
6757 u16 flags)
6758{
6759 struct ixgbe_adapter *adapter = netdev_priv(dev);
6760 int err = -EOPNOTSUPP;
6761
6762 if (ndm->ndm_state & NUD_PERMANENT) {
6763 pr_info("%s: FDB only supports static addresses\n",
6764 ixgbe_driver_name);
6765 return -EINVAL;
6766 }
6767
6768 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6769 if (is_unicast_ether_addr(addr))
6770 err = dev_uc_add_excl(dev, addr);
6771 else if (is_multicast_ether_addr(addr))
6772 err = dev_mc_add_excl(dev, addr);
6773 else
6774 err = -EINVAL;
6775 }
6776
6777 /* Only return duplicate errors if NLM_F_EXCL is set */
6778 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6779 err = 0;
6780
6781 return err;
6782}
6783
6784static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6785 struct net_device *dev,
6786 unsigned char *addr)
6787{
6788 struct ixgbe_adapter *adapter = netdev_priv(dev);
6789 int err = -EOPNOTSUPP;
6790
6791 if (ndm->ndm_state & NUD_PERMANENT) {
6792 pr_info("%s: FDB only supports static addresses\n",
6793 ixgbe_driver_name);
6794 return -EINVAL;
6795 }
6796
6797 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6798 if (is_unicast_ether_addr(addr))
6799 err = dev_uc_del(dev, addr);
6800 else if (is_multicast_ether_addr(addr))
6801 err = dev_mc_del(dev, addr);
6802 else
6803 err = -EINVAL;
6804 }
6805
6806 return err;
6807}
6808
6809static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6810 struct netlink_callback *cb,
6811 struct net_device *dev,
6812 int idx)
6813{
6814 struct ixgbe_adapter *adapter = netdev_priv(dev);
6815
6816 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6817 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6818
6819 return idx;
6820}
6821
0edc3527 6822static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6823 .ndo_open = ixgbe_open,
0edc3527 6824 .ndo_stop = ixgbe_close,
00829823 6825 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6826 .ndo_select_queue = ixgbe_select_queue,
581330ba 6827 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6828 .ndo_validate_addr = eth_validate_addr,
6829 .ndo_set_mac_address = ixgbe_set_mac,
6830 .ndo_change_mtu = ixgbe_change_mtu,
6831 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6832 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6833 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6834 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6835 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6836 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6837 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6838 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6839 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6840 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6841#ifdef CONFIG_IXGBE_DCB
24095aa3 6842 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6843#endif
0edc3527
SH		 6844#ifdef CONFIG_NET_POLL_CONTROLLER
6845 .ndo_poll_controller = ixgbe_netpoll,
6846#endif
332d4a7d
YZ		 6847#ifdef IXGBE_FCOE
6848 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6849 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6850 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6851 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6852 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6853 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6854 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6855#endif /* IXGBE_FCOE */
082757af
DS		 6856 .ndo_set_features = ixgbe_set_features,
6857 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6858 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6859 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6860 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 6861};
6862
1cdd1ec8 6863static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
567d2de2 6864 const struct ixgbe_info *ii)
1cdd1ec8
GR		 6865{
6866#ifdef CONFIG_PCI_IOV
6867 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 6868
c6bda30a 6869 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 6870 return;
6871
6872 /* The 82599 supports up to 64 VFs per physical function
6873 * but this implementation limits allocation to 63 so that
6874 * basic networking resources are still available to the
6b42a9c5
GR		 6875 * physical function. If the user requests greater thn
6876 * 63 VFs then it is an error - reset to default of zero.
1cdd1ec8 6877 */
6b42a9c5 6878 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
c6bda30a 6879 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 6880#endif /* CONFIG_PCI_IOV */
6881}
6882
8e2813f5
JK		 6883/**
6884 * ixgbe_wol_supported - Check whether device supports WoL
6885 * @hw: hw specific details
6886 * @device_id: the device ID
6887 * @subdev_id: the subsystem device ID
6888 *
6889 * This function is used by probe and ethtool to determine
6890 * which devices have WoL support
6891 *
6892 **/
6893int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6894 u16 subdevice_id)
6895{
6896 struct ixgbe_hw *hw = &adapter->hw;
6897 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6898 int is_wol_supported = 0;
6899
6900 switch (device_id) {
6901 case IXGBE_DEV_ID_82599_SFP:
6902 /* Only these subdevices could supports WOL */
6903 switch (subdevice_id) {
6904 case IXGBE_SUBDEV_ID_82599_560FLR:
6905 /* only support first port */
6906 if (hw->bus.func != 0)
6907 break;
6908 case IXGBE_SUBDEV_ID_82599_SFP:
6909 is_wol_supported = 1;
6910 break;
6911 }
6912 break;
6913 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6914 /* All except this subdevice support WOL */
6915 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6916 is_wol_supported = 1;
6917 break;
6918 case IXGBE_DEV_ID_82599_KX4:
6919 is_wol_supported = 1;
6920 break;
6921 case IXGBE_DEV_ID_X540T:
6922 /* check eeprom to see if enabled wol */
6923 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6924 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6925 (hw->bus.func == 0))) {
6926 is_wol_supported = 1;
6927 }
6928 break;
6929 }
6930
6931 return is_wol_supported;
6932}
6933
9a799d71
AK		 6934/**
6935 * ixgbe_probe - Device Initialization Routine
6936 * @pdev: PCI device information struct
6937 * @ent: entry in ixgbe_pci_tbl
6938 *
6939 * Returns 0 on success, negative on failure
6940 *
6941 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6942 * The OS initialization, configuring of the adapter private structure,
6943 * and a hardware reset occur.
6944 **/
6945static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6946 const struct pci_device_id *ent)
9a799d71
AK		 6947{
6948 struct net_device *netdev;
6949 struct ixgbe_adapter *adapter = NULL;
6950 struct ixgbe_hw *hw;
6951 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6952 static int cards_found;
6953 int i, err, pci_using_dac;
289700db 6954 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 6955 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6956#ifdef IXGBE_FCOE
6957 u16 device_caps;
6958#endif
289700db 6959 u32 eec;
9a799d71 6960
bded64a7
AG		 6961 /* Catch broken hardware that put the wrong VF device ID in
6962 * the PCIe SR-IOV capability.
6963 */
6964 if (pdev->is_virtfn) {
6965 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6966 pci_name(pdev), pdev->vendor, pdev->device);
6967 return -EINVAL;
6968 }
6969
9ce77666 6970 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6971 if (err)
6972 return err;
6973
1b507730
NN		 6974 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6975 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6976 pci_using_dac = 1;
6977 } else {
1b507730 6978 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6979 if (err) {
1b507730
NN		 6980 err = dma_set_coherent_mask(&pdev->dev,
6981 DMA_BIT_MASK(32));
9a799d71 6982 if (err) {
b8bc0421
DC		 6983 dev_err(&pdev->dev,
6984 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6985 goto err_dma;
6986 }
6987 }
6988 pci_using_dac = 0;
6989 }
6990
9ce77666 6991 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6992 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6993 if (err) {
b8bc0421
DC		 6994 dev_err(&pdev->dev,
6995 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6996 goto err_pci_reg;
6997 }
6998
19d5afd4 6999 pci_enable_pcie_error_reporting(pdev);
6fabd715 7000
9a799d71 7001 pci_set_master(pdev);
fb3b27bc 7002 pci_save_state(pdev);
9a799d71 7003
e901acd6
JF		 7004#ifdef CONFIG_IXGBE_DCB
7005 indices *= MAX_TRAFFIC_CLASS;
7006#endif
7007
c85a2618
JF		 7008 if (ii->mac == ixgbe_mac_82598EB)
7009 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7010 else
7011 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7012
e901acd6 7013#ifdef IXGBE_FCOE
c85a2618
JF		 7014 indices += min_t(unsigned int, num_possible_cpus(),
7015 IXGBE_MAX_FCOE_INDICES);
7016#endif
c85a2618 7017 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7018 if (!netdev) {
7019 err = -ENOMEM;
7020 goto err_alloc_etherdev;
7021 }
7022
9a799d71
AK		 7023 SET_NETDEV_DEV(netdev, &pdev->dev);
7024
9a799d71 7025 adapter = netdev_priv(netdev);
c60fbb00 7026 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7027
7028 adapter->netdev = netdev;
7029 adapter->pdev = pdev;
7030 hw = &adapter->hw;
7031 hw->back = adapter;
b3f4d599 7032 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7033
05857980 7034 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7035 pci_resource_len(pdev, 0));
9a799d71
AK		 7036 if (!hw->hw_addr) {
7037 err = -EIO;
7038 goto err_ioremap;
7039 }
7040
7041 for (i = 1; i <= 5; i++) {
7042 if (pci_resource_len(pdev, i) == 0)
7043 continue;
7044 }
7045
0edc3527 7046 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7047 ixgbe_set_ethtool_ops(netdev);
9a799d71 7048 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7049 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7050
9a799d71
AK		 7051 adapter->bd_number = cards_found;
7052
9a799d71
AK		 7053 /* Setup hw api */
7054 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7055 hw->mac.type = ii->mac;
9a799d71 7056
c44ade9e
JB		 7057 /* EEPROM */
7058 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7059 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7060 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7061 if (!(eec & (1 << 8)))
7062 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7063
7064 /* PHY */
7065 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7066 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7067 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7068 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7069 hw->phy.mdio.mmds = 0;
7070 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7071 hw->phy.mdio.dev = netdev;
7072 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7073 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7074
8ca783ab 7075 ii->get_invariants(hw);
9a799d71
AK		 7076
7077 /* setup the private structure */
7078 err = ixgbe_sw_init(adapter);
7079 if (err)
7080 goto err_sw_init;
7081
e86bff0e 7082 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7083 switch (adapter->hw.mac.type) {
7084 case ixgbe_mac_82599EB:
7085 case ixgbe_mac_X540:
e86bff0e 7086 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7087 break;
7088 default:
7089 break;
7090 }
e86bff0e 7091
bf069c97
DS		 7092 /*
7093 * If there is a fan on this device and it has failed log the
7094 * failure.
7095 */
7096 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7097 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7098 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7099 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7100 }
7101
8ef78adc
PWJ		 7102 if (allow_unsupported_sfp)
7103 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7104
c44ade9e 7105 /* reset_hw fills in the perm_addr as well */
119fc60a 7106 hw->phy.reset_if_overtemp = true;
c44ade9e 7107 err = hw->mac.ops.reset_hw(hw);
119fc60a 7108 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7109 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7110 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7111 err = 0;
7112 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7113 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7114 "module type was detected.\n");
7115 e_dev_err("Reload the driver after installing a supported "
7116 "module.\n");
04f165ef
PW		 7117 goto err_sw_init;
7118 } else if (err) {
849c4542 7119 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7120 goto err_sw_init;
7121 }
7122
1cdd1ec8
GR		 7123 ixgbe_probe_vf(adapter, ii);
7124
396e799c 7125 netdev->features = NETIF_F_SG |
e8e9f696 7126 NETIF_F_IP_CSUM |
082757af 7127 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7128 NETIF_F_HW_VLAN_TX |
7129 NETIF_F_HW_VLAN_RX |
082757af
DS		 7130 NETIF_F_HW_VLAN_FILTER |
7131 NETIF_F_TSO |
7132 NETIF_F_TSO6 |
082757af
DS		 7133 NETIF_F_RXHASH |
7134 NETIF_F_RXCSUM;
9a799d71 7135
082757af 7136 netdev->hw_features = netdev->features;
ad31c402 7137
58be7666
DS		 7138 switch (adapter->hw.mac.type) {
7139 case ixgbe_mac_82599EB:
7140 case ixgbe_mac_X540:
45a5ead0 7141 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7142 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7143 NETIF_F_NTUPLE;
58be7666
DS		 7144 break;
7145 default:
7146 break;
7147 }
45a5ead0 7148
3f2d1c0f
BG		 7149 netdev->hw_features |= NETIF_F_RXALL;
7150
ad31c402
JK		 7151 netdev->vlan_features |= NETIF_F_TSO;
7152 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7153 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7154 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7155 netdev->vlan_features |= NETIF_F_SG;
7156
01789349 7157 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7158 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7159
1cdd1ec8
GR		 7160 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7161 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7162 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7163
7a6b6f51 7164#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7165 netdev->dcbnl_ops = &dcbnl_ops;
7166#endif
7167
eacd73f7 7168#ifdef IXGBE_FCOE
0d551589 7169 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7170 if (hw->mac.ops.get_device_caps) {
7171 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7172 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7173 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7174 }
7175 }
5e09d7f6
YZ		 7176 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7177 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7178 netdev->vlan_features |= NETIF_F_FSO;
7179 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7180 }
eacd73f7 7181#endif /* IXGBE_FCOE */
7b872a55 7182 if (pci_using_dac) {
9a799d71 7183 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7184 netdev->vlan_features |= NETIF_F_HIGHDMA;
7185 }
9a799d71 7186
082757af
DS		 7187 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7188 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7189 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7190 netdev->features |= NETIF_F_LRO;
7191
9a799d71 7192 /* make sure the EEPROM is good */
c44ade9e 7193 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7194 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7195 err = -EIO;
35937c05 7196 goto err_sw_init;
9a799d71
AK		 7197 }
7198
7199 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7200 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7201
c44ade9e 7202 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7203 e_dev_err("invalid MAC address\n");
9a799d71 7204 err = -EIO;
35937c05 7205 goto err_sw_init;
9a799d71
AK		 7206 }
7207
7086400d 7208 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7209 (unsigned long) adapter);
9a799d71 7210
7086400d
AD		 7211 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7212 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7213
021230d4
AV		 7214 err = ixgbe_init_interrupt_scheme(adapter);
7215 if (err)
7216 goto err_sw_init;
9a799d71 7217
082757af
DS		 7218 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7219 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7220 netdev->features &= ~NETIF_F_RXHASH;
082757af 7221 }
67a74ee2 7222
8e2813f5 7223 /* WOL not supported for all devices */
c23f5b6b 7224 adapter->wol = 0;
8e2813f5
JK		 7225 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7226 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7227 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7228
e8e26350
PW		 7229 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7230
3a6a4eda
JK		 7231#ifdef CONFIG_IXGBE_PTP
7232 ixgbe_ptp_init(adapter);
7233#endif /* CONFIG_IXGBE_PTP*/
7234
15e5209f
ET		 7235 /* save off EEPROM version number */
7236 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7237 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7238
04f165ef
PW		 7239 /* pick up the PCI bus settings for reporting later */
7240 hw->mac.ops.get_bus_info(hw);
7241
9a799d71 7242 /* print bus type/speed/width info */
849c4542 7243 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7244 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7245 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7246 "Unknown"),
7247 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7248 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7249 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7250 "Unknown"),
7251 netdev->dev_addr);
289700db
DS		 7252
7253 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7254 if (err)
9fe93afd 7255 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7256 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7257 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7258 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7259 part_str);
e8e26350 7260 else
289700db
DS		 7261 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7262 hw->mac.type, hw->phy.type, part_str);
9a799d71 7263
e8e26350 7264 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7265 e_dev_warn("PCI-Express bandwidth available for this card is "
7266 "not sufficient for optimal performance.\n");
7267 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7268 "is required.\n");
0c254d86
AK		 7269 }
7270
9a799d71 7271 /* reset the hardware with the new settings */
794caeb2 7272 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7273 if (err == IXGBE_ERR_EEPROM_VERSION) {
7274 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7275 e_dev_warn("This device is a pre-production adapter/LOM. "
7276 "Please be aware there may be issues associated "
7277 "with your hardware. If you are experiencing "
7278 "problems please contact your Intel or hardware "
7279 "representative who provided you with this "
7280 "hardware.\n");
794caeb2 7281 }
9a799d71
AK		 7282 strcpy(netdev->name, "eth%d");
7283 err = register_netdev(netdev);
7284 if (err)
7285 goto err_register;
7286
93d3ce8f
ET		 7287 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7288 if (hw->mac.ops.disable_tx_laser &&
7289 ((hw->phy.multispeed_fiber) ||
7290 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7291 (hw->mac.type == ixgbe_mac_82599EB))))
7292 hw->mac.ops.disable_tx_laser(hw);
7293
54386467
JB		 7294 /* carrier off reporting is important to ethtool even BEFORE open */
7295 netif_carrier_off(netdev);
7296
5dd2d332 7297#ifdef CONFIG_IXGBE_DCA
652f093f 7298 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7299 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7300 ixgbe_setup_dca(adapter);
7301 }
7302#endif
1cdd1ec8 7303 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7304 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7305 for (i = 0; i < adapter->num_vfs; i++)
7306 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7307 }
7308
2466dd9c
JK		 7309 /* firmware requires driver version to be 0xFFFFFFFF
7310 * since os does not support feature
7311 */
9612de92 7312 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7313 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7314 0xFF);
9612de92 7315
0365e6e4
PW		 7316 /* add san mac addr to netdev */
7317 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7318
ea81875a 7319 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7320 cards_found++;
3ca8bc6d 7321
1210982b 7322#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7323 if (ixgbe_sysfs_init(adapter))
7324 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7325#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7326
9a799d71
AK		 7327 return 0;
7328
7329err_register:
5eba3699 7330 ixgbe_release_hw_control(adapter);
7a921c93 7331 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7332err_sw_init:
1cdd1ec8
GR		 7333 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7334 ixgbe_disable_sriov(adapter);
7086400d 7335 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7336 iounmap(hw->hw_addr);
7337err_ioremap:
7338 free_netdev(netdev);
7339err_alloc_etherdev:
e8e9f696
JP		 7340 pci_release_selected_regions(pdev,
7341 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7342err_pci_reg:
7343err_dma:
7344 pci_disable_device(pdev);
7345 return err;
7346}
7347
7348/**
7349 * ixgbe_remove - Device Removal Routine
7350 * @pdev: PCI device information struct
7351 *
7352 * ixgbe_remove is called by the PCI subsystem to alert the driver
7353 * that it should release a PCI device. The could be caused by a
7354 * Hot-Plug event, or because the driver is going to be removed from
7355 * memory.
7356 **/
7357static void __devexit ixgbe_remove(struct pci_dev *pdev)
7358{
c60fbb00
AD		 7359 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7360 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7361
7362 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7363 cancel_work_sync(&adapter->service_task);
9a799d71 7364
3a6a4eda
JK		 7365#ifdef CONFIG_IXGBE_PTP
7366 ixgbe_ptp_stop(adapter);
7367#endif
7368
5dd2d332 7369#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7371 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7372 dca_remove_requester(&pdev->dev);
7373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7374 }
7375
7376#endif
1210982b 7377#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7378 ixgbe_sysfs_exit(adapter);
1210982b 7379#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7380
332d4a7d
YZ		 7381#ifdef IXGBE_FCOE
7382 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7383 ixgbe_cleanup_fcoe(adapter);
7384
7385#endif /* IXGBE_FCOE */
0365e6e4
PW		 7386
7387 /* remove the added san mac */
7388 ixgbe_del_sanmac_netdev(netdev);
7389
c4900be0
DS		 7390 if (netdev->reg_state == NETREG_REGISTERED)
7391 unregister_netdev(netdev);
9a799d71 7392
c6bda30a
GR		 7393 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7394 if (!(ixgbe_check_vf_assignment(adapter)))
7395 ixgbe_disable_sriov(adapter);
7396 else
7397 e_dev_warn("Unloading driver while VFs are assigned "
7398 "- VFs will not be deallocated\n");
7399 }
1cdd1ec8 7400
7a921c93 7401 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7402
021230d4 7403 ixgbe_release_hw_control(adapter);
9a799d71 7404
2b1588c3
AD		 7405#ifdef CONFIG_DCB
7406 kfree(adapter->ixgbe_ieee_pfc);
7407 kfree(adapter->ixgbe_ieee_ets);
7408
7409#endif
9a799d71 7410 iounmap(adapter->hw.hw_addr);
9ce77666 7411 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7412 IORESOURCE_MEM));
9a799d71 7413
849c4542 7414 e_dev_info("complete\n");
021230d4 7415
9a799d71
AK		 7416 free_netdev(netdev);
7417
19d5afd4 7418 pci_disable_pcie_error_reporting(pdev);
6fabd715 7419
9a799d71
AK		 7420 pci_disable_device(pdev);
7421}
7422
7423/**
7424 * ixgbe_io_error_detected - called when PCI error is detected
7425 * @pdev: Pointer to PCI device
7426 * @state: The current pci connection state
7427 *
7428 * This function is called after a PCI bus error affecting
7429 * this device has been detected.
7430 */
7431static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7432 pci_channel_state_t state)
9a799d71 7433{
c60fbb00
AD		 7434 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7435 struct net_device *netdev = adapter->netdev;
9a799d71 7436
83c61fa9
GR		 7437#ifdef CONFIG_PCI_IOV
7438 struct pci_dev *bdev, *vfdev;
7439 u32 dw0, dw1, dw2, dw3;
7440 int vf, pos;
7441 u16 req_id, pf_func;
7442
7443 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7444 adapter->num_vfs == 0)
7445 goto skip_bad_vf_detection;
7446
7447 bdev = pdev->bus->self;
7448 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7449 bdev = bdev->bus->self;
7450
7451 if (!bdev)
7452 goto skip_bad_vf_detection;
7453
7454 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7455 if (!pos)
7456 goto skip_bad_vf_detection;
7457
7458 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7459 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7460 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7461 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7462
7463 req_id = dw1 >> 16;
7464 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7465 if (!(req_id & 0x0080))
7466 goto skip_bad_vf_detection;
7467
7468 pf_func = req_id & 0x01;
7469 if ((pf_func & 1) == (pdev->devfn & 1)) {
7470 unsigned int device_id;
7471
7472 vf = (req_id & 0x7F) >> 1;
7473 e_dev_err("VF %d has caused a PCIe error\n", vf);
7474 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7475 "%8.8x\tdw3: %8.8x\n",
7476 dw0, dw1, dw2, dw3);
7477 switch (adapter->hw.mac.type) {
7478 case ixgbe_mac_82599EB:
7479 device_id = IXGBE_82599_VF_DEVICE_ID;
7480 break;
7481 case ixgbe_mac_X540:
7482 device_id = IXGBE_X540_VF_DEVICE_ID;
7483 break;
7484 default:
7485 device_id = 0;
7486 break;
7487 }
7488
7489 /* Find the pci device of the offending VF */
7490 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7491 while (vfdev) {
7492 if (vfdev->devfn == (req_id & 0xFF))
7493 break;
7494 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7495 device_id, vfdev);
7496 }
7497 /*
7498 * There's a slim chance the VF could have been hot plugged,
7499 * so if it is no longer present we don't need to issue the
7500 * VFLR. Just clean up the AER in that case.
7501 */
7502 if (vfdev) {
7503 e_dev_err("Issuing VFLR to VF %d\n", vf);
7504 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7505 }
7506
7507 pci_cleanup_aer_uncorrect_error_status(pdev);
7508 }
7509
7510 /*
7511 * Even though the error may have occurred on the other port
7512 * we still need to increment the vf error reference count for
7513 * both ports because the I/O resume function will be called
7514 * for both of them.
7515 */
7516 adapter->vferr_refcount++;
7517
7518 return PCI_ERS_RESULT_RECOVERED;
7519
7520skip_bad_vf_detection:
7521#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7522 netif_device_detach(netdev);
7523
3044b8d1
BL		 7524 if (state == pci_channel_io_perm_failure)
7525 return PCI_ERS_RESULT_DISCONNECT;
7526
9a799d71
AK		 7527 if (netif_running(netdev))
7528 ixgbe_down(adapter);
7529 pci_disable_device(pdev);
7530
b4617240 7531 /* Request a slot reset. */
9a799d71
AK		 7532 return PCI_ERS_RESULT_NEED_RESET;
7533}
7534
7535/**
7536 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7537 * @pdev: Pointer to PCI device
7538 *
7539 * Restart the card from scratch, as if from a cold-boot.
7540 */
7541static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7542{
c60fbb00 7543 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7544 pci_ers_result_t result;
7545 int err;
9a799d71 7546
9ce77666 7547 if (pci_enable_device_mem(pdev)) {
396e799c 7548 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7549 result = PCI_ERS_RESULT_DISCONNECT;
7550 } else {
7551 pci_set_master(pdev);
7552 pci_restore_state(pdev);
c0e1f68b 7553 pci_save_state(pdev);
9a799d71 7554
dd4d8ca6 7555 pci_wake_from_d3(pdev, false);
9a799d71 7556
6fabd715 7557 ixgbe_reset(adapter);
88512539 7558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7559 result = PCI_ERS_RESULT_RECOVERED;
7560 }
7561
7562 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7563 if (err) {
849c4542
ET		 7564 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7565 "failed 0x%0x\n", err);
6fabd715
PWJ		 7566 /* non-fatal, continue */
7567 }
9a799d71 7568
6fabd715 7569 return result;
9a799d71
AK		 7570}
7571
7572/**
7573 * ixgbe_io_resume - called when traffic can start flowing again.
7574 * @pdev: Pointer to PCI device
7575 *
7576 * This callback is called when the error recovery driver tells us that
7577 * its OK to resume normal operation.
7578 */
7579static void ixgbe_io_resume(struct pci_dev *pdev)
7580{
c60fbb00
AD		 7581 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7582 struct net_device *netdev = adapter->netdev;
9a799d71 7583
83c61fa9
GR		 7584#ifdef CONFIG_PCI_IOV
7585 if (adapter->vferr_refcount) {
7586 e_info(drv, "Resuming after VF err\n");
7587 adapter->vferr_refcount--;
7588 return;
7589 }
7590
7591#endif
c7ccde0f
AD		 7592 if (netif_running(netdev))
7593 ixgbe_up(adapter);
9a799d71
AK		 7594
7595 netif_device_attach(netdev);
9a799d71
AK		 7596}
7597
7598static struct pci_error_handlers ixgbe_err_handler = {
7599 .error_detected = ixgbe_io_error_detected,
7600 .slot_reset = ixgbe_io_slot_reset,
7601 .resume = ixgbe_io_resume,
7602};
7603
7604static struct pci_driver ixgbe_driver = {
7605 .name = ixgbe_driver_name,
7606 .id_table = ixgbe_pci_tbl,
7607 .probe = ixgbe_probe,
7608 .remove = __devexit_p(ixgbe_remove),
7609#ifdef CONFIG_PM
7610 .suspend = ixgbe_suspend,
7611 .resume = ixgbe_resume,
7612#endif
7613 .shutdown = ixgbe_shutdown,
7614 .err_handler = &ixgbe_err_handler
7615};
7616
7617/**
7618 * ixgbe_init_module - Driver Registration Routine
7619 *
7620 * ixgbe_init_module is the first routine called when the driver is
7621 * loaded. All it does is register with the PCI subsystem.
7622 **/
7623static int __init ixgbe_init_module(void)
7624{
7625 int ret;
c7689578 7626 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7627 pr_info("%s\n", ixgbe_copyright);
9a799d71 7628
5dd2d332 7629#ifdef CONFIG_IXGBE_DCA
bd0362dd 7630 dca_register_notify(&dca_notifier);
bd0362dd 7631#endif
5dd2d332 7632
9a799d71
AK		 7633 ret = pci_register_driver(&ixgbe_driver);
7634 return ret;
7635}
b4617240 7636
9a799d71
AK		 7637module_init(ixgbe_init_module);
7638
7639/**
7640 * ixgbe_exit_module - Driver Exit Cleanup Routine
7641 *
7642 * ixgbe_exit_module is called just before the driver is removed
7643 * from memory.
7644 **/
7645static void __exit ixgbe_exit_module(void)
7646{
5dd2d332 7647#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7648 dca_unregister_notify(&dca_notifier);
7649#endif
9a799d71 7650 pci_unregister_driver(&ixgbe_driver);
1a51502b 7651 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7652}
bd0362dd 7653
5dd2d332 7654#ifdef CONFIG_IXGBE_DCA
bd0362dd 7655static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7656 void *p)
bd0362dd
JC		 7657{
7658 int ret_val;
7659
7660 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7661 __ixgbe_notify_dca);
bd0362dd
JC		 7662
7663 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7664}
b453368d 7665
5dd2d332 7666#endif /* CONFIG_IXGBE_DCA */
849c4542 7667
9a799d71
AK		 7668module_exit(ixgbe_exit_module);
7669
7670/* ixgbe_main.c */
Linux kernel - Deliverables
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