projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgb: use PCI_VENDOR_ID_INTEL
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
729739b7 399 dma_unmap_len(tx_buffer, len) != 0)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
729739b7
AD		 402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
dcd79aeb
TI		 406 }
407 }
408
409 /* Print RX Rings Summary */
410rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 412 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
c7689578
JP		 415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
c7689578
JP		 447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
c7689578 453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
c7689578 464 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
c7689578 470 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
f800326d 481 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 482 }
483 }
484
485 if (i == rx_ring->next_to_use)
c7689578 486 pr_cont(" NTU\n");
dcd79aeb 487 else if (i == rx_ring->next_to_clean)
c7689578 488 pr_cont(" NTC\n");
dcd79aeb 489 else
c7689578 490 pr_cont("\n");
dcd79aeb
TI		 491
492 }
493 }
494
495exit:
496 return;
497}
498
5eba3699
AV		 499static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500{
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 507}
508
509static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510{
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 517}
9a799d71 518
49ce9c2c 519/**
e8e26350
PW		 520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 528 u8 queue, u8 msix_vector)
9a799d71
AK		 529{
530 u32 ivar, index;
e8e26350
PW		 531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
b93a2226 544 case ixgbe_mac_X540:
e8e26350
PW		 545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
9a799d71
AK		 567}
568
fe49f04a 569static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 570 u64 qmask)
fe49f04a
AD		 571{
572 u32 mask;
573
bd508178
AD		 574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
fe49f04a
AD		 576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 578 break;
579 case ixgbe_mac_82599EB:
b93a2226 580 case ixgbe_mac_X540:
fe49f04a
AD		 581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 585 break;
586 default:
587 break;
fe49f04a
AD		 588 }
589}
590
729739b7
AD		 591void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 593{
729739b7
AD		 594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
d3d00239 597 dma_unmap_single(ring->dev,
729739b7
AD		 598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
e5a43549 606 }
729739b7
AD		 607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 611}
612
943561d3 613static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 614{
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 617 int i;
943561d3 618 u32 data;
c84d324c 619
943561d3
AD		 620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
c84d324c 623
943561d3
AD		 624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
c84d324c 632
943561d3
AD		 633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
c84d324c 635 return;
943561d3
AD		 636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640}
641
642static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643{
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 655 return;
943561d3 656 }
c84d324c
JF		 657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 663 break;
c84d324c
JF		 664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 666 }
c84d324c
JF		 667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 673 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 677 }
26f23d82
YZ		 678}
679
c84d324c 680static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 681{
7d7ce682 682 return ring->stats.packets;
c84d324c
JF		 683}
684
685static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686{
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
c84d324c
JF		 690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698}
699
700static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701{
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
7d637bcc 707 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 730 }
731
c84d324c 732 return ret;
9a799d71
AK		 733}
734
c83c6cbd
AD		 735/**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740{
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747}
e01c31a5 748
9a799d71
AK		 749/**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 751 * @q_vector: structure containing interrupt and ring information
e01c31a5 752 * @tx_ring: tx ring to clean
9a799d71 753 **/
fe49f04a 754static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 755 struct ixgbe_ring *tx_ring)
9a799d71 756{
fe49f04a 757 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 760 unsigned int total_bytes = 0, total_packets = 0;
59224555 761 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
9a799d71 766
d3d00239 767 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 769 i -= tx_ring->count;
12207e49 770
729739b7 771 do {
d3d00239
AD		 772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
7f83a9e6
AD		 778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
d3d00239
AD		 781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
8ad494b0 784
d3d00239
AD		 785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
8ad494b0 787
091a6246
AD		 788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
3a6a4eda 792#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 793 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
794 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 795#endif
0ede4a60 796
fd0db0ed
AD		 797 /* free the skb */
798 dev_kfree_skb_any(tx_buffer->skb);
799
729739b7
AD		 800 /* unmap skb header data */
801 dma_unmap_single(tx_ring->dev,
802 dma_unmap_addr(tx_buffer, dma),
803 dma_unmap_len(tx_buffer, len),
804 DMA_TO_DEVICE);
805
fd0db0ed
AD		 806 /* clear tx_buffer data */
807 tx_buffer->skb = NULL;
729739b7 808 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 809
729739b7
AD		 810 /* unmap remaining buffers */
811 while (tx_desc != eop_desc) {
d3d00239
AD		 812 tx_buffer++;
813 tx_desc++;
8ad494b0 814 i++;
729739b7
AD		 815 if (unlikely(!i)) {
816 i -= tx_ring->count;
d3d00239 817 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 819 }
e01c31a5 820
729739b7
AD		 821 /* unmap any remaining paged data */
822 if (dma_unmap_len(tx_buffer, len)) {
823 dma_unmap_page(tx_ring->dev,
824 dma_unmap_addr(tx_buffer, dma),
825 dma_unmap_len(tx_buffer, len),
826 DMA_TO_DEVICE);
827 dma_unmap_len_set(tx_buffer, len, 0);
828 }
829 }
830
831 /* move us one more past the eop_desc for start of next pkt */
832 tx_buffer++;
833 tx_desc++;
834 i++;
835 if (unlikely(!i)) {
836 i -= tx_ring->count;
837 tx_buffer = tx_ring->tx_buffer_info;
838 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
839 }
840
841 /* issue prefetch for next Tx descriptor */
842 prefetch(tx_desc);
12207e49 843
729739b7
AD		 844 /* update budget accounting */
845 budget--;
846 } while (likely(budget));
847
848 i += tx_ring->count;
9a799d71 849 tx_ring->next_to_clean = i;
d3d00239 850 u64_stats_update_begin(&tx_ring->syncp);
b953799e 851 tx_ring->stats.bytes += total_bytes;
bd198058 852 tx_ring->stats.packets += total_packets;
d3d00239 853 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 854 q_vector->tx.total_bytes += total_bytes;
855 q_vector->tx.total_packets += total_packets;
b953799e 856
c84d324c
JF		 857 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
858 /* schedule immediate reset if we believe we hung */
859 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 860 e_err(drv, "Detected Tx Unit Hang\n"
861 " Tx Queue <%d>\n"
862 " TDH, TDT <%x>, <%x>\n"
863 " next_to_use <%x>\n"
864 " next_to_clean <%x>\n"
865 "tx_buffer_info[next_to_clean]\n"
866 " time_stamp <%lx>\n"
867 " jiffies <%lx>\n",
868 tx_ring->queue_index,
869 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
870 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 871 tx_ring->next_to_use, i,
872 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 873
874 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
875
876 e_info(probe,
877 "tx hang %d detected on queue %d, resetting adapter\n",
878 adapter->tx_timeout_count + 1, tx_ring->queue_index);
879
b953799e 880 /* schedule immediate reset if we believe we hung */
c83c6cbd 881 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 882
883 /* the adapter is about to reset, no point in enabling stuff */
59224555 884 return true;
b953799e 885 }
9a799d71 886
b2d96e0a
AD		 887 netdev_tx_completed_queue(txring_txq(tx_ring),
888 total_packets, total_bytes);
889
e092be60 890#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 891 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 892 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 893 /* Make sure that anybody stopping the queue after this
894 * sees the new next_to_clean.
895 */
896 smp_mb();
729739b7
AD		 897 if (__netif_subqueue_stopped(tx_ring->netdev,
898 tx_ring->queue_index)
899 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
900 netif_wake_subqueue(tx_ring->netdev,
901 tx_ring->queue_index);
5b7da515 902 ++tx_ring->tx_stats.restart_queue;
30eba97a 903 }
e092be60 904 }
9a799d71 905
59224555 906 return !!budget;
9a799d71
AK		 907}
908
5dd2d332 909#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 910static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
911 struct ixgbe_ring *tx_ring,
33cf09c9 912 int cpu)
bd0362dd 913{
33cf09c9 914 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 915 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
916 u16 reg_offset;
33cf09c9 917
33cf09c9
AD		 918 switch (hw->mac.type) {
919 case ixgbe_mac_82598EB:
bdda1a61 920 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 921 break;
922 case ixgbe_mac_82599EB:
b93a2226 923 case ixgbe_mac_X540:
bdda1a61
AD		 924 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
925 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 926 break;
927 default:
bdda1a61
AD		 928 /* for unknown hardware do not write register */
929 return;
bd0362dd 930 }
bdda1a61
AD		 931
932 /*
933 * We can enable relaxed ordering for reads, but not writes when
934 * DCA is enabled. This is due to a known issue in some chipsets
935 * which will cause the DCA tag to be cleared.
936 */
937 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
938 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
939 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940
941 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 942}
943
bdda1a61
AD		 944static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *rx_ring,
33cf09c9 946 int cpu)
bd0362dd 947{
33cf09c9 948 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 949 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
950 u8 reg_idx = rx_ring->reg_idx;
951
33cf09c9
AD		 952
953 switch (hw->mac.type) {
33cf09c9 954 case ixgbe_mac_82599EB:
b93a2226 955 case ixgbe_mac_X540:
bdda1a61 956 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 957 break;
958 default:
959 break;
960 }
bdda1a61
AD		 961
962 /*
963 * We can enable relaxed ordering for reads, but not writes when
964 * DCA is enabled. This is due to a known issue in some chipsets
965 * which will cause the DCA tag to be cleared.
966 */
967 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
968 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
969 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
970
971 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 972}
973
974static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975{
976 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 977 struct ixgbe_ring *ring;
bd0362dd 978 int cpu = get_cpu();
bd0362dd 979
33cf09c9
AD		 980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
a557928e 983 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 984 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 985
a557928e 986 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 987 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 988
989 q_vector->cpu = cpu;
990out_no_update:
bd0362dd
JC		 991 put_cpu();
992}
993
994static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995{
996 int i;
997
998 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
999 return;
1000
e35ec126
AD		 1001 /* always use CB2 mode, difference is masked in the CB driver */
1002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1003
49c7ffbe 1004 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1005 adapter->q_vector[i]->cpu = -1;
1006 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1007 }
1008}
1009
1010static int __ixgbe_notify_dca(struct device *dev, void *data)
1011{
c60fbb00 1012 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1013 unsigned long event = *(unsigned long *)data;
1014
2a72c31e 1015 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1016 return 0;
1017
bd0362dd
JC		 1018 switch (event) {
1019 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1020 /* if we're already enabled, don't do it again */
1021 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1022 break;
652f093f 1023 if (dca_add_requester(dev) == 0) {
96b0e0f6 1024 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1025 ixgbe_setup_dca(adapter);
1026 break;
1027 }
1028 /* Fall Through since DCA is disabled. */
1029 case DCA_PROVIDER_REMOVE:
1030 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1031 dca_remove_requester(dev);
1032 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1034 }
1035 break;
1036 }
1037
652f093f 1038 return 0;
bd0362dd 1039}
67a74ee2 1040
bdda1a61 1041#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1042static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1043 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1044 struct sk_buff *skb)
1045{
8a0da21b
AD		 1046 if (ring->netdev->features & NETIF_F_RXHASH)
1047 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1048}
1049
f800326d 1050#ifdef IXGBE_FCOE
ff886dfc
AD		 1051/**
1052 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1053 * @ring: structure containing ring specific data
ff886dfc
AD		 1054 * @rx_desc: advanced rx descriptor
1055 *
1056 * Returns : true if it is FCoE pkt
1057 */
57efd44c 1058static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1059 union ixgbe_adv_rx_desc *rx_desc)
1060{
1061 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1062
57efd44c 1063 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1064 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1065 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1066 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1067}
1068
f800326d 1069#endif /* IXGBE_FCOE */
e59bd25d
AV		 1070/**
1071 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1072 * @ring: structure containing ring specific data
1073 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1074 * @skb: skb currently being received and modified
1075 **/
8a0da21b 1076static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1077 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1078 struct sk_buff *skb)
9a799d71 1079{
8a0da21b 1080 skb_checksum_none_assert(skb);
9a799d71 1081
712744be 1082 /* Rx csum disabled */
8a0da21b 1083 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1084 return;
e59bd25d
AV		 1085
1086 /* if IP and error */
f56e0cb1
AD		 1087 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1088 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1089 ring->rx_stats.csum_err++;
9a799d71
AK		 1090 return;
1091 }
e59bd25d 1092
f56e0cb1 1093 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1094 return;
1095
f56e0cb1 1096 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1097 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1098
1099 /*
1100 * 82599 errata, UDP frames with a 0 checksum can be marked as
1101 * checksum errors.
1102 */
8a0da21b
AD		 1103 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1104 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1105 return;
1106
8a0da21b 1107 ring->rx_stats.csum_err++;
e59bd25d
AV		 1108 return;
1109 }
1110
9a799d71 1111 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1113}
1114
84ea2591 1115static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1116{
f56e0cb1 1117 rx_ring->next_to_use = val;
f800326d
AD		 1118
1119 /* update next to alloc since we have filled the ring */
1120 rx_ring->next_to_alloc = val;
e8e26350
PW		 1121 /*
1122 * Force memory writes to complete before letting h/w
1123 * know there are new descriptors to fetch. (Only
1124 * applicable for weak-ordered memory model archs,
1125 * such as IA-64).
1126 */
1127 wmb();
84ea2591 1128 writel(val, rx_ring->tail);
e8e26350
PW		 1129}
1130
f990b79b
AD		 1131static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1132 struct ixgbe_rx_buffer *bi)
1133{
1134 struct page *page = bi->page;
f800326d 1135 dma_addr_t dma = bi->dma;
f990b79b 1136
f800326d
AD		 1137 /* since we are recycling buffers we should seldom need to alloc */
1138 if (likely(dma))
f990b79b
AD		 1139 return true;
1140
f800326d
AD		 1141 /* alloc new page for storage */
1142 if (likely(!page)) {
8633c084 1143 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
f800326d 1144 ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1145 if (unlikely(!page)) {
1146 rx_ring->rx_stats.alloc_rx_page_failed++;
1147 return false;
1148 }
f800326d 1149 bi->page = page;
f990b79b
AD		 1150 }
1151
f800326d
AD		 1152 /* map page for use */
1153 dma = dma_map_page(rx_ring->dev, page, 0,
1154 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1155
1156 /*
1157 * if mapping failed free memory back to system since
1158 * there isn't much point in holding memory we can't use
1159 */
1160 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1161 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1162 bi->page = NULL;
f990b79b 1163
f990b79b
AD		 1164 rx_ring->rx_stats.alloc_rx_page_failed++;
1165 return false;
1166 }
1167
f800326d
AD		 1168 bi->dma = dma;
1169 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1170
f990b79b
AD		 1171 return true;
1172}
1173
9a799d71 1174/**
f990b79b 1175 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1176 * @rx_ring: ring to place buffers on
1177 * @cleaned_count: number of buffers to replace
9a799d71 1178 **/
fc77dc3c 1179void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1180{
9a799d71 1181 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1182 struct ixgbe_rx_buffer *bi;
d5f398ed 1183 u16 i = rx_ring->next_to_use;
9a799d71 1184
f800326d
AD		 1185 /* nothing to do */
1186 if (!cleaned_count)
fc77dc3c
AD		 1187 return;
1188
e4f74028 1189 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1190 bi = &rx_ring->rx_buffer_info[i];
1191 i -= rx_ring->count;
9a799d71 1192
f800326d
AD		 1193 do {
1194 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1195 break;
d5f398ed 1196
f800326d
AD		 1197 /*
1198 * Refresh the desc even if buffer_addrs didn't change
1199 * because each write-back erases this info.
1200 */
1201 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1202
f990b79b
AD		 1203 rx_desc++;
1204 bi++;
9a799d71 1205 i++;
f990b79b 1206 if (unlikely(!i)) {
e4f74028 1207 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1208 bi = rx_ring->rx_buffer_info;
1209 i -= rx_ring->count;
1210 }
1211
1212 /* clear the hdr_addr for the next_to_use descriptor */
1213 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1214
1215 cleaned_count--;
1216 } while (cleaned_count);
7c6e0a43 1217
f990b79b
AD		 1218 i += rx_ring->count;
1219
f56e0cb1 1220 if (rx_ring->next_to_use != i)
84ea2591 1221 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1222}
1223
1d2024f6
AD		 1224/**
1225 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1226 * @data: pointer to the start of the headers
1227 * @max_len: total length of section to find headers in
1228 *
1229 * This function is meant to determine the length of headers that will
1230 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1231 * motivation of doing this is to only perform one pull for IPv4 TCP
1232 * packets so that we can do basic things like calculating the gso_size
1233 * based on the average data per packet.
1234 **/
1235static unsigned int ixgbe_get_headlen(unsigned char *data,
1236 unsigned int max_len)
1237{
1238 union {
1239 unsigned char *network;
1240 /* l2 headers */
1241 struct ethhdr *eth;
1242 struct vlan_hdr *vlan;
1243 /* l3 headers */
1244 struct iphdr *ipv4;
1245 } hdr;
1246 __be16 protocol;
1247 u8 nexthdr = 0; /* default to not TCP */
1248 u8 hlen;
1249
1250 /* this should never happen, but better safe than sorry */
1251 if (max_len < ETH_HLEN)
1252 return max_len;
1253
1254 /* initialize network frame pointer */
1255 hdr.network = data;
1256
1257 /* set first protocol and move network header forward */
1258 protocol = hdr.eth->h_proto;
1259 hdr.network += ETH_HLEN;
1260
1261 /* handle any vlan tag if present */
1262 if (protocol == __constant_htons(ETH_P_8021Q)) {
1263 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1264 return max_len;
1265
1266 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1267 hdr.network += VLAN_HLEN;
1268 }
1269
1270 /* handle L3 protocols */
1271 if (protocol == __constant_htons(ETH_P_IP)) {
1272 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1273 return max_len;
1274
1275 /* access ihl as a u8 to avoid unaligned access on ia64 */
1276 hlen = (hdr.network[0] & 0x0F) << 2;
1277
1278 /* verify hlen meets minimum size requirements */
1279 if (hlen < sizeof(struct iphdr))
1280 return hdr.network - data;
1281
1282 /* record next protocol */
1283 nexthdr = hdr.ipv4->protocol;
1284 hdr.network += hlen;
f800326d 1285#ifdef IXGBE_FCOE
1d2024f6
AD		 1286 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1287 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1288 return max_len;
1289 hdr.network += FCOE_HEADER_LEN;
1290#endif
1291 } else {
1292 return hdr.network - data;
1293 }
1294
1295 /* finally sort out TCP */
1296 if (nexthdr == IPPROTO_TCP) {
1297 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1298 return max_len;
1299
1300 /* access doff as a u8 to avoid unaligned access on ia64 */
1301 hlen = (hdr.network[12] & 0xF0) >> 2;
1302
1303 /* verify hlen meets minimum size requirements */
1304 if (hlen < sizeof(struct tcphdr))
1305 return hdr.network - data;
1306
1307 hdr.network += hlen;
1308 }
1309
1310 /*
1311 * If everything has gone correctly hdr.network should be the
1312 * data section of the packet and will be the end of the header.
1313 * If not then it probably represents the end of the last recognized
1314 * header.
1315 */
1316 if ((hdr.network - data) < max_len)
1317 return hdr.network - data;
1318 else
1319 return max_len;
1320}
1321
4c1975d7
AD		 1322static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1323 union ixgbe_adv_rx_desc *rx_desc,
1324 struct sk_buff *skb)
aa80175a 1325{
4c1975d7
AD		 1326 __le32 rsc_enabled;
1327 u32 rsc_cnt;
1328
1329 if (!ring_is_rsc_enabled(rx_ring))
1330 return;
1331
1332 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1333 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1334
1335 /* If this is an RSC frame rsc_cnt should be non-zero */
1336 if (!rsc_enabled)
1337 return;
1338
1339 rsc_cnt = le32_to_cpu(rsc_enabled);
1340 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1341
1342 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1343}
43634e82 1344
1d2024f6
AD		 1345static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1346 struct sk_buff *skb)
1347{
f800326d 1348 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1349
1350 /* set gso_size to avoid messing up TCP MSS */
1351 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1352 IXGBE_CB(skb)->append_cnt);
1353}
1354
1355static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1356 struct sk_buff *skb)
1357{
1358 /* if append_cnt is 0 then frame is not RSC */
1359 if (!IXGBE_CB(skb)->append_cnt)
1360 return;
1361
1362 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1363 rx_ring->rx_stats.rsc_flush++;
1364
1365 ixgbe_set_rsc_gso_size(rx_ring, skb);
1366
1367 /* gso_size is computed using append_cnt so always clear it last */
1368 IXGBE_CB(skb)->append_cnt = 0;
1369}
1370
8a0da21b
AD		 1371/**
1372 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1373 * @rx_ring: rx descriptor ring packet is being transacted on
1374 * @rx_desc: pointer to the EOP Rx descriptor
1375 * @skb: pointer to current skb being populated
f8212f97 1376 *
8a0da21b
AD		 1377 * This function checks the ring, descriptor, and packet information in
1378 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1379 * other fields within the skb.
f8212f97 1380 **/
8a0da21b
AD		 1381static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1382 union ixgbe_adv_rx_desc *rx_desc,
1383 struct sk_buff *skb)
f8212f97 1384{
43e95f11
JF		 1385 struct net_device *dev = rx_ring->netdev;
1386
8a0da21b
AD		 1387 ixgbe_update_rsc_stats(rx_ring, skb);
1388
1389 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1390
8a0da21b
AD		 1391 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1392
3a6a4eda 1393#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1394 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1395#endif
1396
43e95f11
JF		 1397 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1398 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1399 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1400 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1401 }
1402
8a0da21b 1403 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1404
43e95f11 1405 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1406}
1407
8a0da21b
AD		 1408static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1409 struct sk_buff *skb)
aa80175a 1410{
8a0da21b
AD		 1411 struct ixgbe_adapter *adapter = q_vector->adapter;
1412
1413 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1414 napi_gro_receive(&q_vector->napi, skb);
1415 else
1416 netif_rx(skb);
aa80175a 1417}
43634e82 1418
f800326d
AD		 1419/**
1420 * ixgbe_is_non_eop - process handling of non-EOP buffers
1421 * @rx_ring: Rx ring being processed
1422 * @rx_desc: Rx descriptor for current buffer
1423 * @skb: Current socket buffer containing buffer in progress
1424 *
1425 * This function updates next to clean. If the buffer is an EOP buffer
1426 * this function exits returning false, otherwise it will place the
1427 * sk_buff in the next buffer to be chained and return true indicating
1428 * that this is in fact a non-EOP buffer.
1429 **/
1430static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1431 union ixgbe_adv_rx_desc *rx_desc,
1432 struct sk_buff *skb)
1433{
1434 u32 ntc = rx_ring->next_to_clean + 1;
1435
1436 /* fetch, update, and store next to clean */
1437 ntc = (ntc < rx_ring->count) ? ntc : 0;
1438 rx_ring->next_to_clean = ntc;
1439
1440 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1441
1442 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1443 return false;
1444
1445 /* append_cnt indicates packet is RSC, if so fetch nextp */
1446 if (IXGBE_CB(skb)->append_cnt) {
1447 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1448 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1449 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1450 }
1451
1452 /* place skb in next buffer to be received */
1453 rx_ring->rx_buffer_info[ntc].skb = skb;
1454 rx_ring->rx_stats.non_eop_descs++;
1455
1456 return true;
1457}
1458
1459/**
1460 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1461 * @rx_ring: rx descriptor ring packet is being transacted on
1462 * @rx_desc: pointer to the EOP Rx descriptor
1463 * @skb: pointer to current skb being fixed
1464 *
1465 * Check for corrupted packet headers caused by senders on the local L2
1466 * embedded NIC switch not setting up their Tx Descriptors right. These
1467 * should be very rare.
1468 *
1469 * Also address the case where we are pulling data in on pages only
1470 * and as such no data is present in the skb header.
1471 *
1472 * In addition if skb is not at least 60 bytes we need to pad it so that
1473 * it is large enough to qualify as a valid Ethernet frame.
1474 *
1475 * Returns true if an error was encountered and skb was freed.
1476 **/
1477static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480{
1481 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1482 struct net_device *netdev = rx_ring->netdev;
1483 unsigned char *va;
1484 unsigned int pull_len;
1485
1486 /* if the page was released unmap it, else just sync our portion */
1487 if (unlikely(IXGBE_CB(skb)->page_released)) {
1488 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1489 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1490 IXGBE_CB(skb)->page_released = false;
1491 } else {
1492 dma_sync_single_range_for_cpu(rx_ring->dev,
1493 IXGBE_CB(skb)->dma,
1494 frag->page_offset,
1495 ixgbe_rx_bufsz(rx_ring),
1496 DMA_FROM_DEVICE);
1497 }
1498 IXGBE_CB(skb)->dma = 0;
1499
1500 /* verify that the packet does not have any known errors */
1501 if (unlikely(ixgbe_test_staterr(rx_desc,
1502 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1503 !(netdev->features & NETIF_F_RXALL))) {
1504 dev_kfree_skb_any(skb);
1505 return true;
1506 }
1507
1508 /*
1509 * it is valid to use page_address instead of kmap since we are
1510 * working with pages allocated out of the lomem pool per
1511 * alloc_page(GFP_ATOMIC)
1512 */
1513 va = skb_frag_address(frag);
1514
1515 /*
1516 * we need the header to contain the greater of either ETH_HLEN or
1517 * 60 bytes if the skb->len is less than 60 for skb_pad.
1518 */
1519 pull_len = skb_frag_size(frag);
1520 if (pull_len > 256)
1521 pull_len = ixgbe_get_headlen(va, pull_len);
1522
1523 /* align pull length to size of long to optimize memcpy performance */
1524 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1525
1526 /* update all of the pointers */
1527 skb_frag_size_sub(frag, pull_len);
1528 frag->page_offset += pull_len;
1529 skb->data_len -= pull_len;
1530 skb->tail += pull_len;
1531
1532 /*
1533 * if we sucked the frag empty then we should free it,
1534 * if there are other frags here something is screwed up in hardware
1535 */
1536 if (skb_frag_size(frag) == 0) {
1537 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1538 skb_shinfo(skb)->nr_frags = 0;
1539 __skb_frag_unref(frag);
1540 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1541 }
1542
57efd44c
AD		 1543#ifdef IXGBE_FCOE
1544 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1545 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1546 return false;
1547
1548#endif
f800326d
AD		 1549 /* if skb_pad returns an error the skb was freed */
1550 if (unlikely(skb->len < 60)) {
1551 int pad_len = 60 - skb->len;
1552
1553 if (skb_pad(skb, pad_len))
1554 return true;
1555 __skb_put(skb, pad_len);
1556 }
1557
1558 return false;
1559}
1560
1561/**
1562 * ixgbe_can_reuse_page - determine if we can reuse a page
1563 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1564 *
1565 * Returns true if page can be reused in another Rx buffer
1566 **/
1567static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1568{
1569 struct page *page = rx_buffer->page;
1570
1571 /* if we are only owner of page and it is local we can reuse it */
1572 return likely(page_count(page) == 1) &&
1573 likely(page_to_nid(page) == numa_node_id());
1574}
1575
1576/**
1577 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1578 * @rx_ring: rx descriptor ring to store buffers on
1579 * @old_buff: donor buffer to have page reused
1580 *
1581 * Syncronizes page for reuse by the adapter
1582 **/
1583static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1584 struct ixgbe_rx_buffer *old_buff)
1585{
1586 struct ixgbe_rx_buffer *new_buff;
1587 u16 nta = rx_ring->next_to_alloc;
1588 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1589
1590 new_buff = &rx_ring->rx_buffer_info[nta];
1591
1592 /* update, and store next to alloc */
1593 nta++;
1594 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1595
1596 /* transfer page from old buffer to new buffer */
1597 new_buff->page = old_buff->page;
1598 new_buff->dma = old_buff->dma;
1599
1600 /* flip page offset to other buffer and store to new_buff */
1601 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1602
1603 /* sync the buffer for use by the device */
1604 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1605 new_buff->page_offset, bufsz,
1606 DMA_FROM_DEVICE);
1607
1608 /* bump ref count on page before it is given to the stack */
1609 get_page(new_buff->page);
1610}
1611
1612/**
1613 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1614 * @rx_ring: rx descriptor ring to transact packets on
1615 * @rx_buffer: buffer containing page to add
1616 * @rx_desc: descriptor containing length of buffer written by hardware
1617 * @skb: sk_buff to place the data into
1618 *
1619 * This function is based on skb_add_rx_frag. I would have used that
1620 * function however it doesn't handle the truesize case correctly since we
1621 * are allocating more memory than might be used for a single receive.
1622 **/
1623static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1624 struct ixgbe_rx_buffer *rx_buffer,
1625 struct sk_buff *skb, int size)
1626{
1627 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1628 rx_buffer->page, rx_buffer->page_offset,
1629 size);
1630 skb->len += size;
1631 skb->data_len += size;
1632 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1633}
1634
1635/**
1636 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1637 * @q_vector: structure containing interrupt and ring information
1638 * @rx_ring: rx descriptor ring to transact packets on
1639 * @budget: Total limit on number of packets to process
1640 *
1641 * This function provides a "bounce buffer" approach to Rx interrupt
1642 * processing. The advantage to this is that on systems that have
1643 * expensive overhead for IOMMU access this provides a means of avoiding
1644 * it by maintaining the mapping of the page to the syste.
1645 *
1646 * Returns true if all work is completed without reaching budget
1647 **/
4ff7fb12 1648static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1649 struct ixgbe_ring *rx_ring,
4ff7fb12 1650 int budget)
9a799d71 1651{
d2f4fbe2 1652 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1653#ifdef IXGBE_FCOE
f800326d 1654 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1655 int ddp_bytes = 0;
1656#endif /* IXGBE_FCOE */
f800326d 1657 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1658
f800326d
AD		 1659 do {
1660 struct ixgbe_rx_buffer *rx_buffer;
1661 union ixgbe_adv_rx_desc *rx_desc;
1662 struct sk_buff *skb;
1663 struct page *page;
1664 u16 ntc;
1665
1666 /* return some buffers to hardware, one at a time is too slow */
1667 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1668 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1669 cleaned_count = 0;
1670 }
1671
1672 ntc = rx_ring->next_to_clean;
1673 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1674 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1675
1676 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1677 break;
9a799d71 1678
f800326d
AD		 1679 /*
1680 * This memory barrier is needed to keep us from reading
1681 * any other fields out of the rx_desc until we know the
1682 * RXD_STAT_DD bit is set
1683 */
1684 rmb();
9a799d71 1685
f800326d
AD		 1686 page = rx_buffer->page;
1687 prefetchw(page);
9a799d71 1688
f800326d 1689 skb = rx_buffer->skb;
c267fc16 1690
f800326d
AD		 1691 if (likely(!skb)) {
1692 void *page_addr = page_address(page) +
1693 rx_buffer->page_offset;
9a799d71 1694
f800326d
AD		 1695 /* prefetch first cache line of first page */
1696 prefetch(page_addr);
1697#if L1_CACHE_BYTES < 128
1698 prefetch(page_addr + L1_CACHE_BYTES);
1699#endif
1700
1701 /* allocate a skb to store the frags */
1702 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1703 IXGBE_RX_HDR_SIZE);
1704 if (unlikely(!skb)) {
1705 rx_ring->rx_stats.alloc_rx_buff_failed++;
1706 break;
c267fc16
AD		 1707 }
1708
f800326d
AD		 1709 /*
1710 * we will be copying header into skb->data in
1711 * pskb_may_pull so it is in our interest to prefetch
1712 * it now to avoid a possible cache miss
1713 */
1714 prefetchw(skb->data);
4c1975d7
AD		 1715
1716 /*
1717 * Delay unmapping of the first packet. It carries the
1718 * header information, HW may still access the header
f800326d
AD		 1719 * after the writeback. Only unmap it when EOP is
1720 * reached
4c1975d7 1721 */
f800326d 1722 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1723 } else {
f800326d
AD		 1724 /* we are reusing so sync this buffer for CPU use */
1725 dma_sync_single_range_for_cpu(rx_ring->dev,
1726 rx_buffer->dma,
1727 rx_buffer->page_offset,
1728 ixgbe_rx_bufsz(rx_ring),
1729 DMA_FROM_DEVICE);
9a799d71
AK		 1730 }
1731
f800326d
AD		 1732 /* pull page into skb */
1733 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1734 le16_to_cpu(rx_desc->wb.upper.length));
9a799d71 1735
f800326d
AD		 1736 if (ixgbe_can_reuse_page(rx_buffer)) {
1737 /* hand second half of page back to the ring */
1738 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1739 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1740 /* the page has been released from the ring */
1741 IXGBE_CB(skb)->page_released = true;
1742 } else {
1743 /* we are not reusing the buffer so unmap it */
1744 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1745 ixgbe_rx_pg_size(rx_ring),
1746 DMA_FROM_DEVICE);
9a799d71
AK		 1747 }
1748
f800326d
AD		 1749 /* clear contents of buffer_info */
1750 rx_buffer->skb = NULL;
1751 rx_buffer->dma = 0;
1752 rx_buffer->page = NULL;
4c1975d7 1753
f800326d 1754 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1755
9a799d71 1756 cleaned_count++;
f8212f97 1757
f800326d
AD		 1758 /* place incomplete frames back on ring for completion */
1759 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1760 continue;
c267fc16 1761
f800326d
AD		 1762 /* verify the packet layout is correct */
1763 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1764 continue;
9a799d71 1765
d2f4fbe2
AV		 1766 /* probably a little skewed due to removing CRC */
1767 total_rx_bytes += skb->len;
1768 total_rx_packets++;
1769
8a0da21b
AD		 1770 /* populate checksum, timestamp, VLAN, and protocol */
1771 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1772
332d4a7d
YZ		 1773#ifdef IXGBE_FCOE
1774 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1775 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1776 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1777 if (!ddp_bytes) {
1778 dev_kfree_skb_any(skb);
f800326d 1779 continue;
63d635b2 1780 }
3d8fd385 1781 }
f800326d 1782
332d4a7d 1783#endif /* IXGBE_FCOE */
8a0da21b 1784 ixgbe_rx_skb(q_vector, skb);
9a799d71 1785
f800326d 1786 /* update budget accounting */
4ff7fb12 1787 budget--;
f800326d 1788 } while (likely(budget));
9a799d71 1789
3d8fd385
YZ		 1790#ifdef IXGBE_FCOE
1791 /* include DDPed FCoE data */
1792 if (ddp_bytes > 0) {
1793 unsigned int mss;
1794
fc77dc3c 1795 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1796 sizeof(struct fc_frame_header) -
1797 sizeof(struct fcoe_crc_eof);
1798 if (mss > 512)
1799 mss &= ~511;
1800 total_rx_bytes += ddp_bytes;
1801 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1802 }
3d8fd385 1803
f800326d 1804#endif /* IXGBE_FCOE */
c267fc16
AD		 1805 u64_stats_update_begin(&rx_ring->syncp);
1806 rx_ring->stats.packets += total_rx_packets;
1807 rx_ring->stats.bytes += total_rx_bytes;
1808 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1809 q_vector->rx.total_packets += total_rx_packets;
1810 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1811
f800326d
AD		 1812 if (cleaned_count)
1813 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1814
4ff7fb12 1815 return !!budget;
9a799d71
AK		 1816}
1817
9a799d71
AK		 1818/**
1819 * ixgbe_configure_msix - Configure MSI-X hardware
1820 * @adapter: board private structure
1821 *
1822 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1823 * interrupts.
1824 **/
1825static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1826{
021230d4 1827 struct ixgbe_q_vector *q_vector;
49c7ffbe 1828 int v_idx;
021230d4 1829 u32 mask;
9a799d71 1830
8e34d1aa
AD		 1831 /* Populate MSIX to EITR Select */
1832 if (adapter->num_vfs > 32) {
1833 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1835 }
1836
4df10466
JB		 1837 /*
1838 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1839 * corresponding register.
1840 */
49c7ffbe 1841 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1842 struct ixgbe_ring *ring;
7a921c93 1843 q_vector = adapter->q_vector[v_idx];
021230d4 1844
a557928e 1845 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1846 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1847
a557928e 1848 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1849 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1850
d5bf4f67
ET		 1851 if (q_vector->tx.ring && !q_vector->rx.ring) {
1852 /* tx only vector */
1853 if (adapter->tx_itr_setting == 1)
1854 q_vector->itr = IXGBE_10K_ITR;
1855 else
1856 q_vector->itr = adapter->tx_itr_setting;
1857 } else {
1858 /* rx or rx/tx vector */
1859 if (adapter->rx_itr_setting == 1)
1860 q_vector->itr = IXGBE_20K_ITR;
1861 else
1862 q_vector->itr = adapter->rx_itr_setting;
1863 }
021230d4 1864
fe49f04a 1865 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1866 }
1867
bd508178
AD		 1868 switch (adapter->hw.mac.type) {
1869 case ixgbe_mac_82598EB:
e8e26350 1870 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1871 v_idx);
bd508178
AD		 1872 break;
1873 case ixgbe_mac_82599EB:
b93a2226 1874 case ixgbe_mac_X540:
e8e26350 1875 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1876 break;
bd508178
AD		 1877 default:
1878 break;
1879 }
021230d4
AV		 1880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1881
41fb9248 1882 /* set up to autoclear timer, and the vectors */
021230d4 1883 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1884 mask &= ~(IXGBE_EIMS_OTHER |
1885 IXGBE_EIMS_MAILBOX |
1886 IXGBE_EIMS_LSC);
1887
021230d4 1888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1889}
1890
f494e8fa
AV		 1891enum latency_range {
1892 lowest_latency = 0,
1893 low_latency = 1,
1894 bulk_latency = 2,
1895 latency_invalid = 255
1896};
1897
1898/**
1899 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1900 * @q_vector: structure containing interrupt and ring information
1901 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1902 *
1903 * Stores a new ITR value based on packets and byte
1904 * counts during the last interrupt. The advantage of per interrupt
1905 * computation is faster updates and more accurate ITR for the current
1906 * traffic pattern. Constants in this function were computed
1907 * based on theoretical maximum wire speed and thresholds were set based
1908 * on testing data as well as attempting to minimize response time
1909 * while increasing bulk throughput.
1910 * this functionality is controlled by the InterruptThrottleRate module
1911 * parameter (see ixgbe_param.c)
1912 **/
bd198058
AD		 1913static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1914 struct ixgbe_ring_container *ring_container)
f494e8fa 1915{
bd198058
AD		 1916 int bytes = ring_container->total_bytes;
1917 int packets = ring_container->total_packets;
1918 u32 timepassed_us;
621bd70e 1919 u64 bytes_perint;
bd198058 1920 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1921
1922 if (packets == 0)
bd198058 1923 return;
f494e8fa
AV		 1924
1925 /* simple throttlerate management
621bd70e
AD		 1926 * 0-10MB/s lowest (100000 ints/s)
1927 * 10-20MB/s low (20000 ints/s)
1928 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1929 */
1930 /* what was last interrupt timeslice? */
d5bf4f67 1931 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1932 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1933
1934 switch (itr_setting) {
1935 case lowest_latency:
621bd70e 1936 if (bytes_perint > 10)
bd198058 1937 itr_setting = low_latency;
f494e8fa
AV		 1938 break;
1939 case low_latency:
621bd70e 1940 if (bytes_perint > 20)
bd198058 1941 itr_setting = bulk_latency;
621bd70e 1942 else if (bytes_perint <= 10)
bd198058 1943 itr_setting = lowest_latency;
f494e8fa
AV		 1944 break;
1945 case bulk_latency:
621bd70e 1946 if (bytes_perint <= 20)
bd198058 1947 itr_setting = low_latency;
f494e8fa
AV		 1948 break;
1949 }
1950
bd198058
AD		 1951 /* clear work counters since we have the values we need */
1952 ring_container->total_bytes = 0;
1953 ring_container->total_packets = 0;
1954
1955 /* write updated itr to ring container */
1956 ring_container->itr = itr_setting;
f494e8fa
AV		 1957}
1958
509ee935
JB		 1959/**
1960 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1961 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1962 *
1963 * This function is made to be called by ethtool and by the driver
1964 * when it needs to update EITR registers at runtime. Hardware
1965 * specific quirks/differences are taken care of here.
1966 */
fe49f04a 1967void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1968{
fe49f04a 1969 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1970 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1971 int v_idx = q_vector->v_idx;
5d967eb7 1972 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1973
bd508178
AD		 1974 switch (adapter->hw.mac.type) {
1975 case ixgbe_mac_82598EB:
509ee935
JB		 1976 /* must write high and low 16 bits to reset counter */
1977 itr_reg |= (itr_reg << 16);
bd508178
AD		 1978 break;
1979 case ixgbe_mac_82599EB:
b93a2226 1980 case ixgbe_mac_X540:
509ee935
JB		 1981 /*
1982 * set the WDIS bit to not clear the timer bits and cause an
1983 * immediate assertion of the interrupt
1984 */
1985 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1986 break;
1987 default:
1988 break;
509ee935
JB		 1989 }
1990 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1991}
1992
bd198058 1993static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1994{
d5bf4f67 1995 u32 new_itr = q_vector->itr;
bd198058 1996 u8 current_itr;
f494e8fa 1997
bd198058
AD		 1998 ixgbe_update_itr(q_vector, &q_vector->tx);
1999 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2000
08c8833b 2001 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2002
2003 switch (current_itr) {
2004 /* counts and packets in update_itr are dependent on these numbers */
2005 case lowest_latency:
d5bf4f67 2006 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2007 break;
2008 case low_latency:
d5bf4f67 2009 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2010 break;
2011 case bulk_latency:
d5bf4f67 2012 new_itr = IXGBE_8K_ITR;
f494e8fa 2013 break;
bd198058
AD		 2014 default:
2015 break;
f494e8fa
AV		 2016 }
2017
d5bf4f67 2018 if (new_itr != q_vector->itr) {
fe49f04a 2019 /* do an exponential smoothing */
d5bf4f67
ET		 2020 new_itr = (10 * new_itr * q_vector->itr) /
2021 ((9 * new_itr) + q_vector->itr);
509ee935 2022
bd198058 2023 /* save the algorithm value here */
5d967eb7 2024 q_vector->itr = new_itr;
fe49f04a
AD		 2025
2026 ixgbe_write_eitr(q_vector);
f494e8fa 2027 }
f494e8fa
AV		 2028}
2029
119fc60a 2030/**
de88eeeb 2031 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2032 * @adapter: pointer to adapter
119fc60a 2033 **/
f0f9778d 2034static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2035{
119fc60a
MC		 2036 struct ixgbe_hw *hw = &adapter->hw;
2037 u32 eicr = adapter->interrupt_event;
2038
f0f9778d 2039 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2040 return;
2041
f0f9778d
AD		 2042 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2043 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2044 return;
2045
2046 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2047
7ca647bd 2048 switch (hw->device_id) {
f0f9778d
AD		 2049 case IXGBE_DEV_ID_82599_T3_LOM:
2050 /*
2051 * Since the warning interrupt is for both ports
2052 * we don't have to check if:
2053 * - This interrupt wasn't for our port.
2054 * - We may have missed the interrupt so always have to
2055 * check if we got a LSC
2056 */
2057 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2058 !(eicr & IXGBE_EICR_LSC))
2059 return;
2060
2061 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2062 u32 autoneg;
2063 bool link_up = false;
7ca647bd 2064
7ca647bd
JP		 2065 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2066
f0f9778d
AD		 2067 if (link_up)
2068 return;
2069 }
2070
2071 /* Check if this is not due to overtemp */
2072 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2073 return;
2074
2075 break;
7ca647bd
JP		 2076 default:
2077 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2078 return;
7ca647bd 2079 break;
119fc60a 2080 }
7ca647bd
JP		 2081 e_crit(drv,
2082 "Network adapter has been stopped because it has over heated. "
2083 "Restart the computer. If the problem persists, "
2084 "power off the system and replace the adapter\n");
f0f9778d
AD		 2085
2086 adapter->interrupt_event = 0;
119fc60a
MC		 2087}
2088
0befdb3e
JB		 2089static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2090{
2091 struct ixgbe_hw *hw = &adapter->hw;
2092
2093 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2094 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2095 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2096 /* write to clear the interrupt */
2097 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2098 }
2099}
cf8280ee 2100
4f51bf70
JK		 2101static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2102{
2103 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2104 return;
2105
2106 switch (adapter->hw.mac.type) {
2107 case ixgbe_mac_82599EB:
2108 /*
2109 * Need to check link state so complete overtemp check
2110 * on service task
2111 */
2112 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2113 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2114 adapter->interrupt_event = eicr;
2115 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2116 ixgbe_service_event_schedule(adapter);
2117 return;
2118 }
2119 return;
2120 case ixgbe_mac_X540:
2121 if (!(eicr & IXGBE_EICR_TS))
2122 return;
2123 break;
2124 default:
2125 return;
2126 }
2127
2128 e_crit(drv,
2129 "Network adapter has been stopped because it has over heated. "
2130 "Restart the computer. If the problem persists, "
2131 "power off the system and replace the adapter\n");
2132}
2133
e8e26350
PW		 2134static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2135{
2136 struct ixgbe_hw *hw = &adapter->hw;
2137
73c4b7cd
AD		 2138 if (eicr & IXGBE_EICR_GPI_SDP2) {
2139 /* Clear the interrupt */
2140 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2141 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2142 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2143 ixgbe_service_event_schedule(adapter);
2144 }
73c4b7cd
AD		 2145 }
2146
e8e26350
PW		 2147 if (eicr & IXGBE_EICR_GPI_SDP1) {
2148 /* Clear the interrupt */
2149 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2150 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2151 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2152 ixgbe_service_event_schedule(adapter);
2153 }
e8e26350
PW		 2154 }
2155}
2156
cf8280ee
JB		 2157static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2158{
2159 struct ixgbe_hw *hw = &adapter->hw;
2160
2161 adapter->lsc_int++;
2162 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2163 adapter->link_check_timeout = jiffies;
2164 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2165 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2166 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2167 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2168 }
2169}
2170
fe49f04a
AD		 2171static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2172 u64 qmask)
2173{
2174 u32 mask;
bd508178 2175 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2176
bd508178
AD		 2177 switch (hw->mac.type) {
2178 case ixgbe_mac_82598EB:
fe49f04a 2179 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2180 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2181 break;
2182 case ixgbe_mac_82599EB:
b93a2226 2183 case ixgbe_mac_X540:
fe49f04a 2184 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2185 if (mask)
2186 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2187 mask = (qmask >> 32);
bd508178
AD		 2188 if (mask)
2189 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2190 break;
2191 default:
2192 break;
fe49f04a
AD		 2193 }
2194 /* skip the flush */
2195}
2196
2197static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2198 u64 qmask)
fe49f04a
AD		 2199{
2200 u32 mask;
bd508178 2201 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2202
bd508178
AD		 2203 switch (hw->mac.type) {
2204 case ixgbe_mac_82598EB:
fe49f04a 2205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2206 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2207 break;
2208 case ixgbe_mac_82599EB:
b93a2226 2209 case ixgbe_mac_X540:
fe49f04a 2210 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2211 if (mask)
2212 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2213 mask = (qmask >> 32);
bd508178
AD		 2214 if (mask)
2215 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2216 break;
2217 default:
2218 break;
fe49f04a
AD		 2219 }
2220 /* skip the flush */
2221}
2222
021230d4 2223/**
2c4af694
AD		 2224 * ixgbe_irq_enable - Enable default interrupt generation settings
2225 * @adapter: board private structure
021230d4 2226 **/
2c4af694
AD		 2227static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2228 bool flush)
9a799d71 2229{
2c4af694 2230 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2231
2c4af694
AD		 2232 /* don't reenable LSC while waiting for link */
2233 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2234 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2235
2c4af694 2236 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2237 switch (adapter->hw.mac.type) {
2238 case ixgbe_mac_82599EB:
2239 mask |= IXGBE_EIMS_GPI_SDP0;
2240 break;
2241 case ixgbe_mac_X540:
2242 mask |= IXGBE_EIMS_TS;
2243 break;
2244 default:
2245 break;
2246 }
2c4af694
AD		 2247 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2248 mask |= IXGBE_EIMS_GPI_SDP1;
2249 switch (adapter->hw.mac.type) {
2250 case ixgbe_mac_82599EB:
2c4af694
AD		 2251 mask |= IXGBE_EIMS_GPI_SDP1;
2252 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2253 case ixgbe_mac_X540:
2254 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2255 mask |= IXGBE_EIMS_MAILBOX;
2256 break;
2257 default:
2258 break;
9a799d71 2259 }
2c4af694
AD		 2260 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2261 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2262 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2263
2c4af694
AD		 2264 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2265 if (queues)
2266 ixgbe_irq_enable_queues(adapter, ~0);
2267 if (flush)
2268 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2269}
2270
2c4af694 2271static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2272{
a65151ba 2273 struct ixgbe_adapter *adapter = data;
9a799d71 2274 struct ixgbe_hw *hw = &adapter->hw;
54037505 2275 u32 eicr;
91281fd3 2276
54037505
DS		 2277 /*
2278 * Workaround for Silicon errata. Use clear-by-write instead
2279 * of clear-by-read. Reading with EICS will return the
2280 * interrupt causes without clearing, which later be done
2281 * with the write to EICR.
2282 */
2283 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2284 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2285
cf8280ee
JB		 2286 if (eicr & IXGBE_EICR_LSC)
2287 ixgbe_check_lsc(adapter);
f0848276 2288
1cdd1ec8
GR		 2289 if (eicr & IXGBE_EICR_MAILBOX)
2290 ixgbe_msg_task(adapter);
efe3d3c8 2291
bd508178
AD		 2292 switch (hw->mac.type) {
2293 case ixgbe_mac_82599EB:
b93a2226 2294 case ixgbe_mac_X540:
2c4af694
AD		 2295 if (eicr & IXGBE_EICR_ECC)
2296 e_info(link, "Received unrecoverable ECC Err, please "
2297 "reboot\n");
c4cf55e5
PWJ		 2298 /* Handle Flow Director Full threshold interrupt */
2299 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2300 int reinit_count = 0;
c4cf55e5 2301 int i;
c4cf55e5 2302 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2303 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2304 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2305 &ring->state))
2306 reinit_count++;
2307 }
2308 if (reinit_count) {
2309 /* no more flow director interrupts until after init */
2310 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2311 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2312 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2313 }
2314 }
f0f9778d 2315 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2316 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2317 break;
2318 default:
2319 break;
c4cf55e5 2320 }
f0848276 2321
bd508178 2322 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2323#ifdef CONFIG_IXGBE_PTP
2324 ixgbe_ptp_check_pps_event(adapter, eicr);
2325#endif
efe3d3c8 2326
7086400d 2327 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2328 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2329 ixgbe_irq_enable(adapter, false, false);
f0848276 2330
9a799d71 2331 return IRQ_HANDLED;
f0848276 2332}
91281fd3 2333
4ff7fb12 2334static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2335{
021230d4 2336 struct ixgbe_q_vector *q_vector = data;
91281fd3 2337
9b471446 2338 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2339
4ff7fb12
AD		 2340 if (q_vector->rx.ring || q_vector->tx.ring)
2341 napi_schedule(&q_vector->napi);
91281fd3 2342
9a799d71 2343 return IRQ_HANDLED;
91281fd3
AD		 2344}
2345
eb01b975
AD		 2346/**
2347 * ixgbe_poll - NAPI Rx polling callback
2348 * @napi: structure for representing this polling device
2349 * @budget: how many packets driver is allowed to clean
2350 *
2351 * This function is used for legacy and MSI, NAPI mode
2352 **/
8af3c33f 2353int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2354{
2355 struct ixgbe_q_vector *q_vector =
2356 container_of(napi, struct ixgbe_q_vector, napi);
2357 struct ixgbe_adapter *adapter = q_vector->adapter;
2358 struct ixgbe_ring *ring;
2359 int per_ring_budget;
2360 bool clean_complete = true;
2361
2362#ifdef CONFIG_IXGBE_DCA
2363 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2364 ixgbe_update_dca(q_vector);
2365#endif
2366
2367 ixgbe_for_each_ring(ring, q_vector->tx)
2368 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2369
2370 /* attempt to distribute budget to each queue fairly, but don't allow
2371 * the budget to go below 1 because we'll exit polling */
2372 if (q_vector->rx.count > 1)
2373 per_ring_budget = max(budget/q_vector->rx.count, 1);
2374 else
2375 per_ring_budget = budget;
2376
2377 ixgbe_for_each_ring(ring, q_vector->rx)
2378 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2379 per_ring_budget);
2380
2381 /* If all work not completed, return budget and keep polling */
2382 if (!clean_complete)
2383 return budget;
2384
2385 /* all work done, exit the polling mode */
2386 napi_complete(napi);
2387 if (adapter->rx_itr_setting & 1)
2388 ixgbe_set_itr(q_vector);
2389 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2390 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2391
2392 return 0;
2393}
2394
021230d4
AV		 2395/**
2396 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2397 * @adapter: board private structure
2398 *
2399 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2400 * interrupts from the kernel.
2401 **/
2402static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2403{
2404 struct net_device *netdev = adapter->netdev;
207867f5 2405 int vector, err;
e8e9f696 2406 int ri = 0, ti = 0;
021230d4 2407
49c7ffbe 2408 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2409 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2410 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2411
4ff7fb12 2412 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2413 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2414 "%s-%s-%d", netdev->name, "TxRx", ri++);
2415 ti++;
2416 } else if (q_vector->rx.ring) {
9fe93afd 2417 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2418 "%s-%s-%d", netdev->name, "rx", ri++);
2419 } else if (q_vector->tx.ring) {
9fe93afd 2420 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2421 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2422 } else {
2423 /* skip this unused q_vector */
2424 continue;
32aa77a4 2425 }
207867f5
AD		 2426 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2427 q_vector->name, q_vector);
9a799d71 2428 if (err) {
396e799c 2429 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2430 "Error: %d\n", err);
021230d4 2431 goto free_queue_irqs;
9a799d71 2432 }
207867f5
AD		 2433 /* If Flow Director is enabled, set interrupt affinity */
2434 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2435 /* assign the mask for this irq */
2436 irq_set_affinity_hint(entry->vector,
de88eeeb 2437 &q_vector->affinity_mask);
207867f5 2438 }
9a799d71
AK		 2439 }
2440
021230d4 2441 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2442 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2443 if (err) {
de88eeeb 2444 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2445 goto free_queue_irqs;
9a799d71
AK		 2446 }
2447
9a799d71
AK		 2448 return 0;
2449
021230d4 2450free_queue_irqs:
207867f5
AD		 2451 while (vector) {
2452 vector--;
2453 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2454 NULL);
2455 free_irq(adapter->msix_entries[vector].vector,
2456 adapter->q_vector[vector]);
2457 }
021230d4
AV		 2458 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2459 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2460 kfree(adapter->msix_entries);
2461 adapter->msix_entries = NULL;
9a799d71
AK		 2462 return err;
2463}
2464
2465/**
021230d4 2466 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2467 * @irq: interrupt number
2468 * @data: pointer to a network interface device structure
9a799d71
AK		 2469 **/
2470static irqreturn_t ixgbe_intr(int irq, void *data)
2471{
a65151ba 2472 struct ixgbe_adapter *adapter = data;
9a799d71 2473 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2474 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2475 u32 eicr;
2476
54037505 2477 /*
24ddd967 2478 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2479 * before the read of EICR.
2480 */
2481 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2482
021230d4 2483 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2484 * therefore no explicit interrupt disable is necessary */
021230d4 2485 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2486 if (!eicr) {
6af3b9eb
ET		 2487 /*
2488 * shared interrupt alert!
f47cf66e 2489 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2490 * have disabled interrupts due to EIAM
2491 * finish the workaround of silicon errata on 82598. Unmask
2492 * the interrupt that we masked before the EICR read.
2493 */
2494 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2495 ixgbe_irq_enable(adapter, true, true);
9a799d71 2496 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2497 }
9a799d71 2498
cf8280ee
JB		 2499 if (eicr & IXGBE_EICR_LSC)
2500 ixgbe_check_lsc(adapter);
021230d4 2501
bd508178
AD		 2502 switch (hw->mac.type) {
2503 case ixgbe_mac_82599EB:
e8e26350 2504 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2505 /* Fall through */
2506 case ixgbe_mac_X540:
2507 if (eicr & IXGBE_EICR_ECC)
2508 e_info(link, "Received unrecoverable ECC err, please "
2509 "reboot\n");
4f51bf70 2510 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2511 break;
2512 default:
2513 break;
2514 }
e8e26350 2515
0befdb3e 2516 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2517#ifdef CONFIG_IXGBE_PTP
2518 ixgbe_ptp_check_pps_event(adapter, eicr);
2519#endif
0befdb3e 2520
b9f6ed2b
AD		 2521 /* would disable interrupts here but EIAM disabled it */
2522 napi_schedule(&q_vector->napi);
9a799d71 2523
6af3b9eb
ET		 2524 /*
2525 * re-enable link(maybe) and non-queue interrupts, no flush.
2526 * ixgbe_poll will re-enable the queue interrupts
2527 */
6af3b9eb
ET		 2528 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2529 ixgbe_irq_enable(adapter, false, false);
2530
9a799d71
AK		 2531 return IRQ_HANDLED;
2532}
2533
2534/**
2535 * ixgbe_request_irq - initialize interrupts
2536 * @adapter: board private structure
2537 *
2538 * Attempts to configure interrupts using the best available
2539 * capabilities of the hardware and kernel.
2540 **/
021230d4 2541static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2542{
2543 struct net_device *netdev = adapter->netdev;
021230d4 2544 int err;
9a799d71 2545
4cc6df29 2546 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2547 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2548 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2549 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2550 netdev->name, adapter);
4cc6df29 2551 else
a0607fd3 2552 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2553 netdev->name, adapter);
9a799d71 2554
de88eeeb 2555 if (err)
396e799c 2556 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2557
9a799d71
AK		 2558 return err;
2559}
2560
2561static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2562{
49c7ffbe 2563 int vector;
9a799d71 2564
49c7ffbe
AD		 2565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2566 free_irq(adapter->pdev->irq, adapter);
2567 return;
2568 }
4cc6df29 2569
49c7ffbe
AD		 2570 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2571 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2572 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2573
49c7ffbe
AD		 2574 /* free only the irqs that were actually requested */
2575 if (!q_vector->rx.ring && !q_vector->tx.ring)
2576 continue;
207867f5 2577
49c7ffbe
AD		 2578 /* clear the affinity_mask in the IRQ descriptor */
2579 irq_set_affinity_hint(entry->vector, NULL);
2580
2581 free_irq(entry->vector, q_vector);
9a799d71 2582 }
49c7ffbe
AD		 2583
2584 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2585}
2586
22d5a71b
JB		 2587/**
2588 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2589 * @adapter: board private structure
2590 **/
2591static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2592{
bd508178
AD		 2593 switch (adapter->hw.mac.type) {
2594 case ixgbe_mac_82598EB:
835462fc 2595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2596 break;
2597 case ixgbe_mac_82599EB:
b93a2226 2598 case ixgbe_mac_X540:
835462fc
NS		 2599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2602 break;
2603 default:
2604 break;
22d5a71b
JB		 2605 }
2606 IXGBE_WRITE_FLUSH(&adapter->hw);
2607 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2608 int vector;
2609
2610 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2611 synchronize_irq(adapter->msix_entries[vector].vector);
2612
2613 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2614 } else {
2615 synchronize_irq(adapter->pdev->irq);
2616 }
2617}
2618
9a799d71
AK		 2619/**
2620 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2621 *
2622 **/
2623static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2624{
d5bf4f67 2625 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2626
d5bf4f67
ET		 2627 /* rx/tx vector */
2628 if (adapter->rx_itr_setting == 1)
2629 q_vector->itr = IXGBE_20K_ITR;
2630 else
2631 q_vector->itr = adapter->rx_itr_setting;
2632
2633 ixgbe_write_eitr(q_vector);
9a799d71 2634
e8e26350
PW		 2635 ixgbe_set_ivar(adapter, 0, 0, 0);
2636 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2637
396e799c 2638 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2639}
2640
43e69bf0
AD		 2641/**
2642 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2643 * @adapter: board private structure
2644 * @ring: structure containing ring specific data
2645 *
2646 * Configure the Tx descriptor ring after a reset.
2647 **/
84418e3b
AD		 2648void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2649 struct ixgbe_ring *ring)
43e69bf0
AD		 2650{
2651 struct ixgbe_hw *hw = &adapter->hw;
2652 u64 tdba = ring->dma;
2f1860b8 2653 int wait_loop = 10;
b88c6de2 2654 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2655 u8 reg_idx = ring->reg_idx;
43e69bf0 2656
2f1860b8 2657 /* disable queue to avoid issues while updating state */
b88c6de2 2658 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2659 IXGBE_WRITE_FLUSH(hw);
2660
43e69bf0 2661 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2662 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2663 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2664 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2665 ring->count * sizeof(union ixgbe_adv_tx_desc));
2666 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2667 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2668 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2669
b88c6de2
AD		 2670 /*
2671 * set WTHRESH to encourage burst writeback, it should not be set
2672 * higher than 1 when ITR is 0 as it could cause false TX hangs
2673 *
2674 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2675 * to or less than the number of on chip descriptors, which is
2676 * currently 40.
2677 */
e954b374 2678 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2679 txdctl |= (1 << 16); /* WTHRESH = 1 */
2680 else
2681 txdctl |= (8 << 16); /* WTHRESH = 8 */
2682
e954b374
AD		 2683 /*
2684 * Setting PTHRESH to 32 both improves performance
2685 * and avoids a TX hang with DFP enabled
2686 */
b88c6de2
AD		 2687 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2688 32; /* PTHRESH = 32 */
2f1860b8
AD		 2689
2690 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2691 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2692 adapter->atr_sample_rate) {
2693 ring->atr_sample_rate = adapter->atr_sample_rate;
2694 ring->atr_count = 0;
2695 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2696 } else {
2697 ring->atr_sample_rate = 0;
2698 }
2f1860b8 2699
c84d324c
JF		 2700 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2701
2f1860b8 2702 /* enable queue */
2f1860b8
AD		 2703 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2704
2705 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2706 if (hw->mac.type == ixgbe_mac_82598EB &&
2707 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2708 return;
2709
2710 /* poll to verify queue is enabled */
2711 do {
032b4325 2712 usleep_range(1000, 2000);
2f1860b8
AD		 2713 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2714 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2715 if (!wait_loop)
2716 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2717}
2718
120ff942
AD		 2719static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2720{
2721 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2722 u32 rttdcs, mtqc;
8b1c0b24 2723 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2724
2725 if (hw->mac.type == ixgbe_mac_82598EB)
2726 return;
2727
2728 /* disable the arbiter while setting MTQC */
2729 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2730 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2731 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2732
2733 /* set transmit pool layout */
671c0adb
AD		 2734 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2735 mtqc = IXGBE_MTQC_VT_ENA;
2736 if (tcs > 4)
2737 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2738 else if (tcs > 1)
2739 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2740 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2741 mtqc |= IXGBE_MTQC_32VF;
2742 else
2743 mtqc |= IXGBE_MTQC_64VF;
2744 } else {
2745 if (tcs > 4)
2746 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2747 else if (tcs > 1)
2748 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2749 else
671c0adb
AD		 2750 mtqc = IXGBE_MTQC_64Q_1PB;
2751 }
120ff942 2752
671c0adb 2753 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2754
671c0adb
AD		 2755 /* Enable Security TX Buffer IFG for multiple pb */
2756 if (tcs) {
2757 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2758 sectx |= IXGBE_SECTX_DCB;
2759 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2760 }
2761
2762 /* re-enable the arbiter */
2763 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2764 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2765}
2766
9a799d71 2767/**
3a581073 2768 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2769 * @adapter: board private structure
2770 *
2771 * Configure the Tx unit of the MAC after a reset.
2772 **/
2773static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2774{
2f1860b8
AD		 2775 struct ixgbe_hw *hw = &adapter->hw;
2776 u32 dmatxctl;
43e69bf0 2777 u32 i;
9a799d71 2778
2f1860b8
AD		 2779 ixgbe_setup_mtqc(adapter);
2780
2781 if (hw->mac.type != ixgbe_mac_82598EB) {
2782 /* DMATXCTL.EN must be before Tx queues are enabled */
2783 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2784 dmatxctl |= IXGBE_DMATXCTL_TE;
2785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2786 }
2787
9a799d71 2788 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2789 for (i = 0; i < adapter->num_tx_queues; i++)
2790 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2791}
2792
3ebe8fde
AD		 2793static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2794 struct ixgbe_ring *ring)
2795{
2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u8 reg_idx = ring->reg_idx;
2798 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2799
2800 srrctl |= IXGBE_SRRCTL_DROP_EN;
2801
2802 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2803}
2804
2805static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2806 struct ixgbe_ring *ring)
2807{
2808 struct ixgbe_hw *hw = &adapter->hw;
2809 u8 reg_idx = ring->reg_idx;
2810 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2811
2812 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2813
2814 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2815}
2816
2817#ifdef CONFIG_IXGBE_DCB
2818void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2819#else
2820static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2821#endif
2822{
2823 int i;
2824 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2825
2826 if (adapter->ixgbe_ieee_pfc)
2827 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2828
2829 /*
2830 * We should set the drop enable bit if:
2831 * SR-IOV is enabled
2832 * or
2833 * Number of Rx queues > 1 and flow control is disabled
2834 *
2835 * This allows us to avoid head of line blocking for security
2836 * and performance reasons.
2837 */
2838 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2839 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2840 for (i = 0; i < adapter->num_rx_queues; i++)
2841 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2842 } else {
2843 for (i = 0; i < adapter->num_rx_queues; i++)
2844 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2845 }
2846}
2847
e8e26350 2848#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2849
a6616b42 2850static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2851 struct ixgbe_ring *rx_ring)
cc41ac7c 2852{
45e9baa5 2853 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2854 u32 srrctl;
bf29ee6c 2855 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2856
45e9baa5
AD		 2857 if (hw->mac.type == ixgbe_mac_82598EB) {
2858 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2859
45e9baa5
AD		 2860 /*
2861 * if VMDq is not active we must program one srrctl register
2862 * per RSS queue since we have enabled RDRXCTL.MVMEN
2863 */
2864 reg_idx &= mask;
2865 }
cc41ac7c 2866
45e9baa5
AD		 2867 /* configure header buffer length, needed for RSC */
2868 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2869
45e9baa5 2870 /* configure the packet buffer length */
f800326d
AD		 2871#if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2872 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2873#else
f800326d 2874 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2875#endif
45e9baa5
AD		 2876
2877 /* configure descriptor type */
f800326d 2878 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2879
45e9baa5 2880 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2881}
9a799d71 2882
05abb126 2883static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2884{
05abb126
AD		 2885 struct ixgbe_hw *hw = &adapter->hw;
2886 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2887 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2888 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2889 u32 mrqc = 0, reta = 0;
2890 u32 rxcsum;
2891 int i, j;
671c0adb
AD		 2892 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2893
671c0adb
AD		 2894 /*
2895 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2896 * make full use of any rings they may have. We will use the
2897 * PSRTYPE register to control how many rings we use within the PF.
2898 */
2899 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2900 rss_i = 2;
0cefafad 2901
05abb126
AD		 2902 /* Fill out hash function seeds */
2903 for (i = 0; i < 10; i++)
2904 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2905
2906 /* Fill out redirection table */
2907 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2908 if (j == rss_i)
05abb126
AD		 2909 j = 0;
2910 /* reta = 4-byte sliding window of
2911 * 0x00..(indices-1)(indices-1)00..etc. */
2912 reta = (reta << 8) | (j * 0x11);
2913 if ((i & 3) == 3)
2914 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2915 }
0cefafad 2916
05abb126
AD		 2917 /* Disable indicating checksum in descriptor, enables RSS hash */
2918 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2919 rxcsum |= IXGBE_RXCSUM_PCSD;
2920 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2921
671c0adb 2922 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 2923 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 2924 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2925 } else {
671c0adb
AD		 2926 u8 tcs = netdev_get_num_tc(adapter->netdev);
2927
2928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2929 if (tcs > 4)
2930 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
2931 else if (tcs > 1)
2932 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
2933 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2934 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 2935 else
671c0adb
AD		 2936 mrqc = IXGBE_MRQC_VMDQRSS64EN;
2937 } else {
2938 if (tcs > 4)
8b1c0b24 2939 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 2940 else if (tcs > 1)
2941 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2942 else
2943 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2944 }
0cefafad
JB		 2945 }
2946
05abb126 2947 /* Perform hash on these packet types */
671c0adb
AD		 2948 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2949 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2950 IXGBE_MRQC_RSS_FIELD_IPV6 |
2951 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 2952
ef6afc0c
AD		 2953 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2954 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2955 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2956 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2957
05abb126 2958 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2959}
2960
bb5a9ad2
NS		 2961/**
2962 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2963 * @adapter: address of board private structure
2964 * @index: index of ring to set
bb5a9ad2 2965 **/
082757af 2966static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2967 struct ixgbe_ring *ring)
bb5a9ad2 2968{
bb5a9ad2 2969 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2970 u32 rscctrl;
bf29ee6c 2971 u8 reg_idx = ring->reg_idx;
7367096a 2972
7d637bcc 2973 if (!ring_is_rsc_enabled(ring))
7367096a 2974 return;
bb5a9ad2 2975
7367096a 2976 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2977 rscctrl |= IXGBE_RSCCTL_RSCEN;
2978 /*
2979 * we must limit the number of descriptors so that the
2980 * total size of max desc * buf_len is not greater
642c680e 2981 * than 65536
bb5a9ad2 2982 */
f800326d
AD		 2983#if (PAGE_SIZE <= 8192)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2985#elif (PAGE_SIZE <= 16384)
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
bb5a9ad2 2987#else
f800326d 2988 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
bb5a9ad2 2989#endif
7367096a 2990 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2991}
2992
9e10e045
AD		 2993#define IXGBE_MAX_RX_DESC_POLL 10
2994static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2995 struct ixgbe_ring *ring)
2996{
2997 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2998 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2999 u32 rxdctl;
bf29ee6c 3000 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3001
3002 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3003 if (hw->mac.type == ixgbe_mac_82598EB &&
3004 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3005 return;
3006
3007 do {
032b4325 3008 usleep_range(1000, 2000);
9e10e045
AD		 3009 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3010 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3011
3012 if (!wait_loop) {
3013 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3014 "the polling period\n", reg_idx);
3015 }
3016}
3017
2d39d576
YZ		 3018void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3019 struct ixgbe_ring *ring)
3020{
3021 struct ixgbe_hw *hw = &adapter->hw;
3022 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3023 u32 rxdctl;
3024 u8 reg_idx = ring->reg_idx;
3025
3026 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3027 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3028
3029 /* write value back with RXDCTL.ENABLE bit cleared */
3030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3031
3032 if (hw->mac.type == ixgbe_mac_82598EB &&
3033 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3034 return;
3035
3036 /* the hardware may take up to 100us to really disable the rx queue */
3037 do {
3038 udelay(10);
3039 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3040 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3041
3042 if (!wait_loop) {
3043 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3044 "the polling period\n", reg_idx);
3045 }
3046}
3047
84418e3b
AD		 3048void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
acd37177
AD		 3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 u64 rdba = ring->dma;
9e10e045 3053 u32 rxdctl;
bf29ee6c 3054 u8 reg_idx = ring->reg_idx;
acd37177 3055
9e10e045
AD		 3056 /* disable queue to avoid issues while updating state */
3057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3058 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3059
acd37177
AD		 3060 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3061 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3062 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3063 ring->count * sizeof(union ixgbe_adv_rx_desc));
3064 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3065 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3066 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3067
3068 ixgbe_configure_srrctl(adapter, ring);
3069 ixgbe_configure_rscctl(adapter, ring);
3070
e9f98072
GR		 3071 /* If operating in IOV mode set RLPML for X540 */
3072 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3073 hw->mac.type == ixgbe_mac_X540) {
3074 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3075 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3076 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3077 }
3078
9e10e045
AD		 3079 if (hw->mac.type == ixgbe_mac_82598EB) {
3080 /*
3081 * enable cache line friendly hardware writes:
3082 * PTHRESH=32 descriptors (half the internal cache),
3083 * this also removes ugly rx_no_buffer_count increment
3084 * HTHRESH=4 descriptors (to minimize latency on fetch)
3085 * WTHRESH=8 burst writeback up to two cache lines
3086 */
3087 rxdctl &= ~0x3FFFFF;
3088 rxdctl |= 0x080420;
3089 }
3090
3091 /* enable receive descriptor ring */
3092 rxdctl |= IXGBE_RXDCTL_ENABLE;
3093 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3094
3095 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3096 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3097}
3098
48654521
AD		 3099static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3100{
3101 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3102 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3103 int p;
3104
3105 /* PSRTYPE must be initialized in non 82598 adapters */
3106 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3107 IXGBE_PSRTYPE_UDPHDR |
3108 IXGBE_PSRTYPE_IPV4HDR |
48654521 3109 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3110 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3111
3112 if (hw->mac.type == ixgbe_mac_82598EB)
3113 return;
3114
fbe7ca7f
AD		 3115 if (rss_i > 3)
3116 psrtype |= 2 << 29;
3117 else if (rss_i > 1)
3118 psrtype |= 1 << 29;
48654521
AD		 3119
3120 for (p = 0; p < adapter->num_rx_pools; p++)
3121 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3122 psrtype);
3123}
3124
f5b4a52e
AD		 3125static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3128 u32 reg_offset, vf_shift;
435b19f6 3129 u32 gcr_ext, vmdctl;
de4c7f65 3130 int i;
f5b4a52e
AD		 3131
3132 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3133 return;
3134
3135 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3136 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3137 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3138 vmdctl |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3139 vmdctl |= IXGBE_VT_CTL_REPLEN;
3140 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e
AD		 3141
3142 vf_shift = adapter->num_vfs % 32;
4cd6923d 3143 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 3144
3145 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3146 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3147 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3148 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3149 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3150 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3151
3152 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3153 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3154
3155 /*
3156 * Set up VF register offsets for selected VT Mode,
3157 * i.e. 32 or 64 VFs for SR-IOV
3158 */
73079ea0
AD		 3159 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3160 case IXGBE_82599_VMDQ_8Q_MASK:
3161 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3162 break;
3163 case IXGBE_82599_VMDQ_4Q_MASK:
3164 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3165 break;
3166 default:
3167 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3168 break;
3169 }
3170
f5b4a52e
AD		 3171 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3172
3173 /* enable Tx loopback for VF/PF communication */
3174 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3175
a985b6c3 3176 /* Enable MAC Anti-Spoofing */
435b19f6 3177 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3178 adapter->num_vfs);
de4c7f65
GR		 3179 /* For VFs that have spoof checking turned off */
3180 for (i = 0; i < adapter->num_vfs; i++) {
3181 if (!adapter->vfinfo[i].spoofchk_enabled)
3182 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3183 }
f5b4a52e
AD		 3184}
3185
477de6ed 3186static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3187{
9a799d71
AK		 3188 struct ixgbe_hw *hw = &adapter->hw;
3189 struct net_device *netdev = adapter->netdev;
3190 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3191 struct ixgbe_ring *rx_ring;
3192 int i;
3193 u32 mhadd, hlreg0;
48654521 3194
63f39bd1 3195#ifdef IXGBE_FCOE
477de6ed
AD		 3196 /* adjust max frame to be able to do baby jumbo for FCoE */
3197 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3198 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3199 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3200
477de6ed
AD		 3201#endif /* IXGBE_FCOE */
3202 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3203 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3204 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3205 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3206
3207 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3208 }
3209
919e78a6
AD		 3210 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3211 max_frame += VLAN_HLEN;
3212
477de6ed
AD		 3213 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3214 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3215 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3216 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3217
0cefafad
JB		 3218 /*
3219 * Setup the HW Rx Head and Tail Descriptor Pointers and
3220 * the Base and Length of the Rx Descriptor Ring
3221 */
9a799d71 3222 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3223 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3224 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3225 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3226 else
7d637bcc 3227 clear_ring_rsc_enabled(rx_ring);
477de6ed 3228 }
477de6ed
AD		 3229}
3230
7367096a
AD		 3231static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3232{
3233 struct ixgbe_hw *hw = &adapter->hw;
3234 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3235
3236 switch (hw->mac.type) {
3237 case ixgbe_mac_82598EB:
3238 /*
3239 * For VMDq support of different descriptor types or
3240 * buffer sizes through the use of multiple SRRCTL
3241 * registers, RDRXCTL.MVMEN must be set to 1
3242 *
3243 * also, the manual doesn't mention it clearly but DCA hints
3244 * will only use queue 0's tags unless this bit is set. Side
3245 * effects of setting this bit are only that SRRCTL must be
3246 * fully programmed [0..15]
3247 */
3248 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3249 break;
3250 case ixgbe_mac_82599EB:
b93a2226 3251 case ixgbe_mac_X540:
7367096a
AD		 3252 /* Disable RSC for ACK packets */
3253 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3254 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3255 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3256 /* hardware requires some bits to be set by default */
3257 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3258 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3259 break;
3260 default:
3261 /* We should do nothing since we don't know this hardware */
3262 return;
3263 }
3264
3265 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3266}
3267
477de6ed
AD		 3268/**
3269 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3270 * @adapter: board private structure
3271 *
3272 * Configure the Rx unit of the MAC after a reset.
3273 **/
3274static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3275{
3276 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3277 int i;
3278 u32 rxctrl;
477de6ed
AD		 3279
3280 /* disable receives while setting up the descriptors */
3281 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3282 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3283
3284 ixgbe_setup_psrtype(adapter);
7367096a 3285 ixgbe_setup_rdrxctl(adapter);
477de6ed 3286
9e10e045 3287 /* Program registers for the distribution of queues */
f5b4a52e 3288 ixgbe_setup_mrqc(adapter);
f5b4a52e 3289
477de6ed
AD		 3290 /* set_rx_buffer_len must be called before ring initialization */
3291 ixgbe_set_rx_buffer_len(adapter);
3292
3293 /*
3294 * Setup the HW Rx Head and Tail Descriptor Pointers and
3295 * the Base and Length of the Rx Descriptor Ring
3296 */
9e10e045
AD		 3297 for (i = 0; i < adapter->num_rx_queues; i++)
3298 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3299
9e10e045
AD		 3300 /* disable drop enable for 82598 parts */
3301 if (hw->mac.type == ixgbe_mac_82598EB)
3302 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3303
3304 /* enable all receives */
3305 rxctrl |= IXGBE_RXCTRL_RXEN;
3306 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3307}
3308
8e586137 3309static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3310{
3311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3312 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3313 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3314
3315 /* add VID to filter table */
1ada1b1b 3316 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3317 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3318
3319 return 0;
068c89b0
DS		 3320}
3321
8e586137 3322static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3323{
3324 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3325 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3326 int pool_ndx = adapter->num_vfs;
068c89b0 3327
068c89b0 3328 /* remove VID from filter table */
1ada1b1b 3329 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3330 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3331
3332 return 0;
068c89b0
DS		 3333}
3334
5f6c0181
JB		 3335/**
3336 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3337 * @adapter: driver data
3338 */
3339static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3340{
3341 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3342 u32 vlnctrl;
3343
3344 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3345 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3346 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3347}
3348
3349/**
3350 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3351 * @adapter: driver data
3352 */
3353static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3354{
3355 struct ixgbe_hw *hw = &adapter->hw;
3356 u32 vlnctrl;
3357
3358 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3359 vlnctrl |= IXGBE_VLNCTRL_VFE;
3360 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3361 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3362}
3363
3364/**
3365 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3366 * @adapter: driver data
3367 */
3368static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3369{
3370 struct ixgbe_hw *hw = &adapter->hw;
3371 u32 vlnctrl;
5f6c0181
JB		 3372 int i, j;
3373
3374 switch (hw->mac.type) {
3375 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3376 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3377 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3378 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3379 break;
3380 case ixgbe_mac_82599EB:
b93a2226 3381 case ixgbe_mac_X540:
5f6c0181
JB		 3382 for (i = 0; i < adapter->num_rx_queues; i++) {
3383 j = adapter->rx_ring[i]->reg_idx;
3384 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3385 vlnctrl &= ~IXGBE_RXDCTL_VME;
3386 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3387 }
3388 break;
3389 default:
3390 break;
3391 }
3392}
3393
3394/**
f62bbb5e 3395 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3396 * @adapter: driver data
3397 */
f62bbb5e 3398static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3399{
3400 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3401 u32 vlnctrl;
5f6c0181
JB		 3402 int i, j;
3403
3404 switch (hw->mac.type) {
3405 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3406 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3407 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3408 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3409 break;
3410 case ixgbe_mac_82599EB:
b93a2226 3411 case ixgbe_mac_X540:
5f6c0181
JB		 3412 for (i = 0; i < adapter->num_rx_queues; i++) {
3413 j = adapter->rx_ring[i]->reg_idx;
3414 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3415 vlnctrl |= IXGBE_RXDCTL_VME;
3416 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3417 }
3418 break;
3419 default:
3420 break;
3421 }
3422}
3423
9a799d71
AK		 3424static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3425{
f62bbb5e 3426 u16 vid;
9a799d71 3427
f62bbb5e
JG		 3428 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3429
3430 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3431 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3432}
3433
2850062a
AD		 3434/**
3435 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3436 * @netdev: network interface device structure
3437 *
3438 * Writes unicast address list to the RAR table.
3439 * Returns: -ENOMEM on failure/insufficient address space
3440 * 0 on no addresses written
3441 * X on writing X addresses to the RAR table
3442 **/
3443static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3444{
3445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3446 struct ixgbe_hw *hw = &adapter->hw;
3447 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3448 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3449 int count = 0;
3450
3451 /* return ENOMEM indicating insufficient memory for addresses */
3452 if (netdev_uc_count(netdev) > rar_entries)
3453 return -ENOMEM;
3454
3455 if (!netdev_uc_empty(netdev) && rar_entries) {
3456 struct netdev_hw_addr *ha;
3457 /* return error if we do not support writing to RAR table */
3458 if (!hw->mac.ops.set_rar)
3459 return -ENOMEM;
3460
3461 netdev_for_each_uc_addr(ha, netdev) {
3462 if (!rar_entries)
3463 break;
3464 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3465 vfn, IXGBE_RAH_AV);
3466 count++;
3467 }
3468 }
3469 /* write the addresses in reverse order to avoid write combining */
3470 for (; rar_entries > 0 ; rar_entries--)
3471 hw->mac.ops.clear_rar(hw, rar_entries);
3472
3473 return count;
3474}
3475
9a799d71 3476/**
2c5645cf 3477 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3478 * @netdev: network interface device structure
3479 *
2c5645cf
CL		 3480 * The set_rx_method entry point is called whenever the unicast/multicast
3481 * address list or the network interface flags are updated. This routine is
3482 * responsible for configuring the hardware for proper unicast, multicast and
3483 * promiscuous mode.
9a799d71 3484 **/
7f870475 3485void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3486{
3487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3488 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3489 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3490 int count;
9a799d71
AK		 3491
3492 /* Check for Promiscuous and All Multicast modes */
3493
3494 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3495
f5dc442b 3496 /* set all bits that we expect to always be set */
3f2d1c0f 3497 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3498 fctrl |= IXGBE_FCTRL_BAM;
3499 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3500 fctrl |= IXGBE_FCTRL_PMCF;
3501
2850062a
AD		 3502 /* clear the bits we are changing the status of */
3503 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3504
9a799d71 3505 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3506 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3507 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3508 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3509 /* don't hardware filter vlans in promisc mode */
3510 ixgbe_vlan_filter_disable(adapter);
9a799d71 3511 } else {
746b9f02
PM		 3512 if (netdev->flags & IFF_ALLMULTI) {
3513 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3514 vmolr |= IXGBE_VMOLR_MPE;
3515 } else {
3516 /*
3517 * Write addresses to the MTA, if the attempt fails
25985edc 3518 * then we should just turn on promiscuous mode so
2850062a
AD		 3519 * that we can at least receive multicast traffic
3520 */
3521 hw->mac.ops.update_mc_addr_list(hw, netdev);
3522 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3523 }
5f6c0181 3524 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3525 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3526 }
3527
3528 /*
3529 * Write addresses to available RAR registers, if there is not
3530 * sufficient space to store all the addresses then enable
3531 * unicast promiscuous mode
3532 */
3533 count = ixgbe_write_uc_addr_list(netdev);
3534 if (count < 0) {
3535 fctrl |= IXGBE_FCTRL_UPE;
3536 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3537 }
3538
2850062a 3539 if (adapter->num_vfs) {
1cdd1ec8 3540 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3541 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3542 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3543 IXGBE_VMOLR_ROPE);
3544 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3545 }
3546
3f2d1c0f
BG		 3547 /* This is useful for sniffing bad packets. */
3548 if (adapter->netdev->features & NETIF_F_RXALL) {
3549 /* UPE and MPE will be handled by normal PROMISC logic
3550 * in e1000e_set_rx_mode */
3551 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3552 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3553 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3554
3555 fctrl &= ~(IXGBE_FCTRL_DPF);
3556 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3557 }
3558
2850062a 3559 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3560
3561 if (netdev->features & NETIF_F_HW_VLAN_RX)
3562 ixgbe_vlan_strip_enable(adapter);
3563 else
3564 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3565}
3566
021230d4
AV		 3567static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3568{
3569 int q_idx;
021230d4 3570
49c7ffbe
AD		 3571 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3572 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3573}
3574
3575static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3576{
3577 int q_idx;
021230d4 3578
49c7ffbe
AD		 3579 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3580 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3581}
3582
7a6b6f51 3583#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3584/**
2f90b865
AD		 3585 * ixgbe_configure_dcb - Configure DCB hardware
3586 * @adapter: ixgbe adapter struct
3587 *
3588 * This is called by the driver on open to configure the DCB hardware.
3589 * This is also called by the gennetlink interface when reconfiguring
3590 * the DCB state.
3591 */
3592static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3593{
3594 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3595 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3596
67ebd791
AD		 3597 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3598 if (hw->mac.type == ixgbe_mac_82598EB)
3599 netif_set_gso_max_size(adapter->netdev, 65536);
3600 return;
3601 }
3602
3603 if (hw->mac.type == ixgbe_mac_82598EB)
3604 netif_set_gso_max_size(adapter->netdev, 32768);
3605
2f90b865 3606 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3607
971060b1 3608#ifdef IXGBE_FCOE
b120818e
JF		 3609 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3610 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3611#endif
b120818e
JF		 3612
3613 /* reconfigure the hardware */
3614 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3615 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3616 DCB_TX_CONFIG);
3617 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3618 DCB_RX_CONFIG);
3619 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3620 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3621 ixgbe_dcb_hw_ets(&adapter->hw,
3622 adapter->ixgbe_ieee_ets,
3623 max_frame);
3624 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3625 adapter->ixgbe_ieee_pfc->pfc_en,
3626 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3627 }
8187cd48
JF		 3628
3629 /* Enable RSS Hash per TC */
3630 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3631 u32 msb = 0;
3632 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3633
d411a936
AD		 3634 while (rss_i) {
3635 msb++;
3636 rss_i >>= 1;
3637 }
8187cd48 3638
4ae63730
AD		 3639 /* write msb to all 8 TCs in one write */
3640 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3641 }
2f90b865 3642}
9da712d2
JF		 3643#endif
3644
3645/* Additional bittime to account for IXGBE framing */
3646#define IXGBE_ETH_FRAMING 20
3647
49ce9c2c 3648/**
9da712d2
JF		 3649 * ixgbe_hpbthresh - calculate high water mark for flow control
3650 *
3651 * @adapter: board private structure to calculate for
49ce9c2c 3652 * @pb: packet buffer to calculate
9da712d2
JF		 3653 */
3654static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3655{
3656 struct ixgbe_hw *hw = &adapter->hw;
3657 struct net_device *dev = adapter->netdev;
3658 int link, tc, kb, marker;
3659 u32 dv_id, rx_pba;
3660
3661 /* Calculate max LAN frame size */
3662 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3663
3664#ifdef IXGBE_FCOE
3665 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3666 if ((dev->features & NETIF_F_FCOE_MTU) &&
3667 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3668 (pb == ixgbe_fcoe_get_tc(adapter)))
3669 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3670
3671#endif
9da712d2
JF		 3672 /* Calculate delay value for device */
3673 switch (hw->mac.type) {
3674 case ixgbe_mac_X540:
3675 dv_id = IXGBE_DV_X540(link, tc);
3676 break;
3677 default:
3678 dv_id = IXGBE_DV(link, tc);
3679 break;
3680 }
3681
3682 /* Loopback switch introduces additional latency */
3683 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3684 dv_id += IXGBE_B2BT(tc);
3685
3686 /* Delay value is calculated in bit times convert to KB */
3687 kb = IXGBE_BT2KB(dv_id);
3688 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3689
3690 marker = rx_pba - kb;
3691
3692 /* It is possible that the packet buffer is not large enough
3693 * to provide required headroom. In this case throw an error
3694 * to user and a do the best we can.
3695 */
3696 if (marker < 0) {
3697 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3698 "headroom to support flow control."
3699 "Decrease MTU or number of traffic classes\n", pb);
3700 marker = tc + 1;
3701 }
3702
3703 return marker;
3704}
3705
49ce9c2c 3706/**
9da712d2
JF		 3707 * ixgbe_lpbthresh - calculate low water mark for for flow control
3708 *
3709 * @adapter: board private structure to calculate for
49ce9c2c 3710 * @pb: packet buffer to calculate
9da712d2
JF		 3711 */
3712static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3713{
3714 struct ixgbe_hw *hw = &adapter->hw;
3715 struct net_device *dev = adapter->netdev;
3716 int tc;
3717 u32 dv_id;
3718
3719 /* Calculate max LAN frame size */
3720 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3721
3722 /* Calculate delay value for device */
3723 switch (hw->mac.type) {
3724 case ixgbe_mac_X540:
3725 dv_id = IXGBE_LOW_DV_X540(tc);
3726 break;
3727 default:
3728 dv_id = IXGBE_LOW_DV(tc);
3729 break;
3730 }
3731
3732 /* Delay value is calculated in bit times convert to KB */
3733 return IXGBE_BT2KB(dv_id);
3734}
3735
3736/*
3737 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3738 */
3739static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3740{
3741 struct ixgbe_hw *hw = &adapter->hw;
3742 int num_tc = netdev_get_num_tc(adapter->netdev);
3743 int i;
3744
3745 if (!num_tc)
3746 num_tc = 1;
3747
3748 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3749
3750 for (i = 0; i < num_tc; i++) {
3751 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3752
3753 /* Low water marks must not be larger than high water marks */
3754 if (hw->fc.low_water > hw->fc.high_water[i])
3755 hw->fc.low_water = 0;
3756 }
3757}
3758
80605c65
JF		 3759static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3760{
80605c65 3761 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3762 int hdrm;
3763 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3764
3765 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3766 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3767 hdrm = 32 << adapter->fdir_pballoc;
3768 else
3769 hdrm = 0;
80605c65 3770
f7e1027f 3771 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3772 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3773}
3774
e4911d57
AD		 3775static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3776{
3777 struct ixgbe_hw *hw = &adapter->hw;
3778 struct hlist_node *node, *node2;
3779 struct ixgbe_fdir_filter *filter;
3780
3781 spin_lock(&adapter->fdir_perfect_lock);
3782
3783 if (!hlist_empty(&adapter->fdir_filter_list))
3784 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3785
3786 hlist_for_each_entry_safe(filter, node, node2,
3787 &adapter->fdir_filter_list, fdir_node) {
3788 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3789 &filter->filter,
3790 filter->sw_idx,
3791 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3792 IXGBE_FDIR_DROP_QUEUE :
3793 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3794 }
3795
3796 spin_unlock(&adapter->fdir_perfect_lock);
3797}
3798
9a799d71
AK		 3799static void ixgbe_configure(struct ixgbe_adapter *adapter)
3800{
d2f5e7f3
AS		 3801 struct ixgbe_hw *hw = &adapter->hw;
3802
80605c65 3803 ixgbe_configure_pb(adapter);
7a6b6f51 3804#ifdef CONFIG_IXGBE_DCB
67ebd791 3805 ixgbe_configure_dcb(adapter);
2f90b865 3806#endif
9a799d71 3807
4c1d7b4b 3808 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3809 ixgbe_restore_vlan(adapter);
3810
eacd73f7
YZ		 3811#ifdef IXGBE_FCOE
3812 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3813 ixgbe_configure_fcoe(adapter);
3814
3815#endif /* IXGBE_FCOE */
d2f5e7f3
AS		 3816
3817 switch (hw->mac.type) {
3818 case ixgbe_mac_82599EB:
3819 case ixgbe_mac_X540:
3820 hw->mac.ops.disable_rx_buff(hw);
3821 break;
3822 default:
3823 break;
3824 }
3825
c4cf55e5 3826 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3827 ixgbe_init_fdir_signature_82599(&adapter->hw,
3828 adapter->fdir_pballoc);
e4911d57
AD		 3829 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3830 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3831 adapter->fdir_pballoc);
3832 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3833 }
4c1d7b4b 3834
d2f5e7f3
AS		 3835 switch (hw->mac.type) {
3836 case ixgbe_mac_82599EB:
3837 case ixgbe_mac_X540:
3838 hw->mac.ops.enable_rx_buff(hw);
3839 break;
3840 default:
3841 break;
3842 }
3843
933d41f1 3844 ixgbe_configure_virtualization(adapter);
c4cf55e5 3845
9a799d71
AK		 3846 ixgbe_configure_tx(adapter);
3847 ixgbe_configure_rx(adapter);
9a799d71
AK		 3848}
3849
e8e26350
PW		 3850static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3851{
3852 switch (hw->phy.type) {
3853 case ixgbe_phy_sfp_avago:
3854 case ixgbe_phy_sfp_ftl:
3855 case ixgbe_phy_sfp_intel:
3856 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3857 case ixgbe_phy_sfp_passive_tyco:
3858 case ixgbe_phy_sfp_passive_unknown:
3859 case ixgbe_phy_sfp_active_unknown:
3860 case ixgbe_phy_sfp_ftl_active:
e8e26350 3861 return true;
8917b447
AD		 3862 case ixgbe_phy_nl:
3863 if (hw->mac.type == ixgbe_mac_82598EB)
3864 return true;
e8e26350
PW		 3865 default:
3866 return false;
3867 }
3868}
3869
0ecc061d 3870/**
e8e26350
PW		 3871 * ixgbe_sfp_link_config - set up SFP+ link
3872 * @adapter: pointer to private adapter struct
3873 **/
3874static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3875{
7086400d 3876 /*
52f33af8 3877 * We are assuming the worst case scenario here, and that
7086400d
AD		 3878 * is that an SFP was inserted/removed after the reset
3879 * but before SFP detection was enabled. As such the best
3880 * solution is to just start searching as soon as we start
3881 */
3882 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3883 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3884
7086400d 3885 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3886}
3887
3888/**
3889 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3890 * @hw: pointer to private hardware struct
3891 *
3892 * Returns 0 on success, negative on failure
3893 **/
e8e26350 3894static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3895{
3896 u32 autoneg;
8620a103 3897 bool negotiation, link_up = false;
0ecc061d
PWJ		 3898 u32 ret = IXGBE_ERR_LINK_SETUP;
3899
3900 if (hw->mac.ops.check_link)
3901 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3902
3903 if (ret)
3904 goto link_cfg_out;
3905
0b0c2b31
ET		 3906 autoneg = hw->phy.autoneg_advertised;
3907 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3908 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3909 &negotiation);
0ecc061d
PWJ		 3910 if (ret)
3911 goto link_cfg_out;
3912
8620a103
MC		 3913 if (hw->mac.ops.setup_link)
3914 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3915link_cfg_out:
3916 return ret;
3917}
3918
a34bcfff 3919static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3920{
9a799d71 3921 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3922 u32 gpie = 0;
9a799d71 3923
9b471446 3924 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3925 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3926 IXGBE_GPIE_OCD;
3927 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3928 /*
3929 * use EIAM to auto-mask when MSI-X interrupt is asserted
3930 * this saves a register write for every interrupt
3931 */
3932 switch (hw->mac.type) {
3933 case ixgbe_mac_82598EB:
3934 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3935 break;
9b471446 3936 case ixgbe_mac_82599EB:
b93a2226
DS		 3937 case ixgbe_mac_X540:
3938 default:
9b471446
JB		 3939 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3940 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3941 break;
3942 }
3943 } else {
021230d4
AV		 3944 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3945 * specifically only auto mask tx and rx interrupts */
3946 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3947 }
9a799d71 3948
a34bcfff
AD		 3949 /* XXX: to interrupt immediately for EICS writes, enable this */
3950 /* gpie |= IXGBE_GPIE_EIMEN; */
3951
3952 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3953 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 3954
3955 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3956 case IXGBE_82599_VMDQ_8Q_MASK:
3957 gpie |= IXGBE_GPIE_VTMODE_16;
3958 break;
3959 case IXGBE_82599_VMDQ_4Q_MASK:
3960 gpie |= IXGBE_GPIE_VTMODE_32;
3961 break;
3962 default:
3963 gpie |= IXGBE_GPIE_VTMODE_64;
3964 break;
3965 }
119fc60a
MC		 3966 }
3967
5fdd31f9 3968 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3969 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3970 switch (adapter->hw.mac.type) {
3971 case ixgbe_mac_82599EB:
3972 gpie |= IXGBE_SDP0_GPIEN;
3973 break;
3974 case ixgbe_mac_X540:
3975 gpie |= IXGBE_EIMS_TS;
3976 break;
3977 default:
3978 break;
3979 }
3980 }
5fdd31f9 3981
a34bcfff
AD		 3982 /* Enable fan failure interrupt */
3983 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3984 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3985
2698b208 3986 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3987 gpie |= IXGBE_SDP1_GPIEN;
3988 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3989 }
a34bcfff
AD		 3990
3991 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3992}
3993
c7ccde0f 3994static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3995{
3996 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3997 int err;
a34bcfff
AD		 3998 u32 ctrl_ext;
3999
4000 ixgbe_get_hw_control(adapter);
4001 ixgbe_setup_gpie(adapter);
e8e26350 4002
9a799d71
AK		 4003 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4004 ixgbe_configure_msix(adapter);
4005 else
4006 ixgbe_configure_msi_and_legacy(adapter);
4007
c6ecf39a
DS		 4008 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4009 if (hw->mac.ops.enable_tx_laser &&
4010 ((hw->phy.multispeed_fiber) ||
9f911707 4011 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4012 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4013 hw->mac.ops.enable_tx_laser(hw);
4014
9a799d71 4015 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4016 ixgbe_napi_enable_all(adapter);
4017
73c4b7cd
AD		 4018 if (ixgbe_is_sfp(hw)) {
4019 ixgbe_sfp_link_config(adapter);
4020 } else {
4021 err = ixgbe_non_sfp_link_config(hw);
4022 if (err)
4023 e_err(probe, "link_config FAILED %d\n", err);
4024 }
4025
021230d4
AV		 4026 /* clear any pending interrupts, may auto mask */
4027 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4028 ixgbe_irq_enable(adapter, true, true);
9a799d71 4029
bf069c97
DS		 4030 /*
4031 * If this adapter has a fan, check to see if we had a failure
4032 * before we enabled the interrupt.
4033 */
4034 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4035 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4036 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4037 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4038 }
4039
1da100bb 4040 /* enable transmits */
477de6ed 4041 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4042
9a799d71
AK		 4043 /* bring the link up in the watchdog, this could race with our first
4044 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4045 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4046 adapter->link_check_timeout = jiffies;
7086400d 4047 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4048
4049 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4050 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4051 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4052 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4053}
4054
d4f80882
AV		 4055void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4056{
4057 WARN_ON(in_interrupt());
7086400d
AD		 4058 /* put off any impending NetWatchDogTimeout */
4059 adapter->netdev->trans_start = jiffies;
4060
d4f80882 4061 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4062 usleep_range(1000, 2000);
d4f80882 4063 ixgbe_down(adapter);
5809a1ae
GR		 4064 /*
4065 * If SR-IOV enabled then wait a bit before bringing the adapter
4066 * back up to give the VFs time to respond to the reset. The
4067 * two second wait is based upon the watchdog timer cycle in
4068 * the VF driver.
4069 */
4070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4071 msleep(2000);
d4f80882
AV		 4072 ixgbe_up(adapter);
4073 clear_bit(__IXGBE_RESETTING, &adapter->state);
4074}
4075
c7ccde0f 4076void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4077{
4078 /* hardware has been reset, we need to reload some things */
4079 ixgbe_configure(adapter);
4080
c7ccde0f 4081 ixgbe_up_complete(adapter);
9a799d71
AK		 4082}
4083
4084void ixgbe_reset(struct ixgbe_adapter *adapter)
4085{
c44ade9e 4086 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4087 int err;
4088
7086400d
AD		 4089 /* lock SFP init bit to prevent race conditions with the watchdog */
4090 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4091 usleep_range(1000, 2000);
4092
4093 /* clear all SFP and link config related flags while holding SFP_INIT */
4094 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4095 IXGBE_FLAG2_SFP_NEEDS_RESET);
4096 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4097
8ca783ab 4098 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4099 switch (err) {
4100 case 0:
4101 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4102 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4103 break;
4104 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4105 e_dev_err("master disable timed out\n");
da4dd0f7 4106 break;
794caeb2
PWJ		 4107 case IXGBE_ERR_EEPROM_VERSION:
4108 /* We are running on a pre-production device, log a warning */
849c4542 4109 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4110 "Please be aware there may be issues associated with "
849c4542
ET		 4111 "your hardware. If you are experiencing problems "
4112 "please contact your Intel or hardware "
4113 "representative who provided you with this "
4114 "hardware.\n");
794caeb2 4115 break;
da4dd0f7 4116 default:
849c4542 4117 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4118 }
9a799d71 4119
7086400d
AD		 4120 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4121
9a799d71 4122 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4123 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4124 IXGBE_RAH_AV);
9a799d71
AK		 4125}
4126
f800326d
AD		 4127/**
4128 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4129 * @rx_ring: ring to setup
4130 *
4131 * On many IA platforms the L1 cache has a critical stride of 4K, this
4132 * results in each receive buffer starting in the same cache set. To help
4133 * reduce the pressure on this cache set we can interleave the offsets so
4134 * that only every other buffer will be in the same cache set.
4135 **/
4136static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4137{
4138 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4139 u16 i;
4140
4141 for (i = 0; i < rx_ring->count; i += 2) {
4142 rx_buffer[0].page_offset = 0;
4143 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4144 rx_buffer = &rx_buffer[2];
4145 }
4146}
4147
9a799d71
AK		 4148/**
4149 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4150 * @rx_ring: ring to free buffers from
4151 **/
b6ec895e 4152static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4153{
b6ec895e 4154 struct device *dev = rx_ring->dev;
9a799d71 4155 unsigned long size;
b6ec895e 4156 u16 i;
9a799d71 4157
84418e3b
AD		 4158 /* ring already cleared, nothing to do */
4159 if (!rx_ring->rx_buffer_info)
4160 return;
9a799d71 4161
84418e3b 4162 /* Free all the Rx ring sk_buffs */
9a799d71 4163 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4164 struct ixgbe_rx_buffer *rx_buffer;
4165
4166 rx_buffer = &rx_ring->rx_buffer_info[i];
4167 if (rx_buffer->skb) {
4168 struct sk_buff *skb = rx_buffer->skb;
4169 if (IXGBE_CB(skb)->page_released) {
4170 dma_unmap_page(dev,
4171 IXGBE_CB(skb)->dma,
4172 ixgbe_rx_bufsz(rx_ring),
4173 DMA_FROM_DEVICE);
4174 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4175 }
4176 dev_kfree_skb(skb);
9a799d71 4177 }
f800326d
AD		 4178 rx_buffer->skb = NULL;
4179 if (rx_buffer->dma)
4180 dma_unmap_page(dev, rx_buffer->dma,
4181 ixgbe_rx_pg_size(rx_ring),
4182 DMA_FROM_DEVICE);
4183 rx_buffer->dma = 0;
4184 if (rx_buffer->page)
dd411ec4
AD		 4185 __free_pages(rx_buffer->page,
4186 ixgbe_rx_pg_order(rx_ring));
f800326d 4187 rx_buffer->page = NULL;
9a799d71
AK		 4188 }
4189
4190 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4191 memset(rx_ring->rx_buffer_info, 0, size);
4192
f800326d
AD		 4193 ixgbe_init_rx_page_offset(rx_ring);
4194
9a799d71
AK		 4195 /* Zero out the descriptor ring */
4196 memset(rx_ring->desc, 0, rx_ring->size);
4197
f800326d 4198 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4199 rx_ring->next_to_clean = 0;
4200 rx_ring->next_to_use = 0;
9a799d71
AK		 4201}
4202
4203/**
4204 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4205 * @tx_ring: ring to be cleaned
4206 **/
b6ec895e 4207static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4208{
4209 struct ixgbe_tx_buffer *tx_buffer_info;
4210 unsigned long size;
b6ec895e 4211 u16 i;
9a799d71 4212
84418e3b
AD		 4213 /* ring already cleared, nothing to do */
4214 if (!tx_ring->tx_buffer_info)
4215 return;
9a799d71 4216
84418e3b 4217 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4218 for (i = 0; i < tx_ring->count; i++) {
4219 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4220 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4221 }
4222
dad8a3b3
JF		 4223 netdev_tx_reset_queue(txring_txq(tx_ring));
4224
9a799d71
AK		 4225 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4226 memset(tx_ring->tx_buffer_info, 0, size);
4227
4228 /* Zero out the descriptor ring */
4229 memset(tx_ring->desc, 0, tx_ring->size);
4230
4231 tx_ring->next_to_use = 0;
4232 tx_ring->next_to_clean = 0;
9a799d71
AK		 4233}
4234
4235/**
021230d4 4236 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4237 * @adapter: board private structure
4238 **/
021230d4 4239static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4240{
4241 int i;
4242
021230d4 4243 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4244 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4245}
4246
4247/**
021230d4 4248 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4249 * @adapter: board private structure
4250 **/
021230d4 4251static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4252{
4253 int i;
4254
021230d4 4255 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4256 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4257}
4258
e4911d57
AD		 4259static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4260{
4261 struct hlist_node *node, *node2;
4262 struct ixgbe_fdir_filter *filter;
4263
4264 spin_lock(&adapter->fdir_perfect_lock);
4265
4266 hlist_for_each_entry_safe(filter, node, node2,
4267 &adapter->fdir_filter_list, fdir_node) {
4268 hlist_del(&filter->fdir_node);
4269 kfree(filter);
4270 }
4271 adapter->fdir_filter_count = 0;
4272
4273 spin_unlock(&adapter->fdir_perfect_lock);
4274}
4275
9a799d71
AK		 4276void ixgbe_down(struct ixgbe_adapter *adapter)
4277{
4278 struct net_device *netdev = adapter->netdev;
7f821875 4279 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4280 u32 rxctrl;
bf29ee6c 4281 int i;
9a799d71
AK		 4282
4283 /* signal that we are down to the interrupt handler */
4284 set_bit(__IXGBE_DOWN, &adapter->state);
4285
4286 /* disable receives */
7f821875
JB		 4287 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4288 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4289
2d39d576
YZ		 4290 /* disable all enabled rx queues */
4291 for (i = 0; i < adapter->num_rx_queues; i++)
4292 /* this call also flushes the previous write */
4293 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4294
032b4325 4295 usleep_range(10000, 20000);
9a799d71 4296
7f821875
JB		 4297 netif_tx_stop_all_queues(netdev);
4298
7086400d 4299 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4300 netif_carrier_off(netdev);
4301 netif_tx_disable(netdev);
4302
4303 ixgbe_irq_disable(adapter);
4304
4305 ixgbe_napi_disable_all(adapter);
4306
d034acf1
AD		 4307 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4308 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4309 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4310
4311 del_timer_sync(&adapter->service_timer);
4312
34cecbbf 4313 if (adapter->num_vfs) {
8e34d1aa
AD		 4314 /* Clear EITR Select mapping */
4315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4316
4317 /* Mark all the VFs as inactive */
4318 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4319 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4320
34cecbbf
AD		 4321 /* ping all the active vfs to let them know we are going down */
4322 ixgbe_ping_all_vfs(adapter);
4323
4324 /* Disable all VFTE/VFRE TX/RX */
4325 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4326 }
4327
7f821875
JB		 4328 /* disable transmits in the hardware now that interrupts are off */
4329 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4330 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4331 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4332 }
34cecbbf
AD		 4333
4334 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4335 switch (hw->mac.type) {
4336 case ixgbe_mac_82599EB:
b93a2226 4337 case ixgbe_mac_X540:
88512539 4338 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4339 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4340 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4341 break;
4342 default:
4343 break;
4344 }
7f821875 4345
6f4a0e45
PL		 4346 if (!pci_channel_offline(adapter->pdev))
4347 ixgbe_reset(adapter);
c6ecf39a
DS		 4348
4349 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4350 if (hw->mac.ops.disable_tx_laser &&
4351 ((hw->phy.multispeed_fiber) ||
9f911707 4352 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4353 (hw->mac.type == ixgbe_mac_82599EB))))
4354 hw->mac.ops.disable_tx_laser(hw);
4355
9a799d71
AK		 4356 ixgbe_clean_all_tx_rings(adapter);
4357 ixgbe_clean_all_rx_rings(adapter);
4358
5dd2d332 4359#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4360 /* since we reset the hardware DCA settings were cleared */
e35ec126 4361 ixgbe_setup_dca(adapter);
96b0e0f6 4362#endif
9a799d71
AK		 4363}
4364
9a799d71
AK		 4365/**
4366 * ixgbe_tx_timeout - Respond to a Tx Hang
4367 * @netdev: network interface device structure
4368 **/
4369static void ixgbe_tx_timeout(struct net_device *netdev)
4370{
4371 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4372
4373 /* Do the reset outside of interrupt context */
c83c6cbd 4374 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4375}
4376
9a799d71
AK		 4377/**
4378 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4379 * @adapter: board private structure to initialize
4380 *
4381 * ixgbe_sw_init initializes the Adapter private data structure.
4382 * Fields are initialized based on PCI device information and
4383 * OS network device settings (MTU size).
4384 **/
4385static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4386{
4387 struct ixgbe_hw *hw = &adapter->hw;
4388 struct pci_dev *pdev = adapter->pdev;
021230d4 4389 unsigned int rss;
7a6b6f51 4390#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4391 int j;
4392 struct tc_configuration *tc;
4393#endif
021230d4 4394
c44ade9e
JB		 4395 /* PCI config space info */
4396
4397 hw->vendor_id = pdev->vendor;
4398 hw->device_id = pdev->device;
4399 hw->revision_id = pdev->revision;
4400 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4401 hw->subsystem_device_id = pdev->subsystem_device;
4402
021230d4 4403 /* Set capability flags */
3ed69d7e 4404 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4405 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4406 switch (hw->mac.type) {
4407 case ixgbe_mac_82598EB:
bf069c97
DS		 4408 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4409 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4410 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4411 break;
b93a2226 4412 case ixgbe_mac_X540:
4f51bf70
JK		 4413 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4414 case ixgbe_mac_82599EB:
49c7ffbe 4415 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4416 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4417 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4418 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4419 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4420 /* Flow Director hash filters enabled */
4421 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4422 adapter->atr_sample_rate = 20;
c087663e 4423 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4424 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4425 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4426#ifdef IXGBE_FCOE
0d551589
YZ		 4427 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4428 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4429#ifdef CONFIG_IXGBE_DCB
6ee16520 4430 /* Default traffic class to use for FCoE */
56075a98 4431 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4432#endif
eacd73f7 4433#endif /* IXGBE_FCOE */
bd508178
AD		 4434 break;
4435 default:
4436 break;
f8212f97 4437 }
2f90b865 4438
1fc5f038
AD		 4439 /* n-tuple support exists, always init our spinlock */
4440 spin_lock_init(&adapter->fdir_perfect_lock);
4441
7a6b6f51 4442#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4443 switch (hw->mac.type) {
4444 case ixgbe_mac_X540:
4445 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4446 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4447 break;
4448 default:
4449 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4450 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4451 break;
4452 }
4453
2f90b865
AD		 4454 /* Configure DCB traffic classes */
4455 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4456 tc = &adapter->dcb_cfg.tc_config[j];
4457 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4458 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4459 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4460 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4461 tc->dcb_pfc = pfc_disabled;
4462 }
4de2a022
JF		 4463
4464 /* Initialize default user to priority mapping, UPx->TC0 */
4465 tc = &adapter->dcb_cfg.tc_config[0];
4466 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4467 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4468
2f90b865
AD		 4469 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4470 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4471 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4472 adapter->dcb_set_bitmap = 0x00;
3032309b 4473 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4474 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4475 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4476
4477#endif
9a799d71
AK		 4478
4479 /* default flow control settings */
cd7664f6 4480 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4481 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4482 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4483 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4484 hw->fc.send_xon = true;
71fd570b 4485 hw->fc.disable_fc_autoneg = false;
9a799d71 4486
30efa5a3 4487 /* enable itr by default in dynamic mode */
f7554a2b 4488 adapter->rx_itr_setting = 1;
f7554a2b 4489 adapter->tx_itr_setting = 1;
30efa5a3 4490
30efa5a3
JB		 4491 /* set default ring sizes */
4492 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4493 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4494
bd198058 4495 /* set default work limits */
59224555 4496 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4497
9a799d71 4498 /* initialize eeprom parameters */
c44ade9e 4499 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4500 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4501 return -EIO;
4502 }
4503
9a799d71
AK		 4504 set_bit(__IXGBE_DOWN, &adapter->state);
4505
4506 return 0;
4507}
4508
4509/**
4510 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4511 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4512 *
4513 * Return 0 on success, negative on failure
4514 **/
b6ec895e 4515int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4516{
b6ec895e 4517 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4518 int orig_node = dev_to_node(dev);
4519 int numa_node = -1;
9a799d71
AK		 4520 int size;
4521
3a581073 4522 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4523
4524 if (tx_ring->q_vector)
4525 numa_node = tx_ring->q_vector->numa_node;
4526
4527 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4528 if (!tx_ring->tx_buffer_info)
89bf67f1 4529 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4530 if (!tx_ring->tx_buffer_info)
4531 goto err;
9a799d71
AK		 4532
4533 /* round up to nearest 4K */
12207e49 4534 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4535 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4536
de88eeeb
AD		 4537 set_dev_node(dev, numa_node);
4538 tx_ring->desc = dma_alloc_coherent(dev,
4539 tx_ring->size,
4540 &tx_ring->dma,
4541 GFP_KERNEL);
4542 set_dev_node(dev, orig_node);
4543 if (!tx_ring->desc)
4544 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4545 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4546 if (!tx_ring->desc)
4547 goto err;
9a799d71 4548
3a581073
JB		 4549 tx_ring->next_to_use = 0;
4550 tx_ring->next_to_clean = 0;
9a799d71 4551 return 0;
e01c31a5
JB		 4552
4553err:
4554 vfree(tx_ring->tx_buffer_info);
4555 tx_ring->tx_buffer_info = NULL;
b6ec895e 4556 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4557 return -ENOMEM;
9a799d71
AK		 4558}
4559
69888674
AD		 4560/**
4561 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4562 * @adapter: board private structure
4563 *
4564 * If this function returns with an error, then it's possible one or
4565 * more of the rings is populated (while the rest are not). It is the
4566 * callers duty to clean those orphaned rings.
4567 *
4568 * Return 0 on success, negative on failure
4569 **/
4570static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4571{
4572 int i, err = 0;
4573
4574 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4575 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4576 if (!err)
4577 continue;
de3d5b94 4578
396e799c 4579 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4580 goto err_setup_tx;
69888674
AD		 4581 }
4582
de3d5b94
AD		 4583 return 0;
4584err_setup_tx:
4585 /* rewind the index freeing the rings as we go */
4586 while (i--)
4587 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4588 return err;
4589}
4590
9a799d71
AK		 4591/**
4592 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4593 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4594 *
4595 * Returns 0 on success, negative on failure
4596 **/
b6ec895e 4597int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4598{
b6ec895e 4599 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4600 int orig_node = dev_to_node(dev);
4601 int numa_node = -1;
021230d4 4602 int size;
9a799d71 4603
3a581073 4604 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4605
4606 if (rx_ring->q_vector)
4607 numa_node = rx_ring->q_vector->numa_node;
4608
4609 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4610 if (!rx_ring->rx_buffer_info)
89bf67f1 4611 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4612 if (!rx_ring->rx_buffer_info)
4613 goto err;
9a799d71 4614
9a799d71 4615 /* Round up to nearest 4K */
3a581073
JB		 4616 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4617 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4618
de88eeeb
AD		 4619 set_dev_node(dev, numa_node);
4620 rx_ring->desc = dma_alloc_coherent(dev,
4621 rx_ring->size,
4622 &rx_ring->dma,
4623 GFP_KERNEL);
4624 set_dev_node(dev, orig_node);
4625 if (!rx_ring->desc)
4626 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4627 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4628 if (!rx_ring->desc)
4629 goto err;
9a799d71 4630
3a581073
JB		 4631 rx_ring->next_to_clean = 0;
4632 rx_ring->next_to_use = 0;
9a799d71 4633
f800326d
AD		 4634 ixgbe_init_rx_page_offset(rx_ring);
4635
9a799d71 4636 return 0;
b6ec895e
AD		 4637err:
4638 vfree(rx_ring->rx_buffer_info);
4639 rx_ring->rx_buffer_info = NULL;
4640 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4641 return -ENOMEM;
9a799d71
AK		 4642}
4643
69888674
AD		 4644/**
4645 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4646 * @adapter: board private structure
4647 *
4648 * If this function returns with an error, then it's possible one or
4649 * more of the rings is populated (while the rest are not). It is the
4650 * callers duty to clean those orphaned rings.
4651 *
4652 * Return 0 on success, negative on failure
4653 **/
69888674
AD		 4654static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4655{
4656 int i, err = 0;
4657
4658 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4659 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4660 if (!err)
4661 continue;
de3d5b94 4662
396e799c 4663 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4664 goto err_setup_rx;
69888674
AD		 4665 }
4666
de3d5b94
AD		 4667 return 0;
4668err_setup_rx:
4669 /* rewind the index freeing the rings as we go */
4670 while (i--)
4671 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4672 return err;
4673}
4674
9a799d71
AK		 4675/**
4676 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4677 * @tx_ring: Tx descriptor ring for a specific queue
4678 *
4679 * Free all transmit software resources
4680 **/
b6ec895e 4681void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4682{
b6ec895e 4683 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4684
4685 vfree(tx_ring->tx_buffer_info);
4686 tx_ring->tx_buffer_info = NULL;
4687
b6ec895e
AD		 4688 /* if not set, then don't free */
4689 if (!tx_ring->desc)
4690 return;
4691
4692 dma_free_coherent(tx_ring->dev, tx_ring->size,
4693 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4694
4695 tx_ring->desc = NULL;
4696}
4697
4698/**
4699 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4700 * @adapter: board private structure
4701 *
4702 * Free all transmit software resources
4703 **/
4704static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4705{
4706 int i;
4707
4708 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4709 if (adapter->tx_ring[i]->desc)
b6ec895e 4710 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4711}
4712
4713/**
b4617240 4714 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4715 * @rx_ring: ring to clean the resources from
4716 *
4717 * Free all receive software resources
4718 **/
b6ec895e 4719void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4720{
b6ec895e 4721 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4722
4723 vfree(rx_ring->rx_buffer_info);
4724 rx_ring->rx_buffer_info = NULL;
4725
b6ec895e
AD		 4726 /* if not set, then don't free */
4727 if (!rx_ring->desc)
4728 return;
4729
4730 dma_free_coherent(rx_ring->dev, rx_ring->size,
4731 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4732
4733 rx_ring->desc = NULL;
4734}
4735
4736/**
4737 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4738 * @adapter: board private structure
4739 *
4740 * Free all receive software resources
4741 **/
4742static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4743{
4744 int i;
4745
4746 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4747 if (adapter->rx_ring[i]->desc)
b6ec895e 4748 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4749}
4750
9a799d71
AK		 4751/**
4752 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4753 * @netdev: network interface device structure
4754 * @new_mtu: new value for maximum frame size
4755 *
4756 * Returns 0 on success, negative on failure
4757 **/
4758static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4759{
4760 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4761 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4762
42c783c5 4763 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4764 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4765 return -EINVAL;
4766
4767 /*
4768 * For 82599EB we cannot allow PF to change MTU greater than 1500
4769 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4770 * don't allocate and chain buffers correctly.
4771 */
4772 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4773 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4774 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4775 return -EINVAL;
9a799d71 4776
396e799c 4777 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4778
021230d4 4779 /* must set new MTU before calling down or up */
9a799d71
AK		 4780 netdev->mtu = new_mtu;
4781
d4f80882
AV		 4782 if (netif_running(netdev))
4783 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4784
4785 return 0;
4786}
4787
4788/**
4789 * ixgbe_open - Called when a network interface is made active
4790 * @netdev: network interface device structure
4791 *
4792 * Returns 0 on success, negative value on failure
4793 *
4794 * The open entry point is called when a network interface is made
4795 * active by the system (IFF_UP). At this point all resources needed
4796 * for transmit and receive operations are allocated, the interrupt
4797 * handler is registered with the OS, the watchdog timer is started,
4798 * and the stack is notified that the interface is ready.
4799 **/
4800static int ixgbe_open(struct net_device *netdev)
4801{
4802 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4803 int err;
4bebfaa5
AK		 4804
4805 /* disallow open during test */
4806 if (test_bit(__IXGBE_TESTING, &adapter->state))
4807 return -EBUSY;
9a799d71 4808
54386467
JB		 4809 netif_carrier_off(netdev);
4810
9a799d71
AK		 4811 /* allocate transmit descriptors */
4812 err = ixgbe_setup_all_tx_resources(adapter);
4813 if (err)
4814 goto err_setup_tx;
4815
9a799d71
AK		 4816 /* allocate receive descriptors */
4817 err = ixgbe_setup_all_rx_resources(adapter);
4818 if (err)
4819 goto err_setup_rx;
4820
4821 ixgbe_configure(adapter);
4822
021230d4 4823 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4824 if (err)
4825 goto err_req_irq;
4826
ac802f5d
AD		 4827 /* Notify the stack of the actual queue counts. */
4828 err = netif_set_real_num_tx_queues(netdev,
4829 adapter->num_rx_pools > 1 ? 1 :
4830 adapter->num_tx_queues);
4831 if (err)
4832 goto err_set_queues;
4833
4834
4835 err = netif_set_real_num_rx_queues(netdev,
4836 adapter->num_rx_pools > 1 ? 1 :
4837 adapter->num_rx_queues);
4838 if (err)
4839 goto err_set_queues;
4840
c7ccde0f 4841 ixgbe_up_complete(adapter);
9a799d71
AK		 4842
4843 return 0;
4844
ac802f5d
AD		 4845err_set_queues:
4846 ixgbe_free_irq(adapter);
9a799d71 4847err_req_irq:
a20a1199 4848 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4849err_setup_rx:
a20a1199 4850 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4851err_setup_tx:
9a799d71
AK		 4852 ixgbe_reset(adapter);
4853
4854 return err;
4855}
4856
4857/**
4858 * ixgbe_close - Disables a network interface
4859 * @netdev: network interface device structure
4860 *
4861 * Returns 0, this is not allowed to fail
4862 *
4863 * The close entry point is called when an interface is de-activated
4864 * by the OS. The hardware is still under the drivers control, but
4865 * needs to be disabled. A global MAC reset is issued to stop the
4866 * hardware, and all transmit and receive resources are freed.
4867 **/
4868static int ixgbe_close(struct net_device *netdev)
4869{
4870 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4871
4872 ixgbe_down(adapter);
4873 ixgbe_free_irq(adapter);
4874
e4911d57
AD		 4875 ixgbe_fdir_filter_exit(adapter);
4876
9a799d71
AK		 4877 ixgbe_free_all_tx_resources(adapter);
4878 ixgbe_free_all_rx_resources(adapter);
4879
5eba3699 4880 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4881
4882 return 0;
4883}
4884
b3c8b4ba
AD		 4885#ifdef CONFIG_PM
4886static int ixgbe_resume(struct pci_dev *pdev)
4887{
c60fbb00
AD		 4888 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4889 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4890 u32 err;
4891
4892 pci_set_power_state(pdev, PCI_D0);
4893 pci_restore_state(pdev);
656ab817
DS		 4894 /*
4895 * pci_restore_state clears dev->state_saved so call
4896 * pci_save_state to restore it.
4897 */
4898 pci_save_state(pdev);
9ce77666 4899
4900 err = pci_enable_device_mem(pdev);
b3c8b4ba 4901 if (err) {
849c4542 4902 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4903 return err;
4904 }
4905 pci_set_master(pdev);
4906
dd4d8ca6 4907 pci_wake_from_d3(pdev, false);
b3c8b4ba 4908
b3c8b4ba
AD		 4909 ixgbe_reset(adapter);
4910
495dce12
WJP		 4911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4912
ac802f5d
AD		 4913 rtnl_lock();
4914 err = ixgbe_init_interrupt_scheme(adapter);
4915 if (!err && netif_running(netdev))
c60fbb00 4916 err = ixgbe_open(netdev);
ac802f5d
AD		 4917
4918 rtnl_unlock();
4919
4920 if (err)
4921 return err;
b3c8b4ba
AD		 4922
4923 netif_device_attach(netdev);
4924
4925 return 0;
4926}
b3c8b4ba 4927#endif /* CONFIG_PM */
9d8d05ae
RW		 4928
4929static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4930{
c60fbb00
AD		 4931 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4932 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4933 struct ixgbe_hw *hw = &adapter->hw;
4934 u32 ctrl, fctrl;
4935 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4936#ifdef CONFIG_PM
4937 int retval = 0;
4938#endif
4939
4940 netif_device_detach(netdev);
4941
4942 if (netif_running(netdev)) {
ab6039a7 4943 rtnl_lock();
b3c8b4ba
AD		 4944 ixgbe_down(adapter);
4945 ixgbe_free_irq(adapter);
4946 ixgbe_free_all_tx_resources(adapter);
4947 ixgbe_free_all_rx_resources(adapter);
ab6039a7 4948 rtnl_unlock();
b3c8b4ba 4949 }
b3c8b4ba 4950
5f5ae6fc
AD		 4951 ixgbe_clear_interrupt_scheme(adapter);
4952
b3c8b4ba
AD		 4953#ifdef CONFIG_PM
4954 retval = pci_save_state(pdev);
4955 if (retval)
4956 return retval;
4df10466 4957
b3c8b4ba 4958#endif
e8e26350
PW		 4959 if (wufc) {
4960 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4961
c509e754
DS		 4962 /*
4963 * enable the optics for both mult-speed fiber and
4964 * 82599 SFP+ fiber as we can WoL.
4965 */
4966 if (hw->mac.ops.enable_tx_laser &&
4967 (hw->phy.multispeed_fiber ||
4968 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4969 hw->mac.type == ixgbe_mac_82599EB)))
4970 hw->mac.ops.enable_tx_laser(hw);
4971
e8e26350
PW		 4972 /* turn on all-multi mode if wake on multicast is enabled */
4973 if (wufc & IXGBE_WUFC_MC) {
4974 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4975 fctrl |= IXGBE_FCTRL_MPE;
4976 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4977 }
4978
4979 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4980 ctrl |= IXGBE_CTRL_GIO_DIS;
4981 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4982
4983 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4984 } else {
4985 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4986 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4987 }
4988
bd508178
AD		 4989 switch (hw->mac.type) {
4990 case ixgbe_mac_82598EB:
dd4d8ca6 4991 pci_wake_from_d3(pdev, false);
bd508178
AD		 4992 break;
4993 case ixgbe_mac_82599EB:
b93a2226 4994 case ixgbe_mac_X540:
bd508178
AD		 4995 pci_wake_from_d3(pdev, !!wufc);
4996 break;
4997 default:
4998 break;
4999 }
b3c8b4ba 5000
9d8d05ae
RW		 5001 *enable_wake = !!wufc;
5002
b3c8b4ba
AD		 5003 ixgbe_release_hw_control(adapter);
5004
5005 pci_disable_device(pdev);
5006
9d8d05ae
RW		 5007 return 0;
5008}
5009
5010#ifdef CONFIG_PM
5011static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5012{
5013 int retval;
5014 bool wake;
5015
5016 retval = __ixgbe_shutdown(pdev, &wake);
5017 if (retval)
5018 return retval;
5019
5020 if (wake) {
5021 pci_prepare_to_sleep(pdev);
5022 } else {
5023 pci_wake_from_d3(pdev, false);
5024 pci_set_power_state(pdev, PCI_D3hot);
5025 }
b3c8b4ba
AD		 5026
5027 return 0;
5028}
9d8d05ae 5029#endif /* CONFIG_PM */
b3c8b4ba
AD		 5030
5031static void ixgbe_shutdown(struct pci_dev *pdev)
5032{
9d8d05ae
RW		 5033 bool wake;
5034
5035 __ixgbe_shutdown(pdev, &wake);
5036
5037 if (system_state == SYSTEM_POWER_OFF) {
5038 pci_wake_from_d3(pdev, wake);
5039 pci_set_power_state(pdev, PCI_D3hot);
5040 }
b3c8b4ba
AD		 5041}
5042
9a799d71
AK		 5043/**
5044 * ixgbe_update_stats - Update the board statistics counters.
5045 * @adapter: board private structure
5046 **/
5047void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5048{
2d86f139 5049 struct net_device *netdev = adapter->netdev;
9a799d71 5050 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5051 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5052 u64 total_mpc = 0;
5053 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5054 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5055 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5056 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5057#ifdef IXGBE_FCOE
5058 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5059 unsigned int cpu;
5060 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5061#endif /* IXGBE_FCOE */
9a799d71 5062
d08935c2
DS		 5063 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5064 test_bit(__IXGBE_RESETTING, &adapter->state))
5065 return;
5066
94b982b2 5067 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5068 u64 rsc_count = 0;
94b982b2 5069 u64 rsc_flush = 0;
94b982b2 5070 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5071 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5072 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5073 }
5074 adapter->rsc_total_count = rsc_count;
5075 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5076 }
5077
5b7da515
AD		 5078 for (i = 0; i < adapter->num_rx_queues; i++) {
5079 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5080 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5081 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5082 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5083 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5084 bytes += rx_ring->stats.bytes;
5085 packets += rx_ring->stats.packets;
5086 }
5087 adapter->non_eop_descs = non_eop_descs;
5088 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5089 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5090 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5091 netdev->stats.rx_bytes = bytes;
5092 netdev->stats.rx_packets = packets;
5093
5094 bytes = 0;
5095 packets = 0;
7ca3bc58 5096 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5097 for (i = 0; i < adapter->num_tx_queues; i++) {
5098 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5099 restart_queue += tx_ring->tx_stats.restart_queue;
5100 tx_busy += tx_ring->tx_stats.tx_busy;
5101 bytes += tx_ring->stats.bytes;
5102 packets += tx_ring->stats.packets;
5103 }
eb985f09 5104 adapter->restart_queue = restart_queue;
5b7da515
AD		 5105 adapter->tx_busy = tx_busy;
5106 netdev->stats.tx_bytes = bytes;
5107 netdev->stats.tx_packets = packets;
7ca3bc58 5108
7ca647bd 5109 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5110
5111 /* 8 register reads */
6f11eef7
AV		 5112 for (i = 0; i < 8; i++) {
5113 /* for packet buffers not used, the register should read 0 */
5114 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5115 missed_rx += mpc;
7ca647bd
JP		 5116 hwstats->mpc[i] += mpc;
5117 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5118 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5119 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5120 switch (hw->mac.type) {
5121 case ixgbe_mac_82598EB:
1a70db4b
ET		 5122 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5123 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5124 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5125 hwstats->pxonrxc[i] +=
5126 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5127 break;
5128 case ixgbe_mac_82599EB:
b93a2226 5129 case ixgbe_mac_X540:
bd508178
AD		 5130 hwstats->pxonrxc[i] +=
5131 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5132 break;
5133 default:
5134 break;
e8e26350 5135 }
6f11eef7 5136 }
1a70db4b
ET		 5137
5138 /*16 register reads */
5139 for (i = 0; i < 16; i++) {
5140 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5141 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5142 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5143 (hw->mac.type == ixgbe_mac_X540)) {
5144 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5145 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5146 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5147 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5148 }
5149 }
5150
7ca647bd 5151 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5152 /* work around hardware counting issue */
7ca647bd 5153 hwstats->gprc -= missed_rx;
6f11eef7 5154
c84d324c
JF		 5155 ixgbe_update_xoff_received(adapter);
5156
6f11eef7 5157 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5158 switch (hw->mac.type) {
5159 case ixgbe_mac_82598EB:
5160 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5161 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5162 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5163 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5164 break;
b93a2226 5165 case ixgbe_mac_X540:
58f6bcf9
ET		 5166 /* OS2BMC stats are X540 only*/
5167 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5168 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5169 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5170 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5171 case ixgbe_mac_82599EB:
a4d4f629
AD		 5172 for (i = 0; i < 16; i++)
5173 adapter->hw_rx_no_dma_resources +=
5174 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5175 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5176 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5177 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5178 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5179 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5180 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5181 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5182 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5183 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5184#ifdef IXGBE_FCOE
7ca647bd
JP		 5185 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5186 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5187 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5188 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5189 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5190 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5191 /* Add up per cpu counters for total ddp aloc fail */
5192 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5193 for_each_possible_cpu(cpu) {
5194 fcoe_noddp_counts_sum +=
5195 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5196 fcoe_noddp_ext_buff_counts_sum +=
5197 *per_cpu_ptr(fcoe->
5198 pcpu_noddp_ext_buff, cpu);
5199 }
5200 }
5201 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5202 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5203#endif /* IXGBE_FCOE */
bd508178
AD		 5204 break;
5205 default:
5206 break;
e8e26350 5207 }
9a799d71 5208 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5209 hwstats->bprc += bprc;
5210 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5211 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5212 hwstats->mprc -= bprc;
5213 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5214 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5215 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5216 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5217 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5218 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5219 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5220 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5221 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5222 hwstats->lxontxc += lxon;
6f11eef7 5223 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5224 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5225 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5226 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5227 /*
5228 * 82598 errata - tx of flow control packets is included in tx counters
5229 */
5230 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5231 hwstats->gptc -= xon_off_tot;
5232 hwstats->mptc -= xon_off_tot;
5233 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5234 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5235 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5236 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5237 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5238 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5239 hwstats->ptc64 -= xon_off_tot;
5240 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5241 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5242 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5243 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5244 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5245 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5246
5247 /* Fill out the OS statistics structure */
7ca647bd 5248 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5249
5250 /* Rx Errors */
7ca647bd 5251 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5252 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5253 netdev->stats.rx_length_errors = hwstats->rlec;
5254 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5255 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5256}
5257
5258/**
d034acf1 5259 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5260 * @adapter: pointer to the device adapter structure
9a799d71 5261 **/
d034acf1 5262static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5263{
cf8280ee 5264 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5265 int i;
cf8280ee 5266
d034acf1
AD		 5267 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5268 return;
5269
5270 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5271
d034acf1 5272 /* if interface is down do nothing */
fe49f04a 5273 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5274 return;
5275
5276 /* do nothing if we are not using signature filters */
5277 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5278 return;
5279
5280 adapter->fdir_overflow++;
5281
93c52dd0
AD		 5282 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5283 for (i = 0; i < adapter->num_tx_queues; i++)
5284 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5285 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5286 /* re-enable flow director interrupts */
5287 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5288 } else {
5289 e_err(probe, "failed to finish FDIR re-initialization, "
5290 "ignored adding FDIR ATR filters\n");
5291 }
93c52dd0
AD		 5292}
5293
5294/**
5295 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5296 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5297 *
5298 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5299 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5300 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5301 * determine if a hang has occurred.
93c52dd0
AD		 5302 */
5303static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5304{
cf8280ee 5305 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5306 u64 eics = 0;
5307 int i;
cf8280ee 5308
93c52dd0
AD		 5309 /* If we're down or resetting, just bail */
5310 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5311 test_bit(__IXGBE_RESETTING, &adapter->state))
5312 return;
22d5a71b 5313
93c52dd0
AD		 5314 /* Force detection of hung controller */
5315 if (netif_carrier_ok(adapter->netdev)) {
5316 for (i = 0; i < adapter->num_tx_queues; i++)
5317 set_check_for_tx_hang(adapter->tx_ring[i]);
5318 }
22d5a71b 5319
fe49f04a
AD		 5320 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5321 /*
5322 * for legacy and MSI interrupts don't set any bits
5323 * that are enabled for EIAM, because this operation
5324 * would set *both* EIMS and EICS for any bit in EIAM
5325 */
5326 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5327 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5328 } else {
5329 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5330 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5331 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5332 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5333 eics |= ((u64)1 << i);
5334 }
cf8280ee 5335 }
9a799d71 5336
93c52dd0 5337 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5338 ixgbe_irq_rearm_queues(adapter, eics);
5339
cf8280ee
JB		 5340}
5341
e8e26350 5342/**
93c52dd0 5343 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5344 * @adapter: pointer to the device adapter structure
5345 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5346 **/
93c52dd0 5347static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5348{
e8e26350 5349 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5350 u32 link_speed = adapter->link_speed;
5351 bool link_up = adapter->link_up;
041441d0 5352 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5353
93c52dd0
AD		 5354 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5355 return;
5356
5357 if (hw->mac.ops.check_link) {
5358 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5359 } else {
93c52dd0
AD		 5360 /* always assume link is up, if no check link function */
5361 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5362 link_up = true;
c4cf55e5 5363 }
041441d0
AD		 5364
5365 if (adapter->ixgbe_ieee_pfc)
5366 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5367
3ebe8fde 5368 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5369 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5370 ixgbe_set_rx_drop_en(adapter);
5371 }
93c52dd0
AD		 5372
5373 if (link_up ||
5374 time_after(jiffies, (adapter->link_check_timeout +
5375 IXGBE_TRY_LINK_TIMEOUT))) {
5376 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5377 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5378 IXGBE_WRITE_FLUSH(hw);
5379 }
5380
5381 adapter->link_up = link_up;
5382 adapter->link_speed = link_speed;
e8e26350
PW		 5383}
5384
5385/**
93c52dd0
AD		 5386 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5387 * print link up message
49ce9c2c 5388 * @adapter: pointer to the device adapter structure
e8e26350 5389 **/
93c52dd0 5390static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5391{
93c52dd0 5392 struct net_device *netdev = adapter->netdev;
e8e26350 5393 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5394 u32 link_speed = adapter->link_speed;
5395 bool flow_rx, flow_tx;
e8e26350 5396
93c52dd0
AD		 5397 /* only continue if link was previously down */
5398 if (netif_carrier_ok(netdev))
a985b6c3 5399 return;
63d6e1d8 5400
93c52dd0 5401 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5402
93c52dd0
AD		 5403 switch (hw->mac.type) {
5404 case ixgbe_mac_82598EB: {
5405 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5406 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5407 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5408 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5409 }
5410 break;
5411 case ixgbe_mac_X540:
5412 case ixgbe_mac_82599EB: {
5413 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5414 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5415 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5416 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5417 }
5418 break;
5419 default:
5420 flow_tx = false;
5421 flow_rx = false;
5422 break;
e8e26350 5423 }
3a6a4eda
JK		 5424
5425#ifdef CONFIG_IXGBE_PTP
5426 ixgbe_ptp_start_cyclecounter(adapter);
5427#endif
5428
93c52dd0
AD		 5429 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5430 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5431 "10 Gbps" :
5432 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5433 "1 Gbps" :
5434 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5435 "100 Mbps" :
5436 "unknown speed"))),
5437 ((flow_rx && flow_tx) ? "RX/TX" :
5438 (flow_rx ? "RX" :
5439 (flow_tx ? "TX" : "None"))));
e8e26350 5440
93c52dd0 5441 netif_carrier_on(netdev);
93c52dd0 5442 ixgbe_check_vf_rate_limit(adapter);
befa2af7
AD		 5443
5444 /* ping all the active vfs to let them know link has changed */
5445 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5446}
5447
c4cf55e5 5448/**
93c52dd0
AD		 5449 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5450 * print link down message
49ce9c2c 5451 * @adapter: pointer to the adapter structure
c4cf55e5 5452 **/
581330ba 5453static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5454{
cf8280ee 5455 struct net_device *netdev = adapter->netdev;
c4cf55e5 5456 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5457
93c52dd0
AD		 5458 adapter->link_up = false;
5459 adapter->link_speed = 0;
cf8280ee 5460
93c52dd0
AD		 5461 /* only continue if link was up previously */
5462 if (!netif_carrier_ok(netdev))
5463 return;
264857b8 5464
93c52dd0
AD		 5465 /* poll for SFP+ cable when link is down */
5466 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5467 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5468
3a6a4eda
JK		 5469#ifdef CONFIG_IXGBE_PTP
5470 ixgbe_ptp_start_cyclecounter(adapter);
5471#endif
5472
93c52dd0
AD		 5473 e_info(drv, "NIC Link is Down\n");
5474 netif_carrier_off(netdev);
befa2af7
AD		 5475
5476 /* ping all the active vfs to let them know link has changed */
5477 ixgbe_ping_all_vfs(adapter);
93c52dd0 5478}
e8e26350 5479
93c52dd0
AD		 5480/**
5481 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5482 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5483 **/
5484static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5485{
c4cf55e5 5486 int i;
93c52dd0 5487 int some_tx_pending = 0;
c4cf55e5 5488
93c52dd0 5489 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5490 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5491 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5492 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5493 some_tx_pending = 1;
5494 break;
5495 }
5496 }
5497
5498 if (some_tx_pending) {
5499 /* We've lost link, so the controller stops DMA,
5500 * but we've got queued Tx work that's never going
5501 * to get done, so reset controller to flush Tx.
5502 * (Do the reset outside of interrupt context).
5503 */
c83c6cbd 5504 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5505 }
c4cf55e5 5506 }
c4cf55e5
PWJ		 5507}
5508
a985b6c3
GR		 5509static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5510{
5511 u32 ssvpc;
5512
5513 /* Do not perform spoof check for 82598 */
5514 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5515 return;
5516
5517 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5518
5519 /*
5520 * ssvpc register is cleared on read, if zero then no
5521 * spoofed packets in the last interval.
5522 */
5523 if (!ssvpc)
5524 return;
5525
5526 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5527}
5528
93c52dd0
AD		 5529/**
5530 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5531 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5532 **/
5533static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5534{
5535 /* if interface is down do nothing */
7edebf9a
ET		 5536 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5537 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5538 return;
5539
5540 ixgbe_watchdog_update_link(adapter);
5541
5542 if (adapter->link_up)
5543 ixgbe_watchdog_link_is_up(adapter);
5544 else
5545 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5546
a985b6c3 5547 ixgbe_spoof_check(adapter);
9a799d71 5548 ixgbe_update_stats(adapter);
93c52dd0
AD		 5549
5550 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5551}
10eec955 5552
cf8280ee 5553/**
7086400d 5554 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5555 * @adapter: the ixgbe adapter structure
cf8280ee 5556 **/
7086400d 5557static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5558{
cf8280ee 5559 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5560 s32 err;
cf8280ee 5561
7086400d
AD		 5562 /* not searching for SFP so there is nothing to do here */
5563 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5564 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5565 return;
10eec955 5566
7086400d
AD		 5567 /* someone else is in init, wait until next service event */
5568 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5569 return;
cf8280ee 5570
7086400d
AD		 5571 err = hw->phy.ops.identify_sfp(hw);
5572 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5573 goto sfp_out;
264857b8 5574
7086400d
AD		 5575 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5576 /* If no cable is present, then we need to reset
5577 * the next time we find a good cable. */
5578 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5579 }
9a799d71 5580
7086400d
AD		 5581 /* exit on error */
5582 if (err)
5583 goto sfp_out;
e8e26350 5584
7086400d
AD		 5585 /* exit if reset not needed */
5586 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5587 goto sfp_out;
9a799d71 5588
7086400d 5589 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5590
7086400d
AD		 5591 /*
5592 * A module may be identified correctly, but the EEPROM may not have
5593 * support for that module. setup_sfp() will fail in that case, so
5594 * we should not allow that module to load.
5595 */
5596 if (hw->mac.type == ixgbe_mac_82598EB)
5597 err = hw->phy.ops.reset(hw);
5598 else
5599 err = hw->mac.ops.setup_sfp(hw);
5600
5601 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5602 goto sfp_out;
5603
5604 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5605 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5606
5607sfp_out:
5608 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5609
5610 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5611 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5612 e_dev_err("failed to initialize because an unsupported "
5613 "SFP+ module type was detected.\n");
5614 e_dev_err("Reload the driver after installing a "
5615 "supported module.\n");
5616 unregister_netdev(adapter->netdev);
bc59fcda 5617 }
7086400d 5618}
bc59fcda 5619
7086400d
AD		 5620/**
5621 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5622 * @adapter: the ixgbe adapter structure
7086400d
AD		 5623 **/
5624static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5625{
5626 struct ixgbe_hw *hw = &adapter->hw;
5627 u32 autoneg;
5628 bool negotiation;
5629
5630 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5631 return;
5632
5633 /* someone else is in init, wait until next service event */
5634 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5635 return;
5636
5637 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5638
5639 autoneg = hw->phy.autoneg_advertised;
5640 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5641 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5642 if (hw->mac.ops.setup_link)
5643 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5644
5645 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5646 adapter->link_check_timeout = jiffies;
5647 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5648}
5649
83c61fa9
GR		 5650#ifdef CONFIG_PCI_IOV
5651static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5652{
5653 int vf;
5654 struct ixgbe_hw *hw = &adapter->hw;
5655 struct net_device *netdev = adapter->netdev;
5656 u32 gpc;
5657 u32 ciaa, ciad;
5658
5659 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5660 if (gpc) /* If incrementing then no need for the check below */
5661 return;
5662 /*
5663 * Check to see if a bad DMA write target from an errant or
5664 * malicious VF has caused a PCIe error. If so then we can
5665 * issue a VFLR to the offending VF(s) and then resume without
5666 * requesting a full slot reset.
5667 */
5668
5669 for (vf = 0; vf < adapter->num_vfs; vf++) {
5670 ciaa = (vf << 16) | 0x80000000;
5671 /* 32 bit read so align, we really want status at offset 6 */
5672 ciaa |= PCI_COMMAND;
5673 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5674 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5675 ciaa &= 0x7FFFFFFF;
5676 /* disable debug mode asap after reading data */
5677 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5678 /* Get the upper 16 bits which will be the PCI status reg */
5679 ciad >>= 16;
5680 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5681 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5682 /* Issue VFLR */
5683 ciaa = (vf << 16) | 0x80000000;
5684 ciaa |= 0xA8;
5685 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5686 ciad = 0x00008000; /* VFLR */
5687 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5688 ciaa &= 0x7FFFFFFF;
5689 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5690 }
5691 }
5692}
5693
5694#endif
7086400d
AD		 5695/**
5696 * ixgbe_service_timer - Timer Call-back
5697 * @data: pointer to adapter cast into an unsigned long
5698 **/
5699static void ixgbe_service_timer(unsigned long data)
5700{
5701 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5702 unsigned long next_event_offset;
83c61fa9 5703 bool ready = true;
7086400d 5704
6bb78cfb
AD		 5705 /* poll faster when waiting for link */
5706 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5707 next_event_offset = HZ / 10;
5708 else
5709 next_event_offset = HZ * 2;
83c61fa9 5710
6bb78cfb 5711#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5712 /*
5713 * don't bother with SR-IOV VF DMA hang check if there are
5714 * no VFs or the link is down
5715 */
5716 if (!adapter->num_vfs ||
6bb78cfb 5717 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5718 goto normal_timer_service;
83c61fa9
GR		 5719
5720 /* If we have VFs allocated then we must check for DMA hangs */
5721 ixgbe_check_for_bad_vf(adapter);
5722 next_event_offset = HZ / 50;
5723 adapter->timer_event_accumulator++;
5724
6bb78cfb 5725 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5726 adapter->timer_event_accumulator = 0;
7086400d 5727 else
6bb78cfb 5728 ready = false;
7086400d 5729
6bb78cfb 5730normal_timer_service:
83c61fa9 5731#endif
7086400d
AD		 5732 /* Reset the timer */
5733 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5734
83c61fa9
GR		 5735 if (ready)
5736 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5737}
5738
c83c6cbd
AD		 5739static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5740{
5741 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5742 return;
5743
5744 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5745
5746 /* If we're already down or resetting, just bail */
5747 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5748 test_bit(__IXGBE_RESETTING, &adapter->state))
5749 return;
5750
5751 ixgbe_dump(adapter);
5752 netdev_err(adapter->netdev, "Reset adapter\n");
5753 adapter->tx_timeout_count++;
5754
5755 ixgbe_reinit_locked(adapter);
5756}
5757
7086400d
AD		 5758/**
5759 * ixgbe_service_task - manages and runs subtasks
5760 * @work: pointer to work_struct containing our data
5761 **/
5762static void ixgbe_service_task(struct work_struct *work)
5763{
5764 struct ixgbe_adapter *adapter = container_of(work,
5765 struct ixgbe_adapter,
5766 service_task);
5767
c83c6cbd 5768 ixgbe_reset_subtask(adapter);
7086400d
AD		 5769 ixgbe_sfp_detection_subtask(adapter);
5770 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5771 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5772 ixgbe_watchdog_subtask(adapter);
d034acf1 5773 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5774 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5775#ifdef CONFIG_IXGBE_PTP
5776 ixgbe_ptp_overflow_check(adapter);
5777#endif
7086400d
AD		 5778
5779 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5780}
5781
fd0db0ed
AD		 5782static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5783 struct ixgbe_tx_buffer *first,
244e27ad 5784 u8 *hdr_len)
897ab156 5785{
fd0db0ed 5786 struct sk_buff *skb = first->skb;
897ab156
AD		 5787 u32 vlan_macip_lens, type_tucmd;
5788 u32 mss_l4len_idx, l4len;
9a799d71 5789
897ab156
AD		 5790 if (!skb_is_gso(skb))
5791 return 0;
9a799d71 5792
897ab156 5793 if (skb_header_cloned(skb)) {
244e27ad 5794 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5795 if (err)
5796 return err;
9a799d71 5797 }
9a799d71 5798
897ab156
AD		 5799 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5800 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5801
244e27ad 5802 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5803 struct iphdr *iph = ip_hdr(skb);
5804 iph->tot_len = 0;
5805 iph->check = 0;
5806 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5807 iph->daddr, 0,
5808 IPPROTO_TCP,
5809 0);
5810 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5811 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5812 IXGBE_TX_FLAGS_CSUM |
5813 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5814 } else if (skb_is_gso_v6(skb)) {
5815 ipv6_hdr(skb)->payload_len = 0;
5816 tcp_hdr(skb)->check =
5817 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5818 &ipv6_hdr(skb)->daddr,
5819 0, IPPROTO_TCP, 0);
244e27ad
AD		 5820 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5821 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5822 }
5823
091a6246 5824 /* compute header lengths */
897ab156
AD		 5825 l4len = tcp_hdrlen(skb);
5826 *hdr_len = skb_transport_offset(skb) + l4len;
5827
091a6246
AD		 5828 /* update gso size and bytecount with header size */
5829 first->gso_segs = skb_shinfo(skb)->gso_segs;
5830 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5831
897ab156
AD		 5832 /* mss_l4len_id: use 1 as index for TSO */
5833 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5834 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5835 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5836
5837 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5838 vlan_macip_lens = skb_network_header_len(skb);
5839 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5840 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5841
5842 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5843 mss_l4len_idx);
897ab156
AD		 5844
5845 return 1;
5846}
5847
244e27ad
AD		 5848static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5849 struct ixgbe_tx_buffer *first)
7ca647bd 5850{
fd0db0ed 5851 struct sk_buff *skb = first->skb;
897ab156
AD		 5852 u32 vlan_macip_lens = 0;
5853 u32 mss_l4len_idx = 0;
5854 u32 type_tucmd = 0;
7ca647bd 5855
897ab156 5856 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5857 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5858 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5859 return;
897ab156
AD		 5860 } else {
5861 u8 l4_hdr = 0;
244e27ad 5862 switch (first->protocol) {
897ab156
AD		 5863 case __constant_htons(ETH_P_IP):
5864 vlan_macip_lens |= skb_network_header_len(skb);
5865 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5866 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5867 break;
897ab156
AD		 5868 case __constant_htons(ETH_P_IPV6):
5869 vlan_macip_lens |= skb_network_header_len(skb);
5870 l4_hdr = ipv6_hdr(skb)->nexthdr;
5871 break;
5872 default:
5873 if (unlikely(net_ratelimit())) {
5874 dev_warn(tx_ring->dev,
5875 "partial checksum but proto=%x!\n",
244e27ad 5876 first->protocol);
897ab156 5877 }
7ca647bd
JP		 5878 break;
5879 }
897ab156
AD		 5880
5881 switch (l4_hdr) {
7ca647bd 5882 case IPPROTO_TCP:
897ab156
AD		 5883 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5884 mss_l4len_idx = tcp_hdrlen(skb) <<
5885 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5886 break;
5887 case IPPROTO_SCTP:
897ab156
AD		 5888 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5889 mss_l4len_idx = sizeof(struct sctphdr) <<
5890 IXGBE_ADVTXD_L4LEN_SHIFT;
5891 break;
5892 case IPPROTO_UDP:
5893 mss_l4len_idx = sizeof(struct udphdr) <<
5894 IXGBE_ADVTXD_L4LEN_SHIFT;
5895 break;
5896 default:
5897 if (unlikely(net_ratelimit())) {
5898 dev_warn(tx_ring->dev,
5899 "partial checksum but l4 proto=%x!\n",
244e27ad 5900 l4_hdr);
897ab156 5901 }
7ca647bd
JP		 5902 break;
5903 }
244e27ad
AD		 5904
5905 /* update TX checksum flag */
5906 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5907 }
5908
244e27ad 5909 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5910 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5911 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5912
897ab156
AD		 5913 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5914 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5915}
5916
d3d00239 5917static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5918{
d3d00239
AD		 5919 /* set type for advanced descriptor with frame checksum insertion */
5920 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5921 IXGBE_ADVTXD_DCMD_IFCS |
5922 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5923
d3d00239 5924 /* set HW vlan bit if vlan is present */
66f32a8b 5925 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5926 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5927
3a6a4eda
JK		 5928#ifdef CONFIG_IXGBE_PTP
5929 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5930 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5931#endif
5932
d3d00239
AD		 5933 /* set segmentation enable bits for TSO/FSO */
5934#ifdef IXGBE_FCOE
93f5b3c1 5935 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5936#else
5937 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5938#endif
5939 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5940
d3d00239
AD		 5941 return cmd_type;
5942}
9a799d71 5943
729739b7
AD		 5944static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5945 u32 tx_flags, unsigned int paylen)
d3d00239 5946{
93f5b3c1 5947 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5948
d3d00239
AD		 5949 /* enable L4 checksum for TSO and TX checksum offload */
5950 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5951 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 5952
93f5b3c1
AD		 5953 /* enble IPv4 checksum for TSO */
5954 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5955 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 5956
93f5b3c1
AD		 5957 /* use index 1 context for TSO/FSO/FCOE */
5958#ifdef IXGBE_FCOE
5959 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5960#else
5961 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 5962#endif
93f5b3c1
AD		 5963 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5964
7f9643fd
AD		 5965 /*
5966 * Check Context must be set if Tx switch is enabled, which it
5967 * always is for case where virtual functions are running
5968 */
93f5b3c1
AD		 5969#ifdef IXGBE_FCOE
5970 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5971#else
7f9643fd 5972 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 5973#endif
7f9643fd
AD		 5974 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5975
729739b7 5976 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 5977}
44df32c5 5978
d3d00239
AD		 5979#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5980 IXGBE_TXD_CMD_RS)
5981
5982static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 5983 struct ixgbe_tx_buffer *first,
d3d00239
AD		 5984 const u8 hdr_len)
5985{
729739b7 5986 dma_addr_t dma;
fd0db0ed 5987 struct sk_buff *skb = first->skb;
729739b7 5988 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 5989 union ixgbe_adv_tx_desc *tx_desc;
729739b7 5990 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 5991 unsigned int data_len = skb->data_len;
5992 unsigned int size = skb_headlen(skb);
729739b7 5993 unsigned int paylen = skb->len - hdr_len;
244e27ad 5994 u32 tx_flags = first->tx_flags;
729739b7 5995 __le32 cmd_type;
d3d00239 5996 u16 i = tx_ring->next_to_use;
d3d00239 5997
729739b7
AD		 5998 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5999
6000 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6001 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6002
d3d00239
AD		 6003#ifdef IXGBE_FCOE
6004 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6005 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6006 size -= sizeof(struct fcoe_crc_eof) - data_len;
6007 data_len = 0;
729739b7
AD		 6008 } else {
6009 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6010 }
6011 }
44df32c5 6012
d3d00239 6013#endif
729739b7
AD		 6014 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6015 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6016 goto dma_error;
8ad494b0 6017
729739b7
AD		 6018 /* record length, and DMA address */
6019 dma_unmap_len_set(first, len, size);
6020 dma_unmap_addr_set(first, dma, dma);
9a799d71 6021
729739b7 6022 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6023
d3d00239 6024 for (;;) {
729739b7 6025 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6026 tx_desc->read.cmd_type_len =
6027 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6028
d3d00239 6029 i++;
729739b7 6030 tx_desc++;
d3d00239 6031 if (i == tx_ring->count) {
e4f74028 6032 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6033 i = 0;
6034 }
729739b7
AD		 6035
6036 dma += IXGBE_MAX_DATA_PER_TXD;
6037 size -= IXGBE_MAX_DATA_PER_TXD;
6038
6039 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6040 tx_desc->read.olinfo_status = 0;
d3d00239 6041 }
e5a43549 6042
729739b7
AD		 6043 if (likely(!data_len))
6044 break;
9a799d71 6045
f43f313e
BG		 6046 if (unlikely(skb->no_fcs))
6047 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6048 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6049
729739b7
AD		 6050 i++;
6051 tx_desc++;
6052 if (i == tx_ring->count) {
6053 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6054 i = 0;
6055 }
9a799d71 6056
d3d00239 6057#ifdef IXGBE_FCOE
9e903e08 6058 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6059#else
9e903e08 6060 size = skb_frag_size(frag);
d3d00239
AD		 6061#endif
6062 data_len -= size;
9a799d71 6063
729739b7
AD		 6064 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6065 DMA_TO_DEVICE);
6066 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6067 goto dma_error;
9a799d71 6068
729739b7
AD		 6069 tx_buffer = &tx_ring->tx_buffer_info[i];
6070 dma_unmap_len_set(tx_buffer, len, size);
6071 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6072
729739b7
AD		 6073 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6074 tx_desc->read.olinfo_status = 0;
9a799d71 6075
729739b7
AD		 6076 frag++;
6077 }
9a799d71 6078
729739b7
AD		 6079 /* write last descriptor with RS and EOP bits */
6080 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6081 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6082
091a6246 6083 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6084
d3d00239
AD		 6085 /* set the timestamp */
6086 first->time_stamp = jiffies;
9a799d71
AK		 6087
6088 /*
729739b7
AD		 6089 * Force memory writes to complete before letting h/w know there
6090 * are new descriptors to fetch. (Only applicable for weak-ordered
6091 * memory model archs, such as IA-64).
6092 *
6093 * We also need this memory barrier to make certain all of the
6094 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6095 */
6096 wmb();
6097
d3d00239
AD		 6098 /* set next_to_watch value indicating a packet is present */
6099 first->next_to_watch = tx_desc;
6100
729739b7
AD		 6101 i++;
6102 if (i == tx_ring->count)
6103 i = 0;
6104
6105 tx_ring->next_to_use = i;
6106
d3d00239 6107 /* notify HW of packet */
84ea2591 6108 writel(i, tx_ring->tail);
d3d00239
AD		 6109
6110 return;
6111dma_error:
729739b7 6112 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6113
6114 /* clear dma mappings for failed tx_buffer_info map */
6115 for (;;) {
729739b7
AD		 6116 tx_buffer = &tx_ring->tx_buffer_info[i];
6117 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6118 if (tx_buffer == first)
d3d00239
AD		 6119 break;
6120 if (i == 0)
6121 i = tx_ring->count;
6122 i--;
6123 }
6124
d3d00239 6125 tx_ring->next_to_use = i;
9a799d71
AK		 6126}
6127
fd0db0ed 6128static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6129 struct ixgbe_tx_buffer *first)
69830529
AD		 6130{
6131 struct ixgbe_q_vector *q_vector = ring->q_vector;
6132 union ixgbe_atr_hash_dword input = { .dword = 0 };
6133 union ixgbe_atr_hash_dword common = { .dword = 0 };
6134 union {
6135 unsigned char *network;
6136 struct iphdr *ipv4;
6137 struct ipv6hdr *ipv6;
6138 } hdr;
ee9e0f0b 6139 struct tcphdr *th;
905e4a41 6140 __be16 vlan_id;
c4cf55e5 6141
69830529
AD		 6142 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6143 if (!q_vector)
6144 return;
6145
6146 /* do nothing if sampling is disabled */
6147 if (!ring->atr_sample_rate)
d3ead241 6148 return;
c4cf55e5 6149
69830529 6150 ring->atr_count++;
c4cf55e5 6151
69830529 6152 /* snag network header to get L4 type and address */
fd0db0ed 6153 hdr.network = skb_network_header(first->skb);
69830529
AD		 6154
6155 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6156 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6157 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6158 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6159 hdr.ipv4->protocol != IPPROTO_TCP))
6160 return;
ee9e0f0b 6161
fd0db0ed 6162 th = tcp_hdr(first->skb);
c4cf55e5 6163
66f32a8b
AD		 6164 /* skip this packet since it is invalid or the socket is closing */
6165 if (!th || th->fin)
69830529
AD		 6166 return;
6167
6168 /* sample on all syn packets or once every atr sample count */
6169 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6170 return;
6171
6172 /* reset sample count */
6173 ring->atr_count = 0;
6174
244e27ad 6175 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6176
6177 /*
6178 * src and dst are inverted, think how the receiver sees them
6179 *
6180 * The input is broken into two sections, a non-compressed section
6181 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6182 * is XORed together and stored in the compressed dword.
6183 */
6184 input.formatted.vlan_id = vlan_id;
6185
6186 /*
6187 * since src port and flex bytes occupy the same word XOR them together
6188 * and write the value to source port portion of compressed dword
6189 */
244e27ad 6190 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6191 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6192 else
244e27ad 6193 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6194 common.port.dst ^= th->source;
6195
244e27ad 6196 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6197 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6198 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6199 } else {
6200 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6201 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6202 hdr.ipv6->saddr.s6_addr32[1] ^
6203 hdr.ipv6->saddr.s6_addr32[2] ^
6204 hdr.ipv6->saddr.s6_addr32[3] ^
6205 hdr.ipv6->daddr.s6_addr32[0] ^
6206 hdr.ipv6->daddr.s6_addr32[1] ^
6207 hdr.ipv6->daddr.s6_addr32[2] ^
6208 hdr.ipv6->daddr.s6_addr32[3];
6209 }
c4cf55e5
PWJ		 6210
6211 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6212 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6213 input, common, ring->queue_index);
c4cf55e5
PWJ		 6214}
6215
63544e9c 6216static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6217{
fc77dc3c 6218 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6219 /* Herbert's original patch had:
6220 * smp_mb__after_netif_stop_queue();
6221 * but since that doesn't exist yet, just open code it. */
6222 smp_mb();
6223
6224 /* We need to check again in a case another CPU has just
6225 * made room available. */
7d4987de 6226 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6227 return -EBUSY;
6228
6229 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6230 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6231 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6232 return 0;
6233}
6234
82d4e46e 6235static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6236{
7d4987de 6237 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6238 return 0;
fc77dc3c 6239 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6240}
6241
09a3b1f8
SH		 6242static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6243{
6244 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6245 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6246 smp_processor_id();
56075a98 6247#ifdef IXGBE_FCOE
6440752c 6248 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6249
e5b64635
JF		 6250 if (((protocol == htons(ETH_P_FCOE)) ||
6251 (protocol == htons(ETH_P_FIP))) &&
6252 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6253 struct ixgbe_ring_feature *f;
6254
6255 f = &adapter->ring_feature[RING_F_FCOE];
6256
6257 while (txq >= f->indices)
6258 txq -= f->indices;
e4b317e9 6259 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6260
e5b64635 6261 return txq;
56075a98
JF		 6262 }
6263#endif
6264
fdd3d631
KK		 6265 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6266 while (unlikely(txq >= dev->real_num_tx_queues))
6267 txq -= dev->real_num_tx_queues;
5f715823 6268 return txq;
fdd3d631 6269 }
c4cf55e5 6270
09a3b1f8
SH		 6271 return skb_tx_hash(dev, skb);
6272}
6273
fc77dc3c 6274netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6275 struct ixgbe_adapter *adapter,
6276 struct ixgbe_ring *tx_ring)
9a799d71 6277{
d3d00239 6278 struct ixgbe_tx_buffer *first;
5f715823 6279 int tso;
d3d00239 6280 u32 tx_flags = 0;
a535c30e
AD		 6281#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6282 unsigned short f;
6283#endif
a535c30e 6284 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6285 __be16 protocol = skb->protocol;
63544e9c 6286 u8 hdr_len = 0;
5e09a105 6287
a535c30e
AD		 6288 /*
6289 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6290 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6291 * + 2 desc gap to keep tail from touching head,
6292 * + 1 desc for context descriptor,
6293 * otherwise try next time
6294 */
6295#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6296 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6297 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6298#else
6299 count += skb_shinfo(skb)->nr_frags;
6300#endif
6301 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6302 tx_ring->tx_stats.tx_busy++;
6303 return NETDEV_TX_BUSY;
6304 }
6305
fd0db0ed
AD		 6306 /* record the location of the first descriptor for this packet */
6307 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6308 first->skb = skb;
091a6246
AD		 6309 first->bytecount = skb->len;
6310 first->gso_segs = 1;
fd0db0ed 6311
66f32a8b 6312 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6313 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6314 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6315 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6316 /* else if it is a SW VLAN check the next protocol and store the tag */
6317 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6318 struct vlan_hdr *vhdr, _vhdr;
6319 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6320 if (!vhdr)
6321 goto out_drop;
6322
6323 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6324 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6325 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6326 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6327 }
6328
aa7bd467
JK		 6329 skb_tx_timestamp(skb);
6330
3a6a4eda
JK		 6331#ifdef CONFIG_IXGBE_PTP
6332 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6333 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6334 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6335 }
6336#endif
6337
9e0c5648
AD		 6338#ifdef CONFIG_PCI_IOV
6339 /*
6340 * Use the l2switch_enable flag - would be false if the DMA
6341 * Tx switch had been disabled.
6342 */
6343 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6344 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6345
6346#endif
32701dc2 6347 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6348 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6349 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6350 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6351 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6352 tx_flags |= (skb->priority & 0x7) <<
6353 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6354 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6355 struct vlan_ethhdr *vhdr;
6356 if (skb_header_cloned(skb) &&
6357 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6358 goto out_drop;
6359 vhdr = (struct vlan_ethhdr *)skb->data;
6360 vhdr->h_vlan_TCI = htons(tx_flags >>
6361 IXGBE_TX_FLAGS_VLAN_SHIFT);
6362 } else {
6363 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6364 }
9a799d71 6365 }
eacd73f7 6366
244e27ad
AD		 6367 /* record initial flags and protocol */
6368 first->tx_flags = tx_flags;
6369 first->protocol = protocol;
6370
eacd73f7 6371#ifdef IXGBE_FCOE
66f32a8b
AD		 6372 /* setup tx offload for FCoE */
6373 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6374 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
244e27ad 6375 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6376 if (tso < 0)
6377 goto out_drop;
9a799d71 6378
66f32a8b 6379 goto xmit_fcoe;
eacd73f7 6380 }
9a799d71 6381
66f32a8b 6382#endif /* IXGBE_FCOE */
244e27ad 6383 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6384 if (tso < 0)
897ab156 6385 goto out_drop;
244e27ad
AD		 6386 else if (!tso)
6387 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6388
6389 /* add the ATR filter if ATR is on */
6390 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6391 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6392
6393#ifdef IXGBE_FCOE
6394xmit_fcoe:
6395#endif /* IXGBE_FCOE */
244e27ad 6396 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6397
6398 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6399
6400 return NETDEV_TX_OK;
897ab156
AD		 6401
6402out_drop:
fd0db0ed
AD		 6403 dev_kfree_skb_any(first->skb);
6404 first->skb = NULL;
6405
897ab156 6406 return NETDEV_TX_OK;
9a799d71
AK		 6407}
6408
a50c29dd
AD		 6409static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6410 struct net_device *netdev)
84418e3b
AD		 6411{
6412 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6413 struct ixgbe_ring *tx_ring;
6414
a50c29dd
AD		 6415 /*
6416 * The minimum packet size for olinfo paylen is 17 so pad the skb
6417 * in order to meet this minimum size requirement.
6418 */
f73332fc
SH		 6419 if (unlikely(skb->len < 17)) {
6420 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6421 return NETDEV_TX_OK;
6422 skb->len = 17;
6423 }
6424
84418e3b 6425 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6426 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6427}
6428
9a799d71
AK		 6429/**
6430 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6431 * @netdev: network interface device structure
6432 * @p: pointer to an address structure
6433 *
6434 * Returns 0 on success, negative on failure
6435 **/
6436static int ixgbe_set_mac(struct net_device *netdev, void *p)
6437{
6438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6439 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6440 struct sockaddr *addr = p;
6441
6442 if (!is_valid_ether_addr(addr->sa_data))
6443 return -EADDRNOTAVAIL;
6444
6445 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6446 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6447
1cdd1ec8
GR		 6448 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6449 IXGBE_RAH_AV);
9a799d71
AK		 6450
6451 return 0;
6452}
6453
6b73e10d
BH		 6454static int
6455ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6456{
6457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6458 struct ixgbe_hw *hw = &adapter->hw;
6459 u16 value;
6460 int rc;
6461
6462 if (prtad != hw->phy.mdio.prtad)
6463 return -EINVAL;
6464 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6465 if (!rc)
6466 rc = value;
6467 return rc;
6468}
6469
6470static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6471 u16 addr, u16 value)
6472{
6473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6474 struct ixgbe_hw *hw = &adapter->hw;
6475
6476 if (prtad != hw->phy.mdio.prtad)
6477 return -EINVAL;
6478 return hw->phy.ops.write_reg(hw, addr, devad, value);
6479}
6480
6481static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6482{
6483 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6484
3a6a4eda
JK		 6485 switch (cmd) {
6486#ifdef CONFIG_IXGBE_PTP
6487 case SIOCSHWTSTAMP:
6488 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6489#endif
6490 default:
6491 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6492 }
6b73e10d
BH		 6493}
6494
0365e6e4
PW		 6495/**
6496 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6497 * netdev->dev_addrs
0365e6e4
PW		 6498 * @netdev: network interface device structure
6499 *
6500 * Returns non-zero on failure
6501 **/
6502static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6503{
6504 int err = 0;
6505 struct ixgbe_adapter *adapter = netdev_priv(dev);
6506 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6507
6508 if (is_valid_ether_addr(mac->san_addr)) {
6509 rtnl_lock();
6510 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6511 rtnl_unlock();
6512 }
6513 return err;
6514}
6515
6516/**
6517 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6518 * netdev->dev_addrs
0365e6e4
PW		 6519 * @netdev: network interface device structure
6520 *
6521 * Returns non-zero on failure
6522 **/
6523static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6524{
6525 int err = 0;
6526 struct ixgbe_adapter *adapter = netdev_priv(dev);
6527 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6528
6529 if (is_valid_ether_addr(mac->san_addr)) {
6530 rtnl_lock();
6531 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6532 rtnl_unlock();
6533 }
6534 return err;
6535}
6536
9a799d71
AK		 6537#ifdef CONFIG_NET_POLL_CONTROLLER
6538/*
6539 * Polling 'interrupt' - used by things like netconsole to send skbs
6540 * without having to re-enable interrupts. It's not called while
6541 * the interrupt routine is executing.
6542 */
6543static void ixgbe_netpoll(struct net_device *netdev)
6544{
6545 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6546 int i;
9a799d71 6547
1a647bd2
AD		 6548 /* if interface is down do nothing */
6549 if (test_bit(__IXGBE_DOWN, &adapter->state))
6550 return;
6551
9a799d71 6552 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6553 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6554 for (i = 0; i < adapter->num_q_vectors; i++)
6555 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6556 } else {
6557 ixgbe_intr(adapter->pdev->irq, netdev);
6558 }
9a799d71 6559 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6560}
9a799d71 6561
581330ba 6562#endif
de1036b1
ED		 6563static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6564 struct rtnl_link_stats64 *stats)
6565{
6566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6567 int i;
6568
1a51502b 6569 rcu_read_lock();
de1036b1 6570 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6571 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6572 u64 bytes, packets;
6573 unsigned int start;
6574
1a51502b
ED		 6575 if (ring) {
6576 do {
6577 start = u64_stats_fetch_begin_bh(&ring->syncp);
6578 packets = ring->stats.packets;
6579 bytes = ring->stats.bytes;
6580 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6581 stats->rx_packets += packets;
6582 stats->rx_bytes += bytes;
6583 }
de1036b1 6584 }
1ac9ad13
ED		 6585
6586 for (i = 0; i < adapter->num_tx_queues; i++) {
6587 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6588 u64 bytes, packets;
6589 unsigned int start;
6590
6591 if (ring) {
6592 do {
6593 start = u64_stats_fetch_begin_bh(&ring->syncp);
6594 packets = ring->stats.packets;
6595 bytes = ring->stats.bytes;
6596 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6597 stats->tx_packets += packets;
6598 stats->tx_bytes += bytes;
6599 }
6600 }
1a51502b 6601 rcu_read_unlock();
de1036b1
ED		 6602 /* following stats updated by ixgbe_watchdog_task() */
6603 stats->multicast = netdev->stats.multicast;
6604 stats->rx_errors = netdev->stats.rx_errors;
6605 stats->rx_length_errors = netdev->stats.rx_length_errors;
6606 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6607 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6608 return stats;
6609}
6610
8af3c33f 6611#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6612/**
6613 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6614 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6615 * @tc: number of traffic classes currently enabled
6616 *
6617 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6618 * 802.1Q priority maps to a packet buffer that exists.
6619 */
6620static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6621{
6622 struct ixgbe_hw *hw = &adapter->hw;
6623 u32 reg, rsave;
6624 int i;
6625
6626 /* 82598 have a static priority to TC mapping that can not
6627 * be changed so no validation is needed.
6628 */
6629 if (hw->mac.type == ixgbe_mac_82598EB)
6630 return;
6631
6632 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6633 rsave = reg;
6634
6635 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6636 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6637
6638 /* If up2tc is out of bounds default to zero */
6639 if (up2tc > tc)
6640 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6641 }
6642
6643 if (reg != rsave)
6644 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6645
6646 return;
6647}
6648
02debdc9
AD		 6649/**
6650 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6651 * @adapter: Pointer to adapter struct
6652 *
6653 * Populate the netdev user priority to tc map
6654 */
6655static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6656{
6657 struct net_device *dev = adapter->netdev;
6658 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6659 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6660 u8 prio;
6661
6662 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6663 u8 tc = 0;
6664
6665 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6666 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6667 else if (ets)
6668 tc = ets->prio_tc[prio];
6669
6670 netdev_set_prio_tc_map(dev, prio, tc);
6671 }
6672}
6673
49ce9c2c
BH		 6674/**
6675 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6676 *
6677 * @netdev: net device to configure
6678 * @tc: number of traffic classes to enable
6679 */
6680int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6681{
8b1c0b24
JF		 6682 struct ixgbe_adapter *adapter = netdev_priv(dev);
6683 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6684
e7589eab
JF		 6685 /* Multiple traffic classes requires multiple queues */
6686 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6687 e_err(drv, "Enable failed, needs MSI-X\n");
6688 return -EINVAL;
6689 }
8b1c0b24
JF		 6690
6691 /* Hardware supports up to 8 traffic classes */
4de2a022 6692 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6693 (hw->mac.type == ixgbe_mac_82598EB &&
6694 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6695 return -EINVAL;
6696
6697 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6698 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6699 * hardware is not flexible enough to do this dynamically.
6700 */
6701 if (netif_running(dev))
6702 ixgbe_close(dev);
6703 ixgbe_clear_interrupt_scheme(adapter);
6704
e7589eab 6705 if (tc) {
8b1c0b24 6706 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6707 ixgbe_set_prio_tc_map(adapter);
6708
e7589eab
JF		 6709 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6710 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6711
943561d3
AD		 6712 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6713 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6714 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6715 }
e7589eab 6716 } else {
8b1c0b24 6717 netdev_reset_tc(dev);
02debdc9 6718
943561d3
AD		 6719 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6720 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6721
6722 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6723 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6724
6725 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6726 adapter->dcb_cfg.pfc_mode_enable = false;
6727 }
6728
8b1c0b24
JF		 6729 ixgbe_init_interrupt_scheme(adapter);
6730 ixgbe_validate_rtr(adapter, tc);
6731 if (netif_running(dev))
6732 ixgbe_open(dev);
6733
6734 return 0;
6735}
de1036b1 6736
8af3c33f 6737#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6738void ixgbe_do_reset(struct net_device *netdev)
6739{
6740 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6741
6742 if (netif_running(netdev))
6743 ixgbe_reinit_locked(adapter);
6744 else
6745 ixgbe_reset(adapter);
6746}
6747
c8f44aff 6748static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6749 netdev_features_t features)
082757af
DS		 6750{
6751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6752
082757af 6753 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6754 if (!(features & NETIF_F_RXCSUM))
6755 features &= ~NETIF_F_LRO;
082757af 6756
567d2de2
AD		 6757 /* Turn off LRO if not RSC capable */
6758 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6759 features &= ~NETIF_F_LRO;
8e2813f5 6760
567d2de2 6761 return features;
082757af
DS		 6762}
6763
c8f44aff 6764static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6765 netdev_features_t features)
082757af
DS		 6766{
6767 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6768 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6769 bool need_reset = false;
6770
082757af 6771 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6772 if (!(features & NETIF_F_LRO)) {
6773 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6774 need_reset = true;
567d2de2
AD		 6775 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6776 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6777 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6778 if (adapter->rx_itr_setting == 1 ||
6779 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6780 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6781 need_reset = true;
6782 } else if ((changed ^ features) & NETIF_F_LRO) {
6783 e_info(probe, "rx-usecs set too low, "
6784 "disabling RSC\n");
082757af
DS		 6785 }
6786 }
6787
6788 /*
6789 * Check if Flow Director n-tuple support was enabled or disabled. If
6790 * the state changed, we need to reset.
6791 */
567d2de2
AD		 6792 if (!(features & NETIF_F_NTUPLE)) {
6793 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6794 /* turn off Flow Director, set ATR and reset */
fbe7ca7f 6795 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
567d2de2
AD		 6796 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6797 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 6798 need_reset = true;
6799 }
082757af 6800 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
567d2de2
AD		 6801 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6802 /* turn off ATR, enable perfect filters and reset */
6803 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6804 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
082757af
DS		 6805 need_reset = true;
6806 }
6807
146d4cc9
JF		 6808 if (features & NETIF_F_HW_VLAN_RX)
6809 ixgbe_vlan_strip_enable(adapter);
6810 else
6811 ixgbe_vlan_strip_disable(adapter);
6812
3f2d1c0f
BG		 6813 if (changed & NETIF_F_RXALL)
6814 need_reset = true;
6815
567d2de2 6816 netdev->features = features;
082757af
DS		 6817 if (need_reset)
6818 ixgbe_do_reset(netdev);
6819
6820 return 0;
082757af
DS		 6821}
6822
0f4b0add
JF		 6823static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6824 struct net_device *dev,
6825 unsigned char *addr,
6826 u16 flags)
6827{
6828 struct ixgbe_adapter *adapter = netdev_priv(dev);
6829 int err = -EOPNOTSUPP;
6830
6831 if (ndm->ndm_state & NUD_PERMANENT) {
6832 pr_info("%s: FDB only supports static addresses\n",
6833 ixgbe_driver_name);
6834 return -EINVAL;
6835 }
6836
6837 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6838 if (is_unicast_ether_addr(addr))
6839 err = dev_uc_add_excl(dev, addr);
6840 else if (is_multicast_ether_addr(addr))
6841 err = dev_mc_add_excl(dev, addr);
6842 else
6843 err = -EINVAL;
6844 }
6845
6846 /* Only return duplicate errors if NLM_F_EXCL is set */
6847 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6848 err = 0;
6849
6850 return err;
6851}
6852
6853static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6854 struct net_device *dev,
6855 unsigned char *addr)
6856{
6857 struct ixgbe_adapter *adapter = netdev_priv(dev);
6858 int err = -EOPNOTSUPP;
6859
6860 if (ndm->ndm_state & NUD_PERMANENT) {
6861 pr_info("%s: FDB only supports static addresses\n",
6862 ixgbe_driver_name);
6863 return -EINVAL;
6864 }
6865
6866 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6867 if (is_unicast_ether_addr(addr))
6868 err = dev_uc_del(dev, addr);
6869 else if (is_multicast_ether_addr(addr))
6870 err = dev_mc_del(dev, addr);
6871 else
6872 err = -EINVAL;
6873 }
6874
6875 return err;
6876}
6877
6878static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6879 struct netlink_callback *cb,
6880 struct net_device *dev,
6881 int idx)
6882{
6883 struct ixgbe_adapter *adapter = netdev_priv(dev);
6884
6885 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6886 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6887
6888 return idx;
6889}
6890
0edc3527 6891static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6892 .ndo_open = ixgbe_open,
0edc3527 6893 .ndo_stop = ixgbe_close,
00829823 6894 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6895 .ndo_select_queue = ixgbe_select_queue,
581330ba 6896 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6897 .ndo_validate_addr = eth_validate_addr,
6898 .ndo_set_mac_address = ixgbe_set_mac,
6899 .ndo_change_mtu = ixgbe_change_mtu,
6900 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6901 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6902 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6903 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6904 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6905 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6906 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6907 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6908 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6909 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6910#ifdef CONFIG_IXGBE_DCB
24095aa3 6911 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6912#endif
0edc3527
SH		 6913#ifdef CONFIG_NET_POLL_CONTROLLER
6914 .ndo_poll_controller = ixgbe_netpoll,
6915#endif
332d4a7d
YZ		 6916#ifdef IXGBE_FCOE
6917 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6918 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6919 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6920 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6921 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6922 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6923 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6924#endif /* IXGBE_FCOE */
082757af
DS		 6925 .ndo_set_features = ixgbe_set_features,
6926 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6927 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6928 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6929 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 6930};
6931
1cdd1ec8 6932static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
567d2de2 6933 const struct ixgbe_info *ii)
1cdd1ec8
GR		 6934{
6935#ifdef CONFIG_PCI_IOV
6936 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 6937
c6bda30a 6938 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 6939 return;
6940
6941 /* The 82599 supports up to 64 VFs per physical function
6942 * but this implementation limits allocation to 63 so that
6943 * basic networking resources are still available to the
6b42a9c5
GR		 6944 * physical function. If the user requests greater thn
6945 * 63 VFs then it is an error - reset to default of zero.
1cdd1ec8 6946 */
6b42a9c5 6947 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
c6bda30a 6948 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 6949#endif /* CONFIG_PCI_IOV */
6950}
6951
8e2813f5
JK		 6952/**
6953 * ixgbe_wol_supported - Check whether device supports WoL
6954 * @hw: hw specific details
6955 * @device_id: the device ID
6956 * @subdev_id: the subsystem device ID
6957 *
6958 * This function is used by probe and ethtool to determine
6959 * which devices have WoL support
6960 *
6961 **/
6962int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6963 u16 subdevice_id)
6964{
6965 struct ixgbe_hw *hw = &adapter->hw;
6966 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6967 int is_wol_supported = 0;
6968
6969 switch (device_id) {
6970 case IXGBE_DEV_ID_82599_SFP:
6971 /* Only these subdevices could supports WOL */
6972 switch (subdevice_id) {
6973 case IXGBE_SUBDEV_ID_82599_560FLR:
6974 /* only support first port */
6975 if (hw->bus.func != 0)
6976 break;
6977 case IXGBE_SUBDEV_ID_82599_SFP:
6978 is_wol_supported = 1;
6979 break;
6980 }
6981 break;
6982 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6983 /* All except this subdevice support WOL */
6984 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6985 is_wol_supported = 1;
6986 break;
6987 case IXGBE_DEV_ID_82599_KX4:
6988 is_wol_supported = 1;
6989 break;
6990 case IXGBE_DEV_ID_X540T:
6991 /* check eeprom to see if enabled wol */
6992 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6993 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6994 (hw->bus.func == 0))) {
6995 is_wol_supported = 1;
6996 }
6997 break;
6998 }
6999
7000 return is_wol_supported;
7001}
7002
9a799d71
AK		 7003/**
7004 * ixgbe_probe - Device Initialization Routine
7005 * @pdev: PCI device information struct
7006 * @ent: entry in ixgbe_pci_tbl
7007 *
7008 * Returns 0 on success, negative on failure
7009 *
7010 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7011 * The OS initialization, configuring of the adapter private structure,
7012 * and a hardware reset occur.
7013 **/
7014static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7015 const struct pci_device_id *ent)
9a799d71
AK		 7016{
7017 struct net_device *netdev;
7018 struct ixgbe_adapter *adapter = NULL;
7019 struct ixgbe_hw *hw;
7020 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7021 static int cards_found;
7022 int i, err, pci_using_dac;
289700db 7023 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7024 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7025#ifdef IXGBE_FCOE
7026 u16 device_caps;
7027#endif
289700db 7028 u32 eec;
9a799d71 7029
bded64a7
AG		 7030 /* Catch broken hardware that put the wrong VF device ID in
7031 * the PCIe SR-IOV capability.
7032 */
7033 if (pdev->is_virtfn) {
7034 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7035 pci_name(pdev), pdev->vendor, pdev->device);
7036 return -EINVAL;
7037 }
7038
9ce77666 7039 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7040 if (err)
7041 return err;
7042
1b507730
NN		 7043 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7044 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7045 pci_using_dac = 1;
7046 } else {
1b507730 7047 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7048 if (err) {
1b507730
NN		 7049 err = dma_set_coherent_mask(&pdev->dev,
7050 DMA_BIT_MASK(32));
9a799d71 7051 if (err) {
b8bc0421
DC		 7052 dev_err(&pdev->dev,
7053 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7054 goto err_dma;
7055 }
7056 }
7057 pci_using_dac = 0;
7058 }
7059
9ce77666 7060 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7061 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7062 if (err) {
b8bc0421
DC		 7063 dev_err(&pdev->dev,
7064 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7065 goto err_pci_reg;
7066 }
7067
19d5afd4 7068 pci_enable_pcie_error_reporting(pdev);
6fabd715 7069
9a799d71 7070 pci_set_master(pdev);
fb3b27bc 7071 pci_save_state(pdev);
9a799d71 7072
e901acd6
JF		 7073#ifdef CONFIG_IXGBE_DCB
7074 indices *= MAX_TRAFFIC_CLASS;
7075#endif
7076
c85a2618 7077 if (ii->mac == ixgbe_mac_82598EB)
d411a936
AD		 7078#ifdef CONFIG_IXGBE_DCB
7079 indices = min_t(unsigned int, indices, MAX_TRAFFIC_CLASS * 4);
7080#else
c85a2618 7081 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
d411a936 7082#endif
c85a2618
JF		 7083 else
7084 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7085
e901acd6 7086#ifdef IXGBE_FCOE
c85a2618
JF		 7087 indices += min_t(unsigned int, num_possible_cpus(),
7088 IXGBE_MAX_FCOE_INDICES);
7089#endif
c85a2618 7090 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7091 if (!netdev) {
7092 err = -ENOMEM;
7093 goto err_alloc_etherdev;
7094 }
7095
9a799d71
AK		 7096 SET_NETDEV_DEV(netdev, &pdev->dev);
7097
9a799d71 7098 adapter = netdev_priv(netdev);
c60fbb00 7099 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7100
7101 adapter->netdev = netdev;
7102 adapter->pdev = pdev;
7103 hw = &adapter->hw;
7104 hw->back = adapter;
b3f4d599 7105 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7106
05857980 7107 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7108 pci_resource_len(pdev, 0));
9a799d71
AK		 7109 if (!hw->hw_addr) {
7110 err = -EIO;
7111 goto err_ioremap;
7112 }
7113
7114 for (i = 1; i <= 5; i++) {
7115 if (pci_resource_len(pdev, i) == 0)
7116 continue;
7117 }
7118
0edc3527 7119 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7120 ixgbe_set_ethtool_ops(netdev);
9a799d71 7121 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7122 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7123
9a799d71
AK		 7124 adapter->bd_number = cards_found;
7125
9a799d71
AK		 7126 /* Setup hw api */
7127 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7128 hw->mac.type = ii->mac;
9a799d71 7129
c44ade9e
JB		 7130 /* EEPROM */
7131 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7132 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7133 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7134 if (!(eec & (1 << 8)))
7135 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7136
7137 /* PHY */
7138 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7139 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7140 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7141 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7142 hw->phy.mdio.mmds = 0;
7143 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7144 hw->phy.mdio.dev = netdev;
7145 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7146 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7147
8ca783ab 7148 ii->get_invariants(hw);
9a799d71
AK		 7149
7150 /* setup the private structure */
7151 err = ixgbe_sw_init(adapter);
7152 if (err)
7153 goto err_sw_init;
7154
e86bff0e 7155 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7156 switch (adapter->hw.mac.type) {
7157 case ixgbe_mac_82599EB:
7158 case ixgbe_mac_X540:
e86bff0e 7159 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7160 break;
7161 default:
7162 break;
7163 }
e86bff0e 7164
bf069c97
DS		 7165 /*
7166 * If there is a fan on this device and it has failed log the
7167 * failure.
7168 */
7169 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7170 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7171 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7172 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7173 }
7174
8ef78adc
PWJ		 7175 if (allow_unsupported_sfp)
7176 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7177
c44ade9e 7178 /* reset_hw fills in the perm_addr as well */
119fc60a 7179 hw->phy.reset_if_overtemp = true;
c44ade9e 7180 err = hw->mac.ops.reset_hw(hw);
119fc60a 7181 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7182 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7183 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7184 err = 0;
7185 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7186 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7187 "module type was detected.\n");
7188 e_dev_err("Reload the driver after installing a supported "
7189 "module.\n");
04f165ef
PW		 7190 goto err_sw_init;
7191 } else if (err) {
849c4542 7192 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7193 goto err_sw_init;
7194 }
7195
1cdd1ec8
GR		 7196 ixgbe_probe_vf(adapter, ii);
7197
396e799c 7198 netdev->features = NETIF_F_SG |
e8e9f696 7199 NETIF_F_IP_CSUM |
082757af 7200 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7201 NETIF_F_HW_VLAN_TX |
7202 NETIF_F_HW_VLAN_RX |
082757af
DS		 7203 NETIF_F_HW_VLAN_FILTER |
7204 NETIF_F_TSO |
7205 NETIF_F_TSO6 |
082757af
DS		 7206 NETIF_F_RXHASH |
7207 NETIF_F_RXCSUM;
9a799d71 7208
082757af 7209 netdev->hw_features = netdev->features;
ad31c402 7210
58be7666
DS		 7211 switch (adapter->hw.mac.type) {
7212 case ixgbe_mac_82599EB:
7213 case ixgbe_mac_X540:
45a5ead0 7214 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7215 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7216 NETIF_F_NTUPLE;
58be7666
DS		 7217 break;
7218 default:
7219 break;
7220 }
45a5ead0 7221
3f2d1c0f
BG		 7222 netdev->hw_features |= NETIF_F_RXALL;
7223
ad31c402
JK		 7224 netdev->vlan_features |= NETIF_F_TSO;
7225 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7226 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7227 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7228 netdev->vlan_features |= NETIF_F_SG;
7229
01789349 7230 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7231 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7232
7a6b6f51 7233#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7234 netdev->dcbnl_ops = &dcbnl_ops;
7235#endif
7236
eacd73f7 7237#ifdef IXGBE_FCOE
0d551589 7238 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7239 if (hw->mac.ops.get_device_caps) {
7240 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7241 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7242 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7243 }
7244 }
5e09d7f6
YZ		 7245 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7246 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7247 netdev->vlan_features |= NETIF_F_FSO;
7248 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7249 }
eacd73f7 7250#endif /* IXGBE_FCOE */
7b872a55 7251 if (pci_using_dac) {
9a799d71 7252 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7253 netdev->vlan_features |= NETIF_F_HIGHDMA;
7254 }
9a799d71 7255
082757af
DS		 7256 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7257 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7258 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7259 netdev->features |= NETIF_F_LRO;
7260
9a799d71 7261 /* make sure the EEPROM is good */
c44ade9e 7262 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7263 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7264 err = -EIO;
35937c05 7265 goto err_sw_init;
9a799d71
AK		 7266 }
7267
7268 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7269 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7270
c44ade9e 7271 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7272 e_dev_err("invalid MAC address\n");
9a799d71 7273 err = -EIO;
35937c05 7274 goto err_sw_init;
9a799d71
AK		 7275 }
7276
7086400d 7277 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7278 (unsigned long) adapter);
9a799d71 7279
7086400d
AD		 7280 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7281 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7282
021230d4
AV		 7283 err = ixgbe_init_interrupt_scheme(adapter);
7284 if (err)
7285 goto err_sw_init;
9a799d71 7286
8e2813f5 7287 /* WOL not supported for all devices */
c23f5b6b 7288 adapter->wol = 0;
8e2813f5
JK		 7289 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7290 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7291 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7292
e8e26350
PW		 7293 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7294
3a6a4eda
JK		 7295#ifdef CONFIG_IXGBE_PTP
7296 ixgbe_ptp_init(adapter);
7297#endif /* CONFIG_IXGBE_PTP*/
7298
15e5209f
ET		 7299 /* save off EEPROM version number */
7300 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7301 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7302
04f165ef
PW		 7303 /* pick up the PCI bus settings for reporting later */
7304 hw->mac.ops.get_bus_info(hw);
7305
9a799d71 7306 /* print bus type/speed/width info */
849c4542 7307 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7308 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7309 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7310 "Unknown"),
7311 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7312 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7313 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7314 "Unknown"),
7315 netdev->dev_addr);
289700db
DS		 7316
7317 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7318 if (err)
9fe93afd 7319 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7320 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7321 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7322 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7323 part_str);
e8e26350 7324 else
289700db
DS		 7325 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7326 hw->mac.type, hw->phy.type, part_str);
9a799d71 7327
e8e26350 7328 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7329 e_dev_warn("PCI-Express bandwidth available for this card is "
7330 "not sufficient for optimal performance.\n");
7331 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7332 "is required.\n");
0c254d86
AK		 7333 }
7334
9a799d71 7335 /* reset the hardware with the new settings */
794caeb2 7336 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7337 if (err == IXGBE_ERR_EEPROM_VERSION) {
7338 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7339 e_dev_warn("This device is a pre-production adapter/LOM. "
7340 "Please be aware there may be issues associated "
7341 "with your hardware. If you are experiencing "
7342 "problems please contact your Intel or hardware "
7343 "representative who provided you with this "
7344 "hardware.\n");
794caeb2 7345 }
9a799d71
AK		 7346 strcpy(netdev->name, "eth%d");
7347 err = register_netdev(netdev);
7348 if (err)
7349 goto err_register;
7350
93d3ce8f
ET		 7351 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7352 if (hw->mac.ops.disable_tx_laser &&
7353 ((hw->phy.multispeed_fiber) ||
7354 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7355 (hw->mac.type == ixgbe_mac_82599EB))))
7356 hw->mac.ops.disable_tx_laser(hw);
7357
54386467
JB		 7358 /* carrier off reporting is important to ethtool even BEFORE open */
7359 netif_carrier_off(netdev);
7360
5dd2d332 7361#ifdef CONFIG_IXGBE_DCA
652f093f 7362 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7363 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7364 ixgbe_setup_dca(adapter);
7365 }
7366#endif
1cdd1ec8 7367 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7368 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7369 for (i = 0; i < adapter->num_vfs; i++)
7370 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7371 }
7372
2466dd9c
JK		 7373 /* firmware requires driver version to be 0xFFFFFFFF
7374 * since os does not support feature
7375 */
9612de92 7376 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7377 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7378 0xFF);
9612de92 7379
0365e6e4
PW		 7380 /* add san mac addr to netdev */
7381 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7382
ea81875a 7383 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7384 cards_found++;
3ca8bc6d 7385
1210982b 7386#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7387 if (ixgbe_sysfs_init(adapter))
7388 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7389#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7390
9a799d71
AK		 7391 return 0;
7392
7393err_register:
5eba3699 7394 ixgbe_release_hw_control(adapter);
7a921c93 7395 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7396err_sw_init:
1cdd1ec8
GR		 7397 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7398 ixgbe_disable_sriov(adapter);
7086400d 7399 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7400 iounmap(hw->hw_addr);
7401err_ioremap:
7402 free_netdev(netdev);
7403err_alloc_etherdev:
e8e9f696
JP		 7404 pci_release_selected_regions(pdev,
7405 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7406err_pci_reg:
7407err_dma:
7408 pci_disable_device(pdev);
7409 return err;
7410}
7411
7412/**
7413 * ixgbe_remove - Device Removal Routine
7414 * @pdev: PCI device information struct
7415 *
7416 * ixgbe_remove is called by the PCI subsystem to alert the driver
7417 * that it should release a PCI device. The could be caused by a
7418 * Hot-Plug event, or because the driver is going to be removed from
7419 * memory.
7420 **/
7421static void __devexit ixgbe_remove(struct pci_dev *pdev)
7422{
c60fbb00
AD		 7423 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7424 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7425
7426 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7427 cancel_work_sync(&adapter->service_task);
9a799d71 7428
3a6a4eda
JK		 7429#ifdef CONFIG_IXGBE_PTP
7430 ixgbe_ptp_stop(adapter);
7431#endif
7432
5dd2d332 7433#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7434 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7435 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7436 dca_remove_requester(&pdev->dev);
7437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7438 }
7439
7440#endif
1210982b 7441#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7442 ixgbe_sysfs_exit(adapter);
1210982b 7443#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7444
332d4a7d
YZ		 7445#ifdef IXGBE_FCOE
7446 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7447 ixgbe_cleanup_fcoe(adapter);
7448
7449#endif /* IXGBE_FCOE */
0365e6e4
PW		 7450
7451 /* remove the added san mac */
7452 ixgbe_del_sanmac_netdev(netdev);
7453
c4900be0
DS		 7454 if (netdev->reg_state == NETREG_REGISTERED)
7455 unregister_netdev(netdev);
9a799d71 7456
c6bda30a
GR		 7457 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7458 if (!(ixgbe_check_vf_assignment(adapter)))
7459 ixgbe_disable_sriov(adapter);
7460 else
7461 e_dev_warn("Unloading driver while VFs are assigned "
7462 "- VFs will not be deallocated\n");
7463 }
1cdd1ec8 7464
7a921c93 7465 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7466
021230d4 7467 ixgbe_release_hw_control(adapter);
9a799d71 7468
2b1588c3
AD		 7469#ifdef CONFIG_DCB
7470 kfree(adapter->ixgbe_ieee_pfc);
7471 kfree(adapter->ixgbe_ieee_ets);
7472
7473#endif
9a799d71 7474 iounmap(adapter->hw.hw_addr);
9ce77666 7475 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7476 IORESOURCE_MEM));
9a799d71 7477
849c4542 7478 e_dev_info("complete\n");
021230d4 7479
9a799d71
AK		 7480 free_netdev(netdev);
7481
19d5afd4 7482 pci_disable_pcie_error_reporting(pdev);
6fabd715 7483
9a799d71
AK		 7484 pci_disable_device(pdev);
7485}
7486
7487/**
7488 * ixgbe_io_error_detected - called when PCI error is detected
7489 * @pdev: Pointer to PCI device
7490 * @state: The current pci connection state
7491 *
7492 * This function is called after a PCI bus error affecting
7493 * this device has been detected.
7494 */
7495static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7496 pci_channel_state_t state)
9a799d71 7497{
c60fbb00
AD		 7498 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7499 struct net_device *netdev = adapter->netdev;
9a799d71 7500
83c61fa9
GR		 7501#ifdef CONFIG_PCI_IOV
7502 struct pci_dev *bdev, *vfdev;
7503 u32 dw0, dw1, dw2, dw3;
7504 int vf, pos;
7505 u16 req_id, pf_func;
7506
7507 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7508 adapter->num_vfs == 0)
7509 goto skip_bad_vf_detection;
7510
7511 bdev = pdev->bus->self;
7512 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7513 bdev = bdev->bus->self;
7514
7515 if (!bdev)
7516 goto skip_bad_vf_detection;
7517
7518 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7519 if (!pos)
7520 goto skip_bad_vf_detection;
7521
7522 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7523 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7524 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7525 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7526
7527 req_id = dw1 >> 16;
7528 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7529 if (!(req_id & 0x0080))
7530 goto skip_bad_vf_detection;
7531
7532 pf_func = req_id & 0x01;
7533 if ((pf_func & 1) == (pdev->devfn & 1)) {
7534 unsigned int device_id;
7535
7536 vf = (req_id & 0x7F) >> 1;
7537 e_dev_err("VF %d has caused a PCIe error\n", vf);
7538 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7539 "%8.8x\tdw3: %8.8x\n",
7540 dw0, dw1, dw2, dw3);
7541 switch (adapter->hw.mac.type) {
7542 case ixgbe_mac_82599EB:
7543 device_id = IXGBE_82599_VF_DEVICE_ID;
7544 break;
7545 case ixgbe_mac_X540:
7546 device_id = IXGBE_X540_VF_DEVICE_ID;
7547 break;
7548 default:
7549 device_id = 0;
7550 break;
7551 }
7552
7553 /* Find the pci device of the offending VF */
7554 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7555 while (vfdev) {
7556 if (vfdev->devfn == (req_id & 0xFF))
7557 break;
7558 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7559 device_id, vfdev);
7560 }
7561 /*
7562 * There's a slim chance the VF could have been hot plugged,
7563 * so if it is no longer present we don't need to issue the
7564 * VFLR. Just clean up the AER in that case.
7565 */
7566 if (vfdev) {
7567 e_dev_err("Issuing VFLR to VF %d\n", vf);
7568 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7569 }
7570
7571 pci_cleanup_aer_uncorrect_error_status(pdev);
7572 }
7573
7574 /*
7575 * Even though the error may have occurred on the other port
7576 * we still need to increment the vf error reference count for
7577 * both ports because the I/O resume function will be called
7578 * for both of them.
7579 */
7580 adapter->vferr_refcount++;
7581
7582 return PCI_ERS_RESULT_RECOVERED;
7583
7584skip_bad_vf_detection:
7585#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7586 netif_device_detach(netdev);
7587
3044b8d1
BL		 7588 if (state == pci_channel_io_perm_failure)
7589 return PCI_ERS_RESULT_DISCONNECT;
7590
9a799d71
AK		 7591 if (netif_running(netdev))
7592 ixgbe_down(adapter);
7593 pci_disable_device(pdev);
7594
b4617240 7595 /* Request a slot reset. */
9a799d71
AK		 7596 return PCI_ERS_RESULT_NEED_RESET;
7597}
7598
7599/**
7600 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7601 * @pdev: Pointer to PCI device
7602 *
7603 * Restart the card from scratch, as if from a cold-boot.
7604 */
7605static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7606{
c60fbb00 7607 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7608 pci_ers_result_t result;
7609 int err;
9a799d71 7610
9ce77666 7611 if (pci_enable_device_mem(pdev)) {
396e799c 7612 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7613 result = PCI_ERS_RESULT_DISCONNECT;
7614 } else {
7615 pci_set_master(pdev);
7616 pci_restore_state(pdev);
c0e1f68b 7617 pci_save_state(pdev);
9a799d71 7618
dd4d8ca6 7619 pci_wake_from_d3(pdev, false);
9a799d71 7620
6fabd715 7621 ixgbe_reset(adapter);
88512539 7622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7623 result = PCI_ERS_RESULT_RECOVERED;
7624 }
7625
7626 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7627 if (err) {
849c4542
ET		 7628 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7629 "failed 0x%0x\n", err);
6fabd715
PWJ		 7630 /* non-fatal, continue */
7631 }
9a799d71 7632
6fabd715 7633 return result;
9a799d71
AK		 7634}
7635
7636/**
7637 * ixgbe_io_resume - called when traffic can start flowing again.
7638 * @pdev: Pointer to PCI device
7639 *
7640 * This callback is called when the error recovery driver tells us that
7641 * its OK to resume normal operation.
7642 */
7643static void ixgbe_io_resume(struct pci_dev *pdev)
7644{
c60fbb00
AD		 7645 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7646 struct net_device *netdev = adapter->netdev;
9a799d71 7647
83c61fa9
GR		 7648#ifdef CONFIG_PCI_IOV
7649 if (adapter->vferr_refcount) {
7650 e_info(drv, "Resuming after VF err\n");
7651 adapter->vferr_refcount--;
7652 return;
7653 }
7654
7655#endif
c7ccde0f
AD		 7656 if (netif_running(netdev))
7657 ixgbe_up(adapter);
9a799d71
AK		 7658
7659 netif_device_attach(netdev);
9a799d71
AK		 7660}
7661
7662static struct pci_error_handlers ixgbe_err_handler = {
7663 .error_detected = ixgbe_io_error_detected,
7664 .slot_reset = ixgbe_io_slot_reset,
7665 .resume = ixgbe_io_resume,
7666};
7667
7668static struct pci_driver ixgbe_driver = {
7669 .name = ixgbe_driver_name,
7670 .id_table = ixgbe_pci_tbl,
7671 .probe = ixgbe_probe,
7672 .remove = __devexit_p(ixgbe_remove),
7673#ifdef CONFIG_PM
7674 .suspend = ixgbe_suspend,
7675 .resume = ixgbe_resume,
7676#endif
7677 .shutdown = ixgbe_shutdown,
7678 .err_handler = &ixgbe_err_handler
7679};
7680
7681/**
7682 * ixgbe_init_module - Driver Registration Routine
7683 *
7684 * ixgbe_init_module is the first routine called when the driver is
7685 * loaded. All it does is register with the PCI subsystem.
7686 **/
7687static int __init ixgbe_init_module(void)
7688{
7689 int ret;
c7689578 7690 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7691 pr_info("%s\n", ixgbe_copyright);
9a799d71 7692
5dd2d332 7693#ifdef CONFIG_IXGBE_DCA
bd0362dd 7694 dca_register_notify(&dca_notifier);
bd0362dd 7695#endif
5dd2d332 7696
9a799d71
AK		 7697 ret = pci_register_driver(&ixgbe_driver);
7698 return ret;
7699}
b4617240 7700
9a799d71
AK		 7701module_init(ixgbe_init_module);
7702
7703/**
7704 * ixgbe_exit_module - Driver Exit Cleanup Routine
7705 *
7706 * ixgbe_exit_module is called just before the driver is removed
7707 * from memory.
7708 **/
7709static void __exit ixgbe_exit_module(void)
7710{
5dd2d332 7711#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7712 dca_unregister_notify(&dca_notifier);
7713#endif
9a799d71 7714 pci_unregister_driver(&ixgbe_driver);
1a51502b 7715 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7716}
bd0362dd 7717
5dd2d332 7718#ifdef CONFIG_IXGBE_DCA
bd0362dd 7719static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7720 void *p)
bd0362dd
JC		 7721{
7722 int ret_val;
7723
7724 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7725 __ixgbe_notify_dca);
bd0362dd
JC		 7726
7727 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7728}
b453368d 7729
5dd2d332 7730#endif /* CONFIG_IXGBE_DCA */
849c4542 7731
9a799d71
AK		 7732module_exit(ixgbe_exit_module);
7733
7734/* ixgbe_main.c */
Linux kernel - Deliverables
This page took 1.502449 seconds and 5 git commands to generate.