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ixgbe: Stop cacheing if the MNG FW enabled
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
b0483c8f 300 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 301}
302
303void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
304{
305 u32 value;
306
307 /* The following check not only optimizes a bit by not
308 * performing a read on the status register when the
309 * register just read was a status register read that
310 * returned IXGBE_FAILED_READ_REG. It also blocks any
311 * potential recursion.
312 */
313 if (reg == IXGBE_STATUS) {
314 ixgbe_remove_adapter(hw);
315 return;
316 }
317 value = ixgbe_read_reg(hw, IXGBE_STATUS);
318 if (value == IXGBE_FAILED_READ_REG)
319 ixgbe_remove_adapter(hw);
320}
321
14438464
MR		 322static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
323{
324 u16 value;
325
326 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
327 if (value == IXGBE_FAILED_READ_CFG_WORD) {
328 ixgbe_remove_adapter(hw);
329 return true;
330 }
331 return false;
332}
333
334u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
335{
336 struct ixgbe_adapter *adapter = hw->back;
337 u16 value;
338
339 if (ixgbe_removed(hw->hw_addr))
340 return IXGBE_FAILED_READ_CFG_WORD;
341 pci_read_config_word(adapter->pdev, reg, &value);
342 if (value == IXGBE_FAILED_READ_CFG_WORD &&
343 ixgbe_check_cfg_remove(hw, adapter->pdev))
344 return IXGBE_FAILED_READ_CFG_WORD;
345 return value;
346}
347
348#ifdef CONFIG_PCI_IOV
349static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
350{
351 struct ixgbe_adapter *adapter = hw->back;
352 u32 value;
353
354 if (ixgbe_removed(hw->hw_addr))
355 return IXGBE_FAILED_READ_CFG_DWORD;
356 pci_read_config_dword(adapter->pdev, reg, &value);
357 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
358 ixgbe_check_cfg_remove(hw, adapter->pdev))
359 return IXGBE_FAILED_READ_CFG_DWORD;
360 return value;
361}
362#endif /* CONFIG_PCI_IOV */
363
ed19231c
JK		 364void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
365{
366 struct ixgbe_adapter *adapter = hw->back;
367
368 if (ixgbe_removed(hw->hw_addr))
369 return;
370 pci_write_config_word(adapter->pdev, reg, value);
371}
372
7086400d
AD		 373static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
374{
375 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
376
52f33af8 377 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 378 smp_mb__before_clear_bit();
379 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
380}
381
dcd79aeb
TI		 382struct ixgbe_reg_info {
383 u32 ofs;
384 char *name;
385};
386
387static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
388
389 /* General Registers */
390 {IXGBE_CTRL, "CTRL"},
391 {IXGBE_STATUS, "STATUS"},
392 {IXGBE_CTRL_EXT, "CTRL_EXT"},
393
394 /* Interrupt Registers */
395 {IXGBE_EICR, "EICR"},
396
397 /* RX Registers */
398 {IXGBE_SRRCTL(0), "SRRCTL"},
399 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
400 {IXGBE_RDLEN(0), "RDLEN"},
401 {IXGBE_RDH(0), "RDH"},
402 {IXGBE_RDT(0), "RDT"},
403 {IXGBE_RXDCTL(0), "RXDCTL"},
404 {IXGBE_RDBAL(0), "RDBAL"},
405 {IXGBE_RDBAH(0), "RDBAH"},
406
407 /* TX Registers */
408 {IXGBE_TDBAL(0), "TDBAL"},
409 {IXGBE_TDBAH(0), "TDBAH"},
410 {IXGBE_TDLEN(0), "TDLEN"},
411 {IXGBE_TDH(0), "TDH"},
412 {IXGBE_TDT(0), "TDT"},
413 {IXGBE_TXDCTL(0), "TXDCTL"},
414
415 /* List Terminator */
416 {}
417};
418
419
420/*
421 * ixgbe_regdump - register printout routine
422 */
423static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
424{
425 int i = 0, j = 0;
426 char rname[16];
427 u32 regs[64];
428
429 switch (reginfo->ofs) {
430 case IXGBE_SRRCTL(0):
431 for (i = 0; i < 64; i++)
432 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
433 break;
434 case IXGBE_DCA_RXCTRL(0):
435 for (i = 0; i < 64; i++)
436 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
437 break;
438 case IXGBE_RDLEN(0):
439 for (i = 0; i < 64; i++)
440 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
441 break;
442 case IXGBE_RDH(0):
443 for (i = 0; i < 64; i++)
444 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
445 break;
446 case IXGBE_RDT(0):
447 for (i = 0; i < 64; i++)
448 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
449 break;
450 case IXGBE_RXDCTL(0):
451 for (i = 0; i < 64; i++)
452 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
453 break;
454 case IXGBE_RDBAL(0):
455 for (i = 0; i < 64; i++)
456 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
457 break;
458 case IXGBE_RDBAH(0):
459 for (i = 0; i < 64; i++)
460 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
461 break;
462 case IXGBE_TDBAL(0):
463 for (i = 0; i < 64; i++)
464 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
465 break;
466 case IXGBE_TDBAH(0):
467 for (i = 0; i < 64; i++)
468 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
469 break;
470 case IXGBE_TDLEN(0):
471 for (i = 0; i < 64; i++)
472 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
473 break;
474 case IXGBE_TDH(0):
475 for (i = 0; i < 64; i++)
476 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
477 break;
478 case IXGBE_TDT(0):
479 for (i = 0; i < 64; i++)
480 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
481 break;
482 case IXGBE_TXDCTL(0):
483 for (i = 0; i < 64; i++)
484 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
485 break;
486 default:
c7689578 487 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 488 IXGBE_READ_REG(hw, reginfo->ofs));
489 return;
490 }
491
492 for (i = 0; i < 8; i++) {
493 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 494 pr_err("%-15s", rname);
dcd79aeb 495 for (j = 0; j < 8; j++)
c7689578
JP		 496 pr_cont(" %08x", regs[i*8+j]);
497 pr_cont("\n");
dcd79aeb
TI		 498 }
499
500}
501
502/*
503 * ixgbe_dump - Print registers, tx-rings and rx-rings
504 */
505static void ixgbe_dump(struct ixgbe_adapter *adapter)
506{
507 struct net_device *netdev = adapter->netdev;
508 struct ixgbe_hw *hw = &adapter->hw;
509 struct ixgbe_reg_info *reginfo;
510 int n = 0;
511 struct ixgbe_ring *tx_ring;
729739b7 512 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 513 union ixgbe_adv_tx_desc *tx_desc;
514 struct my_u0 { u64 a; u64 b; } *u0;
515 struct ixgbe_ring *rx_ring;
516 union ixgbe_adv_rx_desc *rx_desc;
517 struct ixgbe_rx_buffer *rx_buffer_info;
518 u32 staterr;
519 int i = 0;
520
521 if (!netif_msg_hw(adapter))
522 return;
523
524 /* Print netdevice Info */
525 if (netdev) {
526 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 527 pr_info("Device Name state "
dcd79aeb 528 "trans_start last_rx\n");
c7689578
JP		 529 pr_info("%-15s %016lX %016lX %016lX\n",
530 netdev->name,
531 netdev->state,
532 netdev->trans_start,
533 netdev->last_rx);
dcd79aeb
TI		 534 }
535
536 /* Print Registers */
537 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 538 pr_info(" Register Name Value\n");
dcd79aeb
TI		 539 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
540 reginfo->name; reginfo++) {
541 ixgbe_regdump(hw, reginfo);
542 }
543
544 /* Print TX Ring Summary */
545 if (!netdev || !netif_running(netdev))
546 goto exit;
547
548 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 549 pr_info(" %s %s %s %s\n",
550 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
551 "leng", "ntw", "timestamp");
dcd79aeb
TI		 552 for (n = 0; n < adapter->num_tx_queues; n++) {
553 tx_ring = adapter->tx_ring[n];
729739b7 554 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 555 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 556 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 557 (u64)dma_unmap_addr(tx_buffer, dma),
558 dma_unmap_len(tx_buffer, len),
559 tx_buffer->next_to_watch,
560 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 561 }
562
563 /* Print TX Rings */
564 if (!netif_msg_tx_done(adapter))
565 goto rx_ring_summary;
566
567 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
568
569 /* Transmit Descriptor Formats
570 *
39ac868a 571 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 572 * +--------------------------------------------------------------+
573 * 0 | Buffer Address [63:0] |
574 * +--------------------------------------------------------------+
39ac868a 575 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 576 * +--------------------------------------------------------------+
577 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 578 *
579 * 82598 Advanced Transmit Descriptor (Write-Back Format)
580 * +--------------------------------------------------------------+
581 * 0 | RSV [63:0] |
582 * +--------------------------------------------------------------+
583 * 8 | RSV | STA | NXTSEQ |
584 * +--------------------------------------------------------------+
585 * 63 36 35 32 31 0
586 *
587 * 82599+ Advanced Transmit Descriptor
588 * +--------------------------------------------------------------+
589 * 0 | Buffer Address [63:0] |
590 * +--------------------------------------------------------------+
591 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
592 * +--------------------------------------------------------------+
593 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
594 *
595 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
596 * +--------------------------------------------------------------+
597 * 0 | RSV [63:0] |
598 * +--------------------------------------------------------------+
599 * 8 | RSV | STA | RSV |
600 * +--------------------------------------------------------------+
601 * 63 36 35 32 31 0
dcd79aeb
TI		 602 */
603
604 for (n = 0; n < adapter->num_tx_queues; n++) {
605 tx_ring = adapter->tx_ring[n];
c7689578
JP		 606 pr_info("------------------------------------\n");
607 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
608 pr_info("------------------------------------\n");
8ad88e37
JH		 609 pr_info("%s%s %s %s %s %s\n",
610 "T [desc] [address 63:0 ] ",
611 "[PlPOIdStDDt Ln] [bi->dma ] ",
612 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 613
614 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 615 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 616 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 617 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 618 if (dma_unmap_len(tx_buffer, len) > 0) {
619 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
620 i,
621 le64_to_cpu(u0->a),
622 le64_to_cpu(u0->b),
623 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 624 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 625 tx_buffer->next_to_watch,
626 (u64)tx_buffer->time_stamp,
627 tx_buffer->skb);
628 if (i == tx_ring->next_to_use &&
629 i == tx_ring->next_to_clean)
630 pr_cont(" NTC/U\n");
631 else if (i == tx_ring->next_to_use)
632 pr_cont(" NTU\n");
633 else if (i == tx_ring->next_to_clean)
634 pr_cont(" NTC\n");
635 else
636 pr_cont("\n");
637
638 if (netif_msg_pktdata(adapter) &&
639 tx_buffer->skb)
640 print_hex_dump(KERN_INFO, "",
641 DUMP_PREFIX_ADDRESS, 16, 1,
642 tx_buffer->skb->data,
643 dma_unmap_len(tx_buffer, len),
644 true);
645 }
dcd79aeb
TI		 646 }
647 }
648
649 /* Print RX Rings Summary */
650rx_ring_summary:
651 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 652 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 653 for (n = 0; n < adapter->num_rx_queues; n++) {
654 rx_ring = adapter->rx_ring[n];
c7689578
JP		 655 pr_info("%5d %5X %5X\n",
656 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 657 }
658
659 /* Print RX Rings */
660 if (!netif_msg_rx_status(adapter))
661 goto exit;
662
663 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
664
39ac868a
JH		 665 /* Receive Descriptor Formats
666 *
667 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 668 * 63 1 0
669 * +-----------------------------------------------------+
670 * 0 | Packet Buffer Address [63:1] |A0/NSE|
671 * +----------------------------------------------+------+
672 * 8 | Header Buffer Address [63:1] | DD |
673 * +-----------------------------------------------------+
674 *
675 *
39ac868a 676 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 677 *
678 * 63 48 47 32 31 30 21 20 16 15 4 3 0
679 * +------------------------------------------------------+
39ac868a
JH		 680 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
681 * | Packet | IP | | | | Type | Type |
682 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 683 * +------------------------------------------------------+
684 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
685 * +------------------------------------------------------+
686 * 63 48 47 32 31 20 19 0
39ac868a
JH		 687 *
688 * 82599+ Advanced Receive Descriptor (Read) Format
689 * 63 1 0
690 * +-----------------------------------------------------+
691 * 0 | Packet Buffer Address [63:1] |A0/NSE|
692 * +----------------------------------------------+------+
693 * 8 | Header Buffer Address [63:1] | DD |
694 * +-----------------------------------------------------+
695 *
696 *
697 * 82599+ Advanced Receive Descriptor (Write-Back) Format
698 *
699 * 63 48 47 32 31 30 21 20 17 16 4 3 0
700 * +------------------------------------------------------+
701 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
702 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
703 * |/ Flow Dir Flt ID | | | | | |
704 * +------------------------------------------------------+
705 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
706 * +------------------------------------------------------+
707 * 63 48 47 32 31 20 19 0
dcd79aeb 708 */
39ac868a 709
dcd79aeb
TI		 710 for (n = 0; n < adapter->num_rx_queues; n++) {
711 rx_ring = adapter->rx_ring[n];
c7689578
JP		 712 pr_info("------------------------------------\n");
713 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
714 pr_info("------------------------------------\n");
8ad88e37
JH		 715 pr_info("%s%s%s",
716 "R [desc] [ PktBuf A0] ",
717 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 718 "<-- Adv Rx Read format\n");
8ad88e37
JH		 719 pr_info("%s%s%s",
720 "RWB[desc] [PcsmIpSHl PtRs] ",
721 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 722 "<-- Adv Rx Write-Back format\n");
723
724 for (i = 0; i < rx_ring->count; i++) {
725 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 726 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 727 u0 = (struct my_u0 *)rx_desc;
728 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
729 if (staterr & IXGBE_RXD_STAT_DD) {
730 /* Descriptor Done */
c7689578 731 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 732 "%016llX ---------------- %p", i,
733 le64_to_cpu(u0->a),
734 le64_to_cpu(u0->b),
735 rx_buffer_info->skb);
736 } else {
c7689578 737 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 738 "%016llX %016llX %p", i,
739 le64_to_cpu(u0->a),
740 le64_to_cpu(u0->b),
741 (u64)rx_buffer_info->dma,
742 rx_buffer_info->skb);
743
9c50c035
ET		 744 if (netif_msg_pktdata(adapter) &&
745 rx_buffer_info->dma) {
dcd79aeb
TI		 746 print_hex_dump(KERN_INFO, "",
747 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 748 page_address(rx_buffer_info->page) +
749 rx_buffer_info->page_offset,
f800326d 750 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 751 }
752 }
753
754 if (i == rx_ring->next_to_use)
c7689578 755 pr_cont(" NTU\n");
dcd79aeb 756 else if (i == rx_ring->next_to_clean)
c7689578 757 pr_cont(" NTC\n");
dcd79aeb 758 else
c7689578 759 pr_cont("\n");
dcd79aeb
TI		 760
761 }
762 }
763
764exit:
765 return;
766}
767
5eba3699
AV		 768static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
769{
770 u32 ctrl_ext;
771
772 /* Let firmware take over control of h/w */
773 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 775 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 776}
777
778static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
779{
780 u32 ctrl_ext;
781
782 /* Let firmware know the driver has taken over */
783 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 785 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 786}
9a799d71 787
49ce9c2c 788/**
e8e26350
PW		 789 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
790 * @adapter: pointer to adapter struct
791 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
792 * @queue: queue to map the corresponding interrupt to
793 * @msix_vector: the vector to map to the corresponding queue
794 *
795 */
796static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 797 u8 queue, u8 msix_vector)
9a799d71
AK		 798{
799 u32 ivar, index;
e8e26350
PW		 800 struct ixgbe_hw *hw = &adapter->hw;
801 switch (hw->mac.type) {
802 case ixgbe_mac_82598EB:
803 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
804 if (direction == -1)
805 direction = 0;
806 index = (((direction * 64) + queue) >> 2) & 0x1F;
807 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
808 ivar &= ~(0xFF << (8 * (queue & 0x3)));
809 ivar |= (msix_vector << (8 * (queue & 0x3)));
810 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
811 break;
812 case ixgbe_mac_82599EB:
b93a2226 813 case ixgbe_mac_X540:
e8e26350
PW		 814 if (direction == -1) {
815 /* other causes */
816 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
817 index = ((queue & 1) * 8);
818 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
819 ivar &= ~(0xFF << index);
820 ivar |= (msix_vector << index);
821 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
822 break;
823 } else {
824 /* tx or rx causes */
825 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
826 index = ((16 * (queue & 1)) + (8 * direction));
827 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
828 ivar &= ~(0xFF << index);
829 ivar |= (msix_vector << index);
830 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
831 break;
832 }
833 default:
834 break;
835 }
9a799d71
AK		 836}
837
fe49f04a 838static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 839 u64 qmask)
fe49f04a
AD		 840{
841 u32 mask;
842
bd508178
AD		 843 switch (adapter->hw.mac.type) {
844 case ixgbe_mac_82598EB:
fe49f04a
AD		 845 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
846 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 847 break;
848 case ixgbe_mac_82599EB:
b93a2226 849 case ixgbe_mac_X540:
fe49f04a
AD		 850 mask = (qmask & 0xFFFFFFFF);
851 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
852 mask = (qmask >> 32);
853 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 854 break;
855 default:
856 break;
fe49f04a
AD		 857 }
858}
859
729739b7
AD		 860void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
861 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 862{
729739b7
AD		 863 if (tx_buffer->skb) {
864 dev_kfree_skb_any(tx_buffer->skb);
865 if (dma_unmap_len(tx_buffer, len))
d3d00239 866 dma_unmap_single(ring->dev,
729739b7
AD		 867 dma_unmap_addr(tx_buffer, dma),
868 dma_unmap_len(tx_buffer, len),
869 DMA_TO_DEVICE);
870 } else if (dma_unmap_len(tx_buffer, len)) {
871 dma_unmap_page(ring->dev,
872 dma_unmap_addr(tx_buffer, dma),
873 dma_unmap_len(tx_buffer, len),
874 DMA_TO_DEVICE);
e5a43549 875 }
729739b7
AD		 876 tx_buffer->next_to_watch = NULL;
877 tx_buffer->skb = NULL;
878 dma_unmap_len_set(tx_buffer, len, 0);
879 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 880}
881
943561d3 882static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 883{
884 struct ixgbe_hw *hw = &adapter->hw;
885 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 886 int i;
943561d3 887 u32 data;
c84d324c 888
943561d3
AD		 889 if ((hw->fc.current_mode != ixgbe_fc_full) &&
890 (hw->fc.current_mode != ixgbe_fc_rx_pause))
891 return;
c84d324c 892
943561d3
AD		 893 switch (hw->mac.type) {
894 case ixgbe_mac_82598EB:
895 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
896 break;
897 default:
898 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
899 }
900 hwstats->lxoffrxc += data;
c84d324c 901
943561d3
AD		 902 /* refill credits (no tx hang) if we received xoff */
903 if (!data)
c84d324c 904 return;
943561d3
AD		 905
906 for (i = 0; i < adapter->num_tx_queues; i++)
907 clear_bit(__IXGBE_HANG_CHECK_ARMED,
908 &adapter->tx_ring[i]->state);
909}
910
911static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
912{
913 struct ixgbe_hw *hw = &adapter->hw;
914 struct ixgbe_hw_stats *hwstats = &adapter->stats;
915 u32 xoff[8] = {0};
2afaa00d 916 u8 tc;
943561d3
AD		 917 int i;
918 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
919
920 if (adapter->ixgbe_ieee_pfc)
921 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
922
923 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
924 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 925 return;
943561d3 926 }
c84d324c
JF		 927
928 /* update stats for each tc, only valid with PFC enabled */
929 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 930 u32 pxoffrxc;
931
c84d324c
JF		 932 switch (hw->mac.type) {
933 case ixgbe_mac_82598EB:
2afaa00d 934 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 935 break;
c84d324c 936 default:
2afaa00d 937 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 938 }
2afaa00d
PN		 939 hwstats->pxoffrxc[i] += pxoffrxc;
940 /* Get the TC for given UP */
941 tc = netdev_get_prio_tc_map(adapter->netdev, i);
942 xoff[tc] += pxoffrxc;
c84d324c
JF		 943 }
944
945 /* disarm tx queues that have received xoff frames */
946 for (i = 0; i < adapter->num_tx_queues; i++) {
947 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 948
2afaa00d 949 tc = tx_ring->dcb_tc;
c84d324c
JF		 950 if (xoff[tc])
951 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 952 }
26f23d82
YZ		 953}
954
c84d324c 955static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 956{
7d7ce682 957 return ring->stats.packets;
c84d324c
JF		 958}
959
960static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
961{
2a47fa45
JF		 962 struct ixgbe_adapter *adapter;
963 struct ixgbe_hw *hw;
964 u32 head, tail;
965
966 if (ring->l2_accel_priv)
967 adapter = ring->l2_accel_priv->real_adapter;
968 else
969 adapter = netdev_priv(ring->netdev);
e01c31a5 970
2a47fa45
JF		 971 hw = &adapter->hw;
972 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
973 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 974
975 if (head != tail)
976 return (head < tail) ?
977 tail - head : (tail + ring->count - head);
978
979 return 0;
980}
981
982static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
983{
984 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
985 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
986 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
987 bool ret = false;
988
7d637bcc 989 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 990
991 /*
992 * Check for a hung queue, but be thorough. This verifies
993 * that a transmit has been completed since the previous
994 * check AND there is at least one packet pending. The
995 * ARMED bit is set to indicate a potential hang. The
996 * bit is cleared if a pause frame is received to remove
997 * false hang detection due to PFC or 802.3x frames. By
998 * requiring this to fail twice we avoid races with
999 * pfc clearing the ARMED bit and conditions where we
1000 * run the check_tx_hang logic with a transmit completion
1001 * pending but without time to complete it yet.
1002 */
1003 if ((tx_done_old == tx_done) && tx_pending) {
1004 /* make sure it is true for two checks in a row */
1005 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1006 &tx_ring->state);
1007 } else {
1008 /* update completed stats and continue */
1009 tx_ring->tx_stats.tx_done_old = tx_done;
1010 /* reset the countdown */
1011 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 1012 }
1013
c84d324c 1014 return ret;
9a799d71
AK		 1015}
1016
c83c6cbd
AD		 1017/**
1018 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1019 * @adapter: driver private struct
1020 **/
1021static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1022{
1023
1024 /* Do the reset outside of interrupt context */
1025 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1026 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1027 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1028 ixgbe_service_event_schedule(adapter);
1029 }
1030}
e01c31a5 1031
9a799d71
AK		 1032/**
1033 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1034 * @q_vector: structure containing interrupt and ring information
e01c31a5 1035 * @tx_ring: tx ring to clean
9a799d71 1036 **/
fe49f04a 1037static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1038 struct ixgbe_ring *tx_ring)
9a799d71 1039{
fe49f04a 1040 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1041 struct ixgbe_tx_buffer *tx_buffer;
1042 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1043 unsigned int total_bytes = 0, total_packets = 0;
59224555 1044 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1045 unsigned int i = tx_ring->next_to_clean;
1046
1047 if (test_bit(__IXGBE_DOWN, &adapter->state))
1048 return true;
9a799d71 1049
d3d00239 1050 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1051 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1052 i -= tx_ring->count;
12207e49 1053
729739b7 1054 do {
d3d00239
AD		 1055 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1056
1057 /* if next_to_watch is not set then there is no work pending */
1058 if (!eop_desc)
1059 break;
1060
7f83a9e6 1061 /* prevent any other reads prior to eop_desc */
7e63bf49 1062 read_barrier_depends();
7f83a9e6 1063
d3d00239
AD		 1064 /* if DD is not set pending work has not been completed */
1065 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1066 break;
8ad494b0 1067
d3d00239
AD		 1068 /* clear next_to_watch to prevent false hangs */
1069 tx_buffer->next_to_watch = NULL;
8ad494b0 1070
091a6246
AD		 1071 /* update the statistics for this packet */
1072 total_bytes += tx_buffer->bytecount;
1073 total_packets += tx_buffer->gso_segs;
1074
fd0db0ed
AD		 1075 /* free the skb */
1076 dev_kfree_skb_any(tx_buffer->skb);
1077
729739b7
AD		 1078 /* unmap skb header data */
1079 dma_unmap_single(tx_ring->dev,
1080 dma_unmap_addr(tx_buffer, dma),
1081 dma_unmap_len(tx_buffer, len),
1082 DMA_TO_DEVICE);
1083
fd0db0ed
AD		 1084 /* clear tx_buffer data */
1085 tx_buffer->skb = NULL;
729739b7 1086 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1087
729739b7
AD		 1088 /* unmap remaining buffers */
1089 while (tx_desc != eop_desc) {
d3d00239
AD		 1090 tx_buffer++;
1091 tx_desc++;
8ad494b0 1092 i++;
729739b7
AD		 1093 if (unlikely(!i)) {
1094 i -= tx_ring->count;
d3d00239 1095 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1096 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1097 }
e01c31a5 1098
729739b7
AD		 1099 /* unmap any remaining paged data */
1100 if (dma_unmap_len(tx_buffer, len)) {
1101 dma_unmap_page(tx_ring->dev,
1102 dma_unmap_addr(tx_buffer, dma),
1103 dma_unmap_len(tx_buffer, len),
1104 DMA_TO_DEVICE);
1105 dma_unmap_len_set(tx_buffer, len, 0);
1106 }
1107 }
1108
1109 /* move us one more past the eop_desc for start of next pkt */
1110 tx_buffer++;
1111 tx_desc++;
1112 i++;
1113 if (unlikely(!i)) {
1114 i -= tx_ring->count;
1115 tx_buffer = tx_ring->tx_buffer_info;
1116 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1117 }
1118
1119 /* issue prefetch for next Tx descriptor */
1120 prefetch(tx_desc);
12207e49 1121
729739b7
AD		 1122 /* update budget accounting */
1123 budget--;
1124 } while (likely(budget));
1125
1126 i += tx_ring->count;
9a799d71 1127 tx_ring->next_to_clean = i;
d3d00239 1128 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1129 tx_ring->stats.bytes += total_bytes;
bd198058 1130 tx_ring->stats.packets += total_packets;
d3d00239 1131 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1132 q_vector->tx.total_bytes += total_bytes;
1133 q_vector->tx.total_packets += total_packets;
b953799e 1134
c84d324c
JF		 1135 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1136 /* schedule immediate reset if we believe we hung */
1137 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1138 e_err(drv, "Detected Tx Unit Hang\n"
1139 " Tx Queue <%d>\n"
1140 " TDH, TDT <%x>, <%x>\n"
1141 " next_to_use <%x>\n"
1142 " next_to_clean <%x>\n"
1143 "tx_buffer_info[next_to_clean]\n"
1144 " time_stamp <%lx>\n"
1145 " jiffies <%lx>\n",
1146 tx_ring->queue_index,
1147 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1148 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1149 tx_ring->next_to_use, i,
1150 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1151
1152 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1153
1154 e_info(probe,
1155 "tx hang %d detected on queue %d, resetting adapter\n",
1156 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1157
b953799e 1158 /* schedule immediate reset if we believe we hung */
c83c6cbd 1159 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1160
1161 /* the adapter is about to reset, no point in enabling stuff */
59224555 1162 return true;
b953799e 1163 }
9a799d71 1164
b2d96e0a
AD		 1165 netdev_tx_completed_queue(txring_txq(tx_ring),
1166 total_packets, total_bytes);
1167
e092be60 1168#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1169 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1170 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1171 /* Make sure that anybody stopping the queue after this
1172 * sees the new next_to_clean.
1173 */
1174 smp_mb();
729739b7
AD		 1175 if (__netif_subqueue_stopped(tx_ring->netdev,
1176 tx_ring->queue_index)
1177 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1178 netif_wake_subqueue(tx_ring->netdev,
1179 tx_ring->queue_index);
5b7da515 1180 ++tx_ring->tx_stats.restart_queue;
30eba97a 1181 }
e092be60 1182 }
9a799d71 1183
59224555 1184 return !!budget;
9a799d71
AK		 1185}
1186
5dd2d332 1187#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1188static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1189 struct ixgbe_ring *tx_ring,
33cf09c9 1190 int cpu)
bd0362dd 1191{
33cf09c9 1192 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1193 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1194 u16 reg_offset;
33cf09c9 1195
33cf09c9
AD		 1196 switch (hw->mac.type) {
1197 case ixgbe_mac_82598EB:
bdda1a61 1198 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1199 break;
1200 case ixgbe_mac_82599EB:
b93a2226 1201 case ixgbe_mac_X540:
bdda1a61
AD		 1202 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1203 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1204 break;
1205 default:
bdda1a61
AD		 1206 /* for unknown hardware do not write register */
1207 return;
bd0362dd 1208 }
bdda1a61
AD		 1209
1210 /*
1211 * We can enable relaxed ordering for reads, but not writes when
1212 * DCA is enabled. This is due to a known issue in some chipsets
1213 * which will cause the DCA tag to be cleared.
1214 */
1215 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1216 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1217 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1218
1219 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1220}
1221
bdda1a61
AD		 1222static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1223 struct ixgbe_ring *rx_ring,
33cf09c9 1224 int cpu)
bd0362dd 1225{
33cf09c9 1226 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1227 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1228 u8 reg_idx = rx_ring->reg_idx;
1229
33cf09c9
AD		 1230
1231 switch (hw->mac.type) {
33cf09c9 1232 case ixgbe_mac_82599EB:
b93a2226 1233 case ixgbe_mac_X540:
bdda1a61 1234 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1235 break;
1236 default:
1237 break;
1238 }
bdda1a61
AD		 1239
1240 /*
1241 * We can enable relaxed ordering for reads, but not writes when
1242 * DCA is enabled. This is due to a known issue in some chipsets
1243 * which will cause the DCA tag to be cleared.
1244 */
1245 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1246 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1247
1248 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1249}
1250
1251static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1252{
1253 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1254 struct ixgbe_ring *ring;
bd0362dd 1255 int cpu = get_cpu();
bd0362dd 1256
33cf09c9
AD		 1257 if (q_vector->cpu == cpu)
1258 goto out_no_update;
1259
a557928e 1260 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1261 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1262
a557928e 1263 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1264 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1265
1266 q_vector->cpu = cpu;
1267out_no_update:
bd0362dd
JC		 1268 put_cpu();
1269}
1270
1271static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1272{
1273 int i;
1274
1275 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1276 return;
1277
e35ec126
AD		 1278 /* always use CB2 mode, difference is masked in the CB driver */
1279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1280
49c7ffbe 1281 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1282 adapter->q_vector[i]->cpu = -1;
1283 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1284 }
1285}
1286
1287static int __ixgbe_notify_dca(struct device *dev, void *data)
1288{
c60fbb00 1289 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1290 unsigned long event = *(unsigned long *)data;
1291
2a72c31e 1292 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1293 return 0;
1294
bd0362dd
JC		 1295 switch (event) {
1296 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1297 /* if we're already enabled, don't do it again */
1298 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1299 break;
652f093f 1300 if (dca_add_requester(dev) == 0) {
96b0e0f6 1301 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1302 ixgbe_setup_dca(adapter);
1303 break;
1304 }
1305 /* Fall Through since DCA is disabled. */
1306 case DCA_PROVIDER_REMOVE:
1307 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1308 dca_remove_requester(dev);
1309 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1310 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1311 }
1312 break;
1313 }
1314
652f093f 1315 return 0;
bd0362dd 1316}
67a74ee2 1317
bdda1a61 1318#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1319static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1320 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1321 struct sk_buff *skb)
1322{
8a0da21b 1323 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1324 skb_set_hash(skb,
1325 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1326 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1327}
1328
f800326d 1329#ifdef IXGBE_FCOE
ff886dfc
AD		 1330/**
1331 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1332 * @ring: structure containing ring specific data
ff886dfc
AD		 1333 * @rx_desc: advanced rx descriptor
1334 *
1335 * Returns : true if it is FCoE pkt
1336 */
57efd44c 1337static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1338 union ixgbe_adv_rx_desc *rx_desc)
1339{
1340 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1341
57efd44c 1342 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1343 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1344 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1345 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1346}
1347
f800326d 1348#endif /* IXGBE_FCOE */
e59bd25d
AV		 1349/**
1350 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1351 * @ring: structure containing ring specific data
1352 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1353 * @skb: skb currently being received and modified
1354 **/
8a0da21b 1355static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1356 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1357 struct sk_buff *skb)
9a799d71 1358{
8a0da21b 1359 skb_checksum_none_assert(skb);
9a799d71 1360
712744be 1361 /* Rx csum disabled */
8a0da21b 1362 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1363 return;
e59bd25d
AV		 1364
1365 /* if IP and error */
f56e0cb1
AD		 1366 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1367 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1368 ring->rx_stats.csum_err++;
9a799d71
AK		 1369 return;
1370 }
e59bd25d 1371
f56e0cb1 1372 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1373 return;
1374
f56e0cb1 1375 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1376 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1377
1378 /*
1379 * 82599 errata, UDP frames with a 0 checksum can be marked as
1380 * checksum errors.
1381 */
8a0da21b
AD		 1382 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1383 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1384 return;
1385
8a0da21b 1386 ring->rx_stats.csum_err++;
e59bd25d
AV		 1387 return;
1388 }
1389
9a799d71 1390 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1391 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1392}
1393
84ea2591 1394static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1395{
f56e0cb1 1396 rx_ring->next_to_use = val;
f800326d
AD		 1397
1398 /* update next to alloc since we have filled the ring */
1399 rx_ring->next_to_alloc = val;
e8e26350
PW		 1400 /*
1401 * Force memory writes to complete before letting h/w
1402 * know there are new descriptors to fetch. (Only
1403 * applicable for weak-ordered memory model archs,
1404 * such as IA-64).
1405 */
1406 wmb();
84227bcd 1407 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1408}
1409
f990b79b
AD		 1410static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1411 struct ixgbe_rx_buffer *bi)
1412{
1413 struct page *page = bi->page;
f800326d 1414 dma_addr_t dma = bi->dma;
f990b79b 1415
f800326d
AD		 1416 /* since we are recycling buffers we should seldom need to alloc */
1417 if (likely(dma))
f990b79b
AD		 1418 return true;
1419
f800326d
AD		 1420 /* alloc new page for storage */
1421 if (likely(!page)) {
0614002b
MG		 1422 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1423 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1424 if (unlikely(!page)) {
1425 rx_ring->rx_stats.alloc_rx_page_failed++;
1426 return false;
1427 }
f800326d 1428 bi->page = page;
f990b79b
AD		 1429 }
1430
f800326d
AD		 1431 /* map page for use */
1432 dma = dma_map_page(rx_ring->dev, page, 0,
1433 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1434
1435 /*
1436 * if mapping failed free memory back to system since
1437 * there isn't much point in holding memory we can't use
1438 */
1439 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1440 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1441 bi->page = NULL;
f990b79b 1442
f990b79b
AD		 1443 rx_ring->rx_stats.alloc_rx_page_failed++;
1444 return false;
1445 }
1446
f800326d 1447 bi->dma = dma;
afaa9459 1448 bi->page_offset = 0;
f800326d 1449
f990b79b
AD		 1450 return true;
1451}
1452
9a799d71 1453/**
f990b79b 1454 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1455 * @rx_ring: ring to place buffers on
1456 * @cleaned_count: number of buffers to replace
9a799d71 1457 **/
fc77dc3c 1458void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1459{
9a799d71 1460 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1461 struct ixgbe_rx_buffer *bi;
d5f398ed 1462 u16 i = rx_ring->next_to_use;
9a799d71 1463
f800326d
AD		 1464 /* nothing to do */
1465 if (!cleaned_count)
fc77dc3c
AD		 1466 return;
1467
e4f74028 1468 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1469 bi = &rx_ring->rx_buffer_info[i];
1470 i -= rx_ring->count;
9a799d71 1471
f800326d
AD		 1472 do {
1473 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1474 break;
d5f398ed 1475
f800326d
AD		 1476 /*
1477 * Refresh the desc even if buffer_addrs didn't change
1478 * because each write-back erases this info.
1479 */
1480 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1481
f990b79b
AD		 1482 rx_desc++;
1483 bi++;
9a799d71 1484 i++;
f990b79b 1485 if (unlikely(!i)) {
e4f74028 1486 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1487 bi = rx_ring->rx_buffer_info;
1488 i -= rx_ring->count;
1489 }
1490
1491 /* clear the hdr_addr for the next_to_use descriptor */
1492 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1493
1494 cleaned_count--;
1495 } while (cleaned_count);
7c6e0a43 1496
f990b79b
AD		 1497 i += rx_ring->count;
1498
f56e0cb1 1499 if (rx_ring->next_to_use != i)
84ea2591 1500 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1501}
1502
1d2024f6
AD		 1503/**
1504 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1505 * @data: pointer to the start of the headers
1506 * @max_len: total length of section to find headers in
1507 *
1508 * This function is meant to determine the length of headers that will
1509 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1510 * motivation of doing this is to only perform one pull for IPv4 TCP
1511 * packets so that we can do basic things like calculating the gso_size
1512 * based on the average data per packet.
1513 **/
1514static unsigned int ixgbe_get_headlen(unsigned char *data,
1515 unsigned int max_len)
1516{
1517 union {
1518 unsigned char *network;
1519 /* l2 headers */
1520 struct ethhdr *eth;
1521 struct vlan_hdr *vlan;
1522 /* l3 headers */
1523 struct iphdr *ipv4;
a048b40e 1524 struct ipv6hdr *ipv6;
1d2024f6
AD		 1525 } hdr;
1526 __be16 protocol;
1527 u8 nexthdr = 0; /* default to not TCP */
1528 u8 hlen;
1529
1530 /* this should never happen, but better safe than sorry */
1531 if (max_len < ETH_HLEN)
1532 return max_len;
1533
1534 /* initialize network frame pointer */
1535 hdr.network = data;
1536
1537 /* set first protocol and move network header forward */
1538 protocol = hdr.eth->h_proto;
1539 hdr.network += ETH_HLEN;
1540
1541 /* handle any vlan tag if present */
a1108ffd 1542 if (protocol == htons(ETH_P_8021Q)) {
1d2024f6
AD		 1543 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1544 return max_len;
1545
1546 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1547 hdr.network += VLAN_HLEN;
1548 }
1549
1550 /* handle L3 protocols */
a1108ffd 1551 if (protocol == htons(ETH_P_IP)) {
1d2024f6
AD		 1552 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1553 return max_len;
1554
1555 /* access ihl as a u8 to avoid unaligned access on ia64 */
1556 hlen = (hdr.network[0] & 0x0F) << 2;
1557
1558 /* verify hlen meets minimum size requirements */
1559 if (hlen < sizeof(struct iphdr))
1560 return hdr.network - data;
1561
ed83da12 1562 /* record next protocol if header is present */
20967f42 1563 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1564 nexthdr = hdr.ipv4->protocol;
a1108ffd 1565 } else if (protocol == htons(ETH_P_IPV6)) {
a048b40e
AD		 1566 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1567 return max_len;
1568
1569 /* record next protocol */
1570 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1571 hlen = sizeof(struct ipv6hdr);
f800326d 1572#ifdef IXGBE_FCOE
a1108ffd 1573 } else if (protocol == htons(ETH_P_FCOE)) {
1d2024f6
AD		 1574 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1575 return max_len;
ed83da12 1576 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1577#endif
1578 } else {
1579 return hdr.network - data;
1580 }
1581
ed83da12
AD		 1582 /* relocate pointer to start of L4 header */
1583 hdr.network += hlen;
1584
a048b40e 1585 /* finally sort out TCP/UDP */
1d2024f6
AD		 1586 if (nexthdr == IPPROTO_TCP) {
1587 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1588 return max_len;
1589
1590 /* access doff as a u8 to avoid unaligned access on ia64 */
1591 hlen = (hdr.network[12] & 0xF0) >> 2;
1592
1593 /* verify hlen meets minimum size requirements */
1594 if (hlen < sizeof(struct tcphdr))
1595 return hdr.network - data;
1596
1597 hdr.network += hlen;
a048b40e
AD		 1598 } else if (nexthdr == IPPROTO_UDP) {
1599 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1600 return max_len;
1601
1602 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1603 }
1604
1605 /*
1606 * If everything has gone correctly hdr.network should be the
1607 * data section of the packet and will be the end of the header.
1608 * If not then it probably represents the end of the last recognized
1609 * header.
1610 */
1611 if ((hdr.network - data) < max_len)
1612 return hdr.network - data;
1613 else
1614 return max_len;
1615}
1616
1d2024f6
AD		 1617static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1618 struct sk_buff *skb)
1619{
f800326d 1620 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1621
1622 /* set gso_size to avoid messing up TCP MSS */
1623 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1624 IXGBE_CB(skb)->append_cnt);
96be80ab 1625 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1626}
1627
1628static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1629 struct sk_buff *skb)
1630{
1631 /* if append_cnt is 0 then frame is not RSC */
1632 if (!IXGBE_CB(skb)->append_cnt)
1633 return;
1634
1635 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1636 rx_ring->rx_stats.rsc_flush++;
1637
1638 ixgbe_set_rsc_gso_size(rx_ring, skb);
1639
1640 /* gso_size is computed using append_cnt so always clear it last */
1641 IXGBE_CB(skb)->append_cnt = 0;
1642}
1643
8a0da21b
AD		 1644/**
1645 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1646 * @rx_ring: rx descriptor ring packet is being transacted on
1647 * @rx_desc: pointer to the EOP Rx descriptor
1648 * @skb: pointer to current skb being populated
f8212f97 1649 *
8a0da21b
AD		 1650 * This function checks the ring, descriptor, and packet information in
1651 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1652 * other fields within the skb.
f8212f97 1653 **/
8a0da21b
AD		 1654static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1655 union ixgbe_adv_rx_desc *rx_desc,
1656 struct sk_buff *skb)
f8212f97 1657{
43e95f11
JF		 1658 struct net_device *dev = rx_ring->netdev;
1659
8a0da21b
AD		 1660 ixgbe_update_rsc_stats(rx_ring, skb);
1661
1662 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1663
8a0da21b
AD		 1664 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1665
6cb562d6 1666 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1667
f646968f 1668 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1669 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1670 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1671 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1672 }
1673
8a0da21b 1674 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1675
43e95f11 1676 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1677}
1678
8a0da21b
AD		 1679static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1680 struct sk_buff *skb)
aa80175a 1681{
8a0da21b
AD		 1682 struct ixgbe_adapter *adapter = q_vector->adapter;
1683
b4640030 1684 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1685 netif_receive_skb(skb);
1686 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1687 napi_gro_receive(&q_vector->napi, skb);
1688 else
1689 netif_rx(skb);
aa80175a 1690}
43634e82 1691
f800326d
AD		 1692/**
1693 * ixgbe_is_non_eop - process handling of non-EOP buffers
1694 * @rx_ring: Rx ring being processed
1695 * @rx_desc: Rx descriptor for current buffer
1696 * @skb: Current socket buffer containing buffer in progress
1697 *
1698 * This function updates next to clean. If the buffer is an EOP buffer
1699 * this function exits returning false, otherwise it will place the
1700 * sk_buff in the next buffer to be chained and return true indicating
1701 * that this is in fact a non-EOP buffer.
1702 **/
1703static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1704 union ixgbe_adv_rx_desc *rx_desc,
1705 struct sk_buff *skb)
1706{
1707 u32 ntc = rx_ring->next_to_clean + 1;
1708
1709 /* fetch, update, and store next to clean */
1710 ntc = (ntc < rx_ring->count) ? ntc : 0;
1711 rx_ring->next_to_clean = ntc;
1712
1713 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1714
5a02cbd1
AD		 1715 /* update RSC append count if present */
1716 if (ring_is_rsc_enabled(rx_ring)) {
1717 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1718 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1719
1720 if (unlikely(rsc_enabled)) {
1721 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1722
1723 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1724 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1725
5a02cbd1
AD		 1726 /* update ntc based on RSC value */
1727 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1728 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1729 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1730 }
f800326d
AD		 1731 }
1732
5a02cbd1
AD		 1733 /* if we are the last buffer then there is nothing else to do */
1734 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1735 return false;
1736
f800326d
AD		 1737 /* place skb in next buffer to be received */
1738 rx_ring->rx_buffer_info[ntc].skb = skb;
1739 rx_ring->rx_stats.non_eop_descs++;
1740
1741 return true;
1742}
1743
19861ce2
AD		 1744/**
1745 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1746 * @rx_ring: rx descriptor ring packet is being transacted on
1747 * @skb: pointer to current skb being adjusted
1748 *
1749 * This function is an ixgbe specific version of __pskb_pull_tail. The
1750 * main difference between this version and the original function is that
1751 * this function can make several assumptions about the state of things
1752 * that allow for significant optimizations versus the standard function.
1753 * As a result we can do things like drop a frag and maintain an accurate
1754 * truesize for the skb.
1755 */
1756static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1757 struct sk_buff *skb)
1758{
1759 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1760 unsigned char *va;
1761 unsigned int pull_len;
1762
1763 /*
1764 * it is valid to use page_address instead of kmap since we are
1765 * working with pages allocated out of the lomem pool per
1766 * alloc_page(GFP_ATOMIC)
1767 */
1768 va = skb_frag_address(frag);
1769
1770 /*
1771 * we need the header to contain the greater of either ETH_HLEN or
1772 * 60 bytes if the skb->len is less than 60 for skb_pad.
1773 */
cf3fe7ac 1774 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1775
1776 /* align pull length to size of long to optimize memcpy performance */
1777 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1778
1779 /* update all of the pointers */
1780 skb_frag_size_sub(frag, pull_len);
1781 frag->page_offset += pull_len;
1782 skb->data_len -= pull_len;
1783 skb->tail += pull_len;
19861ce2
AD		 1784}
1785
42073d91
AD		 1786/**
1787 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1788 * @rx_ring: rx descriptor ring packet is being transacted on
1789 * @skb: pointer to current skb being updated
1790 *
1791 * This function provides a basic DMA sync up for the first fragment of an
1792 * skb. The reason for doing this is that the first fragment cannot be
1793 * unmapped until we have reached the end of packet descriptor for a buffer
1794 * chain.
1795 */
1796static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1797 struct sk_buff *skb)
1798{
1799 /* if the page was released unmap it, else just sync our portion */
1800 if (unlikely(IXGBE_CB(skb)->page_released)) {
1801 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1802 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1803 IXGBE_CB(skb)->page_released = false;
1804 } else {
1805 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1806
1807 dma_sync_single_range_for_cpu(rx_ring->dev,
1808 IXGBE_CB(skb)->dma,
1809 frag->page_offset,
1810 ixgbe_rx_bufsz(rx_ring),
1811 DMA_FROM_DEVICE);
1812 }
1813 IXGBE_CB(skb)->dma = 0;
1814}
1815
f800326d
AD		 1816/**
1817 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1818 * @rx_ring: rx descriptor ring packet is being transacted on
1819 * @rx_desc: pointer to the EOP Rx descriptor
1820 * @skb: pointer to current skb being fixed
1821 *
1822 * Check for corrupted packet headers caused by senders on the local L2
1823 * embedded NIC switch not setting up their Tx Descriptors right. These
1824 * should be very rare.
1825 *
1826 * Also address the case where we are pulling data in on pages only
1827 * and as such no data is present in the skb header.
1828 *
1829 * In addition if skb is not at least 60 bytes we need to pad it so that
1830 * it is large enough to qualify as a valid Ethernet frame.
1831 *
1832 * Returns true if an error was encountered and skb was freed.
1833 **/
1834static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1835 union ixgbe_adv_rx_desc *rx_desc,
1836 struct sk_buff *skb)
1837{
f800326d 1838 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1839
1840 /* verify that the packet does not have any known errors */
1841 if (unlikely(ixgbe_test_staterr(rx_desc,
1842 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1843 !(netdev->features & NETIF_F_RXALL))) {
1844 dev_kfree_skb_any(skb);
1845 return true;
1846 }
1847
19861ce2 1848 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1849 if (skb_is_nonlinear(skb))
1850 ixgbe_pull_tail(rx_ring, skb);
f800326d 1851
57efd44c
AD		 1852#ifdef IXGBE_FCOE
1853 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1854 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1855 return false;
1856
1857#endif
f800326d
AD		 1858 /* if skb_pad returns an error the skb was freed */
1859 if (unlikely(skb->len < 60)) {
1860 int pad_len = 60 - skb->len;
1861
1862 if (skb_pad(skb, pad_len))
1863 return true;
1864 __skb_put(skb, pad_len);
1865 }
1866
1867 return false;
1868}
1869
f800326d
AD		 1870/**
1871 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1872 * @rx_ring: rx descriptor ring to store buffers on
1873 * @old_buff: donor buffer to have page reused
1874 *
0549ae20 1875 * Synchronizes page for reuse by the adapter
f800326d
AD		 1876 **/
1877static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1878 struct ixgbe_rx_buffer *old_buff)
1879{
1880 struct ixgbe_rx_buffer *new_buff;
1881 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1882
1883 new_buff = &rx_ring->rx_buffer_info[nta];
1884
1885 /* update, and store next to alloc */
1886 nta++;
1887 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1888
1889 /* transfer page from old buffer to new buffer */
1890 new_buff->page = old_buff->page;
1891 new_buff->dma = old_buff->dma;
0549ae20 1892 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1893
1894 /* sync the buffer for use by the device */
1895 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1896 new_buff->page_offset,
1897 ixgbe_rx_bufsz(rx_ring),
f800326d 1898 DMA_FROM_DEVICE);
f800326d
AD		 1899}
1900
1901/**
1902 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1903 * @rx_ring: rx descriptor ring to transact packets on
1904 * @rx_buffer: buffer containing page to add
1905 * @rx_desc: descriptor containing length of buffer written by hardware
1906 * @skb: sk_buff to place the data into
1907 *
0549ae20
AD		 1908 * This function will add the data contained in rx_buffer->page to the skb.
1909 * This is done either through a direct copy if the data in the buffer is
1910 * less than the skb header size, otherwise it will just attach the page as
1911 * a frag to the skb.
1912 *
1913 * The function will then update the page offset if necessary and return
1914 * true if the buffer can be reused by the adapter.
f800326d 1915 **/
0549ae20 1916static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1917 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1918 union ixgbe_adv_rx_desc *rx_desc,
1919 struct sk_buff *skb)
f800326d 1920{
0549ae20
AD		 1921 struct page *page = rx_buffer->page;
1922 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1923#if (PAGE_SIZE < 8192)
0549ae20 1924 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1925#else
1926 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1927 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1928 ixgbe_rx_bufsz(rx_ring);
1929#endif
0549ae20 1930
cf3fe7ac
AD		 1931 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1932 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1933
1934 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1935
1936 /* we can reuse buffer as-is, just make sure it is local */
1937 if (likely(page_to_nid(page) == numa_node_id()))
1938 return true;
1939
1940 /* this page cannot be reused so discard it */
1941 put_page(page);
1942 return false;
1943 }
1944
0549ae20
AD		 1945 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1946 rx_buffer->page_offset, size, truesize);
1947
09816fbe
AD		 1948 /* avoid re-using remote pages */
1949 if (unlikely(page_to_nid(page) != numa_node_id()))
1950 return false;
1951
1952#if (PAGE_SIZE < 8192)
1953 /* if we are only owner of page we can reuse it */
1954 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1955 return false;
1956
1957 /* flip page offset to other buffer */
1958 rx_buffer->page_offset ^= truesize;
1959
09816fbe
AD		 1960 /*
1961 * since we are the only owner of the page and we need to
1962 * increment it, just set the value to 2 in order to avoid
1963 * an unecessary locked operation
1964 */
1965 atomic_set(&page->_count, 2);
1966#else
1967 /* move offset up to the next cache line */
1968 rx_buffer->page_offset += truesize;
1969
1970 if (rx_buffer->page_offset > last_offset)
1971 return false;
1972
0549ae20
AD		 1973 /* bump ref count on page before it is given to the stack */
1974 get_page(page);
09816fbe 1975#endif
0549ae20
AD		 1976
1977 return true;
f800326d
AD		 1978}
1979
18806c9e
AD		 1980static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1981 union ixgbe_adv_rx_desc *rx_desc)
1982{
1983 struct ixgbe_rx_buffer *rx_buffer;
1984 struct sk_buff *skb;
1985 struct page *page;
1986
1987 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1988 page = rx_buffer->page;
1989 prefetchw(page);
1990
1991 skb = rx_buffer->skb;
1992
1993 if (likely(!skb)) {
1994 void *page_addr = page_address(page) +
1995 rx_buffer->page_offset;
1996
1997 /* prefetch first cache line of first page */
1998 prefetch(page_addr);
1999#if L1_CACHE_BYTES < 128
2000 prefetch(page_addr + L1_CACHE_BYTES);
2001#endif
2002
2003 /* allocate a skb to store the frags */
2004 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2005 IXGBE_RX_HDR_SIZE);
2006 if (unlikely(!skb)) {
2007 rx_ring->rx_stats.alloc_rx_buff_failed++;
2008 return NULL;
2009 }
2010
2011 /*
2012 * we will be copying header into skb->data in
2013 * pskb_may_pull so it is in our interest to prefetch
2014 * it now to avoid a possible cache miss
2015 */
2016 prefetchw(skb->data);
2017
2018 /*
2019 * Delay unmapping of the first packet. It carries the
2020 * header information, HW may still access the header
2021 * after the writeback. Only unmap it when EOP is
2022 * reached
2023 */
2024 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2025 goto dma_sync;
2026
2027 IXGBE_CB(skb)->dma = rx_buffer->dma;
2028 } else {
2029 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2030 ixgbe_dma_sync_frag(rx_ring, skb);
2031
2032dma_sync:
2033 /* we are reusing so sync this buffer for CPU use */
2034 dma_sync_single_range_for_cpu(rx_ring->dev,
2035 rx_buffer->dma,
2036 rx_buffer->page_offset,
2037 ixgbe_rx_bufsz(rx_ring),
2038 DMA_FROM_DEVICE);
2039 }
2040
2041 /* pull page into skb */
2042 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2043 /* hand second half of page back to the ring */
2044 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2045 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2046 /* the page has been released from the ring */
2047 IXGBE_CB(skb)->page_released = true;
2048 } else {
2049 /* we are not reusing the buffer so unmap it */
2050 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2051 ixgbe_rx_pg_size(rx_ring),
2052 DMA_FROM_DEVICE);
2053 }
2054
2055 /* clear contents of buffer_info */
2056 rx_buffer->skb = NULL;
2057 rx_buffer->dma = 0;
2058 rx_buffer->page = NULL;
2059
2060 return skb;
f800326d
AD		 2061}
2062
2063/**
2064 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2065 * @q_vector: structure containing interrupt and ring information
2066 * @rx_ring: rx descriptor ring to transact packets on
2067 * @budget: Total limit on number of packets to process
2068 *
2069 * This function provides a "bounce buffer" approach to Rx interrupt
2070 * processing. The advantage to this is that on systems that have
2071 * expensive overhead for IOMMU access this provides a means of avoiding
2072 * it by maintaining the mapping of the page to the syste.
2073 *
5a85e737 2074 * Returns amount of work completed
f800326d 2075 **/
5a85e737 2076static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2077 struct ixgbe_ring *rx_ring,
f4de00ed 2078 const int budget)
9a799d71 2079{
d2f4fbe2 2080 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2081#ifdef IXGBE_FCOE
f800326d 2082 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2083 int ddp_bytes;
2084 unsigned int mss = 0;
3d8fd385 2085#endif /* IXGBE_FCOE */
f800326d 2086 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2087
fdabfc8a 2088 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2089 union ixgbe_adv_rx_desc *rx_desc;
2090 struct sk_buff *skb;
f800326d
AD		 2091
2092 /* return some buffers to hardware, one at a time is too slow */
2093 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2094 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2095 cleaned_count = 0;
2096 }
2097
18806c9e 2098 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2099
2100 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2101 break;
9a799d71 2102
f800326d
AD		 2103 /*
2104 * This memory barrier is needed to keep us from reading
2105 * any other fields out of the rx_desc until we know the
2106 * RXD_STAT_DD bit is set
2107 */
2108 rmb();
9a799d71 2109
18806c9e
AD		 2110 /* retrieve a buffer from the ring */
2111 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2112
18806c9e
AD		 2113 /* exit if we failed to retrieve a buffer */
2114 if (!skb)
2115 break;
9a799d71 2116
9a799d71 2117 cleaned_count++;
f8212f97 2118
f800326d
AD		 2119 /* place incomplete frames back on ring for completion */
2120 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2121 continue;
c267fc16 2122
f800326d
AD		 2123 /* verify the packet layout is correct */
2124 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2125 continue;
9a799d71 2126
d2f4fbe2
AV		 2127 /* probably a little skewed due to removing CRC */
2128 total_rx_bytes += skb->len;
d2f4fbe2 2129
8a0da21b
AD		 2130 /* populate checksum, timestamp, VLAN, and protocol */
2131 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2132
332d4a7d
YZ		 2133#ifdef IXGBE_FCOE
2134 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2135 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2136 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2137 /* include DDPed FCoE data */
2138 if (ddp_bytes > 0) {
2139 if (!mss) {
2140 mss = rx_ring->netdev->mtu -
2141 sizeof(struct fcoe_hdr) -
2142 sizeof(struct fc_frame_header) -
2143 sizeof(struct fcoe_crc_eof);
2144 if (mss > 512)
2145 mss &= ~511;
2146 }
2147 total_rx_bytes += ddp_bytes;
2148 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2149 mss);
2150 }
63d635b2
AD		 2151 if (!ddp_bytes) {
2152 dev_kfree_skb_any(skb);
f800326d 2153 continue;
63d635b2 2154 }
3d8fd385 2155 }
f800326d 2156
332d4a7d 2157#endif /* IXGBE_FCOE */
8b80cda5 2158 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2159 ixgbe_rx_skb(q_vector, skb);
9a799d71 2160
f800326d 2161 /* update budget accounting */
f4de00ed 2162 total_rx_packets++;
fdabfc8a 2163 }
9a799d71 2164
c267fc16
AD		 2165 u64_stats_update_begin(&rx_ring->syncp);
2166 rx_ring->stats.packets += total_rx_packets;
2167 rx_ring->stats.bytes += total_rx_bytes;
2168 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2169 q_vector->rx.total_packets += total_rx_packets;
2170 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2171
f800326d
AD		 2172 if (cleaned_count)
2173 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2174
5a85e737 2175 return total_rx_packets;
9a799d71
AK		 2176}
2177
e0d1095a 2178#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2179/* must be called with local_bh_disable()d */
2180static int ixgbe_low_latency_recv(struct napi_struct *napi)
2181{
2182 struct ixgbe_q_vector *q_vector =
2183 container_of(napi, struct ixgbe_q_vector, napi);
2184 struct ixgbe_adapter *adapter = q_vector->adapter;
2185 struct ixgbe_ring *ring;
2186 int found = 0;
2187
2188 if (test_bit(__IXGBE_DOWN, &adapter->state))
2189 return LL_FLUSH_FAILED;
2190
2191 if (!ixgbe_qv_lock_poll(q_vector))
2192 return LL_FLUSH_BUSY;
2193
2194 ixgbe_for_each_ring(ring, q_vector->rx) {
2195 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2196#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2197 if (found)
2198 ring->stats.cleaned += found;
2199 else
2200 ring->stats.misses++;
2201#endif
5a85e737
ET		 2202 if (found)
2203 break;
2204 }
2205
2206 ixgbe_qv_unlock_poll(q_vector);
2207
2208 return found;
2209}
e0d1095a 2210#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2211
9a799d71
AK		 2212/**
2213 * ixgbe_configure_msix - Configure MSI-X hardware
2214 * @adapter: board private structure
2215 *
2216 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2217 * interrupts.
2218 **/
2219static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2220{
021230d4 2221 struct ixgbe_q_vector *q_vector;
49c7ffbe 2222 int v_idx;
021230d4 2223 u32 mask;
9a799d71 2224
8e34d1aa
AD		 2225 /* Populate MSIX to EITR Select */
2226 if (adapter->num_vfs > 32) {
2227 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2229 }
2230
4df10466
JB		 2231 /*
2232 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2233 * corresponding register.
2234 */
49c7ffbe 2235 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2236 struct ixgbe_ring *ring;
7a921c93 2237 q_vector = adapter->q_vector[v_idx];
021230d4 2238
a557928e 2239 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2240 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2241
a557928e 2242 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2243 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2244
fe49f04a 2245 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2246 }
2247
bd508178
AD		 2248 switch (adapter->hw.mac.type) {
2249 case ixgbe_mac_82598EB:
e8e26350 2250 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2251 v_idx);
bd508178
AD		 2252 break;
2253 case ixgbe_mac_82599EB:
b93a2226 2254 case ixgbe_mac_X540:
e8e26350 2255 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2256 break;
bd508178
AD		 2257 default:
2258 break;
2259 }
021230d4
AV		 2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2261
41fb9248 2262 /* set up to autoclear timer, and the vectors */
021230d4 2263 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2264 mask &= ~(IXGBE_EIMS_OTHER |
2265 IXGBE_EIMS_MAILBOX |
2266 IXGBE_EIMS_LSC);
2267
021230d4 2268 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2269}
2270
f494e8fa
AV		 2271enum latency_range {
2272 lowest_latency = 0,
2273 low_latency = 1,
2274 bulk_latency = 2,
2275 latency_invalid = 255
2276};
2277
2278/**
2279 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2280 * @q_vector: structure containing interrupt and ring information
2281 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2282 *
2283 * Stores a new ITR value based on packets and byte
2284 * counts during the last interrupt. The advantage of per interrupt
2285 * computation is faster updates and more accurate ITR for the current
2286 * traffic pattern. Constants in this function were computed
2287 * based on theoretical maximum wire speed and thresholds were set based
2288 * on testing data as well as attempting to minimize response time
2289 * while increasing bulk throughput.
2290 * this functionality is controlled by the InterruptThrottleRate module
2291 * parameter (see ixgbe_param.c)
2292 **/
bd198058
AD		 2293static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2294 struct ixgbe_ring_container *ring_container)
f494e8fa 2295{
bd198058
AD		 2296 int bytes = ring_container->total_bytes;
2297 int packets = ring_container->total_packets;
2298 u32 timepassed_us;
621bd70e 2299 u64 bytes_perint;
bd198058 2300 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2301
2302 if (packets == 0)
bd198058 2303 return;
f494e8fa
AV		 2304
2305 /* simple throttlerate management
621bd70e
AD		 2306 * 0-10MB/s lowest (100000 ints/s)
2307 * 10-20MB/s low (20000 ints/s)
2308 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2309 */
2310 /* what was last interrupt timeslice? */
d5bf4f67 2311 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2312 if (timepassed_us == 0)
2313 return;
2314
f494e8fa
AV		 2315 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2316
2317 switch (itr_setting) {
2318 case lowest_latency:
621bd70e 2319 if (bytes_perint > 10)
bd198058 2320 itr_setting = low_latency;
f494e8fa
AV		 2321 break;
2322 case low_latency:
621bd70e 2323 if (bytes_perint > 20)
bd198058 2324 itr_setting = bulk_latency;
621bd70e 2325 else if (bytes_perint <= 10)
bd198058 2326 itr_setting = lowest_latency;
f494e8fa
AV		 2327 break;
2328 case bulk_latency:
621bd70e 2329 if (bytes_perint <= 20)
bd198058 2330 itr_setting = low_latency;
f494e8fa
AV		 2331 break;
2332 }
2333
bd198058
AD		 2334 /* clear work counters since we have the values we need */
2335 ring_container->total_bytes = 0;
2336 ring_container->total_packets = 0;
2337
2338 /* write updated itr to ring container */
2339 ring_container->itr = itr_setting;
f494e8fa
AV		 2340}
2341
509ee935
JB		 2342/**
2343 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2344 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2345 *
2346 * This function is made to be called by ethtool and by the driver
2347 * when it needs to update EITR registers at runtime. Hardware
2348 * specific quirks/differences are taken care of here.
2349 */
fe49f04a 2350void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2351{
fe49f04a 2352 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2353 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2354 int v_idx = q_vector->v_idx;
5d967eb7 2355 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2356
bd508178
AD		 2357 switch (adapter->hw.mac.type) {
2358 case ixgbe_mac_82598EB:
509ee935
JB		 2359 /* must write high and low 16 bits to reset counter */
2360 itr_reg |= (itr_reg << 16);
bd508178
AD		 2361 break;
2362 case ixgbe_mac_82599EB:
b93a2226 2363 case ixgbe_mac_X540:
509ee935
JB		 2364 /*
2365 * set the WDIS bit to not clear the timer bits and cause an
2366 * immediate assertion of the interrupt
2367 */
2368 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2369 break;
2370 default:
2371 break;
509ee935
JB		 2372 }
2373 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2374}
2375
bd198058 2376static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2377{
d5bf4f67 2378 u32 new_itr = q_vector->itr;
bd198058 2379 u8 current_itr;
f494e8fa 2380
bd198058
AD		 2381 ixgbe_update_itr(q_vector, &q_vector->tx);
2382 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2383
08c8833b 2384 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2385
2386 switch (current_itr) {
2387 /* counts and packets in update_itr are dependent on these numbers */
2388 case lowest_latency:
d5bf4f67 2389 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2390 break;
2391 case low_latency:
d5bf4f67 2392 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2393 break;
2394 case bulk_latency:
d5bf4f67 2395 new_itr = IXGBE_8K_ITR;
f494e8fa 2396 break;
bd198058
AD		 2397 default:
2398 break;
f494e8fa
AV		 2399 }
2400
d5bf4f67 2401 if (new_itr != q_vector->itr) {
fe49f04a 2402 /* do an exponential smoothing */
d5bf4f67
ET		 2403 new_itr = (10 * new_itr * q_vector->itr) /
2404 ((9 * new_itr) + q_vector->itr);
509ee935 2405
bd198058 2406 /* save the algorithm value here */
5d967eb7 2407 q_vector->itr = new_itr;
fe49f04a
AD		 2408
2409 ixgbe_write_eitr(q_vector);
f494e8fa 2410 }
f494e8fa
AV		 2411}
2412
119fc60a 2413/**
de88eeeb 2414 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2415 * @adapter: pointer to adapter
119fc60a 2416 **/
f0f9778d 2417static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2418{
119fc60a
MC		 2419 struct ixgbe_hw *hw = &adapter->hw;
2420 u32 eicr = adapter->interrupt_event;
2421
f0f9778d 2422 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2423 return;
2424
f0f9778d
AD		 2425 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2426 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2427 return;
2428
2429 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2430
7ca647bd 2431 switch (hw->device_id) {
f0f9778d
AD		 2432 case IXGBE_DEV_ID_82599_T3_LOM:
2433 /*
2434 * Since the warning interrupt is for both ports
2435 * we don't have to check if:
2436 * - This interrupt wasn't for our port.
2437 * - We may have missed the interrupt so always have to
2438 * check if we got a LSC
2439 */
2440 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2441 !(eicr & IXGBE_EICR_LSC))
2442 return;
2443
2444 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2445 u32 speed;
f0f9778d 2446 bool link_up = false;
7ca647bd 2447
3d292265 2448 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2449
f0f9778d
AD		 2450 if (link_up)
2451 return;
2452 }
2453
2454 /* Check if this is not due to overtemp */
2455 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2456 return;
2457
2458 break;
7ca647bd
JP		 2459 default:
2460 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2461 return;
7ca647bd 2462 break;
119fc60a 2463 }
7ca647bd
JP		 2464 e_crit(drv,
2465 "Network adapter has been stopped because it has over heated. "
2466 "Restart the computer. If the problem persists, "
2467 "power off the system and replace the adapter\n");
f0f9778d
AD		 2468
2469 adapter->interrupt_event = 0;
119fc60a
MC		 2470}
2471
0befdb3e
JB		 2472static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2473{
2474 struct ixgbe_hw *hw = &adapter->hw;
2475
2476 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2477 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2478 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2479 /* write to clear the interrupt */
2480 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2481 }
2482}
cf8280ee 2483
4f51bf70
JK		 2484static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2485{
2486 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2487 return;
2488
2489 switch (adapter->hw.mac.type) {
2490 case ixgbe_mac_82599EB:
2491 /*
2492 * Need to check link state so complete overtemp check
2493 * on service task
2494 */
2495 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2496 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2497 adapter->interrupt_event = eicr;
2498 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2499 ixgbe_service_event_schedule(adapter);
2500 return;
2501 }
2502 return;
2503 case ixgbe_mac_X540:
2504 if (!(eicr & IXGBE_EICR_TS))
2505 return;
2506 break;
2507 default:
2508 return;
2509 }
2510
2511 e_crit(drv,
2512 "Network adapter has been stopped because it has over heated. "
2513 "Restart the computer. If the problem persists, "
2514 "power off the system and replace the adapter\n");
2515}
2516
e8e26350
PW		 2517static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2518{
2519 struct ixgbe_hw *hw = &adapter->hw;
2520
73c4b7cd
AD		 2521 if (eicr & IXGBE_EICR_GPI_SDP2) {
2522 /* Clear the interrupt */
2523 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2524 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2525 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2526 ixgbe_service_event_schedule(adapter);
2527 }
73c4b7cd
AD		 2528 }
2529
e8e26350
PW		 2530 if (eicr & IXGBE_EICR_GPI_SDP1) {
2531 /* Clear the interrupt */
2532 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2533 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2534 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2535 ixgbe_service_event_schedule(adapter);
2536 }
e8e26350
PW		 2537 }
2538}
2539
cf8280ee
JB		 2540static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2541{
2542 struct ixgbe_hw *hw = &adapter->hw;
2543
2544 adapter->lsc_int++;
2545 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2546 adapter->link_check_timeout = jiffies;
2547 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2548 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2549 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2550 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2551 }
2552}
2553
fe49f04a
AD		 2554static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2555 u64 qmask)
2556{
2557 u32 mask;
bd508178 2558 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2559
bd508178
AD		 2560 switch (hw->mac.type) {
2561 case ixgbe_mac_82598EB:
fe49f04a 2562 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2563 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2564 break;
2565 case ixgbe_mac_82599EB:
b93a2226 2566 case ixgbe_mac_X540:
fe49f04a 2567 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2568 if (mask)
2569 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2570 mask = (qmask >> 32);
bd508178
AD		 2571 if (mask)
2572 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2573 break;
2574 default:
2575 break;
fe49f04a
AD		 2576 }
2577 /* skip the flush */
2578}
2579
2580static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2581 u64 qmask)
fe49f04a
AD		 2582{
2583 u32 mask;
bd508178 2584 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2585
bd508178
AD		 2586 switch (hw->mac.type) {
2587 case ixgbe_mac_82598EB:
fe49f04a 2588 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2589 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2590 break;
2591 case ixgbe_mac_82599EB:
b93a2226 2592 case ixgbe_mac_X540:
fe49f04a 2593 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2594 if (mask)
2595 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2596 mask = (qmask >> 32);
bd508178
AD		 2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2599 break;
2600 default:
2601 break;
fe49f04a
AD		 2602 }
2603 /* skip the flush */
2604}
2605
021230d4 2606/**
2c4af694
AD		 2607 * ixgbe_irq_enable - Enable default interrupt generation settings
2608 * @adapter: board private structure
021230d4 2609 **/
2c4af694
AD		 2610static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2611 bool flush)
9a799d71 2612{
2c4af694 2613 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2614
2c4af694
AD		 2615 /* don't reenable LSC while waiting for link */
2616 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2617 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2618
2c4af694 2619 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2620 switch (adapter->hw.mac.type) {
2621 case ixgbe_mac_82599EB:
2622 mask |= IXGBE_EIMS_GPI_SDP0;
2623 break;
2624 case ixgbe_mac_X540:
2625 mask |= IXGBE_EIMS_TS;
2626 break;
2627 default:
2628 break;
2629 }
2c4af694
AD		 2630 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2631 mask |= IXGBE_EIMS_GPI_SDP1;
2632 switch (adapter->hw.mac.type) {
2633 case ixgbe_mac_82599EB:
2c4af694
AD		 2634 mask |= IXGBE_EIMS_GPI_SDP1;
2635 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2636 case ixgbe_mac_X540:
2637 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2638 mask |= IXGBE_EIMS_MAILBOX;
2639 break;
2640 default:
2641 break;
9a799d71 2642 }
db0677fa 2643
db0677fa
JK		 2644 if (adapter->hw.mac.type == ixgbe_mac_X540)
2645 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2646
2c4af694
AD		 2647 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2648 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2649 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2650
2c4af694
AD		 2651 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2652 if (queues)
2653 ixgbe_irq_enable_queues(adapter, ~0);
2654 if (flush)
2655 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2656}
2657
2c4af694 2658static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2659{
a65151ba 2660 struct ixgbe_adapter *adapter = data;
9a799d71 2661 struct ixgbe_hw *hw = &adapter->hw;
54037505 2662 u32 eicr;
91281fd3 2663
54037505
DS		 2664 /*
2665 * Workaround for Silicon errata. Use clear-by-write instead
2666 * of clear-by-read. Reading with EICS will return the
2667 * interrupt causes without clearing, which later be done
2668 * with the write to EICR.
2669 */
2670 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2671
2672 /* The lower 16bits of the EICR register are for the queue interrupts
2673 * which should be masked here in order to not accidently clear them if
2674 * the bits are high when ixgbe_msix_other is called. There is a race
2675 * condition otherwise which results in possible performance loss
2676 * especially if the ixgbe_msix_other interrupt is triggering
2677 * consistently (as it would when PPS is turned on for the X540 device)
2678 */
2679 eicr &= 0xFFFF0000;
2680
54037505 2681 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2682
cf8280ee
JB		 2683 if (eicr & IXGBE_EICR_LSC)
2684 ixgbe_check_lsc(adapter);
f0848276 2685
1cdd1ec8
GR		 2686 if (eicr & IXGBE_EICR_MAILBOX)
2687 ixgbe_msg_task(adapter);
efe3d3c8 2688
bd508178
AD		 2689 switch (hw->mac.type) {
2690 case ixgbe_mac_82599EB:
b93a2226 2691 case ixgbe_mac_X540:
d773ce2d
DS		 2692 if (eicr & IXGBE_EICR_ECC) {
2693 e_info(link, "Received ECC Err, initiating reset\n");
2694 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2695 ixgbe_service_event_schedule(adapter);
2696 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2697 }
c4cf55e5
PWJ		 2698 /* Handle Flow Director Full threshold interrupt */
2699 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2700 int reinit_count = 0;
c4cf55e5 2701 int i;
c4cf55e5 2702 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2703 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2704 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2705 &ring->state))
2706 reinit_count++;
2707 }
2708 if (reinit_count) {
2709 /* no more flow director interrupts until after init */
2710 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2711 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2712 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2713 }
2714 }
f0f9778d 2715 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2716 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2717 break;
2718 default:
2719 break;
c4cf55e5 2720 }
f0848276 2721
bd508178 2722 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2723
db0677fa
JK		 2724 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2725 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2726
7086400d 2727 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2728 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2729 ixgbe_irq_enable(adapter, false, false);
f0848276 2730
9a799d71 2731 return IRQ_HANDLED;
f0848276 2732}
91281fd3 2733
4ff7fb12 2734static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2735{
021230d4 2736 struct ixgbe_q_vector *q_vector = data;
91281fd3 2737
9b471446 2738 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2739
4ff7fb12
AD		 2740 if (q_vector->rx.ring || q_vector->tx.ring)
2741 napi_schedule(&q_vector->napi);
91281fd3 2742
9a799d71 2743 return IRQ_HANDLED;
91281fd3
AD		 2744}
2745
eb01b975
AD		 2746/**
2747 * ixgbe_poll - NAPI Rx polling callback
2748 * @napi: structure for representing this polling device
2749 * @budget: how many packets driver is allowed to clean
2750 *
2751 * This function is used for legacy and MSI, NAPI mode
2752 **/
8af3c33f 2753int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2754{
2755 struct ixgbe_q_vector *q_vector =
2756 container_of(napi, struct ixgbe_q_vector, napi);
2757 struct ixgbe_adapter *adapter = q_vector->adapter;
2758 struct ixgbe_ring *ring;
2759 int per_ring_budget;
2760 bool clean_complete = true;
2761
2762#ifdef CONFIG_IXGBE_DCA
2763 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2764 ixgbe_update_dca(q_vector);
2765#endif
2766
2767 ixgbe_for_each_ring(ring, q_vector->tx)
2768 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2769
5a85e737
ET		 2770 if (!ixgbe_qv_lock_napi(q_vector))
2771 return budget;
2772
eb01b975
AD		 2773 /* attempt to distribute budget to each queue fairly, but don't allow
2774 * the budget to go below 1 because we'll exit polling */
2775 if (q_vector->rx.count > 1)
2776 per_ring_budget = max(budget/q_vector->rx.count, 1);
2777 else
2778 per_ring_budget = budget;
2779
2780 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2781 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2782 per_ring_budget) < per_ring_budget);
eb01b975 2783
5a85e737 2784 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2785 /* If all work not completed, return budget and keep polling */
2786 if (!clean_complete)
2787 return budget;
2788
2789 /* all work done, exit the polling mode */
2790 napi_complete(napi);
2791 if (adapter->rx_itr_setting & 1)
2792 ixgbe_set_itr(q_vector);
2793 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2794 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2795
2796 return 0;
2797}
2798
021230d4
AV		 2799/**
2800 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2801 * @adapter: board private structure
2802 *
2803 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2804 * interrupts from the kernel.
2805 **/
2806static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2807{
2808 struct net_device *netdev = adapter->netdev;
207867f5 2809 int vector, err;
e8e9f696 2810 int ri = 0, ti = 0;
021230d4 2811
49c7ffbe 2812 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2813 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2814 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2815
4ff7fb12 2816 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2817 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2818 "%s-%s-%d", netdev->name, "TxRx", ri++);
2819 ti++;
2820 } else if (q_vector->rx.ring) {
9fe93afd 2821 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2822 "%s-%s-%d", netdev->name, "rx", ri++);
2823 } else if (q_vector->tx.ring) {
9fe93afd 2824 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2825 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2826 } else {
2827 /* skip this unused q_vector */
2828 continue;
32aa77a4 2829 }
207867f5
AD		 2830 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2831 q_vector->name, q_vector);
9a799d71 2832 if (err) {
396e799c 2833 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2834 "Error: %d\n", err);
021230d4 2835 goto free_queue_irqs;
9a799d71 2836 }
207867f5
AD		 2837 /* If Flow Director is enabled, set interrupt affinity */
2838 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2839 /* assign the mask for this irq */
2840 irq_set_affinity_hint(entry->vector,
de88eeeb 2841 &q_vector->affinity_mask);
207867f5 2842 }
9a799d71
AK		 2843 }
2844
021230d4 2845 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2846 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2847 if (err) {
de88eeeb 2848 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2849 goto free_queue_irqs;
9a799d71
AK		 2850 }
2851
9a799d71
AK		 2852 return 0;
2853
021230d4 2854free_queue_irqs:
207867f5
AD		 2855 while (vector) {
2856 vector--;
2857 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2858 NULL);
2859 free_irq(adapter->msix_entries[vector].vector,
2860 adapter->q_vector[vector]);
2861 }
021230d4
AV		 2862 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2863 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2864 kfree(adapter->msix_entries);
2865 adapter->msix_entries = NULL;
9a799d71
AK		 2866 return err;
2867}
2868
2869/**
021230d4 2870 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2871 * @irq: interrupt number
2872 * @data: pointer to a network interface device structure
9a799d71
AK		 2873 **/
2874static irqreturn_t ixgbe_intr(int irq, void *data)
2875{
a65151ba 2876 struct ixgbe_adapter *adapter = data;
9a799d71 2877 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2878 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2879 u32 eicr;
2880
54037505 2881 /*
24ddd967 2882 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2883 * before the read of EICR.
2884 */
2885 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2886
021230d4 2887 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2888 * therefore no explicit interrupt disable is necessary */
021230d4 2889 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2890 if (!eicr) {
6af3b9eb
ET		 2891 /*
2892 * shared interrupt alert!
f47cf66e 2893 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2894 * have disabled interrupts due to EIAM
2895 * finish the workaround of silicon errata on 82598. Unmask
2896 * the interrupt that we masked before the EICR read.
2897 */
2898 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2899 ixgbe_irq_enable(adapter, true, true);
9a799d71 2900 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2901 }
9a799d71 2902
cf8280ee
JB		 2903 if (eicr & IXGBE_EICR_LSC)
2904 ixgbe_check_lsc(adapter);
021230d4 2905
bd508178
AD		 2906 switch (hw->mac.type) {
2907 case ixgbe_mac_82599EB:
e8e26350 2908 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2909 /* Fall through */
2910 case ixgbe_mac_X540:
d773ce2d
DS		 2911 if (eicr & IXGBE_EICR_ECC) {
2912 e_info(link, "Received ECC Err, initiating reset\n");
2913 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2914 ixgbe_service_event_schedule(adapter);
2915 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2916 }
4f51bf70 2917 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2918 break;
2919 default:
2920 break;
2921 }
e8e26350 2922
0befdb3e 2923 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2924 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2925 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2926
b9f6ed2b
AD		 2927 /* would disable interrupts here but EIAM disabled it */
2928 napi_schedule(&q_vector->napi);
9a799d71 2929
6af3b9eb
ET		 2930 /*
2931 * re-enable link(maybe) and non-queue interrupts, no flush.
2932 * ixgbe_poll will re-enable the queue interrupts
2933 */
6af3b9eb
ET		 2934 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2935 ixgbe_irq_enable(adapter, false, false);
2936
9a799d71
AK		 2937 return IRQ_HANDLED;
2938}
2939
2940/**
2941 * ixgbe_request_irq - initialize interrupts
2942 * @adapter: board private structure
2943 *
2944 * Attempts to configure interrupts using the best available
2945 * capabilities of the hardware and kernel.
2946 **/
021230d4 2947static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2948{
2949 struct net_device *netdev = adapter->netdev;
021230d4 2950 int err;
9a799d71 2951
4cc6df29 2952 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2953 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2954 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2955 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2956 netdev->name, adapter);
4cc6df29 2957 else
a0607fd3 2958 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2959 netdev->name, adapter);
9a799d71 2960
de88eeeb 2961 if (err)
396e799c 2962 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2963
9a799d71
AK		 2964 return err;
2965}
2966
2967static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2968{
49c7ffbe 2969 int vector;
9a799d71 2970
49c7ffbe
AD		 2971 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2972 free_irq(adapter->pdev->irq, adapter);
2973 return;
2974 }
4cc6df29 2975
49c7ffbe
AD		 2976 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2977 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2978 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2979
49c7ffbe
AD		 2980 /* free only the irqs that were actually requested */
2981 if (!q_vector->rx.ring && !q_vector->tx.ring)
2982 continue;
207867f5 2983
49c7ffbe
AD		 2984 /* clear the affinity_mask in the IRQ descriptor */
2985 irq_set_affinity_hint(entry->vector, NULL);
2986
2987 free_irq(entry->vector, q_vector);
9a799d71 2988 }
49c7ffbe
AD		 2989
2990 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2991}
2992
22d5a71b
JB		 2993/**
2994 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2995 * @adapter: board private structure
2996 **/
2997static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2998{
bd508178
AD		 2999 switch (adapter->hw.mac.type) {
3000 case ixgbe_mac_82598EB:
835462fc 3001 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3002 break;
3003 case ixgbe_mac_82599EB:
b93a2226 3004 case ixgbe_mac_X540:
835462fc
NS		 3005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3007 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3008 break;
3009 default:
3010 break;
22d5a71b
JB		 3011 }
3012 IXGBE_WRITE_FLUSH(&adapter->hw);
3013 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3014 int vector;
3015
3016 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3017 synchronize_irq(adapter->msix_entries[vector].vector);
3018
3019 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3020 } else {
3021 synchronize_irq(adapter->pdev->irq);
3022 }
3023}
3024
9a799d71
AK		 3025/**
3026 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3027 *
3028 **/
3029static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3030{
d5bf4f67 3031 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3032
d5bf4f67 3033 ixgbe_write_eitr(q_vector);
9a799d71 3034
e8e26350
PW		 3035 ixgbe_set_ivar(adapter, 0, 0, 0);
3036 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3037
396e799c 3038 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3039}
3040
43e69bf0
AD		 3041/**
3042 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3043 * @adapter: board private structure
3044 * @ring: structure containing ring specific data
3045 *
3046 * Configure the Tx descriptor ring after a reset.
3047 **/
84418e3b
AD		 3048void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
43e69bf0
AD		 3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 u64 tdba = ring->dma;
2f1860b8 3053 int wait_loop = 10;
b88c6de2 3054 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3055 u8 reg_idx = ring->reg_idx;
43e69bf0 3056
2f1860b8 3057 /* disable queue to avoid issues while updating state */
b88c6de2 3058 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3059 IXGBE_WRITE_FLUSH(hw);
3060
43e69bf0 3061 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3062 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3063 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3064 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3065 ring->count * sizeof(union ixgbe_adv_tx_desc));
3066 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3067 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3068 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3069
b88c6de2
AD		 3070 /*
3071 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3072 * higher than 1 when:
3073 * - ITR is 0 as it could cause false TX hangs
3074 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3075 *
3076 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3077 * to or less than the number of on chip descriptors, which is
3078 * currently 40.
3079 */
67da097e
ET		 3080#if IS_ENABLED(CONFIG_BQL)
3081 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3082#else
e954b374 3083 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3084#endif
b88c6de2
AD		 3085 txdctl |= (1 << 16); /* WTHRESH = 1 */
3086 else
3087 txdctl |= (8 << 16); /* WTHRESH = 8 */
3088
e954b374
AD		 3089 /*
3090 * Setting PTHRESH to 32 both improves performance
3091 * and avoids a TX hang with DFP enabled
3092 */
b88c6de2
AD		 3093 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3094 32; /* PTHRESH = 32 */
2f1860b8
AD		 3095
3096 /* reinitialize flowdirector state */
39cb681b 3097 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3098 ring->atr_sample_rate = adapter->atr_sample_rate;
3099 ring->atr_count = 0;
3100 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3101 } else {
3102 ring->atr_sample_rate = 0;
3103 }
2f1860b8 3104
fd786b7b
AD		 3105 /* initialize XPS */
3106 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3107 struct ixgbe_q_vector *q_vector = ring->q_vector;
3108
3109 if (q_vector)
2a47fa45 3110 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3111 &q_vector->affinity_mask,
3112 ring->queue_index);
3113 }
3114
c84d324c
JF		 3115 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3116
2f1860b8 3117 /* enable queue */
2f1860b8
AD		 3118 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3119
3120 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3121 if (hw->mac.type == ixgbe_mac_82598EB &&
3122 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3123 return;
3124
3125 /* poll to verify queue is enabled */
3126 do {
032b4325 3127 usleep_range(1000, 2000);
2f1860b8
AD		 3128 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3129 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3130 if (!wait_loop)
3131 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3132}
3133
120ff942
AD		 3134static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3135{
3136 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3137 u32 rttdcs, mtqc;
8b1c0b24 3138 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3139
3140 if (hw->mac.type == ixgbe_mac_82598EB)
3141 return;
3142
3143 /* disable the arbiter while setting MTQC */
3144 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3145 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3146 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3147
3148 /* set transmit pool layout */
671c0adb
AD		 3149 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3150 mtqc = IXGBE_MTQC_VT_ENA;
3151 if (tcs > 4)
3152 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3153 else if (tcs > 1)
3154 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3155 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3156 mtqc |= IXGBE_MTQC_32VF;
3157 else
3158 mtqc |= IXGBE_MTQC_64VF;
3159 } else {
3160 if (tcs > 4)
3161 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3162 else if (tcs > 1)
3163 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3164 else
671c0adb
AD		 3165 mtqc = IXGBE_MTQC_64Q_1PB;
3166 }
120ff942 3167
671c0adb 3168 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3169
671c0adb
AD		 3170 /* Enable Security TX Buffer IFG for multiple pb */
3171 if (tcs) {
3172 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3173 sectx |= IXGBE_SECTX_DCB;
3174 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3175 }
3176
3177 /* re-enable the arbiter */
3178 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3179 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3180}
3181
9a799d71 3182/**
3a581073 3183 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3184 * @adapter: board private structure
3185 *
3186 * Configure the Tx unit of the MAC after a reset.
3187 **/
3188static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3189{
2f1860b8
AD		 3190 struct ixgbe_hw *hw = &adapter->hw;
3191 u32 dmatxctl;
43e69bf0 3192 u32 i;
9a799d71 3193
2f1860b8
AD		 3194 ixgbe_setup_mtqc(adapter);
3195
3196 if (hw->mac.type != ixgbe_mac_82598EB) {
3197 /* DMATXCTL.EN must be before Tx queues are enabled */
3198 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3199 dmatxctl |= IXGBE_DMATXCTL_TE;
3200 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3201 }
3202
9a799d71 3203 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3204 for (i = 0; i < adapter->num_tx_queues; i++)
3205 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3206}
3207
3ebe8fde
AD		 3208static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3209 struct ixgbe_ring *ring)
3210{
3211 struct ixgbe_hw *hw = &adapter->hw;
3212 u8 reg_idx = ring->reg_idx;
3213 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3214
3215 srrctl |= IXGBE_SRRCTL_DROP_EN;
3216
3217 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3218}
3219
3220static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3221 struct ixgbe_ring *ring)
3222{
3223 struct ixgbe_hw *hw = &adapter->hw;
3224 u8 reg_idx = ring->reg_idx;
3225 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3226
3227 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3228
3229 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3230}
3231
3232#ifdef CONFIG_IXGBE_DCB
3233void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3234#else
3235static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3236#endif
3237{
3238 int i;
3239 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3240
3241 if (adapter->ixgbe_ieee_pfc)
3242 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3243
3244 /*
3245 * We should set the drop enable bit if:
3246 * SR-IOV is enabled
3247 * or
3248 * Number of Rx queues > 1 and flow control is disabled
3249 *
3250 * This allows us to avoid head of line blocking for security
3251 * and performance reasons.
3252 */
3253 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3254 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3255 for (i = 0; i < adapter->num_rx_queues; i++)
3256 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3257 } else {
3258 for (i = 0; i < adapter->num_rx_queues; i++)
3259 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3260 }
3261}
3262
e8e26350 3263#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3264
a6616b42 3265static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3266 struct ixgbe_ring *rx_ring)
cc41ac7c 3267{
45e9baa5 3268 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3269 u32 srrctl;
bf29ee6c 3270 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3271
45e9baa5
AD		 3272 if (hw->mac.type == ixgbe_mac_82598EB) {
3273 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3274
45e9baa5
AD		 3275 /*
3276 * if VMDq is not active we must program one srrctl register
3277 * per RSS queue since we have enabled RDRXCTL.MVMEN
3278 */
3279 reg_idx &= mask;
3280 }
cc41ac7c 3281
45e9baa5
AD		 3282 /* configure header buffer length, needed for RSC */
3283 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3284
45e9baa5 3285 /* configure the packet buffer length */
f800326d 3286 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3287
3288 /* configure descriptor type */
f800326d 3289 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3290
45e9baa5 3291 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3292}
9a799d71 3293
05abb126 3294static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3295{
05abb126
AD		 3296 struct ixgbe_hw *hw = &adapter->hw;
3297 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3298 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3299 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3300 u32 mrqc = 0, reta = 0;
3301 u32 rxcsum;
3302 int i, j;
671c0adb
AD		 3303 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3304
671c0adb
AD		 3305 /*
3306 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3307 * make full use of any rings they may have. We will use the
3308 * PSRTYPE register to control how many rings we use within the PF.
3309 */
3310 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3311 rss_i = 2;
0cefafad 3312
05abb126
AD		 3313 /* Fill out hash function seeds */
3314 for (i = 0; i < 10; i++)
3315 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3316
3317 /* Fill out redirection table */
3318 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3319 if (j == rss_i)
05abb126
AD		 3320 j = 0;
3321 /* reta = 4-byte sliding window of
3322 * 0x00..(indices-1)(indices-1)00..etc. */
3323 reta = (reta << 8) | (j * 0x11);
3324 if ((i & 3) == 3)
3325 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3326 }
0cefafad 3327
05abb126
AD		 3328 /* Disable indicating checksum in descriptor, enables RSS hash */
3329 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3330 rxcsum |= IXGBE_RXCSUM_PCSD;
3331 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3332
671c0adb 3333 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3334 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3335 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3336 } else {
671c0adb
AD		 3337 u8 tcs = netdev_get_num_tc(adapter->netdev);
3338
3339 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3340 if (tcs > 4)
3341 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3342 else if (tcs > 1)
3343 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3344 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3345 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3346 else
671c0adb
AD		 3347 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3348 } else {
3349 if (tcs > 4)
8b1c0b24 3350 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3351 else if (tcs > 1)
3352 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3353 else
3354 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3355 }
0cefafad
JB		 3356 }
3357
05abb126 3358 /* Perform hash on these packet types */
671c0adb
AD		 3359 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3360 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3361 IXGBE_MRQC_RSS_FIELD_IPV6 |
3362 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3363
ef6afc0c
AD		 3364 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3365 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3366 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3367 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3368
05abb126 3369 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3370}
3371
bb5a9ad2
NS		 3372/**
3373 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3374 * @adapter: address of board private structure
3375 * @index: index of ring to set
bb5a9ad2 3376 **/
082757af 3377static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3378 struct ixgbe_ring *ring)
bb5a9ad2 3379{
bb5a9ad2 3380 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3381 u32 rscctrl;
bf29ee6c 3382 u8 reg_idx = ring->reg_idx;
7367096a 3383
7d637bcc 3384 if (!ring_is_rsc_enabled(ring))
7367096a 3385 return;
bb5a9ad2 3386
7367096a 3387 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3388 rscctrl |= IXGBE_RSCCTL_RSCEN;
3389 /*
3390 * we must limit the number of descriptors so that the
3391 * total size of max desc * buf_len is not greater
642c680e 3392 * than 65536
bb5a9ad2 3393 */
f800326d 3394 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3395 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3396}
3397
9e10e045
AD		 3398#define IXGBE_MAX_RX_DESC_POLL 10
3399static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3400 struct ixgbe_ring *ring)
3401{
3402 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3403 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3404 u32 rxdctl;
bf29ee6c 3405 u8 reg_idx = ring->reg_idx;
9e10e045 3406
b0483c8f
MR		 3407 if (ixgbe_removed(hw->hw_addr))
3408 return;
9e10e045
AD		 3409 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3410 if (hw->mac.type == ixgbe_mac_82598EB &&
3411 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3412 return;
3413
3414 do {
032b4325 3415 usleep_range(1000, 2000);
9e10e045
AD		 3416 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3417 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3418
3419 if (!wait_loop) {
3420 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3421 "the polling period\n", reg_idx);
3422 }
3423}
3424
2d39d576
YZ		 3425void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3426 struct ixgbe_ring *ring)
3427{
3428 struct ixgbe_hw *hw = &adapter->hw;
3429 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3430 u32 rxdctl;
3431 u8 reg_idx = ring->reg_idx;
3432
b0483c8f
MR		 3433 if (ixgbe_removed(hw->hw_addr))
3434 return;
2d39d576
YZ		 3435 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3436 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3437
3438 /* write value back with RXDCTL.ENABLE bit cleared */
3439 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3440
3441 if (hw->mac.type == ixgbe_mac_82598EB &&
3442 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3443 return;
3444
3445 /* the hardware may take up to 100us to really disable the rx queue */
3446 do {
3447 udelay(10);
3448 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3449 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3450
3451 if (!wait_loop) {
3452 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3453 "the polling period\n", reg_idx);
3454 }
3455}
3456
84418e3b
AD		 3457void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3458 struct ixgbe_ring *ring)
acd37177
AD		 3459{
3460 struct ixgbe_hw *hw = &adapter->hw;
3461 u64 rdba = ring->dma;
9e10e045 3462 u32 rxdctl;
bf29ee6c 3463 u8 reg_idx = ring->reg_idx;
acd37177 3464
9e10e045
AD		 3465 /* disable queue to avoid issues while updating state */
3466 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3467 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3468
acd37177
AD		 3469 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3470 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3471 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3472 ring->count * sizeof(union ixgbe_adv_rx_desc));
3473 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3474 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3475 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3476
3477 ixgbe_configure_srrctl(adapter, ring);
3478 ixgbe_configure_rscctl(adapter, ring);
3479
3480 if (hw->mac.type == ixgbe_mac_82598EB) {
3481 /*
3482 * enable cache line friendly hardware writes:
3483 * PTHRESH=32 descriptors (half the internal cache),
3484 * this also removes ugly rx_no_buffer_count increment
3485 * HTHRESH=4 descriptors (to minimize latency on fetch)
3486 * WTHRESH=8 burst writeback up to two cache lines
3487 */
3488 rxdctl &= ~0x3FFFFF;
3489 rxdctl |= 0x080420;
3490 }
3491
3492 /* enable receive descriptor ring */
3493 rxdctl |= IXGBE_RXDCTL_ENABLE;
3494 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3495
3496 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3497 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3498}
3499
48654521
AD		 3500static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3501{
3502 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3503 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3504 u16 pool;
48654521
AD		 3505
3506 /* PSRTYPE must be initialized in non 82598 adapters */
3507 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3508 IXGBE_PSRTYPE_UDPHDR |
3509 IXGBE_PSRTYPE_IPV4HDR |
48654521 3510 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3511 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3512
3513 if (hw->mac.type == ixgbe_mac_82598EB)
3514 return;
3515
fbe7ca7f
AD		 3516 if (rss_i > 3)
3517 psrtype |= 2 << 29;
3518 else if (rss_i > 1)
3519 psrtype |= 1 << 29;
48654521 3520
2a47fa45
JF		 3521 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3522 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3523}
3524
f5b4a52e
AD		 3525static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3526{
3527 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3528 u32 reg_offset, vf_shift;
435b19f6 3529 u32 gcr_ext, vmdctl;
de4c7f65 3530 int i;
f5b4a52e
AD		 3531
3532 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3533 return;
3534
3535 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3536 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3537 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3538 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3539 vmdctl |= IXGBE_VT_CTL_REPLEN;
3540 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3541
1d9c0bfd
AD		 3542 vf_shift = VMDQ_P(0) % 32;
3543 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3544
3545 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3546 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3547 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3548 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3549 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3550 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3551 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3552
3553 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3554 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3555
3556 /*
3557 * Set up VF register offsets for selected VT Mode,
3558 * i.e. 32 or 64 VFs for SR-IOV
3559 */
73079ea0
AD		 3560 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3561 case IXGBE_82599_VMDQ_8Q_MASK:
3562 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3563 break;
3564 case IXGBE_82599_VMDQ_4Q_MASK:
3565 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3566 break;
3567 default:
3568 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3569 break;
3570 }
3571
f5b4a52e
AD		 3572 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3573
435b19f6 3574
a985b6c3 3575 /* Enable MAC Anti-Spoofing */
435b19f6 3576 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3577 adapter->num_vfs);
de4c7f65
GR		 3578 /* For VFs that have spoof checking turned off */
3579 for (i = 0; i < adapter->num_vfs; i++) {
3580 if (!adapter->vfinfo[i].spoofchk_enabled)
3581 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3582 }
f5b4a52e
AD		 3583}
3584
477de6ed 3585static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3586{
9a799d71
AK		 3587 struct ixgbe_hw *hw = &adapter->hw;
3588 struct net_device *netdev = adapter->netdev;
3589 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3590 struct ixgbe_ring *rx_ring;
3591 int i;
3592 u32 mhadd, hlreg0;
48654521 3593
63f39bd1 3594#ifdef IXGBE_FCOE
477de6ed
AD		 3595 /* adjust max frame to be able to do baby jumbo for FCoE */
3596 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3597 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3598 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3599
477de6ed 3600#endif /* IXGBE_FCOE */
872844dd
AD		 3601
3602 /* adjust max frame to be at least the size of a standard frame */
3603 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3604 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3605
477de6ed
AD		 3606 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3607 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3608 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3609 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3610
3611 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3612 }
3613
3614 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3615 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3616 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3617 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3618
0cefafad
JB		 3619 /*
3620 * Setup the HW Rx Head and Tail Descriptor Pointers and
3621 * the Base and Length of the Rx Descriptor Ring
3622 */
9a799d71 3623 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3624 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3625 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3626 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3627 else
7d637bcc 3628 clear_ring_rsc_enabled(rx_ring);
477de6ed 3629 }
477de6ed
AD		 3630}
3631
7367096a
AD		 3632static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3633{
3634 struct ixgbe_hw *hw = &adapter->hw;
3635 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3636
3637 switch (hw->mac.type) {
3638 case ixgbe_mac_82598EB:
3639 /*
3640 * For VMDq support of different descriptor types or
3641 * buffer sizes through the use of multiple SRRCTL
3642 * registers, RDRXCTL.MVMEN must be set to 1
3643 *
3644 * also, the manual doesn't mention it clearly but DCA hints
3645 * will only use queue 0's tags unless this bit is set. Side
3646 * effects of setting this bit are only that SRRCTL must be
3647 * fully programmed [0..15]
3648 */
3649 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3650 break;
3651 case ixgbe_mac_82599EB:
b93a2226 3652 case ixgbe_mac_X540:
7367096a
AD		 3653 /* Disable RSC for ACK packets */
3654 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3655 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3656 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3657 /* hardware requires some bits to be set by default */
3658 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3659 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3660 break;
3661 default:
3662 /* We should do nothing since we don't know this hardware */
3663 return;
3664 }
3665
3666 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3667}
3668
477de6ed
AD		 3669/**
3670 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3671 * @adapter: board private structure
3672 *
3673 * Configure the Rx unit of the MAC after a reset.
3674 **/
3675static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3676{
3677 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3678 int i;
6dcc28b9 3679 u32 rxctrl, rfctl;
477de6ed
AD		 3680
3681 /* disable receives while setting up the descriptors */
3682 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3683 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3684
3685 ixgbe_setup_psrtype(adapter);
7367096a 3686 ixgbe_setup_rdrxctl(adapter);
477de6ed 3687
6dcc28b9
JK		 3688 /* RSC Setup */
3689 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3690 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3691 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3692 rfctl |= IXGBE_RFCTL_RSC_DIS;
3693 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3694
9e10e045 3695 /* Program registers for the distribution of queues */
f5b4a52e 3696 ixgbe_setup_mrqc(adapter);
f5b4a52e 3697
477de6ed
AD		 3698 /* set_rx_buffer_len must be called before ring initialization */
3699 ixgbe_set_rx_buffer_len(adapter);
3700
3701 /*
3702 * Setup the HW Rx Head and Tail Descriptor Pointers and
3703 * the Base and Length of the Rx Descriptor Ring
3704 */
9e10e045
AD		 3705 for (i = 0; i < adapter->num_rx_queues; i++)
3706 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3707
9e10e045
AD		 3708 /* disable drop enable for 82598 parts */
3709 if (hw->mac.type == ixgbe_mac_82598EB)
3710 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3711
3712 /* enable all receives */
3713 rxctrl |= IXGBE_RXCTRL_RXEN;
3714 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3715}
3716
80d5c368
PM		 3717static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3718 __be16 proto, u16 vid)
068c89b0
DS		 3719{
3720 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3721 struct ixgbe_hw *hw = &adapter->hw;
3722
3723 /* add VID to filter table */
1d9c0bfd 3724 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3725 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3726
3727 return 0;
068c89b0
DS		 3728}
3729
80d5c368
PM		 3730static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3731 __be16 proto, u16 vid)
068c89b0
DS		 3732{
3733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3734 struct ixgbe_hw *hw = &adapter->hw;
3735
068c89b0 3736 /* remove VID from filter table */
1d9c0bfd 3737 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3738 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3739
3740 return 0;
068c89b0
DS		 3741}
3742
5f6c0181
JB		 3743/**
3744 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3745 * @adapter: driver data
3746 */
3747static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3748{
3749 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3750 u32 vlnctrl;
3751
3752 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3753 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3754 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3755}
3756
3757/**
3758 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3759 * @adapter: driver data
3760 */
3761static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3762{
3763 struct ixgbe_hw *hw = &adapter->hw;
3764 u32 vlnctrl;
3765
3766 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3767 vlnctrl |= IXGBE_VLNCTRL_VFE;
3768 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3769 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3770}
3771
3772/**
3773 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3774 * @adapter: driver data
3775 */
3776static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3777{
3778 struct ixgbe_hw *hw = &adapter->hw;
3779 u32 vlnctrl;
5f6c0181
JB		 3780 int i, j;
3781
3782 switch (hw->mac.type) {
3783 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3784 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3785 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3786 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3787 break;
3788 case ixgbe_mac_82599EB:
b93a2226 3789 case ixgbe_mac_X540:
5f6c0181 3790 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3791 struct ixgbe_ring *ring = adapter->rx_ring[i];
3792
3793 if (ring->l2_accel_priv)
3794 continue;
3795 j = ring->reg_idx;
5f6c0181
JB		 3796 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3797 vlnctrl &= ~IXGBE_RXDCTL_VME;
3798 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3799 }
3800 break;
3801 default:
3802 break;
3803 }
3804}
3805
3806/**
f62bbb5e 3807 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3808 * @adapter: driver data
3809 */
f62bbb5e 3810static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3811{
3812 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3813 u32 vlnctrl;
5f6c0181
JB		 3814 int i, j;
3815
3816 switch (hw->mac.type) {
3817 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3818 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3819 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3820 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3821 break;
3822 case ixgbe_mac_82599EB:
b93a2226 3823 case ixgbe_mac_X540:
5f6c0181 3824 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3825 struct ixgbe_ring *ring = adapter->rx_ring[i];
3826
3827 if (ring->l2_accel_priv)
3828 continue;
3829 j = ring->reg_idx;
5f6c0181
JB		 3830 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3831 vlnctrl |= IXGBE_RXDCTL_VME;
3832 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3833 }
3834 break;
3835 default:
3836 break;
3837 }
3838}
3839
9a799d71
AK		 3840static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3841{
f62bbb5e 3842 u16 vid;
9a799d71 3843
80d5c368 3844 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3845
3846 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3847 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3848}
3849
2850062a
AD		 3850/**
3851 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3852 * @netdev: network interface device structure
3853 *
3854 * Writes unicast address list to the RAR table.
3855 * Returns: -ENOMEM on failure/insufficient address space
3856 * 0 on no addresses written
3857 * X on writing X addresses to the RAR table
3858 **/
3859static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3860{
3861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3862 struct ixgbe_hw *hw = &adapter->hw;
95447461 3863 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3864 int count = 0;
3865
2a47fa45 3866 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3867 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3868 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3869
2850062a
AD		 3870 /* return ENOMEM indicating insufficient memory for addresses */
3871 if (netdev_uc_count(netdev) > rar_entries)
3872 return -ENOMEM;
3873
95447461 3874 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3875 struct netdev_hw_addr *ha;
3876 /* return error if we do not support writing to RAR table */
3877 if (!hw->mac.ops.set_rar)
3878 return -ENOMEM;
3879
3880 netdev_for_each_uc_addr(ha, netdev) {
3881 if (!rar_entries)
3882 break;
3883 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3884 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3885 count++;
3886 }
3887 }
3888 /* write the addresses in reverse order to avoid write combining */
3889 for (; rar_entries > 0 ; rar_entries--)
3890 hw->mac.ops.clear_rar(hw, rar_entries);
3891
3892 return count;
3893}
3894
9a799d71 3895/**
2c5645cf 3896 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3897 * @netdev: network interface device structure
3898 *
2c5645cf
CL		 3899 * The set_rx_method entry point is called whenever the unicast/multicast
3900 * address list or the network interface flags are updated. This routine is
3901 * responsible for configuring the hardware for proper unicast, multicast and
3902 * promiscuous mode.
9a799d71 3903 **/
7f870475 3904void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3905{
3906 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3907 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3908 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3909 int count;
9a799d71
AK		 3910
3911 /* Check for Promiscuous and All Multicast modes */
3912
3913 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3914
f5dc442b 3915 /* set all bits that we expect to always be set */
3f2d1c0f 3916 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3917 fctrl |= IXGBE_FCTRL_BAM;
3918 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3919 fctrl |= IXGBE_FCTRL_PMCF;
3920
2850062a
AD		 3921 /* clear the bits we are changing the status of */
3922 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3923
9a799d71 3924 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3925 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3926 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3927 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3928 /* Only disable hardware filter vlans in promiscuous mode
3929 * if SR-IOV and VMDQ are disabled - otherwise ensure
3930 * that hardware VLAN filters remain enabled.
3931 */
3932 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3933 IXGBE_FLAG_SRIOV_ENABLED)))
3934 ixgbe_vlan_filter_disable(adapter);
3935 else
3936 ixgbe_vlan_filter_enable(adapter);
9a799d71 3937 } else {
746b9f02
PM		 3938 if (netdev->flags & IFF_ALLMULTI) {
3939 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3940 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3941 }
5f6c0181 3942 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3943 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3944 }
3945
3946 /*
3947 * Write addresses to available RAR registers, if there is not
3948 * sufficient space to store all the addresses then enable
3949 * unicast promiscuous mode
3950 */
3951 count = ixgbe_write_uc_addr_list(netdev);
3952 if (count < 0) {
3953 fctrl |= IXGBE_FCTRL_UPE;
3954 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3955 }
3956
cf78959c
ET		 3957 /* Write addresses to the MTA, if the attempt fails
3958 * then we should just turn on promiscuous mode so
3959 * that we can at least receive multicast traffic
3960 */
3961 hw->mac.ops.update_mc_addr_list(hw, netdev);
3962 vmolr |= IXGBE_VMOLR_ROMPE;
3963
1d9c0bfd 3964 if (adapter->num_vfs)
1cdd1ec8 3965 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3966
3967 if (hw->mac.type != ixgbe_mac_82598EB) {
3968 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3969 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3970 IXGBE_VMOLR_ROPE);
1d9c0bfd 3971 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3972 }
3973
3f2d1c0f
BG		 3974 /* This is useful for sniffing bad packets. */
3975 if (adapter->netdev->features & NETIF_F_RXALL) {
3976 /* UPE and MPE will be handled by normal PROMISC logic
3977 * in e1000e_set_rx_mode */
3978 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3979 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3980 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3981
3982 fctrl &= ~(IXGBE_FCTRL_DPF);
3983 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3984 }
3985
2850062a 3986 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3987
f646968f 3988 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3989 ixgbe_vlan_strip_enable(adapter);
3990 else
3991 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3992}
3993
021230d4
AV		 3994static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3995{
3996 int q_idx;
021230d4 3997
5a85e737
ET		 3998 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3999 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4000 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4001 }
021230d4
AV		 4002}
4003
4004static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4005{
4006 int q_idx;
021230d4 4007
5a85e737 4008 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4009 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4010 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4011 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4012 usleep_range(1000, 20000);
5a85e737
ET		 4013 }
4014 }
021230d4
AV		 4015}
4016
7a6b6f51 4017#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4018/**
2f90b865
AD		 4019 * ixgbe_configure_dcb - Configure DCB hardware
4020 * @adapter: ixgbe adapter struct
4021 *
4022 * This is called by the driver on open to configure the DCB hardware.
4023 * This is also called by the gennetlink interface when reconfiguring
4024 * the DCB state.
4025 */
4026static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4027{
4028 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4029 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4030
67ebd791
AD		 4031 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4032 if (hw->mac.type == ixgbe_mac_82598EB)
4033 netif_set_gso_max_size(adapter->netdev, 65536);
4034 return;
4035 }
4036
4037 if (hw->mac.type == ixgbe_mac_82598EB)
4038 netif_set_gso_max_size(adapter->netdev, 32768);
4039
971060b1 4040#ifdef IXGBE_FCOE
b120818e
JF		 4041 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4042 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4043#endif
b120818e
JF		 4044
4045 /* reconfigure the hardware */
4046 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4047 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4048 DCB_TX_CONFIG);
4049 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4050 DCB_RX_CONFIG);
4051 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4052 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4053 ixgbe_dcb_hw_ets(&adapter->hw,
4054 adapter->ixgbe_ieee_ets,
4055 max_frame);
4056 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4057 adapter->ixgbe_ieee_pfc->pfc_en,
4058 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4059 }
8187cd48
JF		 4060
4061 /* Enable RSS Hash per TC */
4062 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4063 u32 msb = 0;
4064 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4065
d411a936
AD		 4066 while (rss_i) {
4067 msb++;
4068 rss_i >>= 1;
4069 }
8187cd48 4070
4ae63730
AD		 4071 /* write msb to all 8 TCs in one write */
4072 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4073 }
2f90b865 4074}
9da712d2
JF		 4075#endif
4076
4077/* Additional bittime to account for IXGBE framing */
4078#define IXGBE_ETH_FRAMING 20
4079
49ce9c2c 4080/**
9da712d2
JF		 4081 * ixgbe_hpbthresh - calculate high water mark for flow control
4082 *
4083 * @adapter: board private structure to calculate for
49ce9c2c 4084 * @pb: packet buffer to calculate
9da712d2
JF		 4085 */
4086static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4087{
4088 struct ixgbe_hw *hw = &adapter->hw;
4089 struct net_device *dev = adapter->netdev;
4090 int link, tc, kb, marker;
4091 u32 dv_id, rx_pba;
4092
4093 /* Calculate max LAN frame size */
4094 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4095
4096#ifdef IXGBE_FCOE
4097 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4098 if ((dev->features & NETIF_F_FCOE_MTU) &&
4099 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4100 (pb == ixgbe_fcoe_get_tc(adapter)))
4101 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 4102
4103#endif
9da712d2
JF		 4104 /* Calculate delay value for device */
4105 switch (hw->mac.type) {
4106 case ixgbe_mac_X540:
4107 dv_id = IXGBE_DV_X540(link, tc);
4108 break;
4109 default:
4110 dv_id = IXGBE_DV(link, tc);
4111 break;
4112 }
4113
4114 /* Loopback switch introduces additional latency */
4115 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4116 dv_id += IXGBE_B2BT(tc);
4117
4118 /* Delay value is calculated in bit times convert to KB */
4119 kb = IXGBE_BT2KB(dv_id);
4120 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4121
4122 marker = rx_pba - kb;
4123
4124 /* It is possible that the packet buffer is not large enough
4125 * to provide required headroom. In this case throw an error
4126 * to user and a do the best we can.
4127 */
4128 if (marker < 0) {
4129 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4130 "headroom to support flow control."
4131 "Decrease MTU or number of traffic classes\n", pb);
4132 marker = tc + 1;
4133 }
4134
4135 return marker;
4136}
4137
49ce9c2c 4138/**
9da712d2
JF		 4139 * ixgbe_lpbthresh - calculate low water mark for for flow control
4140 *
4141 * @adapter: board private structure to calculate for
49ce9c2c 4142 * @pb: packet buffer to calculate
9da712d2
JF		 4143 */
4144static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4145{
4146 struct ixgbe_hw *hw = &adapter->hw;
4147 struct net_device *dev = adapter->netdev;
4148 int tc;
4149 u32 dv_id;
4150
4151 /* Calculate max LAN frame size */
4152 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4153
4154 /* Calculate delay value for device */
4155 switch (hw->mac.type) {
4156 case ixgbe_mac_X540:
4157 dv_id = IXGBE_LOW_DV_X540(tc);
4158 break;
4159 default:
4160 dv_id = IXGBE_LOW_DV(tc);
4161 break;
4162 }
4163
4164 /* Delay value is calculated in bit times convert to KB */
4165 return IXGBE_BT2KB(dv_id);
4166}
4167
4168/*
4169 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4170 */
4171static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4172{
4173 struct ixgbe_hw *hw = &adapter->hw;
4174 int num_tc = netdev_get_num_tc(adapter->netdev);
4175 int i;
4176
4177 if (!num_tc)
4178 num_tc = 1;
4179
4180 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4181
4182 for (i = 0; i < num_tc; i++) {
4183 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4184
4185 /* Low water marks must not be larger than high water marks */
4186 if (hw->fc.low_water > hw->fc.high_water[i])
4187 hw->fc.low_water = 0;
4188 }
4189}
4190
80605c65
JF		 4191static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4192{
80605c65 4193 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4194 int hdrm;
4195 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4196
4197 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4198 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4199 hdrm = 32 << adapter->fdir_pballoc;
4200 else
4201 hdrm = 0;
80605c65 4202
f7e1027f 4203 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4204 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4205}
4206
e4911d57
AD		 4207static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4208{
4209 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4210 struct hlist_node *node2;
e4911d57
AD		 4211 struct ixgbe_fdir_filter *filter;
4212
4213 spin_lock(&adapter->fdir_perfect_lock);
4214
4215 if (!hlist_empty(&adapter->fdir_filter_list))
4216 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4217
b67bfe0d 4218 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4219 &adapter->fdir_filter_list, fdir_node) {
4220 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4221 &filter->filter,
4222 filter->sw_idx,
4223 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4224 IXGBE_FDIR_DROP_QUEUE :
4225 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4226 }
4227
4228 spin_unlock(&adapter->fdir_perfect_lock);
4229}
4230
2a47fa45
JF		 4231static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4232 struct ixgbe_adapter *adapter)
4233{
4234 struct ixgbe_hw *hw = &adapter->hw;
4235 u32 vmolr;
4236
4237 /* No unicast promiscuous support for VMDQ devices. */
4238 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4239 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4240
4241 /* clear the affected bit */
4242 vmolr &= ~IXGBE_VMOLR_MPE;
4243
4244 if (dev->flags & IFF_ALLMULTI) {
4245 vmolr |= IXGBE_VMOLR_MPE;
4246 } else {
4247 vmolr |= IXGBE_VMOLR_ROMPE;
4248 hw->mac.ops.update_mc_addr_list(hw, dev);
4249 }
4250 ixgbe_write_uc_addr_list(adapter->netdev);
4251 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4252}
4253
4254static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4255 u8 *addr, u16 pool)
4256{
4257 struct ixgbe_hw *hw = &adapter->hw;
4258 unsigned int entry;
4259
4260 entry = hw->mac.num_rar_entries - pool;
4261 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4262}
4263
4264static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4265{
4266 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4267 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4268 struct ixgbe_hw *hw = &adapter->hw;
4269 u16 pool = vadapter->pool;
4270 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4271 IXGBE_PSRTYPE_UDPHDR |
4272 IXGBE_PSRTYPE_IPV4HDR |
4273 IXGBE_PSRTYPE_L2HDR |
4274 IXGBE_PSRTYPE_IPV6HDR;
4275
4276 if (hw->mac.type == ixgbe_mac_82598EB)
4277 return;
4278
4279 if (rss_i > 3)
4280 psrtype |= 2 << 29;
4281 else if (rss_i > 1)
4282 psrtype |= 1 << 29;
4283
4284 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4285}
4286
4287/**
4288 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4289 * @rx_ring: ring to free buffers from
4290 **/
4291static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4292{
4293 struct device *dev = rx_ring->dev;
4294 unsigned long size;
4295 u16 i;
4296
4297 /* ring already cleared, nothing to do */
4298 if (!rx_ring->rx_buffer_info)
4299 return;
4300
4301 /* Free all the Rx ring sk_buffs */
4302 for (i = 0; i < rx_ring->count; i++) {
4303 struct ixgbe_rx_buffer *rx_buffer;
4304
4305 rx_buffer = &rx_ring->rx_buffer_info[i];
4306 if (rx_buffer->skb) {
4307 struct sk_buff *skb = rx_buffer->skb;
4308 if (IXGBE_CB(skb)->page_released) {
4309 dma_unmap_page(dev,
4310 IXGBE_CB(skb)->dma,
4311 ixgbe_rx_bufsz(rx_ring),
4312 DMA_FROM_DEVICE);
4313 IXGBE_CB(skb)->page_released = false;
4314 }
4315 dev_kfree_skb(skb);
4316 }
4317 rx_buffer->skb = NULL;
4318 if (rx_buffer->dma)
4319 dma_unmap_page(dev, rx_buffer->dma,
4320 ixgbe_rx_pg_size(rx_ring),
4321 DMA_FROM_DEVICE);
4322 rx_buffer->dma = 0;
4323 if (rx_buffer->page)
4324 __free_pages(rx_buffer->page,
4325 ixgbe_rx_pg_order(rx_ring));
4326 rx_buffer->page = NULL;
4327 }
4328
4329 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4330 memset(rx_ring->rx_buffer_info, 0, size);
4331
4332 /* Zero out the descriptor ring */
4333 memset(rx_ring->desc, 0, rx_ring->size);
4334
4335 rx_ring->next_to_alloc = 0;
4336 rx_ring->next_to_clean = 0;
4337 rx_ring->next_to_use = 0;
4338}
4339
4340static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4341 struct ixgbe_ring *rx_ring)
4342{
4343 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4344 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4345
4346 /* shutdown specific queue receive and wait for dma to settle */
4347 ixgbe_disable_rx_queue(adapter, rx_ring);
4348 usleep_range(10000, 20000);
4349 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4350 ixgbe_clean_rx_ring(rx_ring);
4351 rx_ring->l2_accel_priv = NULL;
4352}
4353
ae72c8d0
JF		 4354static int ixgbe_fwd_ring_down(struct net_device *vdev,
4355 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4356{
4357 struct ixgbe_adapter *adapter = accel->real_adapter;
4358 unsigned int rxbase = accel->rx_base_queue;
4359 unsigned int txbase = accel->tx_base_queue;
4360 int i;
4361
4362 netif_tx_stop_all_queues(vdev);
4363
4364 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4365 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4366 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4367 }
4368
4369 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4370 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4371 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4372 }
4373
4374
4375 return 0;
4376}
4377
4378static int ixgbe_fwd_ring_up(struct net_device *vdev,
4379 struct ixgbe_fwd_adapter *accel)
4380{
4381 struct ixgbe_adapter *adapter = accel->real_adapter;
4382 unsigned int rxbase, txbase, queues;
4383 int i, baseq, err = 0;
4384
4385 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4386 return 0;
4387
4388 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4389 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4390 accel->pool, adapter->num_rx_pools,
4391 baseq, baseq + adapter->num_rx_queues_per_pool,
4392 adapter->fwd_bitmask);
4393
4394 accel->netdev = vdev;
4395 accel->rx_base_queue = rxbase = baseq;
4396 accel->tx_base_queue = txbase = baseq;
4397
4398 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4399 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4400
4401 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4402 adapter->rx_ring[rxbase + i]->netdev = vdev;
4403 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4404 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4405 }
4406
4407 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4408 adapter->tx_ring[txbase + i]->netdev = vdev;
4409 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4410 }
4411
4412 queues = min_t(unsigned int,
4413 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4414 err = netif_set_real_num_tx_queues(vdev, queues);
4415 if (err)
4416 goto fwd_queue_err;
4417
2a47fa45
JF		 4418 err = netif_set_real_num_rx_queues(vdev, queues);
4419 if (err)
4420 goto fwd_queue_err;
4421
4422 if (is_valid_ether_addr(vdev->dev_addr))
4423 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4424
4425 ixgbe_fwd_psrtype(accel);
4426 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4427 return err;
4428fwd_queue_err:
4429 ixgbe_fwd_ring_down(vdev, accel);
4430 return err;
4431}
4432
4433static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4434{
4435 struct net_device *upper;
4436 struct list_head *iter;
4437 int err;
4438
4439 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4440 if (netif_is_macvlan(upper)) {
4441 struct macvlan_dev *dfwd = netdev_priv(upper);
4442 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4443
4444 if (dfwd->fwd_priv) {
4445 err = ixgbe_fwd_ring_up(upper, vadapter);
4446 if (err)
4447 continue;
4448 }
4449 }
4450 }
4451}
4452
9a799d71
AK		 4453static void ixgbe_configure(struct ixgbe_adapter *adapter)
4454{
d2f5e7f3
AS		 4455 struct ixgbe_hw *hw = &adapter->hw;
4456
80605c65 4457 ixgbe_configure_pb(adapter);
7a6b6f51 4458#ifdef CONFIG_IXGBE_DCB
67ebd791 4459 ixgbe_configure_dcb(adapter);
2f90b865 4460#endif
b35d4d42
AD		 4461 /*
4462 * We must restore virtualization before VLANs or else
4463 * the VLVF registers will not be populated
4464 */
4465 ixgbe_configure_virtualization(adapter);
9a799d71 4466
4c1d7b4b 4467 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4468 ixgbe_restore_vlan(adapter);
4469
d2f5e7f3
AS		 4470 switch (hw->mac.type) {
4471 case ixgbe_mac_82599EB:
4472 case ixgbe_mac_X540:
4473 hw->mac.ops.disable_rx_buff(hw);
4474 break;
4475 default:
4476 break;
4477 }
4478
c4cf55e5 4479 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4480 ixgbe_init_fdir_signature_82599(&adapter->hw,
4481 adapter->fdir_pballoc);
e4911d57
AD		 4482 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4483 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4484 adapter->fdir_pballoc);
4485 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4486 }
4c1d7b4b 4487
d2f5e7f3
AS		 4488 switch (hw->mac.type) {
4489 case ixgbe_mac_82599EB:
4490 case ixgbe_mac_X540:
4491 hw->mac.ops.enable_rx_buff(hw);
4492 break;
4493 default:
4494 break;
4495 }
4496
7c8ae65a
AD		 4497#ifdef IXGBE_FCOE
4498 /* configure FCoE L2 filters, redirection table, and Rx control */
4499 ixgbe_configure_fcoe(adapter);
4500
4501#endif /* IXGBE_FCOE */
9a799d71
AK		 4502 ixgbe_configure_tx(adapter);
4503 ixgbe_configure_rx(adapter);
2a47fa45 4504 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4505}
4506
e8e26350
PW		 4507static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4508{
4509 switch (hw->phy.type) {
4510 case ixgbe_phy_sfp_avago:
4511 case ixgbe_phy_sfp_ftl:
4512 case ixgbe_phy_sfp_intel:
4513 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4514 case ixgbe_phy_sfp_passive_tyco:
4515 case ixgbe_phy_sfp_passive_unknown:
4516 case ixgbe_phy_sfp_active_unknown:
4517 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4518 case ixgbe_phy_qsfp_passive_unknown:
4519 case ixgbe_phy_qsfp_active_unknown:
4520 case ixgbe_phy_qsfp_intel:
4521 case ixgbe_phy_qsfp_unknown:
e8e26350 4522 return true;
8917b447
AD		 4523 case ixgbe_phy_nl:
4524 if (hw->mac.type == ixgbe_mac_82598EB)
4525 return true;
e8e26350
PW		 4526 default:
4527 return false;
4528 }
4529}
4530
0ecc061d 4531/**
e8e26350
PW		 4532 * ixgbe_sfp_link_config - set up SFP+ link
4533 * @adapter: pointer to private adapter struct
4534 **/
4535static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4536{
7086400d 4537 /*
52f33af8 4538 * We are assuming the worst case scenario here, and that
7086400d
AD		 4539 * is that an SFP was inserted/removed after the reset
4540 * but before SFP detection was enabled. As such the best
4541 * solution is to just start searching as soon as we start
4542 */
4543 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4544 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4545
7086400d 4546 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4547}
4548
4549/**
4550 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4551 * @hw: pointer to private hardware struct
4552 *
4553 * Returns 0 on success, negative on failure
4554 **/
e8e26350 4555static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4556{
3d292265
JH		 4557 u32 speed;
4558 bool autoneg, link_up = false;
0ecc061d
PWJ		 4559 u32 ret = IXGBE_ERR_LINK_SETUP;
4560
4561 if (hw->mac.ops.check_link)
3d292265 4562 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4563
4564 if (ret)
4565 goto link_cfg_out;
4566
3d292265
JH		 4567 speed = hw->phy.autoneg_advertised;
4568 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4569 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4570 &autoneg);
0ecc061d
PWJ		 4571 if (ret)
4572 goto link_cfg_out;
4573
8620a103 4574 if (hw->mac.ops.setup_link)
fd0326f2 4575 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4576link_cfg_out:
4577 return ret;
4578}
4579
a34bcfff 4580static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4581{
9a799d71 4582 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4583 u32 gpie = 0;
9a799d71 4584
9b471446 4585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4586 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4587 IXGBE_GPIE_OCD;
4588 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4589 /*
4590 * use EIAM to auto-mask when MSI-X interrupt is asserted
4591 * this saves a register write for every interrupt
4592 */
4593 switch (hw->mac.type) {
4594 case ixgbe_mac_82598EB:
4595 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4596 break;
9b471446 4597 case ixgbe_mac_82599EB:
b93a2226
DS		 4598 case ixgbe_mac_X540:
4599 default:
9b471446
JB		 4600 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4601 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4602 break;
4603 }
4604 } else {
021230d4
AV		 4605 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4606 * specifically only auto mask tx and rx interrupts */
4607 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4608 }
9a799d71 4609
a34bcfff
AD		 4610 /* XXX: to interrupt immediately for EICS writes, enable this */
4611 /* gpie |= IXGBE_GPIE_EIMEN; */
4612
4613 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4614 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4615
4616 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4617 case IXGBE_82599_VMDQ_8Q_MASK:
4618 gpie |= IXGBE_GPIE_VTMODE_16;
4619 break;
4620 case IXGBE_82599_VMDQ_4Q_MASK:
4621 gpie |= IXGBE_GPIE_VTMODE_32;
4622 break;
4623 default:
4624 gpie |= IXGBE_GPIE_VTMODE_64;
4625 break;
4626 }
119fc60a
MC		 4627 }
4628
5fdd31f9 4629 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4630 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4631 switch (adapter->hw.mac.type) {
4632 case ixgbe_mac_82599EB:
4633 gpie |= IXGBE_SDP0_GPIEN;
4634 break;
4635 case ixgbe_mac_X540:
4636 gpie |= IXGBE_EIMS_TS;
4637 break;
4638 default:
4639 break;
4640 }
4641 }
5fdd31f9 4642
a34bcfff
AD		 4643 /* Enable fan failure interrupt */
4644 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4645 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4646
2698b208 4647 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4648 gpie |= IXGBE_SDP1_GPIEN;
4649 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4650 }
a34bcfff
AD		 4651
4652 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4653}
4654
c7ccde0f 4655static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4656{
4657 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4658 struct net_device *upper;
4659 struct list_head *iter;
a34bcfff 4660 int err;
a34bcfff
AD		 4661 u32 ctrl_ext;
4662
4663 ixgbe_get_hw_control(adapter);
4664 ixgbe_setup_gpie(adapter);
e8e26350 4665
9a799d71
AK		 4666 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4667 ixgbe_configure_msix(adapter);
4668 else
4669 ixgbe_configure_msi_and_legacy(adapter);
4670
ec74a471
ET		 4671 /* enable the optics for 82599 SFP+ fiber */
4672 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4673 hw->mac.ops.enable_tx_laser(hw);
4674
c3049c8f 4675 smp_mb__before_clear_bit();
9a799d71 4676 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4677 ixgbe_napi_enable_all(adapter);
4678
73c4b7cd
AD		 4679 if (ixgbe_is_sfp(hw)) {
4680 ixgbe_sfp_link_config(adapter);
4681 } else {
4682 err = ixgbe_non_sfp_link_config(hw);
4683 if (err)
4684 e_err(probe, "link_config FAILED %d\n", err);
4685 }
4686
021230d4
AV		 4687 /* clear any pending interrupts, may auto mask */
4688 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4689 ixgbe_irq_enable(adapter, true, true);
9a799d71 4690
bf069c97
DS		 4691 /*
4692 * If this adapter has a fan, check to see if we had a failure
4693 * before we enabled the interrupt.
4694 */
4695 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4696 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4697 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4698 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4699 }
4700
1da100bb 4701 /* enable transmits */
477de6ed 4702 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4703
2a47fa45
JF		 4704 /* enable any upper devices */
4705 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4706 if (netif_is_macvlan(upper)) {
4707 struct macvlan_dev *vlan = netdev_priv(upper);
4708
4709 if (vlan->fwd_priv)
4710 netif_tx_start_all_queues(upper);
4711 }
4712 }
4713
9a799d71
AK		 4714 /* bring the link up in the watchdog, this could race with our first
4715 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4716 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4717 adapter->link_check_timeout = jiffies;
7086400d 4718 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4719
4720 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4721 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4722 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4723 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4724}
4725
d4f80882
AV		 4726void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4727{
4728 WARN_ON(in_interrupt());
7086400d
AD		 4729 /* put off any impending NetWatchDogTimeout */
4730 adapter->netdev->trans_start = jiffies;
4731
d4f80882 4732 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4733 usleep_range(1000, 2000);
d4f80882 4734 ixgbe_down(adapter);
5809a1ae
GR		 4735 /*
4736 * If SR-IOV enabled then wait a bit before bringing the adapter
4737 * back up to give the VFs time to respond to the reset. The
4738 * two second wait is based upon the watchdog timer cycle in
4739 * the VF driver.
4740 */
4741 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4742 msleep(2000);
d4f80882
AV		 4743 ixgbe_up(adapter);
4744 clear_bit(__IXGBE_RESETTING, &adapter->state);
4745}
4746
c7ccde0f 4747void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4748{
4749 /* hardware has been reset, we need to reload some things */
4750 ixgbe_configure(adapter);
4751
c7ccde0f 4752 ixgbe_up_complete(adapter);
9a799d71
AK		 4753}
4754
4755void ixgbe_reset(struct ixgbe_adapter *adapter)
4756{
c44ade9e 4757 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4758 int err;
4759
b0483c8f
MR		 4760 if (ixgbe_removed(hw->hw_addr))
4761 return;
7086400d
AD		 4762 /* lock SFP init bit to prevent race conditions with the watchdog */
4763 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4764 usleep_range(1000, 2000);
4765
4766 /* clear all SFP and link config related flags while holding SFP_INIT */
4767 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4768 IXGBE_FLAG2_SFP_NEEDS_RESET);
4769 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4770
8ca783ab 4771 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4772 switch (err) {
4773 case 0:
4774 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4775 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4776 break;
4777 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4778 e_dev_err("master disable timed out\n");
da4dd0f7 4779 break;
794caeb2
PWJ		 4780 case IXGBE_ERR_EEPROM_VERSION:
4781 /* We are running on a pre-production device, log a warning */
849c4542 4782 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4783 "Please be aware there may be issues associated with "
849c4542
ET		 4784 "your hardware. If you are experiencing problems "
4785 "please contact your Intel or hardware "
4786 "representative who provided you with this "
4787 "hardware.\n");
794caeb2 4788 break;
da4dd0f7 4789 default:
849c4542 4790 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4791 }
9a799d71 4792
7086400d
AD		 4793 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4794
9a799d71 4795 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4796 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4797
4798 /* update SAN MAC vmdq pool selection */
4799 if (hw->mac.san_mac_rar_index)
4800 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4801
8fecf67c 4802 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4803 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4804}
4805
9a799d71
AK		 4806/**
4807 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4808 * @tx_ring: ring to be cleaned
4809 **/
b6ec895e 4810static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4811{
4812 struct ixgbe_tx_buffer *tx_buffer_info;
4813 unsigned long size;
b6ec895e 4814 u16 i;
9a799d71 4815
84418e3b
AD		 4816 /* ring already cleared, nothing to do */
4817 if (!tx_ring->tx_buffer_info)
4818 return;
9a799d71 4819
84418e3b 4820 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4821 for (i = 0; i < tx_ring->count; i++) {
4822 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4823 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4824 }
4825
dad8a3b3
JF		 4826 netdev_tx_reset_queue(txring_txq(tx_ring));
4827
9a799d71
AK		 4828 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4829 memset(tx_ring->tx_buffer_info, 0, size);
4830
4831 /* Zero out the descriptor ring */
4832 memset(tx_ring->desc, 0, tx_ring->size);
4833
4834 tx_ring->next_to_use = 0;
4835 tx_ring->next_to_clean = 0;
9a799d71
AK		 4836}
4837
4838/**
021230d4 4839 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4840 * @adapter: board private structure
4841 **/
021230d4 4842static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4843{
4844 int i;
4845
021230d4 4846 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4847 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4848}
4849
4850/**
021230d4 4851 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4852 * @adapter: board private structure
4853 **/
021230d4 4854static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4855{
4856 int i;
4857
021230d4 4858 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4859 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4860}
4861
e4911d57
AD		 4862static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4863{
b67bfe0d 4864 struct hlist_node *node2;
e4911d57
AD		 4865 struct ixgbe_fdir_filter *filter;
4866
4867 spin_lock(&adapter->fdir_perfect_lock);
4868
b67bfe0d 4869 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4870 &adapter->fdir_filter_list, fdir_node) {
4871 hlist_del(&filter->fdir_node);
4872 kfree(filter);
4873 }
4874 adapter->fdir_filter_count = 0;
4875
4876 spin_unlock(&adapter->fdir_perfect_lock);
4877}
4878
9a799d71
AK		 4879void ixgbe_down(struct ixgbe_adapter *adapter)
4880{
4881 struct net_device *netdev = adapter->netdev;
7f821875 4882 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4883 struct net_device *upper;
4884 struct list_head *iter;
9a799d71 4885 u32 rxctrl;
bf29ee6c 4886 int i;
9a799d71
AK		 4887
4888 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4889 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4890 return; /* do nothing if already down */
9a799d71
AK		 4891
4892 /* disable receives */
7f821875
JB		 4893 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4894 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4895
2d39d576
YZ		 4896 /* disable all enabled rx queues */
4897 for (i = 0; i < adapter->num_rx_queues; i++)
4898 /* this call also flushes the previous write */
4899 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4900
032b4325 4901 usleep_range(10000, 20000);
9a799d71 4902
7f821875
JB		 4903 netif_tx_stop_all_queues(netdev);
4904
7086400d 4905 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4906 netif_carrier_off(netdev);
4907 netif_tx_disable(netdev);
4908
2a47fa45
JF		 4909 /* disable any upper devices */
4910 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4911 if (netif_is_macvlan(upper)) {
4912 struct macvlan_dev *vlan = netdev_priv(upper);
4913
4914 if (vlan->fwd_priv) {
4915 netif_tx_stop_all_queues(upper);
4916 netif_carrier_off(upper);
4917 netif_tx_disable(upper);
4918 }
4919 }
4920 }
4921
c0dfb90e
JF		 4922 ixgbe_irq_disable(adapter);
4923
4924 ixgbe_napi_disable_all(adapter);
4925
d034acf1
AD		 4926 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4927 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4928 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4929
4930 del_timer_sync(&adapter->service_timer);
4931
34cecbbf 4932 if (adapter->num_vfs) {
8e34d1aa
AD		 4933 /* Clear EITR Select mapping */
4934 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4935
4936 /* Mark all the VFs as inactive */
4937 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4938 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4939
34cecbbf
AD		 4940 /* ping all the active vfs to let them know we are going down */
4941 ixgbe_ping_all_vfs(adapter);
4942
4943 /* Disable all VFTE/VFRE TX/RX */
4944 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4945 }
4946
7f821875
JB		 4947 /* disable transmits in the hardware now that interrupts are off */
4948 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4949 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4950 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4951 }
34cecbbf
AD		 4952
4953 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4954 switch (hw->mac.type) {
4955 case ixgbe_mac_82599EB:
b93a2226 4956 case ixgbe_mac_X540:
88512539 4957 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4958 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4959 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4960 break;
4961 default:
4962 break;
4963 }
7f821875 4964
6f4a0e45
PL		 4965 if (!pci_channel_offline(adapter->pdev))
4966 ixgbe_reset(adapter);
c6ecf39a 4967
ec74a471
ET		 4968 /* power down the optics for 82599 SFP+ fiber */
4969 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4970 hw->mac.ops.disable_tx_laser(hw);
4971
9a799d71
AK		 4972 ixgbe_clean_all_tx_rings(adapter);
4973 ixgbe_clean_all_rx_rings(adapter);
4974
5dd2d332 4975#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4976 /* since we reset the hardware DCA settings were cleared */
e35ec126 4977 ixgbe_setup_dca(adapter);
96b0e0f6 4978#endif
9a799d71
AK		 4979}
4980
9a799d71
AK		 4981/**
4982 * ixgbe_tx_timeout - Respond to a Tx Hang
4983 * @netdev: network interface device structure
4984 **/
4985static void ixgbe_tx_timeout(struct net_device *netdev)
4986{
4987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4988
4989 /* Do the reset outside of interrupt context */
c83c6cbd 4990 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4991}
4992
9a799d71
AK		 4993/**
4994 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4995 * @adapter: board private structure to initialize
4996 *
4997 * ixgbe_sw_init initializes the Adapter private data structure.
4998 * Fields are initialized based on PCI device information and
4999 * OS network device settings (MTU size).
5000 **/
9f9a12f8 5001static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5002{
5003 struct ixgbe_hw *hw = &adapter->hw;
5004 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5005 unsigned int rss, fdir;
cb6d0f5e 5006 u32 fwsm;
7a6b6f51 5007#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5008 int j;
5009 struct tc_configuration *tc;
5010#endif
021230d4 5011
c44ade9e
JB		 5012 /* PCI config space info */
5013
5014 hw->vendor_id = pdev->vendor;
5015 hw->device_id = pdev->device;
5016 hw->revision_id = pdev->revision;
5017 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5018 hw->subsystem_device_id = pdev->subsystem_device;
5019
8fc3bb6d 5020 /* Set common capability flags and settings */
3ed69d7e 5021 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5022 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5023 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5024 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5025 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5026 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5027 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5028 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5029 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5030#ifdef CONFIG_IXGBE_DCA
5031 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5032#endif
5033#ifdef IXGBE_FCOE
5034 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5035 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5036#ifdef CONFIG_IXGBE_DCB
5037 /* Default traffic class to use for FCoE */
5038 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5039#endif /* CONFIG_IXGBE_DCB */
5040#endif /* IXGBE_FCOE */
5041
5042 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5043 switch (hw->mac.type) {
5044 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5045 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5046 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5047
bf069c97
DS		 5048 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5049 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5050
49c7ffbe 5051 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5052 adapter->ring_feature[RING_F_FDIR].limit = 0;
5053 adapter->atr_sample_rate = 0;
5054 adapter->fdir_pballoc = 0;
5055#ifdef IXGBE_FCOE
5056 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5057 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5058#ifdef CONFIG_IXGBE_DCB
5059 adapter->fcoe.up = 0;
5060#endif /* IXGBE_DCB */
5061#endif /* IXGBE_FCOE */
5062 break;
5063 case ixgbe_mac_82599EB:
5064 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5065 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5066 break;
b93a2226 5067 case ixgbe_mac_X540:
cb6d0f5e
JK		 5068 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5069 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5070 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5071 break;
5072 default:
5073 break;
f8212f97 5074 }
2f90b865 5075
7c8ae65a
AD		 5076#ifdef IXGBE_FCOE
5077 /* FCoE support exists, always init the FCoE lock */
5078 spin_lock_init(&adapter->fcoe.lock);
5079
5080#endif
1fc5f038
AD		 5081 /* n-tuple support exists, always init our spinlock */
5082 spin_lock_init(&adapter->fdir_perfect_lock);
5083
7a6b6f51 5084#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5085 switch (hw->mac.type) {
5086 case ixgbe_mac_X540:
5087 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5088 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5089 break;
5090 default:
5091 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5092 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5093 break;
5094 }
5095
2f90b865
AD		 5096 /* Configure DCB traffic classes */
5097 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5098 tc = &adapter->dcb_cfg.tc_config[j];
5099 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5100 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5101 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5102 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5103 tc->dcb_pfc = pfc_disabled;
5104 }
4de2a022
JF		 5105
5106 /* Initialize default user to priority mapping, UPx->TC0 */
5107 tc = &adapter->dcb_cfg.tc_config[0];
5108 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5109 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5110
2f90b865
AD		 5111 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5112 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5113 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5114 adapter->dcb_set_bitmap = 0x00;
3032309b 5115 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5116 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5117 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5118
5119#endif
9a799d71
AK		 5120
5121 /* default flow control settings */
cd7664f6 5122 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5123 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5124 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5125 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5126 hw->fc.send_xon = true;
73d80953 5127 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5128
99d74487 5129#ifdef CONFIG_PCI_IOV
170e8543
JK		 5130 if (max_vfs > 0)
5131 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5132
99d74487 5133 /* assign number of SR-IOV VFs */
170e8543 5134 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5135 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5136 adapter->num_vfs = 0;
5137 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5138 } else {
5139 adapter->num_vfs = max_vfs;
5140 }
5141 }
5142#endif /* CONFIG_PCI_IOV */
99d74487 5143
30efa5a3 5144 /* enable itr by default in dynamic mode */
f7554a2b 5145 adapter->rx_itr_setting = 1;
f7554a2b 5146 adapter->tx_itr_setting = 1;
30efa5a3 5147
30efa5a3
JB		 5148 /* set default ring sizes */
5149 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5150 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5151
bd198058 5152 /* set default work limits */
59224555 5153 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5154
9a799d71 5155 /* initialize eeprom parameters */
c44ade9e 5156 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5157 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5158 return -EIO;
5159 }
5160
2a47fa45
JF		 5161 /* PF holds first pool slot */
5162 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5163 set_bit(__IXGBE_DOWN, &adapter->state);
5164
5165 return 0;
5166}
5167
5168/**
5169 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5170 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5171 *
5172 * Return 0 on success, negative on failure
5173 **/
b6ec895e 5174int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5175{
b6ec895e 5176 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5177 int orig_node = dev_to_node(dev);
5178 int numa_node = -1;
9a799d71
AK		 5179 int size;
5180
3a581073 5181 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5182
5183 if (tx_ring->q_vector)
5184 numa_node = tx_ring->q_vector->numa_node;
5185
5186 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5187 if (!tx_ring->tx_buffer_info)
89bf67f1 5188 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5189 if (!tx_ring->tx_buffer_info)
5190 goto err;
9a799d71 5191
827da44c
JS		 5192 u64_stats_init(&tx_ring->syncp);
5193
9a799d71 5194 /* round up to nearest 4K */
12207e49 5195 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5196 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5197
de88eeeb
AD		 5198 set_dev_node(dev, numa_node);
5199 tx_ring->desc = dma_alloc_coherent(dev,
5200 tx_ring->size,
5201 &tx_ring->dma,
5202 GFP_KERNEL);
5203 set_dev_node(dev, orig_node);
5204 if (!tx_ring->desc)
5205 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5206 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5207 if (!tx_ring->desc)
5208 goto err;
9a799d71 5209
3a581073
JB		 5210 tx_ring->next_to_use = 0;
5211 tx_ring->next_to_clean = 0;
9a799d71 5212 return 0;
e01c31a5
JB		 5213
5214err:
5215 vfree(tx_ring->tx_buffer_info);
5216 tx_ring->tx_buffer_info = NULL;
b6ec895e 5217 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5218 return -ENOMEM;
9a799d71
AK		 5219}
5220
69888674
AD		 5221/**
5222 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5223 * @adapter: board private structure
5224 *
5225 * If this function returns with an error, then it's possible one or
5226 * more of the rings is populated (while the rest are not). It is the
5227 * callers duty to clean those orphaned rings.
5228 *
5229 * Return 0 on success, negative on failure
5230 **/
5231static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5232{
5233 int i, err = 0;
5234
5235 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5236 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5237 if (!err)
5238 continue;
de3d5b94 5239
396e799c 5240 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5241 goto err_setup_tx;
69888674
AD		 5242 }
5243
de3d5b94
AD		 5244 return 0;
5245err_setup_tx:
5246 /* rewind the index freeing the rings as we go */
5247 while (i--)
5248 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5249 return err;
5250}
5251
9a799d71
AK		 5252/**
5253 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5254 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5255 *
5256 * Returns 0 on success, negative on failure
5257 **/
b6ec895e 5258int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5259{
b6ec895e 5260 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5261 int orig_node = dev_to_node(dev);
5262 int numa_node = -1;
021230d4 5263 int size;
9a799d71 5264
3a581073 5265 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5266
5267 if (rx_ring->q_vector)
5268 numa_node = rx_ring->q_vector->numa_node;
5269
5270 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5271 if (!rx_ring->rx_buffer_info)
89bf67f1 5272 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5273 if (!rx_ring->rx_buffer_info)
5274 goto err;
9a799d71 5275
827da44c
JS		 5276 u64_stats_init(&rx_ring->syncp);
5277
9a799d71 5278 /* Round up to nearest 4K */
3a581073
JB		 5279 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5280 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5281
de88eeeb
AD		 5282 set_dev_node(dev, numa_node);
5283 rx_ring->desc = dma_alloc_coherent(dev,
5284 rx_ring->size,
5285 &rx_ring->dma,
5286 GFP_KERNEL);
5287 set_dev_node(dev, orig_node);
5288 if (!rx_ring->desc)
5289 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5290 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5291 if (!rx_ring->desc)
5292 goto err;
9a799d71 5293
3a581073
JB		 5294 rx_ring->next_to_clean = 0;
5295 rx_ring->next_to_use = 0;
9a799d71
AK		 5296
5297 return 0;
b6ec895e
AD		 5298err:
5299 vfree(rx_ring->rx_buffer_info);
5300 rx_ring->rx_buffer_info = NULL;
5301 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5302 return -ENOMEM;
9a799d71
AK		 5303}
5304
69888674
AD		 5305/**
5306 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5307 * @adapter: board private structure
5308 *
5309 * If this function returns with an error, then it's possible one or
5310 * more of the rings is populated (while the rest are not). It is the
5311 * callers duty to clean those orphaned rings.
5312 *
5313 * Return 0 on success, negative on failure
5314 **/
69888674
AD		 5315static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5316{
5317 int i, err = 0;
5318
5319 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5320 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5321 if (!err)
5322 continue;
de3d5b94 5323
396e799c 5324 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5325 goto err_setup_rx;
69888674
AD		 5326 }
5327
7c8ae65a
AD		 5328#ifdef IXGBE_FCOE
5329 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5330 if (!err)
5331#endif
5332 return 0;
de3d5b94
AD		 5333err_setup_rx:
5334 /* rewind the index freeing the rings as we go */
5335 while (i--)
5336 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5337 return err;
5338}
5339
9a799d71
AK		 5340/**
5341 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5342 * @tx_ring: Tx descriptor ring for a specific queue
5343 *
5344 * Free all transmit software resources
5345 **/
b6ec895e 5346void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5347{
b6ec895e 5348 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5349
5350 vfree(tx_ring->tx_buffer_info);
5351 tx_ring->tx_buffer_info = NULL;
5352
b6ec895e
AD		 5353 /* if not set, then don't free */
5354 if (!tx_ring->desc)
5355 return;
5356
5357 dma_free_coherent(tx_ring->dev, tx_ring->size,
5358 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5359
5360 tx_ring->desc = NULL;
5361}
5362
5363/**
5364 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5365 * @adapter: board private structure
5366 *
5367 * Free all transmit software resources
5368 **/
5369static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5370{
5371 int i;
5372
5373 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5374 if (adapter->tx_ring[i]->desc)
b6ec895e 5375 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5376}
5377
5378/**
b4617240 5379 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5380 * @rx_ring: ring to clean the resources from
5381 *
5382 * Free all receive software resources
5383 **/
b6ec895e 5384void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5385{
b6ec895e 5386 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5387
5388 vfree(rx_ring->rx_buffer_info);
5389 rx_ring->rx_buffer_info = NULL;
5390
b6ec895e
AD		 5391 /* if not set, then don't free */
5392 if (!rx_ring->desc)
5393 return;
5394
5395 dma_free_coherent(rx_ring->dev, rx_ring->size,
5396 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5397
5398 rx_ring->desc = NULL;
5399}
5400
5401/**
5402 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5403 * @adapter: board private structure
5404 *
5405 * Free all receive software resources
5406 **/
5407static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5408{
5409 int i;
5410
7c8ae65a
AD		 5411#ifdef IXGBE_FCOE
5412 ixgbe_free_fcoe_ddp_resources(adapter);
5413
5414#endif
9a799d71 5415 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5416 if (adapter->rx_ring[i]->desc)
b6ec895e 5417 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5418}
5419
9a799d71
AK		 5420/**
5421 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5422 * @netdev: network interface device structure
5423 * @new_mtu: new value for maximum frame size
5424 *
5425 * Returns 0 on success, negative on failure
5426 **/
5427static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5428{
5429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5430 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5431
42c783c5 5432 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5433 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5434 return -EINVAL;
5435
5436 /*
872844dd
AD		 5437 * For 82599EB we cannot allow legacy VFs to enable their receive
5438 * paths when MTU greater than 1500 is configured. So display a
5439 * warning that legacy VFs will be disabled.
655309e9
AD		 5440 */
5441 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5442 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5443 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5444 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5445
396e799c 5446 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5447
021230d4 5448 /* must set new MTU before calling down or up */
9a799d71
AK		 5449 netdev->mtu = new_mtu;
5450
d4f80882
AV		 5451 if (netif_running(netdev))
5452 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5453
5454 return 0;
5455}
5456
5457/**
5458 * ixgbe_open - Called when a network interface is made active
5459 * @netdev: network interface device structure
5460 *
5461 * Returns 0 on success, negative value on failure
5462 *
5463 * The open entry point is called when a network interface is made
5464 * active by the system (IFF_UP). At this point all resources needed
5465 * for transmit and receive operations are allocated, the interrupt
5466 * handler is registered with the OS, the watchdog timer is started,
5467 * and the stack is notified that the interface is ready.
5468 **/
5469static int ixgbe_open(struct net_device *netdev)
5470{
5471 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5472 int err, queues;
4bebfaa5
AK		 5473
5474 /* disallow open during test */
5475 if (test_bit(__IXGBE_TESTING, &adapter->state))
5476 return -EBUSY;
9a799d71 5477
54386467
JB		 5478 netif_carrier_off(netdev);
5479
9a799d71
AK		 5480 /* allocate transmit descriptors */
5481 err = ixgbe_setup_all_tx_resources(adapter);
5482 if (err)
5483 goto err_setup_tx;
5484
9a799d71
AK		 5485 /* allocate receive descriptors */
5486 err = ixgbe_setup_all_rx_resources(adapter);
5487 if (err)
5488 goto err_setup_rx;
5489
5490 ixgbe_configure(adapter);
5491
021230d4 5492 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5493 if (err)
5494 goto err_req_irq;
5495
ac802f5d 5496 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5497 if (adapter->num_rx_pools > 1)
5498 queues = adapter->num_rx_queues_per_pool;
5499 else
5500 queues = adapter->num_tx_queues;
5501
5502 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5503 if (err)
5504 goto err_set_queues;
5505
2a47fa45
JF		 5506 if (adapter->num_rx_pools > 1 &&
5507 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5508 queues = IXGBE_MAX_L2A_QUEUES;
5509 else
5510 queues = adapter->num_rx_queues;
5511 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5512 if (err)
5513 goto err_set_queues;
5514
1a71ab24 5515 ixgbe_ptp_init(adapter);
1a71ab24 5516
c7ccde0f 5517 ixgbe_up_complete(adapter);
9a799d71
AK		 5518
5519 return 0;
5520
ac802f5d
AD		 5521err_set_queues:
5522 ixgbe_free_irq(adapter);
9a799d71 5523err_req_irq:
a20a1199 5524 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5525err_setup_rx:
a20a1199 5526 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5527err_setup_tx:
9a799d71
AK		 5528 ixgbe_reset(adapter);
5529
5530 return err;
5531}
5532
5533/**
5534 * ixgbe_close - Disables a network interface
5535 * @netdev: network interface device structure
5536 *
5537 * Returns 0, this is not allowed to fail
5538 *
5539 * The close entry point is called when an interface is de-activated
5540 * by the OS. The hardware is still under the drivers control, but
5541 * needs to be disabled. A global MAC reset is issued to stop the
5542 * hardware, and all transmit and receive resources are freed.
5543 **/
5544static int ixgbe_close(struct net_device *netdev)
5545{
5546 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5547
1a71ab24 5548 ixgbe_ptp_stop(adapter);
1a71ab24 5549
9a799d71
AK		 5550 ixgbe_down(adapter);
5551 ixgbe_free_irq(adapter);
5552
e4911d57
AD		 5553 ixgbe_fdir_filter_exit(adapter);
5554
9a799d71
AK		 5555 ixgbe_free_all_tx_resources(adapter);
5556 ixgbe_free_all_rx_resources(adapter);
5557
5eba3699 5558 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5559
5560 return 0;
5561}
5562
b3c8b4ba
AD		 5563#ifdef CONFIG_PM
5564static int ixgbe_resume(struct pci_dev *pdev)
5565{
c60fbb00
AD		 5566 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5567 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5568 u32 err;
5569
0391bbe3 5570 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5571 pci_set_power_state(pdev, PCI_D0);
5572 pci_restore_state(pdev);
656ab817
DS		 5573 /*
5574 * pci_restore_state clears dev->state_saved so call
5575 * pci_save_state to restore it.
5576 */
5577 pci_save_state(pdev);
9ce77666 5578
5579 err = pci_enable_device_mem(pdev);
b3c8b4ba 5580 if (err) {
849c4542 5581 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5582 return err;
5583 }
5584 pci_set_master(pdev);
5585
dd4d8ca6 5586 pci_wake_from_d3(pdev, false);
b3c8b4ba 5587
b3c8b4ba
AD		 5588 ixgbe_reset(adapter);
5589
495dce12
WJP		 5590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5591
ac802f5d
AD		 5592 rtnl_lock();
5593 err = ixgbe_init_interrupt_scheme(adapter);
5594 if (!err && netif_running(netdev))
c60fbb00 5595 err = ixgbe_open(netdev);
ac802f5d
AD		 5596
5597 rtnl_unlock();
5598
5599 if (err)
5600 return err;
b3c8b4ba
AD		 5601
5602 netif_device_attach(netdev);
5603
5604 return 0;
5605}
b3c8b4ba 5606#endif /* CONFIG_PM */
9d8d05ae
RW		 5607
5608static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5609{
c60fbb00
AD		 5610 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5611 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5612 struct ixgbe_hw *hw = &adapter->hw;
5613 u32 ctrl, fctrl;
5614 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5615#ifdef CONFIG_PM
5616 int retval = 0;
5617#endif
5618
5619 netif_device_detach(netdev);
5620
499ab5cc 5621 rtnl_lock();
b3c8b4ba
AD		 5622 if (netif_running(netdev)) {
5623 ixgbe_down(adapter);
5624 ixgbe_free_irq(adapter);
5625 ixgbe_free_all_tx_resources(adapter);
5626 ixgbe_free_all_rx_resources(adapter);
5627 }
499ab5cc 5628 rtnl_unlock();
b3c8b4ba 5629
5f5ae6fc
AD		 5630 ixgbe_clear_interrupt_scheme(adapter);
5631
b3c8b4ba
AD		 5632#ifdef CONFIG_PM
5633 retval = pci_save_state(pdev);
5634 if (retval)
5635 return retval;
4df10466 5636
b3c8b4ba 5637#endif
f4f1040a
JK		 5638 if (hw->mac.ops.stop_link_on_d3)
5639 hw->mac.ops.stop_link_on_d3(hw);
5640
e8e26350
PW		 5641 if (wufc) {
5642 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5643
ec74a471
ET		 5644 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5645 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5646 hw->mac.ops.enable_tx_laser(hw);
5647
e8e26350
PW		 5648 /* turn on all-multi mode if wake on multicast is enabled */
5649 if (wufc & IXGBE_WUFC_MC) {
5650 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5651 fctrl |= IXGBE_FCTRL_MPE;
5652 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5653 }
5654
5655 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5656 ctrl |= IXGBE_CTRL_GIO_DIS;
5657 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5658
5659 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5660 } else {
5661 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5662 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5663 }
5664
bd508178
AD		 5665 switch (hw->mac.type) {
5666 case ixgbe_mac_82598EB:
dd4d8ca6 5667 pci_wake_from_d3(pdev, false);
bd508178
AD		 5668 break;
5669 case ixgbe_mac_82599EB:
b93a2226 5670 case ixgbe_mac_X540:
bd508178
AD		 5671 pci_wake_from_d3(pdev, !!wufc);
5672 break;
5673 default:
5674 break;
5675 }
b3c8b4ba 5676
9d8d05ae
RW		 5677 *enable_wake = !!wufc;
5678
b3c8b4ba
AD		 5679 ixgbe_release_hw_control(adapter);
5680
5681 pci_disable_device(pdev);
5682
9d8d05ae
RW		 5683 return 0;
5684}
5685
5686#ifdef CONFIG_PM
5687static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5688{
5689 int retval;
5690 bool wake;
5691
5692 retval = __ixgbe_shutdown(pdev, &wake);
5693 if (retval)
5694 return retval;
5695
5696 if (wake) {
5697 pci_prepare_to_sleep(pdev);
5698 } else {
5699 pci_wake_from_d3(pdev, false);
5700 pci_set_power_state(pdev, PCI_D3hot);
5701 }
b3c8b4ba
AD		 5702
5703 return 0;
5704}
9d8d05ae 5705#endif /* CONFIG_PM */
b3c8b4ba
AD		 5706
5707static void ixgbe_shutdown(struct pci_dev *pdev)
5708{
9d8d05ae
RW		 5709 bool wake;
5710
5711 __ixgbe_shutdown(pdev, &wake);
5712
5713 if (system_state == SYSTEM_POWER_OFF) {
5714 pci_wake_from_d3(pdev, wake);
5715 pci_set_power_state(pdev, PCI_D3hot);
5716 }
b3c8b4ba
AD		 5717}
5718
9a799d71
AK		 5719/**
5720 * ixgbe_update_stats - Update the board statistics counters.
5721 * @adapter: board private structure
5722 **/
5723void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5724{
2d86f139 5725 struct net_device *netdev = adapter->netdev;
9a799d71 5726 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5727 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5728 u64 total_mpc = 0;
5729 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5730 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5731 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5732 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5733
d08935c2
DS		 5734 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5735 test_bit(__IXGBE_RESETTING, &adapter->state))
5736 return;
5737
94b982b2 5738 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5739 u64 rsc_count = 0;
94b982b2 5740 u64 rsc_flush = 0;
94b982b2 5741 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5742 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5743 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5744 }
5745 adapter->rsc_total_count = rsc_count;
5746 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5747 }
5748
5b7da515
AD		 5749 for (i = 0; i < adapter->num_rx_queues; i++) {
5750 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5751 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5752 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5753 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5754 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5755 bytes += rx_ring->stats.bytes;
5756 packets += rx_ring->stats.packets;
5757 }
5758 adapter->non_eop_descs = non_eop_descs;
5759 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5760 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5761 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5762 netdev->stats.rx_bytes = bytes;
5763 netdev->stats.rx_packets = packets;
5764
5765 bytes = 0;
5766 packets = 0;
7ca3bc58 5767 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5768 for (i = 0; i < adapter->num_tx_queues; i++) {
5769 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5770 restart_queue += tx_ring->tx_stats.restart_queue;
5771 tx_busy += tx_ring->tx_stats.tx_busy;
5772 bytes += tx_ring->stats.bytes;
5773 packets += tx_ring->stats.packets;
5774 }
eb985f09 5775 adapter->restart_queue = restart_queue;
5b7da515
AD		 5776 adapter->tx_busy = tx_busy;
5777 netdev->stats.tx_bytes = bytes;
5778 netdev->stats.tx_packets = packets;
7ca3bc58 5779
7ca647bd 5780 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5781
5782 /* 8 register reads */
6f11eef7
AV		 5783 for (i = 0; i < 8; i++) {
5784 /* for packet buffers not used, the register should read 0 */
5785 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5786 missed_rx += mpc;
7ca647bd
JP		 5787 hwstats->mpc[i] += mpc;
5788 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5789 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5790 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5791 switch (hw->mac.type) {
5792 case ixgbe_mac_82598EB:
1a70db4b
ET		 5793 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5794 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5795 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5796 hwstats->pxonrxc[i] +=
5797 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5798 break;
5799 case ixgbe_mac_82599EB:
b93a2226 5800 case ixgbe_mac_X540:
bd508178
AD		 5801 hwstats->pxonrxc[i] +=
5802 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5803 break;
5804 default:
5805 break;
e8e26350 5806 }
6f11eef7 5807 }
1a70db4b
ET		 5808
5809 /*16 register reads */
5810 for (i = 0; i < 16; i++) {
5811 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5812 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5813 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5814 (hw->mac.type == ixgbe_mac_X540)) {
5815 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5816 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5817 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5818 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5819 }
5820 }
5821
7ca647bd 5822 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5823 /* work around hardware counting issue */
7ca647bd 5824 hwstats->gprc -= missed_rx;
6f11eef7 5825
c84d324c
JF		 5826 ixgbe_update_xoff_received(adapter);
5827
6f11eef7 5828 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5829 switch (hw->mac.type) {
5830 case ixgbe_mac_82598EB:
5831 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5832 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5833 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5834 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5835 break;
b93a2226 5836 case ixgbe_mac_X540:
58f6bcf9
ET		 5837 /* OS2BMC stats are X540 only*/
5838 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5839 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5840 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5841 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5842 case ixgbe_mac_82599EB:
a4d4f629
AD		 5843 for (i = 0; i < 16; i++)
5844 adapter->hw_rx_no_dma_resources +=
5845 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5846 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5847 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5848 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5849 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5850 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5851 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5852 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5853 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5854 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5855#ifdef IXGBE_FCOE
7ca647bd
JP		 5856 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5857 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5858 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5859 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5860 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5861 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5862 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5863 if (adapter->fcoe.ddp_pool) {
5864 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5865 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5866 unsigned int cpu;
5867 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5868 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5869 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5870 noddp += ddp_pool->noddp;
5871 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5872 }
5a1ee270
AD		 5873 hwstats->fcoe_noddp = noddp;
5874 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5875 }
6d45522c 5876#endif /* IXGBE_FCOE */
bd508178
AD		 5877 break;
5878 default:
5879 break;
e8e26350 5880 }
9a799d71 5881 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5882 hwstats->bprc += bprc;
5883 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5884 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5885 hwstats->mprc -= bprc;
5886 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5887 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5888 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5889 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5890 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5891 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5892 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5893 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5894 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5895 hwstats->lxontxc += lxon;
6f11eef7 5896 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5897 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5898 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5899 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5900 /*
5901 * 82598 errata - tx of flow control packets is included in tx counters
5902 */
5903 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5904 hwstats->gptc -= xon_off_tot;
5905 hwstats->mptc -= xon_off_tot;
5906 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5907 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5908 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5909 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5910 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5911 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5912 hwstats->ptc64 -= xon_off_tot;
5913 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5914 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5915 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5916 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5917 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5918 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5919
5920 /* Fill out the OS statistics structure */
7ca647bd 5921 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5922
5923 /* Rx Errors */
7ca647bd 5924 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5925 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5926 netdev->stats.rx_length_errors = hwstats->rlec;
5927 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5928 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5929}
5930
5931/**
d034acf1 5932 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5933 * @adapter: pointer to the device adapter structure
9a799d71 5934 **/
d034acf1 5935static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5936{
cf8280ee 5937 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5938 int i;
cf8280ee 5939
d034acf1
AD		 5940 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5941 return;
5942
5943 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5944
d034acf1 5945 /* if interface is down do nothing */
fe49f04a 5946 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5947 return;
5948
5949 /* do nothing if we are not using signature filters */
5950 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5951 return;
5952
5953 adapter->fdir_overflow++;
5954
93c52dd0
AD		 5955 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5956 for (i = 0; i < adapter->num_tx_queues; i++)
5957 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5958 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5959 /* re-enable flow director interrupts */
5960 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5961 } else {
5962 e_err(probe, "failed to finish FDIR re-initialization, "
5963 "ignored adding FDIR ATR filters\n");
5964 }
93c52dd0
AD		 5965}
5966
5967/**
5968 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5969 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5970 *
5971 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5972 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5973 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5974 * determine if a hang has occurred.
93c52dd0
AD		 5975 */
5976static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5977{
cf8280ee 5978 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5979 u64 eics = 0;
5980 int i;
cf8280ee 5981
09f40aed 5982 /* If we're down, removing or resetting, just bail */
93c52dd0 5983 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 5984 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 5985 test_bit(__IXGBE_RESETTING, &adapter->state))
5986 return;
22d5a71b 5987
93c52dd0
AD		 5988 /* Force detection of hung controller */
5989 if (netif_carrier_ok(adapter->netdev)) {
5990 for (i = 0; i < adapter->num_tx_queues; i++)
5991 set_check_for_tx_hang(adapter->tx_ring[i]);
5992 }
22d5a71b 5993
fe49f04a
AD		 5994 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5995 /*
5996 * for legacy and MSI interrupts don't set any bits
5997 * that are enabled for EIAM, because this operation
5998 * would set *both* EIMS and EICS for any bit in EIAM
5999 */
6000 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6001 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6002 } else {
6003 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6004 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6005 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6006 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6007 eics |= ((u64)1 << i);
6008 }
cf8280ee 6009 }
9a799d71 6010
93c52dd0 6011 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6012 ixgbe_irq_rearm_queues(adapter, eics);
6013
cf8280ee
JB		 6014}
6015
e8e26350 6016/**
93c52dd0 6017 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6018 * @adapter: pointer to the device adapter structure
6019 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6020 **/
93c52dd0 6021static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6022{
e8e26350 6023 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6024 u32 link_speed = adapter->link_speed;
6025 bool link_up = adapter->link_up;
041441d0 6026 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6027
93c52dd0
AD		 6028 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6029 return;
6030
6031 if (hw->mac.ops.check_link) {
6032 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6033 } else {
93c52dd0
AD		 6034 /* always assume link is up, if no check link function */
6035 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6036 link_up = true;
c4cf55e5 6037 }
041441d0
AD		 6038
6039 if (adapter->ixgbe_ieee_pfc)
6040 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6041
3ebe8fde 6042 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6043 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6044 ixgbe_set_rx_drop_en(adapter);
6045 }
93c52dd0
AD		 6046
6047 if (link_up ||
6048 time_after(jiffies, (adapter->link_check_timeout +
6049 IXGBE_TRY_LINK_TIMEOUT))) {
6050 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6051 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6052 IXGBE_WRITE_FLUSH(hw);
6053 }
6054
6055 adapter->link_up = link_up;
6056 adapter->link_speed = link_speed;
e8e26350
PW		 6057}
6058
107d3018
AD		 6059static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6060{
6061#ifdef CONFIG_IXGBE_DCB
6062 struct net_device *netdev = adapter->netdev;
6063 struct dcb_app app = {
6064 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6065 .protocol = 0,
6066 };
6067 u8 up = 0;
6068
6069 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6070 up = dcb_ieee_getapp_mask(netdev, &app);
6071
6072 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6073#endif
6074}
6075
e8e26350 6076/**
93c52dd0
AD		 6077 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6078 * print link up message
49ce9c2c 6079 * @adapter: pointer to the device adapter structure
e8e26350 6080 **/
93c52dd0 6081static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6082{
93c52dd0 6083 struct net_device *netdev = adapter->netdev;
e8e26350 6084 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6085 u32 link_speed = adapter->link_speed;
6086 bool flow_rx, flow_tx;
e8e26350 6087
93c52dd0
AD		 6088 /* only continue if link was previously down */
6089 if (netif_carrier_ok(netdev))
a985b6c3 6090 return;
63d6e1d8 6091
93c52dd0 6092 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6093
93c52dd0
AD		 6094 switch (hw->mac.type) {
6095 case ixgbe_mac_82598EB: {
6096 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6097 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6098 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6099 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6100 }
6101 break;
6102 case ixgbe_mac_X540:
6103 case ixgbe_mac_82599EB: {
6104 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6105 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6106 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6107 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6108 }
6109 break;
6110 default:
6111 flow_tx = false;
6112 flow_rx = false;
6113 break;
e8e26350 6114 }
3a6a4eda 6115
6cb562d6
JK		 6116 adapter->last_rx_ptp_check = jiffies;
6117
8fecf67c 6118 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6119 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6120
93c52dd0
AD		 6121 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6122 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6123 "10 Gbps" :
6124 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6125 "1 Gbps" :
6126 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6127 "100 Mbps" :
6128 "unknown speed"))),
6129 ((flow_rx && flow_tx) ? "RX/TX" :
6130 (flow_rx ? "RX" :
6131 (flow_tx ? "TX" : "None"))));
e8e26350 6132
93c52dd0 6133 netif_carrier_on(netdev);
93c52dd0 6134 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6135
107d3018
AD		 6136 /* update the default user priority for VFs */
6137 ixgbe_update_default_up(adapter);
6138
befa2af7
AD		 6139 /* ping all the active vfs to let them know link has changed */
6140 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6141}
6142
c4cf55e5 6143/**
93c52dd0
AD		 6144 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6145 * print link down message
49ce9c2c 6146 * @adapter: pointer to the adapter structure
c4cf55e5 6147 **/
581330ba 6148static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6149{
cf8280ee 6150 struct net_device *netdev = adapter->netdev;
c4cf55e5 6151 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6152
93c52dd0
AD		 6153 adapter->link_up = false;
6154 adapter->link_speed = 0;
cf8280ee 6155
93c52dd0
AD		 6156 /* only continue if link was up previously */
6157 if (!netif_carrier_ok(netdev))
6158 return;
264857b8 6159
93c52dd0
AD		 6160 /* poll for SFP+ cable when link is down */
6161 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6162 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6163
8fecf67c 6164 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6165 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6166
93c52dd0
AD		 6167 e_info(drv, "NIC Link is Down\n");
6168 netif_carrier_off(netdev);
befa2af7
AD		 6169
6170 /* ping all the active vfs to let them know link has changed */
6171 ixgbe_ping_all_vfs(adapter);
93c52dd0 6172}
e8e26350 6173
93c52dd0
AD		 6174/**
6175 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6176 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6177 **/
6178static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6179{
c4cf55e5 6180 int i;
93c52dd0 6181 int some_tx_pending = 0;
c4cf55e5 6182
93c52dd0 6183 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6184 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6185 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6186 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6187 some_tx_pending = 1;
6188 break;
6189 }
6190 }
6191
6192 if (some_tx_pending) {
6193 /* We've lost link, so the controller stops DMA,
6194 * but we've got queued Tx work that's never going
6195 * to get done, so reset controller to flush Tx.
6196 * (Do the reset outside of interrupt context).
6197 */
12ff3f3b 6198 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6199 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6200 }
c4cf55e5 6201 }
c4cf55e5
PWJ		 6202}
6203
a985b6c3
GR		 6204static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6205{
6206 u32 ssvpc;
6207
0584d999
GR		 6208 /* Do not perform spoof check for 82598 or if not in IOV mode */
6209 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6210 adapter->num_vfs == 0)
a985b6c3
GR		 6211 return;
6212
6213 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6214
6215 /*
6216 * ssvpc register is cleared on read, if zero then no
6217 * spoofed packets in the last interval.
6218 */
6219 if (!ssvpc)
6220 return;
6221
d6ea0754 6222 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6223}
6224
93c52dd0
AD		 6225/**
6226 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6227 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6228 **/
6229static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6230{
09f40aed 6231 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6232 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6233 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6234 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6235 return;
6236
6237 ixgbe_watchdog_update_link(adapter);
6238
6239 if (adapter->link_up)
6240 ixgbe_watchdog_link_is_up(adapter);
6241 else
6242 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6243
a985b6c3 6244 ixgbe_spoof_check(adapter);
9a799d71 6245 ixgbe_update_stats(adapter);
93c52dd0
AD		 6246
6247 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6248}
10eec955 6249
cf8280ee 6250/**
7086400d 6251 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6252 * @adapter: the ixgbe adapter structure
cf8280ee 6253 **/
7086400d 6254static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6255{
cf8280ee 6256 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6257 s32 err;
cf8280ee 6258
7086400d
AD		 6259 /* not searching for SFP so there is nothing to do here */
6260 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6261 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6262 return;
10eec955 6263
7086400d
AD		 6264 /* someone else is in init, wait until next service event */
6265 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6266 return;
cf8280ee 6267
7086400d
AD		 6268 err = hw->phy.ops.identify_sfp(hw);
6269 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6270 goto sfp_out;
264857b8 6271
7086400d
AD		 6272 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6273 /* If no cable is present, then we need to reset
6274 * the next time we find a good cable. */
6275 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6276 }
9a799d71 6277
7086400d
AD		 6278 /* exit on error */
6279 if (err)
6280 goto sfp_out;
e8e26350 6281
7086400d
AD		 6282 /* exit if reset not needed */
6283 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6284 goto sfp_out;
9a799d71 6285
7086400d 6286 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6287
7086400d
AD		 6288 /*
6289 * A module may be identified correctly, but the EEPROM may not have
6290 * support for that module. setup_sfp() will fail in that case, so
6291 * we should not allow that module to load.
6292 */
6293 if (hw->mac.type == ixgbe_mac_82598EB)
6294 err = hw->phy.ops.reset(hw);
6295 else
6296 err = hw->mac.ops.setup_sfp(hw);
6297
6298 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6299 goto sfp_out;
6300
6301 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6302 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6303
6304sfp_out:
6305 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6306
6307 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6308 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6309 e_dev_err("failed to initialize because an unsupported "
6310 "SFP+ module type was detected.\n");
6311 e_dev_err("Reload the driver after installing a "
6312 "supported module.\n");
6313 unregister_netdev(adapter->netdev);
bc59fcda 6314 }
7086400d 6315}
bc59fcda 6316
7086400d
AD		 6317/**
6318 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6319 * @adapter: the ixgbe adapter structure
7086400d
AD		 6320 **/
6321static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6322{
6323 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6324 u32 speed;
6325 bool autoneg = false;
7086400d
AD		 6326
6327 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6328 return;
6329
6330 /* someone else is in init, wait until next service event */
6331 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6332 return;
6333
6334 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6335
3d292265 6336 speed = hw->phy.autoneg_advertised;
ed33ff66 6337 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6338 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6339
6340 /* setup the highest link when no autoneg */
6341 if (!autoneg) {
6342 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6343 speed = IXGBE_LINK_SPEED_10GB_FULL;
6344 }
6345 }
6346
7086400d 6347 if (hw->mac.ops.setup_link)
fd0326f2 6348 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6349
6350 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6351 adapter->link_check_timeout = jiffies;
6352 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6353}
6354
83c61fa9
GR		 6355#ifdef CONFIG_PCI_IOV
6356static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6357{
6358 int vf;
6359 struct ixgbe_hw *hw = &adapter->hw;
6360 struct net_device *netdev = adapter->netdev;
6361 u32 gpc;
6362 u32 ciaa, ciad;
6363
6364 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6365 if (gpc) /* If incrementing then no need for the check below */
6366 return;
6367 /*
6368 * Check to see if a bad DMA write target from an errant or
6369 * malicious VF has caused a PCIe error. If so then we can
6370 * issue a VFLR to the offending VF(s) and then resume without
6371 * requesting a full slot reset.
6372 */
6373
6374 for (vf = 0; vf < adapter->num_vfs; vf++) {
6375 ciaa = (vf << 16) | 0x80000000;
6376 /* 32 bit read so align, we really want status at offset 6 */
6377 ciaa |= PCI_COMMAND;
6378 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6379 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6380 ciaa &= 0x7FFFFFFF;
6381 /* disable debug mode asap after reading data */
6382 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6383 /* Get the upper 16 bits which will be the PCI status reg */
6384 ciad >>= 16;
6385 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6386 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6387 /* Issue VFLR */
6388 ciaa = (vf << 16) | 0x80000000;
6389 ciaa |= 0xA8;
6390 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6391 ciad = 0x00008000; /* VFLR */
6392 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6393 ciaa &= 0x7FFFFFFF;
6394 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6395 }
6396 }
6397}
6398
6399#endif
7086400d
AD		 6400/**
6401 * ixgbe_service_timer - Timer Call-back
6402 * @data: pointer to adapter cast into an unsigned long
6403 **/
6404static void ixgbe_service_timer(unsigned long data)
6405{
6406 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6407 unsigned long next_event_offset;
83c61fa9 6408 bool ready = true;
7086400d 6409
6bb78cfb
AD		 6410 /* poll faster when waiting for link */
6411 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6412 next_event_offset = HZ / 10;
6413 else
6414 next_event_offset = HZ * 2;
83c61fa9 6415
6bb78cfb 6416#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6417 /*
6418 * don't bother with SR-IOV VF DMA hang check if there are
6419 * no VFs or the link is down
6420 */
6421 if (!adapter->num_vfs ||
6bb78cfb 6422 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6423 goto normal_timer_service;
83c61fa9
GR		 6424
6425 /* If we have VFs allocated then we must check for DMA hangs */
6426 ixgbe_check_for_bad_vf(adapter);
6427 next_event_offset = HZ / 50;
6428 adapter->timer_event_accumulator++;
6429
6bb78cfb 6430 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6431 adapter->timer_event_accumulator = 0;
7086400d 6432 else
6bb78cfb 6433 ready = false;
7086400d 6434
6bb78cfb 6435normal_timer_service:
83c61fa9 6436#endif
7086400d
AD		 6437 /* Reset the timer */
6438 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6439
83c61fa9
GR		 6440 if (ready)
6441 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6442}
6443
c83c6cbd
AD		 6444static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6445{
6446 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6447 return;
6448
6449 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6450
09f40aed 6451 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6452 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6453 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6454 test_bit(__IXGBE_RESETTING, &adapter->state))
6455 return;
6456
6457 ixgbe_dump(adapter);
6458 netdev_err(adapter->netdev, "Reset adapter\n");
6459 adapter->tx_timeout_count++;
6460
8f4c5c9f 6461 rtnl_lock();
c83c6cbd 6462 ixgbe_reinit_locked(adapter);
8f4c5c9f 6463 rtnl_unlock();
c83c6cbd
AD		 6464}
6465
7086400d
AD		 6466/**
6467 * ixgbe_service_task - manages and runs subtasks
6468 * @work: pointer to work_struct containing our data
6469 **/
6470static void ixgbe_service_task(struct work_struct *work)
6471{
6472 struct ixgbe_adapter *adapter = container_of(work,
6473 struct ixgbe_adapter,
6474 service_task);
b0483c8f
MR		 6475 if (ixgbe_removed(adapter->hw.hw_addr)) {
6476 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6477 rtnl_lock();
6478 ixgbe_down(adapter);
6479 rtnl_unlock();
6480 }
6481 ixgbe_service_event_complete(adapter);
6482 return;
6483 }
c83c6cbd 6484 ixgbe_reset_subtask(adapter);
7086400d
AD		 6485 ixgbe_sfp_detection_subtask(adapter);
6486 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6487 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6488 ixgbe_watchdog_subtask(adapter);
d034acf1 6489 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6490 ixgbe_check_hang_subtask(adapter);
891dc082 6491
8fecf67c 6492 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6493 ixgbe_ptp_overflow_check(adapter);
6494 ixgbe_ptp_rx_hang(adapter);
6495 }
7086400d
AD		 6496
6497 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6498}
6499
fd0db0ed
AD		 6500static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6501 struct ixgbe_tx_buffer *first,
244e27ad 6502 u8 *hdr_len)
897ab156 6503{
fd0db0ed 6504 struct sk_buff *skb = first->skb;
897ab156
AD		 6505 u32 vlan_macip_lens, type_tucmd;
6506 u32 mss_l4len_idx, l4len;
9a799d71 6507
8f4fbb9b
AD		 6508 if (skb->ip_summed != CHECKSUM_PARTIAL)
6509 return 0;
6510
897ab156
AD		 6511 if (!skb_is_gso(skb))
6512 return 0;
9a799d71 6513
897ab156 6514 if (skb_header_cloned(skb)) {
244e27ad 6515 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6516 if (err)
6517 return err;
9a799d71 6518 }
9a799d71 6519
897ab156
AD		 6520 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6521 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6522
a1108ffd 6523 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6524 struct iphdr *iph = ip_hdr(skb);
6525 iph->tot_len = 0;
6526 iph->check = 0;
6527 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6528 iph->daddr, 0,
6529 IPPROTO_TCP,
6530 0);
6531 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6532 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6533 IXGBE_TX_FLAGS_CSUM |
6534 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6535 } else if (skb_is_gso_v6(skb)) {
6536 ipv6_hdr(skb)->payload_len = 0;
6537 tcp_hdr(skb)->check =
6538 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6539 &ipv6_hdr(skb)->daddr,
6540 0, IPPROTO_TCP, 0);
244e27ad
AD		 6541 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6542 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6543 }
6544
091a6246 6545 /* compute header lengths */
897ab156
AD		 6546 l4len = tcp_hdrlen(skb);
6547 *hdr_len = skb_transport_offset(skb) + l4len;
6548
091a6246
AD		 6549 /* update gso size and bytecount with header size */
6550 first->gso_segs = skb_shinfo(skb)->gso_segs;
6551 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6552
c44f5f51 6553 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6554 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6555 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6556
6557 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6558 vlan_macip_lens = skb_network_header_len(skb);
6559 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6560 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6561
6562 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6563 mss_l4len_idx);
897ab156
AD		 6564
6565 return 1;
6566}
6567
244e27ad
AD		 6568static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6569 struct ixgbe_tx_buffer *first)
7ca647bd 6570{
fd0db0ed 6571 struct sk_buff *skb = first->skb;
897ab156
AD		 6572 u32 vlan_macip_lens = 0;
6573 u32 mss_l4len_idx = 0;
6574 u32 type_tucmd = 0;
7ca647bd 6575
897ab156 6576 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6577 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6578 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6579 return;
897ab156
AD		 6580 } else {
6581 u8 l4_hdr = 0;
244e27ad 6582 switch (first->protocol) {
a1108ffd 6583 case htons(ETH_P_IP):
897ab156
AD		 6584 vlan_macip_lens |= skb_network_header_len(skb);
6585 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6586 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6587 break;
a1108ffd 6588 case htons(ETH_P_IPV6):
897ab156
AD		 6589 vlan_macip_lens |= skb_network_header_len(skb);
6590 l4_hdr = ipv6_hdr(skb)->nexthdr;
6591 break;
6592 default:
6593 if (unlikely(net_ratelimit())) {
6594 dev_warn(tx_ring->dev,
6595 "partial checksum but proto=%x!\n",
244e27ad 6596 first->protocol);
897ab156 6597 }
7ca647bd
JP		 6598 break;
6599 }
897ab156
AD		 6600
6601 switch (l4_hdr) {
7ca647bd 6602 case IPPROTO_TCP:
897ab156
AD		 6603 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6604 mss_l4len_idx = tcp_hdrlen(skb) <<
6605 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6606 break;
6607 case IPPROTO_SCTP:
897ab156
AD		 6608 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6609 mss_l4len_idx = sizeof(struct sctphdr) <<
6610 IXGBE_ADVTXD_L4LEN_SHIFT;
6611 break;
6612 case IPPROTO_UDP:
6613 mss_l4len_idx = sizeof(struct udphdr) <<
6614 IXGBE_ADVTXD_L4LEN_SHIFT;
6615 break;
6616 default:
6617 if (unlikely(net_ratelimit())) {
6618 dev_warn(tx_ring->dev,
6619 "partial checksum but l4 proto=%x!\n",
244e27ad 6620 l4_hdr);
897ab156 6621 }
7ca647bd
JP		 6622 break;
6623 }
244e27ad
AD		 6624
6625 /* update TX checksum flag */
6626 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6627 }
6628
244e27ad 6629 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6630 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6631 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6632
897ab156
AD		 6633 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6634 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6635}
6636
472148c3
AD		 6637#define IXGBE_SET_FLAG(_input, _flag, _result) \
6638 ((_flag <= _result) ? \
6639 ((u32)(_input & _flag) * (_result / _flag)) : \
6640 ((u32)(_input & _flag) / (_flag / _result)))
6641
6642static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6643{
d3d00239 6644 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6645 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6646 IXGBE_ADVTXD_DCMD_DEXT |
6647 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6648
d3d00239 6649 /* set HW vlan bit if vlan is present */
472148c3
AD		 6650 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6651 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6652
d3d00239 6653 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6654 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6655 IXGBE_ADVTXD_DCMD_TSE);
6656
6657 /* set timestamp bit if present */
6658 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6659 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6660
62748b7b 6661 /* insert frame checksum */
472148c3 6662 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6663
d3d00239
AD		 6664 return cmd_type;
6665}
9a799d71 6666
729739b7
AD		 6667static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6668 u32 tx_flags, unsigned int paylen)
d3d00239 6669{
472148c3 6670 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6671
d3d00239 6672 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6673 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6674 IXGBE_TX_FLAGS_CSUM,
6675 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6676
93f5b3c1 6677 /* enble IPv4 checksum for TSO */
472148c3
AD		 6678 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6679 IXGBE_TX_FLAGS_IPV4,
6680 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6681
7f9643fd
AD		 6682 /*
6683 * Check Context must be set if Tx switch is enabled, which it
6684 * always is for case where virtual functions are running
6685 */
472148c3
AD		 6686 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6687 IXGBE_TX_FLAGS_CC,
6688 IXGBE_ADVTXD_CC);
7f9643fd 6689
472148c3 6690 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6691}
44df32c5 6692
d3d00239
AD		 6693#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6694 IXGBE_TXD_CMD_RS)
6695
6696static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6697 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6698 const u8 hdr_len)
6699{
fd0db0ed 6700 struct sk_buff *skb = first->skb;
729739b7 6701 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6702 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6703 struct skb_frag_struct *frag;
6704 dma_addr_t dma;
6705 unsigned int data_len, size;
244e27ad 6706 u32 tx_flags = first->tx_flags;
472148c3 6707 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6708 u16 i = tx_ring->next_to_use;
d3d00239 6709
729739b7
AD		 6710 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6711
ec718254
AD		 6712 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6713
6714 size = skb_headlen(skb);
6715 data_len = skb->data_len;
729739b7 6716
d3d00239
AD		 6717#ifdef IXGBE_FCOE
6718 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6719 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6720 size -= sizeof(struct fcoe_crc_eof) - data_len;
6721 data_len = 0;
729739b7
AD		 6722 } else {
6723 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6724 }
6725 }
44df32c5 6726
d3d00239 6727#endif
729739b7 6728 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6729
ec718254 6730 tx_buffer = first;
9a799d71 6731
ec718254
AD		 6732 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6733 if (dma_mapping_error(tx_ring->dev, dma))
6734 goto dma_error;
6735
6736 /* record length, and DMA address */
6737 dma_unmap_len_set(tx_buffer, len, size);
6738 dma_unmap_addr_set(tx_buffer, dma, dma);
6739
6740 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6741
729739b7 6742 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6743 tx_desc->read.cmd_type_len =
472148c3 6744 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6745
d3d00239 6746 i++;
729739b7 6747 tx_desc++;
d3d00239 6748 if (i == tx_ring->count) {
e4f74028 6749 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6750 i = 0;
6751 }
ec718254 6752 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6753
6754 dma += IXGBE_MAX_DATA_PER_TXD;
6755 size -= IXGBE_MAX_DATA_PER_TXD;
6756
6757 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6758 }
e5a43549 6759
729739b7
AD		 6760 if (likely(!data_len))
6761 break;
9a799d71 6762
472148c3 6763 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6764
729739b7
AD		 6765 i++;
6766 tx_desc++;
6767 if (i == tx_ring->count) {
6768 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6769 i = 0;
6770 }
ec718254 6771 tx_desc->read.olinfo_status = 0;
9a799d71 6772
d3d00239 6773#ifdef IXGBE_FCOE
9e903e08 6774 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6775#else
9e903e08 6776 size = skb_frag_size(frag);
d3d00239
AD		 6777#endif
6778 data_len -= size;
9a799d71 6779
729739b7
AD		 6780 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6781 DMA_TO_DEVICE);
9a799d71 6782
729739b7 6783 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6784 }
9a799d71 6785
729739b7 6786 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6787 cmd_type |= size | IXGBE_TXD_CMD;
6788 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6789
091a6246 6790 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6791
d3d00239
AD		 6792 /* set the timestamp */
6793 first->time_stamp = jiffies;
9a799d71
AK		 6794
6795 /*
729739b7
AD		 6796 * Force memory writes to complete before letting h/w know there
6797 * are new descriptors to fetch. (Only applicable for weak-ordered
6798 * memory model archs, such as IA-64).
6799 *
6800 * We also need this memory barrier to make certain all of the
6801 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6802 */
6803 wmb();
6804
d3d00239
AD		 6805 /* set next_to_watch value indicating a packet is present */
6806 first->next_to_watch = tx_desc;
6807
729739b7
AD		 6808 i++;
6809 if (i == tx_ring->count)
6810 i = 0;
6811
6812 tx_ring->next_to_use = i;
6813
d3d00239 6814 /* notify HW of packet */
84227bcd 6815 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6816
6817 return;
6818dma_error:
729739b7 6819 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6820
6821 /* clear dma mappings for failed tx_buffer_info map */
6822 for (;;) {
729739b7
AD		 6823 tx_buffer = &tx_ring->tx_buffer_info[i];
6824 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6825 if (tx_buffer == first)
d3d00239
AD		 6826 break;
6827 if (i == 0)
6828 i = tx_ring->count;
6829 i--;
6830 }
6831
d3d00239 6832 tx_ring->next_to_use = i;
9a799d71
AK		 6833}
6834
fd0db0ed 6835static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6836 struct ixgbe_tx_buffer *first)
69830529
AD		 6837{
6838 struct ixgbe_q_vector *q_vector = ring->q_vector;
6839 union ixgbe_atr_hash_dword input = { .dword = 0 };
6840 union ixgbe_atr_hash_dword common = { .dword = 0 };
6841 union {
6842 unsigned char *network;
6843 struct iphdr *ipv4;
6844 struct ipv6hdr *ipv6;
6845 } hdr;
ee9e0f0b 6846 struct tcphdr *th;
905e4a41 6847 __be16 vlan_id;
c4cf55e5 6848
69830529
AD		 6849 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6850 if (!q_vector)
6851 return;
6852
6853 /* do nothing if sampling is disabled */
6854 if (!ring->atr_sample_rate)
d3ead241 6855 return;
c4cf55e5 6856
69830529 6857 ring->atr_count++;
c4cf55e5 6858
69830529 6859 /* snag network header to get L4 type and address */
fd0db0ed 6860 hdr.network = skb_network_header(first->skb);
69830529
AD		 6861
6862 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 6863 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 6864 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 6865 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 6866 hdr.ipv4->protocol != IPPROTO_TCP))
6867 return;
ee9e0f0b 6868
fd0db0ed 6869 th = tcp_hdr(first->skb);
c4cf55e5 6870
66f32a8b
AD		 6871 /* skip this packet since it is invalid or the socket is closing */
6872 if (!th || th->fin)
69830529
AD		 6873 return;
6874
6875 /* sample on all syn packets or once every atr sample count */
6876 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6877 return;
6878
6879 /* reset sample count */
6880 ring->atr_count = 0;
6881
244e27ad 6882 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6883
6884 /*
6885 * src and dst are inverted, think how the receiver sees them
6886 *
6887 * The input is broken into two sections, a non-compressed section
6888 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6889 * is XORed together and stored in the compressed dword.
6890 */
6891 input.formatted.vlan_id = vlan_id;
6892
6893 /*
6894 * since src port and flex bytes occupy the same word XOR them together
6895 * and write the value to source port portion of compressed dword
6896 */
244e27ad 6897 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 6898 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 6899 else
244e27ad 6900 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6901 common.port.dst ^= th->source;
6902
a1108ffd 6903 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 6904 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6905 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6906 } else {
6907 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6908 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6909 hdr.ipv6->saddr.s6_addr32[1] ^
6910 hdr.ipv6->saddr.s6_addr32[2] ^
6911 hdr.ipv6->saddr.s6_addr32[3] ^
6912 hdr.ipv6->daddr.s6_addr32[0] ^
6913 hdr.ipv6->daddr.s6_addr32[1] ^
6914 hdr.ipv6->daddr.s6_addr32[2] ^
6915 hdr.ipv6->daddr.s6_addr32[3];
6916 }
c4cf55e5
PWJ		 6917
6918 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6919 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6920 input, common, ring->queue_index);
c4cf55e5
PWJ		 6921}
6922
63544e9c 6923static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6924{
fc77dc3c 6925 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6926 /* Herbert's original patch had:
6927 * smp_mb__after_netif_stop_queue();
6928 * but since that doesn't exist yet, just open code it. */
6929 smp_mb();
6930
6931 /* We need to check again in a case another CPU has just
6932 * made room available. */
7d4987de 6933 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6934 return -EBUSY;
6935
6936 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6937 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6938 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6939 return 0;
6940}
6941
82d4e46e 6942static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6943{
7d4987de 6944 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6945 return 0;
fc77dc3c 6946 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6947}
6948
f663dd9a 6949static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 6950 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 6951{
f663dd9a
JW		 6952 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6953#ifdef IXGBE_FCOE
97488bd1
AD		 6954 struct ixgbe_adapter *adapter;
6955 struct ixgbe_ring_feature *f;
6956 int txq;
f663dd9a
JW		 6957#endif
6958
6959 if (fwd_adapter)
6960 return skb->queue_mapping + fwd_adapter->tx_base_queue;
6961
6962#ifdef IXGBE_FCOE
5e09a105 6963
97488bd1
AD		 6964 /*
6965 * only execute the code below if protocol is FCoE
6966 * or FIP and we have FCoE enabled on the adapter
6967 */
6968 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 6969 case htons(ETH_P_FCOE):
6970 case htons(ETH_P_FIP):
97488bd1 6971 adapter = netdev_priv(dev);
c087663e 6972
97488bd1
AD		 6973 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6974 break;
6975 default:
99932d4f 6976 return fallback(dev, skb);
97488bd1 6977 }
c087663e 6978
97488bd1 6979 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6980
97488bd1
AD		 6981 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6982 smp_processor_id();
56075a98 6983
97488bd1
AD		 6984 while (txq >= f->indices)
6985 txq -= f->indices;
c4cf55e5 6986
97488bd1 6987 return txq + f->offset;
f663dd9a 6988#else
99932d4f 6989 return fallback(dev, skb);
f663dd9a 6990#endif
09a3b1f8
SH		 6991}
6992
fc77dc3c 6993netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6994 struct ixgbe_adapter *adapter,
6995 struct ixgbe_ring *tx_ring)
9a799d71 6996{
d3d00239 6997 struct ixgbe_tx_buffer *first;
5f715823 6998 int tso;
d3d00239 6999 u32 tx_flags = 0;
a535c30e 7000 unsigned short f;
a535c30e 7001 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7002 __be16 protocol = skb->protocol;
63544e9c 7003 u8 hdr_len = 0;
5e09a105 7004
a535c30e
AD		 7005 /*
7006 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7007 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7008 * + 2 desc gap to keep tail from touching head,
7009 * + 1 desc for context descriptor,
7010 * otherwise try next time
7011 */
a535c30e
AD		 7012 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7013 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7014
a535c30e
AD		 7015 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7016 tx_ring->tx_stats.tx_busy++;
7017 return NETDEV_TX_BUSY;
7018 }
7019
fd0db0ed
AD		 7020 /* record the location of the first descriptor for this packet */
7021 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7022 first->skb = skb;
091a6246
AD		 7023 first->bytecount = skb->len;
7024 first->gso_segs = 1;
fd0db0ed 7025
66f32a8b 7026 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7027 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7028 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7029 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7030 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7031 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7032 struct vlan_hdr *vhdr, _vhdr;
7033 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7034 if (!vhdr)
7035 goto out_drop;
7036
7037 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7038 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7039 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7040 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7041 }
7042
aa7bd467
JK		 7043 skb_tx_timestamp(skb);
7044
3a6a4eda
JK		 7045 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
7046 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7047 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7048
7049 /* schedule check for Tx timestamp */
7050 adapter->ptp_tx_skb = skb_get(skb);
7051 adapter->ptp_tx_start = jiffies;
7052 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7053 }
3a6a4eda 7054
9e0c5648
AD		 7055#ifdef CONFIG_PCI_IOV
7056 /*
7057 * Use the l2switch_enable flag - would be false if the DMA
7058 * Tx switch had been disabled.
7059 */
7060 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7061 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7062
7063#endif
32701dc2 7064 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7065 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7066 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7067 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7068 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7069 tx_flags |= (skb->priority & 0x7) <<
7070 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7071 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7072 struct vlan_ethhdr *vhdr;
7073 if (skb_header_cloned(skb) &&
7074 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7075 goto out_drop;
7076 vhdr = (struct vlan_ethhdr *)skb->data;
7077 vhdr->h_vlan_TCI = htons(tx_flags >>
7078 IXGBE_TX_FLAGS_VLAN_SHIFT);
7079 } else {
7080 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7081 }
9a799d71 7082 }
eacd73f7 7083
244e27ad
AD		 7084 /* record initial flags and protocol */
7085 first->tx_flags = tx_flags;
7086 first->protocol = protocol;
7087
eacd73f7 7088#ifdef IXGBE_FCOE
66f32a8b 7089 /* setup tx offload for FCoE */
a1108ffd 7090 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7091 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7092 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7093 if (tso < 0)
7094 goto out_drop;
9a799d71 7095
66f32a8b 7096 goto xmit_fcoe;
eacd73f7 7097 }
9a799d71 7098
66f32a8b 7099#endif /* IXGBE_FCOE */
244e27ad 7100 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7101 if (tso < 0)
897ab156 7102 goto out_drop;
244e27ad
AD		 7103 else if (!tso)
7104 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7105
7106 /* add the ATR filter if ATR is on */
7107 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7108 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7109
7110#ifdef IXGBE_FCOE
7111xmit_fcoe:
7112#endif /* IXGBE_FCOE */
244e27ad 7113 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7114
7115 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7116
7117 return NETDEV_TX_OK;
897ab156
AD		 7118
7119out_drop:
fd0db0ed
AD		 7120 dev_kfree_skb_any(first->skb);
7121 first->skb = NULL;
7122
897ab156 7123 return NETDEV_TX_OK;
9a799d71
AK		 7124}
7125
2a47fa45
JF		 7126static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7127 struct net_device *netdev,
7128 struct ixgbe_ring *ring)
84418e3b
AD		 7129{
7130 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7131 struct ixgbe_ring *tx_ring;
7132
a50c29dd
AD		 7133 /*
7134 * The minimum packet size for olinfo paylen is 17 so pad the skb
7135 * in order to meet this minimum size requirement.
7136 */
f73332fc
SH		 7137 if (unlikely(skb->len < 17)) {
7138 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7139 return NETDEV_TX_OK;
7140 skb->len = 17;
71a49f77 7141 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7142 }
7143
2a47fa45
JF		 7144 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7145
fc77dc3c 7146 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7147}
7148
2a47fa45
JF		 7149static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7150 struct net_device *netdev)
7151{
7152 return __ixgbe_xmit_frame(skb, netdev, NULL);
7153}
7154
9a799d71
AK		 7155/**
7156 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7157 * @netdev: network interface device structure
7158 * @p: pointer to an address structure
7159 *
7160 * Returns 0 on success, negative on failure
7161 **/
7162static int ixgbe_set_mac(struct net_device *netdev, void *p)
7163{
7164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7165 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7166 struct sockaddr *addr = p;
7167
7168 if (!is_valid_ether_addr(addr->sa_data))
7169 return -EADDRNOTAVAIL;
7170
7171 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7172 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7173
1d9c0bfd 7174 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7175
7176 return 0;
7177}
7178
6b73e10d
BH		 7179static int
7180ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7181{
7182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7183 struct ixgbe_hw *hw = &adapter->hw;
7184 u16 value;
7185 int rc;
7186
7187 if (prtad != hw->phy.mdio.prtad)
7188 return -EINVAL;
7189 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7190 if (!rc)
7191 rc = value;
7192 return rc;
7193}
7194
7195static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7196 u16 addr, u16 value)
7197{
7198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7199 struct ixgbe_hw *hw = &adapter->hw;
7200
7201 if (prtad != hw->phy.mdio.prtad)
7202 return -EINVAL;
7203 return hw->phy.ops.write_reg(hw, addr, devad, value);
7204}
7205
7206static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7207{
7208 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7209
3a6a4eda 7210 switch (cmd) {
3a6a4eda 7211 case SIOCSHWTSTAMP:
93501d48
JK		 7212 return ixgbe_ptp_set_ts_config(adapter, req);
7213 case SIOCGHWTSTAMP:
7214 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7215 default:
7216 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7217 }
6b73e10d
BH		 7218}
7219
0365e6e4
PW		 7220/**
7221 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7222 * netdev->dev_addrs
0365e6e4
PW		 7223 * @netdev: network interface device structure
7224 *
7225 * Returns non-zero on failure
7226 **/
7227static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7228{
7229 int err = 0;
7230 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7231 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7232
7fa7c9dc 7233 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7234 rtnl_lock();
7fa7c9dc 7235 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7236 rtnl_unlock();
7fa7c9dc
AD		 7237
7238 /* update SAN MAC vmdq pool selection */
7239 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7240 }
7241 return err;
7242}
7243
7244/**
7245 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7246 * netdev->dev_addrs
0365e6e4
PW		 7247 * @netdev: network interface device structure
7248 *
7249 * Returns non-zero on failure
7250 **/
7251static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7252{
7253 int err = 0;
7254 struct ixgbe_adapter *adapter = netdev_priv(dev);
7255 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7256
7257 if (is_valid_ether_addr(mac->san_addr)) {
7258 rtnl_lock();
7259 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7260 rtnl_unlock();
7261 }
7262 return err;
7263}
7264
9a799d71
AK		 7265#ifdef CONFIG_NET_POLL_CONTROLLER
7266/*
7267 * Polling 'interrupt' - used by things like netconsole to send skbs
7268 * without having to re-enable interrupts. It's not called while
7269 * the interrupt routine is executing.
7270 */
7271static void ixgbe_netpoll(struct net_device *netdev)
7272{
7273 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7274 int i;
9a799d71 7275
1a647bd2
AD		 7276 /* if interface is down do nothing */
7277 if (test_bit(__IXGBE_DOWN, &adapter->state))
7278 return;
7279
9a799d71 7280 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7281 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7282 for (i = 0; i < adapter->num_q_vectors; i++)
7283 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7284 } else {
7285 ixgbe_intr(adapter->pdev->irq, netdev);
7286 }
9a799d71 7287 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7288}
9a799d71 7289
581330ba 7290#endif
de1036b1
ED		 7291static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7292 struct rtnl_link_stats64 *stats)
7293{
7294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7295 int i;
7296
1a51502b 7297 rcu_read_lock();
de1036b1 7298 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7299 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7300 u64 bytes, packets;
7301 unsigned int start;
7302
1a51502b
ED		 7303 if (ring) {
7304 do {
57a7744e 7305 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7306 packets = ring->stats.packets;
7307 bytes = ring->stats.bytes;
57a7744e 7308 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7309 stats->rx_packets += packets;
7310 stats->rx_bytes += bytes;
7311 }
de1036b1 7312 }
1ac9ad13
ED		 7313
7314 for (i = 0; i < adapter->num_tx_queues; i++) {
7315 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7316 u64 bytes, packets;
7317 unsigned int start;
7318
7319 if (ring) {
7320 do {
57a7744e 7321 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7322 packets = ring->stats.packets;
7323 bytes = ring->stats.bytes;
57a7744e 7324 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7325 stats->tx_packets += packets;
7326 stats->tx_bytes += bytes;
7327 }
7328 }
1a51502b 7329 rcu_read_unlock();
de1036b1
ED		 7330 /* following stats updated by ixgbe_watchdog_task() */
7331 stats->multicast = netdev->stats.multicast;
7332 stats->rx_errors = netdev->stats.rx_errors;
7333 stats->rx_length_errors = netdev->stats.rx_length_errors;
7334 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7335 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7336 return stats;
7337}
7338
8af3c33f 7339#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7340/**
7341 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7342 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7343 * @tc: number of traffic classes currently enabled
7344 *
7345 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7346 * 802.1Q priority maps to a packet buffer that exists.
7347 */
7348static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7349{
7350 struct ixgbe_hw *hw = &adapter->hw;
7351 u32 reg, rsave;
7352 int i;
7353
7354 /* 82598 have a static priority to TC mapping that can not
7355 * be changed so no validation is needed.
7356 */
7357 if (hw->mac.type == ixgbe_mac_82598EB)
7358 return;
7359
7360 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7361 rsave = reg;
7362
7363 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7364 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7365
7366 /* If up2tc is out of bounds default to zero */
7367 if (up2tc > tc)
7368 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7369 }
7370
7371 if (reg != rsave)
7372 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7373
7374 return;
7375}
7376
02debdc9
AD		 7377/**
7378 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7379 * @adapter: Pointer to adapter struct
7380 *
7381 * Populate the netdev user priority to tc map
7382 */
7383static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7384{
7385 struct net_device *dev = adapter->netdev;
7386 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7387 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7388 u8 prio;
7389
7390 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7391 u8 tc = 0;
7392
7393 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7394 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7395 else if (ets)
7396 tc = ets->prio_tc[prio];
7397
7398 netdev_set_prio_tc_map(dev, prio, tc);
7399 }
7400}
7401
cca73c59 7402#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7403/**
7404 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7405 *
7406 * @netdev: net device to configure
7407 * @tc: number of traffic classes to enable
7408 */
7409int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7410{
8b1c0b24
JF		 7411 struct ixgbe_adapter *adapter = netdev_priv(dev);
7412 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7413 bool pools;
8b1c0b24 7414
8b1c0b24 7415 /* Hardware supports up to 8 traffic classes */
4de2a022 7416 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7417 (hw->mac.type == ixgbe_mac_82598EB &&
7418 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7419 return -EINVAL;
7420
2a47fa45
JF		 7421 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7422 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7423 return -EBUSY;
7424
8b1c0b24 7425 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7426 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7427 * hardware is not flexible enough to do this dynamically.
7428 */
7429 if (netif_running(dev))
7430 ixgbe_close(dev);
7431 ixgbe_clear_interrupt_scheme(adapter);
7432
cca73c59 7433#ifdef CONFIG_IXGBE_DCB
e7589eab 7434 if (tc) {
8b1c0b24 7435 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7436 ixgbe_set_prio_tc_map(adapter);
7437
e7589eab 7438 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7439
943561d3
AD		 7440 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7441 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7442 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7443 }
e7589eab 7444 } else {
8b1c0b24 7445 netdev_reset_tc(dev);
02debdc9 7446
943561d3
AD		 7447 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7448 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7449
7450 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7451
7452 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7453 adapter->dcb_cfg.pfc_mode_enable = false;
7454 }
7455
8b1c0b24 7456 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7457
7458#endif /* CONFIG_IXGBE_DCB */
7459 ixgbe_init_interrupt_scheme(adapter);
7460
8b1c0b24 7461 if (netif_running(dev))
cca73c59 7462 return ixgbe_open(dev);
8b1c0b24
JF		 7463
7464 return 0;
7465}
de1036b1 7466
da36b647
GR		 7467#ifdef CONFIG_PCI_IOV
7468void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7469{
7470 struct net_device *netdev = adapter->netdev;
7471
7472 rtnl_lock();
da36b647 7473 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7474 rtnl_unlock();
7475}
7476
7477#endif
082757af
DS		 7478void ixgbe_do_reset(struct net_device *netdev)
7479{
7480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7481
7482 if (netif_running(netdev))
7483 ixgbe_reinit_locked(adapter);
7484 else
7485 ixgbe_reset(adapter);
7486}
7487
c8f44aff 7488static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7489 netdev_features_t features)
082757af
DS		 7490{
7491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7492
082757af 7493 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7494 if (!(features & NETIF_F_RXCSUM))
7495 features &= ~NETIF_F_LRO;
082757af 7496
567d2de2
AD		 7497 /* Turn off LRO if not RSC capable */
7498 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7499 features &= ~NETIF_F_LRO;
8e2813f5 7500
567d2de2 7501 return features;
082757af
DS		 7502}
7503
c8f44aff 7504static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7505 netdev_features_t features)
082757af
DS		 7506{
7507 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7508 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7509 bool need_reset = false;
7510
082757af 7511 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7512 if (!(features & NETIF_F_LRO)) {
7513 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7514 need_reset = true;
567d2de2
AD		 7515 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7516 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7517 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7518 if (adapter->rx_itr_setting == 1 ||
7519 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7520 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7521 need_reset = true;
7522 } else if ((changed ^ features) & NETIF_F_LRO) {
7523 e_info(probe, "rx-usecs set too low, "
7524 "disabling RSC\n");
082757af
DS		 7525 }
7526 }
7527
7528 /*
7529 * Check if Flow Director n-tuple support was enabled or disabled. If
7530 * the state changed, we need to reset.
7531 */
39cb681b
AD		 7532 switch (features & NETIF_F_NTUPLE) {
7533 case NETIF_F_NTUPLE:
567d2de2 7534 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7535 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7536 need_reset = true;
7537
567d2de2
AD		 7538 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7539 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7540 break;
7541 default:
7542 /* turn off perfect filters, enable ATR and reset */
7543 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7544 need_reset = true;
7545
7546 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7547
7548 /* We cannot enable ATR if SR-IOV is enabled */
7549 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7550 break;
7551
7552 /* We cannot enable ATR if we have 2 or more traffic classes */
7553 if (netdev_get_num_tc(netdev) > 1)
7554 break;
7555
7556 /* We cannot enable ATR if RSS is disabled */
7557 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7558 break;
7559
7560 /* A sample rate of 0 indicates ATR disabled */
7561 if (!adapter->atr_sample_rate)
7562 break;
7563
7564 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7565 break;
082757af
DS		 7566 }
7567
f646968f 7568 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7569 ixgbe_vlan_strip_enable(adapter);
7570 else
7571 ixgbe_vlan_strip_disable(adapter);
7572
3f2d1c0f
BG		 7573 if (changed & NETIF_F_RXALL)
7574 need_reset = true;
7575
567d2de2 7576 netdev->features = features;
082757af
DS		 7577 if (need_reset)
7578 ixgbe_do_reset(netdev);
7579
7580 return 0;
082757af
DS		 7581}
7582
edc7d573 7583static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7584 struct net_device *dev,
6b6e2725 7585 const unsigned char *addr,
0f4b0add
JF		 7586 u16 flags)
7587{
7588 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7589 int err;
7590
7591 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7592 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7593
b1ac1ef7
JF		 7594 /* Hardware does not support aging addresses so if a
7595 * ndm_state is given only allow permanent addresses
7596 */
7597 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7598 pr_info("%s: FDB only supports static addresses\n",
7599 ixgbe_driver_name);
7600 return -EINVAL;
7601 }
7602
46acc460 7603 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7604 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7605
7606 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7607 err = dev_uc_add_excl(dev, addr);
0f4b0add 7608 else
95447461
JF		 7609 err = -ENOMEM;
7610 } else if (is_multicast_ether_addr(addr)) {
7611 err = dev_mc_add_excl(dev, addr);
7612 } else {
7613 err = -EINVAL;
0f4b0add
JF		 7614 }
7615
7616 /* Only return duplicate errors if NLM_F_EXCL is set */
7617 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7618 err = 0;
7619
7620 return err;
7621}
7622
815cccbf
JF		 7623static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7624 struct nlmsghdr *nlh)
7625{
7626 struct ixgbe_adapter *adapter = netdev_priv(dev);
7627 struct nlattr *attr, *br_spec;
7628 int rem;
7629
7630 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7631 return -EOPNOTSUPP;
7632
7633 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7634
7635 nla_for_each_nested(attr, br_spec, rem) {
7636 __u16 mode;
7637 u32 reg = 0;
7638
7639 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7640 continue;
7641
7642 mode = nla_get_u16(attr);
9b735984 7643 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7644 reg = 0;
9b735984
GR		 7645 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7646 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7647 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7648 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7649 } else
815cccbf
JF		 7650 return -EINVAL;
7651
7652 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7653
7654 e_info(drv, "enabling bridge mode: %s\n",
7655 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7656 }
7657
7658 return 0;
7659}
7660
7661static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7662 struct net_device *dev,
7663 u32 filter_mask)
815cccbf
JF		 7664{
7665 struct ixgbe_adapter *adapter = netdev_priv(dev);
7666 u16 mode;
7667
7668 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7669 return 0;
7670
9b735984 7671 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7672 mode = BRIDGE_MODE_VEB;
7673 else
7674 mode = BRIDGE_MODE_VEPA;
7675
7676 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7677}
7678
2a47fa45
JF		 7679static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7680{
7681 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7682 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7683 unsigned int limit;
2a47fa45
JF		 7684 int pool, err;
7685
219354d4
JF		 7686#ifdef CONFIG_RPS
7687 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7688 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7689 vdev->name);
7690 return ERR_PTR(-EINVAL);
7691 }
7692#endif
2a47fa45 7693 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7694 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7695 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7696 netdev_info(pdev,
7697 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7698 pdev->name);
7699 return ERR_PTR(-EINVAL);
7700 }
7701
7702 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7703 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7704 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7705 return ERR_PTR(-EBUSY);
7706
7707 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7708 if (!fwd_adapter)
7709 return ERR_PTR(-ENOMEM);
7710
7711 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7712 adapter->num_rx_pools++;
7713 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7714 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7715
7716 /* Enable VMDq flag so device will be set in VM mode */
7717 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7718 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7719 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7720
7721 /* Force reinit of ring allocation with VMDQ enabled */
7722 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7723 if (err)
7724 goto fwd_add_err;
7725 fwd_adapter->pool = pool;
7726 fwd_adapter->real_adapter = adapter;
7727 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7728 if (err)
7729 goto fwd_add_err;
7730 netif_tx_start_all_queues(vdev);
7731 return fwd_adapter;
7732fwd_add_err:
7733 /* unwind counter and free adapter struct */
7734 netdev_info(pdev,
7735 "%s: dfwd hardware acceleration failed\n", vdev->name);
7736 clear_bit(pool, &adapter->fwd_bitmask);
7737 adapter->num_rx_pools--;
7738 kfree(fwd_adapter);
7739 return ERR_PTR(err);
7740}
7741
7742static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7743{
7744 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7745 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7746 unsigned int limit;
2a47fa45
JF		 7747
7748 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7749 adapter->num_rx_pools--;
7750
51f3773b
JF		 7751 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7752 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7753 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7754 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7755 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7756 fwd_adapter->pool, adapter->num_rx_pools,
7757 fwd_adapter->rx_base_queue,
7758 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7759 adapter->fwd_bitmask);
7760 kfree(fwd_adapter);
7761}
7762
0edc3527 7763static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7764 .ndo_open = ixgbe_open,
0edc3527 7765 .ndo_stop = ixgbe_close,
00829823 7766 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7767 .ndo_select_queue = ixgbe_select_queue,
581330ba 7768 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7769 .ndo_validate_addr = eth_validate_addr,
7770 .ndo_set_mac_address = ixgbe_set_mac,
7771 .ndo_change_mtu = ixgbe_change_mtu,
7772 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7773 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7774 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7775 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7776 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7777 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7778 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7779 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7780 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7781 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7782#ifdef CONFIG_IXGBE_DCB
24095aa3 7783 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7784#endif
0edc3527
SH		 7785#ifdef CONFIG_NET_POLL_CONTROLLER
7786 .ndo_poll_controller = ixgbe_netpoll,
7787#endif
e0d1095a 7788#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7789 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7790#endif
332d4a7d
YZ		 7791#ifdef IXGBE_FCOE
7792 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7793 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7794 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7795 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7796 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7797 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7798 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7799#endif /* IXGBE_FCOE */
082757af
DS		 7800 .ndo_set_features = ixgbe_set_features,
7801 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7802 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7803 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7804 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7805 .ndo_dfwd_add_station = ixgbe_fwd_add,
7806 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7807};
7808
e027d1ae
JK		 7809/**
7810 * ixgbe_enumerate_functions - Get the number of ports this device has
7811 * @adapter: adapter structure
7812 *
7813 * This function enumerates the phsyical functions co-located on a single slot,
7814 * in order to determine how many ports a device has. This is most useful in
7815 * determining the required GT/s of PCIe bandwidth necessary for optimal
7816 * performance.
7817 **/
7818static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7819{
e027d1ae
JK		 7820 struct list_head *entry;
7821 int physfns = 0;
7822
f1f96579
JK		 7823 /* Some cards can not use the generic count PCIe functions method,
7824 * because they are behind a parent switch, so we hardcode these with
7825 * the correct number of functions.
e027d1ae 7826 */
f1f96579 7827 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7828 physfns = 4;
f1f96579 7829 } else {
e027d1ae
JK		 7830 list_for_each(entry, &adapter->pdev->bus_list) {
7831 struct pci_dev *pdev =
7832 list_entry(entry, struct pci_dev, bus_list);
7833 /* don't count virtual functions */
7834 if (!pdev->is_virtfn)
7835 physfns++;
7836 }
7837 }
7838
7839 return physfns;
7840}
7841
8e2813f5
JK		 7842/**
7843 * ixgbe_wol_supported - Check whether device supports WoL
7844 * @hw: hw specific details
7845 * @device_id: the device ID
7846 * @subdev_id: the subsystem device ID
7847 *
7848 * This function is used by probe and ethtool to determine
7849 * which devices have WoL support
7850 *
7851 **/
7852int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7853 u16 subdevice_id)
7854{
7855 struct ixgbe_hw *hw = &adapter->hw;
7856 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7857 int is_wol_supported = 0;
7858
7859 switch (device_id) {
7860 case IXGBE_DEV_ID_82599_SFP:
7861 /* Only these subdevices could supports WOL */
7862 switch (subdevice_id) {
87557440 7863 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7864 case IXGBE_SUBDEV_ID_82599_560FLR:
7865 /* only support first port */
7866 if (hw->bus.func != 0)
7867 break;
5700ff26 7868 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7869 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7870 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7871 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7872 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7873 is_wol_supported = 1;
7874 break;
7875 }
7876 break;
5daebbb0
DS		 7877 case IXGBE_DEV_ID_82599EN_SFP:
7878 /* Only this subdevice supports WOL */
7879 switch (subdevice_id) {
7880 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7881 is_wol_supported = 1;
7882 break;
7883 }
7884 break;
8e2813f5
JK		 7885 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7886 /* All except this subdevice support WOL */
7887 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7888 is_wol_supported = 1;
7889 break;
7890 case IXGBE_DEV_ID_82599_KX4:
7891 is_wol_supported = 1;
7892 break;
7893 case IXGBE_DEV_ID_X540T:
df376f0d 7894 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7895 /* check eeprom to see if enabled wol */
7896 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7897 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7898 (hw->bus.func == 0))) {
7899 is_wol_supported = 1;
7900 }
7901 break;
7902 }
7903
7904 return is_wol_supported;
7905}
7906
9a799d71
AK		 7907/**
7908 * ixgbe_probe - Device Initialization Routine
7909 * @pdev: PCI device information struct
7910 * @ent: entry in ixgbe_pci_tbl
7911 *
7912 * Returns 0 on success, negative on failure
7913 *
7914 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7915 * The OS initialization, configuring of the adapter private structure,
7916 * and a hardware reset occur.
7917 **/
1dd06ae8 7918static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7919{
7920 struct net_device *netdev;
7921 struct ixgbe_adapter *adapter = NULL;
7922 struct ixgbe_hw *hw;
7923 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7924 static int cards_found;
e027d1ae 7925 int i, err, pci_using_dac, expected_gts;
d3cb9869 7926 unsigned int indices = MAX_TX_QUEUES;
289700db 7927 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7928#ifdef IXGBE_FCOE
7929 u16 device_caps;
7930#endif
289700db 7931 u32 eec;
9a799d71 7932
bded64a7
AG		 7933 /* Catch broken hardware that put the wrong VF device ID in
7934 * the PCIe SR-IOV capability.
7935 */
7936 if (pdev->is_virtfn) {
7937 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7938 pci_name(pdev), pdev->vendor, pdev->device);
7939 return -EINVAL;
7940 }
7941
9ce77666 7942 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7943 if (err)
7944 return err;
7945
f5f2eda8 7946 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7947 pci_using_dac = 1;
7948 } else {
f5f2eda8 7949 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7950 if (err) {
f5f2eda8
RK		 7951 dev_err(&pdev->dev,
7952 "No usable DMA configuration, aborting\n");
7953 goto err_dma;
9a799d71
AK		 7954 }
7955 pci_using_dac = 0;
7956 }
7957
9ce77666 7958 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7959 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7960 if (err) {
b8bc0421
DC		 7961 dev_err(&pdev->dev,
7962 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7963 goto err_pci_reg;
7964 }
7965
19d5afd4 7966 pci_enable_pcie_error_reporting(pdev);
6fabd715 7967
9a799d71 7968 pci_set_master(pdev);
fb3b27bc 7969 pci_save_state(pdev);
9a799d71 7970
d3cb9869 7971 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7972#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7973 /* 8 TC w/ 4 queues per TC */
7974 indices = 4 * MAX_TRAFFIC_CLASS;
7975#else
7976 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7977#endif
d3cb9869 7978 }
e901acd6 7979
c85a2618 7980 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7981 if (!netdev) {
7982 err = -ENOMEM;
7983 goto err_alloc_etherdev;
7984 }
7985
9a799d71
AK		 7986 SET_NETDEV_DEV(netdev, &pdev->dev);
7987
9a799d71 7988 adapter = netdev_priv(netdev);
c60fbb00 7989 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7990
7991 adapter->netdev = netdev;
7992 adapter->pdev = pdev;
7993 hw = &adapter->hw;
7994 hw->back = adapter;
b3f4d599 7995 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7996
05857980 7997 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7998 pci_resource_len(pdev, 0));
2a1a091c 7999 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8000 if (!hw->hw_addr) {
8001 err = -EIO;
8002 goto err_ioremap;
8003 }
8004
0edc3527 8005 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8006 ixgbe_set_ethtool_ops(netdev);
9a799d71 8007 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 8008 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 8009
9a799d71
AK		 8010 adapter->bd_number = cards_found;
8011
9a799d71
AK		 8012 /* Setup hw api */
8013 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8014 hw->mac.type = ii->mac;
9a799d71 8015
c44ade9e
JB		 8016 /* EEPROM */
8017 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8018 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8019 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8020 if (!(eec & (1 << 8)))
8021 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8022
8023 /* PHY */
8024 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8025 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8026 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8027 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8028 hw->phy.mdio.mmds = 0;
8029 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8030 hw->phy.mdio.dev = netdev;
8031 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8032 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8033
8ca783ab 8034 ii->get_invariants(hw);
9a799d71
AK		 8035
8036 /* setup the private structure */
8037 err = ixgbe_sw_init(adapter);
8038 if (err)
8039 goto err_sw_init;
8040
e86bff0e 8041 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8042 switch (adapter->hw.mac.type) {
8043 case ixgbe_mac_82599EB:
8044 case ixgbe_mac_X540:
e86bff0e 8045 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8046 break;
8047 default:
8048 break;
8049 }
e86bff0e 8050
bf069c97
DS		 8051 /*
8052 * If there is a fan on this device and it has failed log the
8053 * failure.
8054 */
8055 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8056 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8057 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8058 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8059 }
8060
8ef78adc
PWJ		 8061 if (allow_unsupported_sfp)
8062 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8063
c44ade9e 8064 /* reset_hw fills in the perm_addr as well */
119fc60a 8065 hw->phy.reset_if_overtemp = true;
c44ade9e 8066 err = hw->mac.ops.reset_hw(hw);
119fc60a 8067 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8068 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8069 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8070 err = 0;
8071 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8072 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8073 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8074 goto err_sw_init;
8075 } else if (err) {
849c4542 8076 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8077 goto err_sw_init;
8078 }
8079
99d74487 8080#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8081 /* SR-IOV not supported on the 82598 */
8082 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8083 goto skip_sriov;
8084 /* Mailbox */
8085 ixgbe_init_mbx_params_pf(hw);
8086 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8087 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8088 ixgbe_enable_sriov(adapter);
60a1a680 8089skip_sriov:
1cdd1ec8 8090
99d74487 8091#endif
396e799c 8092 netdev->features = NETIF_F_SG |
e8e9f696 8093 NETIF_F_IP_CSUM |
082757af 8094 NETIF_F_IPV6_CSUM |
f646968f
PM		 8095 NETIF_F_HW_VLAN_CTAG_TX |
8096 NETIF_F_HW_VLAN_CTAG_RX |
8097 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8098 NETIF_F_TSO |
8099 NETIF_F_TSO6 |
082757af 8100 NETIF_F_RXHASH |
8bf1264d 8101 NETIF_F_RXCSUM;
9a799d71 8102
8bf1264d 8103 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8104
58be7666
DS		 8105 switch (adapter->hw.mac.type) {
8106 case ixgbe_mac_82599EB:
8107 case ixgbe_mac_X540:
45a5ead0 8108 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8109 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8110 NETIF_F_NTUPLE;
58be7666
DS		 8111 break;
8112 default:
8113 break;
8114 }
45a5ead0 8115
3f2d1c0f
BG		 8116 netdev->hw_features |= NETIF_F_RXALL;
8117
ad31c402
JK		 8118 netdev->vlan_features |= NETIF_F_TSO;
8119 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8120 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8121 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8122 netdev->vlan_features |= NETIF_F_SG;
8123
01789349 8124 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8125 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8126
7a6b6f51 8127#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8128 netdev->dcbnl_ops = &dcbnl_ops;
8129#endif
8130
eacd73f7 8131#ifdef IXGBE_FCOE
0d551589 8132 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8133 unsigned int fcoe_l;
8134
eacd73f7
YZ		 8135 if (hw->mac.ops.get_device_caps) {
8136 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8137 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8138 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8139 }
7c8ae65a 8140
d3cb9869
AD		 8141
8142 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8143 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8144
a58915c7
AD		 8145 netdev->features |= NETIF_F_FSO |
8146 NETIF_F_FCOE_CRC;
8147
7c8ae65a
AD		 8148 netdev->vlan_features |= NETIF_F_FSO |
8149 NETIF_F_FCOE_CRC |
8150 NETIF_F_FCOE_MTU;
5e09d7f6 8151 }
eacd73f7 8152#endif /* IXGBE_FCOE */
7b872a55 8153 if (pci_using_dac) {
9a799d71 8154 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8155 netdev->vlan_features |= NETIF_F_HIGHDMA;
8156 }
9a799d71 8157
082757af
DS		 8158 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8159 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8160 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8161 netdev->features |= NETIF_F_LRO;
8162
9a799d71 8163 /* make sure the EEPROM is good */
c44ade9e 8164 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8165 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8166 err = -EIO;
35937c05 8167 goto err_sw_init;
9a799d71
AK		 8168 }
8169
8170 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8171
aaeb6cdf 8172 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8173 e_dev_err("invalid MAC address\n");
9a799d71 8174 err = -EIO;
35937c05 8175 goto err_sw_init;
9a799d71
AK		 8176 }
8177
7086400d 8178 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8179 (unsigned long) adapter);
9a799d71 8180
7086400d
AD		 8181 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8182 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8183
021230d4
AV		 8184 err = ixgbe_init_interrupt_scheme(adapter);
8185 if (err)
8186 goto err_sw_init;
9a799d71 8187
8e2813f5 8188 /* WOL not supported for all devices */
c23f5b6b 8189 adapter->wol = 0;
8e2813f5 8190 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8191 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8192 pdev->subsystem_device);
6b92b0ba 8193 if (hw->wol_enabled)
9417c464 8194 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8195
e8e26350
PW		 8196 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8197
15e5209f
ET		 8198 /* save off EEPROM version number */
8199 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8200 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8201
04f165ef
PW		 8202 /* pick up the PCI bus settings for reporting later */
8203 hw->mac.ops.get_bus_info(hw);
e027d1ae 8204 if (ixgbe_pcie_from_parent(hw))
b8e82001 8205 ixgbe_get_parent_bus_info(adapter);
04f165ef 8206
e027d1ae
JK		 8207 /* calculate the expected PCIe bandwidth required for optimal
8208 * performance. Note that some older parts will never have enough
8209 * bandwidth due to being older generation PCIe parts. We clamp these
8210 * parts to ensure no warning is displayed if it can't be fixed.
8211 */
8212 switch (hw->mac.type) {
8213 case ixgbe_mac_82598EB:
8214 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8215 break;
8216 default:
8217 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8218 break;
0c254d86 8219 }
e027d1ae 8220 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8221
6a2aae5a
JK		 8222 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8223 if (err)
8224 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8225 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8226 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8227 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8228 part_str);
8229 else
8230 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8231 hw->mac.type, hw->phy.type, part_str);
8232
8233 e_dev_info("%pM\n", netdev->dev_addr);
8234
9a799d71 8235 /* reset the hardware with the new settings */
794caeb2 8236 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8237 if (err == IXGBE_ERR_EEPROM_VERSION) {
8238 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8239 e_dev_warn("This device is a pre-production adapter/LOM. "
8240 "Please be aware there may be issues associated "
8241 "with your hardware. If you are experiencing "
8242 "problems please contact your Intel or hardware "
8243 "representative who provided you with this "
8244 "hardware.\n");
794caeb2 8245 }
9a799d71
AK		 8246 strcpy(netdev->name, "eth%d");
8247 err = register_netdev(netdev);
8248 if (err)
8249 goto err_register;
8250
ec74a471
ET		 8251 /* power down the optics for 82599 SFP+ fiber */
8252 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8253 hw->mac.ops.disable_tx_laser(hw);
8254
54386467
JB		 8255 /* carrier off reporting is important to ethtool even BEFORE open */
8256 netif_carrier_off(netdev);
8257
5dd2d332 8258#ifdef CONFIG_IXGBE_DCA
652f093f 8259 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8260 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8261 ixgbe_setup_dca(adapter);
8262 }
8263#endif
1cdd1ec8 8264 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8265 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8266 for (i = 0; i < adapter->num_vfs; i++)
8267 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8268 }
8269
2466dd9c
JK		 8270 /* firmware requires driver version to be 0xFFFFFFFF
8271 * since os does not support feature
8272 */
9612de92 8273 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8274 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8275 0xFF);
9612de92 8276
0365e6e4
PW		 8277 /* add san mac addr to netdev */
8278 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8279
ea81875a 8280 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8281 cards_found++;
3ca8bc6d 8282
1210982b 8283#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8284 if (ixgbe_sysfs_init(adapter))
8285 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8286#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8287
00949167 8288 ixgbe_dbg_adapter_init(adapter);
00949167 8289
0b2679d6 8290 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7155d051 8291 if (ixgbe_mng_enabled(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8292 hw->mac.ops.setup_link(hw,
8293 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8294 true);
8295
9a799d71
AK		 8296 return 0;
8297
8298err_register:
5eba3699 8299 ixgbe_release_hw_control(adapter);
7a921c93 8300 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8301err_sw_init:
99d74487 8302 ixgbe_disable_sriov(adapter);
7086400d 8303 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8304 iounmap(adapter->io_addr);
9a799d71
AK		 8305err_ioremap:
8306 free_netdev(netdev);
8307err_alloc_etherdev:
e8e9f696
JP		 8308 pci_release_selected_regions(pdev,
8309 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8310err_pci_reg:
8311err_dma:
8312 pci_disable_device(pdev);
8313 return err;
8314}
8315
8316/**
8317 * ixgbe_remove - Device Removal Routine
8318 * @pdev: PCI device information struct
8319 *
8320 * ixgbe_remove is called by the PCI subsystem to alert the driver
8321 * that it should release a PCI device. The could be caused by a
8322 * Hot-Plug event, or because the driver is going to be removed from
8323 * memory.
8324 **/
9f9a12f8 8325static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8326{
c60fbb00
AD		 8327 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8328 struct net_device *netdev = adapter->netdev;
9a799d71 8329
00949167 8330 ixgbe_dbg_adapter_exit(adapter);
00949167 8331
09f40aed 8332 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8333 cancel_work_sync(&adapter->service_task);
9a799d71 8334
3a6a4eda 8335
5dd2d332 8336#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8338 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8339 dca_remove_requester(&pdev->dev);
8340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8341 }
8342
8343#endif
1210982b 8344#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8345 ixgbe_sysfs_exit(adapter);
1210982b 8346#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8347
0365e6e4
PW		 8348 /* remove the added san mac */
8349 ixgbe_del_sanmac_netdev(netdev);
8350
c4900be0
DS		 8351 if (netdev->reg_state == NETREG_REGISTERED)
8352 unregister_netdev(netdev);
9a799d71 8353
da36b647
GR		 8354#ifdef CONFIG_PCI_IOV
8355 /*
8356 * Only disable SR-IOV on unload if the user specified the now
8357 * deprecated max_vfs module parameter.
8358 */
8359 if (max_vfs)
8360 ixgbe_disable_sriov(adapter);
8361#endif
7a921c93 8362 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8363
021230d4 8364 ixgbe_release_hw_control(adapter);
9a799d71 8365
2b1588c3
AD		 8366#ifdef CONFIG_DCB
8367 kfree(adapter->ixgbe_ieee_pfc);
8368 kfree(adapter->ixgbe_ieee_ets);
8369
8370#endif
2a1a091c 8371 iounmap(adapter->io_addr);
9ce77666 8372 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8373 IORESOURCE_MEM));
9a799d71 8374
849c4542 8375 e_dev_info("complete\n");
021230d4 8376
9a799d71
AK		 8377 free_netdev(netdev);
8378
19d5afd4 8379 pci_disable_pcie_error_reporting(pdev);
6fabd715 8380
9a799d71
AK		 8381 pci_disable_device(pdev);
8382}
8383
8384/**
8385 * ixgbe_io_error_detected - called when PCI error is detected
8386 * @pdev: Pointer to PCI device
8387 * @state: The current pci connection state
8388 *
8389 * This function is called after a PCI bus error affecting
8390 * this device has been detected.
8391 */
8392static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8393 pci_channel_state_t state)
9a799d71 8394{
c60fbb00
AD		 8395 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8396 struct net_device *netdev = adapter->netdev;
9a799d71 8397
83c61fa9 8398#ifdef CONFIG_PCI_IOV
14438464 8399 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8400 struct pci_dev *bdev, *vfdev;
8401 u32 dw0, dw1, dw2, dw3;
8402 int vf, pos;
8403 u16 req_id, pf_func;
8404
8405 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8406 adapter->num_vfs == 0)
8407 goto skip_bad_vf_detection;
8408
8409 bdev = pdev->bus->self;
62f87c0e 8410 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8411 bdev = bdev->bus->self;
8412
8413 if (!bdev)
8414 goto skip_bad_vf_detection;
8415
8416 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8417 if (!pos)
8418 goto skip_bad_vf_detection;
8419
14438464
MR		 8420 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8421 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8422 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8423 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8424 if (ixgbe_removed(hw->hw_addr))
8425 goto skip_bad_vf_detection;
83c61fa9
GR		 8426
8427 req_id = dw1 >> 16;
8428 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8429 if (!(req_id & 0x0080))
8430 goto skip_bad_vf_detection;
8431
8432 pf_func = req_id & 0x01;
8433 if ((pf_func & 1) == (pdev->devfn & 1)) {
8434 unsigned int device_id;
8435
8436 vf = (req_id & 0x7F) >> 1;
8437 e_dev_err("VF %d has caused a PCIe error\n", vf);
8438 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8439 "%8.8x\tdw3: %8.8x\n",
8440 dw0, dw1, dw2, dw3);
8441 switch (adapter->hw.mac.type) {
8442 case ixgbe_mac_82599EB:
8443 device_id = IXGBE_82599_VF_DEVICE_ID;
8444 break;
8445 case ixgbe_mac_X540:
8446 device_id = IXGBE_X540_VF_DEVICE_ID;
8447 break;
8448 default:
8449 device_id = 0;
8450 break;
8451 }
8452
8453 /* Find the pci device of the offending VF */
36e90319 8454 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8455 while (vfdev) {
8456 if (vfdev->devfn == (req_id & 0xFF))
8457 break;
36e90319 8458 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8459 device_id, vfdev);
8460 }
8461 /*
8462 * There's a slim chance the VF could have been hot plugged,
8463 * so if it is no longer present we don't need to issue the
8464 * VFLR. Just clean up the AER in that case.
8465 */
8466 if (vfdev) {
8467 e_dev_err("Issuing VFLR to VF %d\n", vf);
8468 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8469 /* Free device reference count */
8470 pci_dev_put(vfdev);
83c61fa9
GR		 8471 }
8472
8473 pci_cleanup_aer_uncorrect_error_status(pdev);
8474 }
8475
8476 /*
8477 * Even though the error may have occurred on the other port
8478 * we still need to increment the vf error reference count for
8479 * both ports because the I/O resume function will be called
8480 * for both of them.
8481 */
8482 adapter->vferr_refcount++;
8483
8484 return PCI_ERS_RESULT_RECOVERED;
8485
8486skip_bad_vf_detection:
8487#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8488 netif_device_detach(netdev);
8489
3044b8d1
BL		 8490 if (state == pci_channel_io_perm_failure)
8491 return PCI_ERS_RESULT_DISCONNECT;
8492
9a799d71
AK		 8493 if (netif_running(netdev))
8494 ixgbe_down(adapter);
8495 pci_disable_device(pdev);
8496
b4617240 8497 /* Request a slot reset. */
9a799d71
AK		 8498 return PCI_ERS_RESULT_NEED_RESET;
8499}
8500
8501/**
8502 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8503 * @pdev: Pointer to PCI device
8504 *
8505 * Restart the card from scratch, as if from a cold-boot.
8506 */
8507static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8508{
c60fbb00 8509 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8510 pci_ers_result_t result;
8511 int err;
9a799d71 8512
9ce77666 8513 if (pci_enable_device_mem(pdev)) {
396e799c 8514 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8515 result = PCI_ERS_RESULT_DISCONNECT;
8516 } else {
0391bbe3 8517 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8518 pci_set_master(pdev);
8519 pci_restore_state(pdev);
c0e1f68b 8520 pci_save_state(pdev);
9a799d71 8521
dd4d8ca6 8522 pci_wake_from_d3(pdev, false);
9a799d71 8523
6fabd715 8524 ixgbe_reset(adapter);
88512539 8525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8526 result = PCI_ERS_RESULT_RECOVERED;
8527 }
8528
8529 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8530 if (err) {
849c4542
ET		 8531 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8532 "failed 0x%0x\n", err);
6fabd715
PWJ		 8533 /* non-fatal, continue */
8534 }
9a799d71 8535
6fabd715 8536 return result;
9a799d71
AK		 8537}
8538
8539/**
8540 * ixgbe_io_resume - called when traffic can start flowing again.
8541 * @pdev: Pointer to PCI device
8542 *
8543 * This callback is called when the error recovery driver tells us that
8544 * its OK to resume normal operation.
8545 */
8546static void ixgbe_io_resume(struct pci_dev *pdev)
8547{
c60fbb00
AD		 8548 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8549 struct net_device *netdev = adapter->netdev;
9a799d71 8550
83c61fa9
GR		 8551#ifdef CONFIG_PCI_IOV
8552 if (adapter->vferr_refcount) {
8553 e_info(drv, "Resuming after VF err\n");
8554 adapter->vferr_refcount--;
8555 return;
8556 }
8557
8558#endif
c7ccde0f
AD		 8559 if (netif_running(netdev))
8560 ixgbe_up(adapter);
9a799d71
AK		 8561
8562 netif_device_attach(netdev);
9a799d71
AK		 8563}
8564
3646f0e5 8565static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8566 .error_detected = ixgbe_io_error_detected,
8567 .slot_reset = ixgbe_io_slot_reset,
8568 .resume = ixgbe_io_resume,
8569};
8570
8571static struct pci_driver ixgbe_driver = {
8572 .name = ixgbe_driver_name,
8573 .id_table = ixgbe_pci_tbl,
8574 .probe = ixgbe_probe,
9f9a12f8 8575 .remove = ixgbe_remove,
9a799d71
AK		 8576#ifdef CONFIG_PM
8577 .suspend = ixgbe_suspend,
8578 .resume = ixgbe_resume,
8579#endif
8580 .shutdown = ixgbe_shutdown,
da36b647 8581 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8582 .err_handler = &ixgbe_err_handler
8583};
8584
8585/**
8586 * ixgbe_init_module - Driver Registration Routine
8587 *
8588 * ixgbe_init_module is the first routine called when the driver is
8589 * loaded. All it does is register with the PCI subsystem.
8590 **/
8591static int __init ixgbe_init_module(void)
8592{
8593 int ret;
c7689578 8594 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8595 pr_info("%s\n", ixgbe_copyright);
9a799d71 8596
00949167 8597 ixgbe_dbg_init();
00949167 8598
f01fc1a8
JK		 8599 ret = pci_register_driver(&ixgbe_driver);
8600 if (ret) {
f01fc1a8 8601 ixgbe_dbg_exit();
f01fc1a8
JK		 8602 return ret;
8603 }
8604
5dd2d332 8605#ifdef CONFIG_IXGBE_DCA
bd0362dd 8606 dca_register_notify(&dca_notifier);
bd0362dd 8607#endif
5dd2d332 8608
f01fc1a8 8609 return 0;
9a799d71 8610}
b4617240 8611
9a799d71
AK		 8612module_init(ixgbe_init_module);
8613
8614/**
8615 * ixgbe_exit_module - Driver Exit Cleanup Routine
8616 *
8617 * ixgbe_exit_module is called just before the driver is removed
8618 * from memory.
8619 **/
8620static void __exit ixgbe_exit_module(void)
8621{
5dd2d332 8622#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8623 dca_unregister_notify(&dca_notifier);
8624#endif
9a799d71 8625 pci_unregister_driver(&ixgbe_driver);
00949167 8626
00949167 8627 ixgbe_dbg_exit();
00949167 8628
1a51502b 8629 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8630}
bd0362dd 8631
5dd2d332 8632#ifdef CONFIG_IXGBE_DCA
bd0362dd 8633static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8634 void *p)
bd0362dd
JC		 8635{
8636 int ret_val;
8637
8638 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8639 __ixgbe_notify_dca);
bd0362dd
JC		 8640
8641 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8642}
b453368d 8643
5dd2d332 8644#endif /* CONFIG_IXGBE_DCA */
849c4542 8645
9a799d71
AK		 8646module_exit(ixgbe_exit_module);
8647
8648/* ixgbe_main.c */
Linux kernel - Deliverables
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