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ixgbe: Introduce function to control MDIO speed
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
37689010 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
b82b17d9
JF		 54#include <net/pkt_cls.h>
55#include <net/tc_act/tc_gact.h>
9a799d71
AK		 56
57#include "ixgbe.h"
58#include "ixgbe_common.h"
ee5f784a 59#include "ixgbe_dcb_82599.h"
1cdd1ec8 60#include "ixgbe_sriov.h"
b82b17d9 61#include "ixgbe_model.h"
9a799d71
AK		 62
63char ixgbe_driver_name[] = "ixgbe";
9c8eb720 64static const char ixgbe_driver_string[] =
e8e9f696 65 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 66#ifdef IXGBE_FCOE
ea81875a
NP		 67char ixgbe_default_device_descr[] =
68 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 69#else
70static char ixgbe_default_device_descr[] =
71 "Intel(R) 10 Gigabit Network Connection";
72#endif
21dd5601 73#define DRV_VERSION "4.2.1-k"
9c8eb720 74const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 75static const char ixgbe_copyright[] =
49425dfc 76 "Copyright (c) 1999-2016 Intel Corporation.";
9a799d71 77
f44e751b
DS		 78static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
79
9a799d71 80static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 81 [board_82598] = &ixgbe_82598_info,
82 [board_82599] = &ixgbe_82599_info,
83 [board_X540] = &ixgbe_X540_info,
84 [board_X550] = &ixgbe_X550_info,
85 [board_X550EM_x] = &ixgbe_X550EM_x_info,
49425dfc 86 [board_x550em_a] = &ixgbe_x550em_a_info,
9a799d71
AK		 87};
88
89/* ixgbe_pci_tbl - PCI Device ID Table
90 *
91 * Wildcard entries (PCI_ANY_ID) should come last
92 * Last entry must be all 0s
93 *
94 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
95 * Class, Class Mask, private data (not used) }
96 */
9baa3c34 97static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
a711ad89 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
6a14ee0c
DS		 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
49425dfc 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
9a799d71
AK		 135 /* required last entry */
136 {0, }
137};
138MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
139
5dd2d332 140#ifdef CONFIG_IXGBE_DCA
bd0362dd 141static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 142 void *p);
bd0362dd
JC		 143static struct notifier_block dca_notifier = {
144 .notifier_call = ixgbe_notify_dca,
145 .next = NULL,
146 .priority = 0
147};
148#endif
149
1cdd1ec8
GR		 150#ifdef CONFIG_PCI_IOV
151static unsigned int max_vfs;
152module_param(max_vfs, uint, 0);
e8e9f696 153MODULE_PARM_DESC(max_vfs,
170e8543 154 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 155#endif /* CONFIG_PCI_IOV */
156
8ef78adc
PWJ		 157static unsigned int allow_unsupported_sfp;
158module_param(allow_unsupported_sfp, uint, 0);
159MODULE_PARM_DESC(allow_unsupported_sfp,
160 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
161
b3f4d599 162#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
163static int debug = -1;
164module_param(debug, int, 0);
165MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
166
9a799d71
AK		 167MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
168MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
169MODULE_LICENSE("GPL");
170MODULE_VERSION(DRV_VERSION);
171
780484d8
MR		 172static struct workqueue_struct *ixgbe_wq;
173
14438464
MR		 174static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
175
b8e82001
JK		 176static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
177 u32 reg, u16 *value)
178{
b8e82001
JK		 179 struct pci_dev *parent_dev;
180 struct pci_bus *parent_bus;
181
182 parent_bus = adapter->pdev->bus->parent;
183 if (!parent_bus)
184 return -1;
185
186 parent_dev = parent_bus->self;
187 if (!parent_dev)
188 return -1;
189
c0798edf 190 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 191 return -1;
192
c0798edf 193 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 194 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
195 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
196 return -1;
b8e82001
JK		 197 return 0;
198}
199
200static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
201{
202 struct ixgbe_hw *hw = &adapter->hw;
203 u16 link_status = 0;
204 int err;
205
206 hw->bus.type = ixgbe_bus_type_pci_express;
207
208 /* Get the negotiated link width and speed from PCI config space of the
209 * parent, as this device is behind a switch
210 */
211 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
212
213 /* assume caller will handle error case */
214 if (err)
215 return err;
216
217 hw->bus.width = ixgbe_convert_bus_width(link_status);
218 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
219
220 return 0;
221}
222
e027d1ae
JK		 223/**
224 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
225 * @hw: hw specific details
226 *
227 * This function is used by probe to determine whether a device's PCI-Express
228 * bandwidth details should be gathered from the parent bus instead of from the
229 * device. Used to ensure that various locations all have the correct device ID
230 * checks.
231 */
232static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
233{
234 switch (hw->device_id) {
235 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 236 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 237 return true;
238 default:
239 return false;
240 }
241}
242
243static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
244 int expected_gts)
245{
f9328bc6 246 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 247 int max_gts = 0;
248 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
249 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
250 struct pci_dev *pdev;
251
f9328bc6
DS		 252 /* Some devices are not connected over PCIe and thus do not negotiate
253 * speed. These devices do not have valid bus info, and thus any report
254 * we generate may not be correct.
255 */
256 if (hw->bus.type == ixgbe_bus_type_internal)
257 return;
258
56d1392f 259 /* determine whether to use the parent device */
e027d1ae
JK		 260 if (ixgbe_pcie_from_parent(&adapter->hw))
261 pdev = adapter->pdev->bus->parent->self;
262 else
263 pdev = adapter->pdev;
264
265 if (pcie_get_minimum_link(pdev, &speed, &width) ||
266 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
267 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
268 return;
269 }
270
271 switch (speed) {
272 case PCIE_SPEED_2_5GT:
273 /* 8b/10b encoding reduces max throughput by 20% */
274 max_gts = 2 * width;
275 break;
276 case PCIE_SPEED_5_0GT:
277 /* 8b/10b encoding reduces max throughput by 20% */
278 max_gts = 4 * width;
279 break;
280 case PCIE_SPEED_8_0GT:
9f0a433c 281 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 282 max_gts = 8 * width;
283 break;
284 default:
285 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
286 return;
287 }
288
289 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
290 max_gts);
291 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
292 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
293 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
294 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
295 "Unknown"),
296 width,
297 (speed == PCIE_SPEED_2_5GT ? "20%" :
298 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 299 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 300 "Unknown"));
301
302 if (max_gts < expected_gts) {
303 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
304 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
305 expected_gts);
306 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
307 }
308}
309
7086400d
AD		 310static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
311{
312 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 313 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 314 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 315 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 316}
317
2a1a091c
MR		 318static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
319{
320 struct ixgbe_adapter *adapter = hw->back;
321
322 if (!hw->hw_addr)
323 return;
324 hw->hw_addr = NULL;
325 e_dev_err("Adapter removed\n");
58cf663f
MR		 326 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
327 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 328}
329
f8e2472f 330static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 331{
332 u32 value;
333
334 /* The following check not only optimizes a bit by not
335 * performing a read on the status register when the
336 * register just read was a status register read that
337 * returned IXGBE_FAILED_READ_REG. It also blocks any
338 * potential recursion.
339 */
340 if (reg == IXGBE_STATUS) {
341 ixgbe_remove_adapter(hw);
342 return;
343 }
344 value = ixgbe_read_reg(hw, IXGBE_STATUS);
345 if (value == IXGBE_FAILED_READ_REG)
346 ixgbe_remove_adapter(hw);
347}
348
f8e2472f
MR		 349/**
350 * ixgbe_read_reg - Read from device register
351 * @hw: hw specific details
352 * @reg: offset of register to read
353 *
354 * Returns : value read or IXGBE_FAILED_READ_REG if removed
355 *
356 * This function is used to read device registers. It checks for device
357 * removal by confirming any read that returns all ones by checking the
358 * status register value for all ones. This function avoids reading from
359 * the hardware if a removal was previously detected in which case it
360 * returns IXGBE_FAILED_READ_REG (all ones).
361 */
362u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
363{
364 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
365 u32 value;
366
367 if (ixgbe_removed(reg_addr))
368 return IXGBE_FAILED_READ_REG;
369 value = readl(reg_addr + reg);
370 if (unlikely(value == IXGBE_FAILED_READ_REG))
371 ixgbe_check_remove(hw, reg);
372 return value;
373}
374
14438464
MR		 375static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
376{
377 u16 value;
378
379 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
380 if (value == IXGBE_FAILED_READ_CFG_WORD) {
381 ixgbe_remove_adapter(hw);
382 return true;
383 }
384 return false;
385}
386
387u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
388{
389 struct ixgbe_adapter *adapter = hw->back;
390 u16 value;
391
392 if (ixgbe_removed(hw->hw_addr))
393 return IXGBE_FAILED_READ_CFG_WORD;
394 pci_read_config_word(adapter->pdev, reg, &value);
395 if (value == IXGBE_FAILED_READ_CFG_WORD &&
396 ixgbe_check_cfg_remove(hw, adapter->pdev))
397 return IXGBE_FAILED_READ_CFG_WORD;
398 return value;
399}
400
401#ifdef CONFIG_PCI_IOV
402static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
403{
404 struct ixgbe_adapter *adapter = hw->back;
405 u32 value;
406
407 if (ixgbe_removed(hw->hw_addr))
408 return IXGBE_FAILED_READ_CFG_DWORD;
409 pci_read_config_dword(adapter->pdev, reg, &value);
410 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
411 ixgbe_check_cfg_remove(hw, adapter->pdev))
412 return IXGBE_FAILED_READ_CFG_DWORD;
413 return value;
414}
415#endif /* CONFIG_PCI_IOV */
416
ed19231c
JK		 417void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
418{
419 struct ixgbe_adapter *adapter = hw->back;
420
421 if (ixgbe_removed(hw->hw_addr))
422 return;
423 pci_write_config_word(adapter->pdev, reg, value);
424}
425
7086400d
AD		 426static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
427{
428 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
429
52f33af8 430 /* flush memory to make sure state is correct before next watchdog */
4e857c58 431 smp_mb__before_atomic();
7086400d
AD		 432 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
433}
434
dcd79aeb
TI		 435struct ixgbe_reg_info {
436 u32 ofs;
437 char *name;
438};
439
440static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
441
442 /* General Registers */
443 {IXGBE_CTRL, "CTRL"},
444 {IXGBE_STATUS, "STATUS"},
445 {IXGBE_CTRL_EXT, "CTRL_EXT"},
446
447 /* Interrupt Registers */
448 {IXGBE_EICR, "EICR"},
449
450 /* RX Registers */
451 {IXGBE_SRRCTL(0), "SRRCTL"},
452 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
453 {IXGBE_RDLEN(0), "RDLEN"},
454 {IXGBE_RDH(0), "RDH"},
455 {IXGBE_RDT(0), "RDT"},
456 {IXGBE_RXDCTL(0), "RXDCTL"},
457 {IXGBE_RDBAL(0), "RDBAL"},
458 {IXGBE_RDBAH(0), "RDBAH"},
459
460 /* TX Registers */
461 {IXGBE_TDBAL(0), "TDBAL"},
462 {IXGBE_TDBAH(0), "TDBAH"},
463 {IXGBE_TDLEN(0), "TDLEN"},
464 {IXGBE_TDH(0), "TDH"},
465 {IXGBE_TDT(0), "TDT"},
466 {IXGBE_TXDCTL(0), "TXDCTL"},
467
468 /* List Terminator */
ca8dfe25 469 { .name = NULL }
dcd79aeb
TI		 470};
471
472
473/*
474 * ixgbe_regdump - register printout routine
475 */
476static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
477{
478 int i = 0, j = 0;
479 char rname[16];
480 u32 regs[64];
481
482 switch (reginfo->ofs) {
483 case IXGBE_SRRCTL(0):
484 for (i = 0; i < 64; i++)
485 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
486 break;
487 case IXGBE_DCA_RXCTRL(0):
488 for (i = 0; i < 64; i++)
489 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
490 break;
491 case IXGBE_RDLEN(0):
492 for (i = 0; i < 64; i++)
493 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
494 break;
495 case IXGBE_RDH(0):
496 for (i = 0; i < 64; i++)
497 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
498 break;
499 case IXGBE_RDT(0):
500 for (i = 0; i < 64; i++)
501 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
502 break;
503 case IXGBE_RXDCTL(0):
504 for (i = 0; i < 64; i++)
505 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
506 break;
507 case IXGBE_RDBAL(0):
508 for (i = 0; i < 64; i++)
509 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
510 break;
511 case IXGBE_RDBAH(0):
512 for (i = 0; i < 64; i++)
513 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
514 break;
515 case IXGBE_TDBAL(0):
516 for (i = 0; i < 64; i++)
517 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
518 break;
519 case IXGBE_TDBAH(0):
520 for (i = 0; i < 64; i++)
521 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
522 break;
523 case IXGBE_TDLEN(0):
524 for (i = 0; i < 64; i++)
525 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
526 break;
527 case IXGBE_TDH(0):
528 for (i = 0; i < 64; i++)
529 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
530 break;
531 case IXGBE_TDT(0):
532 for (i = 0; i < 64; i++)
533 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
534 break;
535 case IXGBE_TXDCTL(0):
536 for (i = 0; i < 64; i++)
537 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
538 break;
539 default:
c7689578 540 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 541 IXGBE_READ_REG(hw, reginfo->ofs));
542 return;
543 }
544
545 for (i = 0; i < 8; i++) {
546 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 547 pr_err("%-15s", rname);
dcd79aeb 548 for (j = 0; j < 8; j++)
c7689578
JP		 549 pr_cont(" %08x", regs[i*8+j]);
550 pr_cont("\n");
dcd79aeb
TI		 551 }
552
553}
554
555/*
556 * ixgbe_dump - Print registers, tx-rings and rx-rings
557 */
558static void ixgbe_dump(struct ixgbe_adapter *adapter)
559{
560 struct net_device *netdev = adapter->netdev;
561 struct ixgbe_hw *hw = &adapter->hw;
562 struct ixgbe_reg_info *reginfo;
563 int n = 0;
564 struct ixgbe_ring *tx_ring;
729739b7 565 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 566 union ixgbe_adv_tx_desc *tx_desc;
567 struct my_u0 { u64 a; u64 b; } *u0;
568 struct ixgbe_ring *rx_ring;
569 union ixgbe_adv_rx_desc *rx_desc;
570 struct ixgbe_rx_buffer *rx_buffer_info;
571 u32 staterr;
572 int i = 0;
573
574 if (!netif_msg_hw(adapter))
575 return;
576
577 /* Print netdevice Info */
578 if (netdev) {
579 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 580 pr_info("Device Name state "
dcd79aeb 581 "trans_start last_rx\n");
c7689578
JP		 582 pr_info("%-15s %016lX %016lX %016lX\n",
583 netdev->name,
584 netdev->state,
585 netdev->trans_start,
586 netdev->last_rx);
dcd79aeb
TI		 587 }
588
589 /* Print Registers */
590 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 591 pr_info(" Register Name Value\n");
dcd79aeb
TI		 592 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
593 reginfo->name; reginfo++) {
594 ixgbe_regdump(hw, reginfo);
595 }
596
597 /* Print TX Ring Summary */
598 if (!netdev || !netif_running(netdev))
e90dd264 599 return;
dcd79aeb
TI		 600
601 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 602 pr_info(" %s %s %s %s\n",
603 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
604 "leng", "ntw", "timestamp");
dcd79aeb
TI		 605 for (n = 0; n < adapter->num_tx_queues; n++) {
606 tx_ring = adapter->tx_ring[n];
729739b7 607 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 608 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 609 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 610 (u64)dma_unmap_addr(tx_buffer, dma),
611 dma_unmap_len(tx_buffer, len),
612 tx_buffer->next_to_watch,
613 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 614 }
615
616 /* Print TX Rings */
617 if (!netif_msg_tx_done(adapter))
618 goto rx_ring_summary;
619
620 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
621
622 /* Transmit Descriptor Formats
623 *
39ac868a 624 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 625 * +--------------------------------------------------------------+
626 * 0 | Buffer Address [63:0] |
627 * +--------------------------------------------------------------+
39ac868a 628 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 629 * +--------------------------------------------------------------+
630 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 631 *
632 * 82598 Advanced Transmit Descriptor (Write-Back Format)
633 * +--------------------------------------------------------------+
634 * 0 | RSV [63:0] |
635 * +--------------------------------------------------------------+
636 * 8 | RSV | STA | NXTSEQ |
637 * +--------------------------------------------------------------+
638 * 63 36 35 32 31 0
639 *
640 * 82599+ Advanced Transmit Descriptor
641 * +--------------------------------------------------------------+
642 * 0 | Buffer Address [63:0] |
643 * +--------------------------------------------------------------+
644 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
645 * +--------------------------------------------------------------+
646 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
647 *
648 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
649 * +--------------------------------------------------------------+
650 * 0 | RSV [63:0] |
651 * +--------------------------------------------------------------+
652 * 8 | RSV | STA | RSV |
653 * +--------------------------------------------------------------+
654 * 63 36 35 32 31 0
dcd79aeb
TI		 655 */
656
657 for (n = 0; n < adapter->num_tx_queues; n++) {
658 tx_ring = adapter->tx_ring[n];
c7689578
JP		 659 pr_info("------------------------------------\n");
660 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
661 pr_info("------------------------------------\n");
8ad88e37
JH		 662 pr_info("%s%s %s %s %s %s\n",
663 "T [desc] [address 63:0 ] ",
664 "[PlPOIdStDDt Ln] [bi->dma ] ",
665 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 666
667 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 668 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 669 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 670 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 671 if (dma_unmap_len(tx_buffer, len) > 0) {
672 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
673 i,
674 le64_to_cpu(u0->a),
675 le64_to_cpu(u0->b),
676 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 677 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 678 tx_buffer->next_to_watch,
679 (u64)tx_buffer->time_stamp,
680 tx_buffer->skb);
681 if (i == tx_ring->next_to_use &&
682 i == tx_ring->next_to_clean)
683 pr_cont(" NTC/U\n");
684 else if (i == tx_ring->next_to_use)
685 pr_cont(" NTU\n");
686 else if (i == tx_ring->next_to_clean)
687 pr_cont(" NTC\n");
688 else
689 pr_cont("\n");
690
691 if (netif_msg_pktdata(adapter) &&
692 tx_buffer->skb)
693 print_hex_dump(KERN_INFO, "",
694 DUMP_PREFIX_ADDRESS, 16, 1,
695 tx_buffer->skb->data,
696 dma_unmap_len(tx_buffer, len),
697 true);
698 }
dcd79aeb
TI		 699 }
700 }
701
702 /* Print RX Rings Summary */
703rx_ring_summary:
704 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 705 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 706 for (n = 0; n < adapter->num_rx_queues; n++) {
707 rx_ring = adapter->rx_ring[n];
c7689578
JP		 708 pr_info("%5d %5X %5X\n",
709 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 710 }
711
712 /* Print RX Rings */
713 if (!netif_msg_rx_status(adapter))
e90dd264 714 return;
dcd79aeb
TI		 715
716 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
717
39ac868a
JH		 718 /* Receive Descriptor Formats
719 *
720 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 721 * 63 1 0
722 * +-----------------------------------------------------+
723 * 0 | Packet Buffer Address [63:1] |A0/NSE|
724 * +----------------------------------------------+------+
725 * 8 | Header Buffer Address [63:1] | DD |
726 * +-----------------------------------------------------+
727 *
728 *
39ac868a 729 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 730 *
731 * 63 48 47 32 31 30 21 20 16 15 4 3 0
732 * +------------------------------------------------------+
39ac868a
JH		 733 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
734 * | Packet | IP | | | | Type | Type |
735 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 736 * +------------------------------------------------------+
737 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
738 * +------------------------------------------------------+
739 * 63 48 47 32 31 20 19 0
39ac868a
JH		 740 *
741 * 82599+ Advanced Receive Descriptor (Read) Format
742 * 63 1 0
743 * +-----------------------------------------------------+
744 * 0 | Packet Buffer Address [63:1] |A0/NSE|
745 * +----------------------------------------------+------+
746 * 8 | Header Buffer Address [63:1] | DD |
747 * +-----------------------------------------------------+
748 *
749 *
750 * 82599+ Advanced Receive Descriptor (Write-Back) Format
751 *
752 * 63 48 47 32 31 30 21 20 17 16 4 3 0
753 * +------------------------------------------------------+
754 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
755 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
756 * |/ Flow Dir Flt ID | | | | | |
757 * +------------------------------------------------------+
758 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
759 * +------------------------------------------------------+
760 * 63 48 47 32 31 20 19 0
dcd79aeb 761 */
39ac868a 762
dcd79aeb
TI		 763 for (n = 0; n < adapter->num_rx_queues; n++) {
764 rx_ring = adapter->rx_ring[n];
c7689578
JP		 765 pr_info("------------------------------------\n");
766 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
767 pr_info("------------------------------------\n");
8ad88e37
JH		 768 pr_info("%s%s%s",
769 "R [desc] [ PktBuf A0] ",
770 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 771 "<-- Adv Rx Read format\n");
8ad88e37
JH		 772 pr_info("%s%s%s",
773 "RWB[desc] [PcsmIpSHl PtRs] ",
774 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 775 "<-- Adv Rx Write-Back format\n");
776
777 for (i = 0; i < rx_ring->count; i++) {
778 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 779 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 780 u0 = (struct my_u0 *)rx_desc;
781 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
782 if (staterr & IXGBE_RXD_STAT_DD) {
783 /* Descriptor Done */
c7689578 784 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 785 "%016llX ---------------- %p", i,
786 le64_to_cpu(u0->a),
787 le64_to_cpu(u0->b),
788 rx_buffer_info->skb);
789 } else {
c7689578 790 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 791 "%016llX %016llX %p", i,
792 le64_to_cpu(u0->a),
793 le64_to_cpu(u0->b),
794 (u64)rx_buffer_info->dma,
795 rx_buffer_info->skb);
796
9c50c035
ET		 797 if (netif_msg_pktdata(adapter) &&
798 rx_buffer_info->dma) {
dcd79aeb
TI		 799 print_hex_dump(KERN_INFO, "",
800 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 801 page_address(rx_buffer_info->page) +
802 rx_buffer_info->page_offset,
f800326d 803 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 804 }
805 }
806
807 if (i == rx_ring->next_to_use)
c7689578 808 pr_cont(" NTU\n");
dcd79aeb 809 else if (i == rx_ring->next_to_clean)
c7689578 810 pr_cont(" NTC\n");
dcd79aeb 811 else
c7689578 812 pr_cont("\n");
dcd79aeb
TI		 813
814 }
815 }
dcd79aeb
TI		 816}
817
5eba3699
AV		 818static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
819{
820 u32 ctrl_ext;
821
822 /* Let firmware take over control of h/w */
823 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 825 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 826}
827
828static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
829{
830 u32 ctrl_ext;
831
832 /* Let firmware know the driver has taken over */
833 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 835 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 836}
9a799d71 837
49ce9c2c 838/**
e8e26350
PW		 839 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
840 * @adapter: pointer to adapter struct
841 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
842 * @queue: queue to map the corresponding interrupt to
843 * @msix_vector: the vector to map to the corresponding queue
844 *
845 */
846static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 847 u8 queue, u8 msix_vector)
9a799d71
AK		 848{
849 u32 ivar, index;
e8e26350
PW		 850 struct ixgbe_hw *hw = &adapter->hw;
851 switch (hw->mac.type) {
852 case ixgbe_mac_82598EB:
853 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
854 if (direction == -1)
855 direction = 0;
856 index = (((direction * 64) + queue) >> 2) & 0x1F;
857 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
858 ivar &= ~(0xFF << (8 * (queue & 0x3)));
859 ivar |= (msix_vector << (8 * (queue & 0x3)));
860 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
861 break;
862 case ixgbe_mac_82599EB:
b93a2226 863 case ixgbe_mac_X540:
9a75a1ac
DS		 864 case ixgbe_mac_X550:
865 case ixgbe_mac_X550EM_x:
49425dfc 866 case ixgbe_mac_x550em_a:
e8e26350
PW		 867 if (direction == -1) {
868 /* other causes */
869 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
870 index = ((queue & 1) * 8);
871 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
872 ivar &= ~(0xFF << index);
873 ivar |= (msix_vector << index);
874 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
875 break;
876 } else {
877 /* tx or rx causes */
878 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
879 index = ((16 * (queue & 1)) + (8 * direction));
880 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
881 ivar &= ~(0xFF << index);
882 ivar |= (msix_vector << index);
883 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
884 break;
885 }
886 default:
887 break;
888 }
9a799d71
AK		 889}
890
fe49f04a 891static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 892 u64 qmask)
fe49f04a
AD		 893{
894 u32 mask;
895
bd508178
AD		 896 switch (adapter->hw.mac.type) {
897 case ixgbe_mac_82598EB:
fe49f04a
AD		 898 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 900 break;
901 case ixgbe_mac_82599EB:
b93a2226 902 case ixgbe_mac_X540:
9a75a1ac
DS		 903 case ixgbe_mac_X550:
904 case ixgbe_mac_X550EM_x:
49425dfc 905 case ixgbe_mac_x550em_a:
fe49f04a
AD		 906 mask = (qmask & 0xFFFFFFFF);
907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
908 mask = (qmask >> 32);
909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 910 break;
911 default:
912 break;
fe49f04a
AD		 913 }
914}
915
729739b7
AD		 916void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
917 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 918{
729739b7
AD		 919 if (tx_buffer->skb) {
920 dev_kfree_skb_any(tx_buffer->skb);
921 if (dma_unmap_len(tx_buffer, len))
d3d00239 922 dma_unmap_single(ring->dev,
729739b7
AD		 923 dma_unmap_addr(tx_buffer, dma),
924 dma_unmap_len(tx_buffer, len),
925 DMA_TO_DEVICE);
926 } else if (dma_unmap_len(tx_buffer, len)) {
927 dma_unmap_page(ring->dev,
928 dma_unmap_addr(tx_buffer, dma),
929 dma_unmap_len(tx_buffer, len),
930 DMA_TO_DEVICE);
e5a43549 931 }
729739b7
AD		 932 tx_buffer->next_to_watch = NULL;
933 tx_buffer->skb = NULL;
934 dma_unmap_len_set(tx_buffer, len, 0);
935 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 936}
937
943561d3 938static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 939{
940 struct ixgbe_hw *hw = &adapter->hw;
941 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 942 int i;
943561d3 943 u32 data;
c84d324c 944
943561d3
AD		 945 if ((hw->fc.current_mode != ixgbe_fc_full) &&
946 (hw->fc.current_mode != ixgbe_fc_rx_pause))
947 return;
c84d324c 948
943561d3
AD		 949 switch (hw->mac.type) {
950 case ixgbe_mac_82598EB:
951 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
952 break;
953 default:
954 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
955 }
956 hwstats->lxoffrxc += data;
c84d324c 957
943561d3
AD		 958 /* refill credits (no tx hang) if we received xoff */
959 if (!data)
c84d324c 960 return;
943561d3
AD		 961
962 for (i = 0; i < adapter->num_tx_queues; i++)
963 clear_bit(__IXGBE_HANG_CHECK_ARMED,
964 &adapter->tx_ring[i]->state);
965}
966
967static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
968{
969 struct ixgbe_hw *hw = &adapter->hw;
970 struct ixgbe_hw_stats *hwstats = &adapter->stats;
971 u32 xoff[8] = {0};
2afaa00d 972 u8 tc;
943561d3
AD		 973 int i;
974 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
975
976 if (adapter->ixgbe_ieee_pfc)
977 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
978
979 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
980 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 981 return;
943561d3 982 }
c84d324c
JF		 983
984 /* update stats for each tc, only valid with PFC enabled */
985 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 986 u32 pxoffrxc;
987
c84d324c
JF		 988 switch (hw->mac.type) {
989 case ixgbe_mac_82598EB:
2afaa00d 990 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 991 break;
c84d324c 992 default:
2afaa00d 993 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 994 }
2afaa00d
PN		 995 hwstats->pxoffrxc[i] += pxoffrxc;
996 /* Get the TC for given UP */
997 tc = netdev_get_prio_tc_map(adapter->netdev, i);
998 xoff[tc] += pxoffrxc;
c84d324c
JF		 999 }
1000
1001 /* disarm tx queues that have received xoff frames */
1002 for (i = 0; i < adapter->num_tx_queues; i++) {
1003 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1004
2afaa00d 1005 tc = tx_ring->dcb_tc;
c84d324c
JF		 1006 if (xoff[tc])
1007 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1008 }
26f23d82
YZ		 1009}
1010
c84d324c 1011static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1012{
7d7ce682 1013 return ring->stats.packets;
c84d324c
JF		 1014}
1015
1016static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1017{
2a47fa45
JF		 1018 struct ixgbe_adapter *adapter;
1019 struct ixgbe_hw *hw;
1020 u32 head, tail;
1021
1022 if (ring->l2_accel_priv)
1023 adapter = ring->l2_accel_priv->real_adapter;
1024 else
1025 adapter = netdev_priv(ring->netdev);
e01c31a5 1026
2a47fa45
JF		 1027 hw = &adapter->hw;
1028 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1029 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1030
1031 if (head != tail)
1032 return (head < tail) ?
1033 tail - head : (tail + ring->count - head);
1034
1035 return 0;
1036}
1037
1038static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1039{
1040 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1041 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1042 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1043
7d637bcc 1044 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1045
1046 /*
1047 * Check for a hung queue, but be thorough. This verifies
1048 * that a transmit has been completed since the previous
1049 * check AND there is at least one packet pending. The
1050 * ARMED bit is set to indicate a potential hang. The
1051 * bit is cleared if a pause frame is received to remove
1052 * false hang detection due to PFC or 802.3x frames. By
1053 * requiring this to fail twice we avoid races with
1054 * pfc clearing the ARMED bit and conditions where we
1055 * run the check_tx_hang logic with a transmit completion
1056 * pending but without time to complete it yet.
1057 */
e90dd264 1058 if (tx_done_old == tx_done && tx_pending)
c84d324c 1059 /* make sure it is true for two checks in a row */
e90dd264
MR		 1060 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1061 &tx_ring->state);
1062 /* update completed stats and continue */
1063 tx_ring->tx_stats.tx_done_old = tx_done;
1064 /* reset the countdown */
1065 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1066
e90dd264 1067 return false;
9a799d71
AK		 1068}
1069
c83c6cbd
AD		 1070/**
1071 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1072 * @adapter: driver private struct
1073 **/
1074static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1075{
1076
1077 /* Do the reset outside of interrupt context */
1078 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1079 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1080 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1081 ixgbe_service_event_schedule(adapter);
1082 }
1083}
e01c31a5 1084
c04f90e5
RP		 1085/**
1086 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1087 **/
1088static int ixgbe_tx_maxrate(struct net_device *netdev,
1089 int queue_index, u32 maxrate)
1090{
1091 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1092 struct ixgbe_hw *hw = &adapter->hw;
1093 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1094
1095 if (!maxrate)
1096 return 0;
1097
1098 /* Calculate the rate factor values to set */
1099 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1100 bcnrc_val /= maxrate;
1101
1102 /* clear everything but the rate factor */
1103 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1104 IXGBE_RTTBCNRC_RF_DEC_MASK;
1105
1106 /* enable the rate scheduler */
1107 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1108
1109 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1110 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1111
1112 return 0;
1113}
1114
9a799d71
AK		 1115/**
1116 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1117 * @q_vector: structure containing interrupt and ring information
e01c31a5 1118 * @tx_ring: tx ring to clean
8220bbc1 1119 * @napi_budget: Used to determine if we are in netpoll
9a799d71 1120 **/
fe49f04a 1121static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1122 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1123{
fe49f04a 1124 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1125 struct ixgbe_tx_buffer *tx_buffer;
1126 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1127 unsigned int total_bytes = 0, total_packets = 0;
59224555 1128 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1129 unsigned int i = tx_ring->next_to_clean;
1130
1131 if (test_bit(__IXGBE_DOWN, &adapter->state))
1132 return true;
9a799d71 1133
d3d00239 1134 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1135 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1136 i -= tx_ring->count;
12207e49 1137
729739b7 1138 do {
d3d00239
AD		 1139 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1140
1141 /* if next_to_watch is not set then there is no work pending */
1142 if (!eop_desc)
1143 break;
1144
7f83a9e6 1145 /* prevent any other reads prior to eop_desc */
7e63bf49 1146 read_barrier_depends();
7f83a9e6 1147
d3d00239
AD		 1148 /* if DD is not set pending work has not been completed */
1149 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1150 break;
8ad494b0 1151
d3d00239
AD		 1152 /* clear next_to_watch to prevent false hangs */
1153 tx_buffer->next_to_watch = NULL;
8ad494b0 1154
091a6246
AD		 1155 /* update the statistics for this packet */
1156 total_bytes += tx_buffer->bytecount;
1157 total_packets += tx_buffer->gso_segs;
1158
fd0db0ed 1159 /* free the skb */
a3a8749d 1160 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1161
729739b7
AD		 1162 /* unmap skb header data */
1163 dma_unmap_single(tx_ring->dev,
1164 dma_unmap_addr(tx_buffer, dma),
1165 dma_unmap_len(tx_buffer, len),
1166 DMA_TO_DEVICE);
1167
fd0db0ed
AD		 1168 /* clear tx_buffer data */
1169 tx_buffer->skb = NULL;
729739b7 1170 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1171
729739b7
AD		 1172 /* unmap remaining buffers */
1173 while (tx_desc != eop_desc) {
d3d00239
AD		 1174 tx_buffer++;
1175 tx_desc++;
8ad494b0 1176 i++;
729739b7
AD		 1177 if (unlikely(!i)) {
1178 i -= tx_ring->count;
d3d00239 1179 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1180 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1181 }
e01c31a5 1182
729739b7
AD		 1183 /* unmap any remaining paged data */
1184 if (dma_unmap_len(tx_buffer, len)) {
1185 dma_unmap_page(tx_ring->dev,
1186 dma_unmap_addr(tx_buffer, dma),
1187 dma_unmap_len(tx_buffer, len),
1188 DMA_TO_DEVICE);
1189 dma_unmap_len_set(tx_buffer, len, 0);
1190 }
1191 }
1192
1193 /* move us one more past the eop_desc for start of next pkt */
1194 tx_buffer++;
1195 tx_desc++;
1196 i++;
1197 if (unlikely(!i)) {
1198 i -= tx_ring->count;
1199 tx_buffer = tx_ring->tx_buffer_info;
1200 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1201 }
1202
1203 /* issue prefetch for next Tx descriptor */
1204 prefetch(tx_desc);
12207e49 1205
729739b7
AD		 1206 /* update budget accounting */
1207 budget--;
1208 } while (likely(budget));
1209
1210 i += tx_ring->count;
9a799d71 1211 tx_ring->next_to_clean = i;
d3d00239 1212 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1213 tx_ring->stats.bytes += total_bytes;
bd198058 1214 tx_ring->stats.packets += total_packets;
d3d00239 1215 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1216 q_vector->tx.total_bytes += total_bytes;
1217 q_vector->tx.total_packets += total_packets;
b953799e 1218
c84d324c
JF		 1219 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1220 /* schedule immediate reset if we believe we hung */
1221 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1222 e_err(drv, "Detected Tx Unit Hang\n"
1223 " Tx Queue <%d>\n"
1224 " TDH, TDT <%x>, <%x>\n"
1225 " next_to_use <%x>\n"
1226 " next_to_clean <%x>\n"
1227 "tx_buffer_info[next_to_clean]\n"
1228 " time_stamp <%lx>\n"
1229 " jiffies <%lx>\n",
1230 tx_ring->queue_index,
1231 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1232 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1233 tx_ring->next_to_use, i,
1234 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1235
1236 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1237
1238 e_info(probe,
1239 "tx hang %d detected on queue %d, resetting adapter\n",
1240 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1241
b953799e 1242 /* schedule immediate reset if we believe we hung */
c83c6cbd 1243 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1244
1245 /* the adapter is about to reset, no point in enabling stuff */
59224555 1246 return true;
b953799e 1247 }
9a799d71 1248
b2d96e0a
AD		 1249 netdev_tx_completed_queue(txring_txq(tx_ring),
1250 total_packets, total_bytes);
1251
e092be60 1252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1255 /* Make sure that anybody stopping the queue after this
1256 * sees the new next_to_clean.
1257 */
1258 smp_mb();
729739b7
AD		 1259 if (__netif_subqueue_stopped(tx_ring->netdev,
1260 tx_ring->queue_index)
1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1262 netif_wake_subqueue(tx_ring->netdev,
1263 tx_ring->queue_index);
5b7da515 1264 ++tx_ring->tx_stats.restart_queue;
30eba97a 1265 }
e092be60 1266 }
9a799d71 1267
59224555 1268 return !!budget;
9a799d71
AK		 1269}
1270
5dd2d332 1271#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1272static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1273 struct ixgbe_ring *tx_ring,
33cf09c9 1274 int cpu)
bd0362dd 1275{
33cf09c9 1276 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1277 u32 txctrl = 0;
bdda1a61 1278 u16 reg_offset;
33cf09c9 1279
9de7605e
MR		 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1282
33cf09c9
AD		 1283 switch (hw->mac.type) {
1284 case ixgbe_mac_82598EB:
bdda1a61 1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1286 break;
1287 case ixgbe_mac_82599EB:
b93a2226 1288 case ixgbe_mac_X540:
bdda1a61
AD		 1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1291 break;
1292 default:
bdda1a61
AD		 1293 /* for unknown hardware do not write register */
1294 return;
bd0362dd 1295 }
bdda1a61
AD		 1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1307}
1308
bdda1a61
AD		 1309static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1310 struct ixgbe_ring *rx_ring,
33cf09c9 1311 int cpu)
bd0362dd 1312{
33cf09c9 1313 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1314 u32 rxctrl = 0;
bdda1a61
AD		 1315 u8 reg_idx = rx_ring->reg_idx;
1316
9de7605e
MR		 1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1319
1320 switch (hw->mac.type) {
33cf09c9 1321 case ixgbe_mac_82599EB:
b93a2226 1322 case ixgbe_mac_X540:
bdda1a61 1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1324 break;
1325 default:
1326 break;
1327 }
bdda1a61
AD		 1328
1329 /*
1330 * We can enable relaxed ordering for reads, but not writes when
1331 * DCA is enabled. This is due to a known issue in some chipsets
1332 * which will cause the DCA tag to be cleared.
1333 */
1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1337
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1339}
1340
1341static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1342{
1343 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1344 struct ixgbe_ring *ring;
bd0362dd 1345 int cpu = get_cpu();
bd0362dd 1346
33cf09c9
AD		 1347 if (q_vector->cpu == cpu)
1348 goto out_no_update;
1349
a557928e 1350 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1351 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1352
a557928e 1353 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1354 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1355
1356 q_vector->cpu = cpu;
1357out_no_update:
bd0362dd
JC		 1358 put_cpu();
1359}
1360
1361static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1362{
1363 int i;
1364
e35ec126 1365 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1369 else
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1371 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1372
49c7ffbe 1373 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1374 adapter->q_vector[i]->cpu = -1;
1375 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1376 }
1377}
1378
1379static int __ixgbe_notify_dca(struct device *dev, void *data)
1380{
c60fbb00 1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1382 unsigned long event = *(unsigned long *)data;
1383
2a72c31e 1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1385 return 0;
1386
bd0362dd
JC		 1387 switch (event) {
1388 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1389 /* if we're already enabled, don't do it again */
1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 break;
652f093f 1392 if (dca_add_requester(dev) == 0) {
96b0e0f6 1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1395 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1396 break;
1397 }
1398 /* Fall Through since DCA is disabled. */
1399 case DCA_PROVIDER_REMOVE:
1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1401 dca_remove_requester(dev);
1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1404 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1405 }
1406 break;
1407 }
1408
652f093f 1409 return 0;
bd0362dd 1410}
67a74ee2 1411
bdda1a61 1412#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1413
1414#define IXGBE_RSS_L4_TYPES_MASK \
1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1419
8a0da21b
AD		 1420static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1421 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1422 struct sk_buff *skb)
1423{
7edda4b8
FD		 1424 u16 rss_type;
1425
1426 if (!(ring->netdev->features & NETIF_F_RXHASH))
1427 return;
1428
1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1430 IXGBE_RXDADV_RSSTYPE_MASK;
1431
1432 if (!rss_type)
1433 return;
1434
1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1438}
1439
f800326d 1440#ifdef IXGBE_FCOE
ff886dfc
AD		 1441/**
1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1443 * @ring: structure containing ring specific data
ff886dfc
AD		 1444 * @rx_desc: advanced rx descriptor
1445 *
1446 * Returns : true if it is FCoE pkt
1447 */
57efd44c 1448static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1449 union ixgbe_adv_rx_desc *rx_desc)
1450{
1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1452
57efd44c 1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1457}
1458
f800326d 1459#endif /* IXGBE_FCOE */
e59bd25d
AV		 1460/**
1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1462 * @ring: structure containing ring specific data
1463 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1464 * @skb: skb currently being received and modified
1465 **/
8a0da21b 1466static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1467 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1468 struct sk_buff *skb)
9a799d71 1469{
3f207800
DS		 1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1471 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1472 bool encap_pkt = false;
1473
8a0da21b 1474 skb_checksum_none_assert(skb);
9a799d71 1475
712744be 1476 /* Rx csum disabled */
8a0da21b 1477 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1478 return;
e59bd25d 1479
3f207800
DS		 1480 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1481 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1482 encap_pkt = true;
1483 skb->encapsulation = 1;
3f207800
DS		 1484 }
1485
e59bd25d 1486 /* if IP and error */
f56e0cb1
AD		 1487 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1488 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1489 ring->rx_stats.csum_err++;
9a799d71
AK		 1490 return;
1491 }
e59bd25d 1492
f56e0cb1 1493 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1494 return;
1495
f56e0cb1 1496 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1497 /*
1498 * 82599 errata, UDP frames with a 0 checksum can be marked as
1499 * checksum errors.
1500 */
8a0da21b
AD		 1501 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1502 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1503 return;
1504
8a0da21b 1505 ring->rx_stats.csum_err++;
e59bd25d
AV		 1506 return;
1507 }
1508
9a799d71 1509 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1510 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1511 if (encap_pkt) {
1512 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1513 return;
1514
1515 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1516 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1517 return;
1518 }
1519 /* If we checked the outer header let the stack know */
1520 skb->csum_level = 1;
1521 }
9a799d71
AK		 1522}
1523
f990b79b
AD		 1524static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1525 struct ixgbe_rx_buffer *bi)
1526{
1527 struct page *page = bi->page;
18cb652a 1528 dma_addr_t dma;
f990b79b 1529
f800326d 1530 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1531 if (likely(page))
f990b79b
AD		 1532 return true;
1533
f800326d 1534 /* alloc new page for storage */
18cb652a
AD		 1535 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1536 if (unlikely(!page)) {
1537 rx_ring->rx_stats.alloc_rx_page_failed++;
1538 return false;
f990b79b
AD		 1539 }
1540
f800326d
AD		 1541 /* map page for use */
1542 dma = dma_map_page(rx_ring->dev, page, 0,
1543 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1544
1545 /*
1546 * if mapping failed free memory back to system since
1547 * there isn't much point in holding memory we can't use
1548 */
1549 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1550 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1551
f990b79b
AD		 1552 rx_ring->rx_stats.alloc_rx_page_failed++;
1553 return false;
1554 }
1555
f800326d 1556 bi->dma = dma;
18cb652a 1557 bi->page = page;
afaa9459 1558 bi->page_offset = 0;
f800326d 1559
f990b79b
AD		 1560 return true;
1561}
1562
9a799d71 1563/**
f990b79b 1564 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1565 * @rx_ring: ring to place buffers on
1566 * @cleaned_count: number of buffers to replace
9a799d71 1567 **/
fc77dc3c 1568void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1569{
9a799d71 1570 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1571 struct ixgbe_rx_buffer *bi;
d5f398ed 1572 u16 i = rx_ring->next_to_use;
9a799d71 1573
f800326d
AD		 1574 /* nothing to do */
1575 if (!cleaned_count)
fc77dc3c
AD		 1576 return;
1577
e4f74028 1578 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1579 bi = &rx_ring->rx_buffer_info[i];
1580 i -= rx_ring->count;
9a799d71 1581
f800326d
AD		 1582 do {
1583 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1584 break;
d5f398ed 1585
f800326d
AD		 1586 /*
1587 * Refresh the desc even if buffer_addrs didn't change
1588 * because each write-back erases this info.
1589 */
1590 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1591
f990b79b
AD		 1592 rx_desc++;
1593 bi++;
9a799d71 1594 i++;
f990b79b 1595 if (unlikely(!i)) {
e4f74028 1596 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1597 bi = rx_ring->rx_buffer_info;
1598 i -= rx_ring->count;
1599 }
1600
18cb652a
AD		 1601 /* clear the status bits for the next_to_use descriptor */
1602 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1603
1604 cleaned_count--;
1605 } while (cleaned_count);
7c6e0a43 1606
f990b79b
AD		 1607 i += rx_ring->count;
1608
ad435ec6
AD		 1609 if (rx_ring->next_to_use != i) {
1610 rx_ring->next_to_use = i;
1611
1612 /* update next to alloc since we have filled the ring */
1613 rx_ring->next_to_alloc = i;
1614
1615 /* Force memory writes to complete before letting h/w
1616 * know there are new descriptors to fetch. (Only
1617 * applicable for weak-ordered memory model archs,
1618 * such as IA-64).
1619 */
1620 wmb();
1621 writel(i, rx_ring->tail);
1622 }
9a799d71
AK		 1623}
1624
1d2024f6
AD		 1625static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1626 struct sk_buff *skb)
1627{
f800326d 1628 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1629
1630 /* set gso_size to avoid messing up TCP MSS */
1631 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1632 IXGBE_CB(skb)->append_cnt);
96be80ab 1633 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1634}
1635
1636static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1637 struct sk_buff *skb)
1638{
1639 /* if append_cnt is 0 then frame is not RSC */
1640 if (!IXGBE_CB(skb)->append_cnt)
1641 return;
1642
1643 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1644 rx_ring->rx_stats.rsc_flush++;
1645
1646 ixgbe_set_rsc_gso_size(rx_ring, skb);
1647
1648 /* gso_size is computed using append_cnt so always clear it last */
1649 IXGBE_CB(skb)->append_cnt = 0;
1650}
1651
8a0da21b
AD		 1652/**
1653 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1654 * @rx_ring: rx descriptor ring packet is being transacted on
1655 * @rx_desc: pointer to the EOP Rx descriptor
1656 * @skb: pointer to current skb being populated
f8212f97 1657 *
8a0da21b
AD		 1658 * This function checks the ring, descriptor, and packet information in
1659 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1660 * other fields within the skb.
f8212f97 1661 **/
8a0da21b
AD		 1662static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1663 union ixgbe_adv_rx_desc *rx_desc,
1664 struct sk_buff *skb)
f8212f97 1665{
43e95f11 1666 struct net_device *dev = rx_ring->netdev;
a9763f3c 1667 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1668
8a0da21b
AD		 1669 ixgbe_update_rsc_stats(rx_ring, skb);
1670
1671 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1672
8a0da21b
AD		 1673 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1674
a9763f3c
MR		 1675 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1676 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1677
f646968f 1678 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1679 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1680 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1681 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1682 }
1683
8a0da21b 1684 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1685
43e95f11 1686 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1687}
1688
8a0da21b
AD		 1689static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1690 struct sk_buff *skb)
aa80175a 1691{
93f93a44 1692 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1693 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1694 netif_receive_skb(skb);
8a0da21b 1695 else
856f606e 1696 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1697}
43634e82 1698
f800326d
AD		 1699/**
1700 * ixgbe_is_non_eop - process handling of non-EOP buffers
1701 * @rx_ring: Rx ring being processed
1702 * @rx_desc: Rx descriptor for current buffer
1703 * @skb: Current socket buffer containing buffer in progress
1704 *
1705 * This function updates next to clean. If the buffer is an EOP buffer
1706 * this function exits returning false, otherwise it will place the
1707 * sk_buff in the next buffer to be chained and return true indicating
1708 * that this is in fact a non-EOP buffer.
1709 **/
1710static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1711 union ixgbe_adv_rx_desc *rx_desc,
1712 struct sk_buff *skb)
1713{
1714 u32 ntc = rx_ring->next_to_clean + 1;
1715
1716 /* fetch, update, and store next to clean */
1717 ntc = (ntc < rx_ring->count) ? ntc : 0;
1718 rx_ring->next_to_clean = ntc;
1719
1720 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1721
5a02cbd1
AD		 1722 /* update RSC append count if present */
1723 if (ring_is_rsc_enabled(rx_ring)) {
1724 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1725 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1726
1727 if (unlikely(rsc_enabled)) {
1728 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1729
1730 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1731 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1732
5a02cbd1
AD		 1733 /* update ntc based on RSC value */
1734 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1735 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1736 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1737 }
f800326d
AD		 1738 }
1739
5a02cbd1
AD		 1740 /* if we are the last buffer then there is nothing else to do */
1741 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1742 return false;
1743
f800326d
AD		 1744 /* place skb in next buffer to be received */
1745 rx_ring->rx_buffer_info[ntc].skb = skb;
1746 rx_ring->rx_stats.non_eop_descs++;
1747
1748 return true;
1749}
1750
19861ce2
AD		 1751/**
1752 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1753 * @rx_ring: rx descriptor ring packet is being transacted on
1754 * @skb: pointer to current skb being adjusted
1755 *
1756 * This function is an ixgbe specific version of __pskb_pull_tail. The
1757 * main difference between this version and the original function is that
1758 * this function can make several assumptions about the state of things
1759 * that allow for significant optimizations versus the standard function.
1760 * As a result we can do things like drop a frag and maintain an accurate
1761 * truesize for the skb.
1762 */
1763static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1764 struct sk_buff *skb)
1765{
1766 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1767 unsigned char *va;
1768 unsigned int pull_len;
1769
1770 /*
1771 * it is valid to use page_address instead of kmap since we are
1772 * working with pages allocated out of the lomem pool per
1773 * alloc_page(GFP_ATOMIC)
1774 */
1775 va = skb_frag_address(frag);
1776
1777 /*
1778 * we need the header to contain the greater of either ETH_HLEN or
1779 * 60 bytes if the skb->len is less than 60 for skb_pad.
1780 */
8496e338 1781 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1782
1783 /* align pull length to size of long to optimize memcpy performance */
1784 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1785
1786 /* update all of the pointers */
1787 skb_frag_size_sub(frag, pull_len);
1788 frag->page_offset += pull_len;
1789 skb->data_len -= pull_len;
1790 skb->tail += pull_len;
19861ce2
AD		 1791}
1792
42073d91
AD		 1793/**
1794 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1795 * @rx_ring: rx descriptor ring packet is being transacted on
1796 * @skb: pointer to current skb being updated
1797 *
1798 * This function provides a basic DMA sync up for the first fragment of an
1799 * skb. The reason for doing this is that the first fragment cannot be
1800 * unmapped until we have reached the end of packet descriptor for a buffer
1801 * chain.
1802 */
1803static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1804 struct sk_buff *skb)
1805{
1806 /* if the page was released unmap it, else just sync our portion */
1807 if (unlikely(IXGBE_CB(skb)->page_released)) {
1808 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1809 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1810 IXGBE_CB(skb)->page_released = false;
1811 } else {
1812 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1813
1814 dma_sync_single_range_for_cpu(rx_ring->dev,
1815 IXGBE_CB(skb)->dma,
1816 frag->page_offset,
1817 ixgbe_rx_bufsz(rx_ring),
1818 DMA_FROM_DEVICE);
1819 }
1820 IXGBE_CB(skb)->dma = 0;
1821}
1822
f800326d
AD		 1823/**
1824 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1825 * @rx_ring: rx descriptor ring packet is being transacted on
1826 * @rx_desc: pointer to the EOP Rx descriptor
1827 * @skb: pointer to current skb being fixed
1828 *
1829 * Check for corrupted packet headers caused by senders on the local L2
1830 * embedded NIC switch not setting up their Tx Descriptors right. These
1831 * should be very rare.
1832 *
1833 * Also address the case where we are pulling data in on pages only
1834 * and as such no data is present in the skb header.
1835 *
1836 * In addition if skb is not at least 60 bytes we need to pad it so that
1837 * it is large enough to qualify as a valid Ethernet frame.
1838 *
1839 * Returns true if an error was encountered and skb was freed.
1840 **/
1841static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1842 union ixgbe_adv_rx_desc *rx_desc,
1843 struct sk_buff *skb)
1844{
f800326d 1845 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1846
1847 /* verify that the packet does not have any known errors */
1848 if (unlikely(ixgbe_test_staterr(rx_desc,
1849 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1850 !(netdev->features & NETIF_F_RXALL))) {
1851 dev_kfree_skb_any(skb);
1852 return true;
1853 }
1854
19861ce2 1855 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1856 if (skb_is_nonlinear(skb))
1857 ixgbe_pull_tail(rx_ring, skb);
f800326d 1858
57efd44c
AD		 1859#ifdef IXGBE_FCOE
1860 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1861 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1862 return false;
1863
1864#endif
a94d9e22
AD		 1865 /* if eth_skb_pad returns an error the skb was freed */
1866 if (eth_skb_pad(skb))
1867 return true;
f800326d
AD		 1868
1869 return false;
1870}
1871
f800326d
AD		 1872/**
1873 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1874 * @rx_ring: rx descriptor ring to store buffers on
1875 * @old_buff: donor buffer to have page reused
1876 *
0549ae20 1877 * Synchronizes page for reuse by the adapter
f800326d
AD		 1878 **/
1879static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1880 struct ixgbe_rx_buffer *old_buff)
1881{
1882 struct ixgbe_rx_buffer *new_buff;
1883 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1884
1885 new_buff = &rx_ring->rx_buffer_info[nta];
1886
1887 /* update, and store next to alloc */
1888 nta++;
1889 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1890
1891 /* transfer page from old buffer to new buffer */
18cb652a 1892 *new_buff = *old_buff;
f800326d
AD		 1893
1894 /* sync the buffer for use by the device */
1895 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1896 new_buff->page_offset,
1897 ixgbe_rx_bufsz(rx_ring),
f800326d 1898 DMA_FROM_DEVICE);
f800326d
AD		 1899}
1900
18cb652a
AD		 1901static inline bool ixgbe_page_is_reserved(struct page *page)
1902{
2f064f34 1903 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1904}
1905
f800326d
AD		 1906/**
1907 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1908 * @rx_ring: rx descriptor ring to transact packets on
1909 * @rx_buffer: buffer containing page to add
1910 * @rx_desc: descriptor containing length of buffer written by hardware
1911 * @skb: sk_buff to place the data into
1912 *
0549ae20
AD		 1913 * This function will add the data contained in rx_buffer->page to the skb.
1914 * This is done either through a direct copy if the data in the buffer is
1915 * less than the skb header size, otherwise it will just attach the page as
1916 * a frag to the skb.
1917 *
1918 * The function will then update the page offset if necessary and return
1919 * true if the buffer can be reused by the adapter.
f800326d 1920 **/
0549ae20 1921static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1922 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1923 union ixgbe_adv_rx_desc *rx_desc,
1924 struct sk_buff *skb)
f800326d 1925{
0549ae20
AD		 1926 struct page *page = rx_buffer->page;
1927 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1928#if (PAGE_SIZE < 8192)
0549ae20 1929 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1930#else
1931 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1932 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1933 ixgbe_rx_bufsz(rx_ring);
1934#endif
0549ae20 1935
cf3fe7ac
AD		 1936 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1937 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1938
1939 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1940
18cb652a
AD		 1941 /* page is not reserved, we can reuse buffer as-is */
1942 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1943 return true;
1944
1945 /* this page cannot be reused so discard it */
18cb652a 1946 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1947 return false;
1948 }
1949
0549ae20
AD		 1950 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1951 rx_buffer->page_offset, size, truesize);
1952
09816fbe 1953 /* avoid re-using remote pages */
18cb652a 1954 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1955 return false;
1956
1957#if (PAGE_SIZE < 8192)
1958 /* if we are only owner of page we can reuse it */
1959 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1960 return false;
1961
1962 /* flip page offset to other buffer */
1963 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1964#else
1965 /* move offset up to the next cache line */
1966 rx_buffer->page_offset += truesize;
1967
1968 if (rx_buffer->page_offset > last_offset)
1969 return false;
09816fbe 1970#endif
0549ae20 1971
18cb652a
AD		 1972 /* Even if we own the page, we are not allowed to use atomic_set()
1973 * This would break get_page_unless_zero() users.
1974 */
fe896d18 1975 page_ref_inc(page);
18cb652a 1976
0549ae20 1977 return true;
f800326d
AD		 1978}
1979
18806c9e
AD		 1980static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1981 union ixgbe_adv_rx_desc *rx_desc)
1982{
1983 struct ixgbe_rx_buffer *rx_buffer;
1984 struct sk_buff *skb;
1985 struct page *page;
1986
1987 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1988 page = rx_buffer->page;
1989 prefetchw(page);
1990
1991 skb = rx_buffer->skb;
1992
1993 if (likely(!skb)) {
1994 void *page_addr = page_address(page) +
1995 rx_buffer->page_offset;
1996
1997 /* prefetch first cache line of first page */
1998 prefetch(page_addr);
1999#if L1_CACHE_BYTES < 128
2000 prefetch(page_addr + L1_CACHE_BYTES);
2001#endif
2002
2003 /* allocate a skb to store the frags */
67fd893e
AD		 2004 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
2005 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 2006 if (unlikely(!skb)) {
2007 rx_ring->rx_stats.alloc_rx_buff_failed++;
2008 return NULL;
2009 }
2010
2011 /*
2012 * we will be copying header into skb->data in
2013 * pskb_may_pull so it is in our interest to prefetch
2014 * it now to avoid a possible cache miss
2015 */
2016 prefetchw(skb->data);
2017
2018 /*
2019 * Delay unmapping of the first packet. It carries the
2020 * header information, HW may still access the header
2021 * after the writeback. Only unmap it when EOP is
2022 * reached
2023 */
2024 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2025 goto dma_sync;
2026
2027 IXGBE_CB(skb)->dma = rx_buffer->dma;
2028 } else {
2029 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2030 ixgbe_dma_sync_frag(rx_ring, skb);
2031
2032dma_sync:
2033 /* we are reusing so sync this buffer for CPU use */
2034 dma_sync_single_range_for_cpu(rx_ring->dev,
2035 rx_buffer->dma,
2036 rx_buffer->page_offset,
2037 ixgbe_rx_bufsz(rx_ring),
2038 DMA_FROM_DEVICE);
18cb652a
AD		 2039
2040 rx_buffer->skb = NULL;
18806c9e
AD		 2041 }
2042
2043 /* pull page into skb */
2044 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2045 /* hand second half of page back to the ring */
2046 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2047 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2048 /* the page has been released from the ring */
2049 IXGBE_CB(skb)->page_released = true;
2050 } else {
2051 /* we are not reusing the buffer so unmap it */
2052 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2053 ixgbe_rx_pg_size(rx_ring),
2054 DMA_FROM_DEVICE);
2055 }
2056
2057 /* clear contents of buffer_info */
18806c9e
AD		 2058 rx_buffer->page = NULL;
2059
2060 return skb;
f800326d
AD		 2061}
2062
2063/**
2064 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2065 * @q_vector: structure containing interrupt and ring information
2066 * @rx_ring: rx descriptor ring to transact packets on
2067 * @budget: Total limit on number of packets to process
2068 *
2069 * This function provides a "bounce buffer" approach to Rx interrupt
2070 * processing. The advantage to this is that on systems that have
2071 * expensive overhead for IOMMU access this provides a means of avoiding
2072 * it by maintaining the mapping of the page to the syste.
2073 *
5a85e737 2074 * Returns amount of work completed
f800326d 2075 **/
5a85e737 2076static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2077 struct ixgbe_ring *rx_ring,
f4de00ed 2078 const int budget)
9a799d71 2079{
d2f4fbe2 2080 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2081#ifdef IXGBE_FCOE
f800326d 2082 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2083 int ddp_bytes;
2084 unsigned int mss = 0;
3d8fd385 2085#endif /* IXGBE_FCOE */
f800326d 2086 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2087
fdabfc8a 2088 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2089 union ixgbe_adv_rx_desc *rx_desc;
2090 struct sk_buff *skb;
f800326d
AD		 2091
2092 /* return some buffers to hardware, one at a time is too slow */
2093 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2094 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2095 cleaned_count = 0;
2096 }
2097
18806c9e 2098 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2099
124b74c1 2100 if (!rx_desc->wb.upper.status_error)
f800326d 2101 break;
9a799d71 2102
124b74c1 2103 /* This memory barrier is needed to keep us from reading
f800326d 2104 * any other fields out of the rx_desc until we know the
124b74c1 2105 * descriptor has been written back
f800326d 2106 */
124b74c1 2107 dma_rmb();
9a799d71 2108
18806c9e
AD		 2109 /* retrieve a buffer from the ring */
2110 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2111
18806c9e
AD		 2112 /* exit if we failed to retrieve a buffer */
2113 if (!skb)
2114 break;
9a799d71 2115
9a799d71 2116 cleaned_count++;
f8212f97 2117
f800326d
AD		 2118 /* place incomplete frames back on ring for completion */
2119 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2120 continue;
c267fc16 2121
f800326d
AD		 2122 /* verify the packet layout is correct */
2123 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2124 continue;
9a799d71 2125
d2f4fbe2
AV		 2126 /* probably a little skewed due to removing CRC */
2127 total_rx_bytes += skb->len;
d2f4fbe2 2128
8a0da21b
AD		 2129 /* populate checksum, timestamp, VLAN, and protocol */
2130 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2131
332d4a7d
YZ		 2132#ifdef IXGBE_FCOE
2133 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2134 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2135 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2136 /* include DDPed FCoE data */
2137 if (ddp_bytes > 0) {
2138 if (!mss) {
2139 mss = rx_ring->netdev->mtu -
2140 sizeof(struct fcoe_hdr) -
2141 sizeof(struct fc_frame_header) -
2142 sizeof(struct fcoe_crc_eof);
2143 if (mss > 512)
2144 mss &= ~511;
2145 }
2146 total_rx_bytes += ddp_bytes;
2147 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2148 mss);
2149 }
63d635b2
AD		 2150 if (!ddp_bytes) {
2151 dev_kfree_skb_any(skb);
f800326d 2152 continue;
63d635b2 2153 }
3d8fd385 2154 }
f800326d 2155
332d4a7d 2156#endif /* IXGBE_FCOE */
8a0da21b 2157 ixgbe_rx_skb(q_vector, skb);
9a799d71 2158
f800326d 2159 /* update budget accounting */
f4de00ed 2160 total_rx_packets++;
fdabfc8a 2161 }
9a799d71 2162
c267fc16
AD		 2163 u64_stats_update_begin(&rx_ring->syncp);
2164 rx_ring->stats.packets += total_rx_packets;
2165 rx_ring->stats.bytes += total_rx_bytes;
2166 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2167 q_vector->rx.total_packets += total_rx_packets;
2168 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2169
5a85e737 2170 return total_rx_packets;
9a799d71
AK		 2171}
2172
e0d1095a 2173#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2174/* must be called with local_bh_disable()d */
2175static int ixgbe_low_latency_recv(struct napi_struct *napi)
2176{
2177 struct ixgbe_q_vector *q_vector =
2178 container_of(napi, struct ixgbe_q_vector, napi);
2179 struct ixgbe_adapter *adapter = q_vector->adapter;
2180 struct ixgbe_ring *ring;
2181 int found = 0;
2182
2183 if (test_bit(__IXGBE_DOWN, &adapter->state))
2184 return LL_FLUSH_FAILED;
2185
2186 if (!ixgbe_qv_lock_poll(q_vector))
2187 return LL_FLUSH_BUSY;
2188
2189 ixgbe_for_each_ring(ring, q_vector->rx) {
2190 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2191#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2192 if (found)
2193 ring->stats.cleaned += found;
2194 else
2195 ring->stats.misses++;
2196#endif
5a85e737
ET		 2197 if (found)
2198 break;
2199 }
2200
2201 ixgbe_qv_unlock_poll(q_vector);
2202
2203 return found;
2204}
e0d1095a 2205#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2206
9a799d71
AK		 2207/**
2208 * ixgbe_configure_msix - Configure MSI-X hardware
2209 * @adapter: board private structure
2210 *
2211 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2212 * interrupts.
2213 **/
2214static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2215{
021230d4 2216 struct ixgbe_q_vector *q_vector;
49c7ffbe 2217 int v_idx;
021230d4 2218 u32 mask;
9a799d71 2219
8e34d1aa
AD		 2220 /* Populate MSIX to EITR Select */
2221 if (adapter->num_vfs > 32) {
2222 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2223 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2224 }
2225
4df10466
JB		 2226 /*
2227 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2228 * corresponding register.
2229 */
49c7ffbe 2230 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2231 struct ixgbe_ring *ring;
7a921c93 2232 q_vector = adapter->q_vector[v_idx];
021230d4 2233
a557928e 2234 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2235 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2236
a557928e 2237 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2238 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2239
fe49f04a 2240 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2241 }
2242
bd508178
AD		 2243 switch (adapter->hw.mac.type) {
2244 case ixgbe_mac_82598EB:
e8e26350 2245 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2246 v_idx);
bd508178
AD		 2247 break;
2248 case ixgbe_mac_82599EB:
b93a2226 2249 case ixgbe_mac_X540:
9a75a1ac
DS		 2250 case ixgbe_mac_X550:
2251 case ixgbe_mac_X550EM_x:
49425dfc 2252 case ixgbe_mac_x550em_a:
e8e26350 2253 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2254 break;
bd508178
AD		 2255 default:
2256 break;
2257 }
021230d4
AV		 2258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2259
41fb9248 2260 /* set up to autoclear timer, and the vectors */
021230d4 2261 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2262 mask &= ~(IXGBE_EIMS_OTHER |
2263 IXGBE_EIMS_MAILBOX |
2264 IXGBE_EIMS_LSC);
2265
021230d4 2266 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2267}
2268
f494e8fa
AV		 2269enum latency_range {
2270 lowest_latency = 0,
2271 low_latency = 1,
2272 bulk_latency = 2,
2273 latency_invalid = 255
2274};
2275
2276/**
2277 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2278 * @q_vector: structure containing interrupt and ring information
2279 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2280 *
2281 * Stores a new ITR value based on packets and byte
2282 * counts during the last interrupt. The advantage of per interrupt
2283 * computation is faster updates and more accurate ITR for the current
2284 * traffic pattern. Constants in this function were computed
2285 * based on theoretical maximum wire speed and thresholds were set based
2286 * on testing data as well as attempting to minimize response time
2287 * while increasing bulk throughput.
2288 * this functionality is controlled by the InterruptThrottleRate module
2289 * parameter (see ixgbe_param.c)
2290 **/
bd198058
AD		 2291static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2292 struct ixgbe_ring_container *ring_container)
f494e8fa 2293{
bd198058
AD		 2294 int bytes = ring_container->total_bytes;
2295 int packets = ring_container->total_packets;
2296 u32 timepassed_us;
621bd70e 2297 u64 bytes_perint;
bd198058 2298 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2299
2300 if (packets == 0)
bd198058 2301 return;
f494e8fa
AV		 2302
2303 /* simple throttlerate management
621bd70e
AD		 2304 * 0-10MB/s lowest (100000 ints/s)
2305 * 10-20MB/s low (20000 ints/s)
8ac34f10 2306 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2307 */
2308 /* what was last interrupt timeslice? */
d5bf4f67 2309 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2310 if (timepassed_us == 0)
2311 return;
2312
f494e8fa
AV		 2313 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2314
2315 switch (itr_setting) {
2316 case lowest_latency:
621bd70e 2317 if (bytes_perint > 10)
bd198058 2318 itr_setting = low_latency;
f494e8fa
AV		 2319 break;
2320 case low_latency:
621bd70e 2321 if (bytes_perint > 20)
bd198058 2322 itr_setting = bulk_latency;
621bd70e 2323 else if (bytes_perint <= 10)
bd198058 2324 itr_setting = lowest_latency;
f494e8fa
AV		 2325 break;
2326 case bulk_latency:
621bd70e 2327 if (bytes_perint <= 20)
bd198058 2328 itr_setting = low_latency;
f494e8fa
AV		 2329 break;
2330 }
2331
bd198058
AD		 2332 /* clear work counters since we have the values we need */
2333 ring_container->total_bytes = 0;
2334 ring_container->total_packets = 0;
2335
2336 /* write updated itr to ring container */
2337 ring_container->itr = itr_setting;
f494e8fa
AV		 2338}
2339
509ee935
JB		 2340/**
2341 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2342 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2343 *
2344 * This function is made to be called by ethtool and by the driver
2345 * when it needs to update EITR registers at runtime. Hardware
2346 * specific quirks/differences are taken care of here.
2347 */
fe49f04a 2348void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2349{
fe49f04a 2350 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2351 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2352 int v_idx = q_vector->v_idx;
5d967eb7 2353 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2354
bd508178
AD		 2355 switch (adapter->hw.mac.type) {
2356 case ixgbe_mac_82598EB:
509ee935
JB		 2357 /* must write high and low 16 bits to reset counter */
2358 itr_reg |= (itr_reg << 16);
bd508178
AD		 2359 break;
2360 case ixgbe_mac_82599EB:
b93a2226 2361 case ixgbe_mac_X540:
9a75a1ac
DS		 2362 case ixgbe_mac_X550:
2363 case ixgbe_mac_X550EM_x:
49425dfc 2364 case ixgbe_mac_x550em_a:
509ee935
JB		 2365 /*
2366 * set the WDIS bit to not clear the timer bits and cause an
2367 * immediate assertion of the interrupt
2368 */
2369 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2370 break;
2371 default:
2372 break;
509ee935
JB		 2373 }
2374 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2375}
2376
bd198058 2377static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2378{
d5bf4f67 2379 u32 new_itr = q_vector->itr;
bd198058 2380 u8 current_itr;
f494e8fa 2381
bd198058
AD		 2382 ixgbe_update_itr(q_vector, &q_vector->tx);
2383 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2384
08c8833b 2385 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2386
2387 switch (current_itr) {
2388 /* counts and packets in update_itr are dependent on these numbers */
2389 case lowest_latency:
d5bf4f67 2390 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2391 break;
2392 case low_latency:
d5bf4f67 2393 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2394 break;
2395 case bulk_latency:
8ac34f10 2396 new_itr = IXGBE_12K_ITR;
f494e8fa 2397 break;
bd198058
AD		 2398 default:
2399 break;
f494e8fa
AV		 2400 }
2401
d5bf4f67 2402 if (new_itr != q_vector->itr) {
fe49f04a 2403 /* do an exponential smoothing */
d5bf4f67
ET		 2404 new_itr = (10 * new_itr * q_vector->itr) /
2405 ((9 * new_itr) + q_vector->itr);
509ee935 2406
bd198058 2407 /* save the algorithm value here */
5d967eb7 2408 q_vector->itr = new_itr;
fe49f04a
AD		 2409
2410 ixgbe_write_eitr(q_vector);
f494e8fa 2411 }
f494e8fa
AV		 2412}
2413
119fc60a 2414/**
de88eeeb 2415 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2416 * @adapter: pointer to adapter
119fc60a 2417 **/
f0f9778d 2418static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2419{
119fc60a
MC		 2420 struct ixgbe_hw *hw = &adapter->hw;
2421 u32 eicr = adapter->interrupt_event;
2422
f0f9778d 2423 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2424 return;
2425
f0f9778d
AD		 2426 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2427 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2428 return;
2429
2430 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2431
7ca647bd 2432 switch (hw->device_id) {
f0f9778d
AD		 2433 case IXGBE_DEV_ID_82599_T3_LOM:
2434 /*
2435 * Since the warning interrupt is for both ports
2436 * we don't have to check if:
2437 * - This interrupt wasn't for our port.
2438 * - We may have missed the interrupt so always have to
2439 * check if we got a LSC
2440 */
9a900eca 2441 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2442 !(eicr & IXGBE_EICR_LSC))
2443 return;
2444
2445 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2446 u32 speed;
f0f9778d 2447 bool link_up = false;
7ca647bd 2448
3d292265 2449 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2450
f0f9778d
AD		 2451 if (link_up)
2452 return;
2453 }
2454
2455 /* Check if this is not due to overtemp */
2456 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2457 return;
2458
2459 break;
7ca647bd 2460 default:
597f22d6
DS		 2461 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2462 return;
9a900eca 2463 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2464 return;
7ca647bd 2465 break;
119fc60a 2466 }
f44e751b 2467 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2468
2469 adapter->interrupt_event = 0;
119fc60a
MC		 2470}
2471
0befdb3e
JB		 2472static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2473{
2474 struct ixgbe_hw *hw = &adapter->hw;
2475
2476 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2477 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2478 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2479 /* write to clear the interrupt */
9a900eca 2480 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2481 }
2482}
cf8280ee 2483
4f51bf70
JK		 2484static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2485{
9a900eca
DS		 2486 struct ixgbe_hw *hw = &adapter->hw;
2487
4f51bf70
JK		 2488 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2489 return;
2490
2491 switch (adapter->hw.mac.type) {
2492 case ixgbe_mac_82599EB:
2493 /*
2494 * Need to check link state so complete overtemp check
2495 * on service task
2496 */
9a900eca
DS		 2497 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2498 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2499 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2500 adapter->interrupt_event = eicr;
2501 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2502 ixgbe_service_event_schedule(adapter);
2503 return;
2504 }
2505 return;
2506 case ixgbe_mac_X540:
2507 if (!(eicr & IXGBE_EICR_TS))
2508 return;
2509 break;
2510 default:
2511 return;
2512 }
2513
f44e751b 2514 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2515}
2516
45788d2a
DS		 2517static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2518{
2519 switch (hw->mac.type) {
2520 case ixgbe_mac_82598EB:
2521 if (hw->phy.type == ixgbe_phy_nl)
2522 return true;
2523 return false;
2524 case ixgbe_mac_82599EB:
2525 case ixgbe_mac_X550EM_x:
49425dfc 2526 case ixgbe_mac_x550em_a:
45788d2a
DS		 2527 switch (hw->mac.ops.get_media_type(hw)) {
2528 case ixgbe_media_type_fiber:
2529 case ixgbe_media_type_fiber_qsfp:
2530 return true;
2531 default:
2532 return false;
2533 }
2534 default:
2535 return false;
2536 }
2537}
2538
e8e26350
PW		 2539static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2540{
2541 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2542 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2543
4ccc650c
DS		 2544 if (!ixgbe_is_sfp(hw))
2545 return;
2546
2547 /* Later MAC's use different SDP */
2548 if (hw->mac.type >= ixgbe_mac_X540)
2549 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2550
2551 if (eicr & eicr_mask) {
73c4b7cd 2552 /* Clear the interrupt */
4ccc650c 2553 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2554 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2555 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2556 adapter->sfp_poll_time = 0;
7086400d
AD		 2557 ixgbe_service_event_schedule(adapter);
2558 }
73c4b7cd
AD		 2559 }
2560
4ccc650c
DS		 2561 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2562 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2563 /* Clear the interrupt */
9a900eca 2564 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2565 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2566 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2567 ixgbe_service_event_schedule(adapter);
2568 }
e8e26350
PW		 2569 }
2570}
2571
cf8280ee
JB		 2572static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2573{
2574 struct ixgbe_hw *hw = &adapter->hw;
2575
2576 adapter->lsc_int++;
2577 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2578 adapter->link_check_timeout = jiffies;
2579 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2580 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2581 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2582 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2583 }
2584}
2585
fe49f04a
AD		 2586static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2587 u64 qmask)
2588{
2589 u32 mask;
bd508178 2590 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2591
bd508178
AD		 2592 switch (hw->mac.type) {
2593 case ixgbe_mac_82598EB:
fe49f04a 2594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2595 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2596 break;
2597 case ixgbe_mac_82599EB:
b93a2226 2598 case ixgbe_mac_X540:
9a75a1ac
DS		 2599 case ixgbe_mac_X550:
2600 case ixgbe_mac_X550EM_x:
49425dfc 2601 case ixgbe_mac_x550em_a:
fe49f04a 2602 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2603 if (mask)
2604 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2605 mask = (qmask >> 32);
bd508178
AD		 2606 if (mask)
2607 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2608 break;
2609 default:
2610 break;
fe49f04a
AD		 2611 }
2612 /* skip the flush */
2613}
2614
2615static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2616 u64 qmask)
fe49f04a
AD		 2617{
2618 u32 mask;
bd508178 2619 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2620
bd508178
AD		 2621 switch (hw->mac.type) {
2622 case ixgbe_mac_82598EB:
fe49f04a 2623 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2624 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2625 break;
2626 case ixgbe_mac_82599EB:
b93a2226 2627 case ixgbe_mac_X540:
9a75a1ac
DS		 2628 case ixgbe_mac_X550:
2629 case ixgbe_mac_X550EM_x:
49425dfc 2630 case ixgbe_mac_x550em_a:
fe49f04a 2631 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2632 if (mask)
2633 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2634 mask = (qmask >> 32);
bd508178
AD		 2635 if (mask)
2636 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2637 break;
2638 default:
2639 break;
fe49f04a
AD		 2640 }
2641 /* skip the flush */
2642}
2643
021230d4 2644/**
2c4af694
AD		 2645 * ixgbe_irq_enable - Enable default interrupt generation settings
2646 * @adapter: board private structure
021230d4 2647 **/
2c4af694
AD		 2648static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2649 bool flush)
9a799d71 2650{
9a900eca 2651 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2652 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2653
2c4af694
AD		 2654 /* don't reenable LSC while waiting for link */
2655 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2656 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2657
2c4af694 2658 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2659 switch (adapter->hw.mac.type) {
2660 case ixgbe_mac_82599EB:
9a900eca 2661 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2662 break;
2663 case ixgbe_mac_X540:
9a75a1ac
DS		 2664 case ixgbe_mac_X550:
2665 case ixgbe_mac_X550EM_x:
49425dfc 2666 case ixgbe_mac_x550em_a:
4f51bf70
JK		 2667 mask |= IXGBE_EIMS_TS;
2668 break;
2669 default:
2670 break;
2671 }
2c4af694 2672 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2673 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2674 switch (adapter->hw.mac.type) {
2675 case ixgbe_mac_82599EB:
9a900eca
DS		 2676 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2677 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2678 /* fall through */
858bc081 2679 case ixgbe_mac_X540:
9a75a1ac
DS		 2680 case ixgbe_mac_X550:
2681 case ixgbe_mac_X550EM_x:
49425dfc
MR		 2682 case ixgbe_mac_x550em_a:
2683 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2684 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
cbd45ec7 2685 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2686 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2687 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2688 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2689 mask |= IXGBE_EIMS_MAILBOX;
2690 break;
2691 default:
2692 break;
9a799d71 2693 }
db0677fa 2694
2c4af694
AD		 2695 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2696 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2697 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2698
2c4af694
AD		 2699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2700 if (queues)
2701 ixgbe_irq_enable_queues(adapter, ~0);
2702 if (flush)
2703 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2704}
2705
2c4af694 2706static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2707{
a65151ba 2708 struct ixgbe_adapter *adapter = data;
9a799d71 2709 struct ixgbe_hw *hw = &adapter->hw;
54037505 2710 u32 eicr;
91281fd3 2711
54037505
DS		 2712 /*
2713 * Workaround for Silicon errata. Use clear-by-write instead
2714 * of clear-by-read. Reading with EICS will return the
2715 * interrupt causes without clearing, which later be done
2716 * with the write to EICR.
2717 */
2718 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2719
2720 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2721 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2722 * the bits are high when ixgbe_msix_other is called. There is a race
2723 * condition otherwise which results in possible performance loss
2724 * especially if the ixgbe_msix_other interrupt is triggering
2725 * consistently (as it would when PPS is turned on for the X540 device)
2726 */
2727 eicr &= 0xFFFF0000;
2728
54037505 2729 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2730
cf8280ee
JB		 2731 if (eicr & IXGBE_EICR_LSC)
2732 ixgbe_check_lsc(adapter);
f0848276 2733
1cdd1ec8
GR		 2734 if (eicr & IXGBE_EICR_MAILBOX)
2735 ixgbe_msg_task(adapter);
efe3d3c8 2736
bd508178
AD		 2737 switch (hw->mac.type) {
2738 case ixgbe_mac_82599EB:
b93a2226 2739 case ixgbe_mac_X540:
9a75a1ac
DS		 2740 case ixgbe_mac_X550:
2741 case ixgbe_mac_X550EM_x:
49425dfc 2742 case ixgbe_mac_x550em_a:
597f22d6
DS		 2743 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2744 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2745 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2746 ixgbe_service_event_schedule(adapter);
2747 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2748 IXGBE_EICR_GPI_SDP0_X540);
2749 }
d773ce2d
DS		 2750 if (eicr & IXGBE_EICR_ECC) {
2751 e_info(link, "Received ECC Err, initiating reset\n");
2752 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2753 ixgbe_service_event_schedule(adapter);
2754 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2755 }
c4cf55e5
PWJ		 2756 /* Handle Flow Director Full threshold interrupt */
2757 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2758 int reinit_count = 0;
c4cf55e5 2759 int i;
c4cf55e5 2760 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2761 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2762 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2763 &ring->state))
2764 reinit_count++;
2765 }
2766 if (reinit_count) {
2767 /* no more flow director interrupts until after init */
2768 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2769 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2770 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2771 }
2772 }
f0f9778d 2773 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2774 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2775 break;
2776 default:
2777 break;
c4cf55e5 2778 }
f0848276 2779
bd508178 2780 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2781
db0677fa 2782 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2783 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2784
7086400d 2785 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2786 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2787 ixgbe_irq_enable(adapter, false, false);
f0848276 2788
9a799d71 2789 return IRQ_HANDLED;
f0848276 2790}
91281fd3 2791
4ff7fb12 2792static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2793{
021230d4 2794 struct ixgbe_q_vector *q_vector = data;
91281fd3 2795
9b471446 2796 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2797
4ff7fb12 2798 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2799 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2800
9a799d71 2801 return IRQ_HANDLED;
91281fd3
AD		 2802}
2803
eb01b975
AD		 2804/**
2805 * ixgbe_poll - NAPI Rx polling callback
2806 * @napi: structure for representing this polling device
2807 * @budget: how many packets driver is allowed to clean
2808 *
2809 * This function is used for legacy and MSI, NAPI mode
2810 **/
8af3c33f 2811int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2812{
2813 struct ixgbe_q_vector *q_vector =
2814 container_of(napi, struct ixgbe_q_vector, napi);
2815 struct ixgbe_adapter *adapter = q_vector->adapter;
2816 struct ixgbe_ring *ring;
32b3e08f 2817 int per_ring_budget, work_done = 0;
eb01b975
AD		 2818 bool clean_complete = true;
2819
2820#ifdef CONFIG_IXGBE_DCA
2821 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2822 ixgbe_update_dca(q_vector);
2823#endif
2824
8220bbc1
AD		 2825 ixgbe_for_each_ring(ring, q_vector->tx) {
2826 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
2827 clean_complete = false;
2828 }
eb01b975 2829
5d6002b7
AD		 2830 /* Exit if we are called by netpoll or busy polling is active */
2831 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2832 return budget;
2833
eb01b975
AD		 2834 /* attempt to distribute budget to each queue fairly, but don't allow
2835 * the budget to go below 1 because we'll exit polling */
2836 if (q_vector->rx.count > 1)
2837 per_ring_budget = max(budget/q_vector->rx.count, 1);
2838 else
2839 per_ring_budget = budget;
2840
32b3e08f
JB		 2841 ixgbe_for_each_ring(ring, q_vector->rx) {
2842 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2843 per_ring_budget);
2844
2845 work_done += cleaned;
8220bbc1
AD		 2846 if (cleaned >= per_ring_budget)
2847 clean_complete = false;
32b3e08f 2848 }
eb01b975 2849
5a85e737 2850 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2851 /* If all work not completed, return budget and keep polling */
2852 if (!clean_complete)
2853 return budget;
2854
2855 /* all work done, exit the polling mode */
32b3e08f 2856 napi_complete_done(napi, work_done);
eb01b975
AD		 2857 if (adapter->rx_itr_setting & 1)
2858 ixgbe_set_itr(q_vector);
2859 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2860 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2861
2862 return 0;
2863}
2864
021230d4
AV		 2865/**
2866 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2867 * @adapter: board private structure
2868 *
2869 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2870 * interrupts from the kernel.
2871 **/
2872static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2873{
2874 struct net_device *netdev = adapter->netdev;
207867f5 2875 int vector, err;
e8e9f696 2876 int ri = 0, ti = 0;
021230d4 2877
49c7ffbe 2878 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2879 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2880 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2881
4ff7fb12 2882 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2883 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2884 "%s-%s-%d", netdev->name, "TxRx", ri++);
2885 ti++;
2886 } else if (q_vector->rx.ring) {
9fe93afd 2887 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2888 "%s-%s-%d", netdev->name, "rx", ri++);
2889 } else if (q_vector->tx.ring) {
9fe93afd 2890 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2891 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2892 } else {
2893 /* skip this unused q_vector */
2894 continue;
32aa77a4 2895 }
207867f5
AD		 2896 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2897 q_vector->name, q_vector);
9a799d71 2898 if (err) {
396e799c 2899 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2900 "Error: %d\n", err);
021230d4 2901 goto free_queue_irqs;
9a799d71 2902 }
207867f5
AD		 2903 /* If Flow Director is enabled, set interrupt affinity */
2904 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2905 /* assign the mask for this irq */
2906 irq_set_affinity_hint(entry->vector,
de88eeeb 2907 &q_vector->affinity_mask);
207867f5 2908 }
9a799d71
AK		 2909 }
2910
021230d4 2911 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2912 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2913 if (err) {
de88eeeb 2914 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2915 goto free_queue_irqs;
9a799d71
AK		 2916 }
2917
9a799d71
AK		 2918 return 0;
2919
021230d4 2920free_queue_irqs:
207867f5
AD		 2921 while (vector) {
2922 vector--;
2923 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2924 NULL);
2925 free_irq(adapter->msix_entries[vector].vector,
2926 adapter->q_vector[vector]);
2927 }
021230d4
AV		 2928 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2929 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2930 kfree(adapter->msix_entries);
2931 adapter->msix_entries = NULL;
9a799d71
AK		 2932 return err;
2933}
2934
2935/**
021230d4 2936 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2937 * @irq: interrupt number
2938 * @data: pointer to a network interface device structure
9a799d71
AK		 2939 **/
2940static irqreturn_t ixgbe_intr(int irq, void *data)
2941{
a65151ba 2942 struct ixgbe_adapter *adapter = data;
9a799d71 2943 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2944 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2945 u32 eicr;
2946
54037505 2947 /*
24ddd967 2948 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2949 * before the read of EICR.
2950 */
2951 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2952
021230d4 2953 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2954 * therefore no explicit interrupt disable is necessary */
021230d4 2955 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2956 if (!eicr) {
6af3b9eb
ET		 2957 /*
2958 * shared interrupt alert!
f47cf66e 2959 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2960 * have disabled interrupts due to EIAM
2961 * finish the workaround of silicon errata on 82598. Unmask
2962 * the interrupt that we masked before the EICR read.
2963 */
2964 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2965 ixgbe_irq_enable(adapter, true, true);
9a799d71 2966 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2967 }
9a799d71 2968
cf8280ee
JB		 2969 if (eicr & IXGBE_EICR_LSC)
2970 ixgbe_check_lsc(adapter);
021230d4 2971
bd508178
AD		 2972 switch (hw->mac.type) {
2973 case ixgbe_mac_82599EB:
e8e26350 2974 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2975 /* Fall through */
2976 case ixgbe_mac_X540:
9a75a1ac
DS		 2977 case ixgbe_mac_X550:
2978 case ixgbe_mac_X550EM_x:
49425dfc 2979 case ixgbe_mac_x550em_a:
d773ce2d
DS		 2980 if (eicr & IXGBE_EICR_ECC) {
2981 e_info(link, "Received ECC Err, initiating reset\n");
2982 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2983 ixgbe_service_event_schedule(adapter);
2984 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2985 }
4f51bf70 2986 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2987 break;
2988 default:
2989 break;
2990 }
e8e26350 2991
0befdb3e 2992 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2993 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2994 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 2995
b9f6ed2b 2996 /* would disable interrupts here but EIAM disabled it */
ef2662b2 2997 napi_schedule_irqoff(&q_vector->napi);
9a799d71 2998
6af3b9eb
ET		 2999 /*
3000 * re-enable link(maybe) and non-queue interrupts, no flush.
3001 * ixgbe_poll will re-enable the queue interrupts
3002 */
6af3b9eb
ET		 3003 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3004 ixgbe_irq_enable(adapter, false, false);
3005
9a799d71
AK		 3006 return IRQ_HANDLED;
3007}
3008
3009/**
3010 * ixgbe_request_irq - initialize interrupts
3011 * @adapter: board private structure
3012 *
3013 * Attempts to configure interrupts using the best available
3014 * capabilities of the hardware and kernel.
3015 **/
021230d4 3016static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 3017{
3018 struct net_device *netdev = adapter->netdev;
021230d4 3019 int err;
9a799d71 3020
4cc6df29 3021 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 3022 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 3023 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 3024 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 3025 netdev->name, adapter);
4cc6df29 3026 else
a0607fd3 3027 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 3028 netdev->name, adapter);
9a799d71 3029
de88eeeb 3030 if (err)
396e799c 3031 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 3032
9a799d71
AK		 3033 return err;
3034}
3035
3036static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3037{
49c7ffbe 3038 int vector;
9a799d71 3039
49c7ffbe
AD		 3040 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3041 free_irq(adapter->pdev->irq, adapter);
3042 return;
3043 }
4cc6df29 3044
49c7ffbe
AD		 3045 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3046 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3047 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3048
49c7ffbe
AD		 3049 /* free only the irqs that were actually requested */
3050 if (!q_vector->rx.ring && !q_vector->tx.ring)
3051 continue;
207867f5 3052
49c7ffbe
AD		 3053 /* clear the affinity_mask in the IRQ descriptor */
3054 irq_set_affinity_hint(entry->vector, NULL);
3055
3056 free_irq(entry->vector, q_vector);
9a799d71 3057 }
49c7ffbe
AD		 3058
3059 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3060}
3061
22d5a71b
JB		 3062/**
3063 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3064 * @adapter: board private structure
3065 **/
3066static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3067{
bd508178
AD		 3068 switch (adapter->hw.mac.type) {
3069 case ixgbe_mac_82598EB:
835462fc 3070 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3071 break;
3072 case ixgbe_mac_82599EB:
b93a2226 3073 case ixgbe_mac_X540:
9a75a1ac
DS		 3074 case ixgbe_mac_X550:
3075 case ixgbe_mac_X550EM_x:
49425dfc 3076 case ixgbe_mac_x550em_a:
835462fc
NS		 3077 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3078 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3079 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3080 break;
3081 default:
3082 break;
22d5a71b
JB		 3083 }
3084 IXGBE_WRITE_FLUSH(&adapter->hw);
3085 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3086 int vector;
3087
3088 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3089 synchronize_irq(adapter->msix_entries[vector].vector);
3090
3091 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3092 } else {
3093 synchronize_irq(adapter->pdev->irq);
3094 }
3095}
3096
9a799d71
AK		 3097/**
3098 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3099 *
3100 **/
3101static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3102{
d5bf4f67 3103 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3104
d5bf4f67 3105 ixgbe_write_eitr(q_vector);
9a799d71 3106
e8e26350
PW		 3107 ixgbe_set_ivar(adapter, 0, 0, 0);
3108 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3109
396e799c 3110 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3111}
3112
43e69bf0
AD		 3113/**
3114 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3115 * @adapter: board private structure
3116 * @ring: structure containing ring specific data
3117 *
3118 * Configure the Tx descriptor ring after a reset.
3119 **/
84418e3b
AD		 3120void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3121 struct ixgbe_ring *ring)
43e69bf0
AD		 3122{
3123 struct ixgbe_hw *hw = &adapter->hw;
3124 u64 tdba = ring->dma;
2f1860b8 3125 int wait_loop = 10;
b88c6de2 3126 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3127 u8 reg_idx = ring->reg_idx;
43e69bf0 3128
2f1860b8 3129 /* disable queue to avoid issues while updating state */
b88c6de2 3130 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3131 IXGBE_WRITE_FLUSH(hw);
3132
43e69bf0 3133 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3134 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3135 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3136 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3137 ring->count * sizeof(union ixgbe_adv_tx_desc));
3138 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3139 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3140 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3141
b88c6de2
AD		 3142 /*
3143 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3144 * higher than 1 when:
3145 * - ITR is 0 as it could cause false TX hangs
3146 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3147 *
3148 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3149 * to or less than the number of on chip descriptors, which is
3150 * currently 40.
3151 */
67da097e 3152 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3153 txdctl |= (1 << 16); /* WTHRESH = 1 */
3154 else
3155 txdctl |= (8 << 16); /* WTHRESH = 8 */
3156
e954b374
AD		 3157 /*
3158 * Setting PTHRESH to 32 both improves performance
3159 * and avoids a TX hang with DFP enabled
3160 */
b88c6de2
AD		 3161 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3162 32; /* PTHRESH = 32 */
2f1860b8
AD		 3163
3164 /* reinitialize flowdirector state */
39cb681b 3165 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3166 ring->atr_sample_rate = adapter->atr_sample_rate;
3167 ring->atr_count = 0;
3168 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3169 } else {
3170 ring->atr_sample_rate = 0;
3171 }
2f1860b8 3172
fd786b7b
AD		 3173 /* initialize XPS */
3174 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3175 struct ixgbe_q_vector *q_vector = ring->q_vector;
3176
3177 if (q_vector)
2a47fa45 3178 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3179 &q_vector->affinity_mask,
3180 ring->queue_index);
3181 }
3182
c84d324c
JF		 3183 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3184
2f1860b8 3185 /* enable queue */
2f1860b8
AD		 3186 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3187
3188 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3189 if (hw->mac.type == ixgbe_mac_82598EB &&
3190 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3191 return;
3192
3193 /* poll to verify queue is enabled */
3194 do {
032b4325 3195 usleep_range(1000, 2000);
2f1860b8
AD		 3196 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3197 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3198 if (!wait_loop)
3199 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3200}
3201
120ff942
AD		 3202static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3203{
3204 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3205 u32 rttdcs, mtqc;
8b1c0b24 3206 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3207
3208 if (hw->mac.type == ixgbe_mac_82598EB)
3209 return;
3210
3211 /* disable the arbiter while setting MTQC */
3212 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3213 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3214 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3215
3216 /* set transmit pool layout */
671c0adb
AD		 3217 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3218 mtqc = IXGBE_MTQC_VT_ENA;
3219 if (tcs > 4)
3220 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3221 else if (tcs > 1)
3222 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3223 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3224 mtqc |= IXGBE_MTQC_32VF;
3225 else
3226 mtqc |= IXGBE_MTQC_64VF;
3227 } else {
3228 if (tcs > 4)
3229 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3230 else if (tcs > 1)
3231 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3232 else
671c0adb
AD		 3233 mtqc = IXGBE_MTQC_64Q_1PB;
3234 }
120ff942 3235
671c0adb 3236 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3237
671c0adb
AD		 3238 /* Enable Security TX Buffer IFG for multiple pb */
3239 if (tcs) {
3240 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3241 sectx |= IXGBE_SECTX_DCB;
3242 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3243 }
3244
3245 /* re-enable the arbiter */
3246 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3247 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3248}
3249
9a799d71 3250/**
3a581073 3251 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3252 * @adapter: board private structure
3253 *
3254 * Configure the Tx unit of the MAC after a reset.
3255 **/
3256static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3257{
2f1860b8
AD		 3258 struct ixgbe_hw *hw = &adapter->hw;
3259 u32 dmatxctl;
43e69bf0 3260 u32 i;
9a799d71 3261
2f1860b8
AD		 3262 ixgbe_setup_mtqc(adapter);
3263
3264 if (hw->mac.type != ixgbe_mac_82598EB) {
3265 /* DMATXCTL.EN must be before Tx queues are enabled */
3266 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3267 dmatxctl |= IXGBE_DMATXCTL_TE;
3268 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3269 }
3270
9a799d71 3271 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3272 for (i = 0; i < adapter->num_tx_queues; i++)
3273 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3274}
3275
3ebe8fde
AD		 3276static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3277 struct ixgbe_ring *ring)
3278{
3279 struct ixgbe_hw *hw = &adapter->hw;
3280 u8 reg_idx = ring->reg_idx;
3281 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3282
3283 srrctl |= IXGBE_SRRCTL_DROP_EN;
3284
3285 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3286}
3287
3288static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3289 struct ixgbe_ring *ring)
3290{
3291 struct ixgbe_hw *hw = &adapter->hw;
3292 u8 reg_idx = ring->reg_idx;
3293 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3294
3295 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3296
3297 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3298}
3299
3300#ifdef CONFIG_IXGBE_DCB
3301void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3302#else
3303static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3304#endif
3305{
3306 int i;
3307 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3308
3309 if (adapter->ixgbe_ieee_pfc)
3310 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3311
3312 /*
3313 * We should set the drop enable bit if:
3314 * SR-IOV is enabled
3315 * or
3316 * Number of Rx queues > 1 and flow control is disabled
3317 *
3318 * This allows us to avoid head of line blocking for security
3319 * and performance reasons.
3320 */
3321 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3322 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3323 for (i = 0; i < adapter->num_rx_queues; i++)
3324 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3325 } else {
3326 for (i = 0; i < adapter->num_rx_queues; i++)
3327 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3328 }
3329}
3330
e8e26350 3331#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3332
a6616b42 3333static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3334 struct ixgbe_ring *rx_ring)
cc41ac7c 3335{
45e9baa5 3336 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3337 u32 srrctl;
bf29ee6c 3338 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3339
45e9baa5
AD		 3340 if (hw->mac.type == ixgbe_mac_82598EB) {
3341 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3342
45e9baa5
AD		 3343 /*
3344 * if VMDq is not active we must program one srrctl register
3345 * per RSS queue since we have enabled RDRXCTL.MVMEN
3346 */
3347 reg_idx &= mask;
3348 }
cc41ac7c 3349
45e9baa5
AD		 3350 /* configure header buffer length, needed for RSC */
3351 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3352
45e9baa5 3353 /* configure the packet buffer length */
f800326d 3354 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3355
3356 /* configure descriptor type */
f800326d 3357 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3358
45e9baa5 3359 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3360}
9a799d71 3361
dfaf891d 3362/**
a897a2ad 3363 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3364 * @adapter: device handle
3365 *
3366 * - 82598/82599/X540: 128
3367 * - X550(non-SRIOV mode): 512
3368 * - X550(SRIOV mode): 64
3369 */
7f276efb 3370u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3371{
3372 if (adapter->hw.mac.type < ixgbe_mac_X550)
3373 return 128;
3374 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3375 return 64;
3376 else
3377 return 512;
3378}
3379
3380/**
a897a2ad 3381 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3382 * @adapter: device handle
3383 *
3384 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3385 */
1c7cf078 3386void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3387{
dfaf891d 3388 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3389 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3390 u32 reta = 0;
dfaf891d
VZ		 3391 u32 indices_multi;
3392 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3393
0f9b232b 3394 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3395 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3396 * indices.
3397 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3398 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3399 */
3400 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3401 indices_multi = 0x11;
3402 else
3403 indices_multi = 0x1;
3404
dfaf891d
VZ		 3405 /* Write redirection table to HW */
3406 for (i = 0; i < reta_entries; i++) {
3407 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3408 if ((i & 3) == 3) {
3409 if (i < 128)
3410 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3411 else
3412 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3413 reta);
dfaf891d 3414 reta = 0;
0f9b232b
DS		 3415 }
3416 }
3417}
3418
dfaf891d 3419/**
a897a2ad 3420 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3421 * @adapter: device handle
3422 *
3423 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3424 */
3425static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3426{
dfaf891d 3427 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3428 struct ixgbe_hw *hw = &adapter->hw;
3429 u32 vfreta = 0;
dfaf891d
VZ		 3430 unsigned int pf_pool = adapter->num_vfs;
3431
3432 /* Write redirection table to HW */
3433 for (i = 0; i < reta_entries; i++) {
3434 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3435 if ((i & 3) == 3) {
3436 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3437 vfreta);
3438 vfreta = 0;
3439 }
3440 }
3441}
3442
3443static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3444{
3445 struct ixgbe_hw *hw = &adapter->hw;
3446 u32 i, j;
3447 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3448 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3449
3450 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3451 * make full use of any rings they may have. We will use the
3452 * PSRTYPE register to control how many rings we use within the PF.
3453 */
3454 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3455 rss_i = 2;
3456
3457 /* Fill out hash function seeds */
3458 for (i = 0; i < 10; i++)
3459 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3460
3461 /* Fill out redirection table */
3462 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3463
3464 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3465 if (j == rss_i)
3466 j = 0;
3467
3468 adapter->rss_indir_tbl[i] = j;
3469 }
3470
3471 ixgbe_store_reta(adapter);
3472}
3473
3474static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3475{
3476 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3477 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3478 unsigned int pf_pool = adapter->num_vfs;
3479 int i, j;
3480
3481 /* Fill out hash function seeds */
3482 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3483 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3484 adapter->rss_key[i]);
0f9b232b
DS		 3485
3486 /* Fill out the redirection table */
3487 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3488 if (j == rss_i)
05abb126 3489 j = 0;
dfaf891d
VZ		 3490
3491 adapter->rss_indir_tbl[i] = j;
05abb126 3492 }
dfaf891d
VZ		 3493
3494 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3495}
3496
3497static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3498{
3499 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3500 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3501 u32 rxcsum;
0cefafad 3502
05abb126
AD		 3503 /* Disable indicating checksum in descriptor, enables RSS hash */
3504 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3505 rxcsum |= IXGBE_RXCSUM_PCSD;
3506 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3507
671c0adb 3508 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3509 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3510 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3511 } else {
671c0adb
AD		 3512 u8 tcs = netdev_get_num_tc(adapter->netdev);
3513
3514 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3515 if (tcs > 4)
3516 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3517 else if (tcs > 1)
3518 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3519 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3520 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3521 else
671c0adb
AD		 3522 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3523 } else {
3524 if (tcs > 4)
8b1c0b24 3525 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3526 else if (tcs > 1)
3527 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3528 else
3529 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3530 }
0cefafad
JB		 3531 }
3532
05abb126 3533 /* Perform hash on these packet types */
d1b849b9
DS		 3534 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3535 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3536 IXGBE_MRQC_RSS_FIELD_IPV6 |
3537 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3538
ef6afc0c 3539 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3540 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3541 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3542 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3543
dfaf891d 3544 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3545 if ((hw->mac.type >= ixgbe_mac_X550) &&
3546 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3547 unsigned int pf_pool = adapter->num_vfs;
3548
3549 /* Enable VF RSS mode */
3550 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3551 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3552
3553 /* Setup RSS through the VF registers */
dfaf891d 3554 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3555 vfmrqc = IXGBE_MRQC_RSSEN;
3556 vfmrqc |= rss_field;
3557 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3558 } else {
dfaf891d 3559 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3560 mrqc |= rss_field;
3561 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3562 }
0cefafad
JB		 3563}
3564
bb5a9ad2
NS		 3565/**
3566 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3567 * @adapter: address of board private structure
3568 * @index: index of ring to set
bb5a9ad2 3569 **/
082757af 3570static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3571 struct ixgbe_ring *ring)
bb5a9ad2 3572{
bb5a9ad2 3573 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3574 u32 rscctrl;
bf29ee6c 3575 u8 reg_idx = ring->reg_idx;
7367096a 3576
7d637bcc 3577 if (!ring_is_rsc_enabled(ring))
7367096a 3578 return;
bb5a9ad2 3579
7367096a 3580 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3581 rscctrl |= IXGBE_RSCCTL_RSCEN;
3582 /*
3583 * we must limit the number of descriptors so that the
3584 * total size of max desc * buf_len is not greater
642c680e 3585 * than 65536
bb5a9ad2 3586 */
f800326d 3587 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3588 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3589}
3590
9e10e045
AD		 3591#define IXGBE_MAX_RX_DESC_POLL 10
3592static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3593 struct ixgbe_ring *ring)
3594{
3595 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3596 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3597 u32 rxdctl;
bf29ee6c 3598 u8 reg_idx = ring->reg_idx;
9e10e045 3599
b0483c8f
MR		 3600 if (ixgbe_removed(hw->hw_addr))
3601 return;
9e10e045
AD		 3602 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3603 if (hw->mac.type == ixgbe_mac_82598EB &&
3604 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3605 return;
3606
3607 do {
032b4325 3608 usleep_range(1000, 2000);
9e10e045
AD		 3609 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3610 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3611
3612 if (!wait_loop) {
3613 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3614 "the polling period\n", reg_idx);
3615 }
3616}
3617
2d39d576
YZ		 3618void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3619 struct ixgbe_ring *ring)
3620{
3621 struct ixgbe_hw *hw = &adapter->hw;
3622 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3623 u32 rxdctl;
3624 u8 reg_idx = ring->reg_idx;
3625
b0483c8f
MR		 3626 if (ixgbe_removed(hw->hw_addr))
3627 return;
2d39d576
YZ		 3628 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3629 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3630
3631 /* write value back with RXDCTL.ENABLE bit cleared */
3632 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3633
3634 if (hw->mac.type == ixgbe_mac_82598EB &&
3635 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3636 return;
3637
3638 /* the hardware may take up to 100us to really disable the rx queue */
3639 do {
3640 udelay(10);
3641 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3642 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3643
3644 if (!wait_loop) {
3645 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3646 "the polling period\n", reg_idx);
3647 }
3648}
3649
84418e3b
AD		 3650void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3651 struct ixgbe_ring *ring)
acd37177
AD		 3652{
3653 struct ixgbe_hw *hw = &adapter->hw;
3654 u64 rdba = ring->dma;
9e10e045 3655 u32 rxdctl;
bf29ee6c 3656 u8 reg_idx = ring->reg_idx;
acd37177 3657
9e10e045
AD		 3658 /* disable queue to avoid issues while updating state */
3659 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3660 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3661
acd37177
AD		 3662 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3663 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3664 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3665 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3666 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3667 IXGBE_WRITE_FLUSH(hw);
3668
acd37177
AD		 3669 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3670 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3671 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3672
3673 ixgbe_configure_srrctl(adapter, ring);
3674 ixgbe_configure_rscctl(adapter, ring);
3675
3676 if (hw->mac.type == ixgbe_mac_82598EB) {
3677 /*
3678 * enable cache line friendly hardware writes:
3679 * PTHRESH=32 descriptors (half the internal cache),
3680 * this also removes ugly rx_no_buffer_count increment
3681 * HTHRESH=4 descriptors (to minimize latency on fetch)
3682 * WTHRESH=8 burst writeback up to two cache lines
3683 */
3684 rxdctl &= ~0x3FFFFF;
3685 rxdctl |= 0x080420;
3686 }
3687
3688 /* enable receive descriptor ring */
3689 rxdctl |= IXGBE_RXDCTL_ENABLE;
3690 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3691
3692 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3693 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3694}
3695
48654521
AD		 3696static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3697{
3698 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3699 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3700 u16 pool;
48654521
AD		 3701
3702 /* PSRTYPE must be initialized in non 82598 adapters */
3703 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3704 IXGBE_PSRTYPE_UDPHDR |
3705 IXGBE_PSRTYPE_IPV4HDR |
48654521 3706 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3707 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3708
3709 if (hw->mac.type == ixgbe_mac_82598EB)
3710 return;
3711
fbe7ca7f
AD		 3712 if (rss_i > 3)
3713 psrtype |= 2 << 29;
3714 else if (rss_i > 1)
3715 psrtype |= 1 << 29;
48654521 3716
2a47fa45
JF		 3717 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3718 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3719}
3720
f5b4a52e
AD		 3721static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3722{
3723 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3724 u32 reg_offset, vf_shift;
435b19f6 3725 u32 gcr_ext, vmdctl;
de4c7f65 3726 int i;
f5b4a52e
AD		 3727
3728 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3729 return;
3730
3731 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3732 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3733 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3734 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3735 vmdctl |= IXGBE_VT_CTL_REPLEN;
3736 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3737
1d9c0bfd
AD		 3738 vf_shift = VMDQ_P(0) % 32;
3739 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3740
3741 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3742 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3743 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3744 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3745 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3746 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3747 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3748
3749 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3750 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3751
16369564
AD		 3752 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3753 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3754
f5b4a52e
AD		 3755 /*
3756 * Set up VF register offsets for selected VT Mode,
3757 * i.e. 32 or 64 VFs for SR-IOV
3758 */
73079ea0
AD		 3759 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3760 case IXGBE_82599_VMDQ_8Q_MASK:
3761 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3762 break;
3763 case IXGBE_82599_VMDQ_4Q_MASK:
3764 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3765 break;
3766 default:
3767 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3768 break;
3769 }
3770
f5b4a52e
AD		 3771 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3772
435b19f6 3773
a985b6c3 3774 /* Enable MAC Anti-Spoofing */
435b19f6 3775 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3776 adapter->num_vfs);
5b7f000f 3777
f079fa00 3778 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
5b7f000f
DS		 3779 * calling set_ethertype_anti_spoofing for each VF in loop below
3780 */
f079fa00 3781 if (hw->mac.ops.set_ethertype_anti_spoofing) {
5b7f000f 3782 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
f079fa00
ET		 3783 (IXGBE_ETQF_FILTER_EN |
3784 IXGBE_ETQF_TX_ANTISPOOF |
3785 IXGBE_ETH_P_LLDP));
3786
3787 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3788 (IXGBE_ETQF_FILTER_EN |
3789 IXGBE_ETQF_TX_ANTISPOOF |
3790 ETH_P_PAUSE));
3791 }
5b7f000f 3792
de4c7f65
GR		 3793 /* For VFs that have spoof checking turned off */
3794 for (i = 0; i < adapter->num_vfs; i++) {
3795 if (!adapter->vfinfo[i].spoofchk_enabled)
3796 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3797
3798 /* enable ethertype anti spoofing if hw supports it */
3799 if (hw->mac.ops.set_ethertype_anti_spoofing)
3800 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3801
3802 /* Enable/Disable RSS query feature */
3803 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3804 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3805 }
f5b4a52e
AD		 3806}
3807
477de6ed 3808static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3809{
9a799d71
AK		 3810 struct ixgbe_hw *hw = &adapter->hw;
3811 struct net_device *netdev = adapter->netdev;
3812 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3813 struct ixgbe_ring *rx_ring;
3814 int i;
3815 u32 mhadd, hlreg0;
48654521 3816
63f39bd1 3817#ifdef IXGBE_FCOE
477de6ed
AD		 3818 /* adjust max frame to be able to do baby jumbo for FCoE */
3819 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3820 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3821 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3822
477de6ed 3823#endif /* IXGBE_FCOE */
872844dd
AD		 3824
3825 /* adjust max frame to be at least the size of a standard frame */
3826 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3827 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3828
477de6ed
AD		 3829 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3830 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3831 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3832 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3833
3834 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3835 }
3836
3837 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3838 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3839 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3840 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3841
0cefafad
JB		 3842 /*
3843 * Setup the HW Rx Head and Tail Descriptor Pointers and
3844 * the Base and Length of the Rx Descriptor Ring
3845 */
9a799d71 3846 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3847 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3848 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3849 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3850 else
7d637bcc 3851 clear_ring_rsc_enabled(rx_ring);
477de6ed 3852 }
477de6ed
AD		 3853}
3854
7367096a
AD		 3855static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3856{
3857 struct ixgbe_hw *hw = &adapter->hw;
3858 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3859
3860 switch (hw->mac.type) {
3861 case ixgbe_mac_82598EB:
3862 /*
3863 * For VMDq support of different descriptor types or
3864 * buffer sizes through the use of multiple SRRCTL
3865 * registers, RDRXCTL.MVMEN must be set to 1
3866 *
3867 * also, the manual doesn't mention it clearly but DCA hints
3868 * will only use queue 0's tags unless this bit is set. Side
3869 * effects of setting this bit are only that SRRCTL must be
3870 * fully programmed [0..15]
3871 */
3872 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3873 break;
052a1a72
MR		 3874 case ixgbe_mac_X550:
3875 case ixgbe_mac_X550EM_x:
49425dfc 3876 case ixgbe_mac_x550em_a:
f961ddae
MR		 3877 if (adapter->num_vfs)
3878 rdrxctl |= IXGBE_RDRXCTL_PSP;
3879 /* fall through for older HW */
7367096a 3880 case ixgbe_mac_82599EB:
b93a2226 3881 case ixgbe_mac_X540:
7367096a
AD		 3882 /* Disable RSC for ACK packets */
3883 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3884 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3885 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3886 /* hardware requires some bits to be set by default */
3887 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3888 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3889 break;
3890 default:
3891 /* We should do nothing since we don't know this hardware */
3892 return;
3893 }
3894
3895 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3896}
3897
477de6ed
AD		 3898/**
3899 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3900 * @adapter: board private structure
3901 *
3902 * Configure the Rx unit of the MAC after a reset.
3903 **/
3904static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3905{
3906 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3907 int i;
6dcc28b9 3908 u32 rxctrl, rfctl;
477de6ed
AD		 3909
3910 /* disable receives while setting up the descriptors */
1f9ac57c 3911 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3912
3913 ixgbe_setup_psrtype(adapter);
7367096a 3914 ixgbe_setup_rdrxctl(adapter);
477de6ed 3915
6dcc28b9
JK		 3916 /* RSC Setup */
3917 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3918 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3919 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3920 rfctl |= IXGBE_RFCTL_RSC_DIS;
3921 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3922
9e10e045 3923 /* Program registers for the distribution of queues */
f5b4a52e 3924 ixgbe_setup_mrqc(adapter);
f5b4a52e 3925
477de6ed
AD		 3926 /* set_rx_buffer_len must be called before ring initialization */
3927 ixgbe_set_rx_buffer_len(adapter);
3928
3929 /*
3930 * Setup the HW Rx Head and Tail Descriptor Pointers and
3931 * the Base and Length of the Rx Descriptor Ring
3932 */
9e10e045
AD		 3933 for (i = 0; i < adapter->num_rx_queues; i++)
3934 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3935
1f9ac57c 3936 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3937 /* disable drop enable for 82598 parts */
3938 if (hw->mac.type == ixgbe_mac_82598EB)
3939 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3940
3941 /* enable all receives */
3942 rxctrl |= IXGBE_RXCTRL_RXEN;
3943 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3944}
3945
80d5c368
PM		 3946static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3947 __be16 proto, u16 vid)
068c89b0
DS		 3948{
3949 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3950 struct ixgbe_hw *hw = &adapter->hw;
3951
3952 /* add VID to filter table */
18be4fce
AD		 3953 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3954 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
3955
f62bbb5e 3956 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3957
3958 return 0;
068c89b0
DS		 3959}
3960
e1d0a2af
AD		 3961static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3962{
3963 u32 vlvf;
3964 int idx;
3965
3966 /* short cut the special case */
3967 if (vlan == 0)
3968 return 0;
3969
3970 /* Search for the vlan id in the VLVF entries */
3971 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3972 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3973 if ((vlvf & VLAN_VID_MASK) == vlan)
3974 break;
3975 }
3976
3977 return idx;
3978}
3979
3980void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3981{
3982 struct ixgbe_hw *hw = &adapter->hw;
3983 u32 bits, word;
3984 int idx;
3985
3986 idx = ixgbe_find_vlvf_entry(hw, vid);
3987 if (!idx)
3988 return;
3989
3990 /* See if any other pools are set for this VLAN filter
3991 * entry other than the PF.
3992 */
3993 word = idx * 2 + (VMDQ_P(0) / 32);
3994 bits = ~(1 << (VMDQ_P(0)) % 32);
3995 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3996
3997 /* Disable the filter so this falls into the default pool. */
3998 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
3999 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4000 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4001 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4002 }
4003}
4004
80d5c368
PM		 4005static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4006 __be16 proto, u16 vid)
068c89b0
DS		 4007{
4008 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4009 struct ixgbe_hw *hw = &adapter->hw;
4010
068c89b0 4011 /* remove VID from filter table */
18be4fce 4012 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
e1d0a2af
AD		 4013 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4014
f62bbb5e 4015 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 4016
4017 return 0;
068c89b0
DS		 4018}
4019
f62bbb5e
JG		 4020/**
4021 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4022 * @adapter: driver data
4023 */
4024static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4025{
4026 struct ixgbe_hw *hw = &adapter->hw;
4027 u32 vlnctrl;
5f6c0181
JB		 4028 int i, j;
4029
4030 switch (hw->mac.type) {
4031 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4032 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4033 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4034 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4035 break;
4036 case ixgbe_mac_82599EB:
b93a2226 4037 case ixgbe_mac_X540:
9a75a1ac
DS		 4038 case ixgbe_mac_X550:
4039 case ixgbe_mac_X550EM_x:
49425dfc 4040 case ixgbe_mac_x550em_a:
5f6c0181 4041 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4042 struct ixgbe_ring *ring = adapter->rx_ring[i];
4043
4044 if (ring->l2_accel_priv)
4045 continue;
4046 j = ring->reg_idx;
5f6c0181
JB		 4047 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4048 vlnctrl &= ~IXGBE_RXDCTL_VME;
4049 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4050 }
4051 break;
4052 default:
4053 break;
4054 }
4055}
4056
4057/**
f62bbb5e 4058 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4059 * @adapter: driver data
4060 */
f62bbb5e 4061static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4062{
4063 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4064 u32 vlnctrl;
5f6c0181
JB		 4065 int i, j;
4066
4067 switch (hw->mac.type) {
4068 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4069 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4070 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4071 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4072 break;
4073 case ixgbe_mac_82599EB:
b93a2226 4074 case ixgbe_mac_X540:
9a75a1ac
DS		 4075 case ixgbe_mac_X550:
4076 case ixgbe_mac_X550EM_x:
49425dfc 4077 case ixgbe_mac_x550em_a:
5f6c0181 4078 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4079 struct ixgbe_ring *ring = adapter->rx_ring[i];
4080
4081 if (ring->l2_accel_priv)
4082 continue;
4083 j = ring->reg_idx;
5f6c0181
JB		 4084 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4085 vlnctrl |= IXGBE_RXDCTL_VME;
4086 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4087 }
4088 break;
4089 default:
4090 break;
4091 }
4092}
4093
16369564
AD		 4094static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4095{
4096 struct ixgbe_hw *hw = &adapter->hw;
4097 u32 vlnctrl, i;
4098
4099 switch (hw->mac.type) {
4100 case ixgbe_mac_82599EB:
4101 case ixgbe_mac_X540:
4102 case ixgbe_mac_X550:
4103 case ixgbe_mac_X550EM_x:
49425dfc 4104 case ixgbe_mac_x550em_a:
16369564
AD		 4105 default:
4106 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4107 break;
4108 /* fall through */
4109 case ixgbe_mac_82598EB:
4110 /* legacy case, we can just disable VLAN filtering */
4111 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4112 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4113 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4114 return;
4115 }
4116
4117 /* We are already in VLAN promisc, nothing to do */
4118 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4119 return;
4120
4121 /* Set flag so we don't redo unnecessary work */
4122 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4123
4124 /* Add PF to all active pools */
4125 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4126 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4127 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4128
4129 vlvfb |= 1 << (VMDQ_P(0) % 32);
4130 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4131 }
4132
4133 /* Set all bits in the VLAN filter table array */
4134 for (i = hw->mac.vft_size; i--;)
4135 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4136}
4137
4138#define VFTA_BLOCK_SIZE 8
4139static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4140{
4141 struct ixgbe_hw *hw = &adapter->hw;
4142 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4143 u32 vid_start = vfta_offset * 32;
4144 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4145 u32 i, vid, word, bits;
4146
4147 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4148 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4149
4150 /* pull VLAN ID from VLVF */
4151 vid = vlvf & VLAN_VID_MASK;
4152
4153 /* only concern outselves with a certain range */
4154 if (vid < vid_start || vid >= vid_end)
4155 continue;
4156
4157 if (vlvf) {
4158 /* record VLAN ID in VFTA */
4159 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4160
4161 /* if PF is part of this then continue */
4162 if (test_bit(vid, adapter->active_vlans))
4163 continue;
4164 }
4165
4166 /* remove PF from the pool */
4167 word = i * 2 + VMDQ_P(0) / 32;
4168 bits = ~(1 << (VMDQ_P(0) % 32));
4169 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4170 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4171 }
4172
4173 /* extract values from active_vlans and write back to VFTA */
4174 for (i = VFTA_BLOCK_SIZE; i--;) {
4175 vid = (vfta_offset + i) * 32;
4176 word = vid / BITS_PER_LONG;
4177 bits = vid % BITS_PER_LONG;
4178
4179 vfta[i] |= adapter->active_vlans[word] >> bits;
4180
4181 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4182 }
4183}
4184
4185static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4186{
4187 struct ixgbe_hw *hw = &adapter->hw;
4188 u32 vlnctrl, i;
4189
4190 switch (hw->mac.type) {
4191 case ixgbe_mac_82599EB:
4192 case ixgbe_mac_X540:
4193 case ixgbe_mac_X550:
4194 case ixgbe_mac_X550EM_x:
49425dfc 4195 case ixgbe_mac_x550em_a:
16369564
AD		 4196 default:
4197 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4198 break;
4199 /* fall through */
4200 case ixgbe_mac_82598EB:
4201 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4202 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4203 vlnctrl |= IXGBE_VLNCTRL_VFE;
4204 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4205 return;
4206 }
4207
4208 /* We are not in VLAN promisc, nothing to do */
4209 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4210 return;
4211
4212 /* Set flag so we don't redo unnecessary work */
4213 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4214
4215 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4216 ixgbe_scrub_vfta(adapter, i);
4217}
4218
9a799d71
AK		 4219static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4220{
06bb1c39 4221 u16 vid = 1;
9a799d71 4222
80d5c368 4223 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e 4224
06bb1c39 4225 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4226 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4227}
4228
b335e75b
JK		 4229/**
4230 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4231 * @netdev: network interface device structure
4232 *
4233 * Writes multicast address list to the MTA hash table.
4234 * Returns: -ENOMEM on failure
4235 * 0 on no addresses written
4236 * X on writing X addresses to MTA
4237 **/
4238static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4239{
4240 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4241 struct ixgbe_hw *hw = &adapter->hw;
4242
4243 if (!netif_running(netdev))
4244 return 0;
4245
4246 if (hw->mac.ops.update_mc_addr_list)
4247 hw->mac.ops.update_mc_addr_list(hw, netdev);
4248 else
4249 return -ENOMEM;
4250
4251#ifdef CONFIG_PCI_IOV
5d7daa35 4252 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4253#endif
4254
4255 return netdev_mc_count(netdev);
4256}
4257
5d7daa35
JK		 4258#ifdef CONFIG_PCI_IOV
4259void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4260{
c9f53e63 4261 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4262 struct ixgbe_hw *hw = &adapter->hw;
4263 int i;
c9f53e63
AD		 4264
4265 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4266 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4267
4268 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4269 hw->mac.ops.set_rar(hw, i,
4270 mac_table->addr,
4271 mac_table->pool,
5d7daa35
JK		 4272 IXGBE_RAH_AV);
4273 else
4274 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4275 }
4276}
5d7daa35 4277
c9f53e63 4278#endif
5d7daa35
JK		 4279static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4280{
c9f53e63 4281 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4282 struct ixgbe_hw *hw = &adapter->hw;
4283 int i;
5d7daa35 4284
c9f53e63
AD		 4285 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4286 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4287 continue;
4288
4289 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4290
4291 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4292 hw->mac.ops.set_rar(hw, i,
4293 mac_table->addr,
4294 mac_table->pool,
4295 IXGBE_RAH_AV);
4296 else
4297 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4298 }
4299}
4300
4301static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4302{
c9f53e63 4303 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4304 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4305 int i;
5d7daa35 4306
c9f53e63
AD		 4307 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4308 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4309 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4310 }
c9f53e63 4311
5d7daa35
JK		 4312 ixgbe_sync_mac_table(adapter);
4313}
4314
c9f53e63 4315static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4316{
c9f53e63 4317 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4318 struct ixgbe_hw *hw = &adapter->hw;
4319 int i, count = 0;
4320
c9f53e63
AD		 4321 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4322 /* do not count default RAR as available */
4323 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4324 continue;
4325
4326 /* only count unused and addresses that belong to us */
4327 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4328 if (mac_table->pool != pool)
4329 continue;
4330 }
4331
4332 count++;
5d7daa35 4333 }
c9f53e63 4334
5d7daa35
JK		 4335 return count;
4336}
4337
4338/* this function destroys the first RAR entry */
c9f53e63 4339static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4340{
c9f53e63 4341 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4342 struct ixgbe_hw *hw = &adapter->hw;
4343
c9f53e63
AD		 4344 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4345 mac_table->pool = VMDQ_P(0);
4346
4347 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4348
4349 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4350 IXGBE_RAH_AV);
4351}
4352
c9f53e63
AD		 4353int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4354 const u8 *addr, u16 pool)
5d7daa35 4355{
c9f53e63 4356 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4357 struct ixgbe_hw *hw = &adapter->hw;
4358 int i;
4359
4360 if (is_zero_ether_addr(addr))
4361 return -EINVAL;
4362
c9f53e63
AD		 4363 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4364 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4365 continue;
c9f53e63
AD		 4366
4367 ether_addr_copy(mac_table->addr, addr);
4368 mac_table->pool = pool;
4369
4370 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4371 IXGBE_MAC_STATE_IN_USE;
4372
5d7daa35 4373 ixgbe_sync_mac_table(adapter);
c9f53e63 4374
5d7daa35
JK		 4375 return i;
4376 }
c9f53e63 4377
5d7daa35
JK		 4378 return -ENOMEM;
4379}
4380
c9f53e63
AD		 4381int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4382 const u8 *addr, u16 pool)
5d7daa35 4383{
c9f53e63 4384 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4385 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4386 int i;
5d7daa35
JK		 4387
4388 if (is_zero_ether_addr(addr))
4389 return -EINVAL;
4390
c9f53e63
AD		 4391 /* search table for addr, if found clear IN_USE flag and sync */
4392 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4393 /* we can only delete an entry if it is in use */
4394 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4395 continue;
4396 /* we only care about entries that belong to the given pool */
4397 if (mac_table->pool != pool)
4398 continue;
4399 /* we only care about a specific MAC address */
4400 if (!ether_addr_equal(addr, mac_table->addr))
4401 continue;
4402
4403 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4404 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4405
4406 ixgbe_sync_mac_table(adapter);
4407
4408 return 0;
5d7daa35 4409 }
c9f53e63 4410
5d7daa35
JK		 4411 return -ENOMEM;
4412}
2850062a
AD		 4413/**
4414 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4415 * @netdev: network interface device structure
4416 *
4417 * Writes unicast address list to the RAR table.
4418 * Returns: -ENOMEM on failure/insufficient address space
4419 * 0 on no addresses written
4420 * X on writing X addresses to the RAR table
4421 **/
5d7daa35 4422static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4423{
4424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4425 int count = 0;
4426
4427 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4428 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4429 return -ENOMEM;
4430
95447461 4431 if (!netdev_uc_empty(netdev)) {
2850062a 4432 struct netdev_hw_addr *ha;
2850062a 4433 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4434 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4435 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4436 count++;
4437 }
4438 }
2850062a
AD		 4439 return count;
4440}
4441
0f079d22
AD		 4442static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4443{
4444 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4445 int ret;
4446
4447 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4448
4449 return min_t(int, ret, 0);
4450}
4451
4452static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4453{
4454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4455
4456 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4457
4458 return 0;
4459}
4460
9a799d71 4461/**
2c5645cf 4462 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4463 * @netdev: network interface device structure
4464 *
2c5645cf
CL		 4465 * The set_rx_method entry point is called whenever the unicast/multicast
4466 * address list or the network interface flags are updated. This routine is
4467 * responsible for configuring the hardware for proper unicast, multicast and
4468 * promiscuous mode.
9a799d71 4469 **/
7f870475 4470void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4471{
4472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4473 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4474 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
0c5a6166 4475 netdev_features_t features = netdev->features;
2850062a 4476 int count;
9a799d71
AK		 4477
4478 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4479 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4480
f5dc442b 4481 /* set all bits that we expect to always be set */
3f2d1c0f 4482 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4483 fctrl |= IXGBE_FCTRL_BAM;
4484 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4485 fctrl |= IXGBE_FCTRL_PMCF;
4486
2850062a
AD		 4487 /* clear the bits we are changing the status of */
4488 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4489 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4490 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4491 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4492 vmolr |= IXGBE_VMOLR_MPE;
0c5a6166 4493 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
9a799d71 4494 } else {
746b9f02
PM		 4495 if (netdev->flags & IFF_ALLMULTI) {
4496 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4497 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4498 }
e433ea1f 4499 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4500 }
4501
4502 /*
4503 * Write addresses to available RAR registers, if there is not
4504 * sufficient space to store all the addresses then enable
4505 * unicast promiscuous mode
4506 */
0f079d22 4507 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4508 fctrl |= IXGBE_FCTRL_UPE;
4509 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4510 }
4511
cf78959c
ET		 4512 /* Write addresses to the MTA, if the attempt fails
4513 * then we should just turn on promiscuous mode so
4514 * that we can at least receive multicast traffic
4515 */
b335e75b
JK		 4516 count = ixgbe_write_mc_addr_list(netdev);
4517 if (count < 0) {
4518 fctrl |= IXGBE_FCTRL_MPE;
4519 vmolr |= IXGBE_VMOLR_MPE;
4520 } else if (count) {
4521 vmolr |= IXGBE_VMOLR_ROMPE;
4522 }
1d9c0bfd
AD		 4523
4524 if (hw->mac.type != ixgbe_mac_82598EB) {
4525 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4526 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4527 IXGBE_VMOLR_ROPE);
1d9c0bfd 4528 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4529 }
4530
3f2d1c0f 4531 /* This is useful for sniffing bad packets. */
0c5a6166 4532 if (features & NETIF_F_RXALL) {
3f2d1c0f
BG		 4533 /* UPE and MPE will be handled by normal PROMISC logic
4534 * in e1000e_set_rx_mode */
4535 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4536 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4537 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4538
4539 fctrl &= ~(IXGBE_FCTRL_DPF);
4540 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4541 }
4542
2850062a 4543 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4544
0c5a6166 4545 if (features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4546 ixgbe_vlan_strip_enable(adapter);
4547 else
4548 ixgbe_vlan_strip_disable(adapter);
0c5a6166
AD		 4549
4550 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4551 ixgbe_vlan_promisc_disable(adapter);
4552 else
4553 ixgbe_vlan_promisc_enable(adapter);
9a799d71
AK		 4554}
4555
021230d4
AV		 4556static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4557{
4558 int q_idx;
021230d4 4559
5a85e737
ET		 4560 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4561 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4562 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4563 }
021230d4
AV		 4564}
4565
4566static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4567{
4568 int q_idx;
021230d4 4569
5a85e737 4570 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4571 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4572 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4573 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4574 usleep_range(1000, 20000);
5a85e737
ET		 4575 }
4576 }
021230d4
AV		 4577}
4578
67359c3c
MR		 4579static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4580{
4581 switch (adapter->hw.mac.type) {
4582 case ixgbe_mac_X550:
4583 case ixgbe_mac_X550EM_x:
49425dfc 4584 case ixgbe_mac_x550em_a:
67359c3c 4585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
67359c3c 4586 adapter->vxlan_port = 0;
67359c3c
MR		 4587 break;
4588 default:
4589 break;
4590 }
4591}
4592
7a6b6f51 4593#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4594/**
2f90b865
AD		 4595 * ixgbe_configure_dcb - Configure DCB hardware
4596 * @adapter: ixgbe adapter struct
4597 *
4598 * This is called by the driver on open to configure the DCB hardware.
4599 * This is also called by the gennetlink interface when reconfiguring
4600 * the DCB state.
4601 */
4602static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4603{
4604 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4605 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4606
67ebd791
AD		 4607 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4608 if (hw->mac.type == ixgbe_mac_82598EB)
4609 netif_set_gso_max_size(adapter->netdev, 65536);
4610 return;
4611 }
4612
4613 if (hw->mac.type == ixgbe_mac_82598EB)
4614 netif_set_gso_max_size(adapter->netdev, 32768);
4615
971060b1 4616#ifdef IXGBE_FCOE
b120818e
JF		 4617 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4618 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4619#endif
b120818e
JF		 4620
4621 /* reconfigure the hardware */
4622 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4623 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4624 DCB_TX_CONFIG);
4625 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4626 DCB_RX_CONFIG);
4627 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4628 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4629 ixgbe_dcb_hw_ets(&adapter->hw,
4630 adapter->ixgbe_ieee_ets,
4631 max_frame);
4632 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4633 adapter->ixgbe_ieee_pfc->pfc_en,
4634 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4635 }
8187cd48
JF		 4636
4637 /* Enable RSS Hash per TC */
4638 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4639 u32 msb = 0;
4640 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4641
d411a936
AD		 4642 while (rss_i) {
4643 msb++;
4644 rss_i >>= 1;
4645 }
8187cd48 4646
4ae63730
AD		 4647 /* write msb to all 8 TCs in one write */
4648 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4649 }
2f90b865 4650}
9da712d2
JF		 4651#endif
4652
4653/* Additional bittime to account for IXGBE framing */
4654#define IXGBE_ETH_FRAMING 20
4655
49ce9c2c 4656/**
9da712d2
JF		 4657 * ixgbe_hpbthresh - calculate high water mark for flow control
4658 *
4659 * @adapter: board private structure to calculate for
49ce9c2c 4660 * @pb: packet buffer to calculate
9da712d2
JF		 4661 */
4662static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4663{
4664 struct ixgbe_hw *hw = &adapter->hw;
4665 struct net_device *dev = adapter->netdev;
4666 int link, tc, kb, marker;
4667 u32 dv_id, rx_pba;
4668
4669 /* Calculate max LAN frame size */
4670 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4671
4672#ifdef IXGBE_FCOE
4673 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4674 if ((dev->features & NETIF_F_FCOE_MTU) &&
4675 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4676 (pb == ixgbe_fcoe_get_tc(adapter)))
4677 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4678#endif
e5776620 4679
9da712d2
JF		 4680 /* Calculate delay value for device */
4681 switch (hw->mac.type) {
4682 case ixgbe_mac_X540:
9a75a1ac
DS		 4683 case ixgbe_mac_X550:
4684 case ixgbe_mac_X550EM_x:
49425dfc 4685 case ixgbe_mac_x550em_a:
9da712d2
JF		 4686 dv_id = IXGBE_DV_X540(link, tc);
4687 break;
4688 default:
4689 dv_id = IXGBE_DV(link, tc);
4690 break;
4691 }
4692
4693 /* Loopback switch introduces additional latency */
4694 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4695 dv_id += IXGBE_B2BT(tc);
4696
4697 /* Delay value is calculated in bit times convert to KB */
4698 kb = IXGBE_BT2KB(dv_id);
4699 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4700
4701 marker = rx_pba - kb;
4702
4703 /* It is possible that the packet buffer is not large enough
4704 * to provide required headroom. In this case throw an error
4705 * to user and a do the best we can.
4706 */
4707 if (marker < 0) {
4708 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4709 "headroom to support flow control."
4710 "Decrease MTU or number of traffic classes\n", pb);
4711 marker = tc + 1;
4712 }
4713
4714 return marker;
4715}
4716
49ce9c2c 4717/**
9da712d2
JF		 4718 * ixgbe_lpbthresh - calculate low water mark for for flow control
4719 *
4720 * @adapter: board private structure to calculate for
49ce9c2c 4721 * @pb: packet buffer to calculate
9da712d2 4722 */
e5776620 4723static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4724{
4725 struct ixgbe_hw *hw = &adapter->hw;
4726 struct net_device *dev = adapter->netdev;
4727 int tc;
4728 u32 dv_id;
4729
4730 /* Calculate max LAN frame size */
4731 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4732
e5776620
JK		 4733#ifdef IXGBE_FCOE
4734 /* FCoE traffic class uses FCOE jumbo frames */
4735 if ((dev->features & NETIF_F_FCOE_MTU) &&
4736 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4737 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4738 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4739#endif
4740
9da712d2
JF		 4741 /* Calculate delay value for device */
4742 switch (hw->mac.type) {
4743 case ixgbe_mac_X540:
9a75a1ac
DS		 4744 case ixgbe_mac_X550:
4745 case ixgbe_mac_X550EM_x:
49425dfc 4746 case ixgbe_mac_x550em_a:
9da712d2
JF		 4747 dv_id = IXGBE_LOW_DV_X540(tc);
4748 break;
4749 default:
4750 dv_id = IXGBE_LOW_DV(tc);
4751 break;
4752 }
4753
4754 /* Delay value is calculated in bit times convert to KB */
4755 return IXGBE_BT2KB(dv_id);
4756}
4757
4758/*
4759 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4760 */
4761static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4762{
4763 struct ixgbe_hw *hw = &adapter->hw;
4764 int num_tc = netdev_get_num_tc(adapter->netdev);
4765 int i;
4766
4767 if (!num_tc)
4768 num_tc = 1;
4769
9da712d2
JF		 4770 for (i = 0; i < num_tc; i++) {
4771 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4772 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4773
4774 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4775 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4776 hw->fc.low_water[i] = 0;
9da712d2 4777 }
e5776620
JK		 4778
4779 for (; i < MAX_TRAFFIC_CLASS; i++)
4780 hw->fc.high_water[i] = 0;
9da712d2
JF		 4781}
4782
80605c65
JF		 4783static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4784{
80605c65 4785 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4786 int hdrm;
4787 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4788
4789 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4790 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4791 hdrm = 32 << adapter->fdir_pballoc;
4792 else
4793 hdrm = 0;
80605c65 4794
f7e1027f 4795 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4796 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4797}
4798
e4911d57
AD		 4799static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4800{
4801 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4802 struct hlist_node *node2;
e4911d57
AD		 4803 struct ixgbe_fdir_filter *filter;
4804
4805 spin_lock(&adapter->fdir_perfect_lock);
4806
4807 if (!hlist_empty(&adapter->fdir_filter_list))
4808 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4809
b67bfe0d 4810 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4811 &adapter->fdir_filter_list, fdir_node) {
4812 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4813 &filter->filter,
4814 filter->sw_idx,
4815 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4816 IXGBE_FDIR_DROP_QUEUE :
4817 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4818 }
4819
4820 spin_unlock(&adapter->fdir_perfect_lock);
4821}
4822
2a47fa45
JF		 4823static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4824 struct ixgbe_adapter *adapter)
4825{
4826 struct ixgbe_hw *hw = &adapter->hw;
4827 u32 vmolr;
4828
4829 /* No unicast promiscuous support for VMDQ devices. */
4830 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4831 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4832
4833 /* clear the affected bit */
4834 vmolr &= ~IXGBE_VMOLR_MPE;
4835
4836 if (dev->flags & IFF_ALLMULTI) {
4837 vmolr |= IXGBE_VMOLR_MPE;
4838 } else {
4839 vmolr |= IXGBE_VMOLR_ROMPE;
4840 hw->mac.ops.update_mc_addr_list(hw, dev);
4841 }
5d7daa35 4842 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4843 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4844}
4845
2a47fa45
JF		 4846static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4847{
4848 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4849 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4850 struct ixgbe_hw *hw = &adapter->hw;
4851 u16 pool = vadapter->pool;
4852 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4853 IXGBE_PSRTYPE_UDPHDR |
4854 IXGBE_PSRTYPE_IPV4HDR |
4855 IXGBE_PSRTYPE_L2HDR |
4856 IXGBE_PSRTYPE_IPV6HDR;
4857
4858 if (hw->mac.type == ixgbe_mac_82598EB)
4859 return;
4860
4861 if (rss_i > 3)
4862 psrtype |= 2 << 29;
4863 else if (rss_i > 1)
4864 psrtype |= 1 << 29;
4865
4866 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4867}
4868
4869/**
4870 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4871 * @rx_ring: ring to free buffers from
4872 **/
4873static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4874{
4875 struct device *dev = rx_ring->dev;
4876 unsigned long size;
4877 u16 i;
4878
4879 /* ring already cleared, nothing to do */
4880 if (!rx_ring->rx_buffer_info)
4881 return;
4882
4883 /* Free all the Rx ring sk_buffs */
4884 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4885 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4886
2a47fa45
JF		 4887 if (rx_buffer->skb) {
4888 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4889 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4890 dma_unmap_page(dev,
4891 IXGBE_CB(skb)->dma,
4892 ixgbe_rx_bufsz(rx_ring),
4893 DMA_FROM_DEVICE);
2a47fa45 4894 dev_kfree_skb(skb);
4d2fcfbc 4895 rx_buffer->skb = NULL;
2a47fa45 4896 }
18cb652a
AD		 4897
4898 if (!rx_buffer->page)
4899 continue;
4900
4901 dma_unmap_page(dev, rx_buffer->dma,
4902 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4903 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4904
2a47fa45
JF		 4905 rx_buffer->page = NULL;
4906 }
4907
4908 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4909 memset(rx_ring->rx_buffer_info, 0, size);
4910
4911 /* Zero out the descriptor ring */
4912 memset(rx_ring->desc, 0, rx_ring->size);
4913
4914 rx_ring->next_to_alloc = 0;
4915 rx_ring->next_to_clean = 0;
4916 rx_ring->next_to_use = 0;
4917}
4918
4919static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4920 struct ixgbe_ring *rx_ring)
4921{
4922 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4923 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4924
4925 /* shutdown specific queue receive and wait for dma to settle */
4926 ixgbe_disable_rx_queue(adapter, rx_ring);
4927 usleep_range(10000, 20000);
4928 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4929 ixgbe_clean_rx_ring(rx_ring);
4930 rx_ring->l2_accel_priv = NULL;
4931}
4932
ae72c8d0
JF		 4933static int ixgbe_fwd_ring_down(struct net_device *vdev,
4934 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4935{
4936 struct ixgbe_adapter *adapter = accel->real_adapter;
4937 unsigned int rxbase = accel->rx_base_queue;
4938 unsigned int txbase = accel->tx_base_queue;
4939 int i;
4940
4941 netif_tx_stop_all_queues(vdev);
4942
4943 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4944 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4945 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4946 }
4947
4948 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4949 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4950 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4951 }
4952
4953
4954 return 0;
4955}
4956
4957static int ixgbe_fwd_ring_up(struct net_device *vdev,
4958 struct ixgbe_fwd_adapter *accel)
4959{
4960 struct ixgbe_adapter *adapter = accel->real_adapter;
4961 unsigned int rxbase, txbase, queues;
4962 int i, baseq, err = 0;
4963
4964 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4965 return 0;
4966
4967 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4968 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4969 accel->pool, adapter->num_rx_pools,
4970 baseq, baseq + adapter->num_rx_queues_per_pool,
4971 adapter->fwd_bitmask);
4972
4973 accel->netdev = vdev;
4974 accel->rx_base_queue = rxbase = baseq;
4975 accel->tx_base_queue = txbase = baseq;
4976
4977 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4978 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4979
4980 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4981 adapter->rx_ring[rxbase + i]->netdev = vdev;
4982 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4983 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4984 }
4985
4986 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4987 adapter->tx_ring[txbase + i]->netdev = vdev;
4988 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4989 }
4990
4991 queues = min_t(unsigned int,
4992 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4993 err = netif_set_real_num_tx_queues(vdev, queues);
4994 if (err)
4995 goto fwd_queue_err;
4996
2a47fa45
JF		 4997 err = netif_set_real_num_rx_queues(vdev, queues);
4998 if (err)
4999 goto fwd_queue_err;
5000
5001 if (is_valid_ether_addr(vdev->dev_addr))
5002 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
5003
5004 ixgbe_fwd_psrtype(accel);
5005 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
5006 return err;
5007fwd_queue_err:
5008 ixgbe_fwd_ring_down(vdev, accel);
5009 return err;
5010}
5011
5012static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5013{
5014 struct net_device *upper;
5015 struct list_head *iter;
5016 int err;
5017
5018 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5019 if (netif_is_macvlan(upper)) {
5020 struct macvlan_dev *dfwd = netdev_priv(upper);
5021 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
5022
5023 if (dfwd->fwd_priv) {
5024 err = ixgbe_fwd_ring_up(upper, vadapter);
5025 if (err)
5026 continue;
5027 }
5028 }
5029 }
5030}
5031
9a799d71
AK		 5032static void ixgbe_configure(struct ixgbe_adapter *adapter)
5033{
d2f5e7f3
AS		 5034 struct ixgbe_hw *hw = &adapter->hw;
5035
80605c65 5036 ixgbe_configure_pb(adapter);
7a6b6f51 5037#ifdef CONFIG_IXGBE_DCB
67ebd791 5038 ixgbe_configure_dcb(adapter);
2f90b865 5039#endif
b35d4d42
AD		 5040 /*
5041 * We must restore virtualization before VLANs or else
5042 * the VLVF registers will not be populated
5043 */
5044 ixgbe_configure_virtualization(adapter);
9a799d71 5045
4c1d7b4b 5046 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 5047 ixgbe_restore_vlan(adapter);
5048
d2f5e7f3
AS		 5049 switch (hw->mac.type) {
5050 case ixgbe_mac_82599EB:
5051 case ixgbe_mac_X540:
5052 hw->mac.ops.disable_rx_buff(hw);
5053 break;
5054 default:
5055 break;
5056 }
5057
c4cf55e5 5058 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5059 ixgbe_init_fdir_signature_82599(&adapter->hw,
5060 adapter->fdir_pballoc);
e4911d57
AD		 5061 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5062 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5063 adapter->fdir_pballoc);
5064 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5065 }
4c1d7b4b 5066
d2f5e7f3
AS		 5067 switch (hw->mac.type) {
5068 case ixgbe_mac_82599EB:
5069 case ixgbe_mac_X540:
5070 hw->mac.ops.enable_rx_buff(hw);
5071 break;
5072 default:
5073 break;
5074 }
5075
9de7605e
MR		 5076#ifdef CONFIG_IXGBE_DCA
5077 /* configure DCA */
5078 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5079 ixgbe_setup_dca(adapter);
5080#endif /* CONFIG_IXGBE_DCA */
5081
7c8ae65a
AD		 5082#ifdef IXGBE_FCOE
5083 /* configure FCoE L2 filters, redirection table, and Rx control */
5084 ixgbe_configure_fcoe(adapter);
5085
5086#endif /* IXGBE_FCOE */
9a799d71
AK		 5087 ixgbe_configure_tx(adapter);
5088 ixgbe_configure_rx(adapter);
2a47fa45 5089 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5090}
5091
0ecc061d 5092/**
e8e26350
PW		 5093 * ixgbe_sfp_link_config - set up SFP+ link
5094 * @adapter: pointer to private adapter struct
5095 **/
5096static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5097{
7086400d 5098 /*
52f33af8 5099 * We are assuming the worst case scenario here, and that
7086400d
AD		 5100 * is that an SFP was inserted/removed after the reset
5101 * but before SFP detection was enabled. As such the best
5102 * solution is to just start searching as soon as we start
5103 */
5104 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5105 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5106
7086400d 5107 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5108 adapter->sfp_poll_time = 0;
e8e26350
PW		 5109}
5110
5111/**
5112 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5113 * @hw: pointer to private hardware struct
5114 *
5115 * Returns 0 on success, negative on failure
5116 **/
e8e26350 5117static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5118{
3d292265
JH		 5119 u32 speed;
5120 bool autoneg, link_up = false;
a1e869de 5121 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5122
5123 if (hw->mac.ops.check_link)
3d292265 5124 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5125
5126 if (ret)
e90dd264 5127 return ret;
0ecc061d 5128
3d292265
JH		 5129 speed = hw->phy.autoneg_advertised;
5130 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5131 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5132 &autoneg);
0ecc061d 5133 if (ret)
e90dd264 5134 return ret;
0ecc061d 5135
8620a103 5136 if (hw->mac.ops.setup_link)
fd0326f2 5137 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5138
0ecc061d
PWJ		 5139 return ret;
5140}
5141
a34bcfff 5142static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5143{
9a799d71 5144 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5145 u32 gpie = 0;
9a799d71 5146
9b471446 5147 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5148 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5149 IXGBE_GPIE_OCD;
5150 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5151 /*
5152 * use EIAM to auto-mask when MSI-X interrupt is asserted
5153 * this saves a register write for every interrupt
5154 */
5155 switch (hw->mac.type) {
5156 case ixgbe_mac_82598EB:
5157 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5158 break;
9b471446 5159 case ixgbe_mac_82599EB:
b93a2226 5160 case ixgbe_mac_X540:
9a75a1ac
DS		 5161 case ixgbe_mac_X550:
5162 case ixgbe_mac_X550EM_x:
49425dfc 5163 case ixgbe_mac_x550em_a:
b93a2226 5164 default:
9b471446
JB		 5165 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5166 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5167 break;
5168 }
5169 } else {
021230d4
AV		 5170 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5171 * specifically only auto mask tx and rx interrupts */
5172 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5173 }
9a799d71 5174
a34bcfff
AD		 5175 /* XXX: to interrupt immediately for EICS writes, enable this */
5176 /* gpie |= IXGBE_GPIE_EIMEN; */
5177
5178 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5179 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5180
5181 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5182 case IXGBE_82599_VMDQ_8Q_MASK:
5183 gpie |= IXGBE_GPIE_VTMODE_16;
5184 break;
5185 case IXGBE_82599_VMDQ_4Q_MASK:
5186 gpie |= IXGBE_GPIE_VTMODE_32;
5187 break;
5188 default:
5189 gpie |= IXGBE_GPIE_VTMODE_64;
5190 break;
5191 }
119fc60a
MC		 5192 }
5193
5fdd31f9 5194 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5195 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5196 switch (adapter->hw.mac.type) {
5197 case ixgbe_mac_82599EB:
9a900eca 5198 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5199 break;
f3df98ec
DS		 5200 default:
5201 break;
5202 }
5203 }
5fdd31f9 5204
a34bcfff
AD		 5205 /* Enable fan failure interrupt */
5206 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5207 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5208
a023bbd0
DS		 5209 switch (hw->mac.type) {
5210 case ixgbe_mac_82599EB:
5211 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5212 break;
5213 case ixgbe_mac_X550EM_x:
49425dfc 5214 case ixgbe_mac_x550em_a:
a023bbd0
DS		 5215 gpie |= IXGBE_SDP0_GPIEN_X540;
5216 break;
5217 default:
5218 break;
2698b208 5219 }
a34bcfff
AD		 5220
5221 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5222}
5223
c7ccde0f 5224static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5225{
5226 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5227 int err;
a34bcfff
AD		 5228 u32 ctrl_ext;
5229
5230 ixgbe_get_hw_control(adapter);
5231 ixgbe_setup_gpie(adapter);
e8e26350 5232
9a799d71
AK		 5233 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5234 ixgbe_configure_msix(adapter);
5235 else
5236 ixgbe_configure_msi_and_legacy(adapter);
5237
ec74a471
ET		 5238 /* enable the optics for 82599 SFP+ fiber */
5239 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5240 hw->mac.ops.enable_tx_laser(hw);
5241
961fac88
DS		 5242 if (hw->phy.ops.set_phy_power)
5243 hw->phy.ops.set_phy_power(hw, true);
5244
4e857c58 5245 smp_mb__before_atomic();
9a799d71 5246 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5247 ixgbe_napi_enable_all(adapter);
5248
73c4b7cd
AD		 5249 if (ixgbe_is_sfp(hw)) {
5250 ixgbe_sfp_link_config(adapter);
5251 } else {
5252 err = ixgbe_non_sfp_link_config(hw);
5253 if (err)
5254 e_err(probe, "link_config FAILED %d\n", err);
5255 }
5256
021230d4
AV		 5257 /* clear any pending interrupts, may auto mask */
5258 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5259 ixgbe_irq_enable(adapter, true, true);
9a799d71 5260
bf069c97
DS		 5261 /*
5262 * If this adapter has a fan, check to see if we had a failure
5263 * before we enabled the interrupt.
5264 */
5265 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5266 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5267 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5268 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5269 }
5270
9a799d71
AK		 5271 /* bring the link up in the watchdog, this could race with our first
5272 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5273 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5274 adapter->link_check_timeout = jiffies;
7086400d 5275 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5276
5277 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5278 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5279 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5280 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5281}
5282
d4f80882
AV		 5283void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5284{
5285 WARN_ON(in_interrupt());
7086400d
AD		 5286 /* put off any impending NetWatchDogTimeout */
5287 adapter->netdev->trans_start = jiffies;
5288
d4f80882 5289 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5290 usleep_range(1000, 2000);
d4f80882 5291 ixgbe_down(adapter);
5809a1ae
GR		 5292 /*
5293 * If SR-IOV enabled then wait a bit before bringing the adapter
5294 * back up to give the VFs time to respond to the reset. The
5295 * two second wait is based upon the watchdog timer cycle in
5296 * the VF driver.
5297 */
5298 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5299 msleep(2000);
d4f80882
AV		 5300 ixgbe_up(adapter);
5301 clear_bit(__IXGBE_RESETTING, &adapter->state);
5302}
5303
c7ccde0f 5304void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5305{
5306 /* hardware has been reset, we need to reload some things */
5307 ixgbe_configure(adapter);
5308
c7ccde0f 5309 ixgbe_up_complete(adapter);
9a799d71
AK		 5310}
5311
5312void ixgbe_reset(struct ixgbe_adapter *adapter)
5313{
c44ade9e 5314 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5315 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5316 int err;
5317
b0483c8f
MR		 5318 if (ixgbe_removed(hw->hw_addr))
5319 return;
7086400d
AD		 5320 /* lock SFP init bit to prevent race conditions with the watchdog */
5321 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5322 usleep_range(1000, 2000);
5323
5324 /* clear all SFP and link config related flags while holding SFP_INIT */
5325 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5326 IXGBE_FLAG2_SFP_NEEDS_RESET);
5327 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5328
8ca783ab 5329 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5330 switch (err) {
5331 case 0:
5332 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5333 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5334 break;
5335 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5336 e_dev_err("master disable timed out\n");
da4dd0f7 5337 break;
794caeb2
PWJ		 5338 case IXGBE_ERR_EEPROM_VERSION:
5339 /* We are running on a pre-production device, log a warning */
849c4542 5340 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5341 "Please be aware there may be issues associated with "
849c4542
ET		 5342 "your hardware. If you are experiencing problems "
5343 "please contact your Intel or hardware "
5344 "representative who provided you with this "
5345 "hardware.\n");
794caeb2 5346 break;
da4dd0f7 5347 default:
849c4542 5348 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5349 }
9a799d71 5350
7086400d 5351 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5352
5353 /* flush entries out of MAC table */
5d7daa35 5354 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5355 __dev_uc_unsync(netdev, NULL);
5356
5357 /* do not flush user set addresses */
c9f53e63 5358 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5359
5360 /* update SAN MAC vmdq pool selection */
5361 if (hw->mac.san_mac_rar_index)
5362 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5363
8fecf67c 5364 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5365 ixgbe_ptp_reset(adapter);
961fac88
DS		 5366
5367 if (hw->phy.ops.set_phy_power) {
5368 if (!netif_running(adapter->netdev) && !adapter->wol)
5369 hw->phy.ops.set_phy_power(hw, false);
5370 else
5371 hw->phy.ops.set_phy_power(hw, true);
5372 }
9a799d71
AK		 5373}
5374
9a799d71
AK		 5375/**
5376 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5377 * @tx_ring: ring to be cleaned
5378 **/
b6ec895e 5379static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5380{
5381 struct ixgbe_tx_buffer *tx_buffer_info;
5382 unsigned long size;
b6ec895e 5383 u16 i;
9a799d71 5384
84418e3b
AD		 5385 /* ring already cleared, nothing to do */
5386 if (!tx_ring->tx_buffer_info)
5387 return;
9a799d71 5388
84418e3b 5389 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5390 for (i = 0; i < tx_ring->count; i++) {
5391 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5392 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5393 }
5394
dad8a3b3
JF		 5395 netdev_tx_reset_queue(txring_txq(tx_ring));
5396
9a799d71
AK		 5397 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5398 memset(tx_ring->tx_buffer_info, 0, size);
5399
5400 /* Zero out the descriptor ring */
5401 memset(tx_ring->desc, 0, tx_ring->size);
5402
5403 tx_ring->next_to_use = 0;
5404 tx_ring->next_to_clean = 0;
9a799d71
AK		 5405}
5406
5407/**
021230d4 5408 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5409 * @adapter: board private structure
5410 **/
021230d4 5411static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5412{
5413 int i;
5414
021230d4 5415 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5416 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5417}
5418
5419/**
021230d4 5420 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5421 * @adapter: board private structure
5422 **/
021230d4 5423static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5424{
5425 int i;
5426
021230d4 5427 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5428 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5429}
5430
e4911d57
AD		 5431static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5432{
b67bfe0d 5433 struct hlist_node *node2;
e4911d57
AD		 5434 struct ixgbe_fdir_filter *filter;
5435
5436 spin_lock(&adapter->fdir_perfect_lock);
5437
b67bfe0d 5438 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5439 &adapter->fdir_filter_list, fdir_node) {
5440 hlist_del(&filter->fdir_node);
5441 kfree(filter);
5442 }
5443 adapter->fdir_filter_count = 0;
5444
5445 spin_unlock(&adapter->fdir_perfect_lock);
5446}
5447
9a799d71
AK		 5448void ixgbe_down(struct ixgbe_adapter *adapter)
5449{
5450 struct net_device *netdev = adapter->netdev;
7f821875 5451 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5452 struct net_device *upper;
5453 struct list_head *iter;
bf29ee6c 5454 int i;
9a799d71
AK		 5455
5456 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5457 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5458 return; /* do nothing if already down */
9a799d71
AK		 5459
5460 /* disable receives */
1f9ac57c 5461 hw->mac.ops.disable_rx(hw);
9a799d71 5462
2d39d576
YZ		 5463 /* disable all enabled rx queues */
5464 for (i = 0; i < adapter->num_rx_queues; i++)
5465 /* this call also flushes the previous write */
5466 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5467
032b4325 5468 usleep_range(10000, 20000);
9a799d71 5469
7f821875
JB		 5470 netif_tx_stop_all_queues(netdev);
5471
7086400d 5472 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5473 netif_carrier_off(netdev);
5474 netif_tx_disable(netdev);
5475
2a47fa45
JF		 5476 /* disable any upper devices */
5477 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5478 if (netif_is_macvlan(upper)) {
5479 struct macvlan_dev *vlan = netdev_priv(upper);
5480
5481 if (vlan->fwd_priv) {
5482 netif_tx_stop_all_queues(upper);
5483 netif_carrier_off(upper);
5484 netif_tx_disable(upper);
5485 }
5486 }
5487 }
5488
c0dfb90e
JF		 5489 ixgbe_irq_disable(adapter);
5490
5491 ixgbe_napi_disable_all(adapter);
5492
d034acf1
AD		 5493 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5494 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5495 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5496
5497 del_timer_sync(&adapter->service_timer);
5498
34cecbbf 5499 if (adapter->num_vfs) {
8e34d1aa
AD		 5500 /* Clear EITR Select mapping */
5501 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5502
5503 /* Mark all the VFs as inactive */
5504 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5505 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5506
34cecbbf
AD		 5507 /* ping all the active vfs to let them know we are going down */
5508 ixgbe_ping_all_vfs(adapter);
5509
5510 /* Disable all VFTE/VFRE TX/RX */
5511 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5512 }
5513
7f821875
JB		 5514 /* disable transmits in the hardware now that interrupts are off */
5515 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5516 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5517 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5518 }
34cecbbf 5519
9a75a1ac 5520 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5521 switch (hw->mac.type) {
5522 case ixgbe_mac_82599EB:
b93a2226 5523 case ixgbe_mac_X540:
9a75a1ac
DS		 5524 case ixgbe_mac_X550:
5525 case ixgbe_mac_X550EM_x:
49425dfc 5526 case ixgbe_mac_x550em_a:
88512539 5527 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5528 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5529 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5530 break;
5531 default:
5532 break;
5533 }
7f821875 5534
6f4a0e45
PL		 5535 if (!pci_channel_offline(adapter->pdev))
5536 ixgbe_reset(adapter);
c6ecf39a 5537
ec74a471
ET		 5538 /* power down the optics for 82599 SFP+ fiber */
5539 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5540 hw->mac.ops.disable_tx_laser(hw);
5541
9a799d71
AK		 5542 ixgbe_clean_all_tx_rings(adapter);
5543 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5544}
5545
9a799d71
AK		 5546/**
5547 * ixgbe_tx_timeout - Respond to a Tx Hang
5548 * @netdev: network interface device structure
5549 **/
5550static void ixgbe_tx_timeout(struct net_device *netdev)
5551{
5552 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5553
5554 /* Do the reset outside of interrupt context */
c83c6cbd 5555 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5556}
5557
9a799d71
AK		 5558/**
5559 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5560 * @adapter: board private structure to initialize
5561 *
5562 * ixgbe_sw_init initializes the Adapter private data structure.
5563 * Fields are initialized based on PCI device information and
5564 * OS network device settings (MTU size).
5565 **/
9f9a12f8 5566static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5567{
5568 struct ixgbe_hw *hw = &adapter->hw;
5569 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5570 unsigned int rss, fdir;
cb6d0f5e 5571 u32 fwsm;
7a6b6f51 5572#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5573 int j;
5574 struct tc_configuration *tc;
5575#endif
021230d4 5576
c44ade9e
JB		 5577 /* PCI config space info */
5578
5579 hw->vendor_id = pdev->vendor;
5580 hw->device_id = pdev->device;
5581 hw->revision_id = pdev->revision;
5582 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5583 hw->subsystem_device_id = pdev->subsystem_device;
5584
8fc3bb6d 5585 /* Set common capability flags and settings */
0f9b232b 5586 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5587 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5588 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5589 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5590 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5591 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5592 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5593 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5594#ifdef CONFIG_IXGBE_DCA
5595 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5596#endif
5597#ifdef IXGBE_FCOE
5598 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5599 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5600#ifdef CONFIG_IXGBE_DCB
5601 /* Default traffic class to use for FCoE */
5602 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5603#endif /* CONFIG_IXGBE_DCB */
5604#endif /* IXGBE_FCOE */
5605
b82b17d9
JF		 5606 /* initialize static ixgbe jump table entries */
5607 adapter->jump_tables[0] = ixgbe_ipv4_fields;
5608
5d7daa35
JK		 5609 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5610 hw->mac.num_rar_entries,
5611 GFP_ATOMIC);
530fd82a
AD		 5612 if (!adapter->mac_table)
5613 return -ENOMEM;
5d7daa35 5614
8fc3bb6d 5615 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5616 switch (hw->mac.type) {
5617 case ixgbe_mac_82598EB:
8fc3bb6d 5618 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5619
bf069c97
DS		 5620 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5621 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5622
49c7ffbe 5623 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5624 adapter->ring_feature[RING_F_FDIR].limit = 0;
5625 adapter->atr_sample_rate = 0;
5626 adapter->fdir_pballoc = 0;
5627#ifdef IXGBE_FCOE
5628 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5629 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5630#ifdef CONFIG_IXGBE_DCB
5631 adapter->fcoe.up = 0;
5632#endif /* IXGBE_DCB */
5633#endif /* IXGBE_FCOE */
5634 break;
5635 case ixgbe_mac_82599EB:
5636 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5637 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5638 break;
b93a2226 5639 case ixgbe_mac_X540:
9a900eca 5640 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5641 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5642 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5643 break;
9a75a1ac 5644 case ixgbe_mac_X550EM_x:
49425dfc 5645 case ixgbe_mac_x550em_a:
9a75a1ac
DS		 5646 case ixgbe_mac_X550:
5647#ifdef CONFIG_IXGBE_DCA
5648 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5649#endif
5650#ifdef CONFIG_IXGBE_VXLAN
5651 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5652#endif
5653 break;
bd508178
AD		 5654 default:
5655 break;
f8212f97 5656 }
2f90b865 5657
7c8ae65a
AD		 5658#ifdef IXGBE_FCOE
5659 /* FCoE support exists, always init the FCoE lock */
5660 spin_lock_init(&adapter->fcoe.lock);
5661
5662#endif
1fc5f038
AD		 5663 /* n-tuple support exists, always init our spinlock */
5664 spin_lock_init(&adapter->fdir_perfect_lock);
5665
7a6b6f51 5666#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5667 switch (hw->mac.type) {
5668 case ixgbe_mac_X540:
9a75a1ac
DS		 5669 case ixgbe_mac_X550:
5670 case ixgbe_mac_X550EM_x:
49425dfc 5671 case ixgbe_mac_x550em_a:
4de2a022
JF		 5672 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5673 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5674 break;
5675 default:
5676 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5677 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5678 break;
5679 }
5680
2f90b865
AD		 5681 /* Configure DCB traffic classes */
5682 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5683 tc = &adapter->dcb_cfg.tc_config[j];
5684 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5685 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5686 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5687 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5688 tc->dcb_pfc = pfc_disabled;
5689 }
4de2a022
JF		 5690
5691 /* Initialize default user to priority mapping, UPx->TC0 */
5692 tc = &adapter->dcb_cfg.tc_config[0];
5693 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5694 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5695
2f90b865
AD		 5696 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5697 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5698 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5699 adapter->dcb_set_bitmap = 0x00;
3032309b 5700 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5701 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5702 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5703
5704#endif
9a799d71
AK		 5705
5706 /* default flow control settings */
cd7664f6 5707 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5708 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5709 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5710 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5711 hw->fc.send_xon = true;
73d80953 5712 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5713
99d74487 5714#ifdef CONFIG_PCI_IOV
170e8543
JK		 5715 if (max_vfs > 0)
5716 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5717
99d74487 5718 /* assign number of SR-IOV VFs */
170e8543 5719 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5720 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5721 adapter->num_vfs = 0;
5722 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5723 } else {
5724 adapter->num_vfs = max_vfs;
5725 }
5726 }
5727#endif /* CONFIG_PCI_IOV */
99d74487 5728
30efa5a3 5729 /* enable itr by default in dynamic mode */
f7554a2b 5730 adapter->rx_itr_setting = 1;
f7554a2b 5731 adapter->tx_itr_setting = 1;
30efa5a3 5732
30efa5a3
JB		 5733 /* set default ring sizes */
5734 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5735 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5736
bd198058 5737 /* set default work limits */
59224555 5738 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5739
9a799d71 5740 /* initialize eeprom parameters */
c44ade9e 5741 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5742 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5743 return -EIO;
5744 }
5745
2a47fa45
JF		 5746 /* PF holds first pool slot */
5747 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5748 set_bit(__IXGBE_DOWN, &adapter->state);
5749
5750 return 0;
5751}
5752
5753/**
5754 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5755 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5756 *
5757 * Return 0 on success, negative on failure
5758 **/
b6ec895e 5759int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5760{
b6ec895e 5761 struct device *dev = tx_ring->dev;
de88eeeb 5762 int orig_node = dev_to_node(dev);
ca8dfe25 5763 int ring_node = -1;
9a799d71
AK		 5764 int size;
5765
3a581073 5766 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5767
5768 if (tx_ring->q_vector)
ca8dfe25 5769 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5770
ca8dfe25 5771 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5772 if (!tx_ring->tx_buffer_info)
89bf67f1 5773 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5774 if (!tx_ring->tx_buffer_info)
5775 goto err;
9a799d71 5776
827da44c
JS		 5777 u64_stats_init(&tx_ring->syncp);
5778
9a799d71 5779 /* round up to nearest 4K */
12207e49 5780 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5781 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5782
ca8dfe25 5783 set_dev_node(dev, ring_node);
de88eeeb
AD		 5784 tx_ring->desc = dma_alloc_coherent(dev,
5785 tx_ring->size,
5786 &tx_ring->dma,
5787 GFP_KERNEL);
5788 set_dev_node(dev, orig_node);
5789 if (!tx_ring->desc)
5790 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5791 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5792 if (!tx_ring->desc)
5793 goto err;
9a799d71 5794
3a581073
JB		 5795 tx_ring->next_to_use = 0;
5796 tx_ring->next_to_clean = 0;
9a799d71 5797 return 0;
e01c31a5
JB		 5798
5799err:
5800 vfree(tx_ring->tx_buffer_info);
5801 tx_ring->tx_buffer_info = NULL;
b6ec895e 5802 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5803 return -ENOMEM;
9a799d71
AK		 5804}
5805
69888674
AD		 5806/**
5807 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5808 * @adapter: board private structure
5809 *
5810 * If this function returns with an error, then it's possible one or
5811 * more of the rings is populated (while the rest are not). It is the
5812 * callers duty to clean those orphaned rings.
5813 *
5814 * Return 0 on success, negative on failure
5815 **/
5816static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5817{
5818 int i, err = 0;
5819
5820 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5821 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5822 if (!err)
5823 continue;
de3d5b94 5824
396e799c 5825 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5826 goto err_setup_tx;
69888674
AD		 5827 }
5828
de3d5b94
AD		 5829 return 0;
5830err_setup_tx:
5831 /* rewind the index freeing the rings as we go */
5832 while (i--)
5833 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5834 return err;
5835}
5836
9a799d71
AK		 5837/**
5838 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5839 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5840 *
5841 * Returns 0 on success, negative on failure
5842 **/
b6ec895e 5843int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5844{
b6ec895e 5845 struct device *dev = rx_ring->dev;
de88eeeb 5846 int orig_node = dev_to_node(dev);
ca8dfe25 5847 int ring_node = -1;
021230d4 5848 int size;
9a799d71 5849
3a581073 5850 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5851
5852 if (rx_ring->q_vector)
ca8dfe25 5853 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5854
ca8dfe25 5855 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5856 if (!rx_ring->rx_buffer_info)
89bf67f1 5857 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5858 if (!rx_ring->rx_buffer_info)
5859 goto err;
9a799d71 5860
827da44c
JS		 5861 u64_stats_init(&rx_ring->syncp);
5862
9a799d71 5863 /* Round up to nearest 4K */
3a581073
JB		 5864 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5865 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5866
ca8dfe25 5867 set_dev_node(dev, ring_node);
de88eeeb
AD		 5868 rx_ring->desc = dma_alloc_coherent(dev,
5869 rx_ring->size,
5870 &rx_ring->dma,
5871 GFP_KERNEL);
5872 set_dev_node(dev, orig_node);
5873 if (!rx_ring->desc)
5874 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5875 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5876 if (!rx_ring->desc)
5877 goto err;
9a799d71 5878
3a581073
JB		 5879 rx_ring->next_to_clean = 0;
5880 rx_ring->next_to_use = 0;
9a799d71
AK		 5881
5882 return 0;
b6ec895e
AD		 5883err:
5884 vfree(rx_ring->rx_buffer_info);
5885 rx_ring->rx_buffer_info = NULL;
5886 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5887 return -ENOMEM;
9a799d71
AK		 5888}
5889
69888674
AD		 5890/**
5891 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5892 * @adapter: board private structure
5893 *
5894 * If this function returns with an error, then it's possible one or
5895 * more of the rings is populated (while the rest are not). It is the
5896 * callers duty to clean those orphaned rings.
5897 *
5898 * Return 0 on success, negative on failure
5899 **/
69888674
AD		 5900static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5901{
5902 int i, err = 0;
5903
5904 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5905 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5906 if (!err)
5907 continue;
de3d5b94 5908
396e799c 5909 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5910 goto err_setup_rx;
69888674
AD		 5911 }
5912
7c8ae65a
AD		 5913#ifdef IXGBE_FCOE
5914 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5915 if (!err)
5916#endif
5917 return 0;
de3d5b94
AD		 5918err_setup_rx:
5919 /* rewind the index freeing the rings as we go */
5920 while (i--)
5921 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5922 return err;
5923}
5924
9a799d71
AK		 5925/**
5926 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5927 * @tx_ring: Tx descriptor ring for a specific queue
5928 *
5929 * Free all transmit software resources
5930 **/
b6ec895e 5931void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5932{
b6ec895e 5933 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5934
5935 vfree(tx_ring->tx_buffer_info);
5936 tx_ring->tx_buffer_info = NULL;
5937
b6ec895e
AD		 5938 /* if not set, then don't free */
5939 if (!tx_ring->desc)
5940 return;
5941
5942 dma_free_coherent(tx_ring->dev, tx_ring->size,
5943 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5944
5945 tx_ring->desc = NULL;
5946}
5947
5948/**
5949 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5950 * @adapter: board private structure
5951 *
5952 * Free all transmit software resources
5953 **/
5954static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5955{
5956 int i;
5957
5958 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5959 if (adapter->tx_ring[i]->desc)
b6ec895e 5960 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5961}
5962
5963/**
b4617240 5964 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5965 * @rx_ring: ring to clean the resources from
5966 *
5967 * Free all receive software resources
5968 **/
b6ec895e 5969void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5970{
b6ec895e 5971 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5972
5973 vfree(rx_ring->rx_buffer_info);
5974 rx_ring->rx_buffer_info = NULL;
5975
b6ec895e
AD		 5976 /* if not set, then don't free */
5977 if (!rx_ring->desc)
5978 return;
5979
5980 dma_free_coherent(rx_ring->dev, rx_ring->size,
5981 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5982
5983 rx_ring->desc = NULL;
5984}
5985
5986/**
5987 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5988 * @adapter: board private structure
5989 *
5990 * Free all receive software resources
5991 **/
5992static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5993{
5994 int i;
5995
7c8ae65a
AD		 5996#ifdef IXGBE_FCOE
5997 ixgbe_free_fcoe_ddp_resources(adapter);
5998
5999#endif
9a799d71 6000 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 6001 if (adapter->rx_ring[i]->desc)
b6ec895e 6002 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 6003}
6004
9a799d71
AK		 6005/**
6006 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6007 * @netdev: network interface device structure
6008 * @new_mtu: new value for maximum frame size
6009 *
6010 * Returns 0 on success, negative on failure
6011 **/
6012static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6013{
6014 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6015 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
6016
42c783c5 6017 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 6018 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
6019 return -EINVAL;
6020
6021 /*
872844dd
AD		 6022 * For 82599EB we cannot allow legacy VFs to enable their receive
6023 * paths when MTU greater than 1500 is configured. So display a
6024 * warning that legacy VFs will be disabled.
655309e9
AD		 6025 */
6026 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6027 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 6028 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 6029 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 6030
396e799c 6031 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 6032
021230d4 6033 /* must set new MTU before calling down or up */
9a799d71
AK		 6034 netdev->mtu = new_mtu;
6035
d4f80882
AV		 6036 if (netif_running(netdev))
6037 ixgbe_reinit_locked(adapter);
9a799d71
AK		 6038
6039 return 0;
6040}
6041
6042/**
6043 * ixgbe_open - Called when a network interface is made active
6044 * @netdev: network interface device structure
6045 *
6046 * Returns 0 on success, negative value on failure
6047 *
6048 * The open entry point is called when a network interface is made
6049 * active by the system (IFF_UP). At this point all resources needed
6050 * for transmit and receive operations are allocated, the interrupt
6051 * handler is registered with the OS, the watchdog timer is started,
6052 * and the stack is notified that the interface is ready.
6053 **/
6c211fe1 6054int ixgbe_open(struct net_device *netdev)
9a799d71
AK		 6055{
6056 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 6057 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 6058 int err, queues;
4bebfaa5
AK		 6059
6060 /* disallow open during test */
6061 if (test_bit(__IXGBE_TESTING, &adapter->state))
6062 return -EBUSY;
9a799d71 6063
54386467
JB		 6064 netif_carrier_off(netdev);
6065
9a799d71
AK		 6066 /* allocate transmit descriptors */
6067 err = ixgbe_setup_all_tx_resources(adapter);
6068 if (err)
6069 goto err_setup_tx;
6070
9a799d71
AK		 6071 /* allocate receive descriptors */
6072 err = ixgbe_setup_all_rx_resources(adapter);
6073 if (err)
6074 goto err_setup_rx;
6075
6076 ixgbe_configure(adapter);
6077
021230d4 6078 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6079 if (err)
6080 goto err_req_irq;
6081
ac802f5d 6082 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6083 if (adapter->num_rx_pools > 1)
6084 queues = adapter->num_rx_queues_per_pool;
6085 else
6086 queues = adapter->num_tx_queues;
6087
6088 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6089 if (err)
6090 goto err_set_queues;
6091
2a47fa45
JF		 6092 if (adapter->num_rx_pools > 1 &&
6093 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6094 queues = IXGBE_MAX_L2A_QUEUES;
6095 else
6096 queues = adapter->num_rx_queues;
6097 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6098 if (err)
6099 goto err_set_queues;
6100
1a71ab24 6101 ixgbe_ptp_init(adapter);
1a71ab24 6102
c7ccde0f 6103 ixgbe_up_complete(adapter);
9a799d71 6104
67359c3c
MR		 6105 ixgbe_clear_vxlan_port(adapter);
6106#ifdef CONFIG_IXGBE_VXLAN
3f207800 6107 vxlan_get_rx_port(netdev);
3f207800 6108#endif
67359c3c 6109
9a799d71
AK		 6110 return 0;
6111
ac802f5d
AD		 6112err_set_queues:
6113 ixgbe_free_irq(adapter);
9a799d71 6114err_req_irq:
a20a1199 6115 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6116 if (hw->phy.ops.set_phy_power && !adapter->wol)
6117 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6118err_setup_rx:
a20a1199 6119 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6120err_setup_tx:
9a799d71
AK		 6121 ixgbe_reset(adapter);
6122
6123 return err;
6124}
6125
a0cccce2
JK		 6126static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6127{
6128 ixgbe_ptp_suspend(adapter);
6129
6ac74394
DS		 6130 if (adapter->hw.phy.ops.enter_lplu) {
6131 adapter->hw.phy.reset_disable = true;
6132 ixgbe_down(adapter);
6133 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6134 adapter->hw.phy.reset_disable = false;
6135 } else {
6136 ixgbe_down(adapter);
6137 }
6138
a0cccce2
JK		 6139 ixgbe_free_irq(adapter);
6140
6141 ixgbe_free_all_tx_resources(adapter);
6142 ixgbe_free_all_rx_resources(adapter);
6143}
6144
9a799d71
AK		 6145/**
6146 * ixgbe_close - Disables a network interface
6147 * @netdev: network interface device structure
6148 *
6149 * Returns 0, this is not allowed to fail
6150 *
6151 * The close entry point is called when an interface is de-activated
6152 * by the OS. The hardware is still under the drivers control, but
6153 * needs to be disabled. A global MAC reset is issued to stop the
6154 * hardware, and all transmit and receive resources are freed.
6155 **/
6c211fe1 6156int ixgbe_close(struct net_device *netdev)
9a799d71
AK		 6157{
6158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6159
1a71ab24 6160 ixgbe_ptp_stop(adapter);
1a71ab24 6161
a0cccce2 6162 ixgbe_close_suspend(adapter);
9a799d71 6163
e4911d57
AD		 6164 ixgbe_fdir_filter_exit(adapter);
6165
5eba3699 6166 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6167
6168 return 0;
6169}
6170
b3c8b4ba
AD		 6171#ifdef CONFIG_PM
6172static int ixgbe_resume(struct pci_dev *pdev)
6173{
c60fbb00
AD		 6174 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6175 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6176 u32 err;
6177
0391bbe3 6178 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6179 pci_set_power_state(pdev, PCI_D0);
6180 pci_restore_state(pdev);
656ab817
DS		 6181 /*
6182 * pci_restore_state clears dev->state_saved so call
6183 * pci_save_state to restore it.
6184 */
6185 pci_save_state(pdev);
9ce77666 6186
6187 err = pci_enable_device_mem(pdev);
b3c8b4ba 6188 if (err) {
849c4542 6189 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6190 return err;
6191 }
4e857c58 6192 smp_mb__before_atomic();
41c62843 6193 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6194 pci_set_master(pdev);
6195
dd4d8ca6 6196 pci_wake_from_d3(pdev, false);
b3c8b4ba 6197
b3c8b4ba
AD		 6198 ixgbe_reset(adapter);
6199
495dce12
WJP		 6200 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6201
ac802f5d
AD		 6202 rtnl_lock();
6203 err = ixgbe_init_interrupt_scheme(adapter);
6204 if (!err && netif_running(netdev))
c60fbb00 6205 err = ixgbe_open(netdev);
ac802f5d
AD		 6206
6207 rtnl_unlock();
6208
6209 if (err)
6210 return err;
b3c8b4ba
AD		 6211
6212 netif_device_attach(netdev);
6213
6214 return 0;
6215}
b3c8b4ba 6216#endif /* CONFIG_PM */
9d8d05ae
RW		 6217
6218static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6219{
c60fbb00
AD		 6220 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6221 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6222 struct ixgbe_hw *hw = &adapter->hw;
6223 u32 ctrl, fctrl;
6224 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6225#ifdef CONFIG_PM
6226 int retval = 0;
6227#endif
6228
6229 netif_device_detach(netdev);
6230
499ab5cc 6231 rtnl_lock();
a0cccce2
JK		 6232 if (netif_running(netdev))
6233 ixgbe_close_suspend(adapter);
499ab5cc 6234 rtnl_unlock();
b3c8b4ba 6235
5f5ae6fc
AD		 6236 ixgbe_clear_interrupt_scheme(adapter);
6237
b3c8b4ba
AD		 6238#ifdef CONFIG_PM
6239 retval = pci_save_state(pdev);
6240 if (retval)
6241 return retval;
4df10466 6242
b3c8b4ba 6243#endif
f4f1040a
JK		 6244 if (hw->mac.ops.stop_link_on_d3)
6245 hw->mac.ops.stop_link_on_d3(hw);
6246
e8e26350
PW		 6247 if (wufc) {
6248 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6249
ec74a471
ET		 6250 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6251 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6252 hw->mac.ops.enable_tx_laser(hw);
6253
e8e26350
PW		 6254 /* turn on all-multi mode if wake on multicast is enabled */
6255 if (wufc & IXGBE_WUFC_MC) {
6256 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6257 fctrl |= IXGBE_FCTRL_MPE;
6258 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6259 }
6260
6261 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6262 ctrl |= IXGBE_CTRL_GIO_DIS;
6263 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6264
6265 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6266 } else {
6267 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6268 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6269 }
6270
bd508178
AD		 6271 switch (hw->mac.type) {
6272 case ixgbe_mac_82598EB:
dd4d8ca6 6273 pci_wake_from_d3(pdev, false);
bd508178
AD		 6274 break;
6275 case ixgbe_mac_82599EB:
b93a2226 6276 case ixgbe_mac_X540:
9a75a1ac
DS		 6277 case ixgbe_mac_X550:
6278 case ixgbe_mac_X550EM_x:
49425dfc 6279 case ixgbe_mac_x550em_a:
bd508178
AD		 6280 pci_wake_from_d3(pdev, !!wufc);
6281 break;
6282 default:
6283 break;
6284 }
b3c8b4ba 6285
9d8d05ae 6286 *enable_wake = !!wufc;
961fac88
DS		 6287 if (hw->phy.ops.set_phy_power && !*enable_wake)
6288 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6289
b3c8b4ba
AD		 6290 ixgbe_release_hw_control(adapter);
6291
41c62843
MR		 6292 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6293 pci_disable_device(pdev);
b3c8b4ba 6294
9d8d05ae
RW		 6295 return 0;
6296}
6297
6298#ifdef CONFIG_PM
6299static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6300{
6301 int retval;
6302 bool wake;
6303
6304 retval = __ixgbe_shutdown(pdev, &wake);
6305 if (retval)
6306 return retval;
6307
6308 if (wake) {
6309 pci_prepare_to_sleep(pdev);
6310 } else {
6311 pci_wake_from_d3(pdev, false);
6312 pci_set_power_state(pdev, PCI_D3hot);
6313 }
b3c8b4ba
AD		 6314
6315 return 0;
6316}
9d8d05ae 6317#endif /* CONFIG_PM */
b3c8b4ba
AD		 6318
6319static void ixgbe_shutdown(struct pci_dev *pdev)
6320{
9d8d05ae
RW		 6321 bool wake;
6322
6323 __ixgbe_shutdown(pdev, &wake);
6324
6325 if (system_state == SYSTEM_POWER_OFF) {
6326 pci_wake_from_d3(pdev, wake);
6327 pci_set_power_state(pdev, PCI_D3hot);
6328 }
b3c8b4ba
AD		 6329}
6330
9a799d71
AK		 6331/**
6332 * ixgbe_update_stats - Update the board statistics counters.
6333 * @adapter: board private structure
6334 **/
6335void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6336{
2d86f139 6337 struct net_device *netdev = adapter->netdev;
9a799d71 6338 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6339 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6340 u64 total_mpc = 0;
6341 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6342 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6343 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6344 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6345
d08935c2
DS		 6346 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6347 test_bit(__IXGBE_RESETTING, &adapter->state))
6348 return;
6349
94b982b2 6350 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6351 u64 rsc_count = 0;
94b982b2 6352 u64 rsc_flush = 0;
94b982b2 6353 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6354 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6355 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6356 }
6357 adapter->rsc_total_count = rsc_count;
6358 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6359 }
6360
5b7da515
AD		 6361 for (i = 0; i < adapter->num_rx_queues; i++) {
6362 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6363 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6364 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6365 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6366 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6367 bytes += rx_ring->stats.bytes;
6368 packets += rx_ring->stats.packets;
6369 }
6370 adapter->non_eop_descs = non_eop_descs;
6371 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6372 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6373 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6374 netdev->stats.rx_bytes = bytes;
6375 netdev->stats.rx_packets = packets;
6376
6377 bytes = 0;
6378 packets = 0;
7ca3bc58 6379 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6380 for (i = 0; i < adapter->num_tx_queues; i++) {
6381 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6382 restart_queue += tx_ring->tx_stats.restart_queue;
6383 tx_busy += tx_ring->tx_stats.tx_busy;
6384 bytes += tx_ring->stats.bytes;
6385 packets += tx_ring->stats.packets;
6386 }
eb985f09 6387 adapter->restart_queue = restart_queue;
5b7da515
AD		 6388 adapter->tx_busy = tx_busy;
6389 netdev->stats.tx_bytes = bytes;
6390 netdev->stats.tx_packets = packets;
7ca3bc58 6391
7ca647bd 6392 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6393
6394 /* 8 register reads */
6f11eef7
AV		 6395 for (i = 0; i < 8; i++) {
6396 /* for packet buffers not used, the register should read 0 */
6397 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6398 missed_rx += mpc;
7ca647bd
JP		 6399 hwstats->mpc[i] += mpc;
6400 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6401 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6402 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6403 switch (hw->mac.type) {
6404 case ixgbe_mac_82598EB:
1a70db4b
ET		 6405 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6406 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6407 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6408 hwstats->pxonrxc[i] +=
6409 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6410 break;
6411 case ixgbe_mac_82599EB:
b93a2226 6412 case ixgbe_mac_X540:
9a75a1ac
DS		 6413 case ixgbe_mac_X550:
6414 case ixgbe_mac_X550EM_x:
49425dfc 6415 case ixgbe_mac_x550em_a:
bd508178
AD		 6416 hwstats->pxonrxc[i] +=
6417 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6418 break;
6419 default:
6420 break;
e8e26350 6421 }
6f11eef7 6422 }
1a70db4b
ET		 6423
6424 /*16 register reads */
6425 for (i = 0; i < 16; i++) {
6426 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6427 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6428 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6429 (hw->mac.type == ixgbe_mac_X540) ||
6430 (hw->mac.type == ixgbe_mac_X550) ||
49425dfc
MR		 6431 (hw->mac.type == ixgbe_mac_X550EM_x) ||
6432 (hw->mac.type == ixgbe_mac_x550em_a)) {
1a70db4b
ET		 6433 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6434 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6435 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6436 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6437 }
6438 }
6439
7ca647bd 6440 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6441 /* work around hardware counting issue */
7ca647bd 6442 hwstats->gprc -= missed_rx;
6f11eef7 6443
c84d324c
JF		 6444 ixgbe_update_xoff_received(adapter);
6445
6f11eef7 6446 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6447 switch (hw->mac.type) {
6448 case ixgbe_mac_82598EB:
6449 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6450 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6451 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6452 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6453 break;
b93a2226 6454 case ixgbe_mac_X540:
9a75a1ac
DS		 6455 case ixgbe_mac_X550:
6456 case ixgbe_mac_X550EM_x:
49425dfc 6457 case ixgbe_mac_x550em_a:
9a75a1ac 6458 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6459 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6460 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6461 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6462 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6463 case ixgbe_mac_82599EB:
a4d4f629
AD		 6464 for (i = 0; i < 16; i++)
6465 adapter->hw_rx_no_dma_resources +=
6466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6467 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6468 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6469 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6470 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6471 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6472 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6473 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6474 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6475 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6476#ifdef IXGBE_FCOE
7ca647bd
JP		 6477 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6478 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6479 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6480 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6481 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6482 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6483 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6484 if (adapter->fcoe.ddp_pool) {
6485 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6486 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6487 unsigned int cpu;
6488 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6489 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6490 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6491 noddp += ddp_pool->noddp;
6492 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6493 }
5a1ee270
AD		 6494 hwstats->fcoe_noddp = noddp;
6495 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6496 }
6d45522c 6497#endif /* IXGBE_FCOE */
bd508178
AD		 6498 break;
6499 default:
6500 break;
e8e26350 6501 }
9a799d71 6502 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6503 hwstats->bprc += bprc;
6504 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6505 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6506 hwstats->mprc -= bprc;
6507 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6508 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6509 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6510 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6511 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6512 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6513 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6514 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6515 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6516 hwstats->lxontxc += lxon;
6f11eef7 6517 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6518 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6519 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6520 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6521 /*
6522 * 82598 errata - tx of flow control packets is included in tx counters
6523 */
6524 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6525 hwstats->gptc -= xon_off_tot;
6526 hwstats->mptc -= xon_off_tot;
6527 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6528 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6529 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6530 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6531 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6532 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6533 hwstats->ptc64 -= xon_off_tot;
6534 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6535 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6536 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6537 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6538 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6539 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6540
6541 /* Fill out the OS statistics structure */
7ca647bd 6542 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6543
6544 /* Rx Errors */
7ca647bd 6545 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6546 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6547 netdev->stats.rx_length_errors = hwstats->rlec;
6548 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6549 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6550}
6551
6552/**
d034acf1 6553 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6554 * @adapter: pointer to the device adapter structure
9a799d71 6555 **/
d034acf1 6556static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6557{
cf8280ee 6558 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6559 int i;
cf8280ee 6560
d034acf1
AD		 6561 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6562 return;
6563
6564 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6565
d034acf1 6566 /* if interface is down do nothing */
fe49f04a 6567 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6568 return;
6569
6570 /* do nothing if we are not using signature filters */
6571 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6572 return;
6573
6574 adapter->fdir_overflow++;
6575
93c52dd0
AD		 6576 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6577 for (i = 0; i < adapter->num_tx_queues; i++)
6578 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6579 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6580 /* re-enable flow director interrupts */
6581 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6582 } else {
6583 e_err(probe, "failed to finish FDIR re-initialization, "
6584 "ignored adding FDIR ATR filters\n");
6585 }
93c52dd0
AD		 6586}
6587
6588/**
6589 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6590 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6591 *
6592 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6593 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6594 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6595 * determine if a hang has occurred.
93c52dd0
AD		 6596 */
6597static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6598{
cf8280ee 6599 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6600 u64 eics = 0;
6601 int i;
cf8280ee 6602
09f40aed 6603 /* If we're down, removing or resetting, just bail */
93c52dd0 6604 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6605 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6606 test_bit(__IXGBE_RESETTING, &adapter->state))
6607 return;
22d5a71b 6608
93c52dd0
AD		 6609 /* Force detection of hung controller */
6610 if (netif_carrier_ok(adapter->netdev)) {
6611 for (i = 0; i < adapter->num_tx_queues; i++)
6612 set_check_for_tx_hang(adapter->tx_ring[i]);
6613 }
22d5a71b 6614
fe49f04a
AD		 6615 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6616 /*
6617 * for legacy and MSI interrupts don't set any bits
6618 * that are enabled for EIAM, because this operation
6619 * would set *both* EIMS and EICS for any bit in EIAM
6620 */
6621 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6622 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6623 } else {
6624 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6625 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6626 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6627 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6628 eics |= ((u64)1 << i);
6629 }
cf8280ee 6630 }
9a799d71 6631
93c52dd0 6632 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6633 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6634}
6635
e8e26350 6636/**
93c52dd0 6637 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6638 * @adapter: pointer to the device adapter structure
6639 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6640 **/
93c52dd0 6641static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6642{
e8e26350 6643 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6644 u32 link_speed = adapter->link_speed;
6645 bool link_up = adapter->link_up;
041441d0 6646 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6647
93c52dd0
AD		 6648 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6649 return;
6650
6651 if (hw->mac.ops.check_link) {
6652 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6653 } else {
93c52dd0
AD		 6654 /* always assume link is up, if no check link function */
6655 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6656 link_up = true;
c4cf55e5 6657 }
041441d0
AD		 6658
6659 if (adapter->ixgbe_ieee_pfc)
6660 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6661
3ebe8fde 6662 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6663 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6664 ixgbe_set_rx_drop_en(adapter);
6665 }
93c52dd0
AD		 6666
6667 if (link_up ||
6668 time_after(jiffies, (adapter->link_check_timeout +
6669 IXGBE_TRY_LINK_TIMEOUT))) {
6670 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6671 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6672 IXGBE_WRITE_FLUSH(hw);
6673 }
6674
6675 adapter->link_up = link_up;
6676 adapter->link_speed = link_speed;
e8e26350
PW		 6677}
6678
107d3018
AD		 6679static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6680{
6681#ifdef CONFIG_IXGBE_DCB
6682 struct net_device *netdev = adapter->netdev;
6683 struct dcb_app app = {
6684 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6685 .protocol = 0,
6686 };
6687 u8 up = 0;
6688
6689 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6690 up = dcb_ieee_getapp_mask(netdev, &app);
6691
6692 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6693#endif
6694}
6695
e8e26350 6696/**
93c52dd0
AD		 6697 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6698 * print link up message
49ce9c2c 6699 * @adapter: pointer to the device adapter structure
e8e26350 6700 **/
93c52dd0 6701static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6702{
93c52dd0 6703 struct net_device *netdev = adapter->netdev;
e8e26350 6704 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6705 struct net_device *upper;
6706 struct list_head *iter;
93c52dd0 6707 u32 link_speed = adapter->link_speed;
454adb00 6708 const char *speed_str;
93c52dd0 6709 bool flow_rx, flow_tx;
e8e26350 6710
93c52dd0
AD		 6711 /* only continue if link was previously down */
6712 if (netif_carrier_ok(netdev))
a985b6c3 6713 return;
63d6e1d8 6714
93c52dd0 6715 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6716
93c52dd0
AD		 6717 switch (hw->mac.type) {
6718 case ixgbe_mac_82598EB: {
6719 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6720 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6721 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6722 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6723 }
6724 break;
6725 case ixgbe_mac_X540:
9a75a1ac
DS		 6726 case ixgbe_mac_X550:
6727 case ixgbe_mac_X550EM_x:
49425dfc 6728 case ixgbe_mac_x550em_a:
93c52dd0
AD		 6729 case ixgbe_mac_82599EB: {
6730 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6731 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6732 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6733 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6734 }
6735 break;
6736 default:
6737 flow_tx = false;
6738 flow_rx = false;
6739 break;
e8e26350 6740 }
3a6a4eda 6741
6cb562d6
JK		 6742 adapter->last_rx_ptp_check = jiffies;
6743
8fecf67c 6744 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6745 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6746
454adb00
MR		 6747 switch (link_speed) {
6748 case IXGBE_LINK_SPEED_10GB_FULL:
6749 speed_str = "10 Gbps";
6750 break;
6751 case IXGBE_LINK_SPEED_2_5GB_FULL:
6752 speed_str = "2.5 Gbps";
6753 break;
6754 case IXGBE_LINK_SPEED_1GB_FULL:
6755 speed_str = "1 Gbps";
6756 break;
6757 case IXGBE_LINK_SPEED_100_FULL:
6758 speed_str = "100 Mbps";
6759 break;
6760 default:
6761 speed_str = "unknown speed";
6762 break;
6763 }
6764 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6765 ((flow_rx && flow_tx) ? "RX/TX" :
6766 (flow_rx ? "RX" :
6767 (flow_tx ? "TX" : "None"))));
e8e26350 6768
93c52dd0 6769 netif_carrier_on(netdev);
93c52dd0 6770 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6771
cdc04dcc
ET		 6772 /* enable transmits */
6773 netif_tx_wake_all_queues(adapter->netdev);
6774
6775 /* enable any upper devices */
6776 rtnl_lock();
6777 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6778 if (netif_is_macvlan(upper)) {
6779 struct macvlan_dev *vlan = netdev_priv(upper);
6780
6781 if (vlan->fwd_priv)
6782 netif_tx_wake_all_queues(upper);
6783 }
6784 }
6785 rtnl_unlock();
6786
107d3018
AD		 6787 /* update the default user priority for VFs */
6788 ixgbe_update_default_up(adapter);
6789
befa2af7
AD		 6790 /* ping all the active vfs to let them know link has changed */
6791 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6792}
6793
c4cf55e5 6794/**
93c52dd0
AD		 6795 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6796 * print link down message
49ce9c2c 6797 * @adapter: pointer to the adapter structure
c4cf55e5 6798 **/
581330ba 6799static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6800{
cf8280ee 6801 struct net_device *netdev = adapter->netdev;
c4cf55e5 6802 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6803
93c52dd0
AD		 6804 adapter->link_up = false;
6805 adapter->link_speed = 0;
cf8280ee 6806
93c52dd0
AD		 6807 /* only continue if link was up previously */
6808 if (!netif_carrier_ok(netdev))
6809 return;
264857b8 6810
93c52dd0
AD		 6811 /* poll for SFP+ cable when link is down */
6812 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6813 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6814
8fecf67c 6815 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6816 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6817
93c52dd0
AD		 6818 e_info(drv, "NIC Link is Down\n");
6819 netif_carrier_off(netdev);
befa2af7
AD		 6820
6821 /* ping all the active vfs to let them know link has changed */
6822 ixgbe_ping_all_vfs(adapter);
93c52dd0 6823}
e8e26350 6824
07923c17
ET		 6825static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6826{
6827 int i;
6828
6829 for (i = 0; i < adapter->num_tx_queues; i++) {
6830 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6831
6832 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6833 return true;
6834 }
6835
6836 return false;
6837}
6838
6839static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6840{
6841 struct ixgbe_hw *hw = &adapter->hw;
6842 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6843 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6844
6845 int i, j;
6846
6847 if (!adapter->num_vfs)
6848 return false;
6849
9a75a1ac
DS		 6850 /* resetting the PF is only needed for MAC before X550 */
6851 if (hw->mac.type >= ixgbe_mac_X550)
6852 return false;
6853
07923c17
ET		 6854 for (i = 0; i < adapter->num_vfs; i++) {
6855 for (j = 0; j < q_per_pool; j++) {
6856 u32 h, t;
6857
6858 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6859 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6860
6861 if (h != t)
6862 return true;
6863 }
6864 }
6865
6866 return false;
6867}
6868
93c52dd0
AD		 6869/**
6870 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6871 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6872 **/
6873static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6874{
93c52dd0 6875 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6876 if (ixgbe_ring_tx_pending(adapter) ||
6877 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6878 /* We've lost link, so the controller stops DMA,
6879 * but we've got queued Tx work that's never going
6880 * to get done, so reset controller to flush Tx.
6881 * (Do the reset outside of interrupt context).
6882 */
12ff3f3b 6883 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6884 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6885 }
c4cf55e5 6886 }
c4cf55e5
PWJ		 6887}
6888
9079e416
ET		 6889#ifdef CONFIG_PCI_IOV
6890static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6891 struct pci_dev *vfdev)
6892{
6893 if (!pci_wait_for_pending_transaction(vfdev))
6894 e_dev_warn("Issuing VFLR with pending transactions\n");
6895
6896 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6897 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6898
6899 msleep(100);
6900}
6901
6902static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6903{
6904 struct ixgbe_hw *hw = &adapter->hw;
6905 struct pci_dev *pdev = adapter->pdev;
988d1307 6906 unsigned int vf;
9079e416 6907 u32 gpc;
9079e416
ET		 6908
6909 if (!(netif_carrier_ok(adapter->netdev)))
6910 return;
6911
6912 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6913 if (gpc) /* If incrementing then no need for the check below */
6914 return;
6915 /* Check to see if a bad DMA write target from an errant or
6916 * malicious VF has caused a PCIe error. If so then we can
6917 * issue a VFLR to the offending VF(s) and then resume without
6918 * requesting a full slot reset.
6919 */
6920
6921 if (!pdev)
6922 return;
6923
9079e416 6924 /* check status reg for all VFs owned by this PF */
988d1307
MR		 6925 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6926 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6927 u16 status_reg;
9079e416 6928
988d1307
MR		 6929 if (!vfdev)
6930 continue;
6931 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6932 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6933 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6934 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 6935 }
6936}
6937
a985b6c3
GR		 6938static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6939{
6940 u32 ssvpc;
6941
0584d999
GR		 6942 /* Do not perform spoof check for 82598 or if not in IOV mode */
6943 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6944 adapter->num_vfs == 0)
a985b6c3
GR		 6945 return;
6946
6947 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6948
6949 /*
6950 * ssvpc register is cleared on read, if zero then no
6951 * spoofed packets in the last interval.
6952 */
6953 if (!ssvpc)
6954 return;
6955
d6ea0754 6956 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6957}
9079e416
ET		 6958#else
6959static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6960{
6961}
6962
6963static void
6964ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6965{
6966}
6967#endif /* CONFIG_PCI_IOV */
6968
a985b6c3 6969
93c52dd0
AD		 6970/**
6971 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6972 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6973 **/
6974static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6975{
09f40aed 6976 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6977 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6978 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6979 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6980 return;
6981
6982 ixgbe_watchdog_update_link(adapter);
6983
6984 if (adapter->link_up)
6985 ixgbe_watchdog_link_is_up(adapter);
6986 else
6987 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6988
9079e416 6989 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6990 ixgbe_spoof_check(adapter);
9a799d71 6991 ixgbe_update_stats(adapter);
93c52dd0
AD		 6992
6993 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6994}
10eec955 6995
cf8280ee 6996/**
7086400d 6997 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6998 * @adapter: the ixgbe adapter structure
cf8280ee 6999 **/
7086400d 7000static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 7001{
cf8280ee 7002 struct ixgbe_hw *hw = &adapter->hw;
7086400d 7003 s32 err;
cf8280ee 7004
7086400d
AD		 7005 /* not searching for SFP so there is nothing to do here */
7006 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7007 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7008 return;
10eec955 7009
58e7cd24
MR		 7010 if (adapter->sfp_poll_time &&
7011 time_after(adapter->sfp_poll_time, jiffies))
7012 return; /* If not yet time to poll for SFP */
7013
7086400d
AD		 7014 /* someone else is in init, wait until next service event */
7015 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7016 return;
cf8280ee 7017
58e7cd24
MR		 7018 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7019
7086400d
AD		 7020 err = hw->phy.ops.identify_sfp(hw);
7021 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7022 goto sfp_out;
264857b8 7023
7086400d
AD		 7024 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7025 /* If no cable is present, then we need to reset
7026 * the next time we find a good cable. */
7027 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 7028 }
9a799d71 7029
7086400d
AD		 7030 /* exit on error */
7031 if (err)
7032 goto sfp_out;
e8e26350 7033
7086400d
AD		 7034 /* exit if reset not needed */
7035 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7036 goto sfp_out;
9a799d71 7037
7086400d 7038 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 7039
7086400d
AD		 7040 /*
7041 * A module may be identified correctly, but the EEPROM may not have
7042 * support for that module. setup_sfp() will fail in that case, so
7043 * we should not allow that module to load.
7044 */
7045 if (hw->mac.type == ixgbe_mac_82598EB)
7046 err = hw->phy.ops.reset(hw);
7047 else
7048 err = hw->mac.ops.setup_sfp(hw);
7049
7050 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7051 goto sfp_out;
7052
7053 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7054 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7055
7056sfp_out:
7057 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7058
7059 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7060 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7061 e_dev_err("failed to initialize because an unsupported "
7062 "SFP+ module type was detected.\n");
7063 e_dev_err("Reload the driver after installing a "
7064 "supported module.\n");
7065 unregister_netdev(adapter->netdev);
bc59fcda 7066 }
7086400d 7067}
bc59fcda 7068
7086400d
AD		 7069/**
7070 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7071 * @adapter: the ixgbe adapter structure
7086400d
AD		 7072 **/
7073static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7074{
7075 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7076 u32 speed;
7077 bool autoneg = false;
7086400d
AD		 7078
7079 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7080 return;
7081
7082 /* someone else is in init, wait until next service event */
7083 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7084 return;
7085
7086 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7087
3d292265 7088 speed = hw->phy.autoneg_advertised;
ed33ff66 7089 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7090 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7091
7092 /* setup the highest link when no autoneg */
7093 if (!autoneg) {
7094 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7095 speed = IXGBE_LINK_SPEED_10GB_FULL;
7096 }
7097 }
7098
7086400d 7099 if (hw->mac.ops.setup_link)
fd0326f2 7100 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7101
7102 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7103 adapter->link_check_timeout = jiffies;
7104 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7105}
7106
7107/**
7108 * ixgbe_service_timer - Timer Call-back
7109 * @data: pointer to adapter cast into an unsigned long
7110 **/
7111static void ixgbe_service_timer(unsigned long data)
7112{
7113 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7114 unsigned long next_event_offset;
7115
6bb78cfb
AD		 7116 /* poll faster when waiting for link */
7117 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7118 next_event_offset = HZ / 10;
7119 else
7120 next_event_offset = HZ * 2;
83c61fa9 7121
7086400d
AD		 7122 /* Reset the timer */
7123 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7124
9079e416 7125 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7126}
7127
597f22d6
DS		 7128static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7129{
7130 struct ixgbe_hw *hw = &adapter->hw;
7131 u32 status;
7132
7133 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7134 return;
7135
7136 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7137
7138 if (!hw->phy.ops.handle_lasi)
7139 return;
7140
7141 status = hw->phy.ops.handle_lasi(&adapter->hw);
7142 if (status != IXGBE_ERR_OVERTEMP)
7143 return;
7144
7145 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7146}
7147
c83c6cbd
AD		 7148static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7149{
7150 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7151 return;
7152
7153 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7154
09f40aed 7155 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7156 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7157 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7158 test_bit(__IXGBE_RESETTING, &adapter->state))
7159 return;
7160
7161 ixgbe_dump(adapter);
7162 netdev_err(adapter->netdev, "Reset adapter\n");
7163 adapter->tx_timeout_count++;
7164
8f4c5c9f 7165 rtnl_lock();
c83c6cbd 7166 ixgbe_reinit_locked(adapter);
8f4c5c9f 7167 rtnl_unlock();
c83c6cbd
AD		 7168}
7169
7086400d
AD		 7170/**
7171 * ixgbe_service_task - manages and runs subtasks
7172 * @work: pointer to work_struct containing our data
7173 **/
7174static void ixgbe_service_task(struct work_struct *work)
7175{
7176 struct ixgbe_adapter *adapter = container_of(work,
7177 struct ixgbe_adapter,
7178 service_task);
b0483c8f
MR		 7179 if (ixgbe_removed(adapter->hw.hw_addr)) {
7180 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7181 rtnl_lock();
7182 ixgbe_down(adapter);
7183 rtnl_unlock();
7184 }
7185 ixgbe_service_event_complete(adapter);
7186 return;
7187 }
67359c3c
MR		 7188#ifdef CONFIG_IXGBE_VXLAN
7189 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7190 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7191 vxlan_get_rx_port(adapter->netdev);
7192 }
7193#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 7194 ixgbe_reset_subtask(adapter);
597f22d6 7195 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7196 ixgbe_sfp_detection_subtask(adapter);
7197 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7198 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7199 ixgbe_watchdog_subtask(adapter);
d034acf1 7200 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7201 ixgbe_check_hang_subtask(adapter);
891dc082 7202
8fecf67c 7203 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7204 ixgbe_ptp_overflow_check(adapter);
7205 ixgbe_ptp_rx_hang(adapter);
7206 }
7086400d
AD		 7207
7208 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7209}
7210
fd0db0ed
AD		 7211static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7212 struct ixgbe_tx_buffer *first,
244e27ad 7213 u8 *hdr_len)
897ab156 7214{
fd0db0ed 7215 struct sk_buff *skb = first->skb;
897ab156
AD		 7216 u32 vlan_macip_lens, type_tucmd;
7217 u32 mss_l4len_idx, l4len;
2049e1f6 7218 int err;
9a799d71 7219
8f4fbb9b
AD		 7220 if (skb->ip_summed != CHECKSUM_PARTIAL)
7221 return 0;
7222
897ab156
AD		 7223 if (!skb_is_gso(skb))
7224 return 0;
9a799d71 7225
2049e1f6
FR		 7226 err = skb_cow_head(skb, 0);
7227 if (err < 0)
7228 return err;
9a799d71 7229
897ab156
AD		 7230 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7231 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7232
a1108ffd 7233 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 7234 struct iphdr *iph = ip_hdr(skb);
7235 iph->tot_len = 0;
7236 iph->check = 0;
7237 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7238 iph->daddr, 0,
7239 IPPROTO_TCP,
7240 0);
7241 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 7242 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7243 IXGBE_TX_FLAGS_CSUM |
7244 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 7245 } else if (skb_is_gso_v6(skb)) {
7246 ipv6_hdr(skb)->payload_len = 0;
7247 tcp_hdr(skb)->check =
7248 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7249 &ipv6_hdr(skb)->daddr,
7250 0, IPPROTO_TCP, 0);
244e27ad
AD		 7251 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7252 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7253 }
7254
091a6246 7255 /* compute header lengths */
897ab156
AD		 7256 l4len = tcp_hdrlen(skb);
7257 *hdr_len = skb_transport_offset(skb) + l4len;
7258
091a6246
AD		 7259 /* update gso size and bytecount with header size */
7260 first->gso_segs = skb_shinfo(skb)->gso_segs;
7261 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7262
c44f5f51 7263 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 7264 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7265 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7266
7267 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7268 vlan_macip_lens = skb_network_header_len(skb);
7269 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7270 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7271
7272 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7273 mss_l4len_idx);
897ab156
AD		 7274
7275 return 1;
7276}
7277
49763de0
AD		 7278static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7279{
7280 unsigned int offset = 0;
7281
7282 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7283
7284 return offset == skb_checksum_start_offset(skb);
7285}
7286
244e27ad
AD		 7287static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7288 struct ixgbe_tx_buffer *first)
7ca647bd 7289{
fd0db0ed 7290 struct sk_buff *skb = first->skb;
897ab156 7291 u32 vlan_macip_lens = 0;
897ab156 7292 u32 type_tucmd = 0;
7ca647bd 7293
897ab156 7294 if (skb->ip_summed != CHECKSUM_PARTIAL) {
49763de0
AD		 7295csum_failed:
7296 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7297 IXGBE_TX_FLAGS_CC)))
472148c3 7298 return;
49763de0
AD		 7299 goto no_csum;
7300 }
897ab156 7301
49763de0
AD		 7302 switch (skb->csum_offset) {
7303 case offsetof(struct tcphdr, check):
7304 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7305 /* fall through */
7306 case offsetof(struct udphdr, check):
7307 break;
7308 case offsetof(struct sctphdr, checksum):
7309 /* validate that this is actually an SCTP request */
7310 if (((first->protocol == htons(ETH_P_IP)) &&
7311 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7312 ((first->protocol == htons(ETH_P_IPV6)) &&
7313 ixgbe_ipv6_csum_is_sctp(skb))) {
7314 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
897ab156 7315 break;
7ca647bd 7316 }
49763de0
AD		 7317 /* fall through */
7318 default:
7319 skb_checksum_help(skb);
7320 goto csum_failed;
7ca647bd
JP		 7321 }
7322
49763de0
AD		 7323 /* update TX checksum flag */
7324 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7325 vlan_macip_lens = skb_checksum_start_offset(skb) -
7326 skb_network_offset(skb);
36a92d71 7327no_csum:
244e27ad 7328 /* vlan_macip_lens: MACLEN, VLAN tag */
49763de0 7329 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7330 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7331
49763de0 7332 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
9a799d71
AK		 7333}
7334
472148c3
AD		 7335#define IXGBE_SET_FLAG(_input, _flag, _result) \
7336 ((_flag <= _result) ? \
7337 ((u32)(_input & _flag) * (_result / _flag)) : \
7338 ((u32)(_input & _flag) / (_flag / _result)))
7339
7340static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7341{
d3d00239 7342 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7343 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7344 IXGBE_ADVTXD_DCMD_DEXT |
7345 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7346
d3d00239 7347 /* set HW vlan bit if vlan is present */
472148c3
AD		 7348 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7349 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7350
d3d00239 7351 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7352 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7353 IXGBE_ADVTXD_DCMD_TSE);
7354
7355 /* set timestamp bit if present */
7356 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7357 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7358
62748b7b 7359 /* insert frame checksum */
472148c3 7360 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7361
d3d00239
AD		 7362 return cmd_type;
7363}
9a799d71 7364
729739b7
AD		 7365static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7366 u32 tx_flags, unsigned int paylen)
d3d00239 7367{
472148c3 7368 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7369
d3d00239 7370 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7371 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7372 IXGBE_TX_FLAGS_CSUM,
7373 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7374
93f5b3c1 7375 /* enble IPv4 checksum for TSO */
472148c3
AD		 7376 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7377 IXGBE_TX_FLAGS_IPV4,
7378 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7379
7f9643fd
AD		 7380 /*
7381 * Check Context must be set if Tx switch is enabled, which it
7382 * always is for case where virtual functions are running
7383 */
472148c3
AD		 7384 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7385 IXGBE_TX_FLAGS_CC,
7386 IXGBE_ADVTXD_CC);
7f9643fd 7387
472148c3 7388 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7389}
44df32c5 7390
2367a173
DB		 7391static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7392{
7393 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7394
7395 /* Herbert's original patch had:
7396 * smp_mb__after_netif_stop_queue();
7397 * but since that doesn't exist yet, just open code it.
7398 */
7399 smp_mb();
7400
7401 /* We need to check again in a case another CPU has just
7402 * made room available.
7403 */
7404 if (likely(ixgbe_desc_unused(tx_ring) < size))
7405 return -EBUSY;
7406
7407 /* A reprieve! - use start_queue because it doesn't call schedule */
7408 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7409 ++tx_ring->tx_stats.restart_queue;
7410 return 0;
7411}
7412
7413static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7414{
7415 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7416 return 0;
7417
7418 return __ixgbe_maybe_stop_tx(tx_ring, size);
7419}
7420
d3d00239
AD		 7421#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7422 IXGBE_TXD_CMD_RS)
7423
7424static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7425 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7426 const u8 hdr_len)
7427{
fd0db0ed 7428 struct sk_buff *skb = first->skb;
729739b7 7429 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7430 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7431 struct skb_frag_struct *frag;
7432 dma_addr_t dma;
7433 unsigned int data_len, size;
244e27ad 7434 u32 tx_flags = first->tx_flags;
472148c3 7435 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7436 u16 i = tx_ring->next_to_use;
d3d00239 7437
729739b7
AD		 7438 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7439
ec718254
AD		 7440 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7441
7442 size = skb_headlen(skb);
7443 data_len = skb->data_len;
729739b7 7444
d3d00239
AD		 7445#ifdef IXGBE_FCOE
7446 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7447 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7448 size -= sizeof(struct fcoe_crc_eof) - data_len;
7449 data_len = 0;
729739b7
AD		 7450 } else {
7451 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7452 }
7453 }
44df32c5 7454
d3d00239 7455#endif
729739b7 7456 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7457
ec718254 7458 tx_buffer = first;
9a799d71 7459
ec718254
AD		 7460 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7461 if (dma_mapping_error(tx_ring->dev, dma))
7462 goto dma_error;
7463
7464 /* record length, and DMA address */
7465 dma_unmap_len_set(tx_buffer, len, size);
7466 dma_unmap_addr_set(tx_buffer, dma, dma);
7467
7468 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7469
729739b7 7470 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7471 tx_desc->read.cmd_type_len =
472148c3 7472 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7473
d3d00239 7474 i++;
729739b7 7475 tx_desc++;
d3d00239 7476 if (i == tx_ring->count) {
e4f74028 7477 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7478 i = 0;
7479 }
ec718254 7480 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7481
7482 dma += IXGBE_MAX_DATA_PER_TXD;
7483 size -= IXGBE_MAX_DATA_PER_TXD;
7484
7485 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7486 }
e5a43549 7487
729739b7
AD		 7488 if (likely(!data_len))
7489 break;
9a799d71 7490
472148c3 7491 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7492
729739b7
AD		 7493 i++;
7494 tx_desc++;
7495 if (i == tx_ring->count) {
7496 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7497 i = 0;
7498 }
ec718254 7499 tx_desc->read.olinfo_status = 0;
9a799d71 7500
d3d00239 7501#ifdef IXGBE_FCOE
9e903e08 7502 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7503#else
9e903e08 7504 size = skb_frag_size(frag);
d3d00239
AD		 7505#endif
7506 data_len -= size;
9a799d71 7507
729739b7
AD		 7508 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7509 DMA_TO_DEVICE);
9a799d71 7510
729739b7 7511 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7512 }
9a799d71 7513
729739b7 7514 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7515 cmd_type |= size | IXGBE_TXD_CMD;
7516 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7517
091a6246 7518 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7519
d3d00239
AD		 7520 /* set the timestamp */
7521 first->time_stamp = jiffies;
9a799d71
AK		 7522
7523 /*
729739b7
AD		 7524 * Force memory writes to complete before letting h/w know there
7525 * are new descriptors to fetch. (Only applicable for weak-ordered
7526 * memory model archs, such as IA-64).
7527 *
7528 * We also need this memory barrier to make certain all of the
7529 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7530 */
7531 wmb();
7532
d3d00239
AD		 7533 /* set next_to_watch value indicating a packet is present */
7534 first->next_to_watch = tx_desc;
7535
729739b7
AD		 7536 i++;
7537 if (i == tx_ring->count)
7538 i = 0;
7539
7540 tx_ring->next_to_use = i;
7541
2367a173
DB		 7542 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7543
7544 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7545 writel(i, tx_ring->tail);
7546
7547 /* we need this if more than one processor can write to our tail
7548 * at a time, it synchronizes IO on IA64/Altix systems
7549 */
7550 mmiowb();
9c938cdd 7551 }
2367a173 7552
d3d00239
AD		 7553 return;
7554dma_error:
729739b7 7555 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7556
7557 /* clear dma mappings for failed tx_buffer_info map */
7558 for (;;) {
729739b7
AD		 7559 tx_buffer = &tx_ring->tx_buffer_info[i];
7560 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7561 if (tx_buffer == first)
d3d00239
AD		 7562 break;
7563 if (i == 0)
7564 i = tx_ring->count;
7565 i--;
7566 }
7567
d3d00239 7568 tx_ring->next_to_use = i;
9a799d71
AK		 7569}
7570
fd0db0ed 7571static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7572 struct ixgbe_tx_buffer *first)
69830529
AD		 7573{
7574 struct ixgbe_q_vector *q_vector = ring->q_vector;
7575 union ixgbe_atr_hash_dword input = { .dword = 0 };
7576 union ixgbe_atr_hash_dword common = { .dword = 0 };
7577 union {
7578 unsigned char *network;
7579 struct iphdr *ipv4;
7580 struct ipv6hdr *ipv6;
7581 } hdr;
ee9e0f0b 7582 struct tcphdr *th;
e2873d43 7583 unsigned int hlen;
67359c3c 7584 struct sk_buff *skb;
905e4a41 7585 __be16 vlan_id;
e2873d43 7586 int l4_proto;
c4cf55e5 7587
69830529
AD		 7588 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7589 if (!q_vector)
7590 return;
7591
7592 /* do nothing if sampling is disabled */
7593 if (!ring->atr_sample_rate)
d3ead241 7594 return;
c4cf55e5 7595
69830529 7596 ring->atr_count++;
c4cf55e5 7597
e2873d43
AD		 7598 /* currently only IPv4/IPv6 with TCP is supported */
7599 if ((first->protocol != htons(ETH_P_IP)) &&
7600 (first->protocol != htons(ETH_P_IPV6)))
7601 return;
7602
69830529 7603 /* snag network header to get L4 type and address */
67359c3c
MR		 7604 skb = first->skb;
7605 hdr.network = skb_network_header(skb);
67359c3c 7606#ifdef CONFIG_IXGBE_VXLAN
9f12df90
AD		 7607 if (skb->encapsulation &&
7608 first->protocol == htons(ETH_P_IP) &&
7609 hdr.ipv4->protocol != IPPROTO_UDP) {
67359c3c 7610 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7611
9f12df90
AD		 7612 /* verify the port is recognized as VXLAN */
7613 if (adapter->vxlan_port &&
e2873d43 7614 udp_hdr(skb)->dest == adapter->vxlan_port)
9f12df90 7615 hdr.network = skb_inner_network_header(skb);
e19dcdeb 7616 }
9f12df90 7617#endif /* CONFIG_IXGBE_VXLAN */
e19dcdeb
MR		 7618
7619 /* Currently only IPv4/IPv6 with TCP is supported */
7620 switch (hdr.ipv4->version) {
7621 case IPVERSION:
e2873d43
AD		 7622 /* access ihl as u8 to avoid unaligned access on ia64 */
7623 hlen = (hdr.network[0] & 0x0F) << 2;
7624 l4_proto = hdr.ipv4->protocol;
e19dcdeb
MR		 7625 break;
7626 case 6:
e2873d43
AD		 7627 hlen = hdr.network - skb->data;
7628 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7629 hlen -= hdr.network - skb->data;
e19dcdeb
MR		 7630 break;
7631 default:
7632 return;
67359c3c 7633 }
c4cf55e5 7634
e2873d43
AD		 7635 if (l4_proto != IPPROTO_TCP)
7636 return;
7637
7638 th = (struct tcphdr *)(hdr.network + hlen);
7639
7640 /* skip this packet since the socket is closing */
7641 if (th->fin)
69830529
AD		 7642 return;
7643
7644 /* sample on all syn packets or once every atr sample count */
7645 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7646 return;
7647
7648 /* reset sample count */
7649 ring->atr_count = 0;
7650
244e27ad 7651 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7652
7653 /*
7654 * src and dst are inverted, think how the receiver sees them
7655 *
7656 * The input is broken into two sections, a non-compressed section
7657 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7658 * is XORed together and stored in the compressed dword.
7659 */
7660 input.formatted.vlan_id = vlan_id;
7661
7662 /*
7663 * since src port and flex bytes occupy the same word XOR them together
7664 * and write the value to source port portion of compressed dword
7665 */
244e27ad 7666 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7667 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7668 else
244e27ad 7669 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7670 common.port.dst ^= th->source;
7671
e19dcdeb
MR		 7672 switch (hdr.ipv4->version) {
7673 case IPVERSION:
69830529
AD		 7674 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7675 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 7676 break;
7677 case 6:
69830529
AD		 7678 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7679 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7680 hdr.ipv6->saddr.s6_addr32[1] ^
7681 hdr.ipv6->saddr.s6_addr32[2] ^
7682 hdr.ipv6->saddr.s6_addr32[3] ^
7683 hdr.ipv6->daddr.s6_addr32[0] ^
7684 hdr.ipv6->daddr.s6_addr32[1] ^
7685 hdr.ipv6->daddr.s6_addr32[2] ^
7686 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 7687 break;
7688 default:
7689 break;
69830529 7690 }
c4cf55e5 7691
9f12df90 7692 if (hdr.network != skb_network_header(skb))
67359c3c 7693 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 7694
c4cf55e5 7695 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7696 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7697 input, common, ring->queue_index);
c4cf55e5
PWJ		 7698}
7699
f663dd9a 7700static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7701 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7702{
f663dd9a
JW		 7703 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7704#ifdef IXGBE_FCOE
97488bd1
AD		 7705 struct ixgbe_adapter *adapter;
7706 struct ixgbe_ring_feature *f;
7707 int txq;
f663dd9a
JW		 7708#endif
7709
7710 if (fwd_adapter)
7711 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7712
7713#ifdef IXGBE_FCOE
5e09a105 7714
97488bd1
AD		 7715 /*
7716 * only execute the code below if protocol is FCoE
7717 * or FIP and we have FCoE enabled on the adapter
7718 */
7719 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7720 case htons(ETH_P_FCOE):
7721 case htons(ETH_P_FIP):
97488bd1 7722 adapter = netdev_priv(dev);
c087663e 7723
97488bd1
AD		 7724 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7725 break;
7726 default:
99932d4f 7727 return fallback(dev, skb);
97488bd1 7728 }
c087663e 7729
97488bd1 7730 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7731
97488bd1
AD		 7732 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7733 smp_processor_id();
56075a98 7734
97488bd1
AD		 7735 while (txq >= f->indices)
7736 txq -= f->indices;
c4cf55e5 7737
97488bd1 7738 return txq + f->offset;
f663dd9a 7739#else
99932d4f 7740 return fallback(dev, skb);
f663dd9a 7741#endif
09a3b1f8
SH		 7742}
7743
fc77dc3c 7744netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7745 struct ixgbe_adapter *adapter,
7746 struct ixgbe_ring *tx_ring)
9a799d71 7747{
d3d00239 7748 struct ixgbe_tx_buffer *first;
5f715823 7749 int tso;
d3d00239 7750 u32 tx_flags = 0;
a535c30e 7751 unsigned short f;
a535c30e 7752 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7753 __be16 protocol = skb->protocol;
63544e9c 7754 u8 hdr_len = 0;
5e09a105 7755
a535c30e
AD		 7756 /*
7757 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7758 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7759 * + 2 desc gap to keep tail from touching head,
7760 * + 1 desc for context descriptor,
7761 * otherwise try next time
7762 */
a535c30e
AD		 7763 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7764 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7765
a535c30e
AD		 7766 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7767 tx_ring->tx_stats.tx_busy++;
7768 return NETDEV_TX_BUSY;
7769 }
7770
fd0db0ed
AD		 7771 /* record the location of the first descriptor for this packet */
7772 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7773 first->skb = skb;
091a6246
AD		 7774 first->bytecount = skb->len;
7775 first->gso_segs = 1;
fd0db0ed 7776
66f32a8b 7777 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7778 if (skb_vlan_tag_present(skb)) {
7779 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7780 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7781 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7782 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7783 struct vlan_hdr *vhdr, _vhdr;
7784 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7785 if (!vhdr)
7786 goto out_drop;
7787
9e0c5648
AD		 7788 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7789 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7790 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7791 }
0213668f 7792 protocol = vlan_get_protocol(skb);
66f32a8b 7793
d5234933
MR		 7794 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7795 adapter->ptp_clock &&
7796 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7797 &adapter->state)) {
3a6a4eda
JK		 7798 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7799 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7800
7801 /* schedule check for Tx timestamp */
7802 adapter->ptp_tx_skb = skb_get(skb);
7803 adapter->ptp_tx_start = jiffies;
7804 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7805 }
3a6a4eda 7806
ff29a86e
JK		 7807 skb_tx_timestamp(skb);
7808
9e0c5648
AD		 7809#ifdef CONFIG_PCI_IOV
7810 /*
7811 * Use the l2switch_enable flag - would be false if the DMA
7812 * Tx switch had been disabled.
7813 */
7814 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7815 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7816
7817#endif
32701dc2 7818 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7819 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7820 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7821 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7822 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7823 tx_flags |= (skb->priority & 0x7) <<
7824 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7825 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7826 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7827
7828 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7829 goto out_drop;
7830 vhdr = (struct vlan_ethhdr *)skb->data;
7831 vhdr->h_vlan_TCI = htons(tx_flags >>
7832 IXGBE_TX_FLAGS_VLAN_SHIFT);
7833 } else {
7834 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7835 }
9a799d71 7836 }
eacd73f7 7837
244e27ad
AD		 7838 /* record initial flags and protocol */
7839 first->tx_flags = tx_flags;
7840 first->protocol = protocol;
7841
eacd73f7 7842#ifdef IXGBE_FCOE
66f32a8b 7843 /* setup tx offload for FCoE */
a1108ffd 7844 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7845 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7846 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7847 if (tso < 0)
7848 goto out_drop;
9a799d71 7849
66f32a8b 7850 goto xmit_fcoe;
eacd73f7 7851 }
9a799d71 7852
66f32a8b 7853#endif /* IXGBE_FCOE */
244e27ad 7854 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7855 if (tso < 0)
897ab156 7856 goto out_drop;
244e27ad
AD		 7857 else if (!tso)
7858 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7859
7860 /* add the ATR filter if ATR is on */
7861 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7862 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7863
7864#ifdef IXGBE_FCOE
7865xmit_fcoe:
7866#endif /* IXGBE_FCOE */
244e27ad 7867 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7868
9a799d71 7869 return NETDEV_TX_OK;
897ab156
AD		 7870
7871out_drop:
fd0db0ed
AD		 7872 dev_kfree_skb_any(first->skb);
7873 first->skb = NULL;
7874
897ab156 7875 return NETDEV_TX_OK;
9a799d71
AK		 7876}
7877
2a47fa45
JF		 7878static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7879 struct net_device *netdev,
7880 struct ixgbe_ring *ring)
84418e3b
AD		 7881{
7882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7883 struct ixgbe_ring *tx_ring;
7884
a50c29dd
AD		 7885 /*
7886 * The minimum packet size for olinfo paylen is 17 so pad the skb
7887 * in order to meet this minimum size requirement.
7888 */
a94d9e22
AD		 7889 if (skb_put_padto(skb, 17))
7890 return NETDEV_TX_OK;
a50c29dd 7891
2a47fa45
JF		 7892 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7893
fc77dc3c 7894 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7895}
7896
2a47fa45
JF		 7897static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7898 struct net_device *netdev)
7899{
7900 return __ixgbe_xmit_frame(skb, netdev, NULL);
7901}
7902
9a799d71
AK		 7903/**
7904 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7905 * @netdev: network interface device structure
7906 * @p: pointer to an address structure
7907 *
7908 * Returns 0 on success, negative on failure
7909 **/
7910static int ixgbe_set_mac(struct net_device *netdev, void *p)
7911{
7912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7913 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7914 struct sockaddr *addr = p;
7915
7916 if (!is_valid_ether_addr(addr->sa_data))
7917 return -EADDRNOTAVAIL;
7918
7919 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7920 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7921
c9f53e63
AD		 7922 ixgbe_mac_set_default_filter(adapter);
7923
7924 return 0;
9a799d71
AK		 7925}
7926
6b73e10d
BH		 7927static int
7928ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7929{
7930 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7931 struct ixgbe_hw *hw = &adapter->hw;
7932 u16 value;
7933 int rc;
7934
7935 if (prtad != hw->phy.mdio.prtad)
7936 return -EINVAL;
7937 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7938 if (!rc)
7939 rc = value;
7940 return rc;
7941}
7942
7943static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7944 u16 addr, u16 value)
7945{
7946 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7947 struct ixgbe_hw *hw = &adapter->hw;
7948
7949 if (prtad != hw->phy.mdio.prtad)
7950 return -EINVAL;
7951 return hw->phy.ops.write_reg(hw, addr, devad, value);
7952}
7953
7954static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7955{
7956 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7957
3a6a4eda 7958 switch (cmd) {
3a6a4eda 7959 case SIOCSHWTSTAMP:
93501d48
JK		 7960 return ixgbe_ptp_set_ts_config(adapter, req);
7961 case SIOCGHWTSTAMP:
7962 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7963 default:
7964 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7965 }
6b73e10d
BH		 7966}
7967
0365e6e4
PW		 7968/**
7969 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7970 * netdev->dev_addrs
0365e6e4
PW		 7971 * @netdev: network interface device structure
7972 *
7973 * Returns non-zero on failure
7974 **/
7975static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7976{
7977 int err = 0;
7978 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7979 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7980
7fa7c9dc 7981 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7982 rtnl_lock();
7fa7c9dc 7983 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7984 rtnl_unlock();
7fa7c9dc
AD		 7985
7986 /* update SAN MAC vmdq pool selection */
7987 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7988 }
7989 return err;
7990}
7991
7992/**
7993 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7994 * netdev->dev_addrs
0365e6e4
PW		 7995 * @netdev: network interface device structure
7996 *
7997 * Returns non-zero on failure
7998 **/
7999static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8000{
8001 int err = 0;
8002 struct ixgbe_adapter *adapter = netdev_priv(dev);
8003 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8004
8005 if (is_valid_ether_addr(mac->san_addr)) {
8006 rtnl_lock();
8007 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8008 rtnl_unlock();
8009 }
8010 return err;
8011}
8012
9a799d71
AK		 8013#ifdef CONFIG_NET_POLL_CONTROLLER
8014/*
8015 * Polling 'interrupt' - used by things like netconsole to send skbs
8016 * without having to re-enable interrupts. It's not called while
8017 * the interrupt routine is executing.
8018 */
8019static void ixgbe_netpoll(struct net_device *netdev)
8020{
8021 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8022 int i;
9a799d71 8023
1a647bd2
AD		 8024 /* if interface is down do nothing */
8025 if (test_bit(__IXGBE_DOWN, &adapter->state))
8026 return;
8027
856f606e
AD		 8028 /* loop through and schedule all active queues */
8029 for (i = 0; i < adapter->num_q_vectors; i++)
8030 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8031}
9a799d71 8032
581330ba 8033#endif
de1036b1
ED		 8034static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8035 struct rtnl_link_stats64 *stats)
8036{
8037 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8038 int i;
8039
1a51502b 8040 rcu_read_lock();
de1036b1 8041 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8042 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8043 u64 bytes, packets;
8044 unsigned int start;
8045
1a51502b
ED		 8046 if (ring) {
8047 do {
57a7744e 8048 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8049 packets = ring->stats.packets;
8050 bytes = ring->stats.bytes;
57a7744e 8051 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8052 stats->rx_packets += packets;
8053 stats->rx_bytes += bytes;
8054 }
de1036b1 8055 }
1ac9ad13
ED		 8056
8057 for (i = 0; i < adapter->num_tx_queues; i++) {
8058 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8059 u64 bytes, packets;
8060 unsigned int start;
8061
8062 if (ring) {
8063 do {
57a7744e 8064 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8065 packets = ring->stats.packets;
8066 bytes = ring->stats.bytes;
57a7744e 8067 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8068 stats->tx_packets += packets;
8069 stats->tx_bytes += bytes;
8070 }
8071 }
1a51502b 8072 rcu_read_unlock();
de1036b1
ED		 8073 /* following stats updated by ixgbe_watchdog_task() */
8074 stats->multicast = netdev->stats.multicast;
8075 stats->rx_errors = netdev->stats.rx_errors;
8076 stats->rx_length_errors = netdev->stats.rx_length_errors;
8077 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8078 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8079 return stats;
8080}
8081
8af3c33f 8082#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8083/**
8084 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8085 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8086 * @tc: number of traffic classes currently enabled
8087 *
8088 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8089 * 802.1Q priority maps to a packet buffer that exists.
8090 */
8091static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8092{
8093 struct ixgbe_hw *hw = &adapter->hw;
8094 u32 reg, rsave;
8095 int i;
8096
8097 /* 82598 have a static priority to TC mapping that can not
8098 * be changed so no validation is needed.
8099 */
8100 if (hw->mac.type == ixgbe_mac_82598EB)
8101 return;
8102
8103 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8104 rsave = reg;
8105
8106 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8107 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8108
8109 /* If up2tc is out of bounds default to zero */
8110 if (up2tc > tc)
8111 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8112 }
8113
8114 if (reg != rsave)
8115 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8116
8117 return;
8118}
8119
02debdc9
AD		 8120/**
8121 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8122 * @adapter: Pointer to adapter struct
8123 *
8124 * Populate the netdev user priority to tc map
8125 */
8126static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8127{
8128 struct net_device *dev = adapter->netdev;
8129 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8130 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8131 u8 prio;
8132
8133 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8134 u8 tc = 0;
8135
8136 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8137 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8138 else if (ets)
8139 tc = ets->prio_tc[prio];
8140
8141 netdev_set_prio_tc_map(dev, prio, tc);
8142 }
8143}
8144
cca73c59 8145#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8146/**
8147 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8148 *
8149 * @netdev: net device to configure
8150 * @tc: number of traffic classes to enable
8151 */
8152int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8153{
8b1c0b24
JF		 8154 struct ixgbe_adapter *adapter = netdev_priv(dev);
8155 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8156 bool pools;
8b1c0b24 8157
8b1c0b24 8158 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8159 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8160 return -EINVAL;
8161
8162 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8163 return -EINVAL;
8164
2a47fa45
JF		 8165 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8166 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8167 return -EBUSY;
8168
8b1c0b24 8169 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8170 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8171 * hardware is not flexible enough to do this dynamically.
8172 */
8173 if (netif_running(dev))
8174 ixgbe_close(dev);
bf4d67d9
AD		 8175 else
8176 ixgbe_reset(adapter);
8177
8b1c0b24
JF		 8178 ixgbe_clear_interrupt_scheme(adapter);
8179
cca73c59 8180#ifdef CONFIG_IXGBE_DCB
e7589eab 8181 if (tc) {
8b1c0b24 8182 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8183 ixgbe_set_prio_tc_map(adapter);
8184
e7589eab 8185 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8186
943561d3
AD		 8187 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8188 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8189 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8190 }
e7589eab 8191 } else {
8b1c0b24 8192 netdev_reset_tc(dev);
02debdc9 8193
943561d3
AD		 8194 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8195 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8196
8197 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8198
8199 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8200 adapter->dcb_cfg.pfc_mode_enable = false;
8201 }
8202
8b1c0b24 8203 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8204
8205#endif /* CONFIG_IXGBE_DCB */
8206 ixgbe_init_interrupt_scheme(adapter);
8207
8b1c0b24 8208 if (netif_running(dev))
cca73c59 8209 return ixgbe_open(dev);
8b1c0b24
JF		 8210
8211 return 0;
8212}
de1036b1 8213
b82b17d9
JF		 8214static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8215 struct tc_cls_u32_offload *cls)
8216{
176621c9
SS		 8217 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
8218 u32 loc;
b82b17d9
JF		 8219 int err;
8220
176621c9
SS		 8221 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8222 return -EINVAL;
8223
8224 loc = cls->knode.handle & 0xfffff;
8225
b82b17d9 8226 spin_lock(&adapter->fdir_perfect_lock);
176621c9 8227 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
b82b17d9
JF		 8228 spin_unlock(&adapter->fdir_perfect_lock);
8229 return err;
8230}
8231
db956ae8
JF		 8232static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8233 __be16 protocol,
8234 struct tc_cls_u32_offload *cls)
8235{
176621c9
SS		 8236 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8237
8238 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8239 return -EINVAL;
8240
db956ae8
JF		 8241 /* This ixgbe devices do not support hash tables at the moment
8242 * so abort when given hash tables.
8243 */
8244 if (cls->hnode.divisor > 0)
8245 return -EINVAL;
8246
176621c9 8247 set_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8248 return 0;
8249}
8250
8251static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8252 struct tc_cls_u32_offload *cls)
8253{
176621c9
SS		 8254 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8255
8256 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8257 return -EINVAL;
8258
8259 clear_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8260 return 0;
8261}
8262
b82b17d9
JF		 8263static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8264 __be16 protocol,
8265 struct tc_cls_u32_offload *cls)
8266{
8267 u32 loc = cls->knode.handle & 0xfffff;
8268 struct ixgbe_hw *hw = &adapter->hw;
8269 struct ixgbe_mat_field *field_ptr;
8270 struct ixgbe_fdir_filter *input;
8271 union ixgbe_atr_input mask;
8272#ifdef CONFIG_NET_CLS_ACT
8273 const struct tc_action *a;
8274#endif
8275 int i, err = 0;
8276 u8 queue;
176621c9 8277 u32 uhtid, link_uhtid;
b82b17d9
JF		 8278
8279 memset(&mask, 0, sizeof(union ixgbe_atr_input));
176621c9
SS		 8280 uhtid = TC_U32_USERHTID(cls->knode.handle);
8281 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
b82b17d9 8282
176621c9 8283 /* At the moment cls_u32 jumps to network layer and skips past
b82b17d9
JF		 8284 * L2 headers. The canonical method to match L2 frames is to use
8285 * negative values. However this is error prone at best but really
8286 * just broken because there is no way to "know" what sort of hdr
176621c9 8287 * is in front of the network layer. Fix cls_u32 to support L2
b82b17d9
JF		 8288 * headers when needed.
8289 */
8290 if (protocol != htons(ETH_P_IP))
8291 return -EINVAL;
8292
176621c9 8293 if (link_uhtid) {
b82b17d9 8294 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
b82b17d9 8295
176621c9
SS		 8296 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8297 return -EINVAL;
8298
8299 if (!test_bit(link_uhtid - 1, &adapter->tables))
db956ae8
JF		 8300 return -EINVAL;
8301
b82b17d9 8302 for (i = 0; nexthdr[i].jump; i++) {
4ae78342
AN		 8303 if (nexthdr[i].o != cls->knode.sel->offoff ||
8304 nexthdr[i].s != cls->knode.sel->offshift ||
8305 nexthdr[i].m != cls->knode.sel->offmask ||
b82b17d9
JF		 8306 /* do not support multiple key jumps its just mad */
8307 cls->knode.sel->nkeys > 1)
8308 return -EINVAL;
8309
4ae78342
AN		 8310 if (nexthdr[i].off == cls->knode.sel->keys[0].off &&
8311 nexthdr[i].val == cls->knode.sel->keys[0].val &&
8312 nexthdr[i].mask == cls->knode.sel->keys[0].mask) {
8313 adapter->jump_tables[link_uhtid] =
8314 nexthdr[i].jump;
8315 break;
8316 }
b82b17d9
JF		 8317 }
8318 return 0;
8319 }
8320
8321 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8322 e_err(drv, "Location out of range\n");
8323 return -EINVAL;
8324 }
8325
8326 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8327 * links and also the fields used to advance the parser across each
8328 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8329 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8330 * To add support for new nodes update ixgbe_model.h parse structures
8331 * this function _should_ be generic try not to hardcode values here.
8332 */
176621c9 8333 if (uhtid == 0x800) {
b82b17d9
JF		 8334 field_ptr = adapter->jump_tables[0];
8335 } else {
176621c9 8336 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
b82b17d9
JF		 8337 return -EINVAL;
8338
176621c9 8339 field_ptr = adapter->jump_tables[uhtid];
b82b17d9
JF		 8340 }
8341
8342 if (!field_ptr)
8343 return -EINVAL;
8344
8345 input = kzalloc(sizeof(*input), GFP_KERNEL);
8346 if (!input)
8347 return -ENOMEM;
8348
8349 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8350 int off = cls->knode.sel->keys[i].off;
8351 __be32 val = cls->knode.sel->keys[i].val;
8352 __be32 m = cls->knode.sel->keys[i].mask;
8353 bool found_entry = false;
8354 int j;
8355
8356 for (j = 0; field_ptr[j].val; j++) {
ebd83ad8 8357 if (field_ptr[j].off == off) {
b82b17d9
JF		 8358 field_ptr[j].val(input, &mask, val, m);
8359 input->filter.formatted.flow_type |=
8360 field_ptr[j].type;
8361 found_entry = true;
8362 break;
8363 }
8364 }
8365
8366 if (!found_entry)
8367 goto err_out;
8368 }
8369
8370 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8371 IXGBE_ATR_L4TYPE_MASK;
8372
8373 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8374 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8375
8376#ifdef CONFIG_NET_CLS_ACT
8377 if (list_empty(&cls->knode.exts->actions))
8378 goto err_out;
8379
8380 list_for_each_entry(a, &cls->knode.exts->actions, list) {
8381 if (!is_tcf_gact_shot(a))
8382 goto err_out;
8383 }
8384#endif
8385
8386 input->action = IXGBE_FDIR_DROP_QUEUE;
8387 queue = IXGBE_FDIR_DROP_QUEUE;
8388 input->sw_idx = loc;
8389
8390 spin_lock(&adapter->fdir_perfect_lock);
8391
8392 if (hlist_empty(&adapter->fdir_filter_list)) {
8393 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
8394 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
8395 if (err)
8396 goto err_out_w_lock;
8397 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
8398 err = -EINVAL;
8399 goto err_out_w_lock;
8400 }
8401
8402 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
8403 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8404 input->sw_idx, queue);
8405 if (!err)
8406 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8407 spin_unlock(&adapter->fdir_perfect_lock);
8408
8409 return err;
8410err_out_w_lock:
8411 spin_unlock(&adapter->fdir_perfect_lock);
8412err_out:
8413 kfree(input);
8414 return -EINVAL;
8415}
8416
6e2a60b5
ET		 8417static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8418 struct tc_to_netdev *tc)
e4c6734e 8419{
b82b17d9
JF		 8420 struct ixgbe_adapter *adapter = netdev_priv(dev);
8421
8422 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8423 tc->type == TC_SETUP_CLSU32) {
b82b17d9
JF		 8424 switch (tc->cls_u32->command) {
8425 case TC_CLSU32_NEW_KNODE:
8426 case TC_CLSU32_REPLACE_KNODE:
8427 return ixgbe_configure_clsu32(adapter,
8428 proto, tc->cls_u32);
8429 case TC_CLSU32_DELETE_KNODE:
8430 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
db956ae8
JF		 8431 case TC_CLSU32_NEW_HNODE:
8432 case TC_CLSU32_REPLACE_HNODE:
8433 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8434 tc->cls_u32);
8435 case TC_CLSU32_DELETE_HNODE:
8436 return ixgbe_configure_clsu32_del_hnode(adapter,
8437 tc->cls_u32);
b82b17d9
JF		 8438 default:
8439 return -EINVAL;
8440 }
8441 }
8442
5eb4dce3 8443 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 8444 return -EINVAL;
8445
16e5cc64 8446 return ixgbe_setup_tc(dev, tc->tc);
e4c6734e
JF		 8447}
8448
da36b647
GR		 8449#ifdef CONFIG_PCI_IOV
8450void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8451{
8452 struct net_device *netdev = adapter->netdev;
8453
8454 rtnl_lock();
da36b647 8455 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8456 rtnl_unlock();
8457}
8458
8459#endif
082757af
DS		 8460void ixgbe_do_reset(struct net_device *netdev)
8461{
8462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8463
8464 if (netif_running(netdev))
8465 ixgbe_reinit_locked(adapter);
8466 else
8467 ixgbe_reset(adapter);
8468}
8469
c8f44aff 8470static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8471 netdev_features_t features)
082757af
DS		 8472{
8473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8474
082757af 8475 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8476 if (!(features & NETIF_F_RXCSUM))
8477 features &= ~NETIF_F_LRO;
082757af 8478
567d2de2
AD		 8479 /* Turn off LRO if not RSC capable */
8480 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8481 features &= ~NETIF_F_LRO;
8e2813f5 8482
567d2de2 8483 return features;
082757af
DS		 8484}
8485
c8f44aff 8486static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8487 netdev_features_t features)
082757af
DS		 8488{
8489 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8490 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8491 bool need_reset = false;
8492
082757af 8493 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8494 if (!(features & NETIF_F_LRO)) {
8495 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8496 need_reset = true;
567d2de2
AD		 8497 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8498 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8499 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8500 if (adapter->rx_itr_setting == 1 ||
8501 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8502 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8503 need_reset = true;
8504 } else if ((changed ^ features) & NETIF_F_LRO) {
8505 e_info(probe, "rx-usecs set too low, "
8506 "disabling RSC\n");
082757af
DS		 8507 }
8508 }
8509
8510 /*
b82b17d9
JF		 8511 * Check if Flow Director n-tuple support or hw_tc support was
8512 * enabled or disabled. If the state changed, we need to reset.
082757af 8513 */
b82b17d9 8514 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 8515 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8516 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8517 need_reset = true;
8518
567d2de2
AD		 8519 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8520 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 8521 } else {
39cb681b
AD		 8522 /* turn off perfect filters, enable ATR and reset */
8523 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8524 need_reset = true;
8525
8526 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8527
8528 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 8529 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8530 /* We cannot enable ATR if we have 2 or more tcs */
8531 (netdev_get_num_tc(netdev) > 1) ||
8532 /* We cannot enable ATR if RSS is disabled */
8533 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8534 /* A sample rate of 0 indicates ATR disabled */
8535 (!adapter->atr_sample_rate))
8536 ; /* do nothing not supported */
8537 else /* otherwise supported and set the flag */
8538 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 8539 }
8540
3f2d1c0f
BG		 8541 if (changed & NETIF_F_RXALL)
8542 need_reset = true;
8543
567d2de2 8544 netdev->features = features;
67359c3c
MR		 8545
8546#ifdef CONFIG_IXGBE_VXLAN
8547 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8548 if (features & NETIF_F_RXCSUM)
8549 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8550 else
8551 ixgbe_clear_vxlan_port(adapter);
8552 }
8553#endif /* CONFIG_IXGBE_VXLAN */
8554
082757af
DS		 8555 if (need_reset)
8556 ixgbe_do_reset(netdev);
0c5a6166
AD		 8557 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
8558 NETIF_F_HW_VLAN_CTAG_FILTER))
8559 ixgbe_set_rx_mode(netdev);
082757af
DS		 8560
8561 return 0;
082757af
DS		 8562}
8563
67359c3c 8564#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8565/**
8566 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8567 * @dev: The port's netdev
8568 * @sa_family: Socket Family that VXLAN is notifiying us about
8569 * @port: New UDP port number that VXLAN started listening to
8570 **/
8571static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8572 __be16 port)
8573{
8574 struct ixgbe_adapter *adapter = netdev_priv(dev);
8575 struct ixgbe_hw *hw = &adapter->hw;
3f207800 8576
67359c3c
MR		 8577 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8578 return;
8579
3f207800
DS		 8580 if (sa_family == AF_INET6)
8581 return;
8582
9f12df90 8583 if (adapter->vxlan_port == port)
3f207800 8584 return;
3f207800
DS		 8585
8586 if (adapter->vxlan_port) {
8587 netdev_info(dev,
67359c3c 8588 "Hit Max num of VXLAN ports, not adding port %d\n",
9f12df90 8589 ntohs(port));
3f207800
DS		 8590 return;
8591 }
8592
9f12df90
AD		 8593 adapter->vxlan_port = port;
8594 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port));
3f207800
DS		 8595}
8596
8597/**
8598 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8599 * @dev: The port's netdev
8600 * @sa_family: Socket Family that VXLAN is notifying us about
8601 * @port: UDP port number that VXLAN stopped listening to
8602 **/
8603static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8604 __be16 port)
8605{
8606 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800 8607
67359c3c
MR		 8608 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8609 return;
8610
3f207800
DS		 8611 if (sa_family == AF_INET6)
8612 return;
8613
9f12df90 8614 if (adapter->vxlan_port != port) {
3f207800 8615 netdev_info(dev, "Port %d was not found, not deleting\n",
9f12df90 8616 ntohs(port));
3f207800
DS		 8617 return;
8618 }
8619
67359c3c
MR		 8620 ixgbe_clear_vxlan_port(adapter);
8621 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8622}
67359c3c 8623#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8624
edc7d573 8625static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8626 struct net_device *dev,
f6f6424b 8627 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8628 u16 flags)
8629{
bcfd3432 8630 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8631 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 8632 struct ixgbe_adapter *adapter = netdev_priv(dev);
8633 u16 pool = VMDQ_P(0);
8634
8635 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 8636 return -ENOMEM;
0f4b0add
JF		 8637 }
8638
f6f6424b 8639 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8640}
8641
219efe97
DS		 8642/**
8643 * ixgbe_configure_bridge_mode - set various bridge modes
8644 * @adapter - the private structure
8645 * @mode - requested bridge mode
8646 *
8647 * Configure some settings require for various bridge modes.
8648 **/
8649static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8650 __u16 mode)
8651{
6d4c96ad
DS		 8652 struct ixgbe_hw *hw = &adapter->hw;
8653 unsigned int p, num_pools;
8654 u32 vmdctl;
8655
219efe97
DS		 8656 switch (mode) {
8657 case BRIDGE_MODE_VEPA:
6d4c96ad 8658 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8660
8661 /* must enable Rx switching replication to allow multicast
8662 * packet reception on all VFs, and to enable source address
8663 * pruning.
8664 */
8665 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8666 vmdctl |= IXGBE_VT_CTL_REPLEN;
8667 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8668
8669 /* enable Rx source address pruning. Note, this requires
8670 * replication to be enabled or else it does nothing.
8671 */
8672 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8673 for (p = 0; p < num_pools; p++) {
8674 if (hw->mac.ops.set_source_address_pruning)
8675 hw->mac.ops.set_source_address_pruning(hw,
8676 true,
8677 p);
8678 }
219efe97
DS		 8679 break;
8680 case BRIDGE_MODE_VEB:
6d4c96ad 8681 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8682 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8683 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8684
8685 /* disable Rx switching replication unless we have SR-IOV
8686 * virtual functions
8687 */
8688 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8689 if (!adapter->num_vfs)
8690 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8691 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8692
8693 /* disable Rx source address pruning, since we don't expect to
8694 * be receiving external loopback of our transmitted frames.
8695 */
8696 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8697 for (p = 0; p < num_pools; p++) {
8698 if (hw->mac.ops.set_source_address_pruning)
8699 hw->mac.ops.set_source_address_pruning(hw,
8700 false,
8701 p);
8702 }
219efe97
DS		 8703 break;
8704 default:
8705 return -EINVAL;
8706 }
8707
8708 adapter->bridge_mode = mode;
8709
8710 e_info(drv, "enabling bridge mode: %s\n",
8711 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8712
8713 return 0;
8714}
8715
815cccbf 8716static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8717 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8718{
8719 struct ixgbe_adapter *adapter = netdev_priv(dev);
8720 struct nlattr *attr, *br_spec;
8721 int rem;
8722
8723 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8724 return -EOPNOTSUPP;
8725
8726 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8727 if (!br_spec)
8728 return -EINVAL;
815cccbf
JF		 8729
8730 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8731 int status;
815cccbf 8732 __u16 mode;
815cccbf
JF		 8733
8734 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8735 continue;
8736
b7c1a314
TG		 8737 if (nla_len(attr) < sizeof(mode))
8738 return -EINVAL;
8739
815cccbf 8740 mode = nla_get_u16(attr);
219efe97
DS		 8741 status = ixgbe_configure_bridge_mode(adapter, mode);
8742 if (status)
8743 return status;
aa2bacb6
DS		 8744
8745 break;
815cccbf
JF		 8746 }
8747
8748 return 0;
8749}
8750
8751static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8752 struct net_device *dev,
46c264da 8753 u32 filter_mask, int nlflags)
815cccbf
JF		 8754{
8755 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8756
8757 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8758 return 0;
8759
aa2bacb6 8760 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8761 adapter->bridge_mode, 0, 0, nlflags,
8762 filter_mask, NULL);
815cccbf
JF		 8763}
8764
2a47fa45
JF		 8765static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8766{
8767 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8768 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8769 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8770 unsigned int limit;
2a47fa45
JF		 8771 int pool, err;
8772
aac2f1bf
JK		 8773 /* Hardware has a limited number of available pools. Each VF, and the
8774 * PF require a pool. Check to ensure we don't attempt to use more
8775 * then the available number of pools.
8776 */
8777 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8778 return ERR_PTR(-EINVAL);
8779
219354d4
JF		 8780#ifdef CONFIG_RPS
8781 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8782 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8783 vdev->name);
8784 return ERR_PTR(-EINVAL);
8785 }
8786#endif
2a47fa45 8787 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8788 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8789 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8790 netdev_info(pdev,
8791 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8792 pdev->name);
8793 return ERR_PTR(-EINVAL);
8794 }
8795
8796 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8797 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8798 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8799 return ERR_PTR(-EBUSY);
8800
bc52f951 8801 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8802 if (!fwd_adapter)
8803 return ERR_PTR(-ENOMEM);
8804
8805 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8806 adapter->num_rx_pools++;
8807 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8808 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8809
8810 /* Enable VMDq flag so device will be set in VM mode */
8811 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8812 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8813 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8814
8815 /* Force reinit of ring allocation with VMDQ enabled */
8816 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8817 if (err)
8818 goto fwd_add_err;
8819 fwd_adapter->pool = pool;
8820 fwd_adapter->real_adapter = adapter;
8821 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8822 if (err)
8823 goto fwd_add_err;
8824 netif_tx_start_all_queues(vdev);
8825 return fwd_adapter;
8826fwd_add_err:
8827 /* unwind counter and free adapter struct */
8828 netdev_info(pdev,
8829 "%s: dfwd hardware acceleration failed\n", vdev->name);
8830 clear_bit(pool, &adapter->fwd_bitmask);
8831 adapter->num_rx_pools--;
8832 kfree(fwd_adapter);
8833 return ERR_PTR(err);
8834}
8835
8836static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8837{
8838 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8839 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8840 unsigned int limit;
2a47fa45
JF		 8841
8842 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8843 adapter->num_rx_pools--;
8844
51f3773b
JF		 8845 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8846 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8847 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8848 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8849 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8850 fwd_adapter->pool, adapter->num_rx_pools,
8851 fwd_adapter->rx_base_queue,
8852 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8853 adapter->fwd_bitmask);
8854 kfree(fwd_adapter);
8855}
8856
f467bc06
MR		 8857#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8858static netdev_features_t
8859ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8860 netdev_features_t features)
8861{
8862 if (!skb->encapsulation)
8863 return features;
8864
8865 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8866 IXGBE_MAX_TUNNEL_HDR_LEN))
a188222b 8867 return features & ~NETIF_F_CSUM_MASK;
f467bc06
MR		 8868
8869 return features;
8870}
8871
0edc3527 8872static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8873 .ndo_open = ixgbe_open,
0edc3527 8874 .ndo_stop = ixgbe_close,
00829823 8875 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8876 .ndo_select_queue = ixgbe_select_queue,
581330ba 8877 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8878 .ndo_validate_addr = eth_validate_addr,
8879 .ndo_set_mac_address = ixgbe_set_mac,
8880 .ndo_change_mtu = ixgbe_change_mtu,
8881 .ndo_tx_timeout = ixgbe_tx_timeout,
c04f90e5 8882 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
0edc3527
SH		 8883 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8884 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8885 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8886 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8887 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8888 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8889 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8890 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8891 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8892 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8893 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 8894 .ndo_setup_tc = __ixgbe_setup_tc,
0edc3527
SH		 8895#ifdef CONFIG_NET_POLL_CONTROLLER
8896 .ndo_poll_controller = ixgbe_netpoll,
8897#endif
e0d1095a 8898#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8899 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8900#endif
332d4a7d
YZ		 8901#ifdef IXGBE_FCOE
8902 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8903 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8904 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8905 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8906 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8907 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8908 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8909#endif /* IXGBE_FCOE */
082757af
DS		 8910 .ndo_set_features = ixgbe_set_features,
8911 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8912 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8913 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8914 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8915 .ndo_dfwd_add_station = ixgbe_fwd_add,
8916 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8917#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8918 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8919 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8920#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8921 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8922};
8923
e027d1ae
JK		 8924/**
8925 * ixgbe_enumerate_functions - Get the number of ports this device has
8926 * @adapter: adapter structure
8927 *
8928 * This function enumerates the phsyical functions co-located on a single slot,
8929 * in order to determine how many ports a device has. This is most useful in
8930 * determining the required GT/s of PCIe bandwidth necessary for optimal
8931 * performance.
8932 **/
8933static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8934{
caafb95d 8935 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8936 int physfns = 0;
8937
f1f96579
JK		 8938 /* Some cards can not use the generic count PCIe functions method,
8939 * because they are behind a parent switch, so we hardcode these with
8940 * the correct number of functions.
e027d1ae 8941 */
8818970d 8942 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8943 physfns = 4;
8818970d
JK		 8944
8945 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8946 /* don't count virtual functions */
caafb95d
JK		 8947 if (entry->is_virtfn)
8948 continue;
8949
8950 /* When the devices on the bus don't all match our device ID,
8951 * we can't reliably determine the correct number of
8952 * functions. This can occur if a function has been direct
8953 * attached to a virtual machine using VT-d, for example. In
8954 * this case, simply return -1 to indicate this.
8955 */
8956 if ((entry->vendor != pdev->vendor) ||
8957 (entry->device != pdev->device))
8958 return -1;
8959
8960 physfns++;
e027d1ae
JK		 8961 }
8962
8963 return physfns;
8964}
8965
8e2813f5
JK		 8966/**
8967 * ixgbe_wol_supported - Check whether device supports WoL
8968 * @hw: hw specific details
8969 * @device_id: the device ID
8970 * @subdev_id: the subsystem device ID
8971 *
8972 * This function is used by probe and ethtool to determine
8973 * which devices have WoL support
8974 *
8975 **/
8976int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8977 u16 subdevice_id)
8978{
8979 struct ixgbe_hw *hw = &adapter->hw;
8980 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8981 int is_wol_supported = 0;
8982
8983 switch (device_id) {
8984 case IXGBE_DEV_ID_82599_SFP:
8985 /* Only these subdevices could supports WOL */
8986 switch (subdevice_id) {
87557440 8987 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8988 case IXGBE_SUBDEV_ID_82599_560FLR:
8989 /* only support first port */
8990 if (hw->bus.func != 0)
8991 break;
5700ff26 8992 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8993 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8994 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8995 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8996 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8997 is_wol_supported = 1;
8998 break;
8999 }
9000 break;
5daebbb0
DS		 9001 case IXGBE_DEV_ID_82599EN_SFP:
9002 /* Only this subdevice supports WOL */
9003 switch (subdevice_id) {
9004 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
9005 is_wol_supported = 1;
9006 break;
9007 }
9008 break;
8e2813f5
JK		 9009 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
9010 /* All except this subdevice support WOL */
9011 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9012 is_wol_supported = 1;
9013 break;
9014 case IXGBE_DEV_ID_82599_KX4:
9015 is_wol_supported = 1;
9016 break;
9017 case IXGBE_DEV_ID_X540T:
df376f0d 9018 case IXGBE_DEV_ID_X540T1:
df8c26fd 9019 case IXGBE_DEV_ID_X550T:
a711ad89 9020 case IXGBE_DEV_ID_X550T1:
df8c26fd
DS		 9021 case IXGBE_DEV_ID_X550EM_X_KX4:
9022 case IXGBE_DEV_ID_X550EM_X_KR:
9023 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 9024 /* check eeprom to see if enabled wol */
9025 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
9026 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
9027 (hw->bus.func == 0))) {
9028 is_wol_supported = 1;
9029 }
9030 break;
9031 }
9032
9033 return is_wol_supported;
9034}
9035
9a799d71
AK		 9036/**
9037 * ixgbe_probe - Device Initialization Routine
9038 * @pdev: PCI device information struct
9039 * @ent: entry in ixgbe_pci_tbl
9040 *
9041 * Returns 0 on success, negative on failure
9042 *
9043 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9044 * The OS initialization, configuring of the adapter private structure,
9045 * and a hardware reset occur.
9046 **/
1dd06ae8 9047static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 9048{
9049 struct net_device *netdev;
9050 struct ixgbe_adapter *adapter = NULL;
9051 struct ixgbe_hw *hw;
9052 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 9053 int i, err, pci_using_dac, expected_gts;
d3cb9869 9054 unsigned int indices = MAX_TX_QUEUES;
289700db 9055 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 9056 bool disable_dev = false;
eacd73f7
YZ		 9057#ifdef IXGBE_FCOE
9058 u16 device_caps;
9059#endif
289700db 9060 u32 eec;
9a799d71 9061
bded64a7
AG		 9062 /* Catch broken hardware that put the wrong VF device ID in
9063 * the PCIe SR-IOV capability.
9064 */
9065 if (pdev->is_virtfn) {
9066 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9067 pci_name(pdev), pdev->vendor, pdev->device);
9068 return -EINVAL;
9069 }
9070
9ce77666 9071 err = pci_enable_device_mem(pdev);
9a799d71
AK		 9072 if (err)
9073 return err;
9074
f5f2eda8 9075 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 9076 pci_using_dac = 1;
9077 } else {
f5f2eda8 9078 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 9079 if (err) {
f5f2eda8
RK		 9080 dev_err(&pdev->dev,
9081 "No usable DMA configuration, aborting\n");
9082 goto err_dma;
9a799d71
AK		 9083 }
9084 pci_using_dac = 0;
9085 }
9086
9ce77666 9087 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9088 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 9089 if (err) {
b8bc0421
DC		 9090 dev_err(&pdev->dev,
9091 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 9092 goto err_pci_reg;
9093 }
9094
19d5afd4 9095 pci_enable_pcie_error_reporting(pdev);
6fabd715 9096
9a799d71 9097 pci_set_master(pdev);
fb3b27bc 9098 pci_save_state(pdev);
9a799d71 9099
d3cb9869 9100 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 9101#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 9102 /* 8 TC w/ 4 queues per TC */
9103 indices = 4 * MAX_TRAFFIC_CLASS;
9104#else
9105 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 9106#endif
d3cb9869 9107 }
e901acd6 9108
c85a2618 9109 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 9110 if (!netdev) {
9111 err = -ENOMEM;
9112 goto err_alloc_etherdev;
9113 }
9114
9a799d71
AK		 9115 SET_NETDEV_DEV(netdev, &pdev->dev);
9116
9a799d71
AK		 9117 adapter = netdev_priv(netdev);
9118
9119 adapter->netdev = netdev;
9120 adapter->pdev = pdev;
9121 hw = &adapter->hw;
9122 hw->back = adapter;
b3f4d599 9123 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 9124
05857980 9125 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 9126 pci_resource_len(pdev, 0));
2a1a091c 9127 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 9128 if (!hw->hw_addr) {
9129 err = -EIO;
9130 goto err_ioremap;
9131 }
9132
0edc3527 9133 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 9134 ixgbe_set_ethtool_ops(netdev);
9a799d71 9135 netdev->watchdog_timeo = 5 * HZ;
339de30f 9136 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 9137
9a799d71 9138 /* Setup hw api */
37689010 9139 hw->mac.ops = *ii->mac_ops;
021230d4 9140 hw->mac.type = ii->mac;
9a900eca 9141 hw->mvals = ii->mvals;
9a799d71 9142
c44ade9e 9143 /* EEPROM */
37689010 9144 hw->eeprom.ops = *ii->eeprom_ops;
9a900eca 9145 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 9146 if (ixgbe_removed(hw->hw_addr)) {
9147 err = -EIO;
9148 goto err_ioremap;
9149 }
c44ade9e
JB		 9150 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
9151 if (!(eec & (1 << 8)))
9152 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9153
9154 /* PHY */
37689010 9155 hw->phy.ops = *ii->phy_ops;
c4900be0 9156 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 9157 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9158 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9159 hw->phy.mdio.mmds = 0;
9160 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9161 hw->phy.mdio.dev = netdev;
9162 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9163 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 9164
8ca783ab 9165 ii->get_invariants(hw);
9a799d71
AK		 9166
9167 /* setup the private structure */
9168 err = ixgbe_sw_init(adapter);
9169 if (err)
9170 goto err_sw_init;
9171
dbd15b8f
DS		 9172 /* Make sure the SWFW semaphore is in a valid state */
9173 if (hw->mac.ops.init_swfw_sync)
9174 hw->mac.ops.init_swfw_sync(hw);
9175
e86bff0e 9176 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 9177 switch (adapter->hw.mac.type) {
9178 case ixgbe_mac_82599EB:
9179 case ixgbe_mac_X540:
9a75a1ac
DS		 9180 case ixgbe_mac_X550:
9181 case ixgbe_mac_X550EM_x:
49425dfc 9182 case ixgbe_mac_x550em_a:
e86bff0e 9183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 9184 break;
9185 default:
9186 break;
9187 }
e86bff0e 9188
bf069c97
DS		 9189 /*
9190 * If there is a fan on this device and it has failed log the
9191 * failure.
9192 */
9193 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9194 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9195 if (esdp & IXGBE_ESDP_SDP1)
396e799c 9196 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 9197 }
9198
8ef78adc
PWJ		 9199 if (allow_unsupported_sfp)
9200 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9201
c44ade9e 9202 /* reset_hw fills in the perm_addr as well */
119fc60a 9203 hw->phy.reset_if_overtemp = true;
c44ade9e 9204 err = hw->mac.ops.reset_hw(hw);
119fc60a 9205 hw->phy.reset_if_overtemp = false;
29a8dca1 9206 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 9207 err = 0;
9208 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 9209 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9210 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 9211 goto err_sw_init;
9212 } else if (err) {
849c4542 9213 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 9214 goto err_sw_init;
9215 }
9216
99d74487 9217#ifdef CONFIG_PCI_IOV
60a1a680
GR		 9218 /* SR-IOV not supported on the 82598 */
9219 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9220 goto skip_sriov;
9221 /* Mailbox */
9222 ixgbe_init_mbx_params_pf(hw);
37689010 9223 hw->mbx.ops = ii->mbx_ops;
dcc23e3a 9224 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 9225 ixgbe_enable_sriov(adapter);
60a1a680 9226skip_sriov:
1cdd1ec8 9227
99d74487 9228#endif
396e799c 9229 netdev->features = NETIF_F_SG |
082757af
DS		 9230 NETIF_F_TSO |
9231 NETIF_F_TSO6 |
082757af 9232 NETIF_F_RXHASH |
49763de0
AD		 9233 NETIF_F_RXCSUM |
9234 NETIF_F_HW_CSUM |
9235 NETIF_F_HW_VLAN_CTAG_TX |
0c5a6166
AD		 9236 NETIF_F_HW_VLAN_CTAG_RX |
9237 NETIF_F_HW_VLAN_CTAG_FILTER;
ad31c402 9238
49763de0 9239 if (hw->mac.type >= ixgbe_mac_82599EB)
53692b1d 9240 netdev->features |= NETIF_F_SCTP_CRC;
49763de0
AD		 9241
9242 /* copy netdev features into list of user selectable features */
9243 netdev->hw_features |= netdev->features;
9244 netdev->hw_features |= NETIF_F_RXALL |
9245 NETIF_F_HW_L2FW_DOFFLOAD;
9246
9247 if (hw->mac.type >= ixgbe_mac_82599EB)
9248 netdev->hw_features |= NETIF_F_NTUPLE |
b82b17d9 9249 NETIF_F_HW_TC;
45a5ead0 9250
49763de0
AD		 9251 netdev->vlan_features |= NETIF_F_SG |
9252 NETIF_F_TSO |
9253 NETIF_F_TSO6 |
9254 NETIF_F_HW_CSUM |
9255 NETIF_F_SCTP_CRC;
ad31c402 9256
49763de0
AD		 9257 netdev->mpls_features |= NETIF_F_HW_CSUM;
9258 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
f467bc06 9259
01789349 9260 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9261 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9262
7a6b6f51 9263#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 9264 netdev->dcbnl_ops = &dcbnl_ops;
9265#endif
9266
eacd73f7 9267#ifdef IXGBE_FCOE
0d551589 9268 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9269 unsigned int fcoe_l;
9270
eacd73f7
YZ		 9271 if (hw->mac.ops.get_device_caps) {
9272 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9273 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9274 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9275 }
7c8ae65a 9276
d3cb9869
AD		 9277
9278 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9279 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9280
a58915c7
AD		 9281 netdev->features |= NETIF_F_FSO |
9282 NETIF_F_FCOE_CRC;
9283
7c8ae65a
AD		 9284 netdev->vlan_features |= NETIF_F_FSO |
9285 NETIF_F_FCOE_CRC |
9286 NETIF_F_FCOE_MTU;
5e09d7f6 9287 }
eacd73f7 9288#endif /* IXGBE_FCOE */
7b872a55 9289 if (pci_using_dac) {
9a799d71 9290 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 9291 netdev->vlan_features |= NETIF_F_HIGHDMA;
9292 }
9a799d71 9293
082757af
DS		 9294 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9295 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9296 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9297 netdev->features |= NETIF_F_LRO;
9298
9a799d71 9299 /* make sure the EEPROM is good */
c44ade9e 9300 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9301 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9302 err = -EIO;
35937c05 9303 goto err_sw_init;
9a799d71
AK		 9304 }
9305
c7374b5a
SV		 9306 eth_platform_get_mac_address(&adapter->pdev->dev,
9307 adapter->hw.mac.perm_addr);
c762dff2 9308
9a799d71 9309 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9310
aaeb6cdf 9311 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9312 e_dev_err("invalid MAC address\n");
9a799d71 9313 err = -EIO;
35937c05 9314 goto err_sw_init;
9a799d71
AK		 9315 }
9316
56768045
TD		 9317 /* Set hw->mac.addr to permanent MAC address */
9318 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 9319 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9320
7086400d 9321 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9322 (unsigned long) adapter);
9a799d71 9323
58cf663f
MR		 9324 if (ixgbe_removed(hw->hw_addr)) {
9325 err = -EIO;
9326 goto err_sw_init;
9327 }
7086400d 9328 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9329 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9330 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9331
021230d4
AV		 9332 err = ixgbe_init_interrupt_scheme(adapter);
9333 if (err)
9334 goto err_sw_init;
9a799d71 9335
8e2813f5 9336 /* WOL not supported for all devices */
c23f5b6b 9337 adapter->wol = 0;
8e2813f5 9338 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9339 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9340 pdev->subsystem_device);
6b92b0ba 9341 if (hw->wol_enabled)
9417c464 9342 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9343
e8e26350
PW		 9344 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9345
15e5209f
ET		 9346 /* save off EEPROM version number */
9347 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9348 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9349
04f165ef 9350 /* pick up the PCI bus settings for reporting later */
e027d1ae 9351 if (ixgbe_pcie_from_parent(hw))
b8e82001 9352 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9353 else
9354 hw->mac.ops.get_bus_info(hw);
04f165ef 9355
e027d1ae
JK		 9356 /* calculate the expected PCIe bandwidth required for optimal
9357 * performance. Note that some older parts will never have enough
9358 * bandwidth due to being older generation PCIe parts. We clamp these
9359 * parts to ensure no warning is displayed if it can't be fixed.
9360 */
9361 switch (hw->mac.type) {
9362 case ixgbe_mac_82598EB:
9363 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9364 break;
9365 default:
9366 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9367 break;
0c254d86 9368 }
caafb95d
JK		 9369
9370 /* don't check link if we failed to enumerate functions */
9371 if (expected_gts > 0)
9372 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9373
339de30f 9374 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9375 if (err)
339de30f 9376 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9377 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9378 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9379 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9380 part_str);
6a2aae5a
JK		 9381 else
9382 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9383 hw->mac.type, hw->phy.type, part_str);
9384
9385 e_dev_info("%pM\n", netdev->dev_addr);
9386
9a799d71 9387 /* reset the hardware with the new settings */
794caeb2 9388 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9389 if (err == IXGBE_ERR_EEPROM_VERSION) {
9390 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9391 e_dev_warn("This device is a pre-production adapter/LOM. "
9392 "Please be aware there may be issues associated "
9393 "with your hardware. If you are experiencing "
9394 "problems please contact your Intel or hardware "
9395 "representative who provided you with this "
9396 "hardware.\n");
794caeb2 9397 }
9a799d71
AK		 9398 strcpy(netdev->name, "eth%d");
9399 err = register_netdev(netdev);
9400 if (err)
9401 goto err_register;
9402
0fb6a55c
ET		 9403 pci_set_drvdata(pdev, adapter);
9404
ec74a471
ET		 9405 /* power down the optics for 82599 SFP+ fiber */
9406 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9407 hw->mac.ops.disable_tx_laser(hw);
9408
54386467
JB		 9409 /* carrier off reporting is important to ethtool even BEFORE open */
9410 netif_carrier_off(netdev);
9411
5dd2d332 9412#ifdef CONFIG_IXGBE_DCA
652f093f 9413 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9414 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9415 ixgbe_setup_dca(adapter);
9416 }
9417#endif
1cdd1ec8 9418 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9419 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9420 for (i = 0; i < adapter->num_vfs; i++)
9421 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9422 }
9423
2466dd9c
JK		 9424 /* firmware requires driver version to be 0xFFFFFFFF
9425 * since os does not support feature
9426 */
9612de92 9427 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9428 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9429 0xFF);
9612de92 9430
0365e6e4
PW		 9431 /* add san mac addr to netdev */
9432 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9433
ea81875a 9434 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9435
1210982b 9436#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9437 if (ixgbe_sysfs_init(adapter))
9438 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9439#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9440
00949167 9441 ixgbe_dbg_adapter_init(adapter);
00949167 9442
d1a35ee2
ET		 9443 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9444 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9445 hw->mac.ops.setup_link(hw,
9446 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9447 true);
9448
9a799d71
AK		 9449 return 0;
9450
9451err_register:
5eba3699 9452 ixgbe_release_hw_control(adapter);
7a921c93 9453 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9454err_sw_init:
99d74487 9455 ixgbe_disable_sriov(adapter);
7086400d 9456 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9457 iounmap(adapter->io_addr);
5d7daa35 9458 kfree(adapter->mac_table);
9a799d71 9459err_ioremap:
b5b2ffc0 9460 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9461 free_netdev(netdev);
9462err_alloc_etherdev:
e8e9f696
JP		 9463 pci_release_selected_regions(pdev,
9464 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9465err_pci_reg:
9466err_dma:
b5b2ffc0 9467 if (!adapter || disable_dev)
41c62843 9468 pci_disable_device(pdev);
9a799d71
AK		 9469 return err;
9470}
9471
9472/**
9473 * ixgbe_remove - Device Removal Routine
9474 * @pdev: PCI device information struct
9475 *
9476 * ixgbe_remove is called by the PCI subsystem to alert the driver
9477 * that it should release a PCI device. The could be caused by a
9478 * Hot-Plug event, or because the driver is going to be removed from
9479 * memory.
9480 **/
9f9a12f8 9481static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9482{
c60fbb00 9483 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9484 struct net_device *netdev;
b5b2ffc0 9485 bool disable_dev;
9a799d71 9486
0fb6a55c
ET		 9487 /* if !adapter then we already cleaned up in probe */
9488 if (!adapter)
9489 return;
9490
9491 netdev = adapter->netdev;
00949167 9492 ixgbe_dbg_adapter_exit(adapter);
00949167 9493
09f40aed 9494 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9495 cancel_work_sync(&adapter->service_task);
9a799d71 9496
3a6a4eda 9497
5dd2d332 9498#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9499 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9500 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9501 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9502 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9503 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9504 }
9505
9506#endif
1210982b 9507#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9508 ixgbe_sysfs_exit(adapter);
1210982b 9509#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9510
0365e6e4
PW		 9511 /* remove the added san mac */
9512 ixgbe_del_sanmac_netdev(netdev);
9513
da36b647 9514#ifdef CONFIG_PCI_IOV
7837e286 9515 ixgbe_disable_sriov(adapter);
da36b647 9516#endif
6b010e9b
AW		 9517 if (netdev->reg_state == NETREG_REGISTERED)
9518 unregister_netdev(netdev);
9519
7a921c93 9520 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9521
021230d4 9522 ixgbe_release_hw_control(adapter);
9a799d71 9523
2b1588c3
AD		 9524#ifdef CONFIG_DCB
9525 kfree(adapter->ixgbe_ieee_pfc);
9526 kfree(adapter->ixgbe_ieee_ets);
9527
9528#endif
2a1a091c 9529 iounmap(adapter->io_addr);
9ce77666 9530 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9531 IORESOURCE_MEM));
9a799d71 9532
849c4542 9533 e_dev_info("complete\n");
021230d4 9534
5d7daa35 9535 kfree(adapter->mac_table);
b5b2ffc0 9536 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9537 free_netdev(netdev);
9538
19d5afd4 9539 pci_disable_pcie_error_reporting(pdev);
6fabd715 9540
b5b2ffc0 9541 if (disable_dev)
41c62843 9542 pci_disable_device(pdev);
9a799d71
AK		 9543}
9544
9545/**
9546 * ixgbe_io_error_detected - called when PCI error is detected
9547 * @pdev: Pointer to PCI device
9548 * @state: The current pci connection state
9549 *
9550 * This function is called after a PCI bus error affecting
9551 * this device has been detected.
9552 */
9553static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9554 pci_channel_state_t state)
9a799d71 9555{
c60fbb00
AD		 9556 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9557 struct net_device *netdev = adapter->netdev;
9a799d71 9558
83c61fa9 9559#ifdef CONFIG_PCI_IOV
14438464 9560 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9561 struct pci_dev *bdev, *vfdev;
9562 u32 dw0, dw1, dw2, dw3;
9563 int vf, pos;
9564 u16 req_id, pf_func;
9565
9566 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9567 adapter->num_vfs == 0)
9568 goto skip_bad_vf_detection;
9569
9570 bdev = pdev->bus->self;
62f87c0e 9571 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9572 bdev = bdev->bus->self;
9573
9574 if (!bdev)
9575 goto skip_bad_vf_detection;
9576
9577 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9578 if (!pos)
9579 goto skip_bad_vf_detection;
9580
14438464
MR		 9581 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9582 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9583 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9584 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9585 if (ixgbe_removed(hw->hw_addr))
9586 goto skip_bad_vf_detection;
83c61fa9
GR		 9587
9588 req_id = dw1 >> 16;
9589 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9590 if (!(req_id & 0x0080))
9591 goto skip_bad_vf_detection;
9592
9593 pf_func = req_id & 0x01;
9594 if ((pf_func & 1) == (pdev->devfn & 1)) {
9595 unsigned int device_id;
9596
9597 vf = (req_id & 0x7F) >> 1;
9598 e_dev_err("VF %d has caused a PCIe error\n", vf);
9599 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9600 "%8.8x\tdw3: %8.8x\n",
9601 dw0, dw1, dw2, dw3);
9602 switch (adapter->hw.mac.type) {
9603 case ixgbe_mac_82599EB:
9604 device_id = IXGBE_82599_VF_DEVICE_ID;
9605 break;
9606 case ixgbe_mac_X540:
9607 device_id = IXGBE_X540_VF_DEVICE_ID;
9608 break;
9a75a1ac
DS		 9609 case ixgbe_mac_X550:
9610 device_id = IXGBE_DEV_ID_X550_VF;
9611 break;
9612 case ixgbe_mac_X550EM_x:
9613 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9614 break;
49425dfc
MR		 9615 case ixgbe_mac_x550em_a:
9616 device_id = IXGBE_DEV_ID_X550EM_A_VF;
9617 break;
83c61fa9
GR		 9618 default:
9619 device_id = 0;
9620 break;
9621 }
9622
9623 /* Find the pci device of the offending VF */
36e90319 9624 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9625 while (vfdev) {
9626 if (vfdev->devfn == (req_id & 0xFF))
9627 break;
36e90319 9628 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9629 device_id, vfdev);
9630 }
9631 /*
9632 * There's a slim chance the VF could have been hot plugged,
9633 * so if it is no longer present we don't need to issue the
9634 * VFLR. Just clean up the AER in that case.
9635 */
9636 if (vfdev) {
9079e416 9637 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9638 /* Free device reference count */
9639 pci_dev_put(vfdev);
83c61fa9
GR		 9640 }
9641
9642 pci_cleanup_aer_uncorrect_error_status(pdev);
9643 }
9644
9645 /*
9646 * Even though the error may have occurred on the other port
9647 * we still need to increment the vf error reference count for
9648 * both ports because the I/O resume function will be called
9649 * for both of them.
9650 */
9651 adapter->vferr_refcount++;
9652
9653 return PCI_ERS_RESULT_RECOVERED;
9654
9655skip_bad_vf_detection:
9656#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9657 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9658 return PCI_ERS_RESULT_DISCONNECT;
9659
41c62843 9660 rtnl_lock();
9a799d71
AK		 9661 netif_device_detach(netdev);
9662
41c62843
MR		 9663 if (state == pci_channel_io_perm_failure) {
9664 rtnl_unlock();
3044b8d1 9665 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9666 }
3044b8d1 9667
9a799d71
AK		 9668 if (netif_running(netdev))
9669 ixgbe_down(adapter);
41c62843
MR		 9670
9671 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9672 pci_disable_device(pdev);
9673 rtnl_unlock();
9a799d71 9674
b4617240 9675 /* Request a slot reset. */
9a799d71
AK		 9676 return PCI_ERS_RESULT_NEED_RESET;
9677}
9678
9679/**
9680 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9681 * @pdev: Pointer to PCI device
9682 *
9683 * Restart the card from scratch, as if from a cold-boot.
9684 */
9685static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9686{
c60fbb00 9687 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9688 pci_ers_result_t result;
9689 int err;
9a799d71 9690
9ce77666 9691 if (pci_enable_device_mem(pdev)) {
396e799c 9692 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9693 result = PCI_ERS_RESULT_DISCONNECT;
9694 } else {
4e857c58 9695 smp_mb__before_atomic();
41c62843 9696 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9697 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9698 pci_set_master(pdev);
9699 pci_restore_state(pdev);
c0e1f68b 9700 pci_save_state(pdev);
9a799d71 9701
dd4d8ca6 9702 pci_wake_from_d3(pdev, false);
9a799d71 9703
6fabd715 9704 ixgbe_reset(adapter);
88512539 9705 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9706 result = PCI_ERS_RESULT_RECOVERED;
9707 }
9708
9709 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9710 if (err) {
849c4542
ET		 9711 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9712 "failed 0x%0x\n", err);
6fabd715
PWJ		 9713 /* non-fatal, continue */
9714 }
9a799d71 9715
6fabd715 9716 return result;
9a799d71
AK		 9717}
9718
9719/**
9720 * ixgbe_io_resume - called when traffic can start flowing again.
9721 * @pdev: Pointer to PCI device
9722 *
9723 * This callback is called when the error recovery driver tells us that
9724 * its OK to resume normal operation.
9725 */
9726static void ixgbe_io_resume(struct pci_dev *pdev)
9727{
c60fbb00
AD		 9728 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9729 struct net_device *netdev = adapter->netdev;
9a799d71 9730
83c61fa9
GR		 9731#ifdef CONFIG_PCI_IOV
9732 if (adapter->vferr_refcount) {
9733 e_info(drv, "Resuming after VF err\n");
9734 adapter->vferr_refcount--;
9735 return;
9736 }
9737
9738#endif
c7ccde0f
AD		 9739 if (netif_running(netdev))
9740 ixgbe_up(adapter);
9a799d71
AK		 9741
9742 netif_device_attach(netdev);
9a799d71
AK		 9743}
9744
3646f0e5 9745static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9746 .error_detected = ixgbe_io_error_detected,
9747 .slot_reset = ixgbe_io_slot_reset,
9748 .resume = ixgbe_io_resume,
9749};
9750
9751static struct pci_driver ixgbe_driver = {
9752 .name = ixgbe_driver_name,
9753 .id_table = ixgbe_pci_tbl,
9754 .probe = ixgbe_probe,
9f9a12f8 9755 .remove = ixgbe_remove,
9a799d71
AK		 9756#ifdef CONFIG_PM
9757 .suspend = ixgbe_suspend,
9758 .resume = ixgbe_resume,
9759#endif
9760 .shutdown = ixgbe_shutdown,
da36b647 9761 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9762 .err_handler = &ixgbe_err_handler
9763};
9764
9765/**
9766 * ixgbe_init_module - Driver Registration Routine
9767 *
9768 * ixgbe_init_module is the first routine called when the driver is
9769 * loaded. All it does is register with the PCI subsystem.
9770 **/
9771static int __init ixgbe_init_module(void)
9772{
9773 int ret;
c7689578 9774 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9775 pr_info("%s\n", ixgbe_copyright);
9a799d71 9776
780484d8
MR		 9777 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9778 if (!ixgbe_wq) {
9779 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9780 return -ENOMEM;
9781 }
9782
00949167 9783 ixgbe_dbg_init();
00949167 9784
f01fc1a8
JK		 9785 ret = pci_register_driver(&ixgbe_driver);
9786 if (ret) {
f01fc1a8 9787 ixgbe_dbg_exit();
f01fc1a8
JK		 9788 return ret;
9789 }
9790
5dd2d332 9791#ifdef CONFIG_IXGBE_DCA
bd0362dd 9792 dca_register_notify(&dca_notifier);
bd0362dd 9793#endif
5dd2d332 9794
f01fc1a8 9795 return 0;
9a799d71 9796}
b4617240 9797
9a799d71
AK		 9798module_init(ixgbe_init_module);
9799
9800/**
9801 * ixgbe_exit_module - Driver Exit Cleanup Routine
9802 *
9803 * ixgbe_exit_module is called just before the driver is removed
9804 * from memory.
9805 **/
9806static void __exit ixgbe_exit_module(void)
9807{
5dd2d332 9808#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9809 dca_unregister_notify(&dca_notifier);
9810#endif
9a799d71 9811 pci_unregister_driver(&ixgbe_driver);
00949167 9812
00949167 9813 ixgbe_dbg_exit();
780484d8
MR		 9814 if (ixgbe_wq) {
9815 destroy_workqueue(ixgbe_wq);
9816 ixgbe_wq = NULL;
9817 }
9a799d71 9818}
bd0362dd 9819
5dd2d332 9820#ifdef CONFIG_IXGBE_DCA
bd0362dd 9821static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9822 void *p)
bd0362dd
JC		 9823{
9824 int ret_val;
9825
9826 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9827 __ixgbe_notify_dca);
bd0362dd
JC		 9828
9829 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9830}
b453368d 9831
5dd2d332 9832#endif /* CONFIG_IXGBE_DCA */
849c4542 9833
9a799d71
AK		 9834module_exit(ixgbe_exit_module);
9835
9836/* ixgbe_main.c */
Linux kernel - Deliverables
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