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ixgbe: Add timeout parameter to ixgbe_host_interface_command
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_type.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
c97506ab 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_TYPE_H_
30#define _IXGBE_TYPE_H_
31
32#include <linux/types.h>
6b73e10d 33#include <linux/mdio.h>
32e7bfc4 34#include <linux/netdevice.h>
9a799d71 35
9a799d71 36/* Device IDs */
1e336d0f 37#define IXGBE_DEV_ID_82598 0x10B6
2f21bdd3 38#define IXGBE_DEV_ID_82598_BX 0x1508
9a799d71
AK		 39#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
40#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
c4900be0 41#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
0befdb3e 42#define IXGBE_DEV_ID_82598AT 0x10C8
3845bec0 43#define IXGBE_DEV_ID_82598AT2 0x150B
9a799d71 44#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
8d792cd9 45#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
c4900be0
DS		 46#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
47#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
b95f5fcb 48#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
11afc1b1 49#define IXGBE_DEV_ID_82599_KX4 0x10F7
dbfec662 50#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
74757d49 51#define IXGBE_DEV_ID_82599_KR 0x1517
119fc60a 52#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
8911184f 53#define IXGBE_DEV_ID_82599_CX4 0x10F9
11afc1b1 54#define IXGBE_DEV_ID_82599_SFP 0x10FB
dbffcb21
DS		 55#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
56#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
0b077fea 57#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
87557440 58#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
b6dfd939 59#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
0e22d043 60#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
5700ff26 61#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
f8a06c2c 62#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
979fe5f7 63#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976
38ad1c8e 64#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
4c40ef02 65#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
7d145282 66#define IXGBE_DEV_ID_82599EN_SFP 0x1557
5daebbb0 67#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
1fcf03e6 68#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
312eb931 69#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
50d6c681 70#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
4f6290cf 71#define IXGBE_DEV_ID_82599_LS 0x154F
b93a2226 72#define IXGBE_DEV_ID_X540T 0x1528
9e791e4a 73#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
8f58332b 74#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
df376f0d 75#define IXGBE_DEV_ID_X540T1 0x1560
9a799d71 76
c6bda30a
GR		 77/* VF Device IDs */
78#define IXGBE_DEV_ID_82599_VF 0x10ED
79#define IXGBE_DEV_ID_X540_VF 0x1515
9a75a1ac
DS		 80#define IXGBE_DEV_ID_X550_VF 0x1565
81#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
c6bda30a 82
9a799d71
AK		 83/* General Registers */
84#define IXGBE_CTRL 0x00000
85#define IXGBE_STATUS 0x00008
86#define IXGBE_CTRL_EXT 0x00018
87#define IXGBE_ESDP 0x00020
88#define IXGBE_EODSDP 0x00028
9a75a1ac
DS		 89#define IXGBE_I2CCTL_BY_MAC(_hw)((((_hw)->mac.type >= ixgbe_mac_X550) ? \
90 0x15F5C : 0x00028))
9a799d71
AK		 91#define IXGBE_LEDCTL 0x00200
92#define IXGBE_FRTIMER 0x00048
93#define IXGBE_TCPTIMER 0x0004C
11afc1b1
PW		 94#define IXGBE_CORESPARE 0x00600
95#define IXGBE_EXVET 0x05078
9a799d71
AK		 96
97/* NVM Registers */
98#define IXGBE_EEC 0x10010
99#define IXGBE_EERD 0x10014
21ce849b 100#define IXGBE_EEWR 0x10018
9a799d71
AK		 101#define IXGBE_FLA 0x1001C
102#define IXGBE_EEMNGCTL 0x10110
103#define IXGBE_EEMNGDATA 0x10114
104#define IXGBE_FLMNGCTL 0x10118
105#define IXGBE_FLMNGDATA 0x1011C
106#define IXGBE_FLMNGCNT 0x10120
107#define IXGBE_FLOP 0x1013C
108#define IXGBE_GRC 0x10200
109
11afc1b1
PW		 110/* General Receive Control */
111#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
888be1a1 112#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
11afc1b1
PW		 113
114#define IXGBE_VPDDIAG0 0x10204
115#define IXGBE_VPDDIAG1 0x10208
116
117/* I2CCTL Bit Masks */
9a75a1ac
DS		 118#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
119 0x00004000 : 0x00000001)
120#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
121 0x00000200 : 0x00000002)
122#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
123 0x00001000 : 0x00000004)
124#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
125 0x00000400 : 0x00000008)
8f56e4b9 126#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
11afc1b1 127
e1ea9158
DS		 128#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
129#define IXGBE_EMC_INTERNAL_DATA 0x00
130#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
131#define IXGBE_EMC_DIODE1_DATA 0x01
132#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
133#define IXGBE_EMC_DIODE2_DATA 0x23
134#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
135
136#define IXGBE_MAX_SENSORS 3
137
138struct ixgbe_thermal_diode_data {
139 u8 location;
140 u8 temp;
141 u8 caution_thresh;
142 u8 max_op_thresh;
143};
144
145struct ixgbe_thermal_sensor_data {
146 struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
147};
148
9a799d71
AK		 149/* Interrupt Registers */
150#define IXGBE_EICR 0x00800
151#define IXGBE_EICS 0x00808
152#define IXGBE_EIMS 0x00880
153#define IXGBE_EIMC 0x00888
154#define IXGBE_EIAC 0x00810
155#define IXGBE_EIAM 0x00890
11afc1b1
PW		 156#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
157#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
158#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
159#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
509ee935
JB		 160/*
161 * 82598 EITR is 16 bits but set the limits based on the max
162 * supported by all ixgbe hardware. 82599 EITR is only 12 bits,
163 * with the lower 3 always zero.
164 */
165#define IXGBE_MAX_INT_RATE 488281
166#define IXGBE_MIN_INT_RATE 956
167#define IXGBE_MAX_EITR 0x00000FF8
168#define IXGBE_MIN_EITR 8
11afc1b1 169#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
e7cf745b 170 (0x012300 + (((_i) - 24) * 4)))
509ee935 171#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
11afc1b1
PW		 172#define IXGBE_EITR_LLI_MOD 0x00008000
173#define IXGBE_EITR_CNT_WDIS 0x80000000
c44ade9e 174#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
11afc1b1
PW		 175#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
176#define IXGBE_EITRSEL 0x00894
9a799d71
AK		 177#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
178#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
c44ade9e 179#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
9a799d71
AK		 180#define IXGBE_GPIE 0x00898
181
182/* Flow Control Registers */
11afc1b1
PW		 183#define IXGBE_FCADBUL 0x03210
184#define IXGBE_FCADBUH 0x03214
185#define IXGBE_FCAMACL 0x04328
186#define IXGBE_FCAMACH 0x0432C
187#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
188#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
9a799d71
AK		 189#define IXGBE_PFCTOP 0x03008
190#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
191#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
192#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
193#define IXGBE_FCRTV 0x032A0
11afc1b1 194#define IXGBE_FCCFG 0x03D00
9a799d71
AK		 195#define IXGBE_TFCS 0x0CE00
196
197/* Receive DMA Registers */
11afc1b1 198#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
795be954 199 (0x0D000 + (((_i) - 64) * 0x40)))
11afc1b1 200#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
795be954 201 (0x0D004 + (((_i) - 64) * 0x40)))
11afc1b1 202#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
795be954 203 (0x0D008 + (((_i) - 64) * 0x40)))
11afc1b1 204#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
795be954 205 (0x0D010 + (((_i) - 64) * 0x40)))
11afc1b1 206#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
795be954 207 (0x0D018 + (((_i) - 64) * 0x40)))
11afc1b1 208#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
795be954 209 (0x0D028 + (((_i) - 64) * 0x40)))
83dfde40 210#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
795be954 211 (0x0D02C + (((_i) - 64) * 0x40)))
83dfde40 212#define IXGBE_RSCDBU 0x03028
11afc1b1
PW		 213#define IXGBE_RDDCC 0x02F20
214#define IXGBE_RXMEMWRAP 0x03190
215#define IXGBE_STARCTRL 0x03024
c44ade9e
JB		 216/*
217 * Split and Replication Receive Control Registers
218 * 00-15 : 0x02100 + n*4
219 * 16-64 : 0x01014 + n*0x40
220 * 64-127: 0x0D014 + (n-64)*0x40
221 */
222#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
e7cf745b 223 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
795be954 224 (0x0D014 + (((_i) - 64) * 0x40))))
c44ade9e
JB		 225/*
226 * Rx DCA Control Register:
227 * 00-15 : 0x02200 + n*4
228 * 16-64 : 0x0100C + n*0x40
229 * 64-127: 0x0D00C + (n-64)*0x40
230 */
231#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
e7cf745b 232 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
795be954 233 (0x0D00C + (((_i) - 64) * 0x40))))
c44ade9e 234#define IXGBE_RDRXCTL 0x02F00
9a799d71 235#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
e7cf745b 236 /* 8 of these 0x03C00 - 0x03C1C */
9a799d71
AK		 237#define IXGBE_RXCTRL 0x03000
238#define IXGBE_DROPEN 0x03D04
239#define IXGBE_RXPBSIZE_SHIFT 10
240
241/* Receive Registers */
242#define IXGBE_RXCSUM 0x05000
243#define IXGBE_RFCTL 0x05008
c44ade9e
JB		 244#define IXGBE_DRECCCTL 0x02F08
245#define IXGBE_DRECCCTL_DISABLE 0
246/* Multicast Table Array - 128 entries */
9a799d71 247#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
11afc1b1 248#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
e7cf745b 249 (0x0A200 + ((_i) * 8)))
11afc1b1 250#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
e7cf745b 251 (0x0A204 + ((_i) * 8)))
11afc1b1
PW		 252#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
253#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
c44ade9e 254/* Packet split receive type */
11afc1b1 255#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
e7cf745b 256 (0x0EA00 + ((_i) * 4)))
c44ade9e 257/* array of 4096 1-bit vlan filters */
9a799d71 258#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
c44ade9e 259/*array of 4096 4-bit vlan vmdq indices */
9a799d71 260#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
9a799d71
AK		 261#define IXGBE_FCTRL 0x05080
262#define IXGBE_VLNCTRL 0x05088
263#define IXGBE_MCSTCTRL 0x05090
264#define IXGBE_MRQC 0x05818
11afc1b1
PW		 265#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
266#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
267#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
268#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
269#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
270#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
271#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
272#define IXGBE_RQTC 0x0EC70
273#define IXGBE_MTQC 0x08120
274#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
275#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
7f01648a 276#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
83dfde40
ET		 277#define IXGBE_VT_CTL 0x051B0
278#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
279#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
280#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
281#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
282#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
283#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
284#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
285#define IXGBE_QDE 0x2F04
286#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
287#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
288#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
289#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
290#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
291#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
292#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
293#define IXGBE_RXFECCERR0 0x051B8
11afc1b1 294#define IXGBE_LLITHRESH 0x0EC90
9a799d71
AK		 295#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
296#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
297#define IXGBE_IMIRVP 0x05AC0
c44ade9e 298#define IXGBE_VMD_CTL 0x0581C
9a799d71 299#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
0f9b232b 300#define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */
9a799d71
AK		 301#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
302
9a75a1ac
DS		 303/* Registers for setting up RSS on X550 with SRIOV
304 * _p - pool number (0..63)
305 * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
306 */
307#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4))
308#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
309#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
310
bfde493e
PWJ		 311/* Flow Director registers */
312#define IXGBE_FDIRCTRL 0x0EE00
313#define IXGBE_FDIRHKEY 0x0EE68
314#define IXGBE_FDIRSKEY 0x0EE6C
315#define IXGBE_FDIRDIP4M 0x0EE3C
316#define IXGBE_FDIRSIP4M 0x0EE40
317#define IXGBE_FDIRTCPM 0x0EE44
318#define IXGBE_FDIRUDPM 0x0EE48
319#define IXGBE_FDIRIP6M 0x0EE74
320#define IXGBE_FDIRM 0x0EE70
321
322/* Flow Director Stats registers */
323#define IXGBE_FDIRFREE 0x0EE38
324#define IXGBE_FDIRLEN 0x0EE4C
325#define IXGBE_FDIRUSTAT 0x0EE50
326#define IXGBE_FDIRFSTAT 0x0EE54
327#define IXGBE_FDIRMATCH 0x0EE58
328#define IXGBE_FDIRMISS 0x0EE5C
329
330/* Flow Director Programming registers */
331#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
332#define IXGBE_FDIRIPSA 0x0EE18
333#define IXGBE_FDIRIPDA 0x0EE1C
334#define IXGBE_FDIRPORT 0x0EE20
335#define IXGBE_FDIRVLAN 0x0EE24
336#define IXGBE_FDIRHASH 0x0EE28
337#define IXGBE_FDIRCMD 0x0EE2C
338
9a799d71 339/* Transmit DMA registers */
c44ade9e 340#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
9a799d71
AK		 341#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
342#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
343#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
344#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
345#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
346#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
347#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
348#define IXGBE_DTXCTL 0x07E00
c44ade9e 349
a985b6c3
GR		 350#define IXGBE_DMATXCTL 0x04A80
351#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
7f870475 352#define IXGBE_PFDTXGSWC 0x08220
11afc1b1
PW		 353#define IXGBE_DTXMXSZRQ 0x08100
354#define IXGBE_DTXTCPFLGL 0x04A88
355#define IXGBE_DTXTCPFLGH 0x04A8C
356#define IXGBE_LBDRPEN 0x0CA00
357#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
358
359#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
360#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
361#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
362#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
7f870475
GR		 363
364#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
a985b6c3
GR		 365
366/* Anti-spoofing defines */
367#define IXGBE_SPOOF_MACAS_MASK 0xFF
368#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
369#define IXGBE_SPOOF_VLANAS_SHIFT 8
370#define IXGBE_PFVFSPOOF_REG_COUNT 8
371
c44ade9e 372#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
11afc1b1
PW		 373/* Tx DCA Control register : 128 of these (0-127) */
374#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
9a799d71 375#define IXGBE_TIPG 0x0CB00
c44ade9e 376#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 377#define IXGBE_MNGTXMAP 0x0CD10
378#define IXGBE_TIPG_FIBER_DEFAULT 3
379#define IXGBE_TXPBSIZE_SHIFT 10
380
381/* Wake up registers */
382#define IXGBE_WUC 0x05800
383#define IXGBE_WUFC 0x05808
384#define IXGBE_WUS 0x05810
385#define IXGBE_IPAV 0x05838
386#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
387#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
c44ade9e 388
9a799d71
AK		 389#define IXGBE_WUPL 0x05900
390#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
795be954
AD		 391#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
392#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
393 * Filter Table */
11afc1b1
PW		 394
395#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
396#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
397
398/* Each Flexible Filter is at most 128 (0x80) bytes in length */
399#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
400#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
401#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
402
403/* Definitions for power management and wakeup registers */
404/* Wake Up Control */
405#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
406#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
888be1a1 407#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
11afc1b1
PW		 408
409/* Wake Up Filter Control */
410#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
411#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
412#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
413#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
414#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
415#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
416#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
417#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
418#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
419
420#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
421#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
422#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
423#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
424#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
425#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
426#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
427#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
428#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
83dfde40 429#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
11afc1b1
PW		 430#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
431
432/* Wake Up Status */
433#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
434#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
435#define IXGBE_WUS_EX IXGBE_WUFC_EX
436#define IXGBE_WUS_MC IXGBE_WUFC_MC
437#define IXGBE_WUS_BC IXGBE_WUFC_BC
438#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
439#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
440#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
441#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
442#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
443#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
444#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
445#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
446#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
447#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
448#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
449
450/* Wake Up Packet Length */
451#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
452
453/* DCB registers */
9da712d2 454#define MAX_TRAFFIC_CLASS 8
4de2a022 455#define X540_TRAFFIC_CLASS 4
9a799d71
AK		 456#define IXGBE_RMCS 0x03D00
457#define IXGBE_DPMCS 0x07F40
458#define IXGBE_PDPMCS 0x0CD00
459#define IXGBE_RUPPBMR 0x050A0
460#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
461#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
462#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
463#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
464#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
465#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
466
c44ade9e 467
11afc1b1
PW		 468/* Security Control Registers */
469#define IXGBE_SECTXCTRL 0x08800
470#define IXGBE_SECTXSTAT 0x08804
471#define IXGBE_SECTXBUFFAF 0x08808
472#define IXGBE_SECTXMINIFG 0x08810
11afc1b1
PW		 473#define IXGBE_SECRXCTRL 0x08D00
474#define IXGBE_SECRXSTAT 0x08D04
475
476/* Security Bit Fields and Masks */
477#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
478#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
479#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
480
481#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
482#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
483
484#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
485#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
486
487#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
488#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
489
490/* LinkSec (MacSec) Registers */
491#define IXGBE_LSECTXCAP 0x08A00
492#define IXGBE_LSECRXCAP 0x08F00
493#define IXGBE_LSECTXCTRL 0x08A04
494#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
495#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
496#define IXGBE_LSECTXSA 0x08A10
497#define IXGBE_LSECTXPN0 0x08A14
498#define IXGBE_LSECTXPN1 0x08A18
499#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
500#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
501#define IXGBE_LSECRXCTRL 0x08F04
502#define IXGBE_LSECRXSCL 0x08F08
503#define IXGBE_LSECRXSCH 0x08F0C
504#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
505#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
506#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
507#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
508#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
509#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
510#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
511#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
512#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
513#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
514#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
515#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
516#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
517#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
518#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
519#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
520#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
521#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
522#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
523#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
524#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
525#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
526
527/* LinkSec (MacSec) Bit Fields and Masks */
528#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
529#define IXGBE_LSECTXCAP_SUM_SHIFT 16
530#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
531#define IXGBE_LSECRXCAP_SUM_SHIFT 16
532
533#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
534#define IXGBE_LSECTXCTRL_DISABLE 0x0
535#define IXGBE_LSECTXCTRL_AUTH 0x1
536#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
537#define IXGBE_LSECTXCTRL_AISCI 0x00000020
538#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
539#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
540
541#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
542#define IXGBE_LSECRXCTRL_EN_SHIFT 2
543#define IXGBE_LSECRXCTRL_DISABLE 0x0
544#define IXGBE_LSECRXCTRL_CHECK 0x1
545#define IXGBE_LSECRXCTRL_STRICT 0x2
546#define IXGBE_LSECRXCTRL_DROP 0x3
547#define IXGBE_LSECRXCTRL_PLSH 0x00000040
548#define IXGBE_LSECRXCTRL_RP 0x00000080
549#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
550
551/* IpSec Registers */
552#define IXGBE_IPSTXIDX 0x08900
553#define IXGBE_IPSTXSALT 0x08904
554#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
555#define IXGBE_IPSRXIDX 0x08E00
556#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
557#define IXGBE_IPSRXSPI 0x08E14
558#define IXGBE_IPSRXIPIDX 0x08E18
559#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
560#define IXGBE_IPSRXSALT 0x08E2C
561#define IXGBE_IPSRXMOD 0x08E30
562
563#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
564
565/* DCB registers */
566#define IXGBE_RTRPCS 0x02430
567#define IXGBE_RTTDCS 0x04900
7f870475 568#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
11afc1b1
PW		 569#define IXGBE_RTTPCS 0x0CD00
570#define IXGBE_RTRUP2TC 0x03020
571#define IXGBE_RTTUP2TC 0x0C800
572#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
83dfde40 573#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
11afc1b1
PW		 574#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
575#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
576#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
577#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
578#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
579#define IXGBE_RTTDQSEL 0x04904
580#define IXGBE_RTTDT1C 0x04908
581#define IXGBE_RTTDT1S 0x0490C
51e409f1
LP		 582#define IXGBE_RTTQCNCR 0x08B00
583#define IXGBE_RTTQCNTG 0x04A90
584#define IXGBE_RTTBCNRD 0x0498C
585#define IXGBE_RTTQCNRR 0x0498C
11afc1b1
PW		 586#define IXGBE_RTTDTECC 0x04990
587#define IXGBE_RTTDTECC_NO_BCN 0x00000100
588#define IXGBE_RTTBCNRC 0x04984
ff4ab206
LL		 589#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
590#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
591#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
592#define IXGBE_RTTBCNRC_RF_INT_MASK \
593 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
7555e83d 594#define IXGBE_RTTBCNRM 0x04980
51e409f1 595#define IXGBE_RTTQCNRM 0x04980
c44ade9e 596
83dfde40 597/* FCoE DMA Context Registers */
bff66176
YZ		 598#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
599#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
600#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
601#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
602#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
603#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
604#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
605#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
606#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
607#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
608#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
609#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
610#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
611#define IXGBE_FCBUFF_OFFSET_SHIFT 16
612#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
613#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
614#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
615#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
616#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
617
618/* FCoE SOF/EOF */
619#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
620#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
621#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
622#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
623/* FCoE Filter Context Registers */
624#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
625#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
626#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
627#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
628#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
629#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
630#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
631#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
632#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
633#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
634/* FCoE Receive Control */
635#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
636#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
637#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
638#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
639#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
640#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
641#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
642#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
643#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
644#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
645#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
646/* FCoE Redirection */
647#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
648#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
649#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
650#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
651#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
652#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
653
9a799d71
AK		 654/* Stats registers */
655#define IXGBE_CRCERRS 0x04000
656#define IXGBE_ILLERRC 0x04004
657#define IXGBE_ERRBC 0x04008
658#define IXGBE_MSPDC 0x04010
659#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
660#define IXGBE_MLFC 0x04034
661#define IXGBE_MRFC 0x04038
662#define IXGBE_RLEC 0x04040
663#define IXGBE_LXONTXC 0x03F60
664#define IXGBE_LXONRXC 0x0CF60
665#define IXGBE_LXOFFTXC 0x03F68
666#define IXGBE_LXOFFRXC 0x0CF68
11afc1b1
PW		 667#define IXGBE_LXONRXCNT 0x041A4
668#define IXGBE_LXOFFRXCNT 0x041A8
669#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
670#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
671#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 672#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
673#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
674#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
675#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
676#define IXGBE_PRC64 0x0405C
677#define IXGBE_PRC127 0x04060
678#define IXGBE_PRC255 0x04064
679#define IXGBE_PRC511 0x04068
680#define IXGBE_PRC1023 0x0406C
681#define IXGBE_PRC1522 0x04070
682#define IXGBE_GPRC 0x04074
683#define IXGBE_BPRC 0x04078
684#define IXGBE_MPRC 0x0407C
685#define IXGBE_GPTC 0x04080
686#define IXGBE_GORCL 0x04088
687#define IXGBE_GORCH 0x0408C
688#define IXGBE_GOTCL 0x04090
689#define IXGBE_GOTCH 0x04094
690#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
691#define IXGBE_RUC 0x040A4
692#define IXGBE_RFC 0x040A8
693#define IXGBE_ROC 0x040AC
694#define IXGBE_RJC 0x040B0
695#define IXGBE_MNGPRC 0x040B4
696#define IXGBE_MNGPDC 0x040B8
697#define IXGBE_MNGPTC 0x0CF90
698#define IXGBE_TORL 0x040C0
699#define IXGBE_TORH 0x040C4
700#define IXGBE_TPR 0x040D0
701#define IXGBE_TPT 0x040D4
702#define IXGBE_PTC64 0x040D8
703#define IXGBE_PTC127 0x040DC
704#define IXGBE_PTC255 0x040E0
705#define IXGBE_PTC511 0x040E4
706#define IXGBE_PTC1023 0x040E8
707#define IXGBE_PTC1522 0x040EC
708#define IXGBE_MPTC 0x040F0
709#define IXGBE_BPTC 0x040F4
710#define IXGBE_XEC 0x04120
11afc1b1 711#define IXGBE_SSVPC 0x08780
9a799d71 712
11afc1b1
PW		 713#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
714#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
e7cf745b 715 (0x08600 + ((_i) * 4)))
11afc1b1 716#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
9a799d71
AK		 717
718#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
719#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
720#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
721#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
667c7565
ET		 722#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
723#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
11afc1b1
PW		 724#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
725#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
726#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
bff66176
YZ		 727#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
728#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
729#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
730#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
731#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
732#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
733#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
58f6bcf9
ET		 734#define IXGBE_O2BGPTC 0x041C4
735#define IXGBE_O2BSPC 0x087B0
736#define IXGBE_B2OSPC 0x041C0
737#define IXGBE_B2OGPRC 0x02F90
a3aeea0e
ET		 738#define IXGBE_PCRC8ECL 0x0E810
739#define IXGBE_PCRC8ECH 0x0E811
740#define IXGBE_PCRC8ECH_MASK 0x1F
741#define IXGBE_LDPCECL 0x0E820
742#define IXGBE_LDPCECH 0x0E821
9a799d71
AK		 743
744/* Management */
745#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
746#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
747#define IXGBE_MANC 0x05820
748#define IXGBE_MFVAL 0x05824
749#define IXGBE_MANC2H 0x05860
750#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
751#define IXGBE_MIPAF 0x058B0
752#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
753#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
754#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
11afc1b1
PW		 755#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
756#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
757#define IXGBE_LSWFW 0x15014
9a799d71 758
0b2679d6
DS		 759/* Management Bit Fields and Masks */
760#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */
761
762/* Firmware Semaphore Register */
763#define IXGBE_FWSM_MODE_MASK 0xE
764#define IXGBE_FWSM_FW_MODE_PT 0x4
765
9a799d71
AK		 766/* ARC Subsystem registers */
767#define IXGBE_HICR 0x15F00
768#define IXGBE_FWSTS 0x15F0C
769#define IXGBE_HSMC0R 0x15F04
770#define IXGBE_HSMC1R 0x15F08
771#define IXGBE_SWSR 0x15F10
772#define IXGBE_HFDR 0x15FE8
773#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
774
9612de92
ET		 775#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */
776/* Driver sets this bit when done to put command in RAM */
777#define IXGBE_HICR_C 0x02
778#define IXGBE_HICR_SV 0x04 /* Status Validity */
779#define IXGBE_HICR_FW_RESET_ENABLE 0x40
780#define IXGBE_HICR_FW_RESET 0x80
781
9a799d71
AK		 782/* PCI-E registers */
783#define IXGBE_GCR 0x11000
784#define IXGBE_GTV 0x11004
785#define IXGBE_FUNCTAG 0x11008
786#define IXGBE_GLT 0x1100C
787#define IXGBE_GSCL_1 0x11010
788#define IXGBE_GSCL_2 0x11014
789#define IXGBE_GSCL_3 0x11018
790#define IXGBE_GSCL_4 0x1101C
791#define IXGBE_GSCN_0 0x11020
792#define IXGBE_GSCN_1 0x11024
793#define IXGBE_GSCN_2 0x11028
794#define IXGBE_GSCN_3 0x1102C
795#define IXGBE_FACTPS 0x10150
796#define IXGBE_PCIEANACTL 0x11040
797#define IXGBE_SWSM 0x10140
798#define IXGBE_FWSM 0x10148
799#define IXGBE_GSSR 0x10160
800#define IXGBE_MREVID 0x11064
801#define IXGBE_DCA_ID 0x11070
802#define IXGBE_DCA_CTRL 0x11074
21ce849b 803#define IXGBE_SWFW_SYNC IXGBE_GSSR
9a799d71 804
11afc1b1
PW		 805/* PCIe registers 82599-specific */
806#define IXGBE_GCR_EXT 0x11050
807#define IXGBE_GSCL_5_82599 0x11030
808#define IXGBE_GSCL_6_82599 0x11034
809#define IXGBE_GSCL_7_82599 0x11038
810#define IXGBE_GSCL_8_82599 0x1103C
811#define IXGBE_PHYADR_82599 0x11040
812#define IXGBE_PHYDAT_82599 0x11044
813#define IXGBE_PHYCTL_82599 0x11048
814#define IXGBE_PBACLR_82599 0x11068
815#define IXGBE_CIAA_82599 0x11088
816#define IXGBE_CIAD_82599 0x1108C
9a75a1ac
DS		 817#define IXGBE_CIAA_X550 0x11508
818#define IXGBE_CIAD_X550 0x11510
819#define IXGBE_CIAA_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
820 IXGBE_CIAA_X550 : IXGBE_CIAA_82599))
821#define IXGBE_CIAD_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
822 IXGBE_CIAD_X550 : IXGBE_CIAD_82599))
83dfde40
ET		 823#define IXGBE_PICAUSE 0x110B0
824#define IXGBE_PIENA 0x110B8
11afc1b1 825#define IXGBE_CDQ_MBR_82599 0x110B4
83dfde40 826#define IXGBE_PCIESPARE 0x110BC
11afc1b1
PW		 827#define IXGBE_MISC_REG_82599 0x110F0
828#define IXGBE_ECC_CTRL_0_82599 0x11100
829#define IXGBE_ECC_CTRL_1_82599 0x11104
830#define IXGBE_ECC_STATUS_82599 0x110E0
831#define IXGBE_BAR_CTRL_82599 0x110F4
832
202ff1ec
MC		 833/* PCI Express Control */
834#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
835#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
836#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
837#define IXGBE_GCR_CAP_VER2 0x00040000
838
7f870475 839#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
ff9d1a5a 840#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
7f870475
GR		 841#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
842#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
843#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
844#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
e7cf745b 845 IXGBE_GCR_EXT_VT_MODE_64)
7f870475 846
11afc1b1
PW		 847/* Time Sync Registers */
848#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
849#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
850#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
851#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
852#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
853#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
854#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
855#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
856#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
857#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
858#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
859#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
83dfde40
ET		 860#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
861#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
862#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
863#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
864#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
865#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
866#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
681ae1ad
JK		 867#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */
868#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */
83dfde40
ET		 869#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
870#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
871#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
872#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
873#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
874#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
11afc1b1 875
9a799d71 876/* Diagnostic Registers */
c44ade9e
JB		 877#define IXGBE_RDSTATCTL 0x02C20
878#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
879#define IXGBE_RDHMPN 0x02F08
98c00a1c 880#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
c44ade9e 881#define IXGBE_RDPROBE 0x02F20
11afc1b1
PW		 882#define IXGBE_RDMAM 0x02F30
883#define IXGBE_RDMAD 0x02F34
c44ade9e
JB		 884#define IXGBE_TDSTATCTL 0x07C20
885#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
886#define IXGBE_TDHMPN 0x07F08
11afc1b1
PW		 887#define IXGBE_TDHMPN2 0x082FC
888#define IXGBE_TXDESCIC 0x082CC
98c00a1c 889#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
11afc1b1 890#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
c44ade9e
JB		 891#define IXGBE_TDPROBE 0x07F20
892#define IXGBE_TXBUFCTRL 0x0C600
9a799d71
AK		 893#define IXGBE_TXBUFDATA0 0x0C610
894#define IXGBE_TXBUFDATA1 0x0C614
895#define IXGBE_TXBUFDATA2 0x0C618
896#define IXGBE_TXBUFDATA3 0x0C61C
897#define IXGBE_RXBUFCTRL 0x03600
898#define IXGBE_RXBUFDATA0 0x03610
899#define IXGBE_RXBUFDATA1 0x03614
900#define IXGBE_RXBUFDATA2 0x03618
901#define IXGBE_RXBUFDATA3 0x0361C
902#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
903#define IXGBE_RFVAL 0x050A4
904#define IXGBE_MDFTC1 0x042B8
905#define IXGBE_MDFTC2 0x042C0
906#define IXGBE_MDFTFIFO1 0x042C4
907#define IXGBE_MDFTFIFO2 0x042C8
908#define IXGBE_MDFTS 0x042CC
909#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
910#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
911#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
912#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
913#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
914#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
915#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
916#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
917#define IXGBE_PCIEECCCTL 0x1106C
83dfde40
ET		 918#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
919#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
920#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
921#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
922#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
923#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
924#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
925#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
11afc1b1
PW		 926#define IXGBE_PCIEECCCTL0 0x11100
927#define IXGBE_PCIEECCCTL1 0x11104
83dfde40
ET		 928#define IXGBE_RXDBUECC 0x03F70
929#define IXGBE_TXDBUECC 0x0CF70
930#define IXGBE_RXDBUEST 0x03F74
931#define IXGBE_TXDBUEST 0x0CF74
9a799d71
AK		 932#define IXGBE_PBTXECC 0x0C300
933#define IXGBE_PBRXECC 0x03300
934#define IXGBE_GHECCR 0x110B0
935
936/* MAC Registers */
937#define IXGBE_PCS1GCFIG 0x04200
938#define IXGBE_PCS1GLCTL 0x04208
939#define IXGBE_PCS1GLSTA 0x0420C
940#define IXGBE_PCS1GDBG0 0x04210
941#define IXGBE_PCS1GDBG1 0x04214
942#define IXGBE_PCS1GANA 0x04218
943#define IXGBE_PCS1GANLP 0x0421C
944#define IXGBE_PCS1GANNP 0x04220
945#define IXGBE_PCS1GANLPNP 0x04224
946#define IXGBE_HLREG0 0x04240
947#define IXGBE_HLREG1 0x04244
948#define IXGBE_PAP 0x04248
949#define IXGBE_MACA 0x0424C
950#define IXGBE_APAE 0x04250
951#define IXGBE_ARD 0x04254
952#define IXGBE_AIS 0x04258
953#define IXGBE_MSCA 0x0425C
954#define IXGBE_MSRWD 0x04260
955#define IXGBE_MLADD 0x04264
956#define IXGBE_MHADD 0x04268
11afc1b1 957#define IXGBE_MAXFRS 0x04268
9a799d71
AK		 958#define IXGBE_TREG 0x0426C
959#define IXGBE_PCSS1 0x04288
960#define IXGBE_PCSS2 0x0428C
961#define IXGBE_XPCSS 0x04290
11afc1b1 962#define IXGBE_MFLCN 0x04294
9a799d71
AK		 963#define IXGBE_SERDESC 0x04298
964#define IXGBE_MACS 0x0429C
965#define IXGBE_AUTOC 0x042A0
966#define IXGBE_LINKS 0x042A4
11afc1b1 967#define IXGBE_LINKS2 0x04324
9a799d71
AK		 968#define IXGBE_AUTOC2 0x042A8
969#define IXGBE_AUTOC3 0x042AC
970#define IXGBE_ANLP1 0x042B0
971#define IXGBE_ANLP2 0x042B4
83dfde40 972#define IXGBE_MACC 0x04330
9a799d71 973#define IXGBE_ATLASCTL 0x04800
11afc1b1
PW		 974#define IXGBE_MMNGC 0x042D0
975#define IXGBE_ANLPNP1 0x042D4
976#define IXGBE_ANLPNP2 0x042D8
977#define IXGBE_KRPCSFC 0x042E0
978#define IXGBE_KRPCSS 0x042E4
979#define IXGBE_FECS1 0x042E8
980#define IXGBE_FECS2 0x042EC
981#define IXGBE_SMADARCTL 0x14F10
982#define IXGBE_MPVC 0x04318
983#define IXGBE_SGMIIC 0x04314
984
83dfde40
ET		 985/* Statistics Registers */
986#define IXGBE_RXNFGPC 0x041B0
987#define IXGBE_RXNFGBCL 0x041B4
988#define IXGBE_RXNFGBCH 0x041B8
989#define IXGBE_RXDGPC 0x02F50
990#define IXGBE_RXDGBCL 0x02F54
991#define IXGBE_RXDGBCH 0x02F58
992#define IXGBE_RXDDGPC 0x02F5C
993#define IXGBE_RXDDGBCL 0x02F60
994#define IXGBE_RXDDGBCH 0x02F64
995#define IXGBE_RXLPBKGPC 0x02F68
996#define IXGBE_RXLPBKGBCL 0x02F6C
997#define IXGBE_RXLPBKGBCH 0x02F70
998#define IXGBE_RXDLPBKGPC 0x02F74
999#define IXGBE_RXDLPBKGBCL 0x02F78
1000#define IXGBE_RXDLPBKGBCH 0x02F7C
1001#define IXGBE_TXDGPC 0x087A0
1002#define IXGBE_TXDGBCL 0x087A4
1003#define IXGBE_TXDGBCH 0x087A8
1004
1005#define IXGBE_RXDSTATCTRL 0x02F40
1006
1007/* Copper Pond 2 link timeout */
734e979f
MC		 1008#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1009
11afc1b1
PW		 1010/* Omer CORECTL */
1011#define IXGBE_CORECTL 0x014F00
1012/* BARCTRL */
83dfde40
ET		 1013#define IXGBE_BARCTRL 0x110F4
1014#define IXGBE_BARCTRL_FLSIZE 0x0700
1015#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
1016#define IXGBE_BARCTRL_CSRSIZE 0x2000
1017
1018/* RSCCTL Bit Masks */
1019#define IXGBE_RSCCTL_RSCEN 0x01
1020#define IXGBE_RSCCTL_MAXDESC_1 0x00
1021#define IXGBE_RSCCTL_MAXDESC_4 0x04
1022#define IXGBE_RSCCTL_MAXDESC_8 0x08
1023#define IXGBE_RSCCTL_MAXDESC_16 0x0C
1024
1025/* RSCDBU Bit Masks */
1026#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1027#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
9a799d71 1028
cc41ac7c
JB		 1029/* RDRXCTL Bit Masks */
1030#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
11afc1b1 1031#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
cc41ac7c
JB		 1032#define IXGBE_RDRXCTL_MVMEN 0x00000020
1033#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
11afc1b1 1034#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
83dfde40
ET		 1035#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
1036#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
7367096a
AD		 1037#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
1038#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
11afc1b1
PW		 1039
1040/* RQTC Bit Masks and Shifts */
1041#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1042#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1043#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1044#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1045#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1046#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1047#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1048#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1049#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1050
1051/* PSRTYPE.RQPL Bit masks and shift */
1052#define IXGBE_PSRTYPE_RQPL_MASK 0x7
1053#define IXGBE_PSRTYPE_RQPL_SHIFT 29
9a799d71
AK		 1054
1055/* CTRL Bit Masks */
1056#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
1057#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
1058#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
8132b54e 1059#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
9a799d71
AK		 1060
1061/* FACTPS */
0b2679d6 1062#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */
9a799d71
AK		 1063#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
1064
1065/* MHADD Bit Masks */
1066#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1067#define IXGBE_MHADD_MFS_SHIFT 16
1068
1069/* Extended Device Control */
11afc1b1 1070#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
9a799d71
AK		 1071#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
1072#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1073#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1074
1075/* Direct Cache Access (DCA) definitions */
1076#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
1077#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1078
1079#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1080#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1081
1082#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
11afc1b1
PW		 1083#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1084#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
9a799d71
AK		 1085#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
1086#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
1087#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
15005a32 1088#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
bdda1a61
AD		 1089#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
1090#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
9a799d71
AK		 1091
1092#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
11afc1b1
PW		 1093#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1094#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
9a799d71 1095#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
bdda1a61
AD		 1096#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
1097#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
1098#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
9a799d71
AK		 1099#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1100
1101/* MSCA Bit Masks */
1102#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
1103#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1104#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
1105#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
1106#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
1107#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
1108#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
1109#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
1110#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
1111#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
83dfde40
ET		 1112#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */
1113#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/
9a799d71
AK		 1114#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
1115#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
1116#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
1117#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
1118#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
1119#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
1120
1121/* MSRWD bit masks */
c44ade9e
JB		 1122#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1123#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1124#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1125#define IXGBE_MSRWD_READ_DATA_SHIFT 16
9a799d71
AK		 1126
1127/* Atlas registers */
1128#define IXGBE_ATLAS_PDN_LPBK 0x24
1129#define IXGBE_ATLAS_PDN_10G 0xB
1130#define IXGBE_ATLAS_PDN_1G 0xC
1131#define IXGBE_ATLAS_PDN_AN 0xD
1132
1133/* Atlas bit masks */
1134#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1135#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1136#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1137#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1138#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1139
11afc1b1
PW		 1140/* Omer bit masks */
1141#define IXGBE_CORECTL_WRITE_CMD 0x00010000
c44ade9e 1142
6b73e10d 1143/* MDIO definitions */
9a799d71 1144
c44ade9e
JB		 1145#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
1146
9a799d71
AK		 1147#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
1148#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1149#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1150#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1151#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1152#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1153
11afc1b1 1154#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
c44ade9e
JB		 1155#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1156#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1157
9dda1736
ET		 1158/* MII clause 22/28 definitions */
1159#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1160#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1161#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1162#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1163#define IXGBE_MII_AUTONEG_REG 0x0
1164
9a799d71
AK		 1165#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1166#define IXGBE_MAX_PHY_ADDR 32
1167
11afc1b1 1168/* PHY IDs*/
0befdb3e
JB		 1169#define TN1010_PHY_ID 0x00A19410
1170#define TNX_FW_REV 0xB
2b264909 1171#define X540_PHY_ID 0x01540200
9a799d71 1172#define QT2022_PHY_ID 0x0043A400
c4900be0 1173#define ATH_PHY_ID 0x03429050
fe15e8e1 1174#define AQ_FW_REV 0x20
9a799d71 1175
c44ade9e
JB		 1176/* PHY Types */
1177#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1178
c4900be0
DS		 1179/* Special PHY Init Routine */
1180#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1181#define IXGBE_PHY_INIT_END_NL 0xFFFF
1182#define IXGBE_CONTROL_MASK_NL 0xF000
1183#define IXGBE_DATA_MASK_NL 0x0FFF
1184#define IXGBE_CONTROL_SHIFT_NL 12
1185#define IXGBE_DELAY_NL 0
1186#define IXGBE_DATA_NL 1
1187#define IXGBE_CONTROL_NL 0x000F
1188#define IXGBE_CONTROL_EOL_NL 0x0FFF
1189#define IXGBE_CONTROL_SOL_NL 0x0000
1190
9a799d71 1191/* General purpose Interrupt Enable */
c44ade9e
JB		 1192#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1193#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
11afc1b1 1194#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
c44ade9e
JB		 1195#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1196#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1197#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1198#define IXGBE_GPIE_EIAME 0x40000000
1199#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
83dfde40 1200#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
11afc1b1
PW		 1201#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1202#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1203#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1204#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
9a799d71 1205
80605c65
JF		 1206/* Packet Buffer Initialization */
1207#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
1208#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
1209#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
1210#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
1211#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
1212#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
1213#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/
1214#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/
1215
1216#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
1217#define IXGBE_MAX_PB 8
1218
1219/* Packet buffer allocation strategies */
1220enum {
1221 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
1222#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1223 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
1224#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1225};
1226
9a799d71
AK		 1227/* Transmit Flow Control status */
1228#define IXGBE_TFCS_TXOFF 0x00000001
1229#define IXGBE_TFCS_TXOFF0 0x00000100
1230#define IXGBE_TFCS_TXOFF1 0x00000200
1231#define IXGBE_TFCS_TXOFF2 0x00000400
1232#define IXGBE_TFCS_TXOFF3 0x00000800
1233#define IXGBE_TFCS_TXOFF4 0x00001000
1234#define IXGBE_TFCS_TXOFF5 0x00002000
1235#define IXGBE_TFCS_TXOFF6 0x00004000
1236#define IXGBE_TFCS_TXOFF7 0x00008000
1237
1238/* TCP Timer */
1239#define IXGBE_TCPTIMER_KS 0x00000100
1240#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1241#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1242#define IXGBE_TCPTIMER_LOOP 0x00000800
1243#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1244
1245/* HLREG0 Bit Masks */
1246#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1247#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1248#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1249#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1250#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1251#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1252#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1253#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1254#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1255#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1256#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1257#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1258#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1259#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1260#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1261
1262/* VMD_CTL bitmasks */
1263#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1264#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1265
11afc1b1
PW		 1266/* VT_CTL bitmasks */
1267#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1268#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1269#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
6e4e87d6
DS		 1270#define IXGBE_VT_CTL_POOL_SHIFT 7
1271#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
11afc1b1
PW		 1272
1273/* VMOLR bitmasks */
1274#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1275#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1276#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1277#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1278#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1279
1280/* VFRE bitmask */
1281#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1282
7f870475
GR		 1283#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1284
9a799d71
AK		 1285/* RDHMPN and TDHMPN bitmasks */
1286#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1287#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1288#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1289#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1290#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1291#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1292
11afc1b1
PW		 1293#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1294#define IXGBE_RDMAM_DWORD_SHIFT 9
1295#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1296#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1297#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1298#define IXGBE_RDMAM_WB_COLL_FIFO 5
1299#define IXGBE_RDMAM_QSC_CNT_RAM 6
1300#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1301#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1302#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1303#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1304#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1305#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1306#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1307#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1308#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1309#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1310#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1311#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1312#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1313#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1314#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1315#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1316
1317#define IXGBE_TXDESCIC_READY 0x80000000
1318
9a799d71
AK		 1319/* Receive Checksum Control */
1320#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1321#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1322
1323/* FCRTL Bit Masks */
11afc1b1
PW		 1324#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1325#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
9a799d71
AK		 1326
1327/* PAP bit masks*/
1328#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1329
1330/* RMCS Bit Masks */
c44ade9e 1331#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
9a799d71
AK		 1332/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1333#define IXGBE_RMCS_RAC 0x00000004
1334#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
11afc1b1
PW		 1335#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1336#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
9a799d71
AK		 1337#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1338
11afc1b1
PW		 1339/* FCCFG Bit Masks */
1340#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1341#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
c44ade9e 1342
9a799d71
AK		 1343/* Interrupt register bitmasks */
1344
1345/* Extended Interrupt Cause Read */
1346#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
11afc1b1
PW		 1347#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1348#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1349#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1350#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
9a799d71 1351#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
11afc1b1 1352#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
c44ade9e 1353#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
4f51bf70 1354#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
681ae1ad 1355#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
c44ade9e
JB		 1356#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1357#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
11afc1b1
PW		 1358#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1359#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
9a799d71
AK		 1360#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1361#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1362#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1363#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1364
1365/* Extended Interrupt Cause Set */
1366#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1367#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1368#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1369#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1370#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
c44ade9e
JB		 1371#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1372#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
681ae1ad 1373#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
c44ade9e
JB		 1374#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1375#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1376#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1377#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e
JB		 1378#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1379#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
9a799d71
AK		 1380#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1381#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1382
1383/* Extended Interrupt Mask Set */
1384#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1385#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1386#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1387#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1388#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
9a799d71
AK		 1389#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1390#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
4f51bf70 1391#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */
681ae1ad 1392#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
c44ade9e
JB		 1393#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1394#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1395#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1396#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e 1397#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
9a799d71
AK		 1398#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1399#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1400#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1401
1402/* Extended Interrupt Mask Clear */
1403#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1404#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1405#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1406#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1407#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
9a799d71
AK		 1408#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1409#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
681ae1ad 1410#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
c44ade9e
JB		 1411#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1412#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1413#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1414#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e
JB		 1415#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1416#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
9a799d71
AK		 1417#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1418#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1419
c44ade9e 1420#define IXGBE_EIMS_ENABLE_MASK ( \
e7cf745b
JK		 1421 IXGBE_EIMS_RTX_QUEUE | \
1422 IXGBE_EIMS_LSC | \
1423 IXGBE_EIMS_TCP_TIMER | \
1424 IXGBE_EIMS_OTHER)
9a799d71 1425
c44ade9e 1426/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
9a799d71
AK		 1427#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1428#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1429#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1430#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1431#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1432#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1433#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1434#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1435#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1436#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
11afc1b1
PW		 1437#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1438#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1439#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1440#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1441#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1442#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1443#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1444#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1445#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1446#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1447#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1448#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1449#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1450
1451#define IXGBE_MAX_FTQF_FILTERS 128
1452#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1453#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1454#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1455#define IXGBE_FTQF_PROTOCOL_SCTP 2
1456#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1457#define IXGBE_FTQF_PRIORITY_SHIFT 2
1458#define IXGBE_FTQF_POOL_MASK 0x0000003F
1459#define IXGBE_FTQF_POOL_SHIFT 8
1460#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1461#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
83dfde40
ET		 1462#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1463#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1464#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1465#define IXGBE_FTQF_DEST_PORT_MASK 0x17
1466#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
11afc1b1
PW		 1467#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1468#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
9a799d71
AK		 1469
1470/* Interrupt clear mask */
1471#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1472
1473/* Interrupt Vector Allocation Registers */
1474#define IXGBE_IVAR_REG_NUM 25
e80e887a 1475#define IXGBE_IVAR_REG_NUM_82599 64
9a799d71
AK		 1476#define IXGBE_IVAR_TXRX_ENTRY 96
1477#define IXGBE_IVAR_RX_ENTRY 64
1478#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1479#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1480#define IXGBE_IVAR_TX_ENTRY 32
1481
1482#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1483#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1484
1485#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1486
1487#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1488
11afc1b1
PW		 1489/* ETYPE Queue Filter/Select Bit Masks */
1490#define IXGBE_MAX_ETQF_FILTERS 8
bff66176 1491#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
11afc1b1
PW		 1492#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1493#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1494#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1495#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
81faddef 1496#define IXGBE_ETQF_POOL_SHIFT 20
11afc1b1
PW		 1497
1498#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1499#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1500#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1501#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1502
1503/*
1504 * ETQF filter list: one static filter per filter consumer. This is
1505 * to avoid filter collisions later. Add new filters
1506 * here!!
1507 *
1508 * Current filters:
1509 * EAPOL 802.1x (0x888e): Filter 0
83dfde40 1510 * FCoE (0x8906): Filter 2
11afc1b1 1511 * 1588 (0x88f7): Filter 3
83dfde40 1512 * FIP (0x8914): Filter 4
11afc1b1
PW		 1513 */
1514#define IXGBE_ETQF_FILTER_EAPOL 0
bff66176 1515#define IXGBE_ETQF_FILTER_FCOE 2
11afc1b1 1516#define IXGBE_ETQF_FILTER_1588 3
af06393b 1517#define IXGBE_ETQF_FILTER_FIP 4
9a799d71
AK		 1518/* VLAN Control Bit Masks */
1519#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1520#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1521#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1522#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1523#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1524
11afc1b1
PW		 1525/* VLAN pool filtering masks */
1526#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1527#define IXGBE_VLVF_ENTRIES 64
7f870475 1528#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
c44ade9e 1529
7f01648a
GR		 1530/* Per VF Port VLAN insertion rules */
1531#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1532#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1533
9a799d71
AK		 1534#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1535
1536/* STATUS Bit Masks */
11afc1b1
PW		 1537#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1538#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1539#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
9a799d71
AK		 1540
1541#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1542#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1543
1544/* ESDP Bit Masks */
50ac58ba
PWJ		 1545#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1546#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1547#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1548#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
11afc1b1
PW		 1549#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1550#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1551#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
681ae1ad 1552#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
8f58332b 1553#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
9a799d71 1554#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
11afc1b1 1555#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
681ae1ad 1556#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */
8f58332b 1557#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
9a799d71
AK		 1558
1559/* LEDCTL Bit Masks */
1560#define IXGBE_LED_IVRT_BASE 0x00000040
1561#define IXGBE_LED_BLINK_BASE 0x00000080
1562#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1563#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
795be954 1564#define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
9a799d71
AK		 1565#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1566#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1567#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1568
1569/* LED modes */
1570#define IXGBE_LED_LINK_UP 0x0
1571#define IXGBE_LED_LINK_10G 0x1
1572#define IXGBE_LED_MAC 0x2
1573#define IXGBE_LED_FILTER 0x3
1574#define IXGBE_LED_LINK_ACTIVE 0x4
1575#define IXGBE_LED_LINK_1G 0x5
1576#define IXGBE_LED_ON 0xE
1577#define IXGBE_LED_OFF 0xF
1578
1579/* AUTOC Bit Masks */
3201d313 1580#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
9a799d71
AK		 1581#define IXGBE_AUTOC_KX4_SUPP 0x80000000
1582#define IXGBE_AUTOC_KX_SUPP 0x40000000
1583#define IXGBE_AUTOC_PAUSE 0x30000000
539e5f02
PWJ		 1584#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1585#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
9a799d71
AK		 1586#define IXGBE_AUTOC_RF 0x08000000
1587#define IXGBE_AUTOC_PD_TMR 0x06000000
1588#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1589#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1590#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
11afc1b1
PW		 1591#define IXGBE_AUTOC_FECA 0x00040000
1592#define IXGBE_AUTOC_FECR 0x00020000
1593#define IXGBE_AUTOC_KR_SUPP 0x00010000
9a799d71
AK		 1594#define IXGBE_AUTOC_AN_RESTART 0x00001000
1595#define IXGBE_AUTOC_FLU 0x00000001
1596#define IXGBE_AUTOC_LMS_SHIFT 13
11afc1b1
PW		 1597#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1598#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1599#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1600#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1601#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
c44ade9e
JB		 1602#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1603#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1604#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1605#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1606#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1607#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1608#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1609
11afc1b1
PW		 1610#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1611#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1612#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1613#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
9a799d71
AK		 1614#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1615#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1616#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1617#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1618#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
11afc1b1
PW		 1619#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1620#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1621
1622#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1623#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1624#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1625#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1626#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1627#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
f4f1040a 1628#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
46d5cedd 1629#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
9a799d71 1630
83dfde40
ET		 1631#define IXGBE_MACC_FLU 0x00000001
1632#define IXGBE_MACC_FSV_10G 0x00030000
1633#define IXGBE_MACC_FS 0x00040000
1634#define IXGBE_MAC_RX2TX_LPBK 0x00000002
1635
c97506ab
DS		 1636/* Veto Bit definiton */
1637#define IXGBE_MMNGC_MNG_VETO 0x00000001
1638
9a799d71
AK		 1639/* LINKS Bit Masks */
1640#define IXGBE_LINKS_KX_AN_COMP 0x80000000
1641#define IXGBE_LINKS_UP 0x40000000
1642#define IXGBE_LINKS_SPEED 0x20000000
1643#define IXGBE_LINKS_MODE 0x18000000
1644#define IXGBE_LINKS_RX_MODE 0x06000000
1645#define IXGBE_LINKS_TX_MODE 0x01800000
1646#define IXGBE_LINKS_XGXS_EN 0x00400000
11afc1b1 1647#define IXGBE_LINKS_SGMII_EN 0x02000000
9a799d71
AK		 1648#define IXGBE_LINKS_PCS_1G_EN 0x00200000
1649#define IXGBE_LINKS_1G_AN_EN 0x00100000
1650#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1651#define IXGBE_LINKS_1G_SYNC 0x00040000
1652#define IXGBE_LINKS_10G_ALIGN 0x00020000
1653#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1654#define IXGBE_LINKS_TL_FAULT 0x00001000
1655#define IXGBE_LINKS_SIGNAL 0x00000F00
1656
9a75a1ac 1657#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
11afc1b1
PW		 1658#define IXGBE_LINKS_SPEED_82599 0x30000000
1659#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1660#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1661#define IXGBE_LINKS_SPEED_100_82599 0x10000000
cf8280ee 1662#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
9a799d71
AK		 1663#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1664
539e5f02
PWJ		 1665#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1666
0ecc061d
PWJ		 1667/* PCS1GLSTA Bit Masks */
1668#define IXGBE_PCS1GLSTA_LINK_OK 1
1669#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1670#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1671#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1672#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1673#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1674#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1675
1676#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1677#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1678
1679/* PCS1GLCTL Bit Masks */
1680#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1681#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1682#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1683#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1684#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1685#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1686
539e5f02
PWJ		 1687/* ANLP1 Bit Masks */
1688#define IXGBE_ANLP1_PAUSE 0x0C00
1689#define IXGBE_ANLP1_SYM_PAUSE 0x0400
1690#define IXGBE_ANLP1_ASM_PAUSE 0x0800
a7f5a5fc
DS		 1691#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1692
9a799d71
AK		 1693/* SW Semaphore Register bitmasks */
1694#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1695#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1696#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
21ce849b 1697#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
9a799d71 1698
21ce849b 1699/* SW_FW_SYNC/GSSR definitions */
9a799d71
AK		 1700#define IXGBE_GSSR_EEP_SM 0x0001
1701#define IXGBE_GSSR_PHY0_SM 0x0002
1702#define IXGBE_GSSR_PHY1_SM 0x0004
1703#define IXGBE_GSSR_MAC_CSR_SM 0x0008
1704#define IXGBE_GSSR_FLASH_SM 0x0010
83dfde40
ET		 1705#define IXGBE_GSSR_SW_MNG_SM 0x0400
1706
1707/* FW Status register bitmask */
1708#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
9a799d71
AK		 1709
1710/* EEC Register */
1711#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1712#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1713#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1714#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1715#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1716#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1717#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1718#define IXGBE_EEC_FWE_SHIFT 4
1719#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1720#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1721#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1722#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
21ce849b 1723#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
fe15e8e1 1724#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
21ce849b 1725#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
9a799d71
AK		 1726/* EEPROM Addressing bits based on type (0-small, 1-large) */
1727#define IXGBE_EEC_ADDR_SIZE 0x00000400
1728#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
83dfde40 1729#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
9a799d71
AK		 1730
1731#define IXGBE_EEC_SIZE_SHIFT 11
1732#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1733#define IXGBE_EEPROM_OPCODE_BITS 8
1734
289700db
DS		 1735/* Part Number String Length */
1736#define IXGBE_PBANUM_LENGTH 11
1737
9a799d71 1738/* Checksum and EEPROM pointers */
289700db 1739#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
9a799d71
AK		 1740#define IXGBE_EEPROM_CHECKSUM 0x3F
1741#define IXGBE_EEPROM_SUM 0xBABA
1742#define IXGBE_PCIE_ANALOG_PTR 0x03
1743#define IXGBE_ATLAS0_CONFIG_PTR 0x04
fe15e8e1 1744#define IXGBE_PHY_PTR 0x04
9a799d71 1745#define IXGBE_ATLAS1_CONFIG_PTR 0x05
fe15e8e1 1746#define IXGBE_OPTION_ROM_PTR 0x05
9a799d71
AK		 1747#define IXGBE_PCIE_GENERAL_PTR 0x06
1748#define IXGBE_PCIE_CONFIG0_PTR 0x07
1749#define IXGBE_PCIE_CONFIG1_PTR 0x08
1750#define IXGBE_CORE0_PTR 0x09
1751#define IXGBE_CORE1_PTR 0x0A
1752#define IXGBE_MAC0_PTR 0x0B
1753#define IXGBE_MAC1_PTR 0x0C
1754#define IXGBE_CSR0_CONFIG_PTR 0x0D
1755#define IXGBE_CSR1_CONFIG_PTR 0x0E
1756#define IXGBE_FW_PTR 0x0F
1757#define IXGBE_PBANUM0_PTR 0x15
1758#define IXGBE_PBANUM1_PTR 0x16
83dfde40 1759#define IXGBE_FREE_SPACE_PTR 0X3E
e1ea9158
DS		 1760
1761/* External Thermal Sensor Config */
1762#define IXGBE_ETS_CFG 0x26
1763#define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0
1764#define IXGBE_ETS_LTHRES_DELTA_SHIFT 6
1765#define IXGBE_ETS_TYPE_MASK 0x0038
1766#define IXGBE_ETS_TYPE_SHIFT 3
1767#define IXGBE_ETS_TYPE_EMC 0x000
1768#define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000
1769#define IXGBE_ETS_NUM_SENSORS_MASK 0x0007
1770#define IXGBE_ETS_DATA_LOC_MASK 0x3C00
1771#define IXGBE_ETS_DATA_LOC_SHIFT 10
1772#define IXGBE_ETS_DATA_INDEX_MASK 0x0300
1773#define IXGBE_ETS_DATA_INDEX_SHIFT 8
1774#define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF
1775
0365e6e4 1776#define IXGBE_SAN_MAC_ADDR_PTR 0x28
83dfde40
ET		 1777#define IXGBE_DEVICE_CAPS 0x2C
1778#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
11afc1b1 1779#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
71161302 1780#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
eb7f139c 1781#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
71161302 1782#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
eb7f139c
PWJ		 1783
1784/* MSI-X capability fields masks */
1785#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
9a799d71 1786
c44ade9e
JB		 1787/* Legacy EEPROM word offsets */
1788#define IXGBE_ISCSI_BOOT_CAPS 0x0033
1789#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1790#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1791
9a799d71
AK		 1792/* EEPROM Commands - SPI */
1793#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1794#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1795#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1796#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1797#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1798#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
c44ade9e 1799/* EEPROM reset Write Enable latch */
9a799d71
AK		 1800#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1801#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1802#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1803#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1804#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1805#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1806
1807/* EEPROM Read Register */
21ce849b
MC		 1808#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1809#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1810#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1811#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1812#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1813#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
9a799d71 1814
68c7005d
ET		 1815#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1816#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
1817#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
1818
f68bfdb1
JK		 1819#define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */
1820#define IXGBE_EEPROM_CCD_BIT 2 /* EEPROM Core Clock Disable bit */
1821
9a799d71
AK		 1822#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1823#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1824#endif
1825
21ce849b
MC		 1826#ifndef IXGBE_EERD_EEWR_ATTEMPTS
1827/* Number of 5 microseconds we wait for EERD read and
1828 * EERW write to complete */
1829#define IXGBE_EERD_EEWR_ATTEMPTS 100000
1830#endif
1831
1832#ifndef IXGBE_FLUDONE_ATTEMPTS
1833/* # attempts we wait for flush update to complete */
1834#define IXGBE_FLUDONE_ATTEMPTS 20000
9a799d71
AK		 1835#endif
1836
c9130180
ET		 1837#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
1838#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
1839#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1840#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1841
0365e6e4
PW		 1842#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1843#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
04193058 1844#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
eacd73f7 1845#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
0fa6d832
ET		 1846#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
1847#define IXGBE_FW_LESM_STATE_1 0x1
1848#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
794caeb2 1849#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
83dfde40
ET		 1850#define IXGBE_FW_PATCH_VERSION_4 0x7
1851#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
1852#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
1853#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
1854#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
1855#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
383ff34b
YZ		 1856#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1857#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1858#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1859#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1860#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1861#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1862#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1863#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1864
c23f5b6b
ET		 1865#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */
1866#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */
1867#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */
1868
9a799d71 1869/* PCI Bus Info */
a4297dc2
ET		 1870#define IXGBE_PCI_DEVICE_STATUS 0xAA
1871#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
9a799d71 1872#define IXGBE_PCI_LINK_STATUS 0xB2
202ff1ec 1873#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
9a799d71
AK		 1874#define IXGBE_PCI_LINK_WIDTH 0x3F0
1875#define IXGBE_PCI_LINK_WIDTH_1 0x10
1876#define IXGBE_PCI_LINK_WIDTH_2 0x20
1877#define IXGBE_PCI_LINK_WIDTH_4 0x40
1878#define IXGBE_PCI_LINK_WIDTH_8 0x80
1879#define IXGBE_PCI_LINK_SPEED 0xF
1880#define IXGBE_PCI_LINK_SPEED_2500 0x1
1881#define IXGBE_PCI_LINK_SPEED_5000 0x2
e8710a5f 1882#define IXGBE_PCI_LINK_SPEED_8000 0x3
11afc1b1
PW		 1883#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1884#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
202ff1ec 1885#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
9a799d71 1886
1f86c983
DS		 1887#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
1888#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
1889#define IXGBE_PCIDEVCTRL2_50_100us 0x1
1890#define IXGBE_PCIDEVCTRL2_1_2ms 0x2
1891#define IXGBE_PCIDEVCTRL2_16_32ms 0x5
1892#define IXGBE_PCIDEVCTRL2_65_130ms 0x6
1893#define IXGBE_PCIDEVCTRL2_260_520ms 0x9
1894#define IXGBE_PCIDEVCTRL2_1_2s 0xa
1895#define IXGBE_PCIDEVCTRL2_4_8s 0xd
1896#define IXGBE_PCIDEVCTRL2_17_34s 0xe
1897
9a799d71 1898/* Number of 100 microseconds we wait for PCI Express master disable */
1f86c983 1899#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
9a799d71 1900
9a799d71
AK		 1901/* RAH */
1902#define IXGBE_RAH_VIND_MASK 0x003C0000
1903#define IXGBE_RAH_VIND_SHIFT 18
1904#define IXGBE_RAH_AV 0x80000000
c44ade9e 1905#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
9a799d71 1906
9a799d71
AK		 1907/* Header split receive */
1908#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1909#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1910#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
6dcc28b9 1911#define IXGBE_RFCTL_RSC_DIS 0x00000020
9a799d71
AK		 1912#define IXGBE_RFCTL_NFSW_DIS 0x00000040
1913#define IXGBE_RFCTL_NFSR_DIS 0x00000080
1914#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1915#define IXGBE_RFCTL_NFS_VER_SHIFT 8
1916#define IXGBE_RFCTL_NFS_VER_2 0
1917#define IXGBE_RFCTL_NFS_VER_3 1
1918#define IXGBE_RFCTL_NFS_VER_4 2
1919#define IXGBE_RFCTL_IPV6_DIS 0x00000400
1920#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1921#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1922#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1923#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1924
1925/* Transmit Config masks */
1926#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1927#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
83dfde40 1928#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
9a799d71
AK		 1929/* Enable short packet padding to 64 bytes */
1930#define IXGBE_TX_PAD_ENABLE 0x00000400
1931#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1932/* This allows for 16K packets + 4k for vlan */
1933#define IXGBE_MAX_FRAME_SZ 0x40040000
1934
1935#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
c44ade9e 1936#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
9a799d71
AK		 1937
1938/* Receive Config masks */
1939#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1940#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1941#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
ff9d1a5a 1942#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
e9f98072
GR		 1943#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
1944#define IXGBE_RXDCTL_RLPML_EN 0x00008000
83dfde40 1945#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
9a799d71 1946
681ae1ad
JK		 1947#define IXGBE_TSAUXC_EN_CLK 0x00000004
1948#define IXGBE_TSAUXC_SYNCLK 0x00000008
1949#define IXGBE_TSAUXC_SDP0_INT 0x00000040
1950
3a6a4eda
JK		 1951#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1952#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
1953
1954#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1955#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1956#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
1957#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
1958#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
1959#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
1960#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */
1961
1962#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
1963#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
1964#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
1965#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
1966#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
1967#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
1968
1969#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
1970#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
1971#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
1972#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
1973#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
1974#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
1975#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
1976#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
1977#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
1978#define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00
1979#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
1980
9a799d71
AK		 1981#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1982#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1983#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1984#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1985#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1986#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
c44ade9e 1987/* Receive Priority Flow Control Enable */
9a799d71
AK		 1988#define IXGBE_FCTRL_RPFCE 0x00004000
1989#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
11afc1b1
PW		 1990#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1991#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1992#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1993#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
041441d0 1994#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */
9a799d71 1995
45a5f720
JF		 1996#define IXGBE_MFLCN_RPFCE_SHIFT 4
1997
9a799d71
AK		 1998/* Multiple Receive Queue Control */
1999#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
11afc1b1
PW		 2000#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
2001#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
2002#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
2003#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
2004#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
2005#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
2006#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
2007#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
2008#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
2009#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
9a799d71
AK		 2010#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2011#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2012#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2013#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2014#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2015#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2016#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2017#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
2018#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
2019#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
0f9b232b 2020#define IXGBE_MRQC_MULTIPLE_RSS 0x00002000
11afc1b1
PW		 2021#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2022
cb6d0f5e
JK		 2023#define IXGBE_FWSM_TS_ENABLED 0x1
2024
11afc1b1 2025/* Queue Drop Enable */
87397379 2026#define IXGBE_QDE_ENABLE 0x00000001
9a75a1ac 2027#define IXGBE_QDE_HIDE_VLAN 0x00000002
87397379
AD		 2028#define IXGBE_QDE_IDX_MASK 0x00007F00
2029#define IXGBE_QDE_IDX_SHIFT 8
2030#define IXGBE_QDE_WRITE 0x00010000
9a799d71
AK		 2031
2032#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
2033#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
2034#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
2035#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
2036#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
2037#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
2038#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
2039#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
2040#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
2041
11afc1b1
PW		 2042#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
2043#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2044#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2045#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
2046#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
2047/* Multiple Transmit Queue Command Register */
2048#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
2049#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
2050#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
d988eadb
DS		 2051#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
2052#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
11afc1b1 2053#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
8b1c0b24 2054#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
11afc1b1 2055
9a799d71
AK		 2056/* Receive Descriptor bit definitions */
2057#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
2058#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
11afc1b1 2059#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
9a799d71 2060#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
11afc1b1
PW		 2061#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2062#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
c44ade9e 2063#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
9a799d71
AK		 2064#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
2065#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
2066#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2067#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
2068#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
2069#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
2070#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
11afc1b1
PW		 2071#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
2072#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
2073#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
2074#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
9a799d71
AK		 2075#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
2076#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
2077#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
2078#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
2079#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
2080#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
2081#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
2082#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
11afc1b1
PW		 2083#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
2084#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
bff66176
YZ		 2085#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
2086#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
bfde493e
PWJ		 2087#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
2088#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
2089#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
c44ade9e 2090#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
9a799d71
AK		 2091#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
2092#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
2093#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
2094#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
2095#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
2096#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
2097#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
2098#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
2099#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2100#define IXGBE_RXD_PRI_SHIFT 13
2101#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
2102#define IXGBE_RXD_CFI_SHIFT 12
2103
11afc1b1
PW		 2104#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
2105#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
2106#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
2107#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
2108#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
bff66176
YZ		 2109#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
2110#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
2111#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2112#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
2113#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2114#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
3a6a4eda 2115#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */
11afc1b1
PW		 2116
2117/* PSRTYPE bit definitions */
2118#define IXGBE_PSRTYPE_TCPHDR 0x00000010
2119#define IXGBE_PSRTYPE_UDPHDR 0x00000020
2120#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2121#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
dfa12f05 2122#define IXGBE_PSRTYPE_L2HDR 0x00001000
c44ade9e 2123
9a799d71 2124/* SRRCTL bit definitions */
c44ade9e 2125#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
11afc1b1
PW		 2126#define IXGBE_SRRCTL_RDMTS_SHIFT 22
2127#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2128#define IXGBE_SRRCTL_DROP_EN 0x10000000
c44ade9e
JB		 2129#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2130#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2131#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
9a799d71
AK		 2132#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2133#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2134#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2135#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
c44ade9e 2136#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
9a799d71
AK		 2137
2138#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2139#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2140
2141#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2142#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
11afc1b1 2143#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
9a799d71 2144#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
83dfde40
ET		 2145#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2146#define IXGBE_RXDADV_RSCCNT_SHIFT 17
9a799d71
AK		 2147#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2148#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2149#define IXGBE_RXDADV_SPH 0x8000
2150
2151/* RSS Hash results */
2152#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2153#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2154#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2155#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2156#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2157#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2158#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2159#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2160#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2161#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2162
2163/* RSS Packet Types as indicated in the receive descriptor. */
2164#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2165#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
2166#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
2167#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
2168#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
2169#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
2170#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
2171#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
2172#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
11afc1b1
PW		 2173#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
2174#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
2175#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
2176#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
2177#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
2178#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2179
2180/* Security Processing bit Indication */
2181#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
2182#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
2183#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
2184#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
2185#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
2186
9a799d71 2187/* Masks to determine if packets should be dropped due to frame errors */
c44ade9e 2188#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
e7cf745b
JK		 2189 IXGBE_RXD_ERR_CE | \
2190 IXGBE_RXD_ERR_LE | \
2191 IXGBE_RXD_ERR_PE | \
2192 IXGBE_RXD_ERR_OSE | \
2193 IXGBE_RXD_ERR_USE)
c44ade9e
JB		 2194
2195#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
e7cf745b
JK		 2196 IXGBE_RXDADV_ERR_CE | \
2197 IXGBE_RXDADV_ERR_LE | \
2198 IXGBE_RXDADV_ERR_PE | \
2199 IXGBE_RXDADV_ERR_OSE | \
2200 IXGBE_RXDADV_ERR_USE)
9a799d71
AK		 2201
2202/* Multicast bit mask */
2203#define IXGBE_MCSTCTRL_MFE 0x4
2204
2205/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2206#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2207#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2208#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2209
2210/* Vlan-specific macros */
2211#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2212#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
2213#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2214#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2215
7f870475
GR		 2216/* SR-IOV specific macros */
2217#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
795be954
AD		 2218#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
2219#define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600))
2220#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
dbf231af 2221/* Translated register #defines */
07923c17
ET		 2222#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2223#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
dbf231af
AD		 2224#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2225#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2226
2227#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2228 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2229#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2230 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
7f870475 2231
07923c17
ET		 2232#define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
2233 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2234#define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
2235 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2236
bfde493e 2237enum ixgbe_fdir_pballoc_type {
c04f6ca8
AD		 2238 IXGBE_FDIR_PBALLOC_NONE = 0,
2239 IXGBE_FDIR_PBALLOC_64K = 1,
2240 IXGBE_FDIR_PBALLOC_128K = 2,
2241 IXGBE_FDIR_PBALLOC_256K = 3,
bfde493e
PWJ		 2242};
2243#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2244
2245/* Flow Director register values */
2246#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2247#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2248#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2249#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2250#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2251#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2252#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2253#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2254#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2255#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2256#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2257#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2258#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2259
2260#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2261#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2262#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2263#define IXGBE_FDIRM_VLANID 0x00000001
2264#define IXGBE_FDIRM_VLANP 0x00000002
2265#define IXGBE_FDIRM_POOL 0x00000004
45b9f509
AD		 2266#define IXGBE_FDIRM_L4P 0x00000008
2267#define IXGBE_FDIRM_FLEX 0x00000010
2268#define IXGBE_FDIRM_DIPv6 0x00000020
bfde493e
PWJ		 2269
2270#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2271#define IXGBE_FDIRFREE_FREE_SHIFT 0
2272#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2273#define IXGBE_FDIRFREE_COLL_SHIFT 16
2274#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2275#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2276#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2277#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2278#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2279#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2280#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2281#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2282#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2283#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2284#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2285#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2286#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2287#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2288#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2289#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2290
2291#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2292#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2293#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2294#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
c04f6ca8 2295#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
bfde493e
PWJ		 2296#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2297#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2298#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2299#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2300#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2301#define IXGBE_FDIRCMD_IPV6 0x00000080
2302#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2303#define IXGBE_FDIRCMD_DROP 0x00000200
2304#define IXGBE_FDIRCMD_INT 0x00000400
2305#define IXGBE_FDIRCMD_LAST 0x00000800
2306#define IXGBE_FDIRCMD_COLLISION 0x00001000
2307#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
905e4a41 2308#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
bfde493e
PWJ		 2309#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2310#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2311#define IXGBE_FDIR_INIT_DONE_POLL 10
2312#define IXGBE_FDIRCMD_CMD_POLL 10
2313
c04f6ca8
AD		 2314#define IXGBE_FDIR_DROP_QUEUE 127
2315
9612de92 2316/* Manageablility Host Interface defines */
b48e4aa3
DS		 2317#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
2318#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2319#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
2320#define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */
2321#define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */
2322#define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */
9612de92
ET		 2323
2324/* CEM Support */
2325#define FW_CEM_HDR_LEN 0x4
2326#define FW_CEM_CMD_DRIVER_INFO 0xDD
2327#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
a38a104d
DS		 2328#define FW_CEM_CMD_RESERVED 0x0
2329#define FW_CEM_UNUSED_VER 0x0
9612de92
ET		 2330#define FW_CEM_MAX_RETRIES 3
2331#define FW_CEM_RESP_STATUS_SUCCESS 0x1
2332
2333/* Host Interface Command Structures */
2334struct ixgbe_hic_hdr {
2335 u8 cmd;
2336 u8 buf_len;
2337 union {
2338 u8 cmd_resv;
2339 u8 ret_status;
2340 } cmd_or_resp;
2341 u8 checksum;
2342};
2343
2344struct ixgbe_hic_drv_info {
2345 struct ixgbe_hic_hdr hdr;
2346 u8 port_num;
2347 u8 ver_sub;
2348 u8 ver_build;
2349 u8 ver_min;
2350 u8 ver_maj;
2351 u8 pad; /* end spacing to ensure length is mult. of dword */
2352 u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2353};
2354
9a799d71
AK		 2355/* Transmit Descriptor - Advanced */
2356union ixgbe_adv_tx_desc {
2357 struct {
c44ade9e 2358 __le64 buffer_addr; /* Address of descriptor's data buf */
8327d000
AV		 2359 __le32 cmd_type_len;
2360 __le32 olinfo_status;
9a799d71
AK		 2361 } read;
2362 struct {
8327d000
AV		 2363 __le64 rsvd; /* Reserved */
2364 __le32 nxtseq_seed;
2365 __le32 status;
9a799d71
AK		 2366 } wb;
2367};
2368
9a799d71
AK		 2369/* Receive Descriptor - Advanced */
2370union ixgbe_adv_rx_desc {
2371 struct {
8327d000
AV		 2372 __le64 pkt_addr; /* Packet buffer address */
2373 __le64 hdr_addr; /* Header buffer address */
9a799d71
AK		 2374 } read;
2375 struct {
2376 struct {
7c6e0a43
JB		 2377 union {
2378 __le32 data;
2379 struct {
c44ade9e
JB		 2380 __le16 pkt_info; /* RSS, Pkt type */
2381 __le16 hdr_info; /* Splithdr, hdrlen */
7c6e0a43 2382 } hs_rss;
9a799d71
AK		 2383 } lo_dword;
2384 union {
8327d000 2385 __le32 rss; /* RSS Hash */
9a799d71 2386 struct {
8327d000 2387 __le16 ip_id; /* IP id */
9da09bb1 2388 __le16 csum; /* Packet Checksum */
9a799d71
AK		 2389 } csum_ip;
2390 } hi_dword;
2391 } lower;
2392 struct {
8327d000
AV		 2393 __le32 status_error; /* ext status/error */
2394 __le16 length; /* Packet length */
2395 __le16 vlan; /* VLAN tag */
9a799d71
AK		 2396 } upper;
2397 } wb; /* writeback */
2398};
2399
2400/* Context descriptors */
2401struct ixgbe_adv_tx_context_desc {
8327d000
AV		 2402 __le32 vlan_macip_lens;
2403 __le32 seqnum_seed;
2404 __le32 type_tucmd_mlhl;
2405 __le32 mss_l4len_idx;
9a799d71
AK		 2406};
2407
2408/* Adv Transmit Descriptor Config Masks */
c44ade9e 2409#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
11afc1b1 2410#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
3a6a4eda 2411#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */
11afc1b1
PW		 2412#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2413#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
9a799d71
AK		 2414#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
2415#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
2416#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
2417#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
2418#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
9a799d71 2419#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
c44ade9e 2420#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
9a799d71
AK		 2421#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2422#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
2423#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
2424#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
c44ade9e 2425#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
9a799d71
AK		 2426#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
2427#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
c44ade9e 2428#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
9a799d71
AK		 2429#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
2430#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
e7cf745b 2431 IXGBE_ADVTXD_POPTS_SHIFT)
9a799d71 2432#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
e7cf745b 2433 IXGBE_ADVTXD_POPTS_SHIFT)
c44ade9e
JB		 2434#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
2435#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
2436#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2437#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2438#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
2439#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
2440#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
2441#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
2442#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
2443#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
2444#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
2445#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
2446#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
2447#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
11afc1b1
PW		 2448#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
2449#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2450#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
bff66176
YZ		 2451#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2452#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
2453#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
2454#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
2455#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
2456#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
2457#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
2458#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
2459#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
2460#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
c44ade9e
JB		 2461#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2462#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2463
2464/* Autonegotiation advertised speeds */
2465typedef u32 ixgbe_autoneg_advertised;
9a799d71 2466/* Link speed */
c44ade9e 2467typedef u32 ixgbe_link_speed;
9a75a1ac
DS		 2468#define IXGBE_LINK_SPEED_UNKNOWN 0
2469#define IXGBE_LINK_SPEED_100_FULL 0x0008
2470#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2471#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
2472#define IXGBE_LINK_SPEED_5GB_FULL 0x0800
2473#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
c44ade9e 2474#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
e7cf745b 2475 IXGBE_LINK_SPEED_10GB_FULL)
11afc1b1 2476#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
e7cf745b
JK		 2477 IXGBE_LINK_SPEED_1GB_FULL | \
2478 IXGBE_LINK_SPEED_10GB_FULL)
11afc1b1 2479
9da712d2
JF		 2480/* Flow Control Data Sheet defined values
2481 * Calculation and defines taken from 802.1bb Annex O
2482 */
2483
2484/* BitTimes (BT) conversion */
4f8a91ad 2485#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
9da712d2
JF		 2486#define IXGBE_B2BT(BT) (BT * 8)
2487
2488/* Calculate Delay to respond to PFC */
2489#define IXGBE_PFC_D 672
2490
2491/* Calculate Cable Delay */
2492#define IXGBE_CABLE_DC 5556 /* Delay Copper */
2493#define IXGBE_CABLE_DO 5000 /* Delay Optical */
2494
2495/* Calculate Interface Delay X540 */
2496#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */
2497#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */
2498#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */
2499
2500#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2501
2502/* Calculate Interface Delay 82598, 82599 */
2503#define IXGBE_PHY_D 12800
2504#define IXGBE_MAC_D 4096
2505#define IXGBE_XAUI_D (2 * 1024)
2506
2507#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2508
2509/* Calculate Delay incurred from higher layer */
2510#define IXGBE_HD 6144
2511
2512/* Calculate PCI Bus delay for low thresholds */
2513#define IXGBE_PCI_DELAY 10000
2514
2515/* Calculate X540 delay value in bit times */
4f8a91ad
JF		 2516#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2517 ((36 * \
2518 (IXGBE_B2BT(_max_frame_link) + \
2519 IXGBE_PFC_D + \
2520 (2 * IXGBE_CABLE_DC) + \
2521 (2 * IXGBE_ID_X540) + \
2522 IXGBE_HD) / 25 + 1) + \
2523 2 * IXGBE_B2BT(_max_frame_tc))
9da712d2
JF		 2524
2525/* Calculate 82599, 82598 delay value in bit times */
4f8a91ad
JF		 2526#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2527 ((36 * \
2528 (IXGBE_B2BT(_max_frame_link) + \
2529 IXGBE_PFC_D + \
2530 (2 * IXGBE_CABLE_DC) + \
2531 (2 * IXGBE_ID) + \
2532 IXGBE_HD) / 25 + 1) + \
2533 2 * IXGBE_B2BT(_max_frame_tc))
16b61beb 2534
9da712d2 2535/* Calculate low threshold delay values */
4f8a91ad
JF		 2536#define IXGBE_LOW_DV_X540(_max_frame_tc) \
2537 (2 * IXGBE_B2BT(_max_frame_tc) + \
2538 (36 * IXGBE_PCI_DELAY / 25) + 1)
2539#define IXGBE_LOW_DV(_max_frame_tc) \
2540 (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
16b61beb 2541
bfde493e 2542/* Software ATR hash keys */
905e4a41
AD		 2543#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2544#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
bfde493e 2545
905e4a41
AD		 2546/* Software ATR input stream values and masks */
2547#define IXGBE_ATR_HASH_MASK 0x7fff
bfde493e 2548#define IXGBE_ATR_L4TYPE_MASK 0x3
bfde493e
PWJ		 2549#define IXGBE_ATR_L4TYPE_UDP 0x1
2550#define IXGBE_ATR_L4TYPE_TCP 0x2
2551#define IXGBE_ATR_L4TYPE_SCTP 0x3
905e4a41
AD		 2552#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2553enum ixgbe_atr_flow_type {
2554 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2555 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2556 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2557 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2558 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2559 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2560 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2561 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2562};
bfde493e
PWJ		 2563
2564/* Flow Director ATR input struct. */
905e4a41
AD		 2565union ixgbe_atr_input {
2566 /*
2567 * Byte layout in order, all values with MSB first:
bfde493e 2568 *
905e4a41
AD		 2569 * vm_pool - 1 byte
2570 * flow_type - 1 byte
bfde493e
PWJ		 2571 * vlan_id - 2 bytes
2572 * src_ip - 16 bytes
2573 * dst_ip - 16 bytes
2574 * src_port - 2 bytes
2575 * dst_port - 2 bytes
2576 * flex_bytes - 2 bytes
c04f6ca8 2577 * bkt_hash - 2 bytes
bfde493e 2578 */
905e4a41
AD		 2579 struct {
2580 u8 vm_pool;
2581 u8 flow_type;
2582 __be16 vlan_id;
2583 __be32 dst_ip[4];
2584 __be32 src_ip[4];
2585 __be16 src_port;
2586 __be16 dst_port;
2587 __be16 flex_bytes;
c04f6ca8 2588 __be16 bkt_hash;
905e4a41
AD		 2589 } formatted;
2590 __be32 dword_stream[11];
bfde493e
PWJ		 2591};
2592
69830529
AD		 2593/* Flow Director compressed ATR hash input struct */
2594union ixgbe_atr_hash_dword {
2595 struct {
2596 u8 vm_pool;
2597 u8 flow_type;
2598 __be16 vlan_id;
2599 } formatted;
2600 __be32 ip;
2601 struct {
2602 __be16 src;
2603 __be16 dst;
2604 } port;
2605 __be16 flex_bytes;
2606 __be32 dword;
2607};
2608
9a799d71
AK		 2609enum ixgbe_eeprom_type {
2610 ixgbe_eeprom_uninitialized = 0,
2611 ixgbe_eeprom_spi,
fe15e8e1 2612 ixgbe_flash,
9a799d71
AK		 2613 ixgbe_eeprom_none /* No NVM support */
2614};
2615
2616enum ixgbe_mac_type {
2617 ixgbe_mac_unknown = 0,
2618 ixgbe_mac_82598EB,
11afc1b1 2619 ixgbe_mac_82599EB,
fe15e8e1 2620 ixgbe_mac_X540,
9a75a1ac
DS		 2621 ixgbe_mac_X550,
2622 ixgbe_mac_X550EM_x,
9a799d71
AK		 2623 ixgbe_num_macs
2624};
2625
2626enum ixgbe_phy_type {
2627 ixgbe_phy_unknown = 0,
21cc5b4f 2628 ixgbe_phy_none,
0befdb3e 2629 ixgbe_phy_tn,
fe15e8e1 2630 ixgbe_phy_aq,
11afc1b1 2631 ixgbe_phy_cu_unknown,
9a799d71 2632 ixgbe_phy_qt,
c44ade9e 2633 ixgbe_phy_xaui,
c4900be0 2634 ixgbe_phy_nl,
ea0a04df
DS		 2635 ixgbe_phy_sfp_passive_tyco,
2636 ixgbe_phy_sfp_passive_unknown,
2637 ixgbe_phy_sfp_active_unknown,
c44ade9e
JB		 2638 ixgbe_phy_sfp_avago,
2639 ixgbe_phy_sfp_ftl,
ea0a04df 2640 ixgbe_phy_sfp_ftl_active,
c44ade9e 2641 ixgbe_phy_sfp_unknown,
11afc1b1 2642 ixgbe_phy_sfp_intel,
8f58332b
DS		 2643 ixgbe_phy_qsfp_passive_unknown,
2644 ixgbe_phy_qsfp_active_unknown,
2645 ixgbe_phy_qsfp_intel,
2646 ixgbe_phy_qsfp_unknown,
fa466e91 2647 ixgbe_phy_sfp_unsupported,
c44ade9e
JB		 2648 ixgbe_phy_generic
2649};
2650
2651/*
2652 * SFP+ module type IDs:
2653 *
11afc1b1 2654 * ID Module Type
c44ade9e 2655 * =============
11afc1b1
PW		 2656 * 0 SFP_DA_CU
2657 * 1 SFP_SR
2658 * 2 SFP_LR
2659 * 3 SFP_DA_CU_CORE0 - 82599-specific
2660 * 4 SFP_DA_CU_CORE1 - 82599-specific
2661 * 5 SFP_SR/LR_CORE0 - 82599-specific
2662 * 6 SFP_SR/LR_CORE1 - 82599-specific
c44ade9e
JB		 2663 */
2664enum ixgbe_sfp_type {
2665 ixgbe_sfp_type_da_cu = 0,
2666 ixgbe_sfp_type_sr = 1,
2667 ixgbe_sfp_type_lr = 2,
11afc1b1
PW		 2668 ixgbe_sfp_type_da_cu_core0 = 3,
2669 ixgbe_sfp_type_da_cu_core1 = 4,
2670 ixgbe_sfp_type_srlr_core0 = 5,
2671 ixgbe_sfp_type_srlr_core1 = 6,
ea0a04df
DS		 2672 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2673 ixgbe_sfp_type_da_act_lmt_core1 = 8,
cb836a97
DS		 2674 ixgbe_sfp_type_1g_cu_core0 = 9,
2675 ixgbe_sfp_type_1g_cu_core1 = 10,
a49fda3e
JK		 2676 ixgbe_sfp_type_1g_sx_core0 = 11,
2677 ixgbe_sfp_type_1g_sx_core1 = 12,
345be204
DS		 2678 ixgbe_sfp_type_1g_lx_core0 = 13,
2679 ixgbe_sfp_type_1g_lx_core1 = 14,
c4900be0 2680 ixgbe_sfp_type_not_present = 0xFFFE,
c44ade9e 2681 ixgbe_sfp_type_unknown = 0xFFFF
9a799d71
AK		 2682};
2683
2684enum ixgbe_media_type {
2685 ixgbe_media_type_unknown = 0,
2686 ixgbe_media_type_fiber,
8f58332b 2687 ixgbe_media_type_fiber_qsfp,
4f6290cf 2688 ixgbe_media_type_fiber_lco,
9a799d71 2689 ixgbe_media_type_copper,
c44ade9e 2690 ixgbe_media_type_backplane,
6b1be199 2691 ixgbe_media_type_cx4,
c44ade9e 2692 ixgbe_media_type_virtual
9a799d71
AK		 2693};
2694
2695/* Flow Control Settings */
0ecc061d 2696enum ixgbe_fc_mode {
9a799d71
AK		 2697 ixgbe_fc_none = 0,
2698 ixgbe_fc_rx_pause,
2699 ixgbe_fc_tx_pause,
2700 ixgbe_fc_full,
2701 ixgbe_fc_default
2702};
2703
cd7e1f0b
DS		 2704/* Smart Speed Settings */
2705#define IXGBE_SMARTSPEED_MAX_RETRIES 3
2706enum ixgbe_smart_speed {
2707 ixgbe_smart_speed_auto = 0,
2708 ixgbe_smart_speed_on,
2709 ixgbe_smart_speed_off
2710};
2711
11afc1b1
PW		 2712/* PCI bus types */
2713enum ixgbe_bus_type {
2714 ixgbe_bus_type_unknown = 0,
2715 ixgbe_bus_type_pci,
2716 ixgbe_bus_type_pcix,
2717 ixgbe_bus_type_pci_express,
2718 ixgbe_bus_type_reserved
2719};
2720
2721/* PCI bus speeds */
2722enum ixgbe_bus_speed {
2723 ixgbe_bus_speed_unknown = 0,
26d6899b
ET		 2724 ixgbe_bus_speed_33 = 33,
2725 ixgbe_bus_speed_66 = 66,
2726 ixgbe_bus_speed_100 = 100,
2727 ixgbe_bus_speed_120 = 120,
2728 ixgbe_bus_speed_133 = 133,
2729 ixgbe_bus_speed_2500 = 2500,
2730 ixgbe_bus_speed_5000 = 5000,
e8710a5f 2731 ixgbe_bus_speed_8000 = 8000,
11afc1b1
PW		 2732 ixgbe_bus_speed_reserved
2733};
2734
2735/* PCI bus widths */
2736enum ixgbe_bus_width {
2737 ixgbe_bus_width_unknown = 0,
26d6899b
ET		 2738 ixgbe_bus_width_pcie_x1 = 1,
2739 ixgbe_bus_width_pcie_x2 = 2,
11afc1b1
PW		 2740 ixgbe_bus_width_pcie_x4 = 4,
2741 ixgbe_bus_width_pcie_x8 = 8,
26d6899b
ET		 2742 ixgbe_bus_width_32 = 32,
2743 ixgbe_bus_width_64 = 64,
11afc1b1
PW		 2744 ixgbe_bus_width_reserved
2745};
2746
9a799d71
AK		 2747struct ixgbe_addr_filter_info {
2748 u32 num_mc_addrs;
2749 u32 rar_used_count;
9a799d71 2750 u32 mta_in_use;
2c5645cf 2751 u32 overflow_promisc;
e433ea1f 2752 bool uc_set_promisc;
2c5645cf 2753 bool user_set_promisc;
9a799d71
AK		 2754};
2755
11afc1b1
PW		 2756/* Bus parameters */
2757struct ixgbe_bus_info {
2758 enum ixgbe_bus_speed speed;
2759 enum ixgbe_bus_width width;
2760 enum ixgbe_bus_type type;
2761
2762 u16 func;
2763 u16 lan_id;
2764};
2765
9a799d71
AK		 2766/* Flow control parameters */
2767struct ixgbe_fc_info {
9da712d2 2768 u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
e5776620 2769 u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */
9a799d71
AK		 2770 u16 pause_time; /* Flow Control Pause timer */
2771 bool send_xon; /* Flow control send XON */
2772 bool strict_ieee; /* Strict IEEE mode */
620fa036
MC		 2773 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2774 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
0ecc061d
PWJ		 2775 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2776 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
9a799d71
AK		 2777};
2778
2779/* Statistics counters collected by the MAC */
2780struct ixgbe_hw_stats {
2781 u64 crcerrs;
2782 u64 illerrc;
2783 u64 errbc;
2784 u64 mspdc;
2785 u64 mpctotal;
2786 u64 mpc[8];
2787 u64 mlfc;
2788 u64 mrfc;
2789 u64 rlec;
2790 u64 lxontxc;
2791 u64 lxonrxc;
2792 u64 lxofftxc;
2793 u64 lxoffrxc;
2794 u64 pxontxc[8];
2795 u64 pxonrxc[8];
2796 u64 pxofftxc[8];
2797 u64 pxoffrxc[8];
2798 u64 prc64;
2799 u64 prc127;
2800 u64 prc255;
2801 u64 prc511;
2802 u64 prc1023;
2803 u64 prc1522;
2804 u64 gprc;
2805 u64 bprc;
2806 u64 mprc;
2807 u64 gptc;
2808 u64 gorc;
2809 u64 gotc;
2810 u64 rnbc[8];
2811 u64 ruc;
2812 u64 rfc;
2813 u64 roc;
2814 u64 rjc;
2815 u64 mngprc;
2816 u64 mngpdc;
2817 u64 mngptc;
2818 u64 tor;
2819 u64 tpr;
2820 u64 tpt;
2821 u64 ptc64;
2822 u64 ptc127;
2823 u64 ptc255;
2824 u64 ptc511;
2825 u64 ptc1023;
2826 u64 ptc1522;
2827 u64 mptc;
2828 u64 bptc;
2829 u64 xec;
2830 u64 rqsmr[16];
2831 u64 tqsmr[8];
2832 u64 qprc[16];
2833 u64 qptc[16];
2834 u64 qbrc[16];
2835 u64 qbtc[16];
11afc1b1
PW		 2836 u64 qprdc[16];
2837 u64 pxon2offc[8];
2838 u64 fdirustat_add;
2839 u64 fdirustat_remove;
2840 u64 fdirfstat_fadd;
2841 u64 fdirfstat_fremove;
2842 u64 fdirmatch;
2843 u64 fdirmiss;
6d45522c
YZ		 2844 u64 fccrc;
2845 u64 fcoerpdc;
2846 u64 fcoeprc;
2847 u64 fcoeptc;
2848 u64 fcoedwrc;
2849 u64 fcoedwtc;
7b859ebc
AH		 2850 u64 fcoe_noddp;
2851 u64 fcoe_noddp_ext_buff;
58f6bcf9
ET		 2852 u64 b2ospc;
2853 u64 b2ogprc;
2854 u64 o2bgptc;
2855 u64 o2bspc;
9a799d71
AK		 2856};
2857
2858/* forward declaration */
2859struct ixgbe_hw;
2860
2c5645cf
CL		 2861/* iterator type for walking multicast address lists */
2862typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
e7cf745b 2863 u32 *vmdq);
2c5645cf 2864
c44ade9e
JB		 2865/* Function pointer table */
2866struct ixgbe_eeprom_operations {
2867 s32 (*init_params)(struct ixgbe_hw *);
2868 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
68c7005d 2869 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
c44ade9e 2870 s32 (*write)(struct ixgbe_hw *, u16, u16);
68c7005d 2871 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
c44ade9e
JB		 2872 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2873 s32 (*update_checksum)(struct ixgbe_hw *);
a391f1d5 2874 u16 (*calc_checksum)(struct ixgbe_hw *);
c44ade9e
JB		 2875};
2876
9a799d71 2877struct ixgbe_mac_operations {
c44ade9e
JB		 2878 s32 (*init_hw)(struct ixgbe_hw *);
2879 s32 (*reset_hw)(struct ixgbe_hw *);
2880 s32 (*start_hw)(struct ixgbe_hw *);
2881 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
9a799d71 2882 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
c44ade9e 2883 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
0365e6e4 2884 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
04193058 2885 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
383ff34b 2886 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
c44ade9e
JB		 2887 s32 (*stop_adapter)(struct ixgbe_hw *);
2888 s32 (*get_bus_info)(struct ixgbe_hw *);
11afc1b1 2889 void (*set_lan_id)(struct ixgbe_hw *);
c44ade9e
JB		 2890 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2891 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
11afc1b1 2892 s32 (*setup_sfp)(struct ixgbe_hw *);
d2f5e7f3
AS		 2893 s32 (*disable_rx_buff)(struct ixgbe_hw *);
2894 s32 (*enable_rx_buff)(struct ixgbe_hw *);
11afc1b1 2895 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
5e655105
DS		 2896 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2897 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
429d6a3b
DS		 2898 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
2899 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
c44ade9e
JB		 2900
2901 /* Link */
61fac744
PW		 2902 void (*disable_tx_laser)(struct ixgbe_hw *);
2903 void (*enable_tx_laser)(struct ixgbe_hw *);
1097cd17 2904 void (*flap_tx_laser)(struct ixgbe_hw *);
f4f1040a 2905 void (*stop_link_on_d3)(struct ixgbe_hw *);
fd0326f2 2906 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
c44ade9e
JB		 2907 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2908 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
e7cf745b 2909 bool *);
c44ade9e 2910
80605c65
JF		 2911 /* Packet Buffer Manipulation */
2912 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
2913
c44ade9e
JB		 2914 /* LED */
2915 s32 (*led_on)(struct ixgbe_hw *, u32);
2916 s32 (*led_off)(struct ixgbe_hw *, u32);
2917 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2918 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2919
2920 /* RAR, Multicast, VLAN */
2921 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2922 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2923 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
7fa7c9dc 2924 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
c44ade9e
JB		 2925 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2926 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2853eb89 2927 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
c44ade9e
JB		 2928 s32 (*enable_mc)(struct ixgbe_hw *);
2929 s32 (*disable_mc)(struct ixgbe_hw *);
2930 s32 (*clear_vfta)(struct ixgbe_hw *);
2931 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2932 s32 (*init_uta_tables)(struct ixgbe_hw *);
a985b6c3
GR		 2933 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2934 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
c44ade9e
JB		 2935
2936 /* Flow Control */
041441d0 2937 s32 (*fc_enable)(struct ixgbe_hw *);
9612de92
ET		 2938
2939 /* Manageability interface */
2940 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
e1ea9158
DS		 2941 s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
2942 s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
9a799d71
AK		 2943};
2944
2945struct ixgbe_phy_operations {
c44ade9e
JB		 2946 s32 (*identify)(struct ixgbe_hw *);
2947 s32 (*identify_sfp)(struct ixgbe_hw *);
04f165ef 2948 s32 (*init)(struct ixgbe_hw *);
c44ade9e
JB		 2949 s32 (*reset)(struct ixgbe_hw *);
2950 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2951 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3dcc2f41
ET		 2952 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
2953 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3957d63d 2954 s32 (*setup_link)(struct ixgbe_hw *);
99b76642 2955 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
0befdb3e
JB		 2956 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2957 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
c44ade9e
JB		 2958 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2959 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
07ce870b 2960 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
c44ade9e
JB		 2961 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2962 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
119fc60a 2963 s32 (*check_overtemp)(struct ixgbe_hw *);
9a799d71
AK		 2964};
2965
9a799d71 2966struct ixgbe_eeprom_info {
c44ade9e
JB		 2967 struct ixgbe_eeprom_operations ops;
2968 enum ixgbe_eeprom_type type;
11afc1b1 2969 u32 semaphore_delay;
c44ade9e
JB		 2970 u16 word_size;
2971 u16 address_bits;
68c7005d 2972 u16 word_page_size;
9a799d71
AK		 2973};
2974
a4297dc2 2975#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
c44ade9e
JB		 2976struct ixgbe_mac_info {
2977 struct ixgbe_mac_operations ops;
2978 enum ixgbe_mac_type type;
ea99d832
JP		 2979 u8 addr[ETH_ALEN];
2980 u8 perm_addr[ETH_ALEN];
2981 u8 san_addr[ETH_ALEN];
383ff34b
YZ		 2982 /* prefix for World Wide Node Name (WWNN) */
2983 u16 wwnn_prefix;
2984 /* prefix for World Wide Port Name (WWPN) */
2985 u16 wwpn_prefix;
71161302 2986 u16 max_msix_vectors;
80960ab0
ET		 2987#define IXGBE_MAX_MTA 128
2988 u32 mta_shadow[IXGBE_MAX_MTA];
c44ade9e
JB		 2989 s32 mc_filter_type;
2990 u32 mcft_size;
2991 u32 vft_size;
2992 u32 num_rar_entries;
21ce849b 2993 u32 rar_highwater;
e09ad236 2994 u32 rx_pb_size;
c44ade9e
JB		 2995 u32 max_tx_queues;
2996 u32 max_rx_queues;
3201d313
PWJ		 2997 u32 orig_autoc;
2998 u32 orig_autoc2;
2999 bool orig_link_settings_stored;
50ac58ba 3000 bool autotry_restart;
a4297dc2 3001 u8 flags;
7fa7c9dc 3002 u8 san_mac_rar_index;
e1ea9158 3003 struct ixgbe_thermal_sensor_data thermal_sensor_data;
9a799d71
AK		 3004};
3005
c44ade9e
JB		 3006struct ixgbe_phy_info {
3007 struct ixgbe_phy_operations ops;
6b73e10d 3008 struct mdio_if_info mdio;
c44ade9e 3009 enum ixgbe_phy_type type;
c44ade9e
JB		 3010 u32 id;
3011 enum ixgbe_sfp_type sfp_type;
553b4497 3012 bool sfp_setup_needed;
c44ade9e
JB		 3013 u32 revision;
3014 enum ixgbe_media_type media_type;
3015 bool reset_disable;
3016 ixgbe_autoneg_advertised autoneg_advertised;
cd7e1f0b
DS		 3017 enum ixgbe_smart_speed smart_speed;
3018 bool smart_speed_active;
0ecc061d 3019 bool multispeed_fiber;
119fc60a 3020 bool reset_if_overtemp;
8f58332b 3021 bool qsfp_shared_i2c_bus;
9a799d71
AK		 3022};
3023
7f870475
GR		 3024#include "ixgbe_mbx.h"
3025
3026struct ixgbe_mbx_operations {
3027 s32 (*init_params)(struct ixgbe_hw *hw);
3028 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
3029 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3030 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3031 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3032 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
3033 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
3034 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
3035};
3036
3037struct ixgbe_mbx_stats {
3038 u32 msgs_tx;
3039 u32 msgs_rx;
3040
3041 u32 acks;
3042 u32 reqs;
3043 u32 rsts;
3044};
3045
3046struct ixgbe_mbx_info {
3047 struct ixgbe_mbx_operations ops;
3048 struct ixgbe_mbx_stats stats;
3049 u32 timeout;
3050 u32 usec_delay;
3051 u32 v2p_mailbox;
3052 u16 size;
3053};
3054
9a799d71
AK		 3055struct ixgbe_hw {
3056 u8 __iomem *hw_addr;
3057 void *back;
3058 struct ixgbe_mac_info mac;
3059 struct ixgbe_addr_filter_info addr_ctrl;
3060 struct ixgbe_fc_info fc;
3061 struct ixgbe_phy_info phy;
3062 struct ixgbe_eeprom_info eeprom;
11afc1b1 3063 struct ixgbe_bus_info bus;
7f870475 3064 struct ixgbe_mbx_info mbx;
9a799d71
AK		 3065 u16 device_id;
3066 u16 vendor_id;
3067 u16 subsystem_device_id;
3068 u16 subsystem_vendor_id;
3069 u8 revision_id;
3070 bool adapter_stopped;
fe15e8e1 3071 bool force_full_reset;
8ef78adc 3072 bool allow_unsupported_sfp;
6b92b0ba 3073 bool wol_enabled;
9a799d71
AK		 3074};
3075
c44ade9e
JB		 3076struct ixgbe_info {
3077 enum ixgbe_mac_type mac;
3078 s32 (*get_invariants)(struct ixgbe_hw *);
3079 struct ixgbe_mac_operations *mac_ops;
3080 struct ixgbe_eeprom_operations *eeprom_ops;
3081 struct ixgbe_phy_operations *phy_ops;
7f870475 3082 struct ixgbe_mbx_operations *mbx_ops;
c44ade9e
JB		 3083};
3084
3085
9a799d71
AK		 3086/* Error Codes */
3087#define IXGBE_ERR_EEPROM -1
3088#define IXGBE_ERR_EEPROM_CHECKSUM -2
3089#define IXGBE_ERR_PHY -3
3090#define IXGBE_ERR_CONFIG -4
3091#define IXGBE_ERR_PARAM -5
3092#define IXGBE_ERR_MAC_TYPE -6
3093#define IXGBE_ERR_UNKNOWN_PHY -7
3094#define IXGBE_ERR_LINK_SETUP -8
3095#define IXGBE_ERR_ADAPTER_STOPPED -9
3096#define IXGBE_ERR_INVALID_MAC_ADDR -10
3097#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
3098#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
3099#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
3100#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
3101#define IXGBE_ERR_RESET_FAILED -15
3102#define IXGBE_ERR_SWFW_SYNC -16
3103#define IXGBE_ERR_PHY_ADDR_INVALID -17
c44ade9e
JB		 3104#define IXGBE_ERR_I2C -18
3105#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
c4900be0 3106#define IXGBE_ERR_SFP_NOT_PRESENT -20
11afc1b1 3107#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
21ce849b 3108#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
bfde493e 3109#define IXGBE_ERR_FDIR_REINIT_FAILED -23
794caeb2 3110#define IXGBE_ERR_EEPROM_VERSION -24
21ce849b 3111#define IXGBE_ERR_NO_SPACE -25
119fc60a 3112#define IXGBE_ERR_OVERTEMP -26
0b0c2b31
ET		 3113#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3114#define IXGBE_ERR_FC_NOT_SUPPORTED -28
a7f5a5fc 3115#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
289700db
DS		 3116#define IXGBE_ERR_PBA_SECTION -31
3117#define IXGBE_ERR_INVALID_ARGUMENT -32
9612de92 3118#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
9a799d71
AK		 3119#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3120
3121#endif /* _IXGBE_TYPE_H_ */
Linux kernel - Deliverables
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