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ixgbevf: Drop use of eitr_low and eitr_high for hard coded values
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbevf / ixgbevf_main.c
CommitLineData
92915f71
GR		 1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
5c47a2b6 4 Copyright(c) 1999 - 2012 Intel Corporation.
92915f71
GR		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/******************************************************************************
30 Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
31******************************************************************************/
dbd9636e
JK		 32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
92915f71 35#include <linux/types.h>
dadcd65f 36#include <linux/bitops.h>
92915f71
GR		 37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/vmalloc.h>
41#include <linux/string.h>
42#include <linux/in.h>
43#include <linux/ip.h>
44#include <linux/tcp.h>
45#include <linux/ipv6.h>
5a0e3ad6 46#include <linux/slab.h>
92915f71
GR		 47#include <net/checksum.h>
48#include <net/ip6_checksum.h>
49#include <linux/ethtool.h>
01789349 50#include <linux/if.h>
92915f71 51#include <linux/if_vlan.h>
70c71606 52#include <linux/prefetch.h>
92915f71
GR		 53
54#include "ixgbevf.h"
55
3d8fe98f 56const char ixgbevf_driver_name[] = "ixgbevf";
92915f71 57static const char ixgbevf_driver_string[] =
422e05d1 58 "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver";
92915f71 59
9cd9130d 60#define DRV_VERSION "2.6.0-k"
92915f71 61const char ixgbevf_driver_version[] = DRV_VERSION;
66c87bd5 62static char ixgbevf_copyright[] =
5c47a2b6 63 "Copyright (c) 2009 - 2012 Intel Corporation.";
92915f71
GR		 64
65static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
2316aa2a
GR		 66 [board_82599_vf] = &ixgbevf_82599_vf_info,
67 [board_X540_vf] = &ixgbevf_X540_vf_info,
92915f71
GR		 68};
69
70/* ixgbevf_pci_tbl - PCI Device ID Table
71 *
72 * Wildcard entries (PCI_ANY_ID) should come last
73 * Last entry must be all 0s
74 *
75 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
76 * Class, Class Mask, private data (not used) }
77 */
78static struct pci_device_id ixgbevf_pci_tbl[] = {
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF),
80 board_82599_vf},
2316aa2a
GR		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF),
82 board_X540_vf},
92915f71
GR		 83
84 /* required last entry */
85 {0, }
86};
87MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl);
88
89MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
90MODULE_DESCRIPTION("Intel(R) 82599 Virtual Function Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
b3f4d599 94#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
95static int debug = -1;
96module_param(debug, int, 0);
97MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92915f71
GR		 98
99/* forward decls */
100static void ixgbevf_set_itr_msix(struct ixgbevf_q_vector *q_vector);
101static void ixgbevf_write_eitr(struct ixgbevf_adapter *adapter, int v_idx,
102 u32 itr_reg);
103
104static inline void ixgbevf_release_rx_desc(struct ixgbe_hw *hw,
105 struct ixgbevf_ring *rx_ring,
106 u32 val)
107{
108 /*
109 * Force memory writes to complete before letting h/w
110 * know there are new descriptors to fetch. (Only
111 * applicable for weak-ordered memory model archs,
112 * such as IA-64).
113 */
114 wmb();
115 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rx_ring->reg_idx), val);
116}
117
49ce9c2c 118/**
65d676c8 119 * ixgbevf_set_ivar - set IVAR registers - maps interrupt causes to vectors
92915f71
GR		 120 * @adapter: pointer to adapter struct
121 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
122 * @queue: queue to map the corresponding interrupt to
123 * @msix_vector: the vector to map to the corresponding queue
124 *
125 */
126static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction,
127 u8 queue, u8 msix_vector)
128{
129 u32 ivar, index;
130 struct ixgbe_hw *hw = &adapter->hw;
131 if (direction == -1) {
132 /* other causes */
133 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
134 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
135 ivar &= ~0xFF;
136 ivar |= msix_vector;
137 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar);
138 } else {
139 /* tx or rx causes */
140 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
141 index = ((16 * (queue & 1)) + (8 * direction));
142 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
143 ivar &= ~(0xFF << index);
144 ivar |= (msix_vector << index);
145 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar);
146 }
147}
148
149static void ixgbevf_unmap_and_free_tx_resource(struct ixgbevf_adapter *adapter,
150 struct ixgbevf_tx_buffer
151 *tx_buffer_info)
152{
153 if (tx_buffer_info->dma) {
154 if (tx_buffer_info->mapped_as_page)
2a1f8794 155 dma_unmap_page(&adapter->pdev->dev,
92915f71
GR		 156 tx_buffer_info->dma,
157 tx_buffer_info->length,
2a1f8794 158 DMA_TO_DEVICE);
92915f71 159 else
2a1f8794 160 dma_unmap_single(&adapter->pdev->dev,
92915f71
GR		 161 tx_buffer_info->dma,
162 tx_buffer_info->length,
2a1f8794 163 DMA_TO_DEVICE);
92915f71
GR		 164 tx_buffer_info->dma = 0;
165 }
166 if (tx_buffer_info->skb) {
167 dev_kfree_skb_any(tx_buffer_info->skb);
168 tx_buffer_info->skb = NULL;
169 }
170 tx_buffer_info->time_stamp = 0;
171 /* tx_buffer_info must be completely set up in the transmit path */
172}
173
92915f71
GR		 174#define IXGBE_MAX_TXD_PWR 14
175#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
176
177/* Tx Descriptors needed, worst case */
178#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
179 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
92915f71
GR		 180#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
181 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
92915f71
GR		 182
183static void ixgbevf_tx_timeout(struct net_device *netdev);
184
185/**
186 * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes
187 * @adapter: board private structure
188 * @tx_ring: tx ring to clean
189 **/
190static bool ixgbevf_clean_tx_irq(struct ixgbevf_adapter *adapter,
191 struct ixgbevf_ring *tx_ring)
192{
193 struct net_device *netdev = adapter->netdev;
194 struct ixgbe_hw *hw = &adapter->hw;
195 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
196 struct ixgbevf_tx_buffer *tx_buffer_info;
197 unsigned int i, eop, count = 0;
198 unsigned int total_bytes = 0, total_packets = 0;
199
200 i = tx_ring->next_to_clean;
201 eop = tx_ring->tx_buffer_info[i].next_to_watch;
202 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
203
204 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
205 (count < tx_ring->work_limit)) {
206 bool cleaned = false;
2d0bb1c1 207 rmb(); /* read buffer_info after eop_desc */
98b9e48f
GR		 208 /* eop could change between read and DD-check */
209 if (unlikely(eop != tx_ring->tx_buffer_info[i].next_to_watch))
210 goto cont_loop;
92915f71
GR		 211 for ( ; !cleaned; count++) {
212 struct sk_buff *skb;
213 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
214 tx_buffer_info = &tx_ring->tx_buffer_info[i];
215 cleaned = (i == eop);
216 skb = tx_buffer_info->skb;
217
218 if (cleaned && skb) {
219 unsigned int segs, bytecount;
220
221 /* gso_segs is currently only valid for tcp */
222 segs = skb_shinfo(skb)->gso_segs ?: 1;
223 /* multiply data chunks by size of headers */
224 bytecount = ((segs - 1) * skb_headlen(skb)) +
225 skb->len;
226 total_packets += segs;
227 total_bytes += bytecount;
228 }
229
230 ixgbevf_unmap_and_free_tx_resource(adapter,
231 tx_buffer_info);
232
233 tx_desc->wb.status = 0;
234
235 i++;
236 if (i == tx_ring->count)
237 i = 0;
238 }
239
98b9e48f 240cont_loop:
92915f71
GR		 241 eop = tx_ring->tx_buffer_info[i].next_to_watch;
242 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
243 }
244
245 tx_ring->next_to_clean = i;
246
247#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
248 if (unlikely(count && netif_carrier_ok(netdev) &&
249 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
250 /* Make sure that anybody stopping the queue after this
251 * sees the new next_to_clean.
252 */
253 smp_mb();
92915f71
GR		 254 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
255 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
256 netif_wake_subqueue(netdev, tx_ring->queue_index);
257 ++adapter->restart_queue;
258 }
92915f71
GR		 259 }
260
92915f71
GR		 261 /* re-arm the interrupt */
262 if ((count >= tx_ring->work_limit) &&
263 (!test_bit(__IXGBEVF_DOWN, &adapter->state))) {
264 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, tx_ring->v_idx);
265 }
266
4197aa7b 267 u64_stats_update_begin(&tx_ring->syncp);
92915f71
GR		 268 tx_ring->total_bytes += total_bytes;
269 tx_ring->total_packets += total_packets;
4197aa7b 270 u64_stats_update_end(&tx_ring->syncp);
92915f71 271
807540ba 272 return count < tx_ring->work_limit;
92915f71
GR		 273}
274
275/**
276 * ixgbevf_receive_skb - Send a completed packet up the stack
277 * @q_vector: structure containing interrupt and ring information
278 * @skb: packet to send up
279 * @status: hardware indication of status of receive
280 * @rx_ring: rx descriptor ring (for a specific queue) to setup
281 * @rx_desc: rx descriptor
282 **/
283static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
284 struct sk_buff *skb, u8 status,
285 struct ixgbevf_ring *ring,
286 union ixgbe_adv_rx_desc *rx_desc)
287{
288 struct ixgbevf_adapter *adapter = q_vector->adapter;
289 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
dd1ed3b7 290 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
92915f71 291
dd1ed3b7 292 if (is_vlan && test_bit(tag, adapter->active_vlans))
dadcd65f 293 __vlan_hwaccel_put_tag(skb, tag);
dadcd65f 294
77d5dfca 295 napi_gro_receive(&q_vector->napi, skb);
92915f71
GR		 296}
297
298/**
299 * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum
300 * @adapter: address of board private structure
301 * @status_err: hardware indication of status of receive
302 * @skb: skb currently being received and modified
303 **/
304static inline void ixgbevf_rx_checksum(struct ixgbevf_adapter *adapter,
305 u32 status_err, struct sk_buff *skb)
306{
bc8acf2c 307 skb_checksum_none_assert(skb);
92915f71
GR		 308
309 /* Rx csum disabled */
525a940c 310 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
92915f71
GR		 311 return;
312
313 /* if IP and error */
314 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
315 (status_err & IXGBE_RXDADV_ERR_IPE)) {
316 adapter->hw_csum_rx_error++;
317 return;
318 }
319
320 if (!(status_err & IXGBE_RXD_STAT_L4CS))
321 return;
322
323 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
324 adapter->hw_csum_rx_error++;
325 return;
326 }
327
328 /* It must be a TCP or UDP packet with a valid checksum */
329 skb->ip_summed = CHECKSUM_UNNECESSARY;
330 adapter->hw_csum_rx_good++;
331}
332
333/**
334 * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split
335 * @adapter: address of board private structure
336 **/
337static void ixgbevf_alloc_rx_buffers(struct ixgbevf_adapter *adapter,
338 struct ixgbevf_ring *rx_ring,
339 int cleaned_count)
340{
341 struct pci_dev *pdev = adapter->pdev;
342 union ixgbe_adv_rx_desc *rx_desc;
343 struct ixgbevf_rx_buffer *bi;
344 struct sk_buff *skb;
345 unsigned int i;
346 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
347
348 i = rx_ring->next_to_use;
349 bi = &rx_ring->rx_buffer_info[i];
350
351 while (cleaned_count--) {
352 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
92915f71
GR		 353 skb = bi->skb;
354 if (!skb) {
355 skb = netdev_alloc_skb(adapter->netdev,
356 bufsz);
357
358 if (!skb) {
359 adapter->alloc_rx_buff_failed++;
360 goto no_buffers;
361 }
362
363 /*
364 * Make buffer alignment 2 beyond a 16 byte boundary
365 * this will result in a 16 byte aligned IP header after
366 * the 14 byte MAC header is removed
367 */
368 skb_reserve(skb, NET_IP_ALIGN);
369
370 bi->skb = skb;
371 }
372 if (!bi->dma) {
2a1f8794 373 bi->dma = dma_map_single(&pdev->dev, skb->data,
92915f71 374 rx_ring->rx_buf_len,
2a1f8794 375 DMA_FROM_DEVICE);
92915f71 376 }
77d5dfca 377 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
92915f71
GR		 378
379 i++;
380 if (i == rx_ring->count)
381 i = 0;
382 bi = &rx_ring->rx_buffer_info[i];
383 }
384
385no_buffers:
386 if (rx_ring->next_to_use != i) {
387 rx_ring->next_to_use = i;
388 if (i-- == 0)
389 i = (rx_ring->count - 1);
390
391 ixgbevf_release_rx_desc(&adapter->hw, rx_ring, i);
392 }
393}
394
395static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter,
396 u64 qmask)
397{
398 u32 mask;
399 struct ixgbe_hw *hw = &adapter->hw;
400
401 mask = (qmask & 0xFFFFFFFF);
402 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
403}
404
92915f71
GR		 405static bool ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector,
406 struct ixgbevf_ring *rx_ring,
407 int *work_done, int work_to_do)
408{
409 struct ixgbevf_adapter *adapter = q_vector->adapter;
410 struct pci_dev *pdev = adapter->pdev;
411 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
412 struct ixgbevf_rx_buffer *rx_buffer_info, *next_buffer;
413 struct sk_buff *skb;
414 unsigned int i;
415 u32 len, staterr;
92915f71
GR		 416 bool cleaned = false;
417 int cleaned_count = 0;
418 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
419
420 i = rx_ring->next_to_clean;
421 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
422 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
423 rx_buffer_info = &rx_ring->rx_buffer_info[i];
424
425 while (staterr & IXGBE_RXD_STAT_DD) {
92915f71
GR		 426 if (*work_done >= work_to_do)
427 break;
428 (*work_done)++;
429
2d0bb1c1 430 rmb(); /* read descriptor and rx_buffer_info after status DD */
77d5dfca 431 len = le16_to_cpu(rx_desc->wb.upper.length);
92915f71
GR		 432 cleaned = true;
433 skb = rx_buffer_info->skb;
434 prefetch(skb->data - NET_IP_ALIGN);
435 rx_buffer_info->skb = NULL;
436
437 if (rx_buffer_info->dma) {
2a1f8794 438 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
92915f71 439 rx_ring->rx_buf_len,
2a1f8794 440 DMA_FROM_DEVICE);
92915f71
GR		 441 rx_buffer_info->dma = 0;
442 skb_put(skb, len);
443 }
444
92915f71
GR		 445 i++;
446 if (i == rx_ring->count)
447 i = 0;
448
449 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
450 prefetch(next_rxd);
451 cleaned_count++;
452
453 next_buffer = &rx_ring->rx_buffer_info[i];
454
455 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
77d5dfca
AD		 456 skb->next = next_buffer->skb;
457 skb->next->prev = skb;
92915f71
GR		 458 adapter->non_eop_descs++;
459 goto next_desc;
460 }
461
462 /* ERR_MASK will only have valid bits if EOP set */
463 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
464 dev_kfree_skb_irq(skb);
465 goto next_desc;
466 }
467
468 ixgbevf_rx_checksum(adapter, staterr, skb);
469
470 /* probably a little skewed due to removing CRC */
471 total_rx_bytes += skb->len;
472 total_rx_packets++;
473
474 /*
475 * Work around issue of some types of VM to VM loop back
476 * packets not getting split correctly
477 */
478 if (staterr & IXGBE_RXD_STAT_LB) {
e743d313 479 u32 header_fixup_len = skb_headlen(skb);
92915f71
GR		 480 if (header_fixup_len < 14)
481 skb_push(skb, header_fixup_len);
482 }
483 skb->protocol = eth_type_trans(skb, adapter->netdev);
484
485 ixgbevf_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
92915f71
GR		 486
487next_desc:
488 rx_desc->wb.upper.status_error = 0;
489
490 /* return some buffers to hardware, one at a time is too slow */
491 if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) {
492 ixgbevf_alloc_rx_buffers(adapter, rx_ring,
493 cleaned_count);
494 cleaned_count = 0;
495 }
496
497 /* use prefetched values */
498 rx_desc = next_rxd;
499 rx_buffer_info = &rx_ring->rx_buffer_info[i];
500
501 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
502 }
503
504 rx_ring->next_to_clean = i;
505 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
506
507 if (cleaned_count)
508 ixgbevf_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
509
4197aa7b 510 u64_stats_update_begin(&rx_ring->syncp);
92915f71
GR		 511 rx_ring->total_packets += total_rx_packets;
512 rx_ring->total_bytes += total_rx_bytes;
4197aa7b 513 u64_stats_update_end(&rx_ring->syncp);
92915f71
GR		 514
515 return cleaned;
516}
517
518/**
519 * ixgbevf_clean_rxonly - msix (aka one shot) rx clean routine
520 * @napi: napi struct with our devices info in it
521 * @budget: amount of work driver is allowed to do this pass, in packets
522 *
523 * This function is optimized for cleaning one queue only on a single
524 * q_vector!!!
525 **/
526static int ixgbevf_clean_rxonly(struct napi_struct *napi, int budget)
527{
528 struct ixgbevf_q_vector *q_vector =
529 container_of(napi, struct ixgbevf_q_vector, napi);
530 struct ixgbevf_adapter *adapter = q_vector->adapter;
531 struct ixgbevf_ring *rx_ring = NULL;
532 int work_done = 0;
533 long r_idx;
534
535 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
536 rx_ring = &(adapter->rx_ring[r_idx]);
537
538 ixgbevf_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
539
540 /* If all Rx work done, exit the polling mode */
541 if (work_done < budget) {
542 napi_complete(napi);
543 if (adapter->itr_setting & 1)
544 ixgbevf_set_itr_msix(q_vector);
545 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
546 ixgbevf_irq_enable_queues(adapter, rx_ring->v_idx);
547 }
548
549 return work_done;
550}
551
552/**
553 * ixgbevf_clean_rxonly_many - msix (aka one shot) rx clean routine
554 * @napi: napi struct with our devices info in it
555 * @budget: amount of work driver is allowed to do this pass, in packets
556 *
557 * This function will clean more than one rx queue associated with a
558 * q_vector.
559 **/
560static int ixgbevf_clean_rxonly_many(struct napi_struct *napi, int budget)
561{
562 struct ixgbevf_q_vector *q_vector =
563 container_of(napi, struct ixgbevf_q_vector, napi);
564 struct ixgbevf_adapter *adapter = q_vector->adapter;
565 struct ixgbevf_ring *rx_ring = NULL;
566 int work_done = 0, i;
567 long r_idx;
568 u64 enable_mask = 0;
569
570 /* attempt to distribute budget to each queue fairly, but don't allow
571 * the budget to go below 1 because we'll exit polling */
572 budget /= (q_vector->rxr_count ?: 1);
573 budget = max(budget, 1);
574 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
575 for (i = 0; i < q_vector->rxr_count; i++) {
576 rx_ring = &(adapter->rx_ring[r_idx]);
577 ixgbevf_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
578 enable_mask |= rx_ring->v_idx;
579 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
580 r_idx + 1);
581 }
582
92915f71
GR		 583 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
584 rx_ring = &(adapter->rx_ring[r_idx]);
585
586 /* If all Rx work done, exit the polling mode */
587 if (work_done < budget) {
588 napi_complete(napi);
589 if (adapter->itr_setting & 1)
590 ixgbevf_set_itr_msix(q_vector);
591 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
592 ixgbevf_irq_enable_queues(adapter, enable_mask);
593 }
594
595 return work_done;
596}
597
598
599/**
600 * ixgbevf_configure_msix - Configure MSI-X hardware
601 * @adapter: board private structure
602 *
603 * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X
604 * interrupts.
605 **/
606static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter)
607{
608 struct ixgbevf_q_vector *q_vector;
609 struct ixgbe_hw *hw = &adapter->hw;
610 int i, j, q_vectors, v_idx, r_idx;
611 u32 mask;
612
613 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
614
615 /*
616 * Populate the IVAR table and set the ITR values to the
617 * corresponding register.
618 */
619 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
620 q_vector = adapter->q_vector[v_idx];
984b3f57 621 /* XXX for_each_set_bit(...) */
92915f71
GR		 622 r_idx = find_first_bit(q_vector->rxr_idx,
623 adapter->num_rx_queues);
624
625 for (i = 0; i < q_vector->rxr_count; i++) {
626 j = adapter->rx_ring[r_idx].reg_idx;
627 ixgbevf_set_ivar(adapter, 0, j, v_idx);
628 r_idx = find_next_bit(q_vector->rxr_idx,
629 adapter->num_rx_queues,
630 r_idx + 1);
631 }
632 r_idx = find_first_bit(q_vector->txr_idx,
633 adapter->num_tx_queues);
634
635 for (i = 0; i < q_vector->txr_count; i++) {
636 j = adapter->tx_ring[r_idx].reg_idx;
637 ixgbevf_set_ivar(adapter, 1, j, v_idx);
638 r_idx = find_next_bit(q_vector->txr_idx,
639 adapter->num_tx_queues,
640 r_idx + 1);
641 }
642
643 /* if this is a tx only vector halve the interrupt rate */
644 if (q_vector->txr_count && !q_vector->rxr_count)
645 q_vector->eitr = (adapter->eitr_param >> 1);
646 else if (q_vector->rxr_count)
647 /* rx only */
648 q_vector->eitr = adapter->eitr_param;
649
650 ixgbevf_write_eitr(adapter, v_idx, q_vector->eitr);
651 }
652
653 ixgbevf_set_ivar(adapter, -1, 1, v_idx);
654
655 /* set up to autoclear timer, and the vectors */
656 mask = IXGBE_EIMS_ENABLE_MASK;
657 mask &= ~IXGBE_EIMS_OTHER;
658 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, mask);
659}
660
661enum latency_range {
662 lowest_latency = 0,
663 low_latency = 1,
664 bulk_latency = 2,
665 latency_invalid = 255
666};
667
668/**
669 * ixgbevf_update_itr - update the dynamic ITR value based on statistics
670 * @adapter: pointer to adapter
671 * @eitr: eitr setting (ints per sec) to give last timeslice
672 * @itr_setting: current throttle rate in ints/second
673 * @packets: the number of packets during this measurement interval
674 * @bytes: the number of bytes during this measurement interval
675 *
676 * Stores a new ITR value based on packets and byte
677 * counts during the last interrupt. The advantage of per interrupt
678 * computation is faster updates and more accurate ITR for the current
679 * traffic pattern. Constants in this function were computed
680 * based on theoretical maximum wire speed and thresholds were set based
681 * on testing data as well as attempting to minimize response time
682 * while increasing bulk throughput.
683 **/
684static u8 ixgbevf_update_itr(struct ixgbevf_adapter *adapter,
685 u32 eitr, u8 itr_setting,
686 int packets, int bytes)
687{
688 unsigned int retval = itr_setting;
689 u32 timepassed_us;
690 u64 bytes_perint;
691
692 if (packets == 0)
693 goto update_itr_done;
694
695
696 /* simple throttlerate management
697 * 0-20MB/s lowest (100000 ints/s)
698 * 20-100MB/s low (20000 ints/s)
699 * 100-1249MB/s bulk (8000 ints/s)
700 */
701 /* what was last interrupt timeslice? */
702 timepassed_us = 1000000/eitr;
703 bytes_perint = bytes / timepassed_us; /* bytes/usec */
704
705 switch (itr_setting) {
706 case lowest_latency:
e2c28ce7 707 if (bytes_perint > 10)
92915f71
GR		 708 retval = low_latency;
709 break;
710 case low_latency:
e2c28ce7 711 if (bytes_perint > 20)
92915f71 712 retval = bulk_latency;
e2c28ce7 713 else if (bytes_perint <= 10)
92915f71
GR		 714 retval = lowest_latency;
715 break;
716 case bulk_latency:
e2c28ce7 717 if (bytes_perint <= 20)
92915f71
GR		 718 retval = low_latency;
719 break;
720 }
721
722update_itr_done:
723 return retval;
724}
725
726/**
727 * ixgbevf_write_eitr - write VTEITR register in hardware specific way
728 * @adapter: pointer to adapter struct
729 * @v_idx: vector index into q_vector array
730 * @itr_reg: new value to be written in *register* format, not ints/s
731 *
732 * This function is made to be called by ethtool and by the driver
733 * when it needs to update VTEITR registers at runtime. Hardware
734 * specific quirks/differences are taken care of here.
735 */
736static void ixgbevf_write_eitr(struct ixgbevf_adapter *adapter, int v_idx,
737 u32 itr_reg)
738{
739 struct ixgbe_hw *hw = &adapter->hw;
740
741 itr_reg = EITR_INTS_PER_SEC_TO_REG(itr_reg);
742
743 /*
744 * set the WDIS bit to not clear the timer bits and cause an
745 * immediate assertion of the interrupt
746 */
747 itr_reg |= IXGBE_EITR_CNT_WDIS;
748
749 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg);
750}
751
752static void ixgbevf_set_itr_msix(struct ixgbevf_q_vector *q_vector)
753{
754 struct ixgbevf_adapter *adapter = q_vector->adapter;
755 u32 new_itr;
756 u8 current_itr, ret_itr;
757 int i, r_idx, v_idx = q_vector->v_idx;
758 struct ixgbevf_ring *rx_ring, *tx_ring;
759
760 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
761 for (i = 0; i < q_vector->txr_count; i++) {
762 tx_ring = &(adapter->tx_ring[r_idx]);
763 ret_itr = ixgbevf_update_itr(adapter, q_vector->eitr,
764 q_vector->tx_itr,
765 tx_ring->total_packets,
766 tx_ring->total_bytes);
767 /* if the result for this queue would decrease interrupt
768 * rate for this vector then use that result */
769 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
770 q_vector->tx_itr - 1 : ret_itr);
771 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
772 r_idx + 1);
773 }
774
775 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
776 for (i = 0; i < q_vector->rxr_count; i++) {
777 rx_ring = &(adapter->rx_ring[r_idx]);
778 ret_itr = ixgbevf_update_itr(adapter, q_vector->eitr,
779 q_vector->rx_itr,
780 rx_ring->total_packets,
781 rx_ring->total_bytes);
782 /* if the result for this queue would decrease interrupt
783 * rate for this vector then use that result */
784 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
785 q_vector->rx_itr - 1 : ret_itr);
786 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
787 r_idx + 1);
788 }
789
790 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
791
792 switch (current_itr) {
793 /* counts and packets in update_itr are dependent on these numbers */
794 case lowest_latency:
795 new_itr = 100000;
796 break;
797 case low_latency:
798 new_itr = 20000; /* aka hwitr = ~200 */
799 break;
800 case bulk_latency:
801 default:
802 new_itr = 8000;
803 break;
804 }
805
806 if (new_itr != q_vector->eitr) {
807 u32 itr_reg;
808
809 /* save the algorithm value here, not the smoothed one */
810 q_vector->eitr = new_itr;
811 /* do an exponential smoothing */
812 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
813 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
814 ixgbevf_write_eitr(adapter, v_idx, itr_reg);
815 }
92915f71
GR		 816}
817
818static irqreturn_t ixgbevf_msix_mbx(int irq, void *data)
819{
820 struct net_device *netdev = data;
821 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
822 struct ixgbe_hw *hw = &adapter->hw;
823 u32 eicr;
a9ee25a2 824 u32 msg;
375b27cf 825 bool got_ack = false;
92915f71
GR		 826
827 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICS);
828 IXGBE_WRITE_REG(hw, IXGBE_VTEICR, eicr);
829
375b27cf
GR		 830 if (!hw->mbx.ops.check_for_ack(hw))
831 got_ack = true;
08259594 832
375b27cf
GR		 833 if (!hw->mbx.ops.check_for_msg(hw)) {
834 hw->mbx.ops.read(hw, &msg, 1);
a9ee25a2 835
375b27cf
GR		 836 if ((msg & IXGBE_MBVFICR_VFREQ_MASK) == IXGBE_PF_CONTROL_MSG)
837 mod_timer(&adapter->watchdog_timer,
838 round_jiffies(jiffies + 1));
a9ee25a2 839
375b27cf
GR		 840 if (msg & IXGBE_VT_MSGTYPE_NACK)
841 pr_warn("Last Request of type %2.2x to PF Nacked\n",
842 msg & 0xFF);
3a2c4033
GR		 843 /*
844 * Restore the PFSTS bit in case someone is polling for a
845 * return message from the PF
846 */
847 hw->mbx.v2p_mailbox |= IXGBE_VFMAILBOX_PFSTS;
375b27cf
GR		 848 }
849
850 /*
851 * checking for the ack clears the PFACK bit. Place
852 * it back in the v2p_mailbox cache so that anyone
853 * polling for an ack will not miss it
854 */
855 if (got_ack)
856 hw->mbx.v2p_mailbox |= IXGBE_VFMAILBOX_PFACK;
3a2c4033 857
92915f71
GR		 858 return IRQ_HANDLED;
859}
860
861static irqreturn_t ixgbevf_msix_clean_tx(int irq, void *data)
862{
863 struct ixgbevf_q_vector *q_vector = data;
864 struct ixgbevf_adapter *adapter = q_vector->adapter;
865 struct ixgbevf_ring *tx_ring;
866 int i, r_idx;
867
868 if (!q_vector->txr_count)
869 return IRQ_HANDLED;
870
871 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
872 for (i = 0; i < q_vector->txr_count; i++) {
873 tx_ring = &(adapter->tx_ring[r_idx]);
874 tx_ring->total_bytes = 0;
875 tx_ring->total_packets = 0;
876 ixgbevf_clean_tx_irq(adapter, tx_ring);
877 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
878 r_idx + 1);
879 }
880
881 if (adapter->itr_setting & 1)
882 ixgbevf_set_itr_msix(q_vector);
883
884 return IRQ_HANDLED;
885}
886
887/**
65d676c8 888 * ixgbevf_msix_clean_rx - single unshared vector rx clean (all queues)
92915f71
GR		 889 * @irq: unused
890 * @data: pointer to our q_vector struct for this interrupt vector
891 **/
892static irqreturn_t ixgbevf_msix_clean_rx(int irq, void *data)
893{
894 struct ixgbevf_q_vector *q_vector = data;
895 struct ixgbevf_adapter *adapter = q_vector->adapter;
896 struct ixgbe_hw *hw = &adapter->hw;
897 struct ixgbevf_ring *rx_ring;
898 int r_idx;
899 int i;
900
901 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
902 for (i = 0; i < q_vector->rxr_count; i++) {
903 rx_ring = &(adapter->rx_ring[r_idx]);
904 rx_ring->total_bytes = 0;
905 rx_ring->total_packets = 0;
906 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
907 r_idx + 1);
908 }
909
910 if (!q_vector->rxr_count)
911 return IRQ_HANDLED;
912
913 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
914 rx_ring = &(adapter->rx_ring[r_idx]);
915 /* disable interrupts on this vector only */
916 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, rx_ring->v_idx);
917 napi_schedule(&q_vector->napi);
918
919
920 return IRQ_HANDLED;
921}
922
923static irqreturn_t ixgbevf_msix_clean_many(int irq, void *data)
924{
925 ixgbevf_msix_clean_rx(irq, data);
926 ixgbevf_msix_clean_tx(irq, data);
927
928 return IRQ_HANDLED;
929}
930
931static inline void map_vector_to_rxq(struct ixgbevf_adapter *a, int v_idx,
932 int r_idx)
933{
934 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
935
936 set_bit(r_idx, q_vector->rxr_idx);
937 q_vector->rxr_count++;
938 a->rx_ring[r_idx].v_idx = 1 << v_idx;
939}
940
941static inline void map_vector_to_txq(struct ixgbevf_adapter *a, int v_idx,
942 int t_idx)
943{
944 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
945
946 set_bit(t_idx, q_vector->txr_idx);
947 q_vector->txr_count++;
948 a->tx_ring[t_idx].v_idx = 1 << v_idx;
949}
950
951/**
952 * ixgbevf_map_rings_to_vectors - Maps descriptor rings to vectors
953 * @adapter: board private structure to initialize
954 *
955 * This function maps descriptor rings to the queue-specific vectors
956 * we were allotted through the MSI-X enabling code. Ideally, we'd have
957 * one vector per ring/queue, but on a constrained vector budget, we
958 * group the rings as "efficiently" as possible. You would add new
959 * mapping configurations in here.
960 **/
961static int ixgbevf_map_rings_to_vectors(struct ixgbevf_adapter *adapter)
962{
963 int q_vectors;
964 int v_start = 0;
965 int rxr_idx = 0, txr_idx = 0;
966 int rxr_remaining = adapter->num_rx_queues;
967 int txr_remaining = adapter->num_tx_queues;
968 int i, j;
969 int rqpv, tqpv;
970 int err = 0;
971
972 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
973
974 /*
975 * The ideal configuration...
976 * We have enough vectors to map one per queue.
977 */
978 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
979 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
980 map_vector_to_rxq(adapter, v_start, rxr_idx);
981
982 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
983 map_vector_to_txq(adapter, v_start, txr_idx);
984 goto out;
985 }
986
987 /*
988 * If we don't have enough vectors for a 1-to-1
989 * mapping, we'll have to group them so there are
990 * multiple queues per vector.
991 */
992 /* Re-adjusting *qpv takes care of the remainder. */
993 for (i = v_start; i < q_vectors; i++) {
994 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
995 for (j = 0; j < rqpv; j++) {
996 map_vector_to_rxq(adapter, i, rxr_idx);
997 rxr_idx++;
998 rxr_remaining--;
999 }
1000 }
1001 for (i = v_start; i < q_vectors; i++) {
1002 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
1003 for (j = 0; j < tqpv; j++) {
1004 map_vector_to_txq(adapter, i, txr_idx);
1005 txr_idx++;
1006 txr_remaining--;
1007 }
1008 }
1009
1010out:
1011 return err;
1012}
1013
1014/**
1015 * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts
1016 * @adapter: board private structure
1017 *
1018 * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests
1019 * interrupts from the kernel.
1020 **/
1021static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter)
1022{
1023 struct net_device *netdev = adapter->netdev;
1024 irqreturn_t (*handler)(int, void *);
1025 int i, vector, q_vectors, err;
1026 int ri = 0, ti = 0;
1027
1028 /* Decrement for Other and TCP Timer vectors */
1029 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1030
1031#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
1032 ? &ixgbevf_msix_clean_many : \
1033 (_v)->rxr_count ? &ixgbevf_msix_clean_rx : \
1034 (_v)->txr_count ? &ixgbevf_msix_clean_tx : \
1035 NULL)
1036 for (vector = 0; vector < q_vectors; vector++) {
1037 handler = SET_HANDLER(adapter->q_vector[vector]);
1038
1039 if (handler == &ixgbevf_msix_clean_rx) {
1040 sprintf(adapter->name[vector], "%s-%s-%d",
1041 netdev->name, "rx", ri++);
1042 } else if (handler == &ixgbevf_msix_clean_tx) {
1043 sprintf(adapter->name[vector], "%s-%s-%d",
1044 netdev->name, "tx", ti++);
1045 } else if (handler == &ixgbevf_msix_clean_many) {
1046 sprintf(adapter->name[vector], "%s-%s-%d",
1047 netdev->name, "TxRx", vector);
1048 } else {
1049 /* skip this unused q_vector */
1050 continue;
1051 }
1052 err = request_irq(adapter->msix_entries[vector].vector,
1053 handler, 0, adapter->name[vector],
1054 adapter->q_vector[vector]);
1055 if (err) {
1056 hw_dbg(&adapter->hw,
1057 "request_irq failed for MSIX interrupt "
1058 "Error: %d\n", err);
1059 goto free_queue_irqs;
1060 }
1061 }
1062
1063 sprintf(adapter->name[vector], "%s:mbx", netdev->name);
1064 err = request_irq(adapter->msix_entries[vector].vector,
1065 &ixgbevf_msix_mbx, 0, adapter->name[vector], netdev);
1066 if (err) {
1067 hw_dbg(&adapter->hw,
1068 "request_irq for msix_mbx failed: %d\n", err);
1069 goto free_queue_irqs;
1070 }
1071
1072 return 0;
1073
1074free_queue_irqs:
1075 for (i = vector - 1; i >= 0; i--)
1076 free_irq(adapter->msix_entries[--vector].vector,
1077 &(adapter->q_vector[i]));
1078 pci_disable_msix(adapter->pdev);
1079 kfree(adapter->msix_entries);
1080 adapter->msix_entries = NULL;
1081 return err;
1082}
1083
1084static inline void ixgbevf_reset_q_vectors(struct ixgbevf_adapter *adapter)
1085{
1086 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1087
1088 for (i = 0; i < q_vectors; i++) {
1089 struct ixgbevf_q_vector *q_vector = adapter->q_vector[i];
1090 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1091 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1092 q_vector->rxr_count = 0;
1093 q_vector->txr_count = 0;
1094 q_vector->eitr = adapter->eitr_param;
1095 }
1096}
1097
1098/**
1099 * ixgbevf_request_irq - initialize interrupts
1100 * @adapter: board private structure
1101 *
1102 * Attempts to configure interrupts using the best available
1103 * capabilities of the hardware and kernel.
1104 **/
1105static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter)
1106{
1107 int err = 0;
1108
1109 err = ixgbevf_request_msix_irqs(adapter);
1110
1111 if (err)
1112 hw_dbg(&adapter->hw,
1113 "request_irq failed, Error %d\n", err);
1114
1115 return err;
1116}
1117
1118static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter)
1119{
1120 struct net_device *netdev = adapter->netdev;
1121 int i, q_vectors;
1122
1123 q_vectors = adapter->num_msix_vectors;
1124
1125 i = q_vectors - 1;
1126
1127 free_irq(adapter->msix_entries[i].vector, netdev);
1128 i--;
1129
1130 for (; i >= 0; i--) {
1131 free_irq(adapter->msix_entries[i].vector,
1132 adapter->q_vector[i]);
1133 }
1134
1135 ixgbevf_reset_q_vectors(adapter);
1136}
1137
1138/**
1139 * ixgbevf_irq_disable - Mask off interrupt generation on the NIC
1140 * @adapter: board private structure
1141 **/
1142static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter)
1143{
1144 int i;
1145 struct ixgbe_hw *hw = &adapter->hw;
1146
1147 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0);
1148
1149 IXGBE_WRITE_FLUSH(hw);
1150
1151 for (i = 0; i < adapter->num_msix_vectors; i++)
1152 synchronize_irq(adapter->msix_entries[i].vector);
1153}
1154
1155/**
1156 * ixgbevf_irq_enable - Enable default interrupt generation settings
1157 * @adapter: board private structure
1158 **/
1159static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter,
1160 bool queues, bool flush)
1161{
1162 struct ixgbe_hw *hw = &adapter->hw;
1163 u32 mask;
1164 u64 qmask;
1165
1166 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1167 qmask = ~0;
1168
1169 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
1170
1171 if (queues)
1172 ixgbevf_irq_enable_queues(adapter, qmask);
1173
1174 if (flush)
1175 IXGBE_WRITE_FLUSH(hw);
1176}
1177
1178/**
1179 * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset
1180 * @adapter: board private structure
1181 *
1182 * Configure the Tx unit of the MAC after a reset.
1183 **/
1184static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter)
1185{
1186 u64 tdba;
1187 struct ixgbe_hw *hw = &adapter->hw;
1188 u32 i, j, tdlen, txctrl;
1189
1190 /* Setup the HW Tx Head and Tail descriptor pointers */
1191 for (i = 0; i < adapter->num_tx_queues; i++) {
1192 struct ixgbevf_ring *ring = &adapter->tx_ring[i];
1193 j = ring->reg_idx;
1194 tdba = ring->dma;
1195 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1196 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j),
1197 (tdba & DMA_BIT_MASK(32)));
1198 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32));
1199 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j), tdlen);
1200 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(j), 0);
1201 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(j), 0);
1202 adapter->tx_ring[i].head = IXGBE_VFTDH(j);
1203 adapter->tx_ring[i].tail = IXGBE_VFTDT(j);
1204 /* Disable Tx Head Writeback RO bit, since this hoses
1205 * bookkeeping if things aren't delivered in order.
1206 */
1207 txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(j));
1208 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1209 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(j), txctrl);
1210 }
1211}
1212
1213#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1214
1215static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, int index)
1216{
1217 struct ixgbevf_ring *rx_ring;
1218 struct ixgbe_hw *hw = &adapter->hw;
1219 u32 srrctl;
1220
1221 rx_ring = &adapter->rx_ring[index];
1222
1223 srrctl = IXGBE_SRRCTL_DROP_EN;
1224
77d5dfca 1225 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
92915f71 1226
77d5dfca
AD		 1227 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1228 srrctl |= IXGBEVF_RXBUFFER_2048 >>
1229 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1230 else
1231 srrctl |= rx_ring->rx_buf_len >>
1232 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
92915f71
GR		 1233 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl);
1234}
1235
1236/**
1237 * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset
1238 * @adapter: board private structure
1239 *
1240 * Configure the Rx unit of the MAC after a reset.
1241 **/
1242static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter)
1243{
1244 u64 rdba;
1245 struct ixgbe_hw *hw = &adapter->hw;
1246 struct net_device *netdev = adapter->netdev;
1247 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1248 int i, j;
1249 u32 rdlen;
1250 int rx_buf_len;
1251
77d5dfca
AD		 1252 /* PSRTYPE must be initialized in 82599 */
1253 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
1254 if (netdev->mtu <= ETH_DATA_LEN)
1255 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1256 else
1257 rx_buf_len = ALIGN(max_frame, 1024);
92915f71
GR		 1258
1259 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1260 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1261 * the Base and Length of the Rx Descriptor Ring */
1262 for (i = 0; i < adapter->num_rx_queues; i++) {
1263 rdba = adapter->rx_ring[i].dma;
1264 j = adapter->rx_ring[i].reg_idx;
1265 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(j),
1266 (rdba & DMA_BIT_MASK(32)));
1267 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(j), (rdba >> 32));
1268 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(j), rdlen);
1269 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(j), 0);
1270 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(j), 0);
1271 adapter->rx_ring[i].head = IXGBE_VFRDH(j);
1272 adapter->rx_ring[i].tail = IXGBE_VFRDT(j);
1273 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1274
1275 ixgbevf_configure_srrctl(adapter, j);
1276 }
1277}
1278
8e586137 1279static int ixgbevf_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
92915f71
GR		 1280{
1281 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1282 struct ixgbe_hw *hw = &adapter->hw;
92915f71
GR		 1283
1284 /* add VID to filter table */
1285 if (hw->mac.ops.set_vfta)
1286 hw->mac.ops.set_vfta(hw, vid, 0, true);
dadcd65f 1287 set_bit(vid, adapter->active_vlans);
8e586137
JP		 1288
1289 return 0;
92915f71
GR		 1290}
1291
8e586137 1292static int ixgbevf_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
92915f71
GR		 1293{
1294 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1295 struct ixgbe_hw *hw = &adapter->hw;
1296
92915f71
GR		 1297 /* remove VID from filter table */
1298 if (hw->mac.ops.set_vfta)
1299 hw->mac.ops.set_vfta(hw, vid, 0, false);
dadcd65f 1300 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 1301
1302 return 0;
92915f71
GR		 1303}
1304
1305static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter)
1306{
dadcd65f 1307 u16 vid;
92915f71 1308
dadcd65f
JP		 1309 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1310 ixgbevf_vlan_rx_add_vid(adapter->netdev, vid);
92915f71
GR		 1311}
1312
46ec20ff
GR		 1313static int ixgbevf_write_uc_addr_list(struct net_device *netdev)
1314{
1315 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1316 struct ixgbe_hw *hw = &adapter->hw;
1317 int count = 0;
1318
1319 if ((netdev_uc_count(netdev)) > 10) {
dbd9636e 1320 pr_err("Too many unicast filters - No Space\n");
46ec20ff
GR		 1321 return -ENOSPC;
1322 }
1323
1324 if (!netdev_uc_empty(netdev)) {
1325 struct netdev_hw_addr *ha;
1326 netdev_for_each_uc_addr(ha, netdev) {
1327 hw->mac.ops.set_uc_addr(hw, ++count, ha->addr);
1328 udelay(200);
1329 }
1330 } else {
1331 /*
1332 * If the list is empty then send message to PF driver to
1333 * clear all macvlans on this VF.
1334 */
1335 hw->mac.ops.set_uc_addr(hw, 0, NULL);
1336 }
1337
1338 return count;
1339}
1340
92915f71
GR		 1341/**
1342 * ixgbevf_set_rx_mode - Multicast set
1343 * @netdev: network interface device structure
1344 *
1345 * The set_rx_method entry point is called whenever the multicast address
1346 * list or the network interface flags are updated. This routine is
1347 * responsible for configuring the hardware for proper multicast mode.
1348 **/
1349static void ixgbevf_set_rx_mode(struct net_device *netdev)
1350{
1351 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1352 struct ixgbe_hw *hw = &adapter->hw;
92915f71
GR		 1353
1354 /* reprogram multicast list */
92915f71 1355 if (hw->mac.ops.update_mc_addr_list)
5c58c47a 1356 hw->mac.ops.update_mc_addr_list(hw, netdev);
46ec20ff
GR		 1357
1358 ixgbevf_write_uc_addr_list(netdev);
92915f71
GR		 1359}
1360
1361static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter)
1362{
1363 int q_idx;
1364 struct ixgbevf_q_vector *q_vector;
1365 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1366
1367 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1368 struct napi_struct *napi;
1369 q_vector = adapter->q_vector[q_idx];
1370 if (!q_vector->rxr_count)
1371 continue;
1372 napi = &q_vector->napi;
1373 if (q_vector->rxr_count > 1)
1374 napi->poll = &ixgbevf_clean_rxonly_many;
1375
1376 napi_enable(napi);
1377 }
1378}
1379
1380static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter)
1381{
1382 int q_idx;
1383 struct ixgbevf_q_vector *q_vector;
1384 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1385
1386 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1387 q_vector = adapter->q_vector[q_idx];
1388 if (!q_vector->rxr_count)
1389 continue;
1390 napi_disable(&q_vector->napi);
1391 }
1392}
1393
1394static void ixgbevf_configure(struct ixgbevf_adapter *adapter)
1395{
1396 struct net_device *netdev = adapter->netdev;
1397 int i;
1398
1399 ixgbevf_set_rx_mode(netdev);
1400
1401 ixgbevf_restore_vlan(adapter);
1402
1403 ixgbevf_configure_tx(adapter);
1404 ixgbevf_configure_rx(adapter);
1405 for (i = 0; i < adapter->num_rx_queues; i++) {
1406 struct ixgbevf_ring *ring = &adapter->rx_ring[i];
1407 ixgbevf_alloc_rx_buffers(adapter, ring, ring->count);
1408 ring->next_to_use = ring->count - 1;
1409 writel(ring->next_to_use, adapter->hw.hw_addr + ring->tail);
1410 }
1411}
1412
1413#define IXGBE_MAX_RX_DESC_POLL 10
1414static inline void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter,
1415 int rxr)
1416{
1417 struct ixgbe_hw *hw = &adapter->hw;
1418 int j = adapter->rx_ring[rxr].reg_idx;
1419 int k;
1420
1421 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
1422 if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1423 break;
1424 else
1425 msleep(1);
1426 }
1427 if (k >= IXGBE_MAX_RX_DESC_POLL) {
1428 hw_dbg(hw, "RXDCTL.ENABLE on Rx queue %d "
1429 "not set within the polling period\n", rxr);
1430 }
1431
1432 ixgbevf_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
1433 (adapter->rx_ring[rxr].count - 1));
1434}
1435
33bd9f60
GR		 1436static void ixgbevf_save_reset_stats(struct ixgbevf_adapter *adapter)
1437{
1438 /* Only save pre-reset stats if there are some */
1439 if (adapter->stats.vfgprc || adapter->stats.vfgptc) {
1440 adapter->stats.saved_reset_vfgprc += adapter->stats.vfgprc -
1441 adapter->stats.base_vfgprc;
1442 adapter->stats.saved_reset_vfgptc += adapter->stats.vfgptc -
1443 adapter->stats.base_vfgptc;
1444 adapter->stats.saved_reset_vfgorc += adapter->stats.vfgorc -
1445 adapter->stats.base_vfgorc;
1446 adapter->stats.saved_reset_vfgotc += adapter->stats.vfgotc -
1447 adapter->stats.base_vfgotc;
1448 adapter->stats.saved_reset_vfmprc += adapter->stats.vfmprc -
1449 adapter->stats.base_vfmprc;
1450 }
1451}
1452
1453static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter)
1454{
1455 struct ixgbe_hw *hw = &adapter->hw;
1456
1457 adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC);
1458 adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB);
1459 adapter->stats.last_vfgorc |=
1460 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32);
1461 adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC);
1462 adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB);
1463 adapter->stats.last_vfgotc |=
1464 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32);
1465 adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC);
1466
1467 adapter->stats.base_vfgprc = adapter->stats.last_vfgprc;
1468 adapter->stats.base_vfgorc = adapter->stats.last_vfgorc;
1469 adapter->stats.base_vfgptc = adapter->stats.last_vfgptc;
1470 adapter->stats.base_vfgotc = adapter->stats.last_vfgotc;
1471 adapter->stats.base_vfmprc = adapter->stats.last_vfmprc;
1472}
1473
795180d8 1474static void ixgbevf_up_complete(struct ixgbevf_adapter *adapter)
92915f71
GR		 1475{
1476 struct net_device *netdev = adapter->netdev;
1477 struct ixgbe_hw *hw = &adapter->hw;
1478 int i, j = 0;
1479 int num_rx_rings = adapter->num_rx_queues;
1480 u32 txdctl, rxdctl;
795180d8 1481 u32 msg[2];
92915f71
GR		 1482
1483 for (i = 0; i < adapter->num_tx_queues; i++) {
1484 j = adapter->tx_ring[i].reg_idx;
1485 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1486 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1487 txdctl |= (8 << 16);
1488 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1489 }
1490
1491 for (i = 0; i < adapter->num_tx_queues; i++) {
1492 j = adapter->tx_ring[i].reg_idx;
1493 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1494 txdctl |= IXGBE_TXDCTL_ENABLE;
1495 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1496 }
1497
1498 for (i = 0; i < num_rx_rings; i++) {
1499 j = adapter->rx_ring[i].reg_idx;
1500 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j));
dadcd65f 1501 rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME;
69bfbec4
GR		 1502 if (hw->mac.type == ixgbe_mac_X540_vf) {
1503 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
1504 rxdctl |= ((netdev->mtu + ETH_HLEN + ETH_FCS_LEN) |
1505 IXGBE_RXDCTL_RLPML_EN);
1506 }
92915f71
GR		 1507 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(j), rxdctl);
1508 ixgbevf_rx_desc_queue_enable(adapter, i);
1509 }
1510
1511 ixgbevf_configure_msix(adapter);
1512
1513 if (hw->mac.ops.set_rar) {
1514 if (is_valid_ether_addr(hw->mac.addr))
1515 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
1516 else
1517 hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0);
1518 }
1519
795180d8
GR		 1520 msg[0] = IXGBE_VF_SET_LPE;
1521 msg[1] = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1522 hw->mbx.ops.write_posted(hw, msg, 2);
1523
92915f71
GR		 1524 clear_bit(__IXGBEVF_DOWN, &adapter->state);
1525 ixgbevf_napi_enable_all(adapter);
1526
1527 /* enable transmits */
1528 netif_tx_start_all_queues(netdev);
1529
33bd9f60
GR		 1530 ixgbevf_save_reset_stats(adapter);
1531 ixgbevf_init_last_counter_stats(adapter);
1532
92915f71 1533 mod_timer(&adapter->watchdog_timer, jiffies);
92915f71
GR		 1534}
1535
795180d8 1536void ixgbevf_up(struct ixgbevf_adapter *adapter)
92915f71 1537{
92915f71
GR		 1538 struct ixgbe_hw *hw = &adapter->hw;
1539
1540 ixgbevf_configure(adapter);
1541
795180d8 1542 ixgbevf_up_complete(adapter);
92915f71
GR		 1543
1544 /* clear any pending interrupts, may auto mask */
1545 IXGBE_READ_REG(hw, IXGBE_VTEICR);
1546
1547 ixgbevf_irq_enable(adapter, true, true);
92915f71
GR		 1548}
1549
1550/**
1551 * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue
1552 * @adapter: board private structure
1553 * @rx_ring: ring to free buffers from
1554 **/
1555static void ixgbevf_clean_rx_ring(struct ixgbevf_adapter *adapter,
1556 struct ixgbevf_ring *rx_ring)
1557{
1558 struct pci_dev *pdev = adapter->pdev;
1559 unsigned long size;
1560 unsigned int i;
1561
c0456c23
GR		 1562 if (!rx_ring->rx_buffer_info)
1563 return;
92915f71 1564
c0456c23 1565 /* Free all the Rx ring sk_buffs */
92915f71
GR		 1566 for (i = 0; i < rx_ring->count; i++) {
1567 struct ixgbevf_rx_buffer *rx_buffer_info;
1568
1569 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1570 if (rx_buffer_info->dma) {
2a1f8794 1571 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
92915f71 1572 rx_ring->rx_buf_len,
2a1f8794 1573 DMA_FROM_DEVICE);
92915f71
GR		 1574 rx_buffer_info->dma = 0;
1575 }
1576 if (rx_buffer_info->skb) {
1577 struct sk_buff *skb = rx_buffer_info->skb;
1578 rx_buffer_info->skb = NULL;
1579 do {
1580 struct sk_buff *this = skb;
1581 skb = skb->prev;
1582 dev_kfree_skb(this);
1583 } while (skb);
1584 }
92915f71
GR		 1585 }
1586
1587 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
1588 memset(rx_ring->rx_buffer_info, 0, size);
1589
1590 /* Zero out the descriptor ring */
1591 memset(rx_ring->desc, 0, rx_ring->size);
1592
1593 rx_ring->next_to_clean = 0;
1594 rx_ring->next_to_use = 0;
1595
1596 if (rx_ring->head)
1597 writel(0, adapter->hw.hw_addr + rx_ring->head);
1598 if (rx_ring->tail)
1599 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1600}
1601
1602/**
1603 * ixgbevf_clean_tx_ring - Free Tx Buffers
1604 * @adapter: board private structure
1605 * @tx_ring: ring to be cleaned
1606 **/
1607static void ixgbevf_clean_tx_ring(struct ixgbevf_adapter *adapter,
1608 struct ixgbevf_ring *tx_ring)
1609{
1610 struct ixgbevf_tx_buffer *tx_buffer_info;
1611 unsigned long size;
1612 unsigned int i;
1613
c0456c23
GR		 1614 if (!tx_ring->tx_buffer_info)
1615 return;
1616
92915f71
GR		 1617 /* Free all the Tx ring sk_buffs */
1618
1619 for (i = 0; i < tx_ring->count; i++) {
1620 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1621 ixgbevf_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1622 }
1623
1624 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
1625 memset(tx_ring->tx_buffer_info, 0, size);
1626
1627 memset(tx_ring->desc, 0, tx_ring->size);
1628
1629 tx_ring->next_to_use = 0;
1630 tx_ring->next_to_clean = 0;
1631
1632 if (tx_ring->head)
1633 writel(0, adapter->hw.hw_addr + tx_ring->head);
1634 if (tx_ring->tail)
1635 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1636}
1637
1638/**
1639 * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues
1640 * @adapter: board private structure
1641 **/
1642static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter)
1643{
1644 int i;
1645
1646 for (i = 0; i < adapter->num_rx_queues; i++)
1647 ixgbevf_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1648}
1649
1650/**
1651 * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues
1652 * @adapter: board private structure
1653 **/
1654static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter)
1655{
1656 int i;
1657
1658 for (i = 0; i < adapter->num_tx_queues; i++)
1659 ixgbevf_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1660}
1661
1662void ixgbevf_down(struct ixgbevf_adapter *adapter)
1663{
1664 struct net_device *netdev = adapter->netdev;
1665 struct ixgbe_hw *hw = &adapter->hw;
1666 u32 txdctl;
1667 int i, j;
1668
1669 /* signal that we are down to the interrupt handler */
1670 set_bit(__IXGBEVF_DOWN, &adapter->state);
1671 /* disable receives */
1672
1673 netif_tx_disable(netdev);
1674
1675 msleep(10);
1676
1677 netif_tx_stop_all_queues(netdev);
1678
1679 ixgbevf_irq_disable(adapter);
1680
1681 ixgbevf_napi_disable_all(adapter);
1682
1683 del_timer_sync(&adapter->watchdog_timer);
1684 /* can't call flush scheduled work here because it can deadlock
1685 * if linkwatch_event tries to acquire the rtnl_lock which we are
1686 * holding */
1687 while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK)
1688 msleep(1);
1689
1690 /* disable transmits in the hardware now that interrupts are off */
1691 for (i = 0; i < adapter->num_tx_queues; i++) {
1692 j = adapter->tx_ring[i].reg_idx;
1693 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1694 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j),
1695 (txdctl & ~IXGBE_TXDCTL_ENABLE));
1696 }
1697
1698 netif_carrier_off(netdev);
1699
1700 if (!pci_channel_offline(adapter->pdev))
1701 ixgbevf_reset(adapter);
1702
1703 ixgbevf_clean_all_tx_rings(adapter);
1704 ixgbevf_clean_all_rx_rings(adapter);
1705}
1706
1707void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter)
1708{
c0456c23
GR		 1709 struct ixgbe_hw *hw = &adapter->hw;
1710
92915f71 1711 WARN_ON(in_interrupt());
c0456c23 1712
92915f71
GR		 1713 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
1714 msleep(1);
1715
c0456c23
GR		 1716 /*
1717 * Check if PF is up before re-init. If not then skip until
1718 * later when the PF is up and ready to service requests from
1719 * the VF via mailbox. If the VF is up and running then the
1720 * watchdog task will continue to schedule reset tasks until
1721 * the PF is up and running.
1722 */
1723 if (!hw->mac.ops.reset_hw(hw)) {
1724 ixgbevf_down(adapter);
1725 ixgbevf_up(adapter);
1726 }
92915f71
GR		 1727
1728 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
1729}
1730
1731void ixgbevf_reset(struct ixgbevf_adapter *adapter)
1732{
1733 struct ixgbe_hw *hw = &adapter->hw;
1734 struct net_device *netdev = adapter->netdev;
1735
1736 if (hw->mac.ops.reset_hw(hw))
1737 hw_dbg(hw, "PF still resetting\n");
1738 else
1739 hw->mac.ops.init_hw(hw);
1740
1741 if (is_valid_ether_addr(adapter->hw.mac.addr)) {
1742 memcpy(netdev->dev_addr, adapter->hw.mac.addr,
1743 netdev->addr_len);
1744 memcpy(netdev->perm_addr, adapter->hw.mac.addr,
1745 netdev->addr_len);
1746 }
1747}
1748
1749static void ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter,
1750 int vectors)
1751{
1752 int err, vector_threshold;
1753
1754 /* We'll want at least 3 (vector_threshold):
1755 * 1) TxQ[0] Cleanup
1756 * 2) RxQ[0] Cleanup
1757 * 3) Other (Link Status Change, etc.)
1758 */
1759 vector_threshold = MIN_MSIX_COUNT;
1760
1761 /* The more we get, the more we will assign to Tx/Rx Cleanup
1762 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1763 * Right now, we simply care about how many we'll get; we'll
1764 * set them up later while requesting irq's.
1765 */
1766 while (vectors >= vector_threshold) {
1767 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1768 vectors);
1769 if (!err) /* Success in acquiring all requested vectors. */
1770 break;
1771 else if (err < 0)
1772 vectors = 0; /* Nasty failure, quit now */
1773 else /* err == number of vectors we should try again with */
1774 vectors = err;
1775 }
1776
1777 if (vectors < vector_threshold) {
1778 /* Can't allocate enough MSI-X interrupts? Oh well.
1779 * This just means we'll go with either a single MSI
1780 * vector or fall back to legacy interrupts.
1781 */
1782 hw_dbg(&adapter->hw,
1783 "Unable to allocate MSI-X interrupts\n");
1784 kfree(adapter->msix_entries);
1785 adapter->msix_entries = NULL;
1786 } else {
1787 /*
1788 * Adjust for only the vectors we'll use, which is minimum
1789 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
1790 * vectors we were allocated.
1791 */
1792 adapter->num_msix_vectors = vectors;
1793 }
1794}
1795
49ce9c2c
BH		 1796/**
1797 * ixgbevf_set_num_queues - Allocate queues for device, feature dependent
92915f71
GR		 1798 * @adapter: board private structure to initialize
1799 *
1800 * This is the top level queue allocation routine. The order here is very
1801 * important, starting with the "most" number of features turned on at once,
1802 * and ending with the smallest set of features. This way large combinations
1803 * can be allocated if they're turned on, and smaller combinations are the
1804 * fallthrough conditions.
1805 *
1806 **/
1807static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter)
1808{
1809 /* Start with base case */
1810 adapter->num_rx_queues = 1;
1811 adapter->num_tx_queues = 1;
92915f71
GR		 1812}
1813
1814/**
1815 * ixgbevf_alloc_queues - Allocate memory for all rings
1816 * @adapter: board private structure to initialize
1817 *
1818 * We allocate one ring per queue at run-time since we don't know the
1819 * number of queues at compile-time. The polling_netdev array is
1820 * intended for Multiqueue, but should work fine with a single queue.
1821 **/
1822static int ixgbevf_alloc_queues(struct ixgbevf_adapter *adapter)
1823{
1824 int i;
1825
1826 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1827 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1828 if (!adapter->tx_ring)
1829 goto err_tx_ring_allocation;
1830
1831 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1832 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1833 if (!adapter->rx_ring)
1834 goto err_rx_ring_allocation;
1835
1836 for (i = 0; i < adapter->num_tx_queues; i++) {
1837 adapter->tx_ring[i].count = adapter->tx_ring_count;
1838 adapter->tx_ring[i].queue_index = i;
1839 adapter->tx_ring[i].reg_idx = i;
1840 }
1841
1842 for (i = 0; i < adapter->num_rx_queues; i++) {
1843 adapter->rx_ring[i].count = adapter->rx_ring_count;
1844 adapter->rx_ring[i].queue_index = i;
1845 adapter->rx_ring[i].reg_idx = i;
1846 }
1847
1848 return 0;
1849
1850err_rx_ring_allocation:
1851 kfree(adapter->tx_ring);
1852err_tx_ring_allocation:
1853 return -ENOMEM;
1854}
1855
1856/**
1857 * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported
1858 * @adapter: board private structure to initialize
1859 *
1860 * Attempt to configure the interrupts using the best available
1861 * capabilities of the hardware and the kernel.
1862 **/
1863static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter)
1864{
1865 int err = 0;
1866 int vector, v_budget;
1867
1868 /*
1869 * It's easy to be greedy for MSI-X vectors, but it really
1870 * doesn't do us much good if we have a lot more vectors
1871 * than CPU's. So let's be conservative and only ask for
1872 * (roughly) twice the number of vectors as there are CPU's.
1873 */
1874 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
1875 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
1876
1877 /* A failure in MSI-X entry allocation isn't fatal, but it does
1878 * mean we disable MSI-X capabilities of the adapter. */
1879 adapter->msix_entries = kcalloc(v_budget,
1880 sizeof(struct msix_entry), GFP_KERNEL);
1881 if (!adapter->msix_entries) {
1882 err = -ENOMEM;
1883 goto out;
1884 }
1885
1886 for (vector = 0; vector < v_budget; vector++)
1887 adapter->msix_entries[vector].entry = vector;
1888
1889 ixgbevf_acquire_msix_vectors(adapter, v_budget);
1890
1891out:
1892 return err;
1893}
1894
1895/**
1896 * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors
1897 * @adapter: board private structure to initialize
1898 *
1899 * We allocate one q_vector per queue interrupt. If allocation fails we
1900 * return -ENOMEM.
1901 **/
1902static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter)
1903{
1904 int q_idx, num_q_vectors;
1905 struct ixgbevf_q_vector *q_vector;
1906 int napi_vectors;
1907 int (*poll)(struct napi_struct *, int);
1908
1909 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1910 napi_vectors = adapter->num_rx_queues;
1911 poll = &ixgbevf_clean_rxonly;
1912
1913 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1914 q_vector = kzalloc(sizeof(struct ixgbevf_q_vector), GFP_KERNEL);
1915 if (!q_vector)
1916 goto err_out;
1917 q_vector->adapter = adapter;
1918 q_vector->v_idx = q_idx;
1919 q_vector->eitr = adapter->eitr_param;
1920 if (q_idx < napi_vectors)
1921 netif_napi_add(adapter->netdev, &q_vector->napi,
1922 (*poll), 64);
1923 adapter->q_vector[q_idx] = q_vector;
1924 }
1925
1926 return 0;
1927
1928err_out:
1929 while (q_idx) {
1930 q_idx--;
1931 q_vector = adapter->q_vector[q_idx];
1932 netif_napi_del(&q_vector->napi);
1933 kfree(q_vector);
1934 adapter->q_vector[q_idx] = NULL;
1935 }
1936 return -ENOMEM;
1937}
1938
1939/**
1940 * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors
1941 * @adapter: board private structure to initialize
1942 *
1943 * This function frees the memory allocated to the q_vectors. In addition if
1944 * NAPI is enabled it will delete any references to the NAPI struct prior
1945 * to freeing the q_vector.
1946 **/
1947static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter)
1948{
1949 int q_idx, num_q_vectors;
1950 int napi_vectors;
1951
1952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1953 napi_vectors = adapter->num_rx_queues;
1954
1955 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1956 struct ixgbevf_q_vector *q_vector = adapter->q_vector[q_idx];
1957
1958 adapter->q_vector[q_idx] = NULL;
1959 if (q_idx < napi_vectors)
1960 netif_napi_del(&q_vector->napi);
1961 kfree(q_vector);
1962 }
1963}
1964
1965/**
1966 * ixgbevf_reset_interrupt_capability - Reset MSIX setup
1967 * @adapter: board private structure
1968 *
1969 **/
1970static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter)
1971{
1972 pci_disable_msix(adapter->pdev);
1973 kfree(adapter->msix_entries);
1974 adapter->msix_entries = NULL;
92915f71
GR		 1975}
1976
1977/**
1978 * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init
1979 * @adapter: board private structure to initialize
1980 *
1981 **/
1982static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter)
1983{
1984 int err;
1985
1986 /* Number of supported queues */
1987 ixgbevf_set_num_queues(adapter);
1988
1989 err = ixgbevf_set_interrupt_capability(adapter);
1990 if (err) {
1991 hw_dbg(&adapter->hw,
1992 "Unable to setup interrupt capabilities\n");
1993 goto err_set_interrupt;
1994 }
1995
1996 err = ixgbevf_alloc_q_vectors(adapter);
1997 if (err) {
1998 hw_dbg(&adapter->hw, "Unable to allocate memory for queue "
1999 "vectors\n");
2000 goto err_alloc_q_vectors;
2001 }
2002
2003 err = ixgbevf_alloc_queues(adapter);
2004 if (err) {
dbd9636e 2005 pr_err("Unable to allocate memory for queues\n");
92915f71
GR		 2006 goto err_alloc_queues;
2007 }
2008
2009 hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, "
2010 "Tx Queue count = %u\n",
2011 (adapter->num_rx_queues > 1) ? "Enabled" :
2012 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2013
2014 set_bit(__IXGBEVF_DOWN, &adapter->state);
2015
2016 return 0;
2017err_alloc_queues:
2018 ixgbevf_free_q_vectors(adapter);
2019err_alloc_q_vectors:
2020 ixgbevf_reset_interrupt_capability(adapter);
2021err_set_interrupt:
2022 return err;
2023}
2024
2025/**
2026 * ixgbevf_sw_init - Initialize general software structures
2027 * (struct ixgbevf_adapter)
2028 * @adapter: board private structure to initialize
2029 *
2030 * ixgbevf_sw_init initializes the Adapter private data structure.
2031 * Fields are initialized based on PCI device information and
2032 * OS network device settings (MTU size).
2033 **/
2034static int __devinit ixgbevf_sw_init(struct ixgbevf_adapter *adapter)
2035{
2036 struct ixgbe_hw *hw = &adapter->hw;
2037 struct pci_dev *pdev = adapter->pdev;
2038 int err;
2039
2040 /* PCI config space info */
2041
2042 hw->vendor_id = pdev->vendor;
2043 hw->device_id = pdev->device;
ff938e43 2044 hw->revision_id = pdev->revision;
92915f71
GR		 2045 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2046 hw->subsystem_device_id = pdev->subsystem_device;
2047
2048 hw->mbx.ops.init_params(hw);
2049 hw->mac.max_tx_queues = MAX_TX_QUEUES;
2050 hw->mac.max_rx_queues = MAX_RX_QUEUES;
2051 err = hw->mac.ops.reset_hw(hw);
2052 if (err) {
2053 dev_info(&pdev->dev,
2054 "PF still in reset state, assigning new address\n");
1a0d6ae5
DK		 2055 eth_hw_addr_random(adapter->netdev);
2056 memcpy(adapter->hw.mac.addr, adapter->netdev->dev_addr,
2057 adapter->netdev->addr_len);
92915f71
GR		 2058 } else {
2059 err = hw->mac.ops.init_hw(hw);
2060 if (err) {
dbd9636e 2061 pr_err("init_shared_code failed: %d\n", err);
92915f71
GR		 2062 goto out;
2063 }
1a0d6ae5
DK		 2064 memcpy(adapter->netdev->dev_addr, adapter->hw.mac.addr,
2065 adapter->netdev->addr_len);
92915f71
GR		 2066 }
2067
2068 /* Enable dynamic interrupt throttling rates */
2069 adapter->eitr_param = 20000;
2070 adapter->itr_setting = 1;
2071
92915f71
GR		 2072 /* set default ring sizes */
2073 adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD;
2074 adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD;
2075
92915f71 2076 set_bit(__IXGBEVF_DOWN, &adapter->state);
1a0d6ae5 2077 return 0;
92915f71
GR		 2078
2079out:
2080 return err;
2081}
2082
92915f71
GR		 2083#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
2084 { \
2085 u32 current_counter = IXGBE_READ_REG(hw, reg); \
2086 if (current_counter < last_counter) \
2087 counter += 0x100000000LL; \
2088 last_counter = current_counter; \
2089 counter &= 0xFFFFFFFF00000000LL; \
2090 counter |= current_counter; \
2091 }
2092
2093#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2094 { \
2095 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
2096 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
2097 u64 current_counter = (current_counter_msb << 32) | \
2098 current_counter_lsb; \
2099 if (current_counter < last_counter) \
2100 counter += 0x1000000000LL; \
2101 last_counter = current_counter; \
2102 counter &= 0xFFFFFFF000000000LL; \
2103 counter |= current_counter; \
2104 }
2105/**
2106 * ixgbevf_update_stats - Update the board statistics counters.
2107 * @adapter: board private structure
2108 **/
2109void ixgbevf_update_stats(struct ixgbevf_adapter *adapter)
2110{
2111 struct ixgbe_hw *hw = &adapter->hw;
2112
2113 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc,
2114 adapter->stats.vfgprc);
2115 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc,
2116 adapter->stats.vfgptc);
2117 UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2118 adapter->stats.last_vfgorc,
2119 adapter->stats.vfgorc);
2120 UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2121 adapter->stats.last_vfgotc,
2122 adapter->stats.vfgotc);
2123 UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc,
2124 adapter->stats.vfmprc);
92915f71
GR		 2125}
2126
2127/**
2128 * ixgbevf_watchdog - Timer Call-back
2129 * @data: pointer to adapter cast into an unsigned long
2130 **/
2131static void ixgbevf_watchdog(unsigned long data)
2132{
2133 struct ixgbevf_adapter *adapter = (struct ixgbevf_adapter *)data;
2134 struct ixgbe_hw *hw = &adapter->hw;
2135 u64 eics = 0;
2136 int i;
2137
2138 /*
2139 * Do the watchdog outside of interrupt context due to the lovely
2140 * delays that some of the newer hardware requires
2141 */
2142
2143 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
2144 goto watchdog_short_circuit;
2145
2146 /* get one bit for every active tx/rx interrupt vector */
2147 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
2148 struct ixgbevf_q_vector *qv = adapter->q_vector[i];
2149 if (qv->rxr_count || qv->txr_count)
2150 eics |= (1 << i);
2151 }
2152
2153 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, (u32)eics);
2154
2155watchdog_short_circuit:
2156 schedule_work(&adapter->watchdog_task);
2157}
2158
2159/**
2160 * ixgbevf_tx_timeout - Respond to a Tx Hang
2161 * @netdev: network interface device structure
2162 **/
2163static void ixgbevf_tx_timeout(struct net_device *netdev)
2164{
2165 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2166
2167 /* Do the reset outside of interrupt context */
2168 schedule_work(&adapter->reset_task);
2169}
2170
2171static void ixgbevf_reset_task(struct work_struct *work)
2172{
2173 struct ixgbevf_adapter *adapter;
2174 adapter = container_of(work, struct ixgbevf_adapter, reset_task);
2175
2176 /* If we're already down or resetting, just bail */
2177 if (test_bit(__IXGBEVF_DOWN, &adapter->state) ||
2178 test_bit(__IXGBEVF_RESETTING, &adapter->state))
2179 return;
2180
2181 adapter->tx_timeout_count++;
2182
2183 ixgbevf_reinit_locked(adapter);
2184}
2185
2186/**
2187 * ixgbevf_watchdog_task - worker thread to bring link up
2188 * @work: pointer to work_struct containing our data
2189 **/
2190static void ixgbevf_watchdog_task(struct work_struct *work)
2191{
2192 struct ixgbevf_adapter *adapter = container_of(work,
2193 struct ixgbevf_adapter,
2194 watchdog_task);
2195 struct net_device *netdev = adapter->netdev;
2196 struct ixgbe_hw *hw = &adapter->hw;
2197 u32 link_speed = adapter->link_speed;
2198 bool link_up = adapter->link_up;
2199
2200 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
2201
2202 /*
2203 * Always check the link on the watchdog because we have
2204 * no LSC interrupt
2205 */
2206 if (hw->mac.ops.check_link) {
2207 if ((hw->mac.ops.check_link(hw, &link_speed,
2208 &link_up, false)) != 0) {
2209 adapter->link_up = link_up;
2210 adapter->link_speed = link_speed;
da6b3330
GR		 2211 netif_carrier_off(netdev);
2212 netif_tx_stop_all_queues(netdev);
92915f71
GR		 2213 schedule_work(&adapter->reset_task);
2214 goto pf_has_reset;
2215 }
2216 } else {
2217 /* always assume link is up, if no check link
2218 * function */
2219 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
2220 link_up = true;
2221 }
2222 adapter->link_up = link_up;
2223 adapter->link_speed = link_speed;
2224
2225 if (link_up) {
2226 if (!netif_carrier_ok(netdev)) {
300bc060
JP		 2227 hw_dbg(&adapter->hw, "NIC Link is Up, %u Gbps\n",
2228 (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
2229 10 : 1);
92915f71
GR		 2230 netif_carrier_on(netdev);
2231 netif_tx_wake_all_queues(netdev);
92915f71
GR		 2232 }
2233 } else {
2234 adapter->link_up = false;
2235 adapter->link_speed = 0;
2236 if (netif_carrier_ok(netdev)) {
2237 hw_dbg(&adapter->hw, "NIC Link is Down\n");
2238 netif_carrier_off(netdev);
2239 netif_tx_stop_all_queues(netdev);
2240 }
2241 }
2242
92915f71
GR		 2243 ixgbevf_update_stats(adapter);
2244
33bd9f60 2245pf_has_reset:
92915f71
GR		 2246 /* Reset the timer */
2247 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
2248 mod_timer(&adapter->watchdog_timer,
2249 round_jiffies(jiffies + (2 * HZ)));
2250
2251 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
2252}
2253
2254/**
2255 * ixgbevf_free_tx_resources - Free Tx Resources per Queue
2256 * @adapter: board private structure
2257 * @tx_ring: Tx descriptor ring for a specific queue
2258 *
2259 * Free all transmit software resources
2260 **/
2261void ixgbevf_free_tx_resources(struct ixgbevf_adapter *adapter,
2262 struct ixgbevf_ring *tx_ring)
2263{
2264 struct pci_dev *pdev = adapter->pdev;
2265
92915f71
GR		 2266 ixgbevf_clean_tx_ring(adapter, tx_ring);
2267
2268 vfree(tx_ring->tx_buffer_info);
2269 tx_ring->tx_buffer_info = NULL;
2270
2a1f8794
NN		 2271 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2272 tx_ring->dma);
92915f71
GR		 2273
2274 tx_ring->desc = NULL;
2275}
2276
2277/**
2278 * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues
2279 * @adapter: board private structure
2280 *
2281 * Free all transmit software resources
2282 **/
2283static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter)
2284{
2285 int i;
2286
2287 for (i = 0; i < adapter->num_tx_queues; i++)
2288 if (adapter->tx_ring[i].desc)
2289 ixgbevf_free_tx_resources(adapter,
2290 &adapter->tx_ring[i]);
2291
2292}
2293
2294/**
2295 * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors)
2296 * @adapter: board private structure
2297 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2298 *
2299 * Return 0 on success, negative on failure
2300 **/
2301int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *adapter,
2302 struct ixgbevf_ring *tx_ring)
2303{
2304 struct pci_dev *pdev = adapter->pdev;
2305 int size;
2306
2307 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
89bf67f1 2308 tx_ring->tx_buffer_info = vzalloc(size);
92915f71
GR		 2309 if (!tx_ring->tx_buffer_info)
2310 goto err;
92915f71
GR		 2311
2312 /* round up to nearest 4K */
2313 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2314 tx_ring->size = ALIGN(tx_ring->size, 4096);
2315
2a1f8794
NN		 2316 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
2317 &tx_ring->dma, GFP_KERNEL);
92915f71
GR		 2318 if (!tx_ring->desc)
2319 goto err;
2320
2321 tx_ring->next_to_use = 0;
2322 tx_ring->next_to_clean = 0;
2323 tx_ring->work_limit = tx_ring->count;
2324 return 0;
2325
2326err:
2327 vfree(tx_ring->tx_buffer_info);
2328 tx_ring->tx_buffer_info = NULL;
2329 hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit "
2330 "descriptor ring\n");
2331 return -ENOMEM;
2332}
2333
2334/**
2335 * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources
2336 * @adapter: board private structure
2337 *
2338 * If this function returns with an error, then it's possible one or
2339 * more of the rings is populated (while the rest are not). It is the
2340 * callers duty to clean those orphaned rings.
2341 *
2342 * Return 0 on success, negative on failure
2343 **/
2344static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter)
2345{
2346 int i, err = 0;
2347
2348 for (i = 0; i < adapter->num_tx_queues; i++) {
2349 err = ixgbevf_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2350 if (!err)
2351 continue;
2352 hw_dbg(&adapter->hw,
2353 "Allocation for Tx Queue %u failed\n", i);
2354 break;
2355 }
2356
2357 return err;
2358}
2359
2360/**
2361 * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors)
2362 * @adapter: board private structure
2363 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2364 *
2365 * Returns 0 on success, negative on failure
2366 **/
2367int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
2368 struct ixgbevf_ring *rx_ring)
2369{
2370 struct pci_dev *pdev = adapter->pdev;
2371 int size;
2372
2373 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
89bf67f1 2374 rx_ring->rx_buffer_info = vzalloc(size);
e404decb 2375 if (!rx_ring->rx_buffer_info)
92915f71 2376 goto alloc_failed;
92915f71
GR		 2377
2378 /* Round up to nearest 4K */
2379 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2380 rx_ring->size = ALIGN(rx_ring->size, 4096);
2381
2a1f8794
NN		 2382 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
2383 &rx_ring->dma, GFP_KERNEL);
92915f71
GR		 2384
2385 if (!rx_ring->desc) {
2386 hw_dbg(&adapter->hw,
2387 "Unable to allocate memory for "
2388 "the receive descriptor ring\n");
2389 vfree(rx_ring->rx_buffer_info);
2390 rx_ring->rx_buffer_info = NULL;
2391 goto alloc_failed;
2392 }
2393
2394 rx_ring->next_to_clean = 0;
2395 rx_ring->next_to_use = 0;
2396
2397 return 0;
2398alloc_failed:
2399 return -ENOMEM;
2400}
2401
2402/**
2403 * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources
2404 * @adapter: board private structure
2405 *
2406 * If this function returns with an error, then it's possible one or
2407 * more of the rings is populated (while the rest are not). It is the
2408 * callers duty to clean those orphaned rings.
2409 *
2410 * Return 0 on success, negative on failure
2411 **/
2412static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter)
2413{
2414 int i, err = 0;
2415
2416 for (i = 0; i < adapter->num_rx_queues; i++) {
2417 err = ixgbevf_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2418 if (!err)
2419 continue;
2420 hw_dbg(&adapter->hw,
2421 "Allocation for Rx Queue %u failed\n", i);
2422 break;
2423 }
2424 return err;
2425}
2426
2427/**
2428 * ixgbevf_free_rx_resources - Free Rx Resources
2429 * @adapter: board private structure
2430 * @rx_ring: ring to clean the resources from
2431 *
2432 * Free all receive software resources
2433 **/
2434void ixgbevf_free_rx_resources(struct ixgbevf_adapter *adapter,
2435 struct ixgbevf_ring *rx_ring)
2436{
2437 struct pci_dev *pdev = adapter->pdev;
2438
2439 ixgbevf_clean_rx_ring(adapter, rx_ring);
2440
2441 vfree(rx_ring->rx_buffer_info);
2442 rx_ring->rx_buffer_info = NULL;
2443
2a1f8794
NN		 2444 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2445 rx_ring->dma);
92915f71
GR		 2446
2447 rx_ring->desc = NULL;
2448}
2449
2450/**
2451 * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues
2452 * @adapter: board private structure
2453 *
2454 * Free all receive software resources
2455 **/
2456static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter)
2457{
2458 int i;
2459
2460 for (i = 0; i < adapter->num_rx_queues; i++)
2461 if (adapter->rx_ring[i].desc)
2462 ixgbevf_free_rx_resources(adapter,
2463 &adapter->rx_ring[i]);
2464}
2465
2466/**
2467 * ixgbevf_open - Called when a network interface is made active
2468 * @netdev: network interface device structure
2469 *
2470 * Returns 0 on success, negative value on failure
2471 *
2472 * The open entry point is called when a network interface is made
2473 * active by the system (IFF_UP). At this point all resources needed
2474 * for transmit and receive operations are allocated, the interrupt
2475 * handler is registered with the OS, the watchdog timer is started,
2476 * and the stack is notified that the interface is ready.
2477 **/
2478static int ixgbevf_open(struct net_device *netdev)
2479{
2480 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
2482 int err;
2483
2484 /* disallow open during test */
2485 if (test_bit(__IXGBEVF_TESTING, &adapter->state))
2486 return -EBUSY;
2487
2488 if (hw->adapter_stopped) {
2489 ixgbevf_reset(adapter);
2490 /* if adapter is still stopped then PF isn't up and
2491 * the vf can't start. */
2492 if (hw->adapter_stopped) {
2493 err = IXGBE_ERR_MBX;
dbd9636e
JK		 2494 pr_err("Unable to start - perhaps the PF Driver isn't "
2495 "up yet\n");
92915f71
GR		 2496 goto err_setup_reset;
2497 }
2498 }
2499
2500 /* allocate transmit descriptors */
2501 err = ixgbevf_setup_all_tx_resources(adapter);
2502 if (err)
2503 goto err_setup_tx;
2504
2505 /* allocate receive descriptors */
2506 err = ixgbevf_setup_all_rx_resources(adapter);
2507 if (err)
2508 goto err_setup_rx;
2509
2510 ixgbevf_configure(adapter);
2511
2512 /*
2513 * Map the Tx/Rx rings to the vectors we were allotted.
2514 * if request_irq will be called in this function map_rings
2515 * must be called *before* up_complete
2516 */
2517 ixgbevf_map_rings_to_vectors(adapter);
2518
795180d8 2519 ixgbevf_up_complete(adapter);
92915f71
GR		 2520
2521 /* clear any pending interrupts, may auto mask */
2522 IXGBE_READ_REG(hw, IXGBE_VTEICR);
2523 err = ixgbevf_request_irq(adapter);
2524 if (err)
2525 goto err_req_irq;
2526
2527 ixgbevf_irq_enable(adapter, true, true);
2528
2529 return 0;
2530
2531err_req_irq:
2532 ixgbevf_down(adapter);
92915f71
GR		 2533 ixgbevf_free_irq(adapter);
2534err_setup_rx:
2535 ixgbevf_free_all_rx_resources(adapter);
2536err_setup_tx:
2537 ixgbevf_free_all_tx_resources(adapter);
2538 ixgbevf_reset(adapter);
2539
2540err_setup_reset:
2541
2542 return err;
2543}
2544
2545/**
2546 * ixgbevf_close - Disables a network interface
2547 * @netdev: network interface device structure
2548 *
2549 * Returns 0, this is not allowed to fail
2550 *
2551 * The close entry point is called when an interface is de-activated
2552 * by the OS. The hardware is still under the drivers control, but
2553 * needs to be disabled. A global MAC reset is issued to stop the
2554 * hardware, and all transmit and receive resources are freed.
2555 **/
2556static int ixgbevf_close(struct net_device *netdev)
2557{
2558 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2559
2560 ixgbevf_down(adapter);
2561 ixgbevf_free_irq(adapter);
2562
2563 ixgbevf_free_all_tx_resources(adapter);
2564 ixgbevf_free_all_rx_resources(adapter);
2565
2566 return 0;
2567}
2568
2569static int ixgbevf_tso(struct ixgbevf_adapter *adapter,
2570 struct ixgbevf_ring *tx_ring,
2571 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2572{
2573 struct ixgbe_adv_tx_context_desc *context_desc;
2574 unsigned int i;
2575 int err;
2576 struct ixgbevf_tx_buffer *tx_buffer_info;
2577 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
2578 u32 mss_l4len_idx, l4len;
2579
2580 if (skb_is_gso(skb)) {
2581 if (skb_header_cloned(skb)) {
2582 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2583 if (err)
2584 return err;
2585 }
2586 l4len = tcp_hdrlen(skb);
2587 *hdr_len += l4len;
2588
2589 if (skb->protocol == htons(ETH_P_IP)) {
2590 struct iphdr *iph = ip_hdr(skb);
2591 iph->tot_len = 0;
2592 iph->check = 0;
2593 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2594 iph->daddr, 0,
2595 IPPROTO_TCP,
2596 0);
2597 adapter->hw_tso_ctxt++;
9010bc33 2598 } else if (skb_is_gso_v6(skb)) {
92915f71
GR		 2599 ipv6_hdr(skb)->payload_len = 0;
2600 tcp_hdr(skb)->check =
2601 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2602 &ipv6_hdr(skb)->daddr,
2603 0, IPPROTO_TCP, 0);
2604 adapter->hw_tso6_ctxt++;
2605 }
2606
2607 i = tx_ring->next_to_use;
2608
2609 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2610 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2611
2612 /* VLAN MACLEN IPLEN */
2613 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2614 vlan_macip_lens |=
2615 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2616 vlan_macip_lens |= ((skb_network_offset(skb)) <<
2617 IXGBE_ADVTXD_MACLEN_SHIFT);
2618 *hdr_len += skb_network_offset(skb);
2619 vlan_macip_lens |=
2620 (skb_transport_header(skb) - skb_network_header(skb));
2621 *hdr_len +=
2622 (skb_transport_header(skb) - skb_network_header(skb));
2623 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2624 context_desc->seqnum_seed = 0;
2625
2626 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2627 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
2628 IXGBE_ADVTXD_DTYP_CTXT);
2629
2630 if (skb->protocol == htons(ETH_P_IP))
2631 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2632 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2633 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2634
2635 /* MSS L4LEN IDX */
2636 mss_l4len_idx =
2637 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
2638 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
2639 /* use index 1 for TSO */
2640 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
2641 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2642
2643 tx_buffer_info->time_stamp = jiffies;
2644 tx_buffer_info->next_to_watch = i;
2645
2646 i++;
2647 if (i == tx_ring->count)
2648 i = 0;
2649 tx_ring->next_to_use = i;
2650
2651 return true;
2652 }
2653
2654 return false;
2655}
2656
2657static bool ixgbevf_tx_csum(struct ixgbevf_adapter *adapter,
2658 struct ixgbevf_ring *tx_ring,
2659 struct sk_buff *skb, u32 tx_flags)
2660{
2661 struct ixgbe_adv_tx_context_desc *context_desc;
2662 unsigned int i;
2663 struct ixgbevf_tx_buffer *tx_buffer_info;
2664 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2665
2666 if (skb->ip_summed == CHECKSUM_PARTIAL ||
2667 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
2668 i = tx_ring->next_to_use;
2669 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2670 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2671
2672 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2673 vlan_macip_lens |= (tx_flags &
2674 IXGBE_TX_FLAGS_VLAN_MASK);
2675 vlan_macip_lens |= (skb_network_offset(skb) <<
2676 IXGBE_ADVTXD_MACLEN_SHIFT);
2677 if (skb->ip_summed == CHECKSUM_PARTIAL)
2678 vlan_macip_lens |= (skb_transport_header(skb) -
2679 skb_network_header(skb));
2680
2681 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2682 context_desc->seqnum_seed = 0;
2683
2684 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2685 IXGBE_ADVTXD_DTYP_CTXT);
2686
2687 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2688 switch (skb->protocol) {
2689 case __constant_htons(ETH_P_IP):
2690 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2691 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2692 type_tucmd_mlhl |=
2693 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2694 break;
2695 case __constant_htons(ETH_P_IPV6):
2696 /* XXX what about other V6 headers?? */
2697 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2698 type_tucmd_mlhl |=
2699 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2700 break;
2701 default:
2702 if (unlikely(net_ratelimit())) {
dbd9636e
JK		 2703 pr_warn("partial checksum but "
2704 "proto=%x!\n", skb->protocol);
92915f71
GR		 2705 }
2706 break;
2707 }
2708 }
2709
2710 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2711 /* use index zero for tx checksum offload */
2712 context_desc->mss_l4len_idx = 0;
2713
2714 tx_buffer_info->time_stamp = jiffies;
2715 tx_buffer_info->next_to_watch = i;
2716
2717 adapter->hw_csum_tx_good++;
2718 i++;
2719 if (i == tx_ring->count)
2720 i = 0;
2721 tx_ring->next_to_use = i;
2722
2723 return true;
2724 }
2725
2726 return false;
2727}
2728
2729static int ixgbevf_tx_map(struct ixgbevf_adapter *adapter,
2730 struct ixgbevf_ring *tx_ring,
2731 struct sk_buff *skb, u32 tx_flags,
2732 unsigned int first)
2733{
2734 struct pci_dev *pdev = adapter->pdev;
2735 struct ixgbevf_tx_buffer *tx_buffer_info;
2736 unsigned int len;
2737 unsigned int total = skb->len;
2540ddb5
KV		 2738 unsigned int offset = 0, size;
2739 int count = 0;
92915f71
GR		 2740 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2741 unsigned int f;
65deeed7 2742 int i;
92915f71
GR		 2743
2744 i = tx_ring->next_to_use;
2745
2746 len = min(skb_headlen(skb), total);
2747 while (len) {
2748 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2749 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2750
2751 tx_buffer_info->length = size;
2752 tx_buffer_info->mapped_as_page = false;
2a1f8794 2753 tx_buffer_info->dma = dma_map_single(&adapter->pdev->dev,
92915f71 2754 skb->data + offset,
2a1f8794
NN		 2755 size, DMA_TO_DEVICE);
2756 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
92915f71
GR		 2757 goto dma_error;
2758 tx_buffer_info->time_stamp = jiffies;
2759 tx_buffer_info->next_to_watch = i;
2760
2761 len -= size;
2762 total -= size;
2763 offset += size;
2764 count++;
2765 i++;
2766 if (i == tx_ring->count)
2767 i = 0;
2768 }
2769
2770 for (f = 0; f < nr_frags; f++) {
9e903e08 2771 const struct skb_frag_struct *frag;
92915f71
GR		 2772
2773 frag = &skb_shinfo(skb)->frags[f];
9e903e08 2774 len = min((unsigned int)skb_frag_size(frag), total);
877749bf 2775 offset = 0;
92915f71
GR		 2776
2777 while (len) {
2778 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2779 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2780
2781 tx_buffer_info->length = size;
877749bf
IC		 2782 tx_buffer_info->dma =
2783 skb_frag_dma_map(&adapter->pdev->dev, frag,
2784 offset, size, DMA_TO_DEVICE);
92915f71 2785 tx_buffer_info->mapped_as_page = true;
2a1f8794 2786 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
92915f71
GR		 2787 goto dma_error;
2788 tx_buffer_info->time_stamp = jiffies;
2789 tx_buffer_info->next_to_watch = i;
2790
2791 len -= size;
2792 total -= size;
2793 offset += size;
2794 count++;
2795 i++;
2796 if (i == tx_ring->count)
2797 i = 0;
2798 }
2799 if (total == 0)
2800 break;
2801 }
2802
2803 if (i == 0)
2804 i = tx_ring->count - 1;
2805 else
2806 i = i - 1;
2807 tx_ring->tx_buffer_info[i].skb = skb;
2808 tx_ring->tx_buffer_info[first].next_to_watch = i;
2809
2810 return count;
2811
2812dma_error:
2813 dev_err(&pdev->dev, "TX DMA map failed\n");
2814
2815 /* clear timestamp and dma mappings for failed tx_buffer_info map */
2816 tx_buffer_info->dma = 0;
2817 tx_buffer_info->time_stamp = 0;
2818 tx_buffer_info->next_to_watch = 0;
2819 count--;
2820
2821 /* clear timestamp and dma mappings for remaining portion of packet */
2822 while (count >= 0) {
2823 count--;
2824 i--;
2825 if (i < 0)
2826 i += tx_ring->count;
2827 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2828 ixgbevf_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2829 }
2830
2831 return count;
2832}
2833
2834static void ixgbevf_tx_queue(struct ixgbevf_adapter *adapter,
2835 struct ixgbevf_ring *tx_ring, int tx_flags,
2836 int count, u32 paylen, u8 hdr_len)
2837{
2838 union ixgbe_adv_tx_desc *tx_desc = NULL;
2839 struct ixgbevf_tx_buffer *tx_buffer_info;
2840 u32 olinfo_status = 0, cmd_type_len = 0;
2841 unsigned int i;
2842
2843 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
2844
2845 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
2846
2847 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
2848
2849 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2850 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
2851
2852 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
2853 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
2854
2855 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
2856 IXGBE_ADVTXD_POPTS_SHIFT;
2857
2858 /* use index 1 context for tso */
2859 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
2860 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
2861 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
2862 IXGBE_ADVTXD_POPTS_SHIFT;
2863
2864 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
2865 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
2866 IXGBE_ADVTXD_POPTS_SHIFT;
2867
2868 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
2869
2870 i = tx_ring->next_to_use;
2871 while (count--) {
2872 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2873 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
2874 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
2875 tx_desc->read.cmd_type_len =
2876 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
2877 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2878 i++;
2879 if (i == tx_ring->count)
2880 i = 0;
2881 }
2882
2883 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
2884
2885 /*
2886 * Force memory writes to complete before letting h/w
2887 * know there are new descriptors to fetch. (Only
2888 * applicable for weak-ordered memory model archs,
2889 * such as IA-64).
2890 */
2891 wmb();
2892
2893 tx_ring->next_to_use = i;
2894 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2895}
2896
2897static int __ixgbevf_maybe_stop_tx(struct net_device *netdev,
2898 struct ixgbevf_ring *tx_ring, int size)
2899{
2900 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2901
2902 netif_stop_subqueue(netdev, tx_ring->queue_index);
2903 /* Herbert's original patch had:
2904 * smp_mb__after_netif_stop_queue();
2905 * but since that doesn't exist yet, just open code it. */
2906 smp_mb();
2907
2908 /* We need to check again in a case another CPU has just
2909 * made room available. */
2910 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
2911 return -EBUSY;
2912
2913 /* A reprieve! - use start_queue because it doesn't call schedule */
2914 netif_start_subqueue(netdev, tx_ring->queue_index);
2915 ++adapter->restart_queue;
2916 return 0;
2917}
2918
2919static int ixgbevf_maybe_stop_tx(struct net_device *netdev,
2920 struct ixgbevf_ring *tx_ring, int size)
2921{
2922 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
2923 return 0;
2924 return __ixgbevf_maybe_stop_tx(netdev, tx_ring, size);
2925}
2926
2927static int ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2928{
2929 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2930 struct ixgbevf_ring *tx_ring;
2931 unsigned int first;
2932 unsigned int tx_flags = 0;
2933 u8 hdr_len = 0;
2934 int r_idx = 0, tso;
2935 int count = 0;
2936
2937 unsigned int f;
2938
2939 tx_ring = &adapter->tx_ring[r_idx];
2940
eab6d18d 2941 if (vlan_tx_tag_present(skb)) {
92915f71
GR		 2942 tx_flags |= vlan_tx_tag_get(skb);
2943 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
2944 tx_flags |= IXGBE_TX_FLAGS_VLAN;
2945 }
2946
2947 /* four things can cause us to need a context descriptor */
2948 if (skb_is_gso(skb) ||
2949 (skb->ip_summed == CHECKSUM_PARTIAL) ||
2950 (tx_flags & IXGBE_TX_FLAGS_VLAN))
2951 count++;
2952
2953 count += TXD_USE_COUNT(skb_headlen(skb));
2954 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9e903e08 2955 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]));
92915f71
GR		 2956
2957 if (ixgbevf_maybe_stop_tx(netdev, tx_ring, count)) {
2958 adapter->tx_busy++;
2959 return NETDEV_TX_BUSY;
2960 }
2961
2962 first = tx_ring->next_to_use;
2963
2964 if (skb->protocol == htons(ETH_P_IP))
2965 tx_flags |= IXGBE_TX_FLAGS_IPV4;
2966 tso = ixgbevf_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
2967 if (tso < 0) {
2968 dev_kfree_skb_any(skb);
2969 return NETDEV_TX_OK;
2970 }
2971
2972 if (tso)
2973 tx_flags |= IXGBE_TX_FLAGS_TSO;
2974 else if (ixgbevf_tx_csum(adapter, tx_ring, skb, tx_flags) &&
2975 (skb->ip_summed == CHECKSUM_PARTIAL))
2976 tx_flags |= IXGBE_TX_FLAGS_CSUM;
2977
2978 ixgbevf_tx_queue(adapter, tx_ring, tx_flags,
2979 ixgbevf_tx_map(adapter, tx_ring, skb, tx_flags, first),
2980 skb->len, hdr_len);
2981
92915f71
GR		 2982 ixgbevf_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
2983
2984 return NETDEV_TX_OK;
2985}
2986
92915f71
GR		 2987/**
2988 * ixgbevf_set_mac - Change the Ethernet Address of the NIC
2989 * @netdev: network interface device structure
2990 * @p: pointer to an address structure
2991 *
2992 * Returns 0 on success, negative on failure
2993 **/
2994static int ixgbevf_set_mac(struct net_device *netdev, void *p)
2995{
2996 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2997 struct ixgbe_hw *hw = &adapter->hw;
2998 struct sockaddr *addr = p;
2999
3000 if (!is_valid_ether_addr(addr->sa_data))
3001 return -EADDRNOTAVAIL;
3002
3003 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3004 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3005
3006 if (hw->mac.ops.set_rar)
3007 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
3008
3009 return 0;
3010}
3011
3012/**
3013 * ixgbevf_change_mtu - Change the Maximum Transfer Unit
3014 * @netdev: network interface device structure
3015 * @new_mtu: new value for maximum frame size
3016 *
3017 * Returns 0 on success, negative on failure
3018 **/
3019static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu)
3020{
3021 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
69bfbec4 3022 struct ixgbe_hw *hw = &adapter->hw;
92915f71 3023 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
69bfbec4
GR		 3024 int max_possible_frame = MAXIMUM_ETHERNET_VLAN_SIZE;
3025 u32 msg[2];
3026
3027 if (adapter->hw.mac.type == ixgbe_mac_X540_vf)
3028 max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE;
92915f71
GR		 3029
3030 /* MTU < 68 is an error and causes problems on some kernels */
69bfbec4 3031 if ((new_mtu < 68) || (max_frame > max_possible_frame))
92915f71
GR		 3032 return -EINVAL;
3033
3034 hw_dbg(&adapter->hw, "changing MTU from %d to %d\n",
3035 netdev->mtu, new_mtu);
3036 /* must set new MTU before calling down or up */
3037 netdev->mtu = new_mtu;
3038
795180d8
GR		 3039 if (!netif_running(netdev)) {
3040 msg[0] = IXGBE_VF_SET_LPE;
3041 msg[1] = max_frame;
3042 hw->mbx.ops.write_posted(hw, msg, 2);
3043 }
69bfbec4 3044
92915f71
GR		 3045 if (netif_running(netdev))
3046 ixgbevf_reinit_locked(adapter);
3047
3048 return 0;
3049}
3050
3051static void ixgbevf_shutdown(struct pci_dev *pdev)
3052{
3053 struct net_device *netdev = pci_get_drvdata(pdev);
3054 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3055
3056 netif_device_detach(netdev);
3057
3058 if (netif_running(netdev)) {
3059 ixgbevf_down(adapter);
3060 ixgbevf_free_irq(adapter);
3061 ixgbevf_free_all_tx_resources(adapter);
3062 ixgbevf_free_all_rx_resources(adapter);
3063 }
3064
92915f71 3065 pci_save_state(pdev);
92915f71
GR		 3066
3067 pci_disable_device(pdev);
3068}
3069
4197aa7b
ED		 3070static struct rtnl_link_stats64 *ixgbevf_get_stats(struct net_device *netdev,
3071 struct rtnl_link_stats64 *stats)
3072{
3073 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3074 unsigned int start;
3075 u64 bytes, packets;
3076 const struct ixgbevf_ring *ring;
3077 int i;
3078
3079 ixgbevf_update_stats(adapter);
3080
3081 stats->multicast = adapter->stats.vfmprc - adapter->stats.base_vfmprc;
3082
3083 for (i = 0; i < adapter->num_rx_queues; i++) {
3084 ring = &adapter->rx_ring[i];
3085 do {
3086 start = u64_stats_fetch_begin_bh(&ring->syncp);
3087 bytes = ring->total_bytes;
3088 packets = ring->total_packets;
3089 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
3090 stats->rx_bytes += bytes;
3091 stats->rx_packets += packets;
3092 }
3093
3094 for (i = 0; i < adapter->num_tx_queues; i++) {
3095 ring = &adapter->tx_ring[i];
3096 do {
3097 start = u64_stats_fetch_begin_bh(&ring->syncp);
3098 bytes = ring->total_bytes;
3099 packets = ring->total_packets;
3100 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
3101 stats->tx_bytes += bytes;
3102 stats->tx_packets += packets;
3103 }
3104
3105 return stats;
3106}
3107
92915f71 3108static const struct net_device_ops ixgbe_netdev_ops = {
c12db769
SH		 3109 .ndo_open = ixgbevf_open,
3110 .ndo_stop = ixgbevf_close,
3111 .ndo_start_xmit = ixgbevf_xmit_frame,
3112 .ndo_set_rx_mode = ixgbevf_set_rx_mode,
4197aa7b 3113 .ndo_get_stats64 = ixgbevf_get_stats,
92915f71 3114 .ndo_validate_addr = eth_validate_addr,
c12db769
SH		 3115 .ndo_set_mac_address = ixgbevf_set_mac,
3116 .ndo_change_mtu = ixgbevf_change_mtu,
3117 .ndo_tx_timeout = ixgbevf_tx_timeout,
c12db769
SH		 3118 .ndo_vlan_rx_add_vid = ixgbevf_vlan_rx_add_vid,
3119 .ndo_vlan_rx_kill_vid = ixgbevf_vlan_rx_kill_vid,
92915f71 3120};
92915f71
GR		 3121
3122static void ixgbevf_assign_netdev_ops(struct net_device *dev)
3123{
92915f71 3124 dev->netdev_ops = &ixgbe_netdev_ops;
92915f71
GR		 3125 ixgbevf_set_ethtool_ops(dev);
3126 dev->watchdog_timeo = 5 * HZ;
3127}
3128
3129/**
3130 * ixgbevf_probe - Device Initialization Routine
3131 * @pdev: PCI device information struct
3132 * @ent: entry in ixgbevf_pci_tbl
3133 *
3134 * Returns 0 on success, negative on failure
3135 *
3136 * ixgbevf_probe initializes an adapter identified by a pci_dev structure.
3137 * The OS initialization, configuring of the adapter private structure,
3138 * and a hardware reset occur.
3139 **/
3140static int __devinit ixgbevf_probe(struct pci_dev *pdev,
3141 const struct pci_device_id *ent)
3142{
3143 struct net_device *netdev;
3144 struct ixgbevf_adapter *adapter = NULL;
3145 struct ixgbe_hw *hw = NULL;
3146 const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data];
3147 static int cards_found;
3148 int err, pci_using_dac;
3149
3150 err = pci_enable_device(pdev);
3151 if (err)
3152 return err;
3153
2a1f8794
NN		 3154 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3155 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
92915f71
GR		 3156 pci_using_dac = 1;
3157 } else {
2a1f8794 3158 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
92915f71 3159 if (err) {
2a1f8794
NN		 3160 err = dma_set_coherent_mask(&pdev->dev,
3161 DMA_BIT_MASK(32));
92915f71
GR		 3162 if (err) {
3163 dev_err(&pdev->dev, "No usable DMA "
3164 "configuration, aborting\n");
3165 goto err_dma;
3166 }
3167 }
3168 pci_using_dac = 0;
3169 }
3170
3171 err = pci_request_regions(pdev, ixgbevf_driver_name);
3172 if (err) {
3173 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3174 goto err_pci_reg;
3175 }
3176
3177 pci_set_master(pdev);
3178
92915f71
GR		 3179 netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter),
3180 MAX_TX_QUEUES);
92915f71
GR		 3181 if (!netdev) {
3182 err = -ENOMEM;
3183 goto err_alloc_etherdev;
3184 }
3185
3186 SET_NETDEV_DEV(netdev, &pdev->dev);
3187
3188 pci_set_drvdata(pdev, netdev);
3189 adapter = netdev_priv(netdev);
3190
3191 adapter->netdev = netdev;
3192 adapter->pdev = pdev;
3193 hw = &adapter->hw;
3194 hw->back = adapter;
b3f4d599 3195 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
92915f71
GR		 3196
3197 /*
3198 * call save state here in standalone driver because it relies on
3199 * adapter struct to exist, and needs to call netdev_priv
3200 */
3201 pci_save_state(pdev);
3202
3203 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3204 pci_resource_len(pdev, 0));
3205 if (!hw->hw_addr) {
3206 err = -EIO;
3207 goto err_ioremap;
3208 }
3209
3210 ixgbevf_assign_netdev_ops(netdev);
3211
3212 adapter->bd_number = cards_found;
3213
3214 /* Setup hw api */
3215 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3216 hw->mac.type = ii->mac;
3217
3218 memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops,
f416dfc0 3219 sizeof(struct ixgbe_mbx_operations));
92915f71 3220
92915f71
GR		 3221 /* setup the private structure */
3222 err = ixgbevf_sw_init(adapter);
1a0d6ae5
DK		 3223 if (err)
3224 goto err_sw_init;
3225
3226 /* The HW MAC address was set and/or determined in sw_init */
3227 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
3228
3229 if (!is_valid_ether_addr(netdev->dev_addr)) {
3230 pr_err("invalid MAC address\n");
3231 err = -EIO;
3232 goto err_sw_init;
3233 }
92915f71 3234
471a76de 3235 netdev->hw_features = NETIF_F_SG |
92915f71 3236 NETIF_F_IP_CSUM |
471a76de
MM		 3237 NETIF_F_IPV6_CSUM |
3238 NETIF_F_TSO |
3239 NETIF_F_TSO6 |
3240 NETIF_F_RXCSUM;
3241
3242 netdev->features = netdev->hw_features |
92915f71
GR		 3243 NETIF_F_HW_VLAN_TX |
3244 NETIF_F_HW_VLAN_RX |
3245 NETIF_F_HW_VLAN_FILTER;
3246
92915f71
GR		 3247 netdev->vlan_features |= NETIF_F_TSO;
3248 netdev->vlan_features |= NETIF_F_TSO6;
3249 netdev->vlan_features |= NETIF_F_IP_CSUM;
3bfacf96 3250 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
92915f71
GR		 3251 netdev->vlan_features |= NETIF_F_SG;
3252
3253 if (pci_using_dac)
3254 netdev->features |= NETIF_F_HIGHDMA;
3255
01789349
JP		 3256 netdev->priv_flags |= IFF_UNICAST_FLT;
3257
92915f71 3258 init_timer(&adapter->watchdog_timer);
c061b18d 3259 adapter->watchdog_timer.function = ixgbevf_watchdog;
92915f71
GR		 3260 adapter->watchdog_timer.data = (unsigned long)adapter;
3261
3262 INIT_WORK(&adapter->reset_task, ixgbevf_reset_task);
3263 INIT_WORK(&adapter->watchdog_task, ixgbevf_watchdog_task);
3264
3265 err = ixgbevf_init_interrupt_scheme(adapter);
3266 if (err)
3267 goto err_sw_init;
3268
3269 /* pick up the PCI bus settings for reporting later */
3270 if (hw->mac.ops.get_bus_info)
3271 hw->mac.ops.get_bus_info(hw);
3272
92915f71
GR		 3273 strcpy(netdev->name, "eth%d");
3274
3275 err = register_netdev(netdev);
3276 if (err)
3277 goto err_register;
3278
5d426ad1
GR		 3279 netif_carrier_off(netdev);
3280
33bd9f60
GR		 3281 ixgbevf_init_last_counter_stats(adapter);
3282
92915f71 3283 /* print the MAC address */
f794e7ef 3284 hw_dbg(hw, "%pM\n", netdev->dev_addr);
92915f71
GR		 3285
3286 hw_dbg(hw, "MAC: %d\n", hw->mac.type);
3287
92915f71
GR		 3288 hw_dbg(hw, "Intel(R) 82599 Virtual Function\n");
3289 cards_found++;
3290 return 0;
3291
3292err_register:
3293err_sw_init:
3294 ixgbevf_reset_interrupt_capability(adapter);
3295 iounmap(hw->hw_addr);
3296err_ioremap:
3297 free_netdev(netdev);
3298err_alloc_etherdev:
3299 pci_release_regions(pdev);
3300err_pci_reg:
3301err_dma:
3302 pci_disable_device(pdev);
3303 return err;
3304}
3305
3306/**
3307 * ixgbevf_remove - Device Removal Routine
3308 * @pdev: PCI device information struct
3309 *
3310 * ixgbevf_remove is called by the PCI subsystem to alert the driver
3311 * that it should release a PCI device. The could be caused by a
3312 * Hot-Plug event, or because the driver is going to be removed from
3313 * memory.
3314 **/
3315static void __devexit ixgbevf_remove(struct pci_dev *pdev)
3316{
3317 struct net_device *netdev = pci_get_drvdata(pdev);
3318 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3319
3320 set_bit(__IXGBEVF_DOWN, &adapter->state);
3321
3322 del_timer_sync(&adapter->watchdog_timer);
3323
23f333a2 3324 cancel_work_sync(&adapter->reset_task);
92915f71
GR		 3325 cancel_work_sync(&adapter->watchdog_task);
3326
fd13a9ab 3327 if (netdev->reg_state == NETREG_REGISTERED)
92915f71 3328 unregister_netdev(netdev);
92915f71
GR		 3329
3330 ixgbevf_reset_interrupt_capability(adapter);
3331
3332 iounmap(adapter->hw.hw_addr);
3333 pci_release_regions(pdev);
3334
3335 hw_dbg(&adapter->hw, "Remove complete\n");
3336
3337 kfree(adapter->tx_ring);
3338 kfree(adapter->rx_ring);
3339
3340 free_netdev(netdev);
3341
3342 pci_disable_device(pdev);
3343}
3344
3345static struct pci_driver ixgbevf_driver = {
3346 .name = ixgbevf_driver_name,
3347 .id_table = ixgbevf_pci_tbl,
3348 .probe = ixgbevf_probe,
3349 .remove = __devexit_p(ixgbevf_remove),
3350 .shutdown = ixgbevf_shutdown,
3351};
3352
3353/**
65d676c8 3354 * ixgbevf_init_module - Driver Registration Routine
92915f71 3355 *
65d676c8 3356 * ixgbevf_init_module is the first routine called when the driver is
92915f71
GR		 3357 * loaded. All it does is register with the PCI subsystem.
3358 **/
3359static int __init ixgbevf_init_module(void)
3360{
3361 int ret;
dbd9636e
JK		 3362 pr_info("%s - version %s\n", ixgbevf_driver_string,
3363 ixgbevf_driver_version);
92915f71 3364
dbd9636e 3365 pr_info("%s\n", ixgbevf_copyright);
92915f71
GR		 3366
3367 ret = pci_register_driver(&ixgbevf_driver);
3368 return ret;
3369}
3370
3371module_init(ixgbevf_init_module);
3372
3373/**
65d676c8 3374 * ixgbevf_exit_module - Driver Exit Cleanup Routine
92915f71 3375 *
65d676c8 3376 * ixgbevf_exit_module is called just before the driver is removed
92915f71
GR		 3377 * from memory.
3378 **/
3379static void __exit ixgbevf_exit_module(void)
3380{
3381 pci_unregister_driver(&ixgbevf_driver);
3382}
3383
3384#ifdef DEBUG
3385/**
65d676c8 3386 * ixgbevf_get_hw_dev_name - return device name string
92915f71
GR		 3387 * used by hardware layer to print debugging information
3388 **/
3389char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw)
3390{
3391 struct ixgbevf_adapter *adapter = hw->back;
3392 return adapter->netdev->name;
3393}
3394
3395#endif
3396module_exit(ixgbevf_exit_module);
3397
3398/* ixgbevf_main.c */
Linux kernel - Deliverables
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