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504d4721 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 12 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
504d4721 JC |
13 | * |
14 | * Copyright (C) 2011 John Crispin <blogic@openwrt.org> | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/uaccess.h> | |
23 | #include <linux/in.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/phy.h> | |
27 | #include <linux/ip.h> | |
28 | #include <linux/tcp.h> | |
29 | #include <linux/skbuff.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/io.h> | |
a32fd63d JC |
36 | #include <linux/dma-mapping.h> |
37 | #include <linux/module.h> | |
504d4721 JC |
38 | |
39 | #include <asm/checksum.h> | |
40 | ||
41 | #include <lantiq_soc.h> | |
42 | #include <xway_dma.h> | |
43 | #include <lantiq_platform.h> | |
44 | ||
45 | #define LTQ_ETOP_MDIO 0x11804 | |
46 | #define MDIO_REQUEST 0x80000000 | |
47 | #define MDIO_READ 0x40000000 | |
48 | #define MDIO_ADDR_MASK 0x1f | |
49 | #define MDIO_ADDR_OFFSET 0x15 | |
50 | #define MDIO_REG_MASK 0x1f | |
51 | #define MDIO_REG_OFFSET 0x10 | |
52 | #define MDIO_VAL_MASK 0xffff | |
53 | ||
54 | #define PPE32_CGEN 0x800 | |
55 | #define LQ_PPE32_ENET_MAC_CFG 0x1840 | |
56 | ||
57 | #define LTQ_ETOP_ENETS0 0x11850 | |
58 | #define LTQ_ETOP_MAC_DA0 0x1186C | |
59 | #define LTQ_ETOP_MAC_DA1 0x11870 | |
60 | #define LTQ_ETOP_CFG 0x16020 | |
61 | #define LTQ_ETOP_IGPLEN 0x16080 | |
62 | ||
63 | #define MAX_DMA_CHAN 0x8 | |
64 | #define MAX_DMA_CRC_LEN 0x4 | |
65 | #define MAX_DMA_DATA_LEN 0x600 | |
66 | ||
67 | #define ETOP_FTCU BIT(28) | |
68 | #define ETOP_MII_MASK 0xf | |
69 | #define ETOP_MII_NORMAL 0xd | |
70 | #define ETOP_MII_REVERSE 0xe | |
71 | #define ETOP_PLEN_UNDER 0x40 | |
72 | #define ETOP_CGEN 0x800 | |
73 | ||
74 | /* use 2 static channels for TX/RX */ | |
75 | #define LTQ_ETOP_TX_CHANNEL 1 | |
76 | #define LTQ_ETOP_RX_CHANNEL 6 | |
77 | #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) | |
78 | #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) | |
79 | ||
80 | #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) | |
81 | #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) | |
82 | #define ltq_etop_w32_mask(x, y, z) \ | |
83 | ltq_w32_mask(x, y, ltq_etop_membase + (z)) | |
84 | ||
85 | #define DRV_VERSION "1.0" | |
86 | ||
87 | static void __iomem *ltq_etop_membase; | |
88 | ||
89 | struct ltq_etop_chan { | |
90 | int idx; | |
91 | int tx_free; | |
92 | struct net_device *netdev; | |
93 | struct napi_struct napi; | |
94 | struct ltq_dma_channel dma; | |
95 | struct sk_buff *skb[LTQ_DESC_NUM]; | |
96 | }; | |
97 | ||
98 | struct ltq_etop_priv { | |
99 | struct net_device *netdev; | |
d1b86507 | 100 | struct platform_device *pdev; |
504d4721 JC |
101 | struct ltq_eth_data *pldata; |
102 | struct resource *res; | |
103 | ||
104 | struct mii_bus *mii_bus; | |
105 | struct phy_device *phydev; | |
106 | ||
107 | struct ltq_etop_chan ch[MAX_DMA_CHAN]; | |
108 | int tx_free[MAX_DMA_CHAN >> 1]; | |
109 | ||
110 | spinlock_t lock; | |
111 | }; | |
112 | ||
113 | static int | |
114 | ltq_etop_alloc_skb(struct ltq_etop_chan *ch) | |
115 | { | |
c056b734 | 116 | ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); |
504d4721 JC |
117 | if (!ch->skb[ch->dma.desc]) |
118 | return -ENOMEM; | |
119 | ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, | |
120 | ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, | |
121 | DMA_FROM_DEVICE); | |
122 | ch->dma.desc_base[ch->dma.desc].addr = | |
123 | CPHYSADDR(ch->skb[ch->dma.desc]->data); | |
124 | ch->dma.desc_base[ch->dma.desc].ctl = | |
125 | LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | | |
126 | MAX_DMA_DATA_LEN; | |
127 | skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static void | |
132 | ltq_etop_hw_receive(struct ltq_etop_chan *ch) | |
133 | { | |
134 | struct ltq_etop_priv *priv = netdev_priv(ch->netdev); | |
135 | struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; | |
136 | struct sk_buff *skb = ch->skb[ch->dma.desc]; | |
137 | int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&priv->lock, flags); | |
141 | if (ltq_etop_alloc_skb(ch)) { | |
142 | netdev_err(ch->netdev, | |
143 | "failed to allocate new rx buffer, stopping DMA\n"); | |
144 | ltq_dma_close(&ch->dma); | |
145 | } | |
146 | ch->dma.desc++; | |
147 | ch->dma.desc %= LTQ_DESC_NUM; | |
148 | spin_unlock_irqrestore(&priv->lock, flags); | |
149 | ||
150 | skb_put(skb, len); | |
504d4721 JC |
151 | skb->protocol = eth_type_trans(skb, ch->netdev); |
152 | netif_receive_skb(skb); | |
153 | } | |
154 | ||
155 | static int | |
156 | ltq_etop_poll_rx(struct napi_struct *napi, int budget) | |
157 | { | |
158 | struct ltq_etop_chan *ch = container_of(napi, | |
159 | struct ltq_etop_chan, napi); | |
160 | int rx = 0; | |
161 | int complete = 0; | |
162 | ||
163 | while ((rx < budget) && !complete) { | |
164 | struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; | |
165 | ||
166 | if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { | |
167 | ltq_etop_hw_receive(ch); | |
168 | rx++; | |
169 | } else { | |
170 | complete = 1; | |
171 | } | |
172 | } | |
173 | if (complete || !rx) { | |
174 | napi_complete(&ch->napi); | |
175 | ltq_dma_ack_irq(&ch->dma); | |
176 | } | |
177 | return rx; | |
178 | } | |
179 | ||
180 | static int | |
181 | ltq_etop_poll_tx(struct napi_struct *napi, int budget) | |
182 | { | |
183 | struct ltq_etop_chan *ch = | |
184 | container_of(napi, struct ltq_etop_chan, napi); | |
185 | struct ltq_etop_priv *priv = netdev_priv(ch->netdev); | |
186 | struct netdev_queue *txq = | |
187 | netdev_get_tx_queue(ch->netdev, ch->idx >> 1); | |
188 | unsigned long flags; | |
189 | ||
190 | spin_lock_irqsave(&priv->lock, flags); | |
191 | while ((ch->dma.desc_base[ch->tx_free].ctl & | |
192 | (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { | |
193 | dev_kfree_skb_any(ch->skb[ch->tx_free]); | |
194 | ch->skb[ch->tx_free] = NULL; | |
195 | memset(&ch->dma.desc_base[ch->tx_free], 0, | |
196 | sizeof(struct ltq_dma_desc)); | |
197 | ch->tx_free++; | |
198 | ch->tx_free %= LTQ_DESC_NUM; | |
199 | } | |
200 | spin_unlock_irqrestore(&priv->lock, flags); | |
201 | ||
202 | if (netif_tx_queue_stopped(txq)) | |
203 | netif_tx_start_queue(txq); | |
204 | napi_complete(&ch->napi); | |
205 | ltq_dma_ack_irq(&ch->dma); | |
206 | return 1; | |
207 | } | |
208 | ||
209 | static irqreturn_t | |
210 | ltq_etop_dma_irq(int irq, void *_priv) | |
211 | { | |
212 | struct ltq_etop_priv *priv = _priv; | |
213 | int ch = irq - LTQ_DMA_CH0_INT; | |
214 | ||
215 | napi_schedule(&priv->ch[ch].napi); | |
216 | return IRQ_HANDLED; | |
217 | } | |
218 | ||
219 | static void | |
220 | ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) | |
221 | { | |
222 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
223 | ||
224 | ltq_dma_free(&ch->dma); | |
225 | if (ch->dma.irq) | |
226 | free_irq(ch->dma.irq, priv); | |
227 | if (IS_RX(ch->idx)) { | |
228 | int desc; | |
229 | for (desc = 0; desc < LTQ_DESC_NUM; desc++) | |
230 | dev_kfree_skb_any(ch->skb[ch->dma.desc]); | |
231 | } | |
232 | } | |
233 | ||
234 | static void | |
235 | ltq_etop_hw_exit(struct net_device *dev) | |
236 | { | |
237 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
238 | int i; | |
239 | ||
240 | ltq_pmu_disable(PMU_PPE); | |
241 | for (i = 0; i < MAX_DMA_CHAN; i++) | |
242 | if (IS_TX(i) || IS_RX(i)) | |
243 | ltq_etop_free_channel(dev, &priv->ch[i]); | |
244 | } | |
245 | ||
246 | static int | |
247 | ltq_etop_hw_init(struct net_device *dev) | |
248 | { | |
249 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
250 | int i; | |
251 | ||
252 | ltq_pmu_enable(PMU_PPE); | |
253 | ||
254 | switch (priv->pldata->mii_mode) { | |
255 | case PHY_INTERFACE_MODE_RMII: | |
256 | ltq_etop_w32_mask(ETOP_MII_MASK, | |
257 | ETOP_MII_REVERSE, LTQ_ETOP_CFG); | |
258 | break; | |
259 | ||
260 | case PHY_INTERFACE_MODE_MII: | |
261 | ltq_etop_w32_mask(ETOP_MII_MASK, | |
262 | ETOP_MII_NORMAL, LTQ_ETOP_CFG); | |
263 | break; | |
264 | ||
265 | default: | |
266 | netdev_err(dev, "unknown mii mode %d\n", | |
267 | priv->pldata->mii_mode); | |
268 | return -ENOTSUPP; | |
269 | } | |
270 | ||
271 | /* enable crc generation */ | |
272 | ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); | |
273 | ||
274 | ltq_dma_init_port(DMA_PORT_ETOP); | |
275 | ||
276 | for (i = 0; i < MAX_DMA_CHAN; i++) { | |
277 | int irq = LTQ_DMA_CH0_INT + i; | |
278 | struct ltq_etop_chan *ch = &priv->ch[i]; | |
279 | ||
280 | ch->idx = ch->dma.nr = i; | |
281 | ||
282 | if (IS_TX(i)) { | |
283 | ltq_dma_alloc_tx(&ch->dma); | |
dddb29e4 | 284 | request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); |
504d4721 JC |
285 | } else if (IS_RX(i)) { |
286 | ltq_dma_alloc_rx(&ch->dma); | |
287 | for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; | |
288 | ch->dma.desc++) | |
289 | if (ltq_etop_alloc_skb(ch)) | |
290 | return -ENOMEM; | |
291 | ch->dma.desc = 0; | |
dddb29e4 | 292 | request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); |
504d4721 JC |
293 | } |
294 | ch->dma.irq = irq; | |
295 | } | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static void | |
300 | ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
301 | { | |
7826d43f JP |
302 | strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver)); |
303 | strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); | |
304 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
504d4721 JC |
305 | } |
306 | ||
307 | static int | |
308 | ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
309 | { | |
310 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
311 | ||
312 | return phy_ethtool_gset(priv->phydev, cmd); | |
313 | } | |
314 | ||
315 | static int | |
316 | ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
317 | { | |
318 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
319 | ||
320 | return phy_ethtool_sset(priv->phydev, cmd); | |
321 | } | |
322 | ||
323 | static int | |
324 | ltq_etop_nway_reset(struct net_device *dev) | |
325 | { | |
326 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
327 | ||
328 | return phy_start_aneg(priv->phydev); | |
329 | } | |
330 | ||
331 | static const struct ethtool_ops ltq_etop_ethtool_ops = { | |
332 | .get_drvinfo = ltq_etop_get_drvinfo, | |
333 | .get_settings = ltq_etop_get_settings, | |
334 | .set_settings = ltq_etop_set_settings, | |
335 | .nway_reset = ltq_etop_nway_reset, | |
336 | }; | |
337 | ||
338 | static int | |
339 | ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) | |
340 | { | |
341 | u32 val = MDIO_REQUEST | | |
342 | ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | | |
343 | ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | | |
344 | phy_data; | |
345 | ||
346 | while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) | |
347 | ; | |
348 | ltq_etop_w32(val, LTQ_ETOP_MDIO); | |
349 | return 0; | |
350 | } | |
351 | ||
352 | static int | |
353 | ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) | |
354 | { | |
355 | u32 val = MDIO_REQUEST | MDIO_READ | | |
356 | ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | | |
357 | ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); | |
358 | ||
359 | while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) | |
360 | ; | |
361 | ltq_etop_w32(val, LTQ_ETOP_MDIO); | |
362 | while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) | |
363 | ; | |
364 | val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; | |
365 | return val; | |
366 | } | |
367 | ||
368 | static void | |
369 | ltq_etop_mdio_link(struct net_device *dev) | |
370 | { | |
371 | /* nothing to do */ | |
372 | } | |
373 | ||
374 | static int | |
375 | ltq_etop_mdio_probe(struct net_device *dev) | |
376 | { | |
377 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
378 | struct phy_device *phydev = NULL; | |
379 | int phy_addr; | |
380 | ||
381 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
382 | if (priv->mii_bus->phy_map[phy_addr]) { | |
383 | phydev = priv->mii_bus->phy_map[phy_addr]; | |
384 | break; | |
385 | } | |
386 | } | |
387 | ||
388 | if (!phydev) { | |
389 | netdev_err(dev, "no PHY found\n"); | |
390 | return -ENODEV; | |
391 | } | |
392 | ||
f9a8f83b FF |
393 | phydev = phy_connect(dev, dev_name(&phydev->dev), |
394 | <q_etop_mdio_link, priv->pldata->mii_mode); | |
504d4721 JC |
395 | |
396 | if (IS_ERR(phydev)) { | |
397 | netdev_err(dev, "Could not attach to PHY\n"); | |
398 | return PTR_ERR(phydev); | |
399 | } | |
400 | ||
401 | phydev->supported &= (SUPPORTED_10baseT_Half | |
402 | | SUPPORTED_10baseT_Full | |
403 | | SUPPORTED_100baseT_Half | |
404 | | SUPPORTED_100baseT_Full | |
405 | | SUPPORTED_Autoneg | |
406 | | SUPPORTED_MII | |
407 | | SUPPORTED_TP); | |
408 | ||
409 | phydev->advertising = phydev->supported; | |
410 | priv->phydev = phydev; | |
411 | pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", | |
412 | dev->name, phydev->drv->name, | |
413 | dev_name(&phydev->dev), phydev->irq); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | static int | |
419 | ltq_etop_mdio_init(struct net_device *dev) | |
420 | { | |
421 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
422 | int i; | |
423 | int err; | |
424 | ||
425 | priv->mii_bus = mdiobus_alloc(); | |
426 | if (!priv->mii_bus) { | |
427 | netdev_err(dev, "failed to allocate mii bus\n"); | |
428 | err = -ENOMEM; | |
429 | goto err_out; | |
430 | } | |
431 | ||
432 | priv->mii_bus->priv = dev; | |
433 | priv->mii_bus->read = ltq_etop_mdio_rd; | |
434 | priv->mii_bus->write = ltq_etop_mdio_wr; | |
435 | priv->mii_bus->name = "ltq_mii"; | |
d1b86507 FF |
436 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
437 | priv->pdev->name, priv->pdev->id); | |
504d4721 JC |
438 | priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); |
439 | if (!priv->mii_bus->irq) { | |
440 | err = -ENOMEM; | |
441 | goto err_out_free_mdiobus; | |
442 | } | |
443 | ||
444 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
445 | priv->mii_bus->irq[i] = PHY_POLL; | |
446 | ||
447 | if (mdiobus_register(priv->mii_bus)) { | |
448 | err = -ENXIO; | |
449 | goto err_out_free_mdio_irq; | |
450 | } | |
451 | ||
452 | if (ltq_etop_mdio_probe(dev)) { | |
453 | err = -ENXIO; | |
454 | goto err_out_unregister_bus; | |
455 | } | |
456 | return 0; | |
457 | ||
458 | err_out_unregister_bus: | |
459 | mdiobus_unregister(priv->mii_bus); | |
460 | err_out_free_mdio_irq: | |
461 | kfree(priv->mii_bus->irq); | |
462 | err_out_free_mdiobus: | |
463 | mdiobus_free(priv->mii_bus); | |
464 | err_out: | |
465 | return err; | |
466 | } | |
467 | ||
468 | static void | |
469 | ltq_etop_mdio_cleanup(struct net_device *dev) | |
470 | { | |
471 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
472 | ||
473 | phy_disconnect(priv->phydev); | |
474 | mdiobus_unregister(priv->mii_bus); | |
475 | kfree(priv->mii_bus->irq); | |
476 | mdiobus_free(priv->mii_bus); | |
477 | } | |
478 | ||
479 | static int | |
480 | ltq_etop_open(struct net_device *dev) | |
481 | { | |
482 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
483 | int i; | |
484 | ||
485 | for (i = 0; i < MAX_DMA_CHAN; i++) { | |
486 | struct ltq_etop_chan *ch = &priv->ch[i]; | |
487 | ||
488 | if (!IS_TX(i) && (!IS_RX(i))) | |
489 | continue; | |
490 | ltq_dma_open(&ch->dma); | |
491 | napi_enable(&ch->napi); | |
492 | } | |
493 | phy_start(priv->phydev); | |
494 | netif_tx_start_all_queues(dev); | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int | |
499 | ltq_etop_stop(struct net_device *dev) | |
500 | { | |
501 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
502 | int i; | |
503 | ||
504 | netif_tx_stop_all_queues(dev); | |
505 | phy_stop(priv->phydev); | |
506 | for (i = 0; i < MAX_DMA_CHAN; i++) { | |
507 | struct ltq_etop_chan *ch = &priv->ch[i]; | |
508 | ||
509 | if (!IS_RX(i) && !IS_TX(i)) | |
510 | continue; | |
511 | napi_disable(&ch->napi); | |
512 | ltq_dma_close(&ch->dma); | |
513 | } | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static int | |
518 | ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) | |
519 | { | |
520 | int queue = skb_get_queue_mapping(skb); | |
521 | struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); | |
522 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
523 | struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; | |
524 | struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; | |
525 | int len; | |
526 | unsigned long flags; | |
527 | u32 byte_offset; | |
528 | ||
529 | len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; | |
530 | ||
531 | if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { | |
532 | dev_kfree_skb_any(skb); | |
533 | netdev_err(dev, "tx ring full\n"); | |
534 | netif_tx_stop_queue(txq); | |
535 | return NETDEV_TX_BUSY; | |
536 | } | |
537 | ||
538 | /* dma needs to start on a 16 byte aligned address */ | |
539 | byte_offset = CPHYSADDR(skb->data) % 16; | |
540 | ch->skb[ch->dma.desc] = skb; | |
541 | ||
542 | dev->trans_start = jiffies; | |
543 | ||
544 | spin_lock_irqsave(&priv->lock, flags); | |
545 | desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, | |
546 | DMA_TO_DEVICE)) - byte_offset; | |
547 | wmb(); | |
548 | desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | | |
549 | LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); | |
550 | ch->dma.desc++; | |
551 | ch->dma.desc %= LTQ_DESC_NUM; | |
552 | spin_unlock_irqrestore(&priv->lock, flags); | |
553 | ||
554 | if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) | |
555 | netif_tx_stop_queue(txq); | |
556 | ||
557 | return NETDEV_TX_OK; | |
558 | } | |
559 | ||
560 | static int | |
561 | ltq_etop_change_mtu(struct net_device *dev, int new_mtu) | |
562 | { | |
563 | int ret = eth_change_mtu(dev, new_mtu); | |
564 | ||
565 | if (!ret) { | |
566 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
567 | unsigned long flags; | |
568 | ||
569 | spin_lock_irqsave(&priv->lock, flags); | |
570 | ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, | |
571 | LTQ_ETOP_IGPLEN); | |
572 | spin_unlock_irqrestore(&priv->lock, flags); | |
573 | } | |
574 | return ret; | |
575 | } | |
576 | ||
577 | static int | |
578 | ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
579 | { | |
580 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
581 | ||
582 | /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ | |
583 | return phy_mii_ioctl(priv->phydev, rq, cmd); | |
584 | } | |
585 | ||
586 | static int | |
587 | ltq_etop_set_mac_address(struct net_device *dev, void *p) | |
588 | { | |
589 | int ret = eth_mac_addr(dev, p); | |
590 | ||
591 | if (!ret) { | |
592 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
593 | unsigned long flags; | |
594 | ||
595 | /* store the mac for the unicast filter */ | |
596 | spin_lock_irqsave(&priv->lock, flags); | |
597 | ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); | |
598 | ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, | |
599 | LTQ_ETOP_MAC_DA1); | |
600 | spin_unlock_irqrestore(&priv->lock, flags); | |
601 | } | |
602 | return ret; | |
603 | } | |
604 | ||
605 | static void | |
606 | ltq_etop_set_multicast_list(struct net_device *dev) | |
607 | { | |
608 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
609 | unsigned long flags; | |
610 | ||
611 | /* ensure that the unicast filter is not enabled in promiscious mode */ | |
612 | spin_lock_irqsave(&priv->lock, flags); | |
613 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) | |
614 | ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); | |
615 | else | |
616 | ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); | |
617 | spin_unlock_irqrestore(&priv->lock, flags); | |
618 | } | |
619 | ||
620 | static u16 | |
f663dd9a | 621 | ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 622 | void *accel_priv, select_queue_fallback_t fallback) |
504d4721 JC |
623 | { |
624 | /* we are currently only using the first queue */ | |
625 | return 0; | |
626 | } | |
627 | ||
628 | static int | |
629 | ltq_etop_init(struct net_device *dev) | |
630 | { | |
631 | struct ltq_etop_priv *priv = netdev_priv(dev); | |
632 | struct sockaddr mac; | |
633 | int err; | |
43aabec5 | 634 | bool random_mac = false; |
504d4721 | 635 | |
504d4721 JC |
636 | dev->watchdog_timeo = 10 * HZ; |
637 | err = ltq_etop_hw_init(dev); | |
638 | if (err) | |
639 | goto err_hw; | |
640 | ltq_etop_change_mtu(dev, 1500); | |
641 | ||
642 | memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); | |
643 | if (!is_valid_ether_addr(mac.sa_data)) { | |
644 | pr_warn("etop: invalid MAC, using random\n"); | |
7efd26d0 | 645 | eth_random_addr(mac.sa_data); |
43aabec5 | 646 | random_mac = true; |
504d4721 JC |
647 | } |
648 | ||
649 | err = ltq_etop_set_mac_address(dev, &mac); | |
650 | if (err) | |
651 | goto err_netdev; | |
43aabec5 DK |
652 | |
653 | /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ | |
654 | if (random_mac) | |
e41b2d7f | 655 | dev->addr_assign_type = NET_ADDR_RANDOM; |
43aabec5 | 656 | |
504d4721 JC |
657 | ltq_etop_set_multicast_list(dev); |
658 | err = ltq_etop_mdio_init(dev); | |
659 | if (err) | |
660 | goto err_netdev; | |
661 | return 0; | |
662 | ||
663 | err_netdev: | |
664 | unregister_netdev(dev); | |
665 | free_netdev(dev); | |
666 | err_hw: | |
667 | ltq_etop_hw_exit(dev); | |
668 | return err; | |
669 | } | |
670 | ||
671 | static void | |
672 | ltq_etop_tx_timeout(struct net_device *dev) | |
673 | { | |
674 | int err; | |
675 | ||
676 | ltq_etop_hw_exit(dev); | |
677 | err = ltq_etop_hw_init(dev); | |
678 | if (err) | |
679 | goto err_hw; | |
680 | dev->trans_start = jiffies; | |
681 | netif_wake_queue(dev); | |
682 | return; | |
683 | ||
684 | err_hw: | |
685 | ltq_etop_hw_exit(dev); | |
686 | netdev_err(dev, "failed to restart etop after TX timeout\n"); | |
687 | } | |
688 | ||
689 | static const struct net_device_ops ltq_eth_netdev_ops = { | |
690 | .ndo_open = ltq_etop_open, | |
691 | .ndo_stop = ltq_etop_stop, | |
692 | .ndo_start_xmit = ltq_etop_tx, | |
693 | .ndo_change_mtu = ltq_etop_change_mtu, | |
694 | .ndo_do_ioctl = ltq_etop_ioctl, | |
695 | .ndo_set_mac_address = ltq_etop_set_mac_address, | |
696 | .ndo_validate_addr = eth_validate_addr, | |
afc4b13d | 697 | .ndo_set_rx_mode = ltq_etop_set_multicast_list, |
504d4721 JC |
698 | .ndo_select_queue = ltq_etop_select_queue, |
699 | .ndo_init = ltq_etop_init, | |
700 | .ndo_tx_timeout = ltq_etop_tx_timeout, | |
701 | }; | |
702 | ||
703 | static int __init | |
704 | ltq_etop_probe(struct platform_device *pdev) | |
705 | { | |
706 | struct net_device *dev; | |
707 | struct ltq_etop_priv *priv; | |
708 | struct resource *res; | |
709 | int err; | |
710 | int i; | |
711 | ||
712 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
713 | if (!res) { | |
714 | dev_err(&pdev->dev, "failed to get etop resource\n"); | |
715 | err = -ENOENT; | |
716 | goto err_out; | |
717 | } | |
718 | ||
719 | res = devm_request_mem_region(&pdev->dev, res->start, | |
720 | resource_size(res), dev_name(&pdev->dev)); | |
721 | if (!res) { | |
722 | dev_err(&pdev->dev, "failed to request etop resource\n"); | |
723 | err = -EBUSY; | |
724 | goto err_out; | |
725 | } | |
726 | ||
727 | ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, | |
728 | res->start, resource_size(res)); | |
729 | if (!ltq_etop_membase) { | |
730 | dev_err(&pdev->dev, "failed to remap etop engine %d\n", | |
731 | pdev->id); | |
732 | err = -ENOMEM; | |
733 | goto err_out; | |
734 | } | |
735 | ||
736 | dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); | |
41de8d4c JP |
737 | if (!dev) { |
738 | err = -ENOMEM; | |
739 | goto err_out; | |
740 | } | |
504d4721 JC |
741 | strcpy(dev->name, "eth%d"); |
742 | dev->netdev_ops = <q_eth_netdev_ops; | |
743 | dev->ethtool_ops = <q_etop_ethtool_ops; | |
744 | priv = netdev_priv(dev); | |
745 | priv->res = res; | |
d1b86507 | 746 | priv->pdev = pdev; |
504d4721 JC |
747 | priv->pldata = dev_get_platdata(&pdev->dev); |
748 | priv->netdev = dev; | |
749 | spin_lock_init(&priv->lock); | |
750 | ||
751 | for (i = 0; i < MAX_DMA_CHAN; i++) { | |
752 | if (IS_TX(i)) | |
753 | netif_napi_add(dev, &priv->ch[i].napi, | |
754 | ltq_etop_poll_tx, 8); | |
755 | else if (IS_RX(i)) | |
756 | netif_napi_add(dev, &priv->ch[i].napi, | |
757 | ltq_etop_poll_rx, 32); | |
758 | priv->ch[i].netdev = dev; | |
759 | } | |
760 | ||
761 | err = register_netdev(dev); | |
762 | if (err) | |
763 | goto err_free; | |
764 | ||
765 | platform_set_drvdata(pdev, dev); | |
766 | return 0; | |
767 | ||
768 | err_free: | |
cb0e51d8 | 769 | free_netdev(dev); |
504d4721 JC |
770 | err_out: |
771 | return err; | |
772 | } | |
773 | ||
a0a4efed | 774 | static int |
504d4721 JC |
775 | ltq_etop_remove(struct platform_device *pdev) |
776 | { | |
777 | struct net_device *dev = platform_get_drvdata(pdev); | |
778 | ||
779 | if (dev) { | |
780 | netif_tx_stop_all_queues(dev); | |
781 | ltq_etop_hw_exit(dev); | |
782 | ltq_etop_mdio_cleanup(dev); | |
783 | unregister_netdev(dev); | |
784 | } | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static struct platform_driver ltq_mii_driver = { | |
a0a4efed | 789 | .remove = ltq_etop_remove, |
504d4721 JC |
790 | .driver = { |
791 | .name = "ltq_etop", | |
504d4721 JC |
792 | }, |
793 | }; | |
794 | ||
795 | int __init | |
796 | init_ltq_etop(void) | |
797 | { | |
798 | int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); | |
799 | ||
800 | if (ret) | |
772301b6 | 801 | pr_err("ltq_etop: Error registering platform driver!"); |
504d4721 JC |
802 | return ret; |
803 | } | |
804 | ||
805 | static void __exit | |
806 | exit_ltq_etop(void) | |
807 | { | |
808 | platform_driver_unregister(<q_mii_driver); | |
809 | } | |
810 | ||
811 | module_init(init_ltq_etop); | |
812 | module_exit(exit_ltq_etop); | |
813 | ||
814 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); | |
815 | MODULE_DESCRIPTION("Lantiq SoC ETOP"); | |
816 | MODULE_LICENSE("GPL"); |