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net: mediatek: fix stop and wakeup of queue
[deliverable/linux.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
53void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54{
55 __raw_writel(val, eth->base + reg);
56}
57
58u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59{
60 return __raw_readl(eth->base + reg);
61}
62
63static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64{
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77}
78
79u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81{
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96}
97
98u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99{
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116}
117
118static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120{
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124}
125
126static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127{
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131}
132
133static void mtk_phy_link_adjust(struct net_device *dev)
134{
135 struct mtk_mac *mac = netdev_priv(dev);
136 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
137 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
138 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
139 MAC_MCR_BACKPR_EN;
140
141 switch (mac->phy_dev->speed) {
142 case SPEED_1000:
143 mcr |= MAC_MCR_SPEED_1000;
144 break;
145 case SPEED_100:
146 mcr |= MAC_MCR_SPEED_100;
147 break;
148 };
149
150 if (mac->phy_dev->link)
151 mcr |= MAC_MCR_FORCE_LINK;
152
153 if (mac->phy_dev->duplex)
154 mcr |= MAC_MCR_FORCE_DPX;
155
156 if (mac->phy_dev->pause)
157 mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
158
159 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
160
161 if (mac->phy_dev->link)
162 netif_carrier_on(dev);
163 else
164 netif_carrier_off(dev);
165}
166
167static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
168 struct device_node *phy_node)
169{
170 const __be32 *_addr = NULL;
171 struct phy_device *phydev;
172 int phy_mode, addr;
173
174 _addr = of_get_property(phy_node, "reg", NULL);
175
176 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
177 pr_err("%s: invalid phy address\n", phy_node->name);
178 return -EINVAL;
179 }
180 addr = be32_to_cpu(*_addr);
181 phy_mode = of_get_phy_mode(phy_node);
182 if (phy_mode < 0) {
183 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
184 return -EINVAL;
185 }
186
187 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
188 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 189 if (!phydev) {
656e7052 190 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 191 return -ENODEV;
656e7052
JC		 192 }
193
194 dev_info(eth->dev,
195 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
196 mac->id, phydev_name(phydev), phydev->phy_id,
197 phydev->drv->name);
198
199 mac->phy_dev = phydev;
200
201 return 0;
202}
203
204static int mtk_phy_connect(struct mtk_mac *mac)
205{
206 struct mtk_eth *eth = mac->hw;
207 struct device_node *np;
208 u32 val, ge_mode;
209
210 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
211 if (!np)
212 return -ENODEV;
213
214 switch (of_get_phy_mode(np)) {
215 case PHY_INTERFACE_MODE_RGMII:
216 ge_mode = 0;
217 break;
218 case PHY_INTERFACE_MODE_MII:
219 ge_mode = 1;
220 break;
221 case PHY_INTERFACE_MODE_RMII:
222 ge_mode = 2;
223 break;
224 default:
225 dev_err(eth->dev, "invalid phy_mode\n");
226 return -1;
227 }
228
229 /* put the gmac into the right mode */
230 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
231 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
232 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
233 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
234
235 mtk_phy_connect_node(eth, mac, np);
236 mac->phy_dev->autoneg = AUTONEG_ENABLE;
237 mac->phy_dev->speed = 0;
238 mac->phy_dev->duplex = 0;
239 mac->phy_dev->supported &= PHY_BASIC_FEATURES;
240 mac->phy_dev->advertising = mac->phy_dev->supported |
241 ADVERTISED_Autoneg;
242 phy_start_aneg(mac->phy_dev);
243
244 return 0;
245}
246
247static int mtk_mdio_init(struct mtk_eth *eth)
248{
249 struct device_node *mii_np;
250 int err;
251
252 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
253 if (!mii_np) {
254 dev_err(eth->dev, "no %s child node found", "mdio-bus");
255 return -ENODEV;
256 }
257
258 if (!of_device_is_available(mii_np)) {
259 err = 0;
260 goto err_put_node;
261 }
262
263 eth->mii_bus = mdiobus_alloc();
264 if (!eth->mii_bus) {
265 err = -ENOMEM;
266 goto err_put_node;
267 }
268
269 eth->mii_bus->name = "mdio";
270 eth->mii_bus->read = mtk_mdio_read;
271 eth->mii_bus->write = mtk_mdio_write;
272 eth->mii_bus->priv = eth;
273 eth->mii_bus->parent = eth->dev;
274
275 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
276 err = of_mdiobus_register(eth->mii_bus, mii_np);
277 if (err)
278 goto err_free_bus;
279
280 return 0;
281
282err_free_bus:
283 kfree(eth->mii_bus);
284
285err_put_node:
286 of_node_put(mii_np);
287 eth->mii_bus = NULL;
288 return err;
289}
290
291static void mtk_mdio_cleanup(struct mtk_eth *eth)
292{
293 if (!eth->mii_bus)
294 return;
295
296 mdiobus_unregister(eth->mii_bus);
297 of_node_put(eth->mii_bus->dev.of_node);
298 kfree(eth->mii_bus);
299}
300
301static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
302{
303 u32 val;
304
305 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
306 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
307 /* flush write */
308 mtk_r32(eth, MTK_QDMA_INT_MASK);
309}
310
311static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
312{
313 u32 val;
314
315 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
316 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
317 /* flush write */
318 mtk_r32(eth, MTK_QDMA_INT_MASK);
319}
320
321static int mtk_set_mac_address(struct net_device *dev, void *p)
322{
323 int ret = eth_mac_addr(dev, p);
324 struct mtk_mac *mac = netdev_priv(dev);
325 const char *macaddr = dev->dev_addr;
326 unsigned long flags;
327
328 if (ret)
329 return ret;
330
331 spin_lock_irqsave(&mac->hw->page_lock, flags);
332 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
333 MTK_GDMA_MAC_ADRH(mac->id));
334 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
335 (macaddr[4] << 8) | macaddr[5],
336 MTK_GDMA_MAC_ADRL(mac->id));
337 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
338
339 return 0;
340}
341
342void mtk_stats_update_mac(struct mtk_mac *mac)
343{
344 struct mtk_hw_stats *hw_stats = mac->hw_stats;
345 unsigned int base = MTK_GDM1_TX_GBCNT;
346 u64 stats;
347
348 base += hw_stats->reg_offset;
349
350 u64_stats_update_begin(&hw_stats->syncp);
351
352 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
353 stats = mtk_r32(mac->hw, base + 0x04);
354 if (stats)
355 hw_stats->rx_bytes += (stats << 32);
356 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
357 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
358 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
359 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
360 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
361 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
362 hw_stats->rx_flow_control_packets +=
363 mtk_r32(mac->hw, base + 0x24);
364 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
365 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
366 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
367 stats = mtk_r32(mac->hw, base + 0x34);
368 if (stats)
369 hw_stats->tx_bytes += (stats << 32);
370 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
371 u64_stats_update_end(&hw_stats->syncp);
372}
373
374static void mtk_stats_update(struct mtk_eth *eth)
375{
376 int i;
377
378 for (i = 0; i < MTK_MAC_COUNT; i++) {
379 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
380 continue;
381 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
382 mtk_stats_update_mac(eth->mac[i]);
383 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
384 }
385 }
386}
387
388static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
389 struct rtnl_link_stats64 *storage)
390{
391 struct mtk_mac *mac = netdev_priv(dev);
392 struct mtk_hw_stats *hw_stats = mac->hw_stats;
393 unsigned int start;
394
395 if (netif_running(dev) && netif_device_present(dev)) {
396 if (spin_trylock(&hw_stats->stats_lock)) {
397 mtk_stats_update_mac(mac);
398 spin_unlock(&hw_stats->stats_lock);
399 }
400 }
401
402 do {
403 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
404 storage->rx_packets = hw_stats->rx_packets;
405 storage->tx_packets = hw_stats->tx_packets;
406 storage->rx_bytes = hw_stats->rx_bytes;
407 storage->tx_bytes = hw_stats->tx_bytes;
408 storage->collisions = hw_stats->tx_collisions;
409 storage->rx_length_errors = hw_stats->rx_short_errors +
410 hw_stats->rx_long_errors;
411 storage->rx_over_errors = hw_stats->rx_overflow;
412 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
413 storage->rx_errors = hw_stats->rx_checksum_errors;
414 storage->tx_aborted_errors = hw_stats->tx_skip;
415 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
416
417 storage->tx_errors = dev->stats.tx_errors;
418 storage->rx_dropped = dev->stats.rx_dropped;
419 storage->tx_dropped = dev->stats.tx_dropped;
420
421 return storage;
422}
423
424static inline int mtk_max_frag_size(int mtu)
425{
426 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
427 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
428 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
429
430 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
431 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
432}
433
434static inline int mtk_max_buf_size(int frag_size)
435{
436 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
437 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
438
439 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
440
441 return buf_size;
442}
443
444static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
445 struct mtk_rx_dma *dma_rxd)
446{
447 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
448 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
449 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
450 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
451}
452
453/* the qdma core needs scratch memory to be setup */
454static int mtk_init_fq_dma(struct mtk_eth *eth)
455{
6aab1a62 456 dma_addr_t phy_ring_head, phy_ring_tail;
656e7052
JC		 457 int cnt = MTK_DMA_SIZE;
458 dma_addr_t dma_addr;
459 int i;
460
461 eth->scratch_ring = dma_alloc_coherent(eth->dev,
462 cnt * sizeof(struct mtk_tx_dma),
463 &phy_ring_head,
464 GFP_ATOMIC | __GFP_ZERO);
465 if (unlikely(!eth->scratch_ring))
466 return -ENOMEM;
467
468 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
469 GFP_KERNEL);
470 dma_addr = dma_map_single(eth->dev,
471 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
472 DMA_FROM_DEVICE);
473 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
474 return -ENOMEM;
475
476 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
477 phy_ring_tail = phy_ring_head +
478 (sizeof(struct mtk_tx_dma) * (cnt - 1));
479
480 for (i = 0; i < cnt; i++) {
481 eth->scratch_ring[i].txd1 =
482 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
483 if (i < cnt - 1)
484 eth->scratch_ring[i].txd2 = (phy_ring_head +
485 ((i + 1) * sizeof(struct mtk_tx_dma)));
486 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
487 }
488
489 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
490 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
491 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
492 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
493
494 return 0;
495}
496
497static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
498{
499 void *ret = ring->dma;
500
501 return ret + (desc - ring->phys);
502}
503
504static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
505 struct mtk_tx_dma *txd)
506{
507 int idx = txd - ring->dma;
508
509 return &ring->buf[idx];
510}
511
512static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
513{
514 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
515 dma_unmap_single(dev,
516 dma_unmap_addr(tx_buf, dma_addr0),
517 dma_unmap_len(tx_buf, dma_len0),
518 DMA_TO_DEVICE);
519 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
520 dma_unmap_page(dev,
521 dma_unmap_addr(tx_buf, dma_addr0),
522 dma_unmap_len(tx_buf, dma_len0),
523 DMA_TO_DEVICE);
524 }
525 tx_buf->flags = 0;
526 if (tx_buf->skb &&
527 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
528 dev_kfree_skb_any(tx_buf->skb);
529 tx_buf->skb = NULL;
530}
531
532static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
533 int tx_num, struct mtk_tx_ring *ring, bool gso)
534{
535 struct mtk_mac *mac = netdev_priv(dev);
536 struct mtk_eth *eth = mac->hw;
537 struct mtk_tx_dma *itxd, *txd;
538 struct mtk_tx_buf *tx_buf;
539 unsigned long flags;
540 dma_addr_t mapped_addr;
541 unsigned int nr_frags;
542 int i, n_desc = 1;
543 u32 txd4 = 0;
544
545 itxd = ring->next_free;
546 if (itxd == ring->last_free)
547 return -ENOMEM;
548
549 /* set the forward port */
550 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
551
552 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
553 memset(tx_buf, 0, sizeof(*tx_buf));
554
555 if (gso)
556 txd4 |= TX_DMA_TSO;
557
558 /* TX Checksum offload */
559 if (skb->ip_summed == CHECKSUM_PARTIAL)
560 txd4 |= TX_DMA_CHKSUM;
561
562 /* VLAN header offload */
563 if (skb_vlan_tag_present(skb))
564 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
565
566 mapped_addr = dma_map_single(&dev->dev, skb->data,
567 skb_headlen(skb), DMA_TO_DEVICE);
568 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
569 return -ENOMEM;
570
571 /* normally we can rely on the stack not calling this more than once,
572 * however we have 2 queues running ont he same ring so we need to lock
573 * the ring access
574 */
575 spin_lock_irqsave(&eth->page_lock, flags);
576 WRITE_ONCE(itxd->txd1, mapped_addr);
577 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
578 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
579 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
580
581 /* TX SG offload */
582 txd = itxd;
583 nr_frags = skb_shinfo(skb)->nr_frags;
584 for (i = 0; i < nr_frags; i++) {
585 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
586 unsigned int offset = 0;
587 int frag_size = skb_frag_size(frag);
588
589 while (frag_size) {
590 bool last_frag = false;
591 unsigned int frag_map_size;
592
593 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
594 if (txd == ring->last_free)
595 goto err_dma;
596
597 n_desc++;
598 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
599 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
600 frag_map_size,
601 DMA_TO_DEVICE);
602 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
603 goto err_dma;
604
605 if (i == nr_frags - 1 &&
606 (frag_size - frag_map_size) == 0)
607 last_frag = true;
608
609 WRITE_ONCE(txd->txd1, mapped_addr);
610 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
611 TX_DMA_PLEN0(frag_map_size) |
612 last_frag * TX_DMA_LS0) |
613 mac->id);
614 WRITE_ONCE(txd->txd4, 0);
615
616 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
617 tx_buf = mtk_desc_to_tx_buf(ring, txd);
618 memset(tx_buf, 0, sizeof(*tx_buf));
619
620 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
621 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
622 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
623 frag_size -= frag_map_size;
624 offset += frag_map_size;
625 }
626 }
627
628 /* store skb to cleanup */
629 tx_buf->skb = skb;
630
631 WRITE_ONCE(itxd->txd4, txd4);
632 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
633 (!nr_frags * TX_DMA_LS0)));
634
635 spin_unlock_irqrestore(&eth->page_lock, flags);
636
637 netdev_sent_queue(dev, skb->len);
638 skb_tx_timestamp(skb);
639
640 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
641 atomic_sub(n_desc, &ring->free_count);
642
643 /* make sure that all changes to the dma ring are flushed before we
644 * continue
645 */
646 wmb();
647
648 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
649 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
650
651 return 0;
652
653err_dma:
654 do {
655 tx_buf = mtk_desc_to_tx_buf(ring, txd);
656
657 /* unmap dma */
658 mtk_tx_unmap(&dev->dev, tx_buf);
659
660 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
661 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
662 } while (itxd != txd);
663
48e77422
DC		 664 spin_unlock_irqrestore(&eth->page_lock, flags);
665
656e7052
JC		 666 return -ENOMEM;
667}
668
669static inline int mtk_cal_txd_req(struct sk_buff *skb)
670{
671 int i, nfrags;
672 struct skb_frag_struct *frag;
673
674 nfrags = 1;
675 if (skb_is_gso(skb)) {
676 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
677 frag = &skb_shinfo(skb)->frags[i];
678 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
679 }
680 } else {
681 nfrags += skb_shinfo(skb)->nr_frags;
682 }
683
beeb4ca4 684 return nfrags;
656e7052
JC		 685}
686
13c822f6
JC		 687static void mtk_wake_queue(struct mtk_eth *eth)
688{
689 int i;
690
691 for (i = 0; i < MTK_MAC_COUNT; i++) {
692 if (!eth->netdev[i])
693 continue;
694 netif_wake_queue(eth->netdev[i]);
695 }
696}
697
698static void mtk_stop_queue(struct mtk_eth *eth)
699{
700 int i;
701
702 for (i = 0; i < MTK_MAC_COUNT; i++) {
703 if (!eth->netdev[i])
704 continue;
705 netif_stop_queue(eth->netdev[i]);
706 }
707}
708
656e7052
JC		 709static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
710{
711 struct mtk_mac *mac = netdev_priv(dev);
712 struct mtk_eth *eth = mac->hw;
713 struct mtk_tx_ring *ring = &eth->tx_ring;
714 struct net_device_stats *stats = &dev->stats;
715 bool gso = false;
716 int tx_num;
717
718 tx_num = mtk_cal_txd_req(skb);
719 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 720 mtk_stop_queue(eth);
656e7052
JC		 721 netif_err(eth, tx_queued, dev,
722 "Tx Ring full when queue awake!\n");
723 return NETDEV_TX_BUSY;
724 }
725
726 /* TSO: fill MSS info in tcp checksum field */
727 if (skb_is_gso(skb)) {
728 if (skb_cow_head(skb, 0)) {
729 netif_warn(eth, tx_err, dev,
730 "GSO expand head fail.\n");
731 goto drop;
732 }
733
734 if (skb_shinfo(skb)->gso_type &
735 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
736 gso = true;
737 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
738 }
739 }
740
741 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
742 goto drop;
743
744 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
13c822f6 745 mtk_stop_queue(eth);
656e7052
JC		 746 if (unlikely(atomic_read(&ring->free_count) >
747 ring->thresh))
13c822f6 748 mtk_wake_queue(eth);
656e7052
JC		 749 }
750
751 return NETDEV_TX_OK;
752
753drop:
754 stats->tx_dropped++;
755 dev_kfree_skb(skb);
756 return NETDEV_TX_OK;
757}
758
759static int mtk_poll_rx(struct napi_struct *napi, int budget,
760 struct mtk_eth *eth, u32 rx_intr)
761{
762 struct mtk_rx_ring *ring = &eth->rx_ring;
763 int idx = ring->calc_idx;
764 struct sk_buff *skb;
765 u8 *data, *new_data;
766 struct mtk_rx_dma *rxd, trxd;
767 int done = 0;
768
769 while (done < budget) {
770 struct net_device *netdev;
771 unsigned int pktlen;
772 dma_addr_t dma_addr;
773 int mac = 0;
774
775 idx = NEXT_RX_DESP_IDX(idx);
776 rxd = &ring->dma[idx];
777 data = ring->data[idx];
778
779 mtk_rx_get_desc(&trxd, rxd);
780 if (!(trxd.rxd2 & RX_DMA_DONE))
781 break;
782
783 /* find out which mac the packet come from. values start at 1 */
784 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
785 RX_DMA_FPORT_MASK;
786 mac--;
787
788 netdev = eth->netdev[mac];
789
790 /* alloc new buffer */
791 new_data = napi_alloc_frag(ring->frag_size);
792 if (unlikely(!new_data)) {
793 netdev->stats.rx_dropped++;
794 goto release_desc;
795 }
796 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
797 new_data + NET_SKB_PAD,
798 ring->buf_size,
799 DMA_FROM_DEVICE);
800 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
801 skb_free_frag(new_data);
802 goto release_desc;
803 }
804
805 /* receive data */
806 skb = build_skb(data, ring->frag_size);
807 if (unlikely(!skb)) {
808 put_page(virt_to_head_page(new_data));
809 goto release_desc;
810 }
811 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
812
813 dma_unmap_single(&netdev->dev, trxd.rxd1,
814 ring->buf_size, DMA_FROM_DEVICE);
815 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
816 skb->dev = netdev;
817 skb_put(skb, pktlen);
818 if (trxd.rxd4 & RX_DMA_L4_VALID)
819 skb->ip_summed = CHECKSUM_UNNECESSARY;
820 else
821 skb_checksum_none_assert(skb);
822 skb->protocol = eth_type_trans(skb, netdev);
823
824 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
825 RX_DMA_VID(trxd.rxd3))
826 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
827 RX_DMA_VID(trxd.rxd3));
828 napi_gro_receive(napi, skb);
829
830 ring->data[idx] = new_data;
831 rxd->rxd1 = (unsigned int)dma_addr;
832
833release_desc:
834 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
835
836 ring->calc_idx = idx;
837 /* make sure that all changes to the dma ring are flushed before
838 * we continue
839 */
840 wmb();
841 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
842 done++;
843 }
844
845 if (done < budget)
846 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
847
848 return done;
849}
850
851static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
852{
853 struct mtk_tx_ring *ring = &eth->tx_ring;
854 struct mtk_tx_dma *desc;
855 struct sk_buff *skb;
856 struct mtk_tx_buf *tx_buf;
857 int total = 0, done[MTK_MAX_DEVS];
858 unsigned int bytes[MTK_MAX_DEVS];
859 u32 cpu, dma;
860 static int condition;
861 int i;
862
863 memset(done, 0, sizeof(done));
864 memset(bytes, 0, sizeof(bytes));
865
866 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
867 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
868
869 desc = mtk_qdma_phys_to_virt(ring, cpu);
870
871 while ((cpu != dma) && budget) {
872 u32 next_cpu = desc->txd2;
873 int mac;
874
875 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
876 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
877 break;
878
879 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
880 TX_DMA_FPORT_MASK;
881 mac--;
882
883 tx_buf = mtk_desc_to_tx_buf(ring, desc);
884 skb = tx_buf->skb;
885 if (!skb) {
886 condition = 1;
887 break;
888 }
889
890 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
891 bytes[mac] += skb->len;
892 done[mac]++;
893 budget--;
894 }
895 mtk_tx_unmap(eth->dev, tx_buf);
896
897 ring->last_free->txd2 = next_cpu;
898 ring->last_free = desc;
899 atomic_inc(&ring->free_count);
900
901 cpu = next_cpu;
902 }
903
904 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
905
906 for (i = 0; i < MTK_MAC_COUNT; i++) {
907 if (!eth->netdev[i] || !done[i])
908 continue;
909 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
910 total += done[i];
911 }
912
913 /* read hw index again make sure no new tx packet */
914 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
915 *tx_again = true;
916 else
917 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
918
919 if (!total)
920 return 0;
921
13c822f6
JC		 922 if (atomic_read(&ring->free_count) > ring->thresh)
923 mtk_wake_queue(eth);
656e7052
JC		 924
925 return total;
926}
927
928static int mtk_poll(struct napi_struct *napi, int budget)
929{
930 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
931 u32 status, status2, mask, tx_intr, rx_intr, status_intr;
932 int tx_done, rx_done;
933 bool tx_again = false;
934
935 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
936 status2 = mtk_r32(eth, MTK_INT_STATUS2);
937 tx_intr = MTK_TX_DONE_INT;
938 rx_intr = MTK_RX_DONE_INT;
939 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
940 tx_done = 0;
941 rx_done = 0;
942 tx_again = 0;
943
944 if (status & tx_intr)
945 tx_done = mtk_poll_tx(eth, budget, &tx_again);
946
947 if (status & rx_intr)
948 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
949
950 if (unlikely(status2 & status_intr)) {
951 mtk_stats_update(eth);
952 mtk_w32(eth, status_intr, MTK_INT_STATUS2);
953 }
954
955 if (unlikely(netif_msg_intr(eth))) {
956 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
957 netdev_info(eth->netdev[0],
958 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
959 tx_done, rx_done, status, mask);
960 }
961
962 if (tx_again || rx_done == budget)
963 return budget;
964
965 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
966 if (status & (tx_intr | rx_intr))
967 return budget;
968
969 napi_complete(napi);
970 mtk_irq_enable(eth, tx_intr | rx_intr);
971
972 return rx_done;
973}
974
975static int mtk_tx_alloc(struct mtk_eth *eth)
976{
977 struct mtk_tx_ring *ring = &eth->tx_ring;
978 int i, sz = sizeof(*ring->dma);
979
980 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
981 GFP_KERNEL);
982 if (!ring->buf)
983 goto no_tx_mem;
984
985 ring->dma = dma_alloc_coherent(eth->dev,
986 MTK_DMA_SIZE * sz,
987 &ring->phys,
988 GFP_ATOMIC | __GFP_ZERO);
989 if (!ring->dma)
990 goto no_tx_mem;
991
992 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
993 for (i = 0; i < MTK_DMA_SIZE; i++) {
994 int next = (i + 1) % MTK_DMA_SIZE;
995 u32 next_ptr = ring->phys + next * sz;
996
997 ring->dma[i].txd2 = next_ptr;
998 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
999 }
1000
1001 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1002 ring->next_free = &ring->dma[0];
1003 ring->last_free = &ring->dma[MTK_DMA_SIZE - 2];
1004 ring->thresh = max((unsigned long)MTK_DMA_SIZE >> 2,
1005 MAX_SKB_FRAGS);
1006
1007 /* make sure that all changes to the dma ring are flushed before we
1008 * continue
1009 */
1010 wmb();
1011
1012 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1013 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1014 mtk_w32(eth,
1015 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1016 MTK_QTX_CRX_PTR);
1017 mtk_w32(eth,
1018 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1019 MTK_QTX_DRX_PTR);
1020
1021 return 0;
1022
1023no_tx_mem:
1024 return -ENOMEM;
1025}
1026
1027static void mtk_tx_clean(struct mtk_eth *eth)
1028{
1029 struct mtk_tx_ring *ring = &eth->tx_ring;
1030 int i;
1031
1032 if (ring->buf) {
1033 for (i = 0; i < MTK_DMA_SIZE; i++)
1034 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1035 kfree(ring->buf);
1036 ring->buf = NULL;
1037 }
1038
1039 if (ring->dma) {
1040 dma_free_coherent(eth->dev,
1041 MTK_DMA_SIZE * sizeof(*ring->dma),
1042 ring->dma,
1043 ring->phys);
1044 ring->dma = NULL;
1045 }
1046}
1047
1048static int mtk_rx_alloc(struct mtk_eth *eth)
1049{
1050 struct mtk_rx_ring *ring = &eth->rx_ring;
1051 int i;
1052
1053 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1054 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1055 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1056 GFP_KERNEL);
1057 if (!ring->data)
1058 return -ENOMEM;
1059
1060 for (i = 0; i < MTK_DMA_SIZE; i++) {
1061 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1062 if (!ring->data[i])
1063 return -ENOMEM;
1064 }
1065
1066 ring->dma = dma_alloc_coherent(eth->dev,
1067 MTK_DMA_SIZE * sizeof(*ring->dma),
1068 &ring->phys,
1069 GFP_ATOMIC | __GFP_ZERO);
1070 if (!ring->dma)
1071 return -ENOMEM;
1072
1073 for (i = 0; i < MTK_DMA_SIZE; i++) {
1074 dma_addr_t dma_addr = dma_map_single(eth->dev,
1075 ring->data[i] + NET_SKB_PAD,
1076 ring->buf_size,
1077 DMA_FROM_DEVICE);
1078 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1079 return -ENOMEM;
1080 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1081
1082 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1083 }
1084 ring->calc_idx = MTK_DMA_SIZE - 1;
1085 /* make sure that all changes to the dma ring are flushed before we
1086 * continue
1087 */
1088 wmb();
1089
1090 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1091 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1092 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1093 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1094 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1095
1096 return 0;
1097}
1098
1099static void mtk_rx_clean(struct mtk_eth *eth)
1100{
1101 struct mtk_rx_ring *ring = &eth->rx_ring;
1102 int i;
1103
1104 if (ring->data && ring->dma) {
1105 for (i = 0; i < MTK_DMA_SIZE; i++) {
1106 if (!ring->data[i])
1107 continue;
1108 if (!ring->dma[i].rxd1)
1109 continue;
1110 dma_unmap_single(eth->dev,
1111 ring->dma[i].rxd1,
1112 ring->buf_size,
1113 DMA_FROM_DEVICE);
1114 skb_free_frag(ring->data[i]);
1115 }
1116 kfree(ring->data);
1117 ring->data = NULL;
1118 }
1119
1120 if (ring->dma) {
1121 dma_free_coherent(eth->dev,
1122 MTK_DMA_SIZE * sizeof(*ring->dma),
1123 ring->dma,
1124 ring->phys);
1125 ring->dma = NULL;
1126 }
1127}
1128
1129/* wait for DMA to finish whatever it is doing before we start using it again */
1130static int mtk_dma_busy_wait(struct mtk_eth *eth)
1131{
1132 unsigned long t_start = jiffies;
1133
1134 while (1) {
1135 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1136 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1137 return 0;
1138 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1139 break;
1140 }
1141
1142 dev_err(eth->dev, "DMA init timeout\n");
1143 return -1;
1144}
1145
1146static int mtk_dma_init(struct mtk_eth *eth)
1147{
1148 int err;
1149
1150 if (mtk_dma_busy_wait(eth))
1151 return -EBUSY;
1152
1153 /* QDMA needs scratch memory for internal reordering of the
1154 * descriptors
1155 */
1156 err = mtk_init_fq_dma(eth);
1157 if (err)
1158 return err;
1159
1160 err = mtk_tx_alloc(eth);
1161 if (err)
1162 return err;
1163
1164 err = mtk_rx_alloc(eth);
1165 if (err)
1166 return err;
1167
1168 /* Enable random early drop and set drop threshold automatically */
1169 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1170 MTK_QDMA_FC_THRES);
1171 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1172
1173 return 0;
1174}
1175
1176static void mtk_dma_free(struct mtk_eth *eth)
1177{
1178 int i;
1179
1180 for (i = 0; i < MTK_MAC_COUNT; i++)
1181 if (eth->netdev[i])
1182 netdev_reset_queue(eth->netdev[i]);
1183 mtk_tx_clean(eth);
1184 mtk_rx_clean(eth);
1185 kfree(eth->scratch_head);
1186}
1187
1188static void mtk_tx_timeout(struct net_device *dev)
1189{
1190 struct mtk_mac *mac = netdev_priv(dev);
1191 struct mtk_eth *eth = mac->hw;
1192
1193 eth->netdev[mac->id]->stats.tx_errors++;
1194 netif_err(eth, tx_err, dev,
1195 "transmit timed out\n");
1196 schedule_work(&mac->pending_work);
1197}
1198
1199static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1200{
1201 struct mtk_eth *eth = _eth;
1202 u32 status;
1203
1204 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1205 if (unlikely(!status))
1206 return IRQ_NONE;
1207
1208 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
1209 if (likely(napi_schedule_prep(&eth->rx_napi)))
1210 __napi_schedule(&eth->rx_napi);
1211 } else {
1212 mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
1213 }
1214 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
1215
1216 return IRQ_HANDLED;
1217}
1218
1219#ifdef CONFIG_NET_POLL_CONTROLLER
1220static void mtk_poll_controller(struct net_device *dev)
1221{
1222 struct mtk_mac *mac = netdev_priv(dev);
1223 struct mtk_eth *eth = mac->hw;
1224 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1225
1226 mtk_irq_disable(eth, int_mask);
1227 mtk_handle_irq(dev->irq, dev);
1228 mtk_irq_enable(eth, int_mask);
1229}
1230#endif
1231
1232static int mtk_start_dma(struct mtk_eth *eth)
1233{
1234 int err;
1235
1236 err = mtk_dma_init(eth);
1237 if (err) {
1238 mtk_dma_free(eth);
1239 return err;
1240 }
1241
1242 mtk_w32(eth,
1243 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1244 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1245 MTK_RX_BT_32DWORDS,
1246 MTK_QDMA_GLO_CFG);
1247
1248 return 0;
1249}
1250
1251static int mtk_open(struct net_device *dev)
1252{
1253 struct mtk_mac *mac = netdev_priv(dev);
1254 struct mtk_eth *eth = mac->hw;
1255
1256 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1257 if (!atomic_read(&eth->dma_refcnt)) {
1258 int err = mtk_start_dma(eth);
1259
1260 if (err)
1261 return err;
1262
1263 napi_enable(&eth->rx_napi);
1264 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1265 }
1266 atomic_inc(&eth->dma_refcnt);
1267
1268 phy_start(mac->phy_dev);
1269 netif_start_queue(dev);
1270
1271 return 0;
1272}
1273
1274static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1275{
1276 unsigned long flags;
1277 u32 val;
1278 int i;
1279
1280 /* stop the dma engine */
1281 spin_lock_irqsave(&eth->page_lock, flags);
1282 val = mtk_r32(eth, glo_cfg);
1283 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1284 glo_cfg);
1285 spin_unlock_irqrestore(&eth->page_lock, flags);
1286
1287 /* wait for dma stop */
1288 for (i = 0; i < 10; i++) {
1289 val = mtk_r32(eth, glo_cfg);
1290 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1291 msleep(20);
1292 continue;
1293 }
1294 break;
1295 }
1296}
1297
1298static int mtk_stop(struct net_device *dev)
1299{
1300 struct mtk_mac *mac = netdev_priv(dev);
1301 struct mtk_eth *eth = mac->hw;
1302
1303 netif_tx_disable(dev);
1304 phy_stop(mac->phy_dev);
1305
1306 /* only shutdown DMA if this is the last user */
1307 if (!atomic_dec_and_test(&eth->dma_refcnt))
1308 return 0;
1309
1310 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1311 napi_disable(&eth->rx_napi);
1312
1313 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1314
1315 mtk_dma_free(eth);
1316
1317 return 0;
1318}
1319
1320static int __init mtk_hw_init(struct mtk_eth *eth)
1321{
1322 int err, i;
1323
1324 /* reset the frame engine */
1325 reset_control_assert(eth->rstc);
1326 usleep_range(10, 20);
1327 reset_control_deassert(eth->rstc);
1328 usleep_range(10, 20);
1329
1330 /* Set GE2 driving and slew rate */
1331 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1332
1333 /* set GE2 TDSEL */
1334 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1335
1336 /* set GE2 TUNE */
1337 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1338
1339 /* GE1, Force 1000M/FD, FC ON */
1340 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1341
1342 /* GE2, Force 1000M/FD, FC ON */
1343 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1344
1345 /* Enable RX VLan Offloading */
1346 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1347
1348 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1349 dev_name(eth->dev), eth);
1350 if (err)
1351 return err;
1352
1353 err = mtk_mdio_init(eth);
1354 if (err)
1355 return err;
1356
1357 /* disable delay and normal interrupt */
1358 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1359 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1360 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1361 mtk_w32(eth, 0, MTK_RST_GL);
1362
1363 /* FE int grouping */
1364 mtk_w32(eth, 0, MTK_FE_INT_GRP);
1365
1366 for (i = 0; i < 2; i++) {
1367 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1368
1369 /* setup the forward port to send frame to QDMA */
1370 val &= ~0xffff;
1371 val |= 0x5555;
1372
1373 /* Enable RX checksum */
1374 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1375
1376 /* setup the mac dma */
1377 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1378 }
1379
1380 return 0;
1381}
1382
1383static int __init mtk_init(struct net_device *dev)
1384{
1385 struct mtk_mac *mac = netdev_priv(dev);
1386 struct mtk_eth *eth = mac->hw;
1387 const char *mac_addr;
1388
1389 mac_addr = of_get_mac_address(mac->of_node);
1390 if (mac_addr)
1391 ether_addr_copy(dev->dev_addr, mac_addr);
1392
1393 /* If the mac address is invalid, use random mac address */
1394 if (!is_valid_ether_addr(dev->dev_addr)) {
1395 random_ether_addr(dev->dev_addr);
1396 dev_err(eth->dev, "generated random MAC address %pM\n",
1397 dev->dev_addr);
1398 dev->addr_assign_type = NET_ADDR_RANDOM;
1399 }
1400
1401 return mtk_phy_connect(mac);
1402}
1403
1404static void mtk_uninit(struct net_device *dev)
1405{
1406 struct mtk_mac *mac = netdev_priv(dev);
1407 struct mtk_eth *eth = mac->hw;
1408
1409 phy_disconnect(mac->phy_dev);
1410 mtk_mdio_cleanup(eth);
1411 mtk_irq_disable(eth, ~0);
1412 free_irq(dev->irq, dev);
1413}
1414
1415static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1416{
1417 struct mtk_mac *mac = netdev_priv(dev);
1418
1419 switch (cmd) {
1420 case SIOCGMIIPHY:
1421 case SIOCGMIIREG:
1422 case SIOCSMIIREG:
1423 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1424 default:
1425 break;
1426 }
1427
1428 return -EOPNOTSUPP;
1429}
1430
1431static void mtk_pending_work(struct work_struct *work)
1432{
1433 struct mtk_mac *mac = container_of(work, struct mtk_mac, pending_work);
1434 struct mtk_eth *eth = mac->hw;
1435 struct net_device *dev = eth->netdev[mac->id];
1436 int err;
1437
1438 rtnl_lock();
1439 mtk_stop(dev);
1440
1441 err = mtk_open(dev);
1442 if (err) {
1443 netif_alert(eth, ifup, dev,
1444 "Driver up/down cycle failed, closing device.\n");
1445 dev_close(dev);
1446 }
1447 rtnl_unlock();
1448}
1449
1450static int mtk_cleanup(struct mtk_eth *eth)
1451{
1452 int i;
1453
1454 for (i = 0; i < MTK_MAC_COUNT; i++) {
1455 struct mtk_mac *mac = netdev_priv(eth->netdev[i]);
1456
1457 if (!eth->netdev[i])
1458 continue;
1459
1460 unregister_netdev(eth->netdev[i]);
1461 free_netdev(eth->netdev[i]);
1462 cancel_work_sync(&mac->pending_work);
1463 }
1464
1465 return 0;
1466}
1467
1468static int mtk_get_settings(struct net_device *dev,
1469 struct ethtool_cmd *cmd)
1470{
1471 struct mtk_mac *mac = netdev_priv(dev);
1472 int err;
1473
1474 err = phy_read_status(mac->phy_dev);
1475 if (err)
1476 return -ENODEV;
1477
1478 return phy_ethtool_gset(mac->phy_dev, cmd);
1479}
1480
1481static int mtk_set_settings(struct net_device *dev,
1482 struct ethtool_cmd *cmd)
1483{
1484 struct mtk_mac *mac = netdev_priv(dev);
1485
1486 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1487 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1488 cmd->phy_address);
1489 if (!mac->phy_dev)
1490 return -ENODEV;
1491 }
1492
1493 return phy_ethtool_sset(mac->phy_dev, cmd);
1494}
1495
1496static void mtk_get_drvinfo(struct net_device *dev,
1497 struct ethtool_drvinfo *info)
1498{
1499 struct mtk_mac *mac = netdev_priv(dev);
1500
1501 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1502 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1503 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1504}
1505
1506static u32 mtk_get_msglevel(struct net_device *dev)
1507{
1508 struct mtk_mac *mac = netdev_priv(dev);
1509
1510 return mac->hw->msg_enable;
1511}
1512
1513static void mtk_set_msglevel(struct net_device *dev, u32 value)
1514{
1515 struct mtk_mac *mac = netdev_priv(dev);
1516
1517 mac->hw->msg_enable = value;
1518}
1519
1520static int mtk_nway_reset(struct net_device *dev)
1521{
1522 struct mtk_mac *mac = netdev_priv(dev);
1523
1524 return genphy_restart_aneg(mac->phy_dev);
1525}
1526
1527static u32 mtk_get_link(struct net_device *dev)
1528{
1529 struct mtk_mac *mac = netdev_priv(dev);
1530 int err;
1531
1532 err = genphy_update_link(mac->phy_dev);
1533 if (err)
1534 return ethtool_op_get_link(dev);
1535
1536 return mac->phy_dev->link;
1537}
1538
1539static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1540{
1541 int i;
1542
1543 switch (stringset) {
1544 case ETH_SS_STATS:
1545 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1546 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1547 data += ETH_GSTRING_LEN;
1548 }
1549 break;
1550 }
1551}
1552
1553static int mtk_get_sset_count(struct net_device *dev, int sset)
1554{
1555 switch (sset) {
1556 case ETH_SS_STATS:
1557 return ARRAY_SIZE(mtk_ethtool_stats);
1558 default:
1559 return -EOPNOTSUPP;
1560 }
1561}
1562
1563static void mtk_get_ethtool_stats(struct net_device *dev,
1564 struct ethtool_stats *stats, u64 *data)
1565{
1566 struct mtk_mac *mac = netdev_priv(dev);
1567 struct mtk_hw_stats *hwstats = mac->hw_stats;
1568 u64 *data_src, *data_dst;
1569 unsigned int start;
1570 int i;
1571
1572 if (netif_running(dev) && netif_device_present(dev)) {
1573 if (spin_trylock(&hwstats->stats_lock)) {
1574 mtk_stats_update_mac(mac);
1575 spin_unlock(&hwstats->stats_lock);
1576 }
1577 }
1578
1579 do {
1580 data_src = (u64*)hwstats;
1581 data_dst = data;
1582 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1583
1584 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1585 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1586 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1587}
1588
1589static struct ethtool_ops mtk_ethtool_ops = {
1590 .get_settings = mtk_get_settings,
1591 .set_settings = mtk_set_settings,
1592 .get_drvinfo = mtk_get_drvinfo,
1593 .get_msglevel = mtk_get_msglevel,
1594 .set_msglevel = mtk_set_msglevel,
1595 .nway_reset = mtk_nway_reset,
1596 .get_link = mtk_get_link,
1597 .get_strings = mtk_get_strings,
1598 .get_sset_count = mtk_get_sset_count,
1599 .get_ethtool_stats = mtk_get_ethtool_stats,
1600};
1601
1602static const struct net_device_ops mtk_netdev_ops = {
1603 .ndo_init = mtk_init,
1604 .ndo_uninit = mtk_uninit,
1605 .ndo_open = mtk_open,
1606 .ndo_stop = mtk_stop,
1607 .ndo_start_xmit = mtk_start_xmit,
1608 .ndo_set_mac_address = mtk_set_mac_address,
1609 .ndo_validate_addr = eth_validate_addr,
1610 .ndo_do_ioctl = mtk_do_ioctl,
1611 .ndo_change_mtu = eth_change_mtu,
1612 .ndo_tx_timeout = mtk_tx_timeout,
1613 .ndo_get_stats64 = mtk_get_stats64,
1614#ifdef CONFIG_NET_POLL_CONTROLLER
1615 .ndo_poll_controller = mtk_poll_controller,
1616#endif
1617};
1618
1619static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1620{
1621 struct mtk_mac *mac;
1622 const __be32 *_id = of_get_property(np, "reg", NULL);
1623 int id, err;
1624
1625 if (!_id) {
1626 dev_err(eth->dev, "missing mac id\n");
1627 return -EINVAL;
1628 }
1629
1630 id = be32_to_cpup(_id);
1631 if (id >= MTK_MAC_COUNT) {
1632 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1633 return -EINVAL;
1634 }
1635
1636 if (eth->netdev[id]) {
1637 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1638 return -EINVAL;
1639 }
1640
1641 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1642 if (!eth->netdev[id]) {
1643 dev_err(eth->dev, "alloc_etherdev failed\n");
1644 return -ENOMEM;
1645 }
1646 mac = netdev_priv(eth->netdev[id]);
1647 eth->mac[id] = mac;
1648 mac->id = id;
1649 mac->hw = eth;
1650 mac->of_node = np;
1651 INIT_WORK(&mac->pending_work, mtk_pending_work);
1652
1653 mac->hw_stats = devm_kzalloc(eth->dev,
1654 sizeof(*mac->hw_stats),
1655 GFP_KERNEL);
1656 if (!mac->hw_stats) {
1657 dev_err(eth->dev, "failed to allocate counter memory\n");
1658 err = -ENOMEM;
1659 goto free_netdev;
1660 }
1661 spin_lock_init(&mac->hw_stats->stats_lock);
1662 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1663
1664 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
82500aa0 1665 eth->netdev[id]->watchdog_timeo = HZ;
656e7052
JC		 1666 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1667 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1668 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1669 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1670 eth->netdev[id]->features |= MTK_HW_FEATURES;
1671 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1672
1673 err = register_netdev(eth->netdev[id]);
1674 if (err) {
1675 dev_err(eth->dev, "error bringing up device\n");
1676 goto free_netdev;
1677 }
1678 eth->netdev[id]->irq = eth->irq;
1679 netif_info(eth, probe, eth->netdev[id],
1680 "mediatek frame engine at 0x%08lx, irq %d\n",
1681 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
1682
1683 return 0;
1684
1685free_netdev:
1686 free_netdev(eth->netdev[id]);
1687 return err;
1688}
1689
1690static int mtk_probe(struct platform_device *pdev)
1691{
1692 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1693 struct device_node *mac_np;
1694 const struct of_device_id *match;
1695 struct mtk_soc_data *soc;
1696 struct mtk_eth *eth;
1697 int err;
1698
656e7052
JC		 1699 match = of_match_device(of_mtk_match, &pdev->dev);
1700 soc = (struct mtk_soc_data *)match->data;
1701
1702 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1703 if (!eth)
1704 return -ENOMEM;
1705
1706 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1707 if (IS_ERR(eth->base))
1708 return PTR_ERR(eth->base);
656e7052
JC		 1709
1710 spin_lock_init(&eth->page_lock);
1711
1712 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1713 "mediatek,ethsys");
1714 if (IS_ERR(eth->ethsys)) {
1715 dev_err(&pdev->dev, "no ethsys regmap found\n");
1716 return PTR_ERR(eth->ethsys);
1717 }
1718
1719 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1720 "mediatek,pctl");
1721 if (IS_ERR(eth->pctl)) {
1722 dev_err(&pdev->dev, "no pctl regmap found\n");
1723 return PTR_ERR(eth->pctl);
1724 }
1725
1726 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1727 if (IS_ERR(eth->rstc)) {
1728 dev_err(&pdev->dev, "no eth reset found\n");
1729 return PTR_ERR(eth->rstc);
1730 }
1731
1732 eth->irq = platform_get_irq(pdev, 0);
1733 if (eth->irq < 0) {
1734 dev_err(&pdev->dev, "no IRQ resource found\n");
1735 return -ENXIO;
1736 }
1737
1738 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1739 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1740 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1741 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1742 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1743 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1744 return -ENODEV;
1745
1746 clk_prepare_enable(eth->clk_ethif);
1747 clk_prepare_enable(eth->clk_esw);
1748 clk_prepare_enable(eth->clk_gp1);
1749 clk_prepare_enable(eth->clk_gp2);
1750
1751 eth->dev = &pdev->dev;
1752 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1753
1754 err = mtk_hw_init(eth);
1755 if (err)
1756 return err;
1757
1758 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1759 if (!of_device_is_compatible(mac_np,
1760 "mediatek,eth-mac"))
1761 continue;
1762
1763 if (!of_device_is_available(mac_np))
1764 continue;
1765
1766 err = mtk_add_mac(eth, mac_np);
1767 if (err)
1768 goto err_free_dev;
1769 }
1770
1771 /* we run 2 devices on the same DMA ring so we need a dummy device
1772 * for NAPI to work
1773 */
1774 init_dummy_netdev(&eth->dummy_dev);
1775 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
1776 MTK_NAPI_WEIGHT);
1777
1778 platform_set_drvdata(pdev, eth);
1779
1780 return 0;
1781
1782err_free_dev:
1783 mtk_cleanup(eth);
1784 return err;
1785}
1786
1787static int mtk_remove(struct platform_device *pdev)
1788{
1789 struct mtk_eth *eth = platform_get_drvdata(pdev);
1790
1791 clk_disable_unprepare(eth->clk_ethif);
1792 clk_disable_unprepare(eth->clk_esw);
1793 clk_disable_unprepare(eth->clk_gp1);
1794 clk_disable_unprepare(eth->clk_gp2);
1795
1796 netif_napi_del(&eth->rx_napi);
1797 mtk_cleanup(eth);
1798 platform_set_drvdata(pdev, NULL);
1799
1800 return 0;
1801}
1802
1803const struct of_device_id of_mtk_match[] = {
1804 { .compatible = "mediatek,mt7623-eth" },
1805 {},
1806};
1807
1808static struct platform_driver mtk_driver = {
1809 .probe = mtk_probe,
1810 .remove = mtk_remove,
1811 .driver = {
1812 .name = "mtk_soc_eth",
1813 .owner = THIS_MODULE,
1814 .of_match_table = of_mtk_match,
1815 },
1816};
1817
1818module_platform_driver(mtk_driver);
1819
1820MODULE_LICENSE("GPL");
1821MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1822MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux kernel - Deliverables
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