Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_cq.c
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1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/mlx4/cq.h>
35#include <linux/mlx4/qp.h>
36#include <linux/mlx4/cmd.h>
37
38#include "mlx4_en.h"
39
40static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
41{
42 return;
43}
44
45
46int mlx4_en_create_cq(struct mlx4_en_priv *priv,
41d942d5 47 struct mlx4_en_cq **pcq,
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48 int entries, int ring, enum cq_type mode,
49 int node)
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50{
51 struct mlx4_en_dev *mdev = priv->mdev;
41d942d5 52 struct mlx4_en_cq *cq;
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53 int err;
54
163561a4 55 cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node);
41d942d5 56 if (!cq) {
163561a4
EE
57 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
58 if (!cq) {
59 en_err(priv, "Failed to allocate CQ structure\n");
60 return -ENOMEM;
61 }
41d942d5
EE
62 }
63
c27a02cd 64 cq->size = entries;
08ff3235 65 cq->buf_size = cq->size * mdev->dev->caps.cqe_size;
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66
67 cq->ring = ring;
68 cq->is_tx = mode;
c27a02cd 69
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70 /* Allocate HW buffers on provided NUMA node.
71 * dev->numa_node is used in mtt range allocation flow.
72 */
73 set_dev_node(&mdev->dev->pdev->dev, node);
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74 err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
75 cq->buf_size, 2 * PAGE_SIZE);
163561a4 76 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
c27a02cd 77 if (err)
41d942d5 78 goto err_cq;
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79
80 err = mlx4_en_map_buffer(&cq->wqres.buf);
81 if (err)
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82 goto err_res;
83
84 cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf;
85 *pcq = cq;
c27a02cd 86
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87 return 0;
88
89err_res:
90 mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
91err_cq:
92 kfree(cq);
93 *pcq = NULL;
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94 return err;
95}
96
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97int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
98 int cq_idx)
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99{
100 struct mlx4_en_dev *mdev = priv->mdev;
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101 int err = 0;
102 char name[25];
ec693d47 103 int timestamp_en = 0;
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104 struct cpu_rmap *rmap =
105#ifdef CONFIG_RFS_ACCEL
106 priv->dev->rx_cpu_rmap;
107#else
108 NULL;
109#endif
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110
111 cq->dev = mdev->pndev[priv->port];
112 cq->mcq.set_ci_db = cq->wqres.db.db;
113 cq->mcq.arm_db = cq->wqres.db.db + 1;
114 *cq->mcq.set_ci_db = 0;
115 *cq->mcq.arm_db = 0;
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116 memset(cq->buf, 0, cq->buf_size);
117
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118 if (cq->is_tx == RX) {
119 if (mdev->dev->caps.comp_pool) {
120 if (!cq->vector) {
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121 sprintf(name, "%s-%d", priv->dev->name,
122 cq->ring);
123 /* Set IRQ for specific name (per ring) */
1eb8c695 124 if (mlx4_assign_eq(mdev->dev, name, rmap,
d9236c3f 125 &cq->vector)) {
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126 cq->vector = (cq->ring + 1 + priv->port)
127 % mdev->dev->caps.num_comp_vectors;
1a91de28 128 mlx4_warn(mdev, "Failed assigning an EQ to %s, falling back to legacy EQ's\n",
76532d0c 129 name);
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130 }
131 }
132 } else {
133 cq->vector = (cq->ring + 1 + priv->port) %
134 mdev->dev->caps.num_comp_vectors;
135 }
136 } else {
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137 /* For TX we use the same irq per
138 ring we assigned for the RX */
139 struct mlx4_en_cq *rx_cq;
140
141 cq_idx = cq_idx % priv->rx_ring_num;
41d942d5 142 rx_cq = priv->rx_cq[cq_idx];
76532d0c 143 cq->vector = rx_cq->vector;
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144 }
145
38aab07c 146 if (!cq->is_tx)
41d942d5 147 cq->size = priv->rx_ring[cq->ring]->actual_size;
38aab07c 148
ec693d47
AV
149 if ((cq->is_tx && priv->hwtstamp_config.tx_type) ||
150 (!cq->is_tx && priv->hwtstamp_config.rx_filter))
151 timestamp_en = 1;
152
153 err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt,
154 &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq,
155 cq->vector, 0, timestamp_en);
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156 if (err)
157 return err;
158
159 cq->mcq.comp = cq->is_tx ? mlx4_en_tx_irq : mlx4_en_rx_irq;
160 cq->mcq.event = mlx4_en_cq_event;
161
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EE
162 if (cq->is_tx) {
163 netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_tx_cq,
164 NAPI_POLL_WEIGHT);
165 } else {
c27a02cd 166 netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64);
9e77a2b8 167 napi_hash_add(&cq->napi);
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168 }
169
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170 napi_enable(&cq->napi);
171
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172 return 0;
173}
174
41d942d5 175void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq)
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176{
177 struct mlx4_en_dev *mdev = priv->mdev;
41d942d5 178 struct mlx4_en_cq *cq = *pcq;
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179
180 mlx4_en_unmap_buffer(&cq->wqres.buf);
181 mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
fe0af03c 182 if (priv->mdev->dev->caps.comp_pool && cq->vector)
1fb9876e 183 mlx4_release_eq(priv->mdev->dev, cq->vector);
cd3109d2 184 cq->vector = 0;
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185 cq->buf_size = 0;
186 cq->buf = NULL;
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187 kfree(cq);
188 *pcq = NULL;
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189}
190
191void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
192{
0276a330 193 napi_disable(&cq->napi);
e22979d9 194 if (!cq->is_tx) {
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195 napi_hash_del(&cq->napi);
196 synchronize_rcu();
72876a60 197 }
0276a330 198 netif_napi_del(&cq->napi);
c27a02cd 199
e22979d9 200 mlx4_cq_free(priv->mdev->dev, &cq->mcq);
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201}
202
203/* Set rx cq moderation parameters */
204int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
205{
206 return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
207 cq->moder_cnt, cq->moder_time);
208}
209
210int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
211{
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212 mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
213 &priv->mdev->uar_lock);
214
215 return 0;
216}
217
218
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