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net: dsa: b53: Fix statistics readings
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
1b136de1 42#include <net/vxlan.h>
09d4d087 43#include <net/devlink.h>
c27a02cd
YP		 44
45#include <linux/mlx4/driver.h>
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/cmd.h>
48#include <linux/mlx4/cq.h>
49
50#include "mlx4_en.h"
51#include "en_port.h"
52
d317966b 53int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 54{
bc6a4744
AV		 55 struct mlx4_en_priv *priv = netdev_priv(dev);
56 int i;
d317966b 57 unsigned int offset = 0;
bc6a4744
AV		 58
59 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 60 return -EINVAL;
61
bc6a4744
AV		 62 netdev_set_num_tc(dev, up);
63
64 /* Partition Tx queues evenly amongst UP's */
bc6a4744 65 for (i = 0; i < up; i++) {
d317966b
AV		 66 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
67 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 68 }
69
897d7846
AV		 70 return 0;
71}
72
16e5cc64
JF		 73static int __mlx4_en_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
74 struct tc_to_netdev *tc)
e4c6734e 75{
5eb4dce3 76 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 77 return -EINVAL;
78
16e5cc64 79 return mlx4_en_setup_tc(dev, tc->tc);
e4c6734e
JF		 80}
81
1eb8c695
AV		 82#ifdef CONFIG_RFS_ACCEL
83
84struct mlx4_en_filter {
85 struct list_head next;
86 struct work_struct work;
87
75a353d4 88 u8 ip_proto;
1eb8c695
AV		 89 __be32 src_ip;
90 __be32 dst_ip;
91 __be16 src_port;
92 __be16 dst_port;
93
94 int rxq_index;
95 struct mlx4_en_priv *priv;
96 u32 flow_id; /* RFS infrastructure id */
97 int id; /* mlx4_en driver id */
98 u64 reg_id; /* Flow steering API id */
99 u8 activated; /* Used to prevent expiry before filter
100 * is attached
101 */
102 struct hlist_node filter_chain;
103};
104
105static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
106
75a353d4
EP		 107static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
108{
109 switch (ip_proto) {
110 case IPPROTO_UDP:
111 return MLX4_NET_TRANS_RULE_ID_UDP;
112 case IPPROTO_TCP:
113 return MLX4_NET_TRANS_RULE_ID_TCP;
114 default:
c3ca5205 115 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 116 }
117};
118
1eb8c695
AV		 119static void mlx4_en_filter_work(struct work_struct *work)
120{
121 struct mlx4_en_filter *filter = container_of(work,
122 struct mlx4_en_filter,
123 work);
124 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 125 struct mlx4_spec_list spec_tcp_udp = {
126 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 127 {
128 .tcp_udp = {
129 .dst_port = filter->dst_port,
130 .dst_port_msk = (__force __be16)-1,
131 .src_port = filter->src_port,
132 .src_port_msk = (__force __be16)-1,
133 },
134 },
135 };
136 struct mlx4_spec_list spec_ip = {
137 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
138 {
139 .ipv4 = {
140 .dst_ip = filter->dst_ip,
141 .dst_ip_msk = (__force __be32)-1,
142 .src_ip = filter->src_ip,
143 .src_ip_msk = (__force __be32)-1,
144 },
145 },
146 };
147 struct mlx4_spec_list spec_eth = {
148 .id = MLX4_NET_TRANS_RULE_ID_ETH,
149 };
150 struct mlx4_net_trans_rule rule = {
151 .list = LIST_HEAD_INIT(rule.list),
152 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
153 .exclusive = 1,
154 .allow_loopback = 1,
f9162539 155 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 156 .port = priv->port,
157 .priority = MLX4_DOMAIN_RFS,
158 };
159 int rc;
1eb8c695
AV		 160 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
161
c3ca5205 162 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 163 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
164 filter->ip_proto);
165 goto ignore;
166 }
1eb8c695
AV		 167 list_add_tail(&spec_eth.list, &rule.list);
168 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 169 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 170
1eb8c695 171 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 172 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 173 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
174
175 filter->activated = 0;
176
177 if (filter->reg_id) {
178 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
179 if (rc && rc != -ENOENT)
180 en_err(priv, "Error detaching flow. rc = %d\n", rc);
181 }
182
183 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
184 if (rc)
185 en_err(priv, "Error attaching flow. err = %d\n", rc);
186
75a353d4 187ignore:
1eb8c695
AV		 188 mlx4_en_filter_rfs_expire(priv);
189
190 filter->activated = 1;
191}
192
193static inline struct hlist_head *
194filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
195 __be16 src_port, __be16 dst_port)
196{
197 unsigned long l;
198 int bucket_idx;
199
200 l = (__force unsigned long)src_port |
201 ((__force unsigned long)dst_port << 2);
202 l ^= (__force unsigned long)(src_ip ^ dst_ip);
203
204 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
205
206 return &priv->filter_hash[bucket_idx];
207}
208
209static struct mlx4_en_filter *
210mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 211 __be32 dst_ip, u8 ip_proto, __be16 src_port,
212 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 213{
214 struct mlx4_en_filter *filter = NULL;
215
216 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
217 if (!filter)
218 return NULL;
219
220 filter->priv = priv;
221 filter->rxq_index = rxq_index;
222 INIT_WORK(&filter->work, mlx4_en_filter_work);
223
224 filter->src_ip = src_ip;
225 filter->dst_ip = dst_ip;
75a353d4 226 filter->ip_proto = ip_proto;
1eb8c695
AV		 227 filter->src_port = src_port;
228 filter->dst_port = dst_port;
229
230 filter->flow_id = flow_id;
231
ee64c0ee 232 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 233
234 list_add_tail(&filter->next, &priv->filters);
235 hlist_add_head(&filter->filter_chain,
236 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
237 dst_port));
238
239 return filter;
240}
241
242static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
243{
244 struct mlx4_en_priv *priv = filter->priv;
245 int rc;
246
247 list_del(&filter->next);
248
249 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
250 if (rc && rc != -ENOENT)
251 en_err(priv, "Error detaching flow. rc = %d\n", rc);
252
253 kfree(filter);
254}
255
256static inline struct mlx4_en_filter *
257mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 258 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 259{
1eb8c695
AV		 260 struct mlx4_en_filter *filter;
261 struct mlx4_en_filter *ret = NULL;
262
b67bfe0d 263 hlist_for_each_entry(filter,
1eb8c695
AV		 264 filter_hash_bucket(priv, src_ip, dst_ip,
265 src_port, dst_port),
266 filter_chain) {
267 if (filter->src_ip == src_ip &&
268 filter->dst_ip == dst_ip &&
75a353d4 269 filter->ip_proto == ip_proto &&
1eb8c695
AV		 270 filter->src_port == src_port &&
271 filter->dst_port == dst_port) {
272 ret = filter;
273 break;
274 }
275 }
276
277 return ret;
278}
279
280static int
281mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
282 u16 rxq_index, u32 flow_id)
283{
284 struct mlx4_en_priv *priv = netdev_priv(net_dev);
285 struct mlx4_en_filter *filter;
286 const struct iphdr *ip;
287 const __be16 *ports;
75a353d4 288 u8 ip_proto;
1eb8c695
AV		 289 __be32 src_ip;
290 __be32 dst_ip;
291 __be16 src_port;
292 __be16 dst_port;
293 int nhoff = skb_network_offset(skb);
294 int ret = 0;
295
296 if (skb->protocol != htons(ETH_P_IP))
297 return -EPROTONOSUPPORT;
298
299 ip = (const struct iphdr *)(skb->data + nhoff);
300 if (ip_is_fragment(ip))
301 return -EPROTONOSUPPORT;
302
75a353d4
EP		 303 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
304 return -EPROTONOSUPPORT;
1eb8c695
AV		 305 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
306
75a353d4 307 ip_proto = ip->protocol;
1eb8c695
AV		 308 src_ip = ip->saddr;
309 dst_ip = ip->daddr;
310 src_port = ports[0];
311 dst_port = ports[1];
312
1eb8c695 313 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 314 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
315 src_port, dst_port);
1eb8c695
AV		 316 if (filter) {
317 if (filter->rxq_index == rxq_index)
318 goto out;
319
320 filter->rxq_index = rxq_index;
321 } else {
322 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 323 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 324 src_port, dst_port, flow_id);
325 if (!filter) {
326 ret = -ENOMEM;
327 goto err;
328 }
329 }
330
331 queue_work(priv->mdev->workqueue, &filter->work);
332
333out:
334 ret = filter->id;
335err:
336 spin_unlock_bh(&priv->filters_lock);
337
338 return ret;
339}
340
41d942d5 341void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 342{
343 struct mlx4_en_filter *filter, *tmp;
344 LIST_HEAD(del_list);
345
346 spin_lock_bh(&priv->filters_lock);
347 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
348 list_move(&filter->next, &del_list);
349 hlist_del(&filter->filter_chain);
350 }
351 spin_unlock_bh(&priv->filters_lock);
352
353 list_for_each_entry_safe(filter, tmp, &del_list, next) {
354 cancel_work_sync(&filter->work);
355 mlx4_en_filter_free(filter);
356 }
357}
358
359static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
360{
361 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
362 LIST_HEAD(del_list);
363 int i = 0;
364
365 spin_lock_bh(&priv->filters_lock);
366 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
367 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
368 break;
369
370 if (filter->activated &&
371 !work_pending(&filter->work) &&
372 rps_may_expire_flow(priv->dev,
373 filter->rxq_index, filter->flow_id,
374 filter->id)) {
375 list_move(&filter->next, &del_list);
376 hlist_del(&filter->filter_chain);
377 } else
378 last_filter = filter;
379
380 i++;
381 }
382
383 if (last_filter && (&last_filter->next != priv->filters.next))
384 list_move(&priv->filters, &last_filter->next);
385
386 spin_unlock_bh(&priv->filters_lock);
387
388 list_for_each_entry_safe(filter, tmp, &del_list, next)
389 mlx4_en_filter_free(filter);
390}
391#endif
392
80d5c368
PM		 393static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
394 __be16 proto, u16 vid)
c27a02cd
YP		 395{
396 struct mlx4_en_priv *priv = netdev_priv(dev);
397 struct mlx4_en_dev *mdev = priv->mdev;
398 int err;
4c3eb3ca 399 int idx;
c27a02cd 400
f1b553fb 401 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 402
f1b553fb 403 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 404
405 /* Add VID to port VLAN filter */
406 mutex_lock(&mdev->state_lock);
407 if (mdev->device_up && priv->port_up) {
f1b553fb 408 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 409 if (err)
453a6082 410 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 411 }
4c3eb3ca 412 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 413 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 414 mutex_unlock(&mdev->state_lock);
4c3eb3ca 415
8e586137 416 return 0;
c27a02cd
YP		 417}
418
80d5c368
PM		 419static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
420 __be16 proto, u16 vid)
c27a02cd
YP		 421{
422 struct mlx4_en_priv *priv = netdev_priv(dev);
423 struct mlx4_en_dev *mdev = priv->mdev;
424 int err;
425
f1b553fb 426 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 427
f1b553fb 428 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 429
430 /* Remove VID from port VLAN filter */
431 mutex_lock(&mdev->state_lock);
2009d005 432 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 433
c27a02cd 434 if (mdev->device_up && priv->port_up) {
f1b553fb 435 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 436 if (err)
453a6082 437 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 438 }
439 mutex_unlock(&mdev->state_lock);
8e586137
JP		 440
441 return 0;
c27a02cd
YP		 442}
443
6bbb6d99
YB		 444static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
445{
bab6a9ea
YB		 446 int i;
447 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 448 dst_mac[i] = src_mac & 0xff;
449 src_mac >>= 8;
450 }
451 memset(&dst_mac[ETH_ALEN], 0, 2);
452}
453
837052d0
OG		 454
455static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
456 int qpn, u64 *reg_id)
457{
458 int err;
837052d0 459
5eff6dad
OG		 460 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
461 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 462 return 0; /* do nothing */
463
b95089d0
OG		 464 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
465 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 466 if (err) {
467 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
468 return err;
469 }
470 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
471 return 0;
472}
473
474
16a10ffd
YB		 475static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
476 unsigned char *mac, int *qpn, u64 *reg_id)
477{
478 struct mlx4_en_dev *mdev = priv->mdev;
479 struct mlx4_dev *dev = mdev->dev;
480 int err;
481
482 switch (dev->caps.steering_mode) {
483 case MLX4_STEERING_MODE_B0: {
484 struct mlx4_qp qp;
485 u8 gid[16] = {0};
486
487 qp.qpn = *qpn;
488 memcpy(&gid[10], mac, ETH_ALEN);
489 gid[5] = priv->port;
490
491 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
492 break;
493 }
494 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
495 struct mlx4_spec_list spec_eth = { {NULL} };
496 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
497
498 struct mlx4_net_trans_rule rule = {
499 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
500 .exclusive = 0,
501 .allow_loopback = 1,
f9162539 502 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 503 .priority = MLX4_DOMAIN_NIC,
504 };
505
506 rule.port = priv->port;
507 rule.qpn = *qpn;
508 INIT_LIST_HEAD(&rule.list);
509
510 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
511 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
512 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
513 list_add_tail(&spec_eth.list, &rule.list);
514
515 err = mlx4_flow_attach(dev, &rule, reg_id);
516 break;
517 }
518 default:
519 return -EINVAL;
520 }
521 if (err)
522 en_warn(priv, "Failed Attaching Unicast\n");
523
524 return err;
525}
526
527static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
528 unsigned char *mac, int qpn, u64 reg_id)
529{
530 struct mlx4_en_dev *mdev = priv->mdev;
531 struct mlx4_dev *dev = mdev->dev;
532
533 switch (dev->caps.steering_mode) {
534 case MLX4_STEERING_MODE_B0: {
535 struct mlx4_qp qp;
536 u8 gid[16] = {0};
537
538 qp.qpn = qpn;
539 memcpy(&gid[10], mac, ETH_ALEN);
540 gid[5] = priv->port;
541
542 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
543 break;
544 }
545 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
546 mlx4_flow_detach(dev, reg_id);
547 break;
548 }
549 default:
550 en_err(priv, "Invalid steering mode.\n");
551 }
552}
553
554static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
555{
556 struct mlx4_en_dev *mdev = priv->mdev;
557 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 558 int index = 0;
559 int err = 0;
16a10ffd 560 int *qpn = &priv->base_qpn;
9813337a 561 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 562
563 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
564 priv->dev->dev_addr);
565 index = mlx4_register_mac(dev, priv->port, mac);
566 if (index < 0) {
567 err = index;
568 en_err(priv, "Failed adding MAC: %pM\n",
569 priv->dev->dev_addr);
570 return err;
571 }
572
573 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
574 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
575 *qpn = base_qpn + index;
576 return 0;
577 }
578
d57febe1 579 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 580 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
581 if (err) {
582 en_err(priv, "Failed to reserve qp for mac registration\n");
ba4b87ae
IS		 583 mlx4_unregister_mac(dev, priv->port, mac);
584 return err;
16a10ffd 585 }
16a10ffd 586
c07cb4b0 587 return 0;
16a10ffd
YB		 588}
589
590static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
591{
592 struct mlx4_en_dev *mdev = priv->mdev;
593 struct mlx4_dev *dev = mdev->dev;
16a10ffd 594 int qpn = priv->base_qpn;
16a10ffd 595
83a5a6ce 596 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
ba4b87ae 597 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 598 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
599 priv->dev->dev_addr);
600 mlx4_unregister_mac(dev, priv->port, mac);
601 } else {
83a5a6ce
YB		 602 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
603 priv->port, qpn);
604 mlx4_qp_release_range(dev, qpn, 1);
605 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 606 }
607}
608
609static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 610 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 611{
612 struct mlx4_en_dev *mdev = priv->mdev;
613 struct mlx4_dev *dev = mdev->dev;
16a10ffd 614 int err = 0;
9813337a 615 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 616
617 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 618 struct hlist_head *bucket;
619 unsigned int mac_hash;
620 struct mlx4_mac_entry *entry;
b67bfe0d 621 struct hlist_node *tmp;
9813337a 622 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 623
624 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 625 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 626 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
627 mlx4_en_uc_steer_release(priv, entry->mac,
628 qpn, entry->reg_id);
629 mlx4_unregister_mac(dev, priv->port,
630 prev_mac_u64);
631 hlist_del_rcu(&entry->hlist);
632 synchronize_rcu();
633 memcpy(entry->mac, new_mac, ETH_ALEN);
634 entry->reg_id = 0;
635 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
636 hlist_add_head_rcu(&entry->hlist,
637 &priv->mac_hash[mac_hash]);
638 mlx4_register_mac(dev, priv->port, new_mac_u64);
639 err = mlx4_en_uc_steer_add(priv, new_mac,
640 &qpn,
641 &entry->reg_id);
2a2083f7
OG		 642 if (err)
643 return err;
644 if (priv->tunnel_reg_id) {
645 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
646 priv->tunnel_reg_id = 0;
647 }
648 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
649 &priv->tunnel_reg_id);
c07cb4b0
YB		 650 return err;
651 }
652 }
653 return -EINVAL;
16a10ffd
YB		 654 }
655
656 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
657}
658
2695bab2
NO		 659static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
660 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 661{
c27a02cd
YP		 662 int err = 0;
663
c27a02cd
YP		 664 if (priv->port_up) {
665 /* Remove old MAC and insert the new one */
16a10ffd 666 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 667 new_mac, priv->current_mac);
c27a02cd 668 if (err)
453a6082 669 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 670 } else
48e551ff 671 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 672
2695bab2
NO		 673 if (!err)
674 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 675
bfa8ab47
YB		 676 return err;
677}
678
679static int mlx4_en_set_mac(struct net_device *dev, void *addr)
680{
681 struct mlx4_en_priv *priv = netdev_priv(dev);
682 struct mlx4_en_dev *mdev = priv->mdev;
683 struct sockaddr *saddr = addr;
2695bab2 684 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 685 int err;
686
687 if (!is_valid_ether_addr(saddr->sa_data))
688 return -EADDRNOTAVAIL;
689
bfa8ab47 690 mutex_lock(&mdev->state_lock);
2695bab2
NO		 691 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
692 err = mlx4_en_do_set_mac(priv, new_mac);
693 if (!err)
694 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 695 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 696
697 return err;
c27a02cd
YP		 698}
699
700static void mlx4_en_clear_list(struct net_device *dev)
701{
702 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 703 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 704
6d199937
YP		 705 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
706 list_del(&mc_to_del->list);
707 kfree(mc_to_del);
708 }
c27a02cd
YP		 709}
710
711static void mlx4_en_cache_mclist(struct net_device *dev)
712{
713 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 714 struct netdev_hw_addr *ha;
6d199937 715 struct mlx4_en_mc_list *tmp;
ff6e2163 716
0e03567a 717 mlx4_en_clear_list(dev);
6d199937
YP		 718 netdev_for_each_mc_addr(ha, dev) {
719 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
720 if (!tmp) {
6d199937
YP		 721 mlx4_en_clear_list(dev);
722 return;
723 }
724 memcpy(tmp->addr, ha->addr, ETH_ALEN);
725 list_add_tail(&tmp->list, &priv->mc_list);
726 }
c27a02cd
YP		 727}
728
6d199937
YP		 729static void update_mclist_flags(struct mlx4_en_priv *priv,
730 struct list_head *dst,
731 struct list_head *src)
732{
733 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
734 bool found;
735
736 /* Find all the entries that should be removed from dst,
737 * These are the entries that are not found in src
738 */
739 list_for_each_entry(dst_tmp, dst, list) {
740 found = false;
741 list_for_each_entry(src_tmp, src, list) {
c0623e58 742 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 743 found = true;
744 break;
745 }
746 }
747 if (!found)
748 dst_tmp->action = MCLIST_REM;
749 }
750
751 /* Add entries that exist in src but not in dst
752 * mark them as need to add
753 */
754 list_for_each_entry(src_tmp, src, list) {
755 found = false;
756 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 757 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 758 dst_tmp->action = MCLIST_NONE;
759 found = true;
760 break;
761 }
762 }
763 if (!found) {
14f8dc49
JP		 764 new_mc = kmemdup(src_tmp,
765 sizeof(struct mlx4_en_mc_list),
6d199937 766 GFP_KERNEL);
14f8dc49 767 if (!new_mc)
6d199937 768 return;
14f8dc49 769
6d199937
YP		 770 new_mc->action = MCLIST_ADD;
771 list_add_tail(&new_mc->list, dst);
772 }
773 }
774}
c27a02cd 775
0eb74fdd 776static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 777{
778 struct mlx4_en_priv *priv = netdev_priv(dev);
779
780 if (!priv->port_up)
781 return;
782
0eb74fdd 783 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 784}
785
0eb74fdd
YB		 786static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
787 struct mlx4_en_dev *mdev)
c27a02cd 788{
c96d97f4 789 int err = 0;
c27a02cd 790
0eb74fdd 791 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 792 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 793 en_warn(priv, "Entering promiscuous mode\n");
794 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 795
0eb74fdd 796 /* Enable promiscouos mode */
c96d97f4 797 switch (mdev->dev->caps.steering_mode) {
592e49dd 798 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 799 err = mlx4_flow_steer_promisc_add(mdev->dev,
800 priv->port,
801 priv->base_qpn,
f9162539 802 MLX4_FS_ALL_DEFAULT);
592e49dd 803 if (err)
0eb74fdd
YB		 804 en_err(priv, "Failed enabling promiscuous mode\n");
805 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 806 break;
807
c96d97f4 808 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 809 err = mlx4_unicast_promisc_add(mdev->dev,
810 priv->base_qpn,
811 priv->port);
c96d97f4 812 if (err)
0eb74fdd
YB		 813 en_err(priv, "Failed enabling unicast promiscuous mode\n");
814
815 /* Add the default qp number as multicast
816 * promisc
817 */
818 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
819 err = mlx4_multicast_promisc_add(mdev->dev,
820 priv->base_qpn,
821 priv->port);
c96d97f4 822 if (err)
0eb74fdd
YB		 823 en_err(priv, "Failed enabling multicast promiscuous mode\n");
824 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 825 }
826 break;
c27a02cd 827
c96d97f4
HHZ		 828 case MLX4_STEERING_MODE_A0:
829 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
830 priv->port,
0eb74fdd
YB		 831 priv->base_qpn,
832 1);
1679200f 833 if (err)
0eb74fdd 834 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 835 break;
1679200f
YP		 836 }
837
0eb74fdd
YB		 838 /* Disable port multicast filter (unconditionally) */
839 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
840 0, MLX4_MCAST_DISABLE);
841 if (err)
842 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 843 }
844}
845
846static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
847 struct mlx4_en_dev *mdev)
848{
849 int err = 0;
850
851 if (netif_msg_rx_status(priv))
852 en_warn(priv, "Leaving promiscuous mode\n");
853 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
854
855 /* Disable promiscouos mode */
856 switch (mdev->dev->caps.steering_mode) {
857 case MLX4_STEERING_MODE_DEVICE_MANAGED:
858 err = mlx4_flow_steer_promisc_remove(mdev->dev,
859 priv->port,
f9162539 860 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 861 if (err)
862 en_err(priv, "Failed disabling promiscuous mode\n");
863 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
864 break;
865
866 case MLX4_STEERING_MODE_B0:
867 err = mlx4_unicast_promisc_remove(mdev->dev,
868 priv->base_qpn,
869 priv->port);
870 if (err)
871 en_err(priv, "Failed disabling unicast promiscuous mode\n");
872 /* Disable Multicast promisc */
873 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
874 err = mlx4_multicast_promisc_remove(mdev->dev,
875 priv->base_qpn,
876 priv->port);
877 if (err)
878 en_err(priv, "Failed disabling multicast promiscuous mode\n");
879 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
880 }
881 break;
882
883 case MLX4_STEERING_MODE_A0:
884 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
885 priv->port,
886 priv->base_qpn, 0);
887 if (err)
888 en_err(priv, "Failed disabling promiscuous mode\n");
889 break;
c27a02cd 890 }
0eb74fdd
YB		 891}
892
893static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
894 struct net_device *dev,
895 struct mlx4_en_dev *mdev)
896{
897 struct mlx4_en_mc_list *mclist, *tmp;
898 u64 mcast_addr = 0;
899 u8 mc_list[16] = {0};
900 int err = 0;
901
c27a02cd
YP		 902 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
903 if (dev->flags & IFF_ALLMULTI) {
904 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
905 0, MLX4_MCAST_DISABLE);
906 if (err)
453a6082 907 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 908
909 /* Add the default qp number as multicast promisc */
910 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 911 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 912 case MLX4_STEERING_MODE_DEVICE_MANAGED:
913 err = mlx4_flow_steer_promisc_add(mdev->dev,
914 priv->port,
915 priv->base_qpn,
f9162539 916 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 917 break;
918
c96d97f4
HHZ		 919 case MLX4_STEERING_MODE_B0:
920 err = mlx4_multicast_promisc_add(mdev->dev,
921 priv->base_qpn,
922 priv->port);
923 break;
924
925 case MLX4_STEERING_MODE_A0:
926 break;
927 }
1679200f
YP		 928 if (err)
929 en_err(priv, "Failed entering multicast promisc mode\n");
930 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
931 }
c27a02cd 932 } else {
1679200f
YP		 933 /* Disable Multicast promisc */
934 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 935 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 936 case MLX4_STEERING_MODE_DEVICE_MANAGED:
937 err = mlx4_flow_steer_promisc_remove(mdev->dev,
938 priv->port,
f9162539 939 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 940 break;
941
c96d97f4
HHZ		 942 case MLX4_STEERING_MODE_B0:
943 err = mlx4_multicast_promisc_remove(mdev->dev,
944 priv->base_qpn,
945 priv->port);
946 break;
947
948 case MLX4_STEERING_MODE_A0:
949 break;
950 }
1679200f 951 if (err)
25985edc 952 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 953 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
954 }
ff6e2163 955
c27a02cd
YP		 956 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
957 0, MLX4_MCAST_DISABLE);
958 if (err)
453a6082 959 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 960
961 /* Flush mcast filter and init it with broadcast address */
962 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
963 1, MLX4_MCAST_CONFIG);
964
965 /* Update multicast list - we cache all addresses so they won't
966 * change while HW is updated holding the command semaphor */
dbd501a8 967 netif_addr_lock_bh(dev);
c27a02cd 968 mlx4_en_cache_mclist(dev);
dbd501a8 969 netif_addr_unlock_bh(dev);
6d199937 970 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 971 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 972 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
973 mcast_addr, 0, MLX4_MCAST_CONFIG);
974 }
975 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
976 0, MLX4_MCAST_ENABLE);
977 if (err)
453a6082 978 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 979
980 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
981 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
982 if (mclist->action == MCLIST_REM) {
983 /* detach this address and delete from list */
984 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
985 mc_list[5] = priv->port;
986 err = mlx4_multicast_detach(mdev->dev,
987 &priv->rss_map.indir_qp,
988 mc_list,
0ff1fb65
HHZ		 989 MLX4_PROT_ETH,
990 mclist->reg_id);
6d199937
YP		 991 if (err)
992 en_err(priv, "Fail to detach multicast address\n");
993
837052d0
OG		 994 if (mclist->tunnel_reg_id) {
995 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
996 if (err)
997 en_err(priv, "Failed to detach multicast address\n");
998 }
999
6d199937
YP		 1000 /* remove from list */
1001 list_del(&mclist->list);
1002 kfree(mclist);
9c64508a 1003 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1004 /* attach the address */
1005 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1006 /* needed for B0 steering support */
6d199937
YP		 1007 mc_list[5] = priv->port;
1008 err = mlx4_multicast_attach(mdev->dev,
1009 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1010 mc_list,
1011 priv->port, 0,
1012 MLX4_PROT_ETH,
1013 &mclist->reg_id);
6d199937
YP		 1014 if (err)
1015 en_err(priv, "Fail to attach multicast address\n");
1016
837052d0
OG		 1017 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1018 &mclist->tunnel_reg_id);
1019 if (err)
1020 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1021 }
1022 }
c27a02cd 1023 }
0eb74fdd
YB		 1024}
1025
cc5387f7
YB		 1026static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1027 struct net_device *dev,
1028 struct mlx4_en_dev *mdev)
1029{
1030 struct netdev_hw_addr *ha;
1031 struct mlx4_mac_entry *entry;
b67bfe0d 1032 struct hlist_node *tmp;
cc5387f7
YB		 1033 bool found;
1034 u64 mac;
1035 int err = 0;
1036 struct hlist_head *bucket;
1037 unsigned int i;
1038 int removed = 0;
1039 u32 prev_flags;
1040
1041 /* Note that we do not need to protect our mac_hash traversal with rcu,
1042 * since all modification code is protected by mdev->state_lock
1043 */
1044
1045 /* find what to remove */
1046 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1047 bucket = &priv->mac_hash[i];
b67bfe0d 1048 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1049 found = false;
1050 netdev_for_each_uc_addr(ha, dev) {
1051 if (ether_addr_equal_64bits(entry->mac,
1052 ha->addr)) {
1053 found = true;
1054 break;
1055 }
1056 }
1057
1058 /* MAC address of the port is not in uc list */
2695bab2
NO		 1059 if (ether_addr_equal_64bits(entry->mac,
1060 priv->current_mac))
cc5387f7
YB		 1061 found = true;
1062
1063 if (!found) {
9813337a 1064 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1065 mlx4_en_uc_steer_release(priv, entry->mac,
1066 priv->base_qpn,
1067 entry->reg_id);
1068 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1069
1070 hlist_del_rcu(&entry->hlist);
1071 kfree_rcu(entry, rcu);
1072 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1073 entry->mac, priv->port);
1074 ++removed;
1075 }
1076 }
1077 }
1078
1079 /* if we didn't remove anything, there is no use in trying to add
1080 * again once we are in a forced promisc mode state
1081 */
1082 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1083 return;
1084
1085 prev_flags = priv->flags;
1086 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1087
1088 /* find what to add */
1089 netdev_for_each_uc_addr(ha, dev) {
1090 found = false;
1091 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1092 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1093 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1094 found = true;
1095 break;
1096 }
1097 }
1098
1099 if (!found) {
1100 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1101 if (!entry) {
1102 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1103 ha->addr, priv->port);
1104 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1105 break;
1106 }
9813337a 1107 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1108 memcpy(entry->mac, ha->addr, ETH_ALEN);
1109 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1110 if (err < 0) {
1111 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1112 ha->addr, priv->port, err);
1113 kfree(entry);
1114 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1115 break;
1116 }
1117 err = mlx4_en_uc_steer_add(priv, ha->addr,
1118 &priv->base_qpn,
1119 &entry->reg_id);
1120 if (err) {
1121 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1122 ha->addr, priv->port, err);
1123 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1124 kfree(entry);
1125 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1126 break;
1127 } else {
1128 unsigned int mac_hash;
1129 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1130 ha->addr, priv->port);
1131 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1132 bucket = &priv->mac_hash[mac_hash];
1133 hlist_add_head_rcu(&entry->hlist, bucket);
1134 }
1135 }
1136 }
1137
1138 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1139 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1140 priv->port);
1141 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1142 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1143 priv->port);
1144 }
1145}
1146
0eb74fdd
YB		 1147static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1148{
1149 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1150 rx_mode_task);
1151 struct mlx4_en_dev *mdev = priv->mdev;
1152 struct net_device *dev = priv->dev;
1153
1154 mutex_lock(&mdev->state_lock);
1155 if (!mdev->device_up) {
1156 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1157 goto out;
1158 }
1159 if (!priv->port_up) {
1160 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1161 goto out;
1162 }
1163
1164 if (!netif_carrier_ok(dev)) {
1165 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1166 if (priv->port_state.link_state) {
1167 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1168 netif_carrier_on(dev);
1169 en_dbg(LINK, priv, "Link Up\n");
1170 }
1171 }
1172 }
1173
cc5387f7
YB		 1174 if (dev->priv_flags & IFF_UNICAST_FLT)
1175 mlx4_en_do_uc_filter(priv, dev, mdev);
1176
0eb74fdd 1177 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1178 if ((dev->flags & IFF_PROMISC) ||
1179 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1180 mlx4_en_set_promisc_mode(priv, mdev);
1181 goto out;
1182 }
1183
1184 /* Not in promiscuous mode */
1185 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1186 mlx4_en_clear_promisc_mode(priv, mdev);
1187
1188 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1189out:
1190 mutex_unlock(&mdev->state_lock);
1191}
1192
1193#ifdef CONFIG_NET_POLL_CONTROLLER
1194static void mlx4_en_netpoll(struct net_device *dev)
1195{
1196 struct mlx4_en_priv *priv = netdev_priv(dev);
1197 struct mlx4_en_cq *cq;
c27a02cd
YP		 1198 int i;
1199
7d71e994
ED		 1200 for (i = 0; i < priv->tx_ring_num; i++) {
1201 cq = priv->tx_cq[i];
c98235cb 1202 napi_schedule(&cq->napi);
c27a02cd
YP		 1203 }
1204}
1205#endif
1206
ba4b87ae
IS		 1207static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1208{
1209 u64 reg_id;
1210 int err = 0;
1211 int *qpn = &priv->base_qpn;
1212 struct mlx4_mac_entry *entry;
1213
1214 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
1215 if (err)
1216 return err;
1217
1218 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1219 &priv->tunnel_reg_id);
1220 if (err)
1221 goto tunnel_err;
1222
1223 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1224 if (!entry) {
1225 err = -ENOMEM;
1226 goto alloc_err;
1227 }
1228
1229 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1230 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1231 entry->reg_id = reg_id;
1232 hlist_add_head_rcu(&entry->hlist,
1233 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1234
1235 return 0;
1236
1237alloc_err:
1238 if (priv->tunnel_reg_id)
1239 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1240
1241tunnel_err:
1242 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1243 return err;
1244}
1245
1246static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1247{
1248 u64 mac;
1249 unsigned int i;
1250 int qpn = priv->base_qpn;
1251 struct hlist_head *bucket;
1252 struct hlist_node *tmp;
1253 struct mlx4_mac_entry *entry;
1254
1255 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1256 bucket = &priv->mac_hash[i];
1257 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1258 mac = mlx4_mac_to_u64(entry->mac);
1259 en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1260 entry->mac);
1261 mlx4_en_uc_steer_release(priv, entry->mac,
1262 qpn, entry->reg_id);
1263
1264 mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1265 hlist_del_rcu(&entry->hlist);
1266 kfree_rcu(entry, rcu);
1267 }
1268 }
1269
1270 if (priv->tunnel_reg_id) {
1271 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1272 priv->tunnel_reg_id = 0;
1273 }
1274}
1275
c27a02cd
YP		 1276static void mlx4_en_tx_timeout(struct net_device *dev)
1277{
1278 struct mlx4_en_priv *priv = netdev_priv(dev);
1279 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1280 int i;
c27a02cd
YP		 1281
1282 if (netif_msg_timer(priv))
453a6082 1283 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1284
b944ebec
YP		 1285 for (i = 0; i < priv->tx_ring_num; i++) {
1286 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1287 continue;
1288 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1289 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1290 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1291 }
1292
1e338db5 1293 priv->port_stats.tx_timeout++;
453a6082 1294 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1295 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1296}
1297
1298
9ed17db1
ED		 1299static struct rtnl_link_stats64 *
1300mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
c27a02cd
YP		 1301{
1302 struct mlx4_en_priv *priv = netdev_priv(dev);
1303
1304 spin_lock_bh(&priv->stats_lock);
f73a6f43 1305 netdev_stats_to_stats64(stats, &dev->stats);
c27a02cd
YP		 1306 spin_unlock_bh(&priv->stats_lock);
1307
9ed17db1 1308 return stats;
c27a02cd
YP		 1309}
1310
1311static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1312{
c27a02cd
YP		 1313 struct mlx4_en_cq *cq;
1314 int i;
1315
1316 /* If we haven't received a specific coalescing setting
98a1708d 1317 * (module param), we set the moderation parameters as follows:
c27a02cd 1318 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1319 * satisfy our coalescing target.
c27a02cd
YP		 1320 * - moder_time is set to a fixed value.
1321 */
3db36fb2 1322 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1323 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1324 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1325 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1326 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1327 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1328
1329 /* Setup cq moderation params */
1330 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1331 cq = priv->rx_cq[i];
c27a02cd
YP		 1332 cq->moder_cnt = priv->rx_frames;
1333 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1334 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1335 priv->last_moder_packets[i] = 0;
1336 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1337 }
1338
1339 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1340 cq = priv->tx_cq[i];
a19a848a
YP		 1341 cq->moder_cnt = priv->tx_frames;
1342 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1343 }
1344
1345 /* Reset auto-moderation params */
1346 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1347 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1348 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1349 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1350 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1351 priv->adaptive_rx_coal = 1;
c27a02cd 1352 priv->last_moder_jiffies = 0;
c27a02cd 1353 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1354}
1355
1356static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1357{
1358 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1359 struct mlx4_en_cq *cq;
1360 unsigned long packets;
1361 unsigned long rate;
1362 unsigned long avg_pkt_size;
1363 unsigned long rx_packets;
1364 unsigned long rx_bytes;
c27a02cd
YP		 1365 unsigned long rx_pkt_diff;
1366 int moder_time;
6b4d8d9f 1367 int ring, err;
c27a02cd
YP		 1368
1369 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1370 return;
1371
6b4d8d9f
AG		 1372 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1373 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1374 rx_packets = priv->rx_ring[ring]->packets;
1375 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1376 spin_unlock_bh(&priv->stats_lock);
1377
1378 rx_pkt_diff = ((unsigned long) (rx_packets -
1379 priv->last_moder_packets[ring]));
1380 packets = rx_pkt_diff;
1381 rate = packets * HZ / period;
1382 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1383 priv->last_moder_bytes[ring])) / packets : 0;
1384
1385 /* Apply auto-moderation only when packet rate
1386 * exceeds a rate that it matters */
1387 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1388 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1389 if (rate < priv->pkt_rate_low)
1390 moder_time = priv->rx_usecs_low;
1391 else if (rate > priv->pkt_rate_high)
1392 moder_time = priv->rx_usecs_high;
1393 else
1394 moder_time = (rate - priv->pkt_rate_low) *
1395 (priv->rx_usecs_high - priv->rx_usecs_low) /
1396 (priv->pkt_rate_high - priv->pkt_rate_low) +
1397 priv->rx_usecs_low;
6b4d8d9f
AG		 1398 } else {
1399 moder_time = priv->rx_usecs_low;
c27a02cd 1400 }
c27a02cd 1401
6b4d8d9f
AG		 1402 if (moder_time != priv->last_moder_time[ring]) {
1403 priv->last_moder_time[ring] = moder_time;
41d942d5 1404 cq = priv->rx_cq[ring];
c27a02cd 1405 cq->moder_time = moder_time;
a1c6693a 1406 cq->moder_cnt = priv->rx_frames;
c27a02cd 1407 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1408 if (err)
48e551ff
YB		 1409 en_err(priv, "Failed modifying moderation for cq:%d\n",
1410 ring);
c27a02cd 1411 }
6b4d8d9f
AG		 1412 priv->last_moder_packets[ring] = rx_packets;
1413 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1414 }
1415
c27a02cd
YP		 1416 priv->last_moder_jiffies = jiffies;
1417}
1418
1419static void mlx4_en_do_get_stats(struct work_struct *work)
1420{
bf6aede7 1421 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1422 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1423 stats_task);
1424 struct mlx4_en_dev *mdev = priv->mdev;
1425 int err;
1426
c27a02cd
YP		 1427 mutex_lock(&mdev->state_lock);
1428 if (mdev->device_up) {
6123db2e
JM		 1429 if (priv->port_up) {
1430 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1431 if (err)
1432 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1433
c27a02cd 1434 mlx4_en_auto_moderation(priv);
6123db2e 1435 }
c27a02cd
YP		 1436
1437 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1438 }
d7e1a487 1439 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1440 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1441 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1442 }
c27a02cd
YP		 1443 mutex_unlock(&mdev->state_lock);
1444}
1445
b6c39bfc
AV		 1446/* mlx4_en_service_task - Run service task for tasks that needed to be done
1447 * periodically
1448 */
1449static void mlx4_en_service_task(struct work_struct *work)
1450{
1451 struct delayed_work *delay = to_delayed_work(work);
1452 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1453 service_task);
1454 struct mlx4_en_dev *mdev = priv->mdev;
1455
1456 mutex_lock(&mdev->state_lock);
1457 if (mdev->device_up) {
dc8142ea
AV		 1458 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1459 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc 1460
07841f9d 1461 mlx4_en_recover_from_oom(priv);
b6c39bfc
AV		 1462 queue_delayed_work(mdev->workqueue, &priv->service_task,
1463 SERVICE_TASK_DELAY);
1464 }
1465 mutex_unlock(&mdev->state_lock);
1466}
1467
c27a02cd
YP		 1468static void mlx4_en_linkstate(struct work_struct *work)
1469{
1470 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1471 linkstate_task);
1472 struct mlx4_en_dev *mdev = priv->mdev;
1473 int linkstate = priv->link_state;
1474
1475 mutex_lock(&mdev->state_lock);
1476 /* If observable port state changed set carrier state and
1477 * report to system log */
1478 if (priv->last_link_state != linkstate) {
1479 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1480 en_info(priv, "Link Down\n");
c27a02cd
YP		 1481 netif_carrier_off(priv->dev);
1482 } else {
e5cc44b2 1483 en_info(priv, "Link Up\n");
c27a02cd
YP		 1484 netif_carrier_on(priv->dev);
1485 }
1486 }
1487 priv->last_link_state = linkstate;
1488 mutex_unlock(&mdev->state_lock);
1489}
1490
9e311e77
YA		 1491static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1492{
1493 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1494 int numa_node = priv->mdev->dev->numa_node;
9e311e77
YA		 1495
1496 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1497 return -ENOMEM;
1498
f36963c9
RR		 1499 cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1500 ring->affinity_mask);
1501 return 0;
9e311e77
YA		 1502}
1503
1504static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1505{
1506 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1507}
c27a02cd 1508
18cc42a3 1509int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1510{
1511 struct mlx4_en_priv *priv = netdev_priv(dev);
1512 struct mlx4_en_dev *mdev = priv->mdev;
1513 struct mlx4_en_cq *cq;
1514 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1515 int rx_index = 0;
1516 int tx_index = 0;
c27a02cd
YP		 1517 int err = 0;
1518 int i;
1519 int j;
1679200f 1520 u8 mc_list[16] = {0};
c27a02cd
YP		 1521
1522 if (priv->port_up) {
453a6082 1523 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1524 return 0;
1525 }
1526
6d199937
YP		 1527 INIT_LIST_HEAD(&priv->mc_list);
1528 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1529 INIT_LIST_HEAD(&priv->ethtool_list);
1530 memset(&priv->ethtool_rules[0], 0,
1531 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1532
c27a02cd
YP		 1533 /* Calculate Rx buf size */
1534 dev->mtu = min(dev->mtu, priv->max_mtu);
1535 mlx4_en_calc_rx_buf(dev);
453a6082 1536 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1537
c27a02cd 1538 /* Configure rx cq's and rings */
38aab07c
YP		 1539 err = mlx4_en_activate_rx_rings(priv);
1540 if (err) {
453a6082 1541 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1542 return err;
1543 }
c27a02cd 1544 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1545 cq = priv->rx_cq[i];
c27a02cd 1546
9e311e77
YA		 1547 err = mlx4_en_init_affinity_hint(priv, i);
1548 if (err) {
1549 en_err(priv, "Failed preparing IRQ affinity hint\n");
1550 goto cq_err;
1551 }
1552
76532d0c 1553 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1554 if (err) {
453a6082 1555 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1556 mlx4_en_free_affinity_hint(priv, i);
a4233304 1557 goto cq_err;
c27a02cd 1558 }
c3f2511f
IS		 1559
1560 for (j = 0; j < cq->size; j++) {
1561 struct mlx4_cqe *cqe = NULL;
1562
1563 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1564 priv->cqe_factor;
1565 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1566 }
1567
c27a02cd
YP		 1568 err = mlx4_en_set_cq_moder(priv, cq);
1569 if (err) {
1a91de28 1570 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1571 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1572 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1573 goto cq_err;
1574 }
1575 mlx4_en_arm_cq(priv, cq);
41d942d5 1576 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1577 ++rx_index;
1578 }
1579
ffe455ad
EE		 1580 /* Set qp number */
1581 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1582 err = mlx4_en_get_qp(priv);
1679200f 1583 if (err) {
ffe455ad 1584 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1585 goto cq_err;
1586 }
1587 mdev->mac_removed[priv->port] = 0;
1588
6de5f7f6
EBE		 1589 priv->counter_index =
1590 mlx4_get_default_counter_index(mdev->dev, priv->port);
1591
c27a02cd
YP		 1592 err = mlx4_en_config_rss_steer(priv);
1593 if (err) {
453a6082 1594 en_err(priv, "Failed configuring rss steering\n");
1679200f 1595 goto mac_err;
c27a02cd
YP		 1596 }
1597
cabdc8ee
HHZ		 1598 err = mlx4_en_create_drop_qp(priv);
1599 if (err)
1600 goto rss_err;
1601
c27a02cd
YP		 1602 /* Configure tx cq's and rings */
1603 for (i = 0; i < priv->tx_ring_num; i++) {
1604 /* Configure cq */
41d942d5 1605 cq = priv->tx_cq[i];
76532d0c 1606 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1607 if (err) {
453a6082 1608 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1609 goto tx_err;
1610 }
1611 err = mlx4_en_set_cq_moder(priv, cq);
1612 if (err) {
1a91de28 1613 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd
YP		 1614 mlx4_en_deactivate_cq(priv, cq);
1615 goto tx_err;
1616 }
453a6082 1617 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1618 cq->buf->wqe_index = cpu_to_be16(0xffff);
1619
1620 /* Configure ring */
41d942d5 1621 tx_ring = priv->tx_ring[i];
0e98b523 1622 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1623 i / priv->num_tx_rings_p_up);
c27a02cd 1624 if (err) {
453a6082 1625 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1626 mlx4_en_deactivate_cq(priv, cq);
1627 goto tx_err;
1628 }
5b263f53 1629 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1630
1631 /* Arm CQ for TX completions */
1632 mlx4_en_arm_cq(priv, cq);
1633
c27a02cd
YP		 1634 /* Set initial ownership of all Tx TXBBs to SW (1) */
1635 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1636 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1637 ++tx_index;
1638 }
1639
1640 /* Configure port */
1641 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1642 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1643 priv->prof->tx_pause,
1644 priv->prof->tx_ppp,
1645 priv->prof->rx_pause,
1646 priv->prof->rx_ppp);
c27a02cd 1647 if (err) {
48e551ff
YB		 1648 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1649 priv->port, err);
c27a02cd
YP		 1650 goto tx_err;
1651 }
1652 /* Set default qp number */
1653 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1654 if (err) {
453a6082 1655 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1656 goto tx_err;
1657 }
c27a02cd 1658
837052d0 1659 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1660 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1661 if (err) {
1662 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1663 err);
1664 goto tx_err;
1665 }
1666 }
1667
c27a02cd 1668 /* Init port */
453a6082 1669 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1670 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1671 if (err) {
453a6082 1672 en_err(priv, "Failed Initializing port\n");
1679200f 1673 goto tx_err;
c27a02cd
YP		 1674 }
1675
ba4b87ae
IS		 1676 /* Set Unicast and VXLAN steering rules */
1677 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1678 mlx4_en_set_rss_steer_rules(priv))
1679 mlx4_warn(mdev, "Failed setting steering rules\n");
1680
1679200f 1681 /* Attach rx QP to bradcast address */
c7bf7169 1682 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1683 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1684 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1685 priv->port, 0, MLX4_PROT_ETH,
1686 &priv->broadcast_id))
1679200f
YP		 1687 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1688
b5845f98
HX		 1689 /* Must redo promiscuous mode setup. */
1690 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1691
c27a02cd 1692 /* Schedule multicast task to populate multicast list */
0eb74fdd 1693 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1694
9737c6ab 1695 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
a831274a
AD		 1696 udp_tunnel_get_rx_info(dev);
1697
c27a02cd 1698 priv->port_up = true;
a11faac7 1699 netif_tx_start_all_queues(dev);
3484aac1
AV		 1700 netif_device_attach(dev);
1701
c27a02cd
YP		 1702 return 0;
1703
c27a02cd
YP		 1704tx_err:
1705 while (tx_index--) {
41d942d5
EE		 1706 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1707 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1708 }
cabdc8ee
HHZ		 1709 mlx4_en_destroy_drop_qp(priv);
1710rss_err:
c27a02cd 1711 mlx4_en_release_rss_steer(priv);
1679200f 1712mac_err:
16a10ffd 1713 mlx4_en_put_qp(priv);
c27a02cd 1714cq_err:
9e311e77 1715 while (rx_index--) {
41d942d5 1716 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
f94813f3 1717 mlx4_en_free_affinity_hint(priv, rx_index);
9e311e77 1718 }
38aab07c 1719 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1720 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1721
1722 return err; /* need to close devices */
1723}
1724
1725
3484aac1 1726void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1727{
1728 struct mlx4_en_priv *priv = netdev_priv(dev);
1729 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1730 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1731 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1732 int i;
1679200f 1733 u8 mc_list[16] = {0};
c27a02cd
YP		 1734
1735 if (!priv->port_up) {
453a6082 1736 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1737 return;
1738 }
c27a02cd 1739
0cc5c8bf
EE		 1740 /* close port*/
1741 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1742
c27a02cd
YP		 1743 /* Synchronize with tx routine */
1744 netif_tx_lock_bh(dev);
3484aac1
AV		 1745 if (detach)
1746 netif_device_detach(dev);
3c05f5ef 1747 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1748 netif_tx_unlock_bh(dev);
1749
3484aac1
AV		 1750 netif_tx_disable(dev);
1751
7c287380 1752 /* Set port as not active */
3c05f5ef 1753 priv->port_up = false;
6de5f7f6 1754 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
c27a02cd 1755
db0e7cba
AY		 1756 /* Promsicuous mode */
1757 if (mdev->dev->caps.steering_mode ==
1758 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1759 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1760 MLX4_EN_FLAG_MC_PROMISC);
1761 mlx4_flow_steer_promisc_remove(mdev->dev,
1762 priv->port,
f9162539 1763 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1764 mlx4_flow_steer_promisc_remove(mdev->dev,
1765 priv->port,
f9162539 1766 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1767 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1768 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1769
1770 /* Disable promiscouos mode */
1771 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1772 priv->port);
1773
1774 /* Disable Multicast promisc */
1775 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1776 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1777 priv->port);
1778 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1779 }
1780 }
1781
1679200f 1782 /* Detach All multicasts */
c7bf7169 1783 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1784 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1785 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1786 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1787 list_for_each_entry(mclist, &priv->curr_list, list) {
1788 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1789 mc_list[5] = priv->port;
1790 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1791 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1792 if (mclist->tunnel_reg_id)
1793 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1794 }
1795 mlx4_en_clear_list(dev);
6d199937
YP		 1796 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1797 list_del(&mclist->list);
1798 kfree(mclist);
1799 }
1800
1679200f
YP		 1801 /* Flush multicast filter */
1802 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1803
6efb5fac
HHZ		 1804 /* Remove flow steering rules for the port*/
1805 if (mdev->dev->caps.steering_mode ==
1806 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1807 ASSERT_RTNL();
1808 list_for_each_entry_safe(flow, tmp_flow,
1809 &priv->ethtool_list, list) {
1810 mlx4_flow_detach(mdev->dev, flow->id);
1811 list_del(&flow->list);
1812 }
1813 }
1814
cabdc8ee
HHZ		 1815 mlx4_en_destroy_drop_qp(priv);
1816
c27a02cd
YP		 1817 /* Free TX Rings */
1818 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1819 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1820 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1821 }
1822 msleep(10);
1823
1824 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1825 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd 1826
ba4b87ae
IS		 1827 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1828 mlx4_en_delete_rss_steer_rules(priv);
1829
c27a02cd
YP		 1830 /* Free RSS qps */
1831 mlx4_en_release_rss_steer(priv);
1832
ffe455ad 1833 /* Unregister Mac address for the port */
16a10ffd 1834 mlx4_en_put_qp(priv);
5930e8d0 1835 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1836 mdev->mac_removed[priv->port] = 1;
ffe455ad 1837
c27a02cd
YP		 1838 /* Free RX Rings */
1839 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1840 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8 1841
f4a36751 1842 napi_synchronize(&cq->napi);
41d942d5 1843 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1844 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1845
1846 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1847 }
1848}
1849
1850static void mlx4_en_restart(struct work_struct *work)
1851{
1852 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1853 watchdog_task);
1854 struct mlx4_en_dev *mdev = priv->mdev;
1855 struct net_device *dev = priv->dev;
1856
453a6082 1857 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5 1858
0c5c3252 1859 rtnl_lock();
1e338db5
YP		 1860 mutex_lock(&mdev->state_lock);
1861 if (priv->port_up) {
3484aac1 1862 mlx4_en_stop_port(dev, 1);
1e338db5 1863 if (mlx4_en_start_port(dev))
453a6082 1864 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1865 }
1866 mutex_unlock(&mdev->state_lock);
0c5c3252 1867 rtnl_unlock();
c27a02cd
YP		 1868}
1869
b477ba62 1870static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1871{
1872 struct mlx4_en_priv *priv = netdev_priv(dev);
1873 struct mlx4_en_dev *mdev = priv->mdev;
1874 int i;
c27a02cd 1875
c27a02cd 1876 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1877 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd 1878
c27a02cd 1879 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1880 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1881 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 1882 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
1883 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
1884 memset(&priv->rx_priority_flowstats, 0,
1885 sizeof(priv->rx_priority_flowstats));
1886 memset(&priv->tx_priority_flowstats, 0,
1887 sizeof(priv->tx_priority_flowstats));
b42de4d0 1888 memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
c27a02cd
YP		 1889
1890 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1891 priv->tx_ring[i]->bytes = 0;
1892 priv->tx_ring[i]->packets = 0;
1893 priv->tx_ring[i]->tx_csum = 0;
63a664b7 1894 priv->tx_ring[i]->tx_dropped = 0;
45acbac6
ED		 1895 priv->tx_ring[i]->queue_stopped = 0;
1896 priv->tx_ring[i]->wake_queue = 0;
1897 priv->tx_ring[i]->tso_packets = 0;
1898 priv->tx_ring[i]->xmit_more = 0;
c27a02cd
YP		 1899 }
1900 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1901 priv->rx_ring[i]->bytes = 0;
1902 priv->rx_ring[i]->packets = 0;
1903 priv->rx_ring[i]->csum_ok = 0;
1904 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1905 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1906 }
b477ba62
EE		 1907}
1908
1909static int mlx4_en_open(struct net_device *dev)
1910{
1911 struct mlx4_en_priv *priv = netdev_priv(dev);
1912 struct mlx4_en_dev *mdev = priv->mdev;
1913 int err = 0;
1914
1915 mutex_lock(&mdev->state_lock);
1916
1917 if (!mdev->device_up) {
1918 en_err(priv, "Cannot open - device down/disabled\n");
1919 err = -EBUSY;
1920 goto out;
1921 }
1922
1923 /* Reset HW statistics and SW counters */
1924 mlx4_en_clear_stats(dev);
c27a02cd 1925
c27a02cd
YP		 1926 err = mlx4_en_start_port(dev);
1927 if (err)
453a6082 1928 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1929
1930out:
1931 mutex_unlock(&mdev->state_lock);
1932 return err;
1933}
1934
1935
1936static int mlx4_en_close(struct net_device *dev)
1937{
1938 struct mlx4_en_priv *priv = netdev_priv(dev);
1939 struct mlx4_en_dev *mdev = priv->mdev;
1940
453a6082 1941 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1942
1943 mutex_lock(&mdev->state_lock);
1944
3484aac1 1945 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1946 netif_carrier_off(dev);
1947
1948 mutex_unlock(&mdev->state_lock);
1949 return 0;
1950}
1951
fe0af03c 1952void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1953{
1954 int i;
1955
1eb8c695 1956#ifdef CONFIG_RFS_ACCEL
1eb8c695
AV		 1957 priv->dev->rx_cpu_rmap = NULL;
1958#endif
1959
c27a02cd 1960 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1961 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1962 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1963 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1964 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1965 }
1966
1967 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1968 if (priv->rx_ring[i])
68355f71
TLSC		 1969 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1970 priv->prof->rx_ring_size, priv->stride);
41d942d5 1971 if (priv->rx_cq[i])
fe0af03c 1972 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1973 }
044ca2a5 1974
c27a02cd
YP		 1975}
1976
18cc42a3 1977int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1978{
c27a02cd
YP		 1979 struct mlx4_en_port_profile *prof = priv->prof;
1980 int i;
163561a4 1981 int node;
87a5c389 1982
c27a02cd
YP		 1983 /* Create tx Rings */
1984 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1985 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1986 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1987 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1988 goto err;
1989
d03a68f8 1990 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
d03a68f8
IS		 1991 prof->tx_ring_size, TXBB_SIZE,
1992 node, i))
c27a02cd
YP		 1993 goto err;
1994 }
1995
1996 /* Create rx Rings */
1997 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 1998 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1999 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2000 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2001 goto err;
2002
2003 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2004 prof->rx_ring_size, priv->stride,
2005 node))
c27a02cd
YP		 2006 goto err;
2007 }
2008
1eb8c695 2009#ifdef CONFIG_RFS_ACCEL
c66fa19c 2010 priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
1eb8c695
AV		 2011#endif
2012
c27a02cd
YP		 2013 return 0;
2014
2015err:
453a6082 2016 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2017 for (i = 0; i < priv->rx_ring_num; i++) {
2018 if (priv->rx_ring[i])
2019 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2020 prof->rx_ring_size,
2021 priv->stride);
2022 if (priv->rx_cq[i])
2023 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2024 }
2025 for (i = 0; i < priv->tx_ring_num; i++) {
2026 if (priv->tx_ring[i])
2027 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2028 if (priv->tx_cq[i])
2029 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2030 }
c27a02cd
YP		 2031 return -ENOMEM;
2032}
2033
2034
2035void mlx4_en_destroy_netdev(struct net_device *dev)
2036{
2037 struct mlx4_en_priv *priv = netdev_priv(dev);
2038 struct mlx4_en_dev *mdev = priv->mdev;
2039
453a6082 2040 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2041
2042 /* Unregister device - this will close the port if it was up */
09d4d087
JP		 2043 if (priv->registered) {
2044 devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev,
2045 priv->port));
c27a02cd 2046 unregister_netdev(dev);
09d4d087 2047 }
c27a02cd
YP		 2048
2049 if (priv->allocated)
2050 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2051
2052 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2053 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2054 /* flush any pending task for this netdev */
2055 flush_workqueue(mdev->workqueue);
2056
90683061
EE		 2057 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2058 mlx4_en_remove_timestamp(mdev);
2059
c27a02cd
YP		 2060 /* Detach the netdev so tasks would not attempt to access it */
2061 mutex_lock(&mdev->state_lock);
2062 mdev->pndev[priv->port] = NULL;
5da03547 2063 mdev->upper[priv->port] = NULL;
c27a02cd
YP		 2064 mutex_unlock(&mdev->state_lock);
2065
fe0af03c 2066 mlx4_en_free_resources(priv);
564c274c 2067
bc6a4744
AV		 2068 kfree(priv->tx_ring);
2069 kfree(priv->tx_cq);
2070
c27a02cd
YP		 2071 free_netdev(dev);
2072}
2073
2074static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2075{
2076 struct mlx4_en_priv *priv = netdev_priv(dev);
2077 struct mlx4_en_dev *mdev = priv->mdev;
2078 int err = 0;
2079
453a6082 2080 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2081 dev->mtu, new_mtu);
2082
2083 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2084 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2085 return -EPERM;
2086 }
2087 dev->mtu = new_mtu;
2088
2089 if (netif_running(dev)) {
2090 mutex_lock(&mdev->state_lock);
2091 if (!mdev->device_up) {
2092 /* NIC is probably restarting - let watchdog task reset
2093 * the port */
453a6082 2094 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2095 } else {
3484aac1 2096 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2097 err = mlx4_en_start_port(dev);
2098 if (err) {
453a6082 2099 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2100 priv->port);
2101 queue_work(mdev->workqueue, &priv->watchdog_task);
2102 }
2103 }
2104 mutex_unlock(&mdev->state_lock);
2105 }
2106 return 0;
2107}
2108
100dbda8 2109static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2110{
2111 struct mlx4_en_priv *priv = netdev_priv(dev);
2112 struct mlx4_en_dev *mdev = priv->mdev;
2113 struct hwtstamp_config config;
2114
2115 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2116 return -EFAULT;
2117
2118 /* reserved for future extensions */
2119 if (config.flags)
2120 return -EINVAL;
2121
2122 /* device doesn't support time stamping */
2123 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2124 return -EINVAL;
2125
2126 /* TX HW timestamp */
2127 switch (config.tx_type) {
2128 case HWTSTAMP_TX_OFF:
2129 case HWTSTAMP_TX_ON:
2130 break;
2131 default:
2132 return -ERANGE;
2133 }
2134
2135 /* RX HW timestamp */
2136 switch (config.rx_filter) {
2137 case HWTSTAMP_FILTER_NONE:
2138 break;
2139 case HWTSTAMP_FILTER_ALL:
2140 case HWTSTAMP_FILTER_SOME:
2141 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2142 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2143 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2144 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2145 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2146 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2147 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2148 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2149 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2150 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2151 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2152 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2153 config.rx_filter = HWTSTAMP_FILTER_ALL;
2154 break;
2155 default:
2156 return -ERANGE;
2157 }
2158
7787fa66 2159 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2160 config.tx_type = HWTSTAMP_TX_OFF;
2161 config.rx_filter = HWTSTAMP_FILTER_NONE;
2162 }
2163
2164 return copy_to_user(ifr->ifr_data, &config,
2165 sizeof(config)) ? -EFAULT : 0;
2166}
2167
100dbda8
BH		 2168static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2169{
2170 struct mlx4_en_priv *priv = netdev_priv(dev);
2171
2172 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2173 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2174}
2175
ec693d47
AV		 2176static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2177{
2178 switch (cmd) {
2179 case SIOCSHWTSTAMP:
100dbda8
BH		 2180 return mlx4_en_hwtstamp_set(dev, ifr);
2181 case SIOCGHWTSTAMP:
2182 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2183 default:
2184 return -EOPNOTSUPP;
2185 }
2186}
2187
e38af4fa
HHZ		 2188static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2189 netdev_features_t features)
2190{
2191 struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2192 struct mlx4_en_dev *mdev = en_priv->mdev;
2193
2194 /* Since there is no support for separate RX C-TAG/S-TAG vlan accel
2195 * enable/disable make sure S-TAG flag is always in same state as
2196 * C-TAG.
2197 */
2198 if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2199 !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2200 features |= NETIF_F_HW_VLAN_STAG_RX;
2201 else
2202 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2203
2204 return features;
2205}
2206
60d6fe99
AV		 2207static int mlx4_en_set_features(struct net_device *netdev,
2208 netdev_features_t features)
2209{
2210 struct mlx4_en_priv *priv = netdev_priv(netdev);
f0df3503 2211 bool reset = false;
537f6f95
SM		 2212 int ret = 0;
2213
f0df3503
MM		 2214 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2215 en_info(priv, "Turn %s RX-FCS\n",
2216 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2217 reset = true;
2218 }
2219
78500b8c
MM		 2220 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2221 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2222
2223 en_info(priv, "Turn %s RX-ALL\n",
2224 ignore_fcs_value ? "ON" : "OFF");
2225 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2226 priv->port, ignore_fcs_value);
2227 if (ret)
2228 return ret;
2229 }
2230
537f6f95
SM		 2231 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2232 en_info(priv, "Turn %s RX vlan strip offload\n",
2233 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
f0df3503 2234 reset = true;
537f6f95 2235 }
60d6fe99 2236
cfb53f36
IS		 2237 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2238 en_info(priv, "Turn %s TX vlan strip offload\n",
2239 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2240
e38af4fa
HHZ		 2241 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2242 en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2243 (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2244
241a08c3
IS		 2245 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2246 en_info(priv, "Turn %s loopback\n",
2247 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2248 mlx4_en_update_loopback_state(netdev, features);
2249 }
79aeaccd 2250
f0df3503
MM		 2251 if (reset) {
2252 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2253 features);
2254 if (ret)
2255 return ret;
2256 }
60d6fe99 2257
f0df3503 2258 return 0;
60d6fe99
AV		 2259}
2260
8f7ba3ca
RE		 2261static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2262{
2263 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2264 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2265 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca 2266
6e522422 2267 if (is_multicast_ether_addr(mac))
8f7ba3ca
RE		 2268 return -EINVAL;
2269
2270 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2271}
2272
3f7fb021
RE		 2273static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2274{
2275 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2276 struct mlx4_en_dev *mdev = en_priv->mdev;
2277
2278 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2279}
2280
cda373f4
IS		 2281static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2282 int max_tx_rate)
2283{
2284 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2285 struct mlx4_en_dev *mdev = en_priv->mdev;
2286
2287 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2288 max_tx_rate);
2289}
2290
e6b6a231
RE		 2291static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2292{
2293 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2294 struct mlx4_en_dev *mdev = en_priv->mdev;
2295
2296 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2297}
2298
2cccb9e4
RE		 2299static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2300{
2301 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2302 struct mlx4_en_dev *mdev = en_priv->mdev;
2303
2304 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2305}
8f7ba3ca 2306
948e306d
RE		 2307static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2308{
2309 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2310 struct mlx4_en_dev *mdev = en_priv->mdev;
2311
2312 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2313}
84c86403 2314
62a89055
EBE		 2315static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2316 struct ifla_vf_stats *vf_stats)
2317{
2318 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2319 struct mlx4_en_dev *mdev = en_priv->mdev;
2320
2321 return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2322}
2323
84c86403
HHZ		 2324#define PORT_ID_BYTE_LEN 8
2325static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2326 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2327{
2328 struct mlx4_en_priv *priv = netdev_priv(dev);
2329 struct mlx4_dev *mdev = priv->mdev->dev;
2330 int i;
2331 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2332
2333 if (!phys_port_id)
2334 return -EOPNOTSUPP;
2335
2336 ppid->id_len = sizeof(phys_port_id);
2337 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2338 ppid->id[i] = phys_port_id & 0xff;
2339 phys_port_id >>= 8;
2340 }
2341 return 0;
2342}
2343
1b136de1
OG		 2344static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2345{
2346 int ret;
2347 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2348 vxlan_add_task);
2349
2350 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2351 if (ret)
2352 goto out;
2353
2354 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2355 VXLAN_STEER_BY_OUTER_MAC, 1);
2356out:
f4a1edd5 2357 if (ret) {
1b136de1 2358 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2359 return;
2360 }
2361
2362 /* set offloads */
09067122
AD		 2363 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2364 NETIF_F_RXCSUM |
2365 NETIF_F_TSO | NETIF_F_TSO6 |
2366 NETIF_F_GSO_UDP_TUNNEL |
3c9346b2
AD		 2367 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2368 NETIF_F_GSO_PARTIAL;
1b136de1
OG		 2369}
2370
2371static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2372{
2373 int ret;
2374 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2375 vxlan_del_task);
f4a1edd5 2376 /* unset offloads */
09067122
AD		 2377 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2378 NETIF_F_RXCSUM |
2379 NETIF_F_TSO | NETIF_F_TSO6 |
2380 NETIF_F_GSO_UDP_TUNNEL |
3c9346b2
AD		 2381 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2382 NETIF_F_GSO_PARTIAL);
1b136de1
OG		 2383
2384 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2385 VXLAN_STEER_BY_OUTER_MAC, 0);
2386 if (ret)
2387 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2388
2389 priv->vxlan_port = 0;
2390}
2391
2392static void mlx4_en_add_vxlan_port(struct net_device *dev,
a831274a 2393 struct udp_tunnel_info *ti)
1b136de1
OG		 2394{
2395 struct mlx4_en_priv *priv = netdev_priv(dev);
a831274a 2396 __be16 port = ti->port;
1b136de1
OG		 2397 __be16 current_port;
2398
a831274a 2399 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
1b136de1
OG		 2400 return;
2401
a831274a
AD		 2402 if (ti->sa_family != AF_INET)
2403 return;
2404
2405 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2406 return;
2407
2408 current_port = priv->vxlan_port;
2409 if (current_port && current_port != port) {
2410 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2411 ntohs(current_port), ntohs(port));
2412 return;
2413 }
2414
2415 priv->vxlan_port = port;
2416 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2417}
2418
2419static void mlx4_en_del_vxlan_port(struct net_device *dev,
a831274a 2420 struct udp_tunnel_info *ti)
1b136de1
OG		 2421{
2422 struct mlx4_en_priv *priv = netdev_priv(dev);
a831274a 2423 __be16 port = ti->port;
1b136de1
OG		 2424 __be16 current_port;
2425
a831274a 2426 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
1b136de1
OG		 2427 return;
2428
a831274a
AD		 2429 if (ti->sa_family != AF_INET)
2430 return;
2431
2432 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2433 return;
2434
2435 current_port = priv->vxlan_port;
2436 if (current_port != port) {
2437 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2438 return;
2439 }
2440
2441 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2442}
956bdab2 2443
5f35227e
JG		 2444static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2445 struct net_device *dev,
2446 netdev_features_t features)
956bdab2 2447{
8cb65d00 2448 features = vlan_features_check(skb, features);
09067122
AD		 2449 features = vxlan_features_check(skb, features);
2450
2451 /* The ConnectX-3 doesn't support outer IPv6 checksums but it does
2452 * support inner IPv6 checksums and segmentation so we need to
2453 * strip that feature if this is an IPv6 encapsulated frame.
2454 */
2455 if (skb->encapsulation &&
2456 (skb->ip_summed == CHECKSUM_PARTIAL) &&
2457 (ip_hdr(skb)->version != 4))
2458 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2459
2460 return features;
956bdab2 2461}
1b136de1 2462
de1cf8a7 2463static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2464{
2465 struct mlx4_en_priv *priv = netdev_priv(dev);
2466 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index];
2467 struct mlx4_update_qp_params params;
2468 int err;
2469
2470 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2471 return -EOPNOTSUPP;
2472
2473 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2474 if (maxrate >> 12) {
2475 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2476 params.rate_val = maxrate / 1000;
2477 } else if (maxrate) {
2478 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2479 params.rate_val = maxrate;
2480 } else { /* zero serves to revoke the QP rate-limitation */
2481 params.rate_unit = 0;
2482 params.rate_val = 0;
2483 }
2484
2485 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2486 &params);
2487 return err;
2488}
2489
3addc568
SH		 2490static const struct net_device_ops mlx4_netdev_ops = {
2491 .ndo_open = mlx4_en_open,
2492 .ndo_stop = mlx4_en_close,
2493 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2494 .ndo_select_queue = mlx4_en_select_queue,
9ed17db1 2495 .ndo_get_stats64 = mlx4_en_get_stats64,
0eb74fdd 2496 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2497 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2498 .ndo_validate_addr = eth_validate_addr,
3addc568 2499 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2500 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2501 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2502 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2503 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2504#ifdef CONFIG_NET_POLL_CONTROLLER
2505 .ndo_poll_controller = mlx4_en_netpoll,
2506#endif
60d6fe99 2507 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2508 .ndo_fix_features = mlx4_en_fix_features,
e4c6734e 2509 .ndo_setup_tc = __mlx4_en_setup_tc,
1eb8c695
AV		 2510#ifdef CONFIG_RFS_ACCEL
2511 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
9e77a2b8 2512#endif
84c86403 2513 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a831274a
AD		 2514 .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2515 .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
5f35227e 2516 .ndo_features_check = mlx4_en_features_check,
c10e4fc6 2517 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
3addc568
SH		 2518};
2519
8f7ba3ca
RE		 2520static const struct net_device_ops mlx4_netdev_ops_master = {
2521 .ndo_open = mlx4_en_open,
2522 .ndo_stop = mlx4_en_close,
2523 .ndo_start_xmit = mlx4_en_xmit,
2524 .ndo_select_queue = mlx4_en_select_queue,
9ed17db1 2525 .ndo_get_stats64 = mlx4_en_get_stats64,
8f7ba3ca
RE		 2526 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2527 .ndo_set_mac_address = mlx4_en_set_mac,
2528 .ndo_validate_addr = eth_validate_addr,
2529 .ndo_change_mtu = mlx4_en_change_mtu,
2530 .ndo_tx_timeout = mlx4_en_tx_timeout,
2531 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2532 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2533 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2534 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2535 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2536 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2537 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
62a89055 2538 .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2cccb9e4 2539 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2540#ifdef CONFIG_NET_POLL_CONTROLLER
2541 .ndo_poll_controller = mlx4_en_netpoll,
2542#endif
2543 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2544 .ndo_fix_features = mlx4_en_fix_features,
e4c6734e 2545 .ndo_setup_tc = __mlx4_en_setup_tc,
8f7ba3ca
RE		 2546#ifdef CONFIG_RFS_ACCEL
2547 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2548#endif
84c86403 2549 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a831274a
AD		 2550 .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2551 .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
5f35227e 2552 .ndo_features_check = mlx4_en_features_check,
c10e4fc6 2553 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
8f7ba3ca
RE		 2554};
2555
5da03547
MS		 2556struct mlx4_en_bond {
2557 struct work_struct work;
2558 struct mlx4_en_priv *priv;
2559 int is_bonded;
2560 struct mlx4_port_map port_map;
2561};
2562
2563static void mlx4_en_bond_work(struct work_struct *work)
2564{
2565 struct mlx4_en_bond *bond = container_of(work,
2566 struct mlx4_en_bond,
2567 work);
2568 int err = 0;
2569 struct mlx4_dev *dev = bond->priv->mdev->dev;
2570
2571 if (bond->is_bonded) {
2572 if (!mlx4_is_bonded(dev)) {
2573 err = mlx4_bond(dev);
2574 if (err)
2575 en_err(bond->priv, "Fail to bond device\n");
2576 }
2577 if (!err) {
2578 err = mlx4_port_map_set(dev, &bond->port_map);
2579 if (err)
2580 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2581 bond->port_map.port1,
2582 bond->port_map.port2,
2583 err);
2584 }
2585 } else if (mlx4_is_bonded(dev)) {
2586 err = mlx4_unbond(dev);
2587 if (err)
2588 en_err(bond->priv, "Fail to unbond device\n");
2589 }
2590 dev_put(bond->priv->dev);
2591 kfree(bond);
2592}
2593
2594static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2595 u8 v2p_p1, u8 v2p_p2)
2596{
2597 struct mlx4_en_bond *bond = NULL;
2598
2599 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2600 if (!bond)
2601 return -ENOMEM;
2602
2603 INIT_WORK(&bond->work, mlx4_en_bond_work);
2604 bond->priv = priv;
2605 bond->is_bonded = is_bonded;
2606 bond->port_map.port1 = v2p_p1;
2607 bond->port_map.port2 = v2p_p2;
2608 dev_hold(priv->dev);
2609 queue_work(priv->mdev->workqueue, &bond->work);
2610 return 0;
2611}
2612
2613int mlx4_en_netdev_event(struct notifier_block *this,
2614 unsigned long event, void *ptr)
2615{
2616 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2617 u8 port = 0;
2618 struct mlx4_en_dev *mdev;
2619 struct mlx4_dev *dev;
2620 int i, num_eth_ports = 0;
2621 bool do_bond = true;
2622 struct mlx4_en_priv *priv;
2623 u8 v2p_port1 = 0;
2624 u8 v2p_port2 = 0;
2625
2626 if (!net_eq(dev_net(ndev), &init_net))
2627 return NOTIFY_DONE;
2628
2629 mdev = container_of(this, struct mlx4_en_dev, nb);
2630 dev = mdev->dev;
2631
2632 /* Go into this mode only when two network devices set on two ports
2633 * of the same mlx4 device are slaves of the same bonding master
2634 */
2635 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2636 ++num_eth_ports;
2637 if (!port && (mdev->pndev[i] == ndev))
2638 port = i;
2639 mdev->upper[i] = mdev->pndev[i] ?
2640 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2641 /* condition not met: network device is a slave */
2642 if (!mdev->upper[i])
2643 do_bond = false;
2644 if (num_eth_ports < 2)
2645 continue;
2646 /* condition not met: same master */
2647 if (mdev->upper[i] != mdev->upper[i-1])
2648 do_bond = false;
2649 }
2650 /* condition not met: 2 salves */
2651 do_bond = (num_eth_ports == 2) ? do_bond : false;
2652
2653 /* handle only events that come with enough info */
2654 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2655 return NOTIFY_DONE;
2656
2657 priv = netdev_priv(ndev);
2658 if (do_bond) {
2659 struct netdev_notifier_bonding_info *notifier_info = ptr;
2660 struct netdev_bonding_info *bonding_info =
2661 &notifier_info->bonding_info;
2662
2663 /* required mode 1, 2 or 4 */
2664 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2665 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2666 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2667 do_bond = false;
2668
2669 /* require exactly 2 slaves */
2670 if (bonding_info->master.num_slaves != 2)
2671 do_bond = false;
2672
2673 /* calc v2p */
2674 if (do_bond) {
2675 if (bonding_info->master.bond_mode ==
2676 BOND_MODE_ACTIVEBACKUP) {
2677 /* in active-backup mode virtual ports are
2678 * mapped to the physical port of the active
2679 * slave */
2680 if (bonding_info->slave.state ==
2681 BOND_STATE_BACKUP) {
2682 if (port == 1) {
2683 v2p_port1 = 2;
2684 v2p_port2 = 2;
2685 } else {
2686 v2p_port1 = 1;
2687 v2p_port2 = 1;
2688 }
2689 } else { /* BOND_STATE_ACTIVE */
2690 if (port == 1) {
2691 v2p_port1 = 1;
2692 v2p_port2 = 1;
2693 } else {
2694 v2p_port1 = 2;
2695 v2p_port2 = 2;
2696 }
2697 }
2698 } else { /* Active-Active */
2699 /* in active-active mode a virtual port is
2700 * mapped to the native physical port if and only
2701 * if the physical port is up */
2702 __s8 link = bonding_info->slave.link;
2703
2704 if (port == 1)
2705 v2p_port2 = 2;
2706 else
2707 v2p_port1 = 1;
2708 if ((link == BOND_LINK_UP) ||
2709 (link == BOND_LINK_FAIL)) {
2710 if (port == 1)
2711 v2p_port1 = 1;
2712 else
2713 v2p_port2 = 2;
2714 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
2715 if (port == 1)
2716 v2p_port1 = 2;
2717 else
2718 v2p_port2 = 1;
2719 }
2720 }
2721 }
2722 }
2723
2724 mlx4_en_queue_bond_work(priv, do_bond,
2725 v2p_port1, v2p_port2);
2726
2727 return NOTIFY_DONE;
2728}
2729
0b131561
MB		 2730void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
2731 struct mlx4_en_stats_bitmap *stats_bitmap,
2732 u8 rx_ppp, u8 rx_pause,
2733 u8 tx_ppp, u8 tx_pause)
2734{
b42de4d0 2735 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
0b131561
MB		 2736
2737 if (!mlx4_is_slave(dev) &&
2738 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
2739 mutex_lock(&stats_bitmap->mutex);
2740 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
2741
2742 if (rx_ppp)
2743 bitmap_set(stats_bitmap->bitmap, last_i,
2744 NUM_FLOW_PRIORITY_STATS_RX);
2745 last_i += NUM_FLOW_PRIORITY_STATS_RX;
2746
2747 if (rx_pause && !(rx_ppp))
2748 bitmap_set(stats_bitmap->bitmap, last_i,
2749 NUM_FLOW_STATS_RX);
2750 last_i += NUM_FLOW_STATS_RX;
2751
2752 if (tx_ppp)
2753 bitmap_set(stats_bitmap->bitmap, last_i,
2754 NUM_FLOW_PRIORITY_STATS_TX);
2755 last_i += NUM_FLOW_PRIORITY_STATS_TX;
2756
2757 if (tx_pause && !(tx_ppp))
2758 bitmap_set(stats_bitmap->bitmap, last_i,
2759 NUM_FLOW_STATS_TX);
2760 last_i += NUM_FLOW_STATS_TX;
2761
2762 mutex_unlock(&stats_bitmap->mutex);
2763 }
2764}
2765
6fcd2735 2766void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 2767 struct mlx4_en_stats_bitmap *stats_bitmap,
2768 u8 rx_ppp, u8 rx_pause,
2769 u8 tx_ppp, u8 tx_pause)
ffa88f37 2770{
6fcd2735
EBE		 2771 int last_i = 0;
2772
3da8a36c
EBE		 2773 mutex_init(&stats_bitmap->mutex);
2774 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 2775
2776 if (mlx4_is_slave(dev)) {
3da8a36c 2777 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2778 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 2779 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2780 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 2781 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2782 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 2783 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2784 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 2785 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2786 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 2787 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 2788 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
2789 } else {
3da8a36c 2790 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 2791 }
6fcd2735 2792 last_i += NUM_MAIN_STATS;
ffa88f37 2793
3da8a36c 2794 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 2795 last_i += NUM_PORT_STATS;
ffa88f37 2796
b42de4d0
EBE		 2797 if (mlx4_is_master(dev))
2798 bitmap_set(stats_bitmap->bitmap, last_i,
2799 NUM_PF_STATS);
2800 last_i += NUM_PF_STATS;
2801
0b131561
MB		 2802 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
2803 rx_ppp, rx_pause,
2804 tx_ppp, tx_pause);
2805 last_i += NUM_FLOW_STATS;
2806
6fcd2735 2807 if (!mlx4_is_slave(dev))
3da8a36c 2808 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
ffa88f37
EBE		 2809}
2810
c27a02cd
YP		 2811int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2812 struct mlx4_en_port_profile *prof)
2813{
2814 struct net_device *dev;
2815 struct mlx4_en_priv *priv;
c07cb4b0 2816 int i;
c27a02cd
YP		 2817 int err;
2818
f1593d22 2819 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2820 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2821 if (dev == NULL)
c27a02cd 2822 return -ENOMEM;
c27a02cd 2823
d317966b
AV		 2824 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2825 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2826
872bf2fb 2827 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 2828 dev->dev_port = port - 1;
c27a02cd
YP		 2829
2830 /*
2831 * Initialize driver private data
2832 */
2833
2834 priv = netdev_priv(dev);
2835 memset(priv, 0, sizeof(struct mlx4_en_priv));
6de5f7f6 2836 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
207af6c5
EE		 2837 spin_lock_init(&priv->stats_lock);
2838 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
2839 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2840 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2841 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
2842 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
207af6c5
EE		 2843 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
2844 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
207af6c5
EE		 2845#ifdef CONFIG_RFS_ACCEL
2846 INIT_LIST_HEAD(&priv->filters);
2847 spin_lock_init(&priv->filters_lock);
2848#endif
2849
c27a02cd
YP		 2850 priv->dev = dev;
2851 priv->mdev = mdev;
ebf8c9aa 2852 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2853 priv->prof = prof;
2854 priv->port = port;
2855 priv->port_up = false;
c27a02cd 2856 priv->flags = prof->flags;
0fef9d03 2857 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 2858 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2859 MLX4_WQE_CTRL_SOLICITED);
d317966b 2860 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2861 priv->tx_ring_num = prof->tx_ring_num;
fbc6daf1 2862 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 2863 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 2864
41d942d5 2865 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2866 GFP_KERNEL);
bc6a4744
AV		 2867 if (!priv->tx_ring) {
2868 err = -ENOMEM;
2869 goto out;
2870 }
41d942d5 2871 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2872 GFP_KERNEL);
bc6a4744
AV		 2873 if (!priv->tx_cq) {
2874 err = -ENOMEM;
2875 goto out;
2876 }
c27a02cd 2877 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2878 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 2879 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 2880 priv->mac_index = -1;
2881 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 2882#ifdef CONFIG_MLX4_EN_DCB
540b3a39 2883 if (!mlx4_is_slave(priv->mdev->dev)) {
3742cc65 2884 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 2885 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2886 } else {
2887 en_info(priv, "enabling only PFC DCB ops\n");
2888 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2889 }
2890 }
564c274c 2891#endif
c27a02cd 2892
c07cb4b0
YB		 2893 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2894 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2895
c27a02cd
YP		 2896 /* Query for default mac and max mtu */
2897 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 2898
f8c6455b
SM		 2899 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
2900 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
2901 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
2902
6bbb6d99
YB		 2903 /* Set default MAC */
2904 dev->addr_len = ETH_ALEN;
2905 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2906 if (!is_valid_ether_addr(dev->dev_addr)) {
2b3ddf27
JM		 2907 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2908 priv->port, dev->dev_addr);
2909 err = -EINVAL;
2910 goto out;
2911 } else if (mlx4_is_slave(priv->mdev->dev) &&
2912 (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
2913 /* Random MAC was assigned in mlx4_slave_cap
2914 * in mlx4_core module
2915 */
2916 dev->addr_assign_type |= NET_ADDR_RANDOM;
2917 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
c27a02cd
YP		 2918 }
2919
2695bab2 2920 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 2921
c27a02cd
YP		 2922 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2923 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2924 err = mlx4_en_alloc_resources(priv);
2925 if (err)
2926 goto out;
2927
ec693d47
AV		 2928 /* Initialize time stamping config */
2929 priv->hwtstamp_config.flags = 0;
2930 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2931 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2932
c27a02cd
YP		 2933 /* Allocate page for receive rings */
2934 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
73898db0 2935 MLX4_EN_PAGE_SIZE);
c27a02cd 2936 if (err) {
453a6082 2937 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2938 goto out;
2939 }
2940 priv->allocated = 1;
2941
c27a02cd
YP		 2942 /*
2943 * Initialize netdev entry points
2944 */
8f7ba3ca
RE		 2945 if (mlx4_is_master(priv->mdev->dev))
2946 dev->netdev_ops = &mlx4_netdev_ops_master;
2947 else
2948 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2949 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2950 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2951 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2952
7ad24ea4 2953 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 2954
c27a02cd
YP		 2955 /*
2956 * Set driver features
2957 */
c8c64cff
MM		 2958 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2959 if (mdev->LSO_support)
2960 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2961
2962 dev->vlan_features = dev->hw_features;
2963
ad86107f 2964 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2965 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2966 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2967 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 2968 dev->hw_features |= NETIF_F_LOOPBACK |
2969 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 2970
e38af4fa
HHZ		 2971 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2972 dev->features |= NETIF_F_HW_VLAN_STAG_RX |
2973 NETIF_F_HW_VLAN_STAG_FILTER;
2974 dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
2975 }
2976
2977 if (mlx4_is_slave(mdev->dev)) {
2978 int phv;
2979
2980 err = get_phv_bit(mdev->dev, port, &phv);
2981 if (!err && phv) {
2982 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
2983 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
2984 }
2985 } else {
2986 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2987 !(mdev->dev->caps.flags2 &
2988 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2989 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
2990 }
2991
f0df3503
MM		 2992 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
2993 dev->hw_features |= NETIF_F_RXFCS;
2994
78500b8c
MM		 2995 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
2996 dev->hw_features |= NETIF_F_RXALL;
2997
1eb8c695 2998 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 2999 MLX4_STEERING_MODE_DEVICE_MANAGED &&
3000 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 3001 dev->hw_features |= NETIF_F_NTUPLE;
3002
cc5387f7
YB		 3003 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
3004 dev->priv_flags |= IFF_UNICAST_FLT;
3005
947cbb0a
EP		 3006 /* Setting a default hash function value */
3007 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
3008 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3009 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
3010 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
3011 } else {
3012 en_warn(priv,
3013 "No RSS hash capabilities exposed, using Toeplitz\n");
3014 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3015 }
3016
925ab1aa 3017 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3c9346b2
AD		 3018 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3019 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3020 NETIF_F_GSO_PARTIAL;
3021 dev->features |= NETIF_F_GSO_UDP_TUNNEL |
3022 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3023 NETIF_F_GSO_PARTIAL;
3024 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
925ab1aa
EE		 3025 }
3026
c27a02cd 3027 mdev->pndev[port] = dev;
5da03547 3028 mdev->upper[port] = NULL;
c27a02cd
YP		 3029
3030 netif_carrier_off(dev);
4801ae70
EE		 3031 mlx4_en_set_default_moderation(priv);
3032
453a6082
YP		 3033 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
3034 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
3035
79aeaccd
YB		 3036 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
3037
90822265 3038 /* Configure port */
5c8e9046 3039 mlx4_en_calc_rx_buf(dev);
90822265 3040 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 3041 priv->rx_skb_size + ETH_FCS_LEN,
3042 prof->tx_pause, prof->tx_ppp,
3043 prof->rx_pause, prof->rx_ppp);
90822265 3044 if (err) {
1a91de28
JP		 3045 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3046 priv->port, err);
90822265
YP		 3047 goto out;
3048 }
3049
837052d0 3050 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 3051 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 3052 if (err) {
3053 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3054 err);
3055 goto out;
3056 }
3057 }
3058
90822265
YP		 3059 /* Init port */
3060 en_warn(priv, "Initializing port\n");
3061 err = mlx4_INIT_PORT(mdev->dev, priv->port);
3062 if (err) {
3063 en_err(priv, "Failed Initializing port\n");
3064 goto out;
3065 }
c27a02cd 3066 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea 3067
90683061 3068 /* Initialize time stamp mechanism */
dc8142ea 3069 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
90683061
EE		 3070 mlx4_en_init_timestamp(mdev);
3071
fc9f5ea9
EE		 3072 queue_delayed_work(mdev->workqueue, &priv->service_task,
3073 SERVICE_TASK_DELAY);
dc8142ea 3074
0b131561
MB		 3075 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3076 mdev->profile.prof[priv->port].rx_ppp,
3077 mdev->profile.prof[priv->port].rx_pause,
3078 mdev->profile.prof[priv->port].tx_ppp,
3079 mdev->profile.prof[priv->port].tx_pause);
39de961a 3080
e5eda89d
IS		 3081 err = register_netdev(dev);
3082 if (err) {
3083 en_err(priv, "Netdev registration failed for port %d\n", port);
3084 goto out;
3085 }
3086
3087 priv->registered = 1;
09d4d087
JP		 3088 devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port),
3089 dev);
e5eda89d 3090
c27a02cd
YP		 3091 return 0;
3092
3093out:
3094 mlx4_en_destroy_netdev(dev);
3095 return err;
3096}
3097
537f6f95
SM		 3098int mlx4_en_reset_config(struct net_device *dev,
3099 struct hwtstamp_config ts_config,
3100 netdev_features_t features)
3101{
3102 struct mlx4_en_priv *priv = netdev_priv(dev);
3103 struct mlx4_en_dev *mdev = priv->mdev;
3104 int port_up = 0;
3105 int err = 0;
3106
3107 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3108 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
f0df3503
MM		 3109 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3110 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
537f6f95
SM		 3111 return 0; /* Nothing to change */
3112
3113 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3114 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3115 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3116 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3117 return -EINVAL;
3118 }
3119
3120 mutex_lock(&mdev->state_lock);
3121 if (priv->port_up) {
3122 port_up = 1;
3123 mlx4_en_stop_port(dev, 1);
3124 }
3125
3126 mlx4_en_free_resources(priv);
3127
3128 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
3129 ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX));
3130
3131 priv->hwtstamp_config.tx_type = ts_config.tx_type;
3132 priv->hwtstamp_config.rx_filter = ts_config.rx_filter;
3133
3134 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3135 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3136 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3137 else
3138 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3139 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3140 /* RX time-stamping is OFF, update the RX vlan offload
3141 * to the latest wanted state
3142 */
3143 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3144 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3145 else
3146 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3147 }
3148
f0df3503
MM		 3149 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3150 if (features & NETIF_F_RXFCS)
3151 dev->features |= NETIF_F_RXFCS;
3152 else
3153 dev->features &= ~NETIF_F_RXFCS;
3154 }
3155
537f6f95
SM		 3156 /* RX vlan offload and RX time-stamping can't co-exist !
3157 * Regardless of the caller's choice,
3158 * Turn Off RX vlan offload in case of time-stamping is ON
3159 */
3160 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3161 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3162 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3163 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3164 }
3165
3166 err = mlx4_en_alloc_resources(priv);
3167 if (err) {
3168 en_err(priv, "Failed reallocating port resources\n");
3169 goto out;
3170 }
3171 if (port_up) {
3172 err = mlx4_en_start_port(dev);
3173 if (err)
3174 en_err(priv, "Failed starting port\n");
3175 }
3176
3177out:
3178 mutex_unlock(&mdev->state_lock);
3179 netdev_features_change(dev);
3180 return err;
3181}
Linux kernel - Deliverables
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