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Merge tag 'pm+acpi-3.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
c27a02cd
YP		 42
43#include <linux/mlx4/driver.h>
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/cmd.h>
46#include <linux/mlx4/cq.h>
47
48#include "mlx4_en.h"
49#include "en_port.h"
50
d317966b 51int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 52{
bc6a4744
AV		 53 struct mlx4_en_priv *priv = netdev_priv(dev);
54 int i;
d317966b 55 unsigned int offset = 0;
bc6a4744
AV		 56
57 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 58 return -EINVAL;
59
bc6a4744
AV		 60 netdev_set_num_tc(dev, up);
61
62 /* Partition Tx queues evenly amongst UP's */
bc6a4744 63 for (i = 0; i < up; i++) {
d317966b
AV		 64 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
65 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 66 }
67
897d7846
AV		 68 return 0;
69}
70
e0d1095a 71#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 72/* must be called with local_bh_disable()d */
73static int mlx4_en_low_latency_recv(struct napi_struct *napi)
74{
75 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
76 struct net_device *dev = cq->dev;
77 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 78 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 79 int done;
80
81 if (!priv->port_up)
82 return LL_FLUSH_FAILED;
83
84 if (!mlx4_en_cq_lock_poll(cq))
85 return LL_FLUSH_BUSY;
86
87 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 88 if (likely(done))
89 rx_ring->cleaned += done;
90 else
91 rx_ring->misses++;
9e77a2b8
AV		 92
93 mlx4_en_cq_unlock_poll(cq);
94
95 return done;
96}
e0d1095a 97#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 98
1eb8c695
AV		 99#ifdef CONFIG_RFS_ACCEL
100
101struct mlx4_en_filter {
102 struct list_head next;
103 struct work_struct work;
104
75a353d4 105 u8 ip_proto;
1eb8c695
AV		 106 __be32 src_ip;
107 __be32 dst_ip;
108 __be16 src_port;
109 __be16 dst_port;
110
111 int rxq_index;
112 struct mlx4_en_priv *priv;
113 u32 flow_id; /* RFS infrastructure id */
114 int id; /* mlx4_en driver id */
115 u64 reg_id; /* Flow steering API id */
116 u8 activated; /* Used to prevent expiry before filter
117 * is attached
118 */
119 struct hlist_node filter_chain;
120};
121
122static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
123
75a353d4
EP		 124static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
125{
126 switch (ip_proto) {
127 case IPPROTO_UDP:
128 return MLX4_NET_TRANS_RULE_ID_UDP;
129 case IPPROTO_TCP:
130 return MLX4_NET_TRANS_RULE_ID_TCP;
131 default:
132 return -EPROTONOSUPPORT;
133 }
134};
135
1eb8c695
AV		 136static void mlx4_en_filter_work(struct work_struct *work)
137{
138 struct mlx4_en_filter *filter = container_of(work,
139 struct mlx4_en_filter,
140 work);
141 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 142 struct mlx4_spec_list spec_tcp_udp = {
143 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 144 {
145 .tcp_udp = {
146 .dst_port = filter->dst_port,
147 .dst_port_msk = (__force __be16)-1,
148 .src_port = filter->src_port,
149 .src_port_msk = (__force __be16)-1,
150 },
151 },
152 };
153 struct mlx4_spec_list spec_ip = {
154 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
155 {
156 .ipv4 = {
157 .dst_ip = filter->dst_ip,
158 .dst_ip_msk = (__force __be32)-1,
159 .src_ip = filter->src_ip,
160 .src_ip_msk = (__force __be32)-1,
161 },
162 },
163 };
164 struct mlx4_spec_list spec_eth = {
165 .id = MLX4_NET_TRANS_RULE_ID_ETH,
166 };
167 struct mlx4_net_trans_rule rule = {
168 .list = LIST_HEAD_INIT(rule.list),
169 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
170 .exclusive = 1,
171 .allow_loopback = 1,
f9162539 172 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 173 .port = priv->port,
174 .priority = MLX4_DOMAIN_RFS,
175 };
176 int rc;
1eb8c695
AV		 177 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
178
75a353d4
EP		 179 if (spec_tcp_udp.id < 0) {
180 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
181 filter->ip_proto);
182 goto ignore;
183 }
1eb8c695
AV		 184 list_add_tail(&spec_eth.list, &rule.list);
185 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 186 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 187
1eb8c695 188 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 189 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 190 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
191
192 filter->activated = 0;
193
194 if (filter->reg_id) {
195 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
196 if (rc && rc != -ENOENT)
197 en_err(priv, "Error detaching flow. rc = %d\n", rc);
198 }
199
200 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
201 if (rc)
202 en_err(priv, "Error attaching flow. err = %d\n", rc);
203
75a353d4 204ignore:
1eb8c695
AV		 205 mlx4_en_filter_rfs_expire(priv);
206
207 filter->activated = 1;
208}
209
210static inline struct hlist_head *
211filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
212 __be16 src_port, __be16 dst_port)
213{
214 unsigned long l;
215 int bucket_idx;
216
217 l = (__force unsigned long)src_port |
218 ((__force unsigned long)dst_port << 2);
219 l ^= (__force unsigned long)(src_ip ^ dst_ip);
220
221 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
222
223 return &priv->filter_hash[bucket_idx];
224}
225
226static struct mlx4_en_filter *
227mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 228 __be32 dst_ip, u8 ip_proto, __be16 src_port,
229 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 230{
231 struct mlx4_en_filter *filter = NULL;
232
233 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
234 if (!filter)
235 return NULL;
236
237 filter->priv = priv;
238 filter->rxq_index = rxq_index;
239 INIT_WORK(&filter->work, mlx4_en_filter_work);
240
241 filter->src_ip = src_ip;
242 filter->dst_ip = dst_ip;
75a353d4 243 filter->ip_proto = ip_proto;
1eb8c695
AV		 244 filter->src_port = src_port;
245 filter->dst_port = dst_port;
246
247 filter->flow_id = flow_id;
248
ee64c0ee 249 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 250
251 list_add_tail(&filter->next, &priv->filters);
252 hlist_add_head(&filter->filter_chain,
253 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
254 dst_port));
255
256 return filter;
257}
258
259static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
260{
261 struct mlx4_en_priv *priv = filter->priv;
262 int rc;
263
264 list_del(&filter->next);
265
266 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
267 if (rc && rc != -ENOENT)
268 en_err(priv, "Error detaching flow. rc = %d\n", rc);
269
270 kfree(filter);
271}
272
273static inline struct mlx4_en_filter *
274mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 275 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 276{
1eb8c695
AV		 277 struct mlx4_en_filter *filter;
278 struct mlx4_en_filter *ret = NULL;
279
b67bfe0d 280 hlist_for_each_entry(filter,
1eb8c695
AV		 281 filter_hash_bucket(priv, src_ip, dst_ip,
282 src_port, dst_port),
283 filter_chain) {
284 if (filter->src_ip == src_ip &&
285 filter->dst_ip == dst_ip &&
75a353d4 286 filter->ip_proto == ip_proto &&
1eb8c695
AV		 287 filter->src_port == src_port &&
288 filter->dst_port == dst_port) {
289 ret = filter;
290 break;
291 }
292 }
293
294 return ret;
295}
296
297static int
298mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
299 u16 rxq_index, u32 flow_id)
300{
301 struct mlx4_en_priv *priv = netdev_priv(net_dev);
302 struct mlx4_en_filter *filter;
303 const struct iphdr *ip;
304 const __be16 *ports;
75a353d4 305 u8 ip_proto;
1eb8c695
AV		 306 __be32 src_ip;
307 __be32 dst_ip;
308 __be16 src_port;
309 __be16 dst_port;
310 int nhoff = skb_network_offset(skb);
311 int ret = 0;
312
313 if (skb->protocol != htons(ETH_P_IP))
314 return -EPROTONOSUPPORT;
315
316 ip = (const struct iphdr *)(skb->data + nhoff);
317 if (ip_is_fragment(ip))
318 return -EPROTONOSUPPORT;
319
75a353d4
EP		 320 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
321 return -EPROTONOSUPPORT;
1eb8c695
AV		 322 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
323
75a353d4 324 ip_proto = ip->protocol;
1eb8c695
AV		 325 src_ip = ip->saddr;
326 dst_ip = ip->daddr;
327 src_port = ports[0];
328 dst_port = ports[1];
329
1eb8c695 330 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 331 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
332 src_port, dst_port);
1eb8c695
AV		 333 if (filter) {
334 if (filter->rxq_index == rxq_index)
335 goto out;
336
337 filter->rxq_index = rxq_index;
338 } else {
339 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 340 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 341 src_port, dst_port, flow_id);
342 if (!filter) {
343 ret = -ENOMEM;
344 goto err;
345 }
346 }
347
348 queue_work(priv->mdev->workqueue, &filter->work);
349
350out:
351 ret = filter->id;
352err:
353 spin_unlock_bh(&priv->filters_lock);
354
355 return ret;
356}
357
41d942d5 358void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 359{
360 struct mlx4_en_filter *filter, *tmp;
361 LIST_HEAD(del_list);
362
363 spin_lock_bh(&priv->filters_lock);
364 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
365 list_move(&filter->next, &del_list);
366 hlist_del(&filter->filter_chain);
367 }
368 spin_unlock_bh(&priv->filters_lock);
369
370 list_for_each_entry_safe(filter, tmp, &del_list, next) {
371 cancel_work_sync(&filter->work);
372 mlx4_en_filter_free(filter);
373 }
374}
375
376static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
377{
378 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
379 LIST_HEAD(del_list);
380 int i = 0;
381
382 spin_lock_bh(&priv->filters_lock);
383 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
384 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
385 break;
386
387 if (filter->activated &&
388 !work_pending(&filter->work) &&
389 rps_may_expire_flow(priv->dev,
390 filter->rxq_index, filter->flow_id,
391 filter->id)) {
392 list_move(&filter->next, &del_list);
393 hlist_del(&filter->filter_chain);
394 } else
395 last_filter = filter;
396
397 i++;
398 }
399
400 if (last_filter && (&last_filter->next != priv->filters.next))
401 list_move(&priv->filters, &last_filter->next);
402
403 spin_unlock_bh(&priv->filters_lock);
404
405 list_for_each_entry_safe(filter, tmp, &del_list, next)
406 mlx4_en_filter_free(filter);
407}
408#endif
409
80d5c368
PM		 410static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
411 __be16 proto, u16 vid)
c27a02cd
YP		 412{
413 struct mlx4_en_priv *priv = netdev_priv(dev);
414 struct mlx4_en_dev *mdev = priv->mdev;
415 int err;
4c3eb3ca 416 int idx;
c27a02cd 417
f1b553fb 418 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 419
f1b553fb 420 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 421
422 /* Add VID to port VLAN filter */
423 mutex_lock(&mdev->state_lock);
424 if (mdev->device_up && priv->port_up) {
f1b553fb 425 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 426 if (err)
453a6082 427 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 428 }
4c3eb3ca 429 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 430 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 431 mutex_unlock(&mdev->state_lock);
4c3eb3ca 432
8e586137 433 return 0;
c27a02cd
YP		 434}
435
80d5c368
PM		 436static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
437 __be16 proto, u16 vid)
c27a02cd
YP		 438{
439 struct mlx4_en_priv *priv = netdev_priv(dev);
440 struct mlx4_en_dev *mdev = priv->mdev;
441 int err;
442
f1b553fb 443 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 444
f1b553fb 445 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 446
447 /* Remove VID from port VLAN filter */
448 mutex_lock(&mdev->state_lock);
2009d005 449 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 450
c27a02cd 451 if (mdev->device_up && priv->port_up) {
f1b553fb 452 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 453 if (err)
453a6082 454 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 455 }
456 mutex_unlock(&mdev->state_lock);
8e586137
JP		 457
458 return 0;
c27a02cd
YP		 459}
460
6bbb6d99
YB		 461static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
462{
bab6a9ea
YB		 463 int i;
464 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 465 dst_mac[i] = src_mac & 0xff;
466 src_mac >>= 8;
467 }
468 memset(&dst_mac[ETH_ALEN], 0, 2);
469}
470
837052d0
OG		 471
472static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
473 int qpn, u64 *reg_id)
474{
475 int err;
476 struct mlx4_spec_list spec_eth_outer = { {NULL} };
477 struct mlx4_spec_list spec_vxlan = { {NULL} };
478 struct mlx4_spec_list spec_eth_inner = { {NULL} };
479
480 struct mlx4_net_trans_rule rule = {
481 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
482 .exclusive = 0,
483 .allow_loopback = 1,
484 .promisc_mode = MLX4_FS_REGULAR,
485 .priority = MLX4_DOMAIN_NIC,
486 };
487
488 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
489
490 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
491 return 0; /* do nothing */
492
493 rule.port = priv->port;
494 rule.qpn = qpn;
495 INIT_LIST_HEAD(&rule.list);
496
497 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
498 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
499 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
500
501 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
502 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
503
504 list_add_tail(&spec_eth_outer.list, &rule.list);
505 list_add_tail(&spec_vxlan.list, &rule.list);
506 list_add_tail(&spec_eth_inner.list, &rule.list);
507
508 err = mlx4_flow_attach(priv->mdev->dev, &rule, reg_id);
509 if (err) {
510 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
511 return err;
512 }
513 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
514 return 0;
515}
516
517
16a10ffd
YB		 518static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
519 unsigned char *mac, int *qpn, u64 *reg_id)
520{
521 struct mlx4_en_dev *mdev = priv->mdev;
522 struct mlx4_dev *dev = mdev->dev;
523 int err;
524
525 switch (dev->caps.steering_mode) {
526 case MLX4_STEERING_MODE_B0: {
527 struct mlx4_qp qp;
528 u8 gid[16] = {0};
529
530 qp.qpn = *qpn;
531 memcpy(&gid[10], mac, ETH_ALEN);
532 gid[5] = priv->port;
533
534 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
535 break;
536 }
537 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
538 struct mlx4_spec_list spec_eth = { {NULL} };
539 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
540
541 struct mlx4_net_trans_rule rule = {
542 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
543 .exclusive = 0,
544 .allow_loopback = 1,
f9162539 545 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 546 .priority = MLX4_DOMAIN_NIC,
547 };
548
549 rule.port = priv->port;
550 rule.qpn = *qpn;
551 INIT_LIST_HEAD(&rule.list);
552
553 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
554 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
555 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
556 list_add_tail(&spec_eth.list, &rule.list);
557
558 err = mlx4_flow_attach(dev, &rule, reg_id);
559 break;
560 }
561 default:
562 return -EINVAL;
563 }
564 if (err)
565 en_warn(priv, "Failed Attaching Unicast\n");
566
567 return err;
568}
569
570static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
571 unsigned char *mac, int qpn, u64 reg_id)
572{
573 struct mlx4_en_dev *mdev = priv->mdev;
574 struct mlx4_dev *dev = mdev->dev;
575
576 switch (dev->caps.steering_mode) {
577 case MLX4_STEERING_MODE_B0: {
578 struct mlx4_qp qp;
579 u8 gid[16] = {0};
580
581 qp.qpn = qpn;
582 memcpy(&gid[10], mac, ETH_ALEN);
583 gid[5] = priv->port;
584
585 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
586 break;
587 }
588 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
589 mlx4_flow_detach(dev, reg_id);
590 break;
591 }
592 default:
593 en_err(priv, "Invalid steering mode.\n");
594 }
595}
596
597static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
598{
599 struct mlx4_en_dev *mdev = priv->mdev;
600 struct mlx4_dev *dev = mdev->dev;
601 struct mlx4_mac_entry *entry;
602 int index = 0;
603 int err = 0;
604 u64 reg_id;
605 int *qpn = &priv->base_qpn;
606 u64 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
607
608 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
609 priv->dev->dev_addr);
610 index = mlx4_register_mac(dev, priv->port, mac);
611 if (index < 0) {
612 err = index;
613 en_err(priv, "Failed adding MAC: %pM\n",
614 priv->dev->dev_addr);
615 return err;
616 }
617
618 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
619 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
620 *qpn = base_qpn + index;
621 return 0;
622 }
623
624 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
625 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
626 if (err) {
627 en_err(priv, "Failed to reserve qp for mac registration\n");
628 goto qp_err;
629 }
630
631 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
632 if (err)
633 goto steer_err;
634
9ba75fb0
WY		 635 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
636 &priv->tunnel_reg_id);
637 if (err)
837052d0
OG		 638 goto tunnel_err;
639
16a10ffd
YB		 640 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
641 if (!entry) {
642 err = -ENOMEM;
643 goto alloc_err;
644 }
645 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
646 entry->reg_id = reg_id;
647
c07cb4b0
YB		 648 hlist_add_head_rcu(&entry->hlist,
649 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 650
c07cb4b0 651 return 0;
16a10ffd
YB		 652
653alloc_err:
837052d0
OG		 654 if (priv->tunnel_reg_id)
655 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
656tunnel_err:
16a10ffd
YB		 657 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
658
659steer_err:
660 mlx4_qp_release_range(dev, *qpn, 1);
661
662qp_err:
663 mlx4_unregister_mac(dev, priv->port, mac);
664 return err;
665}
666
667static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
668{
669 struct mlx4_en_dev *mdev = priv->mdev;
670 struct mlx4_dev *dev = mdev->dev;
16a10ffd 671 int qpn = priv->base_qpn;
83a5a6ce 672 u64 mac;
16a10ffd 673
83a5a6ce
YB		 674 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
675 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
676 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
677 priv->dev->dev_addr);
678 mlx4_unregister_mac(dev, priv->port, mac);
679 } else {
c07cb4b0 680 struct mlx4_mac_entry *entry;
b67bfe0d 681 struct hlist_node *tmp;
c07cb4b0 682 struct hlist_head *bucket;
83a5a6ce 683 unsigned int i;
c07cb4b0 684
83a5a6ce
YB		 685 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
686 bucket = &priv->mac_hash[i];
687 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
688 mac = mlx4_en_mac_to_u64(entry->mac);
689 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
690 entry->mac);
c07cb4b0
YB		 691 mlx4_en_uc_steer_release(priv, entry->mac,
692 qpn, entry->reg_id);
c07cb4b0 693
83a5a6ce 694 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 695 hlist_del_rcu(&entry->hlist);
696 kfree_rcu(entry, rcu);
c07cb4b0 697 }
16a10ffd 698 }
83a5a6ce 699
837052d0
OG		 700 if (priv->tunnel_reg_id) {
701 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
702 priv->tunnel_reg_id = 0;
703 }
704
83a5a6ce
YB		 705 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
706 priv->port, qpn);
707 mlx4_qp_release_range(dev, qpn, 1);
708 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 709 }
710}
711
712static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 713 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 714{
715 struct mlx4_en_dev *mdev = priv->mdev;
716 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 717 int err = 0;
718 u64 new_mac_u64 = mlx4_en_mac_to_u64(new_mac);
719
720 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 721 struct hlist_head *bucket;
722 unsigned int mac_hash;
723 struct mlx4_mac_entry *entry;
b67bfe0d 724 struct hlist_node *tmp;
c07cb4b0
YB		 725 u64 prev_mac_u64 = mlx4_en_mac_to_u64(prev_mac);
726
727 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 728 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 729 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
730 mlx4_en_uc_steer_release(priv, entry->mac,
731 qpn, entry->reg_id);
732 mlx4_unregister_mac(dev, priv->port,
733 prev_mac_u64);
734 hlist_del_rcu(&entry->hlist);
735 synchronize_rcu();
736 memcpy(entry->mac, new_mac, ETH_ALEN);
737 entry->reg_id = 0;
738 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
739 hlist_add_head_rcu(&entry->hlist,
740 &priv->mac_hash[mac_hash]);
741 mlx4_register_mac(dev, priv->port, new_mac_u64);
742 err = mlx4_en_uc_steer_add(priv, new_mac,
743 &qpn,
744 &entry->reg_id);
2a2083f7
OG		 745 if (err)
746 return err;
747 if (priv->tunnel_reg_id) {
748 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
749 priv->tunnel_reg_id = 0;
750 }
751 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
752 &priv->tunnel_reg_id);
c07cb4b0
YB		 753 return err;
754 }
755 }
756 return -EINVAL;
16a10ffd
YB		 757 }
758
759 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
760}
761
e7c1c2c4 762u64 mlx4_en_mac_to_u64(u8 *addr)
c27a02cd
YP		 763{
764 u64 mac = 0;
765 int i;
766
767 for (i = 0; i < ETH_ALEN; i++) {
768 mac <<= 8;
769 mac |= addr[i];
770 }
771 return mac;
772}
773
bfa8ab47 774static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv)
c27a02cd 775{
c27a02cd
YP		 776 int err = 0;
777
c27a02cd
YP		 778 if (priv->port_up) {
779 /* Remove old MAC and insert the new one */
16a10ffd 780 err = mlx4_en_replace_mac(priv, priv->base_qpn,
90bbb74a 781 priv->dev->dev_addr, priv->prev_mac);
c27a02cd 782 if (err)
453a6082 783 en_err(priv, "Failed changing HW MAC address\n");
6bbb6d99
YB		 784 memcpy(priv->prev_mac, priv->dev->dev_addr,
785 sizeof(priv->prev_mac));
c27a02cd 786 } else
48e551ff 787 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 788
bfa8ab47
YB		 789 return err;
790}
791
792static int mlx4_en_set_mac(struct net_device *dev, void *addr)
793{
794 struct mlx4_en_priv *priv = netdev_priv(dev);
795 struct mlx4_en_dev *mdev = priv->mdev;
796 struct sockaddr *saddr = addr;
797 int err;
798
799 if (!is_valid_ether_addr(saddr->sa_data))
800 return -EADDRNOTAVAIL;
801
802 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
803
804 mutex_lock(&mdev->state_lock);
805 err = mlx4_en_do_set_mac(priv);
c27a02cd 806 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 807
808 return err;
c27a02cd
YP		 809}
810
811static void mlx4_en_clear_list(struct net_device *dev)
812{
813 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 814 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 815
6d199937
YP		 816 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
817 list_del(&mc_to_del->list);
818 kfree(mc_to_del);
819 }
c27a02cd
YP		 820}
821
822static void mlx4_en_cache_mclist(struct net_device *dev)
823{
824 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 825 struct netdev_hw_addr *ha;
6d199937 826 struct mlx4_en_mc_list *tmp;
ff6e2163 827
0e03567a 828 mlx4_en_clear_list(dev);
6d199937
YP		 829 netdev_for_each_mc_addr(ha, dev) {
830 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
831 if (!tmp) {
6d199937
YP		 832 mlx4_en_clear_list(dev);
833 return;
834 }
835 memcpy(tmp->addr, ha->addr, ETH_ALEN);
836 list_add_tail(&tmp->list, &priv->mc_list);
837 }
c27a02cd
YP		 838}
839
6d199937
YP		 840static void update_mclist_flags(struct mlx4_en_priv *priv,
841 struct list_head *dst,
842 struct list_head *src)
843{
844 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
845 bool found;
846
847 /* Find all the entries that should be removed from dst,
848 * These are the entries that are not found in src
849 */
850 list_for_each_entry(dst_tmp, dst, list) {
851 found = false;
852 list_for_each_entry(src_tmp, src, list) {
c0623e58 853 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 854 found = true;
855 break;
856 }
857 }
858 if (!found)
859 dst_tmp->action = MCLIST_REM;
860 }
861
862 /* Add entries that exist in src but not in dst
863 * mark them as need to add
864 */
865 list_for_each_entry(src_tmp, src, list) {
866 found = false;
867 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 868 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 869 dst_tmp->action = MCLIST_NONE;
870 found = true;
871 break;
872 }
873 }
874 if (!found) {
14f8dc49
JP		 875 new_mc = kmemdup(src_tmp,
876 sizeof(struct mlx4_en_mc_list),
6d199937 877 GFP_KERNEL);
14f8dc49 878 if (!new_mc)
6d199937 879 return;
14f8dc49 880
6d199937
YP		 881 new_mc->action = MCLIST_ADD;
882 list_add_tail(&new_mc->list, dst);
883 }
884 }
885}
c27a02cd 886
0eb74fdd 887static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 888{
889 struct mlx4_en_priv *priv = netdev_priv(dev);
890
891 if (!priv->port_up)
892 return;
893
0eb74fdd 894 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 895}
896
0eb74fdd
YB		 897static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
898 struct mlx4_en_dev *mdev)
c27a02cd 899{
c96d97f4 900 int err = 0;
c27a02cd 901
0eb74fdd 902 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 903 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 904 en_warn(priv, "Entering promiscuous mode\n");
905 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 906
0eb74fdd 907 /* Enable promiscouos mode */
c96d97f4 908 switch (mdev->dev->caps.steering_mode) {
592e49dd 909 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 910 err = mlx4_flow_steer_promisc_add(mdev->dev,
911 priv->port,
912 priv->base_qpn,
f9162539 913 MLX4_FS_ALL_DEFAULT);
592e49dd 914 if (err)
0eb74fdd
YB		 915 en_err(priv, "Failed enabling promiscuous mode\n");
916 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 917 break;
918
c96d97f4 919 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 920 err = mlx4_unicast_promisc_add(mdev->dev,
921 priv->base_qpn,
922 priv->port);
c96d97f4 923 if (err)
0eb74fdd
YB		 924 en_err(priv, "Failed enabling unicast promiscuous mode\n");
925
926 /* Add the default qp number as multicast
927 * promisc
928 */
929 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
930 err = mlx4_multicast_promisc_add(mdev->dev,
931 priv->base_qpn,
932 priv->port);
c96d97f4 933 if (err)
0eb74fdd
YB		 934 en_err(priv, "Failed enabling multicast promiscuous mode\n");
935 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 936 }
937 break;
c27a02cd 938
c96d97f4
HHZ		 939 case MLX4_STEERING_MODE_A0:
940 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
941 priv->port,
0eb74fdd
YB		 942 priv->base_qpn,
943 1);
1679200f 944 if (err)
0eb74fdd 945 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 946 break;
1679200f
YP		 947 }
948
0eb74fdd
YB		 949 /* Disable port multicast filter (unconditionally) */
950 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
951 0, MLX4_MCAST_DISABLE);
952 if (err)
953 en_err(priv, "Failed disabling multicast filter\n");
954
955 /* Disable port VLAN filter */
f1b553fb 956 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 957 if (err)
0eb74fdd
YB		 958 en_err(priv, "Failed disabling VLAN filter\n");
959 }
960}
961
962static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
963 struct mlx4_en_dev *mdev)
964{
965 int err = 0;
966
967 if (netif_msg_rx_status(priv))
968 en_warn(priv, "Leaving promiscuous mode\n");
969 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
970
971 /* Disable promiscouos mode */
972 switch (mdev->dev->caps.steering_mode) {
973 case MLX4_STEERING_MODE_DEVICE_MANAGED:
974 err = mlx4_flow_steer_promisc_remove(mdev->dev,
975 priv->port,
f9162539 976 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 977 if (err)
978 en_err(priv, "Failed disabling promiscuous mode\n");
979 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
980 break;
981
982 case MLX4_STEERING_MODE_B0:
983 err = mlx4_unicast_promisc_remove(mdev->dev,
984 priv->base_qpn,
985 priv->port);
986 if (err)
987 en_err(priv, "Failed disabling unicast promiscuous mode\n");
988 /* Disable Multicast promisc */
989 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
990 err = mlx4_multicast_promisc_remove(mdev->dev,
991 priv->base_qpn,
992 priv->port);
993 if (err)
994 en_err(priv, "Failed disabling multicast promiscuous mode\n");
995 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
996 }
997 break;
998
999 case MLX4_STEERING_MODE_A0:
1000 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
1001 priv->port,
1002 priv->base_qpn, 0);
1003 if (err)
1004 en_err(priv, "Failed disabling promiscuous mode\n");
1005 break;
c27a02cd
YP		 1006 }
1007
0eb74fdd
YB		 1008 /* Enable port VLAN filter */
1009 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
1010 if (err)
1011 en_err(priv, "Failed enabling VLAN filter\n");
1012}
1013
1014static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
1015 struct net_device *dev,
1016 struct mlx4_en_dev *mdev)
1017{
1018 struct mlx4_en_mc_list *mclist, *tmp;
1019 u64 mcast_addr = 0;
1020 u8 mc_list[16] = {0};
1021 int err = 0;
1022
c27a02cd
YP		 1023 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
1024 if (dev->flags & IFF_ALLMULTI) {
1025 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1026 0, MLX4_MCAST_DISABLE);
1027 if (err)
453a6082 1028 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 1029
1030 /* Add the default qp number as multicast promisc */
1031 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 1032 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1033 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1034 err = mlx4_flow_steer_promisc_add(mdev->dev,
1035 priv->port,
1036 priv->base_qpn,
f9162539 1037 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1038 break;
1039
c96d97f4
HHZ		 1040 case MLX4_STEERING_MODE_B0:
1041 err = mlx4_multicast_promisc_add(mdev->dev,
1042 priv->base_qpn,
1043 priv->port);
1044 break;
1045
1046 case MLX4_STEERING_MODE_A0:
1047 break;
1048 }
1679200f
YP		 1049 if (err)
1050 en_err(priv, "Failed entering multicast promisc mode\n");
1051 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1052 }
c27a02cd 1053 } else {
1679200f
YP		 1054 /* Disable Multicast promisc */
1055 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1056 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1057 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1058 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1059 priv->port,
f9162539 1060 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1061 break;
1062
c96d97f4
HHZ		 1063 case MLX4_STEERING_MODE_B0:
1064 err = mlx4_multicast_promisc_remove(mdev->dev,
1065 priv->base_qpn,
1066 priv->port);
1067 break;
1068
1069 case MLX4_STEERING_MODE_A0:
1070 break;
1071 }
1679200f 1072 if (err)
25985edc 1073 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1074 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1075 }
ff6e2163 1076
c27a02cd
YP		 1077 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1078 0, MLX4_MCAST_DISABLE);
1079 if (err)
453a6082 1080 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1081
1082 /* Flush mcast filter and init it with broadcast address */
1083 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1084 1, MLX4_MCAST_CONFIG);
1085
1086 /* Update multicast list - we cache all addresses so they won't
1087 * change while HW is updated holding the command semaphor */
dbd501a8 1088 netif_addr_lock_bh(dev);
c27a02cd 1089 mlx4_en_cache_mclist(dev);
dbd501a8 1090 netif_addr_unlock_bh(dev);
6d199937
YP		 1091 list_for_each_entry(mclist, &priv->mc_list, list) {
1092 mcast_addr = mlx4_en_mac_to_u64(mclist->addr);
c27a02cd
YP		 1093 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1094 mcast_addr, 0, MLX4_MCAST_CONFIG);
1095 }
1096 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1097 0, MLX4_MCAST_ENABLE);
1098 if (err)
453a6082 1099 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1100
1101 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1102 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1103 if (mclist->action == MCLIST_REM) {
1104 /* detach this address and delete from list */
1105 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1106 mc_list[5] = priv->port;
1107 err = mlx4_multicast_detach(mdev->dev,
1108 &priv->rss_map.indir_qp,
1109 mc_list,
0ff1fb65
HHZ		 1110 MLX4_PROT_ETH,
1111 mclist->reg_id);
6d199937
YP		 1112 if (err)
1113 en_err(priv, "Fail to detach multicast address\n");
1114
837052d0
OG		 1115 if (mclist->tunnel_reg_id) {
1116 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1117 if (err)
1118 en_err(priv, "Failed to detach multicast address\n");
1119 }
1120
6d199937
YP		 1121 /* remove from list */
1122 list_del(&mclist->list);
1123 kfree(mclist);
9c64508a 1124 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1125 /* attach the address */
1126 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1127 /* needed for B0 steering support */
6d199937
YP		 1128 mc_list[5] = priv->port;
1129 err = mlx4_multicast_attach(mdev->dev,
1130 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1131 mc_list,
1132 priv->port, 0,
1133 MLX4_PROT_ETH,
1134 &mclist->reg_id);
6d199937
YP		 1135 if (err)
1136 en_err(priv, "Fail to attach multicast address\n");
1137
837052d0
OG		 1138 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1139 &mclist->tunnel_reg_id);
1140 if (err)
1141 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1142 }
1143 }
c27a02cd 1144 }
0eb74fdd
YB		 1145}
1146
cc5387f7
YB		 1147static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1148 struct net_device *dev,
1149 struct mlx4_en_dev *mdev)
1150{
1151 struct netdev_hw_addr *ha;
1152 struct mlx4_mac_entry *entry;
b67bfe0d 1153 struct hlist_node *tmp;
cc5387f7
YB		 1154 bool found;
1155 u64 mac;
1156 int err = 0;
1157 struct hlist_head *bucket;
1158 unsigned int i;
1159 int removed = 0;
1160 u32 prev_flags;
1161
1162 /* Note that we do not need to protect our mac_hash traversal with rcu,
1163 * since all modification code is protected by mdev->state_lock
1164 */
1165
1166 /* find what to remove */
1167 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1168 bucket = &priv->mac_hash[i];
b67bfe0d 1169 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1170 found = false;
1171 netdev_for_each_uc_addr(ha, dev) {
1172 if (ether_addr_equal_64bits(entry->mac,
1173 ha->addr)) {
1174 found = true;
1175 break;
1176 }
1177 }
1178
1179 /* MAC address of the port is not in uc list */
1180 if (ether_addr_equal_64bits(entry->mac, dev->dev_addr))
1181 found = true;
1182
1183 if (!found) {
1184 mac = mlx4_en_mac_to_u64(entry->mac);
1185 mlx4_en_uc_steer_release(priv, entry->mac,
1186 priv->base_qpn,
1187 entry->reg_id);
1188 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1189
1190 hlist_del_rcu(&entry->hlist);
1191 kfree_rcu(entry, rcu);
1192 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1193 entry->mac, priv->port);
1194 ++removed;
1195 }
1196 }
1197 }
1198
1199 /* if we didn't remove anything, there is no use in trying to add
1200 * again once we are in a forced promisc mode state
1201 */
1202 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1203 return;
1204
1205 prev_flags = priv->flags;
1206 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1207
1208 /* find what to add */
1209 netdev_for_each_uc_addr(ha, dev) {
1210 found = false;
1211 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1212 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1213 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1214 found = true;
1215 break;
1216 }
1217 }
1218
1219 if (!found) {
1220 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1221 if (!entry) {
1222 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1223 ha->addr, priv->port);
1224 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1225 break;
1226 }
1227 mac = mlx4_en_mac_to_u64(ha->addr);
1228 memcpy(entry->mac, ha->addr, ETH_ALEN);
1229 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1230 if (err < 0) {
1231 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1232 ha->addr, priv->port, err);
1233 kfree(entry);
1234 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1235 break;
1236 }
1237 err = mlx4_en_uc_steer_add(priv, ha->addr,
1238 &priv->base_qpn,
1239 &entry->reg_id);
1240 if (err) {
1241 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1242 ha->addr, priv->port, err);
1243 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1244 kfree(entry);
1245 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1246 break;
1247 } else {
1248 unsigned int mac_hash;
1249 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1250 ha->addr, priv->port);
1251 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1252 bucket = &priv->mac_hash[mac_hash];
1253 hlist_add_head_rcu(&entry->hlist, bucket);
1254 }
1255 }
1256 }
1257
1258 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1259 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1260 priv->port);
1261 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1262 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1263 priv->port);
1264 }
1265}
1266
0eb74fdd
YB		 1267static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1268{
1269 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1270 rx_mode_task);
1271 struct mlx4_en_dev *mdev = priv->mdev;
1272 struct net_device *dev = priv->dev;
1273
1274 mutex_lock(&mdev->state_lock);
1275 if (!mdev->device_up) {
1276 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1277 goto out;
1278 }
1279 if (!priv->port_up) {
1280 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1281 goto out;
1282 }
1283
1284 if (!netif_carrier_ok(dev)) {
1285 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1286 if (priv->port_state.link_state) {
1287 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1288 netif_carrier_on(dev);
1289 en_dbg(LINK, priv, "Link Up\n");
1290 }
1291 }
1292 }
1293
cc5387f7
YB		 1294 if (dev->priv_flags & IFF_UNICAST_FLT)
1295 mlx4_en_do_uc_filter(priv, dev, mdev);
1296
0eb74fdd 1297 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1298 if ((dev->flags & IFF_PROMISC) ||
1299 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1300 mlx4_en_set_promisc_mode(priv, mdev);
1301 goto out;
1302 }
1303
1304 /* Not in promiscuous mode */
1305 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1306 mlx4_en_clear_promisc_mode(priv, mdev);
1307
1308 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1309out:
1310 mutex_unlock(&mdev->state_lock);
1311}
1312
1313#ifdef CONFIG_NET_POLL_CONTROLLER
1314static void mlx4_en_netpoll(struct net_device *dev)
1315{
1316 struct mlx4_en_priv *priv = netdev_priv(dev);
1317 struct mlx4_en_cq *cq;
1318 unsigned long flags;
1319 int i;
1320
1321 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1322 cq = priv->rx_cq[i];
c27a02cd
YP		 1323 spin_lock_irqsave(&cq->lock, flags);
1324 napi_synchronize(&cq->napi);
1325 mlx4_en_process_rx_cq(dev, cq, 0);
1326 spin_unlock_irqrestore(&cq->lock, flags);
1327 }
1328}
1329#endif
1330
1331static void mlx4_en_tx_timeout(struct net_device *dev)
1332{
1333 struct mlx4_en_priv *priv = netdev_priv(dev);
1334 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1335 int i;
c27a02cd
YP		 1336
1337 if (netif_msg_timer(priv))
453a6082 1338 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1339
b944ebec
YP		 1340 for (i = 0; i < priv->tx_ring_num; i++) {
1341 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1342 continue;
1343 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1344 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1345 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1346 }
1347
1e338db5 1348 priv->port_stats.tx_timeout++;
453a6082 1349 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1350 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1351}
1352
1353
1354static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1355{
1356 struct mlx4_en_priv *priv = netdev_priv(dev);
1357
1358 spin_lock_bh(&priv->stats_lock);
1359 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1360 spin_unlock_bh(&priv->stats_lock);
1361
1362 return &priv->ret_stats;
1363}
1364
1365static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1366{
c27a02cd
YP		 1367 struct mlx4_en_cq *cq;
1368 int i;
1369
1370 /* If we haven't received a specific coalescing setting
98a1708d 1371 * (module param), we set the moderation parameters as follows:
c27a02cd 1372 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1373 * satisfy our coalescing target.
c27a02cd
YP		 1374 * - moder_time is set to a fixed value.
1375 */
3db36fb2 1376 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1377 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1378 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1379 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1380 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1381 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1382
1383 /* Setup cq moderation params */
1384 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1385 cq = priv->rx_cq[i];
c27a02cd
YP		 1386 cq->moder_cnt = priv->rx_frames;
1387 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1388 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1389 priv->last_moder_packets[i] = 0;
1390 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1391 }
1392
1393 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1394 cq = priv->tx_cq[i];
a19a848a
YP		 1395 cq->moder_cnt = priv->tx_frames;
1396 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1397 }
1398
1399 /* Reset auto-moderation params */
1400 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1401 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1402 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1403 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1404 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1405 priv->adaptive_rx_coal = 1;
c27a02cd 1406 priv->last_moder_jiffies = 0;
c27a02cd 1407 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1408}
1409
1410static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1411{
1412 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1413 struct mlx4_en_cq *cq;
1414 unsigned long packets;
1415 unsigned long rate;
1416 unsigned long avg_pkt_size;
1417 unsigned long rx_packets;
1418 unsigned long rx_bytes;
c27a02cd
YP		 1419 unsigned long rx_pkt_diff;
1420 int moder_time;
6b4d8d9f 1421 int ring, err;
c27a02cd
YP		 1422
1423 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1424 return;
1425
6b4d8d9f
AG		 1426 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1427 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1428 rx_packets = priv->rx_ring[ring]->packets;
1429 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1430 spin_unlock_bh(&priv->stats_lock);
1431
1432 rx_pkt_diff = ((unsigned long) (rx_packets -
1433 priv->last_moder_packets[ring]));
1434 packets = rx_pkt_diff;
1435 rate = packets * HZ / period;
1436 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1437 priv->last_moder_bytes[ring])) / packets : 0;
1438
1439 /* Apply auto-moderation only when packet rate
1440 * exceeds a rate that it matters */
1441 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1442 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1443 if (rate < priv->pkt_rate_low)
1444 moder_time = priv->rx_usecs_low;
1445 else if (rate > priv->pkt_rate_high)
1446 moder_time = priv->rx_usecs_high;
1447 else
1448 moder_time = (rate - priv->pkt_rate_low) *
1449 (priv->rx_usecs_high - priv->rx_usecs_low) /
1450 (priv->pkt_rate_high - priv->pkt_rate_low) +
1451 priv->rx_usecs_low;
6b4d8d9f
AG		 1452 } else {
1453 moder_time = priv->rx_usecs_low;
c27a02cd 1454 }
c27a02cd 1455
6b4d8d9f
AG		 1456 if (moder_time != priv->last_moder_time[ring]) {
1457 priv->last_moder_time[ring] = moder_time;
41d942d5 1458 cq = priv->rx_cq[ring];
c27a02cd 1459 cq->moder_time = moder_time;
a1c6693a 1460 cq->moder_cnt = priv->rx_frames;
c27a02cd 1461 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1462 if (err)
48e551ff
YB		 1463 en_err(priv, "Failed modifying moderation for cq:%d\n",
1464 ring);
c27a02cd 1465 }
6b4d8d9f
AG		 1466 priv->last_moder_packets[ring] = rx_packets;
1467 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1468 }
1469
c27a02cd
YP		 1470 priv->last_moder_jiffies = jiffies;
1471}
1472
1473static void mlx4_en_do_get_stats(struct work_struct *work)
1474{
bf6aede7 1475 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1476 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1477 stats_task);
1478 struct mlx4_en_dev *mdev = priv->mdev;
1479 int err;
1480
c27a02cd
YP		 1481 mutex_lock(&mdev->state_lock);
1482 if (mdev->device_up) {
6123db2e
JM		 1483 if (priv->port_up) {
1484 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1485 if (err)
1486 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1487
c27a02cd 1488 mlx4_en_auto_moderation(priv);
6123db2e 1489 }
c27a02cd
YP		 1490
1491 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1492 }
d7e1a487 1493 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
bfa8ab47 1494 mlx4_en_do_set_mac(priv);
d7e1a487
YP		 1495 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1496 }
c27a02cd
YP		 1497 mutex_unlock(&mdev->state_lock);
1498}
1499
b6c39bfc
AV		 1500/* mlx4_en_service_task - Run service task for tasks that needed to be done
1501 * periodically
1502 */
1503static void mlx4_en_service_task(struct work_struct *work)
1504{
1505 struct delayed_work *delay = to_delayed_work(work);
1506 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1507 service_task);
1508 struct mlx4_en_dev *mdev = priv->mdev;
1509
1510 mutex_lock(&mdev->state_lock);
1511 if (mdev->device_up) {
dc8142ea
AV		 1512 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1513 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV		 1514
1515 queue_delayed_work(mdev->workqueue, &priv->service_task,
1516 SERVICE_TASK_DELAY);
1517 }
1518 mutex_unlock(&mdev->state_lock);
1519}
1520
c27a02cd
YP		 1521static void mlx4_en_linkstate(struct work_struct *work)
1522{
1523 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1524 linkstate_task);
1525 struct mlx4_en_dev *mdev = priv->mdev;
1526 int linkstate = priv->link_state;
1527
1528 mutex_lock(&mdev->state_lock);
1529 /* If observable port state changed set carrier state and
1530 * report to system log */
1531 if (priv->last_link_state != linkstate) {
1532 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1533 en_info(priv, "Link Down\n");
c27a02cd
YP		 1534 netif_carrier_off(priv->dev);
1535 } else {
e5cc44b2 1536 en_info(priv, "Link Up\n");
c27a02cd
YP		 1537 netif_carrier_on(priv->dev);
1538 }
1539 }
1540 priv->last_link_state = linkstate;
1541 mutex_unlock(&mdev->state_lock);
1542}
1543
1544
18cc42a3 1545int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1546{
1547 struct mlx4_en_priv *priv = netdev_priv(dev);
1548 struct mlx4_en_dev *mdev = priv->mdev;
1549 struct mlx4_en_cq *cq;
1550 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1551 int rx_index = 0;
1552 int tx_index = 0;
c27a02cd
YP		 1553 int err = 0;
1554 int i;
1555 int j;
1679200f 1556 u8 mc_list[16] = {0};
c27a02cd
YP		 1557
1558 if (priv->port_up) {
453a6082 1559 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1560 return 0;
1561 }
1562
6d199937
YP		 1563 INIT_LIST_HEAD(&priv->mc_list);
1564 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1565 INIT_LIST_HEAD(&priv->ethtool_list);
1566 memset(&priv->ethtool_rules[0], 0,
1567 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1568
c27a02cd
YP		 1569 /* Calculate Rx buf size */
1570 dev->mtu = min(dev->mtu, priv->max_mtu);
1571 mlx4_en_calc_rx_buf(dev);
453a6082 1572 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1573
c27a02cd 1574 /* Configure rx cq's and rings */
38aab07c
YP		 1575 err = mlx4_en_activate_rx_rings(priv);
1576 if (err) {
453a6082 1577 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1578 return err;
1579 }
c27a02cd 1580 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1581 cq = priv->rx_cq[i];
c27a02cd 1582
9e77a2b8
AV		 1583 mlx4_en_cq_init_lock(cq);
1584
76532d0c 1585 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1586 if (err) {
453a6082 1587 en_err(priv, "Failed activating Rx CQ\n");
a4233304 1588 goto cq_err;
c27a02cd
YP		 1589 }
1590 for (j = 0; j < cq->size; j++)
1591 cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1592 err = mlx4_en_set_cq_moder(priv, cq);
1593 if (err) {
453a6082 1594 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1595 mlx4_en_deactivate_cq(priv, cq);
1596 goto cq_err;
1597 }
1598 mlx4_en_arm_cq(priv, cq);
41d942d5 1599 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1600 ++rx_index;
1601 }
1602
ffe455ad
EE		 1603 /* Set qp number */
1604 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1605 err = mlx4_en_get_qp(priv);
1679200f 1606 if (err) {
ffe455ad 1607 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1608 goto cq_err;
1609 }
1610 mdev->mac_removed[priv->port] = 0;
1611
c27a02cd
YP		 1612 err = mlx4_en_config_rss_steer(priv);
1613 if (err) {
453a6082 1614 en_err(priv, "Failed configuring rss steering\n");
1679200f 1615 goto mac_err;
c27a02cd
YP		 1616 }
1617
cabdc8ee
HHZ		 1618 err = mlx4_en_create_drop_qp(priv);
1619 if (err)
1620 goto rss_err;
1621
c27a02cd
YP		 1622 /* Configure tx cq's and rings */
1623 for (i = 0; i < priv->tx_ring_num; i++) {
1624 /* Configure cq */
41d942d5 1625 cq = priv->tx_cq[i];
76532d0c 1626 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1627 if (err) {
453a6082 1628 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1629 goto tx_err;
1630 }
1631 err = mlx4_en_set_cq_moder(priv, cq);
1632 if (err) {
453a6082 1633 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1634 mlx4_en_deactivate_cq(priv, cq);
1635 goto tx_err;
1636 }
453a6082 1637 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1638 cq->buf->wqe_index = cpu_to_be16(0xffff);
1639
1640 /* Configure ring */
41d942d5 1641 tx_ring = priv->tx_ring[i];
0e98b523 1642 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1643 i / priv->num_tx_rings_p_up);
c27a02cd 1644 if (err) {
453a6082 1645 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1646 mlx4_en_deactivate_cq(priv, cq);
1647 goto tx_err;
1648 }
5b263f53 1649 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1650
1651 /* Arm CQ for TX completions */
1652 mlx4_en_arm_cq(priv, cq);
1653
c27a02cd
YP		 1654 /* Set initial ownership of all Tx TXBBs to SW (1) */
1655 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1656 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1657 ++tx_index;
1658 }
1659
1660 /* Configure port */
1661 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1662 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1663 priv->prof->tx_pause,
1664 priv->prof->tx_ppp,
1665 priv->prof->rx_pause,
1666 priv->prof->rx_ppp);
c27a02cd 1667 if (err) {
48e551ff
YB		 1668 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1669 priv->port, err);
c27a02cd
YP		 1670 goto tx_err;
1671 }
1672 /* Set default qp number */
1673 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1674 if (err) {
453a6082 1675 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1676 goto tx_err;
1677 }
c27a02cd 1678
837052d0
OG		 1679 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1680 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
1681 if (err) {
1682 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1683 err);
1684 goto tx_err;
1685 }
1686 }
1687
c27a02cd 1688 /* Init port */
453a6082 1689 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1690 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1691 if (err) {
453a6082 1692 en_err(priv, "Failed Initializing port\n");
1679200f 1693 goto tx_err;
c27a02cd
YP		 1694 }
1695
1679200f
YP		 1696 /* Attach rx QP to bradcast address */
1697 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1698 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1699 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1700 priv->port, 0, MLX4_PROT_ETH,
1701 &priv->broadcast_id))
1679200f
YP		 1702 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1703
b5845f98
HX		 1704 /* Must redo promiscuous mode setup. */
1705 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1706
c27a02cd 1707 /* Schedule multicast task to populate multicast list */
0eb74fdd 1708 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1709
93ece0c1
EE		 1710 mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
1711
c27a02cd 1712 priv->port_up = true;
a11faac7 1713 netif_tx_start_all_queues(dev);
3484aac1
AV		 1714 netif_device_attach(dev);
1715
c27a02cd
YP		 1716 return 0;
1717
c27a02cd
YP		 1718tx_err:
1719 while (tx_index--) {
41d942d5
EE		 1720 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1721 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1722 }
cabdc8ee
HHZ		 1723 mlx4_en_destroy_drop_qp(priv);
1724rss_err:
c27a02cd 1725 mlx4_en_release_rss_steer(priv);
1679200f 1726mac_err:
16a10ffd 1727 mlx4_en_put_qp(priv);
c27a02cd
YP		 1728cq_err:
1729 while (rx_index--)
41d942d5 1730 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
38aab07c 1731 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1732 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1733
1734 return err; /* need to close devices */
1735}
1736
1737
3484aac1 1738void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1739{
1740 struct mlx4_en_priv *priv = netdev_priv(dev);
1741 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1742 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1743 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1744 int i;
1679200f 1745 u8 mc_list[16] = {0};
c27a02cd
YP		 1746
1747 if (!priv->port_up) {
453a6082 1748 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1749 return;
1750 }
c27a02cd 1751
0cc5c8bf
EE		 1752 /* close port*/
1753 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1754
c27a02cd
YP		 1755 /* Synchronize with tx routine */
1756 netif_tx_lock_bh(dev);
3484aac1
AV		 1757 if (detach)
1758 netif_device_detach(dev);
3c05f5ef 1759 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1760 netif_tx_unlock_bh(dev);
1761
3484aac1
AV		 1762 netif_tx_disable(dev);
1763
7c287380 1764 /* Set port as not active */
3c05f5ef 1765 priv->port_up = false;
c27a02cd 1766
db0e7cba
AY		 1767 /* Promsicuous mode */
1768 if (mdev->dev->caps.steering_mode ==
1769 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1770 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1771 MLX4_EN_FLAG_MC_PROMISC);
1772 mlx4_flow_steer_promisc_remove(mdev->dev,
1773 priv->port,
f9162539 1774 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1775 mlx4_flow_steer_promisc_remove(mdev->dev,
1776 priv->port,
f9162539 1777 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1778 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1779 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1780
1781 /* Disable promiscouos mode */
1782 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1783 priv->port);
1784
1785 /* Disable Multicast promisc */
1786 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1787 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1788 priv->port);
1789 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1790 }
1791 }
1792
1679200f
YP		 1793 /* Detach All multicasts */
1794 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1795 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1796 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1797 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1798 list_for_each_entry(mclist, &priv->curr_list, list) {
1799 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1800 mc_list[5] = priv->port;
1801 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1802 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1803 if (mclist->tunnel_reg_id)
1804 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1805 }
1806 mlx4_en_clear_list(dev);
6d199937
YP		 1807 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1808 list_del(&mclist->list);
1809 kfree(mclist);
1810 }
1811
1679200f
YP		 1812 /* Flush multicast filter */
1813 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1814
6efb5fac
HHZ		 1815 /* Remove flow steering rules for the port*/
1816 if (mdev->dev->caps.steering_mode ==
1817 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1818 ASSERT_RTNL();
1819 list_for_each_entry_safe(flow, tmp_flow,
1820 &priv->ethtool_list, list) {
1821 mlx4_flow_detach(mdev->dev, flow->id);
1822 list_del(&flow->list);
1823 }
1824 }
1825
cabdc8ee
HHZ		 1826 mlx4_en_destroy_drop_qp(priv);
1827
c27a02cd
YP		 1828 /* Free TX Rings */
1829 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1830 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1831 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1832 }
1833 msleep(10);
1834
1835 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1836 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1837
1838 /* Free RSS qps */
1839 mlx4_en_release_rss_steer(priv);
1840
ffe455ad 1841 /* Unregister Mac address for the port */
16a10ffd 1842 mlx4_en_put_qp(priv);
5930e8d0 1843 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1844 mdev->mac_removed[priv->port] = 1;
ffe455ad 1845
c27a02cd
YP		 1846 /* Free RX Rings */
1847 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1848 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1849
1850 local_bh_disable();
1851 while (!mlx4_en_cq_lock_napi(cq)) {
1852 pr_info("CQ %d locked\n", i);
1853 mdelay(1);
1854 }
1855 local_bh_enable();
1856
9e77a2b8 1857 while (test_bit(NAPI_STATE_SCHED, &cq->napi.state))
c27a02cd 1858 msleep(1);
41d942d5 1859 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1860 mlx4_en_deactivate_cq(priv, cq);
c27a02cd
YP		 1861 }
1862}
1863
1864static void mlx4_en_restart(struct work_struct *work)
1865{
1866 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1867 watchdog_task);
1868 struct mlx4_en_dev *mdev = priv->mdev;
1869 struct net_device *dev = priv->dev;
1870
453a6082 1871 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1872
1873 mutex_lock(&mdev->state_lock);
1874 if (priv->port_up) {
3484aac1 1875 mlx4_en_stop_port(dev, 1);
1e338db5 1876 if (mlx4_en_start_port(dev))
453a6082 1877 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1878 }
1879 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1880}
1881
b477ba62 1882static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1883{
1884 struct mlx4_en_priv *priv = netdev_priv(dev);
1885 struct mlx4_en_dev *mdev = priv->mdev;
1886 int i;
c27a02cd 1887
c27a02cd 1888 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1889 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1890
1891 memset(&priv->stats, 0, sizeof(priv->stats));
1892 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1893 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1894 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
c27a02cd
YP		 1895
1896 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1897 priv->tx_ring[i]->bytes = 0;
1898 priv->tx_ring[i]->packets = 0;
1899 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1900 }
1901 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1902 priv->rx_ring[i]->bytes = 0;
1903 priv->rx_ring[i]->packets = 0;
1904 priv->rx_ring[i]->csum_ok = 0;
1905 priv->rx_ring[i]->csum_none = 0;
c27a02cd 1906 }
b477ba62
EE		 1907}
1908
1909static int mlx4_en_open(struct net_device *dev)
1910{
1911 struct mlx4_en_priv *priv = netdev_priv(dev);
1912 struct mlx4_en_dev *mdev = priv->mdev;
1913 int err = 0;
1914
1915 mutex_lock(&mdev->state_lock);
1916
1917 if (!mdev->device_up) {
1918 en_err(priv, "Cannot open - device down/disabled\n");
1919 err = -EBUSY;
1920 goto out;
1921 }
1922
1923 /* Reset HW statistics and SW counters */
1924 mlx4_en_clear_stats(dev);
c27a02cd 1925
c27a02cd
YP		 1926 err = mlx4_en_start_port(dev);
1927 if (err)
453a6082 1928 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1929
1930out:
1931 mutex_unlock(&mdev->state_lock);
1932 return err;
1933}
1934
1935
1936static int mlx4_en_close(struct net_device *dev)
1937{
1938 struct mlx4_en_priv *priv = netdev_priv(dev);
1939 struct mlx4_en_dev *mdev = priv->mdev;
1940
453a6082 1941 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1942
1943 mutex_lock(&mdev->state_lock);
1944
3484aac1 1945 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1946 netif_carrier_off(dev);
1947
1948 mutex_unlock(&mdev->state_lock);
1949 return 0;
1950}
1951
fe0af03c 1952void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1953{
1954 int i;
1955
1eb8c695
AV		 1956#ifdef CONFIG_RFS_ACCEL
1957 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1958 priv->dev->rx_cpu_rmap = NULL;
1959#endif
1960
c27a02cd 1961 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1962 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1963 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1964 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1965 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1966 }
1967
1968 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1969 if (priv->rx_ring[i])
68355f71
TLSC		 1970 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1971 priv->prof->rx_ring_size, priv->stride);
41d942d5 1972 if (priv->rx_cq[i])
fe0af03c 1973 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1974 }
044ca2a5
YP		 1975
1976 if (priv->base_tx_qpn) {
1977 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1978 priv->base_tx_qpn = 0;
1979 }
c27a02cd
YP		 1980}
1981
18cc42a3 1982int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1983{
c27a02cd
YP		 1984 struct mlx4_en_port_profile *prof = priv->prof;
1985 int i;
044ca2a5 1986 int err;
163561a4 1987 int node;
87a5c389 1988
044ca2a5 1989 err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn);
87a5c389
YP		 1990 if (err) {
1991 en_err(priv, "failed reserving range for TX rings\n");
1992 return err;
1993 }
c27a02cd
YP		 1994
1995 /* Create tx Rings */
1996 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1997 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1998 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1999 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 2000 goto err;
2001
d03a68f8
IS		 2002 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
2003 priv->base_tx_qpn + i,
2004 prof->tx_ring_size, TXBB_SIZE,
2005 node, i))
c27a02cd
YP		 2006 goto err;
2007 }
2008
2009 /* Create rx Rings */
2010 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2011 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2012 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2013 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2014 goto err;
2015
2016 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2017 prof->rx_ring_size, priv->stride,
2018 node))
c27a02cd
YP		 2019 goto err;
2020 }
2021
1eb8c695 2022#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2023 if (priv->mdev->dev->caps.comp_pool) {
2024 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2025 if (!priv->dev->rx_cpu_rmap)
2026 goto err;
2027 }
1eb8c695
AV		 2028#endif
2029
c27a02cd
YP		 2030 return 0;
2031
2032err:
453a6082 2033 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2034 for (i = 0; i < priv->rx_ring_num; i++) {
2035 if (priv->rx_ring[i])
2036 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2037 prof->rx_ring_size,
2038 priv->stride);
2039 if (priv->rx_cq[i])
2040 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2041 }
2042 for (i = 0; i < priv->tx_ring_num; i++) {
2043 if (priv->tx_ring[i])
2044 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2045 if (priv->tx_cq[i])
2046 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2047 }
c27a02cd
YP		 2048 return -ENOMEM;
2049}
2050
2051
2052void mlx4_en_destroy_netdev(struct net_device *dev)
2053{
2054 struct mlx4_en_priv *priv = netdev_priv(dev);
2055 struct mlx4_en_dev *mdev = priv->mdev;
2056
453a6082 2057 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2058
2059 /* Unregister device - this will close the port if it was up */
2060 if (priv->registered)
2061 unregister_netdev(dev);
2062
2063 if (priv->allocated)
2064 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2065
2066 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2067 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2068 /* flush any pending task for this netdev */
2069 flush_workqueue(mdev->workqueue);
2070
2071 /* Detach the netdev so tasks would not attempt to access it */
2072 mutex_lock(&mdev->state_lock);
2073 mdev->pndev[priv->port] = NULL;
2074 mutex_unlock(&mdev->state_lock);
2075
fe0af03c 2076 mlx4_en_free_resources(priv);
564c274c 2077
bc6a4744
AV		 2078 kfree(priv->tx_ring);
2079 kfree(priv->tx_cq);
2080
c27a02cd
YP		 2081 free_netdev(dev);
2082}
2083
2084static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2085{
2086 struct mlx4_en_priv *priv = netdev_priv(dev);
2087 struct mlx4_en_dev *mdev = priv->mdev;
2088 int err = 0;
2089
453a6082 2090 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2091 dev->mtu, new_mtu);
2092
2093 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2094 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2095 return -EPERM;
2096 }
2097 dev->mtu = new_mtu;
2098
2099 if (netif_running(dev)) {
2100 mutex_lock(&mdev->state_lock);
2101 if (!mdev->device_up) {
2102 /* NIC is probably restarting - let watchdog task reset
2103 * the port */
453a6082 2104 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2105 } else {
3484aac1 2106 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2107 err = mlx4_en_start_port(dev);
2108 if (err) {
453a6082 2109 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2110 priv->port);
2111 queue_work(mdev->workqueue, &priv->watchdog_task);
2112 }
2113 }
2114 mutex_unlock(&mdev->state_lock);
2115 }
2116 return 0;
2117}
2118
100dbda8 2119static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2120{
2121 struct mlx4_en_priv *priv = netdev_priv(dev);
2122 struct mlx4_en_dev *mdev = priv->mdev;
2123 struct hwtstamp_config config;
2124
2125 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2126 return -EFAULT;
2127
2128 /* reserved for future extensions */
2129 if (config.flags)
2130 return -EINVAL;
2131
2132 /* device doesn't support time stamping */
2133 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2134 return -EINVAL;
2135
2136 /* TX HW timestamp */
2137 switch (config.tx_type) {
2138 case HWTSTAMP_TX_OFF:
2139 case HWTSTAMP_TX_ON:
2140 break;
2141 default:
2142 return -ERANGE;
2143 }
2144
2145 /* RX HW timestamp */
2146 switch (config.rx_filter) {
2147 case HWTSTAMP_FILTER_NONE:
2148 break;
2149 case HWTSTAMP_FILTER_ALL:
2150 case HWTSTAMP_FILTER_SOME:
2151 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2152 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2153 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2154 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2155 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2156 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2157 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2158 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2159 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2160 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2161 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2162 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2163 config.rx_filter = HWTSTAMP_FILTER_ALL;
2164 break;
2165 default:
2166 return -ERANGE;
2167 }
2168
2169 if (mlx4_en_timestamp_config(dev, config.tx_type, config.rx_filter)) {
2170 config.tx_type = HWTSTAMP_TX_OFF;
2171 config.rx_filter = HWTSTAMP_FILTER_NONE;
2172 }
2173
2174 return copy_to_user(ifr->ifr_data, &config,
2175 sizeof(config)) ? -EFAULT : 0;
2176}
2177
100dbda8
BH		 2178static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2179{
2180 struct mlx4_en_priv *priv = netdev_priv(dev);
2181
2182 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2183 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2184}
2185
ec693d47
AV		 2186static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2187{
2188 switch (cmd) {
2189 case SIOCSHWTSTAMP:
100dbda8
BH		 2190 return mlx4_en_hwtstamp_set(dev, ifr);
2191 case SIOCGHWTSTAMP:
2192 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2193 default:
2194 return -EOPNOTSUPP;
2195 }
2196}
2197
60d6fe99
AV		 2198static int mlx4_en_set_features(struct net_device *netdev,
2199 netdev_features_t features)
2200{
2201 struct mlx4_en_priv *priv = netdev_priv(netdev);
2202
2203 if (features & NETIF_F_LOOPBACK)
2204 priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2205 else
2206 priv->ctrl_flags &=
2207 cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
2208
79aeaccd
YB		 2209 mlx4_en_update_loopback_state(netdev, features);
2210
60d6fe99
AV		 2211 return 0;
2212
2213}
2214
8f7ba3ca
RE		 2215static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2216{
2217 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2218 struct mlx4_en_dev *mdev = en_priv->mdev;
2219 u64 mac_u64 = mlx4_en_mac_to_u64(mac);
2220
2221 if (!is_valid_ether_addr(mac))
2222 return -EINVAL;
2223
2224 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2225}
2226
3f7fb021
RE		 2227static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2228{
2229 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2230 struct mlx4_en_dev *mdev = en_priv->mdev;
2231
2232 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2233}
2234
e6b6a231
RE		 2235static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2236{
2237 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2238 struct mlx4_en_dev *mdev = en_priv->mdev;
2239
2240 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2241}
2242
2cccb9e4
RE		 2243static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2244{
2245 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2246 struct mlx4_en_dev *mdev = en_priv->mdev;
2247
2248 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2249}
8f7ba3ca 2250
948e306d
RE		 2251static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2252{
2253 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2254 struct mlx4_en_dev *mdev = en_priv->mdev;
2255
2256 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2257}
84c86403
HHZ		 2258
2259#define PORT_ID_BYTE_LEN 8
2260static int mlx4_en_get_phys_port_id(struct net_device *dev,
2261 struct netdev_phys_port_id *ppid)
2262{
2263 struct mlx4_en_priv *priv = netdev_priv(dev);
2264 struct mlx4_dev *mdev = priv->mdev->dev;
2265 int i;
2266 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2267
2268 if (!phys_port_id)
2269 return -EOPNOTSUPP;
2270
2271 ppid->id_len = sizeof(phys_port_id);
2272 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2273 ppid->id[i] = phys_port_id & 0xff;
2274 phys_port_id >>= 8;
2275 }
2276 return 0;
2277}
2278
3addc568
SH		 2279static const struct net_device_ops mlx4_netdev_ops = {
2280 .ndo_open = mlx4_en_open,
2281 .ndo_stop = mlx4_en_close,
2282 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2283 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2284 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2285 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2286 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2287 .ndo_validate_addr = eth_validate_addr,
3addc568 2288 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2289 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2290 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2291 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2292 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2293#ifdef CONFIG_NET_POLL_CONTROLLER
2294 .ndo_poll_controller = mlx4_en_netpoll,
2295#endif
60d6fe99 2296 .ndo_set_features = mlx4_en_set_features,
897d7846 2297 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2298#ifdef CONFIG_RFS_ACCEL
2299 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2300#endif
e0d1095a 2301#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2302 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2303#endif
84c86403 2304 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
3addc568
SH		 2305};
2306
8f7ba3ca
RE		 2307static const struct net_device_ops mlx4_netdev_ops_master = {
2308 .ndo_open = mlx4_en_open,
2309 .ndo_stop = mlx4_en_close,
2310 .ndo_start_xmit = mlx4_en_xmit,
2311 .ndo_select_queue = mlx4_en_select_queue,
2312 .ndo_get_stats = mlx4_en_get_stats,
2313 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2314 .ndo_set_mac_address = mlx4_en_set_mac,
2315 .ndo_validate_addr = eth_validate_addr,
2316 .ndo_change_mtu = mlx4_en_change_mtu,
2317 .ndo_tx_timeout = mlx4_en_tx_timeout,
2318 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2319 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2320 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2321 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
e6b6a231 2322 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2323 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2324 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2325#ifdef CONFIG_NET_POLL_CONTROLLER
2326 .ndo_poll_controller = mlx4_en_netpoll,
2327#endif
2328 .ndo_set_features = mlx4_en_set_features,
2329 .ndo_setup_tc = mlx4_en_setup_tc,
2330#ifdef CONFIG_RFS_ACCEL
2331 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2332#endif
84c86403 2333 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
8f7ba3ca
RE		 2334};
2335
c27a02cd
YP		 2336int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2337 struct mlx4_en_port_profile *prof)
2338{
2339 struct net_device *dev;
2340 struct mlx4_en_priv *priv;
c07cb4b0 2341 int i;
c27a02cd 2342 int err;
ef96f7d4 2343 u64 mac_u64;
c27a02cd 2344
f1593d22 2345 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2346 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2347 if (dev == NULL)
c27a02cd 2348 return -ENOMEM;
c27a02cd 2349
d317966b
AV		 2350 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2351 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2352
c27a02cd 2353 SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev);
741a00be 2354 dev->dev_id = port - 1;
c27a02cd
YP		 2355
2356 /*
2357 * Initialize driver private data
2358 */
2359
2360 priv = netdev_priv(dev);
2361 memset(priv, 0, sizeof(struct mlx4_en_priv));
2362 priv->dev = dev;
2363 priv->mdev = mdev;
ebf8c9aa 2364 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2365 priv->prof = prof;
2366 priv->port = port;
2367 priv->port_up = false;
c27a02cd 2368 priv->flags = prof->flags;
60d6fe99
AV		 2369 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2370 MLX4_WQE_CTRL_SOLICITED);
d317966b 2371 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2372 priv->tx_ring_num = prof->tx_ring_num;
d317966b 2373
41d942d5 2374 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2375 GFP_KERNEL);
bc6a4744
AV		 2376 if (!priv->tx_ring) {
2377 err = -ENOMEM;
2378 goto out;
2379 }
41d942d5 2380 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2381 GFP_KERNEL);
bc6a4744
AV		 2382 if (!priv->tx_cq) {
2383 err = -ENOMEM;
2384 goto out;
2385 }
c27a02cd 2386 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2387 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
c27a02cd
YP		 2388 priv->mac_index = -1;
2389 priv->msg_enable = MLX4_EN_MSG_LEVEL;
2390 spin_lock_init(&priv->stats_lock);
0eb74fdd 2391 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
c27a02cd
YP		 2392 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2393 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2394 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
b6c39bfc 2395 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
564c274c 2396#ifdef CONFIG_MLX4_EN_DCB
540b3a39
OG		 2397 if (!mlx4_is_slave(priv->mdev->dev)) {
2398 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
2399 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2400 } else {
2401 en_info(priv, "enabling only PFC DCB ops\n");
2402 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2403 }
2404 }
564c274c 2405#endif
c27a02cd 2406
c07cb4b0
YB		 2407 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2408 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2409
c27a02cd
YP		 2410 /* Query for default mac and max mtu */
2411 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99
YB		 2412
2413 /* Set default MAC */
2414 dev->addr_len = ETH_ALEN;
2415 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2416 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2417 if (mlx4_is_slave(priv->mdev->dev)) {
2418 eth_hw_addr_random(dev);
2419 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
2420 mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
2421 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2422 } else {
2423 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2424 priv->port, dev->dev_addr);
2425 err = -EINVAL;
2426 goto out;
2427 }
c27a02cd
YP		 2428 }
2429
6bbb6d99
YB		 2430 memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
2431
c27a02cd
YP		 2432 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2433 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2434 err = mlx4_en_alloc_resources(priv);
2435 if (err)
2436 goto out;
2437
78fb2de7
AV		 2438#ifdef CONFIG_RFS_ACCEL
2439 INIT_LIST_HEAD(&priv->filters);
2440 spin_lock_init(&priv->filters_lock);
2441#endif
2442
ec693d47
AV		 2443 /* Initialize time stamping config */
2444 priv->hwtstamp_config.flags = 0;
2445 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2446 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2447
c27a02cd
YP		 2448 /* Allocate page for receive rings */
2449 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2450 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2451 if (err) {
453a6082 2452 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2453 goto out;
2454 }
2455 priv->allocated = 1;
2456
c27a02cd
YP		 2457 /*
2458 * Initialize netdev entry points
2459 */
8f7ba3ca
RE		 2460 if (mlx4_is_master(priv->mdev->dev))
2461 dev->netdev_ops = &mlx4_netdev_ops_master;
2462 else
2463 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2464 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2465 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2466 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2467
c27a02cd
YP		 2468 SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
2469
c27a02cd
YP		 2470 /*
2471 * Set driver features
2472 */
c8c64cff
MM		 2473 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2474 if (mdev->LSO_support)
2475 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2476
2477 dev->vlan_features = dev->hw_features;
2478
ad86107f 2479 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2480 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2481 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2482 NETIF_F_HW_VLAN_CTAG_FILTER;
60d6fe99 2483 dev->hw_features |= NETIF_F_LOOPBACK;
c27a02cd 2484
1eb8c695
AV		 2485 if (mdev->dev->caps.steering_mode ==
2486 MLX4_STEERING_MODE_DEVICE_MANAGED)
2487 dev->hw_features |= NETIF_F_NTUPLE;
2488
cc5387f7
YB		 2489 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2490 dev->priv_flags |= IFF_UNICAST_FLT;
2491
837052d0
OG		 2492 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2493 dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2494 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2495 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2496 dev->features |= NETIF_F_GSO_UDP_TUNNEL;
2497 }
2498
c27a02cd
YP		 2499 mdev->pndev[port] = dev;
2500
2501 netif_carrier_off(dev);
4801ae70
EE		 2502 mlx4_en_set_default_moderation(priv);
2503
c27a02cd
YP		 2504 err = register_netdev(dev);
2505 if (err) {
453a6082 2506 en_err(priv, "Netdev registration failed for port %d\n", port);
c27a02cd
YP		 2507 goto out;
2508 }
4234144f 2509 priv->registered = 1;
453a6082
YP		 2510
2511 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2512 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2513
79aeaccd
YB		 2514 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2515
90822265 2516 /* Configure port */
5c8e9046 2517 mlx4_en_calc_rx_buf(dev);
90822265 2518 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2519 priv->rx_skb_size + ETH_FCS_LEN,
2520 prof->tx_pause, prof->tx_ppp,
2521 prof->rx_pause, prof->rx_ppp);
90822265
YP		 2522 if (err) {
2523 en_err(priv, "Failed setting port general configurations "
2524 "for port %d, with error %d\n", priv->port, err);
2525 goto out;
2526 }
2527
837052d0
OG		 2528 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2529 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
2530 if (err) {
2531 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2532 err);
2533 goto out;
2534 }
2535 }
2536
90822265
YP		 2537 /* Init port */
2538 en_warn(priv, "Initializing port\n");
2539 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2540 if (err) {
2541 en_err(priv, "Failed Initializing port\n");
2542 goto out;
2543 }
c27a02cd 2544 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2545
2546 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2547 queue_delayed_work(mdev->workqueue, &priv->service_task,
2548 SERVICE_TASK_DELAY);
2549
c27a02cd
YP		 2550 return 0;
2551
2552out:
2553 mlx4_en_destroy_netdev(dev);
2554 return err;
2555}
2556
Linux kernel - Deliverables
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