[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_port.c

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */


#include <linux/if_vlan.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/cmd.h>

#include "en_port.h"
#include "mlx4_en.h"


int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_set_vlan_fltr_mbox *filter;
	int i;
	int j;
	int index = 0;
	u32 entry;
	int err = 0;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	filter = mailbox->buf;
	for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
		entry = 0;
		for (j = 0; j < 32; j++)
			if (test_bit(index++, priv->active_vlans))
				entry |= 1 << j;
		filter->entry[i] = cpu_to_be32(entry);
	}
	err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
		       MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}

int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
{
	struct mlx4_en_query_port_context *qport_context;
	struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
	struct mlx4_en_port_state *state = &priv->port_state;
	struct mlx4_cmd_mailbox *mailbox;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);
	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
			   MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
			   MLX4_CMD_WRAPPED);
	if (err)
		goto out;
	qport_context = mailbox->buf;

	/* This command is always accessed from Ethtool context
	 * already synchronized, no need in locking */
	state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
	switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
	case MLX4_EN_100M_SPEED:
		state->link_speed = SPEED_100;
		break;
	case MLX4_EN_1G_SPEED:
		state->link_speed = SPEED_1000;
		break;
	case MLX4_EN_10G_SPEED_XAUI:
	case MLX4_EN_10G_SPEED_XFI:
		state->link_speed = SPEED_10000;
		break;
	case MLX4_EN_20G_SPEED:
		state->link_speed = SPEED_20000;
		break;
	case MLX4_EN_40G_SPEED:
		state->link_speed = SPEED_40000;
		break;
	case MLX4_EN_56G_SPEED:
		state->link_speed = SPEED_56000;
		break;
	default:
		state->link_speed = -1;
		break;
	}

	state->transceiver = qport_context->transceiver;

	state->flags = 0; /* Reset and recalculate the port flags */
	state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
		MLX4_EN_PORT_ANC : 0;
	state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
		MLX4_EN_PORT_ANE : 0;

out:
	mlx4_free_cmd_mailbox(mdev->dev, mailbox);
	return err;
}

/* Each counter set is located in struct mlx4_en_stat_out_mbox
 * with a const offset between its prio components.
 * This function runs over a counter set and sum all of it's prio components.
 */
static unsigned long en_stats_adder(__be64 *start, __be64 *next, int num)
{
	__be64 *curr = start;
	unsigned long ret = 0;
	int i;
	int offset = next - start;

	for (i = 0; i < num; i++) {
		ret += be64_to_cpu(*curr);
		curr += offset;
	}

	return ret;
}

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
{
	struct mlx4_counter tmp_counter_stats;
	struct mlx4_en_stat_out_mbox *mlx4_en_stats;
	struct mlx4_en_stat_out_flow_control_mbox *flowstats;
	struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
	struct net_device_stats *stats = &priv->stats;
	struct mlx4_cmd_mailbox *mailbox;
	u64 in_mod = reset << 8 | port;
	int err;
	int i, counter_index;

	mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);
	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
			   MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
			   MLX4_CMD_WRAPPED);
	if (err)
		goto out;

	mlx4_en_stats = mailbox->buf;

	spin_lock_bh(&priv->stats_lock);

	stats->rx_packets = 0;
	stats->rx_bytes = 0;
	priv->port_stats.rx_chksum_good = 0;
	priv->port_stats.rx_chksum_none = 0;
	priv->port_stats.rx_chksum_complete = 0;
	for (i = 0; i < priv->rx_ring_num; i++) {
		stats->rx_packets += priv->rx_ring[i]->packets;
		stats->rx_bytes += priv->rx_ring[i]->bytes;
		priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok;
		priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none;
		priv->port_stats.rx_chksum_complete += priv->rx_ring[i]->csum_complete;
	}
	stats->tx_packets = 0;
	stats->tx_bytes = 0;
	priv->port_stats.tx_chksum_offload = 0;
	priv->port_stats.queue_stopped = 0;
	priv->port_stats.wake_queue = 0;
	priv->port_stats.tso_packets = 0;
	priv->port_stats.xmit_more = 0;

	for (i = 0; i < priv->tx_ring_num; i++) {
		const struct mlx4_en_tx_ring *ring = priv->tx_ring[i];

		stats->tx_packets += ring->packets;
		stats->tx_bytes += ring->bytes;
		priv->port_stats.tx_chksum_offload += ring->tx_csum;
		priv->port_stats.queue_stopped     += ring->queue_stopped;
		priv->port_stats.wake_queue        += ring->wake_queue;
		priv->port_stats.tso_packets       += ring->tso_packets;
		priv->port_stats.xmit_more         += ring->xmit_more;
	}
	if (mlx4_is_master(mdev->dev)) {
		stats->rx_packets = en_stats_adder(&mlx4_en_stats->RTOT_prio_0,
						   &mlx4_en_stats->RTOT_prio_1,
						   NUM_PRIORITIES);
		stats->tx_packets = en_stats_adder(&mlx4_en_stats->TTOT_prio_0,
						   &mlx4_en_stats->TTOT_prio_1,
						   NUM_PRIORITIES);
		stats->rx_bytes = en_stats_adder(&mlx4_en_stats->ROCT_prio_0,
						 &mlx4_en_stats->ROCT_prio_1,
						 NUM_PRIORITIES);
		stats->tx_bytes = en_stats_adder(&mlx4_en_stats->TOCT_prio_0,
						 &mlx4_en_stats->TOCT_prio_1,
						 NUM_PRIORITIES);
	}

	/* net device stats */
	stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
			   be32_to_cpu(mlx4_en_stats->RJBBR) +
			   be32_to_cpu(mlx4_en_stats->RCRC) +
			   be32_to_cpu(mlx4_en_stats->RRUNT) +
			   be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) +
			   be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) +
			   be32_to_cpu(mlx4_en_stats->RSHORT) +
			   en_stats_adder(&mlx4_en_stats->RGIANT_prio_0,
					  &mlx4_en_stats->RGIANT_prio_1,
					  NUM_PRIORITIES);
	stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0,
					  &mlx4_en_stats->TGIANT_prio_1,
					  NUM_PRIORITIES);
	stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0,
					  &mlx4_en_stats->MCAST_prio_1,
					  NUM_PRIORITIES);
	stats->collisions = 0;
	stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP);
	stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
	stats->rx_over_errors = 0;
	stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
	stats->rx_frame_errors = 0;
	stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
	stats->rx_missed_errors = 0;
	stats->tx_aborted_errors = 0;
	stats->tx_carrier_errors = 0;
	stats->tx_fifo_errors = 0;
	stats->tx_heartbeat_errors = 0;
	stats->tx_window_errors = 0;
	stats->tx_dropped = be32_to_cpu(mlx4_en_stats->TDROP);

	/* RX stats */
	priv->pkstats.rx_multicast_packets = stats->multicast;
	priv->pkstats.rx_broadcast_packets =
			en_stats_adder(&mlx4_en_stats->RBCAST_prio_0,
				       &mlx4_en_stats->RBCAST_prio_1,
				       NUM_PRIORITIES);
	priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR);
	priv->pkstats.rx_in_range_length_error =
		be64_to_cpu(mlx4_en_stats->RInRangeLengthErr);
	priv->pkstats.rx_out_range_length_error =
		be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr);

	/* Tx stats */
	priv->pkstats.tx_multicast_packets =
		en_stats_adder(&mlx4_en_stats->TMCAST_prio_0,
			       &mlx4_en_stats->TMCAST_prio_1,
			       NUM_PRIORITIES);
	priv->pkstats.tx_broadcast_packets =
		en_stats_adder(&mlx4_en_stats->TBCAST_prio_0,
			       &mlx4_en_stats->TBCAST_prio_1,
			       NUM_PRIORITIES);

	priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
	priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0);
	priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
	priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1);
	priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
	priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2);
	priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
	priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3);
	priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
	priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4);
	priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
	priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5);
	priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
	priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6);
	priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
	priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7);
	priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan);
	priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan);
	priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
	priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0);
	priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
	priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1);
	priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
	priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2);
	priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
	priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3);
	priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
	priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4);
	priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
	priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5);
	priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
	priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6);
	priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
	priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7);
	priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan);
	priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan);

	spin_unlock_bh(&priv->stats_lock);

	memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats));
	counter_index = mlx4_get_default_counter_index(mdev->dev, port);
	err = mlx4_get_counter_stats(mdev->dev, counter_index,
				     &tmp_counter_stats, reset);

	/* 0xffs indicates invalid value */
	memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES);

	if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
		memset(mailbox->buf, 0,
		       sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
		err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma,
				   in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL,
				   0, MLX4_CMD_DUMP_ETH_STATS,
				   MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
		if (err)
			goto out;
	}

	flowstats = mailbox->buf;

	spin_lock_bh(&priv->stats_lock);

	if (tmp_counter_stats.counter_mode == 0) {
		priv->pf_stats.rx_bytes   = be64_to_cpu(tmp_counter_stats.rx_bytes);
		priv->pf_stats.tx_bytes   = be64_to_cpu(tmp_counter_stats.tx_bytes);
		priv->pf_stats.rx_packets = be64_to_cpu(tmp_counter_stats.rx_frames);
		priv->pf_stats.tx_packets = be64_to_cpu(tmp_counter_stats.tx_frames);
	}

	for (i = 0; i < MLX4_NUM_PRIORITIES; i++)	{
		priv->rx_priority_flowstats[i].rx_pause =
			be64_to_cpu(flowstats[i].rx_pause);
		priv->rx_priority_flowstats[i].rx_pause_duration =
			be64_to_cpu(flowstats[i].rx_pause_duration);
		priv->rx_priority_flowstats[i].rx_pause_transition =
			be64_to_cpu(flowstats[i].rx_pause_transition);
		priv->tx_priority_flowstats[i].tx_pause =
			be64_to_cpu(flowstats[i].tx_pause);
		priv->tx_priority_flowstats[i].tx_pause_duration =
			be64_to_cpu(flowstats[i].tx_pause_duration);
		priv->tx_priority_flowstats[i].tx_pause_transition =
			be64_to_cpu(flowstats[i].tx_pause_transition);
	}

	/* if pfc is not in use, all priorities counters have the same value */
	priv->rx_flowstats.rx_pause =
		be64_to_cpu(flowstats[0].rx_pause);
	priv->rx_flowstats.rx_pause_duration =
		be64_to_cpu(flowstats[0].rx_pause_duration);
	priv->rx_flowstats.rx_pause_transition =
		be64_to_cpu(flowstats[0].rx_pause_transition);
	priv->tx_flowstats.tx_pause =
		be64_to_cpu(flowstats[0].tx_pause);
	priv->tx_flowstats.tx_pause_duration =
		be64_to_cpu(flowstats[0].tx_pause_duration);
	priv->tx_flowstats.tx_pause_transition =
		be64_to_cpu(flowstats[0].tx_pause_transition);

	spin_unlock_bh(&priv->stats_lock);

out:
	mlx4_free_cmd_mailbox(mdev->dev, mailbox);
	return err;
}
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34
	35	#include <linux/if_vlan.h>
	36
	37	#include <linux/mlx4/device.h>
	38	#include <linux/mlx4/cmd.h>
	39
	40	#include "en_port.h"
	41	#include "mlx4_en.h"
	42
	43
f1b553fb	44	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, struct mlx4_en_priv priv)
c27a02cd YP	45	{
	46	struct mlx4_cmd_mailbox *mailbox;
	47	struct mlx4_set_vlan_fltr_mbox *filter;
	48	int i;
	49	int j;
	50	int index = 0;
	51	u32 entry;
	52	int err = 0;
	53
	54	mailbox = mlx4_alloc_cmd_mailbox(dev);
	55	if (IS_ERR(mailbox))
	56	return PTR_ERR(mailbox);
	57
	58	filter = mailbox->buf;
f1b553fb JP	59	for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
	60	entry = 0;
	61	for (j = 0; j < 32; j++)
	62	if (test_bit(index++, priv->active_vlans))
	63	entry \|= 1 << j;
	64	filter->entry[i] = cpu_to_be32(entry);
c27a02cd	65	}
f1b553fb	66	err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
f9baff50	67	MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
c27a02cd YP	68	mlx4_free_cmd_mailbox(dev, mailbox);
	69	return err;
	70	}
	71
e7c1c2c4 YP	72	int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
	73	{
	74	struct mlx4_en_query_port_context *qport_context;
	75	struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
	76	struct mlx4_en_port_state *state = &priv->port_state;
	77	struct mlx4_cmd_mailbox *mailbox;
	78	int err;
	79
	80	mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
	81	if (IS_ERR(mailbox))
	82	return PTR_ERR(mailbox);
e7c1c2c4	83	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
f9baff50 JM	84	MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
f9baff50 JM	85	MLX4_CMD_WRAPPED);
e7c1c2c4 YP	86	if (err)
	87	goto out;
	88	qport_context = mailbox->buf;
	89
	90	/* This command is always accessed from Ethtool context
	91	* already synchronized, no need in locking */
	92	state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
f0ec7177	93	switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
dcf972a3 SM	94	case MLX4_EN_100M_SPEED:
	95	state->link_speed = SPEED_100;
	96	break;
f0ec7177	97	case MLX4_EN_1G_SPEED:
dcf972a3	98	state->link_speed = SPEED_1000;
f0ec7177 AG	99	break;
	100	case MLX4_EN_10G_SPEED_XAUI:
	101	case MLX4_EN_10G_SPEED_XFI:
dcf972a3 SM	102	state->link_speed = SPEED_10000;
	103	break;
	104	case MLX4_EN_20G_SPEED:
	105	state->link_speed = SPEED_20000;
f0ec7177 AG	106	break;
f0ec7177 AG	107	case MLX4_EN_40G_SPEED:
dcf972a3 SM	108	state->link_speed = SPEED_40000;
	109	break;
	110	case MLX4_EN_56G_SPEED:
	111	state->link_speed = SPEED_56000;
f0ec7177 AG	112	break;
	113	default:
	114	state->link_speed = -1;
	115	break;
	116	}
2c762679 SM	117
	118	state->transceiver = qport_context->transceiver;
	119
	120	state->flags = 0; /* Reset and recalculate the port flags */
	121	state->flags \|= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
	122	MLX4_EN_PORT_ANC : 0;
	123	state->flags \|= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
	124	MLX4_EN_PORT_ANE : 0;
e7c1c2c4 YP	125
	126	out:
	127	mlx4_free_cmd_mailbox(mdev->dev, mailbox);
	128	return err;
	129	}
c27a02cd	130
a3333b35 EBE	131	/* Each counter set is located in struct mlx4_en_stat_out_mbox
	132	* with a const offset between its prio components.
	133	* This function runs over a counter set and sum all of it's prio components.
	134	*/
	135	static unsigned long en_stats_adder(__be64 start, __be64 next, int num)
	136	{
	137	__be64 *curr = start;
	138	unsigned long ret = 0;
	139	int i;
	140	int offset = next - start;
	141
cae06338	142	for (i = 0; i < num; i++) {
a3333b35 EBE	143	ret += be64_to_cpu(*curr);
	144	curr += offset;
	145	}
	146
	147	return ret;
	148	}
	149
c27a02cd YP	150	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
c27a02cd YP	151	{
b42de4d0	152	struct mlx4_counter tmp_counter_stats;
c27a02cd	153	struct mlx4_en_stat_out_mbox *mlx4_en_stats;
0b131561	154	struct mlx4_en_stat_out_flow_control_mbox *flowstats;
c27a02cd YP	155	struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
	156	struct net_device_stats *stats = &priv->stats;
	157	struct mlx4_cmd_mailbox *mailbox;
	158	u64 in_mod = reset << 8 \| port;
	159	int err;
b42de4d0	160	int i, counter_index;
c27a02cd YP	161
	162	mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
	163	if (IS_ERR(mailbox))
	164	return PTR_ERR(mailbox);
c27a02cd	165	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
f9baff50 JM	166	MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
f9baff50 JM	167	MLX4_CMD_WRAPPED);
c27a02cd YP	168	if (err)
	169	goto out;
	170
	171	mlx4_en_stats = mailbox->buf;
	172
	173	spin_lock_bh(&priv->stats_lock);
	174
b1b243af YP	175	stats->rx_packets = 0;
b1b243af YP	176	stats->rx_bytes = 0;
ad04378c YP	177	priv->port_stats.rx_chksum_good = 0;
ad04378c YP	178	priv->port_stats.rx_chksum_none = 0;
f8c6455b	179	priv->port_stats.rx_chksum_complete = 0;
b1b243af	180	for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 EE	181	stats->rx_packets += priv->rx_ring[i]->packets;
	182	stats->rx_bytes += priv->rx_ring[i]->bytes;
	183	priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok;
	184	priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none;
f8c6455b	185	priv->port_stats.rx_chksum_complete += priv->rx_ring[i]->csum_complete;
b1b243af YP	186	}
	187	stats->tx_packets = 0;
	188	stats->tx_bytes = 0;
ad04378c	189	priv->port_stats.tx_chksum_offload = 0;
15bffdff EE	190	priv->port_stats.queue_stopped = 0;
15bffdff EE	191	priv->port_stats.wake_queue = 0;
9fab426d ED	192	priv->port_stats.tso_packets = 0;
9fab426d ED	193	priv->port_stats.xmit_more = 0;
15bffdff	194
b6055006	195	for (i = 0; i < priv->tx_ring_num; i++) {
9fab426d ED	196	const struct mlx4_en_tx_ring *ring = priv->tx_ring[i];
	197
	198	stats->tx_packets += ring->packets;
	199	stats->tx_bytes += ring->bytes;
	200	priv->port_stats.tx_chksum_offload += ring->tx_csum;
	201	priv->port_stats.queue_stopped += ring->queue_stopped;
	202	priv->port_stats.wake_queue += ring->wake_queue;
	203	priv->port_stats.tso_packets += ring->tso_packets;
	204	priv->port_stats.xmit_more += ring->xmit_more;
b1b243af	205	}
f1a3badb EBE	206	if (mlx4_is_master(mdev->dev)) {
	207	stats->rx_packets = en_stats_adder(&mlx4_en_stats->RTOT_prio_0,
	208	&mlx4_en_stats->RTOT_prio_1,
	209	NUM_PRIORITIES);
	210	stats->tx_packets = en_stats_adder(&mlx4_en_stats->TTOT_prio_0,
	211	&mlx4_en_stats->TTOT_prio_1,
	212	NUM_PRIORITIES);
	213	stats->rx_bytes = en_stats_adder(&mlx4_en_stats->ROCT_prio_0,
	214	&mlx4_en_stats->ROCT_prio_1,
	215	NUM_PRIORITIES);
	216	stats->tx_bytes = en_stats_adder(&mlx4_en_stats->TOCT_prio_0,
	217	&mlx4_en_stats->TOCT_prio_1,
	218	NUM_PRIORITIES);
	219	}
c27a02cd	220
a3333b35	221	/* net device stats */
c27a02cd	222	stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
c27a02cd YP	223	be32_to_cpu(mlx4_en_stats->RJBBR) +
c27a02cd YP	224	be32_to_cpu(mlx4_en_stats->RCRC) +
a3333b35 EBE	225	be32_to_cpu(mlx4_en_stats->RRUNT) +
	226	be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) +
	227	be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) +
	228	be32_to_cpu(mlx4_en_stats->RSHORT) +
	229	en_stats_adder(&mlx4_en_stats->RGIANT_prio_0,
	230	&mlx4_en_stats->RGIANT_prio_1,
	231	NUM_PRIORITIES);
	232	stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0,
	233	&mlx4_en_stats->TGIANT_prio_1,
	234	NUM_PRIORITIES);
	235	stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0,
	236	&mlx4_en_stats->MCAST_prio_1,
	237	NUM_PRIORITIES);
c27a02cd	238	stats->collisions = 0;
a3333b35	239	stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP);
c27a02cd	240	stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
281e8b2f	241	stats->rx_over_errors = 0;
c27a02cd YP	242	stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
	243	stats->rx_frame_errors = 0;
	244	stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
281e8b2f	245	stats->rx_missed_errors = 0;
c27a02cd YP	246	stats->tx_aborted_errors = 0;
	247	stats->tx_carrier_errors = 0;
	248	stats->tx_fifo_errors = 0;
	249	stats->tx_heartbeat_errors = 0;
	250	stats->tx_window_errors = 0;
a3333b35 EBE	251	stats->tx_dropped = be32_to_cpu(mlx4_en_stats->TDROP);
	252
	253	/* RX stats */
	254	priv->pkstats.rx_multicast_packets = stats->multicast;
	255	priv->pkstats.rx_broadcast_packets =
	256	en_stats_adder(&mlx4_en_stats->RBCAST_prio_0,
	257	&mlx4_en_stats->RBCAST_prio_1,
	258	NUM_PRIORITIES);
	259	priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR);
	260	priv->pkstats.rx_in_range_length_error =
	261	be64_to_cpu(mlx4_en_stats->RInRangeLengthErr);
	262	priv->pkstats.rx_out_range_length_error =
	263	be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr);
	264
	265	/* Tx stats */
	266	priv->pkstats.tx_multicast_packets =
	267	en_stats_adder(&mlx4_en_stats->TMCAST_prio_0,
	268	&mlx4_en_stats->TMCAST_prio_1,
	269	NUM_PRIORITIES);
	270	priv->pkstats.tx_broadcast_packets =
	271	en_stats_adder(&mlx4_en_stats->TBCAST_prio_0,
	272	&mlx4_en_stats->TBCAST_prio_1,
	273	NUM_PRIORITIES);
	274
	275	priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
	276	priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0);
	277	priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
	278	priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1);
	279	priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
	280	priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2);
	281	priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
	282	priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3);
	283	priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
	284	priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4);
	285	priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
	286	priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5);
	287	priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
	288	priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6);
	289	priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
	290	priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7);
	291	priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan);
	292	priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan);
	293	priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
	294	priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0);
	295	priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
	296	priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1);
	297	priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
	298	priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2);
	299	priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
	300	priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3);
	301	priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
	302	priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4);
	303	priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
	304	priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5);
	305	priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
	306	priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6);
	307	priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
	308	priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7);
	309	priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan);
	310	priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan);
c27a02cd	311
c27a02cd YP	312	spin_unlock_bh(&priv->stats_lock);
c27a02cd YP	313
b42de4d0 EBE	314	memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats));
	315	counter_index = mlx4_get_default_counter_index(mdev->dev, port);
	316	err = mlx4_get_counter_stats(mdev->dev, counter_index,
	317	&tmp_counter_stats, reset);
	318
0b131561 MB	319	/* 0xffs indicates invalid value */
	320	memset(mailbox->buf, 0xff, sizeof(flowstats) MLX4_NUM_PRIORITIES);
	321
	322	if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
	323	memset(mailbox->buf, 0,
	324	sizeof(flowstats) MLX4_NUM_PRIORITIES);
	325	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma,
	326	in_mod \| MLX4_DUMP_ETH_STATS_FLOW_CONTROL,
	327	0, MLX4_CMD_DUMP_ETH_STATS,
	328	MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
	329	if (err)
	330	goto out;
	331	}
	332
	333	flowstats = mailbox->buf;
	334
	335	spin_lock_bh(&priv->stats_lock);
	336
b42de4d0 EBE	337	if (tmp_counter_stats.counter_mode == 0) {
	338	priv->pf_stats.rx_bytes = be64_to_cpu(tmp_counter_stats.rx_bytes);
	339	priv->pf_stats.tx_bytes = be64_to_cpu(tmp_counter_stats.tx_bytes);
	340	priv->pf_stats.rx_packets = be64_to_cpu(tmp_counter_stats.rx_frames);
	341	priv->pf_stats.tx_packets = be64_to_cpu(tmp_counter_stats.tx_frames);
	342	}
	343
0b131561 MB	344	for (i = 0; i < MLX4_NUM_PRIORITIES; i++) {
	345	priv->rx_priority_flowstats[i].rx_pause =
	346	be64_to_cpu(flowstats[i].rx_pause);
	347	priv->rx_priority_flowstats[i].rx_pause_duration =
	348	be64_to_cpu(flowstats[i].rx_pause_duration);
	349	priv->rx_priority_flowstats[i].rx_pause_transition =
	350	be64_to_cpu(flowstats[i].rx_pause_transition);
	351	priv->tx_priority_flowstats[i].tx_pause =
	352	be64_to_cpu(flowstats[i].tx_pause);
	353	priv->tx_priority_flowstats[i].tx_pause_duration =
	354	be64_to_cpu(flowstats[i].tx_pause_duration);
	355	priv->tx_priority_flowstats[i].tx_pause_transition =
	356	be64_to_cpu(flowstats[i].tx_pause_transition);
	357	}
	358
	359	/* if pfc is not in use, all priorities counters have the same value */
	360	priv->rx_flowstats.rx_pause =
	361	be64_to_cpu(flowstats[0].rx_pause);
	362	priv->rx_flowstats.rx_pause_duration =
	363	be64_to_cpu(flowstats[0].rx_pause_duration);
	364	priv->rx_flowstats.rx_pause_transition =
	365	be64_to_cpu(flowstats[0].rx_pause_transition);
	366	priv->tx_flowstats.tx_pause =
	367	be64_to_cpu(flowstats[0].tx_pause);
	368	priv->tx_flowstats.tx_pause_duration =
	369	be64_to_cpu(flowstats[0].tx_pause_duration);
	370	priv->tx_flowstats.tx_pause_transition =
	371	be64_to_cpu(flowstats[0].tx_pause_transition);
	372
	373	spin_unlock_bh(&priv->stats_lock);
	374
c27a02cd YP	375	out:
	376	mlx4_free_cmd_mailbox(mdev->dev, mailbox);
	377	return err;
	378	}
	379