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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
6eb07caf | 44 | #include <linux/moduleparam.h> |
c27a02cd YP |
45 | |
46 | #include "mlx4_en.h" | |
47 | ||
c27a02cd | 48 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
ddae0349 | 49 | struct mlx4_en_tx_ring **pring, u32 size, |
d03a68f8 | 50 | u16 stride, int node, int queue_index) |
c27a02cd YP |
51 | { |
52 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 53 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
54 | int tmp; |
55 | int err; | |
56 | ||
163561a4 | 57 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 58 | if (!ring) { |
163561a4 EE |
59 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
60 | if (!ring) { | |
61 | en_err(priv, "Failed allocating TX ring\n"); | |
62 | return -ENOMEM; | |
63 | } | |
41d942d5 EE |
64 | } |
65 | ||
c27a02cd YP |
66 | ring->size = size; |
67 | ring->size_mask = size - 1; | |
68 | ring->stride = stride; | |
c27a02cd | 69 | |
c27a02cd | 70 | tmp = size * sizeof(struct mlx4_en_tx_info); |
dc9b06d1 | 71 | ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); |
41d942d5 | 72 | if (!ring->tx_info) { |
163561a4 EE |
73 | ring->tx_info = vmalloc(tmp); |
74 | if (!ring->tx_info) { | |
75 | err = -ENOMEM; | |
76 | goto err_ring; | |
77 | } | |
41d942d5 | 78 | } |
e404decb | 79 | |
453a6082 | 80 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
81 | ring->tx_info, tmp); |
82 | ||
163561a4 | 83 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 84 | if (!ring->bounce_buf) { |
163561a4 EE |
85 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
86 | if (!ring->bounce_buf) { | |
87 | err = -ENOMEM; | |
88 | goto err_info; | |
89 | } | |
c27a02cd YP |
90 | } |
91 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
92 | ||
163561a4 EE |
93 | /* Allocate HW buffers on provided NUMA node */ |
94 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
95 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
96 | 2 * PAGE_SIZE); | |
163561a4 | 97 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 98 | if (err) { |
453a6082 | 99 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
100 | goto err_bounce; |
101 | } | |
102 | ||
103 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
104 | if (err) { | |
453a6082 | 105 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
106 | goto err_hwq_res; |
107 | } | |
108 | ||
109 | ring->buf = ring->wqres.buf.direct.buf; | |
110 | ||
1a91de28 JP |
111 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
112 | ring, ring->buf, ring->size, ring->buf_size, | |
113 | (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 114 | |
ddae0349 EE |
115 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
116 | MLX4_RESERVE_ETH_BF_QP); | |
117 | if (err) { | |
118 | en_err(priv, "failed reserving qp for TX ring\n"); | |
119 | goto err_map; | |
120 | } | |
121 | ||
40f2287b | 122 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); |
c27a02cd | 123 | if (err) { |
453a6082 | 124 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
ddae0349 | 125 | goto err_reserve; |
c27a02cd | 126 | } |
966508f7 | 127 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 128 | |
163561a4 | 129 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 130 | if (err) { |
1a91de28 | 131 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
132 | ring->bf.uar = &mdev->priv_uar; |
133 | ring->bf.uar->map = mdev->uar_map; | |
134 | ring->bf_enabled = false; | |
0fef9d03 AV |
135 | ring->bf_alloced = false; |
136 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
137 | } else { | |
138 | ring->bf_alloced = true; | |
139 | ring->bf_enabled = !!(priv->pflags & | |
140 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
141 | } | |
87a5c389 | 142 | |
ec693d47 | 143 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
144 | ring->queue_index = queue_index; |
145 | ||
146 | if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index)) | |
147 | cpumask_set_cpu(queue_index, &ring->affinity_mask); | |
ec693d47 | 148 | |
41d942d5 | 149 | *pring = ring; |
c27a02cd YP |
150 | return 0; |
151 | ||
ddae0349 EE |
152 | err_reserve: |
153 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
c27a02cd YP |
154 | err_map: |
155 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
156 | err_hwq_res: | |
157 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
158 | err_bounce: | |
159 | kfree(ring->bounce_buf); | |
160 | ring->bounce_buf = NULL; | |
41d942d5 | 161 | err_info: |
dc9b06d1 | 162 | kvfree(ring->tx_info); |
c27a02cd | 163 | ring->tx_info = NULL; |
41d942d5 EE |
164 | err_ring: |
165 | kfree(ring); | |
166 | *pring = NULL; | |
c27a02cd YP |
167 | return err; |
168 | } | |
169 | ||
170 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 171 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
172 | { |
173 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 174 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 175 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 176 | |
0fef9d03 | 177 | if (ring->bf_alloced) |
87a5c389 | 178 | mlx4_bf_free(mdev->dev, &ring->bf); |
c27a02cd YP |
179 | mlx4_qp_remove(mdev->dev, &ring->qp); |
180 | mlx4_qp_free(mdev->dev, &ring->qp); | |
c27a02cd YP |
181 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
182 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
183 | kfree(ring->bounce_buf); | |
184 | ring->bounce_buf = NULL; | |
dc9b06d1 | 185 | kvfree(ring->tx_info); |
c27a02cd | 186 | ring->tx_info = NULL; |
41d942d5 EE |
187 | kfree(ring); |
188 | *pring = NULL; | |
c27a02cd YP |
189 | } |
190 | ||
191 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
192 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 193 | int cq, int user_prio) |
c27a02cd YP |
194 | { |
195 | struct mlx4_en_dev *mdev = priv->mdev; | |
196 | int err; | |
197 | ||
198 | ring->cqn = cq; | |
199 | ring->prod = 0; | |
200 | ring->cons = 0xffffffff; | |
201 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
202 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
203 | memset(ring->buf, 0, ring->buf_size); | |
204 | ||
205 | ring->qp_state = MLX4_QP_STATE_RST; | |
6a4e8121 ED |
206 | ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); |
207 | ring->mr_key = cpu_to_be32(mdev->mr.key); | |
c27a02cd YP |
208 | |
209 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
0e98b523 | 210 | ring->cqn, user_prio, &ring->context); |
0fef9d03 | 211 | if (ring->bf_alloced) |
87a5c389 | 212 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); |
c27a02cd YP |
213 | |
214 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
215 | &ring->qp, &ring->qp_state); | |
d03a68f8 IS |
216 | if (!user_prio && cpu_online(ring->queue_index)) |
217 | netif_set_xps_queue(priv->dev, &ring->affinity_mask, | |
218 | ring->queue_index); | |
c27a02cd YP |
219 | |
220 | return err; | |
221 | } | |
222 | ||
223 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
224 | struct mlx4_en_tx_ring *ring) | |
225 | { | |
226 | struct mlx4_en_dev *mdev = priv->mdev; | |
227 | ||
228 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
229 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
230 | } | |
231 | ||
2d4b6466 EE |
232 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
233 | struct mlx4_en_tx_ring *ring, int index, | |
234 | u8 owner) | |
235 | { | |
236 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
237 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
238 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
239 | void *end = ring->buf + ring->buf_size; | |
240 | __be32 *ptr = (__be32 *)tx_desc; | |
241 | int i; | |
242 | ||
243 | /* Optimize the common case when there are no wraparounds */ | |
244 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
245 | /* Stamp the freed descriptor */ | |
246 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
247 | i += STAMP_STRIDE) { | |
248 | *ptr = stamp; | |
249 | ptr += STAMP_DWORDS; | |
250 | } | |
251 | } else { | |
252 | /* Stamp the freed descriptor */ | |
253 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
254 | i += STAMP_STRIDE) { | |
255 | *ptr = stamp; | |
256 | ptr += STAMP_DWORDS; | |
257 | if ((void *)ptr >= end) { | |
258 | ptr = ring->buf; | |
259 | stamp ^= cpu_to_be32(0x80000000); | |
260 | } | |
261 | } | |
262 | } | |
263 | } | |
264 | ||
c27a02cd YP |
265 | |
266 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
267 | struct mlx4_en_tx_ring *ring, | |
ec693d47 | 268 | int index, u8 owner, u64 timestamp) |
c27a02cd | 269 | { |
c27a02cd YP |
270 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
271 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
272 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
c27a02cd | 273 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
274 | struct sk_buff *skb = tx_info->skb; |
275 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 276 | int i; |
ec693d47 | 277 | |
29d40c90 ED |
278 | /* We do not touch skb here, so prefetch skb->users location |
279 | * to speedup consume_skb() | |
280 | */ | |
281 | prefetchw(&skb->users); | |
282 | ||
3d03641c ED |
283 | if (unlikely(timestamp)) { |
284 | struct skb_shared_hwtstamps hwts; | |
285 | ||
286 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
287 | skb_tstamp_tx(skb, &hwts); |
288 | } | |
c27a02cd YP |
289 | |
290 | /* Optimize the common case when there are no wraparounds */ | |
291 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a | 292 | if (!tx_info->inl) { |
3d03641c | 293 | if (tx_info->linear) |
ebf8c9aa | 294 | dma_unmap_single(priv->ddev, |
3d03641c ED |
295 | tx_info->map0_dma, |
296 | tx_info->map0_byte_count, | |
297 | PCI_DMA_TODEVICE); | |
298 | else | |
299 | dma_unmap_page(priv->ddev, | |
300 | tx_info->map0_dma, | |
301 | tx_info->map0_byte_count, | |
302 | PCI_DMA_TODEVICE); | |
303 | for (i = 1; i < nr_maps; i++) { | |
304 | data++; | |
ebf8c9aa | 305 | dma_unmap_page(priv->ddev, |
3d03641c ED |
306 | (dma_addr_t)be64_to_cpu(data->addr), |
307 | be32_to_cpu(data->byte_count), | |
308 | PCI_DMA_TODEVICE); | |
41efea5a | 309 | } |
c27a02cd | 310 | } |
c27a02cd | 311 | } else { |
41efea5a YP |
312 | if (!tx_info->inl) { |
313 | if ((void *) data >= end) { | |
43d620c8 | 314 | data = ring->buf + ((void *)data - end); |
41efea5a | 315 | } |
c27a02cd | 316 | |
3d03641c | 317 | if (tx_info->linear) |
ebf8c9aa | 318 | dma_unmap_single(priv->ddev, |
3d03641c ED |
319 | tx_info->map0_dma, |
320 | tx_info->map0_byte_count, | |
321 | PCI_DMA_TODEVICE); | |
322 | else | |
323 | dma_unmap_page(priv->ddev, | |
324 | tx_info->map0_dma, | |
325 | tx_info->map0_byte_count, | |
326 | PCI_DMA_TODEVICE); | |
327 | for (i = 1; i < nr_maps; i++) { | |
328 | data++; | |
41efea5a YP |
329 | /* Check for wraparound before unmapping */ |
330 | if ((void *) data >= end) | |
43d620c8 | 331 | data = ring->buf; |
ebf8c9aa | 332 | dma_unmap_page(priv->ddev, |
3d03641c ED |
333 | (dma_addr_t)be64_to_cpu(data->addr), |
334 | be32_to_cpu(data->byte_count), | |
335 | PCI_DMA_TODEVICE); | |
41efea5a | 336 | } |
c27a02cd | 337 | } |
c27a02cd | 338 | } |
b89df95d | 339 | dev_consume_skb_any(skb); |
c27a02cd YP |
340 | return tx_info->nr_txbb; |
341 | } | |
342 | ||
343 | ||
344 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
345 | { | |
346 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
347 | int cnt = 0; | |
348 | ||
349 | /* Skip last polled descriptor */ | |
350 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 351 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
352 | ring->cons, ring->prod); |
353 | ||
354 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
355 | if (netif_msg_tx_err(priv)) | |
453a6082 | 356 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
357 | return 0; |
358 | } | |
359 | ||
360 | while (ring->cons != ring->prod) { | |
361 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
362 | ring->cons & ring->size_mask, | |
ec693d47 | 363 | !!(ring->cons & ring->size), 0); |
c27a02cd YP |
364 | ring->cons += ring->last_nr_txbb; |
365 | cnt++; | |
366 | } | |
367 | ||
41b74920 TH |
368 | netdev_tx_reset_queue(ring->tx_queue); |
369 | ||
c27a02cd | 370 | if (cnt) |
453a6082 | 371 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
372 | |
373 | return cnt; | |
374 | } | |
375 | ||
fbc6daf1 AV |
376 | static bool mlx4_en_process_tx_cq(struct net_device *dev, |
377 | struct mlx4_en_cq *cq) | |
c27a02cd YP |
378 | { |
379 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
380 | struct mlx4_cq *mcq = &cq->mcq; | |
41d942d5 | 381 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; |
f0ab34f0 | 382 | struct mlx4_cqe *cqe; |
c27a02cd | 383 | u16 index; |
2d4b6466 | 384 | u16 new_index, ring_index, stamp_index; |
c27a02cd | 385 | u32 txbbs_skipped = 0; |
2d4b6466 | 386 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
387 | u32 cons_index = mcq->cons_index; |
388 | int size = cq->size; | |
389 | u32 size_mask = ring->size_mask; | |
390 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
391 | u32 packets = 0; |
392 | u32 bytes = 0; | |
08ff3235 | 393 | int factor = priv->cqe_factor; |
ec693d47 | 394 | u64 timestamp = 0; |
0276a330 | 395 | int done = 0; |
fbc6daf1 | 396 | int budget = priv->tx_work_limit; |
fb1843ee ED |
397 | u32 last_nr_txbb; |
398 | u32 ring_cons; | |
c27a02cd YP |
399 | |
400 | if (!priv->port_up) | |
fbc6daf1 | 401 | return true; |
c27a02cd | 402 | |
53511453 ED |
403 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
404 | ||
f0ab34f0 | 405 | index = cons_index & size_mask; |
b1b6b4da | 406 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
fb1843ee ED |
407 | last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); |
408 | ring_cons = ACCESS_ONCE(ring->cons); | |
409 | ring_index = ring_cons & size_mask; | |
2d4b6466 | 410 | stamp_index = ring_index; |
f0ab34f0 YP |
411 | |
412 | /* Process all completed CQEs */ | |
413 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 414 | cons_index & size) && (done < budget)) { |
f0ab34f0 YP |
415 | /* |
416 | * make sure we read the CQE after we read the | |
417 | * ownership bit | |
418 | */ | |
419 | rmb(); | |
420 | ||
bd2f631d AV |
421 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
422 | MLX4_CQE_OPCODE_ERROR)) { | |
423 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
424 | ||
425 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
426 | cqe_err->vendor_err_syndrome, | |
427 | cqe_err->syndrome); | |
428 | } | |
429 | ||
f0ab34f0 YP |
430 | /* Skip over last polled CQE */ |
431 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
432 | ||
c27a02cd | 433 | do { |
fb1843ee ED |
434 | txbbs_skipped += last_nr_txbb; |
435 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
ec693d47 AV |
436 | if (ring->tx_info[ring_index].ts_requested) |
437 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
438 | ||
f0ab34f0 | 439 | /* free next descriptor */ |
fb1843ee | 440 | last_nr_txbb = mlx4_en_free_tx_desc( |
f0ab34f0 | 441 | priv, ring, ring_index, |
fb1843ee | 442 | !!((ring_cons + txbbs_skipped) & |
ec693d47 | 443 | ring->size), timestamp); |
2d4b6466 EE |
444 | |
445 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 446 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
447 | ring->size)); |
448 | stamp_index = ring_index; | |
449 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
450 | packets++; |
451 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 452 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
453 | |
454 | ++cons_index; | |
455 | index = cons_index & size_mask; | |
b1b6b4da | 456 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 457 | } |
c27a02cd | 458 | |
c27a02cd YP |
459 | |
460 | /* | |
461 | * To prevent CQ overflow we first update CQ consumer and only then | |
462 | * the ring consumer. | |
463 | */ | |
f0ab34f0 | 464 | mcq->cons_index = cons_index; |
c27a02cd YP |
465 | mlx4_cq_set_ci(mcq); |
466 | wmb(); | |
fb1843ee ED |
467 | |
468 | /* we want to dirty this cache line once */ | |
469 | ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; | |
470 | ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; | |
471 | ||
5b263f53 | 472 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 473 | |
c18520bd YP |
474 | /* |
475 | * Wakeup Tx queue if this stopped, and at least 1 packet | |
476 | * was completed | |
477 | */ | |
478 | if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { | |
479 | netif_tx_wake_queue(ring->tx_queue); | |
15bffdff | 480 | ring->wake_queue++; |
c27a02cd | 481 | } |
fbc6daf1 | 482 | return done < budget; |
c27a02cd YP |
483 | } |
484 | ||
485 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
486 | { | |
487 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
488 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 489 | |
477b35b4 ED |
490 | if (likely(priv->port_up)) |
491 | napi_schedule_irqoff(&cq->napi); | |
0276a330 EE |
492 | else |
493 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
494 | } |
495 | ||
0276a330 EE |
496 | /* TX CQ polling - called by NAPI */ |
497 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
498 | { | |
499 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
500 | struct net_device *dev = cq->dev; | |
501 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
fbc6daf1 | 502 | int clean_complete; |
0276a330 | 503 | |
fbc6daf1 AV |
504 | clean_complete = mlx4_en_process_tx_cq(dev, cq); |
505 | if (!clean_complete) | |
506 | return budget; | |
0276a330 | 507 | |
fbc6daf1 AV |
508 | napi_complete(napi); |
509 | mlx4_en_arm_cq(priv, cq); | |
510 | ||
511 | return 0; | |
0276a330 | 512 | } |
c27a02cd | 513 | |
c27a02cd YP |
514 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
515 | struct mlx4_en_tx_ring *ring, | |
516 | u32 index, | |
517 | unsigned int desc_size) | |
518 | { | |
519 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
520 | int i; | |
521 | ||
522 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
523 | if ((i & (TXBB_SIZE - 1)) == 0) | |
524 | wmb(); | |
525 | ||
526 | *((u32 *) (ring->buf + i)) = | |
527 | *((u32 *) (ring->bounce_buf + copy + i)); | |
528 | } | |
529 | ||
530 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
531 | if ((i & (TXBB_SIZE - 1)) == 0) | |
532 | wmb(); | |
533 | ||
534 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
535 | *((u32 *) (ring->bounce_buf + i)); | |
536 | } | |
537 | ||
538 | /* Return real descriptor location */ | |
539 | return ring->buf + index * TXBB_SIZE; | |
540 | } | |
541 | ||
acea73d6 ED |
542 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
543 | * | |
544 | * It seems strange we do not simply use skb_copy_bits(). | |
545 | * This would allow to inline all skbs iff skb->len <= inline_thold | |
546 | * | |
547 | * Note that caller already checked skb was not a gso packet | |
548 | */ | |
7dfa4b41 | 549 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
b9d8839a | 550 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 551 | void **pfrag) |
c27a02cd YP |
552 | { |
553 | void *ptr; | |
554 | ||
acea73d6 ED |
555 | if (skb->len > inline_thold || !inline_thold) |
556 | return false; | |
c27a02cd | 557 | |
acea73d6 ED |
558 | if (shinfo->nr_frags == 1) { |
559 | ptr = skb_frag_address_safe(&shinfo->frags[0]); | |
560 | if (unlikely(!ptr)) | |
561 | return false; | |
562 | *pfrag = ptr; | |
563 | return true; | |
c27a02cd | 564 | } |
acea73d6 ED |
565 | if (shinfo->nr_frags) |
566 | return false; | |
567 | return true; | |
c27a02cd YP |
568 | } |
569 | ||
7dfa4b41 | 570 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
571 | { |
572 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
573 | <= MLX4_INLINE_ALIGN) | |
574 | return ALIGN(skb->len + CTRL_SIZE + | |
575 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
576 | else | |
577 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
578 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
579 | } | |
580 | ||
7dfa4b41 | 581 | static int get_real_size(const struct sk_buff *skb, |
b9d8839a | 582 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 583 | struct net_device *dev, |
acea73d6 ED |
584 | int *lso_header_size, |
585 | bool *inline_ok, | |
586 | void **pfrag) | |
c27a02cd YP |
587 | { |
588 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
589 | int real_size; |
590 | ||
b9d8839a | 591 | if (shinfo->gso_size) { |
acea73d6 | 592 | *inline_ok = false; |
837052d0 OG |
593 | if (skb->encapsulation) |
594 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
595 | else | |
596 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
b9d8839a | 597 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
c27a02cd YP |
598 | ALIGN(*lso_header_size + 4, DS_SIZE); |
599 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
600 | /* We add a segment for the skb linear buffer only if | |
601 | * it contains data */ | |
602 | if (*lso_header_size < skb_headlen(skb)) | |
603 | real_size += DS_SIZE; | |
604 | else { | |
605 | if (netif_msg_tx_err(priv)) | |
453a6082 | 606 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
607 | return 0; |
608 | } | |
609 | } | |
c27a02cd YP |
610 | } else { |
611 | *lso_header_size = 0; | |
acea73d6 ED |
612 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
613 | shinfo, pfrag); | |
614 | ||
615 | if (*inline_ok) | |
c27a02cd | 616 | real_size = inline_size(skb); |
acea73d6 ED |
617 | else |
618 | real_size = CTRL_SIZE + | |
619 | (shinfo->nr_frags + 1) * DS_SIZE; | |
c27a02cd YP |
620 | } |
621 | ||
622 | return real_size; | |
623 | } | |
624 | ||
7dfa4b41 ED |
625 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
626 | const struct sk_buff *skb, | |
b9d8839a | 627 | const struct skb_shared_info *shinfo, |
7dfa4b41 ED |
628 | int real_size, u16 *vlan_tag, |
629 | int tx_ind, void *fragptr) | |
c27a02cd YP |
630 | { |
631 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
632 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
e533ac7e | 633 | unsigned int hlen = skb_headlen(skb); |
c27a02cd YP |
634 | |
635 | if (skb->len <= spc) { | |
93591aaa EE |
636 | if (likely(skb->len >= MIN_PKT_LEN)) { |
637 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
638 | } else { | |
639 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
640 | memset(((void *)(inl + 1)) + skb->len, 0, | |
641 | MIN_PKT_LEN - skb->len); | |
642 | } | |
e533ac7e | 643 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
b9d8839a | 644 | if (shinfo->nr_frags) |
e533ac7e | 645 | memcpy(((void *)(inl + 1)) + hlen, fragptr, |
b9d8839a | 646 | skb_frag_size(&shinfo->frags[0])); |
c27a02cd YP |
647 | |
648 | } else { | |
649 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
e533ac7e ED |
650 | if (hlen <= spc) { |
651 | skb_copy_from_linear_data(skb, inl + 1, hlen); | |
652 | if (hlen < spc) { | |
653 | memcpy(((void *)(inl + 1)) + hlen, | |
654 | fragptr, spc - hlen); | |
655 | fragptr += spc - hlen; | |
c27a02cd YP |
656 | } |
657 | inl = (void *) (inl + 1) + spc; | |
658 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
659 | } else { | |
660 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
661 | inl = (void *) (inl + 1) + spc; | |
662 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
e533ac7e | 663 | hlen - spc); |
b9d8839a | 664 | if (shinfo->nr_frags) |
e533ac7e | 665 | memcpy(((void *)(inl + 1)) + hlen - spc, |
b9d8839a ED |
666 | fragptr, |
667 | skb_frag_size(&shinfo->frags[0])); | |
c27a02cd YP |
668 | } |
669 | ||
670 | wmb(); | |
671 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
672 | } | |
c27a02cd YP |
673 | } |
674 | ||
f663dd9a | 675 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 676 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 677 | { |
bc6a4744 | 678 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 679 | u16 rings_p_up = priv->num_tx_rings_p_up; |
bc6a4744 | 680 | u8 up = 0; |
c27a02cd | 681 | |
bc6a4744 AV |
682 | if (dev->num_tc) |
683 | return skb_tx_hash(dev, skb); | |
684 | ||
685 | if (vlan_tx_tag_present(skb)) | |
686 | up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; | |
f813cad8 | 687 | |
99932d4f | 688 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
c27a02cd YP |
689 | } |
690 | ||
7dfa4b41 ED |
691 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
692 | unsigned int bytecnt) | |
87a5c389 YP |
693 | { |
694 | __iowrite64_copy(dst, src, bytecnt / 8); | |
695 | } | |
696 | ||
61357325 | 697 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd | 698 | { |
b9d8839a | 699 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
c27a02cd | 700 | struct mlx4_en_priv *priv = netdev_priv(dev); |
237a3a3b | 701 | struct device *ddev = priv->ddev; |
c27a02cd | 702 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
703 | struct mlx4_en_tx_desc *tx_desc; |
704 | struct mlx4_wqe_data_seg *data; | |
c27a02cd YP |
705 | struct mlx4_en_tx_info *tx_info; |
706 | int tx_ind = 0; | |
707 | int nr_txbb; | |
708 | int desc_size; | |
709 | int real_size; | |
87a5c389 | 710 | u32 index, bf_index; |
c27a02cd | 711 | __be32 op_own; |
f813cad8 | 712 | u16 vlan_tag = 0; |
b9d8839a | 713 | int i_frag; |
c27a02cd | 714 | int lso_header_size; |
acea73d6 | 715 | void *fragptr = NULL; |
87a5c389 | 716 | bool bounce = false; |
5804283d | 717 | bool send_doorbell; |
fe971b95 | 718 | bool stop_queue; |
acea73d6 | 719 | bool inline_ok; |
f905c79e | 720 | u32 ring_cons; |
c27a02cd | 721 | |
3005ad40 YP |
722 | if (!priv->port_up) |
723 | goto tx_drop; | |
724 | ||
f905c79e ED |
725 | tx_ind = skb_get_queue_mapping(skb); |
726 | ring = priv->tx_ring[tx_ind]; | |
727 | ||
728 | /* fetch ring->cons far ahead before needing it to avoid stall */ | |
729 | ring_cons = ACCESS_ONCE(ring->cons); | |
730 | ||
acea73d6 ED |
731 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
732 | &inline_ok, &fragptr); | |
c27a02cd | 733 | if (unlikely(!real_size)) |
7e230913 | 734 | goto tx_drop; |
c27a02cd | 735 | |
25985edc | 736 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
737 | desc_size = ALIGN(real_size, TXBB_SIZE); |
738 | nr_txbb = desc_size / TXBB_SIZE; | |
739 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
740 | if (netif_msg_tx_err(priv)) | |
453a6082 | 741 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 742 | goto tx_drop; |
c27a02cd YP |
743 | } |
744 | ||
eab6d18d | 745 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 746 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd | 747 | |
c27a02cd | 748 | |
53511453 | 749 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
29d40c90 | 750 | |
c27a02cd YP |
751 | /* Track current inflight packets for performance analysis */ |
752 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
f905c79e | 753 | (u32)(ring->prod - ring_cons - 1)); |
c27a02cd YP |
754 | |
755 | /* Packet is good - grab an index and transmit it */ | |
756 | index = ring->prod & ring->size_mask; | |
87a5c389 | 757 | bf_index = ring->prod; |
c27a02cd YP |
758 | |
759 | /* See if we have enough space for whole descriptor TXBB for setting | |
760 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
761 | if (likely(index + nr_txbb <= ring->size)) | |
762 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 763 | else { |
c27a02cd | 764 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
765 | bounce = true; |
766 | } | |
c27a02cd YP |
767 | |
768 | /* Save skb in tx_info ring */ | |
769 | tx_info = &ring->tx_info[index]; | |
770 | tx_info->skb = skb; | |
771 | tx_info->nr_txbb = nr_txbb; | |
772 | ||
7dfa4b41 | 773 | data = &tx_desc->data; |
237a3a3b AV |
774 | if (lso_header_size) |
775 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, | |
776 | DS_SIZE)); | |
237a3a3b AV |
777 | |
778 | /* valid only for none inline segments */ | |
779 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
780 | ||
acea73d6 ED |
781 | tx_info->inl = inline_ok; |
782 | ||
237a3a3b | 783 | tx_info->linear = (lso_header_size < skb_headlen(skb) && |
acea73d6 | 784 | !inline_ok) ? 1 : 0; |
237a3a3b | 785 | |
b9d8839a | 786 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
3d03641c | 787 | data += tx_info->nr_maps - 1; |
237a3a3b | 788 | |
acea73d6 | 789 | if (!tx_info->inl) { |
3d03641c ED |
790 | dma_addr_t dma = 0; |
791 | u32 byte_count = 0; | |
792 | ||
7dfa4b41 | 793 | /* Map fragments if any */ |
b9d8839a | 794 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { |
7dfa4b41 | 795 | const struct skb_frag_struct *frag; |
b9d8839a ED |
796 | |
797 | frag = &shinfo->frags[i_frag]; | |
3d03641c | 798 | byte_count = skb_frag_size(frag); |
237a3a3b | 799 | dma = skb_frag_dma_map(ddev, frag, |
3d03641c | 800 | 0, byte_count, |
237a3a3b AV |
801 | DMA_TO_DEVICE); |
802 | if (dma_mapping_error(ddev, dma)) | |
803 | goto tx_drop_unmap; | |
804 | ||
805 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 806 | data->lkey = ring->mr_key; |
237a3a3b | 807 | wmb(); |
3d03641c | 808 | data->byte_count = cpu_to_be32(byte_count); |
237a3a3b AV |
809 | --data; |
810 | } | |
811 | ||
7dfa4b41 | 812 | /* Map linear part if needed */ |
237a3a3b | 813 | if (tx_info->linear) { |
3d03641c | 814 | byte_count = skb_headlen(skb) - lso_header_size; |
5f1cd200 | 815 | |
237a3a3b AV |
816 | dma = dma_map_single(ddev, skb->data + |
817 | lso_header_size, byte_count, | |
818 | PCI_DMA_TODEVICE); | |
819 | if (dma_mapping_error(ddev, dma)) | |
820 | goto tx_drop_unmap; | |
821 | ||
822 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 823 | data->lkey = ring->mr_key; |
237a3a3b AV |
824 | wmb(); |
825 | data->byte_count = cpu_to_be32(byte_count); | |
826 | } | |
3d03641c ED |
827 | /* tx completion can avoid cache line miss for common cases */ |
828 | tx_info->map0_dma = dma; | |
829 | tx_info->map0_byte_count = byte_count; | |
237a3a3b AV |
830 | } |
831 | ||
ec693d47 AV |
832 | /* |
833 | * For timestamping add flag to skb_shinfo and | |
834 | * set flag for further reference | |
835 | */ | |
e70602a8 | 836 | tx_info->ts_requested = 0; |
7dfa4b41 ED |
837 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
838 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
839 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
840 | tx_info->ts_requested = 1; |
841 | } | |
842 | ||
c27a02cd YP |
843 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
844 | * whether LSO is used */ | |
60d6fe99 | 845 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd | 846 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
a4f2dacb OG |
847 | if (!skb->encapsulation) |
848 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
849 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
850 | else | |
851 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); | |
ad04378c | 852 | ring->tx_csum++; |
c27a02cd YP |
853 | } |
854 | ||
79aeaccd | 855 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
856 | struct ethhdr *ethh; |
857 | ||
213815a1 YB |
858 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
859 | * so that VFs and PF can communicate with each other | |
860 | */ | |
861 | ethh = (struct ethhdr *)skb->data; | |
862 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
863 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
864 | } | |
865 | ||
c27a02cd YP |
866 | /* Handle LSO (TSO) packets */ |
867 | if (lso_header_size) { | |
b9d8839a ED |
868 | int i; |
869 | ||
c27a02cd YP |
870 | /* Mark opcode as LSO */ |
871 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
872 | ((ring->prod & ring->size) ? | |
873 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
874 | ||
875 | /* Fill in the LSO prefix */ | |
876 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
b9d8839a | 877 | shinfo->gso_size << 16 | lso_header_size); |
c27a02cd YP |
878 | |
879 | /* Copy headers; | |
880 | * note that we already verified that it is linear */ | |
881 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd | 882 | |
9fab426d | 883 | ring->tso_packets++; |
b9d8839a ED |
884 | |
885 | i = ((skb->len - lso_header_size) / shinfo->gso_size) + | |
886 | !!((skb->len - lso_header_size) % shinfo->gso_size); | |
5b263f53 | 887 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
888 | ring->packets += i; |
889 | } else { | |
890 | /* Normal (Non LSO) packet */ | |
891 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
892 | ((ring->prod & ring->size) ? | |
893 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 894 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 895 | ring->packets++; |
c27a02cd | 896 | } |
5b263f53 YP |
897 | ring->bytes += tx_info->nr_bytes; |
898 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
899 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
900 | ||
acea73d6 | 901 | if (tx_info->inl) |
b9d8839a ED |
902 | build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag, |
903 | tx_ind, fragptr); | |
c27a02cd | 904 | |
837052d0 OG |
905 | if (skb->encapsulation) { |
906 | struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); | |
907 | if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) | |
908 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); | |
909 | else | |
910 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
911 | } | |
912 | ||
c27a02cd YP |
913 | ring->prod += nr_txbb; |
914 | ||
915 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 916 | if (unlikely(bounce)) |
c27a02cd YP |
917 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
918 | ||
eb0cabbd AV |
919 | skb_tx_timestamp(skb); |
920 | ||
fe971b95 ED |
921 | /* Check available TXBBs And 2K spare for prefetch */ |
922 | stop_queue = (int)(ring->prod - ring_cons) > | |
923 | ring->size - HEADROOM - MAX_DESC_TXBBS; | |
924 | if (unlikely(stop_queue)) { | |
925 | netif_tx_stop_queue(ring->tx_queue); | |
926 | ring->queue_stopped++; | |
927 | } | |
5804283d ED |
928 | send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); |
929 | ||
6a4e8121 ED |
930 | real_size = (real_size / 16) & 0x3f; |
931 | ||
5804283d ED |
932 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && |
933 | !vlan_tx_tag_present(skb) && send_doorbell) { | |
6a4e8121 ED |
934 | tx_desc->ctrl.bf_qpn = ring->doorbell_qpn | |
935 | cpu_to_be32(real_size); | |
ec570940 | 936 | |
87a5c389 | 937 | op_own |= htonl((bf_index & 0xffff) << 8); |
5804283d ED |
938 | /* Ensure new descriptor hits memory |
939 | * before setting ownership of this descriptor to HW | |
940 | */ | |
87a5c389 YP |
941 | wmb(); |
942 | tx_desc->ctrl.owner_opcode = op_own; | |
c27a02cd | 943 | |
87a5c389 YP |
944 | wmb(); |
945 | ||
7dfa4b41 ED |
946 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, |
947 | desc_size); | |
87a5c389 YP |
948 | |
949 | wmb(); | |
950 | ||
951 | ring->bf.offset ^= ring->bf.buf_size; | |
952 | } else { | |
7dfa4b41 ED |
953 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); |
954 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * | |
955 | !!vlan_tx_tag_present(skb); | |
956 | tx_desc->ctrl.fence_size = real_size; | |
957 | ||
5804283d ED |
958 | /* Ensure new descriptor hits memory |
959 | * before setting ownership of this descriptor to HW | |
960 | */ | |
87a5c389 YP |
961 | wmb(); |
962 | tx_desc->ctrl.owner_opcode = op_own; | |
5804283d ED |
963 | if (send_doorbell) { |
964 | wmb(); | |
492f5add AV |
965 | /* Since there is no iowrite*_native() that writes the |
966 | * value as is, without byteswapping - using the one | |
967 | * the doesn't do byteswapping in the relevant arch | |
968 | * endianness. | |
969 | */ | |
970 | #if defined(__LITTLE_ENDIAN) | |
971 | iowrite32( | |
972 | #else | |
973 | iowrite32be( | |
974 | #endif | |
975 | ring->doorbell_qpn, | |
6a4e8121 | 976 | ring->bf.uar->map + MLX4_SEND_DOORBELL); |
9fab426d ED |
977 | } else { |
978 | ring->xmit_more++; | |
5804283d | 979 | } |
87a5c389 | 980 | } |
c27a02cd | 981 | |
fe971b95 ED |
982 | if (unlikely(stop_queue)) { |
983 | /* If queue was emptied after the if (stop_queue) , and before | |
984 | * the netif_tx_stop_queue() - need to wake the queue, | |
985 | * or else it will remain stopped forever. | |
986 | * Need a memory barrier to make sure ring->cons was not | |
987 | * updated before queue was stopped. | |
988 | */ | |
989 | smp_rmb(); | |
990 | ||
991 | ring_cons = ACCESS_ONCE(ring->cons); | |
992 | if (unlikely(((int)(ring->prod - ring_cons)) <= | |
993 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
994 | netif_tx_wake_queue(ring->tx_queue); | |
995 | ring->wake_queue++; | |
996 | } | |
997 | } | |
ec634fe3 | 998 | return NETDEV_TX_OK; |
7e230913 | 999 | |
237a3a3b AV |
1000 | tx_drop_unmap: |
1001 | en_err(priv, "DMA mapping error\n"); | |
1002 | ||
b9d8839a ED |
1003 | while (++i_frag < shinfo->nr_frags) { |
1004 | ++data; | |
237a3a3b AV |
1005 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), |
1006 | be32_to_cpu(data->byte_count), | |
1007 | PCI_DMA_TODEVICE); | |
1008 | } | |
1009 | ||
7e230913 YP |
1010 | tx_drop: |
1011 | dev_kfree_skb_any(skb); | |
1012 | priv->stats.tx_dropped++; | |
1013 | return NETDEV_TX_OK; | |
c27a02cd YP |
1014 | } |
1015 |