projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx4: Add diagnostic counters capability bit
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
38438f7c 52static bool enable_qos = true;
51f5f0ee 53module_param(enable_qos, bool, 0444);
38438f7c 54MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)");
51f5f0ee 55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
17d5ceb6 59 u64 val; \
225c7b1f
RD		 60 switch (sizeof (dest)) { \
61 case 1: (dest) = *(u8 *) __p; break; \
62 case 2: (dest) = be16_to_cpup(__p); break; \
63 case 4: (dest) = be32_to_cpup(__p); break; \
17d5ceb6
DA		 64 case 8: val = get_unaligned((u64 *)__p); \
65 (dest) = be64_to_cpu(val); break; \
225c7b1f
RD		 66 default: __buggy_use_of_MLX4_GET(); \
67 } \
68 } while (0)
69
70#define MLX4_PUT(dest, source, offset) \
71 do { \
72 void *__d = ((char *) (dest) + (offset)); \
73 switch (sizeof(source)) { \
74 case 1: *(u8 *) __d = (source); break; \
75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
78 default: __buggy_use_of_MLX4_PUT(); \
79 } \
80 } while (0)
81
52eafc68 82static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 83{
84 static const char *fname[] = {
85 [ 0] = "RC transport",
86 [ 1] = "UC transport",
87 [ 2] = "UD transport",
ea98054f 88 [ 3] = "XRC transport",
225c7b1f
RD		 89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
4d531aa8 93 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 94 [15] = "Big LSO headers",
225c7b1f
RD		 95 [16] = "MW support",
96 [17] = "APM support",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
ccf86321
OG		 101 [30] = "IBoE support",
102 [32] = "Unicast loopback support",
f3a9d1f2 103 [34] = "FCS header control",
cb2147a9
OG		 104 [37] = "Wake On LAN (port1) support",
105 [38] = "Wake On LAN (port2) support",
ccf86321
OG		 106 [40] = "UDP RSS support",
107 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 108 [42] = "Multicast VEP steering support",
109 [48] = "Counters support",
802f42a8 110 [52] = "RSS IP fragments support",
540b3a39 111 [53] = "Port ETS Scheduler support",
4d531aa8 112 [55] = "Port link type sensing support",
00f5ce99 113 [59] = "Port management change event support",
08ff3235
OG		 114 [61] = "64 byte EQE support",
115 [62] = "64 byte CQE support",
225c7b1f
RD		 116 };
117 int i;
118
119 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 120 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 121 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 122 mlx4_dbg(dev, " %s\n", fname[i]);
123}
124
b3416f44
SP		 125static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
126{
127 static const char * const fname[] = {
128 [0] = "RSS support",
129 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 130 [2] = "RSS XOR Hash Function support",
56cb4567 131 [3] = "Device managed flow steering support",
d998735f 132 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 133 [5] = "Time stamping support",
134 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 135 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 136 [8] = "Dynamic QP updates support",
56cb4567 137 [9] = "Device managed flow steering IPoIB support",
114840c3 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 139 [11] = "MAD DEMUX (Secure-Host) support",
140 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 141 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 142 [14] = "Ethernet protocol control support",
d475c95b 143 [15] = "Ethernet Backplane autoneg support",
7ae0e400 144 [16] = "CONFIG DEV support",
de966c59 145 [17] = "Asymmetric EQs support",
7d077cd3 146 [18] = "More than 80 VFs support",
be6a6b43 147 [19] = "Performance optimized for limited rule configuration flow steering support",
59e14e32 148 [20] = "Recoverable error events support",
d237baa1 149 [21] = "Port Remap support",
fc31e256 150 [22] = "QCN support",
0b131561 151 [23] = "QP rate limiting support",
d019fcb2
IS		 152 [24] = "Ethernet Flow control statistics support",
153 [25] = "Granular QoS per VF support",
3742cc65 154 [26] = "Port ETS Scheduler support",
51af33cf 155 [27] = "Port beacon support",
78500b8c 156 [28] = "RX-ALL support",
77fc29c4 157 [29] = "802.1ad offload support",
9a892835
MG		 158 [31] = "Modifying loopback source checks using UPDATE_QP support",
159 [32] = "Loopback source checks support",
0e451e88
MV		 160 [33] = "RoCEv2 support",
161 [34] = "DMFS Sniffer support (UC & MC)"
b3416f44
SP		 162 };
163 int i;
164
165 for (i = 0; i < ARRAY_SIZE(fname); ++i)
166 if (fname[i] && (flags & (1LL << i)))
167 mlx4_dbg(dev, " %s\n", fname[i]);
168}
169
2d928651
VS		 170int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
171{
172 struct mlx4_cmd_mailbox *mailbox;
173 u32 *inbox;
174 int err = 0;
175
176#define MOD_STAT_CFG_IN_SIZE 0x100
177
178#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
179#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
180
181 mailbox = mlx4_alloc_cmd_mailbox(dev);
182 if (IS_ERR(mailbox))
183 return PTR_ERR(mailbox);
184 inbox = mailbox->buf;
185
2d928651
VS		 186 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
187 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
188
189 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 190 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 191
192 mlx4_free_cmd_mailbox(dev, mailbox);
193 return err;
194}
195
e8c4265b
MB		 196int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
197{
198 struct mlx4_cmd_mailbox *mailbox;
199 u32 *outbox;
200 u8 in_modifier;
201 u8 field;
202 u16 field16;
203 int err;
204
205#define QUERY_FUNC_BUS_OFFSET 0x00
206#define QUERY_FUNC_DEVICE_OFFSET 0x01
207#define QUERY_FUNC_FUNCTION_OFFSET 0x01
208#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
209#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
210#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
211#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
212
213 mailbox = mlx4_alloc_cmd_mailbox(dev);
214 if (IS_ERR(mailbox))
215 return PTR_ERR(mailbox);
216 outbox = mailbox->buf;
217
218 in_modifier = slave;
e8c4265b
MB		 219
220 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
221 MLX4_CMD_QUERY_FUNC,
222 MLX4_CMD_TIME_CLASS_A,
223 MLX4_CMD_NATIVE);
224 if (err)
225 goto out;
226
227 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
228 func->bus = field & 0xf;
229 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
230 func->device = field & 0xf1;
231 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
232 func->function = field & 0x7;
233 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
234 func->physical_function = field & 0xf;
235 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
236 func->rsvd_eqs = field16 & 0xffff;
237 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
238 func->max_eq = field16 & 0xffff;
239 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
240 func->rsvd_uars = field & 0x0f;
241
242 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
243 func->bus, func->device, func->function, func->physical_function,
244 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
245
246out:
247 mlx4_free_cmd_mailbox(dev, mailbox);
248 return err;
249}
250
5cc914f1
MA		 251int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
252 struct mlx4_vhcr *vhcr,
253 struct mlx4_cmd_mailbox *inbox,
254 struct mlx4_cmd_mailbox *outbox,
255 struct mlx4_cmd_info *cmd)
256{
5a0d0a61 257 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 258 u8 field, port;
259 u32 size, proxy_qp, qkey;
5cc914f1 260 int err = 0;
7ae0e400 261 struct mlx4_func func;
5cc914f1
MA		 262
263#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
264#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 265#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 266#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 267#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
268#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
269#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
270#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
271#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
272#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 273#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 274#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
f0ce0615 275#define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
5cc914f1 276
eb456a68
JM		 277#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
278#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
279#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
280#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
281#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
282#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
283
ddae0349
EE		 284#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
285
105c320f
JM		 286#define QUERY_FUNC_CAP_FMR_FLAG 0x80
287#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
288#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 289#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
f0ce0615 290#define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
ddae0349
EE		 291#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
292
293#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
d57febe1 294#define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
105c320f
JM		 295
296/* when opcode modifier = 1 */
5cc914f1 297#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 298#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 299#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
300#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 301
47605df9
JM		 302#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
303#define QUERY_FUNC_CAP_QP0_PROXY 0x14
304#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
305#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 306#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 307
73e74ab4
HHZ		 308#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
309#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 310#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 311#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 312
73e74ab4 313#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 314#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
77fc29c4 315#define QUERY_FUNC_CAP_PHV_BIT 0x40
105c320f 316
5cc914f1 317 if (vhcr->op_modifier == 1) {
449fc488
MB		 318 struct mlx4_active_ports actv_ports =
319 mlx4_get_active_ports(dev, slave);
320 int converted_port = mlx4_slave_convert_port(
321 dev, slave, vhcr->in_modifier);
322
323 if (converted_port < 0)
324 return -EINVAL;
325
326 vhcr->in_modifier = converted_port;
449fc488
MB		 327 /* phys-port = logical-port */
328 field = vhcr->in_modifier -
329 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 330 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
331
99ec41d0
JM		 332 port = vhcr->in_modifier;
333 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
334
335 /* Set nic_info bit to mark new fields support */
336 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
337
338 if (mlx4_vf_smi_enabled(dev, slave, port) &&
339 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
340 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
341 MLX4_PUT(outbox->buf, qkey,
342 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
343 }
344 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
345
47605df9 346 /* size is now the QP number */
99ec41d0 347 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 348 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
349
350 size += 2;
351 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
352
99ec41d0
JM		 353 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
354 proxy_qp += 2;
355 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 356
8e1a28e8
HHZ		 357 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
358 QUERY_FUNC_CAP_PHYS_PORT_ID);
359
77fc29c4
HHZ		 360 if (dev->caps.phv_bit[port]) {
361 field = QUERY_FUNC_CAP_PHV_BIT;
362 MLX4_PUT(outbox->buf, field,
363 QUERY_FUNC_CAP_FLAGS0_OFFSET);
364 }
365
5cc914f1 366 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 367 struct mlx4_active_ports actv_ports =
368 mlx4_get_active_ports(dev, slave);
f0ce0615
JM		 369 /* enable rdma and ethernet interfaces, new quota locations,
370 * and reserved lkey
371 */
eb456a68 372 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
f0ce0615
JM		 373 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX |
374 QUERY_FUNC_CAP_FLAG_RESD_LKEY);
5cc914f1
MA		 375 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
376
449fc488
MB		 377 field = min(
378 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
379 dev->caps.num_ports);
5cc914f1
MA		 380 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
381
08ff3235 382 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 383 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
384
105c320f
JM		 385 field = 0; /* protected FMR support not available as yet */
386 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
387
5a0d0a61 388 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 390 size = dev->caps.num_qps;
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 392
5a0d0a61 393 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 394 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 395 size = dev->caps.num_srqs;
396 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 397
5a0d0a61 398 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 400 size = dev->caps.num_cqs;
401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 402
7ae0e400
MB		 403 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
404 mlx4_QUERY_FUNC(dev, &func, slave)) {
405 size = vhcr->in_modifier &
406 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
407 dev->caps.num_eqs :
408 rounddown_pow_of_two(dev->caps.num_eqs);
409 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
410 size = dev->caps.reserved_eqs;
411 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
412 } else {
413 size = vhcr->in_modifier &
414 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
415 func.max_eq :
416 rounddown_pow_of_two(func.max_eq);
417 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
418 size = func.rsvd_eqs;
419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
420 }
5cc914f1 421
5a0d0a61 422 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 423 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 424 size = dev->caps.num_mpts;
425 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 426
5a0d0a61 427 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 428 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 429 size = dev->caps.num_mtts;
430 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 431
432 size = dev->caps.num_mgms + dev->caps.num_amgms;
433 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 434 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1 435
d57febe1
MB		 436 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
437 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
ddae0349 438 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
f0ce0615
JM		 439
440 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00);
441 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
5cc914f1
MA		 442 } else
443 err = -EINVAL;
444
445 return err;
446}
447
225c6c8c 448int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 449 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 450{
451 struct mlx4_cmd_mailbox *mailbox;
452 u32 *outbox;
47605df9 453 u8 field, op_modifier;
99ec41d0 454 u32 size, qkey;
eb456a68 455 int err = 0, quotas = 0;
7ae0e400 456 u32 in_modifier;
5cc914f1 457
47605df9 458 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 459 in_modifier = op_modifier ? gen_or_port :
460 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 461
462 mailbox = mlx4_alloc_cmd_mailbox(dev);
463 if (IS_ERR(mailbox))
464 return PTR_ERR(mailbox);
465
7ae0e400 466 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 467 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 468 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
469 if (err)
470 goto out;
471
472 outbox = mailbox->buf;
473
47605df9
JM		 474 if (!op_modifier) {
475 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
476 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
477 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
478 err = -EPROTONOSUPPORT;
479 goto out;
480 }
481 func_cap->flags = field;
eb456a68 482 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 483
47605df9
JM		 484 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
485 func_cap->num_ports = field;
5cc914f1 486
47605df9
JM		 487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
488 func_cap->pf_context_behaviour = size;
5cc914f1 489
eb456a68
JM		 490 if (quotas) {
491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
492 func_cap->qp_quota = size & 0xFFFFFF;
493
494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
495 func_cap->srq_quota = size & 0xFFFFFF;
496
497 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
498 func_cap->cq_quota = size & 0xFFFFFF;
499
500 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
501 func_cap->mpt_quota = size & 0xFFFFFF;
502
503 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
504 func_cap->mtt_quota = size & 0xFFFFFF;
505
506 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
507 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 508
eb456a68
JM		 509 } else {
510 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
511 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 512
eb456a68
JM		 513 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
514 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 515
eb456a68
JM		 516 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
517 func_cap->cq_quota = size & 0xFFFFFF;
518
519 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
520 func_cap->mpt_quota = size & 0xFFFFFF;
521
522 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
523 func_cap->mtt_quota = size & 0xFFFFFF;
524
525 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
526 func_cap->mcg_quota = size & 0xFFFFFF;
527 }
47605df9
JM		 528 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
529 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 530
47605df9
JM		 531 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
532 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 533
f0ce0615
JM		 534 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) {
535 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
536 func_cap->reserved_lkey = size;
537 } else {
538 func_cap->reserved_lkey = 0;
539 }
540
ddae0349
EE		 541 func_cap->extra_flags = 0;
542
543 /* Mailbox data from 0x6c and onward should only be treated if
544 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
545 */
546 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
547 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
548 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
549 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
d57febe1
MB		 550 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
551 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
ddae0349
EE		 552 }
553
47605df9
JM		 554 goto out;
555 }
5cc914f1 556
47605df9
JM		 557 /* logical port query */
558 if (gen_or_port > dev->caps.num_ports) {
559 err = -EINVAL;
560 goto out;
561 }
5cc914f1 562
eb17711b 563 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 564 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 565 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 566 mlx4_err(dev, "VLAN is enforced on this port\n");
567 err = -EPROTONOSUPPORT;
5cc914f1 568 goto out;
47605df9 569 }
5cc914f1 570
eb17711b 571 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 572 mlx4_err(dev, "Force mac is enabled on this port\n");
573 err = -EPROTONOSUPPORT;
574 goto out;
5cc914f1 575 }
47605df9 576 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 577 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
578 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 579 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 580 err = -EPROTONOSUPPORT;
581 goto out;
582 }
583 }
5cc914f1 584
47605df9
JM		 585 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
586 func_cap->physical_port = field;
587 if (func_cap->physical_port != gen_or_port) {
588 err = -ENOSYS;
589 goto out;
5cc914f1
MA		 590 }
591
99ec41d0
JM		 592 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
593 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
594 func_cap->qp0_qkey = qkey;
595 } else {
596 func_cap->qp0_qkey = 0;
597 }
598
47605df9
JM		 599 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
600 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
601
602 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
603 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
604
605 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
606 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
607
608 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
609 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
610
8e1a28e8
HHZ		 611 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
612 MLX4_GET(func_cap->phys_port_id, outbox,
613 QUERY_FUNC_CAP_PHYS_PORT_ID);
614
77fc29c4
HHZ		 615 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
616 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT);
617
5cc914f1
MA		 618 /* All other resources are allocated by the master, but we still report
619 * 'num' and 'reserved' capabilities as follows:
620 * - num remains the maximum resource index
621 * - 'num - reserved' is the total available objects of a resource, but
622 * resource indices may be less than 'reserved'
623 * TODO: set per-resource quotas */
624
625out:
626 mlx4_free_cmd_mailbox(dev, mailbox);
627
628 return err;
629}
630
d8ae9141
MS		 631static void disable_unsupported_roce_caps(void *buf);
632
225c7b1f
RD		 633int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
634{
635 struct mlx4_cmd_mailbox *mailbox;
636 u32 *outbox;
637 u8 field;
ccf86321 638 u32 field32, flags, ext_flags;
225c7b1f
RD		 639 u16 size;
640 u16 stat_rate;
641 int err;
5ae2a7a8 642 int i;
225c7b1f
RD		 643
644#define QUERY_DEV_CAP_OUT_SIZE 0x100
645#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
646#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
647#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
648#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
649#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
650#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
651#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
652#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
653#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
654#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
655#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
656#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
657#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
658#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
659#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
660#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
661#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
662#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 663#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 664#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
665#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
666#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 667#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 668#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 669#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
670#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
51af33cf 671#define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34
225c7b1f
RD		 672#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
673#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
674#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 675#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 676#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
677#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 678#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 679#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 680#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 681#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
682#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
683#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
684#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
685#define QUERY_DEV_CAP_BF_OFFSET 0x4c
686#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
687#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
688#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
689#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
690#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
691#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
692#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
693#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
694#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
695#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
696#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
697#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 698#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
699#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 700#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
0b131561 701#define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70
3f7fb021 702#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 703#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 704#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
705#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 706#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
d237baa1 707#define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b
225c7b1f
RD		 708#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
709#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
710#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
711#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
712#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
713#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
714#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
715#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
716#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
717#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 718#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 719#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
77fc29c4 720#define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96
225c7b1f
RD		 721#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
722#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 723#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
c7c122ed 724#define QUERY_DEV_CAP_DIAG_RPRT_PER_PORT 0x9c
955154fa 725#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 726#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 727#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
7d077cd3
MB		 728#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
729#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
fc31e256
OG		 730#define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
731#define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
732#define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
733
225c7b1f 734
b3416f44 735 dev_cap->flags2 = 0;
225c7b1f
RD		 736 mailbox = mlx4_alloc_cmd_mailbox(dev);
737 if (IS_ERR(mailbox))
738 return PTR_ERR(mailbox);
739 outbox = mailbox->buf;
740
741 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 742 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 743 if (err)
744 goto out;
745
d8ae9141
MS		 746 if (mlx4_is_mfunc(dev))
747 disable_unsupported_roce_caps(outbox);
225c7b1f
RD		 748 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
749 dev_cap->reserved_qps = 1 << (field & 0xf);
750 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
751 dev_cap->max_qps = 1 << (field & 0x1f);
752 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
753 dev_cap->reserved_srqs = 1 << (field >> 4);
754 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
755 dev_cap->max_srqs = 1 << (field & 0x1f);
756 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
757 dev_cap->max_cq_sz = 1 << field;
758 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
759 dev_cap->reserved_cqs = 1 << (field & 0xf);
760 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
761 dev_cap->max_cqs = 1 << (field & 0x1f);
762 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
763 dev_cap->max_mpts = 1 << (field & 0x3f);
764 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 765 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 766 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 767 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 768 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
769 dev_cap->reserved_mtts = 1 << (field >> 4);
770 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
771 dev_cap->max_mrw_sz = 1 << field;
772 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
773 dev_cap->reserved_mrws = 1 << (field & 0xf);
774 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
775 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 776 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
777 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 778 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
779 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
780 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
781 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 782 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
783 field &= 0x1f;
784 if (!field)
785 dev_cap->max_gso_sz = 0;
786 else
787 dev_cap->max_gso_sz = 1 << field;
788
b3416f44
SP		 789 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
790 if (field & 0x20)
791 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
792 if (field & 0x10)
793 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
794 field &= 0xf;
795 if (field) {
796 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
797 dev_cap->max_rss_tbl_sz = 1 << field;
798 } else
799 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 800 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
801 dev_cap->max_rdma_global = 1 << (field & 0x3f);
802 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
803 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 804 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 805 dev_cap->num_ports = field & 0xf;
149983af 806 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
fab9adfb 807 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0b131561
MB		 808 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);
809 if (field & 0x10)
810 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;
0ff1fb65
HHZ		 811 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
812 if (field & 0x80)
813 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
814 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
0e451e88
MV		 815 if (field & 0x20)
816 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;
51af33cf
IS		 817 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
818 if (field & 0x80)
819 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;
4de65803
MB		 820 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
821 if (field & 0x80)
822 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 823 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
824 dev_cap->fs_max_num_qp_per_entry = field;
d237baa1
SM		 825 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
826 if (field & 0x1)
827 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
225c7b1f
RD		 828 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
829 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 830 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
831 if (field & 0x80)
832 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 833 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 834 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 835 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 836 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
837 dev_cap->reserved_uars = field >> 4;
838 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
839 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
840 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
841 dev_cap->min_page_sz = 1 << field;
842
843 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
844 if (field & 0x80) {
845 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
846 dev_cap->bf_reg_size = 1 << (field & 0x1f);
847 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 848 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 849 field = 3;
225c7b1f 850 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
225c7b1f
RD		 851 } else {
852 dev_cap->bf_reg_size = 0;
225c7b1f
RD		 853 }
854
855 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
856 dev_cap->max_sq_sg = field;
857 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
858 dev_cap->max_sq_desc_sz = size;
859
860 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
861 dev_cap->max_qp_per_mcg = 1 << field;
862 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
863 dev_cap->reserved_mgms = field & 0xf;
864 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
865 dev_cap->max_mcgs = 1 << field;
866 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
867 dev_cap->reserved_pds = field >> 4;
868 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
869 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 870 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
871 dev_cap->reserved_xrcds = field >> 4;
426dd00d 872 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 873 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 874
875 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
876 dev_cap->rdmarc_entry_sz = size;
877 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
878 dev_cap->qpc_entry_sz = size;
879 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
880 dev_cap->aux_entry_sz = size;
881 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
882 dev_cap->altc_entry_sz = size;
883 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
884 dev_cap->eqc_entry_sz = size;
885 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
886 dev_cap->cqc_entry_sz = size;
887 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
888 dev_cap->srq_entry_sz = size;
889 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
890 dev_cap->cmpt_entry_sz = size;
891 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
892 dev_cap->mtt_entry_sz = size;
893 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
894 dev_cap->dmpt_entry_sz = size;
895
896 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
897 dev_cap->max_srq_sz = 1 << field;
898 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
899 dev_cap->max_qp_sz = 1 << field;
900 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
901 dev_cap->resize_srq = field & 1;
902 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
903 dev_cap->max_rq_sg = field;
904 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
905 dev_cap->max_rq_desc_sz = size;
77507aa2 906 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
d019fcb2
IS		 907 if (field & (1 << 4))
908 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;
adbc7ac5
SM		 909 if (field & (1 << 5))
910 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 911 if (field & (1 << 6))
912 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
913 if (field & (1 << 7))
914 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 915 MLX4_GET(dev_cap->bmme_flags, outbox,
916 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
d8ae9141
MS		 917 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)
918 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
59e14e32
MS		 919 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
920 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
d475c95b
MB		 921 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
922 if (field & 0x20)
923 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
78500b8c
MM		 924 if (field & (1 << 2))
925 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
77fc29c4
HHZ		 926 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);
927 if (field & 0x80)
928 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;
929 if (field & 0x40)
930 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;
931
225c7b1f
RD		 932 MLX4_GET(dev_cap->reserved_lkey, outbox,
933 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 934 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
935 if (field32 & (1 << 0))
936 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
be6a6b43
JM		 937 if (field32 & (1 << 7))
938 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
c7c122ed
MB		 939 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT);
940 if (field32 & (1 << 17))
941 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;
955154fa
MB		 942 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
943 if (field & 1<<6)
5930e8d0 944 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 945 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
946 if (field & 1<<3)
947 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
3742cc65
IS		 948 if (field & (1 << 5))
949 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
225c7b1f
RD		 950 MLX4_GET(dev_cap->max_icm_sz, outbox,
951 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 952 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
953 MLX4_GET(dev_cap->max_counters, outbox,
954 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 955
114840c3
JM		 956 MLX4_GET(field32, outbox,
957 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
958 if (field32 & (1 << 0))
959 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
960
7d077cd3
MB		 961 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
962 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET);
963 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
964 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
965 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET);
966 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
967
fc31e256
OG		 968 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
969 dev_cap->rl_caps.num_rates = size;
970 if (dev_cap->rl_caps.num_rates) {
971 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
972 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET);
973 dev_cap->rl_caps.max_val = size & 0xfff;
974 dev_cap->rl_caps.max_unit = size >> 14;
975 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET);
976 dev_cap->rl_caps.min_val = size & 0xfff;
977 dev_cap->rl_caps.min_unit = size >> 14;
978 }
979
3f7fb021 980 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 981 if (field32 & (1 << 16))
982 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
9a892835
MG		 983 if (field32 & (1 << 18))
984 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;
985 if (field32 & (1 << 19))
986 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;
3f7fb021
RE		 987 if (field32 & (1 << 26))
988 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 989 if (field32 & (1 << 20))
990 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 991 if (field32 & (1 << 21))
992 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 993
431df8c7
MB		 994 for (i = 1; i <= dev_cap->num_ports; i++) {
995 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
996 if (err)
997 goto out;
5ae2a7a8
RD		 998 }
999
225c7b1f
RD		 1000 /*
1001 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
1002 * we can't use any EQs whose doorbell falls on that page,
1003 * even if the EQ itself isn't reserved.
1004 */
7ae0e400
MB		 1005 if (dev_cap->num_sys_eqs == 0)
1006 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
1007 dev_cap->reserved_eqs);
1008 else
1009 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f 1010
c78e25ed
OG		 1011out:
1012 mlx4_free_cmd_mailbox(dev, mailbox);
1013 return err;
1014}
1015
1016void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1017{
1018 if (dev_cap->bf_reg_size > 0)
1019 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
1020 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
1021 else
1022 mlx4_dbg(dev, "BlueFlame not available\n");
1023
1024 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
1025 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 1026 mlx4_dbg(dev, "Max ICM size %lld MB\n",
1027 (unsigned long long) dev_cap->max_icm_sz >> 20);
1028 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1029 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
1030 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1031 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
1032 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1033 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 1034 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
1035 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
1036 dev_cap->eqc_entry_sz);
225c7b1f
RD		 1037 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1038 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
1039 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1040 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
1041 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1042 dev_cap->max_pds, dev_cap->reserved_mgms);
1043 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1044 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
1045 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
431df8c7
MB		 1046 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
1047 dev_cap->port_cap[1].max_port_width);
225c7b1f
RD		 1048 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
1049 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
1050 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
1051 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 1052 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 1053 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 1054 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
7d077cd3
MB		 1055 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n",
1056 dev_cap->dmfs_high_rate_qpn_base);
1057 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n",
1058 dev_cap->dmfs_high_rate_qpn_range);
fc31e256
OG		 1059
1060 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1061 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;
1062
1063 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n",
1064 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val,
1065 rl_caps->min_unit, rl_caps->min_val);
1066 }
1067
225c7b1f 1068 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 1069 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 1070}
1071
431df8c7
MB		 1072int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
1073{
1074 struct mlx4_cmd_mailbox *mailbox;
1075 u32 *outbox;
1076 u8 field;
1077 u32 field32;
1078 int err;
1079
1080 mailbox = mlx4_alloc_cmd_mailbox(dev);
1081 if (IS_ERR(mailbox))
1082 return PTR_ERR(mailbox);
1083 outbox = mailbox->buf;
1084
1085 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1086 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1087 MLX4_CMD_TIME_CLASS_A,
1088 MLX4_CMD_NATIVE);
1089
1090 if (err)
1091 goto out;
1092
1093 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1094 port_cap->max_vl = field >> 4;
1095 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1096 port_cap->ib_mtu = field >> 4;
1097 port_cap->max_port_width = field & 0xf;
1098 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1099 port_cap->max_gids = 1 << (field & 0xf);
1100 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1101 port_cap->max_pkeys = 1 << (field & 0xf);
1102 } else {
1103#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1104#define QUERY_PORT_MTU_OFFSET 0x01
1105#define QUERY_PORT_ETH_MTU_OFFSET 0x02
1106#define QUERY_PORT_WIDTH_OFFSET 0x06
1107#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1108#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1109#define QUERY_PORT_MAX_VL_OFFSET 0x0b
1110#define QUERY_PORT_MAC_OFFSET 0x10
1111#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1112#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1113#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1114
1115 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
1116 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1117 if (err)
1118 goto out;
1119
1120 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
e34305c8 1121 port_cap->link_state = (field & 0x80) >> 7;
431df8c7
MB		 1122 port_cap->supported_port_types = field & 3;
1123 port_cap->suggested_type = (field >> 3) & 1;
1124 port_cap->default_sense = (field >> 4) & 1;
7d077cd3 1125 port_cap->dmfs_optimized_state = (field >> 5) & 1;
431df8c7
MB		 1126 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1127 port_cap->ib_mtu = field & 0xf;
1128 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1129 port_cap->max_port_width = field & 0xf;
1130 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1131 port_cap->max_gids = 1 << (field >> 4);
1132 port_cap->max_pkeys = 1 << (field & 0xf);
1133 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1134 port_cap->max_vl = field & 0xf;
1135 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1136 port_cap->log_max_macs = field & 0xf;
1137 port_cap->log_max_vlans = field >> 4;
1138 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1139 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1140 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1141 port_cap->trans_type = field32 >> 24;
1142 port_cap->vendor_oui = field32 & 0xffffff;
1143 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1144 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1145 }
1146
1147out:
1148 mlx4_free_cmd_mailbox(dev, mailbox);
1149 return err;
1150}
1151
0b131561 1152#define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28)
383677da
OG		 1153#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1154#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1155#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1156
b91cb3eb
JM		 1157int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1158 struct mlx4_vhcr *vhcr,
1159 struct mlx4_cmd_mailbox *inbox,
1160 struct mlx4_cmd_mailbox *outbox,
1161 struct mlx4_cmd_info *cmd)
1162{
2a4fae14 1163 u64 flags;
b91cb3eb
JM		 1164 int err = 0;
1165 u8 field;
fc31e256 1166 u16 field16;
383677da 1167 u32 bmme_flags, field32;
449fc488
MB		 1168 int real_port;
1169 int slave_port;
1170 int first_port;
1171 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 1172
1173 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1174 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1175 if (err)
1176 return err;
1177
d8ae9141 1178 disable_unsupported_roce_caps(outbox->buf);
cc1ade94
SM		 1179 /* add port mng change event capability and disable mw type 1
1180 * unconditionally to slaves
1181 */
2a4fae14
JM		 1182 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1183 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1184 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1185 actv_ports = mlx4_get_active_ports(dev, slave);
1186 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1187 for (slave_port = 0, real_port = first_port;
1188 real_port < first_port +
1189 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1190 ++real_port, ++slave_port) {
1191 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1192 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1193 else
1194 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1195 }
1196 for (; slave_port < dev->caps.num_ports; ++slave_port)
1197 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
802f42a8
IS		 1198
1199 /* Not exposing RSS IP fragments to guests */
1200 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG;
2a4fae14
JM		 1201 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1202
449fc488
MB		 1203 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1204 field &= ~0x0F;
1205 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1206 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1207
30b40c31
AV		 1208 /* For guests, disable timestamp */
1209 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1210 field &= 0x7f;
1211 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1212
3742cc65 1213 /* For guests, disable vxlan tunneling and QoS support */
57352ef4 1214 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
3742cc65 1215 field &= 0xd7;
7ffdf726
OG		 1216 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1217
51af33cf
IS		 1218 /* For guests, disable port BEACON */
1219 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1220 field &= 0x7f;
1221 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1222
b91cb3eb
JM		 1223 /* For guests, report Blueflame disabled */
1224 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1225 field &= 0x7f;
1226 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1227
59e14e32 1228 /* For guests, disable mw type 2 and port remap*/
57352ef4 1229 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94 1230 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
59e14e32 1231 bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
cc1ade94
SM		 1232 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1233
0081c8f3
JM		 1234 /* turn off device-managed steering capability if not enabled */
1235 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1236 MLX4_GET(field, outbox->buf,
1237 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1238 field &= 0x7f;
1239 MLX4_PUT(outbox->buf, field,
1240 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1241 }
4de65803
MB		 1242
1243 /* turn off ipoib managed steering for guests */
57352ef4 1244 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1245 field &= ~0x80;
1246 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1247
383677da
OG		 1248 /* turn off host side virt features (VST, FSM, etc) for guests */
1249 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1250 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
0b131561 1251 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS);
383677da
OG		 1252 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1253
d237baa1
SM		 1254 /* turn off QCN for guests */
1255 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1256 field &= 0xfe;
1257 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1258
fc31e256
OG		 1259 /* turn off QP max-rate limiting for guests */
1260 field16 = 0;
1261 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1262
d019fcb2
IS		 1263 /* turn off QoS per VF support for guests */
1264 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1265 field &= 0xef;
1266 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1267
78500b8c
MM		 1268 /* turn off ignore FCS feature for guests */
1269 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1270 field &= 0xfb;
1271 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1272
b91cb3eb
JM		 1273 return 0;
1274}
1275
d8ae9141
MS		 1276static void disable_unsupported_roce_caps(void *buf)
1277{
1278 u32 flags;
1279
1280 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1281 flags &= ~(1UL << 31);
1282 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1283 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1284 flags &= ~(1UL << 24);
1285 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1286 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1287 flags &= ~(MLX4_FLAG_ROCE_V1_V2);
1288 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1289}
1290
5cc914f1
MA		 1291int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1292 struct mlx4_vhcr *vhcr,
1293 struct mlx4_cmd_mailbox *inbox,
1294 struct mlx4_cmd_mailbox *outbox,
1295 struct mlx4_cmd_info *cmd)
1296{
0eb62b93 1297 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1298 u64 def_mac;
1299 u8 port_type;
6634961c 1300 u16 short_field;
5cc914f1 1301 int err;
948e306d 1302 int admin_link_state;
449fc488
MB		 1303 int port = mlx4_slave_convert_port(dev, slave,
1304 vhcr->in_modifier & 0xFF);
5cc914f1 1305
105c320f 1306#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1307#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1308#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1309#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1310
449fc488
MB		 1311 if (port < 0)
1312 return -EINVAL;
1313
a7401b9c
JM		 1314 /* Protect against untrusted guests: enforce that this is the
1315 * QUERY_PORT general query.
1316 */
1317 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1318 return -EINVAL;
1319
1320 vhcr->in_modifier = port;
449fc488 1321
5cc914f1
MA		 1322 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1323 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1324 MLX4_CMD_NATIVE);
1325
1326 if (!err && dev->caps.function != slave) {
0508ad64 1327 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1328 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1329
1330 /* get port type - currently only eth is enabled */
1331 MLX4_GET(port_type, outbox->buf,
1332 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1333
105c320f
JM		 1334 /* No link sensing allowed */
1335 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1336 /* set port type to currently operating port type */
1337 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1338
948e306d
RE		 1339 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1340 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1341 port_type |= MLX4_PORT_LINK_UP_MASK;
1342 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1343 port_type &= ~MLX4_PORT_LINK_UP_MASK;
e34305c8
OG		 1344 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) {
1345 int other_port = (port == 1) ? 2 : 1;
1346 struct mlx4_port_cap port_cap;
1347
1348 err = mlx4_QUERY_PORT(dev, other_port, &port_cap);
1349 if (err)
1350 goto out;
1351 port_type |= (port_cap.link_state << 7);
1352 }
948e306d 1353
5cc914f1
MA		 1354 MLX4_PUT(outbox->buf, port_type,
1355 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1356
b6ffaeff 1357 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1358 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1359 else
1360 short_field = 1; /* slave max gids */
6634961c
JM		 1361 MLX4_PUT(outbox->buf, short_field,
1362 QUERY_PORT_CUR_MAX_GID_OFFSET);
1363
1364 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1365 MLX4_PUT(outbox->buf, short_field,
1366 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1 1367 }
e34305c8 1368out:
5cc914f1
MA		 1369 return err;
1370}
1371
6634961c
JM		 1372int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1373 int *gid_tbl_len, int *pkey_tbl_len)
1374{
1375 struct mlx4_cmd_mailbox *mailbox;
1376 u32 *outbox;
1377 u16 field;
1378 int err;
1379
1380 mailbox = mlx4_alloc_cmd_mailbox(dev);
1381 if (IS_ERR(mailbox))
1382 return PTR_ERR(mailbox);
1383
1384 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1385 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1386 MLX4_CMD_WRAPPED);
1387 if (err)
1388 goto out;
1389
1390 outbox = mailbox->buf;
1391
1392 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1393 *gid_tbl_len = field;
1394
1395 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1396 *pkey_tbl_len = field;
1397
1398out:
1399 mlx4_free_cmd_mailbox(dev, mailbox);
1400 return err;
1401}
1402EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1403
225c7b1f
RD		 1404int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1405{
1406 struct mlx4_cmd_mailbox *mailbox;
1407 struct mlx4_icm_iter iter;
1408 __be64 *pages;
1409 int lg;
1410 int nent = 0;
1411 int i;
1412 int err = 0;
1413 int ts = 0, tc = 0;
1414
1415 mailbox = mlx4_alloc_cmd_mailbox(dev);
1416 if (IS_ERR(mailbox))
1417 return PTR_ERR(mailbox);
225c7b1f
RD		 1418 pages = mailbox->buf;
1419
1420 for (mlx4_icm_first(icm, &iter);
1421 !mlx4_icm_last(&iter);
1422 mlx4_icm_next(&iter)) {
1423 /*
1424 * We have to pass pages that are aligned to their
1425 * size, so find the least significant 1 in the
1426 * address or size and use that as our log2 size.
1427 */
1428 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1429 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1430 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1431 MLX4_ICM_PAGE_SIZE,
1432 (unsigned long long) mlx4_icm_addr(&iter),
1433 mlx4_icm_size(&iter));
225c7b1f
RD		 1434 err = -EINVAL;
1435 goto out;
1436 }
1437
1438 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1439 if (virt != -1) {
1440 pages[nent * 2] = cpu_to_be64(virt);
1441 virt += 1 << lg;
1442 }
1443
1444 pages[nent * 2 + 1] =
1445 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1446 (lg - MLX4_ICM_PAGE_SHIFT));
1447 ts += 1 << (lg - 10);
1448 ++tc;
1449
1450 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1451 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1452 MLX4_CMD_TIME_CLASS_B,
1453 MLX4_CMD_NATIVE);
225c7b1f
RD		 1454 if (err)
1455 goto out;
1456 nent = 0;
1457 }
1458 }
1459 }
1460
1461 if (nent)
f9baff50
JM		 1462 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1463 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1464 if (err)
1465 goto out;
1466
1467 switch (op) {
1468 case MLX4_CMD_MAP_FA:
1a91de28 1469 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1470 break;
1471 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1472 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1473 break;
1474 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1475 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1476 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1477 break;
1478 }
1479
1480out:
1481 mlx4_free_cmd_mailbox(dev, mailbox);
1482 return err;
1483}
1484
1485int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1486{
1487 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1488}
1489
1490int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1491{
f9baff50
JM		 1492 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1493 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1494}
1495
1496
1497int mlx4_RUN_FW(struct mlx4_dev *dev)
1498{
f9baff50
JM		 1499 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1500 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1501}
1502
1503int mlx4_QUERY_FW(struct mlx4_dev *dev)
1504{
1505 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1506 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1507 struct mlx4_cmd_mailbox *mailbox;
1508 u32 *outbox;
1509 int err = 0;
1510 u64 fw_ver;
fe40900f 1511 u16 cmd_if_rev;
225c7b1f
RD		 1512 u8 lg;
1513
1514#define QUERY_FW_OUT_SIZE 0x100
1515#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1516#define QUERY_FW_PPF_ID 0x09
fe40900f 1517#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1518#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1519#define QUERY_FW_ERR_START_OFFSET 0x30
1520#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1521#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1522
1523#define QUERY_FW_SIZE_OFFSET 0x00
1524#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1525#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1526
5cc914f1
MA		 1527#define QUERY_FW_COMM_BASE_OFFSET 0x40
1528#define QUERY_FW_COMM_BAR_OFFSET 0x48
1529
ddd8a6c1
EE		 1530#define QUERY_FW_CLOCK_OFFSET 0x50
1531#define QUERY_FW_CLOCK_BAR 0x58
1532
225c7b1f
RD		 1533 mailbox = mlx4_alloc_cmd_mailbox(dev);
1534 if (IS_ERR(mailbox))
1535 return PTR_ERR(mailbox);
1536 outbox = mailbox->buf;
1537
1538 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1539 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1540 if (err)
1541 goto out;
1542
1543 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1544 /*
3e1db334 1545 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1546 * version, so swap here.
1547 */
1548 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1549 ((fw_ver & 0xffff0000ull) >> 16) |
1550 ((fw_ver & 0x0000ffffull) << 16);
1551
752a50ca
JM		 1552 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1553 dev->caps.function = lg;
1554
b91cb3eb
JM		 1555 if (mlx4_is_slave(dev))
1556 goto out;
1557
5cc914f1 1558
fe40900f 1559 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1560 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1561 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1562 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1563 cmd_if_rev);
1564 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1565 (int) (dev->caps.fw_ver >> 32),
1566 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1567 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1568 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1569 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1570 err = -ENODEV;
1571 goto out;
1572 }
1573
5ae2a7a8
RD		 1574 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1575 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1576
225c7b1f
RD		 1577 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1578 cmd->max_cmds = 1 << lg;
1579
fe40900f 1580 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1581 (int) (dev->caps.fw_ver >> 32),
1582 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1583 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1584 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1585
1586 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1587 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1588 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1589 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1590
1591 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1592 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1593
1594 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1595 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1596 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1597 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1598
5cc914f1
MA		 1599 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1600 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1601 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1602 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1603 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1604 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1605
ddd8a6c1
EE		 1606 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1607 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1608 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1609 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1610 fw->clock_bar, fw->clock_offset);
1611
225c7b1f
RD		 1612 /*
1613 * Round up number of system pages needed in case
1614 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1615 */
1616 fw->fw_pages =
1617 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1618 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1619
1620 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1621 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1622
1623out:
1624 mlx4_free_cmd_mailbox(dev, mailbox);
1625 return err;
1626}
1627
b91cb3eb
JM		 1628int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1629 struct mlx4_vhcr *vhcr,
1630 struct mlx4_cmd_mailbox *inbox,
1631 struct mlx4_cmd_mailbox *outbox,
1632 struct mlx4_cmd_info *cmd)
1633{
1634 u8 *outbuf;
1635 int err;
1636
1637 outbuf = outbox->buf;
1638 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1639 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1640 if (err)
1641 return err;
1642
752a50ca
JM		 1643 /* for slaves, set pci PPF ID to invalid and zero out everything
1644 * else except FW version */
b91cb3eb
JM		 1645 outbuf[0] = outbuf[1] = 0;
1646 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1647 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1648
b91cb3eb
JM		 1649 return 0;
1650}
1651
225c7b1f
RD		 1652static void get_board_id(void *vsd, char *board_id)
1653{
1654 int i;
1655
1656#define VSD_OFFSET_SIG1 0x00
1657#define VSD_OFFSET_SIG2 0xde
1658#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1659#define VSD_OFFSET_TS_BOARD_ID 0x20
1660
1661#define VSD_SIGNATURE_TOPSPIN 0x5ad
1662
1663 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1664
1665 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1666 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1667 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1668 } else {
1669 /*
1670 * The board ID is a string but the firmware byte
1671 * swaps each 4-byte word before passing it back to
1672 * us. Therefore we need to swab it before printing.
1673 */
17d5ceb6
DA		 1674 u32 *bid_u32 = (u32 *)board_id;
1675
1676 for (i = 0; i < 4; ++i) {
1677 u32 *addr;
1678 u32 val;
1679
1680 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4);
1681 val = get_unaligned(addr);
1682 val = swab32(val);
1683 put_unaligned(val, &bid_u32[i]);
1684 }
225c7b1f
RD		 1685 }
1686}
1687
1688int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1689{
1690 struct mlx4_cmd_mailbox *mailbox;
1691 u32 *outbox;
1692 int err;
1693
1694#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1695#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1696#define QUERY_ADAPTER_VSD_OFFSET 0x20
1697
1698 mailbox = mlx4_alloc_cmd_mailbox(dev);
1699 if (IS_ERR(mailbox))
1700 return PTR_ERR(mailbox);
1701 outbox = mailbox->buf;
1702
1703 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1704 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1705 if (err)
1706 goto out;
1707
225c7b1f
RD		 1708 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1709
1710 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1711 adapter->board_id);
1712
1713out:
1714 mlx4_free_cmd_mailbox(dev, mailbox);
1715 return err;
1716}
1717
1718int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1719{
1720 struct mlx4_cmd_mailbox *mailbox;
1721 __be32 *inbox;
1722 int err;
7d077cd3
MB		 1723 static const u8 a0_dmfs_hw_steering[] = {
1724 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0,
1725 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1,
1726 [MLX4_STEERING_DMFS_A0_STATIC] = 2,
1727 [MLX4_STEERING_DMFS_A0_DISABLE] = 3
1728 };
225c7b1f
RD		 1729
1730#define INIT_HCA_IN_SIZE 0x200
1731#define INIT_HCA_VERSION_OFFSET 0x000
1732#define INIT_HCA_VERSION 2
7ffdf726 1733#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1734#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f 1735#define INIT_HCA_FLAGS_OFFSET 0x014
be6a6b43 1736#define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
225c7b1f
RD		 1737#define INIT_HCA_QPC_OFFSET 0x020
1738#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1739#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1740#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1741#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1742#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1743#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1744#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1745#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1746#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1747#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1748#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1749#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1750#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1751#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1752#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1753#define INIT_HCA_MCAST_OFFSET 0x0c0
1754#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1755#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1756#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1757#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1758#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1759#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1760#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1761#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1762#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
7d077cd3 1763#define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
0ff1fb65
HHZ		 1764#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1765#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1766#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1767#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1768#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1769#define INIT_HCA_TPT_OFFSET 0x0f0
1770#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1771#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1772#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1773#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1774#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1775#define INIT_HCA_UAR_OFFSET 0x120
1776#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1777#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1778
1779 mailbox = mlx4_alloc_cmd_mailbox(dev);
1780 if (IS_ERR(mailbox))
1781 return PTR_ERR(mailbox);
1782 inbox = mailbox->buf;
1783
225c7b1f
RD		 1784 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1785
c57e20dc
EC		 1786 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1787 (ilog2(cache_line_size()) - 4) << 5;
1788
225c7b1f
RD		 1789#if defined(__LITTLE_ENDIAN)
1790 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1791#elif defined(__BIG_ENDIAN)
1792 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1793#else
1794#error Host endianness not defined
1795#endif
1796 /* Check port for UD address vector: */
1797 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1798
8ff095ec
EC		 1799 /* Enable IPoIB checksumming if we can: */
1800 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1801 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1802
51f5f0ee 1803 /* Enable QoS support if module parameter set */
38438f7c 1804 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)
51f5f0ee
JM		 1805 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1806
f2a3f6a3
OG		 1807 /* enable counters */
1808 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1809 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1810
802f42a8
IS		 1811 /* Enable RSS spread to fragmented IP packets when supported */
1812 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG)
1813 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13);
1814
08ff3235
OG		 1815 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1816 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1817 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1818 dev->caps.eqe_size = 64;
1819 dev->caps.eqe_factor = 1;
1820 } else {
1821 dev->caps.eqe_size = 32;
1822 dev->caps.eqe_factor = 0;
1823 }
1824
1825 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1826 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1827 dev->caps.cqe_size = 64;
77507aa2 1828 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1829 } else {
1830 dev->caps.cqe_size = 32;
1831 }
1832
77507aa2
IS		 1833 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1834 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1835 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1836 dev->caps.eqe_size = cache_line_size();
1837 dev->caps.cqe_size = cache_line_size();
1838 dev->caps.eqe_factor = 0;
1839 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1840 (ilog2(dev->caps.eqe_size) - 5)),
1841 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1842
1843 /* User still need to know to support CQE > 32B */
1844 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1845 }
1846
be6a6b43
JM		 1847 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1848 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1849
225c7b1f
RD		 1850 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1851
1852 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1853 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1854 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1855 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1856 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1857 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1858 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1859 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1860 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1861 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1862 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1863 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1864 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1865
0ff1fb65
HHZ		 1866 /* steering attributes */
1867 if (dev->caps.steering_mode ==
1868 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1869 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1870 cpu_to_be32(1 <<
1871 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1872
1873 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1874 MLX4_PUT(inbox, param->log_mc_entry_sz,
1875 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1876 MLX4_PUT(inbox, param->log_mc_table_sz,
1877 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1878 /* Enable Ethernet flow steering
1879 * with udp unicast and tcp unicast
1880 */
7d077cd3
MB		 1881 if (dev->caps.dmfs_high_steer_mode !=
1882 MLX4_STEERING_DMFS_A0_STATIC)
1883 MLX4_PUT(inbox,
1884 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1885 INIT_HCA_FS_ETH_BITS_OFFSET);
0ff1fb65
HHZ		 1886 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1887 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1888 /* Enable IPoIB flow steering
1889 * with udp unicast and tcp unicast
1890 */
23537b73 1891 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1892 INIT_HCA_FS_IB_BITS_OFFSET);
1893 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1894 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
7d077cd3
MB		 1895
1896 if (dev->caps.dmfs_high_steer_mode !=
1897 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1898 MLX4_PUT(inbox,
1899 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode]
1900 << 6)),
1901 INIT_HCA_FS_A0_OFFSET);
0ff1fb65
HHZ		 1902 } else {
1903 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1904 MLX4_PUT(inbox, param->log_mc_entry_sz,
1905 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1906 MLX4_PUT(inbox, param->log_mc_hash_sz,
1907 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1908 MLX4_PUT(inbox, param->log_mc_table_sz,
1909 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1910 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1911 MLX4_PUT(inbox, (u8) (1 << 3),
1912 INIT_HCA_UC_STEERING_OFFSET);
1913 }
225c7b1f
RD		 1914
1915 /* TPT attributes */
1916
1917 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1918 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1919 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1920 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1921 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1922
1923 /* UAR attributes */
1924
ab9c17a0 1925 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1926 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1927
7ffdf726
OG		 1928 /* set parser VXLAN attributes */
1929 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1930 u8 parser_params = 0;
1931 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1932 }
1933
5a031086
JM		 1934 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
1935 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
225c7b1f
RD		 1936
1937 if (err)
1938 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1939
1940 mlx4_free_cmd_mailbox(dev, mailbox);
1941 return err;
1942}
1943
ab9c17a0
JM		 1944int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1945 struct mlx4_init_hca_param *param)
1946{
1947 struct mlx4_cmd_mailbox *mailbox;
1948 __be32 *outbox;
7b8157be 1949 u32 dword_field;
ab9c17a0 1950 int err;
08ff3235 1951 u8 byte_field;
7d077cd3
MB		 1952 static const u8 a0_dmfs_query_hw_steering[] = {
1953 [0] = MLX4_STEERING_DMFS_A0_DEFAULT,
1954 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC,
1955 [2] = MLX4_STEERING_DMFS_A0_STATIC,
1956 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1957 };
ab9c17a0
JM		 1958
1959#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1960#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1961
1962 mailbox = mlx4_alloc_cmd_mailbox(dev);
1963 if (IS_ERR(mailbox))
1964 return PTR_ERR(mailbox);
1965 outbox = mailbox->buf;
1966
1967 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1968 MLX4_CMD_QUERY_HCA,
1969 MLX4_CMD_TIME_CLASS_B,
1970 !mlx4_is_slave(dev));
1971 if (err)
1972 goto out;
1973
1974 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1975 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1976
1977 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1978
1979 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1980 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1981 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1982 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1983 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1984 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1985 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1986 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1987 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1988 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1989 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1990 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1991 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1992
7b8157be
JM		 1993 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1994 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1995 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1996 } else {
1997 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1998 if (byte_field & 0x8)
1999 param->steering_mode = MLX4_STEERING_MODE_B0;
2000 else
2001 param->steering_mode = MLX4_STEERING_MODE_A0;
2002 }
802f42a8
IS		 2003
2004 if (dword_field & (1 << 13))
2005 param->rss_ip_frags = 1;
2006
0ff1fb65 2007 /* steering attributes */
7b8157be 2008 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 2009 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
2010 MLX4_GET(param->log_mc_entry_sz, outbox,
2011 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
2012 MLX4_GET(param->log_mc_table_sz, outbox,
2013 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
7d077cd3
MB		 2014 MLX4_GET(byte_field, outbox,
2015 INIT_HCA_FS_A0_OFFSET);
2016 param->dmfs_high_steer_mode =
2017 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3];
0ff1fb65
HHZ		 2018 } else {
2019 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
2020 MLX4_GET(param->log_mc_entry_sz, outbox,
2021 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
2022 MLX4_GET(param->log_mc_hash_sz, outbox,
2023 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
2024 MLX4_GET(param->log_mc_table_sz, outbox,
2025 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
2026 }
ab9c17a0 2027
08ff3235
OG		 2028 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
2029 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
2030 if (byte_field & 0x20) /* 64-bytes eqe enabled */
2031 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
2032 if (byte_field & 0x40) /* 64-bytes cqe enabled */
2033 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
2034
77507aa2
IS		 2035 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
2036 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
2037 if (byte_field) {
c3f2511f
IS		 2038 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
2039 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
77507aa2
IS		 2040 param->cqe_size = 1 << ((byte_field &
2041 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
2042 param->eqe_size = 1 << (((byte_field &
2043 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
2044 }
2045
ab9c17a0
JM		 2046 /* TPT attributes */
2047
2048 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 2049 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 2050 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
2051 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
2052 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
2053
2054 /* UAR attributes */
2055
2056 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2057 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
2058
77fc29c4
HHZ		 2059 /* phv_check enable */
2060 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET);
2061 if (byte_field & 0x2)
2062 param->phv_check_en = 1;
ab9c17a0
JM		 2063out:
2064 mlx4_free_cmd_mailbox(dev, mailbox);
2065
2066 return err;
2067}
2068
6d6e996c
MD		 2069static int mlx4_hca_core_clock_update(struct mlx4_dev *dev)
2070{
2071 struct mlx4_cmd_mailbox *mailbox;
2072 __be32 *outbox;
2073 int err;
2074
2075 mailbox = mlx4_alloc_cmd_mailbox(dev);
2076 if (IS_ERR(mailbox)) {
2077 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n");
2078 return PTR_ERR(mailbox);
2079 }
2080 outbox = mailbox->buf;
2081
2082 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2083 MLX4_CMD_QUERY_HCA,
2084 MLX4_CMD_TIME_CLASS_B,
2085 !mlx4_is_slave(dev));
2086 if (err) {
2087 mlx4_warn(dev, "hca_core_clock update failed\n");
2088 goto out;
2089 }
2090
2091 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2092
2093out:
2094 mlx4_free_cmd_mailbox(dev, mailbox);
2095
2096 return err;
2097}
2098
980e9001
JM		 2099/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
2100 * and real QP0 are active, so that the paravirtualized QP0 is ready
2101 * to operate */
2102static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
2103{
2104 struct mlx4_priv *priv = mlx4_priv(dev);
2105 /* irrelevant if not infiniband */
2106 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
2107 priv->mfunc.master.qp0_state[port].qp0_active)
2108 return 1;
2109 return 0;
2110}
2111
5cc914f1
MA		 2112int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
2113 struct mlx4_vhcr *vhcr,
2114 struct mlx4_cmd_mailbox *inbox,
2115 struct mlx4_cmd_mailbox *outbox,
2116 struct mlx4_cmd_info *cmd)
2117{
2118 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 2119 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 2120 int err;
2121
449fc488
MB		 2122 if (port < 0)
2123 return -EINVAL;
2124
5cc914f1
MA		 2125 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
2126 return 0;
2127
980e9001
JM		 2128 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2129 /* Enable port only if it was previously disabled */
2130 if (!priv->mfunc.master.init_port_ref[port]) {
2131 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2132 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2133 if (err)
2134 return err;
2135 }
2136 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2137 } else {
2138 if (slave == mlx4_master_func_num(dev)) {
2139 if (check_qp0_state(dev, slave, port) &&
2140 !priv->mfunc.master.qp0_state[port].port_active) {
2141 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2142 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2143 if (err)
2144 return err;
2145 priv->mfunc.master.qp0_state[port].port_active = 1;
2146 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2147 }
2148 } else
2149 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 2150 }
2151 ++priv->mfunc.master.init_port_ref[port];
2152 return 0;
2153}
2154
5ae2a7a8 2155int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 2156{
2157 struct mlx4_cmd_mailbox *mailbox;
2158 u32 *inbox;
2159 int err;
2160 u32 flags;
5ae2a7a8 2161 u16 field;
225c7b1f 2162
5ae2a7a8 2163 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 2164#define INIT_PORT_IN_SIZE 256
2165#define INIT_PORT_FLAGS_OFFSET 0x00
2166#define INIT_PORT_FLAG_SIG (1 << 18)
2167#define INIT_PORT_FLAG_NG (1 << 17)
2168#define INIT_PORT_FLAG_G0 (1 << 16)
2169#define INIT_PORT_VL_SHIFT 4
2170#define INIT_PORT_PORT_WIDTH_SHIFT 8
2171#define INIT_PORT_MTU_OFFSET 0x04
2172#define INIT_PORT_MAX_GID_OFFSET 0x06
2173#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2174#define INIT_PORT_GUID0_OFFSET 0x10
2175#define INIT_PORT_NODE_GUID_OFFSET 0x18
2176#define INIT_PORT_SI_GUID_OFFSET 0x20
2177
5ae2a7a8
RD		 2178 mailbox = mlx4_alloc_cmd_mailbox(dev);
2179 if (IS_ERR(mailbox))
2180 return PTR_ERR(mailbox);
2181 inbox = mailbox->buf;
225c7b1f 2182
5ae2a7a8
RD		 2183 flags = 0;
2184 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
2185 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
2186 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 2187
b79acb49 2188 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 2189 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2190 field = dev->caps.gid_table_len[port];
2191 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2192 field = dev->caps.pkey_table_len[port];
2193 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 2194
5ae2a7a8 2195 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 2196 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 2197
5ae2a7a8
RD		 2198 mlx4_free_cmd_mailbox(dev, mailbox);
2199 } else
2200 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 2201 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f 2202
6d6e996c
MD		 2203 if (!err)
2204 mlx4_hca_core_clock_update(dev);
2205
225c7b1f
RD		 2206 return err;
2207}
2208EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
2209
5cc914f1
MA		 2210int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
2211 struct mlx4_vhcr *vhcr,
2212 struct mlx4_cmd_mailbox *inbox,
2213 struct mlx4_cmd_mailbox *outbox,
2214 struct mlx4_cmd_info *cmd)
2215{
2216 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 2217 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 2218 int err;
2219
449fc488
MB		 2220 if (port < 0)
2221 return -EINVAL;
2222
5cc914f1
MA		 2223 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
2224 (1 << port)))
2225 return 0;
2226
980e9001
JM		 2227 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2228 if (priv->mfunc.master.init_port_ref[port] == 1) {
2229 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
5a031086 2230 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
980e9001
JM		 2231 if (err)
2232 return err;
2233 }
2234 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2235 } else {
2236 /* infiniband port */
2237 if (slave == mlx4_master_func_num(dev)) {
2238 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
2239 priv->mfunc.master.qp0_state[port].port_active) {
2240 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
5a031086 2241 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
980e9001
JM		 2242 if (err)
2243 return err;
2244 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2245 priv->mfunc.master.qp0_state[port].port_active = 0;
2246 }
2247 } else
2248 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 2249 }
5cc914f1
MA		 2250 --priv->mfunc.master.init_port_ref[port];
2251 return 0;
2252}
2253
225c7b1f
RD		 2254int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
2255{
5a031086
JM		 2256 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2257 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 2258}
2259EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
2260
2261int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
2262{
5a031086
JM		 2263 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
2264 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
225c7b1f
RD		 2265}
2266
d18f141a
OG		 2267struct mlx4_config_dev {
2268 __be32 update_flags;
d475c95b 2269 __be32 rsvd1[3];
d18f141a
OG		 2270 __be16 vxlan_udp_dport;
2271 __be16 rsvd2;
fca83006
MS		 2272 __be16 roce_v2_entropy;
2273 __be16 roce_v2_udp_dport;
59e14e32
MS		 2274 __be32 roce_flags;
2275 __be32 rsvd4[25];
2276 __be16 rsvd5;
2277 u8 rsvd6;
d475c95b 2278 u8 rx_checksum_val;
d18f141a
OG		 2279};
2280
2281#define MLX4_VXLAN_UDP_DPORT (1 << 0)
fca83006 2282#define MLX4_ROCE_V2_UDP_DPORT BIT(3)
59e14e32 2283#define MLX4_DISABLE_RX_PORT BIT(18)
d18f141a 2284
d475c95b 2285static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 2286{
2287 int err;
2288 struct mlx4_cmd_mailbox *mailbox;
2289
2290 mailbox = mlx4_alloc_cmd_mailbox(dev);
2291 if (IS_ERR(mailbox))
2292 return PTR_ERR(mailbox);
2293
2294 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2295
2296 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2297 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2298
2299 mlx4_free_cmd_mailbox(dev, mailbox);
2300 return err;
2301}
2302
d475c95b
MB		 2303static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2304{
2305 int err;
2306 struct mlx4_cmd_mailbox *mailbox;
2307
2308 mailbox = mlx4_alloc_cmd_mailbox(dev);
2309 if (IS_ERR(mailbox))
2310 return PTR_ERR(mailbox);
2311
2312 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2313 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2314
2315 if (!err)
2316 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2317
2318 mlx4_free_cmd_mailbox(dev, mailbox);
2319 return err;
2320}
2321
2322/* Conversion between the HW values and the actual functionality.
2323 * The value represented by the array index,
2324 * and the functionality determined by the flags.
2325 */
2326static const u8 config_dev_csum_flags[] = {
2327 [0] = 0,
2328 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2329 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2330 MLX4_RX_CSUM_MODE_L4,
2331 [3] = MLX4_RX_CSUM_MODE_L4 |
2332 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2333 MLX4_RX_CSUM_MODE_MULTI_VLAN
2334};
2335
2336int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2337 struct mlx4_config_dev_params *params)
2338{
6af0a52f 2339 struct mlx4_config_dev config_dev = {0};
d475c95b
MB		 2340 int err;
2341 u8 csum_mask;
2342
2343#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2344#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2345#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2346
2347 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2348 return -ENOTSUPP;
2349
2350 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2351 if (err)
2352 return err;
2353
2354 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2355 CONFIG_DEV_RX_CSUM_MODE_MASK;
2356
2357 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2358 return -EINVAL;
2359 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2360
2361 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2362 CONFIG_DEV_RX_CSUM_MODE_MASK;
2363
2364 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2365 return -EINVAL;
2366 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2367
2368 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2369
2370 return 0;
2371}
2372EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2373
d18f141a
OG		 2374int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2375{
2376 struct mlx4_config_dev config_dev;
2377
2378 memset(&config_dev, 0, sizeof(config_dev));
2379 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2380 config_dev.vxlan_udp_dport = udp_port;
2381
d475c95b 2382 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2383}
2384EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2385
59e14e32
MS		 2386#define CONFIG_DISABLE_RX_PORT BIT(15)
2387int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
2388{
2389 struct mlx4_config_dev config_dev;
2390
2391 memset(&config_dev, 0, sizeof(config_dev));
2392 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
2393 if (dis)
2394 config_dev.roce_flags =
2395 cpu_to_be32(CONFIG_DISABLE_RX_PORT);
2396
2397 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2398}
2399
fca83006
MS		 2400int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port)
2401{
2402 struct mlx4_config_dev config_dev;
2403
2404 memset(&config_dev, 0, sizeof(config_dev));
2405 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT);
2406 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port);
2407
2408 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2409}
2410EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port);
2411
59e14e32
MS		 2412int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
2413{
2414 struct mlx4_cmd_mailbox *mailbox;
2415 struct {
2416 __be32 v_port1;
2417 __be32 v_port2;
2418 } *v2p;
2419 int err;
2420
2421 mailbox = mlx4_alloc_cmd_mailbox(dev);
2422 if (IS_ERR(mailbox))
2423 return -ENOMEM;
2424
2425 v2p = mailbox->buf;
2426 v2p->v_port1 = cpu_to_be32(port1);
2427 v2p->v_port2 = cpu_to_be32(port2);
2428
2429 err = mlx4_cmd(dev, mailbox->dma, 0,
2430 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
2431 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2432
2433 mlx4_free_cmd_mailbox(dev, mailbox);
2434 return err;
2435}
2436
d18f141a 2437
225c7b1f
RD		 2438int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2439{
2440 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2441 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2442 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2443 if (ret)
2444 return ret;
2445
2446 /*
2447 * Round up number of system pages needed in case
2448 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2449 */
2450 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2451 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2452
2453 return 0;
2454}
2455
2456int mlx4_NOP(struct mlx4_dev *dev)
2457{
2458 /* Input modifier of 0x1f means "finish as soon as possible." */
5a031086
JM		 2459 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
2460 MLX4_CMD_NATIVE);
225c7b1f 2461}
14c07b13 2462
8e1a28e8
HHZ		 2463int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2464{
2465 u8 port;
2466 u32 *outbox;
2467 struct mlx4_cmd_mailbox *mailbox;
2468 u32 in_mod;
2469 u32 guid_hi, guid_lo;
2470 int err, ret = 0;
2471#define MOD_STAT_CFG_PORT_OFFSET 8
2472#define MOD_STAT_CFG_GUID_H 0X14
2473#define MOD_STAT_CFG_GUID_L 0X1c
2474
2475 mailbox = mlx4_alloc_cmd_mailbox(dev);
2476 if (IS_ERR(mailbox))
2477 return PTR_ERR(mailbox);
2478 outbox = mailbox->buf;
2479
2480 for (port = 1; port <= dev->caps.num_ports; port++) {
2481 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2482 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2483 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2484 MLX4_CMD_NATIVE);
2485 if (err) {
2486 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2487 port);
2488 ret = err;
2489 } else {
2490 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2491 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2492 dev->caps.phys_port_id[port] = (u64)guid_lo |
2493 (u64)guid_hi << 32;
2494 }
2495 }
2496 mlx4_free_cmd_mailbox(dev, mailbox);
2497 return ret;
2498}
2499
14c07b13
YP		 2500#define MLX4_WOL_SETUP_MODE (5 << 28)
2501int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2502{
2503 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2504
2505 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2506 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2507 MLX4_CMD_NATIVE);
14c07b13
YP		 2508}
2509EXPORT_SYMBOL_GPL(mlx4_wol_read);
2510
2511int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2512{
2513 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2514
2515 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2516 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2517}
2518EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2519
2520enum {
2521 ADD_TO_MCG = 0x26,
2522};
2523
2524
2525void mlx4_opreq_action(struct work_struct *work)
2526{
2527 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2528 opreq_task);
2529 struct mlx4_dev *dev = &priv->dev;
2530 int num_tasks = atomic_read(&priv->opreq_count);
2531 struct mlx4_cmd_mailbox *mailbox;
2532 struct mlx4_mgm *mgm;
2533 u32 *outbox;
2534 u32 modifier;
2535 u16 token;
fe6f700d
YP		 2536 u16 type;
2537 int err;
2538 u32 num_qps;
2539 struct mlx4_qp qp;
2540 int i;
2541 u8 rem_mcg;
2542 u8 prot;
2543
2544#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2545#define GET_OP_REQ_TOKEN_OFFSET 0x14
2546#define GET_OP_REQ_TYPE_OFFSET 0x1a
2547#define GET_OP_REQ_DATA_OFFSET 0x20
2548
2549 mailbox = mlx4_alloc_cmd_mailbox(dev);
2550 if (IS_ERR(mailbox)) {
2551 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2552 return;
2553 }
2554 outbox = mailbox->buf;
2555
2556 while (num_tasks) {
2557 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2558 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2559 MLX4_CMD_NATIVE);
2560 if (err) {
6d3be300 2561 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2562 err);
2563 return;
2564 }
2565 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2566 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2567 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2568 type &= 0xfff;
2569
2570 switch (type) {
2571 case ADD_TO_MCG:
2572 if (dev->caps.steering_mode ==
2573 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2574 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2575 err = EPERM;
2576 break;
2577 }
2578 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2579 GET_OP_REQ_DATA_OFFSET);
2580 num_qps = be32_to_cpu(mgm->members_count) &
2581 MGM_QPN_MASK;
2582 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2583 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2584
2585 for (i = 0; i < num_qps; i++) {
2586 qp.qpn = be32_to_cpu(mgm->qp[i]);
2587 if (rem_mcg)
2588 err = mlx4_multicast_detach(dev, &qp,
2589 mgm->gid,
2590 prot, 0);
2591 else
2592 err = mlx4_multicast_attach(dev, &qp,
2593 mgm->gid,
2594 mgm->gid[5]
2595 , 0, prot,
2596 NULL);
2597 if (err)
2598 break;
2599 }
2600 break;
2601 default:
2602 mlx4_warn(dev, "Bad type for required operation\n");
2603 err = EINVAL;
2604 break;
2605 }
28d222bb
EP		 2606 err = mlx4_cmd(dev, 0, ((u32) err |
2607 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2608 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2609 MLX4_CMD_NATIVE);
2610 if (err) {
2611 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2612 err);
2613 goto out;
2614 }
2615 memset(outbox, 0, 0xffc);
2616 num_tasks = atomic_dec_return(&priv->opreq_count);
2617 }
2618
2619out:
2620 mlx4_free_cmd_mailbox(dev, mailbox);
2621}
114840c3
JM		 2622
2623static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2624 struct mlx4_cmd_mailbox *mailbox)
2625{
2626#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2627#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2628#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2629#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2630
2631 u32 set_attr_mask, getresp_attr_mask;
2632 u32 trap_attr_mask, traprepress_attr_mask;
2633
2634 MLX4_GET(set_attr_mask, mailbox->buf,
2635 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2636 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2637 set_attr_mask);
2638
2639 MLX4_GET(getresp_attr_mask, mailbox->buf,
2640 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2641 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2642 getresp_attr_mask);
2643
2644 MLX4_GET(trap_attr_mask, mailbox->buf,
2645 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2646 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2647 trap_attr_mask);
2648
2649 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2650 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2651 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2652 traprepress_attr_mask);
2653
2654 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2655 traprepress_attr_mask)
2656 return 1;
2657
2658 return 0;
2659}
2660
2661int mlx4_config_mad_demux(struct mlx4_dev *dev)
2662{
2663 struct mlx4_cmd_mailbox *mailbox;
2664 int secure_host_active;
2665 int err;
2666
2667 /* Check if mad_demux is supported */
2668 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2669 return 0;
2670
2671 mailbox = mlx4_alloc_cmd_mailbox(dev);
2672 if (IS_ERR(mailbox)) {
2673 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2674 return -ENOMEM;
2675 }
2676
2677 /* Query mad_demux to find out which MADs are handled by internal sma */
2678 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2679 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2680 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2681 if (err) {
2682 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2683 err);
2684 goto out;
2685 }
2686
2687 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2688
2689 /* Config mad_demux to handle all MADs returned by the query above */
2690 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2691 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2692 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2693 if (err) {
2694 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2695 goto out;
2696 }
2697
2698 if (secure_host_active)
2699 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2700out:
2701 mlx4_free_cmd_mailbox(dev, mailbox);
2702 return err;
2703}
adbc7ac5
SM		 2704
2705/* Access Reg commands */
2706enum mlx4_access_reg_masks {
2707 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2708 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2709 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2710};
2711
2712struct mlx4_access_reg {
2713 __be16 constant1;
2714 u8 status;
2715 u8 resrvd1;
2716 __be16 reg_id;
2717 u8 method;
2718 u8 constant2;
2719 __be32 resrvd2[2];
2720 __be16 len_const;
2721 __be16 resrvd3;
2722#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2723 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2724} __attribute__((__packed__));
2725
2726/**
2727 * mlx4_ACCESS_REG - Generic access reg command.
2728 * @dev: mlx4_dev.
2729 * @reg_id: register ID to access.
2730 * @method: Access method Read/Write.
2731 * @reg_len: register length to Read/Write in bytes.
2732 * @reg_data: reg_data pointer to Read/Write From/To.
2733 *
2734 * Access ConnectX registers FW command.
2735 * Returns 0 on success and copies outbox mlx4_access_reg data
2736 * field into reg_data or a negative error code.
2737 */
2738static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2739 enum mlx4_access_reg_method method,
2740 u16 reg_len, void *reg_data)
2741{
2742 struct mlx4_cmd_mailbox *inbox, *outbox;
2743 struct mlx4_access_reg *inbuf, *outbuf;
2744 int err;
2745
2746 inbox = mlx4_alloc_cmd_mailbox(dev);
2747 if (IS_ERR(inbox))
2748 return PTR_ERR(inbox);
2749
2750 outbox = mlx4_alloc_cmd_mailbox(dev);
2751 if (IS_ERR(outbox)) {
2752 mlx4_free_cmd_mailbox(dev, inbox);
2753 return PTR_ERR(outbox);
2754 }
2755
2756 inbuf = inbox->buf;
2757 outbuf = outbox->buf;
2758
2759 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2760 inbuf->constant2 = 0x1;
2761 inbuf->reg_id = cpu_to_be16(reg_id);
2762 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2763
2764 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2765 inbuf->len_const =
2766 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2767 ((0x3) << 12));
2768
2769 memcpy(inbuf->reg_data, reg_data, reg_len);
2770 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2771 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2772 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2773 if (err)
2774 goto out;
2775
2776 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2777 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2778 mlx4_err(dev,
2779 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2780 reg_id, err);
2781 goto out;
2782 }
2783
2784 memcpy(reg_data, outbuf->reg_data, reg_len);
2785out:
2786 mlx4_free_cmd_mailbox(dev, inbox);
2787 mlx4_free_cmd_mailbox(dev, outbox);
2788 return err;
2789}
2790
2791/* ConnectX registers IDs */
2792enum mlx4_reg_id {
2793 MLX4_REG_ID_PTYS = 0x5004,
2794};
2795
2796/**
2797 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2798 * register
2799 * @dev: mlx4_dev.
2800 * @method: Access method Read/Write.
2801 * @ptys_reg: PTYS register data pointer.
2802 *
2803 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2804 * configuration
2805 * Returns 0 on success or a negative error code.
2806 */
2807int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2808 enum mlx4_access_reg_method method,
2809 struct mlx4_ptys_reg *ptys_reg)
2810{
2811 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2812 method, sizeof(*ptys_reg), ptys_reg);
2813}
2814EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2815
2816int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2817 struct mlx4_vhcr *vhcr,
2818 struct mlx4_cmd_mailbox *inbox,
2819 struct mlx4_cmd_mailbox *outbox,
2820 struct mlx4_cmd_info *cmd)
2821{
2822 struct mlx4_access_reg *inbuf = inbox->buf;
2823 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2824 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2825
2826 if (slave != mlx4_master_func_num(dev) &&
2827 method == MLX4_ACCESS_REG_WRITE)
2828 return -EPERM;
2829
2830 if (reg_id == MLX4_REG_ID_PTYS) {
2831 struct mlx4_ptys_reg *ptys_reg =
2832 (struct mlx4_ptys_reg *)inbuf->reg_data;
2833
2834 ptys_reg->local_port =
2835 mlx4_slave_convert_port(dev, slave,
2836 ptys_reg->local_port);
2837 }
2838
2839 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2840 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2841 MLX4_CMD_NATIVE);
2842}
77fc29c4
HHZ		 2843
2844static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit)
2845{
2846#define SET_PORT_GEN_PHV_VALID 0x10
2847#define SET_PORT_GEN_PHV_EN 0x80
2848
2849 struct mlx4_cmd_mailbox *mailbox;
2850 struct mlx4_set_port_general_context *context;
2851 u32 in_mod;
2852 int err;
2853
2854 mailbox = mlx4_alloc_cmd_mailbox(dev);
2855 if (IS_ERR(mailbox))
2856 return PTR_ERR(mailbox);
2857 context = mailbox->buf;
2858
2859 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID;
2860 if (phv_bit)
2861 context->phv_en |= SET_PORT_GEN_PHV_EN;
2862
2863 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
2864 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
2865 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
2866 MLX4_CMD_NATIVE);
2867
2868 mlx4_free_cmd_mailbox(dev, mailbox);
2869 return err;
2870}
2871
2872int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv)
2873{
2874 int err;
2875 struct mlx4_func_cap func_cap;
2876
2877 memset(&func_cap, 0, sizeof(func_cap));
35e455f4 2878 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap);
77fc29c4
HHZ		 2879 if (!err)
2880 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT;
2881 return err;
2882}
2883EXPORT_SYMBOL(get_phv_bit);
2884
2885int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val)
2886{
2887 int ret;
2888
2889 if (mlx4_is_slave(dev))
2890 return -EPERM;
2891
2892 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2893 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2894 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val);
2895 if (!ret)
2896 dev->caps.phv_bit[port] = new_val;
2897 return ret;
2898 }
2899
2900 return -EOPNOTSUPP;
2901}
2902EXPORT_SYMBOL(set_phv_bit);
2b3ddf27
JM		 2903
2904void mlx4_replace_zero_macs(struct mlx4_dev *dev)
2905{
2906 int i;
2907 u8 mac_addr[ETH_ALEN];
2908
2909 dev->port_random_macs = 0;
2910 for (i = 1; i <= dev->caps.num_ports; ++i)
2911 if (!dev->caps.def_mac[i] &&
2912 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
2913 eth_random_addr(mac_addr);
2914 dev->port_random_macs |= 1 << i;
2915 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr);
2916 }
2917}
2918EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs);
Linux kernel - Deliverables
This page took 1.003654 seconds and 5 git commands to generate.