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mlx4_en: Allow communication between functions on same host
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
ee49bd93 42#include <linux/timer.h>
3142788b 43#include <linux/semaphore.h>
27bf91d6 44#include <linux/workqueue.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
37608eea 47#include <linux/mlx4/driver.h>
225c7b1f 48#include <linux/mlx4/doorbell.h>
623ed84b 49#include <linux/mlx4/cmd.h>
225c7b1f
RD		 50
51#define DRV_NAME "mlx4_core"
e1892fa8
DB		 52#define DRV_VERSION "1.0"
53#define DRV_RELDATE "July 14, 2011"
225c7b1f
RD		 54
55enum {
56 MLX4_HCR_BASE = 0x80680,
57 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 58 MLX4_CLR_INT_SIZE = 0x00008,
59 MLX4_SLAVE_COMM_BASE = 0x0,
60 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 61};
62
225c7b1f 63enum {
0ec2c0f8
EE		 64 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
65 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
66 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 67};
68
225c7b1f
RD		 69enum {
70 MLX4_NUM_PDS = 1 << 15
71};
72
73enum {
74 MLX4_CMPT_TYPE_QP = 0,
75 MLX4_CMPT_TYPE_SRQ = 1,
76 MLX4_CMPT_TYPE_CQ = 2,
77 MLX4_CMPT_TYPE_EQ = 3,
78 MLX4_CMPT_NUM_TYPE
79};
80
81enum {
82 MLX4_CMPT_SHIFT = 24,
83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
84};
85
623ed84b
JM		 86enum mlx4_mr_state {
87 MLX4_MR_DISABLED = 0,
88 MLX4_MR_EN_HW,
89 MLX4_MR_EN_SW
90};
91
92#define MLX4_COMM_TIME 10000
93enum {
94 MLX4_COMM_CMD_RESET,
95 MLX4_COMM_CMD_VHCR0,
96 MLX4_COMM_CMD_VHCR1,
97 MLX4_COMM_CMD_VHCR2,
98 MLX4_COMM_CMD_VHCR_EN,
99 MLX4_COMM_CMD_VHCR_POST,
100 MLX4_COMM_CMD_FLR = 254
101};
102
103/*The flag indicates that the slave should delay the RESET cmd*/
104#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
105/*indicates how many retries will be done if we are in the middle of FLR*/
106#define NUM_OF_RESET_RETRIES 10
107#define SLEEP_TIME_IN_RESET (2 * 1000)
108enum mlx4_resource {
109 RES_QP,
110 RES_CQ,
111 RES_SRQ,
112 RES_XRCD,
113 RES_MPT,
114 RES_MTT,
115 RES_MAC,
116 RES_VLAN,
117 RES_EQ,
118 RES_COUNTER,
119 MLX4_NUM_OF_RESOURCE_TYPE
120};
121
122enum mlx4_alloc_mode {
123 RES_OP_RESERVE,
124 RES_OP_RESERVE_AND_MAP,
125 RES_OP_MAP_ICM,
126};
127
128
129/*
130 *Virtual HCR structures.
131 * mlx4_vhcr is the sw representation, in machine endianess
132 *
133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
134 * to FW to go through communication channel.
135 * It is big endian, and has the same structure as the physical HCR
136 * used by command interface
137 */
138struct mlx4_vhcr {
139 u64 in_param;
140 u64 out_param;
141 u32 in_modifier;
142 u32 errno;
143 u16 op;
144 u16 token;
145 u8 op_modifier;
146 u8 e_bit;
147};
148
149struct mlx4_vhcr_cmd {
150 __be64 in_param;
151 __be32 in_modifier;
152 __be64 out_param;
153 __be16 token;
154 u16 reserved;
155 u8 status;
156 u8 flags;
157 __be16 opcode;
158};
159
160struct mlx4_cmd_info {
161 u16 opcode;
162 bool has_inbox;
163 bool has_outbox;
164 bool out_is_imm;
165 bool encode_slave_id;
166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox);
168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
169 struct mlx4_cmd_mailbox *inbox,
170 struct mlx4_cmd_mailbox *outbox,
171 struct mlx4_cmd_info *cmd);
172};
173
225c7b1f
RD		 174#ifdef CONFIG_MLX4_DEBUG
175extern int mlx4_debug_level;
7b0f5df4
RD		 176#else /* CONFIG_MLX4_DEBUG */
177#define mlx4_debug_level (0)
178#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 179
180#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 181do { \
182 if (mlx4_debug_level) \
183 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
184} while (0)
225c7b1f 185
225c7b1f 186#define mlx4_err(mdev, format, arg...) \
0a645e80 187 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 188#define mlx4_info(mdev, format, arg...) \
0a645e80 189 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 190#define mlx4_warn(mdev, format, arg...) \
0a645e80 191 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 192
0ec2c0f8
EE		 193extern int mlx4_log_num_mgm_entry_size;
194
623ed84b
JM		 195#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
196#define ALL_SLAVES 0xff
197
225c7b1f
RD		 198struct mlx4_bitmap {
199 u32 last;
200 u32 top;
201 u32 max;
93fc9e1b 202 u32 reserved_top;
225c7b1f 203 u32 mask;
42d1e017 204 u32 avail;
225c7b1f
RD		 205 spinlock_t lock;
206 unsigned long *table;
207};
208
209struct mlx4_buddy {
210 unsigned long **bits;
e4044cfc 211 unsigned int *num_free;
225c7b1f
RD		 212 int max_order;
213 spinlock_t lock;
214};
215
216struct mlx4_icm;
217
218struct mlx4_icm_table {
219 u64 virt;
220 int num_icm;
221 int num_obj;
222 int obj_size;
223 int lowmem;
5b0bf5e2 224 int coherent;
225c7b1f
RD		 225 struct mutex mutex;
226 struct mlx4_icm **icm;
227};
228
c82e9aa0
EC		 229/*
230 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
231 */
232struct mlx4_mpt_entry {
233 __be32 flags;
234 __be32 qpn;
235 __be32 key;
236 __be32 pd_flags;
237 __be64 start;
238 __be64 length;
239 __be32 lkey;
240 __be32 win_cnt;
241 u8 reserved1[3];
242 u8 mtt_rep;
243 __be64 mtt_seg;
244 __be32 mtt_sz;
245 __be32 entity_size;
246 __be32 first_byte_offset;
247} __packed;
248
249/*
250 * Must be packed because start is 64 bits but only aligned to 32 bits.
251 */
252struct mlx4_eq_context {
253 __be32 flags;
254 u16 reserved1[3];
255 __be16 page_offset;
256 u8 log_eq_size;
257 u8 reserved2[4];
258 u8 eq_period;
259 u8 reserved3;
260 u8 eq_max_count;
261 u8 reserved4[3];
262 u8 intr;
263 u8 log_page_size;
264 u8 reserved5[2];
265 u8 mtt_base_addr_h;
266 __be32 mtt_base_addr_l;
267 u32 reserved6[2];
268 __be32 consumer_index;
269 __be32 producer_index;
270 u32 reserved7[4];
271};
272
273struct mlx4_cq_context {
274 __be32 flags;
275 u16 reserved1[3];
276 __be16 page_offset;
277 __be32 logsize_usrpage;
278 __be16 cq_period;
279 __be16 cq_max_count;
280 u8 reserved2[3];
281 u8 comp_eqn;
282 u8 log_page_size;
283 u8 reserved3[2];
284 u8 mtt_base_addr_h;
285 __be32 mtt_base_addr_l;
286 __be32 last_notified_index;
287 __be32 solicit_producer_index;
288 __be32 consumer_index;
289 __be32 producer_index;
290 u32 reserved4[2];
291 __be64 db_rec_addr;
292};
293
294struct mlx4_srq_context {
295 __be32 state_logsize_srqn;
296 u8 logstride;
297 u8 reserved1;
298 __be16 xrcd;
299 __be32 pg_offset_cqn;
300 u32 reserved2;
301 u8 log_page_size;
302 u8 reserved3[2];
303 u8 mtt_base_addr_h;
304 __be32 mtt_base_addr_l;
305 __be32 pd;
306 __be16 limit_watermark;
307 __be16 wqe_cnt;
308 u16 reserved4;
309 __be16 wqe_counter;
310 u32 reserved5;
311 __be64 db_rec_addr;
312};
313
623ed84b
JM		 314struct mlx4_eqe {
315 u8 reserved1;
316 u8 type;
317 u8 reserved2;
318 u8 subtype;
319 union {
320 u32 raw[6];
321 struct {
322 __be32 cqn;
323 } __packed comp;
324 struct {
325 u16 reserved1;
326 __be16 token;
327 u32 reserved2;
328 u8 reserved3[3];
329 u8 status;
330 __be64 out_param;
331 } __packed cmd;
332 struct {
333 __be32 qpn;
334 } __packed qp;
335 struct {
336 __be32 srqn;
337 } __packed srq;
338 struct {
339 __be32 cqn;
340 u32 reserved1;
341 u8 reserved2[3];
342 u8 syndrome;
343 } __packed cq_err;
344 struct {
345 u32 reserved1[2];
346 __be32 port;
347 } __packed port_change;
348 struct {
349 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
350 u32 reserved;
351 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
352 } __packed comm_channel_arm;
353 struct {
354 u8 port;
355 u8 reserved[3];
356 __be64 mac;
357 } __packed mac_update;
358 struct {
359 u8 port;
360 } __packed sw_event;
361 struct {
362 __be32 slave_id;
363 } __packed flr_event;
364 } event;
365 u8 slave_id;
366 u8 reserved3[2];
367 u8 owner;
368} __packed;
369
225c7b1f
RD		 370struct mlx4_eq {
371 struct mlx4_dev *dev;
372 void __iomem *doorbell;
373 int eqn;
374 u32 cons_index;
375 u16 irq;
376 u16 have_irq;
377 int nent;
378 struct mlx4_buf_list *page_list;
379 struct mlx4_mtt mtt;
380};
381
623ed84b
JM		 382struct mlx4_slave_eqe {
383 u8 type;
384 u8 port;
385 u32 param;
386};
387
388struct mlx4_slave_event_eq_info {
389 u32 eqn;
390 u16 token;
391 u64 event_type;
392};
393
225c7b1f
RD		 394struct mlx4_profile {
395 int num_qp;
396 int rdmarc_per_qp;
397 int num_srq;
398 int num_cq;
399 int num_mcg;
400 int num_mpt;
401 int num_mtt;
402};
403
404struct mlx4_fw {
405 u64 clr_int_base;
406 u64 catas_offset;
623ed84b 407 u64 comm_base;
225c7b1f
RD		 408 struct mlx4_icm *fw_icm;
409 struct mlx4_icm *aux_icm;
410 u32 catas_size;
411 u16 fw_pages;
412 u8 clr_int_bar;
413 u8 catas_bar;
623ed84b
JM		 414 u8 comm_bar;
415};
416
417struct mlx4_comm {
418 u32 slave_write;
419 u32 slave_read;
225c7b1f
RD		 420};
421
ffe455ad
EE		 422enum {
423 MLX4_MCAST_CONFIG = 0,
424 MLX4_MCAST_DISABLE = 1,
425 MLX4_MCAST_ENABLE = 2,
426};
427
623ed84b
JM		 428#define VLAN_FLTR_SIZE 128
429
430struct mlx4_vlan_fltr {
431 __be32 entry[VLAN_FLTR_SIZE];
432};
433
ffe455ad
EE		 434struct mlx4_mcast_entry {
435 struct list_head list;
436 u64 addr;
437};
438
b12d93d6
YP		 439struct mlx4_promisc_qp {
440 struct list_head list;
441 u32 qpn;
442};
443
444struct mlx4_steer_index {
445 struct list_head list;
446 unsigned int index;
447 struct list_head duplicates;
448};
449
623ed84b
JM		 450struct mlx4_slave_state {
451 u8 comm_toggle;
452 u8 last_cmd;
453 u8 init_port_mask;
454 bool active;
455 u8 function;
456 dma_addr_t vhcr_dma;
457 u16 mtu[MLX4_MAX_PORTS + 1];
458 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
459 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
460 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
461 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_event_eq_info event_eq;
463 u16 eq_pi;
464 u16 eq_ci;
465 spinlock_t lock;
466 /*initialized via the kzalloc*/
467 u8 is_slave_going_down;
468 u32 cookie;
469};
470
471struct slave_list {
472 struct mutex mutex;
473 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
474};
475
476struct mlx4_resource_tracker {
477 spinlock_t lock;
478 /* tree for each resources */
479 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
480 /* num_of_slave's lists, one per slave */
481 struct slave_list *slave_list;
482};
483
484#define SLAVE_EVENT_EQ_SIZE 128
485struct mlx4_slave_event_eq {
486 u32 eqn;
487 u32 cons;
488 u32 prod;
489 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
490};
491
492struct mlx4_master_qp0_state {
493 int proxy_qp0_active;
494 int qp0_active;
495 int port_active;
496};
497
498struct mlx4_mfunc_master_ctx {
499 struct mlx4_slave_state *slave_state;
500 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
501 int init_port_ref[MLX4_MAX_PORTS + 1];
502 u16 max_mtu[MLX4_MAX_PORTS + 1];
503 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
504 struct mlx4_resource_tracker res_tracker;
505 struct workqueue_struct *comm_wq;
506 struct work_struct comm_work;
507 struct work_struct slave_event_work;
508 struct work_struct slave_flr_event_work;
509 spinlock_t slave_state_lock;
f5311ac1 510 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 511 struct mlx4_eqe cmd_eqe;
512 struct mlx4_slave_event_eq slave_eq;
513 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
514};
515
516struct mlx4_mfunc {
517 struct mlx4_comm __iomem *comm;
518 struct mlx4_vhcr_cmd *vhcr;
519 dma_addr_t vhcr_dma;
520
521 struct mlx4_mfunc_master_ctx master;
522};
523
225c7b1f
RD		 524struct mlx4_cmd {
525 struct pci_pool *pool;
526 void __iomem *hcr;
527 struct mutex hcr_mutex;
528 struct semaphore poll_sem;
529 struct semaphore event_sem;
623ed84b 530 struct semaphore slave_sem;
225c7b1f
RD		 531 int max_cmds;
532 spinlock_t context_lock;
533 int free_head;
534 struct mlx4_cmd_context *context;
535 u16 token_mask;
536 u8 use_events;
537 u8 toggle;
623ed84b 538 u8 comm_toggle;
225c7b1f
RD		 539};
540
541struct mlx4_uar_table {
542 struct mlx4_bitmap bitmap;
543};
544
545struct mlx4_mr_table {
546 struct mlx4_bitmap mpt_bitmap;
547 struct mlx4_buddy mtt_buddy;
548 u64 mtt_base;
549 u64 mpt_base;
550 struct mlx4_icm_table mtt_table;
551 struct mlx4_icm_table dmpt_table;
552};
553
554struct mlx4_cq_table {
555 struct mlx4_bitmap bitmap;
556 spinlock_t lock;
557 struct radix_tree_root tree;
558 struct mlx4_icm_table table;
559 struct mlx4_icm_table cmpt_table;
560};
561
562struct mlx4_eq_table {
563 struct mlx4_bitmap bitmap;
b8dd786f 564 char *irq_names;
225c7b1f 565 void __iomem *clr_int;
b8dd786f 566 void __iomem **uar_map;
225c7b1f 567 u32 clr_mask;
b8dd786f 568 struct mlx4_eq *eq;
fa0681d2 569 struct mlx4_icm_table table;
225c7b1f
RD		 570 struct mlx4_icm_table cmpt_table;
571 int have_irq;
572 u8 inta_pin;
573};
574
575struct mlx4_srq_table {
576 struct mlx4_bitmap bitmap;
577 spinlock_t lock;
578 struct radix_tree_root tree;
579 struct mlx4_icm_table table;
580 struct mlx4_icm_table cmpt_table;
581};
582
583struct mlx4_qp_table {
584 struct mlx4_bitmap bitmap;
585 u32 rdmarc_base;
586 int rdmarc_shift;
587 spinlock_t lock;
588 struct mlx4_icm_table qp_table;
589 struct mlx4_icm_table auxc_table;
590 struct mlx4_icm_table altc_table;
591 struct mlx4_icm_table rdmarc_table;
592 struct mlx4_icm_table cmpt_table;
593};
594
595struct mlx4_mcg_table {
596 struct mutex mutex;
597 struct mlx4_bitmap bitmap;
598 struct mlx4_icm_table table;
599};
600
601struct mlx4_catas_err {
602 u32 __iomem *map;
ee49bd93
JM		 603 struct timer_list timer;
604 struct list_head list;
225c7b1f
RD		 605};
606
2a2336f8
YP		 607#define MLX4_MAX_MAC_NUM 128
608#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
609
610struct mlx4_mac_table {
611 __be64 entries[MLX4_MAX_MAC_NUM];
612 int refs[MLX4_MAX_MAC_NUM];
613 struct mutex mutex;
614 int total;
615 int max;
616};
617
618#define MLX4_MAX_VLAN_NUM 128
619#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
620
621struct mlx4_vlan_table {
622 __be32 entries[MLX4_MAX_VLAN_NUM];
623 int refs[MLX4_MAX_VLAN_NUM];
624 struct mutex mutex;
625 int total;
626 int max;
627};
628
ffe455ad
EE		 629#define SET_PORT_GEN_ALL_VALID 0x7
630#define SET_PORT_PROMISC_SHIFT 31
631#define SET_PORT_MC_PROMISC_SHIFT 30
632
633enum {
634 MCAST_DIRECT_ONLY = 0,
635 MCAST_DIRECT = 1,
636 MCAST_DEFAULT = 2
637};
638
639
640struct mlx4_set_port_general_context {
641 u8 reserved[3];
642 u8 flags;
643 u16 reserved2;
644 __be16 mtu;
645 u8 pptx;
646 u8 pfctx;
647 u16 reserved3;
648 u8 pprx;
649 u8 pfcrx;
650 u16 reserved4;
651};
652
653struct mlx4_set_port_rqp_calc_context {
654 __be32 base_qpn;
655 u8 rererved;
656 u8 n_mac;
657 u8 n_vlan;
658 u8 n_prio;
659 u8 reserved2[3];
660 u8 mac_miss;
661 u8 intra_no_vlan;
662 u8 no_vlan;
663 u8 intra_vlan_miss;
664 u8 vlan_miss;
665 u8 reserved3[3];
666 u8 no_vlan_prio;
667 __be32 promisc;
668 __be32 mcast;
669};
670
1679200f
YP		 671struct mlx4_mac_entry {
672 u64 mac;
673};
674
2a2336f8
YP		 675struct mlx4_port_info {
676 struct mlx4_dev *dev;
677 int port;
7ff93f8b
YP		 678 char dev_name[16];
679 struct device_attribute port_attr;
680 enum mlx4_port_type tmp_type;
2a2336f8 681 struct mlx4_mac_table mac_table;
1679200f 682 struct radix_tree_root mac_tree;
2a2336f8 683 struct mlx4_vlan_table vlan_table;
1679200f 684 int base_qpn;
2a2336f8
YP		 685};
686
27bf91d6
YP		 687struct mlx4_sense {
688 struct mlx4_dev *dev;
689 u8 do_sense_port[MLX4_MAX_PORTS + 1];
690 u8 sense_allowed[MLX4_MAX_PORTS + 1];
691 struct delayed_work sense_poll;
692};
693
0b7ca5a9
YP		 694struct mlx4_msix_ctl {
695 u64 pool_bm;
696 spinlock_t pool_lock;
697};
698
b12d93d6
YP		 699struct mlx4_steer {
700 struct list_head promisc_qps[MLX4_NUM_STEERS];
701 struct list_head steer_entries[MLX4_NUM_STEERS];
702 struct list_head high_prios;
703};
704
225c7b1f
RD		 705struct mlx4_priv {
706 struct mlx4_dev dev;
707
708 struct list_head dev_list;
709 struct list_head ctx_list;
710 spinlock_t ctx_lock;
711
6296883c
YP		 712 struct list_head pgdir_list;
713 struct mutex pgdir_mutex;
714
225c7b1f
RD		 715 struct mlx4_fw fw;
716 struct mlx4_cmd cmd;
623ed84b 717 struct mlx4_mfunc mfunc;
225c7b1f
RD		 718
719 struct mlx4_bitmap pd_bitmap;
012a8ff5 720 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 721 struct mlx4_uar_table uar_table;
722 struct mlx4_mr_table mr_table;
723 struct mlx4_cq_table cq_table;
724 struct mlx4_eq_table eq_table;
725 struct mlx4_srq_table srq_table;
726 struct mlx4_qp_table qp_table;
727 struct mlx4_mcg_table mcg_table;
f2a3f6a3 728 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 729
730 struct mlx4_catas_err catas_err;
731
732 void __iomem *clr_base;
733
734 struct mlx4_uar driver_uar;
735 void __iomem *kar;
2a2336f8 736 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 737 struct mlx4_sense sense;
7ff93f8b 738 struct mutex port_mutex;
0b7ca5a9 739 struct mlx4_msix_ctl msix_ctl;
b12d93d6 740 struct mlx4_steer *steer;
c1b43dca
EC		 741 struct list_head bf_list;
742 struct mutex bf_mutex;
743 struct io_mapping *bf_mapping;
ea51b377 744 int reserved_mtts;
225c7b1f
RD		 745};
746
747static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
748{
749 return container_of(dev, struct mlx4_priv, dev);
750}
751
27bf91d6
YP		 752#define MLX4_SENSE_RANGE (HZ * 3)
753
754extern struct workqueue_struct *mlx4_wq;
755
225c7b1f
RD		 756u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
757void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 758u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
759void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 760u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 761int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
762 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 763void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
764
765int mlx4_reset(struct mlx4_dev *dev);
766
b8dd786f
YP		 767int mlx4_alloc_eq_table(struct mlx4_dev *dev);
768void mlx4_free_eq_table(struct mlx4_dev *dev);
769
225c7b1f 770int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 771int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 772int mlx4_init_uar_table(struct mlx4_dev *dev);
773int mlx4_init_mr_table(struct mlx4_dev *dev);
774int mlx4_init_eq_table(struct mlx4_dev *dev);
775int mlx4_init_cq_table(struct mlx4_dev *dev);
776int mlx4_init_qp_table(struct mlx4_dev *dev);
777int mlx4_init_srq_table(struct mlx4_dev *dev);
778int mlx4_init_mcg_table(struct mlx4_dev *dev);
779
780void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 781void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 782void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
783void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
784void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
785void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
786void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
787void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
788void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 789int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
790void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
791int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
792void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
793int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
794void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
795int __mlx4_mr_reserve(struct mlx4_dev *dev);
796void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
797int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
798void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
799u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
800void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 801
623ed84b
JM		 802int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
803 struct mlx4_vhcr *vhcr,
804 struct mlx4_cmd_mailbox *inbox,
805 struct mlx4_cmd_mailbox *outbox,
806 struct mlx4_cmd_info *cmd);
807int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
808 struct mlx4_vhcr *vhcr,
809 struct mlx4_cmd_mailbox *inbox,
810 struct mlx4_cmd_mailbox *outbox,
811 struct mlx4_cmd_info *cmd);
812int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd);
817int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
818 struct mlx4_vhcr *vhcr,
819 struct mlx4_cmd_mailbox *inbox,
820 struct mlx4_cmd_mailbox *outbox,
821 struct mlx4_cmd_info *cmd);
822int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
823 struct mlx4_vhcr *vhcr,
824 struct mlx4_cmd_mailbox *inbox,
825 struct mlx4_cmd_mailbox *outbox,
826 struct mlx4_cmd_info *cmd);
827int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
828 struct mlx4_vhcr *vhcr,
829 struct mlx4_cmd_mailbox *inbox,
830 struct mlx4_cmd_mailbox *outbox,
831 struct mlx4_cmd_info *cmd);
832int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
833 struct mlx4_vhcr *vhcr,
834 struct mlx4_cmd_mailbox *inbox,
835 struct mlx4_cmd_mailbox *outbox,
836 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 837int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
838 int *base);
839void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
840int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
841void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
842int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
843int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
844 int start_index, int npages, u64 *page_list);
623ed84b 845
ee49bd93
JM		 846void mlx4_start_catas_poll(struct mlx4_dev *dev);
847void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 848void mlx4_catas_init(void);
ee49bd93 849int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 850int mlx4_register_device(struct mlx4_dev *dev);
851void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea 852void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f
RD		 853
854struct mlx4_dev_cap;
855struct mlx4_init_hca_param;
856
857u64 mlx4_make_profile(struct mlx4_dev *dev,
858 struct mlx4_profile *request,
859 struct mlx4_dev_cap *dev_cap,
860 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 861void mlx4_master_comm_channel(struct work_struct *work);
862void mlx4_gen_slave_eqe(struct work_struct *work);
863void mlx4_master_handle_slave_flr(struct work_struct *work);
864
865int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
866 struct mlx4_vhcr *vhcr,
867 struct mlx4_cmd_mailbox *inbox,
868 struct mlx4_cmd_mailbox *outbox,
869 struct mlx4_cmd_info *cmd);
870int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
871 struct mlx4_vhcr *vhcr,
872 struct mlx4_cmd_mailbox *inbox,
873 struct mlx4_cmd_mailbox *outbox,
874 struct mlx4_cmd_info *cmd);
875int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
876 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
877 struct mlx4_cmd_mailbox *outbox,
878 struct mlx4_cmd_info *cmd);
879int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
880 struct mlx4_vhcr *vhcr,
881 struct mlx4_cmd_mailbox *inbox,
882 struct mlx4_cmd_mailbox *outbox,
883 struct mlx4_cmd_info *cmd);
884int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
885 struct mlx4_vhcr *vhcr,
886 struct mlx4_cmd_mailbox *inbox,
887 struct mlx4_cmd_mailbox *outbox,
888 struct mlx4_cmd_info *cmd);
889int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
890 struct mlx4_vhcr *vhcr,
891 struct mlx4_cmd_mailbox *inbox,
892 struct mlx4_cmd_mailbox *outbox,
893 struct mlx4_cmd_info *cmd);
894int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
895 struct mlx4_vhcr *vhcr,
896 struct mlx4_cmd_mailbox *inbox,
897 struct mlx4_cmd_mailbox *outbox,
898 struct mlx4_cmd_info *cmd);
899int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
900 struct mlx4_vhcr *vhcr,
901 struct mlx4_cmd_mailbox *inbox,
902 struct mlx4_cmd_mailbox *outbox,
903 struct mlx4_cmd_info *cmd);
904int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr,
906 struct mlx4_cmd_mailbox *inbox,
907 struct mlx4_cmd_mailbox *outbox,
908 struct mlx4_cmd_info *cmd);
909int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
915 struct mlx4_vhcr *vhcr,
916 struct mlx4_cmd_mailbox *inbox,
917 struct mlx4_cmd_mailbox *outbox,
918 struct mlx4_cmd_info *cmd);
919int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
920 struct mlx4_vhcr *vhcr,
921 struct mlx4_cmd_mailbox *inbox,
922 struct mlx4_cmd_mailbox *outbox,
923 struct mlx4_cmd_info *cmd);
924int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
925 struct mlx4_vhcr *vhcr,
926 struct mlx4_cmd_mailbox *inbox,
927 struct mlx4_cmd_mailbox *outbox,
928 struct mlx4_cmd_info *cmd);
929int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
930 struct mlx4_vhcr *vhcr,
931 struct mlx4_cmd_mailbox *inbox,
932 struct mlx4_cmd_mailbox *outbox,
933 struct mlx4_cmd_info *cmd);
934int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
935 struct mlx4_vhcr *vhcr,
936 struct mlx4_cmd_mailbox *inbox,
937 struct mlx4_cmd_mailbox *outbox,
938 struct mlx4_cmd_info *cmd);
939int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
940 struct mlx4_vhcr *vhcr,
941 struct mlx4_cmd_mailbox *inbox,
942 struct mlx4_cmd_mailbox *outbox,
943 struct mlx4_cmd_info *cmd);
944int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
945 struct mlx4_vhcr *vhcr,
946 struct mlx4_cmd_mailbox *inbox,
947 struct mlx4_cmd_mailbox *outbox,
948 struct mlx4_cmd_info *cmd);
949int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
950 struct mlx4_vhcr *vhcr,
951 struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
954
955int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 956
225c7b1f
RD		 957int mlx4_cmd_init(struct mlx4_dev *dev);
958void mlx4_cmd_cleanup(struct mlx4_dev *dev);
959void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
960int mlx4_cmd_use_events(struct mlx4_dev *dev);
961void mlx4_cmd_use_polling(struct mlx4_dev *dev);
962
963void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
964void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
965
966void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
967
968void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
969
970void mlx4_handle_catas_err(struct mlx4_dev *dev);
971
ab6dc30d
YP		 972int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
973 enum mlx4_port_type *type);
27bf91d6
YP		 974void mlx4_do_sense_ports(struct mlx4_dev *dev,
975 enum mlx4_port_type *stype,
976 enum mlx4_port_type *defaults);
977void mlx4_start_sense(struct mlx4_dev *dev);
978void mlx4_stop_sense(struct mlx4_dev *dev);
979void mlx4_sense_init(struct mlx4_dev *dev);
980int mlx4_check_port_params(struct mlx4_dev *dev,
981 enum mlx4_port_type *port_type);
982int mlx4_change_port_types(struct mlx4_dev *dev,
983 enum mlx4_port_type *port_types);
984
2a2336f8
YP		 985void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
986void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
987
7ff93f8b 988int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 989/* resource tracker functions*/
990int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
991 enum mlx4_resource resource_type,
992 int resource_id, int *slave);
993void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
994int mlx4_init_resource_tracker(struct mlx4_dev *dev);
995
996void mlx4_free_resource_tracker(struct mlx4_dev *dev);
997
998int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
1003int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
9a5aa622 1018int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
97285b78 1019int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
7ff93f8b 1020
623ed84b
JM		 1021
1022int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027
1028int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1029 struct mlx4_vhcr *vhcr,
1030 struct mlx4_cmd_mailbox *inbox,
1031 struct mlx4_cmd_mailbox *outbox,
1032 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1033int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1034 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1035int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1036 int block_mcast_loopback, enum mlx4_protocol prot,
1037 enum mlx4_steer_type steer);
623ed84b
JM		 1038int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1039 struct mlx4_vhcr *vhcr,
1040 struct mlx4_cmd_mailbox *inbox,
1041 struct mlx4_cmd_mailbox *outbox,
1042 struct mlx4_cmd_info *cmd);
1043int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
1048int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1049 int port, void *buf);
1050int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1051 struct mlx4_cmd_mailbox *outbox);
1052int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
f5311ac1 1067
0ec2c0f8
EE		 1068int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1069int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1070
5cc914f1
MA		 1071static inline void set_param_l(u64 *arg, u32 val)
1072{
1073 *((u32 *)arg) = val;
1074}
1075
1076static inline void set_param_h(u64 *arg, u32 val)
1077{
1078 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1079}
1080
1081static inline u32 get_param_l(u64 *arg)
1082{
1083 return (u32) (*arg & 0xffffffff);
1084}
1085
1086static inline u32 get_param_h(u64 *arg)
1087{
1088 return (u32)(*arg >> 32);
1089}
1090
c82e9aa0
EC		 1091static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1092{
1093 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1094}
1095
f5311ac1
JM		 1096#define NOT_MASKED_PD_BITS 17
1097
225c7b1f 1098#endif /* MLX4_H */
Linux kernel - Deliverables
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