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net/mlx5e: Expand WQE stride when CQE compression is enabled
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
35static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
37{
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45 "%d.%d.%d",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
49}
50
51static const struct {
52 u32 supported;
53 u32 advertised;
54 u32 speed;
55} ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER] = {
56 [MLX5E_1000BASE_CX_SGMII] = {
57 .supported = SUPPORTED_1000baseKX_Full,
58 .advertised = ADVERTISED_1000baseKX_Full,
59 .speed = 1000,
60 },
61 [MLX5E_1000BASE_KX] = {
62 .supported = SUPPORTED_1000baseKX_Full,
63 .advertised = ADVERTISED_1000baseKX_Full,
64 .speed = 1000,
65 },
66 [MLX5E_10GBASE_CX4] = {
67 .supported = SUPPORTED_10000baseKX4_Full,
68 .advertised = ADVERTISED_10000baseKX4_Full,
69 .speed = 10000,
70 },
71 [MLX5E_10GBASE_KX4] = {
72 .supported = SUPPORTED_10000baseKX4_Full,
73 .advertised = ADVERTISED_10000baseKX4_Full,
74 .speed = 10000,
75 },
76 [MLX5E_10GBASE_KR] = {
77 .supported = SUPPORTED_10000baseKR_Full,
78 .advertised = ADVERTISED_10000baseKR_Full,
79 .speed = 10000,
80 },
81 [MLX5E_20GBASE_KR2] = {
82 .supported = SUPPORTED_20000baseKR2_Full,
83 .advertised = ADVERTISED_20000baseKR2_Full,
84 .speed = 20000,
85 },
86 [MLX5E_40GBASE_CR4] = {
87 .supported = SUPPORTED_40000baseCR4_Full,
88 .advertised = ADVERTISED_40000baseCR4_Full,
89 .speed = 40000,
90 },
91 [MLX5E_40GBASE_KR4] = {
92 .supported = SUPPORTED_40000baseKR4_Full,
93 .advertised = ADVERTISED_40000baseKR4_Full,
94 .speed = 40000,
95 },
96 [MLX5E_56GBASE_R4] = {
97 .supported = SUPPORTED_56000baseKR4_Full,
98 .advertised = ADVERTISED_56000baseKR4_Full,
99 .speed = 56000,
100 },
101 [MLX5E_10GBASE_CR] = {
102 .supported = SUPPORTED_10000baseKR_Full,
103 .advertised = ADVERTISED_10000baseKR_Full,
104 .speed = 10000,
105 },
106 [MLX5E_10GBASE_SR] = {
107 .supported = SUPPORTED_10000baseKR_Full,
108 .advertised = ADVERTISED_10000baseKR_Full,
109 .speed = 10000,
110 },
111 [MLX5E_10GBASE_ER] = {
112 .supported = SUPPORTED_10000baseKR_Full,
113 .advertised = ADVERTISED_10000baseKR_Full,
114 .speed = 10000,
115 },
116 [MLX5E_40GBASE_SR4] = {
117 .supported = SUPPORTED_40000baseSR4_Full,
118 .advertised = ADVERTISED_40000baseSR4_Full,
119 .speed = 40000,
120 },
121 [MLX5E_40GBASE_LR4] = {
122 .supported = SUPPORTED_40000baseLR4_Full,
123 .advertised = ADVERTISED_40000baseLR4_Full,
124 .speed = 40000,
125 },
126 [MLX5E_100GBASE_CR4] = {
127 .speed = 100000,
128 },
129 [MLX5E_100GBASE_SR4] = {
130 .speed = 100000,
131 },
132 [MLX5E_100GBASE_KR4] = {
133 .speed = 100000,
134 },
135 [MLX5E_100GBASE_LR4] = {
136 .speed = 100000,
137 },
138 [MLX5E_100BASE_TX] = {
139 .speed = 100,
140 },
6e4c2189
RS		 141 [MLX5E_1000BASE_T] = {
142 .supported = SUPPORTED_1000baseT_Full,
143 .advertised = ADVERTISED_1000baseT_Full,
144 .speed = 1000,
f62b8bb8
AV		 145 },
146 [MLX5E_10GBASE_T] = {
147 .supported = SUPPORTED_10000baseT_Full,
148 .advertised = ADVERTISED_10000baseT_Full,
149 .speed = 1000,
150 },
151 [MLX5E_25GBASE_CR] = {
152 .speed = 25000,
153 },
154 [MLX5E_25GBASE_KR] = {
155 .speed = 25000,
156 },
157 [MLX5E_25GBASE_SR] = {
158 .speed = 25000,
159 },
160 [MLX5E_50GBASE_CR2] = {
161 .speed = 50000,
162 },
163 [MLX5E_50GBASE_KR2] = {
164 .speed = 50000,
165 },
166};
167
cf678570
GP		 168static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
169{
170 struct mlx5_core_dev *mdev = priv->mdev;
171 u8 pfc_en_tx;
172 u8 pfc_en_rx;
173 int err;
174
175 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
176
177 return err ? 0 : pfc_en_tx | pfc_en_rx;
178}
179
593cf338 180#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
9218b44d
GP		 181#define MLX5E_NUM_RQ_STATS(priv) \
182 (NUM_RQ_STATS * priv->params.num_channels * \
183 test_bit(MLX5E_STATE_OPENED, &priv->state))
184#define MLX5E_NUM_SQ_STATS(priv) \
185 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
186 test_bit(MLX5E_STATE_OPENED, &priv->state))
cf678570 187#define MLX5E_NUM_PFC_COUNTERS(priv) hweight8(mlx5e_query_pfc_combined(priv))
593cf338 188
f62b8bb8
AV		 189static int mlx5e_get_sset_count(struct net_device *dev, int sset)
190{
191 struct mlx5e_priv *priv = netdev_priv(dev);
192
193 switch (sset) {
194 case ETH_SS_STATS:
9218b44d 195 return NUM_SW_COUNTERS +
593cf338 196 MLX5E_NUM_Q_CNTRS(priv) +
9218b44d
GP		 197 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
198 MLX5E_NUM_RQ_STATS(priv) +
cf678570
GP		 199 MLX5E_NUM_SQ_STATS(priv) +
200 MLX5E_NUM_PFC_COUNTERS(priv);
f62b8bb8
AV		 201 /* fallthrough */
202 default:
203 return -EOPNOTSUPP;
204 }
205}
206
9218b44d
GP		 207static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
208{
cf678570
GP		 209 int i, j, tc, prio, idx = 0;
210 unsigned long pfc_combined;
9218b44d
GP		 211
212 /* SW counters */
213 for (i = 0; i < NUM_SW_COUNTERS; i++)
214 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].name);
215
216 /* Q counters */
217 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
218 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].name);
219
220 /* VPORT counters */
221 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
222 strcpy(data + (idx++) * ETH_GSTRING_LEN,
223 vport_stats_desc[i].name);
224
225 /* PPORT counters */
226 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
227 strcpy(data + (idx++) * ETH_GSTRING_LEN,
228 pport_802_3_stats_desc[i].name);
229
230 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
231 strcpy(data + (idx++) * ETH_GSTRING_LEN,
232 pport_2863_stats_desc[i].name);
233
234 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
235 strcpy(data + (idx++) * ETH_GSTRING_LEN,
236 pport_2819_stats_desc[i].name);
237
cf678570
GP		 238 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
239 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
240 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
241 prio,
242 pport_per_prio_traffic_stats_desc[i].name);
243 }
244
245 pfc_combined = mlx5e_query_pfc_combined(priv);
246 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
247 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
248 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
249 prio, pport_per_prio_pfc_stats_desc[i].name);
250 }
251 }
252
9218b44d
GP		 253 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
254 return;
255
256 /* per channel counters */
257 for (i = 0; i < priv->params.num_channels; i++)
258 for (j = 0; j < NUM_RQ_STATS; j++)
259 sprintf(data + (idx++) * ETH_GSTRING_LEN, "rx%d_%s", i,
260 rq_stats_desc[j].name);
261
262 for (tc = 0; tc < priv->params.num_tc; tc++)
263 for (i = 0; i < priv->params.num_channels; i++)
264 for (j = 0; j < NUM_SQ_STATS; j++)
265 sprintf(data + (idx++) * ETH_GSTRING_LEN,
266 "tx%d_%s",
267 priv->channeltc_to_txq_map[i][tc],
268 sq_stats_desc[j].name);
269}
270
f62b8bb8
AV		 271static void mlx5e_get_strings(struct net_device *dev,
272 uint32_t stringset, uint8_t *data)
273{
f62b8bb8
AV		 274 struct mlx5e_priv *priv = netdev_priv(dev);
275
276 switch (stringset) {
277 case ETH_SS_PRIV_FLAGS:
278 break;
279
280 case ETH_SS_TEST:
281 break;
282
283 case ETH_SS_STATS:
9218b44d 284 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 285 break;
286 }
287}
288
289static void mlx5e_get_ethtool_stats(struct net_device *dev,
290 struct ethtool_stats *stats, u64 *data)
291{
292 struct mlx5e_priv *priv = netdev_priv(dev);
cf678570
GP		 293 int i, j, tc, prio, idx = 0;
294 unsigned long pfc_combined;
f62b8bb8
AV		 295
296 if (!data)
297 return;
298
299 mutex_lock(&priv->state_lock);
300 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
301 mlx5e_update_stats(priv);
302 mutex_unlock(&priv->state_lock);
303
9218b44d
GP		 304 for (i = 0; i < NUM_SW_COUNTERS; i++)
305 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
306 sw_stats_desc, i);
f62b8bb8 307
593cf338 308 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 309 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
310 q_stats_desc, i);
311
312 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
313 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
314 vport_stats_desc, i);
593cf338 315
9218b44d
GP		 316 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
317 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
318 pport_802_3_stats_desc, i);
319
320 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
321 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
322 pport_2863_stats_desc, i);
323
324 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
325 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
326 pport_2819_stats_desc, i);
327
cf678570
GP		 328 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
329 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
330 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
331 pport_per_prio_traffic_stats_desc, i);
332 }
333
334 pfc_combined = mlx5e_query_pfc_combined(priv);
335 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
336 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
337 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
338 pport_per_prio_pfc_stats_desc, i);
339 }
340 }
341
9218b44d
GP		 342 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
343 return;
efea389d 344
f62b8bb8
AV		 345 /* per channel counters */
346 for (i = 0; i < priv->params.num_channels; i++)
347 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d
GP		 348 data[idx++] =
349 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
350 rq_stats_desc, j);
f62b8bb8 351
3b619524
TT		 352 for (tc = 0; tc < priv->params.num_tc; tc++)
353 for (i = 0; i < priv->params.num_channels; i++)
f62b8bb8 354 for (j = 0; j < NUM_SQ_STATS; j++)
9218b44d
GP		 355 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
356 sq_stats_desc, j);
f62b8bb8
AV		 357}
358
359static void mlx5e_get_ringparam(struct net_device *dev,
360 struct ethtool_ringparam *param)
361{
362 struct mlx5e_priv *priv = netdev_priv(dev);
461017cb 363 int rq_wq_type = priv->params.rq_wq_type;
f62b8bb8 364
461017cb 365 param->rx_max_pending = 1 << mlx5_max_log_rq_size(rq_wq_type);
f62b8bb8
AV		 366 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
367 param->rx_pending = 1 << priv->params.log_rq_size;
368 param->tx_pending = 1 << priv->params.log_sq_size;
369}
370
371static int mlx5e_set_ringparam(struct net_device *dev,
372 struct ethtool_ringparam *param)
373{
374 struct mlx5e_priv *priv = netdev_priv(dev);
98e81b0a 375 bool was_opened;
461017cb 376 int rq_wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 377 u16 min_rx_wqes;
378 u8 log_rq_size;
379 u8 log_sq_size;
380 int err = 0;
381
382 if (param->rx_jumbo_pending) {
383 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
384 __func__);
385 return -EINVAL;
386 }
387 if (param->rx_mini_pending) {
388 netdev_info(dev, "%s: rx_mini_pending not supported\n",
389 __func__);
390 return -EINVAL;
391 }
461017cb 392 if (param->rx_pending < (1 << mlx5_min_log_rq_size(rq_wq_type))) {
f62b8bb8
AV		 393 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
394 __func__, param->rx_pending,
461017cb 395 1 << mlx5_min_log_rq_size(rq_wq_type));
f62b8bb8
AV		 396 return -EINVAL;
397 }
461017cb 398 if (param->rx_pending > (1 << mlx5_max_log_rq_size(rq_wq_type))) {
f62b8bb8
AV		 399 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
400 __func__, param->rx_pending,
461017cb 401 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8
AV		 402 return -EINVAL;
403 }
404 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
405 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
406 __func__, param->tx_pending,
407 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
408 return -EINVAL;
409 }
410 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
411 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
412 __func__, param->tx_pending,
413 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
414 return -EINVAL;
415 }
416
417 log_rq_size = order_base_2(param->rx_pending);
418 log_sq_size = order_base_2(param->tx_pending);
461017cb 419 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, param->rx_pending);
f62b8bb8
AV		 420
421 if (log_rq_size == priv->params.log_rq_size &&
422 log_sq_size == priv->params.log_sq_size &&
423 min_rx_wqes == priv->params.min_rx_wqes)
424 return 0;
425
426 mutex_lock(&priv->state_lock);
98e81b0a
AS		 427
428 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
429 if (was_opened)
430 mlx5e_close_locked(dev);
431
432 priv->params.log_rq_size = log_rq_size;
433 priv->params.log_sq_size = log_sq_size;
434 priv->params.min_rx_wqes = min_rx_wqes;
435
436 if (was_opened)
437 err = mlx5e_open_locked(dev);
438
f62b8bb8
AV		 439 mutex_unlock(&priv->state_lock);
440
441 return err;
442}
443
444static void mlx5e_get_channels(struct net_device *dev,
445 struct ethtool_channels *ch)
446{
447 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 448
3435ab59 449 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 450 ch->combined_count = priv->params.num_channels;
451}
452
453static int mlx5e_set_channels(struct net_device *dev,
454 struct ethtool_channels *ch)
455{
456 struct mlx5e_priv *priv = netdev_priv(dev);
3435ab59 457 int ncv = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8 458 unsigned int count = ch->combined_count;
45bf454a 459 bool arfs_enabled;
98e81b0a 460 bool was_opened;
f62b8bb8
AV		 461 int err = 0;
462
463 if (!count) {
464 netdev_info(dev, "%s: combined_count=0 not supported\n",
465 __func__);
466 return -EINVAL;
467 }
468 if (ch->rx_count || ch->tx_count) {
469 netdev_info(dev, "%s: separate rx/tx count not supported\n",
470 __func__);
471 return -EINVAL;
472 }
473 if (count > ncv) {
474 netdev_info(dev, "%s: count (%d) > max (%d)\n",
475 __func__, count, ncv);
476 return -EINVAL;
477 }
478
479 if (priv->params.num_channels == count)
480 return 0;
481
482 mutex_lock(&priv->state_lock);
98e81b0a
AS		 483
484 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
485 if (was_opened)
486 mlx5e_close_locked(dev);
487
45bf454a
MG		 488 arfs_enabled = dev->features & NETIF_F_NTUPLE;
489 if (arfs_enabled)
490 mlx5e_arfs_disable(priv);
491
98e81b0a 492 priv->params.num_channels = count;
d8c9660d 493 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
85082dba 494 MLX5E_INDIR_RQT_SIZE, count);
98e81b0a
AS		 495
496 if (was_opened)
497 err = mlx5e_open_locked(dev);
45bf454a
MG		 498 if (err)
499 goto out;
500
501 if (arfs_enabled) {
502 err = mlx5e_arfs_enable(priv);
503 if (err)
504 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
505 __func__, err);
506 }
98e81b0a 507
45bf454a 508out:
f62b8bb8
AV		 509 mutex_unlock(&priv->state_lock);
510
511 return err;
512}
513
514static int mlx5e_get_coalesce(struct net_device *netdev,
515 struct ethtool_coalesce *coal)
516{
517 struct mlx5e_priv *priv = netdev_priv(netdev);
518
7524a5d8
GP		 519 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
520 return -ENOTSUPP;
521
f62b8bb8
AV		 522 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation_usec;
523 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation_pkts;
524 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation_usec;
525 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation_pkts;
526
527 return 0;
528}
529
530static int mlx5e_set_coalesce(struct net_device *netdev,
531 struct ethtool_coalesce *coal)
532{
533 struct mlx5e_priv *priv = netdev_priv(netdev);
534 struct mlx5_core_dev *mdev = priv->mdev;
535 struct mlx5e_channel *c;
536 int tc;
537 int i;
538
7524a5d8
GP		 539 if (!MLX5_CAP_GEN(mdev, cq_moderation))
540 return -ENOTSUPP;
541
2fcb92fb 542 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 543 priv->params.tx_cq_moderation_usec = coal->tx_coalesce_usecs;
544 priv->params.tx_cq_moderation_pkts = coal->tx_max_coalesced_frames;
545 priv->params.rx_cq_moderation_usec = coal->rx_coalesce_usecs;
546 priv->params.rx_cq_moderation_pkts = coal->rx_max_coalesced_frames;
547
2fcb92fb
GP		 548 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
549 goto out;
550
f62b8bb8
AV		 551 for (i = 0; i < priv->params.num_channels; ++i) {
552 c = priv->channel[i];
553
554 for (tc = 0; tc < c->num_tc; tc++) {
555 mlx5_core_modify_cq_moderation(mdev,
556 &c->sq[tc].cq.mcq,
557 coal->tx_coalesce_usecs,
558 coal->tx_max_coalesced_frames);
559 }
560
561 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
562 coal->rx_coalesce_usecs,
563 coal->rx_max_coalesced_frames);
564 }
565
2fcb92fb
GP		 566out:
567 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 568 return 0;
569}
570
571static u32 ptys2ethtool_supported_link(u32 eth_proto_cap)
572{
573 int i;
574 u32 supported_modes = 0;
575
576 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
577 if (eth_proto_cap & MLX5E_PROT_MASK(i))
578 supported_modes |= ptys2ethtool_table[i].supported;
579 }
580 return supported_modes;
581}
582
583static u32 ptys2ethtool_adver_link(u32 eth_proto_cap)
584{
585 int i;
586 u32 advertising_modes = 0;
587
588 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
589 if (eth_proto_cap & MLX5E_PROT_MASK(i))
590 advertising_modes |= ptys2ethtool_table[i].advertised;
591 }
592 return advertising_modes;
593}
594
595static u32 ptys2ethtool_supported_port(u32 eth_proto_cap)
596{
597 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
598 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
599 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
600 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
601 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
602 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
603 return SUPPORTED_FIBRE;
604 }
605
606 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
607 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
608 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
609 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
610 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
611 return SUPPORTED_Backplane;
612 }
613 return 0;
614}
615
616static void get_speed_duplex(struct net_device *netdev,
617 u32 eth_proto_oper,
618 struct ethtool_cmd *cmd)
619{
620 int i;
621 u32 speed = SPEED_UNKNOWN;
622 u8 duplex = DUPLEX_UNKNOWN;
623
624 if (!netif_carrier_ok(netdev))
625 goto out;
626
627 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
628 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
629 speed = ptys2ethtool_table[i].speed;
630 duplex = DUPLEX_FULL;
631 break;
632 }
633 }
634out:
635 ethtool_cmd_speed_set(cmd, speed);
636 cmd->duplex = duplex;
637}
638
639static void get_supported(u32 eth_proto_cap, u32 *supported)
640{
641 *supported |= ptys2ethtool_supported_port(eth_proto_cap);
642 *supported |= ptys2ethtool_supported_link(eth_proto_cap);
643 *supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
644}
645
646static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
647 u8 rx_pause, u32 *advertising)
648{
649 *advertising |= ptys2ethtool_adver_link(eth_proto_cap);
650 *advertising |= tx_pause ? ADVERTISED_Pause : 0;
651 *advertising |= (tx_pause ^ rx_pause) ? ADVERTISED_Asym_Pause : 0;
652}
653
654static u8 get_connector_port(u32 eth_proto)
655{
656 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
657 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
658 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
659 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
660 return PORT_FIBRE;
661 }
662
663 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
664 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
665 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
666 return PORT_DA;
667 }
668
669 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
670 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
671 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
672 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
673 return PORT_NONE;
674 }
675
676 return PORT_OTHER;
677}
678
679static void get_lp_advertising(u32 eth_proto_lp, u32 *lp_advertising)
680{
681 *lp_advertising = ptys2ethtool_adver_link(eth_proto_lp);
682}
683
684static int mlx5e_get_settings(struct net_device *netdev,
685 struct ethtool_cmd *cmd)
686{
687 struct mlx5e_priv *priv = netdev_priv(netdev);
688 struct mlx5_core_dev *mdev = priv->mdev;
689 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
690 u32 eth_proto_cap;
691 u32 eth_proto_admin;
692 u32 eth_proto_lp;
693 u32 eth_proto_oper;
694 int err;
695
a05bdefa 696 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 697
698 if (err) {
699 netdev_err(netdev, "%s: query port ptys failed: %d\n",
700 __func__, err);
701 goto err_query_ptys;
702 }
703
704 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
705 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
706 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
707 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
708
709 cmd->supported = 0;
710 cmd->advertising = 0;
711
712 get_supported(eth_proto_cap, &cmd->supported);
713 get_advertising(eth_proto_admin, 0, 0, &cmd->advertising);
714 get_speed_duplex(netdev, eth_proto_oper, cmd);
715
716 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
717
718 cmd->port = get_connector_port(eth_proto_oper);
719 get_lp_advertising(eth_proto_lp, &cmd->lp_advertising);
720
721 cmd->transceiver = XCVR_INTERNAL;
722
723err_query_ptys:
724 return err;
725}
726
727static u32 mlx5e_ethtool2ptys_adver_link(u32 link_modes)
728{
729 u32 i, ptys_modes = 0;
730
731 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
732 if (ptys2ethtool_table[i].advertised & link_modes)
733 ptys_modes |= MLX5E_PROT_MASK(i);
734 }
735
736 return ptys_modes;
737}
738
739static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
740{
741 u32 i, speed_links = 0;
742
743 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
744 if (ptys2ethtool_table[i].speed == speed)
745 speed_links |= MLX5E_PROT_MASK(i);
746 }
747
748 return speed_links;
749}
750
751static int mlx5e_set_settings(struct net_device *netdev,
752 struct ethtool_cmd *cmd)
753{
754 struct mlx5e_priv *priv = netdev_priv(netdev);
755 struct mlx5_core_dev *mdev = priv->mdev;
756 u32 link_modes;
757 u32 speed;
758 u32 eth_proto_cap, eth_proto_admin;
6fa1bcab 759 enum mlx5_port_status ps;
f62b8bb8
AV		 760 int err;
761
762 speed = ethtool_cmd_speed(cmd);
763
764 link_modes = cmd->autoneg == AUTONEG_ENABLE ?
765 mlx5e_ethtool2ptys_adver_link(cmd->advertising) :
766 mlx5e_ethtool2ptys_speed_link(speed);
767
768 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
769 if (err) {
770 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
771 __func__, err);
772 goto out;
773 }
774
775 link_modes = link_modes & eth_proto_cap;
776 if (!link_modes) {
777 netdev_err(netdev, "%s: Not supported link mode(s) requested",
778 __func__);
779 err = -EINVAL;
780 goto out;
781 }
782
783 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
784 if (err) {
785 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
786 __func__, err);
787 goto out;
788 }
789
790 if (link_modes == eth_proto_admin)
791 goto out;
792
6fa1bcab
AS		 793 mlx5_query_port_admin_status(mdev, &ps);
794 if (ps == MLX5_PORT_UP)
795 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
796 mlx5_set_port_proto(mdev, link_modes, MLX5_PTYS_EN);
797 if (ps == MLX5_PORT_UP)
798 mlx5_set_port_admin_status(mdev, MLX5_PORT_UP);
f62b8bb8 799
f62b8bb8
AV		 800out:
801 return err;
802}
803
2d75b2bc
AS		 804static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
805{
806 struct mlx5e_priv *priv = netdev_priv(netdev);
807
808 return sizeof(priv->params.toeplitz_hash_key);
809}
810
811static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
812{
813 return MLX5E_INDIR_RQT_SIZE;
814}
815
2be6967c
SM		 816static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
817 u8 *hfunc)
818{
819 struct mlx5e_priv *priv = netdev_priv(netdev);
820
2d75b2bc
AS		 821 if (indir)
822 memcpy(indir, priv->params.indirection_rqt,
823 sizeof(priv->params.indirection_rqt));
824
825 if (key)
826 memcpy(key, priv->params.toeplitz_hash_key,
827 sizeof(priv->params.toeplitz_hash_key));
828
2be6967c
SM		 829 if (hfunc)
830 *hfunc = priv->params.rss_hfunc;
831
832 return 0;
833}
834
bdfc028d
TT		 835static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
836{
837 struct mlx5_core_dev *mdev = priv->mdev;
838 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
839 int i;
840
841 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
842 mlx5e_build_tir_ctx_hash(tirc, priv);
843
1da36696
TT		 844 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
845 mlx5_core_modify_tir(mdev, priv->indir_tirn[i], in, inlen);
bdfc028d
TT		 846}
847
98e81b0a 848static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 849 const u8 *key, const u8 hfunc)
850{
98e81b0a 851 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d
TT		 852 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
853 void *in;
2be6967c 854
2d75b2bc
AS		 855 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
856 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 857 (hfunc != ETH_RSS_HASH_TOP))
858 return -EINVAL;
859
bdfc028d
TT		 860 in = mlx5_vzalloc(inlen);
861 if (!in)
862 return -ENOMEM;
863
2be6967c
SM		 864 mutex_lock(&priv->state_lock);
865
2d75b2bc 866 if (indir) {
1da36696
TT		 867 u32 rqtn = priv->indir_rqtn;
868
2d75b2bc
AS		 869 memcpy(priv->params.indirection_rqt, indir,
870 sizeof(priv->params.indirection_rqt));
1da36696 871 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2be6967c
SM		 872 }
873
2d75b2bc
AS		 874 if (key)
875 memcpy(priv->params.toeplitz_hash_key, key,
876 sizeof(priv->params.toeplitz_hash_key));
877
878 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
879 priv->params.rss_hfunc = hfunc;
880
bdfc028d 881 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 882
2be6967c
SM		 883 mutex_unlock(&priv->state_lock);
884
bdfc028d
TT		 885 kvfree(in);
886
887 return 0;
2be6967c
SM		 888}
889
2d75b2bc
AS		 890static int mlx5e_get_rxnfc(struct net_device *netdev,
891 struct ethtool_rxnfc *info, u32 *rule_locs)
892{
893 struct mlx5e_priv *priv = netdev_priv(netdev);
894 int err = 0;
895
896 switch (info->cmd) {
897 case ETHTOOL_GRXRINGS:
898 info->data = priv->params.num_channels;
899 break;
900 default:
901 err = -EOPNOTSUPP;
902 break;
903 }
904
905 return err;
906}
907
58d52291
AS		 908static int mlx5e_get_tunable(struct net_device *dev,
909 const struct ethtool_tunable *tuna,
910 void *data)
911{
912 const struct mlx5e_priv *priv = netdev_priv(dev);
913 int err = 0;
914
915 switch (tuna->id) {
916 case ETHTOOL_TX_COPYBREAK:
917 *(u32 *)data = priv->params.tx_max_inline;
918 break;
919 default:
920 err = -EINVAL;
921 break;
922 }
923
924 return err;
925}
926
927static int mlx5e_set_tunable(struct net_device *dev,
928 const struct ethtool_tunable *tuna,
929 const void *data)
930{
931 struct mlx5e_priv *priv = netdev_priv(dev);
932 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 933 bool was_opened;
58d52291
AS		 934 u32 val;
935 int err = 0;
936
937 switch (tuna->id) {
938 case ETHTOOL_TX_COPYBREAK:
939 val = *(u32 *)data;
940 if (val > mlx5e_get_max_inline_cap(mdev)) {
941 err = -EINVAL;
942 break;
943 }
944
945 mutex_lock(&priv->state_lock);
98e81b0a
AS		 946
947 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
948 if (was_opened)
949 mlx5e_close_locked(dev);
950
951 priv->params.tx_max_inline = val;
952
953 if (was_opened)
954 err = mlx5e_open_locked(dev);
955
58d52291
AS		 956 mutex_unlock(&priv->state_lock);
957 break;
958 default:
959 err = -EINVAL;
960 break;
961 }
962
963 return err;
964}
965
3c2d18ef
AS		 966static void mlx5e_get_pauseparam(struct net_device *netdev,
967 struct ethtool_pauseparam *pauseparam)
968{
969 struct mlx5e_priv *priv = netdev_priv(netdev);
970 struct mlx5_core_dev *mdev = priv->mdev;
971 int err;
972
973 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
974 &pauseparam->tx_pause);
975 if (err) {
976 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
977 __func__, err);
978 }
979}
980
981static int mlx5e_set_pauseparam(struct net_device *netdev,
982 struct ethtool_pauseparam *pauseparam)
983{
984 struct mlx5e_priv *priv = netdev_priv(netdev);
985 struct mlx5_core_dev *mdev = priv->mdev;
986 int err;
987
988 if (pauseparam->autoneg)
989 return -EINVAL;
990
991 err = mlx5_set_port_pause(mdev,
992 pauseparam->rx_pause ? 1 : 0,
993 pauseparam->tx_pause ? 1 : 0);
994 if (err) {
995 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
996 __func__, err);
997 }
998
999 return err;
1000}
1001
ef9814de
EBE		 1002static int mlx5e_get_ts_info(struct net_device *dev,
1003 struct ethtool_ts_info *info)
1004{
1005 struct mlx5e_priv *priv = netdev_priv(dev);
1006 int ret;
1007
1008 ret = ethtool_op_get_ts_info(dev, info);
1009 if (ret)
1010 return ret;
1011
3d8c38af
EBE		 1012 info->phc_index = priv->tstamp.ptp ?
1013 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1014
1015 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1016 return 0;
1017
1018 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1019 SOF_TIMESTAMPING_RX_HARDWARE |
1020 SOF_TIMESTAMPING_RAW_HARDWARE;
1021
1022 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1023 (BIT(1) << HWTSTAMP_TX_ON);
1024
1025 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1026 (BIT(1) << HWTSTAMP_FILTER_ALL);
1027
1028 return 0;
1029}
1030
928cfe87
TT		 1031static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1032{
1033 __u32 ret = 0;
1034
1035 if (MLX5_CAP_GEN(mdev, wol_g))
1036 ret |= WAKE_MAGIC;
1037
1038 if (MLX5_CAP_GEN(mdev, wol_s))
1039 ret |= WAKE_MAGICSECURE;
1040
1041 if (MLX5_CAP_GEN(mdev, wol_a))
1042 ret |= WAKE_ARP;
1043
1044 if (MLX5_CAP_GEN(mdev, wol_b))
1045 ret |= WAKE_BCAST;
1046
1047 if (MLX5_CAP_GEN(mdev, wol_m))
1048 ret |= WAKE_MCAST;
1049
1050 if (MLX5_CAP_GEN(mdev, wol_u))
1051 ret |= WAKE_UCAST;
1052
1053 if (MLX5_CAP_GEN(mdev, wol_p))
1054 ret |= WAKE_PHY;
1055
1056 return ret;
1057}
1058
1059static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1060{
1061 __u32 ret = 0;
1062
1063 if (mode & MLX5_WOL_MAGIC)
1064 ret |= WAKE_MAGIC;
1065
1066 if (mode & MLX5_WOL_SECURED_MAGIC)
1067 ret |= WAKE_MAGICSECURE;
1068
1069 if (mode & MLX5_WOL_ARP)
1070 ret |= WAKE_ARP;
1071
1072 if (mode & MLX5_WOL_BROADCAST)
1073 ret |= WAKE_BCAST;
1074
1075 if (mode & MLX5_WOL_MULTICAST)
1076 ret |= WAKE_MCAST;
1077
1078 if (mode & MLX5_WOL_UNICAST)
1079 ret |= WAKE_UCAST;
1080
1081 if (mode & MLX5_WOL_PHY_ACTIVITY)
1082 ret |= WAKE_PHY;
1083
1084 return ret;
1085}
1086
1087static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1088{
1089 u8 ret = 0;
1090
1091 if (mode & WAKE_MAGIC)
1092 ret |= MLX5_WOL_MAGIC;
1093
1094 if (mode & WAKE_MAGICSECURE)
1095 ret |= MLX5_WOL_SECURED_MAGIC;
1096
1097 if (mode & WAKE_ARP)
1098 ret |= MLX5_WOL_ARP;
1099
1100 if (mode & WAKE_BCAST)
1101 ret |= MLX5_WOL_BROADCAST;
1102
1103 if (mode & WAKE_MCAST)
1104 ret |= MLX5_WOL_MULTICAST;
1105
1106 if (mode & WAKE_UCAST)
1107 ret |= MLX5_WOL_UNICAST;
1108
1109 if (mode & WAKE_PHY)
1110 ret |= MLX5_WOL_PHY_ACTIVITY;
1111
1112 return ret;
1113}
1114
1115static void mlx5e_get_wol(struct net_device *netdev,
1116 struct ethtool_wolinfo *wol)
1117{
1118 struct mlx5e_priv *priv = netdev_priv(netdev);
1119 struct mlx5_core_dev *mdev = priv->mdev;
1120 u8 mlx5_wol_mode;
1121 int err;
1122
1123 memset(wol, 0, sizeof(*wol));
1124
1125 wol->supported = mlx5e_get_wol_supported(mdev);
1126 if (!wol->supported)
1127 return;
1128
1129 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1130 if (err)
1131 return;
1132
1133 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1134}
1135
1136static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1137{
1138 struct mlx5e_priv *priv = netdev_priv(netdev);
1139 struct mlx5_core_dev *mdev = priv->mdev;
1140 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1141 u32 mlx5_wol_mode;
1142
1143 if (!wol_supported)
1144 return -ENOTSUPP;
1145
1146 if (wol->wolopts & ~wol_supported)
1147 return -EINVAL;
1148
1149 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1150
1151 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1152}
1153
da54d24e
GP		 1154static int mlx5e_set_phys_id(struct net_device *dev,
1155 enum ethtool_phys_id_state state)
1156{
1157 struct mlx5e_priv *priv = netdev_priv(dev);
1158 struct mlx5_core_dev *mdev = priv->mdev;
1159 u16 beacon_duration;
1160
1161 if (!MLX5_CAP_GEN(mdev, beacon_led))
1162 return -EOPNOTSUPP;
1163
1164 switch (state) {
1165 case ETHTOOL_ID_ACTIVE:
1166 beacon_duration = MLX5_BEACON_DURATION_INF;
1167 break;
1168 case ETHTOOL_ID_INACTIVE:
1169 beacon_duration = MLX5_BEACON_DURATION_OFF;
1170 break;
1171 default:
1172 return -EOPNOTSUPP;
1173 }
1174
1175 return mlx5_set_port_beacon(mdev, beacon_duration);
1176}
1177
bb64143e
GP		 1178static int mlx5e_get_module_info(struct net_device *netdev,
1179 struct ethtool_modinfo *modinfo)
1180{
1181 struct mlx5e_priv *priv = netdev_priv(netdev);
1182 struct mlx5_core_dev *dev = priv->mdev;
1183 int size_read = 0;
1184 u8 data[4];
1185
1186 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1187 if (size_read < 2)
1188 return -EIO;
1189
1190 /* data[0] = identifier byte */
1191 switch (data[0]) {
1192 case MLX5_MODULE_ID_QSFP:
1193 modinfo->type = ETH_MODULE_SFF_8436;
1194 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1195 break;
1196 case MLX5_MODULE_ID_QSFP_PLUS:
1197 case MLX5_MODULE_ID_QSFP28:
1198 /* data[1] = revision id */
1199 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1200 modinfo->type = ETH_MODULE_SFF_8636;
1201 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1202 } else {
1203 modinfo->type = ETH_MODULE_SFF_8436;
1204 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1205 }
1206 break;
1207 case MLX5_MODULE_ID_SFP:
1208 modinfo->type = ETH_MODULE_SFF_8472;
1209 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1210 break;
1211 default:
1212 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1213 __func__, data[0]);
1214 return -EINVAL;
1215 }
1216
1217 return 0;
1218}
1219
1220static int mlx5e_get_module_eeprom(struct net_device *netdev,
1221 struct ethtool_eeprom *ee,
1222 u8 *data)
1223{
1224 struct mlx5e_priv *priv = netdev_priv(netdev);
1225 struct mlx5_core_dev *mdev = priv->mdev;
1226 int offset = ee->offset;
1227 int size_read;
1228 int i = 0;
1229
1230 if (!ee->len)
1231 return -EINVAL;
1232
1233 memset(data, 0, ee->len);
1234
1235 while (i < ee->len) {
1236 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1237 data + i);
1238
1239 if (!size_read)
1240 /* Done reading */
1241 return 0;
1242
1243 if (size_read < 0) {
1244 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1245 __func__, size_read);
1246 return 0;
1247 }
1248
1249 i += size_read;
1250 offset += size_read;
1251 }
1252
1253 return 0;
1254}
1255
f62b8bb8
AV		 1256const struct ethtool_ops mlx5e_ethtool_ops = {
1257 .get_drvinfo = mlx5e_get_drvinfo,
1258 .get_link = ethtool_op_get_link,
1259 .get_strings = mlx5e_get_strings,
1260 .get_sset_count = mlx5e_get_sset_count,
1261 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1262 .get_ringparam = mlx5e_get_ringparam,
1263 .set_ringparam = mlx5e_set_ringparam,
1264 .get_channels = mlx5e_get_channels,
1265 .set_channels = mlx5e_set_channels,
1266 .get_coalesce = mlx5e_get_coalesce,
1267 .set_coalesce = mlx5e_set_coalesce,
1268 .get_settings = mlx5e_get_settings,
1269 .set_settings = mlx5e_set_settings,
2d75b2bc
AS		 1270 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1271 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1272 .get_rxfh = mlx5e_get_rxfh,
1273 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1274 .get_rxnfc = mlx5e_get_rxnfc,
58d52291
AS		 1275 .get_tunable = mlx5e_get_tunable,
1276 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1277 .get_pauseparam = mlx5e_get_pauseparam,
1278 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1279 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1280 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1281 .get_wol = mlx5e_get_wol,
1282 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1283 .get_module_info = mlx5e_get_module_info,
1284 .get_module_eeprom = mlx5e_get_module_eeprom,
f62b8bb8 1285};
Linux kernel - Deliverables
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