net/mlx5e: Add ethtool counter for TX xmit_more
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.h
CommitLineData
9218b44d
GP
1/*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#ifndef __MLX5_EN_STATS_H__
33#define __MLX5_EN_STATS_H__
34
35#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be64_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
43
44#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
bfe6d8d1
GP
45#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
9218b44d
GP
47
48struct counter_desc {
bfe6d8d1 49 char format[ETH_GSTRING_LEN];
9218b44d
GP
50 int offset; /* Byte offset */
51};
52
53struct mlx5e_sw_stats {
54 u64 rx_packets;
55 u64 rx_bytes;
56 u64 tx_packets;
57 u64 tx_bytes;
bfe6d8d1
GP
58 u64 tx_tso_packets;
59 u64 tx_tso_bytes;
60 u64 tx_tso_inner_packets;
61 u64 tx_tso_inner_bytes;
62 u64 rx_lro_packets;
63 u64 rx_lro_bytes;
64 u64 rx_csum_unnecessary;
9218b44d 65 u64 rx_csum_none;
bfe6d8d1
GP
66 u64 rx_csum_complete;
67 u64 rx_csum_unnecessary_inner;
68 u64 tx_csum_partial;
69 u64 tx_csum_partial_inner;
9218b44d
GP
70 u64 tx_queue_stopped;
71 u64 tx_queue_wake;
72 u64 tx_queue_dropped;
c8cf78fe 73 u64 tx_xmit_more;
9218b44d
GP
74 u64 rx_wqe_err;
75 u64 rx_mpwqe_filler;
76 u64 rx_mpwqe_frag;
77 u64 rx_buff_alloc_err;
7219ab34
TT
78 u64 rx_cqe_compress_blks;
79 u64 rx_cqe_compress_pkts;
121fcdc8
GP
80
81 /* Special handling counters */
bfe6d8d1 82 u64 link_down_events_phy;
9218b44d
GP
83};
84
85static const struct counter_desc sw_stats_desc[] = {
86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
bfe6d8d1
GP
90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
9218b44d 97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
bfe6d8d1
GP
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
9218b44d
GP
102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
c8cf78fe 105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
9218b44d
GP
106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_frag) },
109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
7219ab34
TT
110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
111 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
bfe6d8d1 112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) },
9218b44d
GP
113};
114
115struct mlx5e_qcounter_stats {
116 u32 rx_out_of_buffer;
117};
118
119static const struct counter_desc q_stats_desc[] = {
120 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
121};
122
123#define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
124#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
125 vstats->query_vport_out, c)
126
127struct mlx5e_vport_stats {
128 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
129};
130
131static const struct counter_desc vport_stats_desc[] = {
8075cb72 132 { "rx_vport_unicast_packets",
9218b44d 133 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
8075cb72
GP
134 { "rx_vport_unicast_bytes",
135 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
136 { "tx_vport_unicast_packets",
9218b44d 137 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
8075cb72 138 { "tx_vport_unicast_bytes",
9218b44d 139 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
8075cb72 140 { "rx_vport_multicast_packets",
9218b44d 141 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
8075cb72 142 { "rx_vport_multicast_bytes",
9218b44d 143 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
8075cb72 144 { "tx_vport_multicast_packets",
9218b44d 145 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
8075cb72 146 { "tx_vport_multicast_bytes",
9218b44d 147 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
8075cb72 148 { "rx_vport_broadcast_packets",
9218b44d 149 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
8075cb72 150 { "rx_vport_broadcast_bytes",
9218b44d 151 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
8075cb72 152 { "tx_vport_broadcast_packets",
9218b44d 153 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
8075cb72 154 { "tx_vport_broadcast_bytes",
9218b44d 155 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
fe6b9bd9
GP
156 { "rx_vport_rdma_unicast_packets",
157 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
158 { "rx_vport_rdma_unicast_bytes",
159 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
160 { "tx_vport_rdma_unicast_packets",
161 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
162 { "tx_vport_rdma_unicast_bytes",
163 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
164 { "rx_vport_rdma_multicast_packets",
165 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
166 { "rx_vport_rdma_multicast_bytes",
167 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
168 { "tx_vport_rdma_multicast_packets",
169 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
170 { "tx_vport_rdma_multicast_bytes",
171 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
9218b44d
GP
172};
173
174#define PPORT_802_3_OFF(c) \
175 MLX5_BYTE_OFF(ppcnt_reg, \
176 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
177#define PPORT_802_3_GET(pstats, c) \
178 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
179 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
180#define PPORT_2863_OFF(c) \
181 MLX5_BYTE_OFF(ppcnt_reg, \
182 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
183#define PPORT_2863_GET(pstats, c) \
184 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
185 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
186#define PPORT_2819_OFF(c) \
187 MLX5_BYTE_OFF(ppcnt_reg, \
188 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
189#define PPORT_2819_GET(pstats, c) \
190 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
191 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
cf678570
GP
192#define PPORT_PER_PRIO_OFF(c) \
193 MLX5_BYTE_OFF(ppcnt_reg, \
194 counter_set.eth_per_prio_grp_data_layout.c##_high)
195#define PPORT_PER_PRIO_GET(pstats, prio, c) \
196 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
197 counter_set.eth_per_prio_grp_data_layout.c##_high)
198#define NUM_PPORT_PRIO 8
9218b44d
GP
199
200struct mlx5e_pport_stats {
201 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
202 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
203 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
cf678570 204 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
121fcdc8 205 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
9218b44d
GP
206};
207
208static const struct counter_desc pport_802_3_stats_desc[] = {
bfe6d8d1
GP
209 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
210 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
211 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
212 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
213 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
214 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
215 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
216 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
217 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
218 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
219 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
220 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
221 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
222 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
223 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
224 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
225 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
226 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
9218b44d
GP
227};
228
229static const struct counter_desc pport_2863_stats_desc[] = {
bfe6d8d1
GP
230 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
231 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
232 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
9218b44d
GP
233};
234
235static const struct counter_desc pport_2819_stats_desc[] = {
bfe6d8d1
GP
236 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
237 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
238 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
239 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
240 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
241 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
242 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
243 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
244 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
245 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
246 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
247 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
248 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
9218b44d
GP
249};
250
cf678570 251static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
bfe6d8d1
GP
252 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
253 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
254 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
255 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
cf678570
GP
256};
257
258static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
e989d5a5
GP
259 /* %s is "global" or "prio{i}" */
260 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
261 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
262 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
263 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
264 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
cf678570
GP
265};
266
9218b44d
GP
267struct mlx5e_rq_stats {
268 u64 packets;
269 u64 bytes;
bfe6d8d1
GP
270 u64 csum_complete;
271 u64 csum_unnecessary_inner;
1b223dd3 272 u64 csum_none;
9218b44d
GP
273 u64 lro_packets;
274 u64 lro_bytes;
275 u64 wqe_err;
276 u64 mpwqe_filler;
277 u64 mpwqe_frag;
278 u64 buff_alloc_err;
7219ab34
TT
279 u64 cqe_compress_blks;
280 u64 cqe_compress_pkts;
9218b44d
GP
281};
282
283static const struct counter_desc rq_stats_desc[] = {
bfe6d8d1
GP
284 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
285 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
286 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
287 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
288 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
289 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
290 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
291 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
292 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
293 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_frag) },
294 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
295 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
296 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
9218b44d
GP
297};
298
299struct mlx5e_sq_stats {
300 /* commonly accessed in data path */
301 u64 packets;
302 u64 bytes;
c8cf78fe 303 u64 xmit_more;
9218b44d
GP
304 u64 tso_packets;
305 u64 tso_bytes;
306 u64 tso_inner_packets;
307 u64 tso_inner_bytes;
bfe6d8d1 308 u64 csum_partial_inner;
9218b44d
GP
309 u64 nop;
310 /* less likely accessed in data path */
bfe6d8d1 311 u64 csum_none;
9218b44d
GP
312 u64 stopped;
313 u64 wake;
314 u64 dropped;
315};
316
317static const struct counter_desc sq_stats_desc[] = {
bfe6d8d1
GP
318 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
319 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
320 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
321 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
322 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
323 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
324 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
325 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
326 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
327 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
328 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
329 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
c8cf78fe 330 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
9218b44d
GP
331};
332
333#define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
334#define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
335#define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
336#define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
337#define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
338#define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
cf678570
GP
339#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \
340 ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
341#define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
342 ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
9218b44d
GP
343#define NUM_PPORT_COUNTERS (NUM_PPORT_802_3_COUNTERS + \
344 NUM_PPORT_2863_COUNTERS + \
cf678570
GP
345 NUM_PPORT_2819_COUNTERS + \
346 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \
347 NUM_PPORT_PRIO)
9218b44d
GP
348#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
349#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
350
351struct mlx5e_stats {
352 struct mlx5e_sw_stats sw;
353 struct mlx5e_qcounter_stats qcnt;
354 struct mlx5e_vport_stats vport;
355 struct mlx5e_pport_stats pport;
356};
357
358#endif /* __MLX5_EN_STATS_H__ */
This page took 0.079028 seconds and 5 git commands to generate.