[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tx.c

/*
 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/tcp.h>
#include <linux/if_vlan.h>
#include "en.h"

#define MLX5E_SQ_NOPS_ROOM  MLX5_SEND_WQE_MAX_WQEBBS
#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
			    MLX5E_SQ_NOPS_ROOM)

void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
{
	struct mlx5_wq_cyc                *wq  = &sq->wq;

	u16 pi = sq->pc & wq->sz_m1;
	struct mlx5e_tx_wqe              *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);

	struct mlx5_wqe_ctrl_seg         *cseg = &wqe->ctrl;

	memset(cseg, 0, sizeof(*cseg));

	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | 0x01);

	sq->skb[pi] = NULL;
	sq->pc++;
	sq->stats.nop++;

	if (notify_hw) {
		cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
		mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
	}
}

static inline void mlx5e_tx_dma_unmap(struct device *pdev,
				      struct mlx5e_sq_dma *dma)
{
	switch (dma->type) {
	case MLX5E_DMA_MAP_SINGLE:
		dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
		break;
	case MLX5E_DMA_MAP_PAGE:
		dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
		break;
	default:
		WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
	}
}

static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
				  dma_addr_t addr,
				  u32 size,
				  enum mlx5e_dma_map_type map_type)
{
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
	sq->dma_fifo_pc++;
}

static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_sq *sq, u32 i)
{
	return &sq->dma_fifo[i & sq->dma_fifo_mask];
}

static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma)
{
	int i;

	for (i = 0; i < num_dma; i++) {
		struct mlx5e_sq_dma *last_pushed_dma =
			mlx5e_dma_get(sq, --sq->dma_fifo_pc);

		mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
	}
}

u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
		       void *accel_priv, select_queue_fallback_t fallback)
{
	struct mlx5e_priv *priv = netdev_priv(dev);
	int channel_ix = fallback(dev, skb);
	int up = (netdev_get_num_tc(dev) && skb_vlan_tag_present(skb)) ?
		 skb->vlan_tci >> VLAN_PRIO_SHIFT : 0;

	return priv->channeltc_to_txq_map[channel_ix][up];
}

static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
					    struct sk_buff *skb, bool bf)
{
	/* Some NIC TX decisions, e.g loopback, are based on the packet
	 * headers and occur before the data gather.
	 * Therefore these headers must be copied into the WQE
	 */
#define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)

	if (bf) {
		u16 ihs = skb_headlen(skb);

		if (skb_vlan_tag_present(skb))
			ihs += VLAN_HLEN;

		if (ihs <= sq->max_inline)
			return skb_headlen(skb);
	}

	return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
}

static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
					    unsigned int *skb_len,
					    unsigned int len)
{
	*skb_len -= len;
	*skb_data += len;
}

static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
				     unsigned char **skb_data,
				     unsigned int *skb_len)
{
	struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
	int cpy1_sz = 2 * ETH_ALEN;
	int cpy2_sz = ihs - cpy1_sz;

	memcpy(vhdr, *skb_data, cpy1_sz);
	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
	vhdr->h_vlan_proto = skb->vlan_proto;
	vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
	memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
}

static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
{
	struct mlx5_wq_cyc       *wq   = &sq->wq;

	u16 pi = sq->pc & wq->sz_m1;
	struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
	struct mlx5e_tx_wqe_info *wi   = &sq->wqe_info[pi];

	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
	struct mlx5_wqe_data_seg *dseg;

	unsigned char *skb_data = skb->data;
	unsigned int skb_len = skb->len;
	u8  opcode = MLX5_OPCODE_SEND;
	dma_addr_t dma_addr = 0;
	unsigned int num_bytes;
	bool bf = false;
	u16 headlen;
	u16 ds_cnt;
	u16 ihs;
	int i;

	memset(wqe, 0, sizeof(*wqe));

	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
		eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
		if (skb->encapsulation) {
			eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
					  MLX5_ETH_WQE_L4_INNER_CSUM;
			sq->stats.csum_partial_inner++;
		} else {
			eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
		}
	} else
		sq->stats.csum_none++;

	if (sq->cc != sq->prev_cc) {
		sq->prev_cc = sq->cc;
		sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
	}

	if (skb_is_gso(skb)) {
		eseg->mss    = cpu_to_be16(skb_shinfo(skb)->gso_size);
		opcode       = MLX5_OPCODE_LSO;

		if (skb->encapsulation) {
			ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
			sq->stats.tso_inner_packets++;
			sq->stats.tso_inner_bytes += skb->len - ihs;
		} else {
			ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
			sq->stats.tso_packets++;
			sq->stats.tso_bytes += skb->len - ihs;
		}

		num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
	} else {
		bf = sq->bf_budget &&
		     !skb->xmit_more &&
		     !skb_shinfo(skb)->nr_frags;
		ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
		num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
	}

	wi->num_bytes = num_bytes;

	if (skb_vlan_tag_present(skb)) {
		mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data,
				  &skb_len);
		ihs += VLAN_HLEN;
	} else {
		memcpy(eseg->inline_hdr_start, skb_data, ihs);
		mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
	}

	eseg->inline_hdr_sz = cpu_to_be16(ihs);

	ds_cnt  = sizeof(*wqe) / MLX5_SEND_WQE_DS;
	ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
			       MLX5_SEND_WQE_DS);
	dseg    = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;

	wi->num_dma = 0;

	headlen = skb_len - skb->data_len;
	if (headlen) {
		dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
					  DMA_TO_DEVICE);
		if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
			goto dma_unmap_wqe_err;

		dseg->addr       = cpu_to_be64(dma_addr);
		dseg->lkey       = sq->mkey_be;
		dseg->byte_count = cpu_to_be32(headlen);

		mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
		wi->num_dma++;

		dseg++;
	}

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
		int fsz = skb_frag_size(frag);

		dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
					    DMA_TO_DEVICE);
		if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
			goto dma_unmap_wqe_err;

		dseg->addr       = cpu_to_be64(dma_addr);
		dseg->lkey       = sq->mkey_be;
		dseg->byte_count = cpu_to_be32(fsz);

		mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
		wi->num_dma++;

		dseg++;
	}

	ds_cnt += wi->num_dma;

	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);

	sq->skb[pi] = skb;

	wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
	sq->pc += wi->num_wqebbs;

	netdev_tx_sent_queue(sq->txq, wi->num_bytes);

	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;

	if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
		netif_tx_stop_queue(sq->txq);
		sq->stats.stopped++;
	}

	if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) {
		int bf_sz = 0;

		if (bf && test_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state))
			bf_sz = wi->num_wqebbs << 3;

		cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
		mlx5e_tx_notify_hw(sq, &wqe->ctrl, bf_sz);
	}

	/* fill sq edge with nops to avoid wqe wrap around */
	while ((sq->pc & wq->sz_m1) > sq->edge)
		mlx5e_send_nop(sq, false);

	if (bf)
		sq->bf_budget--;

	sq->stats.packets++;
	sq->stats.bytes += num_bytes;
	return NETDEV_TX_OK;

dma_unmap_wqe_err:
	sq->stats.dropped++;
	mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);

	dev_kfree_skb_any(skb);

	return NETDEV_TX_OK;
}

netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct mlx5e_priv *priv = netdev_priv(dev);
	struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];

	return mlx5e_sq_xmit(sq, skb);
}

void mlx5e_free_tx_descs(struct mlx5e_sq *sq)
{
	struct mlx5e_tx_wqe_info *wi;
	struct sk_buff *skb;
	u16 ci;
	int i;

	while (sq->cc != sq->pc) {
		ci = sq->cc & sq->wq.sz_m1;
		skb = sq->skb[ci];
		wi = &sq->wqe_info[ci];

		if (!skb) { /* nop */
			sq->cc++;
			continue;
		}

		for (i = 0; i < wi->num_dma; i++) {
			struct mlx5e_sq_dma *dma =
				mlx5e_dma_get(sq, sq->dma_fifo_cc++);

			mlx5e_tx_dma_unmap(sq->pdev, dma);
		}

		dev_kfree_skb_any(skb);
		sq->cc += wi->num_wqebbs;
	}
}

bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
{
	struct mlx5e_sq *sq;
	u32 dma_fifo_cc;
	u32 nbytes;
	u16 npkts;
	u16 sqcc;
	int i;

	sq = container_of(cq, struct mlx5e_sq, cq);

	if (unlikely(test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)))
		return false;

	npkts = 0;
	nbytes = 0;

	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	 * otherwise a cq overrun may occur
	 */
	sqcc = sq->cc;

	/* avoid dirtying sq cache line every cqe */
	dma_fifo_cc = sq->dma_fifo_cc;

	for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
		struct mlx5_cqe64 *cqe;
		u16 wqe_counter;
		bool last_wqe;

		cqe = mlx5e_get_cqe(cq);
		if (!cqe)
			break;

		mlx5_cqwq_pop(&cq->wq);

		wqe_counter = be16_to_cpu(cqe->wqe_counter);

		do {
			struct mlx5e_tx_wqe_info *wi;
			struct sk_buff *skb;
			u16 ci;
			int j;

			last_wqe = (sqcc == wqe_counter);

			ci = sqcc & sq->wq.sz_m1;
			skb = sq->skb[ci];
			wi = &sq->wqe_info[ci];

			if (unlikely(!skb)) { /* nop */
				sqcc++;
				continue;
			}

			if (unlikely(skb_shinfo(skb)->tx_flags &
				     SKBTX_HW_TSTAMP)) {
				struct skb_shared_hwtstamps hwts = {};

				mlx5e_fill_hwstamp(sq->tstamp,
						   get_cqe_ts(cqe), &hwts);
				skb_tstamp_tx(skb, &hwts);
			}

			for (j = 0; j < wi->num_dma; j++) {
				struct mlx5e_sq_dma *dma =
					mlx5e_dma_get(sq, dma_fifo_cc++);

				mlx5e_tx_dma_unmap(sq->pdev, dma);
			}

			npkts++;
			nbytes += wi->num_bytes;
			sqcc += wi->num_wqebbs;
			napi_consume_skb(skb, napi_budget);
		} while (!last_wqe);
	}

	mlx5_cqwq_update_db_record(&cq->wq);

	/* ensure cq space is freed before enabling more cqes */
	wmb();

	sq->dma_fifo_cc = dma_fifo_cc;
	sq->cc = sqcc;

	netdev_tx_completed_queue(sq->txq, npkts, nbytes);

	if (netif_tx_queue_stopped(sq->txq) &&
	    mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
	    likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
				netif_tx_wake_queue(sq->txq);
				sq->stats.wake++;
	}

	return (i == MLX5E_TX_CQ_POLL_BUDGET);
}
Commit	Line	Data
e586b3b0	1	/*
98795158	2	* Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
e586b3b0 AV	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/tcp.h>
	34	#include <linux/if_vlan.h>
	35	#include "en.h"
	36
12be4b21 SM	37	#define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
	38	#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
	39	MLX5E_SQ_NOPS_ROOM)
	40
	41	void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
	42	{
	43	struct mlx5_wq_cyc *wq = &sq->wq;
	44
	45	u16 pi = sq->pc & wq->sz_m1;
	46	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
	47
	48	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	49
	50	memset(cseg, 0, sizeof(*cseg));
	51
	52	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) \| MLX5_OPCODE_NOP);
	53	cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) \| 0x01);
	54
	55	sq->skb[pi] = NULL;
	56	sq->pc++;
d3c9bc27	57	sq->stats.nop++;
12be4b21 SM	58
	59	if (notify_hw) {
	60	cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
bc77b240	61	mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
12be4b21 SM	62	}
	63	}
	64
d4e28cbd AS	65	static inline void mlx5e_tx_dma_unmap(struct device *pdev,
d4e28cbd AS	66	struct mlx5e_sq_dma *dma)
e586b3b0	67	{
d4e28cbd AS	68	switch (dma->type) {
	69	case MLX5E_DMA_MAP_SINGLE:
	70	dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
	71	break;
	72	case MLX5E_DMA_MAP_PAGE:
	73	dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
	74	break;
	75	default:
	76	WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
e586b3b0 AV	77	}
	78	}
	79
d4e28cbd AS	80	static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
	81	dma_addr_t addr,
	82	u32 size,
	83	enum mlx5e_dma_map_type map_type)
e586b3b0 AV	84	{
	85	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
	86	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
d4e28cbd	87	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
e586b3b0 AV	88	sq->dma_fifo_pc++;
	89	}
	90
d4e28cbd AS	91	static inline struct mlx5e_sq_dma mlx5e_dma_get(struct mlx5e_sq sq, u32 i)
	92	{
	93	return &sq->dma_fifo[i & sq->dma_fifo_mask];
	94	}
	95
34802a42	96	static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma)
e586b3b0	97	{
d4e28cbd AS	98	int i;
d4e28cbd AS	99
34802a42	100	for (i = 0; i < num_dma; i++) {
d4e28cbd AS	101	struct mlx5e_sq_dma *last_pushed_dma =
	102	mlx5e_dma_get(sq, --sq->dma_fifo_pc);
	103
	104	mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
	105	}
e586b3b0 AV	106	}
	107
	108	u16 mlx5e_select_queue(struct net_device dev, struct sk_buff skb,
	109	void *accel_priv, select_queue_fallback_t fallback)
	110	{
	111	struct mlx5e_priv *priv = netdev_priv(dev);
	112	int channel_ix = fallback(dev, skb);
08fb1dac SM	113	int up = (netdev_get_num_tc(dev) && skb_vlan_tag_present(skb)) ?
08fb1dac SM	114	skb->vlan_tci >> VLAN_PRIO_SHIFT : 0;
e586b3b0	115
08fb1dac	116	return priv->channeltc_to_txq_map[channel_ix][up];
e586b3b0 AV	117	}
	118
	119	static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
88a85f99	120	struct sk_buff *skb, bool bf)
e586b3b0	121	{
58d52291 AS	122	/* Some NIC TX decisions, e.g loopback, are based on the packet
	123	* headers and occur before the data gather.
	124	* Therefore these headers must be copied into the WQE
	125	*/
e3a19b53	126	#define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
58d52291	127
ba6c4c09 SM	128	if (bf) {
	129	u16 ihs = skb_headlen(skb);
	130
	131	if (skb_vlan_tag_present(skb))
	132	ihs += VLAN_HLEN;
	133
	134	if (ihs <= sq->max_inline)
	135	return skb_headlen(skb);
	136	}
58d52291	137
e3a19b53	138	return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
e586b3b0 AV	139	}
e586b3b0 AV	140
34802a42 AS	141	static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
	142	unsigned int *skb_len,
	143	unsigned int len)
	144	{
	145	*skb_len -= len;
	146	*skb_data += len;
	147	}
	148
	149	static inline void mlx5e_insert_vlan(void start, struct sk_buff skb, u16 ihs,
	150	unsigned char **skb_data,
	151	unsigned int *skb_len)
e4cf27bd AS	152	{
	153	struct vlan_ethhdr vhdr = (struct vlan_ethhdr )start;
	154	int cpy1_sz = 2 * ETH_ALEN;
3ea4891d	155	int cpy2_sz = ihs - cpy1_sz;
e4cf27bd	156
34802a42 AS	157	memcpy(vhdr, *skb_data, cpy1_sz);
34802a42 AS	158	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
e4cf27bd AS	159	vhdr->h_vlan_proto = skb->vlan_proto;
e4cf27bd AS	160	vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
34802a42 AS	161	memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
34802a42 AS	162	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
e4cf27bd AS	163	}
e4cf27bd AS	164
e586b3b0 AV	165	static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq sq, struct sk_buff skb)
	166	{
	167	struct mlx5_wq_cyc *wq = &sq->wq;
	168
	169	u16 pi = sq->pc & wq->sz_m1;
	170	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
34802a42	171	struct mlx5e_tx_wqe_info *wi = &sq->wqe_info[pi];
e586b3b0 AV	172
	173	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	174	struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
	175	struct mlx5_wqe_data_seg *dseg;
	176
34802a42 AS	177	unsigned char *skb_data = skb->data;
34802a42 AS	178	unsigned int skb_len = skb->len;
e586b3b0 AV	179	u8 opcode = MLX5_OPCODE_SEND;
e586b3b0 AV	180	dma_addr_t dma_addr = 0;
b081da5e	181	unsigned int num_bytes;
88a85f99	182	bool bf = false;
e586b3b0 AV	183	u16 headlen;
	184	u16 ds_cnt;
	185	u16 ihs;
	186	int i;
	187
	188	memset(wqe, 0, sizeof(*wqe));
	189
98795158 MF	190	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
98795158 MF	191	eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
89db09eb	192	if (skb->encapsulation) {
98795158 MF	193	eseg->cs_flags \|= MLX5_ETH_WQE_L3_INNER_CSUM \|
98795158 MF	194	MLX5_ETH_WQE_L4_INNER_CSUM;
bfe6d8d1	195	sq->stats.csum_partial_inner++;
89db09eb	196	} else {
98795158	197	eseg->cs_flags \|= MLX5_ETH_WQE_L4_CSUM;
89db09eb	198	}
98795158	199	} else
bfe6d8d1	200	sq->stats.csum_none++;
e586b3b0	201
88a85f99 AS	202	if (sq->cc != sq->prev_cc) {
	203	sq->prev_cc = sq->cc;
	204	sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
	205	}
	206
e586b3b0	207	if (skb_is_gso(skb)) {
e586b3b0 AV	208	eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
e586b3b0 AV	209	opcode = MLX5_OPCODE_LSO;
98795158	210
89db09eb	211	if (skb->encapsulation) {
98795158	212	ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
89db09eb MF	213	sq->stats.tso_inner_packets++;
	214	sq->stats.tso_inner_bytes += skb->len - ihs;
	215	} else {
98795158	216	ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
89db09eb MF	217	sq->stats.tso_packets++;
	218	sq->stats.tso_bytes += skb->len - ihs;
	219	}
98795158	220
b081da5e	221	num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
e586b3b0	222	} else {
88a85f99 AS	223	bf = sq->bf_budget &&
	224	!skb->xmit_more &&
	225	!skb_shinfo(skb)->nr_frags;
	226	ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
b081da5e	227	num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
e586b3b0 AV	228	}
e586b3b0 AV	229
b081da5e GP	230	wi->num_bytes = num_bytes;
b081da5e GP	231
e4cf27bd	232	if (skb_vlan_tag_present(skb)) {
34802a42 AS	233	mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data,
34802a42 AS	234	&skb_len);
3ea4891d	235	ihs += VLAN_HLEN;
e4cf27bd	236	} else {
34802a42 AS	237	memcpy(eseg->inline_hdr_start, skb_data, ihs);
34802a42 AS	238	mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
e4cf27bd	239	}
e586b3b0	240
8ca56ce3	241	eseg->inline_hdr_sz = cpu_to_be16(ihs);
e586b3b0 AV	242
	243	ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
	244	ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
	245	MLX5_SEND_WQE_DS);
	246	dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
	247
34802a42	248	wi->num_dma = 0;
e586b3b0	249
34802a42	250	headlen = skb_len - skb->data_len;
e586b3b0	251	if (headlen) {
34802a42	252	dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
e586b3b0 AV	253	DMA_TO_DEVICE);
	254	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
	255	goto dma_unmap_wqe_err;
	256
	257	dseg->addr = cpu_to_be64(dma_addr);
	258	dseg->lkey = sq->mkey_be;
	259	dseg->byte_count = cpu_to_be32(headlen);
	260
d4e28cbd	261	mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
34802a42	262	wi->num_dma++;
e586b3b0 AV	263
	264	dseg++;
	265	}
	266
	267	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
	268	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
	269	int fsz = skb_frag_size(frag);
	270
	271	dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
	272	DMA_TO_DEVICE);
	273	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
	274	goto dma_unmap_wqe_err;
	275
	276	dseg->addr = cpu_to_be64(dma_addr);
	277	dseg->lkey = sq->mkey_be;
	278	dseg->byte_count = cpu_to_be32(fsz);
	279
d4e28cbd	280	mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
34802a42	281	wi->num_dma++;
e586b3b0 AV	282
	283	dseg++;
	284	}
	285
34802a42	286	ds_cnt += wi->num_dma;
e586b3b0	287
8ca56ce3 AS	288	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) \| opcode);
8ca56ce3 AS	289	cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) \| ds_cnt);
e586b3b0 AV	290
	291	sq->skb[pi] = skb;
	292
34802a42 AS	293	wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
34802a42 AS	294	sq->pc += wi->num_wqebbs;
e586b3b0	295
34802a42	296	netdev_tx_sent_queue(sq->txq, wi->num_bytes);
e586b3b0	297
ef9814de EBE	298	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
	299	skb_shinfo(skb)->tx_flags \|= SKBTX_IN_PROGRESS;
	300
12be4b21	301	if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
e586b3b0 AV	302	netif_tx_stop_queue(sq->txq);
	303	sq->stats.stopped++;
	304	}
	305
059ba072	306	if (!skb->xmit_more \|\| netif_xmit_stopped(sq->txq)) {
88a85f99 AS	307	int bf_sz = 0;
88a85f99 AS	308
0ba42241	309	if (bf && test_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state))
34802a42	310	bf_sz = wi->num_wqebbs << 3;
88a85f99	311
059ba072	312	cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
bc77b240	313	mlx5e_tx_notify_hw(sq, &wqe->ctrl, bf_sz);
059ba072	314	}
e586b3b0	315
12be4b21 SM	316	/* fill sq edge with nops to avoid wqe wrap around */
	317	while ((sq->pc & wq->sz_m1) > sq->edge)
	318	mlx5e_send_nop(sq, false);
	319
0ca00fc1 EC	320	if (bf)
0ca00fc1 EC	321	sq->bf_budget--;
88a85f99	322
e586b3b0	323	sq->stats.packets++;
b081da5e	324	sq->stats.bytes += num_bytes;
e586b3b0 AV	325	return NETDEV_TX_OK;
	326
	327	dma_unmap_wqe_err:
	328	sq->stats.dropped++;
34802a42	329	mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
e586b3b0 AV	330
	331	dev_kfree_skb_any(skb);
	332
	333	return NETDEV_TX_OK;
	334	}
	335
	336	netdev_tx_t mlx5e_xmit(struct sk_buff skb, struct net_device dev)
	337	{
	338	struct mlx5e_priv *priv = netdev_priv(dev);
03289b88	339	struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
e586b3b0 AV	340
	341	return mlx5e_sq_xmit(sq, skb);
	342	}
	343
29429f33 DJ	344	void mlx5e_free_tx_descs(struct mlx5e_sq *sq)
	345	{
	346	struct mlx5e_tx_wqe_info *wi;
	347	struct sk_buff *skb;
	348	u16 ci;
	349	int i;
	350
	351	while (sq->cc != sq->pc) {
	352	ci = sq->cc & sq->wq.sz_m1;
	353	skb = sq->skb[ci];
	354	wi = &sq->wqe_info[ci];
	355
	356	if (!skb) { /* nop */
	357	sq->cc++;
	358	continue;
	359	}
	360
	361	for (i = 0; i < wi->num_dma; i++) {
	362	struct mlx5e_sq_dma *dma =
	363	mlx5e_dma_get(sq, sq->dma_fifo_cc++);
	364
	365	mlx5e_tx_dma_unmap(sq->pdev, dma);
	366	}
	367
	368	dev_kfree_skb_any(skb);
	369	sq->cc += wi->num_wqebbs;
	370	}
	371	}
	372
8ec736e5	373	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
e586b3b0 AV	374	{
	375	struct mlx5e_sq *sq;
	376	u32 dma_fifo_cc;
	377	u32 nbytes;
	378	u16 npkts;
	379	u16 sqcc;
	380	int i;
	381
e3391054	382	sq = container_of(cq, struct mlx5e_sq, cq);
e586b3b0	383
29429f33 DJ	384	if (unlikely(test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)))
	385	return false;
	386
e586b3b0 AV	387	npkts = 0;
	388	nbytes = 0;
	389
	390	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	391	* otherwise a cq overrun may occur
	392	*/
	393	sqcc = sq->cc;
	394
	395	/* avoid dirtying sq cache line every cqe */
	396	dma_fifo_cc = sq->dma_fifo_cc;
	397
	398	for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
	399	struct mlx5_cqe64 *cqe;
059ba072 AS	400	u16 wqe_counter;
059ba072 AS	401	bool last_wqe;
e586b3b0 AV	402
	403	cqe = mlx5e_get_cqe(cq);
	404	if (!cqe)
	405	break;
	406
a1f5a1a8 AS	407	mlx5_cqwq_pop(&cq->wq);
a1f5a1a8 AS	408
059ba072 AS	409	wqe_counter = be16_to_cpu(cqe->wqe_counter);
	410
	411	do {
34802a42	412	struct mlx5e_tx_wqe_info *wi;
059ba072 AS	413	struct sk_buff *skb;
	414	u16 ci;
	415	int j;
	416
	417	last_wqe = (sqcc == wqe_counter);
	418
	419	ci = sqcc & sq->wq.sz_m1;
	420	skb = sq->skb[ci];
34802a42	421	wi = &sq->wqe_info[ci];
e586b3b0	422
059ba072	423	if (unlikely(!skb)) { /* nop */
059ba072 AS	424	sqcc++;
	425	continue;
	426	}
e586b3b0	427
ef9814de EBE	428	if (unlikely(skb_shinfo(skb)->tx_flags &
	429	SKBTX_HW_TSTAMP)) {
	430	struct skb_shared_hwtstamps hwts = {};
	431
	432	mlx5e_fill_hwstamp(sq->tstamp,
	433	get_cqe_ts(cqe), &hwts);
	434	skb_tstamp_tx(skb, &hwts);
	435	}
	436
34802a42	437	for (j = 0; j < wi->num_dma; j++) {
d4e28cbd AS	438	struct mlx5e_sq_dma *dma =
d4e28cbd AS	439	mlx5e_dma_get(sq, dma_fifo_cc++);
e586b3b0	440
d4e28cbd	441	mlx5e_tx_dma_unmap(sq->pdev, dma);
059ba072	442	}
e586b3b0	443
059ba072	444	npkts++;
34802a42 AS	445	nbytes += wi->num_bytes;
34802a42 AS	446	sqcc += wi->num_wqebbs;
8ec736e5	447	napi_consume_skb(skb, napi_budget);
059ba072	448	} while (!last_wqe);
e586b3b0 AV	449	}
	450
	451	mlx5_cqwq_update_db_record(&cq->wq);
	452
	453	/* ensure cq space is freed before enabling more cqes */
	454	wmb();
	455
	456	sq->dma_fifo_cc = dma_fifo_cc;
	457	sq->cc = sqcc;
	458
	459	netdev_tx_completed_queue(sq->txq, npkts, nbytes);
	460
	461	if (netif_tx_queue_stopped(sq->txq) &&
12be4b21	462	mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
e586b3b0 AV	463	likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
	464	netif_tx_wake_queue(sq->txq);
	465	sq->stats.wake++;
	466	}
e586b3b0	467
59a7c2fd	468	return (i == MLX5E_TX_CQ_POLL_BUDGET);
e586b3b0	469	}