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Merge tag 'batadv-next-for-davem-20160701' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.c
CommitLineData
073bb189
SM		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
86d722ad 37#include <linux/mlx5/fs.h>
073bb189
SM		 38#include "mlx5_core.h"
39#include "eswitch.h"
40
81848731
SM		 41#define UPLINK_VPORT 0xFFFF
42
073bb189
SM		 43#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
44
45#define esw_info(dev, format, ...) \
46 pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
47
48#define esw_warn(dev, format, ...) \
49 pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
50
51#define esw_debug(dev, format, ...) \
52 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
53
54enum {
55 MLX5_ACTION_NONE = 0,
56 MLX5_ACTION_ADD = 1,
57 MLX5_ACTION_DEL = 2,
58};
59
81848731
SM		 60/* E-Switch UC L2 table hash node */
61struct esw_uc_addr {
073bb189 62 struct l2addr_node node;
073bb189
SM		 63 u32 table_index;
64 u32 vport;
65};
66
81848731
SM		 67/* E-Switch MC FDB table hash node */
68struct esw_mc_addr { /* SRIOV only */
69 struct l2addr_node node;
70 struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
71 u32 refcnt;
72};
73
74/* Vport UC/MC hash node */
75struct vport_addr {
76 struct l2addr_node node;
77 u8 action;
78 u32 vport;
79 struct mlx5_flow_rule *flow_rule; /* SRIOV only */
a35f71f2
MHY		 80 /* A flag indicating that mac was added due to mc promiscuous vport */
81 bool mc_promisc;
073bb189
SM		 82};
83
84enum {
85 UC_ADDR_CHANGE = BIT(0),
86 MC_ADDR_CHANGE = BIT(1),
a35f71f2 87 PROMISC_CHANGE = BIT(3),
073bb189
SM		 88};
89
81848731
SM		 90/* Vport context events */
91#define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
a35f71f2
MHY		 92 MC_ADDR_CHANGE | \
93 PROMISC_CHANGE)
81848731
SM		 94
95static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
073bb189
SM		 96 u32 events_mask)
97{
98 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)];
99 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)];
100 void *nic_vport_ctx;
101 int err;
102
103 memset(out, 0, sizeof(out));
104 memset(in, 0, sizeof(in));
105
106 MLX5_SET(modify_nic_vport_context_in, in,
107 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
108 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
109 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
110 if (vport)
111 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
112 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
113 in, nic_vport_context);
114
115 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
116
117 if (events_mask & UC_ADDR_CHANGE)
118 MLX5_SET(nic_vport_context, nic_vport_ctx,
119 event_on_uc_address_change, 1);
120 if (events_mask & MC_ADDR_CHANGE)
121 MLX5_SET(nic_vport_context, nic_vport_ctx,
122 event_on_mc_address_change, 1);
a35f71f2
MHY		 123 if (events_mask & PROMISC_CHANGE)
124 MLX5_SET(nic_vport_context, nic_vport_ctx,
125 event_on_promisc_change, 1);
073bb189
SM		 126
127 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
128 if (err)
129 goto ex;
130 err = mlx5_cmd_status_to_err_v2(out);
131 if (err)
132 goto ex;
133 return 0;
134ex:
135 return err;
136}
137
9e7ea352
SM		 138/* E-Switch vport context HW commands */
139static int query_esw_vport_context_cmd(struct mlx5_core_dev *mdev, u32 vport,
140 u32 *out, int outlen)
141{
142 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)];
143
144 memset(in, 0, sizeof(in));
145
146 MLX5_SET(query_nic_vport_context_in, in, opcode,
147 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
148
149 MLX5_SET(query_esw_vport_context_in, in, vport_number, vport);
150 if (vport)
151 MLX5_SET(query_esw_vport_context_in, in, other_vport, 1);
152
153 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in), out, outlen);
154}
155
156static int query_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
157 u16 *vlan, u8 *qos)
158{
159 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)];
160 int err;
161 bool cvlan_strip;
162 bool cvlan_insert;
163
164 memset(out, 0, sizeof(out));
165
166 *vlan = 0;
167 *qos = 0;
168
169 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
170 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
171 return -ENOTSUPP;
172
173 err = query_esw_vport_context_cmd(dev, vport, out, sizeof(out));
174 if (err)
175 goto out;
176
177 cvlan_strip = MLX5_GET(query_esw_vport_context_out, out,
178 esw_vport_context.vport_cvlan_strip);
179
180 cvlan_insert = MLX5_GET(query_esw_vport_context_out, out,
181 esw_vport_context.vport_cvlan_insert);
182
183 if (cvlan_strip || cvlan_insert) {
184 *vlan = MLX5_GET(query_esw_vport_context_out, out,
185 esw_vport_context.cvlan_id);
186 *qos = MLX5_GET(query_esw_vport_context_out, out,
187 esw_vport_context.cvlan_pcp);
188 }
189
190 esw_debug(dev, "Query Vport[%d] cvlan: VLAN %d qos=%d\n",
191 vport, *vlan, *qos);
192out:
193 return err;
194}
195
196static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
197 void *in, int inlen)
198{
199 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)];
200
201 memset(out, 0, sizeof(out));
202
203 MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
204 if (vport)
205 MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
206
207 MLX5_SET(modify_esw_vport_context_in, in, opcode,
208 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
209
210 return mlx5_cmd_exec_check_status(dev, in, inlen,
211 out, sizeof(out));
212}
213
214static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
215 u16 vlan, u8 qos, bool set)
216{
217 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)];
218
219 memset(in, 0, sizeof(in));
220
221 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
222 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
223 return -ENOTSUPP;
224
225 esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%d\n",
226 vport, vlan, qos, set);
227
228 if (set) {
229 MLX5_SET(modify_esw_vport_context_in, in,
230 esw_vport_context.vport_cvlan_strip, 1);
231 /* insert only if no vlan in packet */
232 MLX5_SET(modify_esw_vport_context_in, in,
233 esw_vport_context.vport_cvlan_insert, 1);
234 MLX5_SET(modify_esw_vport_context_in, in,
235 esw_vport_context.cvlan_pcp, qos);
236 MLX5_SET(modify_esw_vport_context_in, in,
237 esw_vport_context.cvlan_id, vlan);
238 }
239
240 MLX5_SET(modify_esw_vport_context_in, in,
241 field_select.vport_cvlan_strip, 1);
242 MLX5_SET(modify_esw_vport_context_in, in,
243 field_select.vport_cvlan_insert, 1);
244
245 return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
246}
247
073bb189
SM		 248/* HW L2 Table (MPFS) management */
249static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
250 u8 *mac, u8 vlan_valid, u16 vlan)
251{
252 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)];
253 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)];
254 u8 *in_mac_addr;
255
256 memset(in, 0, sizeof(in));
257 memset(out, 0, sizeof(out));
258
259 MLX5_SET(set_l2_table_entry_in, in, opcode,
260 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
261 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
262 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
263 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
264
265 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
266 ether_addr_copy(&in_mac_addr[2], mac);
267
268 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
269 out, sizeof(out));
270}
271
272static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
273{
274 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)];
275 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)];
276
277 memset(in, 0, sizeof(in));
278 memset(out, 0, sizeof(out));
279
280 MLX5_SET(delete_l2_table_entry_in, in, opcode,
281 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
282 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
283 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
284 out, sizeof(out));
285}
286
287static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
288{
289 int err = 0;
290
291 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
292 if (*ix >= l2_table->size)
293 err = -ENOSPC;
294 else
295 __set_bit(*ix, l2_table->bitmap);
296
297 return err;
298}
299
300static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
301{
302 __clear_bit(ix, l2_table->bitmap);
303}
304
305static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
306 u8 vlan_valid, u16 vlan,
307 u32 *index)
308{
309 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
310 int err;
311
312 err = alloc_l2_table_index(l2_table, index);
313 if (err)
314 return err;
315
316 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
317 if (err)
318 free_l2_table_index(l2_table, *index);
319
320 return err;
321}
322
323static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
324{
325 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
326
327 del_l2_table_entry_cmd(dev, index);
328 free_l2_table_index(l2_table, index);
329}
330
81848731
SM		 331/* E-Switch FDB */
332static struct mlx5_flow_rule *
a35f71f2 333__esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
78a9199b 334 u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
81848731 335{
78a9199b
MHY		 336 int match_header = (is_zero_ether_addr(mac_c) ? 0 :
337 MLX5_MATCH_OUTER_HEADERS);
81848731 338 struct mlx5_flow_rule *flow_rule = NULL;
78a9199b 339 struct mlx5_flow_destination dest;
a35f71f2
MHY		 340 void *mv_misc = NULL;
341 void *mc_misc = NULL;
78a9199b
MHY		 342 u8 *dmac_v = NULL;
343 u8 *dmac_c = NULL;
81848731
SM		 344 u32 *match_v;
345 u32 *match_c;
81848731 346
a35f71f2
MHY		 347 if (rx_rule)
348 match_header |= MLX5_MATCH_MISC_PARAMETERS;
81848731
SM		 349 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
350 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
351 if (!match_v || !match_c) {
352 pr_warn("FDB: Failed to alloc match parameters\n");
353 goto out;
354 }
78a9199b 355
81848731
SM		 356 dmac_v = MLX5_ADDR_OF(fte_match_param, match_v,
357 outer_headers.dmac_47_16);
358 dmac_c = MLX5_ADDR_OF(fte_match_param, match_c,
359 outer_headers.dmac_47_16);
360
a35f71f2 361 if (match_header & MLX5_MATCH_OUTER_HEADERS) {
78a9199b
MHY		 362 ether_addr_copy(dmac_v, mac_v);
363 ether_addr_copy(dmac_c, mac_c);
364 }
81848731 365
a35f71f2
MHY		 366 if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
367 mv_misc = MLX5_ADDR_OF(fte_match_param, match_v, misc_parameters);
368 mc_misc = MLX5_ADDR_OF(fte_match_param, match_c, misc_parameters);
369 MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
370 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
371 }
372
81848731
SM		 373 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
374 dest.vport_num = vport;
375
376 esw_debug(esw->dev,
377 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
378 dmac_v, dmac_c, vport);
379 flow_rule =
86d722ad 380 mlx5_add_flow_rule(esw->fdb_table.fdb,
81848731
SM		 381 match_header,
382 match_c,
383 match_v,
384 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
385 0, &dest);
3f42ac66 386 if (IS_ERR(flow_rule)) {
81848731
SM		 387 pr_warn(
388 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
389 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
390 flow_rule = NULL;
391 }
392out:
393 kfree(match_v);
394 kfree(match_c);
395 return flow_rule;
396}
397
78a9199b
MHY		 398static struct mlx5_flow_rule *
399esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
400{
401 u8 mac_c[ETH_ALEN];
402
403 eth_broadcast_addr(mac_c);
a35f71f2
MHY		 404 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
405}
406
407static struct mlx5_flow_rule *
408esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
409{
410 u8 mac_c[ETH_ALEN];
411 u8 mac_v[ETH_ALEN];
412
413 eth_zero_addr(mac_c);
414 eth_zero_addr(mac_v);
415 mac_c[0] = 0x01;
416 mac_v[0] = 0x01;
417 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
418}
419
420static struct mlx5_flow_rule *
421esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
422{
423 u8 mac_c[ETH_ALEN];
424 u8 mac_v[ETH_ALEN];
425
426 eth_zero_addr(mac_c);
427 eth_zero_addr(mac_v);
428 return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
78a9199b
MHY		 429}
430
81848731
SM		 431static int esw_create_fdb_table(struct mlx5_eswitch *esw, int nvports)
432{
86d722ad 433 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
81848731 434 struct mlx5_core_dev *dev = esw->dev;
86d722ad 435 struct mlx5_flow_namespace *root_ns;
81848731 436 struct mlx5_flow_table *fdb;
86d722ad
MG		 437 struct mlx5_flow_group *g;
438 void *match_criteria;
439 int table_size;
440 u32 *flow_group_in;
81848731 441 u8 *dmac;
86d722ad 442 int err = 0;
81848731
SM		 443
444 esw_debug(dev, "Create FDB log_max_size(%d)\n",
445 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
446
86d722ad
MG		 447 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
448 if (!root_ns) {
449 esw_warn(dev, "Failed to get FDB flow namespace\n");
450 return -ENOMEM;
451 }
81848731 452
86d722ad
MG		 453 flow_group_in = mlx5_vzalloc(inlen);
454 if (!flow_group_in)
455 return -ENOMEM;
456 memset(flow_group_in, 0, inlen);
457
458 table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
d63cd286 459 fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0);
3f42ac66 460 if (IS_ERR(fdb)) {
86d722ad
MG		 461 err = PTR_ERR(fdb);
462 esw_warn(dev, "Failed to create FDB Table err %d\n", err);
463 goto out;
464 }
78a9199b 465 esw->fdb_table.fdb = fdb;
81848731 466
78a9199b 467 /* Addresses group : Full match unicast/multicast addresses */
86d722ad
MG		 468 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
469 MLX5_MATCH_OUTER_HEADERS);
470 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
471 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
472 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
78a9199b
MHY		 473 /* Preserve 2 entries for allmulti and promisc rules*/
474 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
86d722ad 475 eth_broadcast_addr(dmac);
86d722ad 476 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 477 if (IS_ERR(g)) {
86d722ad
MG		 478 err = PTR_ERR(g);
479 esw_warn(dev, "Failed to create flow group err(%d)\n", err);
480 goto out;
481 }
86d722ad 482 esw->fdb_table.addr_grp = g;
78a9199b
MHY		 483
484 /* Allmulti group : One rule that forwards any mcast traffic */
485 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
486 MLX5_MATCH_OUTER_HEADERS);
487 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
488 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
489 eth_zero_addr(dmac);
490 dmac[0] = 0x01;
491 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 492 if (IS_ERR(g)) {
78a9199b
MHY		 493 err = PTR_ERR(g);
494 esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
495 goto out;
496 }
497 esw->fdb_table.allmulti_grp = g;
498
499 /* Promiscuous group :
500 * One rule that forward all unmatched traffic from previous groups
501 */
502 eth_zero_addr(dmac);
503 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
504 MLX5_MATCH_MISC_PARAMETERS);
505 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
506 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
507 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
508 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 509 if (IS_ERR(g)) {
78a9199b
MHY		 510 err = PTR_ERR(g);
511 esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
512 goto out;
513 }
514 esw->fdb_table.promisc_grp = g;
515
86d722ad 516out:
78a9199b
MHY		 517 if (err) {
518 if (!IS_ERR_OR_NULL(esw->fdb_table.allmulti_grp)) {
519 mlx5_destroy_flow_group(esw->fdb_table.allmulti_grp);
520 esw->fdb_table.allmulti_grp = NULL;
521 }
522 if (!IS_ERR_OR_NULL(esw->fdb_table.addr_grp)) {
523 mlx5_destroy_flow_group(esw->fdb_table.addr_grp);
524 esw->fdb_table.addr_grp = NULL;
525 }
526 if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
527 mlx5_destroy_flow_table(esw->fdb_table.fdb);
528 esw->fdb_table.fdb = NULL;
529 }
530 }
531
3fe3d819 532 kvfree(flow_group_in);
86d722ad 533 return err;
81848731
SM		 534}
535
536static void esw_destroy_fdb_table(struct mlx5_eswitch *esw)
537{
538 if (!esw->fdb_table.fdb)
539 return;
540
86d722ad 541 esw_debug(esw->dev, "Destroy FDB Table\n");
78a9199b
MHY		 542 mlx5_destroy_flow_group(esw->fdb_table.promisc_grp);
543 mlx5_destroy_flow_group(esw->fdb_table.allmulti_grp);
86d722ad 544 mlx5_destroy_flow_group(esw->fdb_table.addr_grp);
81848731
SM		 545 mlx5_destroy_flow_table(esw->fdb_table.fdb);
546 esw->fdb_table.fdb = NULL;
86d722ad 547 esw->fdb_table.addr_grp = NULL;
78a9199b
MHY		 548 esw->fdb_table.allmulti_grp = NULL;
549 esw->fdb_table.promisc_grp = NULL;
81848731
SM		 550}
551
552/* E-Switch vport UC/MC lists management */
553typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
554 struct vport_addr *vaddr);
555
556static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
557{
558 struct hlist_head *hash = esw->l2_table.l2_hash;
559 struct esw_uc_addr *esw_uc;
560 u8 *mac = vaddr->node.addr;
561 u32 vport = vaddr->vport;
562 int err;
563
564 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
565 if (esw_uc) {
073bb189
SM		 566 esw_warn(esw->dev,
567 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
81848731 568 mac, vport, esw_uc->vport);
073bb189
SM		 569 return -EEXIST;
570 }
571
81848731
SM		 572 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
573 if (!esw_uc)
073bb189 574 return -ENOMEM;
81848731 575 esw_uc->vport = vport;
073bb189 576
81848731 577 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
073bb189 578 if (err)
81848731
SM		 579 goto abort;
580
581 if (esw->fdb_table.fdb) /* SRIOV is enabled: Forward UC MAC to vport */
582 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
583
584 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
585 vport, mac, esw_uc->table_index, vaddr->flow_rule);
586 return err;
587abort:
588 l2addr_hash_del(esw_uc);
073bb189
SM		 589 return err;
590}
591
81848731 592static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
073bb189 593{
81848731
SM		 594 struct hlist_head *hash = esw->l2_table.l2_hash;
595 struct esw_uc_addr *esw_uc;
596 u8 *mac = vaddr->node.addr;
597 u32 vport = vaddr->vport;
598
599 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
600 if (!esw_uc || esw_uc->vport != vport) {
601 esw_debug(esw->dev,
602 "MAC(%pM) doesn't belong to vport (%d)\n",
603 mac, vport);
604 return -EINVAL;
605 }
606 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
607 vport, mac, esw_uc->table_index, vaddr->flow_rule);
608
609 del_l2_table_entry(esw->dev, esw_uc->table_index);
610
611 if (vaddr->flow_rule)
86d722ad 612 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 613 vaddr->flow_rule = NULL;
614
615 l2addr_hash_del(esw_uc);
616 return 0;
617}
618
a35f71f2
MHY		 619static void update_allmulti_vports(struct mlx5_eswitch *esw,
620 struct vport_addr *vaddr,
621 struct esw_mc_addr *esw_mc)
622{
623 u8 *mac = vaddr->node.addr;
624 u32 vport_idx = 0;
625
626 for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
627 struct mlx5_vport *vport = &esw->vports[vport_idx];
628 struct hlist_head *vport_hash = vport->mc_list;
629 struct vport_addr *iter_vaddr =
630 l2addr_hash_find(vport_hash,
631 mac,
632 struct vport_addr);
633 if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
634 vaddr->vport == vport_idx)
635 continue;
636 switch (vaddr->action) {
637 case MLX5_ACTION_ADD:
638 if (iter_vaddr)
639 continue;
640 iter_vaddr = l2addr_hash_add(vport_hash, mac,
641 struct vport_addr,
642 GFP_KERNEL);
643 if (!iter_vaddr) {
644 esw_warn(esw->dev,
645 "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
646 mac, vport_idx);
647 continue;
648 }
649 iter_vaddr->vport = vport_idx;
650 iter_vaddr->flow_rule =
651 esw_fdb_set_vport_rule(esw,
652 mac,
653 vport_idx);
62e3c24a 654 iter_vaddr->mc_promisc = true;
a35f71f2
MHY		 655 break;
656 case MLX5_ACTION_DEL:
657 if (!iter_vaddr)
658 continue;
659 mlx5_del_flow_rule(iter_vaddr->flow_rule);
660 l2addr_hash_del(iter_vaddr);
661 break;
662 }
663 }
664}
665
81848731
SM		 666static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
667{
668 struct hlist_head *hash = esw->mc_table;
669 struct esw_mc_addr *esw_mc;
670 u8 *mac = vaddr->node.addr;
671 u32 vport = vaddr->vport;
672
673 if (!esw->fdb_table.fdb)
674 return 0;
675
676 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
677 if (esw_mc)
678 goto add;
679
680 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
681 if (!esw_mc)
682 return -ENOMEM;
683
684 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
685 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
a35f71f2
MHY		 686
687 /* Add this multicast mac to all the mc promiscuous vports */
688 update_allmulti_vports(esw, vaddr, esw_mc);
689
81848731 690add:
a35f71f2
MHY		 691 /* If the multicast mac is added as a result of mc promiscuous vport,
692 * don't increment the multicast ref count
693 */
694 if (!vaddr->mc_promisc)
695 esw_mc->refcnt++;
696
81848731
SM		 697 /* Forward MC MAC to vport */
698 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
699 esw_debug(esw->dev,
700 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
701 vport, mac, vaddr->flow_rule,
702 esw_mc->refcnt, esw_mc->uplink_rule);
703 return 0;
704}
705
706static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
707{
708 struct hlist_head *hash = esw->mc_table;
709 struct esw_mc_addr *esw_mc;
710 u8 *mac = vaddr->node.addr;
711 u32 vport = vaddr->vport;
073bb189 712
81848731
SM		 713 if (!esw->fdb_table.fdb)
714 return 0;
715
716 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
717 if (!esw_mc) {
718 esw_warn(esw->dev,
719 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
073bb189
SM		 720 mac, vport);
721 return -EINVAL;
722 }
81848731
SM		 723 esw_debug(esw->dev,
724 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
725 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
726 esw_mc->uplink_rule);
727
728 if (vaddr->flow_rule)
86d722ad 729 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 730 vaddr->flow_rule = NULL;
731
a35f71f2
MHY		 732 /* If the multicast mac is added as a result of mc promiscuous vport,
733 * don't decrement the multicast ref count.
734 */
735 if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
81848731 736 return 0;
073bb189 737
a35f71f2
MHY		 738 /* Remove this multicast mac from all the mc promiscuous vports */
739 update_allmulti_vports(esw, vaddr, esw_mc);
740
81848731 741 if (esw_mc->uplink_rule)
86d722ad 742 mlx5_del_flow_rule(esw_mc->uplink_rule);
81848731
SM		 743
744 l2addr_hash_del(esw_mc);
073bb189
SM		 745 return 0;
746}
747
81848731
SM		 748/* Apply vport UC/MC list to HW l2 table and FDB table */
749static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
750 u32 vport_num, int list_type)
073bb189
SM		 751{
752 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731
SM		 753 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
754 vport_addr_action vport_addr_add;
755 vport_addr_action vport_addr_del;
756 struct vport_addr *addr;
073bb189
SM		 757 struct l2addr_node *node;
758 struct hlist_head *hash;
759 struct hlist_node *tmp;
760 int hi;
761
81848731
SM		 762 vport_addr_add = is_uc ? esw_add_uc_addr :
763 esw_add_mc_addr;
764 vport_addr_del = is_uc ? esw_del_uc_addr :
765 esw_del_mc_addr;
766
767 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189 768 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 769 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 770 switch (addr->action) {
771 case MLX5_ACTION_ADD:
81848731 772 vport_addr_add(esw, addr);
073bb189
SM		 773 addr->action = MLX5_ACTION_NONE;
774 break;
775 case MLX5_ACTION_DEL:
81848731 776 vport_addr_del(esw, addr);
073bb189
SM		 777 l2addr_hash_del(addr);
778 break;
779 }
780 }
781}
782
81848731
SM		 783/* Sync vport UC/MC list from vport context */
784static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
785 u32 vport_num, int list_type)
073bb189
SM		 786{
787 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731 788 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
073bb189 789 u8 (*mac_list)[ETH_ALEN];
81848731
SM		 790 struct l2addr_node *node;
791 struct vport_addr *addr;
073bb189
SM		 792 struct hlist_head *hash;
793 struct hlist_node *tmp;
794 int size;
795 int err;
796 int hi;
797 int i;
798
81848731
SM		 799 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
800 MLX5_MAX_MC_PER_VPORT(esw->dev);
073bb189
SM		 801
802 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
803 if (!mac_list)
804 return;
805
81848731 806 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189
SM		 807
808 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 809 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 810 addr->action = MLX5_ACTION_DEL;
811 }
812
586cfa7f
MHY		 813 if (!vport->enabled)
814 goto out;
815
81848731 816 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
073bb189
SM		 817 mac_list, &size);
818 if (err)
761e205b 819 goto out;
81848731
SM		 820 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
821 vport_num, is_uc ? "UC" : "MC", size);
073bb189
SM		 822
823 for (i = 0; i < size; i++) {
81848731 824 if (is_uc && !is_valid_ether_addr(mac_list[i]))
073bb189
SM		 825 continue;
826
81848731
SM		 827 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
828 continue;
829
830 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
073bb189
SM		 831 if (addr) {
832 addr->action = MLX5_ACTION_NONE;
a35f71f2
MHY		 833 /* If this mac was previously added because of allmulti
834 * promiscuous rx mode, its now converted to be original
835 * vport mac.
836 */
837 if (addr->mc_promisc) {
838 struct esw_mc_addr *esw_mc =
839 l2addr_hash_find(esw->mc_table,
840 mac_list[i],
841 struct esw_mc_addr);
842 if (!esw_mc) {
843 esw_warn(esw->dev,
844 "Failed to MAC(%pM) in mcast DB\n",
845 mac_list[i]);
846 continue;
847 }
848 esw_mc->refcnt++;
849 addr->mc_promisc = false;
850 }
073bb189
SM		 851 continue;
852 }
853
81848731 854 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
073bb189
SM		 855 GFP_KERNEL);
856 if (!addr) {
857 esw_warn(esw->dev,
858 "Failed to add MAC(%pM) to vport[%d] DB\n",
859 mac_list[i], vport_num);
860 continue;
861 }
81848731 862 addr->vport = vport_num;
073bb189
SM		 863 addr->action = MLX5_ACTION_ADD;
864 }
761e205b 865out:
073bb189
SM		 866 kfree(mac_list);
867}
868
a35f71f2
MHY		 869/* Sync vport UC/MC list from vport context
870 * Must be called after esw_update_vport_addr_list
871 */
872static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
873{
874 struct mlx5_vport *vport = &esw->vports[vport_num];
875 struct l2addr_node *node;
876 struct vport_addr *addr;
877 struct hlist_head *hash;
878 struct hlist_node *tmp;
879 int hi;
880
881 hash = vport->mc_list;
882
883 for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
884 u8 *mac = node->addr;
885
886 addr = l2addr_hash_find(hash, mac, struct vport_addr);
887 if (addr) {
888 if (addr->action == MLX5_ACTION_DEL)
889 addr->action = MLX5_ACTION_NONE;
890 continue;
891 }
892 addr = l2addr_hash_add(hash, mac, struct vport_addr,
893 GFP_KERNEL);
894 if (!addr) {
895 esw_warn(esw->dev,
896 "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
897 mac, vport_num);
898 continue;
899 }
900 addr->vport = vport_num;
901 addr->action = MLX5_ACTION_ADD;
902 addr->mc_promisc = true;
903 }
904}
905
906/* Apply vport rx mode to HW FDB table */
907static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
908 bool promisc, bool mc_promisc)
909{
910 struct esw_mc_addr *allmulti_addr = esw->mc_promisc;
911 struct mlx5_vport *vport = &esw->vports[vport_num];
912
913 if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
914 goto promisc;
915
916 if (mc_promisc) {
917 vport->allmulti_rule =
918 esw_fdb_set_vport_allmulti_rule(esw, vport_num);
919 if (!allmulti_addr->uplink_rule)
920 allmulti_addr->uplink_rule =
921 esw_fdb_set_vport_allmulti_rule(esw,
922 UPLINK_VPORT);
923 allmulti_addr->refcnt++;
924 } else if (vport->allmulti_rule) {
925 mlx5_del_flow_rule(vport->allmulti_rule);
926 vport->allmulti_rule = NULL;
927
928 if (--allmulti_addr->refcnt > 0)
929 goto promisc;
930
931 if (allmulti_addr->uplink_rule)
932 mlx5_del_flow_rule(allmulti_addr->uplink_rule);
933 allmulti_addr->uplink_rule = NULL;
934 }
935
936promisc:
937 if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
938 return;
939
940 if (promisc) {
941 vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
942 vport_num);
943 } else if (vport->promisc_rule) {
944 mlx5_del_flow_rule(vport->promisc_rule);
945 vport->promisc_rule = NULL;
946 }
947}
948
949/* Sync vport rx mode from vport context */
950static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
951{
952 struct mlx5_vport *vport = &esw->vports[vport_num];
953 int promisc_all = 0;
954 int promisc_uc = 0;
955 int promisc_mc = 0;
956 int err;
957
958 err = mlx5_query_nic_vport_promisc(esw->dev,
959 vport_num,
960 &promisc_uc,
961 &promisc_mc,
962 &promisc_all);
963 if (err)
964 return;
965 esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
966 vport_num, promisc_all, promisc_mc);
967
968 if (!vport->trusted || !vport->enabled) {
969 promisc_uc = 0;
970 promisc_mc = 0;
971 promisc_all = 0;
972 }
973
974 esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
975 (promisc_all || promisc_mc));
976}
977
1edc57e2 978static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
073bb189 979{
073bb189 980 struct mlx5_core_dev *dev = vport->dev;
81848731 981 struct mlx5_eswitch *esw = dev->priv.eswitch;
073bb189
SM		 982 u8 mac[ETH_ALEN];
983
984 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
81848731
SM		 985 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
986 vport->vport, mac);
987
988 if (vport->enabled_events & UC_ADDR_CHANGE) {
989 esw_update_vport_addr_list(esw, vport->vport,
990 MLX5_NVPRT_LIST_TYPE_UC);
991 esw_apply_vport_addr_list(esw, vport->vport,
992 MLX5_NVPRT_LIST_TYPE_UC);
993 }
073bb189 994
81848731
SM		 995 if (vport->enabled_events & MC_ADDR_CHANGE) {
996 esw_update_vport_addr_list(esw, vport->vport,
997 MLX5_NVPRT_LIST_TYPE_MC);
a35f71f2
MHY		 998 }
999
1000 if (vport->enabled_events & PROMISC_CHANGE) {
1001 esw_update_vport_rx_mode(esw, vport->vport);
1002 if (!IS_ERR_OR_NULL(vport->allmulti_rule))
1003 esw_update_vport_mc_promisc(esw, vport->vport);
1004 }
1005
1006 if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
81848731
SM		 1007 esw_apply_vport_addr_list(esw, vport->vport,
1008 MLX5_NVPRT_LIST_TYPE_MC);
1009 }
073bb189 1010
81848731 1011 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
073bb189
SM		 1012 if (vport->enabled)
1013 arm_vport_context_events_cmd(dev, vport->vport,
81848731 1014 vport->enabled_events);
073bb189
SM		 1015}
1016
1edc57e2
MHY		 1017static void esw_vport_change_handler(struct work_struct *work)
1018{
1019 struct mlx5_vport *vport =
1020 container_of(work, struct mlx5_vport, vport_change_handler);
1021 struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
1022
1023 mutex_lock(&esw->state_lock);
1024 esw_vport_change_handle_locked(vport);
1025 mutex_unlock(&esw->state_lock);
1026}
1027
5742df0f
MHY		 1028static void esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
1029 struct mlx5_vport *vport)
1030{
1031 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1032 struct mlx5_flow_group *vlan_grp = NULL;
1033 struct mlx5_flow_group *drop_grp = NULL;
1034 struct mlx5_core_dev *dev = esw->dev;
1035 struct mlx5_flow_namespace *root_ns;
1036 struct mlx5_flow_table *acl;
1037 void *match_criteria;
1038 u32 *flow_group_in;
1039 /* The egress acl table contains 2 rules:
1040 * 1)Allow traffic with vlan_tag=vst_vlan_id
1041 * 2)Drop all other traffic.
1042 */
1043 int table_size = 2;
1044 int err = 0;
1045
01f51f22
MHY		 1046 if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support) ||
1047 !IS_ERR_OR_NULL(vport->egress.acl))
5742df0f
MHY		 1048 return;
1049
1050 esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
1051 vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
1052
1053 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
1054 if (!root_ns) {
1055 esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
1056 return;
1057 }
1058
1059 flow_group_in = mlx5_vzalloc(inlen);
1060 if (!flow_group_in)
1061 return;
1062
1063 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1064 if (IS_ERR(acl)) {
5742df0f
MHY		 1065 err = PTR_ERR(acl);
1066 esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
1067 vport->vport, err);
1068 goto out;
1069 }
1070
1071 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1072 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1073 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1074 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
1075 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1076 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1077
1078 vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1079 if (IS_ERR(vlan_grp)) {
5742df0f
MHY		 1080 err = PTR_ERR(vlan_grp);
1081 esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
1082 vport->vport, err);
1083 goto out;
1084 }
1085
1086 memset(flow_group_in, 0, inlen);
1087 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1088 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1089 drop_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1090 if (IS_ERR(drop_grp)) {
5742df0f
MHY		 1091 err = PTR_ERR(drop_grp);
1092 esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
1093 vport->vport, err);
1094 goto out;
1095 }
1096
1097 vport->egress.acl = acl;
1098 vport->egress.drop_grp = drop_grp;
1099 vport->egress.allowed_vlans_grp = vlan_grp;
1100out:
3fe3d819 1101 kvfree(flow_group_in);
5742df0f
MHY		 1102 if (err && !IS_ERR_OR_NULL(vlan_grp))
1103 mlx5_destroy_flow_group(vlan_grp);
1104 if (err && !IS_ERR_OR_NULL(acl))
1105 mlx5_destroy_flow_table(acl);
1106}
1107
dfcb1ed3
MHY		 1108static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
1109 struct mlx5_vport *vport)
1110{
1111 if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
1112 mlx5_del_flow_rule(vport->egress.allowed_vlan);
1113
1114 if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
1115 mlx5_del_flow_rule(vport->egress.drop_rule);
1116
1117 vport->egress.allowed_vlan = NULL;
1118 vport->egress.drop_rule = NULL;
1119}
1120
5742df0f
MHY		 1121static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
1122 struct mlx5_vport *vport)
1123{
1124 if (IS_ERR_OR_NULL(vport->egress.acl))
1125 return;
1126
1127 esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
1128
dfcb1ed3 1129 esw_vport_cleanup_egress_rules(esw, vport);
5742df0f
MHY		 1130 mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
1131 mlx5_destroy_flow_group(vport->egress.drop_grp);
1132 mlx5_destroy_flow_table(vport->egress.acl);
1133 vport->egress.allowed_vlans_grp = NULL;
1134 vport->egress.drop_grp = NULL;
1135 vport->egress.acl = NULL;
1136}
1137
1138static void esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
1139 struct mlx5_vport *vport)
1140{
1141 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1142 struct mlx5_core_dev *dev = esw->dev;
1143 struct mlx5_flow_namespace *root_ns;
1144 struct mlx5_flow_table *acl;
1145 struct mlx5_flow_group *g;
1146 void *match_criteria;
1147 u32 *flow_group_in;
1148 /* The ingress acl table contains 4 groups
1149 * (2 active rules at the same time -
1150 * 1 allow rule from one of the first 3 groups.
1151 * 1 drop rule from the last group):
1152 * 1)Allow untagged traffic with smac=original mac.
1153 * 2)Allow untagged traffic.
1154 * 3)Allow traffic with smac=original mac.
1155 * 4)Drop all other traffic.
1156 */
1157 int table_size = 4;
1158 int err = 0;
1159
01f51f22
MHY		 1160 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support) ||
1161 !IS_ERR_OR_NULL(vport->ingress.acl))
5742df0f
MHY		 1162 return;
1163
1164 esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
1165 vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
1166
1167 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
1168 if (!root_ns) {
1169 esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
1170 return;
1171 }
1172
1173 flow_group_in = mlx5_vzalloc(inlen);
1174 if (!flow_group_in)
1175 return;
1176
1177 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1178 if (IS_ERR(acl)) {
5742df0f
MHY		 1179 err = PTR_ERR(acl);
1180 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
1181 vport->vport, err);
1182 goto out;
1183 }
1184 vport->ingress.acl = acl;
1185
1186 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1187
1188 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1189 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1190 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1191 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1192 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1193 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1194
1195 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1196 if (IS_ERR(g)) {
5742df0f
MHY		 1197 err = PTR_ERR(g);
1198 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
1199 vport->vport, err);
1200 goto out;
1201 }
1202 vport->ingress.allow_untagged_spoofchk_grp = g;
1203
1204 memset(flow_group_in, 0, inlen);
1205 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1206 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1207 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1208 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1209
1210 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1211 if (IS_ERR(g)) {
5742df0f
MHY		 1212 err = PTR_ERR(g);
1213 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
1214 vport->vport, err);
1215 goto out;
1216 }
1217 vport->ingress.allow_untagged_only_grp = g;
1218
1219 memset(flow_group_in, 0, inlen);
1220 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1221 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1222 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1223 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
1224 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
1225
1226 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1227 if (IS_ERR(g)) {
5742df0f
MHY		 1228 err = PTR_ERR(g);
1229 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
1230 vport->vport, err);
1231 goto out;
1232 }
1233 vport->ingress.allow_spoofchk_only_grp = g;
1234
1235 memset(flow_group_in, 0, inlen);
1236 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
1237 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
1238
1239 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1240 if (IS_ERR(g)) {
5742df0f
MHY		 1241 err = PTR_ERR(g);
1242 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
1243 vport->vport, err);
1244 goto out;
1245 }
1246 vport->ingress.drop_grp = g;
1247
1248out:
1249 if (err) {
1250 if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
1251 mlx5_destroy_flow_group(
1252 vport->ingress.allow_spoofchk_only_grp);
1253 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
1254 mlx5_destroy_flow_group(
1255 vport->ingress.allow_untagged_only_grp);
1256 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
1257 mlx5_destroy_flow_group(
1258 vport->ingress.allow_untagged_spoofchk_grp);
1259 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1260 mlx5_destroy_flow_table(vport->ingress.acl);
1261 }
1262
3fe3d819 1263 kvfree(flow_group_in);
5742df0f
MHY		 1264}
1265
dfcb1ed3
MHY		 1266static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
1267 struct mlx5_vport *vport)
1268{
1269 if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
1270 mlx5_del_flow_rule(vport->ingress.drop_rule);
f942380c
MHY		 1271
1272 if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
1273 mlx5_del_flow_rule(vport->ingress.allow_rule);
1274
dfcb1ed3 1275 vport->ingress.drop_rule = NULL;
f942380c 1276 vport->ingress.allow_rule = NULL;
dfcb1ed3
MHY		 1277}
1278
5742df0f
MHY		 1279static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
1280 struct mlx5_vport *vport)
1281{
1282 if (IS_ERR_OR_NULL(vport->ingress.acl))
1283 return;
1284
1285 esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
1286
dfcb1ed3 1287 esw_vport_cleanup_ingress_rules(esw, vport);
5742df0f
MHY		 1288 mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
1289 mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
1290 mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
1291 mlx5_destroy_flow_group(vport->ingress.drop_grp);
1292 mlx5_destroy_flow_table(vport->ingress.acl);
1293 vport->ingress.acl = NULL;
1294 vport->ingress.drop_grp = NULL;
1295 vport->ingress.allow_spoofchk_only_grp = NULL;
1296 vport->ingress.allow_untagged_only_grp = NULL;
1297 vport->ingress.allow_untagged_spoofchk_grp = NULL;
1298}
1299
dfcb1ed3
MHY		 1300static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1301 struct mlx5_vport *vport)
1302{
f942380c 1303 u8 smac[ETH_ALEN];
dfcb1ed3
MHY		 1304 u32 *match_v;
1305 u32 *match_c;
1306 int err = 0;
f942380c 1307 u8 *smac_v;
dfcb1ed3 1308
f942380c
MHY		 1309 if (vport->spoofchk) {
1310 err = mlx5_query_nic_vport_mac_address(esw->dev, vport->vport, smac);
1311 if (err) {
1312 esw_warn(esw->dev,
1313 "vport[%d] configure ingress rules failed, query smac failed, err(%d)\n",
1314 vport->vport, err);
1315 return err;
1316 }
1317
1318 if (!is_valid_ether_addr(smac)) {
1319 mlx5_core_warn(esw->dev,
1320 "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
1321 vport->vport);
1322 return -EPERM;
1323 }
1324 }
1325
dfcb1ed3
MHY		 1326 esw_vport_cleanup_ingress_rules(esw, vport);
1327
01f51f22
MHY		 1328 if (!vport->vlan && !vport->qos && !vport->spoofchk) {
1329 esw_vport_disable_ingress_acl(esw, vport);
dfcb1ed3 1330 return 0;
01f51f22
MHY		 1331 }
1332
1333 esw_vport_enable_ingress_acl(esw, vport);
dfcb1ed3
MHY		 1334
1335 esw_debug(esw->dev,
1336 "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
1337 vport->vport, vport->vlan, vport->qos);
1338
1339 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1340 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1341 if (!match_v || !match_c) {
1342 err = -ENOMEM;
1343 esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n",
1344 vport->vport, err);
1345 goto out;
1346 }
dfcb1ed3 1347
f942380c
MHY		 1348 if (vport->vlan || vport->qos)
1349 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.vlan_tag);
1350
1351 if (vport->spoofchk) {
1352 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.smac_47_16);
1353 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.smac_15_0);
1354 smac_v = MLX5_ADDR_OF(fte_match_param,
1355 match_v,
1356 outer_headers.smac_47_16);
1357 ether_addr_copy(smac_v, smac);
1358 }
1359
1360 vport->ingress.allow_rule =
dfcb1ed3
MHY		 1361 mlx5_add_flow_rule(vport->ingress.acl,
1362 MLX5_MATCH_OUTER_HEADERS,
1363 match_c,
1364 match_v,
f942380c
MHY		 1365 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1366 0, NULL);
3f42ac66 1367 if (IS_ERR(vport->ingress.allow_rule)) {
f942380c
MHY		 1368 err = PTR_ERR(vport->ingress.allow_rule);
1369 pr_warn("vport[%d] configure ingress allow rule, err(%d)\n",
1370 vport->vport, err);
1371 vport->ingress.allow_rule = NULL;
1372 goto out;
1373 }
1374
1375 memset(match_c, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1376 memset(match_v, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1377 vport->ingress.drop_rule =
1378 mlx5_add_flow_rule(vport->ingress.acl,
1379 0,
1380 match_c,
1381 match_v,
dfcb1ed3
MHY		 1382 MLX5_FLOW_CONTEXT_ACTION_DROP,
1383 0, NULL);
3f42ac66 1384 if (IS_ERR(vport->ingress.drop_rule)) {
dfcb1ed3 1385 err = PTR_ERR(vport->ingress.drop_rule);
f942380c 1386 pr_warn("vport[%d] configure ingress drop rule, err(%d)\n",
dfcb1ed3
MHY		 1387 vport->vport, err);
1388 vport->ingress.drop_rule = NULL;
f942380c 1389 goto out;
dfcb1ed3 1390 }
f942380c 1391
dfcb1ed3 1392out:
f942380c
MHY		 1393 if (err)
1394 esw_vport_cleanup_ingress_rules(esw, vport);
1395
dfcb1ed3
MHY		 1396 kfree(match_v);
1397 kfree(match_c);
1398 return err;
1399}
1400
1401static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1402 struct mlx5_vport *vport)
1403{
1404 u32 *match_v;
1405 u32 *match_c;
1406 int err = 0;
1407
dfcb1ed3
MHY		 1408 esw_vport_cleanup_egress_rules(esw, vport);
1409
01f51f22
MHY		 1410 if (!vport->vlan && !vport->qos) {
1411 esw_vport_disable_egress_acl(esw, vport);
dfcb1ed3 1412 return 0;
01f51f22
MHY		 1413 }
1414
1415 esw_vport_enable_egress_acl(esw, vport);
dfcb1ed3
MHY		 1416
1417 esw_debug(esw->dev,
1418 "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
1419 vport->vport, vport->vlan, vport->qos);
1420
1421 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1422 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1423 if (!match_v || !match_c) {
1424 err = -ENOMEM;
1425 esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n",
1426 vport->vport, err);
1427 goto out;
1428 }
1429
1430 /* Allowed vlan rule */
1431 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.vlan_tag);
1432 MLX5_SET_TO_ONES(fte_match_param, match_v, outer_headers.vlan_tag);
1433 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.first_vid);
1434 MLX5_SET(fte_match_param, match_v, outer_headers.first_vid, vport->vlan);
1435
1436 vport->egress.allowed_vlan =
1437 mlx5_add_flow_rule(vport->egress.acl,
1438 MLX5_MATCH_OUTER_HEADERS,
1439 match_c,
1440 match_v,
1441 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1442 0, NULL);
3f42ac66 1443 if (IS_ERR(vport->egress.allowed_vlan)) {
dfcb1ed3
MHY		 1444 err = PTR_ERR(vport->egress.allowed_vlan);
1445 pr_warn("vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
1446 vport->vport, err);
1447 vport->egress.allowed_vlan = NULL;
1448 goto out;
1449 }
1450
1451 /* Drop others rule (star rule) */
1452 memset(match_c, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1453 memset(match_v, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1454 vport->egress.drop_rule =
1455 mlx5_add_flow_rule(vport->egress.acl,
1456 0,
1457 match_c,
1458 match_v,
1459 MLX5_FLOW_CONTEXT_ACTION_DROP,
1460 0, NULL);
3f42ac66 1461 if (IS_ERR(vport->egress.drop_rule)) {
dfcb1ed3
MHY		 1462 err = PTR_ERR(vport->egress.drop_rule);
1463 pr_warn("vport[%d] configure egress drop rule failed, err(%d)\n",
1464 vport->vport, err);
1465 vport->egress.drop_rule = NULL;
1466 }
1467out:
1468 kfree(match_v);
1469 kfree(match_c);
1470 return err;
1471}
1472
81848731
SM		 1473static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
1474 int enable_events)
073bb189
SM		 1475{
1476 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189 1477
dfcb1ed3 1478 mutex_lock(&esw->state_lock);
81848731
SM		 1479 WARN_ON(vport->enabled);
1480
1481 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
5742df0f
MHY		 1482
1483 if (vport_num) { /* Only VFs need ACLs for VST and spoofchk filtering */
dfcb1ed3
MHY		 1484 esw_vport_ingress_config(esw, vport);
1485 esw_vport_egress_config(esw, vport);
5742df0f
MHY		 1486 }
1487
81848731
SM		 1488 mlx5_modify_vport_admin_state(esw->dev,
1489 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1490 vport_num,
1491 MLX5_ESW_VPORT_ADMIN_STATE_AUTO);
1492
1493 /* Sync with current vport context */
1494 vport->enabled_events = enable_events;
073bb189 1495 vport->enabled = true;
073bb189 1496
a35f71f2
MHY		 1497 /* only PF is trusted by default */
1498 vport->trusted = (vport_num) ? false : true;
25fff58c 1499 esw_vport_change_handle_locked(vport);
81848731
SM		 1500
1501 esw->enabled_vports++;
1502 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
dfcb1ed3 1503 mutex_unlock(&esw->state_lock);
81848731
SM		 1504}
1505
073bb189
SM		 1506static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
1507{
1508 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189
SM		 1509
1510 if (!vport->enabled)
1511 return;
1512
81848731 1513 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
073bb189 1514 /* Mark this vport as disabled to discard new events */
073bb189 1515 vport->enabled = false;
831cae1d
MHY		 1516
1517 synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
073bb189 1518
81848731
SM		 1519 mlx5_modify_vport_admin_state(esw->dev,
1520 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1521 vport_num,
1522 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
073bb189
SM		 1523 /* Wait for current already scheduled events to complete */
1524 flush_workqueue(esw->work_queue);
073bb189
SM		 1525 /* Disable events from this vport */
1526 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
dfcb1ed3 1527 mutex_lock(&esw->state_lock);
586cfa7f
MHY		 1528 /* We don't assume VFs will cleanup after themselves.
1529 * Calling vport change handler while vport is disabled will cleanup
1530 * the vport resources.
1531 */
1edc57e2 1532 esw_vport_change_handle_locked(vport);
586cfa7f 1533 vport->enabled_events = 0;
5742df0f
MHY		 1534 if (vport_num) {
1535 esw_vport_disable_egress_acl(esw, vport);
1536 esw_vport_disable_ingress_acl(esw, vport);
1537 }
81848731 1538 esw->enabled_vports--;
dfcb1ed3 1539 mutex_unlock(&esw->state_lock);
073bb189
SM		 1540}
1541
1542/* Public E-Switch API */
81848731
SM		 1543int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs)
1544{
1545 int err;
1546 int i;
1547
1548 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1549 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1550 return 0;
1551
1552 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
1553 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
1554 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
1555 return -ENOTSUPP;
1556 }
1557
5742df0f
MHY		 1558 if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
1559 esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
1560
1561 if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
1562 esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
1563
81848731
SM		 1564 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d)\n", nvfs);
1565
1566 esw_disable_vport(esw, 0);
1567
1568 err = esw_create_fdb_table(esw, nvfs + 1);
1569 if (err)
1570 goto abort;
1571
1572 for (i = 0; i <= nvfs; i++)
1573 esw_enable_vport(esw, i, SRIOV_VPORT_EVENTS);
1574
1575 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
1576 esw->enabled_vports);
1577 return 0;
1578
1579abort:
1580 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1581 return err;
1582}
1583
1584void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
1585{
a35f71f2 1586 struct esw_mc_addr *mc_promisc;
81848731
SM		 1587 int i;
1588
1589 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1590 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1591 return;
1592
1593 esw_info(esw->dev, "disable SRIOV: active vports(%d)\n",
1594 esw->enabled_vports);
1595
a35f71f2
MHY		 1596 mc_promisc = esw->mc_promisc;
1597
81848731
SM		 1598 for (i = 0; i < esw->total_vports; i++)
1599 esw_disable_vport(esw, i);
1600
a35f71f2
MHY		 1601 if (mc_promisc && mc_promisc->uplink_rule)
1602 mlx5_del_flow_rule(mc_promisc->uplink_rule);
1603
81848731
SM		 1604 esw_destroy_fdb_table(esw);
1605
1606 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
1607 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1608}
1609
073bb189
SM		 1610int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1611{
1612 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
efdc810b 1613 int total_vports = MLX5_TOTAL_VPORTS(dev);
a35f71f2 1614 struct esw_mc_addr *mc_promisc;
073bb189
SM		 1615 struct mlx5_eswitch *esw;
1616 int vport_num;
1617 int err;
1618
1619 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
1620 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1621 return 0;
1622
1623 esw_info(dev,
1624 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
1625 total_vports, l2_table_size,
1626 MLX5_MAX_UC_PER_VPORT(dev),
1627 MLX5_MAX_MC_PER_VPORT(dev));
1628
1629 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
1630 if (!esw)
1631 return -ENOMEM;
1632
1633 esw->dev = dev;
1634
1635 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
1636 sizeof(uintptr_t), GFP_KERNEL);
1637 if (!esw->l2_table.bitmap) {
1638 err = -ENOMEM;
1639 goto abort;
1640 }
1641 esw->l2_table.size = l2_table_size;
1642
a35f71f2
MHY		 1643 mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL);
1644 if (!mc_promisc) {
1645 err = -ENOMEM;
1646 goto abort;
1647 }
1648 esw->mc_promisc = mc_promisc;
1649
073bb189
SM		 1650 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
1651 if (!esw->work_queue) {
1652 err = -ENOMEM;
1653 goto abort;
1654 }
1655
1656 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
1657 GFP_KERNEL);
1658 if (!esw->vports) {
1659 err = -ENOMEM;
1660 goto abort;
1661 }
1662
dfcb1ed3
MHY		 1663 mutex_init(&esw->state_lock);
1664
073bb189
SM		 1665 for (vport_num = 0; vport_num < total_vports; vport_num++) {
1666 struct mlx5_vport *vport = &esw->vports[vport_num];
1667
1668 vport->vport = vport_num;
1669 vport->dev = dev;
1670 INIT_WORK(&vport->vport_change_handler,
1671 esw_vport_change_handler);
073bb189
SM		 1672 }
1673
81848731
SM		 1674 esw->total_vports = total_vports;
1675 esw->enabled_vports = 0;
073bb189 1676
81848731
SM		 1677 dev->priv.eswitch = esw;
1678 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
073bb189
SM		 1679 /* VF Vports will be enabled when SRIOV is enabled */
1680 return 0;
1681abort:
1682 if (esw->work_queue)
1683 destroy_workqueue(esw->work_queue);
1684 kfree(esw->l2_table.bitmap);
1685 kfree(esw->vports);
1686 kfree(esw);
1687 return err;
1688}
1689
1690void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
1691{
1692 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1693 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1694 return;
1695
1696 esw_info(esw->dev, "cleanup\n");
1697 esw_disable_vport(esw, 0);
1698
1699 esw->dev->priv.eswitch = NULL;
1700 destroy_workqueue(esw->work_queue);
1701 kfree(esw->l2_table.bitmap);
a35f71f2 1702 kfree(esw->mc_promisc);
073bb189
SM		 1703 kfree(esw->vports);
1704 kfree(esw);
1705}
1706
1707void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1708{
1709 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1710 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1711 struct mlx5_vport *vport;
1712
1713 if (!esw) {
1714 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1715 vport_num);
1716 return;
1717 }
1718
1719 vport = &esw->vports[vport_num];
073bb189
SM		 1720 if (vport->enabled)
1721 queue_work(esw->work_queue, &vport->vport_change_handler);
073bb189 1722}
77256579
SM		 1723
1724/* Vport Administration */
1725#define ESW_ALLOWED(esw) \
1726 (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
1727#define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
1728
23898c76
NO		 1729static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
1730{
1731 ((u8 *)node_guid)[7] = mac[0];
1732 ((u8 *)node_guid)[6] = mac[1];
1733 ((u8 *)node_guid)[5] = mac[2];
1734 ((u8 *)node_guid)[4] = 0xff;
1735 ((u8 *)node_guid)[3] = 0xfe;
1736 ((u8 *)node_guid)[2] = mac[3];
1737 ((u8 *)node_guid)[1] = mac[4];
1738 ((u8 *)node_guid)[0] = mac[5];
1739}
1740
77256579
SM		 1741int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
1742 int vport, u8 mac[ETH_ALEN])
1743{
f942380c 1744 struct mlx5_vport *evport;
23898c76
NO		 1745 u64 node_guid;
1746 int err = 0;
77256579
SM		 1747
1748 if (!ESW_ALLOWED(esw))
1749 return -EPERM;
1750 if (!LEGAL_VPORT(esw, vport))
1751 return -EINVAL;
1752
f942380c
MHY		 1753 evport = &esw->vports[vport];
1754
1755 if (evport->spoofchk && !is_valid_ether_addr(mac)) {
1756 mlx5_core_warn(esw->dev,
1757 "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
1758 vport);
1759 return -EPERM;
1760 }
1761
77256579
SM		 1762 err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
1763 if (err) {
1764 mlx5_core_warn(esw->dev,
1765 "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
1766 vport, err);
1767 return err;
1768 }
1769
23898c76
NO		 1770 node_guid_gen_from_mac(&node_guid, mac);
1771 err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
1772 if (err)
1773 mlx5_core_warn(esw->dev,
1774 "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
1775 vport, err);
1776
f942380c
MHY		 1777 mutex_lock(&esw->state_lock);
1778 if (evport->enabled)
1779 err = esw_vport_ingress_config(esw, evport);
1780 mutex_unlock(&esw->state_lock);
77256579
SM		 1781 return err;
1782}
1783
1784int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
1785 int vport, int link_state)
1786{
1787 if (!ESW_ALLOWED(esw))
1788 return -EPERM;
1789 if (!LEGAL_VPORT(esw, vport))
1790 return -EINVAL;
1791
1792 return mlx5_modify_vport_admin_state(esw->dev,
1793 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1794 vport, link_state);
1795}
1796
1797int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
1798 int vport, struct ifla_vf_info *ivi)
1799{
f942380c 1800 struct mlx5_vport *evport;
9e7ea352
SM		 1801 u16 vlan;
1802 u8 qos;
1803
77256579
SM		 1804 if (!ESW_ALLOWED(esw))
1805 return -EPERM;
1806 if (!LEGAL_VPORT(esw, vport))
1807 return -EINVAL;
1808
f942380c
MHY		 1809 evport = &esw->vports[vport];
1810
77256579
SM		 1811 memset(ivi, 0, sizeof(*ivi));
1812 ivi->vf = vport - 1;
1813
1814 mlx5_query_nic_vport_mac_address(esw->dev, vport, ivi->mac);
1815 ivi->linkstate = mlx5_query_vport_admin_state(esw->dev,
1816 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1817 vport);
9e7ea352
SM		 1818 query_esw_vport_cvlan(esw->dev, vport, &vlan, &qos);
1819 ivi->vlan = vlan;
1820 ivi->qos = qos;
f942380c 1821 ivi->spoofchk = evport->spoofchk;
77256579
SM		 1822
1823 return 0;
1824}
9e7ea352
SM		 1825
1826int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1827 int vport, u16 vlan, u8 qos)
1828{
dfcb1ed3
MHY		 1829 struct mlx5_vport *evport;
1830 int err = 0;
9e7ea352
SM		 1831 int set = 0;
1832
1833 if (!ESW_ALLOWED(esw))
1834 return -EPERM;
1835 if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
1836 return -EINVAL;
1837
1838 if (vlan || qos)
1839 set = 1;
1840
dfcb1ed3
MHY		 1841 evport = &esw->vports[vport];
1842
1843 err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set);
1844 if (err)
1845 return err;
1846
1847 mutex_lock(&esw->state_lock);
1848 evport->vlan = vlan;
1849 evport->qos = qos;
1850 if (evport->enabled) {
1851 err = esw_vport_ingress_config(esw, evport);
1852 if (err)
1853 goto out;
1854 err = esw_vport_egress_config(esw, evport);
1855 }
1856
1857out:
1858 mutex_unlock(&esw->state_lock);
1859 return err;
9e7ea352 1860}
3b751a2a 1861
f942380c
MHY		 1862int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
1863 int vport, bool spoofchk)
1864{
1865 struct mlx5_vport *evport;
1866 bool pschk;
1867 int err = 0;
1868
1869 if (!ESW_ALLOWED(esw))
1870 return -EPERM;
1871 if (!LEGAL_VPORT(esw, vport))
1872 return -EINVAL;
1873
1874 evport = &esw->vports[vport];
1875
1876 mutex_lock(&esw->state_lock);
1877 pschk = evport->spoofchk;
1878 evport->spoofchk = spoofchk;
1879 if (evport->enabled)
1880 err = esw_vport_ingress_config(esw, evport);
1881 if (err)
1882 evport->spoofchk = pschk;
1883 mutex_unlock(&esw->state_lock);
1884
1885 return err;
1886}
1887
1edc57e2
MHY		 1888int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1889 int vport, bool setting)
1890{
1891 struct mlx5_vport *evport;
1892
1893 if (!ESW_ALLOWED(esw))
1894 return -EPERM;
1895 if (!LEGAL_VPORT(esw, vport))
1896 return -EINVAL;
1897
1898 evport = &esw->vports[vport];
1899
1900 mutex_lock(&esw->state_lock);
1901 evport->trusted = setting;
1902 if (evport->enabled)
1903 esw_vport_change_handle_locked(evport);
1904 mutex_unlock(&esw->state_lock);
1905
1906 return 0;
1907}
1908
3b751a2a
SM		 1909int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
1910 int vport,
1911 struct ifla_vf_stats *vf_stats)
1912{
1913 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
1914 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
1915 int err = 0;
1916 u32 *out;
1917
1918 if (!ESW_ALLOWED(esw))
1919 return -EPERM;
1920 if (!LEGAL_VPORT(esw, vport))
1921 return -EINVAL;
1922
1923 out = mlx5_vzalloc(outlen);
1924 if (!out)
1925 return -ENOMEM;
1926
1927 memset(in, 0, sizeof(in));
1928
1929 MLX5_SET(query_vport_counter_in, in, opcode,
1930 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
1931 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
1932 MLX5_SET(query_vport_counter_in, in, vport_number, vport);
1933 if (vport)
1934 MLX5_SET(query_vport_counter_in, in, other_vport, 1);
1935
1936 memset(out, 0, outlen);
1937 err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
1938 if (err)
1939 goto free_out;
1940
1941 #define MLX5_GET_CTR(p, x) \
1942 MLX5_GET64(query_vport_counter_out, p, x)
1943
1944 memset(vf_stats, 0, sizeof(*vf_stats));
1945 vf_stats->rx_packets =
1946 MLX5_GET_CTR(out, received_eth_unicast.packets) +
1947 MLX5_GET_CTR(out, received_eth_multicast.packets) +
1948 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1949
1950 vf_stats->rx_bytes =
1951 MLX5_GET_CTR(out, received_eth_unicast.octets) +
1952 MLX5_GET_CTR(out, received_eth_multicast.octets) +
1953 MLX5_GET_CTR(out, received_eth_broadcast.octets);
1954
1955 vf_stats->tx_packets =
1956 MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
1957 MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
1958 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
1959
1960 vf_stats->tx_bytes =
1961 MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
1962 MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
1963 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
1964
1965 vf_stats->multicast =
1966 MLX5_GET_CTR(out, received_eth_multicast.packets);
1967
1968 vf_stats->broadcast =
1969 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1970
1971free_out:
1972 kvfree(out);
1973 return err;
1974}
Linux kernel - Deliverables
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