[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c

/*
 * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <asm-generic/kmap_types.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/io-mapping.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/cq.h>
#include <linux/mlx5/qp.h>
#include <linux/mlx5/srq.h>
#include <linux/debugfs.h>
#include "mlx5_core.h"

#define DRIVER_NAME "mlx5_core"
#define DRIVER_VERSION "1.0"
#define DRIVER_RELDATE	"June 2013"

MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION(DRIVER_VERSION);

int mlx5_core_debug_mask;
module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");

struct workqueue_struct *mlx5_core_wq;

static int set_dma_caps(struct pci_dev *pdev)
{
	int err;

	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
	if (err) {
		dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (err) {
			dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
			return err;
		}
	}

	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
	if (err) {
		dev_warn(&pdev->dev,
			 "Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
		if (err) {
			dev_err(&pdev->dev,
				"Can't set consistent PCI DMA mask, aborting.\n");
			return err;
		}
	}

	dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
	return err;
}

static int request_bar(struct pci_dev *pdev)
{
	int err = 0;

	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
		dev_err(&pdev->dev, "Missing registers BAR, aborting.\n");
		return -ENODEV;
	}

	err = pci_request_regions(pdev, DRIVER_NAME);
	if (err)
		dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");

	return err;
}

static void release_bar(struct pci_dev *pdev)
{
	pci_release_regions(pdev);
}

static int mlx5_enable_msix(struct mlx5_core_dev *dev)
{
	struct mlx5_eq_table *table = &dev->priv.eq_table;
	int num_eqs = 1 << dev->caps.log_max_eq;
	int nvec;
	int err;
	int i;

	nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
	nvec = min_t(int, nvec, num_eqs);
	if (nvec <= MLX5_EQ_VEC_COMP_BASE)
		return -ENOMEM;

	table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
	if (!table->msix_arr)
		return -ENOMEM;

	for (i = 0; i < nvec; i++)
		table->msix_arr[i].entry = i;

retry:
	table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
	err = pci_enable_msix(dev->pdev, table->msix_arr, nvec);
	if (err <= 0) {
		return err;
	} else if (err > 2) {
		nvec = err;
		goto retry;
	}

	mlx5_core_dbg(dev, "received %d MSI vectors out of %d requested\n", err, nvec);

	return 0;
}

static void mlx5_disable_msix(struct mlx5_core_dev *dev)
{
	struct mlx5_eq_table *table = &dev->priv.eq_table;

	pci_disable_msix(dev->pdev);
	kfree(table->msix_arr);
}

struct mlx5_reg_host_endianess {
	u8	he;
	u8      rsvd[15];
};

static int handle_hca_cap(struct mlx5_core_dev *dev)
{
	struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
	struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
	struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
	struct mlx5_cmd_set_hca_cap_mbox_out set_out;
	struct mlx5_profile *prof = dev->profile;
	u64 flags;
	int csum = 1;
	int err;

	memset(&query_ctx, 0, sizeof(query_ctx));
	query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
	if (!query_out)
		return -ENOMEM;

	set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
	if (!set_ctx) {
		err = -ENOMEM;
		goto query_ex;
	}

	query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
	query_ctx.hdr.opmod  = cpu_to_be16(0x1);
	err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
				 query_out, sizeof(*query_out));
	if (err)
		goto query_ex;

	err = mlx5_cmd_status_to_err(&query_out->hdr);
	if (err) {
		mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
		goto query_ex;
	}

	memcpy(&set_ctx->hca_cap, &query_out->hca_cap,
	       sizeof(set_ctx->hca_cap));

	if (prof->mask & MLX5_PROF_MASK_CMDIF_CSUM) {
		csum = !!prof->cmdif_csum;
		flags = be64_to_cpu(set_ctx->hca_cap.flags);
		if (csum)
			flags |= MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
		else
			flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;

		set_ctx->hca_cap.flags = cpu_to_be64(flags);
	}

	if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
		set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;

	memset(&set_out, 0, sizeof(set_out));
	set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
	set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
	err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
				 &set_out, sizeof(set_out));
	if (err) {
		mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
		goto query_ex;
	}

	err = mlx5_cmd_status_to_err(&set_out.hdr);
	if (err)
		goto query_ex;

	if (!csum)
		dev->cmd.checksum_disabled = 1;

query_ex:
	kfree(query_out);
	kfree(set_ctx);

	return err;
}

static int set_hca_ctrl(struct mlx5_core_dev *dev)
{
	struct mlx5_reg_host_endianess he_in;
	struct mlx5_reg_host_endianess he_out;
	int err;

	memset(&he_in, 0, sizeof(he_in));
	he_in.he = MLX5_SET_HOST_ENDIANNESS;
	err = mlx5_core_access_reg(dev, &he_in,  sizeof(he_in),
					&he_out, sizeof(he_out),
					MLX5_REG_HOST_ENDIANNESS, 0, 1);
	return err;
}

static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
{
	int err;
	struct mlx5_enable_hca_mbox_in in;
	struct mlx5_enable_hca_mbox_out out;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		return mlx5_cmd_status_to_err(&out.hdr);

	return 0;
}

static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
{
	int err;
	struct mlx5_disable_hca_mbox_in in;
	struct mlx5_disable_hca_mbox_out out;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		return mlx5_cmd_status_to_err(&out.hdr);

	return 0;
}

int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
{
	struct mlx5_priv *priv = &dev->priv;
	int err;

	dev->pdev = pdev;
	pci_set_drvdata(dev->pdev, dev);
	strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
	priv->name[MLX5_MAX_NAME_LEN - 1] = 0;

	mutex_init(&priv->pgdir_mutex);
	INIT_LIST_HEAD(&priv->pgdir_list);
	spin_lock_init(&priv->mkey_lock);

	priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
	if (!priv->dbg_root)
		return -ENOMEM;

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
		goto err_dbg;
	}

	err = request_bar(pdev);
	if (err) {
		dev_err(&pdev->dev, "error requesting BARs, aborting.\n");
		goto err_disable;
	}

	pci_set_master(pdev);

	err = set_dma_caps(pdev);
	if (err) {
		dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
		goto err_clr_master;
	}

	dev->iseg_base = pci_resource_start(dev->pdev, 0);
	dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
	if (!dev->iseg) {
		err = -ENOMEM;
		dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
		goto err_clr_master;
	}
	dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
		 fw_rev_min(dev), fw_rev_sub(dev));

	err = mlx5_cmd_init(dev);
	if (err) {
		dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
		goto err_unmap;
	}

	mlx5_pagealloc_init(dev);

	err = mlx5_core_enable_hca(dev);
	if (err) {
		dev_err(&pdev->dev, "enable hca failed\n");
		goto err_pagealloc_cleanup;
	}

	err = mlx5_satisfy_startup_pages(dev, 1);
	if (err) {
		dev_err(&pdev->dev, "failed to allocate boot pages\n");
		goto err_disable_hca;
	}

	err = set_hca_ctrl(dev);
	if (err) {
		dev_err(&pdev->dev, "set_hca_ctrl failed\n");
		goto reclaim_boot_pages;
	}

	err = handle_hca_cap(dev);
	if (err) {
		dev_err(&pdev->dev, "handle_hca_cap failed\n");
		goto reclaim_boot_pages;
	}

	err = mlx5_satisfy_startup_pages(dev, 0);
	if (err) {
		dev_err(&pdev->dev, "failed to allocate init pages\n");
		goto reclaim_boot_pages;
	}

	err = mlx5_pagealloc_start(dev);
	if (err) {
		dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
		goto reclaim_boot_pages;
	}

	err = mlx5_cmd_init_hca(dev);
	if (err) {
		dev_err(&pdev->dev, "init hca failed\n");
		goto err_pagealloc_stop;
	}

	mlx5_start_health_poll(dev);

	err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
	if (err) {
		dev_err(&pdev->dev, "query hca failed\n");
		goto err_stop_poll;
	}

	err = mlx5_cmd_query_adapter(dev);
	if (err) {
		dev_err(&pdev->dev, "query adapter failed\n");
		goto err_stop_poll;
	}

	err = mlx5_enable_msix(dev);
	if (err) {
		dev_err(&pdev->dev, "enable msix failed\n");
		goto err_stop_poll;
	}

	err = mlx5_eq_init(dev);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize eq\n");
		goto disable_msix;
	}

	err = mlx5_alloc_uuars(dev, &priv->uuari);
	if (err) {
		dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
		goto err_eq_cleanup;
	}

	err = mlx5_start_eqs(dev);
	if (err) {
		dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
		goto err_free_uar;
	}

	MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);

	mlx5_init_cq_table(dev);
	mlx5_init_qp_table(dev);
	mlx5_init_srq_table(dev);

	return 0;

err_free_uar:
	mlx5_free_uuars(dev, &priv->uuari);

err_eq_cleanup:
	mlx5_eq_cleanup(dev);

disable_msix:
	mlx5_disable_msix(dev);

err_stop_poll:
	mlx5_stop_health_poll(dev);
	mlx5_cmd_teardown_hca(dev);

err_pagealloc_stop:
	mlx5_pagealloc_stop(dev);

reclaim_boot_pages:
	mlx5_reclaim_startup_pages(dev);

err_disable_hca:
	mlx5_core_disable_hca(dev);

err_pagealloc_cleanup:
	mlx5_pagealloc_cleanup(dev);
	mlx5_cmd_cleanup(dev);

err_unmap:
	iounmap(dev->iseg);

err_clr_master:
	pci_clear_master(dev->pdev);
	release_bar(dev->pdev);

err_disable:
	pci_disable_device(dev->pdev);

err_dbg:
	debugfs_remove(priv->dbg_root);
	return err;
}
EXPORT_SYMBOL(mlx5_dev_init);

void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
{
	struct mlx5_priv *priv = &dev->priv;

	mlx5_cleanup_srq_table(dev);
	mlx5_cleanup_qp_table(dev);
	mlx5_cleanup_cq_table(dev);
	mlx5_stop_eqs(dev);
	mlx5_free_uuars(dev, &priv->uuari);
	mlx5_eq_cleanup(dev);
	mlx5_disable_msix(dev);
	mlx5_stop_health_poll(dev);
	mlx5_cmd_teardown_hca(dev);
	mlx5_pagealloc_stop(dev);
	mlx5_reclaim_startup_pages(dev);
	mlx5_core_disable_hca(dev);
	mlx5_pagealloc_cleanup(dev);
	mlx5_cmd_cleanup(dev);
	iounmap(dev->iseg);
	pci_clear_master(dev->pdev);
	release_bar(dev->pdev);
	pci_disable_device(dev->pdev);
	debugfs_remove(priv->dbg_root);
}
EXPORT_SYMBOL(mlx5_dev_cleanup);

static int __init init(void)
{
	int err;

	mlx5_register_debugfs();
	mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
	if (!mlx5_core_wq) {
		err = -ENOMEM;
		goto err_debug;
	}
	mlx5_health_init();

	return 0;

	mlx5_health_cleanup();
err_debug:
	mlx5_unregister_debugfs();
	return err;
}

static void __exit cleanup(void)
{
	mlx5_health_cleanup();
	destroy_workqueue(mlx5_core_wq);
	mlx5_unregister_debugfs();
}

module_init(init);
module_exit(cleanup);
Commit	Line	Data
e126ba97 EC	1	/*
	2	* Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <asm-generic/kmap_types.h>
	34	#include <linux/module.h>
	35	#include <linux/init.h>
	36	#include <linux/errno.h>
	37	#include <linux/pci.h>
	38	#include <linux/dma-mapping.h>
	39	#include <linux/slab.h>
	40	#include <linux/io-mapping.h>
	41	#include <linux/mlx5/driver.h>
	42	#include <linux/mlx5/cq.h>
	43	#include <linux/mlx5/qp.h>
	44	#include <linux/mlx5/srq.h>
	45	#include <linux/debugfs.h>
	46	#include "mlx5_core.h"
	47
	48	#define DRIVER_NAME "mlx5_core"
	49	#define DRIVER_VERSION "1.0"
	50	#define DRIVER_RELDATE "June 2013"
	51
	52	MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
	53	MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
	54	MODULE_LICENSE("Dual BSD/GPL");
	55	MODULE_VERSION(DRIVER_VERSION);
	56
	57	int mlx5_core_debug_mask;
	58	module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
	59	MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
	60
	61	struct workqueue_struct *mlx5_core_wq;
	62
	63	static int set_dma_caps(struct pci_dev *pdev)
	64	{
65	int err;
66
67	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
68	if (err) {
69	dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
70	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
71	if (err) {
72	dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
73	return err;
74	}
75	}
76
77	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
78	if (err) {
79	dev_warn(&pdev->dev,
80	"Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
81	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
82	if (err) {
83	dev_err(&pdev->dev,
84	"Can't set consistent PCI DMA mask, aborting.\n");
85	return err;
86	}
87	}
88
89	dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
90	return err;
91	}
92
93	static int request_bar(struct pci_dev *pdev)
94	{
95	int err = 0;
96
97	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
98	dev_err(&pdev->dev, "Missing registers BAR, aborting.\n");
99	return -ENODEV;
100	}
101
102	err = pci_request_regions(pdev, DRIVER_NAME);
103	if (err)
104	dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
105
106	return err;
107	}
108
109	static void release_bar(struct pci_dev *pdev)
110	{
111	pci_release_regions(pdev);
112	}
113
114	static int mlx5_enable_msix(struct mlx5_core_dev *dev)
115	{
116	struct mlx5_eq_table *table = &dev->priv.eq_table;
117	int num_eqs = 1 << dev->caps.log_max_eq;
118	int nvec;
119	int err;
120	int i;
121
122	nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
123	nvec = min_t(int, nvec, num_eqs);
124	if (nvec <= MLX5_EQ_VEC_COMP_BASE)
125	return -ENOMEM;
126
127	table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
128	if (!table->msix_arr)
129	return -ENOMEM;
130
131	for (i = 0; i < nvec; i++)
132	table->msix_arr[i].entry = i;
133
134	retry:
135	table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
136	err = pci_enable_msix(dev->pdev, table->msix_arr, nvec);
137	if (err <= 0) {
138	return err;
139	} else if (err > 2) {
140	nvec = err;
141	goto retry;
142	}
143
144	mlx5_core_dbg(dev, "received %d MSI vectors out of %d requested\n", err, nvec);
145
146	return 0;
147	}
148
149	static void mlx5_disable_msix(struct mlx5_core_dev *dev)
150	{
151	struct mlx5_eq_table *table = &dev->priv.eq_table;
152
153	pci_disable_msix(dev->pdev);
154	kfree(table->msix_arr);
155	}
156
157	struct mlx5_reg_host_endianess {
158	u8 he;
159	u8 rsvd[15];
160	};
161
162	static int handle_hca_cap(struct mlx5_core_dev *dev)
163	{
164	struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
165	struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
166	struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
167	struct mlx5_cmd_set_hca_cap_mbox_out set_out;
168	struct mlx5_profile *prof = dev->profile;
169	u64 flags;
170	int csum = 1;
171	int err;
172
173	memset(&query_ctx, 0, sizeof(query_ctx));
174	query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
175	if (!query_out)
176	return -ENOMEM;
177
178	set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
179	if (!set_ctx) {
180	err = -ENOMEM;
181	goto query_ex;
182	}
183
184	query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
185	query_ctx.hdr.opmod = cpu_to_be16(0x1);
186	err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
187	query_out, sizeof(*query_out));
188	if (err)
189	goto query_ex;
190
191	err = mlx5_cmd_status_to_err(&query_out->hdr);
192	if (err) {
193	mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
194	goto query_ex;
195	}
196
197	memcpy(&set_ctx->hca_cap, &query_out->hca_cap,
198	sizeof(set_ctx->hca_cap));
199
200	if (prof->mask & MLX5_PROF_MASK_CMDIF_CSUM) {
201	csum = !!prof->cmdif_csum;
202	flags = be64_to_cpu(set_ctx->hca_cap.flags);
203	if (csum)
204	flags \|= MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
205	else
206	flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
207
208	set_ctx->hca_cap.flags = cpu_to_be64(flags);
209	}
210
211	if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
212	set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
213
214	memset(&set_out, 0, sizeof(set_out));
288dde9f	215	set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
e126ba97 EC	216	set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
	217	err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
	218	&set_out, sizeof(set_out));
	219	if (err) {
	220	mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
	221	goto query_ex;
	222	}
	223
	224	err = mlx5_cmd_status_to_err(&set_out.hdr);
	225	if (err)
	226	goto query_ex;
	227
	228	if (!csum)
	229	dev->cmd.checksum_disabled = 1;
	230
	231	query_ex:
	232	kfree(query_out);
	233	kfree(set_ctx);
	234
	235	return err;
	236	}
	237
	238	static int set_hca_ctrl(struct mlx5_core_dev *dev)
	239	{
	240	struct mlx5_reg_host_endianess he_in;
	241	struct mlx5_reg_host_endianess he_out;
	242	int err;
	243
	244	memset(&he_in, 0, sizeof(he_in));
	245	he_in.he = MLX5_SET_HOST_ENDIANNESS;
	246	err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
	247	&he_out, sizeof(he_out),
	248	MLX5_REG_HOST_ENDIANNESS, 0, 1);
	249	return err;
	250	}
	251
cd23b14b EC	252	static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
	253	{
	254	int err;
	255	struct mlx5_enable_hca_mbox_in in;
	256	struct mlx5_enable_hca_mbox_out out;
	257
	258	memset(&in, 0, sizeof(in));
	259	memset(&out, 0, sizeof(out));
	260	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
	261	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	262	if (err)
	263	return err;
	264
	265	if (out.hdr.status)
	266	return mlx5_cmd_status_to_err(&out.hdr);
	267
	268	return 0;
	269	}
	270
	271	static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
	272	{
	273	int err;
	274	struct mlx5_disable_hca_mbox_in in;
	275	struct mlx5_disable_hca_mbox_out out;
	276
	277	memset(&in, 0, sizeof(in));
	278	memset(&out, 0, sizeof(out));
	279	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
	280	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	281	if (err)
	282	return err;
	283
	284	if (out.hdr.status)
	285	return mlx5_cmd_status_to_err(&out.hdr);
	286
	287	return 0;
	288	}
	289
e126ba97 EC	290	int mlx5_dev_init(struct mlx5_core_dev dev, struct pci_dev pdev)
	291	{
	292	struct mlx5_priv *priv = &dev->priv;
	293	int err;
	294
	295	dev->pdev = pdev;
	296	pci_set_drvdata(dev->pdev, dev);
	297	strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
	298	priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
	299
	300	mutex_init(&priv->pgdir_mutex);
	301	INIT_LIST_HEAD(&priv->pgdir_list);
	302	spin_lock_init(&priv->mkey_lock);
	303
	304	priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
	305	if (!priv->dbg_root)
	306	return -ENOMEM;
	307
	308	err = pci_enable_device(pdev);
	309	if (err) {
	310	dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
	311	goto err_dbg;
	312	}
	313
	314	err = request_bar(pdev);
	315	if (err) {
	316	dev_err(&pdev->dev, "error requesting BARs, aborting.\n");
	317	goto err_disable;
	318	}
	319
	320	pci_set_master(pdev);
	321
	322	err = set_dma_caps(pdev);
	323	if (err) {
	324	dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
	325	goto err_clr_master;
	326	}
	327
	328	dev->iseg_base = pci_resource_start(dev->pdev, 0);
	329	dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
	330	if (!dev->iseg) {
	331	err = -ENOMEM;
	332	dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
	333	goto err_clr_master;
	334	}
	335	dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
	336	fw_rev_min(dev), fw_rev_sub(dev));
	337
	338	err = mlx5_cmd_init(dev);
	339	if (err) {
	340	dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
	341	goto err_unmap;
	342	}
	343
	344	mlx5_pagealloc_init(dev);
cd23b14b EC	345
	346	err = mlx5_core_enable_hca(dev);
	347	if (err) {
	348	dev_err(&pdev->dev, "enable hca failed\n");
	349	goto err_pagealloc_cleanup;
	350	}
	351
	352	err = mlx5_satisfy_startup_pages(dev, 1);
	353	if (err) {
	354	dev_err(&pdev->dev, "failed to allocate boot pages\n");
	355	goto err_disable_hca;
	356	}
	357
e126ba97 EC	358	err = set_hca_ctrl(dev);
	359	if (err) {
	360	dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b	361	goto reclaim_boot_pages;
e126ba97 EC	362	}
	363
	364	err = handle_hca_cap(dev);
	365	if (err) {
	366	dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b	367	goto reclaim_boot_pages;
e126ba97 EC	368	}
e126ba97 EC	369
cd23b14b	370	err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97	371	if (err) {
cd23b14b EC	372	dev_err(&pdev->dev, "failed to allocate init pages\n");
cd23b14b EC	373	goto reclaim_boot_pages;
e126ba97 EC	374	}
	375
	376	err = mlx5_pagealloc_start(dev);
	377	if (err) {
	378	dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b	379	goto reclaim_boot_pages;
e126ba97 EC	380	}
	381
	382	err = mlx5_cmd_init_hca(dev);
	383	if (err) {
	384	dev_err(&pdev->dev, "init hca failed\n");
	385	goto err_pagealloc_stop;
	386	}
	387
	388	mlx5_start_health_poll(dev);
	389
	390	err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
	391	if (err) {
	392	dev_err(&pdev->dev, "query hca failed\n");
	393	goto err_stop_poll;
	394	}
	395
	396	err = mlx5_cmd_query_adapter(dev);
	397	if (err) {
	398	dev_err(&pdev->dev, "query adapter failed\n");
	399	goto err_stop_poll;
	400	}
	401
	402	err = mlx5_enable_msix(dev);
	403	if (err) {
	404	dev_err(&pdev->dev, "enable msix failed\n");
	405	goto err_stop_poll;
	406	}
	407
	408	err = mlx5_eq_init(dev);
	409	if (err) {
	410	dev_err(&pdev->dev, "failed to initialize eq\n");
	411	goto disable_msix;
	412	}
	413
	414	err = mlx5_alloc_uuars(dev, &priv->uuari);
	415	if (err) {
	416	dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
	417	goto err_eq_cleanup;
	418	}
	419
	420	err = mlx5_start_eqs(dev);
	421	if (err) {
	422	dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
	423	goto err_free_uar;
	424	}
	425
	426	MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
	427
	428	mlx5_init_cq_table(dev);
	429	mlx5_init_qp_table(dev);
	430	mlx5_init_srq_table(dev);
	431
	432	return 0;
	433
	434	err_free_uar:
	435	mlx5_free_uuars(dev, &priv->uuari);
	436
	437	err_eq_cleanup:
	438	mlx5_eq_cleanup(dev);
	439
	440	disable_msix:
	441	mlx5_disable_msix(dev);
	442
	443	err_stop_poll:
444	mlx5_stop_health_poll(dev);
445	mlx5_cmd_teardown_hca(dev);
446
447	err_pagealloc_stop:
448	mlx5_pagealloc_stop(dev);
449
cd23b14b	450	reclaim_boot_pages:
e126ba97 EC	451	mlx5_reclaim_startup_pages(dev);
e126ba97 EC	452
cd23b14b EC	453	err_disable_hca:
	454	mlx5_core_disable_hca(dev);
	455
e126ba97 EC	456	err_pagealloc_cleanup:
	457	mlx5_pagealloc_cleanup(dev);
	458	mlx5_cmd_cleanup(dev);
	459
	460	err_unmap:
	461	iounmap(dev->iseg);
	462
	463	err_clr_master:
	464	pci_clear_master(dev->pdev);
	465	release_bar(dev->pdev);
	466
	467	err_disable:
	468	pci_disable_device(dev->pdev);
	469
	470	err_dbg:
	471	debugfs_remove(priv->dbg_root);
	472	return err;
	473	}
	474	EXPORT_SYMBOL(mlx5_dev_init);
	475
	476	void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
	477	{
	478	struct mlx5_priv *priv = &dev->priv;
	479
	480	mlx5_cleanup_srq_table(dev);
	481	mlx5_cleanup_qp_table(dev);
	482	mlx5_cleanup_cq_table(dev);
	483	mlx5_stop_eqs(dev);
	484	mlx5_free_uuars(dev, &priv->uuari);
	485	mlx5_eq_cleanup(dev);
	486	mlx5_disable_msix(dev);
	487	mlx5_stop_health_poll(dev);
	488	mlx5_cmd_teardown_hca(dev);
	489	mlx5_pagealloc_stop(dev);
	490	mlx5_reclaim_startup_pages(dev);
cd23b14b	491	mlx5_core_disable_hca(dev);
e126ba97 EC	492	mlx5_pagealloc_cleanup(dev);
	493	mlx5_cmd_cleanup(dev);
	494	iounmap(dev->iseg);
	495	pci_clear_master(dev->pdev);
	496	release_bar(dev->pdev);
	497	pci_disable_device(dev->pdev);
	498	debugfs_remove(priv->dbg_root);
	499	}
	500	EXPORT_SYMBOL(mlx5_dev_cleanup);
	501
	502	static int __init init(void)
	503	{
	504	int err;
	505
	506	mlx5_register_debugfs();
	507	mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
	508	if (!mlx5_core_wq) {
	509	err = -ENOMEM;
	510	goto err_debug;
	511	}
	512	mlx5_health_init();
	513
	514	return 0;
	515
	516	mlx5_health_cleanup();
	517	err_debug:
	518	mlx5_unregister_debugfs();
	519	return err;
	520	}
	521
	522	static void __exit cleanup(void)
	523	{
	524	mlx5_health_cleanup();
	525	destroy_workqueue(mlx5_core_wq);
	526	mlx5_unregister_debugfs();
	527	}
	528
	529	module_init(init);
	530	module_exit(cleanup);